apt-X Evaluation CoDec. User Manual
Contents
1. Setting it to the Off position removes the loopback of the encoded data inside the FPGA instead the data is routed out via a FIFO to pin 12 of the expansion header Cn4 Connecting pin 12 to pin 13 of Cn4 will again loopback the data from the encoder to the decoder By placing oscilloscope probes on pins 12 and 14 of Cn4 it is possible to see the encoded or compressed apt X data and the clock associated with it The two tests above are the quickest to set up and will prove basic operation of the module however there are many more modes of operation the module is capable of How to achieve all of these are described in the following sections which will explain the differences between Master and Slave modes as well as how to select between low delay and SRC modes The configuration is described from the perspective of configuration being done via the PC interface software included with the board An advanced description of how to achieve all these modes using the DIP switches is included as the last section Rev 1 0 apt X Evaluation CoDec Power Requirements The preferred option is to use the supplied 9v d c power supply connected to the input jack This will then let the module generate all its required internal voltages this input remains effective with unregulated input voltages as low as 6 5v It is recommended that a supply voltage above 9v should not be used The second option is to power the unit via the ex2. The data flow is as follows the S PDIF data is received the PCM data is extracted and supplied to the DSP for encode via the FPGA The encoded data is then returned to the DSP again by the FPGA for decode The PCM is then routed to the S PDIF output stage and retransmitted at the same sample frequency Fs as the input This is known as a Low Delay mode since the SRCs are not being used this mode will show the truest latency figures for the algorithm Before even connecting power to the module the jumpers or links must be set up L2 should be set to connect pins and 2 This sets the module to accept configuration from the dip switches Links J3 J4 JS and J6 should all have jumpers on them why this is the case is explained later The next step is to set the 10 way DIP switch as follows SW1 1 On_ Loopback SW1 2 Off SW1 3 On SW 1 4 Off SW1 5 Off SW1 6 Off SW1 7 Off SW1 8 Off SW1 9 On SW1 10 Off The module is now configured for Eapt X16 low delay loopback at Fs 44 1kHz Once this configuration is set powering on the module will set the unit up to take in a stereo S PDIF stream with an Fs of 44 1kHz encode and decode it Then return it out the S PDIF out port A CD player is an ideal source for this first test Test 2 The next logical step is to loopback the data at the expansion header where it can be examined as it goes past To do this only requires one switch to be changed SW1 1
3. the encoder only produces half the apt X data Equivalently the decoder will only receive one channels worth of apt X data but it will output the same PCM to both channels this is not inherent to the algorithm but is usually desirable Data Path This option has already been demonstrated in the getting started section It controls whether the encoded data is sent out to the expansion header or looped by the FPGA and sent back to the DSP Autosync Check box This control only becomes active when the apt X16 algorithm is selected This is because Autosync cannot be turned off in the enhanced algorithms Autosync is a very low overhead embedded code which allows the apt X stream of data to travel without the need for a framing or word clock Some very early APT products worked without Autosync as framing information could be recovered from other sources Non Autosync mode and how to frame it are discussed later It is recommended that it be left on at all times Low Delay Mode Mabe 18 55 91 Eia Ke gaske alier pel Digtal arbo Cptione Lea Tais SAE ied T mi kai 5 amplo Feats jF ni C Ek P apie MT T Eas a rice T Eai b T recado he 5 PIA pdpad ran ache re ite M Te p d This mode can only be used if the unit is configured in Master mode The low delay is achieved at the cost of bypassing the SRCs in and out of the module This means the DSP MUST run at Rev 1 0 apt X Evaluation CoDec the same Fs as t
4. If a configuration is rejected by the hardware a message will be displayed in the middle of the screen stating this The application will be inactive until the window shown here has been acknowledged Note If the module is power cycled then the application should also be closed and reopened Rev 1 0 Dip Switch Configuration apt X Evaluation CoDec This method is for stand alone mode where no PC with a USB port is available In this mode the module configuration is set by the ten way DIP switches that are labelled Configuration on the PCB To enable stand alone mode the jumper on L2 must be moved to link pins one and two The functionality of each switch is shown in the table below Switch 10 9 8 7 6 5 4 3 2 1 No Stereo SRC SRC SRC SRC Clock Algorithm Algorithm A sync Loop Mono Mode Mode Mode Mode Mode Select 1 Select 0 On Off Back Bl BO Al AO aptX16 The Stereo Mono switch is Off for Stereo and On for Mono the operational changes are the same as the equivalent radio button group on the windows application The SRC mode switches 9 to 6 are a little more complex in operation The function of switches 9 and 8 depend on the settings of switches 7 and 6 If switches 7 and 6 are OFF this means the module is in Low Delay mode The function of switches 9 and 8 are then to set up the module for the appropriate incoming sample rate The table below shows the exa
5. A E AUDIO PROCESSING T E C H N O L O G Y apt X Evaluation CoDec User Manual Rev 1 0 apt X Evaluation CoDec Issue Index Rey ae da q a Sd GR ener er ees Original Release Rev 1 0 apt X Evaluation CoDec Overview The apt X Evaluation CoDec Module is for encoding and or decoding one or two channels of digital audio using any of the apt X algorithms The algorithms are run on a Motorola 56362 DSP The module has an S PDIF audio I O section and the ability to Sample Rate Convert SRC in both directions Either a Windows G U I via USB or a bank of dip switches configures the mode of operation for the module The module also has an expansion header to enable users to interface equipment into the data path at certain points This gives the ability to bypass some of the on board components The power is normally supplied by an external 9v dc supply needing a mains input via an IEC320 C8 lead E apt X CoDec Block Diagram of Data Flow and Control Paths Expansion Header Digital Audio In S PDIF Sample Receiver Rate Converter i Field Programmable S PDIF Sample i Gate Array Transmitter Rate E Xilinx Converter Digital Audio Out Oscillators amp PLL Circuits Power Sequencing amp 3 3v 2 5v generation USB Connection amp Configuration Switches Rev 1 0 apt X Evaluation CoDec Getting Started Test 1 This section describes how to configure the module for a simple apt X loopback
6. Hz Mono x Master mode SRC S PDIF out 32kHz 12kHz Stereo 240 Master mode SRC S PDIF out 32kHz 12kHz Mono 120 Master mode SRC S PDIF out 32kHz 15kHz Stereo 320 Master mode SRC S PDIF out 32kHz 15kHz Mono 160 Master mode SRC S PDIF out 32kHz 20kHz Stereo 480 Master mode SRC S PDIF out 32kHz 20kHz Mono 240 Master mode SRC S PDIF out 44 1kHz 7kHz Stereo Master mode SRC S PDIF out 44 1kHz 7kHz Mono x Master mode SRC S PDIF out 44 1kHz 12kHz Stereo Master mode SRC S PDIF out 44 1kHz 12kHz Mono Master mode SRC S PDIF out 44 1kHz 15kHz Stereo Master mode SRC S PDIF out 44 1kHz 15kHz Mono Master mode SRC S PDIF out 44 1kHz 20kHz Stereo Master mode SRC S PDIF out 44 1kHz 20kHz Mono Master mode SRC S PDIF out 48kHz 7kHz Stereo Master mode SRC S PDIF out 48kHz 7kHz Mono Master mode SRC S PDIF out 48kHz 12kHz Stereo Master mode SRC S PDIF out 48kHz 12kHz Mono Master mode SRC S PDIF out 48kHz 15kHz Stereo Master mode SRC S PDIF out 48kHz 15kHz Mono Master mode SRC S PDIF out 48kHz 20kHz Stereo Rev 1 0 Master mode SRC S PDIF out 48kHz 20kHz Mono Items commented with are invalid modes Function apt X Evaluation CoDec Invalid mode Invalid mode Invalid mode Invalid mode Invalid mode Invalid mo
7. ate rate supplied to it If the switch is Off the module is in Master mode and will provide a clock at the data rate Switches 4 and 3 are used for Algorithm selection The exact settings are shown below Mode Algorithm Algorithm Select 1 Select 0 apt X 16bit Off Off Eapt X Off On 16bit Eapt X On Off 20bit Eapt X On On 24bit Switch 2 controls the use of Autosync when the apt X16 algorithm is selected If any other algorithm is selected Autosync can not be turned off so the state of this switch is irrelevant For apt X 16 if the switch is On then Autosync is On Switch 1 controls the flow of the apt X data If the switch is ON then the data is looped so the DSP decodes what it has just encoded If the switch is Off then the encoded data goes out to the expansion header and data for decode is expected from the expansion header Additional Information Since this module has been designed as a platform to show the excellent audio quality properties of the apt X algorithms some of the flexibility of use has been omitted in order to achieve the best possible audio quality One example of this is the use of the precision VCXO s which enable the module to provide an S PDIF output with jitter below 2nS Fs 48kHz even if the input jitter is much higher The penalty of this however is the low tolerance to clocks which are above or below the frequency specified for any particular mode The VCXO s only ha
8. ct settings Switches 7 amp 6 Mode SRC SRC Mode A1 Mode A0 SRC Bypass Off Off Switches 9 amp 8 if SRC Bypass selected Mode SRC SRC Mode Mode B1 BO S PDIF 48kHz Off Off In S PDIF 32kHz Off On In S PDIF On Off 44 1kHz In S PDIF 48kHz On On In Any other setting of switches 7 and 6 will configure the module for SRC mode This means that switches 7 and 6 set up the rate of the S PDIF output Switches 9 and 8 are now used to select the audio bandwidth to be encoded decoded The table below shows the precise settings for each mode Switches 7 amp 6 Mode SRC SRC Mode Al Mode AO S PDIF Off On 32kHz Out S PDIF On Off 44 1kHz Out S PDIF On On 48kHz Out Rev 1 0 Switches 9 amp 8 if SRC mode selected Mode SRC SRC Mode Mode B1 BO 7kHz Off Off 12kHz Off On 15kHz On Off 20kHz On On apt X Evaluation CoDec Switch 5 is the Master Slave selection On for Slave and Off for Master As explained earlier for the PC interface it is impossible to run the module in Slave mode while Low Delay is selected This is why the PC interface will not allow the user to send that configuration The DIP switches can be set for this invalid mode but the module will not run properly If the switch is On then the module is in Slave mode This means the unit needs an external clock at the appropri
9. de Invalid mode Invalid mode Slave mode SRC S PDIF out 32kHz 7kHz Stereo Slave mode SRC S PDIF out 32kHz 7kHz Mono Slave mode SRC S PDIF out 32kHz 12kHz Stereo Slave mode SRC S PDIF out 32kHz 12kHz Mono Slave mode SRC S PDIF out 32kHz 15kHz Stereo Slave mode SRC S PDIF out 32kHz 15kHz Mono Slave mode SRC S PDIF out 32kHz 20kHz Stereo Slave mode SRC S PDIF out 32kHz 20kHz Mono Slave mode SRC S PDIF out 44 1kHz 7kHz Stereo Slave mode SRC S PDIF out 44 1kHz 7kHz Mono Slave mode SRC S PDIF out 44 1kHz 12kHz Stereo Slave mode SRC S PDIF out 44 1kHz 12kHz Mono Slave mode SRC S PDIF out 44 1kHz 15kHz Stereo Slave mode SRC S PDIF out 44 1kHz 15kHz Mono Slave mode SRC S PDIF out 44 1kHz 20kHz Stereo Slave mode SRC S PDIF out 44 1kHz 20kHz Mono Slave mode SRC S PDIF out 48kHz 7kHz Stereo Slave mode SRC S PDIF out 48kHz 7kHz Mono Slave mode SRC S PDIF out 48kHz 12kHz Stereo Slave mode SRC S PDIF out 48kHz 12kHz Mono Slave mode SRC S PDIF out 48kHz 15kHz Stereo Slave mode SRC S PDIF out 48kHz 15kHz Mono Slave mode SRC S PDIF out 48kHz 20kHz Stereo Rev 1 0 Slave mode SRC S PDIF out 48kHz 20kHz Mono Items commented with are invalid modes
10. he audio is coming in at Since the audio comes in at a fixed rate there is no way of slaving the DSP to different network rate without the SRCs When in Low Delay mode the only option available to set is the input sample rate Fsi This needs set to ensure good audio quality SRC Modes B api Crahan Dood Gl Mel a E LTT 15 53 FEER kled daie Che me D gaad Rk Dewa Len Dalay SPC Mads Cope flg o p Aado Barer 6 bpt otn P Ear di SPLAT Dda Fiada P Empada fuithr Shaan J Mena Select TE Nano T goea nois Duda Pair Ha Corgan Sent P Leka Y La Cas ro Candie When the SRCs are in circuit the module is much more flexible regarding data rates and clocks There are now two more options which need set The first is the audio bandwidth to be encoded and the other is the output rate of the S PDIF Fso The Audio Bandwidth setting determides the sample rate of the DSP and therefore the amount encoded data For example assume 16 bit algorithm stereo mode At Fs 16kHz the apt X bit rate will be 128kbps but at Fs 48kHz the apt X bit rate will be 384kbps The S PDIF output rate is self explanatory Pressing the Configure button will send the current settings to the module If any of the options in the application are changed the hardware will not be updated until the configuration button is pressed A summary of the last configuration mode sent is displayed in the application window just above the configure button
11. n the OFF position Once the module has been set up and powered on the USB cable can be connected and then the configuration application apt_eval exe can then be opened When it opens the application will be in the default mode as shown Docking Hace Car ed Dang dante Opera Loa Dg ER e Aado Durer Rev 1 0 apt X Evaluation CoDec The first option on the application is Master Slave this setting depends on whether the unit is to SLAVE to an external network clock DTE operation or is allowed to generate its own network clock for the apt X data DCE operation For example to connect two modules back to back one needs to be a master and the other a slave However to connect two modules via a network both units need to be slaves If the module is set as a slave the clock supplied must be within 50ppm of the frequency specified for that mode These frequencies can be found in the appendix For standalone loop backs Master mode should be selected Slave mode cannot be selected with low delay mode this is explained later Compression Algorithm This simply selects which of the four apt X algorithms will be run by the DSP As the algorithm resolution increases so will the amount of encoded data produced The encoder and decoder cannot be set for different algorithms Stereo Mono This selects whether both channels of the incoming S PDIF stream are encoded Stereo or just the first channel Mono If a mono mode is chosen
12. pansion header CN4 where 5v 3 3v 2 5v and Ov Gnd connections are available These supplied voltages must be regulated and free from noise When the 3 3v supply is active the LD2 indication will illuminate This will also illuminate on connection of an active USB cable and is NOT a guarantee of all power supply voltages being correct The module CANNOT be powered using only the USB Installing the PC Interface Before the Windows application can be used it is necessary to load the appropriate USB driver files on to the PC This process only needs to be completed once and is quite simple Insert the supplied CD into the PC Ensure that L2 on the module is set with pins two and three linked Make sure the USB cable is not connected to the module and then power it up Connect the USB cable to the module The PC will now detect the new hardware and start the standard windows driver install When prompted for the location of the driver browse to the DRIVERS directory on the supplied CD Copy the apt_eval exe from the CD onto an appropriate place on the PC such as Desktop Run the apt_eval exe file This will now bring up a new window with all the configuration options shown Using the PC Interface This method of configuration is using the supplied Windows application via the USB port on the module To ensure correct operation of this mode L2 on the module must have pins two and three linked and the DIP switches must all be i
13. ve a pull of 100p p m this is why the clock provided to a module in slave mode must be accurate and stable The following pages show the switch settings for all the modes and the associated clocks that are generated required The data clock must match the data rate for example 384kb s needs a 384kHz clock The modes highlighted with a grey background are functional however there is little point running the DSP set for 20kHz when the incoming bandwidth is restricted to 15kHz by the 32kHz incoming sample rate An electronic copy of the module s schematic is included on the supplied CD apt X Eval SCM To view this requires CADSTAR 5 0 or greater alternatively there is a viewer available FREE at http www cadstarworld com down viewer6 asp Po Rev 1 0 Stereo Mono Function apt X Evaluation CoDec kb s 20 bit Master mode SRC Bypass S PDIF in 48kHz Stereo Loopback Master mode SRC Bypass S PDIF in 48kHz Mono Loopback Master mode SRC Bypass S PDIF in 32kHz Stereo Loopback Master mode SRC Bypass S PDIF in 32kHz Mono Loopback Master mode SRC Bypass S PDIF in 44 1kHz Stereo Loopback Master mode SRC Bypass S PDIF in 44 1kHz Mono Loopback Master mode SRC Bypass S PDIF in 48kHz Stereo Loopback Master mode SRC Bypass S PDIF in 48kHz Mono Master mode SRC S PDIF out 32kHz 7kHz Stereo Loopback Master mode SRC S PDIF out 32kHz 7k
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