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M30201 Group User`s manual (tentative)

1. Note This register is only exist in flash memory version Figure 1 8 Location of peripheral unit control registers 2 11 xX O Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CPU Central Processing Unit CPU The CPU has a total of 13 registers shown in Figure 1 9 Seven of these registers RO R1 R2 R3 AO A1 and FB come in two sets therefore these have two register banks bo Program counter Data registers b15 bo b19 bo INTB H L Interrupt table LIHAA register b15 j User stack pointer b15 b15 Moo Interrupt stack Loittiitiiiitit pointer Address b15 bO registers b15 Static base LLttttirtitiiiit pni ee ai register b15 bo b15 bo Frame base Flag register Pittttititiiritt registers a a a a i o B s z Note These registers consist of two register banks Figure 1 9 Central processing unit register 1 Data registers RO ROH ROL R1 R1H R1L R2 and R3 Data registers RO R1 R2 and R3 are configured with 16 bits and are used primarily for transfer and arithmetic logic operations Registers RO and R1 each can be used
2. LII Set to 1 by software Cleared to 0 by software A D conversion start flag A D register 0 x Result A D register 1 A D register i X Result Note When lt ap frequency is less than 1MHz sample and hold function cannot be selected Conversion rate per analog input pin is 49 sap cycles for 8 bit resolution and 59 ab cycles for 10 bit resolution Figure 2 7 11 Operation timing of repeat sweep 0 mode 284 O aS Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter Selecting Sample and hold b7 b0 olololi A D control register 2 Address 03D416 D D D D l ADCON2 L A D conversion method select bit 1 With sample and hold Must be fixed to 0 k a Setting A D control register 0 and A D control register 1 b7 bo b7 0 0 0 1 A D control register 0 Address 03D616 A D control register 1 Address 03D716 ADCONO ADCON1 Invalid in repeat sweep mode 0 A D sweep pin select bit Note 2 b1 bo 00 ANo AN1 2 pins 0 1 ANo to ANs 4 pins i 1 0 ANo to ANs 6 pins Must be fixed to 0 11 ANo to AN7 8 pins Repeat sweep m
3. Address Register Page Address Register Page 038016 Count start flag TABSR 51 030015 A D register 0 ADO 038116 Clock prescaler reset flag CPSRF 03C116 9 ADO 038216 One shot start flag ONSF 52 osc2ie Ap register 1 AD1 038316 Trigger select register TRGSR 030316 038416 Up down flag UDF 51 03C4ie a i 038516 g pene A D register 2 AD2 088616 T 030616 o3a7ie Timer AO TAO 51 o7 AD register 3 AD3 n 088816 nT 03C816 i 038916 Timer XO TX0 CI A D register 4 AD4 038A16 J 03CA16 o3gBie Timer X1 TX1 67 ca A D register 5 ADS 038616 Ti 03CC16 n osspie TimMer X2 TX2 asop AD register 6 AD6 038E16 Clock divided counter CDC O8CE16 A i 038F 16 Cacris A D register 7 AD7 03901 i 03D016 039116 1Imer BO TBO si 03D116 ieee 03D216 o39316 mer B1 TB1 03D316 Saag 03D41s A D control register 2 ADCON2 93 099916 03D516 039616 Timer AO mode register TAOMR 50 03D616 A D control register 0 ADCONO 039716 Timer XO mode register TXOMR 030716 A D control register 1 ADCON1 92 039816 Timer X1 mode register TX1MR 66 03D816 039916 Timer X2 mode register TX2MR 03D916 039A16 03DA16 039B16 Timer BO mode register TBOMR 60 03DB16 039C16 Timer B1 mode register TB1MR 03DC16 039016 03DD16 039E16 03DE16 039F16 03DF16 03A016 UARTO transmit receive mode register UOMR
4. A D control register 0 address 03D616 Addresses i 03C116 03C016 A D register 0 16 03C316 030216 A D register 1 16 03C516 030416 A D register 2 16 16 16 03C716 03C616 A D register 3 03C916 03C816 A D register 4 03CB16 03CA16 A D register 5 16 03CD16 03CC16 A D register 6 16 03CF16 03CE16 A D register 7 16 Data bus high order Decoder VIN Comparator AhaAdAaAdA Data bus low order YVYVVVYVVY H2 CH1 CHO 000 H2 CH1 CHO 001 H2 CH1 CHO 010 ADGSELO 0 H2 CH1 CHO 011 H2 CH1 CHO 100 oo H2 CH1 CHO 101 H2 CH1 CHO 110 H2 CH1 CHO 111 ee merry P50 AN50 O CH2 CH1 CH0 000_5 o P51 AN51 CH2 CH1 CH0 001 0 0 ADGSELO 1 P52 ANs2 O CH2 CH1 CHO 010 a E P53 ANs3 O CH2 CH1 CHO 011_S P54 AN54 CH2 CH1 CHO 100 O Port P6 group P60 ANo P61 AN1 P62 AN2 O P63 AN3 O P64 AN4 P6s ANs O P66 AN6 O P67 AN7 O 190 IO JIO Q Q QOO Figure 1 82 Block diagram of A D converter 91 x N Q gf Mitsubishi microcomputers Sas M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter A D con
5. bo Port P3 direction register 1 1 Address 03E716 PD3 Key scan output port P04 to P07 pulled high bo Port P3 register o Address 03E516 P3 b7 Key input interrupt control register bo Key scan data KEKX 0 ol ea hea 004D16 Interrupt enable level IPL 0 Interrupt priority level select bit Interrupt enable flag I 0 Set higher value than the present IPL Se A f Setting interrupt except stop mode cancel Interrupt control register KUPIC Address 004D16 ADIC Address 004E16 SiTIC i Address 005116 005316 SIRIC i Address 005216 005416 TAIIC Address 005516 b7 bo TXilC 2 Address 005616 to 005816 KKK 0 0 TBIIC i 0 1 Address 005A16 005816 INTiIC i 0 1 Address 005D16 005E16 Interrupt priority level select bit Interrupt priority level select bit 0 0 0 Interrupt disabled 000 Interrupt disabled Always set to 0 re i 0 ti Sooo o ie Canceling protect b0 b7 2 Protect register Address 000A16 ARAA ZA 1 PRCR Enables writing to system clock control registers 0 and 1 addresses 000616 and 000716 1 Write enabled Setting operation clock after returning from stop mode When operating with XIN after returning When operating with XCIN after returning i bo System
6. Setting UARTO transmit receive control register 0 UARTO transmit receive control register 0 U0CO Address 03A416 BRG count source select bit b1 bO 0 0 f1 is selected 0 1 fs is selected 10 fs2 is selected 11 fc is selected Must be 0 in clock synchronous I O mode Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed Must be 1 in clock synchronous I O mode Data output select bit Note 0 TxDi pin is CMOS output 1 TxDi pin is N channel open drain output CLK polarity select bit 0 Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 LSB first Note Set the corresponding port direction register to 1 output mode Setting UART transmit receive control register 2 b7 UART transmit receive control register 2 UCON Address 03B016 UARTO transmit interrupt cause select bit 1 Transmission completed TXEPT 1 Must be 0 in clock synchronous I O mode Must be 0 in clock synchronous I O mode CLK CLKS select bit 0 0 Clock output to CLKO 1 Clock output to CLKS CLK CLKS select bit 1 1 Transfer clock output from multiple pins finction selected Continued to the next page Figure 2 5 9 Set up procedure of transmission in clock
7. Processor mode register 1 000516 34 Timer B1 mode register 039C 16 35 UARTO transmit receive mode of 35 recister 03A016 36 UARTO transmit receive control register 0 Address match interrupt 37 UARTO transmit receive control 03A516 enable register 000916 register 1 38 UART1 transmit receive mode register 39 UART1 transmit receive control register 0 System clock control register 0 000616 System clock control register 1 000716 03A416 Protect register OO0A16 03A816 Watchdog timer control register 000F 16 03AC16 Address match interrupt 001016 40 UART1 transmit receive control 03AD16 register 0 register 1 41 UART transmit receive control register 2 Flash memory control register 0 ai 42 001216 42 Note Address match interrupt 001416 43 Flash memory control register 1 03B516 register 1 Note 001516 44 Flash command register 03B616 4 001116 03B016 03B416 001616 45 A D control register 2 03D416 10 Key input interrupt control register 004D16 2 46 A D control register 0 03D616 a Da e EA interrupt 004E16 2 47 A D control register 1 03D716 iE pads
8. Note 2 The CLKO pin level when not TXDo x Do x D1 x D2 yx D3 x D4 x D5 X D6 X D7 transferring data is L X Do X D1 X D2 X D3 X D4 X D5 X De X D7 RXDo Do D1 Figure 1 76 Polarity of transfer clock b LSB first MSB first select function As shown in Figure 1 77 when the transfer format select bit bit 7 at addresses 03A416 0 the transfer format is LSB first when the bit 1 the transfer format is MSB first e When transfer format select bit 0 CLKo TXDo X Do X D1 X D2 X D3 X D4 X D5 X De X D7 RXDo X Do X Di X D2 X D3 X D4 X D5 X De X D7 LSB first e When transfer format select bit 1 CLKo TXDo X D7 X De X Ds X D4 X D3 X D2 X Dt X Do RXDo X D7 X De X Ds X D4 X D3 X D2 X Di X Do MSB first Note This applies when the CLK polarity select bit 0 Figure 1 77 Transfer format 84 amp CA 7 siai A Mitsubishi Icroco puters s M30201 Group RA Q ve 2 SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock synchronous serial I O mode c Transfer clock output from multiple pins function This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit bits 4 and 5 at address 03B016 See Figure 1 78 The multipl
9. Table 1 55 Serial I O Standard Parameter Min Max tc CK CLKO input cycle time tw CKh CLKO input HIGH pulse width tw CKL CLKO input LOW pulse width ta C Q TxDi output delay time th C Q TxDi hold time tsu D C RxDi input setup time th C D RxDi input hold time Table 1 56 External interrupt INTi inputs aoe Symbol Parameter Unit tw INH INTi input HIGH pulse width tw INL INTi input LOW pulse width 118 x xe R Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 5V TAOIN input TAOOUT input TAOOUT input Up down input x During event counter mode TAOIN input When count on falling th Tin UP tsu UP Tin edge is selected TAOIN input When count on rising edge is selected TBIIN input TXiINOUT input TxDi RxDi INTI input PX A we lt SF ww Electrical characteristics Vcc 3V Table 1 57 Electrical characteristics Note 1 HIGH output voltage Parameter POo to P07 P10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Vcc 3V Standard Measuring condition loH 1mA Min Typ Max HIGH output voltage HIGHPOWER LOWPOWER XOUT loH 1 mA loH
10. Transition of stop mode wait mode Normal mode Transition of normal mode Main clock is oscillating Sub clock is stopped Medium speed mode divided by 8 mode CMO6 1 BCLK f Xin 8 CM07 0 CMO6 1 Main clock is oscillating CM04 of ee ao Sub clock is oscillating Notas 1 0 Reset All oscillators stopped 1 s WAIT CPU operation stopped a CM10 1 Medium speed mode instruction i Stop mode eee oUm Sp Wait mode k SOP mo y Interrupt divided by 8 mode _ Interrupt Ne es All oscillator Intorty t wait CPU operation d 24 High speed medium Hnstruction p Stop mode ME Wait mode eee ees j speed mode _ Interrupt ene ji WAIT C d Stop mode 422 Low speea iow power piostucton gt Wait mode Interrupt dissipation mode _ Interrupt Refer to the following for the transition of normal mode Note 1 3 _ CM07 1 Note 2 CMO5 1 Main clock is oscillating Sub clock is oscillating Low speed mode CM07 0 BCLK f XciNn CM07 1 CM07 1 Note 2 CMO05 0 CMO05 1 Main clock is stopped Sub clock is oscillating Low power dissipation mode BCLK f XciNn CM07 1 Medium speed mode High speed mode divided by
11. 0 Must always be 0 in event counter mode Count operation type select bit 0 Reload type Invalid in event counter mode Can be 0 or 1 Note Set the corresponding port direction register to 1 output mode ee TXiINOUT pin input is not selected as count source when pulse output function is selected Setting trigger select register Be Trigger select register Address 038316 TRGSR Timer X0 event trigger select bit b3 b2 0 1 TB1 overflow is selected 1 0 TAO overflow is selected 1 1 TX1 overflow is selected Timer X1 event trigger select bit b5 b4 0 1 TB1 overflow is selected 1 0 TXO overflow is selected 1 1 TX2 overflow is selected Timer X1 event trigger select bit b7 b6 0 1 TB1 overflow is selected 10 TX1 overflow is selected 1 1 TAO overflow is selected i Setting divide ratio b15 b8 ate uaa bO Timer XO register Address 038916 038816 TXO Timer X1 register Address 038B16 038A16 TX1 Timer X2 register Address 038D16 038C16 TX2 o Can be set to 000016 to FFFF16 Setting count start flag b7 b0 Count start flag Address 038016 TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag Start count Figure 2 4 11 Set up procedure of event counter mode reload type selected 219 O s Mitsubishi microcomputers Ss M30201 Group ro SINGLE CHIP 16 BIT CMOS MICROC
12. Pull up selection Direction register D gt lt Data bus Port latch Pull up selection Direction register e gt i lt output Data bus 4 Port latch i Input to respective peripheral functions P40 P43 P44 Figure 1 90 Programmable I O ports 1 101 x Q amp Mitsubishi microcomputers SF M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Port Pull up selection Pio to P17 Direction register i K Data bus Port latch Dy i Drive capacity control register Pull up selection Direction register K Data bus Port latch Analog input Serial I O input Pull up selection Direction register t gt i lt Data bus Port latch P50 P53 P54 Analog input Pull up selection Direction register gt i lt Data bus Port latch Serial clock input Gf Analog input Figure 1 91 Programmable I O ports 2 102
13. 50 x N amp sf Mitsubishi microcomputers ve M30201 Group d SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Timer AO register Note oY po Address When reset 038716 038616 Indeterminate Function Values that can be set Timer mode 000016 to FFFF16 Counts an internal count source e Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow One shot timer mode 000016 to FFFF16 Counts a one shot width XO e Pulse width modulation mode 16 bit PWM Functions as a 16 bit pulse width modulator Pulse width modulation mode 8 bit PWM oore to FF16 Timer low order address functions as an 8 bit t ma prescaler and high order address functions as an 8 bit 0016 to FE16 Low pulse width modulator order addresses Note Read and write data in 16 bit units Count start flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset TABSR 038016 000X00002 Bit symbol Bit name Function 4 TAOS Timer AO count start flag 0 Stops counting Timer XO count start flag 1 Starts counting Timer X1 count start flag Timer X2 count start flag Nothing is assigned When write set 0 When read their contents are indeterminate Timer BO count start flag 0 Stops counting 1 Starts counting Timer B1 count start flag Clock devided count start flag Up down flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset UDF 038416 XXX0XXX02 Timer A0 up down flag 0 Down
14. Timer mode 000016 to FFFF16 Counts an internal count source e Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow e One shot timer mode 000016 to FFFF16 XO Counts a one shot width e Pulse period pulse width measurement mode o x Measures a pulse period or width e Pulse width modulation mode 16 bit PWM Functions as a 16 bit pulse ah St e Pulse width modulation mode 8 bit PWM 0016 to FF 16 Timer low order address functions as an 8 bit tae prescaler and high order address functions as an 8 bit 0016 to FFi6 Low pulse width modulator order addresses Note Read and write data in 16 bit units Count start flag b7 b6 b5 b4 b3 b2 bi bd Symbol Address When reset TABSR 038016 000X00002 Timer AO count start flag 0 Stops counting 1 Starts counting Nothing is assigned When write set 0 When read their contents are indeterminate TBOS Timer BO count start flag 0 Stops counting o o TB1S Timer B1 count start flag hse Staite counting CDCS Clock devided count start flag Figure 1 58 Timer X related registers 2 67 x Ss Q s Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X One shot start flag Smed E Wasi wade b7 b6 b5 b4 b3 b2 bi bO ONSF 038216 XXXX00002 PODOI LL 1 Tiner san eo When read the value is 0 Nothing is assigned When write set 0 When read its content is indeterminate yroccce Trigge
15. b15 bo FB Note Frame base Flag register A A A T A A A A O E registers ER EUL LGEE Figure 1 10 Flag register FLG 14 x xe gf Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Reset Reset There are two kinds of resets hardware and software In both cases operation is the same after the reset See Software Reset for details of software resets This section explains on hardware resets When the supply voltage is in the range where operation is guaranteed a reset is effected by holding the reset pin level L 0 2Vcc max for at least 20 cycles When the reset pin level is then returned to the H level while main clock is stable the reset status is cancelled and program execution resumes from the address in the reset vector table Figure 1 11 shows the example reset circuit Figure 1 12 shows the reset sequence Ped ps Example when Vcc 5V Figure 1 11 Example reset circuit More than 20 cycles are needed RESET BCLK 24cyc Internal clock Content of reset vector Address FFFFC16 FFFFE16 Y Internal address signal Figure 1 12 Reset sequence 15 x O R Mitsubishi microcomputers NO M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Processor mode register 0 000416 33 Timer BO mode register 039B16
16. 0 PM03 Software reset bit The device is reset when this bit is set to 1 The value of this bit is 0 when read Nothing is assigned When write set 0 When read their contents are indeterminate Note Set bit 1 of the protect register address 000A16 to 1 when writing new values to this register Processor mode register 1 Note b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset DYDUD ele PM1 000516 00XXXXX02 Reserved bit Must always be set to 0 loio Nothing is assigned When write set 0 When read their contents are indeterminate PM17 Wait bit i No wait state Wait state inserted Note Set bit 1 of the protect register address 000A16 to 1 when writing new values to this register Figure 1 14 Processor mode register 0 and 1 17 xX Cy O RX Mitsubishi microcomputers SF of M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Bus Control Software wait The wait bit bit 7 of the processor mode register 1 address 000516 note allows you to insert software wait states for the internal ROM RAM areas If this bit is 0 the bus cycle is executed in one BCLK internal clock period if the bit is 1 the bus cycle is executed in two BCLK periods This bit is cleared to 0 after a reset The SFR area is unaffected by this control bit it is always accessed in two BCLK periods Table 1 2 shows the relationship between software wait states and bus cycles Note Bef
17. Count start flag Timer Bi interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software Timer Bi overflow flag Note 1 Counter is initialized at completion of measurement Note 2 Timer has overflowed Figure 2 3 10 Operation timing of pulse width measurement mode 204 x O S S Mitsubishi microcomputers Sy O M30201 Group 2 SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B Selecting pulse period pulse width measurement mode and functions Timer Bi mode register i 0 1 Address 039B16 039C16 TBiMR i 0 1 Selection of pulse period pulse width measurement mode Measurement mode select bit b3 b2 1 0 Pulse width measurement Interval between measurement pulse falling edge to rising edge and between rising edge to falling edge Timer Bi overflow flag 0 Timer did not overflow 1 Timer has overflowed pi source selectbit Count Count source period O0 f1 i Source f XIN 10MHz_ f XcIN 32 768kHz 01 fe 100ns 10 f32 800ns 1 fc32 7 3 2us 976 56us Note Set the corresponding port direction register which sets the measurement pulse to 0 input mode Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 Clock prescaler reset flag Address 038116 LADD CPSRF Clock p
18. Program counter PCL Program counter PCm Flag register FLG Program counter PCx Flag register FLGu Sequence in which order registers are saved Saved simultaneously all 8 bits Finished saving registers in four operations Note SP denotes the initial value of the stack pointer SP when interrupt request is acknowledged After registers are saved the SP content is SP minus 4 Figure 1 28 Operation of saving registers 41 X Se Mitsubishi microcomputers Q Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register FLG as it was immediately before the start of interrupt sequence and the contents of the program counter PC both of which have been saved in the stack area Then control returns to the program that was being executed before the acceptance of the interrupt request so that the suspended process re sumes Return the other registers saved by software within the interrupt routine using the POPM or similar in struction before executing the REIT instruction Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling checking whether interrupt requests are made the interrupt assigned a higher priority is accepted Assign an arbitrary priority to maskable
19. Repeat sweep mode 1 is selected Note 1 A D operation mode select bit 1 Note 1 1 Must always be 1 in repeat sweep mode 1 8 10 bit mode select bit Frequency select bit 0 0 8 bit mode 0 fAD 4 is selected 1 10 bit mode 1 fap 2 is selected A D conversion start flag 0 A D conversion disabled Frequency select bit 1 O faD 2 or fAD 4 is selected 1 fab is selected Vref connect bit 1 Vref connected _____________ Must be fixed to 0 _ A D input group select bit 0 Port P6 group is selected Note 1 Rewrite to analog input pin select bit after changing A D operation mode 1 Port P5 group is selected Note 2 Set the corresponding port direction register to 0 input mode When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins ANso to ANsa A Setting A D conversion start flag b7 b0 A D control register 0 Address 03D616 ADCONO A D conversion start flag 1 A D conversion started N Converts non selected pin after converting pins selected through the A D sweep pin select bit CLETELETTTETTTTTTTTTETETTTLTTTTELETTEITTTEETTTTETTTTETTTTETTTTTTTT a Start A D conversion Reading conversion result A D register O Address 03C116 03C016 015 bs A D register 1 Address 03C316 03C216 b7 bO b7 A D register2 Address 03C516 03C416 XxXKKKE A D register 3 Addre
20. moo A D operation mode 1 1 Repeat sweep mode 0 select bit 0 Set this bit to 0 A D conversion start flag 0 A D conversion disabled 1 A D conversion started Frequency select bit 0 0 faD 4 is selected 1 fap 2 is selected Note If the A D control register is rewritten during A D conversion the conversion result is indeterminate A D control register 1 Note 1 b7 b6 b5 b4 b3 b2 bi b0 CEPLER Bu a ae Bit symbol Bit name Function A D sweep pin select bit When single sweep and repeat sweep mode 0 are selected b1 b0 0 0 ANo AN1 2 pins 0 1 ANo to AN3 4 pins l o ANo to AN5 6 pS ANo to AN7 8 pins Note 2 3 A D operation mode Set this bit to 0 in this mode select bit 1 BITS 8 10 bit mode select bit 0 8 bit mode 1 10 bit mode CKS1 Frequency select bit 1 n faD 2 or fAD 4 is selected faD is selected VCUT Vref connect bit 1 Vref connected Set this bit to 0 ADGSELO A D input group select bit O Port P6 group is selected 1 Port P5 group is selected Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 ANso to AN54 can be used in the same way as for ANo to AN4 Note 3 If port P5 group is selected the contents of A D registers 5 to 7 are indeterminate Figure 1 88 A D conversion register in repeat sweep mode 0 97 Q gf Mitsubishi microcomputers Sas M30201 Group SINGLE
21. x Cy O s Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Port Pull up selection Direction register id P60 to P67 Data bus Port latch Analog input Figure 1 92 Programmable I O ports 3 103 Q gf Mitsubishi microcomputers Sas M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Port Port Pi direction register Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PDi i 0 to 7 03E216 03E316 03E716 03EA16 0016 03EB16 03EE16 03EF16 0016 Bit symbol PDi_O Port Pio direction register 10 0 i TEN 0 Input mode Port Pit direction register Functions as an input port 1 Output mode Functions as an output port i 0107 except 2 POLS Port Pie direction register Note 1 Set bit 2 of protect register address 000A16 to 1 before rewriting to the port P4 direction register Note 2 Nothing is assigned in direction register of P36 P37 P46 P47 P55 to p57 P72 to P77 These bits can either be set nor reset When read its contents are indeterminate Figure 1 93 Direction register 104 x N O sf Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Port Port Pi register be be BE ba baba bibo Symbol Address When reset Pi
22. 1 is written to this bit returns the bit Figure 2 1 1 Protect register 2 1 2 Protect Operation The following explains the protect operation Figure 2 1 2 shows the set up procedure Operation 1 Setting 1 in the write enable bit of system clock control registers 0 and 1 causes system clock control register 0 and system clock control register 1 to be in write enabled state 2 The contents of system clock control register 0 and that of system clock control register 1 are changed 3 Setting O in the write enable bit of system control registers 0 and 1 causes system clock control register 0 and system control register 1 to be in write inhibited state 4 To change the contents of processor mode register 0 and that of processor mode register 1 follow the same steps as in dealing with system clock control registers 5 The write enable bit of port P4 direction register goes to 0 when the next write instruction is executed after write enabled state is readied Make changes in input output immediately af ter the instruction that sets 1 in the write enable bit of port P4 direction register avoid causing an interrupt 160 x xe Mitsubishi microcomputers SX M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Protect 1 Clearing the protect set to write enabled state bO Protect register Address 000A16 PRCR Enables writing to system clock control registers 0 and 1 addresses 000616 and 0
23. 4016 in the first bus cycle When an address and data to be program is write in the second bus cycle the flash memory control circuit executes the program operation The program operation requires approximately 20 us Wait for 20 us or more before the user go to the next processing Note 1 The write operation is not completed immediately by writing a program command once The user must always execute a program verify command after each program command executed And if verification fails the user need to execute the program command repeatedly until the verification passes See Figure CC 4 for an example of a programming flowchart 140 x Cy O s Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Parallel I O Mode Program verify command C016 The program verify mode is entered by writing the command code C016 in the first bus cycle and the verify data is output from the data I O pins Do D7 in the second bus cycle Erase command 2016 2016 The flash memory control circuit executes an erase operation by writing command code 2016 in the first bus cycle and the same command code again in the second bus cycle The erase operation requires approximately 20 ms Wait for 20 ms or more before the user go to the next processing Before this erase command can be performed all memory locations to be erased must have had data 0016 written to by using the program and program veri
24. CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 Setting count start flag b7 b0 Count start flag Address 038016 TABSR Timer BO count start flag Timer B1 count start flag Start count Paii overflow Ki Timer Bi Ton register i 0 1 Address 039B16 to 039D16 TTX CT TBIMR i 0 1 Timer Bi overflow flag 0 Timer did not overflow Figure 2 3 9 Set up procedure of pulse period measurement mode 203 O S Mitsubishi microcomputers SS M30201 Group sy SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 3 5 Operation of Timer B pulse width measurement mode In pulse period pulse width measurement mode choose functions from those listed in Table 2 3 4 Op erations of the circled items are described below Figure 2 3 10 shows the operation timing and Figure 2 3 11 shows the set up procedure Table 2 3 4 Choosed functions Count source Internal count source f1 fs f32 fc32 Measurement Pulse period measurement interval between measurement pulse falling edge to falling edge mode Pulse period measurement interval between measurement pulse rising edge to rising edge Pulse width measurement interval between measurement pulse falling edge to rising edge and between rising edge to falling edge Operation 1 Setting the count start flag to 1 causes the counter to start counting the count so
25. Interrupt enable flag I flag xz Interrupt request Address match accepted Watchdog timer Figure 1 30 Interrupt resolution circuit 43 N Q s Mitsubishi microcomputers Sy M30201 Group a SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Key Input Interrupt Key Input Interrupt If the direction register of any of POo to P07 is set for input and a falling edge is input to that port a key input interrupt is generated A key input interrupt can also be used as a key on wakeup function for cancelling the wait mode or stop mode Figure 1 31 shows the block diagram of the key input interrupt Note that if an L level is input to any pin that has not been disabled for input inputs to the other pins are not detected as an interrupt Port P04 P07 pull up select it b Pull up Key input interrupt control register address 004D16 transistor Port P07 direction register Port P07 direction register P07 KI7 Port P06 direction Pull u ie register transistor Interrupt control Key input interrupt P06 Kl6 i circuit request Pull up transistor Port P01 direction register Poi Kli O y Port POo direction register Pull up transistor Poo Ko O m Da Figure 1 31 Block diagram of key input interrupt 44 eS Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Address Match Interrupt Address Match Interrupt An address match interrupt is generat
26. It is affected neither by the processor interrupt priority level IPL nor the interrupt enable flag I flag 2 Timing of the address match interrupt An interrupt occurs immediately before executing the instruction in the address indicated by the ad dress match interrupt register Set the first address of the instruction in the address match interrupt register Setting a half address of an instruction or an address of tabulated data does not generate an address match interrupt The first instruction of an interrupt routine does not generate an address match interrupt either 3 Returning from an address match interrupt The return address put in the stack when an address match interrupt occurs depends on the instruc tion not yet executed the instruction the address match interrupt register indicates The return ad dress is not put in the stack For this reason to return from an address match interrupt either rewrite the content of the stack and use the REIT instruction or use the POP instruction to restore the stack to the state as it was before the interrupt occurred and return by use of a jump instruction Figure 2 9 1 shows unexecuted instructions and corresponding the stacked addresses lt Instructions whose address is added to by 2 when an address match interrupt occurs gt e 16 bit operation code instructions e 8 bit operation code instructions given below ADD B S IMM8 dest SUB B S IMM8 dest AND B S IMM8 dest OR B
27. No overrun error 0 Note 1 Overrun error found Overrun error found Framing error flag Invalid No framing error Note Framing error found Parity error flag Invalid No parity error Note Parity error found Error sum flag Invalid No error Note Error found Note Bits 15 through 12 are set to 0 when the serial I O mode select bit bits 2 to 0 at addresses 03A016 and 03A816 are set to 0002 or the receive enable bit is set to 0 Bit 15 is set to O when bits 14 to 12 all are set to 0 Bits 14 and 13 are also set to 0 when the lower byte of the UARTIi receive buffer register addresses 03A616 and 0 3AE16 is read out UARTI bit rate generator b7 bO Address When reset 03A116 Indeterminate Lo 03A916 Indeterminate Values that can be set Assuming that set value n BRGi divides the 0016 to FFie xO count source by n 1 Figure 2 6 3 UARTi related registers 1 261 Q e Mitsubishi microcomputers Sy M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UARTI transmit receive mode register Address 03A016 03A816 When reset 0016 b7 b6 b5 b4 b3 b2 bi b0 Symbol UiMR i 0 1 Function During clock synchronous serial I O mode Must be fixed to 001 b2 b1 b0 0 0 Serial I O invalid 10 Inhibited 11 Inhibited 11 Inhibited Function During UART mode Bly Bit name N att O MOOO a 0000r Z
28. Serial I O mode select bit Note 1 2 Transfer data 7 bits long Transfer data 8 bits long Transfer data 9 bits long Serial I O invalid Inhibited Inhibited Inhibited OO 0 Internal clock 0 Internal clock o o 1 External clock 1 External clock Invalid 0 One stop bit ISING stop bits ais Invalid Valid when bit 6 1 OO Odd parity Invalid AOOO nm hmg 0 0 0 1 Internal external clock select bit Note 2 Stop bit length select bit Odd even parity select bit Even parity Parity disabled Parity enable bit I Parity enabled Sleep mode deselected Sleep select bit Sleep mode selected Must always be 0 Note 1 UART1 cannot be used in clock synchronous serial I O Note 2 UART1 can use only internal clock Must set this bit to 1 UARTi transmit receive control register 0 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset UiCO i 0 1 03A416 O3AC16 0816 Function Note During clock synchronous serial I O mode Bit name bi bO Function During UART mode bi bO BRG count source h 0 0 f1 is selected select bit 0 1 fs is selected 1 0 f32 is selected 11 fc is selected 0 0 fi is selected 0 1 fa is selected 1 0 f32 is selected 1 1 fc is selected Set this bit to 0 Data present in transmit register during transmission No data present in transmit register transmission comple
29. TMOD1 select bit measurement mode Measurement mode 3t select bit 0 0 Pulse period measurement Interval between measurement pulse s falling edge to falling edge 0 1 Pulse period measurement Interval between measurement pulse s rising edge to rising edge Nothing is assigned When write set 0 When read their contents are indeterminate Timer Bi overflow Timer did not overflow flag Note Timer has overflowed Count source select bit 1 0 Pulse width measurement Interval between measurement pulse s falling edge to rising edge and between rising edge to falling edge 1 1 Inhibited Note The timer Bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer Bi mode register This flag cannot be set to 1 by software Figure 1 53 Timer Bi mode register in pulse period pulse width measurement mode 64 O s Mitsubishi microcomputers SF of M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Measurement pulse l Transfer measured value Reload register counter transfer timing Timing at which counter reaches 000016 Count start flag Timer Bi interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software Timer Bi overflow flag Ej Note 1 Counter is initialized at completion of measurement Note 2 Timer has overflowed Figure 1 54 Operation timing when measuring a pulse per
30. When writing to the timer register when a count is stopped the value is written both to the reload register and to the counter Write a value in 16 bit units 6 Relation between the input output to from the timer and the direction register With the output function of the timer set the direction register of the relevant port to input To input an external signal to the timer set the direction register of the relevant port to input 7 Pins related to timer A a TAOIN Input pins to timer A b TAQOUT Output pins from timer A They become input pins to timer A when event counter mode is active 163 X Ss Q RY Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 8 Registers related to timer A Figure 2 2 1 shows the memory map of timer A related registers Figures 2 2 2 through 2 2 5 show timer A related registers 005516 Timer AO interrupt control register TAOIC EN X 038016 Count start flag TABSR 038116 Clock prescaler reset flag CPSRF 038216 One shot start flag ONSF 038316 Trigger select register TRGSR 038416 Up down flag UDF 03861 Timer AO TAO 038716 NA az 039616 Timer AO mode register TAOMR Figure 2 2 1 Memory map of timer A related registers Timer AO mode register Symbol Address When reset b7 b6 b5 b4 b3 b2 bi bO TAOMR 039616 0016 Bit symbol RW Operation mode select bit t Timer mode Event c
31. 1 2 4 8 or 16 The BCLK is derived by dividing the main clock by 8 after a reset The main clock division select bit O bit 6 at address 000616 changes to 1 when shifting from high speed medium speed to stop mode and at reset When shifting from low speed low power dissipation mode to stop mode the value before stop mode is retained 4 Peripheral function clock f1 f8 32 fAD The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32 The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit bit 2 at 000616 to 1 and then executing a WAIT instruction 5 fc32 This clock is derived by dividing the sub clock by 32 It is used for the timer A timer B and timer X counts 6 fc This clock has the same frequency as the sub clock It is used for BCLK and for the watchdog timer 21 xX S amp S gS Mitsubishi microcomputers s X M30201 Group a SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Generating Circuit Figure 1 18 shows the system clock control registers 0 and 1 System clock control register 0 Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset CMO 000616 4816 Bil symbal b1 b0 Sar rh function 00 1 O port P54 loo Select bl 01 fc output i i fg output Clock divide counter output CMo2 WAIT peripheral function y T not stop peripheral function clock in wait mode clock stop
32. 10 fee 11 fc32 Figure 1 51 Timer Bi mode register in timer mode 62 N O S Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 Event counter mode In this mode the timer counts an external signal or an internal timer s overflow See Table 1 19 Figure 1 52 shows the timer Bi mode register in event counter mode Table 1 19 Timer specifications in event counter mode Count source e External signals input to TBIIN pin e Effective edge of count source can be a rising edge a falling edge or falling and rising edges as selected by software Count operation e Counts down e When the timer underflows it reloads the reload register contents before continuing counting Divide ratio 1 n 1 n Set value Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing The timer underflows TBIIN pin function Count source input Read from timer Count value can be read out by reading timer Bi register Write to timer When counting stopped When a value is written to timer Bi register it is written to both reload register and counter When counting in progress When a value is written to timer Bi register it is written to only reload register Transferred to counter at next reload time Timer Bi mode register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset IIX oli T
33. 79 03E016 Port PO PO ae 03A116 UARTO bit rate generator UOBRG 03E116 Port P1 P1 paan i 78 03E216 Port PO direction register PDO 034316 UARTO transmit buffer register UOTB o3E31e Port P1 direction register PDT 104 03A416 UARTO transmit receive control register 0 UOCO 79 03E416 Port P2 P2 03A516 UARTO transmit receive control register 1 U0C1 80 03E516 Port P3 P3 109 03A616 03E616 Port P2 direction register PD2 cena UARTO receive buffer register UORB 78 03716 Port P3 direction CET PD3 104 03A816 UART1 transmit receive mode register U1MR 79 03E816 Port P4 P4 105 o3A96 UART1 bit rate generator U1BRG 03E916 Port P5 P5 03AA16 78 03EA16 Port P4 direction register PD4 sna UART1 transmit buffer register U1TB 03EB16 Port P5 direction a PD5 104 03AC16 UART1 transmit receive control register 0 U1C0 79 O3EC16 Port P6 P6 105 03AD16 UART1 transmit receive control register 1 U1C1 80 O3ED16 cot et rae aan 03AE16 03EE16 ort irection register osak UARTI receive buffer register U1RB 72 dace Pon P7 ee es PD 104 038016 UART transmit receive control register 2 UCON 80 03F016 03B116 03F116 03B216 03F216 03B316 03F316 03B416 Flash memory control register 0 FCONO Note 03F416 03B516 Flash memory cont
34. Address 03AD16 Transmit enable bit 1 Transmission enabled Writing transmit data b15 b8 b7 b0 b7 b0 XXKKKKE d UARTO transmit buffer register Address 03A316 03A216 UOTB UART1 transmit buffer register Address 03AB16 O3AA16 U1TB Setting transmission data BANNNNNGNESENNNNAGENANNNNNNANENAENNNNNAGENNENNEENAGENNENNNNN Start transmission Checking the status of UARTi transmit buffer register i 0 1 b7 bo UARTO transmit receive control register 1 UOC1 Address 03A516 E UART1 transmit receive control register 1 U1C1 Address 03AD16 Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Writing next transmit data enabled 7 Writing next transmit data b15 b8 b7 bO b7 bO UARTO transmit buffer register Address 03A316 03A216 UOTB a UARTI transmit buffer register Address O3AB16 O3AA16 U1TB Setting transmission data a nnnnnnannnnnnnnnnnnnannnnnnnnannanannnnna a Jfansmission is complete Figure 2 6 8 Set up procedure of transmission in UART mode 2 267 N S Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART 2 6 3 Operation of Serial I O reception in UART mode In receiving data in UART mode choose functions from those listed in Table 2 6 5 Operations of the circled items are described below Figu
35. Figure 3 1 2 Connection diagram of long period timers 327 amp K amp Mitsubishi microcomputers S Y SF of M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications Setting timer X0 Selecting timer mode and functions roToT To OTe oT 0 T mode register Address 039716 Selection of timer mode Pulse output function select bit 0 Pulse is not output TXOINOUT pin is a normal port pin Gate function select bit b4 b3 0 0 Gate function not available TXOINOUT pin is a normal port pin 0 Must always be 0 in timer mode Count source select bit Count Count source period 6G i SOUICE Xin 10MHZ f Xcin 32 768kKHz 100ns 800ns 3 2us 976 56us Setting divide ratio b15 b8 b7 b0 b7 b0 n Setting timer X1 Selecting event counter mode and each function uli 00 Timer X1 mode register Address 039816 fofofofofofolol Txim Selection of event counter mode Pulse output function select bit 0 Pulse is not output TX1INOUT pin is a normal port pin Count polarity select bit 0 Must always be 0 in event counter mode 0 Must always be 0 in event counter mode Count operation type select bit 0 Reload type 0 Must always be 0 in event counter mode Continued to the next page Figure 3 1 3 Set up procedure of long period timers 1 328 iS FS M
36. Glock Control dihindari ia aai Manat ahi lai tenis 20 Aole HDLU Te U h EAE EEE E atege cies pe leaneee ad cre nina feeds ee ade viata Nee veka uit aces 23 Stop Mode eniinn eani aiaia eh ee he eae ac eel anal ete eae de ed ie 24 Wan MOJE sche Sareea clea eet kent ee eee ada ee eee atid 24 POWSR SAVING EAE E ae ctadane E E t Mocha ches Mea suc sect yal tadenuiat eid EAE 26 Protection stadiaiian ati eae beara ea data dite al aan E nid aia 28 laite nae EE D E T E E reer E reece ecerretcer EEE E cere reer errr rete err E E 29 jaren le a Wia AEE E EE E EE EE E E E T EAT T T E EN 47 TINO a E AA E a N rrerrene tree rere reece eee 49 TM Aerei a a ea e A E 50 TMT B rdan E EA E Renae aay 60 AE an O EAE N E E AE E ER E E ROE EA E EATE ET E E dears 66 Seall Orere e ae a AE eer e a a a a aa 76 AD Gonventei otantik a a a aa a a tea a lee Bl 90 Programmable lO POMS aces sc ccaie 5 exssngedecycans deck act tases bv sanbeceasancvesedesoGhinea paanasnbedeageathededus Puaecaaetauny tia ieedh 100 USAGES PreECAULlOM xc iccceiestccteccwergtuebecey Eee AE A EAEEREN E E AEE EEEE EEEE E AE ENESE 108 Electrical characte riStcs oara a A EAE E A EE EEEREN tines 112 Outline Performance Flash Memory cccccccceeeeeeceeeeeeeeeeeceaeeeeaaeesecaeeeeaaaesseeeesaaeeeeeeeesedaeeeseeeeeeas 126 FleaSI Mem rea eiar E E EEE ATAA N 127 OBA EAEAN oTo E AA E O EEA EET E EE EATE 128 Parallel O Mode a a a tite a a aa a a Aa OS 135 Standard Serial O Mode sret e aa a a a raa eaa a
37. M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Selecting PWM mode and functions I Timer Xi mode register i 0 to 2 Address 039716 to 039916 IT LELE TXiMR i 0 to 2 Selection of PWM mode 1 Must always be 1 in PWM mode Invalid in event counter mode Can be 0 or 1 Trigger select bit 1 Selected by event trigger select register 16 8 bit PWM mode select bit 1 Functions as a 8 bit pulse width modulator Count source select bit Count Count source period BABS X SOUICE f X n 10MHZ f Xcin 32 768kHz EL fi Toons 01 fs gt 10 f32 fs 800ns 11 fce32 fa2 3 2us fc32 976 56us Note Set the corresponding port direction register which outputs the pulse to 1 output mode Ne Clearing timer Xi interrupt request bit Refer to Precaution for Timer X pulse width modulation mode b7 b0 OOO Timer Xi interrupt control register i 0 to 2 Address 005616 to 005816 TXiIC i 0 to 2 Mes Interrupt request bit Setting trigger select register b7 b0 Trigger select register Address 038316 TRGSR Timer XO event trigger select bit b3 b2 0 1 TB1 overflow is selected 1 0 TAO overflow is selected 11 TX1 overflow is selected Timer X1 event trigger select bit b5 b4 0 1 TB1 overflow is selected 1 0 TXO overflow is selected 1 1 TX2 overflow is selected Timer X1 event
38. Max tw TAH TAOIN input HIGH pulse width 100 tw TAL TAOIN input LOW pulse width 100 Table 1 46 Timer A input up down input in event counter mode Standard Parameter Min Max tc UP TAOouT input cycle time tw UPH TAOouT input HIGH pulse width tw UPL TAOout input LOW pulse width tsu UP TIN TAOout input setup time th TIN UP TAOout input hold time N amp gf Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 5V Vcc 5V Timing requirements referenced to Vcc 5V VSS 0V at Ta 25 C unless otherwise specified Table 1 47 Timer B input counter input in event counter mode Standard Parameter Min Max tc TB TBiIN input cycle time counted on one edge tw TBH TBiiN input HIGH pulse width counted on one edge tw TBL TBiIN input LOW pulse width counted on one edge te TB TBiIN input cycle time counted on both edges tw TBH TBiIN input HIGH pulse width counted on both edges tw TBL TBiin input LOW pulse width counted on both edges Table 1 48 Timer B input pulse period measurement mode Standard Parameter Min Max tc TB TBIIN input cycle time tw TBH TBiIN input HIGH pulse width tw TBL TBiIN input LOW pulse width Table 1 49 Timer B input pulse width measurement mode Standard Parameter Min Max te TB TBiIN
39. Note Set the corresponding port direction register to 1 output mode va Setting UART transmit receive control register 2 XX o o o po UART transmit receive control register 2 UCON Address 03B016 UARTO transmit interrupt cause select bit 0 Transmit buffer empty TI 1 Must be 0 in clock synchronous I O mode Must be 0 in clock synchronous I O mode Valid when bit 5 1 CLK CLKS select bit 1 0 Normal mode Continued to the next page Figure 2 5 6 Set up procedure of transmission in clock synchronous serial I O mode 1 244 x N amp as Mitsubishi microcomputers ve M30201 Group d SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Continued from the previous page ff Setting UARTO bit rate generator b7 bo UARTO bit rate generator Address 03A116 UOBRG DE E Can be set to 0016 to FF16 Note Note Write to UARTO bit rate generator when transmission reception is halted Transmission enabled b7 b0 EXIDE UARTO transmit receive control register 1 Address 03A516 UOC1 Transmit enable bit 1 Transmission enabled Writing transmit data b8 b0 b7 UARTO receive buffer register Address 03A316 03A216 UOTB Setting transmission data m cececceceeececeuseeececeneeeeeeceusaeenereenaeeneeaa nents Start transmission la i S Checking the status of UARTO
40. Note 3 Set the corresponding port direction register to 1 output mode when the pulse is output Figure 1 45 Timer AO mode register in pulse width modulation mode 58 x A amp sf Mitsubishi microcomputers Sor M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Condition Reload register 000316 when external trigger rising edge of TAOIN pin input signal is selected 1 fix 216 1 u 1 1 1 Count source TAOIN pin input signal PWM pulse output from TAOOouT pin Timer AO interrupt request bit fi Frequency of count source f1 fs f32 fe32 Cleared to 0 when interrupt request is accepted or cleared by software Note n 000016 to FFFF16 Figure 1 46 Example of how a 16 bit pulse width modulator operates Condition Reload register high order 8 bits 0216 Reload register low order 8 bits 0216 External trigger falling edge of TAOIN pin input signal is selected 1 fi X m 1 X 2 1 rie EDT Count source Note1 TAOIN pin input signal Underflow signal of 8 bit prescaler Note2 q PWM pulse output from TAQouT pin Timer AO interrupt request bit fi Frequency of count source Cleared to 0 when interrupt request is accepted or cleaerd by software f1 fs f32 fc32 Note 1 The 8 bit prescaler counts the count source Note 2 The 8 bit pulse width modulator counts the 8 bit prescaler s underflow signal Note 3 m 0016 to FF16
41. PASS FAIL PASS FAIL Figure BB 3 Program and erase execution flowchart in the CPU rewrite mode 133 s S K S eS Appendix Parallel I O Mode Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Description of Pin Function Flash Memory Parallel I O Mode Pin name Voc Vss Signal name Power supply input Function Apply 5 V 10 to the Vcc pin and 0 V to the Vss pin CNVss CNVss Apply 12 V 5 to the CNVSs pin RESET Reset input Connect this pin to Vss XIN Clock input XOUT Clock output Connect a ceramic or crystal resonator between the XIN and XOUT pins When entering an externally derived clock enter it from XIN and leave XOUT open AVcc AVSs Analog power supply input Connect AVss to Vss and AVcc to Vcc respectively VREF Reference voltage input Connect this pin to Vss POo to P07 Data I O Do to D7 These are data Do D7 input output pins P10 to P17 Address input As to A15 These are address As A15 input pins P30 to P33 Address input A4 to A7 Input port P3 These are address A4 A7 input pins Enter low signals to these pins WE input Input port P4 This is a WE input pin Enter high signals or low signals to these pins Address input A17 Input port P5 Thissis address A17 input pin Apply VIH 5 V to this pin when VPP VP
42. Send the 4116 command code in the 1st byte of the transmission 2 Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively 3 From the 4th byte onward as write data Do D7 for the page 256 bytes specified with addresses As to A23 isinputsequentially from the smallest address first that page is automatically written When reception setup for the next 256 bytes ends the P53 BUSY signal changes from the H to the L level The result of the page program can be known by reading the status register For more information see the section on the status register As to A16 to P53 BUSY Figure DD 6 Timing for the page program ee 150 N 2 C Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode Erase All Unlocked Blocks Command This command erases the content of all blocks Execute the erase all unlocked blocks command as explained here following 1 Send the A716 command code in the 1st byte of the transmission 2 Send the verify command code D016 in the 2nd byte of the transmission With the verify com mand code the erase operation will start and continue for all blocks in the flash memory When block erasing ends the P53 BUSY signal changes from the H to the L level The result of the erase operation can be known by reading the status register CLKO HA HA TxDO D016
43. Sy M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CPU Rewrite Mode Reset command FF16 FF16 The reset command is used to stop the program command or the erase command in the middle of operation After writing command code 4016 or 2016 twice to the flash command register write command code FF 16 to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle The program command or erase command is disabled with the flash memory placed in read mode Program Erase Start Start Address first location All bytes 0016 Loop counter X 0 NO gt Write program command Write 4016 Write program data Write Program data address Duration 20 us Program all bytes 0016 Address First address Loop counter X 0 Write erase command _ erase command Write 2016 Loop counter X X 1 Write 2016 Duration 20ms Loop counter X X 1 Write program verify command Write erase verify 7 Write A016 Duration 6 us command address Hews Duration 6us Write C016 Read expect value FF16 FAIL Last address Next address Next address Last address y P Write read command N Write read command Write 0016 Write read command gt Write read command Write 0016 v Y
44. Transmit enable bit 0 Transmission disabled H Transmission disabled 1 Transmission enabled Transmission enabled eje 0 Data present in transmit buffer register 1 No data present in transmit buffer register 0 No data present in receive buffer register 1 Data present in receive buffer register Nothing is assigned When write set 0 When read the value of these bits is 0 Note UART1 cannot be used in clock synchronous serial I O UART transmit receive control register 2 b7 b6 b5 b4 b3 b2 bi b0 6 b5 b4 b3 b Symbol UCON Bit UOIRS UARTO transmit interrupt cause select bit UART1 transmit interrupt cause select bit UARTO continuous receive mode enable bit Set this bit to 0 CLKMDO CLK CLKS select bit 0 CLKMD1 CLK CLKS select bit 1 Note 2 Nothing is assigned When write set 0 Address 03B016 When reset XX0000002 Function During clock synchronous serial I O mode 0 Transmit buffer empty Tl 1 Transmission completed TXEPT 1 Set this bit to 0 Continuous receive mode disabled Continuous receive mode enable Valid when bit 5 1 a Clock output to CLK1 Clock output to CLKS1 0 Normal mode CLK output is CLKO only Transfer clock output from multiple pins function selected When read its content is indeterminate Note 1 UART1 cannot be used in clock synchronous serial I O Note 2 When using multipl
45. UARTO transmit receive control register 1 Address 03A516 UOC1 Transmit enable bit 1 Transmission enabled Receive enable bit Note 1 Reception enabled Note Set the corresponding port direction register to O input mode Writing dummy data b15 b8 b7 b0 b7 bO KKKEKKEEKEX E UARTO transmit buffer register Address 03A316 03A216 UOTB Setting dummy data Start reception Checking completion of reception b7 bo UARTO transmit receive control register 1 Address 03A516 UOC1 Receive complete flag 0 No data present in receive buffer register 1 Data present in receive buffer register Checking error b15 b8 b7 b0 b7 bo ee E UARTO receive buffer register Address 03A716 03A616 JUORB Receive data Overrun error flag 0 No overrun error 1 Overrun error found Processing after reading out reception data Figure 2 5 13 Set up procedure of reception in clock synchronous serial I O mode 2 253 N amp amp Mitsubishi microcomputers R Sty M30201 Group 4 SINGLE CHIP 16 BIT CMOS MICROCOMPUTER gt Clock Synchronous Serial I O 2 5 5 Precautions for Serial I O in clock synchronous serial I O Transmission 1 With an external clock selected perform the following set up procedure with the CLKO pin input level H if the CLK polarity select bit 0 or with the CLKO pin input level L if th
46. dsp 8 FB IMM8 dsp 8 FB IMM8 IMM8 dsp 8 FB IMM8 abel 1111 F SUB B S OR B S DEC B NOT B S STZ STZX JSRS UND IMM8 abs16 IMM8 abs16 abs16 abs16 IMM8 abs16 IMM8 IMM8 abs16 IMM8 MITSUBISHI Single Chip Microcomputer User s Manual M30201 Group Feb First Edition 1999 REV A Editioned by Committee of editing of Mitsubishi Semiconductor USER S MANUAL Published by Mitsubishi Electric Corp Kitaitami Works This book or parts thereof may not be reproduced in any form without permission of Mitsubishi Electric Corporation 1999 MITSUBISHI ELECTRIC CORPORATION
47. input to the ANo AN5o pin 2 After the A D conversion on voltage input to the ANo AN50 pin is completed the content of the succes sive comparison register conversion result is transmitted to A D register 0 3 Every time the A D converter carries out A D conversion on a selected analog input pin the A D converter carries out A D conversion on only one unselected pin and then the A D converter carries out A D conver sion from the ANO pin again See Figure 2 7 13 The conversion result is transmitted to A D register i every time conversion on a pin is completed The A D conversion interrupt request bit does not go to 1 4 The A D converter continues operating until software goes the A D conversion start flag to O When AN0 is selected When ANo AN1 are selected When ANo to AN2 are selected When ANo to AN3 are selected Time Converted analog input pin Converted analog input pin Converted analog input pin Converted analog input pin Figure 2 7 13 ANi pin s sweep sequence in repeat sweep mode 2 Conversion result is 1 Start ANo AN5o pin transfered to A D 3 Consecutive conversion conversion 8 bit resolution 28 AD cycles conversion register gt l 4 A D 8 bit resolution i 8 bit resolution 8 bit resolution 1 conversion 28 taD cycles 28 taD cycles 28 aD cycles is complete 10 bit resolution 10 bit resolution 10 bit resolution 10 bit resolution 33 a
48. n 0016 to FF16 Figure 1 47 Example of how an 8 bit pulse width modulator operates 59 XX Ss eS Mitsubishi microcomputers s O M30201 Group e SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B Timer B Figure 1 48 shows the block diagram of timer B Figures 1 49 and 1 50 show the timer B related registers Use the timer Bi mode register i 0 1 bits 0 and 1 to choose the desired mode Timer B has three operation modes listed as follows e Timer mode The timer counts an internal count source e Event counter mode The timer counts pulses from an external source or a timer overflow e Pulse period pulse width measuring mode The timer measures an external signal s pulse period or pulse width Data bus high order TZ Data bus low order iz Clock source selection i eee fi o e Timer fg o Pulse period pulse width measurement Reload register 16 f32 _o fc32____o Event counter Polarity switching and edge pulse Can be selected in only event counter mode TBj overflow o j 1 when i 0 j 0 wheni 1 Figure 1 48 Block diagram of timer B Timer Bi mode register Symbol Address When reset 296 D5 64 DO bR B1 Bo TBIMR i 0 1 039B16 039C16 00XX00002 Bit symbol TMODO Operation mode select bit i Timermoda Event counter mode TMOD1 Pulse period pulse width measurement mode Inhibited Function varies with each operation mode MR1 TCK1 Function varies wit
49. 03C216 038316 Trigger select register TRGSR 03C316 038416 Up down flag UDF 03C416 038516 030516 038616 03C616 038716 imer AO TAO mere 038816 03C816 03891 TimMer XO TXO 03C916 038A16 _ 03CA16 038B16 Timer X1 TX1 03CB16 A D register 1 AD1 A D register 2 AD2 A D register 3 AD3 A D register 4 AD4 A D register 5 AD5 038C16 _ 03CC16 Timer X2 TX2 038D16 03CD16 A D register 6 AD6 038E16 Clock divided counter CDC 03CE16 038F16 oacris A D register 7 AD7 039016 j 03D016 039116 imer BO TBO 03D116 039216 03D216 039316 Timer Gate 03D316 039416 03D416 A D control register 2 ADCON2 039516 03D516 039616 Timer AO mode register TAOMR 03D616 A D control register 0 ADCONO 039716 Timer XO mode register TXOMR 03D716 A D control register 1 ADCON1 039816 Timer X1 mode register TX1MR 03D816 039916 Timer X2 mode register TX2MR 03D916 039A16 03DA16 039B16 Timer BO mode register TBOMR 03DB16 039C16 Timer B1 mode register TB1MR 03DC16 039D16 03DD16 039E16 03DE16 039F16 03DF16 03A016 UARTO transmit receive mode register UOMR 03E016 Port PO PO 03A116 UARTO bit rate generator UOBRG 03E116 Port P1 P1 03A216 03E216 Port PO direction register PDO ree UARTO transmit buffer register UOTB 03E316 Port P1 direction register PD1 03A416 UARTO transmit receive control register 0 UOCO 0
50. 1 MSB first Note UART1 cannot be used in clock synchronous serial 1 0 Must always be 0 Figure 2 5 3 Serial l O related registers 2 240 x xe sf Mitsubishi microcomputers ve M30201 Group Se SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O UARTI transmit receive control register 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset UiC1 i 0 1 03A516 03AD16 0216 Function Bit Function Bit name During clock synchronous Sme ia e serial VO mode ae A sais i enable bit o Transmission disabled T Transmission disabled Transmission enabled Transmission enabled fiat ii buffer 0 Data present in 0 Data present in empty flag transmit buffer register transmit buffer register 1 No data present in 1 No data present in transmit buffer register transmit buffer register Receive complete flag 0 No data present in 0 No data present in receive buffer register receive buffer register Data present in 1 Data present in receive buffer register receive buffer register Nothing is assigned When write set 0 When read the value of these bits is 0 Note UART1 cannot be used in clock synchronous serial I O UART transmit receive control register 2 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset UCON 03B016 XX0000002 Function i Bit F Function RWI Bit During clock synchronous RWI symbol name serial I O mode During UART mode UOIRS UARTO trans
51. 1 84 A D converter related registers 2 93 x Q gf Mitsubishi microcomputers ve M30201 Group S SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 1 One shot mode In one shot mode the pin selected using the analog input pin select bit is used for one shot A D conver sion See Table 1 31 Figure 1 85 shows the A D control register in one shot mode Table 1 31 One shot mode specifications Item Specification Function The pin selected by the analog input pin select bit is used for one A D conversion Start condition Writing 1 to A D conversion start flag Stop condition e End of A D conversion A D conversion start flag changes to 0 e Writing 0 to A D conversion start flag Interrupt request generation timing End of A D conversion Input pin One of ANo to AN7 as selected Note Reading of result of A D converter Read A D register corresponding to selected pin Note AN50 to AN54 can be used in the same way as for ANo to AN4 A D control register 0 Note 1 b7 b6 b5 b4 b3 b2 bl bO Symbol Address When reset J lololo Abcone 03D616 00000XXX2 Bit symbol Bit name Function i ANo is selected AN1 is selected AN2 is selected AN3 is selected AN4 is selected AN5 is selected AN6 is selected AN7 is selected CHO Analog input pin select bit O 0 0 00 A D operation mode MDO select bit 0 One shot mode He A D conversion disab
52. 10 bit mode AN6 is selected AN7 is selected 1 0 Ti 00 0 1 e 10 Ti Frequency select bit 1 0 fAD 2 or fAD 4 is selected 1 fAD is selected One shot mode is selected Note 1 Must be fixed to 0 __________ Vref connect bit L AD conversion start flag 1 Vref connected 0 A D conversion disabled Must be fixed to 0 Frequency select bit 0 0 faD 4 is selected 1 fap 2 is selected A D input group select bit 0 Port P6 group is selected 1 Port P5 group is selected Note 1 Rewrite to analog input pin select bit after changing A D operation mode Note 2 Set the corresponding port direction register to 0 input mode When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins ANso to ANs4 Setting A D conversion start flag 2 7 po A D control register 0 Address 03D616 ADCONO A D conversion start flag 1 A D conversion started Start A D conversion Stop A D conversion i i A D registerO0 Address 03C116 03C016 ADO Reading ea vs A D register 1 Address 03C316 03C216 AD1 b0 b7 A D register 2 Address 03C516 03C416 AD2 A D register 3 Address 03C716 03C616 AD3 A D register 4 Address 03C916 03C816 AD4 A D register 5 Address 03CB16 03CA16 AD5 A D register 6 Address 03CD16 03CC16 AD6 A D register 7 Address 03CF16 03CE16 AD7 Eight low order bits of A D
53. 16 BIT CMOS MICROCOMPUTER A D Converter A D Converter The A D converter consists of one 10 bit successive approximation A D converter circuit with a capacitive coupling amplifier Pins P60 to P67 and P50 to P54 also function as the analog signal input pins The direction registers of these pins for A D conversion must therefore be set to input The Vref connect bit bit 5 at address 03D716 can be used to isolate the resistance ladder of the A D converter from the reference voltage input pin VREF when the A D converter is not used Doing so stops any current flowing into the resistance ladder from VREF reducing the power dissipation When using the A D converter start A D conversion only after setting bit 5 of 03D716 to connect VREF The result of A D conversion is stored in the A D registers of the selected pins When set to 10 bit precision the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses When set to 8 bit precision the low 8 bits are stored in the even addresses Table 1 30 shows the performance of the A D converter Figure 1 82 shows the block diagram of the A D converter and Figures 1 83 and 1 84 show the A D converter related registers Table 1 30 Performance of A D converter Item Performance Method of A D conversion Successive approximation capacitive coupling amplifier Analog input voltage Note 1 OV to AVcc Vcc Operating clock oAD Note 2 Vcc 5V __ fAD divide by 2 of fAD d
54. 2 4 5 shows the set up procedure Table 2 4 1 Choosed functions Count source Internal count source f1 fs f32 fc32 Pulse output function No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TXiINOUT pin is at L level Performs count only for the period in which the TXiINOUT pin is at H level Operation 1 Setting the count start flag to 1 causes the counter to perform a down count on the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer Xi interrupt request bit goes to 1 3 Setting the count start flag to O causes the counter to hold its value and to stop n reload register content 1 Start count 2 Underflow m i Counter content hex Set to 1 by software L software i Cleared to 0 by l N Start count again Z gt Time Set to 1 by software ia Count start flag o Cleared to 0 when interrupt request is accepted or cleared by software Timer Xi interrupt request bit Figure 2 4 4 Operation timing of timer mode T ON 212 x N O aS Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Selecting timer mode and functions Timer Xi mode register i 0 to 2 Address 039716 to 03991
55. 3 Can be selected when bit 6 of the system clock control register 0 address 000616 is 0 If 1 division mode is fixed at 8 Note 4 If this bit is set to 1 XOUT turns H and the built in feedback resistor is cut off XCIN and XCOUT turn high impedance state Figure 2 11 4 Power control related registers 314 x N amp gf Mitsubishi microcomputers ve M30201 Group d SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Power Control 2 11 2 Stop Mode Set Up Settings and operation for entering stop mode are described here Operation 1 Enables the interrupt used for returning from stop mode 2 Sets the interrupt enable flag I flag to 1 3 Clearing the protection and setting every clock stop bit to 1 stops oscillation and causes the processor to go into stop mode 1 Setting interrupt to cancel stop mode Interrupt control register KUPIC Address 004D16 ADIC Address 004E16 Address 005116 005316 Address 005216 005416 Address 005516 Address 005616 to 005816 Address 005A16 005B16 P 2 LETT Sooo aS 24 ee n gt fed f b7 INTiIC i 0 1 bO Address 005D16 005E16 hir Interrupt priority level select bit Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority IPL of the routine where the WAIT instruction is executed Interrupt priority level s
56. 3 4 Characteristics of ICC f XIN Vcc 5V 382 xX Cy O RX Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics Flash memory version 5 4 Standard Characteristics of Pull Up Resistor Figure 5 4 1 shows an example of the standard characteristics of the pull up resistor VI V Note Data described here are characteristic examples The data values are not guaranteed Figure 5 4 1 Example of the standard characteristics of the pull up resistor 383 x Cy Q s Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix 1 Appendix 1 Check Sheet The following check sheet was created based on items which had been the source of problems in the past We recommend you refer to the check sheet when troubleshooting Checks regarding register initial settings L Has the initial setting been made in the interrupt stack pointer ISP at the top of the program L Has the initial setting been made in the user stack pointer USP Only if using the USP LI Does the USP overlap the ISP area Only if using the USP O Is interrupt enabled after setting the ISP and USP L Is the top address of the variable interrupt vector table set in the interrupt table register INTB O Is interrupt enabled after setting the INTB L Has the initial setting been made in the frame base register FB Only if using the FB LC Has the initial s
57. 32 b7 b0 Clock prescaler reset flag Address 038116 LPL CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O NS Setting count start flag b7 bO Count start flag Address 038016 TABSR Timer XO count start flag Timer X1 count start flag Timer X2 count start flag Start count Figure 2 4 7 Set up procedure of timer mode gate function selected 215 amp lt Mitsubishi microcomputers R Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 4 Operation of Timer X timer mode pulse output function selected In timer mode choose functions from those listed in Table 2 4 3 Operations of the circled items are described below Figure 2 4 8 shows the operation timing and Figure 2 4 9 shows the set up procedure Table 2 4 3 Choosed functions Count source Internal count source f1 fs f32 fc32 Pulse output function No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TXiINOUT pin is at L level Performs count only for the period in which the TXiinourT pin is at H level Operation 1 Setting the count start flag to 1 causes the counter to perform a down count on the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer
58. 326 3 2 Variable Period Variable Duty PWM Output 0 cecceeceeeeeeenee centres eeeaeeseeeeeeeeaeeseeeeeeseaeeeseaeeeeea 330 3 3 Delayed One Shot Output 00 cceececceceeeeeececeeee cece eae eeeeeeecaaaesdeaaeecaaeeeeaaeeseaeeseaaaeseeneeeseaaeseeeeeeee 334 3 4 Buzzer Output siiani aaa a aa a eani o tide queda ne Sd ala es 338 3 5 Solution for External Interrupt Pins Shortage eccccececeeeeeeeee cece eeeeeeeseeeeeeeeeaeeeeeeeeesiaeeeeeneee 340 3 6 Controlling Power Using Stop Mode ccececceceeeeeeseeeeeeeeeeeeaeeeeeeeeeeeaaeeseeeeeesaeeseeeeeesaeeeeeeeeeed 342 3 7 Controling Power Using Wait Mode cccccecceeeceeeeeeeeeneeeeeaeeeeeneeeeeaaeeseeeeeesaeeeseeeeesnaeeeseaaeeeed 346 Chapter 4 Interrupt 4 1 Overview of Interrupt 2 0 2 2 cece eeceeee cece eeeeeeeeeceeeeeeeaeeeaeeeceaaeseaeeeeceaeeseeaeeeecaeeeseaaeseeeeeestaeeeeeeeeee 352 4 1 1 Type of Interrupts oon aa anen a ia eNi eaS AENEA EEA A ERANA EAEE RA EA 352 4 1 2 Software Interrupts 22 20 eeeccceeceeeeeeeceeeeceeeeee cease eeeaaeeeaeeeseaaeeegeeeecaaeesseeeeseaeesseaeeeseaeeesenaeeee 353 4 1 3 Hardware Interrupts enraiar isai ivairias taan iNANO E EE E A 354 4 1 4 Interrupts and Interrupt Vector Tables 20 0 0 eeeeneeeeeeeenee eee eeeae eee eeeeaaeeeeeetaaeeeeeeeaeeeeeneaa 355 4 2 Interrupt Control iiien cae tle aiiva leet hate ine ee tetera 357 4 2 1 Interrupt Enable Flago EE E AET a A A a 359 4 2 2 Interrupt Request Bit oieri eeni na
59. 83DATA 1SP m 1ST 8DATA 2SP m 1ST 8DATA 1PAR 1SP 1ST 8DATA 1PAR 2SP Transfer data length 9 bits _ 1ST 9DATA __ 1SP m 1ST 9DATA _ 2SP m 1ST 9DATA 1PAR 1SP 1ST 9DATA 1PAR 2SP ST Start bit Character bit Transfer data Parity bit Stop bit Figure 2 6 1 Transmission reception format Table 2 6 1 Transmission data names and functions ST start bit A 1 bit L signal to be added immediately before character bits This bit signals the start of data transmission DATA character bits Transmission data set in the UARTIi transmit buffer register PAR parity bit A signal to be added immediately after character bits so as to increase data reliability The level of this signal so varies that the total number of 1 s in character bits and this bit always becomes even or odd depending on which parity is chosen even or odd SP stop bit Either 1 bit or 2 bit H signal to be added immediately after character bits after the parity bit if parity is checked This they signals the end of data transmission 256 Ss amp Mitsubishi microcomputers RA ke SX M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART 2 Transfer rate The divide by 16 frequency resulting from division in the bit rate generator BRG becomes the trans fer rate The count source for the
60. AN54 can be used in the same way as for ANo to AN4 A D control register 0 Note b7 b6 b5 b4 b3 b2 bl b0 Symbol ola p Apem Address 03D616 When reset 00000XXX2 Bit name Analog input pin select bit A D operation mode MD1 select bit 0 Set this bit to 0 ADST A D conversion start flag Function Invalid in single sweep mode b4 b3 10 Single sweep mode 0 A D conversion disabled 1 A D conversion started CKSO Frequency select bit 0 0 faD 4 is selected 1 faD 2 is selected Note If the A D control register is rewritten during A D conversion the conversion result is indeterminate A D control register 1 Note 1 b7 b6 b5 b4 b3 b2 bi b0 Address 03D716 When reset Symbol ADCON1 0016 A D sweep pin select bit When single sweep and repeat sweep mode 0 are selected b1 b0 0 0 ANo AN1 2 pins 0 1 ANo to AN3 4 pins 10 ANo to AN5 6 pins 1 1 ANo to AN7 8 pins Set this bit to 0 in this mode ewer Bit symbol Note 2 3 A D operation mode select bit 1 BITS 8 10 bit mode select bit Frequency select bit 1 He 8 bit mode 10 bit mode 0 fAD 2 or fAD 4 is selected 1 faD is selected Vref connect bit 1 Vref connected Set this bit to 0 A D input group select bit Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 ANso to AN54 can be used
61. BRGi count source f1 fs 32 fc e One stop bit fEXT frequency of BRGi count source external clock e Transmit interrupt cause select bit 1 n value set to BRGi Figure 2 6 6 Operation timing of transmission in UART mode 265 Q e Mitsubishi microcomputers Sy M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Setting UARTIi transmit receive mode register i 0 1 b0 1lol1 UARTO transmit receive mode register UOMR Address 03A016 UART1 transmit receive mode register U1MR Address 03A816 KE Serial I O mode select bit b2 b1 b0 1 0 1 Transfer data 8 bits long Internal external clock select bit 0 Internal clock Stop bit length select bit 0 One stop bit Odd even parity select bit Valid when bit 6 1 0 Odd parity Parity enable bit 1 Parity enabled Sleep select bit 0 Invalid Setting UARTI transmit receive control register 0 i 0 1 bo UARTO transmit receive control register 0 UOCO Address 03A416 UART1 transmit receive control register 0 U1C0 Address 03AC 16 BRG count source select bit b1 b0 00 ft is selected 01 fs is selected 1 0 f32 is selected 1 1 fc is selected Must be 0 in UART mode Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmissi
62. CHIP 16 BIT CMOS MICROCOMPUTER CPU Rewrite Mode Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode 1 Operation speed During erase program mode set BCLK to one of the following frequencies by changing the divide ratio 5 MHz or less when wait bit bit 7 at address 000516 0 without internal access wait state 10 MHz or less when wait bit bit 7 at address 000516 1 with internal access wait state 2 Instructions inhibited against use The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory UND instruction INTO instruction JMPS instruction JSRS instruction and BRK instruction 3 Interrupts inhibited against use No interrupts can be used that look up the fixed vector table in the flash memory area Maskable interrupts may be used by setting the interrupt vector table in a location outside the flash memory area 130 ES S L ys RS eS CPU Rewrite Mode Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Software Commands Table BB 1 lists the software commands available with the M30201 flash memory version When CPU rewrite mode is enabled write software commands to the flash command register to specify the operation to erase or program The content of each software command is explained below Table BB 1 List of Software Com
63. CMOS MICROCOMPUTER Power Saving Power Saving There are three power save modes 1 Normal operating mode e High speed mode In this mode one main clock cycle forms BCLK The CPU operates on the BCLK The peripheral functions operate on the clocks specified for each respective function Medium speed mode In this mode the main clock is divided into 2 4 8 or 16 to form BCLK The CPU operates on the BCLK The peripheral functions operated on the clocks specified for each respective function Low speed mode In this mode fc forms BCLK The CPU operates on the fc clock fc is the clock supplied by the subclock The peripheral functions operate on the clocks specified for each respective function Low power dissipation mode This mode is selected when the main clock is stopped from low speed mode The CPU operates on the fc clock fc is the clock supplied by the subclock Only the peripheral functions for which the subclock was selected as the count source continue to run 2 Wait mode CPU operation is halted in this mode The oscillator continues to run 3 Stop mode All oscillators stop in this mode The CPU and internal peripheral functions all stop Of all 3 power saving modes power savings are greatest in this mode Figure 1 20 shows the transition between each of the three modes 1 2 and 3 26 S LK Ss X O Power Saving Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER
64. Changing the Interrupt Control Register lt Program examples gt The program examples are described as follow Example 1 INT_SWITCH1 FCLR AND B 00h 0055h NOP NOP FSET Example 2 INT_SWITCH2 FCLR AND B 00h 0055h MOV W MEM RO FSET Example 3 INT_SWITCHS3 PUSHC FLG FCLR AND B 00h 0055h POPC FLG Disable interrupts Clear TAOIC int priority level and int request bit Four NOP instructions are required when using HOLD function Enable interrupts Disable interrupts Clear TAOIC int priority level and int request bit Dummy read Enable interrupts Push Flag register onto stack Disable interrupts Clear TAOIC int priority level and int request bit Enable interrupts The reason why two NOP instructions or dummy read are inserted before FSET in Examples 1 and 2 is to prevent the interrupt enable flag from being set before the interrupt control register is rewritten due to effects of the instruction queue If changing the interrupt control register using an instruction other than the instructions listed hear and tions given below to change the register Following instructions AND OR BCLR or BSET 37 if an interrupt occurs associated with this register during execution of the instruction there can be instances in which the interrupt request bit is not set To avoid this problem use one of the instruc X Se Mitsubishi microcomp
65. Count source Internal count source fi fs f32 fc32 Pulse output function No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TAOIN pin is at L level Performs count only for the period in which the TAOIN pin is at H level Operation 1 When the count start flag is set to 1 and the TAOIN pin inputs at H level the counter performs a down count on the count source 2 When the TAOIN pin inputs at L level the counter holds its value and stops 3 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer AO interrupt request bit goes to 1 4 Setting the count start flag to 0 causes the counter to hold its value and to stop Note e Make the pulse width of the signal input to the TAOIN pin not less than two cycles of the count source n reload register content 1 Start count 3 Underflow 2 Stop count 7 4 Stop count Counter content hex gt 9 Start count again 000016 7 i i Cleared to 0 by Time Set to 1 by software i y software Set to 1 by software Count start flag TAON pin H input signal nj Cleared to 0 when interrupt request is accepted or cleared by software Timer AO interrupt 1 i request bit g Figure 2 2 8 Operation timing of timer mode gate f
66. EEE a AA EE EEA FREE EEREN 359 4 2 3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level IPL 0 360 4 2 4 Rewrite the interrupt Control register 2 eeceeeeeeeeeneee teeter eee eeetaeee eee taaeeeeeetaeeeeeeeaeeeeeeeaa 361 4 3 INTErrUPtSOQUueNCE a t r meae aa a ead Ae ave ue eee 362 4 3 1 Interrupt RESPONSE TIME anioros E AA ESE R 362 4 3 2 Variation of IPL when Interrupt Request is Accepted sssssssssesssssrrssssrrrssrrirrnsrrnnsssrrnnnns 363 e Re tetehi Mmt e EE a A EA E E E A 364 4 4 Returning from an Interrupt Routine 20 cece eect eee ee eee ee eee eae eee teeta ae ee eee taaaeeeeeeeaeeeeeneaaeeeeeeena 366 4 5 Interrupt Prony aenn ted oanhedens cadeedd e eaade dh aug hnoedh SAREES 366 4 6 Multiple Interrupts sic ccfbccnoceeiehi cece cave sadened Yeanevteebeded AEAEE REEE Ee EREEREER EEEIEE KEEA ERER 368 4 7 Precautions for IMterrupts cccceeccceceeeeeeceeeeteseeceeeeeseeeeeeeseaaeaeaeesaaeaaeeeessaceeeeseseaeeeeseeeeeeentnaes 370 Chapter 5 Standard Characteristics 5 1 Standard DC Characteristics snini riiai an na an aaa aiiai aeiiaaie nda ida 374 5 1 1 Standard Ports Characteristics eeeeeeeeeeeee eesse eeen n tentent tttinttnisstissstnssstunstnnstnnnnnntnn nnt 374 5 1 2 Characteristics of ICC f XIN ccceeeseeececeeeeeeeeeeeeeeeeceaaeseeeeeeseaeeeseaeeeseaeeeeeaaeeseeeeeesaeeseeeeeess 377 5 2 Standard Characteristics of Pull Up Resistor ccceceeeeeeeeeeeeee
67. Error sum flag Invalid 0 No error OX Note 1 Error found Note Bits 15 through 12 are set to 0 when the serial I O mode select bit bits 2 to 0 at addresses 03A016 and 03A816 are set to 0002 or the receive enable bit is set to 0 Bit 15 is set to 0 when bits 14 to 12 all are set to O Bits 14 and 13 are also set to 0 when the lower byte of the UARTIi receive buffer register addresses 03A616 and 0 3AE16 is read out UARTI bit rate generator b7 bo Address When reset 03A116 Indeterminate 03A916 Indeterminate Values that can be set Assuming that set value n BRGi divides the 0016 to FFie count source by n 1 Figure 1 71 Serial l O related registers 1 78 amp A Q lt se Ss Serial I O UARTi transmit receive mode register Address 03A016 03A816 When reset 0016 b7 b6 b5 b4 b3 b2 bi b0 Symbol UiMR i 0 1 Function During clock synchronous serial I O mode Must be fixed to 001 Bit name SMDO Serial I O mode select bit Serial I O invalid Inhibited Inhibited Inhibited SMD1 SMD2 CKDIR STPS Internal external clock select bit Note 2 Stop bit length select bit Invalid Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Function During UART mode mp 32420 0056 3200005 3 Transfer data 7 bits long Transfer data 8 bits long Transfer data 9 bits long Serial I O
68. Functions Usage xX Se es Mitsubishi microcomputers Sy O M30201 Group e SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Protect 2 1 Protect 2 1 1 Overview Protect is a function that causes a value held in a register to be unchanged even when a program runs away The following is an overview of the protect function 1 Registers affected by the protect function The registers affected by the protect function are a System clock control registers 0 1 addresses 000616 and 000716 b Processor mode registers 0 1 addresses 000416 and 000516 c Port P4 direction register address 03EA16 The values in registers 1 through 3 cannot be changed in write protect state To change values in the registers put the individual registers in write enabled state 2 Protect register Figure 2 1 1 shows protect register Protect register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PRCR 000A16 XXXXX0002 Btsynbel e O O o TR Enables writing to system clock control registers 0 and 1 addresses H biti Ds 000616 and 000716 eee Enables writing to processor mode 0 Write inhibited registers 0 and 1 addresses 000416 and 000516 PRC2 Enables writing to port P4 direction 0 Write inhibited register address 03EA16 Note 1 Write enabled Nothing is assigned These bits can neither be set nor reset When read their contents are indeterminate 1 Write enabled Note Writing a value to an address after
69. If an overrun error occurs the UARTO receive buffer will have the next data written in Note also that the UARTO receive interrupt request bit is not set to 1 81 Clock synchronous serial I O mode UARTO transmit receive mode registers AAE Symbol Address When reset o fofols UomR O3AO16 0016 Serial O mode select bit 2 21 b0 0 0 1 Clock synchronous serial I O mode CKDIR Internal external clock 0 Internal clock select bit 1 External clock STPS Invalid in clock synchronous serial I O mode PRYE SLEP 0 Must always be 0 in clock synchronous serial I O mode Figure 1 74 UARTO transmit receive mode register in clock synchronous serial I O mode Table 1 27 lists the functions of the input output pins during clock synchronous serial I O mode Note that for a period from when the UARTO operation mode is selected to when transfer starts the TxDO pin outputs a H If the N channel open drain is selected this pin is in floating state Table 1 27 Input output pin functions in clock synchronous serial I O mode Serial data output Port P50 direction register bit O at address 03EB16 1 Outputs dummy data when performing reception only Serial data input Port P51 direction register bit 1 at address 03EB16 0 Can be used as an input port when performing transmission only Transfer clock output Internal external clock select bit bit 3 at address 03A016 0 Intern
70. If the A D control register is rewritten during A D conversion the conversion result is indeterminate A D control register 1 Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset o ADCON1 03D716 0016 Bit symbol Bit name Function A D sweep pin select bit When single sweep and repeat sweep SCANO mode 1 are selected b1 b0 00 ANo 1 pins 0 1 ANo AN1 2 pins 1 0 ANo to AN2 3 pins 1 1 ANo to AN8 4 pins Note 2 3 A D operation mode Set 1 in this mode select bit 1 8 10 bit mode select bit 8 bit mode 10 bit mode Frequency select bit 1 fap 2 or fAD 4 is selected faD is selected Vref connect bit Vref connected Set this bit to 0 Di a 0 Port P6 group is selected ADGSELO A D input group select bit 1 Port P5 group is selected Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 ANso to AN54 can be used in the same way as for ANo to AN4 Note 3 If port P5 group is selected the contents of A D registers 5 to 7 are indeterminate Figure 1 89 A D conversion register in repeat sweep mode 1 98 x xe sf Mitsubishi microcomputers ve M30201 Group D SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter e Sample and hold Sample and hold is selected by setting bit 0 of the A D control register 2 address 03D416 to 1 When sample and hold is selected the r
71. Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport contrary to the export control laws and regulations of JAPAN and or the country of destination is prohibited Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein Preface This user s manual describes the function and features of the Mitsubishi M30201 CMOS 16 bit microcomputer The software features are ex plained to help designers take full advantage of the M16C functions For details about the software please refer to the M16C 60 M16C 20 series software manual and for the development support tools please refer to the related instruction manual Chapter 1 Hardware iL Chapter 2 Peripheral Functions Usage 20 SSS Chapter 3 Examples of Peripheral Functions Applications i lL ELE Chapter 4 Interrupt Cu Chapter 5 Standard Characteristics How to Use This Manual This user s manual is written for the M30201 group The reader of this manual is expected to have the basic knowledge of electric and logic circuits and microcomputers This manual is for the use of the models below e M30201M2 XXXSP FP e M30201M2T XXXSP FP e M30201M4 XXXSP FP e M30201M4T XXXSP FP e M30201F6SP FP e M30201F6TSP FP These products have similar features except for the memories which differ from
72. Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figure 5 1 1 IOH VOH standard characteristics of ports PO to P7 Vcc 5V voL V Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figure 5 1 2 loL VoL standard characteristics of ports PO to P7 Vcc 5V voL V Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figure 5 1 3 lo VOL standard characteristics of port P1 Vcc 5V HIGH POWER E 375 xX N O S Mitsubishi microcomputers S M30201 Group Ra SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figure 5 1 4 10H VOH standard characteristics of ports PO to P7 Vcc 3V voL V Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figure 5 1 5 loL VoL standard characteristics of ports PO to P7 Vcc 3V 0 1 2 3 voL V Note Data described here are characteristic examples The dat
73. Note 2 The bit can be 0 or 1 Note 3 Set the corresponding port direction register to 0 input mode Figure 1 41 Timer AO mode register in timer mode 53 N amp Mitsubishi microcomputers xe QR Sy O M30201 Group a SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 Event counter mode In this mode the timer counts an external signal or an internal timer s overflow Timer AO can count a single phase and a two phase external signal Table 1 14 lists timer specifications when counting a single phase external signal Figure 1 42 shows the timer AO mode register in event counter mode Table 1 15 lists timer specifications when counting a two phase external signal Figure 1 43 shows the timer AO mode register in event counter mode Table 1 14 Timer specifications in event counter mode when not processing two phase pulse signal Item Specification Count source External signals input to TAOIN pin effective edge can be selected by software TB1 overflow TXO overflow TX2 overflow Count operation Up count or down count can be selected by external signal or software When the timer overflows or underflows it reloads the reload register con tents before continuing counting Note Divide ratio 1 FFFF16 n 1 for up count 1 n 1 for down count n Set value Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing The
74. P53 BUSY Figure DD 15 Timing for boot area output 153 amp CA r E E cut Mitsubishi microco puters SE St M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode ID Check This command checks the ID code Execute the boot ID check command as explained here following 1 Send the F516 command code in the 1st byte of the transmission 2 Send addresses Ao to A7 As to A15 and A16 to A23 of the 1st byte of the ID code in the 2nd 3rd and 4th bytes of the transmission respectively 3 Send the number of data sets of the ID code in the 5th byte 4 The ID code is sent in the 6th byte onward starting with the 1st byte of the code rs ed P53 BUSY Figure DD 16 Timing for the ID check ID Code When the flash memory is not blank the ID code sent from the serial programmer and the ID code written in the flash memory are compared to see if they match If the codes do not match the com mand sent from the serial programmer is not accepted An ID code contains 8 bits of data Area is from the 1st byte addresses OFFFDF16 OFFFE316 OFFFEBi6 OFFFEFi6 OFFFF316 and OFFFF 716 Write a program into the flash memory which already has the ID code set for these addresses OFFFE316 to OFFFE016 ID2 Overflow vector OFFFE716 to OFFFE416 BRK instruction vector Address A noA a OFFFDF16 to OFFFDC16 ID1 Undefined instruction vector OFFFEB16 to OFFFE816 ID3 A
75. Parameter TXiINOUT input cycle time Standard Min Max TXiINOUT input HIGH pulse width Table 1 72 tc TX TXiINOUT input LOW pulse width Timer X input pulse width measurement mode Parameter TXiINOUT input cycle time Standard Min Max tw TXH TXiINOUT input HIGH pulse width tw TXL Table 1 73 tc CK TXiiNouT input LOW pulse width Serial I O Parameter CLKO input cycle time Standard Min Max tw CKH CLKO input HIGH pulse width tw CKL CLKO input LOW pulse width td C Q TxDi output delay time th C Q TxDi hold time tsu D C RxDi input setup time th C D Table 1 74 Symbol tw INH RxDi input hold time External interrupt INTi inputs ae Parameter INT input HIGH pulse width tw INL INTi input LOW pulse width 124 F X O lt Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 3V TAOIN input TAOOUT input TAOOUT input Up down input x During event counter mode TAOIN input When count on falling th Tin UP tsu UP Tin edge is selected TAOIN input When count on rising edge is selected TBIIN input TXiINOUT input TxDi RxDi INTI input 125 xX Ss Q s Mitsubishi microc
76. Protect control address 143 PN S S J P we Appendix Standard Serial I O Mode Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Pin functions Flash memory standard serial I O mode Pin Name O Description Vcc Vss Power input Apply 5V 10 to Vcc pin and 0 V to Vss pin CNVss CNVss Apply 12V 5 to this pin RESET Reset input l Reset input pin While reset is L level a 20 cycle or longer clock must be input to XIN pin XIN Clock input Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins To input an externally generated clock input it to XIN pin XOUT Clock output o and open XourT pin AVcc AVss Analog power supply input Connect AVss to Vss and AVcc to Vcc respectively VREF Reference voltage input Enter the reference voltage for AD from this pin POo to P07 Input port PO Input H or L level signal or open P10 to P17 Input port P1 Input H or L level signal or open P30 to P35 Input port P3 Input H or L level signal or open P40 to P45 Input port P4 Input H or Level signal or open P54 Input port P5 Input H or L level signal or open Po TxD output O Seria data outbut pin gt P51 RxD input Serial data input pin Pe SCLK input A 4 fy Serialclockinputpin Pos i BUSY output A hy O BUSY signal output pin P60 to P67 Input port P6 Input H or L level signal or open P70 to P71 In
77. Push Flag register onto stack FCLR Disable interrupts AND B 00h 0055h Clear TAOIC int priority level and int request bit POPC FLG Enable interrupts The reason why two NOP instructions four when using the HOLD function or dummy read are inserted before FSET in Examples 1 and 2 is to prevent the interrupt enable flag from being set before the interrupt control register is rewritten due to effects of the instruction queue e When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener ated This will depend on the instruction If this creates problems use the below instructions to change the register Instructions AND OR BCLR BSET 371 Chapter 5 Standard Characteristics N O S Mitsubishi microcomputers S M30201 Group x SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics 5 1 Standard DC Characteristics The standard characteristics given in this section are examples of M30201M4 XXXFP The contents of these examples cannot be guaranteed For standardized values see Electric characteristics 5 1 1 Standard Ports Characteristics Figures 5 1 1 through 5 1 6 show the standard ports characteristics 374 O sf Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics Von V
78. ROM and boot ROM areas shown in Figure CC 1 can be rewritten In the boot ROM area an erase block operation is applied to only one 4 K byte block The boot ROM area has had a standard serial I O mode control program stored in it when shipped from the Mitsubishi factory Therefore using the device in standard serial input output mode the user does not need to write to the boot ROM area Functional Outline Parallel 1 O Mode In parallel I O mode bus operation modes Read Output Disable Standby and Write are selected by the status of the CE OE WE VAFY and CNVSs input pins The contents of erase program and other operations are selected by writing a software command The data in memory can only be read out by a read after software command input Program and erase operations are controlled using software commands Table CC 3 Relationship between control signals and bus operation modes Pin name Mode CE QE WE VRFY VPP Do to D7 Read VIL VIL VIH VIL VpeH Data output Sd Output disabled Vil VIH VIH VIL VPPH Hi Z Stand by VIH X x VIL VpPpH Hi Z Read VIL VIL VIH VIH VPPH Data output ae Output disabled Vie VIH VIH VIH VppH Hi Z Stand by ViH X X VIH VppH Hi Z Write VIL VIH VIL VIH VPPH Data input Note Xan be VIL or VIH 138 N j Mitsubishi microcomputers L L NO M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Parallel I O Mode The
79. SF M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 4 Operation of Timer A timer mode pulse output function selected In timer mode choose functions from those listed in Table 2 2 3 Operations of the circled items are described below Figure 2 2 10 shows the operation timing and Figure 2 2 11 shows the set up proce dure Table 2 2 3 Choosed functions Count source Internal count source f fs f32 fc32 Pulse output function No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TAOIN pin is at L level Performs count only for the period in which the TAOIN pin is at H level Operation 1 Setting the count start flag to 1 causes the counter to perform a down count on the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer AO interrupt request bit goes to 1 Also the output polarity of the TAOOUT pin reverses 3 Setting the count start flag to O causes the counter to hold its value and to stop Also the TAOOUT pin outputs an L level n reload register content 1 Start count 3 Stop count 2 Underflow c Counter content hex Cleared to g by etto 1 by software software Set to 1 by software Count start flag Pulse output from TAOOUT pin Cleared to 0 when
80. Set bit 2 of protect register address 000A16 to 1 before rewriting to the port P4 direction register Note 2 Nothing is assigned in direction register of P36 P37 P46 P47 P55 to p57 P72 to P77 These bits can either be set nor reset When read its contents are indeterminate Port Pi register babe BS bd b3 ba bt b0 Symbol Address When reset Pi i 0 to 7 03E016 03E116 03E516 03E816 Indeterminate 03E916 03EC16 03ED16 Indeterminate Bit symbol R Port Pio regi Data is input and output to and from Port Pit register each pin by reading and writing to Port Piz register and from each corresponding bit n i 0 L level data Port Pis register 1 H level data Port Pi4 register Pi_5 Port Pis register i 0 to 7 except 2 Port Pie register Pi_7 Port Pi7 register Note Nothing is assigned in direction register of P36 P37 P46 P47 P55 to p57 P72 to P77 This bit can either be set nor reset When read its content is indeterminate Figure 2 12 2 Programmable I O ports related registers 1 321 xX xe Mitsubishi microcomputers vf M30201 Group og SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Ports Pull up control register 0 b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset PURO 03FC16 0016 Bit symbol PU00 Poo to Pos PUP The corresponding port is pulled PUO1 P04 to P07 pull up high with a pull up resistor 0 Not pulled high PU02 P10 to P13 pull up 1 Pulled high PU03 P14
81. Sleep mode is a mode in which data is transferred to a particular microcomputer among those con nected by use of clock asynchronous serial I O devices The following are examples in which functions a to e are chosen e Transmission WITHOUT other functions 0 eceeeceeeeeeeeeeeeeeeeeeeeeaeeeeeaaeeeeaeeeesaaaeseeeeeesiaaeeneaeees e Reception WITHOUT other functions 0 ceceece cece eeeeeeeeeceeeeeeeeececaeeeseaaeseceeeeseaaeeeeneeeessaeenseaeees 6 Input output to the serial I O and the direction register To input an external signal to the serial I O set the direction register of the relevant port to input To output a signal from the serial I O set the direction register of the relevant port to output 7 Pins related to the serial I O e CLKo pins Input pins for the transfer clock e RxDo RxD1 pins Input pins for data e TxDo TxD1 pins Output pins for data 259 N Q Mitsubishi microcomputers R Sy M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART 8 Registers related to the serial I O Figure 2 6 2 shows the memory map of serial I O related registers and Figures 2 6 3 to 2 6 7 show UARTi related registers 005116 UARTO transmit interrupt control register SOTIC 005216 UARTO receive interrupt control register SORIC 005316 UART1 transmit interrupt control regster S1 TIC 005416 UART1 receive interrupt control register S1 RIC 03A016 UARTO transmit receive mode regist
82. Stack status before interrupt request Stack status after interrupt request is acknowledged is acknowledged Figure 1 27 State of stack before and after acceptance of interrupt request 40 Interrupts Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer Note at the time of acceptance of an interrupt request is even or odd If the content of the stack pointer Note is even the content of the flag register FLG and the content of the program counter PC are saved 16 bits at a time If odd their contents are saved in two steps 8 bits at atime Figure 1 28 shows the operation of the saving registers Note Stack pointer indicated by U flag 1 Stack pointer SP contains even number Address SP 5 Odd SP 4 Even SP 3 Odd SP 2 Even SP 1 Odd SP Even Stack area Program counter PCL Program counter PCm Flag register FLG Flag register FLGu Program counter PCx Sequence in which order registers are saved 2 Saved simultaneously all 16 bits 1 Saved simultaneously all 16 bits Finished saving registers in two operations 2 Stack pointer SP contains odd number Address SP 5 Even SP 4 Odd SP 3 Even SP 2 Odd SP 1 Even SP Odd Stack area
83. Time Time n reload register content n reload register content Figure 2 2 29 Reading timer AO register Voc 5V XIN 10MHz cane Min Min TA4IN Vcc 3V f XIN 7MHz one wait TA20UT TAS3OUT TA40UT Figure 2 2 30 Standard of 2 phase pulses 191 x o amp g Mitsubishi microcomputers S M30201 Group T A SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Imer 2 2 15 Precautions for Timer A one shot timer mode 1 To clear reset the count start flag is set to 0 Set a value in the timer AO register then set the flag to 1 2 Setting the count start flag to 0 while a count is in progress causes as follows e The counter stops counting and a content of reload register is reloaded e The TAOOUT pin outputs L level e The interrupt request generated and the timer AO interrupt request bit goes to 1 3 The output from the one shot timer synchronizes with the count source generated internally Therefore when an external trigger has been selected a delay of one cycle of the maximum count source occurs between the trigger input to the TAOIN pin and the one shot timer output 4 The timer AO interrupt request bit goes to 1 if the timer s operation mode is set using any of the following procedures e Selecting one shot timer mode after reset e Changing operation mode from timer mode to one shot timer mode e Changing operation mode from event counter mode to
84. Timer A related registers 2 165 x OS Q P Mitsubishi microcomputers OO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Up down flag b7 b6 b5 b4 b3 b2 bi bd Symbol Address When reset UDF 038416 XXXOXXX02 Timer AO up down flag 0 Down count 1 Up count This specification becomes valid when the up down flag content is selected for up down switching cause Nothing is assigned When write set 0 When read their contents are indeterminate Timer AO two phase 0 two phase pulse signal pulse signal processing processing disabled select bit 1 two phase pulse signal processing enabled When not using the two phase pulse signal processing function set the select bit to 0 Nothing is assigned When write set 0 When read their contents are indeterminate One shot start flag yrrib l Aadtess When reset b7 b6 b5 b4 b3 b2 bi b0 ONSF 038216 XXXX00002 IE Timer AO one shot start flag 4 Timer start loio Timer X0 one shot start flag When read the value is 0 joio processes Timer X1 one shot start flag Timer X2 one shot start flag Nothing is assigned When write set 0 When read its content is indeterminate Figure 2 2 4 Timer A related registers 3 166 Timer A Trigger select register b7 b6 b5 b4 b3 b2 bi bO Symbol TRGSR Address 038316 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER When reset 0016 Bit symbol Rw
85. Trigger select bit 0 When the one shot start flag is set 1 0 Must always be 0 in one shot timer mode Count source select bit Count Count source period YB fi SOUrCe Xin 10MHZ f Xcin 32 768kHz 01 f8 0 100ns 10 f32 i 800ns 1 1 fcs2 3 24s 976 56us Note Set the corresponding port direction register to 1 output mode TXiINOUT pin is not selected as count source when pulse output function selected io Clearing timer Xi interrupt request bit Refer to Precaution for Timer X one shot timer mode b7 b0 0 Timer Xi interrupt control register Address 005516 TXiIC i 0 to 2 Interrupt request bit Xe Setting one shot timer s time b15 b8 b7 0 b7 Timer XO register Address 038916 038816 TXO Timer X1 register Address 038B16 038A16 TX1 Timer X2 register Address 038D16 038C16 TX1 Can be set to 000116 to FFFF16 7 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 Clock prescaler reset flag Address 038116 LADD CPSRE Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O a Setting count start flag b7 bo x Ee Count start flag Address 038016 TABSR Timer X0 count start flag Timer X1 count star
86. U1IRS UART1 transmit Set this bit to 0 interrupt cause select bit Continuous receive mode disabled Continuous receive mode enable UORRM UARTO continuous receive mode enable bit Set this bit to O CLKMDO CLK CLKS select bit 0 Valid when bit 5 1 0 Clock output to CLK1 1 Clock output to CLKS1 CLKMD1 CLK CLKS select 0 Normal mode bit 1 Note 2 CLK output is CLKO only Transfer clock output from multiple pins function selected Nothing is assigned When write set 0 When read its content is indeterminate Note 1 UART1 cannot be used in clock synchronous serial I O transmit buffer register During clock synchronous 0 Data present in transmit buffer register No data present in transmit buffer register 0 No data present in receive buffer register Data present in receive buffer register Function During UART mode 0 Transmit buffer empty Tl 1 T RA completed TXEPT 1 0 Transmit buffer empty Tl 1 1 Transmission completed TXEPT 1 Invalid eke Must always be 0 Note 2 When using multiple pins to output the transfer clock the following requirements must be met e UARTO internal external clock select bit bit 3 at address 03A016 0 Figure 1 73 Serial l O related registers 3 80 x Ss Q s Mitsubishi microcomputers ve M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock synchronous
87. When going to low speed or lower power consumption mode make sure the sub clock is oscillating stably 4 Division by 16 mode The main clock is divided by 16 to obtain the BCLK 5 No division mode The main clock is divided by 1 to obtain the BCLK 6 Low speed mode fc is used as BCLK Note that oscillation of both the main and sub clocks must have stabilized before transferring from this mode to another or vice versa At least 2 to 3 seconds are required after the sub clock starts Therefore the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled 7 Low power dissipation mode fc is the BCLK and the main clock is stopped Note Before the count source for BCLK can be changed from XIN to XCIN or vice versa the clock to which the count source is going to be switched must be oscillating stably Allow a wait time in software for the oscillation to stabilize before switching over the clock Table 1 6 Operating modes dictated by settings of system clock control registers 0 and 1 Operating mode of BCLK Invalid Division by 2 mode Invalid Division by 4 mode Invalid Invalid Invalid Division by 8 mode 1 1 Invalid Division by 16 mode 0 0 Invalid No division mode Invalid Invalid Invalid Low speed mode Invalid Invalid Invalid Low power dissipation mode y x Mitsubishi microcomputers df Sy M30201 Group og SINGLE CHIP 16 BIT
88. address 2 Vector address 3 High address 0000 Figure 1 23 Format for specifying interrupt vector addresses Fixed vector tables The fixed vector table is a table in which addresses are fixed The vector tables are located in an area extending from FFFDC16 to FFFFF1i6 One vector table comprises four bytes Set the first address of interrupt routine in each vector table Table 1 7 shows the interrupts assigned to the fixed vector tables and addresses of vector tables Table 1 7 Interrupt and fixed vector address Interrupt source Vector table addresses Address L to address H Undefined instruction FFFDCie to FFFDFi6 Remarks Interrupt on UND instruction Overflow FFFE016 to FFFES3i6 Interrupt on INTO instruction BRK instruction FFFE416 to FFFE716 If the vector is filled with FF16 program execution starts from the address shown by the vector in the variable vector table Address match FFFE816 to FFFEB16 There is an address matching interrupt enable bit Single step Note FFFECie to FFFEFi6 Do not use Watchdog timer FFFFO16 to FFFF316 DBC Note FFFF416 to FFFF7 16 Do not use FFFF816 to FFFFB16 Reset Note Interrupts used for debugging purposes only FFFFCis to FFFFFie 32 Interrupts Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Variable vector tables The addresses in the varia
89. address 000E16 and when a watchdog timer interrupt request is generated The prescaler is initialized only when the microcomputer is reset After a reset is cancelled the watchdog timer and prescaler are both stopped The count is started by writing to the watchdog timer start register address 000E 16 Figure 1 34 shows the block diagram of the watchdog timer Figure 1 35 shows the watchdog timer related registers Prescaler Watchdog timer interrupt request Watchdog timer e Write to the watchdog timer start register address 000E16 pest gt gt Figure 1 34 Block diagram of watchdog timer 47 amp O amp Mitsubishi microcomputers Se M30201 Group a SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Watchdog Timer Watchdog timer control register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset lojo I WDC 000F16 000XXXXX2 Bit symbol High order bit of watchdog timer Reserved bit Must always be set to 0 ee i Reserved bit Must always be set to 0 o 0 WDC7 Prescaler select bit 0 Divided by 16 1 Divided by 128 Watchdog timer start register br Bo Symbol Address When reset Loo O WDTS 000E16 Indeterminate Function i The watchdog timer is initialized and starts counting after a write instruction to this register The watchdog timer value is always initialized to 7FFF16 regardless of whatever value is written Figure 1 35 Watch
90. all memory locations to be erased must have had data 0016 written to by using the program and program verify commands During erase operation the watchdog timer remains idle with the value 7FFF16 set in it Note 1 The erase operation is not completed immediately by writing an erase command once The user must always execute an erase verify command after each erase command executed And if verification fails the user need to execute the erase command repeatedly until the verification passes See Figure BB 3 for an example of an erase flowchart Erase verify command A016 The erase verify mode is entered by writing the command code A016 to the flash command register in the first bus cycle When the user execute an instruction to read byte data from the address to be verified e g LDE instruction in the second bus cycle the content of the address is read out The GPU must sequentially erase verify memory contents one address at a time over the entire area erased If any address is encountered whose content is not FF 16 not erased the CPU must stop erase verify at that point and execute erase and erase verify operations one more time Note 1 If any unerased memory location is encountered during erase verify operation be sure to execute erase and erase verify operations one more time In this case however the user does not need to write data 0016 to memory before erasing 132 amp Ss Mitsubishi microcomputers
91. and falling edges Timer overflow TBj overflow Operation 1 Setting the count start flag to 1 causes the counter to count the falling edges of the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer Bi interrupt request bit goes to 1 3 Setting the count start flag to O causes the counter to hold its value and to stop n reload register content 1 Start count 2 Underflow 3 Stop count Counter content hex Time Set to 1 by software TA Set to 1 by softwar A software Count start flag i i ii Cleared to 0 by l Cleared to 0 when interrupt request is accepted or cleared by software Timer Bi interrupt 4 E d 4 request bit g Figure 2 3 6 Operation timing of event counter mode 200 x N O aS Mitsubishi microcomputers SF of M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B Selecting event counter mode and functions Timer Bi mode register i 0 1 Address 039B16 039C16 TBiMR i 0 1 Selection of event counter mode Count polarity select bit b3 b2 0 0 Counts external signal falling edges Fixed to 0 in event counter mode Event clock select 0 Input from TBiIN pin Note Note Set the corresponding port direction register to 0 input mode Setting divide r
92. be performed in some cases It is recommended to see that measurements fall within a specific range by use of software 9 For pulse width measurement pulse widths are successively measured Use software to check whether the measurement result is an H level width or an L level width 207 O s Mitsubishi microcomputers Ss M30201 Group ro SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 Timer X 2 4 1 Overview The following is an overview for timer X a 16 bit timer 1 Mode Timer X operates in one of the four modes a Timer mode In this mode the internal count source is counted Two functions can be selected the pulse output function that reverses output from a port every time an overflow occurs or the gate function which controls the count start stop according to the input signal from a port lt Timer mode operaio es tees eesti etvedaneateetveriacerbante tei EEEE NEER E eile P212 Timer mode gate function operation s sseesesrsessssrresseennesennnnnnstennneennnnnnnetenneeennnannnnennneennnnnne P214 e Timer mode pulse output function operation ssssssssssrisssssrisssrrrsnstirnnnstinnnnntennnnntnnnnnnntennane P216 b Event counter mode This mode counts the pulses from the outside and the number of overflows in other timers The free run type in which nothing is reloaded from the reload register can be selected when an underflow occurs The pulse output function can also be selected Even
93. bit Stop peripheral function clock in wait mode Note 8 CM03 XCIN XCOUT drive capacity 0 LOW select bit Note 2 1 HIGH Port Xc select bit 0 I O port CM05 Main clock XIN XOUT r On stop bit Note 3 4 5 Off CM06 Main clock division select o CM16 and CM17 valid bit 0 Note 7 Division by 8 mode ee clock select bit 0 XIN XOUT Set bit 0 of the protect register address 000A16 to 1 before writing to this register Changes to 1 when shifting to stop mode and at a reset This bit is used to stop the main clock when placing the device in a low power mode If you want to operate with XIN after exiting from the stop mode set this bit to O When operating with a self excited oscillator set the system clock select bit CM07 to 1 before setting this bit to 1 When inputting external clock only clock oscillation buffer is stopped and clock input is acceptable If this bit is set to 1 XouT turns H The built in feedback resistor remains being connected so XIN turns pulled up to XouT H via the feedback resistor Set port Xc select bit CM04 to 1 and stabilize the sub clock oscillating before setting to this bit from 0 to 1 Do not write to both bits at the same time And also set the main clock stop bit CM05 to 0 and stabilize the main clock oscillating before setting this bit from 1 to O This bit changes to 1 when shiftin
94. cause select bit 1 TAiOuT pin s input signal Note 3 0 Must always be fixed to 0 in event counter mode Count operation type 0 Reload type select bit 1 Free run type TCK1 Two phase pulse operation 0 Normal processing operation select bit Note 4 1 Multiply by 4 processing operation Note 1 Set the corresponding port direction register to 1 output mode Note 2 This bit is valid when only counting an external signal Note 3 Set the corresponding port direction register to 0 input mode Note 4 When performing two phase pulse signal processing make sure the two phase pulse signal processing operation select bit address 038416 is set to 1 and event trigger select bits addresses 038316 to 00 Figure 1 42 Timer AO mode register in event counter mode 54 amp A ww lt S OC ww Timer A Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Table 1 15 Timer specifications in event counter mode when processing two phase pulse signal Specification Count source e Two phase pulse signals input to TAOIN or TAQOUT pin Count operation Up count or down count can be selected by two phase pulse signal e When the timer overflows or underflows the reload register content is reloaded and the timer starts over again Note Divide ratio e 1 FFFFis n 1 for up count e 1 n 1 for down count n Set value Count st
95. conversion result During 10 bit mode Two high order bits of A D conversion result During 8 bit mode When read the content is indeterminate Figure 2 7 6 Set up procedure of one shot mode 279 Ni Q amp Mitsubishi microcomputers Sy M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 3 Operation of A D Converter in repeat mode In repeat mode choose functions from those listed in Table 2 7 3 Operations of the circled items are described below Figure 2 7 7 shows timing chart and Figure 2 7 8 shows the set up procedure Table 2 7 3 Choosed functions Operation clock fAD Divided by 4 fab divided by 2 fab fAD Resolution 8 bit 10 bit Analog input pin One of ANo pin to AN7 pin Note Sample amp Hold Not activated Activated Note When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins AN50 to AN54 Operation 1 Setting the A D conversion start flag to 1 causes the A D converter to start operating 2 After the first conversion is completed the content of the successive comparison register conversion result is transmitted to A D register i The A D conversion interrupt request bit does not go to 1 3 The A D converter continues operating until the A D conversion start flag is set to O by software The conversion result is transmitted to A D register i every time a conversion is completed
96. count Timer AO two phase pulse signal processing select bit 0 Two phase pulse signal processing disabled Setting trigger select register b7 2 Trigger select register Address 038316 PERLA TRGSR Timer AO event trigger select bit b1 b0 0 0 Input on TAOIN is selected Note Note Set the corresponding port direction register to 0 input mode Setting divide ratio b15 b8 b7 b0 b7 bo Timer AO register Address 038716 038616 TAO E Can be set to 000016 to FFFF16 Setting count start flag b7 bo Count start flag Address 038016 TABSR Timer AO count start flag Start count Figure 2 2 13 Set up procedure of event counter mode reload type selected 175 x O Q sf Mitsubishi microcomputers SX M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 6 Operation of Timer A event counter mode free run type selected In event counter mode choose functions from those listed in Table 2 2 5 Operations of the circled items are described below Figure 2 2 14 shows the operation timing and Figure 2 2 15 shows the set up procedure Table 2 2 5 Choosed functions Count source Input signal to TAOIN Pulse output function No pulses output counting falling edges Pulses output Input signal to TAOIN Count operation type Reload type counting rising edges Free run type Timer overflow Factor for switching Content of u
97. delayed one shot output 335 K amp Mitsubishi microcomputers S Y SF of M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications Setting timer X0 Selecting one shot timer mode and functions Selection of one shot timer mode Pulse output function select bit 0 Pulse is not output External trigger select bit 0 Falling edge of TXOINOUT pin s input signal Trigger select bit 1 Selected by event trigger select register 0 Must always be 0 in one shot timer mode Count source select bit Count Count source period b7 b6 source f Xin 10MHz_ f XcIN 32 768kHz 00 fi Toons 800ns 3 2us 976 56us Setting trigger select register Select TXOINOUT pin to input TXO trigger ia eer To ea register Address 038316 E Timer X0 event trigger select bit b3 b2 0 0 Input on TXOINOUT is selected Note Note Set the corresponding port direction register to 0 input mode Setting delay time b15 b8 b7 b0 b7 b0 Continued to the next page Figure 3 3 3 Set up procedure of delayed one shot output 1 336 S xe amp Mitsubishi microcomputers SS M30201 Group ka ee SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications Continued from the previous page Setting timer X1 Selecting one shot timer mode and functions Selection of one shot timer mode Pulse output function select bit Note 1 Pul
98. diagram for the M30201 group amp S S SeS O Description Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Performance Outline Table 1 1 is performance outline of M30201 group Table 1 1 Performance outline of M30201 group ltem Performance Number of basic instructions 91 instructions Shortest instruction execution time 100ns f XIN 10MHz Memory ROM See figure 4 ROM expansion capacity RAM See figure 4 ROM expansion I O port PO to P7 43 lines Multifunction TAO 16 bits x 1 timer TBO TB1 16 bits x 2 TXO TX1 TX2 16 bits x 3 Serial I O UARTO UART or clock synchronous x 1 UART1 UART x 1 A D converter 10 bits x 8 channels Expandable up to 13 channels Watchdog timer 15 bits x 1 with prescaler Interrupt 9 internal and 3 external sources 4 software sources Clock generating circuit 2 built in clock generation circuits built in feedback resistor and external ceramic or quartz oscillator Supply voltage 4 0 to 5 5V f XIN 10MHz mask ROM version 2 7 to 5 5V f XIN 7MHz with software one wait mask ROM version 4 0 to 5 5V f XIN 10MHZ flash memory version Power consumption 18mW f XIN 7MHz with software one wait Vcc 3V mask ROM version 95mW f XIN 10MHz no wait Vcc 5V flash memory version O I O withstand voltage 5V characte
99. edge of transfer clock and receive data is input at rising edge Transmit data is output at rising edge of transfer clock and receive data is input at falling edge CKPOL CLK polarity select bit Note UART1 cannot be used in clock synchronous serial I O Figure 1 72 Serial l O related registers 2 79 TXDi pin is CMOS output TXDi pin is N channel open drain output Must always be 0 Serial I O UARTIi transmit receive control register 1 b7 b6 b5 b4 b3 b2 bi bO Address 03A516 03AD16 When reset 0216 Symbol UiC1 i 0 1 Bit Function serial I O mode During clock synchronous Function During UART mode je enable bit o Transmission disabled ne Transmission disabled Transmission enabled Transmission enabled ae buffer empty flag 0 Data present in No data present in transmit buffer register Receive complete flag 0 No data present in receive buffer register Data present in receive buffer register Nothing is assigned When write set 0 When read the value of these bits is 0 Note UART1 cannot be used in clock synchronous serial I O UART transmit receive control register 2 1 b7 b6 b5 b4 b3 b2 bi b0 Address 03B016 Bit Bit symbol name UOIRS UARTO transmit interrupt cause select bit When reset XX0000002 Symbol UCON Function serial I O mode 0 Transmit buffer empty Tl 1 1 Transmission completed TXEPT 1
100. eee TABSR Timer AO count start flag Start count Figure 2 2 11 Set up procedure of timer mode pulse output function selected 173 x O Q sf Mitsubishi microcomputers SF M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 5 Operation of Timer A event counter mode reload type selected In event counter mode choose functions from those listed in Table 2 2 4 Operations of the circled items are described below Figure 2 2 12 shows the operation timing and Figure 2 2 13 shows the set up procedure Table 2 2 4 Choosed functions Count source Input signal to TAOIN Pulse output function No pulses output counting falling edges Pulses output Input signal to TAOIN Count operation type Reload type counting rising edges Free run type Timer overflow Factor for switching Content of up down flag between up and TB1 TX0 TX2 overflow dawn p Input signal to TAQout Operation 1 Setting the count start flag to 1 causes the counter to count the falling edges of the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer AO interrupt request bit goes to 1 3 If switching from an up count to a down count or vice versa while a count is in progress the switch takes effect from the next effective edge of the count source 4 Setting the count start flag to O causes the c
101. f1 2 If the counter of timer XO underflows the counter reloads the content of the reload register and continues counting At this time the timer XO interrupt request bit goes to 1 The counter of timer X1 performs a down count on underflows in timer XO 3 If the counter of timer X1 underflows the counter reloads the content of the reload register and continues counting At this time the timer X1 interrupt request bit goes to 1 reload register content 1 Start count 2 Timer X0 underflow 3 Timer X1 underflow Timer XO counter content hex n reload register content i Start count l i o 2 E Q 3 x lt ta E k content hex Set to 1 by software Cleard 0 by software Time 1 1 i be a i Timer XO count start flag i i Set to 1 by software Timer X1 count 1 i i start flag Timer XO interrupt 1 i i request bit 0 lt a Cleared to 0 when interrupt request is accepted or cleared by software pee Timer X1 interrupt 1 Cid request bit 9 SSN Yr _ Figure 3 1 1 Operation timing of long period timers 326 Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Used for timer mode Timer XO interrupt request bit Timer X1 interrupt request bit Used for event counter mode
102. following explains about bus operation modes software commands and status register Bus Operation Modes Read only mode is entered by applying VPPH to the CNVSs pin and a low voltage to the VRFY pin Read only mode has three states Read Output Disable and Standby which are selected by setting the CE OE and WE pins high or low Read write mode is entered by applying VPPH to the CNVSs pin and a high voltage to the VRFY pin Read write mode has four states Read Output Disable Standby and Write which are selected by setting the CE OE and WE pins high or low Read The Read mode is entered by pulling the WE pin high when the CE and OE pins are low In Read mode the data corresponding to each software command entered is output from the data I O pins Do D7 Output Disable The Output Disable mode is entered by pulling the CE pin low and the WE and OE pins high Also the data I O pins are placed in the high impedance state Standby The Standby mode is entered by driving the CE pin high Also the data I O pins are placed in the high impedance state Write The Write mode is entered by applying VPPH to the CNVSs pin and a high voltage to the VRFY pin and then pulling the WE pin low when the CE pin is low and OE pin is high In this mode the device accepts the software commands or write data entered from the data I O pins A program erase or some other operation is initiated depending on the content of the software command entered
103. ie transmit interrupt control 005116 2 48 Port PO direction register 03E216 register is patria receive interrupt contro 005216 7 49 Port P1 direction register 03E316 14 e transmit interrupt control 9Q5316 r 50 Port P2 direction register 03E616 15 UART1 receive interrupt contro 005416 2 51 Port P3 direction register 03E716 register 16 Timer AO interrupt control regis 005516 52 Port P4 direction register 03EA16 17 Timer XO interrupt control regis 005616 2 53 Port P5 direction register 03EB16 18 Timer X1 interrupt control regis 005716 54 Port P6 direction register 03EE16 19 Timer X2 interrupt control regis 005816 2 55 Port P7 direction register O3EF 16 20 Timer BO interrupt control regis 005A16 2 56 Pull up control register 0 03FC16 4 21 Timer B1 interrupt control regis 005B16 7 57 Pull up control register 1 03FD16 0016 22 INTO interrupt control register 005D16 58 e drive capacity control 03FE16 0016 23 INT1 interrupt control register 005E16 2 59 Data registers RO R1 R2 R3 000016 24 Count start flag 038016 60 Address registers A0 A1 000016 25 Clock prescaler reset flag 038116 61 Frame base register FB 00
104. instruction Wait mode Figure 2 11 6 Example of wait mode set up ET 316 x Cy xe Ss Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Power Control 2 11 4 Precautions in Power Control 1 When returning from stop mode by hardware reset RESET pin must be set to L level until main clock oscillation is stabilized 2 When switching to either wait mode or stop mode instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every clock stop bit to 1 within the instruction queue are prefetched and then the program stops So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every clock stop bit to 1 3 Suggestions to reduce power consumption e Ports The processor retains the state of each programmable I O port even when it goes to wait mode or to stop mode A current flows in active I O ports A pass current flows in input ports that float When entering wait mode or stop mode set non used ports to input and stabilize the potential a A D converter A current always flows in the VREF pin When entering wait mode or stop mode set the Vref connection bit to 0 so that no current flows into the VREF pin b Stopping peripheral functions In wait mode stop non used wait peripheral functions using the peripheral function clock stop bit c Switching
105. instruction is executed 2 Interrupt enable flag I flag lt 1 Interrupt priority level select bit Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority IPL of the routine where the WAIT instruction is executed Reserved bit Must be set to 0 3 Canceling protect b7 b0 PPP PI T T Protect register Address 000A16 PRCR addresses 000616 and 000716 C 1 Write enabled Enables writing to system clock control registers 0 and 1 a 3 Control of CPU clock b7 b0 System clock control register 1 0 0 0jo0 Address 000716 CM1 Reserved bit Must be set to 0 Main clock division select bit b7 b6 0 0 No division mode 0 1 Division by 2 mode 1 0 Division by 4 mode 1 1 Division by 16 mode Note When switching the system clock it is necessary to wait for the oscillation to stabilize System clock control register 0 Address 000616 CMO WAIT peripheral function clock stop bit 0 Do not stop f1 fa f32 in wait mode Stop f1 fs f32 in wait mode Port Xc select bit 0 I O port XCIN XCOUT generation Main clock XIN XOuT stop bit 0 On Off Main clock division select bit 0 0 CM16 and CM17 valid Division by 8 mode System clock select bit Note 0 XIN XouT XCIN XCOUT 4 WAIT
106. interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt Also the interrupt enable flag flag and the IPL are located in the flag register FLG Figure 1 24 shows the interrupt control registers 34 O S Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Interrupt control register Address When reset 004D16 XXXXX0002 004E16 XXXXX0002 005116 005316 XXXXX0002 005216 005416 XXXXX0002 b7 b6 b5 b4 b3 b2 bi bO ilC i 005516 XXXXX0002 i 005616 to 005816 XXXXX0002 005A16 005B16 XXXXX0002 Interrupt priority level select bit Level 0 interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Interrupt request bit 0 Interrupt not requested Oo Oo 1 Interrupt requested Note Nothing is assigned When write set 0 When read their contents are indeterminate Note This bit can only be accessed for reset 0 but cannot be accessed for set 1 b b4 b3 b2 bi bO Symbol Address When reset 7 b6 b5 INTiIC i 0 1 005D16 005E XX00X000 A E E EEn Interrupt priority level select bit Level 0 interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 oo Level 6 Level 7 Interrupt request bit 0 Interrupt not requested o o 1 Interrupt requested Note POL Polarity select bit 0 Selects falling edge 1 Selects rising edge Re
107. interrupt request is accepted or cleared by software Timer AO interrupt 2 ee E request bit uA Figure 2 2 10 Operation timing of timer mode pulse output function selected 172 O V Mitsubishi microcomputers we M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Selecting timer mode and functions Selection of timer mode Pulse output function select bit Note 1 Pulse is output TAOOUT pin is a pulse output pin Gate function select bit b4b3 n Gate function not available TAOIN pin is a normal port pin 0 Must always be 0 in timer mode Count source select bit Count Count source period b7 b6 SOUICE f X N 10MHZz f Xc n 32 768kHz 00 f1 7 01 f8 a 10 f32 l 800ns 1 1 fc32 3 2us 976 56us Note Set the corresponding port direction register to 1 output mode Setting divide ratio b8 b0 b7 bO OoOo DO E Timer AO register Address 038716 038616 TAO a Can be set to 000016 to FFFF16 S Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 bO Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 Setting count start flag Bl bo Count start flag Address 038016
108. is completed The transfer clock stops at H level 4 If the next transmission data is set in the UARTO transmit buffer register while transmission is in progress before the eighth bit has been transmitted the data is transmitted in succession 242 x N xe sf Mitsubishi microcomputers SF M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Example of wiring Microcomputer Receiver side IC CLKO CLK TxDO RxD Example of operation 1 Transmission enabled 3 Transmission is complete 4 Transmit next data 2 Start transmission Tce j i Transfer clock Transmit enable bit TE Data is set to UARTi transmit buffer register Transmit buffer empty flag TI i i ag T Transferred from UARTI transmit buffer register to UARTi transmit register Tek Stopped pulsing because transfer enable bit 0 noo POOOOOOCIOOHOHOOOE_LOOOOOOOE Transmit register empty flag TXEPT Transmit interrupt request bit IR xX A Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols Tc TCLK 2 n 1 fi The above timing applies to the following settings fi frequency of BRGi count source f1 f8 32 fC Internal clock is selected n value set to BRGi e CLK polarity select bit 0 e Transmit interrupt cause select bit 0 Figure 2 5 5 Operation timing of transmission in clock synch
109. is generated for every PWM output cycle Also when FF 16 is set for the significant 8 bits of the timer AO register the PWM output is H level for the entire period and an interrupt request is generated for every PWM output cycle fi Count source frequency f1 fs f32 fc32 n Timer value Conditions Reload register high order 8 bits 0216 Reload register low order 8 bits 0216 When timer overflow is selected in trigger 1 fi X m 1 X 2 1 Count source Note 1 Count start flag or i 1 Start count L Output level H to L 3 One period is g complete Cl eared to 0 when interrupt request is accepted or cleared by Sotware Interrupt request bit H of timer becoming a j trigger 4 Stop count eh yx met Underflow signal of 8 H bit prescaler Note 2 op I I l ll 4 fX m 1 Xn PWM pulse output p gt ee ee ieee enema mt Se J Le from TXiINOUT pin i i i Cleared to 0 when interrupt request is accepted or cleared by software Timer Xi interrupt request bit Note 1 The 8 bit prescaler counts the count source Note 2 The 8 bit pulse width modulator counts the 8 bit prescaler s underflow signal Note 3 m 0016 to FF16 n 0016 to FF16 Figure 2 4 22 Operation timing of pulse width modulation mode with 8 bit PWM mode selected 230 S S S ve xe Timer X Mitsubishi microcomputers
110. no U Connect oscillator circuit _P45 TX2INouT lt gt P44 INT1 TX1INOUT gt 79 P43 INTo TXOINOUT lt gt 20 P42 RxD1 lt gt P41 TAQout gt 55 P40 TAOIN TXD1 lt gt 23 Figure CC 2 Pin connection diagram in parallel I O mode 1 136 x N O s Mitsubishi microcomputers NO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER gt Appendix Parallel I O Mode Go GD ao lt gt P64 AN4 Apply Vi to this pin when VPP VPPH or Vit when VPP VPPL Step down transformer P51 RxDo ANs1 lt gt lt gt P67 AN7 C17 P50 TxDo AN5o d lt gt P52 CLK0o AN52 lt gt P53 CLKS ANs3 lt gt P54 CKouT AN54 5d 55 54 lt gt P62 AN2 lt gt P63 AN3 4J lt gt P66 ANe N C J gt POo Klo lt gt PoiiKh 3 lt gt P02 Ki2 gt Po3 Kis M30201 F6FP po Connect oscillator M30201F6TFP gt POs Kle O circuit Kle lt gt P07 KI7 gt P10 LEDo P45 TX2inouT lt gt 12 lt gt P11 LED1 P4a INT1 TXtinouT 4 gt J lt gt P12 LED2 P43 INTo TXOiNout lt gt 14 gt P13 LEDs3 Q EE Lie EF P42 RxD1 lt p P41 TAOOuT lt gt P40 TAOIN TxD1 lt gt Ge Figure CC 3 Pin connection diagram in parallel I O mode 2 137 N S amp YV N DO 2 gt Appendix Parallel I O Mode Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER User ROM and Boot ROM Areas In parallel I O mode the user
111. oase BRG count source select bit Invalid when external clock is selected Must be 0 in clock synchronous I O mode Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed Must be 1 in clock synchronous I O mode Data output select bit 0 TxDo pin is CMOS output 1 TxDo pin is N channel open drain output CLK polarity select bit Note 0 Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 LSB first Note Set the corresponding port direction register to O input mode ra Setting UART transmit receive control register 2 Z po UART transmit receive control register 2 XxIxle Jo 0 UCON Address 03B016 Must be 0 in clock synchronous I O mode UARTO continuous receive mode enable bit 0 Continuous receive mode disabled Must be 0 in clock synchronous I O mode Valid when bit 5 1 CLK CLKS select bit 1 0 Normal mode Continued to the next page Figure 2 5 12 Set up procedure of reception in clock synchronous serial I O mode 1 252 x N xe sf Mitsubishi microcomputers SF M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Continued from the previous page Reception enabled b7 b0 KEKE PTT
112. of occurs when the total number the UARTIi receive buffer of 1 s in character bits and the register parity bit is different from the specified number Error sum flag e This flag turns on when any e When all error overrun error overrun framing or framing and parity are parity is detected removed the flag is cleared 4 How to deal with an error When receiving data read an error flag and reception data simultaneously to determine which error has occurred If the data read is erroneous initialize the error flag and the UARTIi receive buffer register then receive the data again To initialize the UARTi receive buffer register 1 Set the receive enable bit to O disable reception 2 Set the receive enable bit to 1 again enable reception To transmit data again due to an error on the reception side set the UARTIi transmit buffer register again then transmit the data again To set the UARTi transmit buffer register again 1 Set the serial I O mode select bits to 0002 invalidate serial I O 2 Set the serial I O mode select bits again 3 Set the transmit enable bit to 1 enable transmission then set transmission data in the UARTi transmit buffer register 258 amp CA PEE SRT Mitsubishi microco puters F amp S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART 5 Functions selection In operating UART the following functions can be used a Sleep mode
113. of watchdog timer 300 O gs Mitsubishi microcomputers Sy M30201 Group sy SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Watchdog Timer a Setting watchdog timer control register Watchdog timer control register Address O000F 16 Reserved bit Must always be 0 Prescaler select bit 0 Divided by 16 1 Divided by 128 7 Setting watchdog timer start register b7 bo oo Watchdog timer start register Address 000E16 WDTS Loo The watchdog timer is initialized and starts counting with a write instruction to this register The watchdog timer value is always initialized to 7FFF16 regardless of the value written Generating watchdog timer interrupt Software reset oa Processor mode register 0 Address 000416 PMO Software reset bit The device is reset when this bit is set to 1 The value of this bit is O when read XX Figure 2 8 4 Set up procedure of watchdog timer 301 N O Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Address Match Interrupt 2 9 Address Match Interrupt 2 9 1 Overview The address match interrupt is used for correcting a ROM or for a simplified debugging purpose monitor The following is an overview of the address match interrupt 1 Enabling disabling the address match interrupt The address match interrupt enable bit can be used to enable and disable an address match interrupt
114. one product to another This manual gives descriptions of M30201M4 XXXSP Memories built in are as shown below Be careful when writing a program as the memories have different capacities The figure of each register configuration describes its functions contents at reset and attributes as follows RAM Size Byte pgp Ne chee ata ate ea O ae OEE M30201F6SP FP ea M30201F6TSP FP i Under development M30201M4 XXXSP FP 4k ar Gla aaa ieee M30201M4T XXXSP FP j 77 7 7 77 7 Under development 5ta hem M30201M2 XXXSP FP Ne cet ete S f cine ednwecene M30201M2T XXXSP FP Under planning 16K 32K 48K ROM Size Byte This manual comprises of eight chapters Use the suggested chapters as a reference for the following topics e Bit attribute R Read W Write O Possible to read O Possible to write X Impossible to read X lmpossible to write Bit attribute One shot start flag Symbol Address When reset b7_b6 W5 ba WS 62 bi W ONSF 038216 00x000002 i i Bit symbol Bit name Function Eoi oioi i tf 54 TA0OS Timer AO one shot start flag 4 Timer start DOROGA eese TAiOS Timer A1 one shot start flag When read ine value is 0 OO roe eae eee TA20S_ Timer A2 one shot start flag oo NPG Geeeeeteeee TA30S_ Timer A3 one shot start flag oo iS i REEE TA4OS Timer A4 one shot start flag oo
115. particular when the Vref connection bit is changed from 0 to 1 start A D conversion after an elapse of 1 us or longer 2 When changing A D operation mode select analog input pin again 3 Using one shot mode or single sweep mode Read the correspondence A D register after confirming A D conversion is finished It is known by A D conversion interrupt request bit 4 Using repeat mode repeat sweep mode 0 or repeat sweep mode 1 Use the undivided main clock as the internal CPU clock Stop Mode and Wait Mode 1 When returning from stop mode by hardware reset RESET pin must be set to L level until main clock oscillation is stabilized 2 When shifting to WAIT mode or STOP mode the program stops after reading 8 bytes from the WAIT instruction and the instruction that sets all clock stop bits to 1 in the instruction queue Therefore insert a minimum of 8 NOPs after the WAIT instruction and the instruction that sets all clock stop bits to 1 110 N O S Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Usage precaution Interrupts 1 Reading address 0000016 e When maskable interrupt is occurred CPU read the interrupt information the interrupt number and interrupt request level in the interrupt sequence The interrupt request bit of the certain interrupt written in address 0000016 will then be set to O Reading address 0000016 by software sets enabled hi
116. pin H input signal en i Cleared to 0 when interrupt request is accepted or cleared by software Timer Xi interrupt 1 M request bit g Set to 1 by software i Figure 2 4 6 Operation timing of timer mode gate function selected 214 x N O aS Mitsubishi microcomputers Se M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Selecting timer mode and functions Timer Xi mode register i 0 to 2 Address 039716 to 039916 TXiMR i 0 to 2 Selection of timer mode Pulse output function select bit 0 Pulse is not output Set to O when gate function selected Gate function select bit b4 b3 1 1 Timer counts only when TXiINOUT pin is held H Note L 0 Must always be 0 in timer mode om source select bit Count Count source period 00 f SOUICE XIN 10MHz f XcIN 32 768kHz 01 fs 100ns 10 f32 800ns 1 1 fc32 3 2us 976 56us aks Set the corresponding port direction register to 0 input mode Setting divide ratio bs poe Timer XO register Address 038916 038816 TXO Timer X1 register Address 038B16 038A16 TX1 Timer X2 register Address 038D16 038c16 TX2 _ Can be set to 000016 to FFFF16 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by
117. pins for the transfer clock e RxDO RxD1 pins Input pins for data e TxDO TxD1 pins Output pins for data Since TxD2 pin is N channel open drain this pin needs pull up resistor e CLKS pin Output pin for transfer clock Can be used as transfer clock output pin in the transfer clock output to multiple pins function Note UART1 cannot be used in clock synchronous serial I O mode 8 Registers related to the serial I O Figure 2 5 1 shows the memory map of serial I O related registers and Figures 2 5 2 to 2 5 4 show serial I O related registers UART1 transmit interrupt control regster S1TIC UART1 receive interrupt control register S1 RIC 034016 UARTO transmit receive mode register UOMR 03A116 UARTO bit rate generator UOBRG 03A316 UARTO transmit buffer register UOTB 03A416 UARTO transmit receive control register 0 UOCO 03A516 UARTO transmit receive control register 1 U0C1 03A616 7 eo UARTO receive buffer register UORB 034816 UART1 transmit receive mode register U1MR 03A916 UART1 bit rate generator U1BRG 03AA16 3 o3ABie UART1 transmit buffer register U1TB 03AC16 UART1 transmit receive control register 0 U1C0 03AD16 UART1 transmit receive control register 1 U1C1 O3AE16 i o3AFie UART1 receive buffer register U1RB 03B016 UART transmit receive control register 2 UCON 03B116 Figure 2 5 1 Memory map of serial I O related registers 238
118. prescaler selected Table 2 8 1 The watchdog timer cycle Period Approx 52 4ms Note Approx 419 2ms Note Approx 104 9ms Note Approx 838 8ms Note Approx 209 7ms Note Approx 1 68s Note Approx 838 8ms Note Approx 6 71s Note 0 Approx 419 2ms Note 1 Approx 3 35s Note 10MHz 5MHz 2 5MHz 0 625MHz 1 Invalid Invalid 1 25MHz Invalid Invalid Invalid 32kHz Invalid Approx 2s Note Note An error due to the prescaler occurs 298 xX Ss O s Mitsubishi microcomputers Sy M30201 Group sy SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Watchdog Timer 6 Registers related to the watchdog timer Figure 2 8 1 shows the memory map of watchdog timer related registers and Figure 2 8 2 shows watchdog timer related registers 000E16 Watchdog timer start register WDTS 000F16 Watchdog timer control register WDC Figure 2 8 1 Memory map of watchdog timer related registers Watchdog timer control register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset ojo WDC 000F16 000XXXXX2 High order bit of watchdog timer Reserved bit Must always be set to 0 a i Reserved bit Must always be set to 0 o0 WDC7 Prescaler select bit 0 Divided by 16 1 Divided by 128 Watchdog timer start register b7 bo Symbol Address When reset Lo WDTS 000E16 Indeterminate Function The watchdog timer is initialized and starts countin
119. register 16 8 bit PWM mode select bit 0 Functions as a 16 bit pulse width modulator Count source select bit Count Count source period b7 b6 i SOUICE f Xin 10MHz f XcIN 32 768kHz 00 fi 100ns 01 fat 0 f321 800ns 1 fc32 3 2us 976 56us Note 1 Set the corresponding port direction register which outputs the pulse to 1 output mode Clearing timer AO interrupt request bit Refer to Precaution for Timer A pulse width modulation mode XXXL T Timer AO interrupt control register Address 005516 TAOIC Interrupt request bit Setting trigger select register b7 b0 Trigger select register Address 038316 TRGSR L Timer AO event trigger select bit b1 b0 0 0 Input on TAOIN is selected Note 2 Note 2 Set the corresponding port direction register to 0 input mode a Setting PWM pulse s H level width b15 b8 b7 b0 b7 bo a Timer AO register Address 038716 038616 TAO a Can be set to 000016 to FFFE16 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 DDDDPEM Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O xe Setting coun
120. register the PWM output is L level for the entire period and an interrupt request is generated for every PWM output cycle Also when FFFF 16 is set for the timer AO register the PWM output is H level for the entire period and an interrupt request is generated for every PWM output cycle fi Count source frequency f1 fs f32 f 32 n Timer value Conditions Reload register 000316 external trigger rising edge of TAOIN pin input signal is selected 1 fiX 2 1 i i Count source H i TAOIN pin see i i i input signal f Trigger is not generated by this signal Set to 1 by software y oa Count start flag 1 Start count 2 Output level H to L 3 One period is complete w 1 fi Xn 4 Stop count PWM pulse output from TAOOUT pin Cleared to 0 when interrupt request is Timer AO interrupt 1 accepted or cleared by software request bit o Note n 000016 to FFFE16 Figure 2 2 24 Operation timing of pulse width modulation mode 16 bit PWM mode selected 186 x N xe sf Mitsubishi microcomputers S M30201 Group T A SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Imer Selecting PWM mode and functions p7 a Timer AO mode register Address 039616 Selection of PWM mode 1 Must always be 1 in PWM mode External trigger select bit 1 Rising edge of TAOIN pin s input signal Note 1 Trigger select bit 1 Selected by event trigger select
121. register is not reloaded but the count continues At this time the timer AO interrupt request bit goes to 1 Note e The up count or down count conditions are as follows Table 2 2 8 The up count or down count conditions Input signal to the TAOOUT pin H level Input signal to the TAOIN pin Rising L level Falling Rising L level Falling 1 Start count H level es Input signal to the TAOOUT pin H level Input signal to the TAOIN pin Falling L level Rising Rising H level Falling L level ore ittad rrr Input pulse FELI FFFF16 PA z oO g E Q i 2 3 fe Q 000016 Set to 1 by software _ 2 Underflow 3 Time Overflow Count start flag 1 o Timer AO interrupt 4 request bit o Cleared to 0 when interrupt request is accepted or cleared by software r Figure 2 2 18 Operation timing of 2 phase pulse signal process in event counter mode multiply by 4 mode selected 180 O s Mitsubishi microcomputers we M30201 Group v SINGLE CHIP 16 BIT CMO
122. reload timing is in step with the next count source input after the trigger 4 Setting the count start flag to O causes the counter to stop and to reload the content of the reload register Also the TAOOUT pin outputs an L level At this time the timer AO interrupt request bit goes to 1 n reload register content g 2 Stop count 1 Start count 3 Start count Start count 4 Stop count Reload E Reload Counter content hex Cleared to 0 by software sa Count start flag Write signal to one shot start flag One shot pulse output H from TAQOUT pin Timer AO interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software Figure 2 2 20 Operation timing of one shot mode 182 amp ORS S OX x Timer A Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Selecting one shot timer mode and functions b7 Selection of one shot timer mode Pulse output function select bit 1 Pulse is output Note External trigger select bit When internal is selected this bit can be 1 or 0 Trigger select bit 0 When the one shot start flag is set 1 0 Must always be 0 in one shot timer mode Count source select bit b7 be Count Count source period ie source f XiN 10MHz f Xcin 32 768kHz s 01 f8 fi 100ns 10 f32 i fe 800ns 11 fc32 f32
123. serial I O mode 1 Clock synchronous serial I O mode The clock synchronous serial I O mode uses a transfer clock to transmit and receive data See Table 1 26 Figure 1 65 shows the UARTO transmit receive mode register Table 1 26 Specifications of clock synchronous serial I O mode Transfer data format e Transfer data length 8 bits Transfer clock e When internal clock is selected bit 3 at address 03A016 O fi 2 n 1 Note 1 fi f1 f8 32 fe e When external clock is selected bit 3 at address 03A016 1 Input from CLKO pin Transmission start e To start transmission the following requirements must be met condition Transmit enable bit bit 0 at address 03A516 1 Transmit buffer empty flag bit 1 at addresses 03A516 0 e Furthermore if external clock is selected the following requirements must also be met CLKO polarity select bit bit 6 at address 03A416 0 CLKO input level H CLKO polarity select bit bit 6 at address 03A416 1 CLKO input level L Reception start e To start reception the following requirements must be met conditio Receive enable bit bit 2 at address 03A516 1 Transmit enable bit bit O at address 03A516 1 Transmit buffer empty flag bit 1 at address 03A516 0 e Furthermore if external clock is selected the following requirements must also be met CLKO polarity select bit bit 6 at address 03A41
124. start flag TABSR 038116 Clock prescaler reset flag CPSRF 038216 One shot start flag ONSF 038316 Trigger select register TRGSR 038416 Up down flag UDF 038816 038916 038A16 038B16 Timer XO TX0 Timer X1 TX1 038C16 Timer X2 TX2 038D16 039716 Timer XO mode register TXOMR 039816 Timer X1 mode register TX1MR 039916 Timer X2 mode register TX2MR Figure 2 4 1 Memory map of timer X related registers E 209 O s Mitsubishi microcomputers Sis M30201 Group v SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer Xi mode register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset TXiMR i 0 to 2 039716 to 039916 0016 Bit symbol Bit name Function TMODO Operation mode Timer mode select bit Event counter mode 0 One shot timer mode or pulse period pulse width measurement mode Pulse width modulation PWM mode Function varies with each operation mode Count source select bit Function varies with each operation mode Note 1 Must set 00 to operation mode select bit when using timer X2 of M30200 Timer Xi register Note b15 Address When reset b7 038916 038816 Indeterminate 038B16 038A16 Indeterminate 038D16 038C16 Indeterminate Function Values that can be set R W Timer mode 000016 to FFFF16 i A Counts an internal count source 1 Event counter mode 000016 to FFFF16 Counts pulses from an ex
125. start flag to O while a count is in progress causes as follows e The counter stops counting and a content of reload register is reloaded e The TAOOUT pin outputs L level e The interrupt request generated and the timer AO interrupt request bit goes to 1 2 The timer AO interrupt request bit goes to 1 if the timer s operation mode is set using any of the following procedures e Selecting one shot timer mode after reset e Changing operation mode from timer mode to one shot timer mode e Changing operation mode from event counter mode to one shot timer mode Therefore to use timer AO interrupt interrupt request bit set timer AO interrupt request bit to 0 after the above listed changes have been made Timer A pulse width modulation mode 1 The timer AO interrupt request bit becomes 1 if setting operation mode of the timer in compliance with any of the following procedures e Selecting PWM mode after reset e Changing operation mode from timer mode to PWM mode e Changing operation mode from event counter mode to PWM mode Therefore to use timer AO interrupt interrupt request bit set timer AO interrupt request bit to 0 after the above listed changes have been made 2 Setting the count start flag to O while PWM pulses are being output causes the counter to stop counting If the TAOOUT pin is outputting an H level in this instance the output level goes to L and the timer AO inte
126. the operation timing and Figure 2 2 7 shows the set up procedure Table 2 2 1 Choosed functions Count source Internal count source f1 fs f32 fc32 Pulse output function No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TAOIN pin is at L level Performs count only for the period in which the TAOIN pin is at H level Operation 1 Setting the count start flag to 1 causes the counter to perform a down count on the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer AO interrupt request bit goes to 1 3 Setting the count start flag to O causes the counter to hold its value and to stop n reload register content 1 Start count 2 Underflow Start count again Counter content hex Time Cleared to 0 by l Set to 1 by software software Contstatflag L a a S a Cleared to 0 when interrupt request is accepted or cleared by software Timer AO interrupt 4 m rd D BS request bit g Figure 2 2 6 Operation timing of timer mode Set to 1 by software 168 O g Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Selecting timer mode and functions Selection of timer mode Pulse output function select bit 0 Pul
127. the oscillation driving capacity Set the driving capacity to LOW when oscillation is stable d External clock When using an external clock input for the CPU clock set the main clock stop bit to 1 Setting the main clock stop bit to 1 causes the XOUT pin not to operate and the power consumption goes down when using an external clock input the clock signal is input regardless of the content of the main clock stop bit 317 xX Se xe Ss Mitsubishi microcomputers SF of M30201 Group og SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Ports 2 12 Programmable I O Ports 2 12 1 Overview Fourty three programmable I O ports I O pins also serve as I O pins for built in peripheral functions Each port has a direction register that defines the I O direction and also has a port register for I O data In addition each port has a pull up control register that defines pull up in terms of 4 bits Port P1 can be set to N channel output transistor drive capacity The following is an overview of the programmable I O ports 1 Writing to a port register With the direction register set to output the level of the written values from each relevant pin is output by writing to a port register The output level conforms to CMOS output Writing to the port register with the direction register set to input inputs a value to the port register but nothing is output to the relevant pins The output level remains floating 2 R
128. timer overflows or underflows TAOIN pin function Programmable I O port or count source input TAOOUT pin function Programmable I O port pulse output or up down count select input Read from timer Count value can be read out by reading timer AO register Write to timer e When counting stopped When a value is written to timer AO register it is written to both reload register and counter When counting in progress When a value is written to timer AO register it is written to only reload register Transferred to counter at next reload time Select function e Free run count function Even when the timer overflows or underflows the reload register content is not reloaded to it e Pulse output function Each time the timer overflows or underflows the TAQOUT pin s polarity is reversed Note This does not apply when the free run function is selected Timer AO mode register When not using two phase pulse signal processing b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset 1 TAOMR 039616 0016 Bit symbol Bit name Function TMODO Operation mode select bit 51 0 1 Event counter mode Pulse output function 0 Pulse is not output select bit TAOOUT pin is a normal port pin Pulse is output Note 1 TAOOUT pin is a pulse output pin Count polarity Counts external signal s falling edge select bit Note 2 Counts external signal s rising edge Up down switching 0 Up down flag s content
129. timer underflows TAOIN pin function Programmable I O port or gate input TAOOUT pin function Programmable I O port or pulse output Read from timer Count value can be read out by reading timer AO register Write to timer e When counting stopped When a value is written to timer AO register it is written to both reload register and counter e When counting in progress When a value is written to timer AO register it is written to only reload register Transferred to counter at next reload time Select function e Gate function Counting can be started and stopped by the TAOIN pin s input signal e Pulse output function Each time the timer underflows the TAQOUT pin s polarity is reversed Timer AO mode register b7 b6 b5 b4 b3 b2 bi b0 Address 039616 When reset 0016 RW Operation mode b1 b0 i 0 0 Timer mode select bit 0 Pulse is not output TAOOUT pin is a normal port pin 1 Pulse is output Note 1 TAOOuT pin is a pulse output pin b4 b3 0 X Note 2 Gate function not available TAOIN pin is a normal port pin 1 0 Timer counts only when TAOIN pin is held L Note 3 1 1 Timer counts only when TAOIN pin is held H Note 3 Symbol TAOMR Pulse output function select bit Gate function select bit 0 Must always be fixed to 0 in timer mode Count source select bit Note 1 Set the corresponding port direction register to 1 output mode
130. to 1 by hardware when an interrupt is requested After the interrupt is accepted and jumps to the corresponding interrupt vector the request bit is set to 0 by hardware The interrupt request bit can also be set to 0 by software Do not set this bit to 1 359 xX Cy xe Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 2 3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level IPL Set the interrupt priority level using the interrupt priority level select bit which is one of the component bits of the interrupt control register When an interrupt request occurs the interrupt priority level is compared with the IPL The interrupt is enabled only when the priority level of the interrupt is higher than the IPL Therefore setting the interrupt priority level to 0 disables the interrupt Table 4 2 1 shows the settings of interrupt priority levels and Table 4 2 2 shows the interrupt levels en abled according to the consist of the IPL The following are conditions under which an interrupt is accepted interrupt enable flag I flag 1 interrupt request bit 1 interrupt priority level gt IPL The interrupt enable flag I flag the interrupt request bit the interrupt priority select bit and the IPL are independent and they are not affected by one another Table 4 2 1 Settings of interrupt priority levels Table 4 2 2 Interrupt levels enabled a
131. to P17 pull up PU06 P30 to P33 pull up PU07 P34 to P35 pull up Pull up control register 1 b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset PUR1 03FD16 0016 Bi aya F PHO P4o to P43 pull up The corresponding port is pulled high with a pull up resistor 1 Pulled high i Port P1 drive capacity control register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset DRR 03FE16 0016 AW Sel PI Nehamneloutpet O G transistor drive capaciy O O Bre o0 o0 oo o0 oio oio Figure 2 12 3 Programmable I O ports related registers 2 322 Chapter 3 Examples of Peripheral functions Applications x s O gs Mitsubishi microcomputers SF of M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Applications This chapter presents applications in which peripheral functions built in the M16C 20 are used They are shown here as examples In practical use make suitable changes and perform sufficient evaluation For basic use see Chapter 2 How to Use Peripheral Functions Here follows the list of applications that appear in this chapter 8 1 LONG PENOd TIM SIS semis anesiedepeded aah eaeaeiatedes E Geel aaena P326 e 3 2 Variable period variable duty PWM output eee eeeeetne cette enna e ee ee taaeeeeeetaeeeeeeeeaeeeeenena P330 e 3 3 Delayed one shot output ee cece eeceeeeceneeeeeeeee cent eeeaaeeeeeeeeeseaeeeseneeesaeeeseaaeeseeeeesaaeseenees P334 s 84 BUZZOPr QUU raana oi RA det ciene def
132. to PO P40 to P45 I O port P4 Input output This is a 6 bit I O port equivalent to PO The P40 pin is shared with timer AO input and serial I O output TxD1 The P41 pin is shared with timer AO output The P42 pin is shared with serial I O input RxD1 The P43 pin is shared with external interrupt INTO and timer XO input output TXOINOUT The P44 pin is shared with external interrupt INT1 and timer X1 input output TX1INOUT The P45 pin is shared with timer X2 input output TX2INOUT P50 to P54 I O port P5 Input output This is a 5 bit I O port equivalent to PO The P50 P51 P52 and P53 pins are shared with serial I O pins TxDo RxDo CLKo and CLKS The P54 pin is shared with clock output CLKOUT Also these pins are shared with analog input pins AN50 through AN54 P60 to P67 I O port P6 Input output This is an 8 bit I O port equivalent to PO These pins are shared with analog input pins ANo through AN7 P70 to P71 I O port P7 Input output This is a 2 bit I O port equivalent to PO These pins are used for input output to and from the oscillator circuit for the clock Connect a crystal oscillator between the XCIN and the XCOUT pins x O lt Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Memory Operation of Functional Blocks The M30201 accommodates certain units in a single chip These units include ROM and RAM to store instructions and data
133. transmit buffer register b7 b0 UARTO transmit receive control register 1 Address 03A516 U0C1 Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Writing next transmit data enabled XX a Writing next transmit data b15 b8 b7 b0 b7 DXEXKEKIXKIKE UARTO transmit buffer register Address 03A316 03A216 UOTB Setting transmission data a A EETETTETTETIETEETEETTTTETTETTETTETTETTITE oe Transmission is complete Figure 2 5 7 Set up procedure of transmission in clock synchronous serial I O mode 2 245 N A Mitsubishi microcomputers se M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O 2 5 3 Operation of the Serial I O transmission in clock synchronous serial I O mode transfer clock output from multiple pins function selected In transmitting data in clock synchronous serial I O mode choose functions from those listed in Table 2 5 2 Operations of the circled items are described below Figure 2 5 8 shows the operation timing and Figures 2 5 9 and 2 5 10 show the set up procedures Table 2 5 2 Choosed functions Transfer clock Internal clock f1 fa f32 fc source External clock CLKO pin CLK polarity Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer cl
134. trigger select bit b7 b6 0 1 TB1 overflow is selected 10 TX1 overflow is selected 1 1 TAO overflow is selected b7 Setting PWM pulse s H leve b15 b8 b0 b7 bO Timer X0 register Address 038916 038816 TXO Timer X1 register Address 038B16 038A16 TX1 Timer X2 register Address 038D16 038C16 TX2 Can be set to 000016 to FFFE16 Setting clock prescaler reset flag Me This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 CL XKKKKKEX Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O gt i Setting count starts flag b7 b0 TLLELIILI 1 Count start flag Address 038016 TABSR ___ Timer XO count start flag Timer X1 count start flag Timer X2 count start flag Start count Figure 2 4 23 Set up procedure of pulse width modulation mode 8 bit PWM mode selected 231 N A S LS Mitsubishi microcomputers SF of M30201 Group v SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 12 Precautions for Timer X timer mode event counter mode 1 To clear reset the count start flag is set to O Set a value in the timer Xi register then set the flag to 1 2 Reading the timer Xi register while a count i
135. x N xe sf Mitsubishi microcomputers SF M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O UARTIi transmit buffer register b15 b8 Symbol Address When reset b7 b0 b7 UOTB 03A316 03A216 Indeterminate U1TB O3ABi6 O3AA16 Indeterminate Transmit data Nothing is assigned When write set 0 When read their contents are indeterminate UARTi receive buffer register b15 b8 Symbol Address When reset bo by UORB 03A716 0O3A616 Indeterminate U1RB 03AF16 03AE16 Indeterminate Function During clock Function Bit name synchronous serial I O During UART mode mode Receive data Receive data Nothing is assigned When write set 0 When read the value of these bits is 0 Overrun error flag 0 No overrun error No overrun error Note 1 Overrun error found Overrun error found Framing error flag Invalid No framing error Note Framing error found Parity error flag Invalid No parity error Note Parity error found Error sum flag Invalid No error Note Error found Note Bits 15 through 12 are set to 0 when the serial I O mode select bit bits 2 to 0 at addresses 03A016 and 03A816 are set to 0002 or the receive enable bit is set to 0 Bit 15 is set to 0 when bits 14 to 12 all are set to O Bits 14 and 13 are also set to 0 when the lower byte of the UARTI receive buffer regi
136. 0 lt gt N C 4 gt POo Kio lt gt Pork g lt gt P02 Kle lt gt P03 Kis M30201F6FP lt gt Pos Kls lt gt P05 Ki5 M30201F6TFP 4 gt POsiKie gt Po7 KI7 gt P10 LEDo gt P11 LED1 4 gt P12 LED2 gt P13 LEDs O TEND Connect oscillator P45 TX2iNouT lt gt P4a INT1 TX1inout lt gt P43 INTo TXOINouT lt gt 14 Ko P42 RxD1 lt gt 45 P41 TAQOUT lt p gt P40 TAOIN TXD1 lt gt 17 Figure DD 2 Pin connections for serial I O mode 2 146 x Se xe RX Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode Standard Serial I O Mode The standard serial I O mode serially inputs and outputs the software commands addresses and data necessary for operating read program erase etc the internal flash memory It uses a purpose specific serial programmer The standard serial I O mode differs from the parallel I O mode in that the CPU controls operations like rewriting uses the CPU rewrite mode in the flash memory or serial input for rewriting data The standard serial I O mode is started by clearing the reset with VPPH at the CNVss pin For the normal microprocessor mode set CNVss to L This control program is written in the boot ROM area when shipped from Mitsubishi Electric Therefore if the boot ROM area is rewritten in the parallel I O mode the standard serial O mode cannot be used Fig
137. 0016 26 One shot start flag 038216 62 Interrupt table register INTB 0000016 27 Trigger select flag 038316 63 User stack pointer USP 000016 28 Up down flag 038416 64 Interrupt stack pointer ISP 000016 29 Timer AO mode register 039616 65 Static base register SB 000016 30 Timer XO mode register 039716 66 Flag register FLG 000016 31 Timer X1 mode register 039816 32 Timer X2 mode register 039916 x Nothing is mapped to this bit Undefined The content of other registers and RAM is undefined when the microcomputer is reset The initial values must therefore be set Note This register is only exist in flash memory version Figure 1 13 Device s internal status after a reset is cleared 16 x xe sf Mitsubishi microcomputers ve M30201 Group Se SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Software Reset Software Reset Writing 1 to bit 3 of the processor mode register 0 address 000416 applies a software reset to the microcomputer A software reset has almost the same effect as a hardware reset The contents of internal RAM are preserved Figure 1 14 shows the processor mode register 0 and 1 Processor mode register 0 Note b7 b6 b5 b4 b3 b bi b0 Symbol Address When reset ONANI o JoJo o PMO 000416 XXXX00002 Reserved bit Must always be set to
138. 0016 Timer AO event trigger ar select bit 93 Input on TAOIN is selected Note TB1 overflow is selected TAOTGH TX2 overflow is selected TXO overflow is selected Timer XO event trigger Tree select bit Input on TXOINoUuT is selected Note TB1 overflow is selected TXOTGH TAO overflow is selected TX1 overflow is selected select bit Input on TX1INouT is selected Note TB1 overflow is selected TX1TGH TXO overflow is selected TX2 overflow is selected TX2TGL Timer X2 event trigger select bit Input on TX2INOuT is selected Note TB1 overflow is selected TX2TGH TX1 overflow is selected TAO overflow is selected TX1TGL Timer X1 event trigger 00 Note Set the corresponding port direction register to O input mode Clock prescaler reset flag b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset CPSRF 038116 0XXXXXXX2 Bitsymbol Bitname Foncion RW Nothing is assigned When write set 0 When read their contents are indeterminate 0 No effect 1 Prescaler is reset When read the value is 0 Clock prescaler reset flag Figure 2 4 3 Timer X related registers 2 211 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 2 4 2 Operation of Timer X timer mode In timer mode choose functions from those listed in Table 2 4 1 Operations of the circled items are described below Figure 2 4 4 shows the operation timing and Figure
139. 00716 1 Write enabled Enables writing to port P4 direction register address 03EA16 0 Write inhibited 1 Write enabled J S 2 Setting system clock control register i i 0 1 x 3 Setting the protect set to write inhibited state b Protect register Address 000A16 PRCR Enables writing to system clock control registers 0 and 1 addresses 000616 and 000716 0 Write inhibited Enables writing to port P4 direction register address 03EA16 0 Write inhibited 1 Write enabled 4 Clearing the protect set to write enabled state b0 Protect register Address 000A16 PRCR Enables writing to system clock control registers 0 and 1 addresses 000616 and 000716 0 Write inhibited 1 Write enabled Enables writing to port P4 direction register address 03EA16 1 Write enabled Changes in port P4 direction register Figure 2 1 2 Set up procedure for protect function 2 1 3 Precaution for Protect 1 The write enable bit of port P4 direction register goes to 0 when the next write instruction is executed after write enabled state is readied Make changes in input output immediately af ter the instruction that sets 1 in the write enable bit of port P4 direction register avoid causing an interrupt 161 X Ss Q RY Mitsubishi microcomputers OO M30201 Group X SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 Timer A 2 2 1 Over
140. 03A816 O fi 16 n 1 Note 1 fi f1 fs f32 fc e When external clock is selected bit 3 at addresses 03A016 1 fEXT 16 n 1 Note 1 Note 2 Transmission start condition e To start transmission the following requirements must be met Transmit enable bit bit 0 at addresses 03A516 O3AD16 1 Transmit buffer empty flag bit 1 at addresses 03A516 O3AD16 0 Reception start condi tion e To start reception the following requirements must be met Receive enable bit bit 2 at addresses 03A516 O3AD16 1 Start bit detection e When transmitting Transmit interrupt cause select bits bits 0 1 at address 03B016 0 Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed Transmit interrupt cause select bits bits 0 1 at address 03B016 1 Interrupts requested when data transmission from UARTI transfer register is completed e When receiving Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed e Overrun error Note 3 This error occurs when the next data is ready before contents of UARTi receive buffer register are read out e Framing error This error occurs when the number of stop bits set is not detected e Parity error This error occurs when if parity is enabled the number of 1 s in parity and character bits does not match the number o
141. 1 124 to 127 Note Software interrupt number 32 to Software interrupt number 63 128 to 131 to 252 to 255 Note Note Software interrupt Note Address relative to address in interrupt table register INTB 356 Cannot be masked by flag amp ORS oe x Interrupt Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 4 2 Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted What is described here does not apply to non maskable interrupts Enable or disable a non maskable interrupt using the interrupt enable flag I flag interrupt priority level selection bit or processor interrupt priority level IPL Whether an interrupt request is present or absent is indicated by the interrupt request bit The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt Also the interrupt enable flag flag and the IPL are located in the flag register FLG Table 4 2 1 shows the memory map of the interrupt control registers and Table 4 2 2 shows the interrupt control registers r 005D16 INTO interrupt control register INTOIC 005E16 INT1 interrupt control register INT11C Table 4 2 1 Memory map of the interrupt control registers 357 xX xe sf Mitsubishi microcomputers Sty M30201 Gr
142. 1 Start A D conversion 2 Conversion result is transferred to the A D register 8 bit resolution 28 AD cycles 8 bit resolution 28 AD cycles 3 A D conversion 10 bit resolution 33 AD cycles 10 bit resolution 33 AD cycles is complete Set to 1 by software we A D conversion 1 start flag g A D register i Result Result A D conversion Stop Convert Convert Convert Stop Note When ap frequency is less than 1MHz sample and hold function cannot be selected Conversion rate per analog input pin is 49 aD cycles for 8 bit resolution and 59 lt AD cycles for 10 bit resolution Figure 2 7 7 Operation timing of repeat mode 280 O aS Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter a Selecting Sample and hold b7 b0 olololi A D control register 2 Address 03D416 ADCON2 A D conversion method select bit 1 With sample and hold Must be fixed to 0 Ne J N Setting A D control register 0 and A D control register 1 bo b7 b7 A B000 A D control register 0 Address 03D616 A D control register 1 Address 03D716 LT ADCONO ADCONI Analog input pin select bit Note 2 Invalid in repeat mode b2 b1 b0 0 0 0 ANd is selected A D operation mode select bit 1 Note 1 AN1 is selected 0 Must always be 0 in repeat mode AN2 is selected AN3 is selected 8 10 bit mode select bit AN4 is selecte
143. 1 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Software Interrupts A software interrupt occurs when executing certain instructions Software interrupts are non maskable interrupts e Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction e Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag O flag set to 1 The following are instructions whose O flag changes by arithmetic ABS ADC ADCF ADD CMP DIV DIVU DIVX NEG RMPA SBB SHA SUB BRK interrupt A BRK interrupt occurs when executing the BRK instruction INT interrupt An INT interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the INT instruction Software interrupt numbers 0 through 31 are assigned to peripheral I O interrupts so executing the INT instruction allows executing the same interrupt routine that a peripheral I O interrupt does The stack pointer SP used for the INT interrupt is dependent on which software interrupt number is involved So far as software interrupt numbers 0 through 31 are concerned the microcomputer saves the stack pointer assignment flag U flag when it accepts an interrupt request If change the U flag to O and select the interrupt stack pointer ISP and then execute an interrupt sequence When returning from the interrupt routine the U flag is returned to the state i
144. 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 9 Method of A D Conversion 8 bit mode 1 In 8 bit mode 8 higher order bits of the 10 bit successive comparison register becomes A D conversion result Hence if compared to a result obtained by using an 8 bit A D converter the voltage compared is different by 3 VREF 2048 see what are underscored in Table 2 7 9 and differences in stepping points of output codes occur as shown in Figure 2 7 18 Table 2 7 9 The comparison voltage in 8 bit mode compared to 8 bit A D converter re 8 bit mode 8 bit A D converter n 0 Comparison voltage n 1 to 255 Vref Optimal conversion characteristics of 8 bit A D converter VREF 5 12 V Output code Result of A D conversion 02 01 00 10 30 Analog input voltage mV Optimal conversion characteristics in 8 bit mode VREF 5 12 V Output code Result of A D conversion 8 bit 10 bit 10bit mode 8bit mode 37 5 Analog input voltage mV Note Differences in stepping points of output code for analog input voltage Figure 2 7 18 The level conversion characteristics of 8 bit mode and 8 bit A D converter 291 amp 7 Q rs Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter Table 2 7 10 Variation of the successive comparison register and Vref while A D conversion is in progress 8 bit mode A D converter stopped V l VREF 1st comparison
145. 16 shows the an example of connecting the capaci tors to these pins Microcomputer C2 10 47 uF C2 20 47 uF C2 3100 pF for reference Use thick and shortest possible wiring to connect capacitors Figure 2 7 16 Use of capacitors to reduce noice 3 Set the direction register of the following ports to input the port corresponding to a pin to be used as an analog input pin and external trigger input pin 4 If using the A D converter with Vcc 2 7V to 4 0 V Use without fAD no frequency division for PAD Select without the Sample amp Hold feature Select 8 bit mode 5 Rewrite to analog input pin after changing A D operation mode The two cannot be set at the same time 6 When using the one shot or single sweep mode Confirm that A D conversion is complete before reading the A D register Note When A D conversion interrupt request bit is set it shows that A D conversion is completed 7 When using the repeat mode or repeat sweep mode 0 or 1 Use the undivided main clock as the internal CPU clock 288 N O P Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 8 Method of A D Conversion 10 bit mode 1 The A D converter compares the reference voltage Vref generated internally based on the contents of the successive comparison register with the analog input voltage VIN input from the analog input pin Each bit of the comp
146. 2 A XIN 4 XIN 8 e XIN 16 5 6 f XIN MHz Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figures 5 1 8 Characteristics of ICC f XIN Vcc 3V 378 xX Cy O RX Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics 5 2 Standard Characteristics of Pull Up Resistor Figure 5 2 1 shows an example of the standard characteristics of the pull up resistor 2 VI V Note Data described here are characteristic examples The data values are not guaranteed Figure 5 2 1 Example of the standard characteristics of the pull up resistor 379 N A Mitsubishi microcomputers FS S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics Flash memory version 5 3 Standard DC Characteristics Flash memory version The standard characteristics given in this section are examples of M30201F6FP The contents of these examples cannot be guaranteed For standardized values see Electric characteristics 5 3 1 Standard Ports Characteristics Figures 5 3 1 through 5 3 3 show the standard ports characteristics 380 O sf Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER VoH V Note Data described here are characteristic examples The data values are not guarantee
147. 2 Operation timing of PWM output mode 193 x A O S Mitsubishi microcomputers VO M30201 Group sy SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 3 Timer B 2 3 1 Overview The following is an overview for timer B a 16 bit timer 1 Mode Timer B operates in one of three modes a Timer mode The internal count source is counted e Operation in timer mode ceeeceececeeeeeneeeeeeeeeeeaaeeeeeeeecaaeeseeaeeecaaeeseeaaeesseeesssaaaessaneeessaaeeeeneees P198 b Event counter mode The number of pulses coming from outside and the number of the timer overflows are counted e Operation in event counter MOE ceeeececeeteeeeeeeeeeeeeeeeeeaeeeeeeeeecaaeeeeeneeecaeeeseaaeeseeeeetiaaeeenness P200 c Pulse period measurement pulse width measurement mode External pulse period or external pulse widths are measured If pulse period measurement mode is selected the periods of input pulses are continuously measured If pulse width measurement mode is selected widths of H level pulses and those of L level pulses are continuously measured e Operation in pulse period measurement MOE ceeeececeeesseeeeeeesseeeeeeessneeeeeesesneeeeesesseeeeeeees P202 e Operation in pulse width measurement MOE ccceeccceceessteeeeeeesseeeeeeeesteeeeeeesseeeeeeeseeeeeness P204 2 Count source An internal count source can be selected from f1 f8 f32 and fc32 f1 f8 and f32 are clocks obtained by dividing the CPU m
148. 2 Port bof ff Bit symbol Bit name Function RW hor or or 4 4 4 1J EGONOO CPU rewrite mode 0 CPU rewrite mode is invalid oio TE E a a select bit 1 CPU rewrite mode is valid a i Reserved bit This bit can not write The value if 1g Se a oa read turns out to be indeterminate 7 i FCono2 CPU rewrite mode 0 CPU rewrite mode is invalid i HM ig phe po Sessami monitor flag 1 CPU rewrite mode is valid O1 POUE Mtn Uateedees ata Reserved bit Must always be set to 0 03KO IOP beeen eee eee eee Reserved bit Must always be set to 1 O O Po Nothing is assigned In an attempt to write this bit write 0 The value T pe er ee if read turns out to be 0 TA eee nese ee eee e eee dee Reserved bit Must always be set to 0 o O Flash memory control register 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PEREKI ol 0 FCON1 03B516 XXXXXX002 Bit symbol Bit name Function Reserved bit Must always be set to 0 value if read turns out to be indeterminate Nothing is assigned In an attempt to write these bits write 0 The Figure BB 1 Flash memory control register Flash command register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset FCMD 03B616 0016 Function RW Writing of software command lt Software command name gt lt Command code gt Read command 0016 Program command 4016 x o Program verify command C01
149. 2 mode BCLK f Xin BCLK f Xin 2 CMo7 0 CMO6 0 CMo7 o CMo6 o Medium speed mode CM17 0 CM16 0 CM17 0 CM16 1 divided by 8 mode f BCLK f Xin 8 Medium speed mode Medium speed mode CM07 0 divided by 4 mode divided by 16 mode CMO6 1 BCLK f Xin 4 BCLK f Xin 16 CM07 0 CMO6 0 CM07 0 CMO6 0 CM17 1 CM16 0 CM17 1 CM16 1 CM04 O Main clock is oscillating CM04 1 Sub clock is stopped Medium speed mode High speed mode divided by 2 mode BCLK f XiN BCLK f Xin 2 CM07 0 CMO06 0 CM07 0 CMO6 0 CM17 0 CM16 0 CM17 0 CM16 1 CM06 0 Medium speed mode Medium speed mode Notes 1 3 divided by 4 mode divided by 16 mode BCLK f Xin 4 BCLK f Xin 16 CM07 0 CMO6 0 CM07 0 CMO6 0 CM17 1 CM16 0 CM17 1 CM16 1 Ne Note 1 Switch clock after oscillation of main clock is sufficiently stable Note 2 Switch clock after oscillation of sub clock is sufficiently stable Note 3 Change CMO06 after changing CM17 and CM16 Note 4 Transit in accordance with arrow S Figure 1 20 Clock transition 27 O S Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Protection Protection The pro
150. 2048 V VREF v ng 1 VREF VREF 4 2nd comparison 010 0 ta 2048 V VREF n 0 3 st comparison result et VREF VREF _ VREF V 3rd comparison ns 10 0 0100 ty 8 2048 A ond comparison result ns 0 VREF _ VREF IV 8th i ng ns nej n5 n4 n3 MEE comparison 256 2048 v complete This data transfers to bit 0 to bit 7 of A D register Result of A D conversion Theoretical A D conversion characteristic of general 8 bit A D converter Theoretical A D conversion characteristic in the 8 bit mode VREF x 4 VREF y 954 VREF y 255 VREF 256 256 256 Analog input voltage Figure 2 7 19 Theoretical A D conversion characteristics 8 bit mode 292 xX Cy O s Mitsubishi microcomputers SX M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 10 Absolute Accuracy and Differential Non Linearity Error e Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A D conversion characteristics and actual A D conversion result When measuring absolute accuracy the voltage at the middle point of the width of analog input voltage 1 LSB width that can meet the expectation of outputting an equal code based on the theoretical A D conversion characteristics is used as an ana log input voltage For
151. 3 2us fc32 976 56us Note Set the corresponding port direction register to 1 output mode Clearing timer AO interrupt request bit Refer to Precaution for Timer A one shot timer mode b7 bo KXKKXol TT Timer AO interrupt control register Address 005516 TAOIC Interrupt request bit Res Setting one shot timer s time b15 b8 b7 bO b7 b0 DOOS T E Timer AO register Address 038716 038616 TAO _ Can be set to 000116 to FFFF16 NX Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 XXKKKKEX Clock prescaler reset flag Address 0381 16 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O b7 b0 Count start flag Address 038016 TABSR Timer AO count start flag Setting one shot start flag b7 bo KKK LLL 1 One shot start flag Address 038216 ONSF L Timer AO one shot start flag N Setting count start flag l Start count Figure 2 2 21 Set up procedure of one shot mode 183 amp r EPR 4 Mitsubishi ICroco puters os Sy M30201 Group ae A SINGLE CHIP 16 BIT CMOS MICROCOMPUTER imer 2 2 10 Operation of Timer A one shot timer mode external trigger selected In one shot timer mode choose functions from those
152. 30 to P35 P40 to P4s current P50 to P54 P60 to P67 P70 P71 lot avg LOW average output P10 to P17 HIGHPOWER cals LOWPOWER 5 0 f XIN Without Mask ROM version Vec 4 0V to 5 5V 10 Main clock input it oscillation bi Vec 2 7V to 4 0V 5 x Vcc 10 000 frequency Flash memory version Vcc 4 0V to 5 5V 10 With wait Mask ROM version Vec 4 0V to 5 5V 10 Vcc 2 7V to 4 0V 2 31 x Vcc 0 760 Flash memory version Vec 4 0V to 5 5V 10 Subclock oscillation frequency 50 Note 1 Unless otherwise noted Vcc 2 7V to 5 5V Vss OV Ta 20 to 85 C Extended operating temperature version 40 to 85 C Flash version Vcc 4 0V to 5 5V Vss OV Ta 20 to 85 C Extended operating temperature version 40 to 85 C Note 2 Flash version Vcc 4 0V to 5 5V Note 3 The average output current is an average value measured over 100ms Note 4 Keep output current as follows The sum of port P3 and P4 IOL peak is under 40 mA The sum of port P1 IOL peak is under 60 mA The sum of port P1 P3 and P4 IOH peak is under 40 mA The sum of port PO P5 P6 and P7 IOL peak is under 80 mA The sum of port PO P5 P6 and P7 IOH peak is under 80 mA Highest operation frequency MHz a Highest operation frequency MHz Main clock input oscillation frequency Without wait 10 0 5 x Vcc 10 000MHz 10 0 231 7 0 3 5 2 7 4 0 5
153. 39016 Indeterminate b15 039316 039216 Indeterminate Function e Timer mode 000016 to FFFF16 Counts the timer s period e Event counter mode 000016 to FFFF16 Counts external pulses input or a timer overflow Note1 Read and write data in 16 bit units Count start flag b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset TABSR 038016 000X00002 1 1 1 1 1 1 TAOS Timer AO count start flag 0 Stops counting TXOS Timer XO count start flag 1 Starts counting TX1S Timer X1 count start flag TX2S Timer X2 count start flag Nothing is assigned When write set 0 When read their contents are indeterminate TBOS Timer BO count start flag 0 Stops counting TB1IS Timer B1 count start flag Tastartsicounting CDCS Clock devided count start flag Clock prescaler reset flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset CPSRF 038116 OXXXXXXX2 Bit symbol Nothing is assigned When write set 0 When read their contents are indeterminate Clock prescaler reset flag 0 No effect PRS PS g 1 Prescaler is reset When read the value is O Figure 2 3 3 Timer B related registers 2 197 S O S Mitsubishi microcomputers ve M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 3 2 Operation of Timer B timer mode In timer mode choose functions from those listed in Table 2 3 1 Operations of the circled items are described below Figure 2 3 4 shows the operation timing and
154. 3E416 _Port P2 P2 Reserved 03A516 UARTO transmit receive control register 1 U0C1 03E516 Port P3 P3 03A616 03E616 _Port P2 direction register PD2 Reserved DATE UARTO receive buffer register UORB 03E716 Port P3 direction register PD3 03A816 UART1 transmit receive mode register U1MR 03E816 _Port P4 P4 03A916 UART1 bit rate generator U1BRG 03E916 _Port P5 P5 03AA16 03EA16 _Port P4 direction register PD4 03AB1e UART1 transmit buffer register U1TB 03E81s Port P5 direction register PD5 03AC16 UART1 transmit receive control register 0 U1C0 03ECi6 Port P6 P6 03AD16 UART1 transmit receive control register 1 U1C1 03ED16 _Port P7 P7 03AE16 F 03EE1s Port P6 direction register PD6 OSAFi6 UART1 receive buffer register U1RB 03EF16 Port P7 direction register PD7 03B016 UART transmit receive control register 2 UCON 03F016 03B116 03F 116 03B216 03F216 03B316 03F316 03B416 Flash memory control register 0 FCONO Note 03F416 03B516 Flash memory control register 1 FCON1 Note O3F516 03B616 Flash command register FCMD Note 03F616 03B716 O3F716 03B816 O3F 816 03B916 O3F916 03BA16 03FA16 03BB16 03FB16 03BC16 03FC16 _Pull up control register 0 PURO 03BD16 03FD16 _Pull up control register 1 PUR1 03BE16 03FE16 Port P1 drive control register DRR 03BF16 03FF16
155. 5 Power supply voltage V Main clock no division Main clock input oscillation frequency With wait x Vcc 0 760MHz y N fe 2 7 4 0 5 5 Power supply voltage V Main clock no division 113 we g Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 5V Vcc 5V Table 1 39 Electrical characteristics Note HIGH output voltage Parameter POo to P07 P10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 Standard Measuring condition loH 5 mA Min Typ Max HIGH output voltage P0o to P07 P10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 lOH 200 pA HIGH output voltage HIGHPOWER LOWPOWER XOUT loH 1 mA loH 0 5 mA HIGH output voltage HIGHPOWER LOWPOWER XCOUT No load No load LOW output voltage POo to P07 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 loL 5 mA LOW output voltage POo to P07 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 loL 200 pA LOW output voltage HIGHPOWER LOWPOWER Pio to P17 loL 15mA L 5 mA LOW output voltage HIGHPOWER L 200 uA P1o to P17 LOWPOWER L 200 pA LOW output voltage HIGHPOWER LOWPOWER XOUT loH 1mA loH 0 5 mA LOW output voltage HIGHPOWER LOWPOWER XOUT No load No load Hysteresis TAOIN TXOINOUT
156. 5 5V f XIN 7MHz with software one wait mask ROM version 4 0 to 5 5V f XIN 10MHZz flash memory version MUS MUPUS mer 9 internal and 3 external interrupt sources 4 software including key input interrupt e Multifunction 16 bit timer 0 Timer A x 1 timer B x 2 timer X x 3 e Clock output Seal W O vesdessasccdunivsvatdinsessnaccaecdsaavtvacstes 1 channel for UART or clock synchronous 1 for UART A D converter 2 ceeeceeeteeeesteeeeneeteees 10 bits X 8 channels Expandable up to 13 channels e Watchdog timer 1 line e Programmable I O sssi 43 lines LED drive ports sssiirrsirivnsieriniveeiines 8 ports e Clock generating Circuit 0 eee 2 built in clock generation circuits built in feedback resistor and external ceramic or quartz oscillator Applications Home appliances Audio office equipment Automobiles Specifications written in this manual are believed to be accurate but are not guaranteed to be entirely free of error Specifications in this manual may be changed for functional or performance improvements Please make sure your manual is the latest edition Central Processing Unit CPU sasse 12 IMET uyinni atte essen ae 37 Beee A EET 15 Senak O erranera ee aa 64 Clock Generating Circuit eeeeeeeeeee 19 A D Converter ssssssesssesssesssssssrrssrrrserrserrnens 78 PrOtEGUON ocisch sacs cccdsscciatccnnissatecdbsctiteeesaes tutes 26 Programmable I O Ports e ee
157. 5 b8 b7 b0 b7 b0 Clock prescaler reset flag Address 038116 LEOTTA Geshe i Rrescaler is reset TOTT Count start flag Address 038016 TBO start counting b7 Timer BO interrupt control register Address 005A16 TBOIC TBO interrupt priority level b7 b0 INTO interrupt control register Address 005D16 DOr lolol intoic te INTO interrupt priority level Interrupt priority level IPL 0 Interrupt enable flag I 0 Setting interrupt except clearing wait mode Interrupt control register KUPIC Address 004D16 Address 004E16 Address 005116 005316 Address 005216 005416 Address 005516 2 Address 005616 to 005816 Address 005A16 005B16 b7 b0 0 0 0 oun you oko weno 90 Interrupt priority level select bit b2 bi b0 000 Interrupt disabled Continued to the next page Figure 3 7 2 Set up procedure of controlling power using wait mode 1 347 xX Se O s Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications Continued from the previous page Canceling protect b7 gt Protect register Address 000A16 Enables writing to system clock control registers 0 and 1 address 000616 and 000716 1 write enabled ot x Switching system clock b7 bo Syst lock control register 0 Add 0006 ry TT TTT oo control register ress 16 System clock
158. 50 pA HIGH output voltage HIGHPOWER LOWPOWER XCOUT No load No load LOW output voltage POo to P07 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 loL 1 mA LOW output voltage HIGHPOWER LOWPOWER P1o to P17 loL 3 mA loL 1 mA LOW output voltage HIGHPOWER LOWPOWER loH 0 1 mA loH 50 pA LOW output voltage HIGHPOWER LOWPOWER XOUT No load No load Hysteresis TAOIN TXOINOUT TX1INOUT SO TX2INOUT TBOIN TB11N INTo INT1 CLKo Hysteresis RESET HIGH input current POo to P07 P10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 XIN RESET CNVss LOW input current P0o to P07 P10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 XiIN RESET CNVss RPULLUP Pull up resistor POo to P07 P10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 RXIN Feedback resistor XIN RXIN Feedback resistor XIN VRAM RAM retention voltage When clock is stopped Power supply current f XIN 7MHz Square wave no division f XCIN 32kHz Square wave f XCIN 32kHz With wait Oscillation capacity HIGH Note 2 f XCIN 32kHz With wait Oscillation capacity LOW Note 2 Ta 25C when clock is stopped Ta 85C when clock is stopped Note 1 Unless otherwise noted Vcc 3V Vss OV at Ta 25 C f XIN 7MHz with wait Note 2 With one
159. 6 0 CLKO input level H CLKO polarity select bit bit 6 at address 03A416 1 CLKO input level L Interrupt request e When transmitting generation timing Transmit interrupt cause select bit bit O at address 03B016 0 Interrupts re quested when data transfer from UARTO transfer buffer register to UARTO transmit register is completed Transmit interrupt cause select bit bit O at address 03B016 1 Interrupts re quested when data transmission from UARTO transfer register is completed e When receiving Interrupts requested when data transfer from UARTO receive register to UARTO receive buffer register is completed Error detection e Overrun error Note 2 This error occurs when the next data is ready before contents of UARTO receive buffer register are read out Select function e CLK polarity selection Whether transmit data is output input at the rising edge or falling edge of the trans fer clock can be selected e LSB first MSB first selection Whether transmission reception begins with bit 0 or bit 7 can be selected e Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register e Transfer clock output from multiple pins selection UARTO transfer clock can be chosen by software to be output from one of the two pins set Note 1 n denotes the value 0016 to FF 16 that is set to the UART bit rate generator Note 2
160. 6 TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag Start count Figure 2 4 13 Set up procedure of event counter mode free run type selected 221 O Ss Mitsubishi microcomputers SF of M30201 Group ro SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 7 Operation of Timer X one shot timer mode In one shot timer mode choose functions from those listed in Table 2 4 6 Operations of the circled items are described below Figure 2 4 14 shows the operation timing and Figure 2 4 15 shows the set up procedure Table 2 4 6 Choosed functions Count source Internal count source f1 fs f32 fc32 Pulse output function No pulses output Pulses output Count start condition External trigger input falling edge of input signal to the TXiINOUT pin External trigger input rising edge of input signal to the TXiINOUT pin Timer overflow TB1 TX0 TXi overflow Writing 1 to the one shot start flag Operation 1 Setting the one shot start flag to 1 with the count start flag set to 1 causes the counter to perform a down count on the count source At this time the TXiINOUT pin outputs an H level 2 The instant the value of the counter becomes 000016 the TXiINOUT pin outputs an L level and the counter reloads the content of the reload register and stops counting At this time the timer Xi interrupt request bit goes t
161. 6 45 43 P51 RxDo ANs1 lt gt lt gt P67 AN7 P50 TxDo AN50 lt gt 2 N C lt gt P00 Klo lt gt P0i KIt gt P02 Kl2 M30201MX XXXFP lt gt POKE M30201MXT XXXFP lt gt POK M30201F6FP lt gt POsiKis O M30201F6TFP lt gt Posikls lt gt P07 KI7 lt gt P10 LEDo lt gt P11 LED1 gt P12 LED2 lt gt P13 LEDs3 P45 TX2INOUT lt gt P44 INT1 TX1INOUT lt gt P43 INTo TXOINouT lt gt 4 O 15 16 17 P35 lt p gt P34 lt p gt P42 RxD1 lt gt P41 TAQOUT lt gt P40 TAOIN TxD1 lt gt N C Package 56P6S A Figure 1 2 Pin configuration for the M30201 group QFP product top view N g Mitsubishi microcomputers amp S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Description Block Diagram Figure 1 3 is a block diagram of the M30201 group 5 a 2 O ports A D converter System clock generator 10 bits x 8 channels XIN XOUT Expandable up to 13 channels XCIN XCOUT Timer TAO Timer TBO 16 bits Timer TB1 16 bits UART clock synchronous SI O Timer TXO 16 bits 8 bits x 1 channel Timer TX1 16 bits i UART Timer TX2 16 bits 8 bits x 1 channel M16C 60 series16 bit CPU core Registers Program counter Watchdog timer 15 bits ROH Vector table INTB Stack pointer Multiplier C s C ae Note 1 ROM size depends on MCU type Note 2 RAM size depends on MCU type Figure 1 3 Block
162. 6 TXiMR i 0 to 2 Selection of timer mode Pulse output function select bit 0 Pulse is not output TXiINOUT pin is a normal port pin Gate function select bit b4 b3 00 01 Gate function not available TXiINOUT pin is a normal port pin 0 Must always be 0 in timer mode cial source select bit Count Count source period 00 f Source f XIN 10MHz f XcIN 32 768kKHz 01 fe 100ns 10 f32 800ns 1 1 fc32 i 3 2us 976 56us Setting divide ratio Timer XO register Address 038916 038916 TXO Timer X1 register Address 038B16 038A16 TX1 Timer X2 register Address 038D16 038C16 TX2 E Can be set to 000016 to FFFF16 S Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 bO Clock prescaler reset flag Address 038116 mo CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O Setting count start flag b7 b0 Count start flag Address 038016 TABSR Timer XO count start flag Timer X1 count start flag Timer X2 count start flag Start count Figure 2 4 5 Set up procedure of timer mode 213 O s Mitsubishi microcomputers ve M30201 Group s SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 2 4 3 Operation of Timer X timer mode gate funct
163. 6 03CC16 A D register 7 Address 03CF16 03CE16 Eight low order bits of A D conversion result During 10 bit mode Two high order bits of A D conversion result During 8 bit mode When read the content is indeterminate N a Setting A D conversion start flag b7 bo 0 A D control register 0 Address 03D616 A D conversion start flag C 0 A D conversion disabled Stop A D conversion Figure 2 7 12 Set up procedure of repeat sweep 0 mode 285 A D Converter Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 2 7 6 Operation of A D Converter in repeat sweep mode 1 In repeat sweep 1 mode choose functions from those listed in Table 2 7 6 Operations of the circled items are described below Figure 2 7 13 shows ANi pin s sweep sequence Figure 2 7 14 shows timing chart and Figure 2 7 15 shows the set up procedure Table 2 7 6 Choosed functions Operation clock fap Divided by 4 fab divided by 2 fab fAD Resolution 8 bit 10 bit Analog input pin ANo 1 pins ANo to AN1 2 pins ANo to AN2 3 pins ANo to ANs 4 pins Note Sample amp Hold Not activated Activated Note When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins AN50 to AN54 Operation 1 Setting the A D conversion start flag to 1 causes the A D converter to start the conversion on voltage
164. 6 i Erase command 2016 2016 Erase verify command A016 Reset command FF16 FFe Figure BB 2 Flash command register 128 N amp amp Mitsubishi microcomputers SS M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CPU Rewrite Mode Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I O mode beforehand If the control program is written into the boot ROM area the standard serial I O mode becomes unusable See Figure AA 3 for details about the boot ROM area Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSss pin low Vss In this case the CPU starts operating using the control program in the user ROM area When the microcomputer is reset by pulling the P52 pin high Vcc the CNVss pinshigh VPPH the CPU starts operating using the control program in the boot ROM area This mode is called the boot mode The control program in the boot ROM area can also be used to rewrite the user ROM area CPU rewrite mode operation procedure The internal flash memory can be operated on to program read verify or erase it while being placed on board by writing commands from the CPU to the flash memory control register addresses 03B416 03B516 and flash command register address 03B616 Note that when in CPU rewrite mode the boot ROM area cannot be accessed for program read verify or
165. 60 shows the timer Xi mode register in timer mode Table 1 21 Specifications of timer mode Item Specification Count source f1 f8 132 fC32 Count operation e Down count e When the timer underflows it reloads the reload register contents before continuing counting Divide ratio 1 n 1 n Set value Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing When the timer underflows TXiINOUT pin function Programmable I O port gate input or pulse output Read from timer Count value can be read out by reading timer Xi register Write to timer e When counting stopped When a value is written to timer Xi register it is written to both reload register and counter e When counting in progress When a value is written to timer Xi register it is written to only reload register Transferred to counter at next reload time Select function e Gate function Counting can be started and stopped by the TXiINOUT pin s input signal e Pulse output function Each time the timer underflows the TXiINOUT pin s polarity is reversed Timer Xi mode register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset fol Jofo TXIMR i 0 to 2 039716 to 039916 0016 Bil syimbal Rw TMODO Operation mode b1bO TMOD1 select bit 0 0 Timer mode MRO Pulse output function 0 Pulse is not output select bi
166. 92 to 95 Note Timer X1 Software interrupt number 24 96 to 99 Note Timer X2 Software interrupt number 25 100 to 103 Note Software interrupt number 26 104 to 107 Note Timer BO Software interrupt number 27 108 to 111 Note Timer B1 Software interrupt number 28 112 to 115 Note Software interrupt number 29 116 to 119 Note INTO Software interrupt number 30 120 to 123 Note INT1 Software interrupt number 31 124 to 127 Note Software interrupt number 32 to Software interrupt number 63 128 to 131 to 252 to 255 Note Note Software interrupt Note Address relative to address in interrupt table register INTB 33 Cannot be masked by flag x Q lt Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted What is described here does not apply to non maskable interrupts Enable or disable a maskable interrupt using the interrupt enable flag I flag interrupt priority level select bit and processor interrupt priority level IPL Whether an interrupt request is present or absent is indi cated by the interrupt request bit The
167. A SUB BRK interrupt A BRK interrupt occurs when executing the BRK instruction INT interrupt An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing the INT instruction Software interrupt numbers 0 through 31 are assigned to peripheral I O interrupts so executing the INT instruction allows executing the same interrupt routine that a peripheral I O interrupt does The stack pointer SP used for the INT interrupt is dependent on which software interrupt number is involved So far as software interrupt numbers 0 through 31 are concerned the microcomputer saves the stack pointer assignment flag U flag when it accepts an interrupt request If change the U flag to 0 and select the interrupt stack pointer ISP and then execute an interrupt sequence When returning from the interrupt routine the U flag is returned to the state it was before the acceptance of interrupt re quest So far as software numbers 32 through 63 are concerned the stack pointer does not make a shift 353 xX Cy xe Mitsubishi microcomputers DO M30201 Group x SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 1 3 Hardware Interrupts Hardware interrupts are classified into two types special interrupts and peripheral I O interrupts 1 Special interrupts Special interrupts are non maskable interrupts Reset Reset occurs if an L is input to the RESET pin e DBC interrupt This interrupt is excl
168. After the interrupt sequence is completed the processor resumes executing instructions from the first address of the interrupt routine Figure 2 11 2 shows the sequence of returning from stop mode Writing 1 to CM10 all clock stop control bit Operated by divided by 8 mode BCLK Vitae indeterminate Y SP2 Y SP4 vee vece Address bus i i 00000 A Indeterminate SP 2 SP 4 vec vec 2 f on a amp SO i Data bus oe Indeterminate contents contents contents contents w RD Indeterminate J Indeterminate J WR gt Stop mode Oscillation start up Interrupt sequence approximately 20 cycle 16u sec Single chip mode f Xin 10MHz Figure 2 11 2 Sequence of returning from stop mode 6 Registers related to power control Figure 2 11 3 shows the memory map of power control related registers and Figure 2 11 4 shows power control related registers 313 xX N O lt Mitsubishi microcomputers NO M30201 Group D SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Power Control 000616 System clock control register 0 CM0 000716 System clock control register 1 CM1 Figure 2 11 3 Memory map of power control related registers System clock control register 0 Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol CMO Address 000616 When reset 4816 Bit symbol Bit name CM00 Function b1 b0 0 0 I O port P54 0 1 fc output 1 0 f8 output 1 Clock divide counter out
169. B first When busy either during transmission or reception or while executing an erase operation or program the P53 BUSY pin is H level Accordingly do not start the next transmission until the P53 BUSY pin is L level Also data in memory and the status register can be read after inputting a software command It is pos sible to check flash memory operating status or whether a program or erase operation ended success fully or in error by reading the status register Software commands and the status register are explained here following 147 N O amp Mitsubishi microcomputers so M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode Software Commands Table DD 1 lists software commands In the standard serial I O mode erase operations programs and reading are controlled by transferring software commands via the RxD pin Software commands are explained here below Table DD 1 Software commands Standard serial I O mode Control command 2nd byte 3rd byte 4th byte 5th byte 6th byte ee in y aa not verificate all Pageread Address Address Data Not j FFis middle high i acceptable 2 Page program 4116 Address Address Data Data Data Data input Not middle high input input input to 259th acceptable byte N 3 Erase all unlocked blocks A746 owl M 4 Read status regist
170. BiMR i 0 1 039B16 to 039C16 00XX00002 Bitsymbol 7 TMODO Operation mode select bit ee ent i p Event counter mode TMOD1 MRO Count polarity select pee bit Note 1 y 0 0 Counts external signal s falling edges Counts external signal s MR1 rising edges Counts external signal s falling and rising edges Inhibited Nothing is assigned When write set 0 When read their contents are indeterminate Invalid in event counter mode This bit can neither be set nor reset When read in event counter mode its content is indeterminate MR3 TCKO Invalid in event counter mode Can be 0 or 1 TCK1 Event clock select 0 Input from TBiIN pin Note 2 1 TBj overflow j 1 wheni 0 j 0 wheni 1 Note 1 Valid only when input from the TBIIN pin is selected as the event clock If timer s overflow is selected this bit can be 0 or 1 Note 2 Set the corresponding port direction register to O input mode Figure 1 52 Timer Bi mode register in event counter mode 63 Q V Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 3 Pulse period pulse width measurement mode In this mode the timer measures the pulse period or pulse width of an external signal See Table 1 20 Figure 1 53 shows the timer Bi mode register in pulse period pulse width measurement mode Figure 1 54 shows the operation timing when measuring a pulse period
171. CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 5 Repeat sweep mode 1 In repeat sweep mode 1 all pins are used for A D conversion with emphasis on the pin or pins selected using the A D sweep pin select bit See Table 1 35 Figure 1 89 shows the A D control register in repeat sweep mode Table 1 35 Repeat sweep mode 1 specifications Function All pins perform repeat sweep A D conversion with emphasis on the pin or pins selected by the A D sweep pin select bit Example ANo selected ANo AN1 ANo AN2 ANo AN3 etc Start condition Writing 1 to A D conversion start flag Stop condition Writing 0 to A D conversion start flag Interrupt request generation timing None generated Input pin ANo 1 pin ANo and AN1 2 pins ANo to AN2 3 pins ANo to AN8 4 pins Note Reading of result of A D converter Read A D register corresponding to selected pin at any time Note AN50 to AN54 can be used in the same way as for ANo to AN4 A D control register 0 Note b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset ADCONO 03D616 00000XXxX2 Bit symbol Bit name Function Analog input pin select bit Invalid in repeat sweep mode 1 A D operation mode select bit 0 Set this bit to 0 b4 b3 1 1 Repeat sweep mode 1 A D conversion start flag A D conversion disabled A D conversion started Frequency select bit 0 faD 4 is selected faD 2 is selected Note
172. CM17 1 CM16 0 Medium speed mode divided by 16 mode BCLK f Xin 16 CM07 0 CMO6 0 CM17 1 CM16 1 Medium speed mode divided by 8 mode BCLK f Xin 8 CM07 0 CMO6 1 CM07 0 Note 1 3 CM07 1 Note 2 CM06 0 Notes 1 3 Figure 2 11 1 State transition diagram of power control mode Main clock is oscillating CM04 1 Sub clock is stopped Va High speed mode BCLK f Xin CMO7 0 CMO6 CM17 0 CM16 Medium speed mode divided by 2 mode BCLK f Xin 2 CM07 0 CMO6 0 CM17 0 CM16 1 g 9 S Medium speed mode divided by 4 mode Medium speed mode divided by 16 mode CM07 CM06 CM04 BCLK f Xin 4 CMO7 0 CMO06 0 CM17 1 CM16 0 BCLK f Xin 16 CMO07 0 CMO6 0 CM17 1 CM16 1 K J Note 1 Main clock is oscillating Sub clock is oscillating Low speed mode BCLK f Xcin CMO07 1 CMO05 O CMO05 1 Main clock is stopped Sub clock is oscillating Low power dissipation mode CM07 1 Note 2 CMO5 1 Note 1 g 0 Note 3 q Note 1 Switch clock after oscillation of main clock is sufficiently stable Note 2 Switch clock after oscillation of sub
173. D cycles 33 saD cycles 33 saD cycles 33 aD cycles Hl ni Cleared to 0 by software conversion start flag i Set to 1 by software A D aj Pet A D register 0 y Result A D register 1 y Result A D register 2 y Result Note When AD frequency is less than 1MHz sample and hold function cannot be selected Conversion rate per analog input pin is 49 AD cycles for 8 bit resolution and 59 AD cycles for 10 bit resolution Figure 2 7 14 Operation timing of repeat sweep 1 mode 286 s Mitsubishi microcomputers Sty M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter we Selecting Sample and hold b7 b0 0 oli A D control register 2 Address 03D416 EO i ADcon2 L A D conversion method select bit 1 With sample and hold Must be fixed to 0 wh Setting A D control register 0 and A D control register 1 b7 bO b7 bo A D control register 0 Address 03D616 A D control register 1 Address 03D716 ADCONO ADCON1 Invalid in repeat sweep mode 1 A D sweep pin select bit Note 2 b1 bo 00 ANo 1 pins 0 1 ANo AN1 2 pins r 1 0 ANo to AN2 3 pins Must be fixed to 0 1 1 ANo to AN3 4 pins
174. Figure 1 55 shows the operation timing when measuring a pulse width Table 1 20 Timer specifications in pulse period pulse width measurement mode Count source f1 fa 32 fc32 Count operation e Up count e Counter value 000016 is transferred to reload register at measurement pulse s effective edge and the timer continues counting Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing When measurement pulse s effective edge is input Note 1 When an overflow occurs Simultaneously the timer Bi overflow flag changes to 1 The timer Bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer Bi mode register TBIIN pin function Measurement pulse input Read from timer When timer Bi register is read it indicates the reload register s content measurement result Note 2 Write to timer Cannot be written to Note 1 An interrupt request is not generated when the first effective edge is input after the timer has started counting Note 2 The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer Timer Bi mode register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset Aod TBIMR i 0 1 039B16 039C16 00XX00002 SISA T Function TMODO bibo ToDo Operation mode 1 0 Pulse period pulse width
175. Figure 2 3 5 shows the set up procedure Table 2 3 1 Choosed functions Count source Internal count source f1 fs f32 fc32 Operation 1 Setting the count start flag to 1 causes the counter to perform a down count on the count source 2 If an underflow occurs the content of the reload register is reloaded and the counter contin ues counting At this time the timer Bi interrupt request bit goes to 1 3 Setting the count start flag to O causes the counter to hold its value and to stop n reload register content 1 Start count 2 Underflow aa Start count again gan x ai a 2 fo is lt 2 z 3 O O Time a i Cleared to 0 by Set to 1 by software Set to 1 by software software Gountstartlag PC L_ J Cleared to 0 when interrupt request is accepted or cleared by software Timer Bi interrupt 1 ie request bit g Figure 2 3 4 Operation timing of timer mode 198 x N O aS Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B Selecting timer mode and functions b7 b0 f F i i Timer Bi mode register i 0 1 Address 039B16 039C16 XI o 0 TBiMR ico to 2 L Selection of timer mode Invalid in timer mode Can be 0 or 1 Fixed to 0 in timer mode i roe source Serene i Count Count source period 00 f1 SOUICE f X
176. Group e SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 11 Operation of Timer X pulse width modulation mode 8 bit PWM mode selected In pulse width modulation mode choose functions from those listed in Table 2 4 10 Operations of the circled items are described below Figure 2 4 22 shows the operation timing and Figure 2 4 22 shows the set up procedure Table 2 4 10 Choosed functions Count source Internal count source f1 fs f32 fc32 PWM mode 16 bit PWM 8 bit PWM Count start condition Timer overflow TB1 TAO TXi overflow Operation 1 Selected timer overflow is generated with the count start flag set to 1 the counter performs a down count on the count source Also the TXiINOUT pin outputs an H level 2 The TXiINOUT pin output level changes from H to L when a set time period elapses At this time the timer Xi interrupt request bit goes to 1 3 The counter reloads the content of the reload register every time PWM pulses are output for one cycle and continues counting 4 Setting the count start flag to O causes the counter to hold its value and to stop Also the TXiOUT pin outputs an L level Note e PWM pulse cycle is m 1 x 28 1 fi whereas H level duration is n x m 1 fi However when 0016 is set for the significant 8 bits of the timer AO register the PWM output is L level for the entire period and an interrupt request
177. H pulse width tw TAL TAO input LOW pulse width Table 1 62 Timer A input external trigger input in one shot timer mode Standard Parameter Min Max TAOIN input cycle time TAOIN input HIGH pulse width TAOIN input LOW pulse width Table 1 63 Timer A input external trigger input in pulse width modulation mode qe tw TAH TAOIN input HIGH pulse width 150 tw TAL TAOIN input LOW pulse width 150 Table 1 64 Timer A input up down input in event counter mode Standard Parameter Min Max tc UP TAOouTt input cycle time tw UPH TAOouT input HIGH pulse width tw UPL TAOouT input LOW pulse width tsu UP TIN TAOOouT input setup time th TIN UP TAOouTt input hold time 122 O S Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 3V Vcc 3V Timing requirements referenced to Vcc 3V Vss OV at Ta 25 C unless otherwise specified Table 1 65 Timer B input counter input in event counter mode Standard i Max Parameter tc TB TBiIN input cycle time counted on one edge tw TBH TBiIN input HIGH pulse width counted on one edge tw TBL TBiIN input LOW pulse width counted on one edge te TB TBiiN input cycle time counted on both edges tw TBH TBiIN input HIGH pulse width counted on both edges tw TBL TBiin input LOW pulse width count
178. IN 10MHz f Xc n 32 768kHz 01 f8 100ns 10 f32 800ns 11 fc32 3 2us 976 56us Setting divide ratio b15 b8 b7 Doo O OE Timer BO register Address 039116 039016 TBO Timer B1 register Address 039316 039216 TB1 Oo Can be set to 000016 to FFFF16 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O Setting count start flag b7 bO Count start flag Address 038016 TABSR Timer BO count start flag Timer B1 count start flag Start count Figure 2 3 5 Set up procedure of timer mode 199 O Mitsubishi microcomputers SS M30201 Group sy SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 3 3 Operation of Timer B event counter mode In event counter mode choose functions from those listed in Table 2 3 2 Operations of the circled items are described below Figure 2 3 6 shows the operation timing and Figure 2 3 7 shows the set up procedure Table 2 3 2 Choosed functions Count source Input signal to the TBiIN pin counting falling edges Input signal to the TBiIN pin counting rising edges Input signal to the TBiIN pin counting rising edges
179. Input pins to timer B 8 Registers related to timer B Figure 2 3 1 shows the memory map of timer B related registers Figures 2 3 2 and 2 3 3 show timer B related registers 005A16 Timer BO interrupt control register TBOIC 005B16 Timer B1 interrupt control register TB1IC RY 038016 Count start flag TABSR 038116 Clock prescaler reset flag CPSRF 038216 One shot start flag ONSF 038316 Trigger select register TRGSR 038416 Up down flag UDF 039016 039116 039216 039316 Timer BO TBO Timer B1 TB1 wy 039B16 Timer BO mode register TBOMR 039C16 Timer B1 mode register TB1MR Figure 2 3 1 Memory map of timer B related registers 195 O Mitsubishi microcomputers VO M30201 Group v SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer Bi mode register Symbol Address When reset 2C De Do DA D E TBiMR i 0 1 039B16 039C16 00XX00002 Bit symbol TMODO Operation mode select bit Timer mode Event counter mode Pulse period pulse width measurement mode Inhibited OD1 Function varies with each operation mode MR1 MR2 MR3 TCKO Count source select bit TCK1 Function varies with each operation mode Note 1 Timer BO Note 2 Timer B1 Figure 2 3 2 Timer B related registers 1 196 x N O aS Mitsubishi microcomputers SX ef M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B Timer Bi register Note Address When reset 039116 0
180. MICROCOMPUTER Timer A Timer A Figure 1 37 shows the block diagram of timer A Figures 1 38 to 1 40 show the timer A related registers Use the timer AO mode register bits 0 and 1 to choose the desired mode Timer A has the four operation modes listed as follows e Timer mode The timer counts an internal count source e Event counter mode The timer counts pulses from an external source or a timer over flow One shot timer mode The timer stops counting when the count reaches 000016 e Pulse width modulation PWM mode The timer outputs pulses of a given width Data bus high order T Clock source selection oTi Data bus low order hie fi o High order f8 o y 8 bits f32 O e Timer gate function e Event counter Counter 16 Clock selection Up count down count Count start flag Always down count except in event counter mode TB1 overflow _ O Down count O External TXO overflow ___o0 trigger Up down flag O O TX2 overflow O Pulse output TAOQOUT O Toggle flip flop Figure 1 37 Block diagram of timer A Timer AO mode register Symbol Address When reset b7 b6 b5 b4 b3 b2 bi bO TAOMR 039616 0016 Bit symbol RW Timer mode Event counter mode One shot timer mode Pulse width modulation PWM mode t TCKO Count source select bit Function varies with each operation mode Figure 1 38 Timer A related registers 1
181. MOS MICROCOMPUTER Pin Description Pin name Vcc Vss Signal name Power supply input I O type Function Supply 2 7 to 5 5 V to the Vcc pin Supply 0 V to the Vss pin CNVss CNVss Input Connect it to the Vss pin RESET Reset input Input A L on this input resets the microcomputer XIN XOUT Clock input Clock output Input Output These pins are provided for the main clock generating circuit Connect a ceramic resonator or crystal between the XIN and the XOUT pins To use an externally derived clock input it to the XIN pin and leave the XOUT pin open AVcc Analog power supply input This pin is a power supply input for the A D converter Connect it to Vcc AVSS Analog power supply input This pin is a power supply input for the A D converter Connect it to VSS VREF Reference voltage input Input This pin is a reference voltage input for the A D converter POo to P07 I O port PO Input output This is an 8 bit CMOS I O port It has an input output port direction register that allows the user to set each pin for input or output individually When set for input the user can specify in units of four bits via software whether or not they are tied toa pull up resistor P10 to P17 I O port P1 Input output This is an 8 bit I O port equivalent to PO P30 to P35 I O port P3 Input output This is a 6 bit I O port equivalent
182. Mitsubishi single chip microcomputer M30201 Group User s manual tentative Specifications written in this user s manual are believed to be accurate but are not guaranteed to be entirely free of error Specifications in this manual may be changed for functional or performance im provements Please make sure your manual is the latest edition Mitsubishi Electric Corporation Kitaitami Works Mitsubishi Electric Semiconductor System Corporation REV A keep safety first in your circuit designs Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Mitsubishi Electric Corporation or a third party Mitsubishi Electric Corporation assumes no responsibility for any d
183. Nothing is assigned In an attempt to write to this bit write 0 The value if read turns out to be indeterminate b7 b6 io EEE AE PEE TAOTGL Timer AO event trigger oo select bit 0 0 Input on TAOIN is selected Note 0 1 TB2 overflow is selected ee eee TAOTGH 1 0 TA4 overflow is selected fone 11 TA1 overflow is selected Note Set the corresponding port direction register to 0 To understand hardware Specifications ccccceceeeeceeeeeeeeeeeteeeeeeeeeeeees Chapter 1 Hardware To understand the basic way of using peripheral features and the operation timing ceeeeeeeees Chapter 2 Peripheral Functions Usage To observe applications of peripheral features ccee Chapter 3 Examples of Peripheral Functions Applications To understand interrupt timing in detail cceeeeeeeeeeeeeeeeteeeeeeeeeeeees Chapter 4 Interrupts To understand standard data ccccessseccceeeeeeeeeeeeees Chapter 5 Standard Characteristics This manual includes a quick reference immediately following the Table of Contents indicate the page of the topic to be pursued To find a page describing a specific register by the register address eeeeeeeeeeeeeees Quick Reference to Pages Classified by Address M16C Family related document list Usages Microcomputer development flow Selection of Type of document Outli
184. O interrupt interrupt request bit set timer AO interrupt request bit to 0 after the above listed changes have been made 3 Setting the count start flag to O while PWM pulses are being output causes the counter to stop counting If the TAQOUT pin is outputting an H level in this instance the output level goes to L and the timer AO interrupt request bit goes to 1 If the TAOOUT pin is outputting an L level in this instance the level does not change and the timer AO interrupt request bit does not becomes 1 4 Normal PWM output is restored according to the interrupt request generate timing both in the case of 16 bit PWM and 8 bit PWM when PWM output is either H or L level for the entire period This holds only when a value other than 000016 or FFFF 16 is set during 16 bit PWM or a value other than 0016 or FF 16 is set during 8 bit PWM When PWM output is H level for the entire period Writing to the timer AO PWM pulse output from TAQouT pin Timer AO interrupt request bit Fa Cleared to 0 when interrupt request is accepted or cleared by software When PWM output is L level for the entire period Writing to the 1 fi X n timer AO PWM pulse output H from TAOouT pin L i Timer AO interrupt 1 m request bit o ie ZA Cleared to 0 when interrupt request is accepted or cleared by software Figure 2 2 3
185. O pin 2 Port registers Figure 1 94 shows the port registers These registers are used to write and read data for input and output to and from an external device A port register consists of a port latch to hold output data and a circuit to read the status of a pin Each bit in port registers corresponds one for one to each I O pin 3 Pull up control registers Figure 1 95 shows the pull up control registers The pull up control register can be set to apply a pull up resistance to each block of 4 ports When ports are set to have a pull up resistance the pull up resistance is connected only when the direction register is set for input 4 Port P1 drive capacity control register Figure 1 95 shows a structure of the port P1 drive capacity control register This register is used to control the drive capacity of the port P1 s N channel output transistor Each bit in this register corresponds one for one to the port pins 100 N O amp Mitsubishi microcomputers Va se M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Port Pull up selection Direction register i lt P30 to P35 Data bus Port latch i Pull up selection POo to P07 P42 P71 Direction register i lt Data bus Port latch Input to respective peripheral functions
186. OMPUTER Timer X 2 4 6 Operation of Timer X event counter mode free run type selected In event counter mode choose functions from those listed in Table 2 4 5 Operations of the circled items are described below Figure 2 4 12 shows the operation timing and Figure 2 4 13 shows the set up procedure Table 2 4 5 Choosed functions Count source Input signal to TXiiNouT counting falling edges Input signal to TXiINouT counting rising edges Timer overflow TB1 TAO TXi overflow Pulse output function No pulses output Pulses output Count operation type Reload type Free run type Operation 1 Setting the count start flag to 1 causes the counter to count the falling edges of the count source 2 Even if an underflow occurs the content of the reload register is not reloaded but the count continues At this time the timer Xi interrupt request bit goes to 1 3 Setting the count start flag to O causes the counter to hold its value and to stop n reload register content 1 Start count i i 4 Stop count i 2 Underflow FFFF16 I Start count again i i gt a Counter content hex Cleared to 0 by Set to 1 software software Count start flag ie Cleared to 0 when interrupt request is accepted or cleared by software Timer Xi interrupt 1 d 4 request bit Q Figure 2 4 12 Operation timing of event counter mode free
187. PH 12 V or VIL 0 V when VPP VPPL 5 V Enter high signals or low signals to these pins P64 to P67 Address input Ao to A3 Input port P6 These are address A0 A3 input pins Enter high signals or low signals to these pins P70 to P74 Input port P7 Enter high signals or low signals to these pins 134 BS os ve gt Appendix Parallel I O Mode Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Parallel 1 O Mode The parallel I O mode is entered by making connections shown in Figures CC 2 and CC 3 and then turning the VPPH power supply on In this mode the M30201 flash memory version operates in a manner similar to the NOR flash memory M5M28F101 from Mitsubishi Note however that there are some differences with regard to the functions not available with the microcomputer function of read device identification code and matters related to memory capacity Table CC 2 shows pin relationship between the M30201 and M5M28F 101 in parallel I O mode Table CC 2 Pin relationship in parallel I O mode Vcc M30201 flash memory version Vcc M5M28F 101 Vss Vss Address input P60 to P63 P30 to P33 P10 to P17 P50 Data I O POo to P07 OE input P4 CE input P43 WE input P40 VRFY input Note P51 Note The VRFY input only selects read only or read write mode and does not have any pin associat
188. RxDO P53 BUSY Figure DD 8 Timing for erasing all unlocked blocks Read Lock Bit Status Command This command reads the lock bit status of the specified block Execute the read lock bit status com mand as explained here following 1 Send the 7116 command code in the 1st byte of the transmission 2 Send addresses As to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec tively 3 The lock bit data of the specified block is output in the 4th byte of the transmission Write the highest address of the specified block for addresses As to A23 The M30201 flash memory version does not have the lock bit so the read value is always 1 block unlock As to A16 to 1x00 RxDO DQ6 P53 BUSY Figure DD 10 Timing for reading lock bit status 151 N O R Mitsubishi microcomputers S M30201 Group e SINGLE CHIP 16 BIT CMOS MICROCOMPUTER gt Appendix Standard Serial I O Mode Download Command This command downloads a program to the RAM for execution Execute the download command as explained here following 1 Send the FA16 command code in the 1st byte of the transmission 2 Send the program size in the 2nd and 3rd bytes of the transmission 3 Send the check sum in the 4th byte of the transmission The check sum is added to all data sent in the 5th byte onward 4 The program to execute is sent in the 5th byte onward When all data has been transmitted
189. S IMM8 dest MOV B S IMM8 dest STZ B S IMM8 dest STNZ B S IMM8 dest STZX B S IMM81 IMM82 dest CMP B S IMM8 dest PUSHM src POPM dest JMPS IMM8 JSRS IMM8 MOV B S _ IMM dest However dest A0 A1 lt Instructions whose address is added to by 1 when an address match interrupt occurs gt e Instructions other than those listed above Figure 2 9 1 Unexecuted instructions and corresponding stacked addresses 4 How to determine an address match interrupt Address match interrupts can be set at two different locations However both location will have the same vector address Therefore it is necessary to determine which interrupt has occurred address match interrupt 0 or address match interrupt 1 Using the content of the stack etc determine which interrupt has occurred according to the first part of the address match interrupt routine 302 Ni Q R Mitsubishi microcomputers DO M30201 Group Ra SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Address Match Interrupt 5 Registers related to the address match interrupt Figure 2 9 2 shows the memory map of address match interrupt related registers and Figure 2 9 3 shows address match interrupt related registers 000916 Address match interrupt enable register AIER 000A16 000B16 000E16 000F16 001016 001116 Address match interrupt register 0 RMADO 001216 001316 001416 001516 Address match interrupt register 1 RMAD1 001616 Figure 2 9 2 M
190. S MICROCOMPUTER Timer A Selecting event counter mode and functions Timer AO mode register Address 039616 TAOMR Selection of event counter mode 0 Must always be 0 when using two phase pulse signal processing 0 Must always be 0 when using two phase pulse signal processing 1 Must always be 1 when using two phase pulse signal processing 0 Must always be 0 when using two phase pulse signal processing Count operation type select bit 1 Free run type Two phase pulse signal processing operation select bit 1 Multiply by 4 processing operation Note Set the corresponding port direction register which inputs the pulse to 0 input mode J D Two phase pulse signal processing select bit bO b7 Up d fl Add 0384 PPPI DDPA ur Address 038416 Timer AO two phase pulse signal processing select bit 1 Two phase pulse signal processing enabled b7 b0 Trigger select register Address 038316 olo trigcer E 00 Must always be 00 when using two phase pulse signal processing Setting divide ratio b15 b8 b7 bO b7 b0 es Timer AO register Address 038716 038616 TAO _ Can be set to 000016 to FFFF16 S i J T k Setting count start flag b7 b0 Count start flag Address 038016 HiB TABSR Timer AO count start flag Start count Figure 2 2 19 Set up procedure of2 phase pulse signal process in
191. S NC B MOV B Z MOV B S STNZ CMP B S JMP W IMM8 ROL IMM8 ROL ROL 0 ROL IMM8 ROL IMM8 ROL IMM8 ROL label 0101 5 ADD B S AND B S NC B MOV B Z MOV B S STNZ CMP B S JSR W IMM8 dsp 8 SB IMM8 dsp 8 SB dsp 8 SB 0 dsp 8 SB IMM8 dsp 8 SB IMM8 dsp 8 SB IMM8 dsp 8 SB label 0110 6 ADD B S AND B S NC B MOV B Z MOV B S STNZ CMP B S INTO IMM8 dsp 8 FB IMM8 dsp 8 FB dsp 8 FB 0 dsp 8 FB IMM8 dsp 8 FB IMM8 dsp 8 FB IMM8 dsp 8 FB 0111 7 ADD B S AND B S NC B MOV B Z MOV B S STNZ CMP B S IMM8 abs16 IMM8 abs16 abs16 0 abs16 IMM8 abs16 IMM8 abs16 IMM8 abs16 1000 8 XOR B OR B G SUB B G SBB B ADD B Q MOV B Q SHL B ADJNZ B src dest src dest src dest src dest IMM dest IMM dest IMM dest IMM dest label 1001 9 XOR W OR W G SUB W G SBB W ADD W Q MOV W Q SHL W ADJNZ W src dest src dest src dest src dest IMM dest IMM dest IMM dest IMM dest label 1010 A PUSH B S POP B S MOV W S INC W PUSH W S POP W S MOV B S DEC W ROH ROH IMM A1 A1 A1 A1 IMM A1 A1 1011 B SUB B S OR B S DEC B NOT B S STZ STZX CODE_EB REIT IMM8 ROH IMM8 ROH ROH ROH IMM8 ROH IMM8 IMM8 ROH 1100 Cc SUB B S OR B S DEC B NOT B S STZ STZX PUSHM JMP A IMM8 ROL IMM8 ROL ROL ROL IMM8 ROL IMM8 IMM8 ROL src abel 1101 D SUB B S OR B S DEC B NOT B S STZ STZX POPM JSR A IMM8 dsp 8 SB IMM8 dsp 8 SB dsp 8 SB dsp 8 SB IMM8 dsp 8 SB IMM8 IMM8 dsp 8 SB dest abel 1110 E SUB B S OR B S DEC B NOT B S STZ STZX JMPS JMP B IMM8 dsp 8 FB IMM8 dsp 8 FB dsp 8 FB
192. T CMOS MICROCOMPUTER Imer 2 2 11 Operation of Timer A pulse width modulation mode 16 bit PWM mode selected In pulse width modulation mode choose functions from those listed in Table 2 2 11 Operations of the circled items are described below Figure 2 2 24 shows the operation timing and Figure 2 2 25 shows the set up procedure Table 2 2 11 Choosed functions Count source Internal count source f1 fs f32 fc32 PWM mode 16 bit PWM 8 bit PWM Count start condition External trigger input falling edge of input signal to the TAOIN pin External trigger input rising edge of input signal to the TAOIN pin Timer overflow TB1 TX0 TX2 overflow Operation 1 If the TAOIN pin input level changes from L to H with the count start flag set to 1 the counter performs a down count on the count source Also the TAOOUT pin outputs an H level 2 The TAQOUT pin output level changes from H to L when a set time period elapses At this time the timer AO interrupt request bit goes to 1 3 The counter reloads the content of the reload register every time PWM pulses are output for one cycle and continues counting 4 Setting the count start flag to O causes the counter to hold its value and to stop Also the TAOOUT outputs an L level Note e PWM pulse cycle is 2 6 1 fi whereas H level duration is n fi However when 000016 is set for the timer AO
193. T Does not stop When fc selected When fs clock devided counter output selected Does not stop when the WAIT peripheral function clock stop bit is O When the WAIT peripheral function clock stop bit is 1 the status immedi ately prior to entering wait mode is maintained 24 es s Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Status Transition of BCLK Status Transition of BCLK Power dissipation can be reduced and low voltage operation achieved by changing the count source for BCLK Table 1 6 shows the operating modes corresponding to the settings of system clock control regis ters 0 and 1 When reset the device starts in division by 8 mode The main clock division select bit O bit 6 at address 000616 changes to 1 when shifting from high speed medium speed to stop mode and at a reset When shifting from low speed low power dissipation mode to stop mode the value before stop mode is retained The following shows the operational modes of BCLK 1 Division by 2 mode The main clock is divided by 2 to obtain the BCLK 2 Division by 4 mode The main clock is divided by 4 to obtain the BCLK 3 Division by 8 mode The main clock is divided by 8 to obtain the BCLK When reset the device starts operating from this mode Before the user can go from this mode to no division mode division by 2 mode or division by 4 mode the main clock must be oscillating stably
194. TAOTGL TAOTGH TXOTGL TXOTGH TX1TGL TX1TGH TX2TGL TX2TGH Timer AO event trigger select bit Timer XO event trigger select bit Timer X1 event trigger select bit Timer X2 event trigger select bit Input on TAOIN is selected Note TB1 overflow is selected TX2 overflow is selected TXO overflow is selected Input on TXOINouT is selected Note TB1 overflow is selected TAO overflow is selected TX1 overflow is selected Input on TX1INouT is selected Note TB1 overflow is selected TXO overflow is selected TX2 overflow is selected Input on TX2iNouT is selected Note TB1 overflow is selected TX1 overflow is selected TAO overflow is selected Note Set the corresponding port direction register to O input mode Clock prescaler reset flag b7 b6 b5 b4 b3 b2 bi bO Symbol CPSRF Address 038116 When reset OXXXXXXX2 Biaymba Strane Fon JRW Nothing is assigned When write set 0 When read their contents are indeterminate Clock prescaler reset flag Figure 2 2 5 Timer A related registers 4 167 0 No effect 1 Prescaler is reset When read the value is 0 O Q sf Mitsubishi microcomputers SX oF M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 2 Operation of Timer A timer mode In timer mode choose functions from those listed in Table 2 2 1 Operations of the circled items are described below Figure 2 2 6 shows
195. TMODO _ Operation mode select bit 1 20 0 0 1 0 One shot timer mode TMOD1 0 0 MRO Pulse output function 0 Pulse is not output select bit TAOOUT pin is a normal port pin 1 Pulse is output Note 1 TAOOuT pin is a pulse output pin External trigger select Falling edge of TAOIN pin s input signal Note 3 bit Note 2 Rising edge of TAOIN pin s input signal Note 3 Trigger select bit One shot start flag is valid Selected by event trigger select register MR3 0 Must always be 0 in one shot timer mode b7 b6 00 f1 01 fs TCK1 10 f32 1 1 fc32 TCKO Count source select bit Note 1 Set the corresponding port direction register to 1 output mode Note 2 Valid only when the TAOIN pin is selected by the event trigger select bit addresses 038316 If timer overflow is selected this bit can be 1 or 0 Note 3 Set the corresponding port direction register to O input mode Figure 1 44 Timer AO mode register in one shot timer mode 57 xX xe Ss Mitsubishi microcomputers Sty M30201 Group Ra SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 4 Pulse width modulation PWM mode In this mode the timer outputs pulses of a given width in succession See Table 1 17 In this mode the counter functions as either a 16 bit pulse width modulator or an 8 bit pulse width modulator Figure 1 45 shows the timer AO mode register in pulse width modulation mode Figure 1 46 sho
196. TO transmit buffer register to UARTO transmit register CLKO Receive data is taken in RxDO Transferred from UARTO receive register Read out from UARTO receive buffer register Receive complete d to UARTO receive buffer register flag RI Receive interrupt 1 request bit IR P pe Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols The above timing applies to the following settings Meet the following conditions are met when the CLK External clock is selected input before data reception H e CLK polarity select bit 0 Transmit enable bit gt 1 e Receive enable bit 1 Dummy data write to UARTO transmit buffer register fEXT frequency of external clock Figure 1 75 Typical transmit receive timings in clock synchronous serial I O mode E 83 Clock synchronous serial I O mode a Polarity select function As shown in Figure 1 76 the CLK polarity select bit bit 6 at addresses 03A416 allows selection of the polarity of the transfer clock e When CLK polarity select bit 0 CLKo l l TxDo X DO X D1 X D2 Ix D3 X D4 A D5 X De x D7 Note 1 The CLKO pin level when not X Do X D1 X J transferring data is H D2 X D3 X D4 X D5 X De X D7 RxDo Do D1 e When CLK polarity select bit 1 CLKo
197. TX1INOUT TX2INOUT TBOIN TB1IN INTo INT1 CLKo Hysteresis RESET HIGH input current P0o to P07 P10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 XIN RESET CNVss LOW input current POo to P07 P10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 XiIN RESET CNVss RPULLUP Pull up resister POo to P07 P10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 RXIN Feedback resister XIN RXCIN Feedback resister XCIN VRAM RAM retention voltage When clock is stopped Note Unless otherwise noted Vcc 5V Vss OV at Ta 25 C f XIN 10MHz Power supply current 114 f XIN 1 OMHz Square wave no division f XCIN 32kHz Square wave I O pin has no f XCIN 32kHz load With wait Ta 25 C when clock is stopped Ta 85 C when clock is stopped Electrical characteristics Vcc 5V Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Table 1 40 A D conversion characteristics Parameter Resolution Measuring condition Vrer Vcc Vcc 5V Standard Min Typ Max Absolute Sample amp hold function not available VREF Vcc 5V accuracy Sample amp hold function available 10bit VREF Vcc 5V Sample amp hold function available 8bit VREF Vcc 5V RLADDER Ladder resistance Vrer Vcc
198. TXO Timer X1 register Address 038B16 038A16 TX1 Timer X2 register Address 038D16 038C16 TX2 Can be set to 000016 to FFFF16 S Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 bO Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 Me Setting count start flag b7 bO Count start flag Address 038016 TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag Start count Figure 2 4 9 Set up procedure of timer mode pulse output function selected 217 O s Mitsubishi microcomputers Ss M30201 Group ro SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 5 Operation of Timer X event counter mode reload type selected In event counter mode choose functions from those listed in Table 2 4 4 Operations of the circled items are described below Figure 2 4 10 shows the operation timing and Figure 2 4 11 shows the set up procedure Table 2 4 4 Choosed functions Count source Input signal to TXiiInouT counting falling edges Input signal to TXiINouT counting rising edges Timer overflow TB1 TAO TXi overflow Pulse output function No pulses output Pulses output Count operation type Reload typ
199. Table 1 11 Table 1 11 Time required for executing the interrupt sequence Interrupt vector address Stack pointer SP value 16 bit bus without wait 8 bit bus without wait Even 18 cycles Note 1 20 cycles Note 1 Even 19 cycles Note 1 20 cycles Note 1 Odd Note 2 19 cycles Note 1 20 cycles Note 1 Odd Note 2 20 cycles Note 1 20 cycles Note 1 Note 1 Add 2 cycles in the case of a DBC interrupt add 1 cycle in the case either of an address match interrupt or of a single step interrupt Note 2 Locate an interrupt vector address in an even address if possible BCLK Address bus y Address Indeterminate i SP 2 SP 4 vec vec 2 PC Data bus ae indeterminate SP 2 SP 4 vec vec 2 information contents contents contents contents Indeterminate The indeterminate segment is dependent on the queue buffer If the queue buffer is ready to take an instruction a read cycle occurs Figure 1 26 Time required for executing the interrupt sequence Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted the interrupt priority level of the accepted interrupt is set in the IPL If an interrupt request that does not have an interrupt priority level is accepted one of the values show
200. The clock output function select bit allows you to choose the clock from fs fc or a divide by n clock that is output from the P54 CKOUT pin The clock divide counter is an 8 bit counter whose count source is f32 and its divide ratio can be set in the range of 0016 to FFi6 Figure 1 19 shows a block diagram of clock output Clock source selection P54___ o f8 o P54 CKOUT fc o Clock divided couter 8 Division n 1 n 0016 to FF16 Example i When f Xin 10MHz Hepat Address 038E t6 n 0716 approx 16 5kHz Low order 8 bits n 2616 approx 4 0kHz n 4D16 approx 2 0kHz Data bus low order bits n 9B16 approx 1 0kHz Figure 1 19 Block diagram of clock output 23 xX xe g Mitsubishi microcomputers S M30201 Group Ra SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Wait Mode Stop Mode Writing 1 to the all clock stop control bit bit O at address 000716 stops all oscillation and the microcom puter enters stop mode In stop mode the content of the internal RAM is retained provided that Vcc remains above 2V Because the oscillation of BCLK f1 to f32 fc f 32 and fAD stops in stop mode peripheral functions such as the A D converter and watchdog timer do not function However timer A timer B and timer X operate provided that the event counter mode is set to an external pulse and UARTO functions provided an external clock is selected Table 1 4 shows the status of the ports in stop mode Stop mode is cance
201. Type of Interrupts Figure 4 1 1 lists the types of interrupts Undefined instruction UND instruction Overflow INTO instruction BRK instruction INT instruction Software Interrupt Reset DBC Special J Watchdog timer Single step Address matched Hardware Peripheral I O Note Note Peripheral I O interrupts are generated by the peripheral functions built into the microcomputer system Figure 4 1 1 Classification of interrupts e Maskable interrupt An interrupt which can be enabled disabled by the interrupt enable flag I flag or whose interrupt priority can be changed by priority level e Non maskable interrupt An interrupt which cannot be enabled disabled by the interrupt enable flag I flag or whose interrupt priority cannot be changed by priority level 352 x Cy amp s Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 1 2 Software Interrupts A software interrupt occurs when executing certain instructions Software interrupts are non maskable interrupts Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction e Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag O flag set to 1 The following are instructions whose O flag changes by arithmetic ABS ADC ADCF ADD CMP DIV DIVU DIVX NEG RMPA SBB SH
202. UT pin outputs an H level 2 The TXiINOUT pin output level changes from H to L when a set time period elapses At this time the timer Xi interrupt request bit goes to 1 3 The counter reloads the content of the reload register every time PWM pulses are output for one cycle and continues counting 4 Setting the count start flag to O causes the counter to hold its value and to stop Also the TXiINOUT outputs an L level Note e PWM pulse cycle is 218 1 fi whereas H level duration is n fi However when 000016 is set for the timer AO register the PWM output is L level for the entire period and an interrupt request is generated for every PWM output cycle Also when FFFF 16 is set for the timer AO register the PWM output is H level for the entire period and an interrupt request is generated for every PWM output cycle fi Count source frequency f1 fs f32 fc32 n Timer value Conditions Reload register 000316 when timer overflow is selected in trigger irix 2 1 cones MANNS APL Cleared to o when interrupt request is accepted or cleared by software Timer Interrupt H i request bit _ Pa becoming trigger Set to yn by software Cleared to 0 by software Count start flag 1 Start count 2 Output level H to L 3 One period is complete 1 fi Xn i 4 Stop count PWM pulse output H
203. Xi interrupt request bit goes to 1 Also the output polarity of the TXiINOUT pin reverses 3 Setting the count start flag to O causes the counter to hold its value and to stop Also the TXiINOUT pin outputs an L level n reload register content 3 Stop count 2 Underflow 1 Start count Counter content hex Cleared to 0 by software Count start flag Pulse output from H TXiINOUT pin Timer Xi interrupt request bit Figure 2 4 8 Operation timing of timer mode pulse output function selected 216 N O amp Mitsubishi microcomputers S ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Selecting timer mode and functions Timer Xi mode register i 0 to 2 Address 039716 to 039916 TXiMR i 0 to 2 Selection of timer mode Pulse output function select bit 1 Pulse is output Note TXiINOUT pin is a pulse output pin Gate function select bit b4 b3 5 i Gate function not available Set to 0X when pulse output function selected 0 Must always be 0 in timer mode Count source select bit Count Count source period b7 b6 source f Xin 10MHZ f Xcin 32 768kHz j 100ns 10 f32 pull 1 1 fc32 i 3 2us 976 56us Note Set the corresponding port direction register to 1 output mode Setting divide ratio b8 b0 a Timer XO register Address 038916 038816
204. Xi interrupt request bit to 0 after the above listed changes have been made 4 If a trigger occurs while a count is in progress after the counter performs one down count following the reoccurrence of a trigger the reload register contents are reloaded and the count continues To generate a trigger while a count is in progress generate the second trigger after an elapse longer than one cycle of the timer s count source after the previous trigger occurred 233 N O Mitsubishi microcomputers R SF of M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 14 Precautions for Timer X pulse period pulse width measurement mode 1 The timer Xi interrupt request bit goes to 1 when an effective edge of a measurement pulse is input or timer Xi is overflowed The factor of interrupt request can be determined by use of the timer Xi overflow flag within the interrupt routine 2 If the timer overflow occurs simultaneously with the input of a measurement pulse and if the interrupt factor cannot be determined from the timer Xi overflow flag connect the timers and count the number of overflows 3 When reset the timer Xi overflow flag goes to 1 This flag cannot be set to 0 by writing to the timer Xi mode register when the count start flag is 1 4 Use the timer Xi interrupt request bit to detect only overflows Use the timer Xi overflow flag only to determine the interrupt factor within the i
205. a 10 MHz oscillator to XIN Operation 1 Setting the count start flag to 1 causes the counter of timer X0 to begin counting The counter of timer XO performs a down count on count source f1 2 If the counter of timer XO underflows the counter reloads the content of the reload register and continues counting At this time the timer XO interrupt request bit gose to 1 3 An underflow in timer X0 triggers the counter of timer X1 and causes it to begin counting When the counter of timer X1 begins counting the output level of the TX1INOUT pin gose to H 4 As soon as the count of the counter of timer X1 becomes 000016 the output level of TX1INOUT pin gose to L and the counter reloads the content of the reload register and stops counting At the same time the timer X1 interrupt request bit gose to 1 330 Mitsubishi microcomputers se S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications reload register content 1 Timer XO start count o 2 Timer X0 underflow Timer X0 counter content hex n reload register content 3 Timer X1 start count 4 Timer X1 e count n 000016 re o 2 Z gt Q 8 pn gt x lt i E H content hex Set to 1 by software Timer XO count le start flag 0 i Set to 1 by software Timer X1 count 1 i i i r start flag g o1 ant i 500us PWM pulse output H segen fr
206. a a a t 147 Chapter 2 Peripheral Functions Usage 21 Protect 2ccsd ea o EATE eddies lenis le ei eddie Nidhi eed tlie adie ae 160 2 1 3 Precaution for Protect cccccececeeeececeeeeeeeeceeaeeeeaaeeseeaeeeeaaaeseaeeecaaaeseeeeesaaeseeeeeeseaeeseaaeeee 161 22 TUMOR Ay ia shatter aa a a a OR ide UR tack Scene ce dda a lease ad ee een 162 PAED VITTEN sa cates adic seas a at ath eee ts eae eda ath ese eae edhe tea deg A 162 2 2 2 Operation of Timer A timer mode eeeeeeceeeeeeeeeeeeeeeeeeeaeeeeeeeeesaaeeeeeeeeesaaeeeeeaeeeseeeeeeaeeeee 168 2 2 3 Operation of Timer A timer mode gate function Selected cceeceeeeeeeeeeteeeeeteeeeeneeeees 170 2 2 4 Operation of Timer A timer mode pulse output function Selected cceeeeeeeeeeeeeees 172 2 2 5 Operation of Timer A event counter mode reload type selected ccceeceeeseeeeeeeeees 174 2 2 6 Operation of Timer A event counter mode free run type Selected eeeeeeeeeteeeeeeeees 176 2 2 7 Operation of timer A 2 phase pulse signal process in event counter mod normal mode se eee e p E E A E ye vagudbianiveedutivavesecciievvsaudiiaelevecciayi vie 178 2 2 8 Operation of timer A 2 phase pulse signal process in event counter mode multiply by 4 mode SCIGCIOG ciate acter ate ee get he ata tei aoe teeta A DE baa ragreeen teat Chae ees 180 2 2 9 Operation of Timer A one shot timer mode eeeeeceeeteeeeeeeeececeeeeeeeeeeeeaeeeeeaeeseeaeeeeeaeeeee
207. a values are not guaranteed Refer to section Electrical characteristics for rated values Figure 5 1 6 loL VoL standard characteristics of port P1 Vcc 3V HIGH POWER E 376 N RA lt Ss Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics 5 1 2 Characteristics of ICC f XIN Figures 5 1 7 and 5 1 8 show the Characteristics of ICC f XIN e Measurement conditions Vcc 5V Ta 25 C f XIN square waveform input single chip mode When access to ROM and RAM without wait e Register setting condition XIN XOUT drive capacity select bit 1 HIGH Main clock XIN XQUT stop bit 0 On m XIN 2 a XIN 4 x XIN 8 XIN 16 6 f XIN MHz Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figures 5 1 7 Characteristics of ICC f XIN Vcc 5V 377 xX O S Mitsubishi microcomputers NO M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics Vcc 3V e Measurement conditions Vcc 3V Ta 25 C f XIN square waveform input single chip mode When access to ROM and RAM without wait e Register setting condition XIN XOUT drive capacity select bit 1 HIGH Main clock XIN XOUT stop bit 0 On eo XIN 1 E XIN
208. aches 000016 Count start flag Timer Xi interrupt request bit 1 Cleared to 0 when interrupt request is accepted or cleared by software Timer Xi overflow flag Note 1 Counter is initialized at completion of measurement Note 2 Timer has overflowed Figure 2 4 18 Operation timing of pulse width measurement mode 226 x N amp os Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X a Selecting pulse period pulse width measurement mode and functions b7 b0 1M 1 1 Timer Xi mode register i 0 to 2 Address 039716 to 039916 TERETE TL tricot Selection of pulse period pulse width measurement mode Measurement mode select bit b3 b2 1 0 Pulse width measurement Interval between measurement pulse falling edge to rising edge and between rising edge to falling edge Timer Xi overflow flag 0 Timer did not overflow 1 Timer has overflowed 1 Must always be 1 in pulse period pulse width measurement mode a source Select bit Count Count source period 00 f source f Xin 10MHZ f Xcin 32 768kHz 01 fs i 100ns 10 f32 800ns 11 fc32 3 2us 976 56us Note Set the corresponding port direction register which sets the measurement pulse to 0 input mode k Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the presc
209. address Duration 20 us Loop counter X X 1 Write program verify command Duration 6 us Last address b Next address Write 4016 Write Program data Write C016 FAIL y C Write read command Write read command J Write 0016 PASS y FAIL Erase Start All bytes 0016 NO Program all bytes 0016 Address First address Loop counter X 0 Write erase command Write erase command Duration 20ms Loop counter X X 1 Write erase verify command address Duration 6ps Last address Next address Write 2016 Write 2016 Write A016 Read expect value FF16 Write read command Write read command Write 0016 v PASS v FAIL Figure CC 4 Program and erase execution flowchart in the CPU rewrite mode 142 x Cy O s Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Parallel I O Mode Protect function In parallel I O mode the internal flash memory has the protect function available This function protects the flash memory contents from being read or rewritten easily Depending on the content at the protect control address FFFFF16 in parallel 1 O mode this function inhibits the flash memory contents against read or modifi
210. ain clock by 1 8 and 32 respectively fc32 is the clock obtained by dividing the CPU secondary clock by 32 3 Frequency division ratio The frequency division ratio equals the value set in the timer register 1 The counter underflows when a count source equal to a frequency division ratio is input and an interrupt request occurs 4 Reading the timer In timer mode or event counter mode the count value at the time of reading the timer register will be read Read the register in 16 bit increments In both the pulse period measurement mode and pulse width measurement mode an indeterminate value is read until the second effective edge is input after a count is started otherwise the measurement results are read 5 Writing to the timer When writing to the timer register while a count is in progress the value is written only to the reload register When writing to the timer register while a count has stopped the value is written both to the reload register and the count Write the value in 16 bit increments The timer register cannot be written to in either the pulse period measurement mode or the pulse width measurement mode 194 Ni O aS Mitsubishi microcomputers SX ef M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 6 Input to the timer and the direction register To input an external signal to the timer set the direction register of the relevant port to input 7 Pins related to timer B a TBOIN TB1IN
211. al cv cut se A eet dae oe ceca tied Sad da dnd ape E ceee ee 272 2 7 A OVGVIOW eat aeania ianao tie ade a eee ui a el ae a 272 2 7 2 Operation of A D converter one shot mode ceeeeceeeeeeeeeeeee eee eeeeeeeeseaeeeseaeeeeeaeeeeeaaeeee 278 2 7 3 Operation of A D Converter in repeat MOdEe ceceecececeeeeeeee cece eeeeeeeseaeeeseaeeseeeeeeeaaeeees 280 2 7 4 Operation of A D Converter in single sweep mode ee eeeeceeeeteeeeeeee cee eeeeeeeteteeeeeaeeeees 282 2 7 5 Operation of A D Converter in repeat Sweep mode 0 ceeccceeeeeeeeeeeeeseteeeeeeeeeeetaeeeeeeeee 284 2 7 6 Operation of A D Converter in repeat Sweep mode 1 ceeeeceeeeeeeeeeeeeeteeeeeeeesetaeeeeeeeees 286 2 7 7 Precautions for A D Converter cccccceescceceeeeeeeeaeeceeeeeeeaaaeeeeeeseaaaesseneeesaaaeseeneeeseaeeseaaeeee 288 2 7 8 Method of A D Conversion 10 bit mode ceeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeeaaeeeeneeeesaeeeeeeeee 289 2 7 9 Method of A D Conversion 8 bit mode ccccceeeeeeeeee cece eeeeeeeeeeaeeeeeeeeesaaeeeeeaeeeeeaeeeeeaaeeee 291 2 7 10 Absolute Accuracy and Differential Non Linearity Error cei ceeeeeeeeeeeeeeeteeeeeeeneeeeeneea 293 2 7 11 Internal Equivalent Circuit of Analog INDUt ccccececceceeeeeeeeeeeeeaeeeeeeeeesaeeeeeaeeeseaeeeeeaeeees 295 2 7 12 Sensor s Output Impedance under A D Conversion c cccececeeeeeeeeeeeeeeeeeeeeeeeeeeeaeeeees 296 258 WatchdOg TIMET ss sisss
212. al external clock select bit bit 3 at address 03A016 1 Transterelockinput Port P52 direction register bit 2 at address 03EB16 0 82 N Q amp Mitsubishi microcomputers Sos M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock synchronous serial I O mode e Example of transmit timing when internal clock is selected Te Transfer clock UUUUUUUUUUUUUULUUU ULUL E a mmo Transmit enable Data is set in UARTO transmit buffer bit TE 0 register Transmit buffer empty flag TI Transferred from UARTO transmit buffer register to UARTO transmit register TCLK a Stopped pulsing because transfer enable bit 0 noo 000000000000 aooe Transmit j register empty s Loo y Ef flag TXEPT 8 r Transmit interrupt 1 request bit IR aa x A Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols The above timing applies to the following settings Tc TCLK 2 n 1 fi e Internal clock is selected fi frequency of BRGO count source f1 f8 32 fc e CLK polarity select bit 0 n value set to BRGO e Transmit interrupt cause select bit 0 e Example of receive timing when external clock is selected 1 Receive enable bit RE 0 Transmit enable bit TE o Dummy data is set in UARTO transmit buffer register Transmit buffer empty flag TI Transferred from UAR
213. aler for generating fc32 by dividing the XcIN by 32 b7 b0 Clock prescaler reset flag Address 038116 LDPE CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 Setting count start flag b7 0 Count start flag Address 038016 TABSR Timer XO count start flag Timer X1 count start flag Timer X2 count start flag Start count Clearing overflow flag 2 PO Timer Xi mode register i 0 to 2 Address 039716 to 039916 T e txime 0 to 2 Timer Xi overflow flag 0 Timer did not overflow Figure 2 4 19 Set up procedure of pulse width measurement mode 227 N O Mitsubishi microcomputers Y S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 10 Operation of Timer X pulse width modulation mode 16 bit PWM mode selected In pulse width modulation mode choose functions from those listed in Table 2 4 9 Operations of the circled items are described below Figure 2 4 20 shows the operation timing and Figure 2 4 21 shows the set up procedure Table 2 4 9 Choosed functions Count source Internal count source f1 fs f32 fc32 PWM mode 16 bit PWM 8 bit PWM Count start condition Timer overflow TB1 TAO TXi overflow Operation 1 Selected timer overflow is generated with the count start flag set to 1 the counter performs a down count on the count source Also the TXiINO
214. amage or infringement of any third party s rights originating in the use of any product data diagrams charts or circuit application examples contained in these materials All information contained in these materials including product data diagrams and charts represent information on products at the time of publication of these materials and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials If these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the
215. and the central processing unit CPU to execute arithmetic logic operations Also included are peripheral units such as timers serial I O A D converter and I O ports The following explains each unit Memory Figure 1 6 is a memory map of the M30201 The address space extends the 1M bytes from address 0000016 to FFFFF16 From FFFFF16 down is ROM For example in the M30201M4 XXXFP there is 32K bytes of internal ROM from F800016 to FFFFF16 The vector table for fixed interrupts such as the reset are mapped to FFFDC16 to FFFFF 16 The starting address of the interrupt routine is stored here The address of the vector table for timer interrupts etc can be set as desired using the internal register INTB See the section on interrupts for details From 0040016 up is RAM For example in the M30201M4 XXXFP there is 1K byte of internal RAM from 0040016 to 007FF16 In addition to storing data the RAM also stores the stack used when calling subrou tines and when interrupts are generated The SFR area is mapped to 0000016 to OO3FF16 This area accommodates the control registers for periph eral devices such as I O ports A D converter serial I O and timers etc Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes The special page vector table is mapped to FFE0016 to FFFDB16 If the starting addresses of subroutines or the destination addresses of jumps are stored here subroutine call instructions and jump in
216. ansferred from UARTO receive register Read out from UARTO receive buffer register Receive complete q to UARTO receive buffer register DN flag RI _ y g Receive interrupt request bit IR phd Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols The above timing applies to the following settings Make sure that the following conditions are met when e External clock is selected the CLKO pin input H before data reception e CLK polarity select bit 0 e Transmit enable bit fi 1 e Receive enable bit fi 1 e Dummy data write to UARTO transmit buffer register fEXT frequency of external clock Figure 2 5 11 Operation timing of reception in clock synchronous serial I O mode 251 amp RX Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Setting UARTO transmit receive mode register b0 UARTO transmit receive mode register UOMR Address 03A016 Must be fixed to 001 Internal external clock select bit 1 External clock Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Sleep select bit Must be 0 in clock synchronous I O mode Setting UARTi transmit receive control register 0 i 0 to 2 b7 b0 UARTO t mit ive control register 0 LoloT ToT Tel 1 A a convo
217. ansferred to the reload register The timer Xi interrupt request does not generate 3 If a measurement pulse changes from H to L again the value of the counter is transferred to the reload register and the timer Xi interrupt request bit goes to 1 Then the value of the counter becomes 000016 and the measurement is started again Note e The timer Xi interrupt request bit goes to 1 when an effective edge of a measurement pulse is input or timer Xi is overflowed The factor of interrupt request can be determined by use of the timer Xi overflow flag within the interrupt routine e The value of the counter at the beginning of a count is indeterminate Thus there can be in stances in which the timer Xi overflow flag goes to 1 immediately after a count is performed e The timer Xi overflow flag goes to 0 if timer Xi mode register is written to when the count start flag is 1 This flag cannot be set to 1 by software Measurement of pulse time interval from falling edge to falling edge 1 Start count 2 Start measurement 3 Start measurement again Count source s Measurement pulse M 1 1 i 1 n 1 i j I ji l Transfer Transfer Reload register lt counter indeterminate valje measured value transfer timing Pae i Note 1 x Note 2 Timing at which counter ka reaches 000016 Count start flag Cleared to 0 when interrupt request is accepted or c
218. arison result is stored in the successive comparison register until analog to digital conversion Successive comparison method is complete If a trigger occurs the A D converter carries out the following 1 Fixes bit 9 of the successive comparison register Compares Vref with VIN In this instance the contents of the successive comparison register are 10000000002 default Bit 9 of the successive comparison register varies depending on the comparison re sult as follows If Vref lt VIN then 1 is assigned to bit 9 If Vref gt VIN then 0 is assigned to bit 9 2 Fixes bit 8 of the successive comparison register Sets bit 8 of the successive comparison register to 1 then compares Vref with VIN Bit 8 of the successive comparison register varies depending on the comparison result as follows If Vref lt VIN then 1 is assigned to bit 8 If Vref gt VIN then 0 is assigned to bit 8 3 Fixes bit 7 through bit 0 of the successive comparison register Carries out step 2 above on bit 7 through bit 0 After bit 0 is fixed the contents of the successive comparison register conversion result are transmitted to A D register i Vref is generated based on the latest content of the successive comparison register Table 2 7 7 shows the relationship of the successive comparison register contents and Vref Table 2 7 8 shows how the successive comparison register and Vref vary while A D conversion is in progres
219. art condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing Timer overflows or underflows TAOIN pin function Two phase pulse input TAOOUT pin function Two phase pulse input Read from timer Count value can be read out by reading timer AO register Write to timer When counting stopped When a value is written to timer AO register it is written to both reload regis ter and counter When counting in progress When a value is written to timer AO register it is written to only reload regis ter Transferred to counter at next reload time Select function Normal processing operation The timer counts up rising edges or counts down falling edges on the TAOIN pin when input signal on the TAOOUT pin is H TAQOUT TAOIN i a B t Up Up Up Down Down Down count count count count count count Multiply by 4 processing operation If the phase relationship is such that the TAOIN pin goes H when the input signal on the TAOQOUT pin is H the timer counts up rising and falling edges on the TAOQOUT and TAOIN pins If the phase relationship is such that the TAOIN pin goes L when the input signal on the TAOOUT pin is H the timer counts down rising and falling edges on the TAOQOUT and TAOIN pins Taoout fy dy f viva y lt Count up all edges Count down all edges s a
220. as separate 8 bit data registers high order bits as ROH R1H and low order bits as ROL R1L In some instructions registers R2 and RO as well as R3 and R1 can use as 32 bit data registers R2RO R3R1 2 Address registers AO and A1 Address registers AO and A1 are configured with 16 bits and have functions equivalent to those of data registers These registers can also be used for address register indirect addressing and address register relative addressing In some instructions registers A1 and AO can be combined for use as a 32 bit address register A1A0 12 amp sf Mitsubishi microcomputers ve M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CPU 3 Frame base register FB Frame base register FB is configured with 16 bits and is used for FB relative addressing 4 Program counter PC Program counter PC is configured with 20 bits indicating the address of an instruction to be executed 5 Interrupt table register INTB Interrupt table register INTB is configured with 20 bits indicating the start address of an interrupt vector table 6 Stack pointer USP ISP Stack pointer comes in two types user stack pointer USP and interrupt stack pointer ISP each config ured with 16 bits Your desired type of stack pointer USP or ISP can be selected by a stack pointer select flag U flag This flag is located at the position of bit 7 in the flag register FLG 7 Static base register SB Static b
221. ase register SB is configured with 16 bits and is used for SB relative addressing 8 Flag register FLG Flag register FLG is configured with 11 bits each bit is used as a flag Figure 1 10 shows the flag register FLG The following explains the function of each flag e Bit 0 Carry flag C flag This flag retains a carry borrow or shift out bit that has occurred in the arithmetic logic unit Bit 1 Debug flag D flag This flag enables a single step interrupt When this flag is 1 a single step interrupt is generated after instruction execution This flag is cleared to 0 when the interrupt is acknowledged e Bit 2 Zero flag Z flag This flag is set to 1 when an arithmetic operation resulted in 0 otherwise cleared to 0 e Bit 3 Sign flag S flag This flag is set to 1 when an arithmetic operation resulted in a negative value otherwise cleared to 0 e Bit 4 Register bank select flag B flag This flag chooses a register bank Register bank 0 is selected when this flag is 0 register bank 1 is selected when this flag is 1 e Bit 5 Overflow flag O flag This flag is set to 1 when an arithmetic operation resulted in overflow otherwise cleared to 0 e Bit 6 Interrupt enable flag I flag This flag enables a maskable interrupt An interrupt is disabled when this flag is O and is enabled when this flag is 1 This flag is cleared to 0 when the interrupt i
222. ate of conversion of each pin increases As a result a 28 AD cycle is achieved with 8 bit resolution and 33 oAD with 10 bit resolution Sample and hold can be selected in all modes However in all modes be sure to specify before starting A D conversion whether sample and hold is to be used 99 X eo lt Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Port Programmable I O Ports There are 43 programmable I O ports PO to P7 Each port can be set independently for input or output using the direction register A pull up resistance for each block of 4 ports can be set The port P1 allows the drive capacity of its N channel output transistor to be set as necessary Figures 1 90 to 1 92 show the programmable I O ports Each pin functions as a programmable I O port and as the I O for the built in peripheral devices To use the pins as the inputs for the built in peripheral devices set the direction register of each pin to input mode When the pins are used as the outputs for the built in peripheral devices they function as outputs regardless of the contents of the direction registers See the descriptions of the respective functions for how to set up the built in peripheral devices 1 Direction registers Figure 1 93 shows the direction registers These registers are used to choose the direction of the programmable I O ports Each bit in these regis ters corresponds one for one to each I
223. atio b8 be Timer BO register Address 039116 039016 TBO L Timer Bt register Address 039316 039216 TBI O Can be set to 000016 to FFFF 16 n Setting count start flag b7 0 Count start flag Address 038016 TABSR Timer BO count start flag Timer B1 count start flag Start count Figure 2 3 7 Set up procedure of event counter mode 201 O Mitsubishi microcomputers SS M30201 Group sy SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 3 4 Operation of Timer B pulse period measurement mode In pulse period pulse width measurement mode choose functions from those listed in Table 2 3 3 Op erations of the circled items are described below Figure 2 3 8 shows the operation timing and Figure 2 3 9 shows the set up procedure Table 2 3 3 Choosed functions Count source Internal count source f1 fe f32 fc32 Measurement Pulse period measurement interval between measurement pulse falling edge to falling edge mode Pulse period measurement interval between measurement pulse rising edge to rising edge Pulse width measurement interval between measurement pulse falling edge to rising edge and between rising edge to falling edge Operation 1 Setting the count start flag to 1 causes the counter to start counting the count source 2 If a measurement pulse changes from H to L the value of the counter goes to 000016 and measurement i
224. autions for Timer B pulse period pulse width measurement mode 1 The timer Bi interrupt request bit goes to 1 when an effective edge of a measurement pulse is input or timer Bi is overflowed The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine 2 If the timer overflow occurs simultaneously with the input of a measurement pulse and if the interrupt factor cannot be determined from the timer Bi overflow flag connect the timers and count the number of overflows 3 When reset the timer Bi overflow flag goes to 1 This flag cannot be set to 0 by writing to the timer Bi mode register when the count start flag is 1 4 Use the timer Bi interrupt request bit to detect only overflows Use the timer Bi overflow flag only to determine the interrupt factor within the interrupt routine 5 When the first effective edge is input after a count is started an indeterminate value is trans ferred to the reload register At this time timer Bi interrupt request is not generated 6 The value of the counter is indeterminate at the beginning of a count Therefore the timer Bi overflow flag may go to 1 immediately after a count is started 7 If changing the measurement mode select bit is set after a count is started the timer Bi interrupt request bit goes to 1 8 If the input signal to the TBiIN pin is affected by noise precise measurement may not
225. aves the content of the program counter PC in the stack area 6 Sets the interrupt priority level of the accepted instruction in the IPL After the interrupt sequence is completed the processor resumes executing instructions from the first address of the interrupt routine Note This register cannot be utilized by the user Interrupt Response Time Interrupt response time is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment a and the time required for executing the interrupt sequence b Figure 1 25 shows the interrupt response time Interrupt request generated Interrupt request acknowledged Instruction Interrupt sequence _ Instruction in interrupt routine a Interrupt response time a Time from interrupt request is generated to when the instruction then under execution is completed b Time in which the instruction sequence is executed Figure 1 25 Interrupt response time SSS a 38 amp amp Mitsubishi microcomputers Sas M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Time a is dependent on the instruction under execution Thirty cycles is the maximum required for the DIVX instruction without wait Time b is as shown in
226. bit resolution and 59 aD cycles for 10 bit resolution Figure 2 7 9 Operation timing of single sweep mode 282 x N O aS Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter Selecting Sample and hold b7 b0 A D control register 2 Address 03D416 DDDDI 121214 Ancon A D conversion method select bit 1 With sample and hold Must be fixed to 0 Setting A D control register 0 and A D control register 1 b7 b0 b7 b0 z i A D control register 1 Add 03D7 EL erecting register 0 Address 03D616 Io ITTI ADCONT register 1 Address 16 Invalid in single sweep mode A D sweep pin select bit Note 2 bt bO Single sweep mode is selected Note 1 0 0 ANo AN1 2 pins ing P i 0 1 ANo to AN3 4 pins 1 0 ANo to AN5 6 pins Must be fixed to 0 1 1 ANo to AN7 8 pins A D conversion start flag ve nen more ele bit 1 Note 1 0 A D conversion disabled Must always be 0 in single sweep mode 8 10 bit mode select bit Frequency select bit 0 0 8 bit mode 0 faD 4 is selected 1 10 bit mode 1 faD 2 is selected Frequency select bit 1 0 faD 2 or fAD 4 is selected 1 faD is selected ______________ Vref connect bit 1 Vref connected Must be fixed to 0 A D input group select bit 0 Port P6 group is selected Note 1 Rewrite to analog input pin select bit after changing A D operation mo
227. ble vector table can be modified according to the user s settings Indicate the first address using the interrupt table register INTB The 256 byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables One vector table comprises four bytes Set the first address of the interrupt routine in each vector table Table 1 8 shows the interrupts assigned to the variable vector tables and addresses of vector tables Table 1 8 Interrupt causes variable interrupt vector addresses Software interrupt number Software interrupt number 0 Vector table address Address L to address H 0 to 3 Note Interrupt source BRK instruction Remarks Cannot be masked by flag Software interrupt number 11 44 to 47 Note Software interrupt number 12 Note Software interrupt number 13 52 to 55 Note Key input interrupt Software interrupt number 14 Note 48 to 51 Note Note Note 56 to 59 Note A D Software interrupt number 17 68 to 71 Note UARTO transmit Software interrupt number 18 72 to 75 Note UARTO receive Software interrupt number 19 76 to 79 Note UART1 transmit Software interrupt number 20 80 to 83 Note UART1 receive Software interrupt number 21 84 to 87 Note Timer AO Software interrupt number 22 88 to 91 Note Timer XO Software interrupt number 23
228. cation The protect control address FFFFF16 is shown in Figure CC 5 This address exists in the user ROM area The protect function is enabled by setting one of the two protect set bits to 0 so that the internal flash memory contents are inhibited against read or modification The protect function is disabled by setting both of the two protect reset bits to 00 so that the internal flash memory contents can be read or modified Once the protect function is set the user cannot change settings of the protect clear bits while in parallel I O mode Settings of the protect reset bits can only be changed in CPU rewrite mode Protect control address b7 b6 b5 b4 b3 b2 bi bO Symbol Address When shipping FF16 Py fd fafafayi ROMCP FFFFF16 ff eteymbo sitrame_ ___Funetion iY a Reserved bit Always set to 1 Port b5 b4 EO eee Ge ee ROMCR Protect reset bit 00 Protect removed Loe 01 Protect set bit effective it 10 Protect set bit effective a 11 Protect set bit effective b7 b6 e ena ROMCP Protect set bit 00 Protect enabled 01 Protect enabled 10 Protect enabled 11 Protect disabled Note 1 When protect is turned on the flash memory version is protected against readout or modification in parallel I O mode Note 2 The protect reset bits can be used to turn off protect However since these bits cannot be changed in parallel I O mode they need to be rewritten in CPU rewrite mode Figure CC 5
229. ccording to the contents of the IPL Tee Interrupt priority Priory IPL Enabled interrupt priority levels b2 bi b0 IPL2 IPLi IPLo 000 Level 0 interrupt disabled 0 0 0 Interrupt levels 1 and above are enabled 0 0 1 Level 1 Low 0 1 Interrupt levels 2 and above are enabled O 1 0 Level 2 01t 0 Interrupt levels 3 and above are enabled O 1 1 Level 3 0O 1 1 Interrupt levels 4 and above are enabled 1 0 0 Level 4 1 00 Interrupt levels 5 and above are enabled 101 Level 5 7 0 4 Interrupt levels 6 and above are enabled 11 0 Level 6 1 1 0 Interrupt levels 7 and above are enabled ttt Al Level 7 High tt Al All maskable interrupts are disabled When either the IPL or the interrupt priority level is changed the new level is reflected to the interrupt in the following timing e When changing the IPL using the REIT instruction the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle in volved in the REIT instruction e When changing the IPL using either the POPC LDC or LDIPL instruction the reflection takes effect as of the instruction that is executed in 3 cycles after the last clock cycle involved in the instruction used e When changing the interrupt priority level using the MOV or similar instruction the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved in the
230. ce selection Timer One shot fi o PWM Low order High order fg O Pulse period pulse width measurement 8 bits 8 bits O O f32 O Timer Reload register 16 iunet S eas i o Ui TXiINOUT e Event counter O i 0 to 2 Polarity gt Counter 16 O switching and edge pulse Data bus low order bits Clock selection Count start flag Counter reset circuit O oO TB1 overflow External 4 O trigger 1 TAO 2 TX1 when TXO 2 _O 1 TXO 2 TX2 when TX1 1 1X1 2 TAO when TX2 Pulse output lt Toggle flip flop Figure 1 56 Block diagram of timer X Timer Xi mode register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset TXIMR i 0 to 2 039716 to 039916 0016 Bit symbol R TMMOB Operation mode 00 Timer mode select bit 01 Event counter mode TMOD1 1 0 One shot timer mode or pulse period pulse width measurement mode 1 1 Pulse width modulation PWM mode MR1 MR2 MR3 TCKO TCK1 Function varies with each operation mode Count source select bit Function varies with each operation mode oio Figure 1 57 Timer X related registers 1 66 amp oe Mitsubishi microcomputers ss M30201 Group Ti X SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Imer Timer Xi register Note bs Address When reset b0b7 bO 038916 038816 Indeterminate Loo T O 038D18038C16 Indeterminate 038D16 038C16 Indeterminate Function Values that can be set
231. ceeezdanecdatssaeheeecaastenaeed ed dank cde cd E sobsatiechey canna dest sabhddend feGhaieehansenee A 298 PRR OVEIVIOW A A teneesteebeasd ca eatue headend ing stecsrbeiearebl E T A E EE 298 2 8 2 Operation of Watchdog Timer cececeesceeceeeeeeeeeeceeeeeceaeececeeeeeaaaeeeeeeeesaaeseeeeeeseaeeeeeneeee 300 2 9 Address Matoh Interrupt i vceisisngedverateen ad geet e aa e EE E aE ROS 302 2 9 TOVEIS W oie aa r a a a a a N caress 302 2 9 2 Operation of Address Match Interrupt sssssseessesesssessisssirssirresinssrnsstnnstnnnnnnsnnnnennnnnnnnsnnnt 304 210 Key lmput Iter eie a EE da na dakota ad T EE EAE 306 2 iO OVEMICW sis iiat Ate tee a ae hint thle ee tesa a a a ah eat a 306 2 10 2 Operation of Key Input Interrupt 20 2 cceeeeeceeeeeeneeeeeeeeeeeeeeeeeeeeeeaaeseeeeeeseeaeeeeeeeeetaeeneeeeees 308 24 WPOWSHGOMUOL ccsseteas ethics E A EEEE TTE EE AE EET 310 A SOM CIVIC Whee a a ela oat ae a E a rete 310 2 1t2 Stop Mode Set Up a tcavcn nics tie iit tie Ate reed a a 315 2 11 3 Wait Mode Set Up oo ceeeececccceeeeeeeeeeeeeeeeeeeeeeaeeeseeeeeceaeeeeeaaeeenaeeseeaaeeseeeeseaaeesseeeeesaeeeseneeees 316 2 1 1 4 Precautions in Power Control e aa a raaa aaa naaa a a EEEa EEE AR ATACAT AAEN Eaa 317 2 12 Programmable I O Ports e aaa a a a a aa a a a AREA T a Eaa aii 318 ZV 2M SOVENWIOW ah taia a ace late tee cca toate a ae a a a 318 Chapter 3 Examples of Peripheral functions Applications 3 1 LONG Penod MMES Secrecion a a a a a a a ee Dee
232. ch bit to transmit first This function is to choose whether to transmit data from bit 0 or from bit 7 Choose either of the following e LSB first Data is transmitted from bit 0 e MSB first Data is transmitted from bit 7 c Function for choosing successive reception mode Successive reception mode is a mode in which reading the receive buffer register makes the recep tion enabled status ready In this mode there is no need to write dummy data to the transmit buffer register so as to make the reception enabled status ready But at the time of starting reception read the receive buffer register into a dummy manner e Normal mode Writing dummy data to the transmit buffer register makes the reception enabled status ready e Successive reception mode Reading the reception buffer register makes the reception enabled status ready d Function for outputting transfer clock to multiple pins This function is to switch among pins to output the transfer clock This function is effective only when selecting the internal clock Switching among pins for outputting the transfer clock allows data trans mission to two external ICs in a time sharing manner e Function for choosing a transmission interrupt factor The timing to generate a transmission interrupt can be selected from the following the instant the transmission buffer is emptied or the instant the transmission register is emptied When transmis sion buffer empty timing is selected an interru
233. charge is held to 0 1LSB at time of A D conversion in the 10 bit mode Actual error however is the value of absolute precision added to 0 1LSB When f XIN 10 MHz T 0 3 us in the A D conversion mode with sample amp hold Output impedance RO for sufficiently charging capacitor C within time T is determined as follows T 0 3 ms R 7 8 kw C 3 pF X 0 1 and Y 1024 Hence 0 3 X 10 RO 7 8 X10834 3 0 X 108 3 0 X 10 In a 1024 Thus the allowable output impedance of the sensor circuit capable of thoroughly driving the A D con verter turns out to be approximately 3 0 kw Tables 2 7 11 and 2 7 12 show output impedance values based on the LSB values Microprocessor s inside Sensor equivalent circuit R 7 8kW YW VV e C 3 0pF Z a Vc Figure 2 7 23 A circuit equivalent to the A D conversion terminal 296 Q S Mitsubishi microcomputers NO M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter Tables 2 7 11 Output ouihi values based on the LSB values 1 f Xin o Ri Rf Resolution ROmax ine ns kohm oF SS 3 x an Sample amp hold bit is enabled 2x cycle Sample amp hold bit is disabled 3 x cycle Sample amp hold bit is enabled 2 x cycle Sample amp hold bit is disabled 297 N 2 Mitsubishi microcomputers S S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Watchdog Timer 2 8 Watchdo
234. ck The following is a description of the three available power control modes 1 Modes Power control is available in three modes a Normal operation mode e High speed mode Divide by 1 frequency of the main clock becomes the BCLK The CPU operates with the BCLK selected Each peripheral function operates according to its assigned clock Medium speed mode Divide by 2 divide by 4 divide by 8 or divide by 16 frequency of the main clock becomes the BCLK The CPU operates according to the BCLK selected Each peripheral function operates according to its assigned clock Low speed mode fc becomes the BCLK The CPU operates according to the fc clock The fc clock is supplied by the secondary clock Each peripheral function operates according to its assigned clock e Low power consumption mode The main clock operating in low speed mode is stopped The CPU operates according to the fc clock The fc clock is supplied by the secondary clock The only peripheral functions that operate are those with the sub clock selected as the count source b Wait mode The CPU operation is stopped The oscillators do not stop c Stop mode All oscillators stop The CPU and all built in peripheral functions stop This mode among the three modes listed here is the most effective in decreasing power consumption Figure 2 11 1 is the state transition diagram of the above modes 310 amp S S Sas O Power Control Transition of stop mo
235. clock control register 0 bo System clock control register 0 l 0 Address 000616 Address 000616 CMO CMO Main clock XIN XOUT stop bit Port Xc select bit On XCIN XCOUT generation System clock select bit ____________________ System clock select bit XIN XOUT XCIN XCOUT As this register becomes setting mentioned above when As this register becomes setting mentioned above when operating with XCIN operating with XIN count source of BCLK is Xin count source of BCLK is XcIN the user does not need to set it again the user does not need to set it again When operating with XIN set port Xc select bit to 1 before setting system clock select bit to 1 The both bits cannot be set at the same time at Interrupt enable flag I flag lt 1 gt clocks off stop mode bo 1 System clock control register 1 Address 000716 CM1 All clock stop control bit 1 All clocks off stop mode Reserved bit Always set to 0 NOP instruction X 5 Key input interrupt request generation Pa Figure 3 6 3 Set up procedure of controlling power using stop mode 1 344 x N xe sf Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications Key input interrupt gt 7 a Store the regist
236. clock is sufficiently stable Note 3 Change CMO06 after changing CM17 and CM16 Note 4 Transit in accordance with arrow BCLK f Xcin CMO07 1 311 N eS OC ww Power Control Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 2 Switching the driving capacity of the oscillation circuit Both the main clock and the secondary clock have the ability to switch the driving capacity Reducing the driving capacity after the oscillation stabilizes allows for further reduction in power consumption 3 Clearing stop mode and wait mode The stop mode and wait mode can be cleared by generating an interrupt request or by resetting hardware Set the priority level of the interrupt to be used for clearing higher than the processor interrupt priority level IPL and enable the interrupt enable flag I flag When an interrupt clears a mode that interrupt is processed Table 2 11 1 shows the interrupts that can be used for clearing a stop mode and wait mode 4 BCLK in returning from wait mode or stop mode a Returning from wait mode The processor immediately returns to the BCLK which was in use before entering wait mode b Returning from stop mode If operation was performed in the high speed mode or medium speed mode prior to engaging the stop mode CMO6 will change to 1 when operation shifts to the stop mode CM17 CM16 and CM07 do not change Accordingly when operation is re
237. count 1 Up count This specification becomes valid when the up down flag content is selected for up down switching cause Nothing is assigned When write set 0 When read their contents are indeterminate Timer AO two phase 0 two phase pulse signal pulse signal processing processing disabled select bit 1 two phase pulse signal processing enabled When not using the two phase pulse signal processing function set the select bit to 0 Nothing is assigned When write set 0 When read their contents are indeterminate Figure 1 39 Timer A related registers 2 51 xX N sf Mitsubishi microcomputers Sty M30201 Group Ra SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A ne sh rt fl One shot start flag Symbol Address When reset b7 b6 b5 b4 b3 b2 bi b0 ONSF 038216 XXXX00002 RW When read the value is 0 Nothing is assigned When write set 0 When read its content is indeterminate Trigger select register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset TRGSR 038316 0016 Bit symbol Timer AO event trigger te select bit a Input on TAOIN is selected Note TB1 overflow is selected TAOTGH TX2 overflow is selected TXO overflow is selected Timer X0 event trigger nee select bit Input on TXOINOUT is selected Note TB1 overflow is selected TXOTGH TAO overflow is selected TX1 overflow is selected select bit Input on TX1INOUT is selected Note TB1 overflow is select
238. ct bit b1 bO 0 0 Input on TAOIN is selected Note 2 Note 2 Set the corresponding port direction register to 0 input mode Setting PWM pulse s period and H level width b15 b8 b7 b0 b7 bo Timer AO register Address 038716 038616 TAO oo Can be set to 0016 to FE16 Can be set to 0016 to FE16 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 XXKKKKKEX Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 Setting count start flag b7 b0 Count start flag Address 038016 TABSR Timer AO count start flag Start count Figure 2 2 27 Set up procedure of pulse width modulation mode 8 bit PWM mode selected 189 oe Mitsubishi microcomputers Se O M30201 Group Ti A SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Imer 2 2 13 Precautions for Timer A timer mode 1 To clear reset the count start flag is set to 0 Set a value in the timer AO register then set the flag to 1 2 Reading the timer AO register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer AO register with the reload timing shown in Figure 2 2 28 gets FFFF16 Readin
239. cted 1 Vref connected Di a 0 Port P6 group is selected AD Input group selget pit 1 Port P5 group is selected Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 AN50 to AN54 can be used in the same way as for ANo to AN4 Note 3 If the repeat sweep mode is selected for the port P5 group the contents of A D registers 5 to 7 are indeterminate Figure 1 83 A D converter related registers 1 92 x N xe sf Mitsubishi microcomputers FX M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter A D control register 2 Note b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset ONXA of 0 of ADCON2 03D416 XXXX00002 SMP A D conversion method 0 Without sample and hold select bit 1 With sample and hold Reserved bit Always set to 0 Nothing is assigned When write set 0 When read their content is indeterminate Note If the A D control register is rewritten during A D conversion the conversion result is indeterminate A D register i Symbol Address When reset ADi i 0 to 7 03C016 to 03CF16 Indeterminate bo Eight low order bits of A D conversion result e During 10 bit mode Two high order bits of A D conversion result e During 8 bit mode When read the content is indeterminate nn i fn cic cya Ce eee eens Nothing is assigned When write set 0 When read their content is indeterminate Figure
240. d 1 Sleep mode selected Note 1 UART1 cannot be used in clock synchronous serial I O Note 2 UART1 can use only internal clock Must set this bit to 1 UARTI transmit receive control register 0 b7 b6 b5 b4 b3 b2 bi b0 Address 03A416 03AC16 When reset 0816 Symbol UiCO i 0 1 Function Note Bit name During clock synchronous serial I O mode b1 b0 0 0 f1 is selected 0 1 fais selected 1 0 f32 is selected 1 1 fc is selected Function During UART mode b1 bO 0 0 f1 is selected 0 1 f8 is selected 1 0 f32 is selected 1 1 fc is selected BRG count source select bit Set this bit to 0 Data present in transmit register during transmission No data present in transmit register transmission completed Data present in transmit register during transmission No data present in transmit register transmission completed TXEPT Transmit register empty Set this bit to 1 TXDi pin is CMOS output TXDi pin is N channel open drain output TXDi pin is CMOS output TXDi pin is N channel open drain output Data output select bit Transmit data is output at falling edge of transfer clock and receive data is input at rising edge Transmit data is output at rising edge of transfer clock and receive data is input at falling edge CLK polarity select bit Must always be 0 Transfer format select bit 0 LSB first
241. d Refer to section Electrical characteristics for rated values Figure 5 3 1 IOH VOH standard characteristics of ports PO to P7 Vcc 5V VoL V Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figure 5 3 2 lo VOL standard characteristics of ports PO to P7 Vcc 5V 0 VoL V Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figure 5 3 3 lot VOL standard characteristics of port P1 Vcc 5V HIGH POWER 381 N Q amp Mitsubishi microcomputers J SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Standard Characteristics Flash memory version 5 3 2 Characteristics of ICC f XIN Figure 5 3 4 shows the Characteristics of ICC f XIN Vcc 5V e Measurement conditions Vcc 5V Ta 25 C f XIN square waveform input single chip mode When access to ROM and RAM without wait e Register setting condition XIN XOUT drive capacity select bit 1 HIGH Main clock XIN XOUT stop bit 0 On o XIN 1 m XIN 2 A XIN 4 x XIN 8 Se XIN 16 6 f XIN MHz Note Data described here are characteristic examples The data values are not guaranteed Refer to section Electrical characteristics for rated values Figures 5
242. d 0 8 bit mode ANs is selected 1 10 bit mode AN6 is selected AN7 is selected Frequency select bit 1 O faD 2 or fAD 4 is selected 1 fap is selected Repeat mode is selected Note 1 Must be fixed to 0 _______________ Vref connect bit A D conversion start flag 1 Vref connected 0 A D conversion disabled Must be fixed to 0 Frequency select bit 0 0 fAD 4 is selected 1 faD 2 is selected ____________________ A D input group select bit 0 Port P6 group is selected 1 Port P5 group is selected Note 1 Rewrite to analog input pin select bit after changing A D operation mode Note 2 Set the corresponding port direction register to 0 input mode When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins ANso to ANs4 a Setting A D conversion start flag 5 1 2 A D control register 0 Address 03D616 ADCONO A D conversion start flag 1 A D conversion started Start A D conversion va registerO Address 03C116 03C016 register 1 Address 03C316 03C216 register 2 Address 03C516 03C416 Reading conversion result AD A D A D register3 Address 03C716 03C616 A D A D b8 b0 b7 register 4 Address 03C916 03C816 register 5 Address 03CB16 03CA16 A D register6 Address 03CD16 03CC16 A D register 7 Address 03CF16 03CE16 Eight low order bits of A D c
243. d enter wait mode In this instance enable the timer BO interrupt and the INTO interrupt 3 When a timer BO interrupt request occurs at 1 second intervals start supplying the BCLK from XCIN At this time count the clock within the routine that handles the timer BO interrupts and enter wait mode again 4 If a INTO interrupt occurs start supplying the BCLK from XCcIN Start the XIN oscillation within the INTO interrupt and switch the system clock to XIN 1 Shift to low speed mode 2 Stop XIN 3 Timer BO interrupt 4 INTo interrupt XOUT NWA XCIN Timer BO overflow Timer BO interrupt processing High speed o High speed re gt gt e a Low speed l Low speed Low speed Low speed Figure 3 7 1 Operation timing of controling power using wait mode E 346 xe sf Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications Initial condition b7 b0 Syst lock trol register 0 Add 000616 fof o ae clock control register ress 16 WAIT state internal clock stop bit XCIN XCOUT drive capacity select bit Port Xc select bit 1 Functions as XcIN XCOUT oscillator Main clock XIN XOUT stop bit 0 Oscillating Main clock divide ratio select bit 0 System clock select bit 0 XIN XOUT Operation mode select bit b1 b0 0 0 Timer mode Count source select bit b7 b6 1 1 fc32 f XCIN divided by 32 b1
244. d the other one using an externally derived clock for input Circuit constants in Figures 15 and 16 vary with each oscillator used Use the values recommended by the manufacturer of your oscillator M30201 Built in feedback resistor M30201 Built in feedback resistor XIN XIN XOUT t Open Externally derived clock Figure 1 15 Examples of main clock M30201 Built in feedback resistor M30201 Built in feedback resistor XCIN XCOUT XCIN XCOUT t Open Externally derived clock agura gA Vss Figure 1 16 Examples of sub clock Note Insert a damping resistor if required The resistance will vary depending on the oscillator and the oscillation drive capacity setting Use the value recommended by the maker of the oscillator When the oscillation drive capacity is set to low check that oscillation is stable Also if the oscillator manufacturer s data sheet specifies that a feedback resistor be added external to the chip insert a feedback resistor between XIN and XouT following the instruction Insert a damping resistor if required The resistance will vary depending on the oscillator and the oscillation drive capacity setting Use the value recommended by the maker of the oscillator When the oscillation drive capacity is set to low check that oscillation is stable Also if the oscillator manufacturer s data sheet specifies that a feedback resistor be added external to the chip insert a f
245. data is transmitted again If an overrun error occurs the UARTO receive interrupt request bit does not go to 1 4 To receive data in succession set dummy data in the lower order byte of the UARTO transmit buffer register every time reception is made 5 With an external clock selected perform the following set up procedure with the CLKO pin input level H if the CLK polarity select bit 0 or with the CLKO pin input level L if the CLK polarity select bit 1 1 Set receive enable bit to 1 2 Set transmit enable bit to 1 3 Write dummy data to the UARTO transmit buffer register 255 x N Q e Mitsubishi microcomputers Sy M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART 2 6 Clock Asynchronous Serial I O UART 2 6 1 Overview UART handles communications by means of character by character synchronization The transmission side and the reception side are independent of each other so full duplex communication is possible The following is an overview of the clock asynchronous serial I O 1 Transmission reception format Figure 2 6 1 shows the transmission reception format and Table 2 6 1 shows the names and func tions of transmission data Transfer data length 7 bits _ 1ST 7DATA __ 1SP m 1ST 7DATA 2SP m 1ST 7DATA 1PAR 1SP 1ST 7DATA 1PAR 2SP Transfer data length 8 bits _ 1ST
246. ddress match vector OFFFEF16 to OFFFEC16 ID4 Single step vector OFFFF316 to OFFFFO16 ID5 Watchdog timer vector OFFFF716 to OFFFF416 OFFFFB16 to OFFFF816 ID7 OFFFFF16 to OFFFFC16 Reset eH Figure DD 17 ID code storage addresses 154 x Se xe RX Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode Status Register SRD The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error It can be read by writing the read status register command 7016 Also the status register is cleared by writing the clear status register command 5016 Table DD 2 gives the definition of each status register bit After clearing the reset the status register outputs 8016 Table DD 2 Status register SRD Definition SRDO bits Status name Status bit Ready Busy Reserved Erase bit Terminated inserror Terminated normally Program bit Terminated in error Terminated normally Reserved x Reserved Reserved Reserved Status Bit SR7 The status bit indicates the operating status of the flash memory When power is turned on 1 ready is set for it The bit is set to O busy during an auto write or auto erase operation but it is set back to 1 when the operation ends Erase Bit SR5 The e
247. de 1 Port P5 group is selected Note 2 Set the corresponding port direction register to 0 input mode When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins AN50 to AN54 Setting A D conversion start flag A D control register 0 Address 03D616 ADCONO A D conversion start flag 1 A D conversion started Start A D conversion Stop A D onversion moooe C commnl inann i i A D registerO Address 03C116 03C016 ADO Reading ee A D register 1 Address 03C316 03C216 AD1 bO b7 A D register 2 Address 03C516 03C416 AD2 A D register 3 Address 03C716 03C616 AD3 A D register 4 Address 03C916 03C816 AD4 A D register 5 Address 03CB16 03CA16 AD5 A D register6 Address 03CD16 03CC16 AD6 A D register 7 Address 03CF16 03CE16 AD7 Eight low order bits of A D conversion result During 10 bit mode Two high order bits of A D conversion result During 8 bit mode When read the content is indeterminate Figure 2 7 10 Set up procedure of single sweep mode 283 So Mitsubishi microcomputers v8 Sy M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 5 Operation of A D Converter in repeat sweep mode 0 In repeat sweep 0 mode choose functions from those listed in Table 2 7 5 Operations of the circled items are described below Figure 2 7 11 shows timing chart and Figure 2 7 12 shows the set up procedur
248. de wait mode C Stop mode 2 Stop mode gt Aloscillators stopped 7 A Reset a S Interrupt WAIT M 1 Ne High speed medium speed mode t WAIT CM10 1 Interrupt lt CM10 1 Low speed low power instruction p _ dissipation mode nerus Normal mode Refer to the following for the transition of normal mode Transition of normal mode Main clock is oscillating Sub clock is oscillating Main clock is oscillating Sub clock is stopped Medium speed mode divided by 8 mode BCLK f Xin 8 CM07 0 CMO6 1 nt CMo4 1 a of hee 1 3 WAIT All oscillators stopped oC M10 1 Medium speed T instruction _ divided by 8 mode Interrupt instruction gt Interrupt Interrupt Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER S Wait mode CPU operation stopped CP CP Wait mode Sooo J Wait mode ration ration d CM07 CM06 CM04 0 q g ka High speed mode Medium speed mode divided by 2 mode BCLK Xin CM07 0 CMo6 o CM17 0 CM16 0 BCLK f Xin 2 CMO7 0 CMO6 0 CM17 0 CM16 1 Medium speed mode divided by 4 mode BCLK f Xin 4 CM07 0 CMO6 0
249. devieweideseeatie dee evn EAEE EA P228 B bit PWM mode Operation ceeccccceceeeccceeeeeeeceeeeeeeeceeeneeeceeeeenssecaaeeessaeeeeeenseeceaeeseeeeeeeenenees P230 2 Count source The internal count source can be selected from f1 f8 32 and fc32 Clocks f1 f8 and f32 are derived by dividing the CPU s main clock by 1 8 and 32 respectively Clock fc32 is derived by dividing the CPU s secondary clock by 32 208 Ni O aS Mitsubishi microcomputers Se M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 3 Frequency division ratio In timer mode or pulse width modulation mode the value set in the timer register 1 becomes the frequency division ratio In event counter mode the set value 1 becomes the frequency division ratio when a down count is performed or FFFF16 the set value 1 becomes the frequency division ratio when an up count is performed In one shot timer mode the value set in the timer register be comes the frequency division ratio The counter overflows or underflows when a count source equal to a frequency division ratio is input and an interrupt occurs For the pulse output function the output from the port varies the value in the port register does not vary 4 Reading the timer Either in timer mode or in event counter mode reading the timer register takes out the count at that moment Read it in 16 bit units The data either in one shot timer mode or in pulse width modulation mode is i
250. dog timer control and start registers 48 amp Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer Timer There are six 16 bit timers These timers can be classified by function into timer A one timers B two and timers X three All these timers function independently Figure 1 36 show the block diagram of timers Clock prescaler XCIN O 1 32 Clock prescaler reset flag bit 7 Reset at address 038116 set to 1 XIN O Timer mode One shot mode a FEAM Ode Timer AO filter e Event counter mode O Timer mode One shot mode PWM mode e Pulse width measuring mode O Timer XO filter e Event counter mode Timer X0 TXOINOUT _ Timer mode One shot mode PWM mode e Pulse width measuring mode e Event counter mode Timer X1 TX1INoUTC e Timer mode One shot mode PWM mode e Pulse width measuring mode a E Timer X2 O ats gt fy 0000 Y TX2INouTC filter e Event counter mode e Timer mode aX e Pulse width measuring mode Timer BO filter WY he tee e Event counter mode Wibod Timer mode e Pulse width measuring mode Noise 7 filter Timer B1 e Event counter mode Timer B1 Figure 1 36 Timer block diagram 49 xe Ss Mitsubishi microcomputers Sty M30201 Group Ra SINGLE CHIP 16 BIT CMOS
251. e Free run type Operation 1 Setting the count start flag to 1 causes the counter to count the falling edges of the count source 2 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer Xi interrupt request bit goes to 1 3 Setting the count start flag to O causes the counter to hold its value and to stop n reload register content 2 Underflow 4 Stop count lt gt Start count again gt 9 i 1 1 Jeoewsi kroi i aia sees bee 1 1 1 1 1 1 Counter content hex Cleared to 0 by software Ne Set to 1 by Set to 1 by software K Count start flag ff Lyf software i Cleared to 0 when interrupt request is accepted or cleared by software Timer Xi interrupt 1 request bit Q Figure 2 4 10 Operation timing of event counter mode reload type selected 218 x N O aS Mitsubishi microcomputers Se M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Selecting event counter mode and functions E 2 Timer Xi mode register i 0 to 2 Address 039716 to 039916 TXIMR i 0 to 2 Selection of event counter mode Pulse output function select bit Note 1 Pulse is output TXiINOUT pin is a pulse output pin Invalid when the external signal is not used as a count source Invalid in event counter mode Can be 0 or 1
252. e Table 2 7 5 Choosed functions Operation clock fAD Divided by 4 fab divided by 2 fab fAD Resolution 8 bit 10 bit ANo and AN1 2 pins ANo to ANs 4 pins ANo to ANs 6 pins ANo to AN7 8 pins Analog input pin Note Sample amp Hold Not activated Activated Note When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins ANs50 to AN54 Operation 1 Setting the A D conversion start flag to 1 causes the A D converter to start the conversion on voltage input to the ANo AN5o pin 2 After the A D conversion of voltage input to the ANo AN50 pin is completed the content of the successive comparison register conversion result is transmitted to A D register 0 3 The A D converter converts all pins selected by the user The conversion result is transmitted to A D register i corresponding to each pin every time A D conversion on the pin is com pleted The A D conversion interrupt request bit does not go to 1 4 The A D converter continues operating until the A D conversion start flag is set to O by software 1 Start A D conversion 2 AN1 AN51 conversion begins after 4 A _ ANo AN50 conversion is complete 4 A D conversion 3 Consecutive conversion is complete 8 bit resolution 28 sap cycles 8 bit resolution 28 saD cycles 10 bit resolution 33 cap cycles 10 bit resolution 33 lt ap cycles a a gt Piri ry
253. e CLK polarity select bit 1 1 Set the transmit enable bit to 1 2 Write transmission data to the UARTO transmit buffer register 254 N Ss ON Mitsubishi microcomputers DOO O M30201 Group d SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Reception 1 In operating the clock synchronous serial I O operating a transmitter generates a shift clock Fix settings for transmission even when using the device only for reception Dummy data is output to the outside from the TxDo pin transmission pin when receiving data 2 With the internal clock selected setting the transmit enable bit to 1 transmission enabled status and setting dummy data in the UARTO transmission buffer register generates a shift clock With the external clock selected a shift clock is generated when the transmit enable bit is set to 1 dummy data is set in the UARTO transmit buffer register and the external clock is input to the CLKO pin 3 In receiving data in succession an overrun error occurs when the next reception data is made ready in the UARTO receive register with the receive complete flag set to 1 before the content of the UARTO receive buffer register is read and overrun error flag is set to 1 In this instance the next data is written to the UARTO receive buffer register so handle with this problem by writing programs on transmission side and reception side so that the previous
254. e Program counter PCm gt Flag register FLG Flag register Program counter PCH SP Content of previous stack x ponter Content of previous stack interrupt occurs Content of previous stack Content of previous stack Stack status before interrupt request Stack status after interrupt request is acknowledged is acknowledged Figure 4 3 3 State of stack before and after acceptance of interrupt request 364 xe s Mitsubishi microcomputers DO M30201 Group i a t SINGLE CHIP 16 BIT CMOS MICROCOMPUTER nterrup The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer at the time of acceptance of an interrupt request is even or odd If the content of the stack pointer Note is even the content of the flag register FLG and the content of the program counter PC are saved 16 bits at a time If odd their contents are saved in two steps 8 bits at atime Figure 4 3 4 shows the operation of the saving registers Note Stack pointer indicated by U flag 1 Stack pointer SP contains even number Address Stack area Sequence in which order registers are saved SP 4 Even Program counter PCL 2 Saved simultaneously SP 3 Odd Program counter PCm all 16 bits SP 2 Even Flag register FLG 1 Saved simultaneously _ Flag register Program all 16 bits SF 1 Odd FLGH counter PCu in two
255. e 88 IMCS PUPS con S 27 Electric Characteristics ceeeeeeeeeeeeeeneees 95 Watchdog Timer ccccccececeeseeseeeeeeteeeeeeees 35 Flash Memory VersiOn cccscccsccceseeeeeeees 126 S OE Mitsubishi microcomputers w M30201 Group Se SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Description Pin Configuration Figures 1 1 to 1 2 show the pin configurations top view PIN CONFIGURATION top view P61 AN1 P60 ANo lt gt 2 P62 AN2 P63 AN3 P64 AN4 P54 CKout ANs4 gt 5 P65 AN5 P53 CLKS ANss gt LS P66 AN6 P52 CLKo ANse lt gt P67 AN7 P51 RxDo ANs1 gt L8 POo Klo P50 TxDo ANso lt gt L9 P01 Kl1 P02 Kl2 P03 KI3 P04 Kl4 P05 Kl5 P06 Kle P07 KI7 P10o LEDo dS94LOZOEN dSXXX LXWLOCOEN lt OO D m fon 09 lt dSXXX XWLOCOEW P45 TX2inout lt gt P44 INT1 TX1INouT lt gt 19 P43 INTo TXOINOUT lt gt po P42 RxDi lt gt P41 TAQout gt 292 P40 TAOIN TxD1 gt 23 Package 52P4B Figure 1 1 Pin configuration for the M30201 group shrink DIP product top view N Q amp Mitsubishi microcomputers S NO M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Description PIN CONFIGURATION top view qp P52 CLK0 AN52 lt gt P53 CLKS AN53 lt p gt P54 CKout ANs54 lt gt P60 ANo lt gt P61 AN1 lt gt P62 AN2 lt gt P63 AN3 lt gt P64 AN4 lt gt P66 ANe EG 55 54 50 43 47 4
256. e I O Port Example connection of unused pins Table 1 36 Example connection of unused pins Pin name Connection Ports PO P1 P3 to P7 After setting for input mode connect every pin to Vss pull down or after setting for output mode leave these pins open XouT Note Open AVcc Connect to Vcc AVSss VREF Connect to Vss Note With external clock input to XIN pin 107 xX Ss Q RY Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Usage precaution Usage Precaution Timer A timer mode 1 Reading the timer AO register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer AO register with the reload timing gets FFFF 16 Reading the timer AO register after setting a value in the timer AO register with a count halted but before the counter starts counting gets a proper value Timer A event counter mode 1 Reading the timer AO register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer AO register with the reload timing gets FFFF16 by under flow or 000016 by overflow Reading the timer AO register after setting a value in the timer AO register with a count halted but before the counter starts counting gets a proper value 2 When stop counting in free run type set timer again Timer A one shot timer mode 1 Setting the count
257. e boot ROM area is selected when this address input is low Type No XXXXX16 YYYYY16 M30201F6 F400016 OOBFF16 Figure AA 3 Block diagram of flash memory version 127 N Q amp Mitsubishi microcomputers SS M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CPU Rewrite Mode CPU Rewrite Mode In CPU rewrite mode the on chip flash memory can be operated on read program or erase under control of the Central Processing Unit CPU In CPU rewrite mode the flash memory can be operated on by reading or writing to the flash memory control register and flash command register Figure BB 1 Figure BB 2 show the flash memory control register and flash command register respectively Also in CPU rewrite mode the CNVSs pin is used as the VPP power supply pin Apply the power supply voltage VPPH from an external source to this pin In CPU rewrite mode only the user ROM area shown in Figure AA 3 can be rewritten the boot ROM area cannot be rewritten Make sure the program and block commands are issued for only the user ROM area The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area In the CPU rewrite mode because the flash memory cannot be read from the CPU the rewrite control program must be transferred to internal RAM before it can be executed Flash memory control register 0 b7 b5 b4 b3 b2 bo Symbol Address When reset 1o JX of X FCONO 03B416 00100000
258. e first bit the start bit of the transmission data is transmitted from the TxDi pin Then data is transmitted bit by bit in sequence LSB MSB parity bit and stop bit s 3 When the stop bit s is are transmitted the transmit register empty flag goes to 1 which indicates that transmission is completed At this time the UARTi transmit interrupt request bit goes to 1 The transfer clock stops at H level 4 If the transmission condition of the next data is ready when transmission is completed a start bit is generated following to stop bit s and the next data is transmitted 264 O aS Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Example of wiring Microcomputer Receiver side IC Example of operation Transfer clock LI 1 Transmission enabled 3 Confirme stop bit 4 Start transmission 2 Start transmission i Transmit enable bit TE Transmit buffer empty flag TI Transferred from UARTI transmit buffer register to UARTi transmit register Parity Stop Stopped pulsing because transfer enable bit 0 bit Yo TxDi Transmit register empty flag TXEPT Transmit interrupt request g bit IR Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols The above timing applies to the following settings Tc 16 n 1 fi or 16 n 1 fExT e Parity is enabled fi frequency of
259. e pins function is valid only when the internal clock is selected for UARTO Microcomputer TxDo P50 CLKS P53 CLKo P52 Note This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I O mode Figure 1 78 The transfer clock output from the multiple pins function usage d Continuous receive mode If the continuous receive mode enable bit bits 2 and 3 at address 03B016 is set to 1 the unit is placed in continuous receive mode In this mode when the receive buffer register is read out the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again 85 amp Mitsubishi microcomputers vo M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock asynchronous serial I O UART mode 2 Clock asynchronous serial I O UART mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format See Table 1 28 Figure 1 79 shows the UARTi transmit receive mode register Table 1 28 Specifications of UART Mode Item Transfer data format Specification e Character bit transfer data 7 bits 8 bits or 9 bits as selected e Start bit 1 bit e Parity bit Odd even or nothing as selected e Stop bit 1 bit or 2 bits as selected Transfer clock e When internal clock is selected bit 3 at addresses 03A016
260. e pins to output the transfer clock the following requirements must be met e UARTO internal external clock select bit bit 3 at address 03A016 0 Figure 2 6 5 UARTi related registers 3 263 0 Transmit buffer empty Tl 1 PORER completed TXEPT 1 0 Transmit buffer empty Tl 1 Transmission completed TXEPT 1 Must always be 0 Function During UART mode Invalid i Invalid N S Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART 2 6 2 Operation of Serial I O transmission in UART mode In transmitting data in UART mode choose functions from those listed in Table 2 6 4 Operations of the circled items are described below Figure 2 6 6 shows the operation timing and Figures 2 6 7 and 2 6 8 show the set up procedures Table 2 6 4 Choosed functions Transfer clock Internal clock f1 fs f32 fc source A External clock CLKO pin Note Transmission Transmission buffer empty interrupt factor Transmission complete Sleep mode Sleep mode off Sleep mode selected Note UART1 cannot be selected external clock Operation 1 Setting the transmit enable bit to 1 and writing transmission data to the UARTi transmit buffer register readies the data transmissible status 2 Transmission data held in the UARTIi transmit buffer register is transmitted to the UARTi transmit register At this time th
261. e select bit 0 8 bit mode 1 10 bit mode Frequency select bit 1 0 faD 2 or faD 4 is selected CKS1 s 1 faD is selected VCUT Vref connect bit 1 Vref connected joo Repeat mode Set this bit to 0 Di a 0 Port P6 group is selected ADGSELO A D input group select bit 1 Port P5 group is selected Note If the A D control register is rewritten during A D conversion the conversion result is indeterminate Figure 1 86 A D conversion register in repeat mode 95 Q gf Mitsubishi microcomputers Sas M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 3 Single sweep mode In single sweep mode the pins selected using the A D sweep pin select bit are used for one by one A D conversion See Table 1 33 Figure 1 87 shows the A D control register in single sweep mode Table 1 33 Single sweep mode specifications Item Specification Function The pins selected by the A D sweep pin select bit are used for one by one A D conversion Start condition Writing 1 to A D converter start flag e End of A D conversion A D conversion start flag changes to O e Writing 0 to A D conversion start flag End of A D conversion Stop condition Interrupt request generation timing Input pin ANo and AN1 2 pins ANo to ANs 4 pins ANo to AN5 6 pins or ANo to AN7 8 pins Note Reading of result of A D converter Read A D register corresponding to selected pin Note AN50 to
262. e the accepting of INTi interrupt request Set the interrupt enable flag to 1 Enable interrupt i Figure 1 33 Switching condition of INT interrupt request 4 Changing interrupt control register See Changing Interrupt Control Register 46 xX Ss O RX Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Watchdog Timer Watchdog Timer The watchdog timer has the function of detecting when the program is out of control The watchdog timer is a 15 bit counter which down counts the clock derived by dividing the BCLK using the prescaler A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer When XIN is selected for the BCLK bit 7 of the watchdog timer control register address OOOF 16 selects the prescaler division ratio by 16 or by 128 When XCIN is selected as the BCLK the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register address OOOF 16 When XIN is selected in BCLK Prescaler division ratio 16 or 128 x watchdog timer count 82768 BCLK Watchdog timer cycle When XCIN is selected in BCLK Prescaler division ratio 2 x watchdog timer count 32768 BCLK Watchdog timer cycle For example when BCLK is 10MHz and the prescaler division ratio is set to 16 the watchdog timer cycle is approximately 52 4 ms The watchdog timer is initialized by writing to the watchdog timer start register
263. eading a port register With the direction register set to output reading a port register takes out the content of the port regis ter not the content of the pin With the direction register set to input reading the port register takes out the content of the pin 3 Effect of the protection register Data written to the direction register of P4 is affected by the protection register The direction register of P4 cannot be easily rewritten 4 Setting pull up The pull up control bit allows setting of the pull up in terms of 4 bits either in use or not in use For the four bits chosen pull up is effective only in the ports whose direction register is set to input Pull up is not effective in ports whose direction register is set to output Do not set pull up of corresponding pin when XCIN XCOUT is set or a port is used as A D input 5 Drive capacity control The drive capacity of the N channel output transistor on P1 can be set between LOW and HIGH in units of 1 bit One bit corresponds to one pin 318 x Cy s Mitsubishi microcomputers ve M30201 Group D SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Ports 6 I O functions of built in peripheral devices Table 2 12 1 shows relation between ports and I O functions of built in peripheral devices Table 2 12 1 Relation between ports and I O functions of built in peripheral devices Port Internal peripheral device I O pins PO key input interrupt functi
264. eceeeeeeeeeeeeeaeeeseaeeseeeeeetaeeneaes 379 5 3 Standard DC Characteristics Flash memory version cceeeeeeeeeeeeeeeeeeeeeaeeeseaeeeseeeeeeaeeteaes 380 5 3 1 Standard Ports Characteristics ccccccccecseeeeeeeeeeeeeeeeeeaeeeceaeeeeeeaeeseeeeeeeaaeeeeeeeeseaeeeeeeeees 380 5 3 2 Characteristics of ICC f XIN cceeeeseeececeeeeeeeee seers eeseaaeseeeeeeceaeeeseaeeeseaeeeseaaeeseeeeeesaeeseeneees 382 5 4 Standard Characteristics of Pull Up Resistor c ccceceececeeeeeeeeeeeceeeeeeeeeeseaeeeeeaeeseeneeesenaeeneaes 383 Quick Reference to Pages Classified by Address Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003Bi6 003C16 003D16 003E16 Register Page Processor mode register 0 PMO Processor mode register 1 PM1 17 System clock control register 0 CMO System clock control register 1 CM1 Address match interrupt enable register AIER 45 Protect register PRCR 28 Watchdog timer start register WDTS Watchdog ti
265. ecking whether interrupt requests are made the interrupt assigned a higher priority is accepted Assign an arbitrary priority to maskable interrupts peripheral I O interrupts using the interrupt priority level select bit If the same interrupt priority level is assigned however the interrupt assigned a higher hardware priority is accepted see Figure 4 5 1 Priorities of the special interrupts such as Reset dealt with as an interrupt assigned the highest priority watchdog timer interrupt etc are regulated by hardware Figure 4 5 2 shows the priorities of hardware interrupts Software interrupts are not affected by the interrupt priority If an instruction is executed control branches invariably to the interrupt routine 366 S xe rs Mitsubishi microcomputers Ss M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER nterrupt zZ Timer BO Timer X2 Timer X0 Timer B1 Timer X1 Priority of peripheral I O interrupts if priority levels are same UART1 reception UARTO reception A D conversion Timer AO UART1 transmission UARTO transmission oO Key input interrupt Figure 4 5 1 Maskable interrupts priorities peripheral I O interrupts Reset gt DBC gt Watchdog timer gt Peripheral I O gt Single step gt Address match Figure 4 5 2 Hardware interrupts priorities 367 4 Mitsubishi microcomputers g S M30201 Group a SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 6 Multi
266. ect bit 0 Counts external signal s falling edge Up down switching cause select bit 0 Up down flag s content 0 Must always be 0 in event counter mode Count operation type select bit 1 Free run type Invalid when not using two phase pulse signal processing 5 Setting up down flag b7 Up down flag Address 038416 UDF 0 0 0 Timer AO up down flag 0 Down count Timer AO two phase pulse signal processing select bit 0 Two phase pulse signal processing disabled 7 Setting trigger select register au Bo Trigger select register Address 038316 SG TRGSR Timer AO event trigger select bit b1 bO 0 0 Input on TAOIN is selected Note Note Set the corresponding port direction register to 0 input mode Setting divide ratio b8 b0 b7 b0 Timer AO register Address 038716 038616 TAO _ Can be set to 000016 to FFFF16 Setting count start flag b7 bo Count start flag Address 038016 TABSR Timer AO count start flag Start count Figure 2 2 15 Set up procedure of event counter mode free run type selected 177 X Ss Q RY Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 2 7 Operation of timer A 2 phase pulse signal process in event counter mode normal mode selected In processing 2 phase pulse signals in event counter mode choose functi
267. ed TX1TGH TXO overflow is selected TX2 overflow is selected TX2TGL Timer X2 event trigger select bit Input on TX2iINoOuT is selected Note TB1 overflow is selected TX2TGH TX1 overflow is selected TAO overflow is selected TX1TGL_ Timer X1 event trigger 00 Note Set the corresponding port direction register to O input mode Clock prescaler reset flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset CPSRF 038116 OXXXXXXX2 Bitsymbol Btname Fma RW Nothing is assigned When write set 0 When read their contents are indeterminate 0 No effect 1 Prescaler is reset When read the value is 0 besarssesk Clock prescaler reset flag Figure 1 40 Timer A related registers 3 52 Timer A Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 1 Timer mode In this mode the timer counts an internally generated count source See Table 1 13 Figure 1 41 shows the timer AO mode register in timer mode Table 1 13 Specifications of timer mode Item Specification Count source f1 f8 32 fe32 Count operation e Down count e When the timer underflows it reloads the reload register contents before continuing counting Divide ratio 1 n 1 n Set value Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing When the
268. ed on both edges Table 1 66 Timer B input pulse period measurement mode Standard Parameter Max TBiIN input cycle time TBiIN input HIGH pulse width TBiiN input LOW pulse width Table 1 67 Timer B input pulse width measurement mode Standard Parameter Max tc TB TBiIN input cycle time tw TBH TBiIN input HIGH pulse width tw TBL TBiIN input LOW pulse width Table 1 68 Timer X input counter input in event counter mode Standard i Max Parameter TXiINOUT input cycle time TXiiNouT input HIGH pulse width TXiiNouT input LOW pulse width Table 1 69 Timer X input gate input in timer mode Standard Parameter Min Max te Tx TXiINOUT input cycle time tw TXH TXiinout input HIGH pulse width tw TXL TXiiNouT input LOW pulse width Table 1 70 Timer X input external trigger input in one shot timer mode Standard Parameter Min Max to TX TXiINOUT input cycle time tw TXH TXiinout input HIGH pulse width tw TXL TXiiNouT input LOW pulse width 123 x So Va O O Electrical characteristics Vcc 3V Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Vcc 3V Timing requirements referenced to Vcc 3V Vss 0V at Ta 25 C unless otherwise specified Table 1 71 Timer X input pulse period measurement mode
269. ed when the address match interrupt address register contents match the program counter value Two address match interrupts can be set each of which can be enabled and disabled by an address match interrupt enable bit Address match interrupts are not affected by the inter rupt enable flag I flag and processor interrupt priority level IPL Figure 1 32 shows the address match interrupt related registers Address match interrupt enable register OE a B0 Symbol Address When reset AIER 000916 XXXXXX002 Bi symbol RW AlERO Address match interrupt O O Interrupt disabled enable bit 4 Interrupt enabled AIER1 Address match interrupt 1 O Interrupt disabled enable bit 1 Interrupt enabled Nothing is assigned When write set 0 When read their contents are indeterminate Address match interrupt register i i 0 1 b19 b16 b15 b8 Symbol Address When reset b3 b0 b7 b0 b7 RMADO 001216 to 001016 X0000016 RMAD1 001616 to 001416 X0000016 Address setting register for address match interrupt 0000016 to FFFFF16 loo Nothing is assigned When write set 0 When read their contents are indeterminate Figure 1 32 Address match interrupt related registers 45 X Se Q s Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Precautions for Interrupts 1 Reading address 0000016 e When maskable interrupt is occurred CPU read the interrupt information
270. ed with it on the M5M28F101 Microcomputer mode 0000016 0040016 YYYYY16 DF00016 Collective erasable programmable DFFFF16 Collective User ROM erasable area programmable FFFFF16 Parallel I O mode Boot ROM area 4K bytes User ROM area CPU rewrite mode Standard serial I O mode Boot ROM area 4K bytes Collective erasable User ROM programmable area Note 1 In CPU rewrite and standard serial I O modes the user ROM is the only erasable programmable area Note 2 In parallel I O mode the area to be erased programmed can be selected by the address A17 input The user ROM area is selected when this address input is high and the boot ROM area is selected when this address input is low XXXXX16 F400016 Type No M30201F6 YYYYY16 OOBFF16 Figure CC 1 Block diagram of flash memory version 135 xX N O S Mitsubishi microcomputers NO M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Parallel I O Mode P61 AN1 P62 AN2 P63 AN3 P64 AN4 P54 CKout ANs4 lt gt P65 AN Apply Vix to this pin L cone when VPP VPPH or P53 CLKS ANs3 lt gt P66 ANe Vit when VPP VPPL P52 CLKo ANs2 lt gt 7 P67 AN7 Step down transformer P51 RxDo ANs1 lt gt 8 POo Klo P50 TxDo ANs0 lt gt 9 P01 Kl1 P02 Kl2 P03 Kl3 Po4 Kl4 POs Kis POs Kle P07 KI7 P71 TB1IN XCIN lt gt P70 TBOIN Xcout lt gt dS94 LOcOEW or oS D o T ez
271. eedback resistor between XCIN and XCOUT following the instruction 19 s S K R S eS Clock Generating Circuit Clock Control Figure 1 17 shows the block diagram of the clock generating circuit XCOUT CM10 1 Sub clock Write signal RESET fd D gt Software reset JA O n clock CM05 CM02 Interrupt request level judgment output B WAIT instruction CMOi Bit i at address 000616 CM1i Bit i at address 000716 WDCi Bit i at address 000F16 Figure 1 17 Clock generating circuit Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER b a ee CM06 0 CMO06 0 CM17 CM16 11 CMO6 1 CM17 CM16 10 O d CM06 0 CM17 CM16 01 oO oO CM06 0 CM17 CM 20 Details of divider O s Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Generating Circuit The following paragraphs describes the clocks generated by the clock generating circuit 1 Main clock The main clock is generated by the main clock oscillation circuit After a reset the clock is divided by 8 to BCLK The clock can be stopped using the main clock stop bit bit 5 at address 000616 Stopping the clock after switching the operating clock source of CPU t
272. eeeeeee 232 2 4 13 Precautions for Timer X one shot timer mode eect ee eteee cette eeee eee eeeeeaeeeeeeeaaeeeeneeea 233 2 4 14 Precautions for Timer X pulse period pulse width measurement mode eee 234 2 4 15 Precautions for Timer X pulse width Modulation mode eee eeeeeeeeeeeeeeeeteeeeeeeeteeeeeeeea 235 2 5 Clock Synchronous Serial VOe iini ieni eaea e r aa aeaa aaaeeeaa aa a aaa aaa a a aaas 236 PE SERON EIA A A A A A A O T 236 2 5 2 Operation of Serial I O transmission in clock synchronous serial I O mode 0 086 242 2 5 3 Operation of the Serial I O transmission in clock synchronous serial I O mode transfer clock output from multiple pins function selected 2 eee eee eeeeeee eee teee eee eeteeeeeeeeeteeeeaeeeeeeneaeeees 246 2 5 4 Operation of Serial I O reception in clock synchronous serial I O Mode ccccceeeee 250 2 5 5 Precautions for Serial I O in clock synchronous Serial I O cccecceesseeeeeteeeeteeeeeneeeees 254 2 6 Clock Asynchronous Serial I O UART ccc ccccceeeeeeeeeececeeeeeeeeeeeaeeeeaaeesecaeeesaaaeeeeeeeesaaeeteeeeeeed 256 2 61 OVOWIOW seag saatiin aa aaa anti aaia a d aaa attested aie det 256 2 6 2 Operation of Serial I O transmission in UART mode esseesseessseesrrssrrnssrnssrrrssrssrrnssse 264 2 6 3 Operation of Serial I O reception in UART mode c ccccceeeeeseeeeeceeeeeeeeseeeeeeeeaaeeeeneeess 268 2a l BRE OIEI NE EAE E ETE c
273. effect 1 Prescaler is reset When read the value is O Setting count start flag b7 b0 Count start flag Address 038016 TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag Start count Clearing overflow flag 00 Timer Xi mode register i 0 to 2 Address 039716 to 039916 Pty lof rxime ico to 2 Timer Xi overflow flag 0 Timer did not overflow Figure 2 4 17 Set up procedure of pulse period measurement mode 225 N O Mitsubishi microcomputers R SF of M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 9 Operation of Timer X pulse width measurement mode In pulse period pulse width measurement mode choose functions from those listed in Table 2 4 8 Op erations of the circled items are described below Figure 2 4 18 shows the operation timing and Figure 2 4 19 shows the set up procedure Table 2 4 8 Choosed functions Count source Internal count source f1 fs f32 fc32 Measurement Pulse period measurement interval between measurement pulse falling edge to falling edge mode Pulse period measurement interval between measurement pulse rising edge to rising edge Pulse width measurement interval between measurement pulse falling edge to rising edge and between rising edge to falling edge Operation 1 Setting the count start flag to 1 causes the counter to sta
274. egisters 358 x Cy N Mitsubishi microcomputers s 5s M30201 Group 2 SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 2 1 Interrupt Enable Flag The interrupt enable flag I flag controls the enabling and disabling of maskable interrupts Setting this flag to 1 enables all maskable interrupts setting it to O disables all maskable interrupts This flag is set to O after reset The content is changed when the flag is changed causes the acceptance of the interrupt request in the following timing e When changing the flag using the REIT instruction the acceptance of the interrupt takes effect as the REIT instruction is executed e When changing the flag using one of the FCLR FSET POPC and LDC instructions the acceptance of the interrupt is effective as the next instruction is executed When changed by REIT instruction Determination whether or not to Interrupt request generated accept interrupt request Previous REIT Interrupt sequence instruction If flag is changed from 0 to 1 by REIT instruction When changed by FCLR FSET POPC or LDC instruction Determination whether or not to Interrupt request generated accept n t request Previous instruction FSET Next instruction Interrupt sequence If flag is changed from 0 to 1 by FSET instruction Figure 4 2 3 The timing of reflecting the change in the flag to the interrupt 4 2 2 Interrupt Request Bit The interrupt request bit is set
275. el 0101 5 MOV B S AND B S BCLR S BNOT CODE_75 ROH dsp 8 SB dsp 8 SB ROH dsp 8 SB ROH dsp 8 SB A1 5 11 SB 5 11 S 0110 6 MOV B S AND B S BCLR S BNOT CODE_76 ROH dsp 8 FB dsp 8 FB ROH dsp 8 FB ROH dsp 8 FB A1 6 11 SB 6 11 S 0111 7 MOV B S AND B S ADD B S MOV B S BCLR S BNOT S CODE_77 ROH abs16 abs16 ROH abs16 ROH abs16 A1 7 14 SB 7 11 SB 1000 8 MOV B S OR B S SUB B S CMP B S BSET S BTST S MUL B ROH ROL ROH ROL ROH ROL ROH ROL 0 11 SB 0 11 SB src dest 1001 9 MOV B S OR B S SUB B S CMP B S BSET S BTST MUL W dsp 8 SB ROL dsp 8 SB ROL dsp 8 SB ROL dsp 8 SB ROL 1 11 SB 1 11 S src dest 1010 A MOV B S OR B S BSET S BTST CODE_7A dsp 8 FB ROL dsp 8 FB ROL dsp 8 FB ROL dsp 8 FB ROL 2 11 SB 2 11 S 1011 B MOV B S OR B S SUB B S CMP B S BSET S BTST JN CODE_7B abs16 ROL abs16 ROL abs16 ROL abs16 ROL 3 11 SB 3 11 SB abel 1100 Cc MOV B S OR B S SUB B S CMP B S BSET S BTST S TU NC CODE_7C ROL ROH ROL ROH ROL ROH ROL ROH 4 11 SB 4 11 SB abel 1101 D MOV B S OR B S SUB B S CMP B S BSET S BTST S JLEU CODE_7D dsp 8 SB ROH dsp 8 SB ROH dsp 8 SB ROH dsp 8 SB ROH 5 11 SB 5 11 SB abel 1110 E MOV B S OR B S BSET S BTST S JNE JNZ CODE_7E dsp 8 FB ROH dsp 8 FB ROH dsp 8 FB ROH dsp 8 FB ROH 6 11 SB 6 11 SB abel 1111 F MOV B S OR B S SUB B S CMP B S BSET S BTST S abs16 ROH abs16 ROH abs16 ROH abs16 ROH 7 11 SB 7 11 SB The next inst
276. elect bit Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority IPL of the routine where the WAIT instruction is executed Reserved bit Must be set to 0 2 Interrupt enable flag I flag lt 1 3 Canceling protect b7 bo Protect register Address 000A16 PRCR addresses 000616 and 000716 1 Write enabled L Enables writing to system clock control registers 0 and 1 3 Setting operation clock after returning from stop mode When operating with XIN after returning System clock control register Address 000616 CMO Main clock XIN XOuT stop bit On b7 b0 eI Te System clock select bit XIN XOUT As this register becomes setting mentioned above when operating with XIN count source of BCLK is XIN the user does not need to set it again When operating with XCIN after returning b0 System clock control register 0 Address 000616 CMO Port Xc select bit XCIN XCOUT generation System clock select bit XCIN XCOUT As this register becomes setting mentioned above when operating with XCIN count source of BCLK is XcIN the user does not need to set it again When operating with XIN set port Xc select bit to 1 before setting system clock select bit to 1 The both bits cannot be se
277. elect register Note 4 MR3 0 Must always be 0 in one shot timer mode TCKO Count source select bit Set the corresponding port direction register to 1 output mode External trigger cannot be selected as count start condition when pulse output function is selected Valid only when the TXiINOUT pin is selected by the event trigger select bit addresses 038316 If timer overflow is selected this bit can be 1 or 0 Set the corresponding port direction register to 0 input mode Pulse output function cannot be selected when TXiINOUT pin is selected by the event trigger select bit addresses 038316 Figure 1 62 Timer Xi mode register in one shot timer mode 71 x Ss Q s Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 4 Pulse period pulse width measurement mode In this mode the timer measures the pulse period or pulse width of an external signal See Table 1 24 Figure 1 63 shows the timer Xi mode register in pulse period pulse width measurement mode Figure 1 64 shows the operation timing when measuring a pulse period Figure 1 65 shows the operation timing when measuring a pulse width Table 1 24 Timer specifications in pulse period pulse width measurement mode Item Specification Count source f1 f8 32 fc32 Count operation e Up count e Counter value 000016 is transferred to reload register at measurement pulse s effecti
278. emory map of address match interrupt related registers Address match interrupt enable register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset AIER 000916 XXXXXX002 Bit symbol Bit name Function Ea Address match interrupt 0 0 Ce ee disabled enable bit Ce ee enabled Eua Address match interrupt 1 4 Interrupt disabled enable bit Interrupt enabled Nothing is assigned When write set 0 When read their contents are indeterminate Address match interrupt register i i 0 1 019 b16 b15 b8 Address When reset E L 001216 to 001016 X0000016 001616 to 001416 X0000016 Address setting register for address match interrupt 0000016 to FFFFF16 loio Nothing is assigned When write set 0 When read their contents are indeterminate Figure 2 9 3 Address match interrupt related registers 303 x Cy Q s Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Address Match Interrupt 2 9 2 Operation of Address Match Interrupt The following is an operation of address match interrupt Figure 2 9 4 shows the set up procedure of address match interrupt and Figure 2 9 5 shows the overview of the address match interrupt handling routine Operation 1 The address match interrupt handling routine sets an address to be used to cause the ad dress match interrupt register to generate an interrupt 2 Setting the address match enable flag to 1 enables an interrupt to occ
279. en timer AO register is read it indicates an indeterminate value Write to timer e When counting stopped When a value is written to timer AO register it is written to both reload register and counter e When counting in progress When a value is written to timer AO register it is written to only reload register Transferred to counter at next reload time Note When set value of H level width is 0016 or 000016 pulse outputs L level and inversion value FF16 or FFFF16 is set to timer Timer AO mode register BF DB D5 104 De Be bI bO Symbol Address When reset 1 1 1 TAOMR 039616 0016 Bit symbol Bit name Function TMODO __ Operation mode b1 bo TMOD1 select bit 11 PWM mode 1 Must always be 1 in PWM mode External trigger select 0 Falling edge of TAO pin s input signal Note 2 bit Note 1 1 Rising edge of TAOIN pin s input signal Note 2 Trigger select bit 0 Count start flag is valid 1 Selected by event trigger select register 16 8 bit PWM mode 0 Functions as a 16 bit pulse width modulator select bit 1 Functions as an 8 bit pulse width modulator _ b7 b6 Count source select bit 0 0 f4 01 fs 10 f32 TORI 11 fese Note 1 Valid only when the TAOIN pin is selected by the event trigger select bit addresses 038316 If timer overflow is selected this bit can be 1 or 0 Note 2 Set the corresponding port direction register to O input mode
280. ence pened dena eeg ee gies dene P338 e 3 5 Solution for external interrupt pins shortage e ee ceeeceeeeceeeeeeeeeeeeeeeeeeeeesaaeeseneeeesaeeeseneees P340 e 3 6 Controlling power USING stop MOE cccceeeeeeeeeeeeeeeeeeeeeneeeceaeeeeeaaeeseaeeeesaaaeseeeeeesaaeeneaeees P342 e 3 7 Controlling power USING Wait Mode ceceecececeeeeeeeeeeeeaeeeeeeeecaaeeeseeeeseaeeeseaaeseceeeeetaeeneneees P346 324 Ss Mitsubishi microcomputers we M30201 Group e SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Applications 325 N A Mitsubishi microcomputers PS SF of M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications 3 1 Long Period Timers Overview In this process Timer XO and Timer X1 are connected to make a 16 bit timer with a 16 bit prescaler Figure 3 1 1 shows the operation timing Figure 3 1 2 shows the connection dia gram and Figures 3 1 3 and 3 1 4 show the set up procedure Use the following peripheral functions e Timer mode of timer X e Event counter mode of timer X Specifications 1 Set timer XO to timer mode and set timer X1 to event counter mode 2 Perform a count on count source f1 using timer XO to count for 1 ms and perform a count on timer XO using timer X1 to count for 1 second 3 Connect a 10 MHz oscillator to XIN Operation 1 Setting the count start flag to 1 causes the counter to begin counting The counter of timer XO performs a down count on count source
281. enenees P188 162 N A Mitsubishi microcomputers FK S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A 2 Count source The internal count source can be selected from f1 fs f32 and fc32 Clocks f1 f8 and f32 are derived by dividing the CPU s main clock by 1 8 and 32 respectively Clock fc32 is derived by dividing the CPU s secondary clock by 32 3 Frequency division ratio In timer mode or pulse width modulation mode the value set in the timer register 1 becomes the frequency division ratio In event counter mode the set value 1 becomes the frequency division ratio when a down count is performed or FFFF16 the set value 1 becomes the frequency division ratio when an up count is performed In one shot timer mode the value set in the timer register be comes the frequency division ratio The counter overflows or underflows when a count source equal to a frequency division ratio is input and an interrupt occurs For the pulse output function the output from the port varies the value in the port register does not vary 4 Reading the timer Either in timer mode or in event counter mode reading the timer register takes out the count at that moment Read it in 16 bit units The data either in one shot timer mode or in pulse width modulation mode is indeterminate 5 Writing to the timer To write to the timer register when a count is in progress the value is written only to the reload register
282. ep mode Donaci iioii n n R S O P284 Repeated Sweep mode Taosrendiiroroniiiininiiriiiiiit ritn A EEEE TEE P286 5 Input to A D converter and direction register To use the A D converter set the direction register of the relevant port to input 6 Pins related to A D converter a ANo pin through AN7 pin Input pins of the A D converter Port P6 group b AN50 pin through AN57 pin Input pins of the A D converter Port P5 group c AVcc pin Power source pin of the analog section d VREF pin Input pin of reference voltage e AVss pin GND pin of the analog section 273 A K Ss ww A D Converter Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 7 A D converter and related registers Figure 2 7 1 shows the memory map of A D converter related registers and Figures 2 7 2 through 2 7 4 show A D converter related registers 004E16 A D conversion interrupt control register ADIC x a 03C016 A D register 0 ADO 03C116 030216 A D register 1 AD1 03C316 030416 A D register 2 AD2 030516 03C616 A D register 3 AD3 03C716 03C816 A D register 4 AD4 03C916 03CA16 A D register 5 AD5 O3CBi6 ahs A D register 6 AD6 oscDi6e register 6 03CE16 e a 03CFie register 7 a a Figure 2 7 1 Memory map of A D converter related registers 274 x N O aS Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Convert
283. er A D control register 0 Note 1 b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset TT Jo Abcone 03D616 00000XXX2 Bitsymbol Bitname Funcion RW Analog input pin select bit 0 0 ANo is selected AN1 is selected om AN2 is selected CHO CH1 AN8 is selected CH2 AN4 is selected AN5 is selected iid AN6 is selected AN7 is selected A D operation mode One sh select bit 0 One shot mode Repeat mode Single sweep mode Repeat sweep mode 0 Repeat sweep mode 1 Set this bit to 0 A D conversion start flag 0 A D conversion disabled ADST 1 A D conversion started CKSO Frequency select bit 0 0 faD 4 is selected 1 fap 2 is selected Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 AN50 to ANs54 can be used in the same way as for ANo to AN4 Figure 2 7 2 A D converter related registers 1 275 N amp Mitsubishi microcomputers s Ss M30201 Group F SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter A D control register 1 Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset eR Ie hia E 03D716 0016 A D sweep pin select bit When single sweep and repeat sweep mode 0 are selected b1 b0 0 0 ANo AN1 2 pins 0 1 ANo to AN3 4 pins 1 0 ANo to AN5 6 pins 1 1 ANo to AN7 8 pins When repeat sweep mode 1 is selected ANo 1 pin ANo AN1 2 pins ANo to AN2 3 p
284. er UOMR 03A116 UARTO bit rate generator UOBRG a UARTO t t buff ter UOTB aha ransmit buffer register i 03A416 UARTO transmit receive control register 0 UOCO i i 03A516 UARTO transmit receive control register 1 U0C1 03A616 03A716 03A816 UART1 transmit receive mode register U1MR 03A916 UART1 bit rate generator U1BRG O3AA16 03AB16 03AC16 UART1 transmit receive control register 0 U1C0 03AD16 UART1 transmit receive control register 1 U1C1 O3AE16 O3AF 16 03B016 UART transmit receive control register 2 UCON UARTO receive buffer register VORB UART1 transmit buffer register U1TB UART1 receive buffer register U1 RB Figure 2 6 2 Memory map of UARTi related registers 260 Mitsubishi microcomputers Sis M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UARTIi transmit buffer register b15 b8 Symbol Address When reset b7 b0_b7 U0TB 03A316 O3A216 Indeterminate U1TB O3ABi16 03AA16 Indeterminate Transmit data Nothing is assigned When write set 0 When read their contents are indeterminate UARTI receive buffer register b15 b8 Symbol Address When reset bo br UORB 03A716 03A616 Indeterminate U1RB 03AF16 03AE1s Indeterminate Bit Function During clock Function Receive data Receive data Nothing is assigned When write set 0 When read the value of these bits is 0 OER Overrun error flag 0 No overrun error
285. er 1 RMAD1 005316 UART1 transmit interrupt control register S1TIC 001616 005416 UART1 receive interrupt control register S1RIC 001716 005516 Timer AO interrupt control register TAOIC 001816 005616 Timer XO interrupt control register TXOIC 001916 005716 Timer X1 interrupt control register TX1IC 001A16 005816 Timer X2 interrupt control register TX2IC 001Bis 005916 001Ci6 005A16 Timer BO interrupt control register TBOIC 001Di6 005B1e Timer B1 interrupt control register TB1IC 001E16 005Ci6 001F 16 005D16 INTO interrupt control register INTOIC 002016 005E16 INTT interrupt control register INTTIC 002116 005F16 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Figure 1 7 Location of peripheral unit control registers 1 10 O S Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 038016 Count start flag TABSR 03C016 038116 Clock prescaler Fee tea CPSRF o3c116 A D register 0 ADO 038216 One shot start flag ONSF
286. er 7016 Acceptable N 5 Clear status register 5046 M f Address Address Not 6 Read lockbit status 7116 middle high acceptable Address Address Address ID size ID1 To ID7 Acceptable 7 ID check function F546 low middle high 8 D joad functi Size Size Check Data To Not Ai aaa FA16 low high sum input required acceptable number of times 9 Version data output function FB Acceptable Address Address Not 14 Boot area output function FC4e middle high deceotable Note1 Shading indicates transfer from flash memory microcomputer to serial programmer All other data is transferred from the serial programmer to the flash memory microcomputer Note2 SRD refers to status register data SRD1 refers to status register 1 data Note3 All commands can be accepted when the flash memory is totally blank 148 N S Mitsubishi microcomputers D oS S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode Page Read Command This command reads the specified page 256 bytes in the flash memory sequentially one byte at a time Execute the page read command as explained here following 1 Send the FF16 command code in the 1st byte of the transmission 2 Send addresses As to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec tively 3 From the 4th byte onward data Do D7 for the page 256 bytes specified with addresses As to A23 w
287. eral function e Event counter mode of timer X Specifications 1 Inputting a falling edge to the TXOINOUT pin generates a timer XO interrupt Operation 1 Set timer XO to event counter mode set timer to 0 and set interrupt priority levels in timer XO 2 Inputting a falling edge to the TXOINOUT pin generates a timer XO interrupt 340 xe sf Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications n Initialization of timer X0 b7 b0 b0 Timer XO register Timer XO mode register 0 0 0 0 O Oj Oj 1 TXOMR Address 039716 TXO Address 038916 038816 Selection of event counter mode Pulse output function select bit 0 Pulse is not output TXOINOUT pin is a normal port pin Count polarity select bit 0 Counts external signal s falling edge 0 Must al ways be 0 in event counter mode 0 Must always be 0 in event counter mode Count operation type select bit 0 Reload type 0 Must always be 0 in event counter mode b7 bo 1 r ti petit Count slart flag Address 038016 Timer XO count start flag 1 Starts counting b7 b0 T T ofo Le register Address 038316 l Timer XO event trigger select bit b3 b2 0 0 Input on TXOINOUT is selected Setting interrupt priority levels in timer XO Timer XO interrupt control register Address 005616 TXOIC Interrupt control level set a
288. erase operations Before this can be accom plished a CPU write control program must be written into the boot ROM area in parallel input output mode The following shows a CPU rewrite mode operation procedure lt Start procedure Note 1 gt 1 Apply VPPH to the CNVss VPP pin and Vcc tothe port P52 pin for reset release Or the user can jump from the user ROM area to the boot ROM area using the JMP instruction and execute the CPU write control program In this case set the CPU write mode select bit of the flash memory control register to 1 before applying VPPH tothe CNVss VPP pin 2 After transferring the CPU write control program from the boot ROM area to the internal RAM jump to this control program in RAM Theoperations described below are controlled by this program 3 Set the CPU rewrite mode select bit to 1 4 Read the CPU rewrite mode monitor flag to see that the CPU rewrite mode is enabled 5 Execute operation on the flash memory by writing software commands to the flash command regis ter Note 1 In addition to the above various other operations need to be performed such as for entering the data to be written to flash memory from an external source e g serial I O initializing the ports and writing to the watchdog timer lt Clearing procedure gt 1 Apply Vss to the CNVSs VPP pin 2 Set the CPU rewrite mode select bit to O 129 A Q lt Mitsubishi microcomputers DO M30201 Group SINGLE
289. ers Key matrix scan b7 bo OTH Port P3 register Address 03E516 P3 Key scan data 1110 1101 1011 0111 Me Decision of key input data a b7 T ero a P3 register Address 03E5416 3 Lt ft Key scan data KS Restore the registers C REIT instruction J Figure 3 6 4 Set up procedure of controlling power using stop mode 2 345 N g Mitsubishi microcomputers Ok Sty M30201 Group x SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications 3 7 Controling Power Using Wait Mode Overview The following are steps for controling power using wait mode Figure 3 7 1 shows the operation timing and Figures 3 7 2 to 3 7 4 show the set up procedure Use the following peripheral functions e Timer mode of timer B e Wait mode A flag named F WIT is used in the set up procedure The purpose of this flag is to decide whether or not to clear wait mode If F_WIT 1 in the main program the wait mode is entered if F_WIT 0 the wait mode is cleared Specifications 1 Connect a 32 768 kHz oscillator to XCIN to serve as the timer count source As interrupts occur every one second which is a count the timer reaches the controller returns from wait mode and count the clock using a program 2 Clear wait mode if a INTO interrupt request occurs Operation 1 Switch the system clock from XIN to XCIN to get low speed mode 2 Stop XIN an
290. es an up count or down count in the event counter mode depending on the phase of the two input signals Operation of the 2 phase pulse signal processing function in normal event counter mode P178 Operation of the 2 phase pulse signal processing function in 4 multiplication mode P180 c One shot timer mode In this mode the timer is started by the trigger and stops when the timer goes to 0 The trigger can be selected from the following 3 types an external input signal an overflow of the timer or a software trigger The pulse output function can also be selected Please refer to the timer mode explanation for details as the operation is identical e Operation in one shot timer mode effected by software ccceceeeeeeeeeeeeteeeeteeteseeeettaeeteneees P182 e Operation in one shot timer mode effected by an external trigger cccccceseeeeeeeeeeesteeeeeeees P184 d Pulse width modulation PWM mode In this mode the arbitrary pulses are successively output Either a 16 bit fixed period PWM mode or 8 bit variable period mode can be selected The trigger for initiating output can also be selected Please refer to the one shot timer mode explanation for details as the operation is identical 16 bit PWM MmOde Ope rations si scescadcesnit Hevesi anew ceeneaneeeynit a AERE EE ENER P186 B bit PWM mode Operation 0 0 ceeccccceceseccceeeeeeeceeeeeeseeaeeeeeneecaeeeensaeeeaeeesaaeeeeeesseeaeeeeseeeeaee
291. esponding port is pulled oio PUO1 P04 to P07 pull up high with a pull up resistor O 0 PU02 P10 to P13 pull up H Bi h 0 0 PU03 P14 to P17 pull up O O PU06 P30 to P33 pull up 10 0 PU07 P34 to P35 pull up Figure 2 10 2 key input interrupt related registers 307 N O Mitsubishi microcomputers R SF of M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Key Input Interrupt 2 10 2 Operation of Key Input Interrupt The following is an operation of key input interrupt Figure 2 10 3 shows an example of a circuit that uses the key input interrupt Figure 2 10 4 shows an example of operation of key input interrupt and Figure 2 10 5 shows the setting procedure of key input interrupt Operation 1 Set the direction register of the ports to be changed to key input interrupt pins to input and set the pull up function 2 Setting the key input interrupt control register and setting the interrupt enable flag makes the interrupt enabled state ready 3 If a falling edge is input to either Klo through KI7 the key input interrupt request bit goes to 1 P30 P31 P32 P33 gt 1 0 port POo Klo P01 Kl P02 KI2 POs KI3 P04 Kl4 POs KI5 P06 Kle P07 Ki7 Figure 2 10 3 Example of circuit using the key input interrupt 1 Enter to stop mode 2 Cancel stop mode 3 Key scan i Key matrix scan 4 Enter to stop
292. etting been made in the stack base register SB Only if using the SB Checks regarding the internal memory L Does the RAM capacity used in the program exceed the RAM capacity of the microcomputer LI Does the ROM capacity used in the program exceed the ROM capacity of the microcomputer Checks regarding the protect register L Is writing enabled in the protect register address 000A16 before writing in the system clock control register addresses 000616 and 000716 L Is writing enabled in the protect register before writing in the processor mode register addresses 000416 and 000516 L Is writing enabled in the protect register before writing in the port P4 direction register address O3EA16 L Is writing effectuated in the port P4 direction register by the next instruction after writing is enabled in the protect register _ Does not an interrupt generate between the instruction writing is enabled in the protect register and the instruction writing in the port P4 direction register 384 O RX Mitsubishi microcomputers Sr M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix 1 Checks regarding the timer _ Is the timer started after a value is set in the timer register Checks regarding low power consumption _ In the low power consumption mode does not current flow from Vref when the Vref connection bit bit 5 in address 03D716 is set L Is not voltage level of port floating in the low power co
293. event counter mode multiply by 4 mode selected 181 xX N O aS Mitsubishi microcomputers Sy M30201 Group ae A SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Imer 2 2 9 Operation of Timer A one shot timer mode In one shot timer mode choose functions from those listed in Table 2 2 9 Operations of the circled items are described below Figure 2 2 20 shows the operation timing and Figure 2 2 21 shows the set up procedure Table 2 2 9 Choosed functions Count source Internal count source f1 fs f32 fc32 Pulse output function No pulses output Pulses output Count start condition External trigger input falling edge of input signal to the TAOIN pin External trigger input rising edge of input signal to the TAOIN pin Timer overflow TB1 TX0 TX2 overflow Writing 1 to the one shot start flag Operation 1 Setting the one shot start flag to 1 with the count start flag set to 1 causes the counter to perform a down count on the count source At this time the TAQOUT pin outputs an H level 2 The instant the value of the counter becomes 000016 the TAOQOUT pin outputs an L level and the counter reloads the content of the reload register and stops counting At this time the timer AO interrupt request bit goes to 1 3 If a trigger occurs while a count is in progress the counter reloads the value in the reload register again and continues counting The
294. example if 10 bit resolution is used and if VREF reference voltage 5 12 V then 1 LSB width becomes 5 mV and 0 mV 5 mV 10 mV 15 mV 20 mV are used as analog input voltages If analog input voltage is 25 mV absolute accuracy 3LSB refers to the fact that actual A D conversion falls on a range from 00216 to 00816 though an output code 00516 can be ex pected from the theoretical A D conversion characteristics Zero error and full scale error are included in absolute accuracy Also all the output codes for analog input voltage between VREF and AVcc becomes 3FF 16 Output code result of A D conversion Theoretical A D conversion characteristic 10 15 20 25 30 35 40 45 50 55 Analog input voltage mV Figure 2 7 20 Absolute accuracy 10 bit resolution 293 N S Mitsubishi microcomputers aes Sy M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter Differential non linearity error Differential non linearity error refers to the difference between 1 LSB width based on the theoretical A D conversion characteristics an analog input width that can meet the expectation of outputting an equal code and an actually measured 1 LSB width analog input voltage width that outputs an equal code If 10 bit resolution is used and if VREF reference voltage 5 12 V differential non linearity error 1LSB refers to the fact that 1 LSB width actually measured
295. f 1 s set e Error sum flag This flag is set 1 when any of the overrun framing and parity errors is encountered e Sleep mode selection This mode is used to transfer data to and from one of multiple slave micro computers Interrupt request gen eration timing Error detection Select function Note 1 n denotes the value 0016 to FF 16 that is set to the UART bit rate generator Note 2 fEXT is input from the CLKO pin Since UART1 does not have this pin cannot select external clock Note 3 If an overrun error occurs the UARTIi receive buffer will have the next data written in Note also that the UARTI receive interrupt request bit is not set to 1 B 86 x O lt Mitsubishi microcomputers DVO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock asynchronous serial I O UART mode UARTIi transmit receive mode registers b7 b6 b5 b4 b3 b2 bi bd Symbol Address When reset UiMR i 0 1 03A016 03A816 0016 SMDO Serial I O mode select bit 521 5 SMD1 100 Transfer data 7 bits long 101 Transfer data 8 bits long SMD2 110 Transfer data 9 bits long re CKDIR Internal external clock 0 Internal clock select bit Note 1 External clock STPS Stop bit length select bit 0 One stop bit 1 Two stop bits PRY Odd even parity Valid when bit 6 1 select bit 0 Odd parity 1 Even parity PRYE Parity enable bit 0 Parity disabled 1 Parity enabled SLEP Sleep selec
296. falls on a range from 0 mV to 10 mV though 1 LSB width based on the theoretical A D conversion characteristics is 5 mV see 5 2 A D converter s standard characteristics Output code result of A D conversion 1LSB width for theoretical A D conversion characteristic Differential non linear error 15 20 2 30 35 40 45 Analog input voltage mV Figure 2 7 21 Differential non linearity error 10 bit resolution 294 x N O X Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 11 Internal Equivalent Circuit of Analog Input Figure 2 7 22 shows the internal equivalent circuit of analog input Parasitic ON resistor diode ON resistor approx 0 6k approx 2k Wiring resistor ANO approx 0 2k Analog input voltage l ON resistor Parasitic h 5k diode i A approx 5 Sampling control signal l i ladder type E switches i ladder type wiring is 10 resistors i 10 Chopper type amplifier A D successive conversion 2 b1 bo i register A D control register 0 Peference control j signal Comparison voltage ON resistor approx 0 6k ADT A D conversion interrupt request Comparison reference voltage Vref generator Sampling Comparison Connect to O SW1 conducts only on the ports selected for analog input Control signal SW2 and SW3 are open when A D conversion is not in for SW2 progress their status varies a
297. fications 1 Sound a 2 kHz buzz beep by use of timer XO 2 Effect pull up in the relevant port by use of a pull up resistor When the buzzer is off set the port high impedance and stabilize the potential resulting from pulling up 3 Connect a 10 MHz oscillator to XIN Operation 1 The microcomputer begins performing a count on timer X0 Timer X0 has disabled interrupts 2 P43 is TXOINOUT pin Setting the port P43 direction register to 1 output mode and outputs 2 kHz pulses 3 The microcomputer stops outputting pulses by setting the port P43 direction register to 0 input mode P43 goes to an input pin and the output from the pin becomes high impedance 1 Start count 2 Buzzer output ON 3 Buzzer output OFF Timer X0 overflow timing i Count start flag g i Port P43 direction 1 register ag P43 output High impedance High impedance Figure 3 4 1 Operation timing of buzzer output 338 x N amp sf Mitsubishi microcomputers ve M30201 Group D SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications Initialization of port P4 direction register b0 7 Protect register Address 000A16 ed ee PRCR Enables writing to port P4 direction register 1 Write enabled Port P4 direction register Address 03EA16 PD4 Port P43 direction register 0 Input mode Initialization of timer X0 b7 b0 b15 b8 b7 b0 3 Timer XO register 0 110 T
298. from TXiINOUT pin q Cleared to 0 when interrupt request is accepted or cleared by software Timer Xi interrupt 1 Va request bit we Oe Note n 000016 to FFFE16 Figure 2 4 20 Operation timing of pulse width modulation mode 16 bit PWM mode selected 228 x N amp os Mitsubishi microcomputers ve M30201 Group D SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Selecting PWM mode and functions Timer Xi mode register i 0 to 2 Address 039716 to 039916 TXiMR i 0 to 2 Selection of PWM mode 1 Must always be 1 in PWM mode 0 1 1 11 Invalid in event counter mode Can be 0 or 1 Trigger select bit 1 Selected by event trigger select register 16 8 bit PWM mode select bit 0 Functions as a 16 bit pulse width modulator Count source select bit b7 b6 Count Count source period b7 b6 source f Xin 10MHz f Xcin 32 768kHz ae foo h 10ms aa CRIE fe 800ns 110 1 1 10 f32 1 1 fc32 fa2 3 2us fc32 976 56us Note Set the corresponding port direction register which outputs the pulse to 1 output mode NX 7 Clearing timer Xi interrupt request bit Refer to Precaution for Timer X pulse width modulation mode b7 bo Timer Xi interrupt control register i 0 to 2 Address 005616 to 005816 DOPPI xic ot 3 G i Interrupt request bit N Setting trigger select regis
299. fy commands Note 1 The erase operation is not completed immediately by writing an erase command once The user must always execute an erase verify command after each erase command executed And if verification fails the user need to execute the erase command repeatedly until the verification passes See Figure CC 4 for an example of an erase flowchart Erase verify command A016 The erase verify mode is entered by writing the command code A016 in the first bus cycle and the verify data is output from the data I O pins Do D7 in the second bus cycle Note 1 If any unerased memory location is encountered during erase verify operation be sure to execute erase and erase verify operations one more time In this case however the user does not need to write data 0016 to memory before erasing 141 s S K S eS Appendix Parallel I O Mode Reset command FF16 FF16 The reset command is used to stop the program command or the erase command in the middle of operation After writing command code 4016 or 2016 twice write command code FF 16 in the first bus cycle and the same command code again in the second bus cycle The program command or erase command is disabled with the flash memory placed in read mode SINGLE CHIP Mitsubishi microcomputers M30201 Group 16 BIT CMOS MICROCOMPUTER Program Address first location Loop counter X 0 Write program command Write program data
300. g Timer 2 8 1 Overview The watchdog timer can detect a runaway program using its 15 bit timer prescaler The following is an overview of the watchdog timer 1 Watchdog timer start procedure When reset the watchdog timer is in stopped state Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and causes it to start performing a down count The watchdog timer once started operating cannot be stopped by any means other than stopping conditions 2 Watchdog timer stop conditions The watchdog timer stops in any one of the following states a Period in which the CPU is in stopped state b Period in which the CPU is in waiting state 3 Watchdog timer initialization The watchdog timer is initialized to 7FFF16 in the cases given below and begins a down count a When the watchdog timer writes to the watchdog timer start register while a count is in progress b When the watchdog timer underflows 4 Runaway detection When the watchdog timer underflows a watchdog timer interrupt occurs In writing a program write to the watchdog timer start register before the watchdog timer underflows The watchdog timer interrupt occurs regardless of the status of the interrupt enable flag I flag In processing a watchdog timer interrupt set the software reset bit to 1 to reset software 5 Watchdog timer cycle The watchdog timer cycle varies depending on the BCLK and the frequency division ratio of the
301. g after a write instruction to this register The watchdog timer value is always initialized to 7FFF16 regardless of whatever value is written Figure 2 8 2 Watchdog timer related registers 299 xX Cy O RX Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Watchdog Timer 2 8 2 Operation of Watchdog Timer The following is an operation of the watchdog timer Figure 2 8 3 shows the operation timing and Figure 2 8 4 shows the set up procedure Operation 1 Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and causes it to start a down count 2 With a count in progress writing to the watchdog timer start register again initializes the watchdog timer to 7FFF16 and causes it to resume counting 3 Either executing the WAIT instruction or going to the stopped state causes the watchdog timer to hold the count in progress and to stop counting The watchdog timer resumes count ing after returning from the execution of the WAIT instruction or from the stopped state 4 If the watchdog timer underflows it is initialized to 7FFF16 and continues counting At this time a watchdog timer interrupt occurs 1 Start count 3 In stopped state or WAIT 4 Generate i instruction is executing etc watchdog timer 2 Write operation interrupt 000016 Write signal to the H watchdog timer start register ee Figure 2 8 3 Operation timing
302. g from high speed medium speed mode to stop mode and at a reset When shifting from low speed low power dissipation mode to stop mode the value before stop mode is retained Note 8 fc32 is not included System clock control register 1 Note 1 b7 b6 b5 b4 b3 b2 bi b0 T Telefo Symbol Address When reset CM1 000716 2016 Bit symbol Bit name Function L CM10 All clock stop control bit 0 Clock on Note 4 1 All clocks off stop mode ee sited o es ee e e p e e ne ae select bit Note 2 gt HIGH CM16 Main clock division No division mode select bit 1 Note 3 Division by 2 mode Division by 4 mode Division by 16 mode Note 1 Set bit 0 of the protect register address 000A16 to 1 before writing to this register Note 2 This bit changes to 1 when shifting from high speed medium speed mode to stop mode and at a reset When shifting from low speed low power dissipation mode to stop mode the value before stop mode is retained Note 3 Can be selected when bit 6 of the system clock control register 0 address 000616 is O If 1 division mode is fixed at 8 Note 4 If this bit is set to 1 XouT turns H and the built in feedback resistor is cut off XCIN and XCOUT turn high impedance state Figure 1 18 Clock control registers 0 and 1 22 O s Mitsubishi microcomputers ve M30201 Group d SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Generating Circuit Clock Output
303. g the timer AO register after setting a value in the timer AO register with a count halted but before the counter starts counting gets a proper value Reload caneret TE Ta Te E novvcrn e o reef Time n reload register content Figure 2 2 28 Reading timer AO register 190 xe sf Mitsubishi microcomputers ve M30201 Group Timer A SINGLE CHIP 16 BIT CMOS MICROCOMPUTER l 2 2 14 Precautions for Timer A event counter mode 1 To clear reset the count start flag is set to 0 Set a value in the timer AO register then set the flag to 1 2 Reading the timer AO register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer AO register with the reload timing shown in Figure 2 2 29 gets FFFF16 by underflow or 000016 by overflow Reading the timer AO register after setting a value in the timer AO register with a count halted but before the counter starts counting gets a proper value 3 Please note the standards for the differences between the 2 pulses used in the 2 phase pulse signals input signals to the TAOIN pin and TAQOUT pin as shown in Figure 2 2 30 4 When free run type is selected if count is stopped set a value in the timer AO register again 1 Down count 2 Up count Reload Counter value Counter value tHe p2 1foln in fe FFFD FFFE FFFE n n 1 neadvaue Ta ojee Rewe lereo eere errr oooo n 1 gt gt
304. generates UARTO and UART1 reception interrupt These are interrupts that the serial I O reception generates Timer AO interrupt This is an interrupt that timer A generates e Timer BO interrupt and timer B1 interrupt These are interrupts that timer B generates Timer XO interrupt through timer X2 interrupt e INTO interrupt and INT1 interrupt An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin 354 X Fa SF ww Interrupt Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 4 1 4 Interrupts and Interrupt Vector Tables If an interrupt request is accepted a program branches to the interrupt routine set in the interrupt vector table Set the first address of the interrupt routine in each vector table Two types of interrupt vector tables are available fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting e Fixed vector tables The fixed vector table is a table in which addresses are fixed The vector tables are located in an area extending from FFFDC16 to FFFFF16 One vector table comprises four bytes Set the first address of interrupt routine in each vector table Table 4 1 1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables Table 4 1 1 Interrupts assigned to the fixed vector tables and addresses of vector tables Interrupt source Undefined instructio
305. ghest priority interrupt source request bit to 0 Though the interrupt is generated the interrupt routine may not be executed Do not read address 0000016 by software 2 Setting the stack pointer e The value of the stack pointer immediately after reset is initialized to 000016 Accepting an inter rupt before setting a value in the stack pointer may become a factor of runaway Be sure to set a value in the stack pointer before accepting an interrupt Concerning the first instruction immediately after reset generating any interrupt is prohibited 3 External interrupt When changing a polarity of pins INTO and INT1 the interrupt request bit may become 1 Clear the interrupt request bit after changing the polarity 4 Changing interrupt control register See Changing Interrupt Control Register 111 x N Q aS Mitsubishi microcomputers Sr M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Electrical characteristics Table 1 37 Absolute maximum ratings Parameter Supply voltage Condition Rated value 0 3 to 7 Analog supply voltage 0 3 to 7 Input voltage RESET CNVss POo to P07 P10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 VREF XIN 0 3 to Vcc 0 3 Note 1 Output voltage P0o to P07 P10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 VREF XIN 0 3 to Vcc 0 3 Power dissipation 1000 Note 2 O
306. h each operation mode MR2 MR3 TCKO Count source select bit Note 1 Timer BO Note 2 Timer B1 Figure 1 49 Timer B related registers 1 60 O S Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Address When reset 039116 039016 Indeterminate b15 039316 039216 Indeterminate Function e Timer mode 000016 to FFFF16 Counts the timer s period e Event counter mode 000016 to FFFF16 Counts external pulses input or a timer overflow Note1 Read and write data in 16 bit units Count start flag b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset TABSR 038016 000X00002 1 Starts counting Nothing is assigned When write set 0 When read their contents are indeterminate TBOS Timer BO count start flag 0 Stops counting TB1S Timer B1 count start flag pester couniag 1 1 1 1 1 1 1 t Clock prescaler reset flag b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset CPSRF 038116 OXXXXXXX2 Bit symbol Nothing is assigned When write set 0 When read their contents are indeterminate Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 Figure 1 50 Timer B related registers 2 61 Ni Q V Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 1 Timer mode In this mode the timer counts an internally generated count source See Table 1 18 Figure 1 51 sho
307. he corresponding port direction register to 1 output mode Clearing timer AO interrupt request bit Refer to Precaution for Timer A one shot timer mode b7 bo PPDA Timer AO interrupt control register Address 005516 TAOIC N Interrupt request bit Setting Trigger select register b7 0 Trigger select register Address 038316 bo 0 tRGSR Timer AO event trigger select bit 0 0 Input on TAON is selected Note 2 Note 2 Set the corresponding port direction register to O input mode A b15 b7 Setting one shot timer s time Timer AO register Address 038716 038616 TAO b8 b8 b0 b7 bo a Me Can be set to 000116 to FFFF16 b7 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 LDDDPDDEM PO Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 Setting count start flag b7 b0 EERTE Count start flag Address 038016 TABSR Timer AO count start flag Start count Figure 2 2 23 Set up procedure of one shot mode external trigger selected 185 xX Cy O s Mitsubishi microcomputers Sy M30201 Group ae A SINGLE CHIP 16 BI
308. here The input data suchas address is latched at the falling edge of WE pin The input data such as software command is latched at the rising edge of WE pin 139 4 N g Mitsubishi microcomputers S DO M30201 Group v SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Parallel I O Mode Software Commands Table CC 4 lists the software commands available with the M30201 flash memory version By entering a software command from the data I O pins Do D7 in Write mode specify the content of the operation such as erase or program operation to be performed The following explains the content of each software command Table CC 4 Software command list parallel I O mode First bus cycle Second bus cycle Command Data Data Address Do to D7 Mode Address Do to D7 Read Program Program Program address data Program verify Verify data Erase x 2016 Erase verify Verify Verify address data Reset FF16 Read Command 0016 The read mode is entered by writing the command code 0016 in the first bus cycle When an address to be read is input in one of the bus cycles that follow the content of the specified address is read out at the data I O pins Do D7 The read mode is retained intact until another command is written After reset and after the reset command is executed the read mode is set Program Command 4016 The program mode is entered by writing the command code
309. i 0 to 7 03E016 03E116 03E516 O3E816 Indeterminate TTT IT TTT 03E916 03EC16 O3ED16 Indeterminate Port Pio register oe i Data is input and output to and from i Port Pit register each pin by reading and writing to Port Pi2 register and from each corresponding bit 0 L level data Port Pls register 1 H level data Port Pi4 register i5 Port Pis register i 0to7 except 2 i Port Pie register Pi_7 Port Piz register Note Nothing is assigned in direction register of P36 P37 P46 P47 P55 to p57 P72 to P77 This bit can either be set nor reset When read its content is indeterminate Figure 1 94 Port register 105 Q s Mitsubishi microcomputers Sas M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Port Pull up control register 0 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PURO 03FC16 R moei e E a ae Pull up control register 1 b7 b6 b5 b4 b3 b2 bl b0 Symbol Address When reset PUR1 0016 The corresponding port is pulled high with a pull up resistor E E o o Port P1 drive capacity control register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset DRR 03FE16 0016 R Set P1 N channel output DaRi Port Pts drive capacuty transistor drive capacity 1 HIGH Figure 1 95 Pull up control register 106 O P Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmabl
310. i interrupt request bit ett Cleared to 0 when interrupt request is accepted or cleared by software Figure 2 4 25 Operation timing of PWM output mode 235 N A Mitsubishi microcomputers P S S M30201 Group X SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O 2 5 Clock Synchronous Serial I O 2 5 1 Overview Clock synchronous serial I O carries out 8 bit data communications in synchronization with the clock The following is an overview of the clock synchronous serial I O 1 Transmission reception format 8 bit data 2 Transfer rate If the internal clock is selected as the transfer clock the divide by 2 frequency resulting from the bit rate generator division becomes the transfer rate The bit rate generator count source can be se lected from the following f1 f8 82 and fc Clocks f1 fg and f32 are derived by dividing the CPU s main clock by 1 8 and 32 respectively Clock fc is derived by dividing the CPU s sub clock by 1 respec tively Furthermore if an external clock is selected as the transfer clock the clock frequency input to the CLK pin becomes the transfer rate 3 Error detection Only overrun error can be detected Overrun error is an error that occurs when the next data is made ready before the reception buffer register is read 4 How to deal with an error When receiving data read an error flag and reception data simultaneously to determine which error has occ
311. if the check sum matches the downloaded program is executed The size of the program will vary according to the internal RAM Data size low Check fogram V Program moo Awe A hone feta cat at N Data size high P53 BUSY Figure DD 13 Timing for download 152 N S Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode Version Information Output Command This command outputs the version information of the control program stored in the boot area Execute the version information output command as explained here following 1 Send the FB16 command code in the 1st byte of the transmission 2 The version information will be output from the 2nd byte onward This data is composed of 8 ASCII code characters P53 BUSY Figure DD 14 Timing for version information output Boot Area Output Command This command outputs the control program stored in the boot area in one page blocks 256 bytes Execute the boot area output command as explained here following 1 Send the FC16 command code in the 1st byte of the transmission 2 Send addresses As to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respec tively 3 From the 4th byte onward data Do D7 for the page 256 bytes specified with addresses As to A23 will be output sequentially from the smallest address first in sync with the rise of the clock coms
312. ill be output sequentially from the smallest address first in sync with the rise of the clock As to V A16 to P53 BUSY Figure DD 3 Timing for page read Read Status Register Command This command reads status information When the 7016 command code is sent in the 1st byte of the transmission the contents of the status register SRD specified in the 2nd byte of the transmission and the contents of status register 1 SRD1 specified in the 3rd byte of the transmission are read TxDO 7016 SRD SRD1 PxDO output P53 BUSY Figure DD 4 Timing for reading the status register 149 amp CA r PE E ES Mitsubishi microco puters SE St M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode Clear Status Register Command This command clears the bits SR3 SR4 which are set when the status register operation ends in error When the 5016 command code is sent in the 1st byte of the transmission the aforementioned bits are cleared When the clear status register operation ends the P53 BUSY signal changes from the H to the L level CLKO lll TxDO 5016 RxDO P53 BUSY Figure DD 5 Timing for clearing the status register Page Program Command This command writes the specified page 256 bytes in the flash memory sequentially one byte at a time Execute the page program command as explained here following 1
313. imer B timer mode event counter mode eceeeeeeeeeeeetteeeeeeetteeeeeeeee 206 2 3 7 Precautions for Timer B pulse period pulse width measurement mode 0 cceeeeeees 207 2A TIMONX o ae a e a taae eteaiint entd a a aerials a a 208 2A ROIA EI E T 208 2 4 2 Operation of Timer X timer mode eeeeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeeaeeeeeneeesaeeeseaeeeeeueeeseaeeee 212 2 4 3 Operation of Timer X timer mode gate function Selected ssessesssressrrssrrsssrrssresssees 214 2 4 4 Operation of Timer X timer mode pulse output function selected cceseeeeeeeeeeeeeeees 216 2 4 5 Operation of Timer X event counter mode reload type Selected ceeeceeeeeteeeetteeees 218 2 4 6 Operation of Timer X event counter mode free run type Selected ceeeceeeeeeeereees 220 2 4 7 Operation of Timer X one shot timer mode ceeeeeceeeeeeeeeeeeeeeaeeeeeeeeeteaeeeseaeeeseeeeeeeeeee 222 2 4 8 Operation of Timer X pulse period measurement mode cceeeeeeeeeeeee cesses teeeeeeeeeetees 224 2 4 9 Operation of Timer X pulse width measurement MOE ccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 226 2 4 10 Operation of Timer X pulse width modulation mode 16 bit PWM mode selected 228 2 4 11 Operation of Timer X pulse width modulation mode 8 bit PWM mode selected 230 2 4 12 Precautions for Timer X timer mode event Counter mode eect eetteeeeeeetteee
314. imer XO mode register 0 0 0 0 0 TXOMR Address 039716 0016 F916 TXO Address 038916 038816 b7 b0 Selection of timer mode Pulse output function select bit 1 Pulse is output Gate function select bit b4 b3 0 0 Gate function not available 0 Must always be 0 in timer mode Count source select bit b7 b6 b7 be Count Count source period 00 e source f Xin 10MHz f Xcin 32 768kHz 100ns 800ns 3 2us 976 56us Count start flag Address 038016 TABSR Timer X0 count start flag 1 Starts counting Buzzer ON b7 PEX Protect register Address 000A16 PRCR Enables writing to port P4 direction register 1 Write enabled Port P4 direction register Address 03EA16 PD4 Port P43 direction register 1 Output mode Buzzer OFF Protect register Address 000A16 PRCR Enables writing to port P4 direction register 1 Write enabled Port P4 direction register Address 03EA16 PD4 Port P43 direction register 0 Input mode Figure 3 4 2 Set up procedure of buzzer output 339 xX O s Mitsubishi microcomputers DO M30201 Group amp a SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications 3 5 Solution for External Interrupt Pins Shortage Overview The following are solution for external interrupt pins shortage Figure 3 5 1 shows the set up procedure Use the following periph
315. imer Xi interrupt request bit becomes 1 if setting operation mode of the timer in compliance with any of the following procedures e Selecting PWM mode after reset e Changing operation mode from timer mode to PWM mode e Changing operation mode from event counter mode to PWM mode Therefore to use timer Xi interrupt interrupt request bit set timer Xi interrupt request bit to O after the above listed changes have been made 2 Setting the count start flag to O while PWM pulses are being output causes the counter to stop counting If the TXiINOUT pin is outputting an H level in this instance the output level goes to L and the timer Xi interrupt request bit goes to 1 If the TXiINOUT pin is outputting an L level in this instance the level does not change and the timer Xi interrupt request bit does not becomes 1 Timer X pulse period pulse width measurement mode 1 If changing the measurement mode select bit is set after a count is started the timer Xi interrupt request bit goes to 1 2 When the first effective edge is input after a count is started an indeterminate value is transferred to the reload register At this time timer Xi interrupt request is not generated A D Converter 1 Write to each bit except bit 6 of A D control register 0 to each bit of A D control register 1 and to bit 0 of A D control register 2 when A D conversion is stopped before a trigger occurs In
316. in the same way as for ANo to AN4 Note 3 If port P5 group is selected do not select 6 pins and 8 pins sweep mode E Port P6 group is selected ADGSELO Port P5 group is selected Figure 1 87 A D conversion register in single sweep mode 96 xe sf Mitsubishi microcomputers Fe M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 4 Repeat sweep mode 0 In repeat sweep mode 0 the pins selected using the A D sweep pin select bit are used for repeat sweep A D conversion See Table 1 34 Figure 1 88 shows the A D control register in repeat sweep mode 0 Table 1 34 Repeat sweep mode 0 specifications Item Specification Function The pins selected by the A D sweep pin select bit are used for repeat sweep A D conversion Start condition Writing 1 to A D conversion start flag Stop condition Writing 0 to A D conversion start flag Interrupt request generation timing None generated Input pin ANo and AN1 2 pins ANo to AN3 4 pins ANo to AN5 6 pins or ANo to AN7 8 pins Note Reading of result of A D converter Read A D register corresponding to selected pin at any time Note AN50 to AN54 can be used in the same way as for ANo to AN4 A D control register 0 Note b7 b6 p5 b4 53 b2 ibi bO Symbol Address When reset I oh avcono 03D616 00000XXX2 Bit symbol Bit name Function Analog input pin select bit Invalid in repeat sweep mode 0 R b4 b3
317. input cycle time tw TBH TBiIN input HIGH pulse width tw TBL TBiIN input LOW pulse width Table 1 50 Timer X input counter input in event counter mode Standard Parameter Min Max TXiINOUT input cycle time TXiiNouT input HIGH pulse width TXiiNouT input LOW pulse width Table 1 51 Timer X input gate input in timer mode Standard Parameter Min Max te TX TXiINOUT input cycle time tw TXH TXiinouT input HIGH pulse width tw TXL TXiinouT input LOW pulse width Table 1 52 Timer X input external trigger input in one shot timer mode Standard Parameter Min Max te TX TXiinout input cycle time tw TXH TXiinout input HIGH pulse width tw TXL TXiiNouT input LOW pulse width 117 Q s Mitsubishi microcomputers Sr M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 5V Vcc 5V Timing requirements referenced to Vcc 5V Vss 0V at Ta 25 C unless otherwise specified Table 1 53 Timer X input pulse period measurement mode Standard Parameter Min Max TXiINOUT input cycle time TXiINOUT input HIGH pulse width TXiINOUT input LOW pulse width Table 1 54 Timer X input pulse width measurement mode Standard Parameter Min Max te TX TXiiNout input cycle time tw TXH TXiinouT input HIGH pulse width tw TXL TXiiNouT input LOW pulse width
318. ins Note 2 3 ANo to AN8 4 pins A D operation mode 0 Any mode other than repeat sweep select bit 1 mode 1 Repeat sweep mode 1 BITS 8 10 bit mode select bit 0 8 bit mode 1 10 bit mode CKS1 Frequency select bit 1 0 faD 2 or faD 4 is selected 1 fAD is selected Vref connect bit 0 Vref not connected VCUT 1 Vref connected joo Set this bit to 0 Di a 0 Port P6 group is selected ADGSELO A D input group select bit 1 Port P5 group is selected o0 Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 ANso to AN54 can be used in the same way as for ANo to AN4 Note 3 If the repeat sweep mode is selected for the port P5 group the contents of A D registers 5 to 7 are indeterminate Figure 2 7 3 A D converter related registers 2 276 x N O aS Mitsubishi microcomputers Sr M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter A D control register 2 Note b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset ONN ofo Of ADCON2 03D416 XXXX00002 RW SMP A D conversion method 0 Without sample and hold select bit 1 With sample and hold Reserved bit Always set to 0 TE ca ime ft 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 L 4 Nothing is assigned When write set 0 When read their content is indeterminate Note If the A D control register is rewritten during A D conversion the c
319. instruction used 360 x Cy amp s Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 2 4 Rewrite the interrupt control register To rewrite the interrupt control register do so at a point that does not generate the interrupt request for that register If there is possibility of the interrupt request occur rewrite the interrupt control register after the interrupt is disabled The program examples are described as follow Example 1 INT_SWITCH1 FCLR Disable interrupts AND B 00h 0055h Clear TAOIC int priority level and int request bit NOP Four NOP instructions are required when using HOLD function NOP FSET Enable interrupts Example 2 INT_SWITCH2 FCLR Disable interrupts AND B 00h 0055h Clear TAOIC int priority level and int request bit MOV W MEM RO Dummy read FSET Enable interrupts Example 3 INT_SWITCHS PUSHC FLG Push Flag register onto stack FCLR Disable interrupts AND B 00h 0055h Clear TAOIC int priority level and int request bit POPC FLG Enable interrupts The reason why two NOP instructions four when using the HOLD function or dummy read are inserted before FSET in Examples 1 and 2 is to prevent the interrupt enable flag from being set before the interrupt control register is rewritten due to effects of the instruction queue When a instruction to rewrite the interrupt control register is executed b
320. interrupt Table 1 9 shows the settings of interrupt priority levels and Table 1 10 shows the interrupt levels enabled according to the consist of the IPL The following are conditions under which an interrupt is accepted interrupt enable flag I flag 1 interrupt request bit 1 interrupt priority level gt IPL The interrupt enable flag I flag the interrupt request bit the interrupt priority select bit and the IPL are independent and they are not affected by one another Table 1 9 Settings of interrupt priority levels Table 1 10 Interrupt levels enabled according to the contents of the IPL Interrupt priority Interrupt priority Priority IPL icval ecloct bit j vel order Enabled interrupt priority levels IPL2 IPL1 IPLo b2 bi bO Level 0 0 0 0 Interrupt levels 1 and above are enabled 0 0 interrupt disabled 0 0 0 1 Level 1 Low 0 Interrupt levels 2 and above are enabled O 1 0 Level 2 0 Interrupt levels 3 and above are enabled 0 1 1 Level 3 0 Interrupt levels 4 and above are enabled 1 0 0 Level 4 Interrupt levels 5 and above are enabled 1 0 1 Level 5 Interrupt levels 6 and above are enabled 1 1 0 Level 6 1 1 1 Level 7 High Interrupt levels 7 and above are enabled All maskable interrupts are disabled 36 RA NOO Ro c N amp O x Interrupts Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER
321. interrupts peripheral I O interrupts using the interrupt priority level select bit If the same interrupt priority level is assigned however the interrupt assigned a higher hardware priority is accepted Priorities of the special interrupts such as Reset dealt with as an interrupt assigned the highest priority watchdog timer interrupt etc are regulated by hardware Figure 1 29 shows the priorities of hardware interrupts Software interrupts are not affected by the interrupt priority If an instruction is executed control branches invariably to the interrupt routine Interrupt Priority Level Judge Circuit This circuit selects the interrupt with the highest priority level when two or more interrupts are generated simultaneously Figure 1 30 shows the interrupt resolution circuit 42 O amp Mitsubishi microcomputers Sas M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Reset gt DBC gt Watchdog timer gt Peripheral I O gt Single step gt Address match Figure 1 29 Hardware interrupts priorities Priority level of each interrupt Level 0 initial value INT1 Timer BO High Timer X2 KEK EK ERK EK EK EEK Er Ek EK Ek Timer X0 INTO Timer B1 Timer X1 UART1 reception UARTO reception A D conversion Timer AO Priority of peripheral I O interrupts if priority levels are same UART1 transmission UARTO transmission Key input interrupt Processor interrupt priority level IPL
322. invalid Inhibited Inhibited Inhibited 000 n nao 0 One stop bit 1 Two stop bits PRY Odd even parity select bit Invalid Parity enable bit Invalid Valid when bit 6 1 Odd parity Even parity Parity disabled Parity enabled Sleep select bit Must always be 0 Note 1 UART1 cannot be used in clock synchronous serial I O Note 2 UART1 can use only internal clock Must set this bit to 1 UARTi transmit receive control register 0 b7 b6 b5 b4 b3 b2 bi bO Address 03A416 03AC16 When reset 0816 Symbol UiCO i 0 1 Function Note Bit name During clock synchronous serial I O mode b1 b0 0 0 f1 is selected 0 1 f8 is selected 1 0 f32 is selected 11 fc is selected Bit symbol 4 CLKO BRG count source select bit Sleep mode deselected Sleep mode selected Function During UART mode b1 b0 00 f1 is selected 0 1 fs is selected 10 f32 is selected 11 fc is selected Set this bit to 0 Data present in transmit register during transmission No data present in transmit register transmission completed TXEPT Transmit register empty Set this bit to 1 Data present in transmit register during transmission No data present in transmit register transmission completed TXDi pin is CMOS output TXDi pin is N channel open drain output Data output select bit Transmit data is output at falling
323. iod Count source Measurement pulse 1 Transfer Transfer Transfer Transfer g indeterminate measured value yw measured g measured value value a we ea i Reload register counter transfer timing si Aeon peed i Nets 1 Note Timing at which counter reaches 000016 Count start flag Timer Bi interrupt request bit a A A Cleared to 0 when interrupt request is accepted or cleared by software Timer Bi overflow flag l Note 1 Counter is initialized at completion of measurement Note 2 Timer has overflowed Figure 1 55 Operation timing when measuring a pulse width 65 N O S Mitsubishi microcomputers GG M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Timer X Figure 1 56 shows the block diagram of timer X Figures 1 57 to 1 59 show the timer X related registers Use the timer Xi mode register bits 0 and 1 to choose the desired mode Timer X has the five operation modes listed as follows e Timer mode The timer counts an internal count source e Event counter mode The timer counts pulses from an external source or a timer overflow e One shot timer mode The timer stops counting when the count reaches 000016 e Pulse period pulse width measuring mode The timer measures an external signal s pulse period or pulse width e Pulse width modulation PWM mode The timer outputs pulses of a given width Data bus high order bits Clock sour
324. iodically by use of software increases program reliability Note 2 When an external clock is input to the XIN pin 319 xX Se xe Ss Mitsubishi microcomputers SF of M30201 Group og SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Ports 8 Registers related to the programmable I O ports Figure 2 12 1 shows the memory map of programmable I O ports related registers and Figures 2 12 2 to 2 12 4 show programmable I O ports related registers 03E016 Port PO PO S BSEMe Pon PIPI O O OOO OO O O 03E216 Port PO direction register PDO 03E316 Port P1 direction register PD1 oM o S OSESt6 PortP3 P3 Koa ee 03E716 Port P3 direction register PD3 O3E816 Port PAPO 03E916 Port P5 P5 S o3Ec1e Pon P6 PE aw AS 03FC16 Pull up control register O PURO 03FD16 Pull up control register 1 PUR1 03FE16 Port P1 drive control register DRR Figure 2 12 1 Memory map of programmable I O ports related registers 320 x N amp os Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Programmable I O Ports Port Pi direction register Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset PDi i 0 to 7 03E216 03E316 03E716 03EA16 0016 03EB16 03EE16 03EF16 PDio Pon Pio direction register Port Pi1 direction register a eo an input port 1 Output mode Functions as an output port i 0107 except 2 PDie Port Pie direction register Note 1
325. ion of IPL when Interrupt Request is Accepted If an interrupt request is accepted the interrupt priority level of the accepted interrupt is set in the IPL If an interrupt request that does not have an interrupt priority level is accepted one of the values shown in Table 4 3 2 is set in the IPL Table 4 3 2 Relationship between interrupts without interrupt priority levels and IPL Interrupt sources without priority levels Value set in the IPL Watchdog timer 7 Reset 0 Other Not changed xX O R Mitsubishi microcomputers S M30201 Group F SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 3 3 Saving Registers In the interrupt sequence only the contents of the flag register FLG and that of the program counter PC are saved in the stack area First the processor saves the four higher order bits of the program counter and 4 upper order bits and 8 lower order bits of the FLG register 16 bits in total in the stack area then saves 16 lower order bits of the program counter Figure 4 3 3 shows the state of the stack as it was before the acceptance of the interrupt request and the state the stack after the acceptance of the interrupt request Save other necessary registers at the beginning of the interrupt routine using software Using the PUSHM instruction alone can save all the registers except the stack pointer SP Stack area Stack area Address Address SB MSB SP Program counter PC New stack pointer valu
326. ion of one shot timer mode Pulse output function select bit Note 1 Pulse is output External trigger select bit Invalid when choosing timer s overflow as trigger Trigger select bit 1 Selected by event trigger select register 0 Must always be 0 in one shot timer mode ronn source select bit Count Count source period 00 f1 gt SOUrCe f XiN 10MHz_ f Xcin 32 768kHz 100ns 800ns 3 2us 976 56us Note Set the corresponding port direction register to 1 output mode Continued to the next page Figure 3 2 3 Set up procedure of variable period variable duty PWM output 1 332 S amp amp Mitsubishi microcomputers SS M30201 Group ka ee SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications Continued from the previous page Setting trigger select register b7 b0 Trigger select register Address 038316 I ilo tR sR E Timer X1 event trigger select bit b5 b4 1 0 TXO overflow is selected Setting one shot timer s time b15 b8 bz bobr b0 Timer X1 register Address 038B16 038A16 Setting count start flag bo XI Tii Sag flag Address 038016 Timer X0 count start flag 1 Starts counting Timer X1 count start flag 1 Starts counting Start counting Figure 3 2 4 Set up procedure of variable period variable duty PWM output 2 333 S L ys ASS eS Mitsubishi microc
327. ion selected In timer mode choose functions from those listed in Table 2 4 2 Operations of the circled items are described below Figure 2 4 6 shows the operation timing and Figure 2 4 7 shows the set up procedure Table 2 4 2 Choosed functions Count source Internal count source f1 fs f32 fc32 Pulse output function No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TXiINOUT pin is at L level Performs count only for the period in which the TXiINoUT pin is at H level Operation 1 When the count start flag is set to 1 and the TXiINOUT pin inputs at H level the counter performs a down count on the count source 2 When the TXiINOUT pin inputs at L level the counter holds its value and stops 3 If an underflow occurs the content of the reload register is reloaded and the count continues At this time the timer Xi interrupt request bit goes to 1 4 Setting the count start flag to O causes the counter to hold its value and to stop Note e Make the pulse width of the signal input to the TXiINOUT pin not less than two cycles of the count source n reload register content 1 Start count 3 Underflow 2 Stop count to 7 4 Stop count Counter content hex Start count again Cleared to O by Time Software E D 1 by software Count start flag o TXiiNouT
328. iting 1 to A D conversion start flag Stop condition Writing 0 to A D conversion start flag Interrupt request generation timing None generated Input pin One of ANo to AN7 as selected Note Reading of result of A D converter Read A D register corresponding to selected pin Note AN50 to AN54 can be used in the same way as for ANo to AN4 A D control register 0 Note 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset T olo ABcono 03D616 00000XXX2 ooo 2 po ee Oooo o Tr 0 AN0 is selected AN1 is selected AN2 is selected AN8 is selected AN4 is selected AN5 is selected AN6 is selected AN7 is selected Analog input pin select bit 0 0 0 Og A D operation mode select bit 0 Set this bit to 0 ADST A D conversion start flag 0 A D conversion disabled 1 A D conversion started Frequency select bit 0 0 fAD 4 is selected CKSO j 1 fAD 2 is selected Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 AN50 to AN54 can be used in the same way as for ANo to AN4 A D control register 1 Note D7 IDG IBS Abe BS Des Bi b0 Address When reset S LLLI Acon a a Bit symbol Bit name Function hor ot ot 1 1 4 44 SCANO A D sweep pin select bit Invalid in repeat mode SCAN1 MD2 A D operation mode Set this bit to 0 in this mode select bit 1 BITS 8 10 bit mod
329. its MSB LSB conversion circuit T D7 De Ds Dai Ds D2 D1 Do VARTI transmit buffer register UART 8 bits UART 9 bits Clock UART 9 bits synchronous type PAR 2SP enabled O p Hie B l oo LHH O P O 1 F 7 S PERE UART 7 bits UART 7 bits UARTi transmit register t UART 8 bits ge Clock SP Stop bit synchronous PAR Parity bit type Note UART1 cannot be used in clock synchronous serial I O Figure 1 70 Block diagram of transmit receive unit 77 Serial I O UARTI transmit buffer register b8 Symbol Address When reset b0 b7 UOTB 03A316 03A216 Indeterminate U1TB 03AB16 03AA16 Indeterminate Transmit data Nothing is assigned When write set 0 When read their contents are indeterminate UARTI receive buffer register b8 Symbol Address When reset 50 b7 UORB 03A716 03A616 Indeterminate U1RB 03AF16 03AE16 Indeterminate Function During clock Function RW synchronous aa 1 0 During UART mode RW mode i Receive data Receive data Nothing is assigned When write set 0 When read the value of these bits is 0 Ta OER Overrun error flag re No overrun error 0 No overrun error Note Overrun error found 1 Overrun error found Framing error flag Invalid T No framing error Note Framing error found O Parity error flag Invalid 0 No parity error Note 1 Parity error found
330. itsubishi microcomputers So OX M30201 Group ko ee SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications Continued from the previous page Setting trigger select register Corer oo register Address 038316 Timer X1 event trigger select bit b5 b4 10 TXO overflow is selected Setting divide ratio b15 b8 bz bo br bo Timer X1 register Address 038B16 038A16 Setting count start flag S T ou san flag Address 038016 Timer XO count start flag 1 Starts counting Timer X1 count start flag 1 Starts counting Start counting Figure 3 1 4 Set up procedure of long period timers 2 329 N O amp Mitsubishi microcomputers Sas M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications 3 2 Variable Period Variable Duty PWM Output Overview In this process Timer XO and A1 are used to generate variable period variable duty PWM out put Figure 3 2 1 shows the operation timing Figure 3 2 2 shows the connection diagram and Figures 3 2 3 and 3 2 4 show the set up procedure Use the following peripheral functions e Timer mode of timer X e One shot timer mode of timer X Specifications 1 Set timer XO in timer mode and set timer X1 in one shot timer mode with pulse output function 2 Set 1 ms the PWM period to timer X0 Set 500 us the width of PWM H pulse to timer X1 Both timer XO and timer X1 use f1 for the count source 3 Connect
331. ivide by 4 of fAD fAD f XIN Vcc 3V divide by 2 of fab divide by 4 of fAD fAD f XIN Resolution 8 bit or 10 bit selectable Absolute precision Vcc 5V e Without sample and hold function 3LSB e With sample and hold function 8 bit resolution 2LSB e With sample and hold function 10 bit resolution 3LSB Vcc 3V e Without sample and hold function 8 bit resolution 2LSB Operating modes One shot mode repeat mode single sweep mode repeat sweep mode 0 and repeat sweep mode 1 Analog input pins 8 pins ANo to AN7 5 pins AN50 to AN54 A D conversion start condition e Software trigger A D conversion starts when the A D conversion start flag changes to 1 Conversion speed per pin Without sample and hold function 8 bit resolution 49 oAD cycles 10 bit resolution 59 AD cycles e With sample and hold function 8 bit resolution 28 oAD cycles 10 bit resolution 33 AD cycles Note 1 Does not depend on use of sample and hold function Note 2 Without sample and hold function set the oAD frequency to 250kHz min With the sample and hold function set the oAD frequency to 1MHz min 90 N s Mitsubishi microcomputers ww SS M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter CKS1 1 O o AD cksi o A D conversion rate selection Resistor ladder PETE Successive conversion register A D control register 1 address 03D716
332. k Synchronous Serial I O Example of wiring Microcomputer TxDo P50 CLKS P53 CLKo P52 Note This applies when performing only transmission with an internal clock selected in the clock synchronous serial I O mode Example of operation 1 Transmission enabled 3 Transmission is complete 2 Start transmission 4 Clock switched Transfer clock LIUUUUUUU UU UU i Transmit enable bit Transmit buffer empty flag CLK CLKS select bit 1 CLK CLKS select bit 0 eo anni noo 702000 O D O OCOC Transmit interrupt request bit 0 a Cleared to 0 when interrupt request is accepted or cleared by software Figure 2 5 8 Operation timing of transmission in clock synchronous serial I O mode transfer clock output from multiple pins function selected 247 N S Clock Synchronous Serial I O Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER b7 bo o o of 4 Setting UARTO transmit receive mode register UARTO transmit receive mode register UOMR Address 03A016 Must be fixed to 001 Internal external clock select bit 0 Internal clock Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Sleep select bit Must be 0 in clock synchronous I O mode b7 0 0 E o
333. l Count up all edges Count down all edges TAOIN Note This does not apply when the free run function is selected 55 N amp Mitsubishi microcomputers xe S Si O M30201 Group a SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Timer AO mode register When using two phase pulse signal processing b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset Jofifofofo i TAOMR 039616 0016 E ES TMODO Operation mode select bit i d P TMOD1 vent counter mode 0 Must a be 0 when using two phase pulse signal dsa 0 Must always be 0 when using two phase pulse signal processo Must always be 1 when using two phase pulse signal i rian MR3 0 Must always be 0 when using two phase pulse signal processing TCKO Count operation type 0 Reload type select bit 1 Free run type Two phase pulse processing operation 0 Normal processing operation select bit Note 1 Multiply by 4 processing operation Note When performing two phase pulse signal processing make sure the two phase pulse signal processing operation select bit address 038416 is set to 1 Also always be sure to set the event trigger select bit addresses 038316 to 00 Figure 1 43 Timer AO mode register in event counter mode 56 Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 3 One shot timer mode In this mode the timer operates only once See Table 1 16 When a trigger
334. l processing Setting divide ratio i b8 b0 b7 bO DOSS DO o OE Timer AO register Address 038716 038616 TAO oo Can be set to 000016 to FFFF16 C l J Setting count start flag b7 b0 Count start flag Address 038016 HEBT TABSR Timer AO count start flag Start count Figure 2 2 17 Set up procedure of 2 phase pulse signal process in event counter mode normal mode selected 179 A we lt se gt Timer A Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 2 2 8 Operation of timer A 2 phase pulse signal process in event counter mode multiply by 4 mode selected In processing 2 phase pulse signals in event counter mode choose functions from those listed in Table 2 2 7 Operations of the circled items are described below Figure 2 2 18 shows the operation timing and Figure 2 2 19 shows the set up procedure Table 2 2 7 Choosed functions Count operation type Reload type Processing 2 phase Normal processing O Free run type pulses 0 4 multiplication processing Operation 1 Setting the count start flag to 1 causes the counter to count effective edges of the count source 2 Even if an underflow occurs the content of the reload register is not reloaded but the count continues At this time the timer AO interrupt request bit goes to 1 3 Even if an overflow occurs the content of the reload
335. leared by software Timer Xi interrupt request bit Timer Xi overflow flag g Note 1 Counter is initialized at completion of measurement Note 2 Timer has overflowed Figure 2 4 16 Operation timing of pulse period measurement mode 224 x N amp os Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Selecting pulse period pulse width measurement mode and functions b7 b0 SZ Timer Xi mode register i 0 to 2 Address 039716 to 039916 EEXEENI Kiise Selection of pulse period pulse width measurement mode Measurement mode select bit b3 b2 0 0 Pulse period measurement Interval between measurement pulse falling edge to falling edge Timer Xi overflow flag 0 Timer did not overflow 1 Timer has overflowed 1 Must always be 1 in pulse period pulse width measurement mode Count source select bit b7 b6 Count Count source period source f XIN 10MHz_ f XcIN 32 768kHz 01 100ns 10 i 800ns ii 3 2us 976 56us Note Set the corresponding port direction register which sets the measurement pulse to 0 input mode 2 i a S Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 b0 Clock prescaler reset flag Address 0381 16 LADD CPSRF Clock prescaler reset flag 0 No
336. led A D conversion started Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 ANso to AN54 can be used in the same way as for ANo to AN4 A D control register 1 Note D7 RG D5 D103 p2 he Symbol Address When reset hd ADCON1 03D716 0016 io i Bit symbol rii A D sweep pin select bit Invalid in one shot mode Por ob i i kad SCAN A D operation mode Set this bit to 0 in this mode select bit 1 8 10 bit mode select bit i 8 bit mode 10 bit mode Frequency select bit 1 0 faD 2 or fAD 4 is selected CKS1 1 faD is selected VCUT Vref connect bit 1 Vref connected joo MD2 Set this bit to 0 Di 10 Port P6 group is selected ADGSELO A D input group select bit 1 Port P5 group is selected o o Note If the A D control register is rewritten during A D conversion the conversion result is indeterminate Figure 1 85 A D conversion register in one shot mode 94 wv g Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 Repeat mode In repeat mode the pin selected using the analog input pin select bit is used for repeated A D conversion See Table 1 32 Figure 1 86 shows the A D control register in repeat mode Table 1 32 Repeat mode specifications A E e Function The pin selected by the analog input pin select bit is used for repeated A D conversion Start condition Wr
337. level width nx m 1 fi n values set to timer Xi register s high order address Cycle time 28 1 x m 1 fi m values set to timer Xi register s low order address Count start condition The timer overflows The count start flag is set 1 Count stop condition The count start flag is reset 0 Interrupt 8 bits PWM Set value of H level width is except FF16 0016 PWM pulse goes L request Set value of H level width is FF16 0016 Timing that count value goes to 0116 generation 16 bits PWM Set value of H level width is except FFFF16 000016 PWM pulse goes L timing Set value of H level width is FFFF16 000016 Timing that count value goes to 000116 TXiINOUT pin function Pulse output Read from timer When timer Xi register is read it indicates an indeterminate value Write to timer When counting stopped When a value is written to timer Xi register it is written to both reload register and counter e When counting in progress When a value is written to timer Xi register it is written to only reload register Transferred to counter at next reload time Note When set value of H level width is 0016 or 000016 pulse outputs L level and inversion value FF16 or FFFF 16 is set to timer Timer Xi mode register Bi b6 p5 be b3 b2 bt bo Address When reset JIII bhii TAME 0to2 039716 to 039916 0016 iiid ip eoma Seme n TMODO Operation mode b1 bo TMOD1
338. listed in Table 2 2 10 Operations of the circled items are described below Figure 2 2 22 shows the operation timing and Figure 2 2 23 shows the set up procedure Table 2 2 10 Choosed functions Count source Internal count source f1 fs f32 fc32 Pulse output function No pulses output Pulses output Count start condition External trigger input falling edge of input signal to the TAOIN pin External trigger input rising edge of input signal to the TAOIN pin Timer overflow TB1 TX0 TX2 overflow Writing 1 to the one shot start flag Operation 1 If the TAOIN pin input level changes from L to H with the count start flag set to 1 the counter performs a down count on the count source At this time the TAOOUT pin output level goes to H level 2 If the value of the counter becomes 000016 the TAOOUT pin outputs an L level and the counter reloads the content of the reload register and stops counting At this time the timer AO interrupt request bit goes to 1 3 If a trigger occurs while a count is in progress the counter reloads the value of the reload register again and continues counting The reload timing is in step with the next count source input after the trigger 4 Setting the count start flag to O causes the counter to stop and to reload the content of the reload register Also the TAOOUT pin outputs an L level At this time the
339. lled by a hardware reset or an interrupt If an interrupt is to be used to cancel stop mode that interrupt must first have been enabled If returning by an interrupt that interrupt routine is executed When shifting from high speed medium speed mode to stop mode and at a reset the main clock division select bit 0 bit 6 at address 000616 is set to 1 When shifting from low speed low power dissipation mode to stop mode the value before stop mode is retained Table 1 4 Port status during stop mode States Port CLKOUT Retains status before stop mode H When fc selected When fg clock devided counter output selected Retains status before stop mode Wait Mode When a WAIT instruction is executed BCLK stops and the microcomputer enters the wait mode In this mode oscillation continues but BCLK and watchdog timer stop Writing 1 to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions allowing power dissipation to be reduced Table 1 5 shows the status of the ports in wait mode Wait mode is cancelled by a hardware reset or interrupt If an interrupt is used to cancel wait mode the microcomputer restarts from the interrupt routine using as BCLK the clock that had been selected when the WAIT instruction was executed Table 1 5 Port status during wait mode Pin States Port Retains status before wait mode CLKOU
340. m TAOOUT pin Timer AO interrupt request bit 4 0 H L Underflow signal of 8 bit H dd H L ie 0 Figure 2 2 26 Operation timing of pulse width modulation mode with 8 bit PWM mode selected 188 N S Mitsubishi microcomputers x SS M30201 Group T A SINGLE CHIP 16 BIT CMOS MICROCOMPUTER imer Selecting PWM mode and function b7 po Timer AO mode register Address 039616 TAOMR Selection of PWM mode 1 Must always be 1 in PWM mode 1 DE External trigger select bit 0 Falling edge of TAOIN pin s input signal Note 1 Trigger select bit 1 Selected by event trigger select register 16 8 bit PWM mode select bit 1 Functions as an 8 bit pulse width modulator Count source select bit i Count Count source period b7 b6 i source f XIN 10MHz f Xcin 32 768kHz 00 f1 i 01 fs i 100ns 10 f32 800ns 1 1 fc32 3 2us 976 56us Note 1 Set the corresponding port direction register which outputs the pulse to 1 output mode Clearing timer AO interrupt request bit Refer to Precaution for Timer A pulse width modulation mode b7 bd PECADO TL Timer AO interrupt control register Address 005516 TAOIC Interrupt request bit as Setting trigger select register b7 b0 Trigger select register Address 038316 CEREC TRGSR Timer AO event trigger sele
341. mands CPU Rewrite Mode Read 03B616 First bus cycle Second bus cycle Command Data Data Address Do to D7 Mode Address Do to D7 Program 03B616 Program Program address data Program verify 03B616 Verify Verify address data Erase 03B616 03B616 2016 Erase verify 03B616 Verify Verify address data Reset 03B616 FF16 Read Command 0016 The read mode is entered by writing the command code 0016 to the flash command register in the first bus cycle When an address to be read is input in one of the bus cycles that follow the content of the specified address is read out at the data bus Do D7 8 bits at a time The read mode is retained intact until another command is written After reset and after the reset command is executed the read mode is set Program Command 4016 The program mode is entered by writing the command code 4016 to the flash command register in the first bus cycle When the user execute an instruction to write byte data to the desired address e g STE instruction in the second bus cycle the flash memory control circuit executes the program op eration The program operation requires approximately 20 us Wait for 20 us or more before the user go to the next processing During program operation the watchdog timer remains idle with the value 7FFF 16 set in it Note 1 The write operation is not completed immediately by writing a program comma
342. mer control register WDC 48 Address match interrupt register 0 RMADO 45 Address match interrupt register 1 RMAD1 45 Address Register Page 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004Die Key input interrupt control register KUPIC 004E16 A D conversion interrupt control register ADIC 2 004F16 005016 005116 UARTO transmit interrupt control register SOTIC 005216 UARTO receive interrupt control register SORIC 005316 UART1 transmit interrupt control register S1TIC 005416 UART1 receive interrupt control register S1RIC 35 005516 _ Timer AO interrupt control register TAOIC 005616 _ limer XO interrupt control register TXOIC 005716 Timer X1 interrupt control register TX1IC 005816 _ Timer X2 interrupt control register TX2IC 005916 005A16 _limer BO interrupt control register TBOIC 005B16 _ Timer B1 interrupt control register TB1IC oe 005C16 005D16 INTO interrupt control register INTOIC 005E16 _INT1 interrupt control register INT1IC 005F16 Quick Reference to Pages Classified by Address
343. mit 0 Transmit buffer empty Transmit buffer empty interrupt cause select bit T509 TI 1 1 Transmission completed ee ee completed TXEPT 1 TXEPT 1 UART1 transmit Set this bit to 0 acre buffer empty interrupt cause select bit m i Transmission completed TXEPT 1 UARTO continuous Continuous receive Invalid receive mode enable bit mode disabled Continuous receive mode enable Set this bit to 0 CLKMDO CLK CLKS select bit 0 Valid when bit 5 1 Invalid Clock output to CLK1 Clock output to CLKS1 1 CLKMD1 CLK CLKS select 0 Normal mode Must always be 0 bit 1 Note 2 CLK output is CLKO only Transfer clock output from multiple pins function selected Nothing is assigned When write set 0 When read its content is indeterminate Note 1 UART1 cannot be used in clock synchronous serial I O Note 2 When using multiple pins to output the transfer clock the following requirements must be met e UARTO internal external clock select bit bit 3 at address 03A016 0 Figure 2 5 4 Serial l O related registers 3 241 N A Mitsubishi microcomputers FS Sty M30201 Group 4 SINGLE CHIP 16 BIT CMOS MICROCOMPUTER gt Clock Synchronous Serial I O 2 5 2 Operation of Serial I O transmission in clock synchronous serial I O mode In transmitting data in clock synchronous serial I O mode choose functions from those listed in Table 2 5 1 Operati
344. mode P30 output P31 output P32 output P33 output P04 to P07 input y y y Key input Key OFF Key ON Key OFF Key ON Key input interrupt processing r Figure 2 10 4 Example of operation of key input interrupt e a 308 N O Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Key Input Interrupt Setting port P10 direction register b7 bO PET Tr Port PO direction register Address 03E216 PDO 0 Input mode Functions as an input port 1 Output mode Functions as an output port Setting pull up control register 0 b7 bO Pull up control register 0 Address 03FC16 PURO 1 Pulled high P0o to POs 1 Pulled high P04 to P07 Setting interrupt control register b7 bO iw Key input interrupt control register Address 004D16 DSA 5 0 Mr acl i EE Interrupt priority level select bit b2 b1 bO 0 0 Level 0 interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Interrupt request bit 0 Interrupt not requested Figure 2 10 5 Set up procedure of key input interrupt 309 xX Cy O Ss Mitsubishi microcomputers Sy M30201 Group og SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Power Control 2 11 Power Control 2 11 1 Overview Power Control refers to the reduction of CPU power consumption by stopping the CPU and oscillators or decreasing the operation clo
345. mode Can be 0 or 1 Count polarity T Counts external signal s falling edge select bit Note 3 Counts external signal s rising edge 0 Must always be fixed to 0 in event counter mode TCKO Count operation type A Reload type select bit Free run type TCK1 Invalid in event counter mode Can be 0 or 1 Note 1 Count source is selected by event trigger select bit address 038316 in event counter mode Note 2 Set the corresponding port direction register to 1 output mode TXiINOUT pin input is not selected as count source when pulse output function is selected Note 3 This bit is valid when only counting an external signal Figure 1 61 Timer Xi mode register in event counter mode 70 x A xe S Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 3 One shot timer mode In this mode the timer operates only once See Table 1 23 When a trigger occurs the timer starts up and continues operating for a given period Figure 1 62 shows the timer Xi mode register in one shot timer mode Table 1 23 Timer specifications in one shot timer mode Specification Count source f1 fa f32 fC32 Count operation The timer counts down When the count reaches 000016 the timer stops counting after reloading a new count e Ifa trigger occurs when counting the timer reloads a new count and restarts counting Divide ratio 1 n n Set value Co
346. n Vector table addresses Address L to address H FFFDC16 to FFFDF16 Remarks Interrupt on UND instruction Overflow FFFE016 to FFFE316 Interrupt on INTO instruction BRK instruction FFFE416 to FFFE716 If the vector contains FF 16 program execution starts from the address shown by the vector in the variable vector table Address match FFFE816 to FFFEBi6 There is an address matching interrupt enable bit Single step Note FFFEC16 to FFFEF 16 Do not use Watchdog timer FFFFO16 to FFFF316 DBC Note FFFF416 to FFFF716 Do not use FFFF816 to FFFFB16 Reset Note Interrupts used for debugging purposes only FFFFC16 to FFFFF 16 355 xX Cy xe S Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt Variable vector tables The addresses in the variable vector table can be modified according to the user s settings Indicate the first address using the interrupt table register INTB The 256 byte area subsequent to the ad dress the INTB indicates becomes the area for the variable vector tables One vector table comprises four bytes Set the first address of the interrupt routine in each vector table Table 4 1 2 shows the interrupts assigned to the variable vector tables and addresses of vector tables Table 4 1 2 Interrupts assigned to the variable vector tables and addresses of vector tables Vector table add
347. n in Table 1 12 is set in the IPL Table 1 12 Relationship between interrupts without interrupt priority levels and IPL Interrupt sources without priority levels Value set in the IPL Watchdog timer 7 Reset 0 Other Not changed 39 N Q amp Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Saving Registers In the interrupt sequence only the contents of the flag register FLG and that of the program counter PC are saved in the stack area First the processor saves the 4 high order bits of the program counter and 4 high order bits and 8 low order bits of the FLG register 16 bits in total in the stack area then saves 16 low order bits of the program counter Figure 1 27 shows the state of the stack as it was before the acceptance of the interrupt request and the state the stack after the acceptance of the interrupt request Save other necessary registers at the beginning of the interrupt routine using software Using the PUSHM instruction alone can save all the registers except the stack pointer SP Address Stack area Address Stack area MSB LSB SB SP Program counter PC New stack pointer value Program counter PCm gt Flag register FLG Flag register Program SP FLGu counter PCH Content of previous stack a an Geral Content of previous stack interrupt occurs Content of previous stack Content of previous stack a ed
348. n one shot mode and one shot sweep mode 312 x Cy xe Ss Mitsubishi microcomputers ve M30201 Group d SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Power Control 5 Sequence of returning from stop mode Sequence of returning from stop mode is oscillation start up time and interrupt sequence When interrupt is generated in stop mode CM10 becomes 0 and clearing stop mode Starting oscillation and supplying BCLK execute the interrupt sequence as follow In the interrupt sequence the processor carries out the following in sequence given a CPU gets the interrupt information the interrupt number and interrupt request level by read ing address 0000016 The interrupt request bit of the interrupt written in address 0000016 will then be set to 0 b Saves the content of the flag register FLG as it was immediately before the start of interrupt sequence in the temporary register Note within the CPU c Sets the interrupt enable flag I flag the debug flag D flag and the stack pointer assignment flag U flag to O the U flag however does not change if the INT instruction in software interrupt numbers 32 through 63 is executed d Saves the content of the temporary register Note within the CPU in the stack area e Saves the content of the program counter PC in the stack area f Sets the interrupt priority level of the accepted instruction in the IPL Note This register cannot be utilized by the user
349. nd once The user must always execute a program verify command after each program command executed And if verification fails the user need to execute the program command repeatedly until the verification passes See Figure 1 BB 3 for an example of a programming flowchart 131 N Q aS Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CPU Rewrite Mode Program verify command C016 The program verify mode is entered by writing the command code C016 to the flash command register in the first bus cycle When the user execute an instruction e g LDE instruction to read byte data from the address to be verified the previously programmed address in the second bus cycle the content that has actually been written to the address is read out from the memory The CPU compares this read data with the data that it previously wrote to the address using the program command If the compared data do not match the user need to execute the program and program verify operations one more time Erase command 2016 2016 The flash memory control circuit executes an erase operation by writing command code 2016 to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle The erase operation requires approximately 20 ms Wait for 20 ms or more before the user go to the next processing Before this erase command can be performed
350. nd the stack pointer select flag U flag to 0 the U flag however does not change if the INT instruction in software interrupt numbers 32 through 63 is executed 4 Saves the content of the temporary register Note 1 within the CPU in the stack area 5 Saves the content of the program counter PC in the stack area 6 Sets the interrupt priority level of the accepted instruction in the IPL After the interrupt sequence is completed the processor resumes executing instructions from the first address of the interrupt routine Note This register cannot be utilized by the user 4 3 1 Interrupt Response Time Interrupt response time is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment a and the time required for executing the interrupt sequence b Figure 4 3 1 shows the interrupt response time Interrupt request generated Interrupt request acknowledged Instruction Interrupt sequence _ Instruction in interrupt routine Interrupt response time a Time from interrupt request is generated to when the instruction then under execution is completed b Time in which the instruction sequence is executed Figure 4 3 1 Interrupt response time SSS SSS SSS SS lt 362 xe as Mitsubishi micr
351. ndeterminate In both the pulse period measurement mode and pulse width measurement mode an indeterminate value is read until the second effective edge is input after a count is started otherwise the measurement results are read 5 Writing to the timer When writing to the timer register while a count is in progress the value is written only to the reload register When writing to the timer register while a count has stopped the value is written both to the reload register and the count Write the value in 16 bit increments The timer register cannot be written to in either the pulse period measurement mode or the pulse width measurement mode 6 Relation between the input output to from the timer and the direction register With the output function of the timer set the direction register of the relevant port to input To input an external signal to the timer set the direction register of the relevant port to input However pulse output cannot be selected when inputting an external signal to the timer and vice versa 7 Pins related to timer X a TXOINOUT TX1INOUT TX2INOUT Input output pins to timer X 8 Registers related to timer X Figure 2 4 1 shows the memory map of timer X related registers Figures 2 4 2 and 2 4 3 show timer X related registers 005616 Timer XO interrupt control register TXOIC 005716 Timer X1 interrupt control register TX1IC 005816 Timer X2 interrupt control register TX2IC 038016 Count
352. ne design Data sheet and data book Contents Hardware specifications pin assignment memory map specifications of peripheral functions electrical characteristics timing charts Hardware a al Detail design of system User s manual Detailed description about hardware specifi cations operation and application examples connection with peripherals relationship with software Programming manual Method for creating programs using assem bly and C languages Hard 2 ware Software manual Software System evaluation M16C Family Line up M16C 80 Series M16C Family M16C 60 Series M16C 20 Series Detailed description about operation of each instruction assembly language M16C 80 Group M16C 60 Group M16C 61 Group M16C 62 Group M16C 20 Group M16C 21 Group Table of Contents Chapter 1 Hardware DOSCIDTION asea ne e EA EAT ag aattieataeenenea day NE acta eee einen et veda die dai he 2 MO MOPY soniais ioi AEEA T ENA ee UL A a ak a 9 Central Processing Unit CPU ccccececceeeeeeeeeeeeeeeeeaaeeceaeeeecaaeeeeneeecaaeeeeeneeeseaeesesaaeeseeeeesaeeseenees 12 e A E adn niie oe a ie diel i aia 15 Software Reset nre r aaae a enti eee eden eet as 17 Software Walt ta sseeg iaiia tinal anne Rad na aa See edie 18 Clock Generating Circuit sre aea annaran dees aeaaee aad ae aaa aaa cea she taraia aar danena daa 19
353. ng edge Pulse width measurement Interval between measurement pulse s falling edge to rising edge and between rising edge to falling edge Inhibited Timer Xi overflow 0 Timer did not overflow flag Note 1 Timer has overflowed Count source select bit Note The timer Xi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer Xi mode register This flag cannot be set to 1 by software Figure 1 63 Timer Xi mode register in pulse period pulse width measurement mode 72 N g S S x Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X When measuring measurement pulse time interval from falling edge to falling edge Count source Measurement pulse indeterminate value Fa measured value Reload register counter transfer timing i i i i i i i i Transfer Transfer i i i i i i Timing at which counter reaches 000016 Count start flag Timer Xi interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software Timer Xi overflow flag Be Note 1 Counter is initialized at completion of measurement Note 2 Timer has overflowed Figure 1 64 Operation timing when measuring a pulse period Count source Measurement pulse Transfer Transfer Transfer yg indeterminate Iw measured jy measured value 7 1 value A val
354. ng operation mode from event counter mode to PWM mode Therefore to use timer Xi interrupt interrupt request bit set timer Xi interrupt request bit to 0 after the above listed changes have been made 3 Setting the count start flag to O while PWM pulses are being output causes the counter to stop counting If the TXiINOUT pin is outputting an H level in this instance the output level goes to L and the timer Xi interrupt request bit goes to 1 If the TXiINOUT pin is outputting an L level in this instance the level does not change and the timer Xi interrupt request bit does not becomes 1 4 Normal PWM output is restored according to the interrupt request generate timing both in the case of 16 bit PWM and 8 bit PWM when PWM output is either H or L level for the entire period This holds only when a value other than 000016 or FFFF 16 is set during 16 bit PWM or a value other than 0016 or FF 16 is set during 8 bit PWM l l Normal PWM restored here When PWM output is H level for the entire period Writing to the ims i 1 4 X n PWM pulse output from TXiINOUT pin Timer Xi interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software When PWM output is L level for the entire period Writing to the i 1 fi X n timer Xi PWM pulse output H l from TXiINOUT pin i i I L Timer X
355. ng the receive enable bit to 1 and the transmit enable bit to 1 makes the data receivable status ready 2 In synchronization with the first rising edge of the transfer clock the input signal to the RxDO pin is stored in the highest bit of the UARTO receive register Then data is taken in by shifting right the content of the UARTO reception data in synchronization with the rising edges of the transfer clock 3 When 1 byte data lines up in the UARTO receive register the content of the UARTO receive register is transmitted to the UARTO receive buffer register The transfer clock stops at H level At this time the receive complete flag and the UARTO receive interrupt request bit goes to 1 4 The receive complete flag goes to 0 when the lower order byte of the UARTO buffer register is read 250 xe sf Mitsubishi microcomputers Fe M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Example of wiring Microcomputer Transmitter side IC CLKO CLK RxDO TxD Example of operation 1 Reception enabled 3 Reception is complete I 1 2 Start reception 4 Read of reception data 1 i Receive enable bit RE Transmit enable bit TE Dummy data is set in UARTO transmit buffer register Transmit buffer empty flag TI Transferred from UARTO transmit buffer register to UARTO transmit register ej ja 1 fext D Reception data is taken in RxDO Tr
356. nsumption mode Checks regarding Interrupt LI When rewrite the interrupt register do so at a point that does not generate the interruput request Checks regarding low voltage LI When using at low voltage have you checked recommended operating conditions and changed the wait bit address 000516 bit 7 to 1 Checks regarding A D converter L Have you selected other than fap no dividing for AD when using the A D converter at Vcc 2 7 4 0V LI Have you selected no sample amp hold function when using the A D converter at Vcc 2 7 4 0V L Have you selected 8 bit mode when using the A D converter at Vcc 2 7 4 0V 385 Appendix 2 Hexadecimal instruction CODE table D7 to D4 0000 0001 0010 0011 0100 0101 0110 0111 D3 to DO 0 t 2 3 4 5 6 7 0000 0 BRK AND B S ADD B S MOV B S BCLR S BNOT S JMP S MULU B ROH ROL ROH ROL ROH AO 0 11 SB 0 11 SB abel src dest 0001 1 MOV B S AND B S ADD B S MOV B S BCLR S BNOT S JMP S MULU W ROL dsp 8 SB dsp 8 SB ROL dsp 8 SB ROL dsp 8 SB A0 1 11 SB 1 11 SB abel src dest 0010 2 MOV B S AND B S ADD B S MOV B S BCLR S BNOT S JMP S MOV B G ROL dsp 8 FB dsp 8 FB ROL dsp 8 FB ROL dsp 8 FB A0 2 11 SB 2 11 SB abel src dest 0011 3 MOV B S AND B S ADD B S MOV B S BCLR S BNOT S JMP S MOV W G ROL abs16 abs16 ROL abs16 ROL abs16 A0 3 11 SB 3 11 SB abel src dest 0100 4 NOP AND B S ADD B S MOV B S BCLR S BNOT S JMP S CODE_74 ROL ROH ROL ROH ROCk A1 4 11 SB 4 11 SB ab
357. nterrupt routine 5 When the first effective edge is input after a count is started an indeterminate value is trans ferred to the reload register At this time timer Xi interrupt request is not generated 6 The value of the counter is indeterminate at the beginning of a count Therefore the timer Xi overflow flag may go to 1 immediately after a count is started 7 If changing the measurement mode select bit is set after a count is started the timer Xi interrupt request bit goes to 1 8 If the input signal to the TXiINOUT pin is affected by noise precise measurement may not be performed in some cases It is recommended to see that measurements fall within a specific range by use of software 9 For pulse width measurement pulse widths are successively measured Use software to check whether the measurement result is an H level width or an L level width 234 x Cy amp s Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 15 Precautions for Timer X pulse width modulation mode 1 To clear reset the count start flag is set to O Set a value in the timer Xi register then set the flag to 1 2 The timer Xi interrupt request bit becomes 1 if setting operation mode of the timer in compli ance with any of the following procedures Selecting PWM mode after reset e Changing operation mode from timer mode to PWM mode e Changi
358. numbers 0 through 31 the INT instruction uses Peripheral I O interrupts are maskable interrupts e Key input interrupt A key input interrupt occurs if an L is input to the KI pin A D conversion interrupt This is an interrupt that the A D converter generates e UARTO and UART1 transmission interrupt These are interrupts that the serial I O transmission generates UARTO and UART1 reception interrupt These are interrupts that the serial I O reception generates Timer AO interrupt This is an interrupts that timer AO generates Timer BO and timer B2 interrupt These are interrupts that timer B generates e Timer XO to timer X2 interrupt These are interrupts that timer X generates e INTO and INT1 interrupt An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin 31 Ry s eS Vd se Interrupts Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts and Interrupt Vector Tables If an interrupt request is accepted a program branches to the interrupt routine set in the interrupt vector table Set the first address of the interrupt routine in each vector table Figure 1 23 shows format for specifying interrupt vector addresses Two types of interrupt vector tables are available fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting Vector address 0 Vector address 1 Vector
359. o gt oO E Q O na oO E 3 Q Oo Set to 1 by software Count start flag Timer AO interrupt T request bit 0 a Z Cleared to 0 when interrupt request is accepted or cleared by software Figure 2 2 16 Operation timing of 2 phase pulse signal process in event counter mode normal mode selected 178 O g Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Selecting event counter mode and functions Selection of event counter mode 0 Must always be 0 when using two phase pulse signal processing 0 Must always be 0 when using two phase pulse signal processing 1 Must always be 1 when using two phase pulse signal processing __________________ Q Must always be 0 when using two phase pulse signal processing Count operation type select bit 1 Free run type Two phase pulse signal processing operation select bit 0 Normal processing operation Note Set the corresponding port direction register which inputs the pulse to 0 input mode Two phase pulse signal processing select bit b7 bO AAA 1 IXIXEX aoe flag Address 038416 Timer AO two phase pulse signal processing select bit 1 Two phase pulse signal processing enabled b7 bO TT TTT oTo Trigger select register Address 038316 LEE TRIGGER 00 Must always be 00 when using two phase pulse signa
360. o 1 3 If a trigger occurs while a count is in progress the counter reloads the value in the reload register again and continues counting The reload timing is in step with the next count source input after the trigger 4 Setting the count start flag to O causes the counter to stop and to reload the content of the reload register Also the TXiINOUT pin outputs an L level At this time the timer Xi interrupt request bit goes to 1 n reload register content g 2 Stop count 1 Start count 3 Start count Start count 4 Stop count gt gt Reload Counter content hex Set to 1 by software i Cleared to 0 by software S Count start flag Write signal to one shot start flag le f X n One shot pulse output H from TXiINOUT pin Timer Xi interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software Figure 2 4 14 Operation timing of one shot mode 222 Timer X Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Selecting one shot timer mode and functions b7 b0 olo iTi Timer Xi mode register i 0 to 2 Address 039716 to 039916 TXiMR i 0 to 2 Selection of one shot timer mode Pulse output function select bit Note 1 Pulse is output TXiINOUT pin is a pulse output pin Invalid when the external signal is not used as a count source
361. o the sub clock reduces the power dissipation After the oscillation of the main clock oscillation circuit has stabilized the drive capacity of the main clock oscillation circuit can be reduced using the XIN XOUT drive capacity select bit bit 5 at address 000716 Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation This bit changes to 1 when shifting from high speed medium speed mode to stop mode and at a reset When shifting from low speed low power dissipation mode to stop mode the value before stop mode is re tained 2 Sub clock The sub clock is generated by the sub clock oscillation circuit No sub clock is generated after a reset After oscillation is started using the port Xc select bit bit 4 at address 000616 the sub clock can be selected as BCLK by using the system clock select bit bit 7 at address 000616 However be sure that the sub clock oscillation has fully stabilized before switching After the oscillation of the sub clock oscillation circuit has stabilized the drive capacity of the sub clock oscillation circuit can be reduced using the XCIN XCOUT drive capacity select bit bit 3 at address 000616 Reducing the drive capacity of the sub clock oscillation circuit reduces the power dissipation This bit changes to 1 when shifting to stop mode and at a reset 3 BCLK The BCLK is the clock that drives the CPU and is fc or the clock is derived by dividing the main clock by
362. occurs the timer starts up and continues operating for a given period Figure 1 44 shows the timer AO mode register in one shot timer mode Table 1 16 Timer specifications in one shot timer mode Item Specification Count source f1 f8 f32 fC32 Count operation e The timer counts down When the count reaches 000016 the timer stops counting after reloading a new count e Ifa trigger occurs when counting the timer reloads a new count and restarts counting Divide ratio 1 n n Set value Count start condition e An external trigger is input e The timer overflows e The one shot start flag is set 1 Count stop condition A new count is reloaded after the count has reached 000016 e The count start flag is reset 0 Interrupt request generation timing The count reaches 000016 TAOIN pin function Programmable I O port or trigger input TAOOUT pin function Programmable I O port or pulse output Read from timer When timer AO register is read it indicates an indeterminate value Write to timer When counting stopped When a value is written to timer AO register it is written to both reload register and counter e When counting in progress When a value is written to timer AO register it is written to only reload register Transferred to counter at next reload time Timer AO mode register b7 b6 b5 b4 b3 b2 bi b0 PT fol ilo TAVA pigs Address When reset
363. ock Transfer clock LSB first MSB first Transmission Transmission buffer empty interrupt factor Transmission complete Output transfer clock Not selected to multiple pins Note PSR Selected Note This can be selected only when UARTO is used in combination with the internal clock Operation 1 Setting the transmit enable bit to 1 makes data transmissible status ready 2 When transmission data is written to the UARTO transmit buffer register transmission data held in the UARTO transmit buffer register is transmitted to the UARTO transmit register in synchronization with the first falling edge of the transfer clock At this time the first bit of the transmission data is transmitted from the TxDo pin Then the data is transmitted bit by bit from the lower order in synchronization with the falling edges of the transfer clock 3 When transmission of 1 byte data is completed the transmit register empty flag goes to 1 which indicates that the transmission is completed The transfer clock stops at H level At this time the UARTO transmit interrupt request bit goes to 1 4 Setting CLK CLKS select bit 1 to 1 and setting CLK CLKS select bit 0 to 1 causes the CLKS pin to go to the transfer clock output pin Change the transfer clock output pin when transmission is halted 246 xe sf Mitsubishi microcomputers Fe M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Cloc
364. ocomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt Time a is dependent on the instruction under execution Thirty cycles is the maximum required for the DIVX instruction without wait Time b is as shown in Table 4 3 1 Table 4 3 1 Time required for executing the interrupt sequence Interrupt vector address Stack pointer SP value 16 Bit bus without wait 8 Bit bus without wait Even 18 cycles Note 1 20 cycles Note 1 Even 19 cycles Note 1 20 cycles Note 1 Odd Note 2 19 cycles Note 1 20 cycles Note 1 Odd Note 2 20 cycles Note 1 20 cycles Note 1 Note 1 Add 2 cycles in the case of a DBC interrupt add 1 cycle in the case either of an address coincidence interrupt or of a single step interrupt Note 2 Locate an interrupt vector address in an even address if possible BCLK Address bus Address Indeterminate SP 2 SP 4 vec vec 2 PC Data bus Interrupt RET Indeterminate SP 2 SP 4 vec vec 2 contents contents contents contents Indeterminate The indeterminate segment is dependent on the queue buffer If the queue buffer is ready to take an instruction a read cycle occurs Figure 4 3 2 Time required for executing the interrupt sequence 4 3 2 Variat
365. ode 0 is selected Note 1 A D operation mode select bit 1 Note 1 A D conversion start flag 0 Must always be 0 in repeat sweep mode 0 0 A D conversion disabled 8 10 bit mode select bit __ Frequency select bit 0 p 8 bit mode 0 fAD 4 is selected 1 10 bit mode 1 fAD 2 is selected Frequency select bit 1 0 fAD 2 or fAD 4 is selected 1 fad is selected Vref connect bit 1 Vref connected Must be fixed to 0 A D input group select bit 0 Port P6 group is selected Note 1 Rewrite to analog input pin select bit after changing A D operation mode 1 Port P5 group is selected Note 2 Set the corresponding port direction register to 0 input mode When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins ANso to ANs4 k Setting A D conversion start flag b7 b0 7 A D control register 0 Address 03D616 ADCONO A D conversion start flag 1 A D conversion started Repeatedly carries out A D conversion on pins selected through the A D sweep pin select bit Start A D conversion 2 Reading conversion result A D register O Address 03C116 03C016 ba A D register 1 Address 03C316 03C216 bO b7 bo A D register2 Address 03C516 030416 A D register 3 Address 03C716 03C616 A D register 4 Address 03C916 03C816 A D register 5 Address 03CB16 03CA16 A D register 6 Address 03CD1
366. oes to 1 Also the A D conversion start flag goes to 0 and the A D converter stops operating 1 Start A D conversion 2 A D conversion is complete 8 bit resolution 28 f AD cycles 10 bit resolution 33 fAD cycles A Dconversion 1 start flag A D register i A D conversion interrupt request Cleared to 0 when interrupt request is accepted or cleared by software Note When fap frequency is less than 1MHz sample and hold function cannot be selected Conversion rate per analog input pin is 49 AD cycles for 8 bit resolution and 59 fap cycles for 10 bit resolution Figure 2 7 5 Operation timing of one shot mode 278 x O Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter Selecting Sample and hold A D control register 2 Address 03D416 ADCON2 A D conversion method select bit 1 With sample and hold Must be fixed to 0 Setting A D control register 0 and A D conirol register 1 b7 bo b7 b0 F alo oio A D control register 0 Address 03D616 A D control register 1 Address 03D716 ADCONO ADCON1 Analog input pin select bit Note 2 Invalid in one shot mode b2 b1 b0 0 0 0 AN0 is selected A D operation mode select bit 1 Note 1 AN1 is selected 0 Must always be 0 in one shot mode AN2 is selected ANs is selected 8 10 bit mode select bit AN4 is selected 0 8 bit mode AN5 is selected 1
367. ol program was downloaded to the RAM or not using the down load function Check Sum Consistency Bit SR12 This flag indicates whether the check sum matches or not when a program is downloaded for execu tion using the download function ID Check Completed Bits SR11 and SR10 These flags indicate the result of ID checks Some commands cannot be accepted without an ID check Data Reception Time Out SR9 This flag indicates when a time out error is generated during data reception If this flag is attached during data reception the received data is discarded and the microcomputer returns to the command wait state 156 x Ss 2 RX Mitsubishi microcomputers ve M30201 Group s SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode Example Circuit Application for The Standard Serial I O Mode The below figure shows a circuit application for the standard serial O mode Control pins will vary ac cording to programmer therefore see the programmer manual for more information Clock input CLKO P53 BUSY Data input RxDO Data output TxDO M30201 Flash memory version CNVss 1 Control pins and external circuitry will vary according to programmer For more information see the programmer manual 2 In this example the microprocessor mode and standard serial I O mode are switched via a switch Figure DD 20 Example circuit application for the standard serial I O mode 157 Chapter 2 Peripheral
368. olarity set the interrupt request bit to 0 Figure 4 7 1 shows the procedure for changing the INT interrupt generate factor Clear the interrupt enable flag to 0 Disable interrupt Set the interrupt priority level to level 0 Disable INTi interrupt Set the polarity select bit Clear the interrupt request bit to O Set the interrupt priority level to level 1 to 7 Enable the accepting of INTi interrupt request Set the interrupt enable flag to 1 Enable interrupt Figure 4 7 1 Switching condition of INT interrupt request 370 g Mitsubishi microcomputers DOO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 Rewrite the interrupt control register e To rewrite the interrupt control register do so at a point that does not generate the interrupt request for that register If there is possibility of the interrupt request occur rewrite the interrupt control register after the interrupt is disabled The program examples are described as follow Example 1 INT_SWITCH1 FCLR Disable interrupts AND B 00h 0055h Clear TAOIC int priority level and int request bit NOP Four NOP instructions are required when using HOLD function NOP FSET Enable interrupts Example 2 INT_SWITCH2 FCLR Disable interrupts AND B 00h 0055h Clear TAOIC int priority level and int request bit MOV W MEM RO Dummy read FSET Enable interrupts Example 3 INT_SWITCHS PUSHC FLG
369. om TX1INOUT pin o Timer XO interrupt 1 request bit Q Cleared to 0 when interrupt request is accepted or cleared by software Timer X1 interrupt 1 request bit g Cleared to 0 when interrupt request is accepted or cleared by software Figure 3 2 1 Operation timing of variable period variable duty PWM output Used for timer mode Set to period Timer XO interrupt request bit Timer X1 interrupt request bit Used for one shot timer mode Set to H width Figure 3 2 2 Connection diagram of variable period variable duty PWM output 331 Mitsubishi microcomputers Sass SF of M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications Setting timer X0 Selecting timer mode and functions oT eT oy oPop oT ayo TOMA mode register Address 039716 Selection of timer mode Pulse output function select bit 0 Pulse is not output TXOINOUT pin is a normal port pin Gate function select bit b4 b3 00 Gate function not available TXOINOUT pin is a normal port pin 0 Must always be 0 in timer mode Count source select bit Count Count source period br bG SOUICE f X n 10MHz_ f XcIN 32 768kHz 00 f1 Toons 800ns 3 2us 976 56us Setting divide ratio b15 bz Timer XO register Address 038916 038816 TXO Setting timer X1 y Selecting one shot timer mode and functions Select
370. omparison register conversion result is transmitted to A D register 0 The A D converter converts all analog input pins selected by the user The conversion result is trans mitted to A D register i corresponding to each pin every time conversion on one pin is com pleted 3 When the A D conversion on all the analog input pins selected is completed the A D conver sion interrupt request bit goes to 1 At this time the A D conversion start flag goes to 0 The A D converter stops operating E 2 After A D conversion on ANo AN50 pin is complete Vrstan AE Conversion A D converter begins converting a sing selected 3 A D conversion i is complete 8 bit resolution 28 tan cycles 8 bit resolution 28 saD cycles 10 bit resolution 33 san cycles 10 bit resolution 33 saD cycles e e a UU Set to 1 by software A D conversion 4 start flag A D register 0 x Result A D register 1 X Result A D register i X Result A D conversion 1 interrupt request o bit A Cleared to 0 when interrupt request is accepted or cleared by software Note When zan frequency is less than 1MHz sample and hold function cannot be selected Conversion rate per analog input pin is 49 saD cycles for 8
371. omputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications 3 3 Delayed One Shot Output Overview The following are steps of outputting a pulse only once after a specified elapse since an external trigger is input Figure 3 3 1 shows the operation timing Figure 3 3 2 shows the connection dia gram and Figures 3 3 3 and 3 3 4 show the set up procedure Use the following peripheral function e One shot timer mode of timer X Specifications Operation 1 Set timer X0 in one shot timer mode and set timer X1 in one shot timer mode with pulse output function 2 Set 1 ms an interval before a pulse is output in timer X0 and set 50 us a pulse width in timer X1 Both timer XO and timer X1 use f1 for the count source 3 Connect a 10 MHz oscillator to XIN 1 Setting the trigger select bit to 1 and setting the count start flag to 1 enables the counter of timer XO to count 2 If an effective edge selected by use of the external trigger select bit is input to the TXOINOUT pin the counter begins a down count The counter of timer XO performs a down count on count source f1 3 As soon as the counter of timer XO becomes 000016 the counter reloads the content of the reload register and stops counting At this time the timer XO interrupt request bit gose to 1 4 An underflow in timer XO triggers the counter of timer X1 and causes it to begin counting When timer X1 begins co
372. omputers Sf M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Description Outline Performance Table AA 1 shows the outline performance of the M30201 flash memory version Table AA 1 Outline Performance of the M30201 flash memory version Item Performance Power supply voltage 4 0V to 5 5 V f XIN 10MHz Program erase voltage VPP 12V 5 f XIN 10MHZz Voc 5V 5 f XIN 10MHZz Flash memory operation mode Three modes parallel O standard serial I O CPU rewrite Erase block User ROM area See Figure AA 3 division ace Boot ROM area One division 4 Kbytes Note 1 Program method In units of byte Erase method Collective erase Program erase control method Program erase control by software command Number of commands 6 commands Program erase count 100 times ROM code protect Parallel I O mode is supported Note The boot ROM area contains a standard serial I O mode control program which is stored in it when shipped from the factory This area can be erased and programmed in only parallel I O mode 126 x N Q ae Mitsubishi microcomputers S M30201 Group v PET SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Description Flash Memory The M30201 flash memory version contains the NOR type of flash memory that requires a high voltage VPP power supply for program erase operations in addition to the Vcc power supply for device operation For this flash memory three fla
373. on completed Must be 1 in UART mode Data output select bit Note 0 TxDi pin is CMOS output 1 TxDi pin is N channel open drain output Must be 0 in UART mode Must be 0 in UART mode Note Set the corresponding port direction register to 1 output mode NX Setting UART transmit receive control register 2 b7 b0 0 UART transmit receive control register 2 UCON Address 03B016 UARTO transmit interrupt cause select bit 1 Transmission completed TXEPT 1 UART1 transmit interrupt cause select bit 1 Transmission completed TXEPT 1 L4 Invalid in UART mode Must be 0 in UART mode Invalid in UART mode Must be 0 in UART mode Continued to the next page Figure 2 6 7 Set up procedure of transmission in UART mode 1 266 O aS Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Continued from the previous page Setting UARTi bit rate generator i 0 1 b7 b0 UARTi bit rate generator i 0 1 Address 03A116 03A916 UiBRG i 0 1 Can be set to 0016 to FF16 Note Note Write to UARTI bit rate generator when transmission reception is halted Transmission enabled b7 b0 WITT UARTO transmit receive control register 1 UOC1 Address 03A516 Xxx LT UART1 transmit receive control register 1 U1C1
374. on input pins P40 I O pin for serial I O communication Timer A input pin P41 Timer A output pin P42 Serial I O input pin P43 P44 Input pins for external interrupt Timer X I O pins P45 Timer X I O pin P50 to P54 I O pins for serial I O communication A D converter input pins P6 A D converter input pins P70 P71 Timer B input pins 7 Examples of working on non used pins Table 2 12 2 contains examples of working on non used pins There are shown here for mere ex amples In practical use make suitable changes and perform sufficient evaluation in compliance with you application Table 2 12 2 Examples of working on unused pins in single chip mode Pin name Connection Ports PO P1 P3 to P7 After setting for input mode connect every pin to Vss or Vcc via a resistor or after setting for output mode leave these pins open Note 1 XouT Note 2 Open AVcC Connect to Vcc AVss VREF BYTE Connect to Vss Note 1 If setting these pins in output mode and opening them ports are in input mode until switched into output mode by use of software after reset Thus the voltage levels of the pins become unstable and there can be instances in which the power source current increases while the ports are in input mode In view of an instance in which the contents of the direction registers change due to a runaway generated by noise or other causes setting the contents of the direction registers per
375. one shot timer mode Therefore to use timer AO interrupt interrupt request bit set timer AO interrupt request bit to 0 after the above listed changes have been made 5 If a trigger occurs while a count is in progress after the counter performs one down count following the reoccurrence of a trigger the reload register contents are reloaded and the count continues To generate a trigger while a count is in progress generate the second trigger after an elapse longer than one cycle of the timer s count source after the previous trigger occurred TAOIN pin input signal a Trigger input Count source One shot pulse i output from TAQOUT pin i Start one shot pulse output Note The above applies when an external trigger falling edge of TAOIN pin input signal is selected Figure 2 2 31 One shot timer delay 192 xe sf Mitsubishi microcomputers S M30201 Group T A SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Imer 2 2 16 Precautions for Timer A pulse width modulation mode 1 To clear reset the count start flag is set to 0 Set a value in the timer AO register then set the flag to 1 2 The timer AO interrupt request bit becomes 1 if setting operation mode of the timer in com pliance with any of the following procedures Selecting PWM mode after reset e Changing operation mode from timer mode to PWM mode e Changing operation mode from event counter mode to PWM mode Therefore to use timer A
376. ons from those listed in Table 2 2 6 Operations of the circled items are described below Figure 2 2 16 shows the operation timing and Figure 2 2 17 shows the set up procedure Table 2 2 6 Choosed functions Count operation type Reload type Free run type 2 phase pulses Normal processing process 4 multiplication processing Operation 1 Setting the count start flag to 1 causes the counter to count effective edges of the count source 2 Even if an underflow occurs the content of the reload register is not reloaded but the count continues At this time the timer AO interrupt request bit goes to 1 3 Even if an overflow occurs the content of the reload register is not reloaded but the count continues At this time the timer AO interrupt request bit goes to 1 Note e The up count or down count conditions are as follows If a rising edge is present at the TAOIN pin when the input signal level to the TAOQOUT pin is H an up count is performed If a falling edge is present at the TAOIN pin when the input signal level to the TAQOUT pin is H a down count is performed 1 Start count k Input pulse 2 Undertlow FFFF16 esal 000016 gt x lt
377. ons of the circled items are described below Figure 2 5 5 shows the operation timing and Figures 2 5 6 and 2 5 7 show the set up procedures Table 2 5 1 Choosed functions Transfer clock Internal clock f1 fe f32 fc source External clock CLKO pin CLK polarity Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer clock Transfer clock LSB first MSB first Transmission Transmission buffer empty interrupt factor Transmission complete Output transfer clock Not selected to multiple pins Note eae Selected Note This can be selected only when UARTO is used in combination with the internal clock Operation 1 Setting the transmit enable bit to 1 and writing transmission data to the UARTO transmit buffer register makes data transmissible status ready 2 In synchronization with the first falling edge of the transfer clock transmission data held in the UARTO transmit buffer register is transmitted to the UARTO transmit register At this time the UARTO transmit interrupt request bit goes to 1 Also the first bit of the transmission data is transmitted from the TxDo pin Then the data is transmitted bit by bit from the lower order in synchronization with the falling edges 3 When transmission of 1 byte data is completed the transmit register empty flag goes to 1 which indicates that transmission
378. ontrol circuit receive unit fs N Internal UART transmission Transmit 320 Oo 1 m 1 H18 Q Transmission clock fc 2 Extemal Clock synchronous type o control circuit Clock synchronous type when internal clock is selected eal o Clock synchronous type Clock synchronous type when internal clock is selected when external clock is 1 selected CLK Qo polarity j reversing circuit Clock output pin select switch UART1 RxD1O Receive Clock source selection R Reception clock Transmit fi o Bit rate generator control circuit receive unit fg 1 n 1 f32 o Transmit issi clock fc o 1 16 Transmission control circuit m Values set to UARTO bit rate generator BRGO n Values set to UART1 bit rate generator BRG1 Figure 1 69 Block diagram of UARTi i 0 1 76 N Q amp Mitsubishi microcomputers Ss M30201 Group Pos ial I O SINGLE CHIP 16 BIT CMOS MICROCOMPUTER eria Clock synchronous type PAR Wee bt UART 7 bits UARTI receive register disabled Lo Sal ag ial PAR i alter UART 9bits synchronous type UART 8 bits UART 9 bits i H r i UARTI receive D7 De Ds D4 D3 D2 D1 Do butter register MSB LSB conversion circuit Data bus high order bits Data bus low order b
379. onversion result is indeterminate A D register i Symbol Address When reset ADi i 0 to 7 03C016 to O3CF16 Indeterminate e During 10 bit mode Two high order bits of A D conversion result e During 8 bit mode When read the content is indeterminate eee ee ee nnn Nothing is assigned When write set 0 When read their content is indeterminate Figure 2 7 4 A D converter related registers 3 277 Ni Q amp Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 2 Operation of A D converter one shot mode In one shot mode choose functions from those listed in Table 2 7 2 Operations of the circled items are described below Figure 2 7 5 shows the operation timing and Figure 2 7 6 shows the set up procedure Table 2 7 2 Choosed functions Operation clock fAD Divided by 4 fan divided by 2 fab fap Resolution 8 bit 10 bit Analog input pin One of ANo pin to AN7 pin Note Sample amp Hold Not activated Activated Note When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins AN50 to AN54 Operation 1 Setting the A D conversion start flag to 1 causes the A D converter to begin operating 2 After A D conversion is completed the content of the successive comparison register con version result is transmitted to A D register i At this time the A D conversion interrupt re quest bit g
380. onversion result During 10 bit mode Two high order bits of A D conversion result During 8 bit mode When read the content is indeterminate Setting A D conversion start flag b7 bo FroTLLiLet i A D control register 0 Address 03D616 ADCONO A D conversion start flag 0 A D conversion disabled W Stop A D conversion Figure 2 7 8 Set up procedure of repeat mode 281 Ni Q amp Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 4 Operation of A D Converter in single sweep mode In single sweep mode choose functions from those listed in Table 2 7 4 Operations of the circled items are described below Figure 2 7 9 shows timing chart and Figure 2 7 10 shows the set up procedure Table 2 7 4 Choosed functions Operation clock fAD Divided by 4 fab divided by 2 fab fAD Resolution 8 bit 10 bit Analog input pin Ae AN1 2 pins ANo to ANs 4 pins ANo to ANs 6 pins ANo to AN7 8 pins Sample amp Hold Not activated Activated Note When the port P5 group is selected analog input pins are changed from ANo to AN4 to pins AN50 to AN54 Operation 1 Setting the A D conversion start flag to 1 causes the A D converter to start the conversion on voltage input to the ANo AN50 pin 2 After the A D conversion of voltage input to the ANo AN50 pin is completed the content of the successive c
381. onversion starts and carries out A D conversion on the voltage sampled When A D conversion starts input voltage is sampled for 3 cycles of the operation clock When the Sample amp Hold function is selected set the operation clock for A D conversion to 1 MHz or higher b 8 bit A D to 10 bit A D switching function Either 8 bit resolution or 10 bit resolution can be selected When 8 bit resolution is selected the 8 higher order bits of the 10 bit A D are subjected to A D conversion The equations for 10 bit resolu tion and 8 bit resolution are given below 10 bit resolution Vref X n 210 Vref X0 5 10 0 n 1 to 1023 0 n 0 8 bit resolution Vref X n 28 Vref X0 5 210 n 1 to 256 0 n 0 c Analog input group function The analog input pins can be switched between the port P6 group ANo to AN4 and the port P5 group AN50 to AN54 d Connecting or cutting Vref Cutting Vref allows decrease of the current flowing into the A D converter To decrease the microcomputer s power consumption cut Vref To carry out A D conversion start A D conversion 1 ms or longer after connecting Vref The following are exsamples in which functions a through d are selected OMO SMOb MOUE ia cas csiarice ct itinira ae aa iaai aaia araea aaaea aa aa a aE ATANAS P278 Repeat M0de srriioniniiiooiiirin iei avin tiie eit eines vive divi ieee EARANN P280 Single SWEEP MODS issons daa ae aaa aaa EAE E aaa GEENEN P282 Repeated Swe
382. operations Finished saving registers 2 Stack pointer SP contains odd number Address Stack area Sequence in which order registers are saved SP 4 Odd Program counter PCL Program counter PCm Il 8 bi SP 2 Odd Flag register FLG1 a18 piis Flag register Program SP T Ev n FLGx counter PCx SP Odd Finished saving registers in four operations Note SP denotes the initial value of the stack pointer SP when interrupt request is acknowledged After registers are saved the SP content is SP minus 4 Figure 4 3 4 Operation of saving registers 365 4 Mitsubishi microcomputers g NO M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 4 Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register FLG as it was immediately before the start of interrupt sequence and the contents of the program counter PC both of which have been saved in the stack area Then control returns to the program that was being executed before the acceptance of the interrupt request so that the suspended process resumes Return the other registers saved by software within the interrupt routine using the POPM or similar instruc tion before executing the REIT instruction 4 5 Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling ch
383. or one cycle and continues counting 4 Setting the count start flag to O causes the counter to hold its value and to stop Also the TAOOUT pin outputs an L level Note e PWM pulse cycle is m 1 x 28 1 fi whereas H level duration is n x m 1 fi However when 0016 is set for the significant 8 bits of the timer AO register the PWM output is L level for the entire period and an interrupt request is generated for every PWM output cycle Also when FF 16 is set for the significant 8 bits of the timer AO register the PWM output is H level for the entire period and an interrupt request is generated for every PWM output cycle fi Count source frequency f1 fs f32 fc32 n Timer value Conditions Reload register high order 8 bits 0216 Reload register low order 8 bits 0216 External trigger falling oe of TAOIN pin input signal is selected 1 fi X m 1 X 2 1 else Count source Note 1 Count start flag 1 Start count n 2 Output level H to L 3 One period is TAOIN pin input i 1 Di i complete 1 1 X m prescaler Note 2 oa i gt ee i 1 fX m 1 Xn r Cleared to 0 when interrupt request is accepted or cleared by software Note 1 The 8 bit prescaler counts the count source Note 2 The 8 bit pulse width modulator counts the 8 bit prescaler s underflow signal Note 3 m 0016 to FF16 n 0016 to FF16 PWM pulse output fro
384. ore attempting to change the contents of the processor mode register 1 set bit 1 of the protect register address 000A16 to 1 Table 1 2 Software waits and bus cycles Wait bit Bus cycle SFR Invalid 2 BCLK cycles Internal 1 BCLK cycle ROM RAM 2 BCLK cycles 18 Clock Generating Circuit Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units Table 1 3 Main clock and sub clock generating circuits e CPU s operating clock source e Internal peripheral units operating clock source Use of clock e CPU s operating clock source Timer A B X s count clock source Usable oscillator Ceramic or crystal oscillator Crystal oscillator Pins to connect oscillator XIN XOUT XCIN XCOUT Oscillation stop restart function Available Available Oscillator status immediately after reset Oscillating Stopped Other Externally derived clock can be input Example of oscillator circuit Figure 1 15 shows some examples of the main clock circuit one using an oscillator connected to the circuit and the other one using an externally derived clock for input Figure 1 16 shows some examples of sub clock circuits one using an oscillator connected to the circuit an
385. ount source Note1 Trigger signal Underflow signal of 8 bit prescaler Note2 q 1 f X m 1 Xn 4 PWM pulse output from TXiINOUT pin Timer Xi interrupt request bit fi Frequency of count source f1 fe f32 fc32 Cleared to 0 when interrupt request is accepted or cleaerd by software Note 1 The 8 bit prescaler counts the count source Note 2 The 8 bit pulse width modulator counts the 8 bit prescaler s underflow signal Note 3 m 0016 to FF16 n 0016 to FF16 Figure 1 68 Example of how an 8 bit pulse width modulator operates 75 Serial I O Serial I O Serial I O is configured as two channels UARTO and UART1 UARTO and UART1 each have an exclusive timer to generate a transfer clock so they operate indepen dently of each other Figure 1 69 shows the block diagram of UARTO and UART1 Figure 1 70 shows the block diagram of the transmit receive unit UARTO has two operation modes a clock synchronous serial I O mode and a clock asynchronous serial O mode UART mode The contents of the serial I O mode select bits bits 0 to 2 at addresses 03A016 and 03A816 determine whether UARTO is used as a clock synchronous serial I O or as a UART UART1 is used as a UART only Figures 1 71 through 1 73 show the registers related to UARTIi UARTO RxD O lel UART reception 5 Receive Clock source selection L Reception clock Transmit o Bit rate generator Clock synchronous type e c
386. ounter mode One shot timer mode Pulse width modulation PWM mode TCKO Count source select bit Function varies with each operation mode ae 1 ie Function varies with each operation mode i 0 9 o o 0 9 elle jo o Figure 2 2 2 Timer A related registers 1 164 O g Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Timer AO register Note pa Address When reset 038716 038616 Indeterminate Function Values that can be set e Timer mode 000016 to FFFF16 Counts an internal count source e Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow e One shot timer mode 000016 to FFFFi6 Counts a one shot width XO e Pulse width modulation mode 16 bit PWM 000016 to FFFE16 y fo Functions as a 16 bit pulse a see Pulse width modulation mode 8 bit PWM pay e Timer low order address functions as an 8 bit S E prescaler and high order address functions as an 8 bit 0016 to FE16 Low pulse width modulator order addresses Note Read and write data in 16 bit units Count start flag b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset TABSR 038016 000X00002 1 Starts counting Nothing is assigned When write set 0 When read their contents are indeterminate TBOS Timer BO count start flag 0 Stops counting TB1S Timer B1 count start flag trstans counting CDCS Clock devided count start flag Figure 2 2 3
387. ounter to hold its value and to stop 5 If an overflow occurs the content of the reload register is reloaded and the count continues At this time the timer AO interrupt request bit goes to 1 n reload register content 5 Overflow Start count again Counter content hex i MAn Time Set to 1 by software tto 1 by software software i Count start flag i i Set to 1 by software i 1 ooo Up down flag i l leared to 0 when interrupt request is accepted or cleared by sdftware Timer AO interrupt 1 5 I request bit g Figure 2 2 12 Operation timing of event counter mode reload type selected 174 O g Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A x Selecting event counter mode and functions Bopoooga Timer AO mode register Address 039616 TAOMR Selection of event counter mode Pulse output function select bit 0 Pulse is not output TAOOUT pin is a normal port pin Count polarity select bit 0 Counts external signal s falling edge Up down switching cause select bit 0 Up down flag s content 0 Must always be 0 in event counter mode Count operation type select bit 0 Reload type Invalid when not using two phase pulse signal processing S Setting up down flag b7 bo Up d fl Add 0384 DDE yppa feo Address 0384s Timer AO up down flag 0 Down
388. oup SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt Interrupt control register Address When reset 004D16 XXXXX0002 004E16 XXXXX0002 005116 005316 XXXXX0002 005216 005416 XXXXX0002 005516 XXXXX0002 005616 to 005816 XXXXX0002 005A16 005B16 XXXXX0002 Bit symbol Interrupt priority level select bit ay Hees Tl oS Ta b7 b6 b5 b4 b3 b2 bi b0 OGO 6 piped Level 0 interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Interrupt request bit 0 Interrupt not requested O O 1 Interrupt requested Note Nothing is assigned When write set 0 When read their contents are indeterminate Note This bit can only be accessed for reset 0 but cannot be accessed for set 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset XX ITITI INTIIC i 0 1 005D16 005E16 XX00X0002 VN Interrupt priority level select bit b2 b1 b0 0 0 0 Level 0 interrupt disabled 001 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 1 1 0 0 1 1 Interrupt request bit 0 Interrupt not requested 1 Interrupt requested POL Polarity select bit 0 Selects falling edge 1 Selects rising edge Reserved bit Always set to 0 Nothing is assigned When write set 0 When read their contents are indeterminate Note This bit can only be accessed for reset 0 but cannot be accessed for set 1 Figure 4 2 2 Interrupt control r
389. p down flag between up and TB1 TX0 TX2 overflow dawn p Input signal to TAQouT Operation 1 Setting the count start flag to 1 causes the counter to count the falling edges of the count source 2 Even if an underflow occurs the content of the reload register is not reloaded but the count continues At this time the timer AO interrupt request bit goes to 1 3 If switching from an up count to a down count or vice versa while a count is in progress the switch takes effect from the next effective edge of the count source 4 Even if an overflow occurs the content of the reload register is not reloaded but the count continues At this time the timer AO interrupt request bit goes to 1 n reload register content 2 Underflow 3 Switch count 4 Overflow Counter content hex Count start flag A Set to 1 by software q 1 Up down flag 0 i i i i Cleared to 0 when interrupt request is accepted or cleared by software Timer AO interrupt 4 ma i Pa request bit un l Figure 2 2 14 Operation timing of event counter mode free run type selected 176 O g Mitsubishi microcomputers DO M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A Selecting event counter mode and functions Selection of event counter mode Pulse output function select bit 0 Pulse is not output TAOOUT pin is a normal port pin Count polarity sel
390. perating ambient temperature 20 to 85 Note 3 Storage temperature Note 1 When writing to fash MCU CNVss is 0 3 to 13 V Note 3 Extended operating temperature version 40 to 85 C Note 4 Extended operating temperature version 65 to 150 C Note 2 Flat package 56P6S A is 300 mW 112 40 to 150 Note 4 Electrical characteristics Vcc 5V Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Table 1 38 Recommended operating conditions Note 1 Parameter Supply voltage Note 2 Mask ROM version Vcc 5V Standard Typ Flash memory version Analog supply voltage Supply voltage Analog supply voltage HIGH input voltage POo to P07 P10 to P17 P30 to P35 P40 to P45 P50 to P54 P60 to P67 P70 P71 Xin RESET CNVss ViL LOW input voltage P00 to P07 P10 to P17 P30 to P35 P40 to P4s P50 to P54 P60 to P67 P70 P71 Xin RESET CNVss loH peak HIGH peak output P0Oo to P07 P10 to P17 P30 to P35 P40 to P4s current P50 to P54 P60 to P67 P70 P71 OL peak LOW peak output POo to P07 P30 to P35 P40 to P45 current P50 to P54 P60 to P67 P70 P71 IOL peak LOW peak output Pio to P17 HIGHPOWER current LOWPOWER lOH avg HIGH average output P0Oo to P07 P10 to P17 P30 to P35 P40 to P45 current P50 to P54 P60 to P67 P70 P71 lot avg LOW average output P00 to P07 P
391. ple Interrupts The state when control branched to an interrupt routine is described below The interrupt enable flag I flag is set to 0 the interrupt is disabled The interrupt request bit of the accepted interrupt is set to 0 The processor interrupt priority level IPL is assigned to the same interrupt priority level as assigned to the accepted interrupt Setting the interrupt enable flag I flag to 1 within an interrupt routine allows an interrupt request assigned a priority higher than the IPL to be accepted Figure 4 6 1 shows the scheme of multiple interrupts An interrupt request that is not accepted because of low priority will be held If the condition following is met when the REIT instruction returns the IPL and the interrupt priority is determined then the interrupt request being held is accepted Interrupt priority level of the interrupt request being held gt Returned the IPL 368 x xe s Mitsubishi microcomputers S M30201 Group i SINGLE CHIP 16 BIT CMOS MICROCOMPUTER nterrupt Interrupt request k generated Nesting Reset Wain ouine Interrupt 1 Interrupt priority level 3 Interrupt 2 Multiple interrupts Interrupt priority level 5 Interrupt 3 Interrupt priority level 2 Not acknowledged because of low interrupt priority lt Main routine instructions are not executed Interrupt enable flag Processor interrupt priority level A
392. present in receive buffer register 1 Data present in receive buffer register Checking error b0 UARTO receive buffer register Address 03A716 03A616 UORB Receive data Overrun error flag 0 No overrun error 1 Overrun error found Framing error flag 0 No framing error 1 Framing error found Parity error flag 0 No parity error 1 Parity error found Error sum flag 0 No error 1 Error found Processing after reading out reception data Figure 2 6 11 Set up procedure of reception in UART mode 2 271 N S Mitsubishi microcomputers SS ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 A D Converter 2 7 1 Overview The A D converter used in the M16C 60 group operates on a successive conversion basis The following is an overview of the A D converter 1 Mode The A D converter operates in one of five modes a One shot mode Carries out A D conversion on input level of one specified pin only once b Repetition mode Repeatedly carries out A D conversion on input level of one specified pin c Single sweep mode Carries out A D conversion on input level of two or more specified pins only once d Repeated sweep mode 0 Repeatedly carries out A D conversion on input level of two or more pins e Repeated sweep mode 1 Repeatedly carries out A D conversion on input level of two or more pins This mode is different from
393. pt 2 Determining the interrupt address Determining which factor generated the interrupt 3 Rewriting the stack Rewriting the return address Figure 2 9 5 Overview of the address match interrupt handling routine 305 N O sg Mitsubishi microcomputers SF of M30201 Group Ra SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Key Input Interrupt 2 10 Key Input Interrupt 2 10 1 Overview Key input interrupt occurs when a falling edge is input to POo through P07 The following is an overview of the key input interrupt 1 Enabling disabling the key input interrupt The key input interrupt can be enabled and disabled using the key input interrupt register The key input interrupt is affected by the interrupt priority level IPL and the interrupt enable flag I flag 2 Occurrence timing of the key input interrupt With key input interrupt acceptance enabled pins POo through P07 which are set to input become key input interrupt pins Klo through KI7 A key input interrupt occurs when a falling edge is input to a key input interrupt pin At this moment the level of other key input interrupt pins must be H No interrupt occurs when the level of other key input interrupt pins is L 3 How to determine a key input interrupt A key input interrupt occurs when a falling edge is input to one of eight pins but each pin has the same vector address Therefore read the input level of pins POo through P07 in the key input interrupt ro
394. pt occurs when transmitted data is moved from the transmission buffer to the transmission register Therefore data can be transmitted in succession When transmission register empty timing is selected an interrupt occurs when data transmission is complete Following are some examples in which various functions a through e are selected e Transmission Operation WITH transmission at falling edge of transfer clock LSB First interrupt at instant transmission buffer is emptied WITHOUT transfer clock output to multiple pins function e Transmission Operation WITH transmission at falling edge of transfer clock LSB First interrupt at instant transmission is completed WITH transfer clock output to multiple pins function UARTO selection avallable jeansa a EAE AE AAEE P246 e Reception WITH reception at falling edge of transfer clock LSB First successive reception mode disabled WITHOUT transfer clock output to multiple pins function sssesseeesseeeseeeseeeeeeeen P250 6 Input output to the serial I O and the direction register To input an external signal to the serial I O set the direction register of the relevant port to input To output signal from the serial I O set the direction register of the relevant port to output 237 N amp amp Mitsubishi microcomputers R Sty M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O 7 Pins related to the serial I O e CLKO pin Input output
395. put Do not stop peripheral function clock in wait mode Stop peripheral function clock in wait mode Note 8 LOW HIGH I O port XCIN XCOUT generation Main clock XIN XOUT 0 On stop bit Note 3 4 5 1 Off 0 CM16 and CM17 valid 1 Division by 8 mode 0 XIN XOUT 1 XCIN XCOUT Clock output function select bit WAIT peripheral function clock stop bit XCIN XCOUT drive capacity select bit Note 2 0 1 Port Xc select bit 0 1 Main clock division select bit 0 Note 7 System cl Note 6 lock select bit Set bit 0 of the protect register address 000A16 to 1 before writing to this register Changes to 1 when shifting to stop mode and at a reset This bit is used to stop the main clock when placing the device in a low power mode If you want to operate with XIN after exiting from the stop mode set this bit to 0 When operating with a self excited oscillator set the system clock select bit CM07 to 1 before setting this bit to 1 When inputting external clock only clock oscillation buffer is stopped and clock input is acceptable If this bit is set to 1 XouT turns H The built in feedback resistor remains being connected so XIN turns pulled up to XoutT H via the feedback resistor Set port Xc select bit CM04 to 1 and stabilize the sub clock oscillating before setting to this bit from 0 to 1 Do not write to both bit
396. put port P7 Input H or L level signal or open 144 x Se xe RX Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode Mode setup method CNVss VpPH RESET Vss gt Vcc P61 AN1 P60 ANo lt p gt P62 AN2 P63 AN3 P64 AN4 P54 CKouT AN54 lt gt 5 P65 AN5 P53 CLKS ANs3 gt 6 P66 ANe P52 CLKo ANs2 lt gt 7 P67 AN7 P51 RxDo ANs51 lt gt 8 POo Klo P50 TxDo ANso lt gt 3 Pow Klt CNVss gt ig P02 Kl2 P71 TB1IN XcIN lt gt P0s Kl3 P70 TBOIn Xcout 4 42 P04 Kl4 P05 Kl5 P06 Kle P07 KI7 P10 LEDo P11 LED1 _P45 TX2inout lt gt ig P12 LED2 P44 INT1 TX1 Inout lt gt 19 P13 LED3 P43 INTo T XOINOUT lt gt 50 LEDs Connect oscillator circuit z lt S wW Ww O O D N ONE 77 D Q Joa vU U 2 P42 RxD1 gt p LEDs P41 TAQouT lt gt 59 LEDs P40 TAOIN TXD1 lt gt P17 LED7 Figure DD 1 Pin connections for serial I O mode 1 145 amp CA r PE E cute Mitsubishi microco puters oS NO M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode Mode setup method Signal Value CNVss VpPH RESET Vss gt Vcc lt gt P52 CLK0o AN52 lt gt P53 CLKS AN53 lt gt P54 CKouT AN54 lt gt P61 ANi lt gt P62 AN2 lt gt P63 AN3 lt gt P64 AN4 lt gt P66 ANe 5d 54 4d P51 RxDo AN51 lt gt lt gt P67 AN7 P50 TxDo ANs5
397. r empty flag T1 Transferred from UARTI transmit buffer register to UARTi transmit register Parity Stop Stopped pulsing because transmit enable bit 0 i TxDi Transmit register 1 empty flag TXEPT Transmit interrupt T request bit IR Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols The above timing applies to the following settings Tce 16 n 1 fior 16 n 1 fexT Parity is enabled fi frequency of BRGi count source f1 f8 32 fc One stop bit fEXT frequency of BRGi count source external clock e Transmit interrupt cause select bit 1 n value set to BRGi e Example of transmit timing when transfer data is 9 bits long parity disabled two stop bits Tc Transfer clock UUL ULUL IL UULU TULLU ULUL Transmit enable bit TE g Data is set in UARTi transmit buffer register Transmit buffer empty flag Tl Transferred from UARTi transmit buffer register to UARTi transmit register Stop Stop TxDi Transmit register 1 empty flag TXEPT Transmit interrupt 1 request bit IR Cleared to 0 when interrupt request is accepted or cleared by software Shown in are bit symbols The above timing applies to the following settings Te 16 n 1 fi or 16 n 1 fext Parity is disabled fi frequency of BRGi count source f1 f8 32 e Two stop bits fEXT frequency of BRGi coun
398. r Transferred from UARTO receive register Clock is generated by falling edge to UARTO receive buffer register Receive 4 of start bit complete flag A eee Read to UARTO receive buffer register Receive interrupt 1 request bit ee Ce Cleared to 0 when interrupt request is accepted or cleared by software Timing of transfer data 8 bits long applies to the following settings Transfer data length is 8 bits Parity is disabled One stop bit Figure 2 6 9 Operation timing of reception in UART mode 269 Q e Mitsubishi microcomputers Sy M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Setting UARTO transmit receive mode register b0 0 1 1 0 1 UARTO transmit receive mode register UOMR Address 03A016 Serial I O mode select bit b2 b1 b0 1 0 1 Transfer data 8 bits long Internal external clock select bit 1 External clock Note Stop bit length select bit 0 One stop bit Valid when bit 6 1 Parity enable bit 0 Parity diabled Sleep select bit 0 Sleep mode diabled Note UATRT1 cannot be selected external clock ye Setting UARTO transmit receive control register 0 b7 bO 0 0 UARTO transmit receive control register 0 UOCO Address 03A416 BRG count source select bit Invalid when external clock is selected Must be 0 in UART mode Transmit register empty flag 0 Data present in transmit register during t
399. r select register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset TRGSR 038316 0016 Timer AO event trigger select bit 99 Input on TAOIN is selected Note TB1 overflow is selected TAOTGH TX2 overflow is selected TXO overflow is selected Timer X0 event trigger Tier select bit Input on TXOINOUT is selected Note TB1 overflow is selected TXOTGH TAO overflow is selected TX1 overflow is selected TXITGL a ai evenuingaet Input on TX1INouT is selected Note TB1 overflow is selected TX1TGH TXO overflow is selected TX2 overflow is selected TX2TGL Timer X2 event trigger select bit Input on TX2iNouT is selected Note TB1 overflow is selected TX2TGH TX1 overflow is selected TAO overflow is selected Note Set the corresponding port direction register to O input mode Clock prescaler reset flag b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset CPSRF 038116 OXXXXXXX2 Bitsymbol Bitname Fuon RW Nothing is assigned When write set 0 When read their contents are indeterminate 0 No effect 1 Prescaler is reset When read the value is 0 r Clock prescaler reset flag Figure 1 59 Timer X related registers 3 68 x oe SS L ww A Timer X 1 Timer mode Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER In this mode the timer counts an internally generated count source See Table 1 21 Figure 1
400. ransmission 1 No data present in transmit register transmission completed Must be 1 in UART mode Data output select bit 0 TxDO pin is CMOS output 1 TxDO pin is N channel open drain output Must be 0 in UART mode Must be 0 in UART mode Setting UART transmit receive control register 2 b7 bO Xlo Jo I UART transmit receive control register 2 UCON Address 03B016 Invalid in UART mode Must be 0 in UART mode Invalid in UART mode Must be 0 in UART mode Continued to the next page Figure 2 6 10 Set up procedure of reception in UART mode 1 270 O aS Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Continued from the previous page Setting UARTO bit rate generator b7 bo TLLLILLLI UARTO bit rate generator Address 03A116 03A916 UOBRG a be set to 0016 to FF16 Note 1 Note 1 Write to UARTi bit rate generator when transmission reception is halted Reception enabled 7 rec UARTO transmit receive control register 1 U0C1 Address 03A516 UART1 transmit receive control register 1 U1C1 Address 03AD16 Receive enable bit 1 Reception enabled Note 2 Set the corresponding port direction register to 0 input mode Start reception Checking completion of reception b7 bO UARTO transmit receive control register 1 UOC1 Address 03A516 Receive complete flag 0 No data
401. rase bit reports the operating status of the auto erase operation If an erase error occurs it is set to 1 When the erase status is cleared it is set to O Program Bit SR4 The program bit reports the operating status of the auto write operation If a write error occurs it is set to 1 When the program status is cleared it is set to O 155 xX Cy O RX Mitsubishi microcomputers NO M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Appendix Standard Serial I O Mode Status Register 1 SRD1 Status register 1 indicates the status of serial communications results from ID checks and results from check sum comparisons It can be read after the SRD by writing the read status register command 7016 Also status register 1 is cleared by writing the clear status register command 5016 Table DD 3 gives the definition of each status register 1 bit 0016 is output when power is turned ON and the flag status is maintained even after the reset Table DD 3 Status register 1 SRD1 SRD1 bits Status name Definition gt Boot update completed bit Update completed Not update Reserved Reserved Checksum match bit Mismatch ID check completed bits Not verified Verification mismatch Reserved Verified SR9 bit1 Data receive time out Time out Normal operation SR8 bit0 Reserved 7 Boot Update Completed Bit SR15 This flag indicates whether the contr
402. re 2 6 9 shows the operation timing and Figures 2 6 10 and 2 6 11 show the set up procedures Table 2 6 5 Choosed functions Transfer clock Internal clock f1 fs f32 fc source External clock CLKO pin Note Sleep mode Sleep mode off Sleep mode selected Note UART1 cannot be selected external clock Operation 1 Setting the receive enable bit to 1 readies data receivable status 2 When the first bit the start bit of reception data is received from the RxDi pin Then data is received bit by bit in sequence LSB MSB and stop bit s 3 When the stop bit s is are received the content of the UARTi receive register is transmitted to the UARTIi receive buffer register At this time the receive complete flag goes to 1 to indicate that the reception is completed the UARTI receive interrupt request bit goes to 1 4 The receive complete flag goes to 0 when the lower order byte of the UARTi buffer register is read 268 O aS Mitsubishi microcomputers SX M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Example of wiring Microcomputer Transmitter side IC CLKO CLK RxDO TxD Example of operation 4 Data is read 1 Reception enabled 3 Receiving is 2 Start reception 3 g completed source JUU a Receive enable i bit rd i l pa A D7 Stop bit i Receive data taken in Transfer clock 7 a T e Reception started when transfe
403. rescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O s Setting count start flag b7 Count start flag Address 038016 TABSR Timer BO count start flag Timer B1 count start flag Start count Clearing overflow flag Timer Bi T register i 0 1 Address 039B16 039C16 TEX CLO TBIMR i 0 1 Timer Bi overflow flag 0 Timer did not overflow Figure 2 3 11 Set up procedure of pulse width measurement mode 205 x A O S Mitsubishi microcomputers VO M30201 Group v SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 3 6 Precautions for Timer B timer mode event counter mode 1 To clear reset the count start flag is set to 0 Set a value in the timer Bi register then set the flag to 1 2 Reading the timer Bi register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer Bi register with the reload timing shown in Figure 2 3 12 gets FFFF16 Reading the timer Bi register after setting a value in the timer Bi regis ter with a count halted but before the counter starts counting gets a proper value Reload Read value Hex f 2 1 oo FFFF I Time n reload register content Figure 2 3 12 Reading timer Bi register 206 Ni O aS Mitsubishi microcomputers SX ef M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B 2 3 7 Prec
404. ress Address L to address H Software interrupt number Interrupt source Remarks Software interrupt number 0 0 to 3 Note BRK instruction Cannot be masked by flag Software interrupt number 11 44 to 47 Note Software interrupt number 12 Note Software interrupt number 13 52 to 55 Note Key input interrupt Software interrupt number 14 Note 48 to 51 Note Note Note 56 to 59 Note A D Software interrupt number 17 68 to 71 Note UARTO transmit Software interrupt number 18 72 to 75 Note UARTO receive Software interrupt number 19 76 to 79 Note UART1 transmit Software interrupt number 20 80 to 83 Note UART1 receive Software interrupt number 21 84 to 87 Note Timer AO Software interrupt number 22 88 to 91 Note Timer XO Software interrupt number 23 92 to 95 Note Timer X1 Software interrupt number 24 96 to 99 Note Timer X2 Software interrupt number 25 100 to 103 Note Software interrupt number 26 104 to 107 Note Timer BO Software interrupt number 27 108 to 111 Note Timer B1 Software interrupt number 28 112 to 115 Note Software interrupt number 29 116 to 119 Note INTO Software interrupt number 30 120 to 123 Note INT1 Software interrupt number 3
405. ristics Output current 5mA 15mA LED drive port Device configuration CMOS silicon gate Package 52 pin plastic mold SDIP 56 pin plastic mold QFP O s Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Description Mitsubishi plans to release the following products in the M30201 group 1 Support for mask ROM version and flash memory version 2 ROM capacity 3 Package 52P4B Plastic molded SDIP mask ROM version and flash memory version 56P6S A Plastic molded QFP mask ROM version and flash memory version July 1998 RAM Size Byte 2K M30201F6SP FP M30201F6TSP FP Under development M30201M4 XXXSP FP M30201M4T XXXSP FP Under development M30201M2 XXXSP FP M30201M2T XXXSP FP Under planning Figure 1 4 ROM expansion Type No M30201M4T XXX SP i Package type SP Package 52P4B FP Package 56P6S A ROM No Omitted for flash memory version Shows difference of characteristics and usage etc Nothing Common T Automobiles ROM capacity 2 16K bytes 4 32K bytes 6 48K bytes Memory type M Mask ROM version F Flash memory version Shows pin count etc The value itself has no specific meaning M16C 20 Group M16C Family Figure 1 5 Type No memory size and package A S S S eS Pin Description Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT C
406. riting to port P4 direction 0 Write inhibited register address 03EA16 Note 1 Write enabled Nothing is assigned These bits can neither be set nor reset When read their contents are indeterminate Note Writing a value to an address after 1 is written to this bit returns the bit to 0 Other bits do not automatically return to 0 and they must therefore be reset by the program Figure 1 21 Protect register 28 N S Mitsubishi microcomputers RA Sas M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Overview of Interrupt Type of Interrupts Figure 1 22 lists the types of interrupts Undefined instruction UND instruction Overflow INTO instruction Software 4 _ BRK instruction INT instruction Interrupt P Reset DBC Special Watchdog timer Single step Hardware Address matched Peripheral I O 1 Peripheral I O interrupts are generated by the peripheral functions built into the microcomputer system Figure 1 22 Classification of interrupts e Maskable interrupt An interrupt which can be enabled disabled by the interrupt enable flag I flag or whose interrupt priority can be changed by priority level e Non maskable interrupt An interrupt which cannot be enabled disabled by the interrupt enable flag I flag or whose interrupt priority cannot be changed by priority level 29 X Se Q s Mitsubishi microcomputers DO M3020
407. rol register 1 FCON1 Note 128 03F516 03B616 Flash command register FCMD Note 03F616 03B716 03F716 03B816 03F816 03B916 03F916 03BA16 03FA16 03BB16 03FB16 03BC16 03FC16 _Pull up control register 0 PURO 03BD16 03FD16 _Pull up control register 1 PUR1 106 03BE16 03FE16 Pull up control register 2 PUR2 03BF16 03FF16 Note This register is only exist in flash memory version Chapter 1 Hardware Q s Mitsubishi microcomputers SX M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Description Description The M30201 group of single chip microcomputers are built using the high performance silicon gate CMOS process using a M16C 60 Series CPU core M30201 group is packaged in a 52 pin plastic molded SDIP or 56 pin plastic molded QFP These single chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency With 1M bytes of address space they are capable of execut ing instructions at high speed The M30201 group includes a wide range of products with different internal memory types and sizes and various package types Features e Basic machine instructions 4 Compatible with the M16C 60 series e Memory Capacity ceeeeeeseeeeeenes ROM RAM See figure 1 4 ROM expansion e Shortest instruction execution time 100ns f XIN 10MHz e Supply Voltage snesen 4 0 to 5 5V f XIN 10MHz mask ROM version 2 7 to
408. ronous serial I O mode 243 N amp gs Mitsubishi microcomputers Sty M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Setting UARTO transmit receive mode register b7 UARTO transmit receive mode register 0 0 0 UOMR Address 03A016 Must be fixed to 001 Internal external clock select bit 0 Internal clock Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Invalid in clock synchronous I O mode Sleep select bit Must be 0 in clock synchronous I O mode Setting UARTO transmit receive control register 0 UARTO transmit receive control register 0 U0CO Address 03A416 BRG count source select bit b1 b0 0 0 f1 is selected 0 1 fs is selected 1 0 f32 is selected 11 fc is selected Must be 0 in clock synchronous I O mode Transmit register empty flag 0 Data present in transmit register during transmission 1 No data present in transmit register transmission completed Must be 1 in clock synchronous I O mode Data output select bit Note 0 TxDi pin is CMOS output 1 TxDi pin is N channel open drain output CLK polarity select bit 0 Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 LSB first
409. rrupt request bit goes to 1 If the TAOOUT pin is outputting an L level in this instance the level does not change and the timer AO interrupt request bit does not becomes 1 108 X Ss O Ss Mitsubishi microcomputers Sy M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Usage precaution Timer B timer mode event counter mode 1 Reading the timer Bi register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer Bi register with the reload timing gets FFFF16 Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a proper value Timer B pulse period pulse width measurement mode 1 If changing the measurement mode select bit is set after a count is started the timer Bi interrupt request bit goes to 1 2 When the first effective edge is input after a count is started an indeterminate value is transferred to the reload register At this time timer Bi interrupt request is not generated Timer X timer mode 1 Reading the timer Xi register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer Xi register with the reload timing gets FFFF16 Reading the timer AO register after setting a value in the timer Xi register with a count halted but before the counter starts counting gets a proper
410. rt counting the count source 2 If an effective edge of a pulse to be measured is input the value of the counter goes to 000016 and measurement is started In this instance an indeterminate value is transferred to the reload register The timer Xi interrupt request does not generate 3 If an effective edge of a pulse to be measured is input again the value of the counter is transferred to the reload register and the timer Xi interrupt request bit goes to 1 Then the value of the counter becomes 000016 and measurement is started again Note e The timer Xi interrupt request bit goes to 1 when an effective edge of a pulse to be measured is input or timer Xi is overflows The factor of interrupt request can be determined by use of the timer Xi overflow flag within the interrupt routine e The value of the counter at the beginning of a count is indeterminate Thus there can be in stances in which the timer Xi overflow flag goes to 1 immediately after a count is performed e The timer Xi overflow flag goes to 0 if timer Xi mode register is written to when the count start flag is 1 This flag cannot be set to 1 by software 1 Start count 3 Start measurement again 2 Start measurement Count source LLL Le H Measurement pulse ia i a i Transfer Transfer measured value f indeterminate L l it Li Reload register lt counter value transfer timing Timing at which counter re
411. rt flag Cleared to 0 when interrupt request is cere io when ierupt requests accepten or cleared by software Timer Bi interrupt q request bit o q Timer Bi overflow flag g E ee Note 1 Counter is initialized at completion of measurement Note 2 Timer has overflowed Figure 2 3 8 Operation timing of pulse period measurement mode 202 x O S S Mitsubishi microcomputers Sy O M30201 Group 2 SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer B Selecting pulse period pulse width measurement mode and functions Timer Bi mode register i 0 1 Address 039B16 039C16 TBiMR i 0 1 Selection of pulse period pulse width measurement mode Measurement mode select bit b3 b2 0 0 Pulse period measurement Interval between measurement pulse falling edge to falling edge Timer Bi overflow flag 0 Timer did not overflow 1 Timer has overflowed Count source select bit b7 b6 l Count Count source period 00 f source Xin 10MHz_ f XciN 32 768kHz Ke 100ns a 800ns 1 fc32 3 24s 976 56us Note Set the corresponding port direction register which sets the measurement pulse to 0 input mode P Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 bO Clock prescaler reset flag Address 038116
412. ruction is arranged in each CODE CODE_74 STE MOV PUSH NEG ROT NOT LDE POP SHL SHA CODE_75 STE MOV PUSH NEG ROT NOT LDE POP SHL SHA CODE_76 TST XOR AND OR ADD SUB ADC SBB CMP DIVX ROLC RORC DIVU DIV ADCF ABS CODE_77 TST XOR AND OR ADD SUB ADC SBB CMP DIVX ROLC RORC DIVU DIV ADCF ABS CODE_7A XCHG LDC CODE_7B XCHG STC CODE_7C MOV Dir MULU MUL EXTS STC DIVU DIV PUSH DIVX DADD DSUB DADC DSBB SMOVF SMOVB SSTR ADD LDCTX RMPA ENTER CODE_7D JMPI JSRI MULU MUL PUSHA LDIPL ADD J Cnd BMCnd DIVU DIV PUSH DIVX DADD DSUB DADC DSBB SMOVF SMOVB SSTR STCTX RMPA EXITD WAIT CODE_7E BTSTC BM Cnd BNTST BAND BNAND BOR BNOR BCLR BSET BNOT BTST BXOR BNXOR CODE_EB SHL FSET FCLR MOVA LDC SHA PUSHC POPC INT 386 Appendix 2 Hexadecimal instruction CODE table 387 D7 to D4 1000 1001 1010 1011 1100 1101 1110 1111 D3 to DO 8 9 A B C D E F 0000 0 TST B AND B G ADD B G ADC B CMP B G CMP B Q ROT B SHA B src dest src dest src dest src dest src dest IMM dest IMM dest IMM dest 0001 1 TST W AND W G ADD W G ADC w CMP W G CMP W Q ROT W SHA W src dest src dest src dest src dest src dest IMM dest IMM dest IMM dest 0010 2 PUSH B S POP B S MOV W S INC W PUSH W S POP W S MOV B S DEC W ROL ROL IMM AO AO AO AO IMM AO AO 0011 3 ADD B S AND B S NC B MOV B Z MOV B S STNZ CMP B S RTS IMM8 ROH IMM8 ROH ROH 0 ROH IMM8 ROH IMM8 ROH IMM8 ROH 0100 4 ADD B S AND B
413. run type selected 220 x N O aS Mitsubishi microcomputers SX of M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Selecting event counter mode and functions 1 po Timer Xi mode register i 0 to 2 Address 039716 to 039916 TXiMR i 0 to 2 Selection of event counter mode Pulse output function select bit 0 Pulse is not output Count polarity select bit 0 Counts external signal s falling edge Invalid in event counter mode Can be 0 or 1 0 Must always be 0 in event counter mode Count operation type select bit 1 Free run type Invalid in event counter mode Can be 0 or 1 Setting trigger select register br gt o Trigger select register Address 038316 TRGSR Timer X0 event trigger select bit b3 b2 0 0 Input on TXOINOUT is selected Note Timer X1 event trigger select bit b5 b4 0 0 Input on TX1INOUT is selected Note Timer X1 event trigger select bit b7 b6 0 0 Input on TX2INOUT is selected Note Note Set the corresponding port direction register to 0 input mode r Setting divide ratio b15 b8 Bf po be b0 Timer XO register Address 038916 038816 TXO Timer X1 register Address 038B16 038A16 TX1 Timer X2 register Address 038D16 038C16 TX2 Can be set to 000016 to FFFF16 k Setting count start flag b7 b0 Count start flag Address 03801
414. s Figure 2 7 17 shows theoretical A D conversion characteristics Table 2 7 7 Relationship of the successive comparison register contents and Vref Successive approximation register n Vref V 0 1 01023 289 Q rs Mitsubishi microcomputers Sy M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter Table 2 7 8 Variation of the successive comparison register and Vref while A D conversion is in progress 10 bit mode VREF V 2 M VREF VREF 1st comparison gt 9048 V 4 n9 1 VREF VREF VREF V 2 A D converter stopped 2nd comparison u 0 2 4 2048 no 0 4 4 4st comparison result ve 3rd comparison ngns 1lololololo VREF VREF VREF VREF v k l 2 4 8 2048 ns 0 2nd comparison result 10th comparison ns nelnsln4ln3 VREF 4 VREF 4 VREF VREF _ VREF y 2 4 1024 2048 Conversion complete ng n7 n6 nd n4 n3 n2 n1 no This data transfers to the bit 0 to bit 9 of A D register Result of A D conversion Theoretical A D conversion characteristic Ideal A D conversion characteristic VREF VREF VREF VREF V 1024X 3 1024 1021 1024 1022 1024 1028 Analog input voltage Figure 2 7 17 Theoretical A D conversion characteristics 10 bit mode 290 xX Cy O s Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP
415. s 182 2 2 10 Operation of Timer A one shot timer mode external trigger selected cceeeeeeee 184 2 2 11 Operation of Timer A pulse width modulation mode 16 bit PWM mode selected 186 2 2 12 Operation of Timer A pulse width modulation mode 8 bit PWM mode selected 188 2 2 13 Precautions for Timer A timer MOE eee eeeeeee eee eete cette eece ee ee etna eee ee eaaeeeeeeeaeeeeeeenaeeeeeneaa 190 2 2 14 Precautions for Timer A event counter mode eeeeeeeeeeeeeeee cette eteeeeeeeaaeeeeeteaeeeeeeenea 191 2 2 15 Precautions for Timer A one shot timer MOE ee eeeeeeeeeeeeneeeeeee eee eeeeeetaeeeeeeetaeeeeeee 192 2 2 16 Precautions for Timer A pulse width Modulation mode eeeeeeeeeeeeeeee eee eeteeeeteeeteeeeeeeee 193 2S AMIMON Bia tryta te oe Oe leh a e el ast Aid CAs i eed Lat oud OM Tol Gala cates A 194 2 Srl CVEIVIOW Ss esc icc a tact aehca bas genoa cd satus desired a a aa aE e E 194 2 3 2 Operation of Timer B timer mode ceeeecceeeeeeeeeee cece eeeeeaeeeeeeeeeeeaeeeeeeeeesaaeeeeeaeeeseaeeeteaaeeee 198 2 3 3 Operation of Timer B event Counter mode cceeeeeeeeeeeeeeeeeeeeaeeeeeeeeeeaeeeeeneeeeeeeeeenaeeee 200 2 3 4 Operation of Timer B pulse period measurement mode cceeccceeesteceeeeeseteeeeeeeseeeeeeeees 202 2 3 5 Operation of Timer B pulse width measurement mode ceeeececeeesseceeeeeseteeeeeessteeeeeeeees 204 2 3 6 Precautions for T
416. s acknowledged 13 X O R Mitsubishi microcomputers DO M30201 Group x SINGLE CHIP 16 BIT CMOS MICROCOMPUTER CPU e Bit 7 Stack pointer select flag U flag Interrupt stack pointer ISP is selected when this flag is O user stack pointer USP is selected when this flag is 1 This flag is cleared to O when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos 0 to 31 is executed e Bits 8 to 11 Reserved area e Bits 12 to 14 Processor interrupt priority level IPL Processor interrupt priority level IPL is configured with three bits for specification of up to eight processor interrupt priority levels from level 0 to level 7 If a requested interrupt has priority greater than the processor interrupt priority level IPL the interrupt is enabled Bit 15 Reserved area The C Z S and O flags are changed when instructions are executed See the software manual for details RO Note b15 b8 b7 bO b19 bo R 1 Note H L PC Program cour UNE es se 1 AN LILLIE Pitt tEppppttet ppt typ tt L Data registers b15 bO R2 Note Interrupt table HRN A D D D D D B A A B A B register b15 R3 Note USP User stack po ES A V A S D A te O S S D DA S bo b15 bo AO Note ISP memupt stacl pburitiititiiiilt Litititiriiiiitt pointer Address b15 bo registers A1 Note Static base AL A register
417. s at the same time And also set the main clock stop bit CM05 to 0 and stabilize the main clock oscillating before setting this bit from 1 to 0 e 7 This bit changes to 1 when shifting from high speed medium speed mode to stop mode and at a reset When shifting rom low speed low power dissipation mode to stop mode the value before stop mode is retained e 8 fc32 is not included No No No System clock control register 1 Note 1 b6 b5 b4 b3 b2 bi b0 0 0 0 0 Symbol CM1 Address 000716 When reset 2016 Bit symbol Bit name Function CM10 All clock stop control bit Note 4 Reserved bit 0 Clock on 1 All clocks off stop mode Always set to 0 Reserved bit Reserved bit Always set to 0 Always set to 0 Reserved bit CM15 XIN XOUT drive capacity select bit Note 2 Always set to 0 0 LOW 1 HIGH CM16 CM17 Main clock division select bit 1 Note 3 b7 b6 0 0 No division mode 0 1 Division by 2 mode 1 0 Division by 4 mode 1 1 Division by 16 mode Note 1 Set bit 0 of the protect register address 000A16 to 1 before writing to this register Note 2 This bit changes to 1 when shifting from high speed medium speed mode to stop mode and at a reset When shifting from low speed low power dissipation mode to stop mode the value before stop mode is retained Note
418. s in progress allows reading with arbitrary timing the value of the counter Reading the timer Xi register with the reload timing shown in Figure 2 4 24 gets FFFF16 Reading the timer Xi register after setting a value in the timer Xi regis ter with a count halted but before the counter starts counting gets a proper value Reload Read value Hex ESEA FFFF ie Time n reload register content Figure 2 4 24 Reading timer Xi register 232 x Cy amp s Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 13 Precautions for Timer X one shot timer mode 1 To clear reset the count start flag is set to O Set a value in the timer Xi register then set the flag to 1 2 Setting the count start flag to 0 while a count is in progress causes as follows e The counter stops counting and a content of reload register is reloaded e The TXiINOUT pin outputs L level e The interrupt request generated and the timer Xi interrupt request bit goes to 1 3 The timer Xi interrupt request bit goes to 1 if the timer s operation mode is set using any of the following procedures e Selecting one shot timer mode after reset e Changing operation mode from timer mode to one shot timer mode e Changing operation mode from event counter mode to one shot timer mode Therefore to use timer Xi interrupt interrupt request bit set timer
419. s shown by the waveforms in Connect to the diagrams on the left Connect to O SW4 conducts only when A D conversion is not in progress Control signal for SW3 Connect to Warning Use only as a standard for designing this data Mass production may cause some changes in device characteristics Figure 2 7 22 Internal equivalent circuit to analog input 295 X Ss RY sO RY Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 12 Sensor s Output Impedance under A D Conversion To carry out A D conversion properly charging the internal capacitor C shown in Figure 2 7 23 has to be completed within a specified period of time With T as the specified time time T is the time that switches SW2 and SW3 are connected to O in Figure 2 7 22 Let output impedance of sensor equivalent circuit be RO microcomputer s internal resistance be R precision error of the A D converter be X and the A D converter s resolution be Y Y is 1024 in the 10 bit mode and 256 in the 8 bit mode t Vc is generally Vc VIN 1 e C RO R Andwhent T Vc VIN SVINeviN t Hence RO R Cen X Y With the model shown in Figure 2 7 29 as an example when the difference between VIN and Vc becomes 0 1LSB we find impedance RO when voltage between pins Vc changes from 0 to VIN 0 1 1024 VIN in time T 0 1 1024 means that A D precision drop due to insufficient capacitor
420. s started In this instance an indeterminate value is transferred to the reload register The timer Bi interrupt request does not generate 3 If a measurement pulse changes from H to L again the value of the counter is transferred to the reload register and the timer Bi interrupt request bit goes to 1 Then the value of the counter becomes 000016 and the measurement is started again Note e The timer Bi interrupt request bit goes to 1 when an effective edge of a measurement pulse is input or timer Bi is overflowed The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine e The value of the counter at the beginning of a count is indeterminate Thus there can be in stances in which the timer Bi overflow flag goes to 1 immediately after a count is performed e The timer Bi overflow flag goes to 0 if timer Bi mode register is written to when the count start flag is 1 This flag cannot be set to 1 by software Measurement of pulse time interval from falling edge to falling edge 1 Start count 2 Start measurement 3 Start measurement again Count source wt i Measurement pulse Transfer 4 Transfer Reload register lt counter i indeterminate value gt measured value transfer timing ee sin uM i Note 1 w Note 1 x Note 2 q Timing at which counter reaches 000016 E Count sta
421. se is not output TAQOUT pin is a normal port pin Gate function select bit b4 b3 00 01 Gate function not available TAOIN pin is a normal port pin 0 Must always be 0 in timer mode eal source select bit Count Count source period 00 fi Source f XIN 10MHz f XcIN 32 768kHz 0 1 f8 100ns 10 f32 800ns 11 fc32 3 Dus 976 56us k Setting divide ratio b15 b8 b7 bO b7 bO A N o Ooo Can be set to 000016 to FFFF16 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XCIN by 32 b7 bO Clock prescaler reset flag Address 038116 L PEPPE CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is 0 ie Setting count start flag b7 bO Count start flag Address 038016 TABSR Timer AO count start flag Start count Figure 2 2 7 Set up procedure of timer mode 169 Mitsubishi microcomputers K M30201 Group ww SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 2 2 3 Operation of Timer A timer mode gate function selected In timer mode choose functions from those listed in Table 2 2 2 Operations of the circled items are described below Figure 2 2 8 shows the operation timing and Figure 2 2 9 shows the set up procedure Table 2 2 2 Choosed functions
422. se is output TX1INOUT pin is pulse output pin External trigger select bit Invalid when choosing timer s overflow Trigger select bit 1 Selected by event trigger select register 0 Must always be 0 in one shot timer mode Gout source select bit r Toim Count source pened 00 f1 p source Xin 10MHz_ f XciN 32 768kHz 100ns 800ns 3 2us 976 56us Note Set the corresponding port direction register to 1 output mode Setting trigger select register Set timer XO to trigger timer X1 Ceo ee register Address 038316 Timer X1 event trigger select bit b5 b4 1 0 TXO overflow is selected r Setting one shot timer s time b15 b8 br bo b7 50 Timer X1 register Address 038B16 038A16 Setting count start flag bo XA EEL Coun sran flag Address 038016 Timer X0 count start flag 1 Starts counting Timer X1 count start flag 1 Starts counting Start countin Figure 3 3 4 Set up procedure of delayed one shot output 2 337 x O S Mitsubishi microcomputers DO M30201 Group amp a SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications 3 4 Buzzer Output Overview The timer mode is used to make the buzzer ring Figure 3 4 1 shows the operation timing and Figure 3 4 2 shows the set up procedure Use the following peripheral function e The pulse outputting function in timer mode of timer X Speci
423. select bit 1 XCIN XCOUT Stopping main clock b7 b0 System clock control register 0 Address 000616 HITTI o sli l Main clock XIN XOUT stop bit 1 Off Interrupt enable flag I flag ale F_WIT 1 WAIT instruction NOP instruction X 5 INTO interrupt request generated _ A TBO interrupt request generated Starting main clock oscillator b7 b0 Jo T System clock control register 0 Address 000616 CMO Main clock XIN XOUT stop bit 0 On Switching system clock b7 b0 Syst lock control register 0 Add 0006 oT Td TL TT 7 a clock control register ress 16 System clock select bit 0 XIN XOUT Figure 3 7 3 Set up procedure of controlling power using wait mode 2 348 xe amp Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications INTO interrupt Timer BO interrupt Store the registers Store the registers F_WIT 0 Counting clock Restore the registers Restore the registers REIT instruction REIT instruction Figure 3 7 4 Set up procedure of controlling power using wait mode 3 349 Chapter 4 Interrupt xX Cy xe Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 1 Overview of Interrupt 4 1 1
424. select bit 1 1 PWM mode MRO 1 Must always be 1 in PWM mode MR1 Invalid in PWM mode Can be 0 or 1 MR 16 8 bit PWM mode 0 Functions as a 16 bit pulse width modulator select bit 1 Functions as an 8 bit pulse width modulator TCKO Count source select bit TCK1 MR2 Trigger select bit 0 Count start flag is valid Note 1 1 Selected by event trigger select register i eo Note 1 TXiINOUT pin inout cannot be selected by the event trigger select bit addresses 038316 Note 2 Set the corresponding port direction register to 1 output mode Figure 1 66 Timer Xi mode register in pulse width modulation mode 74 x A xe S Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Condition Reload register 000316 when trigger timer overflow is selected 1 fix 2 e 1 Count source Trigger signal tH i be E Trigger is not generated by this signal lt 1 fixn PWM pulse output H from TXiINOUT pin w Timer Xi interrupt request bit fi Frequency of count source f1 f8 f32 fc32 Cleared to 0 when interrupt request is accepted or cleared by software Note1 n 000016 to FFFF 16 Figure 1 67 Example of how a 16 bit pulse width modulator operates Condition Reload register high order 8 bits 0216 Reload register low order 8 bits 0216 Trigger timer overflow is selected 1 fi X m 1 X 28 1 C
425. served bit Always set to 0 o 0 Nothing is assigned When write set 0 When read their contents are indeterminate Note This bit can only be accessed for reset 0 but cannot be accessed for set 1 Figure 1 24 Interrupt control register 35 N Q amp Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Interrupt Enable Flag The interrupt enable flag I flag controls the enabling and disabling of maskable interrupts Setting this flag to 1 enables all maskable interrupts setting it to O disables all maskable interrupts This flag is set to 0 after reset Interrupt Request Bit The interrupt request bit is set to 1 by hardware when an interrupt is requested After the interrupt is accepted and jumps to the corresponding interrupt vector the request bit is set to 0 by hardware The interrupt request bit can also be set to 0 by software Do not set this bit to 1 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level IPL Set the interrupt priority level using the interrupt priority level select bit which is one of the component bits of the interrupt control register When an interrupt request occurs the interrupt priority level is compared with the IPL The interrupt is enabled only when the priority level of the interrupt is higher than the IPL Therefore setting the interrupt priority level to O disables the
426. sh memory modes are available in which to read program and erase parallel I O and standard serial I O modes in which the flash memory can be manipulated using a program mer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit CPU Each mode is detailed in the pages to follow In addition to the ordinary user ROM area to store a microcomputer operation control program the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I O modes This boot ROM area has had a standard serial I O mode control program stored in it when shipped from the factory However the user can write a rewrite control program in this area that suits the user s application system This boot ROM area can be rewritten in only parallel 1 O mode Microcomputer mode Parallel I O mode CPU rewrite mode Standard serial I O mode 0000016 0040016 YYYYY16 DF00016 Collective erasable programmable Boot ROM Boot ROM area area 4K bytes 4K bytes DFFFF16 Collective Collective User ROM erasable User ROM erasable User ROM area programmable area programmable area FFFFF16 Note 1 In CPU rewrite and standard serial I O modes the user ROM is the only erasable programmable area Note 2 In parallel I O mode the area to be erased programmed can be selected by the address A17 input The user ROM area is selected when this address input is high and th
427. ss 03C716 03C616 A D register4 Address 03C916 03C816 A Dregister5 Address 03CB16 03CA16 A D register6 Address 03CD16 03CC16 A D register 7 Address 03CF 16 03CE16 Eight low order bits of A D conversion result During 10 bit mode Two high order bits of A D conversion result During 8 bit mode When read the content is indeterminate XN Setting A D conversion start flag b7 b0 0 A D control register 0 Address 03D616 ADCONO A D conversion start flag 0 A D conversion disabled Stop A D conversion Figure 2 7 15 Set up procedure of repeat sweep 1 mode 287 N S Mitsubishi microcomputers FS S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 2 7 7 Precautions for A D Converter 1 Write to each bit except bit 6 of A D control register 0 to each bit of A D control register 1 and to bit 0 of A D control register 2 when A D conversion is stopped before a trigger occurs In particular when the Vref connection bit is changed from 0 to 1 start A D conversion after an elapse of 1 ms or longer 2 To reduce conversion error due to noise connect a voltage to the AVcc pin and to the Vref pin from an independent source It is recommended to connect a capacitor between the AVss pin and the AVcc pin between the AVss pin and the Vref pin and between the AVss pin and the analog input pin ANi ANSsi Figure 2 7
428. ssion data 7 af ENENEENENNNNEENENENENNNNNNNNENNNNNNNENNNNNENNNNNNANENENNNNENENNNNNNENNNNNEENNANNNNENENET i sonnunnnunnunnannnunnannannnnnnnnnnnan nnu TPANSMISSION is complete Figure 2 5 10 Set up procedure of transmission in clock synchronous serial I O mode transfer clock output from multiple pins function selected 2 249 N amp amp Mitsubishi microcomputers R Sty M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O 2 5 4 Operation of Serial I O reception in clock synchronous serial I O mode In receiving data in clock synchronous serial I O mode choose functions from those listed in Table 2 5 3 Operations of the circled items are described below Figure 2 5 11 shows the operation timing and Fig ures 2 5 12 and 2 5 13 show the set up procedures Table 2 5 3 Choosed functions Transfer clock Internal clock f1 fs f32 fc source External clock CLKO pin CLK polarity Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer clock Transfer clock LSB first MSB first Continuous receive Disabled d a Enabled Output transfer clock Not selected to multiple pins Note se Selected Note This can be selected only when UARTO is used in combination with the internal clock Operation 1 Writing dummy data to the UARTO transmit buffer register setti
429. ster addresses 03A616 and 0 3AE16 is read out UARTI bit rate generator b7 bO Address When reset 03A116 Indeterminate 03A916 Indeterminate Values that can be set Assuming that set value n BRGi divides the 0016 to FF16 count source by n 1 Figure 2 5 2 Serial l O related registers 1 239 Mitsubishi microcomputers M30201 Group og SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O UARTI transmit receive mode register Address 03A016 03A816 When reset 0016 b7 b6 b5 b4 b3 b2 bi b0 Symbol UiMR i 0 1 Function During clock synchronous serial I O mode Must be fixed to 001 b2 b1 b0 0 0 0 Serial I O invalid 010 Inhibited 0 1 1 Inhibited 111 Inhibited Function Bit name During UART mode ny 0 009 43200005 Serial I O mode select bit Note 1 ee Transfer data 8 bits long Transfer data 9 bits long Serial I O invalid Inhibited Inhibited Inhibited 000 p 0 Internal clock 1 External clock 0 One stop bit 1 Two stop bits Valid when bit 6 1 0 Odd parity 1 Even parity 0 Parity disabled 1 Parity enabled 0 Internal clock 1 External clock Internal external clock select bit Note 2 Stop bit length select bit Invalid Odd even parity select bit Invalid PRYE Parity enable bit Invalid Sleep select bit Must always be 0 0 Sleep mode deselecte
430. stored from the stop mode operation starts in the 8 division mode Also if operation was performed in the low speed mode prior to engaging the stop mode CMO06 CM17 CM16 and CM07 do not change When operation is restored from the stop mode operation starts in the low speed mode Table 2 11 1 Interrupts available for clearing stop mode and wait mode Interrupt for clearing Key input interrupt Wait mode CM02 0 Possible CM02 1 Possible Stop mode Possible A D interrupt Note 3 Impossible Impossible UARTO transmit interrupt Possible Note 1 Note 1 UARTO receive interrupt Possible Note 1 Note 1 UART1 transmit interrupt Possible Impossible Impossible UART1 receive interrupt Possible Impossible Impossible Timer AO interrupt Possible Note 2 Note 2 Timer BO interrupt Possible Note 2 Note 2 Timer B1 interrupt Possible Note 2 Note 2 Timer XO interrupt Possible Note 2 Note 2 Timer X1 interrupt Possible Note 2 Note 2 Timer X2 interrupt Possible Note 2 Note 2 INTO interrupt Possible Possible Possible INT1 interrupt Possible Possible Possible Note 1 Can be used when an external clock in clock synchronous serial I O mode is selected Note 2 Can be used when the external signal is being counted in event counter mode Note 3 Can be used i
431. structions can be used as 2 byte instructions reducing the number of program steps 0000016 SFR area For details see Figures 1 7 to 1 8 FFE0016 0040016 Internal RAM area Special page vector table i Undefined instruction Address Address XXXXX1s YYYYYi6 M30201M4 F800016 007FF16 BRK instruction Address match M30201M2 FC00016s 005FF16 Single step pem timer M30201F6 F400016 00BFF16 Internal ROM area FFFFF16 Figure 1 6 Memory map amp Mitsubishi microcomputers NO M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER 000016 004016 000116 004116 000216 004216 000316 004316 000416 Processor mode register 0 PMO 004416 000516 Processor mode register 1 PM1 004516 000616 System clock control register 0 CMO 004616 000716 System clock control register 1 CM1 004716 000816 004816 000916 Address match interrupt enable register AIER 000A16 Protect register PRCR 004916 000Bi6 000C16 004A16 000D16 004B16 000E16 Watchdog timer start register WDTS 004C16 000F1s Watchdog timer control register WDC 004D16 Key input interrupt control register KUPIC 001016 004E16 A D conversion interrupt control register ADIC 001116 Address match interrupt register 0 RMADO 004F16 001216 005016 001316 005116 UARTO transmit interrupt control register SOTIC 001416 005216 UARTO receive interrupt control register SORIC 001516 Address match interrupt regist
432. synchronous serial I O mode transfer clock output from multiple pins function selected 1 eS SSS SS SS SSS SS SS SS SS SS SS 248 x N xe sf Mitsubishi microcomputers ve M30201 Group d SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock Synchronous Serial I O Continued from the previous page fr Setting UARTO bit rate generator b7 b0 UARTO bit rate generator Address 03A116 UOBRG Po Can be set to 0016 to FF16 Note Note Write to UARTO bit rate generator when transmission reception is halted 7 Transmission enabled b7 bo KKK TT 4 UARTO transmit receive control register 1 Address 03A516 U0C1 Transmit enable bit 1 Transmission enabled r Writing transmit data b8 b0 b7 UARTO receive buffer register Address 03A316 03A216 UOTB Setting transmission data A m LLLLLLLLLLLLLLLLLTETLLLETETTETETETTTEEEETETETETTETTETTTETET Start transmission r Checking the status of UARTO transmit buffer register b7 b0 IEX UARTO transmit receive control register 1 Address 03A516 U0C1 Transmit buffer empty flag 0 Data present in transmit buffer register 1 No data present in transmit buffer register Writing next transmit data enabled N Writing next transmit data b15 b8 b7 b0 b7 UARTO transmit buffer register Address 03A316 03A216 UOTB Setting transmi
433. t TXiINOUT pin is a normal port pin 1 Pulse is output Note 1 TXiINOUT pin is a pulse output pin i i b4 b3 Gale tunclionselece Dit 0 X Note 2 Gate function not available eo TXiINOUT pin is a normal port pin 10 Timer counts only when TXiINOUT MR2 pin is held L Note 3 1 1 Timer counts only when TXiINOUT pin is held H Note 3 R3 O10 M 0 Must always be fixed to 0 in timer mode TCKO Count source select bit TCK1 Note 1 Set the corresponding port direction register to 1 output mode Gate function cannot be selected when pulse output function is selected Note 2 The bit can be 0 or 1 Note 3 Set the corresponding port direction register to 0 input mode Pulse output function cannot be selected when gate function is selected Figure 1 60 Timer Xi mode register in timer mode 69 amp Q Mitsubishi microcomputers Sis M30201 Group F SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 Event counter mode In this mode the timer counts an external signal or an internal timer s overflow See Table 1 22 Figure 1 61 shows the timer Xi mode register in event counter mode Table 1 22 Timer specifications in event counter mode when not processing two phase pulse signal Count source External signals input to TXiINOUT pin effective edge can be selected by software TB1 overflow TAO overflow TXi overflow Count operation Down count When the timer underflo
434. t at the same time Pi 3 All clocks off stop mode b7 b0 o o ofoji CM1 All clock stop control bit 1 All clocks off stop mode Reserved bit Must be set to 0 System clock control register Address 000716 All clocks off stop mode Figure 2 11 5 Example of stop mode set up 315 xX amp Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Power Control 2 11 3 Wait Mode Set Up Settings and operation for entering wait mode are described here 1 Enables the interrupt used for returning from wait mode 2 Sets the interrupt enable flag I flag to 1 3 Clears the protection and changes the content of the system clock control register 4 Executes the WAIT instruction Operation _ a 1 Setting interrupt to cancel wait mode Interrupt control register KUPIC Address 004D16 ADIC Address 004E16 SiTIC i 0 1 Address 005116 005316 SiRIC i 0 1 Address 005216 005416 TAiIC i 0 Address 005516 TXiIC i 0 to 2 Address 005616 to 005816 TBIIC i 0 1 Address 005A16 005B16 INTiIC i 0 1 b7 bo bo Address 005Di6 005E16 an Interrupt priority level select bit Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority IPL of the routine where the WAIT
435. t bit 0 Sleep mode deselected 1 Sleep mode selected Note UART1 can use only internal clock Must set this bit to 1 Figure 1 79 UARTi transmit receive mode register in UART mode Table 1 29 lists the functions of the input output pins during UART mode Note that for a period from when the UARTI operation mode is selected to when transfer starts the TxDi pin outputs a H If the N channel open drain is selected this pin is in floating state Table 1 29 Input output pin functions in UART mode Pin name Function Method of selection TxDi Serial data output Port P51 and P42 direction register bit 0 at address 03EB16 bit 0 at P50 P40 address 03EA16 1 Can be used as an input port when performing reception only RxDi Serial data input Port P51 and P42 direction register bit 1 at address 03EB16 bit 2 at P51 P42 address 03EA16 0 Can be used as an input port when performing transmission only CLKO Programmable I O port Internal external clock select bit bit 3 at address 03A016 0 P52 Transfer clock input Internal external clock select bit bit 3 at address 03A016 1 87 x Q S Mitsubishi microcomputers ve M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock asynchronous serial I O UART mode Example of transmit timing when transfer data is 8 bits long parity enabled one stop bit Transfer clock Transmit enable bit TE Transmit buffe
436. t counter Mode OporatiQli fessietcccceetecceennetned ened euE A ENAERE east E ARES P218 e Event counter mode free run type operation ccecceeceeceeeneeeeeeeeeeeeeeceeeeeesaeeseeeeeessaeeeneneees P220 c One shot timer mode In this mode the timer is started by the trigger and stops when the timer goes to 0 The trigger can be selected from the following 3 types an external input signal an overflow of the timer or a software trigger e One shot timer mode operation eceecceeecceeeeeeeeeeeeeeeeeesaeeeeeaeeecaeeeeeaaeeseeeeesaaaeseeeeeessaaeeseneees P222 d Pulse period measurement pulse width measurement mode External pulse period or external pulse widths are measured If pulse period measurement mode is selected the periods of input pulses are continuously measured If pulse width measurement mode is selected widths of H level pulses and those of L level pulses are continuously measured e Operation in pulse period measurement MOE cceeececeeesteeeeeeeseeeeeeeeeseeeeeeesseeeeeeesseeeeeeees P224 e Operation in pulse width measurement MOE ccccecececeeesteeeeeeseeeeeeeeeesneeeeeeessieeeeeseseeeeeeens P226 d Pulse width modulation PWM mode In this mode the arbitrary pulses are successively output Either a 16 bit fixed period PWM mode or 8 bit variable period mode can be selected The trigger for initiating output can also be selected 16 bit PWM mode Operation wis 2 iaeecce een eiec
437. t flag Timer X2 count start flag Setting one shot start flag b7 b0 EECA One shot start flag Address 038216 ONSF ___ Timer X0 one shot start flag Timer X1 one shot start flag Timer X2 one shot start flag Start count Figure 2 4 15 Set up procedure of one shot mode 223 O Ss Mitsubishi microcomputers SF of M30201 Group ro SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 2 4 8 Operation of Timer X pulse period measurement mode In pulse period pulse width measurement mode choose functions from those listed in Table 2 4 7 Op erations of the circled items are described below Figure 2 4 16 shows the operation timing and Figure 2 4 17 shows the set up procedure Table 2 4 7 Choosed functions Count source Internal count source f1 fs f32 fc32 Measurement Pulse period measurement interval between measurement pulse falling edge to falling edge mode Pulse period measurement interval between measurement pulse rising edge to rising edge Pulse width measurement interval between measurement pulse falling edge to rising edge and between rising edge to falling edge Operation 1 Setting the count start flag to 1 causes the counter to start counting the count source 2 If a measurement pulse changes from H to L the value of the counter goes to 000016 and measurement is started In this instance an indeterminate value is tr
438. t source external clock e Transmit interrupt cause select bit 0 n value set to BRGi Figure 1 80 Typical transmit timings in UART mode 88 N O S Mitsubishi microcomputers S M30201 Group aa SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Clock asynchronous serial I O UART mode e Example of receive timing when transfer data is 8 bits long parity disabled one stop bit BRGi count source q Receive enable bit 9 RxDi Receive data taken in Transfer clock Reception triggered when transfer clock Transferred from UARTI receive register to Receive 1 is generated by falling edge of start bit UARTi receive buffer register complete flag Receive interrupt 4 request bit o eee a Cleared to 0 when interrupt request is accepted or cleared by software The above timing applies to the following settings Parity is disabled One stop bit Figure 1 81 Typical receive timing in UART mode a Sleep mode This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi The sleep mode is selected when the sleep select bit bit 7 at addresses 03A016 03A816 is set to 1 during reception In this mode the unit performs receive operation when the MSB of the received data 1 and does not perform receive operation when the MSB 0 89 A Q lt Mitsubishi microcomputers SS M30201 Group SINGLE CHIP
439. t starts flag b7 b0 Count start flag Address 038016 UTA Tir TABSR Timer AO count start flag Start count Figure 2 2 25 Set up procedure of pulse width modulation mode 16 bit PWM mode selected 187 N Q Sf Mitsubishi microcomputers Sa amp M30201 Group Tr A SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Imer 2 2 12 Operation of Timer A pulse width modulation mode 8 bit PWM mode selected In pulse width modulation mode choose functions from those listed in Table 2 2 12 Operations of the circled items are described below Figure 2 2 26 shows the operation timing and Figure 2 2 27 shows the set up procedure Table 2 2 12 Choosed functions Count source Internal count source f1 fs f32 fc32 PWM mode 16 bit PWM 8 bit PWM Count start condition External trigger input falling edge of input signal to the TAOIN pin External trigger input rising edge of input signal to the TAOIN pin Timer overflow TB1 TX0 TX2 overflow Operation 1 If the TAOIN pin input level changes from H to L with the count start flag set to 1 the counter performs a down count on the count source Also the TAOOUT pin outputs an H level 2 The TAQOUT pin output level changes from H to L when a set time period elapses At this time the timer AO interrupt request bit goes to 1 3 The counter reloads the content of the reload register every time PWM pulses are output f
440. t was before the acceptance of interrupt request So far as software numbers 32 through 63 are concerned the stack pointer does not make a shift 30 O amp Mitsubishi microcomputers Sas M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Hardware Interrupts Hardware interrupts are classified into two types special interrupts and peripheral I O interrupts 1 Special interrupts Special interrupts are non maskable interrupts Reset Reset occurs if an L is input to the RESET pin DBC interrupt This interrupt is exclusively for the debugger do not use it in other circumstances e Watchdog timer interrupt Generated by the watchdog timer e Single step interrupt This interrupt is exclusively for the debugger do not use it in other circumstances With the debug flag D flag set to 1 a single step interrupt occurs after one instruction is executed Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to 1 If an address other than the first address of the instruction in the address match interrupt register is set no address match interrupt occurs 2 Peripheral I O interrupts A peripheral I O interrupt is generated by one of built in peripheral functions The interrupt vector table is the same as the one for software interrupt
441. tconv Conversion time 1 Obit tconv Conversion time 8bit tsamP Sampling time VREF Reference voltage VIA Analog input voltage 115 N Q aS Mitsubishi microcomputers Sr M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 5V Vcc 5V Timing requirements referenced to Vcc 5V Vss 0V at Ta 25 C unless otherwise specified Table 1 41 External clock input Standard Parameter Min Max External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Table 1 42 Timer A input counter input in event counter mode Standard Parameter Min Max te TA TAOIN input cycle time tw TAH TAOIN input HIGH pulse width tw TAL TAOIN input LOW pulse width Table 1 43 Timer A input gating input in timer mode Standard Parameter Min Max te TA TAOIN input cycle time tw TAH TAOIN input HIGH pulse width tw TAL TAOIN input LOW pulse width Table 1 44 Timer A input external trigger input in one shot timer mode Standard Parameter in Max TAOIN input cycle time TAOIN input HIGH pulse width TAOIN input LOW pulse width Table 1 45 Timer A input external trigger input in pulse width modulation mode Standard Symbol Parameter Min
442. tection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control Figure 1 21 shows the protect register The values in the processor mode register 0 address 000416 processor mode register 1 address 000516 system clock control reg ister O address 000616 system clock control register 1 address 000716 and port P4 direction register address 03EA16 can only be changed when the respective bit in the protect register is set to 1 There fore important outputs can be allocated to port P4 If after 1 write enabled has been written to the port P4 direction register write enable bit bit 2 at address 000A16 a value is written to any address the bit automatically reverts to 0 write inhibited However the system clock control registers 0 and 1 write enable bit bit O at 000A16 and processor mode register 0 and 1 write enable bit bit 1 at 000A16 do not automatically return to 0 after a value has been written to an address The program must therefore be written to return these bits to O Protect register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset PRCR 000A16 XXXXX0002 Bima Do Enables writing to system clock EEE pos PRCO control registers 0 and 1 addresses i ce 000616 and 000716 SEEE 7 Enables writing to processor mode lt Write inhibj PRC1 registers 0 and 1 addresses 000416 H i A T and 000516 Enables w
443. ted Data present in transmit register during transmission No data present in transmit register transmission completed TXEPT Transmit register empty Set this bit to 1 TXDi pin is CMOS output TXDi pin is N channel open drain output TXDi pin is CMOS output TXDi pin is N channel open drain output Data output select bit Transmit data is output at falling edge of transfer clock and receive data is input at rising edge Transmit data is output at rising edge of transfer clock and receive data is input at falling edge LSB first MSB first Note UART1 cannot be used in clock synchronous serial I O CKPOL CLK polarity select bit Must always be 0 UFORM Transfer format select bit Must always be 0 Figure 2 6 4 UARTi related registers 2 262 O aS Mitsubishi microcomputers SX M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UARTIi transmit receive control register 1 b7 b6 b5 b4 b3 b2 bi b0 Symbol UiC1 i 0 1 Bit symbol Bit name Transmit buffer empty flag Receive enable bit Receive complete flag Address 03A516 03AD16 When reset 0216 Function During clock synchronous serial I O mode 0 Data present in transmit buffer register 1 No data present in transmit buffer register 0 No data present in receive buffer register 1 Data present in receive buffer register Function y During UART mode
444. ter b7 b0 Trigger select register Address 038316 TRGSR Timer X0 event trigger select bit b3 b2 TB1 overflow is selected TAO overflow is selected TX1 overflow is selected X1 event trigger select bit TB1 overflow is selected TXO overflow is selected TX2 overflow is selected X1 event trigger select bit TB1 overflow is selected TX1 overflow is selected TAO overflow is selected N Setting PWM pulse s H level width b15 b8 b7 bO b7 bo Timer XO register Address 038916 038816 TXO Doo T ER Timer X1 register Address 038B16 038A16 TX1 Timer X2 register Address 038D16 038C16 TX2 Can be set to 000016 to FFFE16 Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XcIN by 32 b7 b0 XKKKKKEX Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect 1 Prescaler is reset When read the value is O Setting count starts flag Count start flag Address 038016 TABSR Timer XO count start flag Timer X1 count start flag Timer X2 count start flag Start count Figure 2 4 21 Set up procedure of pulse width modulation mode 16 bit PWM mode selected 229 amp Mitsubishi microcomputers RQ s s M30201
445. ternal source or timer overflow One shot timer mode 000016 to FFFF16 Counts a one shot width e Pulse period pulse width measurement mode Measures a pulse period or width e Pulse width modulation mode 16 bit PWM 000016 to FFFE16 Functions as a 16 bit pulse width modulator Pulse width modulation mode 8 bit PWM pd o anu Timer low order address functions as an 8 bit t ddresses prescaler and high order address functions as an 8 bit 0016 to FF16 Low pulse width modulator order addresses Note Read and write data in 16 bit units Count start flag b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset TABSR 038016 000X00002 TXOS Timer X0 count start flag 1 Starts counting TX1S Timer X1 count start flag Nothing is assigned When write set 0 When read their contents are indeterminate TBOS Timer BO count start flag 0 Stops counting TBiS Timer B1 count start flag Starts counting CDCS Clock devided count start flag Figure 2 4 2 Timer X related registers 1 210 N O amp Mitsubishi microcomputers SS M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X One shot start flag Symbol Address When reset b7 b6 b5 b4 b3 b2 bi bO ONSF 038216 XXXX00002 RW When read the value is 0 Nothing is assigned When write set 0 When read its content is indeterminate proccess Trigger select register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset TRGSR 038316
446. the interrupt number and interrupt request level in the interrupt sequence The interrupt request bit of the certain interrupt written in address 0000016 will then be set to 0 Reading address 0000016 by software sets enabled highest priority interrupt source request bit to 0 Though the interrupt is generated the interrupt routine may not be executed Do not read address 0000016 by software 2 Setting the stack pointer e The value of the stack pointer immediately after reset is initialized to 000016 Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway Be sure to set a value in the stack pointer before accepting an interrupt Concerning the first instruction immediately after reset generating any interrupts is prohibited 3 External interrupt e Either an L level or an H level of at least 250 ns width is necessary for the signal input to pins INTO and INT1 regardless of the CPU operation clock e When changing a polarity of pins INTO and INT1 the interrupt request bit may become 1 Clear the interrupt request bit after changing the polarity Figure 1 33 shows the switching condition of INT inter rupt request Clear the interrupt enable flag to 0 Disable interrupt Set the interrupt priority level to level 0 Disable INTi interrupt Set the polarity select bit Clear the interrupt request bit to 0 Set the interrupt priority level to level 1 to 7 Enabl
447. the repeated sweep mode 0 in that weights can be assigned to specifing pins control the number of conversion times 2 Operation clock The operation clock in 5 V operation can be selected from the following fAD divide by 2 fAD and divide by 4 fAD In 3 V operation the selection is divide by 2 fAD or divide by 4 The fAD frequency is equal to that of the CPU s main clock 3 Conversion time Number of conversion for A D convertor varies depending on resolution as given Table 2 7 1 shows relation between the A D converter operation clock and conversion time Sample amp Hold function selected 33 cycles for 10 bit resolution or 28 cycles for 8 bit resolution No Sample amp Hold function 59 cycles for 10 bit resolution or 49 cycles for 8 bit resolution Table 2 7 1 Conversion time every operation clock Frequency selection bit 1 1 Frequency selection bit 0 Invalid A D converter s operation clock fAD fAD Min conversion 8 bit mode cycles Note 1 10 bit mode 33 X EAD Min conversion 8 bit mode i a 10 bit mode Note 1 The number of conversion cycles per one analog input pin Note 2 The conversion time per one analog input pin when fAD f XIN 10 MHz ee 272 x N O aS Mitsubishi microcomputers ve M30201 Group gt SINGLE CHIP 16 BIT CMOS MICROCOMPUTER A D Converter 4 Functions selection a Sample amp Hold function Sample amp Hold function samples input voltage when A D c
448. timer AO interrupt request bit goes to 1 rel i n reload register content Stop count 1 Start count l 3 Start count 4 Stop count i l l Start count Stop Reload Reload soy Counter content hex Set to 1 by software Cleared to 0 by software Count start flag 1 l 7 0 Trigger during count S TAOIN pin H X k input signal up y One shot pulse output H s from TAQOUT pin q 1 fi_ X n 1 Timer AO interrupt 1 request bit 9 Cleared to 0 when interrupt request is accepted or cleared by software Figure 2 2 22 Operation timing of one shot mode external trigger selected 184 S FS s x Timer A S Mitsubishi microcomputers M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Selecting one shot timer mode and functions Timer AO mode register Address 039616 Selection of one shot timer mode Pulse output function select bit 1 Pulse is output Note 1 External trigger select bit 1 Rising edge of TAOIN pin s input signal Trigger select bit 1 Selected by event trigger select register 0 Must always be 0 in one shot timer mode Count source select bit Me Count source period f XcIN 32 768kHz 100ns 800ns 3 2us 976 56us Count source f X n 10MHz b7 b6 00 fi 01 fs 10 fs2 11 fce32 fcs2 Note 1 Set t
449. timer operated using fC32 120 O S Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 3V Vcc 3V Table 1 58 A D conversion characteristics 7 l Ni dii Standard arameter easuring con ition Min Typ Max Resolution Vrer Vcc Absolute Sample amp hold function not available VREF Voc 3V accuracy 8bit AD fAD 2 Riapper Ladder resistance VREF Vcc tconv Conversion time 8bit VREF Reference voltage Via Analog input voltage 121 x S Q aS Mitsubishi microcomputers ve M30201 Group S SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Electrical characteristics Vcc 3V Vcc 3V Timing requirements referenced to Vcc 3V Vss 0V at Ta 25 C unless otherwise specified Table 1 59 External clock input Standard Parameter Min Max External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Table 1 60 Timer A input counter input in event counter mode Standard Parameter Min Max te TA TAOIN input cycle time tw TAH TAOIN input HIGH pulse width tw TAL TAOIN input LOW pulse width Table 1 61 Timer A input gating input in timer mode Standard Parameter Min Max te TA TAOIN input cycle time tw TAH TAOIN input HIG
450. transfer rate register can be selected from f1 f8 32 and the input from the CLK pin Clocks f1 f8 f32 are derived by dividing the CPU s main clock by 1 8 and 32 respectively Table 2 6 2 Example of baud rate setting Baud rate BRG s System clock 10MHz System clock 7 3728MHz bps POH Sone BRG s set value n Actual time bps BRG s set value n Actual time bps 257 Q RY Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER UART 3 An error detection In clock asynchronous serial I O mode detect errors are shown in Table 2 6 3 Table 2 6 3 Error detection Type of error Description When the flag turns on How to clear the flag Overrun error e This error occurs when the next data lines up before the content of the UARTI receive e Set the serial I O mode select buffer register is read bits to 0002 The next data is written to the e Set the receive enable bit to UARTi receive buffer register 0 e The UARTI receive interrupt request bit does not go to 1 The error is detected Framing error e This error occurs when the when data is e Set the serial I O mode select stop bit falls short of the set transferred from the bits to 0002 number of stop bits UARTI receive register Set the receive enable bit to Pi Q Parity error e With parity enabled this error a oo e Read the lower order byte
451. trol register 0 Note 1 b6 b4 b3 b2 bO Symbol Address When reset ADCONO 03D616 00000XXxX2 0 ANo is selected AN1 is selected AN2 is selected AN3 is selected AN4 is selected AN5 is selected AN6 is selected AN7 is selected Analog input pin select bit 7A or O 0 O0c A D operation mode One sh select bit 0 One shot mode Repeat mode Single sweep mode Repeat sweep mode 0 Repeat sweep mode 1 0 0g 242424200008 0 A D conversion disabled 1 A D conversion started Note 1 If the A D control register is rewritten during A D conversion the conversion result is indeterminate Note 2 AN50 to AN54 can be used in the same way as for ANo to AN4 A D control register 1 Note 1 b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset err Gis aren 03D716 0016 A D sweep pin select bit When single sweep and repeat sweep mode 0 are selected b1 b0 0 0 ANo AN1 2 pins 0 1 ANo to AN3 4 pins 10 ANo to AN5 6 pins 1 1 ANo to AN7 8 pins r When repeat sweep mode 1 is selected b1 b0 00 ANo 1 pin 0 1 ANo AN1 2 pins 1 0 ANo to AN2 3 pins 111 ANo to AN3 4 pins NOte 2 3 A D operation mode 0 Any mode other than repeat sweep select bit 1 mode 1 1 Repeat sweep mode 1 8 10 bit mode select bit 0 8 bit mode 1 10 bit mode Frequency select bit 1 0 faD 2 or fAD 4 is selected 1 fAD is selected Vref connect bit 0 Vref not conne
452. ue Pa Reload register counter transfer timing Timing at which counter reaches 000016 Count start flag Timer Xi interrupt request bit A A Cleared to 0 when interrupt request is accepted or cleared by software Timer Xi overflow flag a g _ Note 1 Counter is initialized at completion of measurement Note 2 Timer has overflowed Figure 1 65 Operation timing when measuring a pulse width 73 x Ss Q s Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X 5 Pulse width modulation PWM mode In this mode the timer outputs pulses of a given width in succession See Table 1 25 In this mode the counter functions as either a 16 bit pulse width modulator or an 8 bit pulse width modulator Figure 1 66 shows the timer Xi mode register in pulse width modulation mode Figure 1 67 shows the example of how a 16 bit pulse width modulator operates Figure 1 68 shows the example of how an 8 bit pulse width modulator operates Table 1 25 Timer specifications in pulse width modulation mode Item Specification Count source f1 f8 f32 fC32 Count operation e Down counts operating as an 8 bit or a 16 bit pulse width modulator The timer reloads a new count at a rising edge of PWM pulse and continues counting The timer is not affected by a trigger that occurs when counting 16 bit PWM H level width n fi n Set value Cycle time 218 1 fi fixed 8 bit PWM H
453. unction selected 170 O V Mitsubishi microcomputers we M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer A We Selecting timer mode and functions Selection of timer mode Pulse output function select bit 0 Pulse is not output TAOOUT pin is a normal port pin Gate function select bit b4 b3 1 1 Timer counts only when TAOIN pin is held H Note 0 Must always be 0 in timer mode pet source select bit Count Count source period 00 f1 SOUICE f XIN 10MHz f XcIN 32 768kHz 01 fs 100ns 10 f32 800ns 11 fc32 3 2us 976 56us Note Set the corresponding port direction register to O input mode Setting divide ratio b8 b0 b7 Timer AO register Address 038716 038616 TAO O Can be set to 000016 to FFFF16 J Ts a Setting clock prescaler reset flag This function is effective when fc32 is selected as the count source Reset the prescaler for generating fc32 by dividing the XcIN by 32 b7 bO Clock prescaler reset flag Address 038116 CPSRF Clock prescaler reset flag 0 No effect Ke 1 Prescaler is reset When read the value is 0 Setting count start flag b7 bO Count start flag Address 038016 EAA TABSR Timer AO count start flag Start count Figure 2 2 9 Set up procedure of timer mode gate function selected 171 O Q sf Mitsubishi microcomputers
454. unt start condition An external trigger is input e The timer overflows e The one shot start flag is set 1 Count stop condition A new count is reloaded after the count has reached 000016 e The count start flag is reset 0 Interrupt request generation timing The count reaches 000016 TXiINOUT pin function Programmable I O port trigger input or pulse output Read from timer When timer Xi register is read it indicates an indeterminate value Write to timer When counting stopped When a value is written to timer Xi register it is written to both reload register and counter When counting in progress When a value is written to timer Xi register it is written to only reload register Transferred to counter at next reload time Timer Xi mode register b7 b6 b5 b4 b3 b2 bi bO bol Address When reset fol hifo TANU 0to 2 039716 to 039916 0016 i A TMODO Operation mode b1 bo al select bit 1 0 One shot timer mode or pulse period TMOD1 pulse width measurement mode MRO Pulse output function 0 Pulse is not output i select bit TXiINOOUT pin is a normal port pin 1 Pulse is output Note 1 TXiINOOUT pin is a pulse output pin MR1 External trigger select 0 Falling edge of TXiINOOUT pin s input signal Note 3 joi bit Note 2 1 Rising edge of TXiINOOUT pin s input signal Note 3 MR2 Trigger select bit 0 One shot start flag is valid 1 Selected by event trigger s
455. unting the output level of the TX1INOUT pin gose to H 5 As soon as the counter of timer X1 becomes 000016 the output level of the TX1INOUT pin gose to L the counter reloads the content of the reload register and stops counting At this time timer X1 interrupt request bit gose to 1 334 S xe amp Mitsubishi microcomputers SS M30201 Group ka ee SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Timer X Applications reload register content 1 Count enabled 2 Timer XO start count 3 Timer X0 stop count Timer XO counter content hex i n reload register content 4 Timer X1 start count i ye 5 Timer X1 stop counti S 2 E Q 0 x lt a D E content hex Set to 1 by software Timer X0 count start flag Set to 1 by software Timer X1 count start flag Input signal from TXOINOUT pin PWM pulse output from TX1INOUT pin Timer XO interrupt request bit Cleared to 0 when interrupt request is accepted or cleared by software Timer X1 interrupt request bit E Er Cleared to 0 when interrupt request is accepted or cleared by software Figure 3 3 1 Operation timing of delayed one shot output TXOINOUT pin input fi fs O Used for one shot timer mode i Timer XO interrupt request bit Timer X1 interrupt request bit Used for one shot timer mode Figure 3 3 2 Connection diagram of
456. ur 3 An address match interrupt occurs immediately before the instruction in the address indicated by the address match interrupt register as a program is executed Setting address match interrupt register N Address match interrupt register 0 Address 001216 to 001016 RMADO Address match interrupt register 1 Address 001616 to 001416 MAD1 b23 b20 b19 b16 b15 b8 b7 b4 b3 b0 b7 b0 b7 E Can be set to 0000016 to FFFFF16 Setting address match interrupt enable register b7 b0 Address match interrupt enable register Address 000916 AIER Address match interrupt 0 enable bit 1 Interrupt enabled Address match interrupt 1 enable bit 1 Interrupt enabled Figure 2 9 4 Set up procedure of address match interrupt 304 X Ss Q Ss Mitsubishi microcomputers Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Address Match Interrupt C Address match interrupt routine D 1 Storing registers 2 Determining the interrupt address ee ae sssi No Pee Address match 0 oa Yes a No Address match 0 program Address MAGN ee T Yes Address match 1 program lt 3 Rewriting the stack Restoring registers y REIT Handling an error Explanation 1 Storing the contents of the registers holding the main program status to be ke
457. urce 2 If an effective edge of a pulse to be measured is input the value of the counter goes to 000016 and measurement is started In this instance an indeterminate value is transferred to the reload register The timer Bi interrupt request does not generate 3 If an effective edge of a pulse to be measured is input again the value of the counter is transferred to the reload register and the timer Bi interrupt request bit goes to 1 Then the value of the counter becomes 000016 and measurement is started again Note e The timer Bi interrupt request bit goes to 1 when an effective edge of a pulse to be measured is input or timer Bi is overflows The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine e The value of the counter at the beginning of a count is indeterminate Thus there can be in stances in which the timer Bi overflow flag goes to 1 immediately after a count is performed e The timer Bi overflow flag goes to 0 if timer Bi mode register is written to when the count start flag is 1 This flag cannot be set to 1 by software 1 Start count 3 Start measurement again 2 Start measurement Count source COU H Measurement pulse si T pai Transfer Transfer measured value i indeterminate i VA tt i Reload register lt counter value transfer timing Timing at which counter reaches 000016
458. ures DD 1 and DD 2 show the pin connections for the standard serial I O mode Serial data I O uses three UARTO pins CLKo RxDo and TxDo and port P53 BUSY The CLKo pin is the transfer clock input pin and it transfers the external transfer clock The TxDo pin outputs the CMOS signal The P53 BUSY pin outputs an L level when reception setup ends and an H level when the reception operation starts Transmission and reception data is transferred serially in 8 byte blocks In the standard serial I O mode only the user ROM area shown in Figure CC 1 can be rewritten the boot ROM area cannot The standard serial I O mode has a 7 byte ID code When the flash memory is not blank and the ID code does not match the content of the flash memory the command sent from the programmer is not accepted Function Overview Standard Serial I O Mode In the standard serial I O mode software commands addresses and data are input and output between the flash memory and an external device serial programmer etc using a clock synchronized serial I O UARTO and P53 In reception the software commands addresses and program data are synchronized with the rise of the transfer clock input to the CLKo pin and input into the flash memory via the RxDo pin In transmission the read data and status are synchronized with the fall of the transfer clock and output to the outside from the TxDo pin The TxD1 pin is CMOS output Transmission is in 8 bit blocks and LS
459. urred If the data read is erroneous initialize the error flag and the UARTO receive buffer register then receive the data again To initialize the UARTO receive buffer register 1 Set the receive enable bit to O disable reception 2 Set the serial I O mode select bit to 0002 invalid serial I O 3 Set the serial I O mode select bit 4 Set the receive enable bit to 1 again enable reception To transmit data again due to an error on the reception side set the UARTO transmit buffer register again then transmit the data again To set the UARTO transmit buffer register again 1 Set the serial I O mode select bits to 0002 invalidate serial I O 2 Set the serial I O mode select bits again 3 Set the transmit enable bit to 1 enable transmission then set transmission data in the UARTO transmit buffer register 5 Function selection For clock synchronous serial I O the following functions can be selected a Function for choosing polarity This function switches the polarity of the transfer clock The following operations are available e Data is input at the falling edge of the transfer clock and is output at the rising edge e Data is input at the rising edge of the transfer clock and is output at the falling edge 236 amp xe amp Mitsubishi microcomputers SS Ros 3 M30201 Group gt Clock Synchronous Serial I O SINGLE CHIP 16 BIT CMOS MICROCOMPUTER b Function for choosing whi
460. usively for the debugger do not use it in other circumstances e Watchdog timer interrupt Generated by the watchdog timer e Single step interrupt This interrupt is exclusively for the debugger do not use it in other circumstances With the debug flag D flag set to 1 a single step interrupt occurs after one instruction is executed Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to 1 If an address other than the first address of the instruction in the address match interrupt register is set no address match interrupt occurs For address match interrupt see 2 9 Address match Interrupt 2 Peripheral I O interrupts A peripheral I O interrupt is generated by one of built in peripheral functions Built in peripheral func tions are dependent on classes of products so the interrupt factors too are dependent on classes of products The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INI instruction uses Peripheral I O interrupts are maskable interrupts e Key input interrupt A key input interrupt occurs if an L is input to the KI pin A D conversion interrupt This is an interrupt that the A D converter generates e UARTO and UART1 transmission interrupt These are interrupts that the serial I O transmission
461. ut the interrupt is disabled the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener ated This will depend on the instruction If this creates problems use the below instructions to change the register Instructions AND OR BCLR BSET 361 4 Mitsubishi microcomputers g S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 3 Interrupt Sequence An interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here If an interrupt occurs during execution of an instruction the processor determines its priority when the execution of the instruction is completed and transfers control to the interrupt sequence from the next cycle If an interrupt occurs during execution of either the SMOVB SMOVF SSTR or RMPA instruction the processor temporarily suspends the instruction being executed and transfers control to the interrupt sequence In the interrupt sequence the processor carries out the following in sequence given 1 CPU gets the interrupt information the interrupt number and interrupt request level by reading ad dress 0000016 2 Saves the content of the flag register FLG as it was immediately before the start of interrupt sequence in the temporary register Note within the CPU 3 Sets the interrupt enable flag I flag the debug flag D flag a
462. ut to one of pins Klo through KI7 to clear stop mode A key input interrupt occurs to execute the key input interrupt handling routine 3 Sequentially set P30 through P33 to L to determine which key was pressed 4 When the process to determine the key pressed is completed change the output from P30 through P33 to L again and enter stop mode 1 Shift to stop mode 2 Cancel a stop mode 3 Key scan Key matrix scan 4 Shift to stop mode x P30 output P31 output P32 output P33 output POo to P07 input Key input Key OFF Key ON Key OFF Key ON Key input l L interrupt processing CPU clock _ __ D Pe Stop mode Stop mode Figure 3 6 1 Operation timing of controlling power using stop mode 342 amp Ss Mitsubishi microcomputers Sas M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications P33 I O port P00 Klo P01 Kh P02 KI2 P03 KI3 P04 Kla POs KI5 P06 Kle tmo Hmo FID pd Hmo FWD Hmo Hmo P07 KI7 Figure 3 6 2 Example of circuit of controling power using stop mode 343 S Mitsubishi microcomputers OS ON M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Initial condition b7 bo Pull up control register 0 b7 vo Port PO direction register Address 03FC16 Address 03E216 1 Buro o ofofofofo ofo Bso P00 to POs pulled high Key scan input port
463. uters Q Ss M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupts Interrupt Sequence An interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here If an interrupt occurs during execution of an instruction the processor determines its priority when the execution of the instruction is completed and transfers control to the interrupt sequence from the next cycle If an interrupt occurs during execution of either the SMOVB SMOVF SSTR or RMPA instruction the processor temporarily suspends the instruction being executed and transfers control to the interrupt sequence In the interrupt sequence the processor carries out the following in sequence given 1 CPU gets the interrupt information the interrupt number and interrupt request level by reading address 0000016 After this the corresponding interrupt request bit becomes 0 2 Saves the content of the flag register FLG as it was immediately before the start of interrupt sequence in the temporary register Note within the CPU 3 Sets the interrupt enable flag I flag the debug flag D flag and the stack pointer select flag U flag to O the U flag however does not change if the INT instruction in software interrupt numbers 32 through 63 is executed 4 Saves the content of the temporary register Note within the CPU in the stack area 5 S
464. utine to determine the interrupted pin 4 Registers related to the key input interrupt Figure 2 10 1 shows the memory map of key input interrupt related registers and Figure 2 10 2 shows key input interrupt related registers 004D16 Key input interrupt control register KUPIC 03E216 Port PO direction register PDO 03FC16 Pull up control register 0 PURO Figure 2 10 1 Memory map of key input interrupt related registers 306 Ni O gf Mitsubishi microcomputers Sy M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Key Input Interrupt Interrupt control register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset KUPIC 004D16 XXXXX0002 Bit symbol Interrupt priority level select bit Level 0 interrupt disabled Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Interrupt request bit 0 Interrupt not requested Oo O 1 Interrupt requested Note Nothing is assigned When write set 0 When read their contents are indeterminate Note This bit can only be accessed for reset 0 but cannot be accessed for set 1 Port PO direction register 7 4 2 bi b0 b7 b6 b5 b4 b3 b2 bi b Symbol Address When reset PDO 03E216 0016 R Port P01 direction register or Eei an input port 1 Output mode Functions as an output port Pull up control register 0 b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset PURO 03FC16 0016 Bit symbol AW PUDO P90 10 R03 BaD The corr
465. utomatically executed Be sure to set in software Figure 4 6 1 Multiple interrupts 369 xX O s Mitsubishi microcomputers Sty M30201 Group x SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Interrupt 4 7 Precautions for Interrupts 1 Reading address 0000016 e When maskable interrupt is occurred CPU read the interrupt information the interrupt number and interrupt request level in the interrupt sequence The interrupt request bit of the certain interrupt written in address 0000016 will then be set to 0 Reading address 0000016 by software sets enabled highest priority interrupt source request bit to O Though the interrupt is generated the interrupt routine may not be executed Do not read address 0000016 by software 2 Setting the stack pointer e The value of the stack pointer immediately after reset is initialized to 000016 Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway Be sure to set a value in the stack pointer before accepting an interrupt Concerning the first instruction immediately after reset generating any interrupts is prohibited 3 External interrupt e Either an L level or an H level of at least 250 ns width is necessary for the signal input to pins INTo and INT1 regardless of the CPU operation clock e When the polarity of the INTo and INT1 pins is changed the interrupt request bit is sometimes set to 1 After changing the p
466. value Timer X event counter mode 1 Reading the timer Xi register while a count is in progress allows reading with arbitrary timing the value of the counter Reading the timer Xi register with the reload timing gets FFFF16 by underflow or 000016 by overflow Reading the timer Xi register after setting a value in the timer Xi register with a count halted but before the counter starts counting gets a proper value 2 When stop counting in free run type set timer again Timer X one shot timer mode 1 Setting the count start flag to O while a count is in progress causes as follows e The counter stops counting and a content of reload register is reloaded e The TXiINOUT pin outputs L level e The interrupt request generated and the timer Xi interrupt request bit goes to 1 2 The timer Xi interrupt request bit goes to 1 if the timer s operation mode is set using any of the following procedures e Selecting one shot timer mode after reset e Changing operation mode from timer mode to one shot timer mode e Changing operation mode from event counter mode to one shot timer mode Therefore to use timer Xi interrupt interrupt request bit set timer Xi interrupt request bit to O after the above listed changes have been made 109 xX Ss Q RY Mitsubishi microcomputers S M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Usage precaution Timer X pulse width modulation mode 1 The t
467. value 1 to 7 Initialization of port P4 direction register b7 b0 Protect register Add 000A XXX tT T Bi register Address 16 Enables writing to port P4 direction register 1 Write enabled Port P4 direction register Address 03EA16 PD4 Port P43 direction register 0 Input mode Setting interrupt enable flag I flag Figure 3 5 1 Set up procedure of solution for a shortage of external interrupt pins 341 N g Mitsubishi microcomputers x SaS M30201 Group SINGLE CHIP 16 BIT CMOS MICROCOMPUTER Controlling Power Applications 3 6 Controlling Power Using Stop Mode Overview The following are steps for controlling power using stop mode Figure 3 6 1 shows the operation timing Figure 3 6 2 shows an example of circuit and Figures 3 6 3 and 3 6 4 show the set up procedure Use the following peripheral functions e Key input interrupts Stop mode e Pull up function Specifications 1 Use P30 through P33 for the scan output pins of a key matrix Use the input pins Klo through KI7 of the key input interrupt function for the key input reading pins The pull up function is also used 2 If a key input interrupt request occurs clear the stop mode and read a key Operation 1 Enable a key input interrupt and set the pull up function to pins Klo through KI7 Change the output of P30 through P33 to L and enter stop mode 2 If a key is pressed L is inp
468. ve edge and the timer continues counting Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing When measurement pulse s effective edge is input Note 1 When an overflow occurs Simultaneously the timer Xi overflow flag changes to 1 The timer Xi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer Xi mode register TXiINOUT pin function Measurement pulse input Read from timer When timer Xi register is read it indicates the reload register s content measurement result Note 2 Write to timer Cannot be written to Note 1 An interrupt request is not generated when the first effective edge is input after the timer has started counting Note 2 The value read out from the timer Xi register is indeterminate until the second effective edge is input after the timer Timer Xi mode register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset I 1 ilo TXMRG 0t02 039716t0 0399168 002 Bit symbol Function RiW TMODO Operation mode ts O10 lect bit 1 0 One shot timer mode or pulse period Tuop1 See mon pulse width measurement mode MRO Measurement mode F select bit Pulse period measurement Interval between measurement pulse s falling edge to falling edge Pulse period measurement Interval between measurement pulse s rising edge to risi
469. view The following is an overview for timer A a 16 bit timer 1 Mode Timer A operates in one of the four modes a Timer mode In this mode the internal count source is counted Two functions can be selected the pulse output function that reverses output from a port every time an overflow occurs or the gate function which controls the count start stop according to the input signal from a port lt Timer mode operaio es teesceeenntedetvedateateetvnreecerbante devi EEEE e devia eee een eae eee P168 Timer mode gate function operation 00 2 eee eee eect ettte ee teeta eee eet a dees eee eaaeeee ee etaaeeeeeeeaaeeeeeeeea P170 e Timer mode pulse output FUNCTION operation 2 eee eee eeteeeeeeeeeee eee eee eaeee eee eaaeeeeeetaeeeeeeeaea P172 b Event counter mode This mode counts the pulses from the outside and the number of overflows in other timers The free run type in which nothing is reloaded from the reload register can be selected when an underflow occurs The pulse output function can also be selected Please refer to the timer mode explanation for details as the operation is identical Event counter Mode Operation ececceeecceeee eee eene eee teeta eee ee tana ee eee eaaeeeeeeeaaaeeeeeeeaeeeeeeeenaeeeeeeena P174 e Event counter mode free run type Operation ccccceecceeceeeeeeeeeneeeeeeeeceeeeeeeaaeeseeeeeessaeeeseaeees P176 Furthermore Timer A has a 2 phase pulse signal processing function which generat
470. ws it reloads the reload register contents before continuing counting Note Divide ratio 1 n 1 n Set value Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing The timer underflows TXiINOUT pin function Programmable I O port count source input or pulse output Read from timer Count value can be read out by reading timer Xi register Write to timer e When counting stopped When a value is written to timer Xi register it is written to both reload register and counter When counting in progress When a value is written to timer Xi register it is written to only reload register Transferred to counter at next reload time Select function e Free run count function Even when the timer underflows the reload register content is not reloaded to it e Pulse output function Each time the timer underflows the TXiINOUT pin s polarity is reversed Note This does not apply when the free run function is selected Timer Xi mode register b7 b6 b5 b4 b3 b2 bi b0 Symbol Address When reset fol Joli TXiIMR i 0 to 2 039716 to 039916 0016 7 TMODO Operation mode select bit 5 gt 0 0 i TMOD1 0 1 Event counter mode Note 1 O O Pulse output function 0 Pulse is not output select bit TXiINOUT pin is a normal port pin Pulse is output Note 2 TXiINOUT pin is a pulse output pin Invalid in event counter
471. ws the timer Bi mode register in timer mode Table 1 18 Timer specifications in timer mode Count source f1 f8 f32 fC32 Count operation Counts down e When the timer underflows it reloads the reload register contents before continuing counting Divide ratio 1 n 1 n Set value Count start condition Count start flag is set 1 Count stop condition Count start flag is reset 0 Interrupt request generation timing The timer underflows TBIIN pin function Programmable I O port Read from timer Count value is read out by reading timer Bi register Write to timer e When counting stopped When a value is written to timer Bi register it is written to both reload register and counter e When counting in progress When a value is written to timer Bi register it is written to only reload register Transferred to counter at next reload time Timer Bi mode register b7 b6 b5 b4 b3 b2 bi bO Symbol Address When reset X I lofo TBiMR i 0 1 039B16 to 039C16 00XX00002 Bit symbol Bitname Function R w Ca ee es TMOD i i b1 bo Eo Eoo Operation mode select bit 0 0 Timer mode 7 TMOD1 eae LOT oO EZET MRO Invalid in timer mode Peis ESEJ Nothing is assigned When write set 0 When read their contents are indeterminate Invalid in timer mode This bit can neither be set nor reset When read in timer mode its content is indeterminate Count source select bit b7 b6 00 fi 01 f8
472. ws the example of how a 16 bit pulse width modulator operates Figure 1 47 shows the example of how an 8 bit pulse width modulator operates Table 1 17 Timer specifications in pulse width modulation mode Specification Count source f1 f8 f32 fc32 Count operation e The timer counts down operating as an 8 bit or a 16 bit pulse width modulator e The timer reloads a new count at a rising edge of PWM pulse and continues counting e The timer is not affected by a trigger that occurs when counting 16 bit PWM e High level width n fi n Set value e Cycle time 218 1 fi fixed 8 bit PWM e High level width n X m 1 fi n values set to timer AO register s high order address e Cycle time 28 1 x m 1 fi m values set to timer AO register s low order address Count start condition e External trigger is input e The timer overflows e The count start flag is set 1 Count stop condition e The count start flag is reset 0 Interrupt 8 bits PWM Set value of H level width is except FF16 0016 PWM pulse goes L request e Set value of H level width is FF 16 0016 Timing that count value goes to 0116 generation 16 bits PWM Set value of H level width is except FFFF16 000016 PWM pulse goes L timing e Set value of H level width is FFFF16 000016 Timing that count value goes to 000116 TAOIN pin function Programmable I O port or trigger input TAOOUT pin function Pulse output Read from timer Wh

M30201 Group User`s manual (tentative)

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