Manual - W-IE-NE
Contents
1. Command Send Receive Function BO send CRC checksum of all bytes sent BO send CRC checksum of all bytes received Example sequence Number format in HEX ASCI L A 00000001 setaddress pointer ASE asoa set address pointer AIO a a 00000004 L 00000200 write to current address A 10 the 32Bit value 512 BFE __ write the byte value 255 to the addresse A 10 1 increase the address counter by 1 A I wosa writethe value 77210 A1 20000 setbloek transfer counter Autoiner to2 set address counter back to A 10 FFO4 block transfer of 2 bytes with auto increment Addressing All Logic Pool modules are addressed through a 24 bit address Address bits A31 A24 irrelevant A23 A16 0 255 type address of a Logic Pool module e g T L A15 A8 1 255 Module address of a Logic Pool module A7 A0 0 255 sub address for arbitrary parameters Every module must notify his presence to subaddress 0 with a byte 0 254 If no module is present at a specific address the value 255 or FF is returned Therefore an application e g October 10 8 00Sachnummer A User s Manual Nembox W Ie Ne R Plein amp Baus GmbH OPEN in LabVIEW can check that all modules are available and create a table of modules and addresses All other module parameters on further sub addresses are specific for each module The width of the data word is arbitrary between 1 and 4 bytes 3 32. 50 Ohm u Open 3 3V L a High Imp 960mV 50 Ohm 6 3 3V Internal Internal Clock 1 programmed with a frequency of 1000 Hz is connected to output 2 NIM open non terminated Digital I O inputs 1 and 2 both NIM and with 50 ohm termination are connected to the AND logic gate 1 The output of the logic gate is sent to digital I O 3 NIM open o TEE 0 o October 10 16 00Sachnummer A User s Manual Nembox W Ie Ne R Plein amp Baus GmbH Discriminator 1 programmed with a threshold of 100mV and an hysteresis of 30mV s connected to an internal inverter NIM Logic NIM TRUE corresponds to a negative voltage whose output is connected to digital I O port 2 NIM open non terminated 0 Discriminator 1 programmed with a threshold of 200mV and an hysteresis of 30mV is connected to Gate Generator 1 generating gates of 100 x 10ns lus whose output is connected to digital I O port 2 TTL 10ns is the internal clock period The typical minimum signal delay introduced by this simple circuit and by Im cables for measurement between Discriminator 1 and DIO 2 is about 50ns TTL High Imp In this sequence digital I O port 1 is programmed as NIM Input and connected to Counter and Trigger inputs of internal Counter 1 Then there is a waiting time of 5 seconds and afterwards the Counter 1 is read out The output is sent to the Counte
3. IEW 7 1 user lib LogicPool DACF Yvi Fast 14 Bit DAT module with max 100MHz clock rate Support SUYLO f 2 24 Ri 50 Ohm Values stored in an onboard memory hyp 0 10241 will be read out after trigger on input TRIG with selectable rate Divider and converted to analog voltages This allows to generate an arbitrary analog time Function 4FG Arbitrary Function Generator In mode Continous the sequence will be repeated automatically For periodic signals The output BUSY denotes the running of the module IF the module is not started the value of address 0 is generated Params Divider divider for any frequency f 100MHz2 Divider Continous chooses auto repeating mode Addr start address For loading DATA DATA data array 14 Bit The length of the array determines the length of the generated Function Function Connect connects all infoutputs and sets all parameters Set TRIG change input TRIG fet BUSY return output state BUSY Write Params Clear loads alle parameters and stops DALF number of module must be unique USB In and USE Out are related to the selected USE interface Mo connection uses global parameter set by OPEN Wil Figure 3 Labview documentation of DAC October 10 21 00Sachnummer A 4 1 4 2 5 1 User s Manual Nembox W Ie Ne R Plein amp Baus GmbH Advanced usage Installing other firmwares provided by Wiener Plein amp Baus It is possible to install other firm
4. big endian most significant bytes first Table 4 System poe a Bytes Sent 31 0 pk PF system Reset Table 5 Transfer A fabyres __ set address pointer A31 0 3 bytes set address pointer A23 0 een Aka S 1 byte L set address pointer A7 0 Sata read address pointer A31 0 increase address pointer A31 0 by 1 flower adress pointer A310 by 1 gt 2 bytes set counter N15 0 for block transfer A autoincr DR N set counter N15 0 for FIFO transfer A N 4 bytes write N longword s A Oil mA ongnerd A C m fut bytes write N Triple A ooo TR _ N 2 Bytes write N Word s A Oa on ame O B fntiBye JwriteN Bye A Bo fur Byte read N Bye C Block transfers In case the block transfer counter N commands N and F is set tol a corresponding byte transfer according to the selected datawidth is executed October 10 7 00Sachnummer A 3 2 User s Manual Nembox W Ie Ne R Plein amp Baus GmbH When N gt I N read or write cycles are executed and in case the counter was set with the N command the address pointer is incremented at each transfer In case the command F is used all transfers are executed at the same address typ FIFO The counter N after a block transfer is always set to 1 the address pointer A is resetted to the start address CRC Check not yet available Status 14 6 2007
5. if execution is successful IMPORTANT the USB address string needed to identify NIMbox NEMbox under LabVIEW can be found on a label on the backside of the module October 10 1 00Sachnummer A User s Manual Nembox W Ie Ne R Plein amp Baus GmbH 1 2 2 Linux 1 3 Please check www wiener d com for updates Programming the FPGA In order to quickly program the FPGA with predefined functionalities it is recommended to use LabVIEW Copy the NIMbox NEMbox Logic Pool VIs from the NIMbox Nembox package to the VI user library directory of LabVIEW IM For example copy trom D Labview 8 2 LogicPool to C Programs National Instruments LabVIEW 8 2 user lib Tests and Demos can be copied to an arbitrary directory By starting LabVIEWTM the new Logic Pool VIs will be available These VIs are described n this manual By connecting the Logic Pool VIs and by starting your application you will load a configuration to the FPGA This configuration will hold as long as you don t overwrite it by starting another application or as long as you don t reset or swich off NIMbox NEMbox The close VI will ask the user whether he wants to permanently save the configuration on the internal EEPROM so that it won t be lost in case of power off When starting VIs for the first time t may be necessary to ass st LabVIEW manually in searching the path to DL700 FX2 dll October 10 2 00Sachnummer A 2 1 2 2 2 3 User s M
6. user is used to pass values to Function For example it can be used to determine the level of the I O port This could be choosen between e TTL High Imp e TTL 50 Ohm e NIM Open e NIM 50 Ohm e A debounce value may cancel spurious or intermittent input signals The DIO integer value provided by the user identifies the physical port For example by choosing a TTL option for Params and the number 3 for DIO the resulting physical port will be the T3 i e the 4 where the 1 is the uppermost and the 16 the lowermost port The VI has an input OUT because it is used to feed the real output signal which will actually be generated by Nembox and an output IN because it is used to receive an input signal into the Nembox DIO Pn Bytes Read Bytes write o po fa MUXIN tt rx STATE IN ft Mode termination 0 NIMC Debounce debouncing disabled 1 255 debouncing with 1 255 ms enabled 3 5 2 Discriminator The DISCR output can be connected to other logical function or to an output port Function can be set to e Connect default e Get DISCR get the input status True or False e Write Threshold set the DAC for the threshold e Write Hysteresis set the DAC for hysteresis By using the Params cluster values for threshold and hysteresis can be set DISCRIMINATOR October 10 11 00Sachnummer A User s Manual Nembox W Ie Ne R Plein amp Bau
7. Definining FPGA connections Each module has typically one or more signal inputs and outputs Every output MUX_ has a specific connection value that can be read out by every module Moreover the logic state STATE_ at output can be inquired at any time Usually these values are stored on the read subaddresses 0 n Every input MUX is outfitted with a multiplexer switch that allows to set up the connection to any output Therefore any arbitrary interconnection between modules becomes possible The multiplexer are set to the user defined connection through a value in a register Typically the input multiplexer values are written from the user to the write subadresses 0 n Example the output of the module T10 should be directed to the input of moduls I3 The command E T OA00 b delivers the connection value 02 Hence the command E T 0300 B 02 connect the signal as intended 3 3 1 Reserved values By setting the MSB most significant bit of the multiplexer register it is possible to invert every input without using other resources z B E T 0300 B 82 e Value 0 characterizes an open not connected input or output e Value 127 produces a short trigger pulse after that it is set to 128 not yet implemented e Value 128 corresponds to a constant LOW level e Value 255 corresponds to a constant HIGH level 3 4 Example Port Mapping Front Panel In order to be able to assign a
8. El closed r Ca PARAMS pata op 1 ADC Sample 1 EJ m GiWidth ne 9 OK clear ee sum HPO T q F t 5 1 Ok Start Threshold 10000 Gin Coton 2 DIO Trigger za SK Pre amples 512 DIO Discr 2 Ok Read Data PostSamples 512 FIFO Memory Zl Ganz o 284 3328 B i emo FIFO Mode COUNT 1024 Waveform Graph ES LB Trigger Internal Run Amplitude Figure 2 Labview test ADC VI screen shot User s Manual Nembox W Ie Ne R Plein amp Baus GmbH 3 8 Usage of the DACs Unless custom specific ex works settings are requested the DAC outputs of SU710 consist of two channels on 4 plugs For each channel there are two plugs the signal is generated with positive and negative polar ty on both plugs Furthermore for each channel one s gnal either positiv or negative is amplified The DAC has a clock of 100MHz therefore it is able to generate a new user defined voltage every 10 ns The usage of the DACs is very simple in order to obtain an analog signal the user should provide a vector describing the signal to DATA within the Params argument and connect a start signal to TRIG Divider option for lower freguencies and continuous mode option are foreseen For every DAC channel there is a straight and an inverted output One of these two outputs in amplified in SU710 B Context Help DACFS USE In LISE Our TRIG Params Function DAC Fast LC Programme National Instruments Lab
9. FIFO and starts Recording Read Status return Running amp COUNT Read Data return array of FIFO ADCF number of module must be unique USE In and USE Out are related to the selected USB interface A amp i Figure 1 Labview documentation of ADC VI The ADC circuit samples and converts contineoulsy the analog input Inp with the System clock of 100 MHz The 14 Bit data Data are compared in a comperator gt with the Threshold value Based on the comparison result the output signals Discr as well as IntTrigger are set The dual ported memory RAM stores the data depending on the value of WriteAddr The memory is limited to 1024 samples size In order to realise slower sample rates the WriteAddr value can be set dependent on the Divider parameter also with a lower frequency of 100 MHz n TriggerCntrl recognizes an external if wired trigger ExtTrigger or is using the internally generated IntTrigger signal considers the defined size of PreSamples and PostSamples for the WriteAddr In the event of a trigger the control circuit first makes sure that the required number of PreSamples is written into the memory RAM and then sets a trigger signal Then the defined number of PostSamples is written into the RAM Once the writing into the memory is completed the signal Running with be cleared This is normally the moment to read out the sampled data fromn the memory For this purpose the current address WriteAddr will be read and the Re
10. Modul can be run in Emo Modes 1 Mode all false Rising edge of GATE triggers recording of raw ADC data with PreSamples in FIFO typ 1024 words 2 Mode any true each value determines which parameter will be recorded on every GATE into FIFO see Mode PARAMS Sample actual sampling rate F 100 MHz 5ample Threshold determines output DISCR FreSamples number of recordings before trigger PostSamples number of recordings after trigger Gain 2 reducing gain Factor use in Histo mode to scale down to 0 1024 FIFOIHISTO switch between readout mode Mode recording mode selecting none will record raw SOC data on trigger awidth duration of GATE fin sampling steps sum Sum af ADC values over duration of GATE 32 Bit raw aMin Minimum value within GATE GMinPos Position of GMin after start of GATE GMax Maximum value within GATE SMaxPos Position of GMax after start of GATE Min Minimum value before GATE Max Maximum value before GATE DATA Running true if recording module stops only on CLEAR Overflow true if trigger gate after memory Full Ready true when COUNT gt Pre amples PostSamples COUNT number of data in FIFO FIFO array of raw data or gate parameters after read Function Connect connects in amp outputs and loads all parameters Set TRIG change input TRIG Get DISCR return output DISER Write Params amp Clear loads parameters clears
11. W Ie Ne R NIMbox NEMbox wiener Wiener er NIMbox NIMbox 7 ve P n Plein amp M amp status POWER wener NEMbox NIM TTL 1 0 DAC2 DAC24 DACI DAC T8 7 ADC a User s Manual QOSachnummer AO General Remarks The only purpose of this manual is a description of the product It must not be interpreted as a declaration of conformity for this product including the product and software W Ie Ne R revises this product and manual without notice Differences between the description in manual and the product are possible W Ie Ne R excludes completely any liability for loss of profits loss of business loss of use or data interrupt of business or for indirect special incidental or consequential damages of any kind even if W Ie Ne R has been advises of the possibility of such damages arising from any defect or error in this manual or product Any use of the product which may influence health of human beings requires the express written permission of W Ie Ne R Products mentioned in this manual are mentioned for identification purposes only Product names appearing in this manual may or may not be registered trademarks or copyrights of their respective companies No part of this product including the product and the software may be reproduced transmitted transcribed stored in a retrieval system or translated into any language in any form by any means without the expres
12. a a a a i i a i a a a S 15 347 CARS 0 LEA IDC Ss ia aa D a V a a a a aaa a a a a 18 34 ADC VIO e SIT a a 20 3 8 SO Lie DAC S aimas a as ee a a een ern 21 M EPP PPP PPP 22 4 1 Installing other firmwares provided by Wiener Plein amp Baus 2222222200sseeeesenensnnnnnnnnnnneennnnn 22 4 2 Installing self made firmwares ire 22 o RO A e P E A TS SL R Stoke TC EEPROM sias aa ai a ia een i i a a ee er 22 October 10 1 00Sachnummer A October 10 111 00Sachnummer A 1 1 1 2 User s Manual Nembox W Ie Ne R Plein amp Baus GmbH Quick startup Power up On power up the power LEDs are active and if the firmware has been installed the BUSY LED will blink shortly NIMbox NEMbox is shipped with preinstalled firmware which is consistent with the hardware version and with the position of the installed submodules on the main FPGA board Immediately after the first power up the USB communication is possible but no configuration setup or default configuration is loaded within a couple of seconds If the user saves a configuration in the internal EEPROM NIMbox NEMbox loads the saved configuration Important remark for NIMbox NEMbox with ADCs SU706 Since a new connector has been added to each ADC channel to fully exploit the differential capability of the ADC chip even with unipolar input connectors in order to operate the ADC with an unipolar input it is necessary to short circuit the unused connector A s
13. adAddr modulo 1024 is set to WriteAddr PostSamples PreSamples October 10 19 00Sachnummer A User s Manual Nembox W Ie Ne R Plein amp Baus GmbH in order to start reading the data from the beginning of the recording After reading the sampled the memory can be used again for recodring data An additional functional block PulsParams determines independently and in real time some pulse characteristics which can be read out in addition to the sampled data These characteristics refer to a pulse which is above the defined threshold as shown in the following figure Data May Hee ee essen i I I Sum I I RSS Threshold SEES SETS ee te a tee ee a oe tee ae ae ee et ae ce eee ee eer MaxPos i Min E 777 7 Width IntTrigger Fig 2 Definition of pulse characteristics parameters 3 7 1 ADC VI usage example In order to correctly read out the ADC with the provided Labview VIs the typical sequence of operations is 1 Use ReadStatus to ask for overflow TRUE and running FALSE 2 Use ReadData to read the wave 3 Use WriteParamsAndClear to reset the ADC for the next trigger Alternatively the ADC vi can be used in histogramming mode see parameters File Edit Operate Tools Browse Window Help an USB LogicBorx Version Interface Reset Program Th ene i PRE TR EE re me SS atv iin GE ee er ee ih et tf fot TTT TTT TT T ET 7 E2LFYEIA5O
14. anual Nembox W Ie Ne R Plein amp Baus GmbH Hardware description FPGAs A field programmable gate array is a semiconductor device containing programmable logic components and programmable interconnects The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as AND OR XOR NOT or more complex combinational functions such as decoders or simple mathematical functions In most FPGAs these programmable logic components or logic blocks in FPGA parlance also include memory elements which may be simple flip flops or more complete blocks of memories An hierarchy of programmable interconnects allows the logic blocks of an FPGA to be interconnected as needed by the system designer somewhat like a one chip programmable breadboard These logic blocks and interconnects can be programmed after the manufacturing process by the customer designer to implement any logical function hence field programmable However this hardware programming is somewhat complex and requires programming tools for example VHDL and considerable development effort For this reason Nembox is shipped with a special software Logic Pool that provides the user with a large number of preprogrammed function modules that are typically useful in signal processing General description of Nembox Nembox is a programmable NIM module based on a FPGA board DL706 with 4 slots for I O submodules that serve as interface between t
15. e follow these steps a contact Wiener Plein amp Baus to get authorization to open NIMbox NEMbox if it is under guarantee b disconnect and open NIMbox NEMbox c setthe jumper close to the quarz oscillator near the USB plug see picture d power and connect NIMbox NEMbox it w ll show up as new device e reinstall the drivers run the DL700_FX2_ Install tool or request it at Wiener Plein amp Baus f disconnect NIMbox NEMbox to remove the jumper g close NIMbox NEMbox power and connect Warning restoring the EEPROM deletes any saved configuration October 10 22 00Sachnummer A User s Manual PAS Nembox W Ie Ne R Plein amp Baus GmbH gt lt t amp 6 u amp we 4 8 wee gt 84 we een so e ee ere 2 LA an en oo 5 4 E gan 111 g 1100500 g 4 L 4 Figure 4 Location of the jumper to restore the EEPROM red arrow on the lower right corner October 10 23 00Sachnummer A User s Manual Nembox W Ie Ne R Plein amp Baus GmbH October 10 24 00Sachnummer A
16. function to input output ports by means of a software we need to assign them a number Let s consider the DNAE version SU703 SU704 SU706 and SU710 as example The 17 I O ports of NIMbox NEMbox DNAE version have a default assi NIMbox NIM module top gt bottom nment as follows Table 6 Mapping of physical I O ports on front panel T indicates a programmable TTL VO port A an ADC input N a NIM or TTL programmable I O port D a discriminator input port and E a DAC output port Please note that in order to change a NIM I O into a TTL I O or viceversa a hardware intervention is needed it is necessary to change the position of the corresponding jumper in SU704 This labeling is very important in order to map the physical position of the I O ports to the corrisponding software identifiers While using LabVIEW VIs the integer number which is part of the port label should be provided as input October 10 9 QOSachnummer AO User s Manual Nembox W Ie Ne R Plein amp Baus GmbH NIM and TTL VO ports are identified seguentially in Labview e g T1 corresponds to port 1 T2 to port 2 and N4 corresponds to port 8 3 5 Logic Pool for Labview M Logic Pool is a set of tools for programming the Nembox FPGA under Labview It consists of the following components e Firmware e USB communication VI e Applications VIs The firmware is preinstalled on Nembox and can only be modified by advanced u
17. he FPGA I O signals and the signals in the external environment It 1s equipped with a USB port for programming and read out and a connector for direct FPGA programming debugging Its 100 MHz clock makes Nembox well suited for processing signals with length down to 10 ns and frequencies of several MHz Such signals are common in nuclear and particle physics applications where NIM and TTL standards are used for signal transmission and processing NIMbox can be used for several application Typical examples are ADC discriminator DAC NIM TTL logic trigger implementations gate generation and data acquisition I O submodules Presently the following submodules are available for Nembox Table 1 Nembox I O submodules Suibmodule SU700 5x TTL I O LEMO COAX SU705 16 MByte RAM 2x Fast DAC 100 Mhz SU711 6 x programmable Delayline 0 5ns 128 ns SU712 16 x ADC 5 us 14 Bit SU713 16 x DAC 14 Bit October 10 3 00Sachnummer A 2 4 2 5 User s Manual Nembox W Ie Ne R Plein amp Baus GmbH Hardware configuration The slots for submodules in the main FPGA board are named MODO MOD1 MOD2 and MOD3 counting top to bottom For example in the NDL8 version see Wiener product catalog two slots are occupied by SU703s discriminator and two by SU704s NIM TTL VO Please note that the preinstalled firmware depends on the ex works hardware configuration therefore only advanced users should consider removing subst
18. horting plug is needed for this operation Examples of operation with default configuration a Positive signals Insert the shorting plug in the first connector Connect the signal cable to the second connector b Negative signals Connect the s gnal cable to the first connector Insert the shorting plug in the second connector Wrong connections result in absence of s gnal or in wrong output values for peaks and charge integrals n the FPGA Hardware detection and software installation 1 2 1 Windows Once NIMbox NEMbox has been powered and connected to a USB port the hardware installation wizard will guide the user through the installation steps It is recommended not to let Windows look for a proper driver Choose instead to manually install the driver software from the NIMbox NEMbox package If the package drive is D the driver directory is D NIMbox NEMbox Version USB Driver FX2 You may look for the driver files with the Hardware Manager of Windows or run the installation script in the above directory After successful installation the user can verify the proper operation of NIMbox NEMbox in the Control Panel in the Device Manager there should be a new entry named DL7XX LogicBox Alternatively the user can start the LabVIEW based programs IsNimboxThere vi or ListModules vi available in the package which has a field for the NIMbox NEMbox USB address string and will return the NIMbox NEMbox device ID
19. ituting or swapping submodules because this operation requires firmware reprogramming SU703 Discriminator I O SU703 has 1 to 4 discriminator inputs and 4 to 1 TTL I O ports where the total sum of the devices is limited to 5 1 e the number of LEMO COAX connectors on the front The first LEMO connector corresponds always to a discriminator while the last one always to a TTL I O port Connectors 2 to 4 are discriminators by default but their functionality can be changed with minor hardware modifications Discriminators thresholds can be programmed within the 2 5 2 5 V range and discriminators hystereses within the 0 60 mV range both with 12 bit resolution High hysterese values are used to prevent multiple threshold crossing and thus multiple signal generation due to noise The propagation delay is 3 4 ns and the maximum input frequency is 100 MHz The LEDs can be programmed independently from the I O ports and a 10 ms stretcher is applied in order to make short signals visible TTL I Os can generate a current of more than 60 mA and therefore a sufficient TTL level gt 3V with a 50 Ohm terminated coaxial line If used as inputs TTL I Os must be terminated with 50 Ohm Alternatively it is possible to bring the input port high through a pull up resistor of about 1 kOhm and through a simple switch it is possible to bring it down by shorting Table 2 SU703 discriminator pin assignments LT COUT 4 p discr out ch 4 p
20. n ch 3 17 OUT3 NIM TTL out ch 3 INECL3 NIM in ch 3 21 TINTTL2 TTL in ch 2 October 10 5 00Sachnummer A User s Manual Nembox W Ie Ne R Plein amp Baus GmbH 28 OUTI NIM TTL out ch I 29 30 2 7 SU706 ADC submodule 2 7 1 Jumper settings at input stage Since the 3 generation of SU706 september 2009 a new input connector has been added to SU706 Since the signal applied internally to the ADC input is differential while the input connectors are unipolar with a second connector it is possible to preprocess data with the same FPGA algorythm for negative and positive signals In other words it is possible to exploit the differential capability to invert the singal by swapping connector However the connector where no signal is applied must be shorted either externally or from trained staff internally through jumpers The default jumper settings in the input circuitry behind the ADC connectors left is as follows da 112 4 By default JX1 and JX2 are set to 1 2 October 10 6 00Sachnummer A 3 1 User s Manual Nembox W Ie Ne R Plein amp Baus GmbH Software description USB communication The Nembox USB interface provides a number of commands for communicating with the system or with the submodules All commands are byte oriented and identified by an ASCII character Addresses and data 1 to 4 bytes are binary and the sequence of word and longword transfers is
21. ositive 3 COUT 4 n discr out ch 4 negative COUT 3 p discr out ch 3 positive 6 COUT 3 n discr out ch 3 negative Un COUT 2 p discr out ch 2 positive 8 COUT 2 n diser out ch 2 negative 9 COUT 1 p discr out ch 1 positive 13 LDAC_n load DAC 17 IN2 TTL in ch 2 ch 4 21 OE_4_n enable TTL out ch 4 low active OUT_3 TTL out ch 3 OE 3 n enable TTL out ch 3 low active OUT 2 TTL out ch 2 October 10 4 00Sachnummer A User s Manual Nembox W Ie Ne R Plein amp Baus GmbH OE_2_n enable TTL out ch 2 low active 26 OE 1 n enable TTL out ch 1 low active LEDS IN4 TTL in ch 4 2 6 SU704 NIM VO SU704 has 5 identical LEMO COAX I O connectors to be used as programmable digital I O ports Every I O port supports both NIM and TTL levels but the selected level is defined by a jumper setting on the SU704 board default level 1s NIM Input impedance can be set to 50 Ohm through a relais Every NIM output can draw a current of 16mA thus with a 50 Ohm impedance the level is 0 8V The corresponding input threshold with 50 Ohm set is 0 4V Maximum frequency is 100 MHz and propagation delay less than 4 ns Table 3 SU704 NIM VO pin assignments 5 INECL5 NIM in ch 5 OUT4 NIM TTL out ch 4 INECL4 NIM in ch 4 ENA4 enable TTL out ch 4 low active REL4 relais 4 INTTL3 TTL i
22. r indicator that indicates how many signals were received from port 1 within the 5 seconds mE EEE EEE GE EEE EEE EEE EEE EEE EEE EEE EEE EEE EEE EEE EEE HE GE EEE EEE NEO October 10 17 00Sachnummer A User s Manual Nembox W Ie Ne R Plein amp Baus GmbH 3 7 Usage of the ADCs The ADCH VIl is a fast 14 Bit ADC Module with max 100 MHz sampling rate for recording of selected pulse parameters based on the SU706 ADC plug on SU706 is the 14 bit 100MHZ sampling ADC module with AC coupled bipolar input with 50 Ohms impedance The following picture 1 shows the block diagram and principle operation of the ADCH module Width ee Puls Sum _ Params Min Max o _ _ re O Distr Pos ne Data ReadAddr WriteAdcr Threshold Trigger Addr PresSamples ris Counter PostSamples S 100 MHz Fig 1 ADC block diagram October 10 18 00Sachnummer A User s Manual Nembox W Ie Ne R Plein amp Baus GmbH I Locked Context Help ADCH USE In USE Out GATE DISCR DATA PARAMS Function ADC Histogrammer LC Programme National Instruments LabVIEW 7 l userib LogicPool ADCH Yi Fast 14 Bit ADC Module with max 100 MHz sampling rate for recording of raw data and gate parameters This version allows alternatively histograrmming of any datal Support SUYO6 Output DISCR goes true for ADC data gt Threshold
23. s written permission of W Ie Ne R October 10 1 00Sachnummer A Table of contents ES S SP r OREN AEE ae RT ETAT ON EN Ore AE EE CeIn RETA emer ety Lsd TOW SL UD basi EE E l 1 1 1 Important remark for NIMbox NEMbox with ADCs SU706 RR 1 1 2 Hardware detection and software installation ccccccccccccccccceeeesesesseseseececcceeeeeeeeesaaaassessseseeeeeeeeess l 121 A E E E E E E E E E E E l le EN A A E 2 Eo Porinom n oF Ae i i a a a E ss aa 2 2 o E L aa israiska enters 3 PS is ii ia ase i i aa a a i a a a a a 3 2 2 General description of NEmMBOK 45 issiusti kia ei ano ku is ui i a ra a so a k i bs aaa o a 3 253 L POQUE E T 3 ZA Hardware COM trank a O k i nenni Dessehanetescse 4 23 SUO DSC EM AEG ig aisiais i a i i i a a a e 4 26 SLO NIN RO a ed sta 5 21 I OOS DC SUB MIO GNC ann eee ea a en ane ane aa eee cd 6 2 141 Juniperseltinss AC input Stage 6 S MM aa P A TS 7 3l USB commune aon esseen O eOr E ob OES 7 e P Sos ce castes E Ai e sasas a a e E E a ais E 8 3 3 Definining FPGA connections 9 Pod Reserve A ec E es ee ye E E 9 3 4 Example Port Mapping Front Panel sens 9 S sis od OO OR LAD IC Eisiu aa a a a a a o a i a as aaa 10 Rs Bio MPP pP PP r becencteidaseaabs aaatat eg auacas yecenctonceeasanscentaw 10 3932 Disc M LUE Le 11 ER else 12 COR asies E S aaa aa asa aaa S aa ob ao aids 13 3 33 CLS GO ee eee 13 390 LED si i i i i i i i i a a i i Ce 13 3 9 EX AMOS S ania a ie is i i
24. s GmbH D n Bytes Read Bytes write o lo li MUX IN a Threshold pa a STATE_IN Threshold The threshold 2 5V 2 5V for the analog input signal is set through a 12Bit DAC The most significant 4 bits determine the channel in each module Hysteresis The hysteresis 0 60mV for the analog input signal is set through a 12Bit DAC The most significant 4 bits determine the channel in each module 3 5 3 Logic Module Module one USB In TE USE Out fi nn NN T ni P OR j E Is Ps er x E LPL LL LIT Function Function OR AND This set of VIs provides the basic logic functions LOGIC MUX_Out A_MUX Ci pa STATE O ai Bmux Mode OR AND XOR RS FF S FF D FF Differentiator Differentiator Start Asynchronously Synchronisator Synchronisator Start Asynchronously FF Flip Flop 0 FF is deleted 1 255 FF is set October 10 12 00Sachnummer A User s Manual Nembox W Ie Ne R Plein amp Baus GmbH 3 5 4 Counter Module f e Module LISE In TRIG USE Cut TRIG Lk Count CLK Params Bar Function Function PULSER COUNT This set of VIs can be used for counting scalers or to generate an arbitrary train of pulses COUNTER lil TS NS Counter Mode Clear Counter et Palse marks Clear Counter Pan Lt a Pulse marks Clear Counter Mode 0 COUNTER 1 PULSER 2 ASYNC PULSER 3 5 5 Gate Generator LATELEM LISE In Params Func
25. sers with detailed hardware information For example the DNAE version is equipped with the following FPGA resources e 1x ADC to control the ADC inputs e 3xTTLI O e 5x NIM or TTL I O e 8x Logic e 4x Counter e 10x LED e 1 x TDC These resources are described in this chapter and each one has its corresponding application VI for easy access The USB communication VIS is a VI interface to the file DL7xx_FX2 dll The application VIs implement the following functionalities e DIO e DISCRIMINATOR e LOGIC e COUNTER e LED e TDC e ADC e DAC In order to make it possible to use more than one Nembox instance at one all VIs have the I O parameters USB In and USB Out that can be used to distinguish sessions By using the provided OPEN vi instrument the selected USB device will be stored in a local variable for reference of all other modules This simplifies wiring of the moduls for single NemboX setups 3 5 1 DIO Lt LISE In LISE Our If Mrurerrenrunuig 2 OUT Params Function D O DI vi Picture 1 Digital I O Virtual Instrument 10 00Sachnummer A User s Manual Nembox W Ie Ne R Plein amp Baus GmbH This VI controls a physical NIM or TTL VO port on Nembox Function can be set to e Connect default and normally executed once initially e Set IN sets the output to True or False overrides any connection to OUT e Get OUT returns the status of the port The Params cluster provided by the
26. tion This VI is a simplified version of the pulser and is used to generate a programmable gate when a trigger TRIG fires 3 5 6 LED LED LISE In USB Out STATE Function LED This VI is used to control the status of the LEDs The integer LED determines which LED is being programmed according to NIMbox NIM module top gt bottom October 10 13 00Sachnummer A User s Manual Nembox W Ie Ne R Plein amp Baus GmbH Table 6 LED Pa Bytes Read Bytes write o o il lot Pex October 10 14 00Sachnummer A User s Manual Nembox W Ie Ne R Plein amp Baus GmbH 3 6 Examples Basic application structure 0 Digital I O Port 2 is programmed as NIM output without termination digital I O Port 3 is programmed as TTL output unlike the 50 Ohm NIM and TTL levels are NOT software selectable Jumpers must be in the corresponding position S TTL High Imp October 10 15 00Sachnummer A User s Manual Nembox W Ie Ne R Plein amp Baus GmbH Digital I O port 1 is programmed as NIM input with 50 Ohm termination and is connected to digital I O port 2 which is programmed as NIM output without termination and digital I O Port 3 which is programmed as TTL output Examples of NIM and TTL levels are pictured The typical signal delay introduced by this simple circuit and by 1m cables for measurement between DIO 1 and DIO 2 or 3 is about 20ns 950mV
27. wares than the default one provided the hardware configuration matches Please contact Wiener Plein amp Baus GmbH for information and to get authorization in case your device is under guarantee FpgaUpdateTool can be used to install new firmwares via USB The firmware must be in the main directory of your local hard disk e g c myFirmware bit Installations from other directories with special characters or from network drives may fail Installing self made firmwares Wiener Plein amp Baus GmbH may disclose hardware information to expert users and or VHDL programmers in order to program NIMbox NEMbox to meet special requirements For writing and installing self made software the IDE tool from Xilinx is highly recommended The user also needs to know which FPGA and which memory s used in the device and which are the pin assignments of its components in order to find the correct libraries for new applications and in order to correctly synthesize and build the firmwares Please contact Wiener Plein amp Baus before reprogramming the device Troubleshooting Restoring the EEPROM Incorrect software usage power supply interruptions or other events may result in EEPROM corruption In case NIMbox NEMbox no longer appears in your USB device list on the device manager please make sure at first that it s properly powered and connected If t is impossible to esthablish USB communication it may be helpful to restore the EEPROM Pleas
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