Have I Really Met Timing? - Validating PrimeTime Timing
Contents
1. Timing path cell 2 falling U16 d1 gt falling U16 x The side pin U16 d0 The side pin U16 s10 is sensitized to is sensitized to high KKK KKK ck Ck Sk ck Ck ck Ck Ck Ck kk Ck kk kk ck kk Sk kk ko kk ko kc k ko kc KKK KK SPICE pin order used pin sub node X U16 x D0 U16 d0 xU16 U16 x U16 d0 U16 d1 U16 s10 mux2 2 KKK KKK KKK ck kk ck kk Ck kk Ck kk kk ck kk ko kk Sk kk ko kc k ko KKK KKK A2AAAAAAAAAA HHHHHHhHHHHHHHHHHsHhH ox x CO CO COO OGOGO0GO0GO0cGO0cgoOi ccocdoccoocgocoocdccoocccocccococccocococ Timing path net 2 resistor s for net ips rdata 3 driver pin U16 x round capacit mp 100 ips rdata ips rdata 101 ips rdata ips rdata 102 ips rdata id ips rdata 103 ips rdata 3 ips rdata 104 ips rdata 3 ips rdata 105 ips rdata 33 ips rdata 106 ips rdata RI U16 x 107 ips rdata sl ips rdata 108 ips rdata SQ ips rdata 109 ips rdata us ips rdata 110 ips rdata TIS ips rdata 111 ips rdata 18 ips rdata 112 ips rdata 6 ips rdata 113 ips rdata 6 ips rdata 114 ips rdata 6 ips rdata 115 ips rdata tU ips rdata 116 ips rdata 7 ips rdata S i 9 Q9 9 9 9 9 9 9 9 9 9 B2 C29 CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO falling ips rdata 3 Ww CO C0 CO CO CO C9 CO CO CO WW CO CO CO CO low for net ips rdata 3 102 ips rdata 0 0 001f 103 ips rdata 0 0 065391f 104 ips_rdata 5 0 0 0247121f 105 ips rdata 4 0 0 422. 1 The Golden Reference for timing Static Timing Analysis has become the method of choice for timing sign off before tape out Because of its superior analysis speed especially on chip level and the completeness that no pattern set can provide it has pushed back simulation with timing to a state where it is only little more than an option on the flow chart in a modern design flow Only very few customers for ASIC chips today require a chip level simulation with timing for acceptance of the silicon As for timing simulation the basis for Static Timing Analysis is delay calculation The goal of delay calculation is to predict the timing that the silicon reality 1530 1591 04 20 00 c 2004 IEEE of all devices on the chip will show But there is a pitfall Due to process variations temperature dependencies and the influence of voltage variations there is not one single silicon that can serve as a reference When developing a new silicon technology a lot of time money and effort is spent on collecting statistical information on the variation of timing and other characteristics like power and reliability with process parameters voltage and temperature PVT From these statistical models the so called transistor models in Spice format are generated These are one of the fundamental bricks a silicon library is built of They describe the characteristics of a transistor based on parameters like its length width and many more It is becau
3. 5 Generating a reference timing report When verifying the timing of a path through a single cell there are only two timing points on the path the start point and the end point Anything inside the cell is not visible to PrimeTime This approach of just analyzing the delay from start to end point can of course also be used on more complex timing paths through more levels of logic If the Spice simulation results in the same delay from start point to end point this information is sufficient But if there should be a difference you will need more details for analyzing the source of the problem The advantage of generating and triggering the Spice simulation from the PrimeTime shell is that you know which timing points can be found on the timing path Also the names of the timing points in the Spice deck and the timing path object are identical So it is easy to add additional measure statements to the Spice deck to access any timing number you need measure total delay tran d 1 2 trig v ips_addr 7 val 0 81 fall 1 targ v U73 B val 0 81 fall 1 tran d 1 3 trig v ips_addr 7 val 0 81 fall 1 targ v U73 Y val 0 81 fall 1 tran d 1 4 trig v ips_addr 7 val 0 81 fall 1 targ v U72 D val 0 81 fall 1 measure measure measure 53 measure measure val 0 81 rise 1 measure delta delay measure tran d 2 3 trig v U73 B val 0 81 fall 1 measure tran d 3 4 trig v U73 Y val 0 81 fall 1 measure tran d 4 5 trig v U72 D val 0
4. 7 fal gt thresholds can be if ios ips sdatadoi ei your design contains several voltage pin domains For example if you have pad cells at the start or end point of your timing path you need to find the correct voltage level for each point on the path to trigger your measurement correctly The parser for the Spice result file now ips addr 7 73 B TIY 72 D 72 X 70 A 70 Y 67 C 67 Y 76 A TOLY 78 A 78 Y needs to be enhanced to 2 he read the simulation ips rdata 0 results back into PrimeTime The TCL capabilities of 1 se edge fall fall fall fall fall fall rise rise fall fall rise rise rise rise rise rise PrimeTime is 2 82 off the Spice results from the simulation and compare it to the timing that was calculated by PrimeTime Table 7 shows an example for such a report It contains the delta and total delay for each stage of the timing path From such a report you can easily locate the source of differences in the timing Of course there are endless possibilities for additional analysis for example the transition times at all timing points of the path could be measured in the simulation and be compared to the calculated transition times Such a report can only show if there are differences in the delays and if there are which cells or interconnects contribute to the difference A possible reason for a mismatch could be that the signal slope at some timing point excee
5. 81 fall 1 tran d 1 15 trig v ips_addr 7 val 0 81 tran d 1 16 trig v ips_addr 7 val 0 81 fall 1 targ v U92 Y val 0 81 rise 1 fall 1 targ v ips_rdata 0 V U73 Y v4tU72 D V U72 Y val 0 81 val 0 81 val 0 81 targ targ targ measure tran d 15 16 trig v U92 Y val 0 81 rise 1 targ v ips_rdata 0 val 0 81 rise 1 Table 6 Measure statements that can be added to the Spice deck for a detailed analysis I found it most useful to generate a report that resembles the output of the report timing command in PimeTime This timing report shows the incremental delay for each cell and each interconnect between the cells on the timing path In addition to that the total delay from the start point to each point on the path is reported Table 6 shows an example for the measure section to acquire the information for such a detailed report When generating the measure statements you need to be careful which voltage threshold to select Depending on the setting in your library the thresholds for delays could be 50 of the supply voltage or for example 20 for a rising edge and 80 for a falling edge If the thresholds for the measurements are set differently than in your library you will find that the total path delay will be close to what you expect but the delta delays for the cells and nets will sometimes be significantly smaller or larger Another challenge when generating the measure PATH 41 from ips addr
6. ET FE AE FE EH HEE E FE AE FE EE ET HEE EE AE AE EE HEE EE EE EH HHPAHAPAAPAPAPAHAPAAHAHA CHAAR ee E E E set lib delay expr get attribute Sendpoint arrival get attribute startpoint arrival if spice delay gt 1ib delay set diff expr spice delay 1lib delay 100 0 spice delay else set diff expr 1ib delay spice delay 100 0 1ib delay puts format s s s s PrimeTime 4f Spice 4f Difference get attribute get attribute Sstartpoint object full name get attribute startpoint rise fall get attribute get attribute Sendpoint object full name get attribute endpoint rise fall 1ib delay spice delay diff EOF
7. timing References 1 PrimeTime User Guide Fundamentals Synopsys Version T 2002 09 2 PrimeTime User Guide Advanced Timing Analysis Synopsys Version T 2002 09 3 PrimeTime SI User Guide Synopsys Version T 2002 09 4 HSPICE User s Manual Meta Software Volume 1 3 California 1992 5 Brent B Welch Practical Programming in TCL and TK 3 Edition Prentice Hall 1999 810 668m 14 000 time nsec 7 Appendix 7 1 An example for a Spice deck generated by PrimeTime lib lib lib lib lib lib lib vb lib lib Lib libraries tsmc18 spice mapped libraries tsmc18 spice mapped libraries tsmc18 spice mapped libraries tsmc18 spice mapped libraries tsmc18 spice mapped libraries tsmc18 spice mapped libraries tsmc18 spice mapped libraries tsmc18 spice mapped libraries tsmcl18 spice mapped libraries tsmc18 spice mapped s libraries tsmc18 spice mapped MIN timing path section rising ips rdata 3 global vdd vss vvdd vvss temp 150 prot lude home tobias spice netlist unprot inc Timing path section rising timer 1l counter buf reg 3 ck gt vdd 0 1 35 vss 0 0 rev2c rev2c rev2c rev2c rev2c rev2c rev2c rev2c rev2c rev2c rev2c timer 1 counter buf reg 3 ck BASE BSI WCS PARA WCS FE WCS IO DIODE RESIS DEFINE MOSFE WCS_NATO WCS_NA
8. write spice deck output spice file header header file sub circuit file netlist file timing path Table 1 The most important arguments of the write spice deck command The basic components for any Spice simulation are the Spice models These Spice models are stored in one or more Spice library files and contain the information on the basic components of your technology like CMOS transistors diodes resistors etc These Spice models are only needed for the Spice simulation not for the generation of the Spice deck in PrimeTime However The write spice deck command generates a complete deck for the Spice simulator that contains everything to start simulating not only the netlist Therefore it is possible to specify a Spice header file when generating the deck This header file contains a list of model libraries that need to be read in by the simulator An example for such a header file is shown in Table 2 18 spice mapped 18 spice mapped 18 spice mapped 18 spice mapped 18 spice mapped 18 spice mapped 18 spice mapped 18 spice mapped 18 spice mapped 18 spice mapped 18 spice mapped dp c E ORS Table 2 An Example for a Spice header file The lib statement instructs the Spice simulator to read from a technology file the named library As you can see there are not only libraries for elements like transistors and diodes but also libraries that define p
9. 1554f 106 ips rdata 5 0 0 162986f 107 ips_rdata 26 0 0 087714 108 ips_rdata s 0 0 0328137 109 ips rdata 8 0 0 001f 110 ips rdata 9 0 0 0122159f 111 ips rdata 10 0 0 001f 112 ips rdata ld 0 0 0249453f DOOVOFDOFWODODODOFONO 7 a CDOCOCVOHNOBRODVOO IO D1 U16 d1 SL0 U16 s10 6725 916 W N N falling falling ips_rdata 3 c00113 ips rdata 3 12 0 0 00125659f c00114 ips_rdata 3 13 0 0 001f c00115 ips_rdata 3 14 0 0 001f c00116 ips rdata 3 15 0 0 001f c00117 U16 x 0 0 001 f c00118 ips rdata 3 17 0 0 001f c00119 ips rdata 3 18 0 0 001f aaa KKK KKK KKK KK KKK KKK KEK KKK KKK KKK KK KKK KKK KKK KKK INFO PrimeTime created the following PWL or voltage source Please verify KEKE KK KKK KKK KKK KKK KKK KKK KKK ck ck ck ko ck kv Sk KKK ko ko ko ko Timing path sequential data pin voltage section rising timer l counter buf reg 3 ck falling ips rdata 3 Arrival Window Info for pin timer l counter buf reg 3 d x x clk pos edge min r f 3 47638 3 54304 max r f 5 73091 6 00015 clock rise fall 0 5 For rising pwl vtimer 1 counter buf reg 3 d timer 1 counter buf reg 3 d 0 pwl 0 0ns 0 a 13 4263ns 0 t 13 5376ns 1 35 For falling pwl vtimer 1 counter buf reg 3 d timer 1l counter buf reg 3 d 0 pwl 0 0ns 1 35 13 4881ns 1 35 t 13 6102ns 0 End of timing path sequential data pin voltage section Timing pa
10. E FE EEE ERE FE HE E TE EE E E AE AE E E E E E E E E E E E E E E EE proc verify_path_timing path global spice_header spice_netlist supply_voltage create the Spice deck write_spice_deck output spice pt header spice_header sub_circuit_file spice_netlist path add a measure statement to the spice deck for the path delay sh sed e s print print e s unprot unprot N e s prot prot s end end spice pt gt spice ckt set points get attribute path points set siz sizeof collection points set startpoint index collection points 0 set endpoint index collection points expr size 1 set startname get attribute get attribute startpoint object full name set endname get attribute get attribute Sendpoint object full name regsub all Sstartname startname regsub all endname endnam echo format measure tran delay trig v s val f s 1 startname expr supply voltage 0 5 get attribute startpoint rise fall gt gt spice ckt echo format targ v s val f s 1 Sendname expr supply voltage 0 5 get attribute Sendpoint rise fall gt gt spice ckt echo end gt gt spice ckt Pre rr rrr rrr rrr rr rr re gZL ETIE ECEE ETTET EERE EEE ET ER TITEL GG GSP GG Gg 01 11 1g The following command is specific for the Spice simulator used This needs to be custo
11. EER EEEE HE HEHE HH EH RE HE EEE EE EE EE HE EEE FE EE EE HE EEE BE EEE EE HE EEE FEE EH proc create_testcase_for_cell cell filename search for library cell foreach_in_collection lib get_libs set libname get_attribute lib full_name set libcell get lib cells libname cell quiet if Slibcell break if info exists libcell Slibcell puts Error could not find cell cell in any library return 1 Create string lists foreach in collection pin get lib pins of object 1libcell set pinname get attribute Spin base name set pindir get attribute Spin pin direction append portlist pinname append pinlist pinname Spinname append iolist An Spindir put pinname write testcase fil set FILE open filename w puts SFILE format module verification top s string trimleft Sportlist J I puts SFILE string trimleft Siolist puts SFILE puts SFILE format S cell DUT s string trimleft pinlist puts SFILE endmodule close SFILE return Slibcell HEHE FE FE HE E TE EH TE FE HE EEE FE HE EE FE FE EE EEE EE HE HE HE E TE FE FE EE ER EE E TE EE ERE EE HE HE E E ERE EE E E E EE EE Run Spice simulation on a timing path parse and compare the results HEHE FE FE HE E TE HE HE TE FE HE E TE FE FE HE TE FE FE FE E T
12. Have I Really Met Timing Validating PrimeTime Timing Reports with Spice Tobias Thiel Motorola GmbH Semiconductor Products Sector Munich Germany tobias thiel 9 motorola com Abstract At sign off everybody is wondering about how good the accuracy of the static timing analysis timing reports generated with PrimeTime really is Errors can be introduced by STA setup interconnect modeling library characterization etc The claims that path timing calculated by PrimeTime usually is within a few percent of Spice don t help to ease your uncertainty When the Signal Integrity features were introduced to PrimeTime there was also a feature added that was hardly announced PrimeTime can write out timing paths for simulation with Spice that can be used to validate the timing numbers calculated by PrimeTime By comparing the numbers calculated by PrimeTime to a simulation with Spice for selected paths the designers can verify the timing and build up confidence or identify errors This paper will describe a validation flow for PrimeTime timing reports that is based on extraction of the Spice paths starting the Spice simulation parsing the simulation results and creating a report comparing PrimeTime and Spice timing All these steps are done inside the TCL environment of PrimeTime It will describe this flow what is needed for the Spice simulation how it can be set up what can go wrong and what kind of problems in the STA can be identified
13. an be verified using the command verify_cell_timing BUFX2 The script generates an output like in Table 4 Investigating BUFX2 A f gt Y f PrimeTime PrimeTime 0 4393 Spice 0 4411 Difference 0 3685 Spice 0 3602 Difference Table 4 An example for the output of verify_cell_timing Simulating just a single cell in Spice takes only a few seconds So using this script it is possible to compare all timing arcs of all cells in a library to the Spice simulation This can be started running the commands listed in Table 5 read_db library lt library gt set allcells foreach in collection cell sort collection get lib cells lt libname gt set allcells concat Sallcells get_attribute cell base_nam l verify cell timing Sallcells Table 5 Verifying all cells of a library Such a comparison of a whole library can easily be run over night In such a comparison it is normal to have a difference of a few per cent on each timing arc Since the Spice simulation is run only for one set of boundary conditions depending on how well these match the conditions for which the cells were characterized the difference will vary It can happen that for complex gates such as a multiplexer the timing model in the library is incomplete or is not modeled correctly Using this approach of verifying all timing arcs to Spice such modeling errors stick out by showing differences of more than 10
14. arameters for the process What libraries are actually available and needed is specific to each technology Often header files for the different process conditions are delivered with the library If this should not be the case once you have located the Spice library file you can search for the lib statements inside this file and find out which libraries are available Based on this it is easy to set up the header file The final ingredient for the Spice deck extraction and the simulation are the extracted netlists for the standard cells These netlists are the links between the standard cell based netlist that is used by PrimeTime and the basic elements that are used in Spice Table 3 shows an example for such a netlist The netlists for all standard cells need to be concatenated into a single file Alternatively it is possible to generate a file referencing separate netlist files with the include subckt BUF Y A m pl vdd netl Y vdd pch m nl Y netl vss vss nch m pO vdd A netl vdd pch m n0 netl A vss vss nch cl netl vss 6 52119E 16 c2 Y vss 2 48623E 16 C3 A vss 4 12536E 16 ends E 1 J I 0 0 0 0 Table 3 An example for the extracted netlist of a standard cell Spice statement This global netlist file is passed to the write spice deck command with the sub circuit file switch PrimeTime will parse this file when generating the Spice deck to determine the pin order on the sub circuits that form the standard c
15. ds the range for which the library cell was characterized This can happen on nets with high loads but also on nets with small load that have a strong driver In these cases the slope is smaller than the smallest or PrimeTime timing delta total Spice timing delta total 00 44 108 007 624 006 181 015 421 018 869 024 501 680 986 003 000000 000044 462152 462159 860783 860789 987970 987985 125406 125424 266293 266317 597818 600498 759484 759487 00 43 418 027 903 038 866 082 432 084 620 044 523 659 551 009 000000 000043 443462 443489 850391 850429 961295 961378 091809 091893 221513 221557 540080 542739 711290 711299 CO OOOOOoOooooocoocococo ODROWOFOFDOFODWWORDOO ODONFDDOOANONODONOO BPR RP eHO O O 0 0 0 2 C QOOOOooooooococococococo ODROWOFOFRFOFOROBROO C OO0h2OOCO Oo OO OO 00000 c0 IE pERLBEPPmPPmPPPHCOOCOOOOOO 4 1 3 2 1 6 6 9 2 3 4 3 5 PrimeTi is pessimistic PrimeTime can also be Table 7 A timing report comparing PrimeTime timing to the Spice simulation used to format the data results larger than the largest entry in the timing table The delay calculation tool will in such a case extrapolate the value what can be quite inaccurate Another example for an error that was found using the comparison to Spice was when a pad library was used that operated at 3 0 volt while the core cells ope
16. ed to the same clock signal After the netlist of the timing path follows the dynamic voltage sources for the inputs that trigger the transition on the path If the path doesn t contain any sequential elements only the start point is driven by a dynamic source In the example in the appendix you can see that there are two dynamic voltage sources One source is for the clock signal that is the starting point of the timing path The second dynamic source stimulates the data input of the flipflop in the path so that it is first initialized to receiver pin Receiver Picture 1 Interconnect modeling with Wire Load Models high After this input changes to low a falling edge at the output of the flipflop is triggered with the next clock event In addition to the dynamic voltage sources there are a number of static sources that set the inputs of the gates to defined values so that the path you want to simulate is sensitized and the transition can propagate through all cells At the very end of the Spice deck you can find a tran statement This tells the Spice simulator to run a transient analysis with the given minimal time resolution and duration This Spice deck is sufficient to simulate the timing path However to analyze the results and to compare them to the PrimeTime timing there are some measurements needed Probably the best way to add these measurements is to insert them into the Spice deck based on the timing path the deck was
17. ells If a cell is missing in the netlist file the PrimeTime tool will generate a warning message Obtaining the complete and correct set of extracted netlists is sometimes the most challenging work when setting up the Spice simulation In many library distributions only Spice netlists targeted for LVS analysis are available These netlists usually don t contain the parasitic elements and therefore result in inaccurate timing You should always check that the netlists contain extracted parasitic elements like the three capacitors in the netlist in Table 3 If your design contains non standard cells like memories obtaining the netlist for these blocks is usually even more challenging Of course it is possible to extract a Spice netlist of a memory block from the layout but the large number of elements probably will significantly impair your simulation time In such a case you should consider to extract only a part of the memory like the access logic or maybe you can live with a dummy model 3 The Spice deck generated by PrimeTime Although the write spice deck command of PrimeTime usually generates a complete Spice file that can be directly simulated there are some basic points you should know about the Spice deck to be able to debug or enhance the results In the appendix you can find an example for a Spice deck generated by PrimeTime At the beginning of the spice deck you will find the header that reads the model libraries a definiti
18. generated from This can be done in PrimeTime using a TCL script A r Y r 4 The first step validate your models and library When running a Spice simulation with a library for the first time it is helpful to take a step by step approach At first you should always verify that the Spice model library and the extracted netlists you have for your standard cells give you the same timing behavior as the timing library that is read by PrimeTime Although this sounds trivial there are severe differences that can occur here One example is the correct scale of the transistor sizes It is possible to define the unit for the dimensions of your transistors in the Spice setup So if the width of a transistor in the netlist is given with w 1 0 this could result in a transistor with a width of lum or Im depending on your scale setting Using the TCL scripting interface of PrimeTime comparing the timing in the library against the Spice simulation can be easily automated The script verify_cell_timing that you can find in the appendix can be used to create a small Verilog netlist instantiating a single cell to be tested It reads in this Verilog netlist and applies one set of boundary conditions For this test setup all possible timing paths are selected and Spice decks are generated These Spice decks are than simulated the simulation results are parsed and compared to the timing calculated in PrimeTime Using this script a single cell c
19. iming cells global link_path default_input_slope default_output_load read in all libraries in link_path if get_libs quiet wu foreach lib 1link path if string match db 1ib read db library S lib foreach cell cells Create verilog netlist set libcell create testcase for cell S cell tmp netlist v if 1ibcell 1 continue puts Investigating cell read design remove design all gt gt dev null read verilog tmp netlist v gt gt dev null link dev null Create a virtual reference clock and apply conatraints create clock period 10 0 name ref clock set input transition default input slope all inputs set load default output load all outputs set input delay clock ref clock 5 0 all inputs create real clock on clock inputs foreach in collection pin get lib pins of object 1libcell if get attribute Spin is clock pin true j set clock get attribute pin base name create clock period 10 0 Sclock set propagated clock clock foreach in collection path get timing path delay type max nworst 1000 to all outputs verify path timing path foreach in collection path 4 foreach cell HEHEHE HE HE HEHE EH EERE HE EEE EH EEE EE HE EEE EE EE EEE HE EEE EEE EE HE EEE FE EEE SH Create a testcase verilog file instanciating a single test cell P
20. mized for different simulators Prrr rrr GG S rrr SNB rrr rrr Gg Gg g baa ea rprrprrrrrgrgrggg exec your spice simulator b spice ckt gt amp spice result parse the simulation output set spice delay parse result file spice result print result print result Sstartpoint Sendpoint S spice delay HEPES FE E FE E E E FE EEE EEE EEE ERE ERE EEE EEE HEHE HERE HEH EEE HE HEHE HEE Parse the simulation results This may need to be changed for a different Spice simulator FE E E E HE E HE HE FE HE HE E E EERE E EEE EERE EERE EERE EEE EERE EEE EEE HERE HE EEE E EEE HEE HEH HERE proc parse_result_file file set FILE open file r set last line set spice delay 1 0 while gets SFILE line gt 0 if string match S last line in 3 scan line s s s s s fieldl field2 field3 field4 field5 i c if string match delay fieldl amp amp string match failed Sfieldl set spice delay expr fieldl 1 0e 9 set last line line TERRE EERE RE ER HEHE HE HEHE RE EN Format and print the result TERRE RARE HEH HE HE HEE EH HF proc print_result startpoint endpoint spice_delay close SFILE For flipflops substract 1 clk period for the event is triggered with the 2nd clk event if Sspice_delay gt 10 0 return expr Sspice_delay 10 return Sspice_delay RE TE FEAE HE EE EH
21. om the timing library For all interconnects between the cells the delay and edge degradation is calculated from the parasitic capacitances and resistances of the wires It is quite obvious that on the way from the golden reference the extracted Spice netlist to the calculated delays used for STA a number of approximations are taken that result in inaccurate results During timing characterization only a limited number of reference simulations can be done to acquire the delay model in the timing library For all operation conditions of the cells that don t exactly match the conditions of the reference simulation the table entries of the library need to be interpolated Also the algorithms for calculating the interconnect delay the signal edge degradation and the effective load on a driver do approximations and are proprietary to the tool vendor Therefore the actual accuracy of the calculated delays is difficult to estimate With the introduction of PrimeTime SI not only features for the analysis of crosstalk effects were added to the PrimeTime tool Also the command write spice deck was added that allows you to write out a netlist for a Spice simulation of selected timing paths The Spice netlist that is written out by this command is composed of the capacitances and resistances of interconnect wires and the spice netlists of all gates connected to this timing path While of course a Spice simulation of a complete chip is in most cases no
22. on of the supply voltages and the operating temperature and an include statement to read the Spice netlist containing the standard cells After that header section follows the timing path section This part of the Spice deck contains the instantiations of the standard cells and the models for the wires between the cells Of course the verification of the timing paths is most useful on a layouted design with an extracted netlist where detailed information on the interconnect is available However it is also possible to do a Spice simulation when PrimeTime works on Wire Load Models In this case PrimeTime will place a capacitance with the value from the statistical Wire Load Model at the driver pin and connect the driver to the receiver using two voltage sources as shown in Picture 1 With this approach all timing points of the path the driver pin the net and the receiver pin are available in the Spice simulation If your timing path contains nets with more than one receiver you will find that the generated spice deck not only instanciates the cells that are part of the timing path but all cells that are connected to the drivers of the path This is important to know because although these cells are only used to accurately model the load on the nets also their elements are simulated So if you want to do a Spice simulation on a netlist before clock tree insertion you might end up simulating hundreds or even thousands of flipflops all connect
23. rated at 1 5 volts Since the pad library contained scalers to adjust for different pad voltages the pad timing was accidentally calculated not for the 3 0 volt operating condition but for 1 5 volt All I O paths were calculated with about 2ns pessimistic timing 6 To the digital designer Many digital design engineers shy the difficult setup of a Spice simulation and the high runtime on the designs that they usually work on Therefore very few consider doing reference simulations with Spice However using the interface to Spice that PrimeTime provides allows you to create the whole setup for simulating only that fraction of the circuit you are interested in with very little effort The TCL script that is provided in the Appendix is not 1 700 1 400 1 100 trang velk 8 808 D 6 568 6 266 0 100 1 600 1 300 1 888 tran4 vittimeout CW 6 768 6 408 9 188 0 200 810 868m intended to be a complete solution for all types of Spice simulators and analysis details you may need But I hope it will serve as a starting point for setting up and automating your verification process To conclude I can only encourage you to spend the effort and validate your STA results with a Spice simulation Once you have set up the simulation it is easy to impress your colleges and your boss with some plots from the analog world to prove that your Static Timing Analysis matches the golden references and that you have really met
24. se of these variations with PVT that the only predictable reference for the timing of a chip are the Spice models It may sound bizarre but it is the Spice models and not the finished silicon that is the golden reference for the design of an ASIC Once a technology has been defined and validated it is the job of the fab or foundry to produce silicon that matches this reference and guarantee that the finished product will meet the specification In a standard cell library a timing model for each cell is generated To generate these timing models all active and passive components like transistors capacitances and resistances are extracted from the cell s geometry data These extracted netlists are usually different from the ideal netists that were used to design the standard cells In addition to the active elements that provide the functionality they contain all the parasitic elements resulting for example from the cell s internal wiring that have a strong influence on the performance and drive characteristic of the cell In a step called the timing characterization the extracted netlist is simulated in a number of environments like different input slopes and output loads for combinational gates The timing numbers and drive characteristics gathered in these simulation runs is stored in tables or in polynomial models that form the timing library When doing delay calculation for each cell the delay and transition time at the output is taken fr
25. t feasible simulating just a fragment of the whole design takes only a few seconds or minutes And since the netlist simulated here is the extracted netlist with all parasitic elements in the cell and the interconnect such a Spice simulation can be used as the golden reference to measure your STA results against The goal of such a Spice simulation can of course never be to fully verify a chip s timing But it can be a useful tool to validate that the timing library the calculated delays and the STA setup result in correct timing numbers and it can give the designer a feeling how accurate these results are compared to the golden reference 2 What do I need for timing validation The command in PrimeTime that is used to generate a netlist from a timing path for Spice simulation is write spice deck This command was added in the 2001 08 release of PrimeTime and is part of the Signal Integrity extension of the tool Therefore this feature requires a PrimeTime SI license and can not be used with the standard tool license Table 1 shows the most important arguments of the write spice deck command Probably the most important input for the Spice deck generation is a Timing Path object This object contains all the information on the path through the circuit for which the Spice deck shall be written out This Timing Path object can be generated using the PrimeTime command get timing paths that is very similar to the report timing command
26. th clock tree input voltage section rising timer l counter buf reg 3 ck gt falling ips rdata 3 Ck ck ck kk ck kk ck Ck ck kk Ck kk Ck kk kk ck kk ko kk Sk kk ko kc k ko KKK KKK vclk clk 0 pulse 0 1 35 11 2333ns 1 66667ns 1 66667ns 3 33333ns 10ns Kk ck Ck ck ck Ck ck ck kk KKK Ck Sk ck kk ck kk ck kk ck kk ko kk Sk kc k ko ko kc KK KKK ru Dk Kok ck Ck ck ck Ck ck Ck ck ck ck ck Ck Ck ck Ck ck ck ck ck ck ck ok ck ock ck ko ck ko ck kv kx Sk Mk Sk ko ko ko ko The side pin U16 d0 of cell U16 mux2_2 is set to low by sensitization vU16 d0 U16 d0 0 0 Dk Ok ck ck Ck ck ck Ck ck Ck ck ck 0k ck Ck ck Ck ck ck ck ck Ck ck ok kk ck ck ck ko Sk ko Sk kv Mk k ko ko ko ko The side pin U16 s10 of cell U16 mux2 2 is set to high by sensitization vU16 s10 U16 s10 0 1 35 Cosa transient analysis tran 0O 1ns 50ns end 7 2 TCL script to automatically compare the timing of library cells to Spice simulation some global variables set spice header home tobias spice header set spice netlist home tobias spice netlist set default input slope 1 0 set default output load 0 05 set supply voltage 1 62 EEEE EE E E E E E E E E E E E E E E E E E ERE ERE E REE EE EEE EEE EEE EEE EEE HEE HEE HEH HE HHH HH HH HH Compare the timing of the listed cells to Spice simulation EEEE E E E E E E E E E E E E E E E E E E E E E E EEE EEE EEE EEE EAE EEE EEE EGE HEHE HEH HEH HE HH HH HH proc verify_cell_t
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