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PowerPC™ Microprocessor Family: The Programmer`s Reference

1. Idux 31 D A B 53 0 Idx 31 D A B 21 0 50 D A d 51 Ifdux 31 D A B 631 0 31 B 599 0 Ifs 48 D A d Ifsu 49 D A d Ifsux 31 D A B 567 0 Ifsx 31 D A B 535 0 Iha 42 D A d Ihau 43 D A d Ihaux 31 D A B 375 0 31 B 343 0 Ihbrx 31 D A B 790 0 Ihz 40 D A d Ihzu 41 D A d Ihzux 31 D A B 311 0 Ihzx 31 D A B 279 0 Imw 3 46 D A d Iswi 31 D A NB 597 0 Iswx 31 D A B 533 0 58 D A ds 2 Iwarx 31 D A B 20 0 Iwaux 31 D A B 373 0 31 D A B 341 0 Iwbrx 31 D A B 534 0 Iwz 32 D A d Iwzu 33 D A d Iwzux 31 D A B 55 0 Iwzx 31 D A B 23 0 merf 19 00 erfS 00 00000 0 0 merfs 63 00 erfS 00 00000 64 0 PowerPC Microprocessor Family The Programmer s Reference Guide 47 Name 0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 merxr 31 00 00000 00000 512 0 mfcr 31 D 00000 00000 19 0 mffsx 63 D 00000 00000 583 Rc mfmsr 81 D 00000 00000 83 0 mfspr 2 31 D spr 339 0 mfsr 15 31 D 0 SR 00000 595 0 mfsrin 16 31 D 00000 B 659 0 mftb 31 D tbr 371 0 31 S 0 CRM 0 144 0 mt sb0x 63 crbD 00000 00000 70 Rc mtfsb1x 63 crbD 00000 00000 38 Rc mt sfx 63 0 FM 0 B 711 Rc mt sfix 63 00 00000 IMM 0 134 Rc mtmsr 31 S 00000 00000 146 0 mtspr 31 S spr
2. Figure 4 XER Register Table 5 provides bit setting information for XER Table 5 XER Bit Definitions Bit s Name Description 0 Summary overflow The summary overflow bit SO is set whenever an instruction except mtspr sets the overflow bit OV Once set the SO bit remains set until it is cleared by an mtspr instruction specifying the XER or an merxr instruction It is not altered by compare instructions nor by other instructions except mtspr to the XER and merxr that cannot overflow Executing an mtspr instruction to the XER supplying the values zero for SO and one for OV causes SO to be cleared and OV to be set 1 Overflow The overflow bit OV is set to indicate that an overflow has occurred during execution of an instruction Add subtract from and negate instructions having OE 1 set the OV bit if the carry out of the msb is not equal to the carry out of the msb 1 and clear it otherwise Multiply low and divide instructions having OE 1 set the OV bit if the result cannot be represented in 64 bits mulld divd divdu or in 32 bits mullw divw divwu and clear it otherwise The OV bit is not altered by compare instructions that cannot overflow except mtspr to the XER and merxr 8 PowerPC Microprocessor Family The Programmer s Reference Guide Table 5 XER Bit Definitions Continued Bit s Description 2 Carry The carry bit CA is set during execution of the follo
3. sldx 01 S A B 0000011011 Rc 01 S A B 0000011100 Rc 01 0 B 0000100000 0 subfx 01 D A B 0000101000 Rc Idux 01 D A B 0000110101 0 dcbst 01 00000 A B 0000110110 0 01 D A B 0000110111 0 entizdx 01 S A 00000 0000111010 Rc andcx 01 S A B 0000111100 Rc td 01 TO A B 0001000100 0 muldx 01 D A B 0 0001001001 Rc mulhwx 01 D A B 0 0001001011 Rc mfmsr 01 D 00000 00000 0001010011 0 Idax 01 D A B 0001010100 0 01 00000 A B 0001010110 0 Ibzx 01 D A B 0001010111 0 negx 01 D A 00000 0001101000 Rc lbzux 01 0001110111 0 01 S A B 0001111100 Rc subfex 01 B 0010001000 Rc addex 01 D A B 0010001010 01 S 0 CRM 0 0010010000 0 mtmsr 01 S 00000 00000 0010010010 0 stdx 01 S A B 0010010101 0 stwex 01 S A B 0010010110 1 stwx 01 S A B 0010010111 0 stdux 01 S A B 0010110101 0 stwux 01 S A B 0010110111 0 subfzex 01 00000 0011001000 Rc addzex 01 D A 00000 0011001010 Rc mtsr 8 01 S 0 SR 00000 0011010010 0 4 01 S B 0011010110 1 stbx 01 S B 0011010111 0 PowerPC Microprocessor Family The Programmer s Reference Guide 53 Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 subfmex 01 D A 00000 0011101000 Rc mulld 01 D A
4. fnmaddsx 1011 D A B C 11111 std 1110 S A ds 0 stdu 1110 S A ds 1 fcmpu 1111 00 B 0000000000 0 frspx 1111 D 00000 B 0000001100 fctiwx 1111 D 00000 B 0000001110 fctiwzx 1111 D 00000 B 0000001111 Rc fdivx 1111 D A B 00000 10010 fsubx 1111 D A B 00000 10100 Re faddx 1111 D A B 00000 10101 Rc fsqrtx 5 1111 D 00000 B 00000 10110 fselx 1111 D A B C 10111 fmulx 1111 D A 00000 C 11001 frsqrtex 5 1111 D 00000 B 00000 11010 fmsubx 1111 D A B C 11100 fmaddx 1111 D A B C 11101 fnmsubx 1111 D A B C 11110 fnmaddx 1111 D A B C 11111 fcmpo 1111 00 A B 0000100000 0 mtfsb1x 1111 crbD 00000 00000 0000100110 fnegx 1111 D 00000 B 0000101000 mcr s 1111 00 crfS 00 00000 0001000000 0 mtfsbOx 1111 crbD 00000 00000 0001000110 fmrx 1111 D 00000 B 0001001000 mtfsfix 1111 00 00000 IMM 0 0010000110 fnabsx 1111 D 00000 B 0010001000 PowerPC Microprocessor Family The Programmer s Reference Guide 57 Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fabsx D 00000 B 0100001000 Rc mffsx 111111 D 00000 00000 1001000111 Re mtfsfx 111111 0 FM 0 B 1011000111 Re fetid 5 111111 D 00000 B 1100101110 Re fctidzx 111111 D 00000 B 1100101111 Rc fcfidx 111111 D 00000 B 1101001110 Rc 1 2 3 64 bit instruction 5 Optional instruction
5. Reserved HTABORG 0000000 HTABMASK 0 15 16 22 23 31 Figure 33 SDR1 Register Format 32 Bit Implementations Table 29 SDR1 Register Bit Settings 32 Bit Implementations Bits Name Description HTABORG Physical base address of page table 16 22 I Reserved 23 31 HTABMASK Mask for page table address The HTABORG field in SDR1 contains the high order 16 bits of the 32 bit physical address of the page table Therefore the beginning of the page table lies on a 216 byte 64 Kbyte boundary at a minimum As with 64 bit implementations if the processor does not support 32 bits of physical address software should write zeroes to those unsupported bits in the HTABORG field as the implementation treats them as reserved Otherwise a machine check exception can occur A page table can be any size 2 bytes where 16 n 25 The field in SDRI contains a mask value that determines how many bits from the output of the hashing function are used as the page table index This mask must be of the form 0500 011 1 a string of 0 bits followed by a string of 1 bits As the table size increases more bits are used from the output of the hashing function to index into the table The 1 bits in HTABMASK determine how many additional bits beyond the minimum of 10 from the hash are used in the index the HTABORG field must have the same number of lower order bits equal to 0 as the
6. field has lower order bits equal to 1 PowerPC Microprocessor Family The Programmer s Reference Guide 39 Part 3 Exception Vectors Exceptions and conditions that cause them are listed in Table 30 Table 30 Exceptions and Conditions Exception Vector Offset Causing Conditions Type hex unavailable floating point instruction including floating point load store and move instructions when the floating point available bit is cleared MSR FP 0 Reserved 00000 System reset 00100 The causes of system reset exceptions are implementation dependent If the conditions that cause the exception also cause the processor state to be corrupted such that the contents of SRRO and SRR1 are no longer valid or such that other processor resources are so corrupted that the processor cannot reliably resume execution the copy of the RI bit copied from the MSR to SRR1 is cleared Machine check 00200 The causes for machine check exceptions are implementation dependent but typically these causes are related to conditions such as bus parity errors or attempting to access an invalid physical address Typically these exceptions are triggered by an input signal to the processor Note that not all processors provide the same level of error checking The machine check exception is disabled when MSR ME 0 If a machine check exception condition exists and the ME bit is cleared the processor goes into the checkstop stat
7. 1 Instruction address translation is enabled 59 Data address translation 0 Data address translation is disabled 1 Data address translation is enabled 2 28 29 Reserved Full function Recoverable exception for system reset and machine check exceptions 0 Exception is recoverable 1 Exception is recoverable 3 Little endian mode enable 0 The processor runs in big endian mode 1 The processor runs in little endian mode 17 PR 18 FP 19 ME 20 FEO 21 SE 22 BE 23 FE1 24 25 26 IR 27 DR 30 RI 1 LE PowerPC Microprocessor Family The Programmer s Reference Guide 17 The floating point exception mode bits are interpreted as shown in Table 13 Note that these bits can be logically ORed so that if either is set the processor operates in precise mode Table 13 Floating Point Exception Mode Bits Floating point exceptions disabled 1 Floating point imprecise nonrecoverable 0 Floating point imprecise recoverable ERES Floating point precise mode Table 14 indicates the initial state of the MSR Table 14 State of MSR at Power Up 64 Bit 32 Bit Description Description Unspecified Unspecified o 1 Unspecified Unspecified U D m m m a N N e a N T m 1 0 o mj rm 0 0 e Unspecified Unspecified Etro e 18 Power
8. CRM RA RB RT RS rB rD rS respectively SI U IMM Ul UIMM 1 Hf Hl 0 0 shaded PowerPC Microprocessor Family The Programmer s Reference Guide Part 1 Register Summary This section describes the register organization defined by the three levels of the PowerPC architecture user instruction set architecture UISA virtual environment architecture VEA and operating environment architecture OEA The PowerPC architecture defines register to register operations for all computational instructions Source data for these instructions are accessed from the on chip registers or are provided as immediate values embedded in the opcode The three register instruction format allows specification of a target register distinct from the two source registers thus preserving the original data for use by other instructions and reducing the number of instructions required for certain operations Data is transferred between memory and registers with explicit load and store instructions only Figure 1 shows a graphic representation of the entire PowerPC register set The number to the right of the register name indicates the number that is used in the syntax of the instruction operands to access the register for example the number used to access the XER is SPR1 Many of the SPRs can be accessed only by supervisor level instructions any attempt to access these SPRs with user level instructions results in a supervisor level
9. This document was created with FrameMaker 4 0 4 Introduction The primary objective of this document is to provide a concise method by which system software and hardware developers and application programmers may more readily provide software that is compatible across the family of PowerPC processors and other devices A more detailed account of the following topics or the PowerPC architecture in general may be obtained from the PowerPC Microprocessor Family The Programming Environments referred to as The Programming Environments Manual The PowerPC Architecture A Specification for a New Family of RISC Processors defines the architecture from the perspective of the three programming environments and remains the defining document for the PowerPC architecture This document is divided into four parts Part 1 Register Summary on page 4 provides a brief overview of the PowerPC register set including a programming model and quick reference guides for both 32 and 64 bit registers Part 2 Memory Control Model on page 28 provides a brief outline of the page table entry and segment table entry for both 32 and 64 bit implementations Part 3 Exception Vectors on page 40 provides a quick reference for exception types and the conditions that cause them e Part 4 PowerPC Instruction Set on page 41 provides detailed information on the instruction field summary including syntax and notation conventions Also
10. SRR1 Figure 20 Machine Status Save Restore Register 1 SRR1 On 64 bit implementations when an exception occurs bits 33 36 and 42 47 of SRRI are loaded with exception specific information and bits 0 32 37 41 and 48 63 of MSR placed into the corresponding bit positions of SRRI 24 PowerPC Microprocessor Family The Programmer s Reference Guide For 32 bit implementations when an exception occurs bits 1 4 and 10 15 of SRRI are loaded with exception specific information and bits 0 5 9 and 16 31 of MSR are placed into the corresponding bit positions of SRR1 Note that in some implementations every instruction fetch when MSR IR 1 and every instruction execution requiring address translation when MSR DR 1 may modify SRRI 1 19 Time Base Facility TB The time base TB shown in Figure 21 is a 64 bit structure that contains a 64 bit unsigned integer that is incremented periodically Each increment adds 1 to the low order bit bit 63 The frequency at which the counter is incremented is implementation dependent TBU Upper 32 bits of time base TBL Lower 32 bits of time base 0 310 31 Figure 21 Time Base TB The TB increments until its value becomes OXFFFF FFFF FFFF FFFF 284 1 At the next increment its value becomes 0x0000_0000_0000_0000 Note that there is no explicit indication that this has occurred that is no exception is generated The period of the time base
11. description of SDR1 1 12 Address Space Register ASR The address space register ASR is a 64 bit SPR that holds 0 51 of the segment table s physical address The segment table is the segment descriptor mechanism for 64 bit implementations For more detailed information about the ASR refer to Section 2 2 1 1 Address Space Register ASR 1 13 Segment Registers SRs Segment registers are used in page and direct store segment address translations Refer to Section 2 2 Segment Descriptor Definitions for information on segment registers 1 14 Data Address Register DAR The DAR is a 64 bit register in 64 bit implementations and a 32 bit register in 32 bit implementations The DAR is shown in Figure 16 DAR 0 63 Figure 16 Data Address Register DAR The effective address generated by a memory access instruction is placed in the DAR if the access causes an exception for example an alignment exception If the exception occurs in a 64 bit implementation operating in 32 bit mode the high order 32 bits of the DAR are cleared 22 PowerPC Microprocessor Family The Programmer s Reference Guide 1 15 SPRGO SPRG3 SPRGO SPRG3 are 64 bit or 32 bit registers depending on the type of PowerPC microprocessor They are provided for general operating system use such as performing a fast state save or for supporting multiprocessor implementations The formats of SPRGO through are shown in Figure 17
12. 64 Bit i 0 SF Sixty four bit mode 0 The 64 bit processor runs 32 bit mode 1 64 bit processor runs in 64 bit mode Note that this is the default setting 1 32 Reserved Full function 33 36 ENEN Reserved Partial function 37 41 HOM Reserved Full function 42 44 10 12 Reserved Partial function 45 13 Power management enable 0 Power management disabled normal operation mode 1 Power management enabled reduced power mode Note Power management functions are implementation dependent If the function is not implemented this bit is treated as reserved Reserved Implementation specific 15 Exception little endian mode When an exception occurs this bit is copied into MSR LE to select the endian mode for the context established by the exception External interrupt enable 0 While the bit is cleared the processor delays recognition of external interrupts and decrementer exception conditions 1 The processor is enabled to take an external interrupt or the decrementer exception 16 PowerPC Microprocessor Family The Programmer s Reference Guide Table 12 MSR Bit Settings Continued Description Privilege level 0 The processor can execute both user and supervisor level instructions 1 The processor can only execute user level instructions Floating point available 0 The processor prevents dispatch of floating point instructions including floating point loads stores and moves 1 Th
13. EAR register is provided to support the External Control In Word Indexed eciwx and External Control Out Word Indexed ecowx instructions Access to the EAR is supervisor level thus the operating system can determine which tasks are allowed to issue external access instructions and when they are allowed to do so The bit settings for the EAR are described in Table 19 PowerPC Microprocessor Family The Programmer s Reference Guide 27 The data access of eciwx and ecowx is performed as though the memory access mode bits WIMG were 0101 For example if the external control facility is used to support a graphics adapter the ecowx instruction could be used to send the translated physical address of a buffer containing graphics data to the graphics device The eciwx instruction could be used to load status information from the graphics adapter Table 19 External Access Register EAR Bit Settings Bit Name Description 0 E Enable bit 1 Enabled 0 Disabled If this bit is set the eciwx and ecowx instructions can perform the specified external operation If the bit is cleared an eciwx or ecowx instruction causes a DSI exception 1 25 Reserved 26 31 RID Resource ID This register can also be accessed by using the mtspr and mfspr instructions Part 2 Memory Control Model Memory in the PowerPC OEA is divided into 256 Mbyte segments This segmented memory model provides a way to map 4 Kbyte pages of effective address
14. FPRO IBAT2L SPR 533 DBAT2L SPR 541 1 IBAT3U SPR 534 DBAT3U SPR 542 IBAT3L SPR 535 DBAT3L SPR 543 2 SDR1 Register Segment Registers 1 5081 SPR 25 SRO Condition Register SRI cR Address Space Register e ASR SPR 280 Floating Point Status SRIS and Control Register FPSCR Exception Handling Registers Data Address Register DSISR Register XER Register DAR SPR 19 SER Sedi DSISR SPR 18 SPRG Registers Save and Restore Registers Link Register SERGO 272 5 SPRG1 SPR 273 SHRO REGI LR SPR8 SPRG2 SEH274 SRR1 SPR 27 Count Register SERGS CTR SPR9 Miscellaneous Registers E E Time Base Facility Data Address Time Base Facility Write Only Breakpoint Register Read Only TBL SPR 284 DABR SPR 1013 TBL TBR 268 TBU SPR 285 TBU TBR 269 External Address Register niet EAR SPR 282 DEC SPR22 E 1 These registers are in 32 bit implementations only These registers are in 64 bit implementations only 3 These registers are optional in the PowerPC architecture Figure 1 PowerPC Programming Model Registers PowerPC Microprocessor Family The Programmer s Reference Guide Table 3 provides a quick method by which to reference the SPR and TBR numbers and bit fields for all 32 bit PowerPC registers Note that reserved bits are shaded Number SPR 1 SPR 8 SPR9 SPR 18 SPR 19 SPR 22 SPR 25 SPR 26 SPR 27 SPR 272 SPR 282 SPR 284 SPR 285 SPR 28
15. Register LR The link register LR is a 64 bit register in 64 bit implementations and a 32 bit register in 32 bit implementations The LR supplies the branch target address for the Branch Conditional to Link Register belrx instruction and can be used to hold the logical address of the instruction that follows a branch and link instruction The format of LR is shown in Figure 7 Branch Address 0 63 31 Figure 7 Link Register LR Note that although the two least significant bits can accept any values written to them they are ignored when the LR is used as an address The link register can be accessed by the mtspr and mfspr instructions using SPR8 Fetching instructions along the target path loaded by an mtspr instruction is possible provided the link register is loaded sufficiently ahead of the branch instruction It is possible for a PowerPC microprocessor to fetch along a target path loaded by a branch and link instruction Both conditional and unconditional branch instructions include the option of placing the effective address of the instruction following the branch instruction in the LR 14 PowerPC Microprocessor Family The Programmer s Reference Guide 1 7 Count Register CTR The count register CTR is a 64 bit register in 64 bit implementations and a 32 bit register in 32 bit implementations The CTR can hold a loop count that can be decremented during execution of branch instructions that contain an appro
16. and CR bit 3 receives a copy of the summary overflow bit XER SO The result as an unsigned quantity or a bit string can be deduced from the EQ bit For floating point instructions CR bits 4 7 are set to reflect floating point exception floating point enabled exception floating point invalid operation exception and floating point overflow exception Note that the architecture specification refers to exceptions also as interrupts rD 6 10 Field used to specify a GPR to be used as a destination rS 6 10 Field used to specify a GPR to be used as a source SH 16 20 Field used to specify a shift amount SIMM 16 31 Immediate field used to specify a 16 bit signed integer SR 12 15 Field used to specify one of the 16 segment registers 32 bit implementations only Field used to specify the conditions on which to trap UIMM 16 31 Immediate field used to specify a 16 bit unsigned integer XO 21 29 Extended opcode field 21 30 22 30 Bits 21 29 27 29 27 30 30 31 pertain to 64 bit implementations only 26 30 27 29 27 30 or 30 31 Split fields mb me sh spr and tbr are described in Table 32 Table 32 Split Field Notation and Conventions ER 12 1 Field used in rotate instructions to specify the first 1 bit a 64 bit mask 32 bits 32 bit implementations This field is defined in 64 bit implementations only Field used in rotate instruction
17. included is the entire PowerPC instruction set sorted by mnemonic and opcode In this document the term 60x is used to denote a 32 bit microprocessor from the PowerPC architecture family 60x processors implement the PowerPC architecture as it is specified for 32 bit addressing which provides 32 bit effective logical addresses integer data types of 8 16 and 32 bits and floating point data types of 32 and 64 bits single precision and double precision Table 1 contains acronyms and abbreviations that are used in this document Note that the meanings for some acronyms such as SDR1 and are historical and the words for which an acronym stands may not be intuitively obvious PowerPC Microprocessor Family The Programmer s Reference Guide 1 This document was created with FrameMaker 4 0 4 Term ASR Table 1 Acronyms and Abbreviated Terms Meaning Address space register BAT BUID CR CTR Block address translation Bus unit ID Condition register Count register DAR DBAT Data address register Data BAT EA DEC Decrementer register DSISR Register used for determining the source of a DSI exception DTLB Data translation lookaside buffer Effective address EAR External access register FPR Floating point register FPSCR Floating point status and control register GPR General purpose register IBAT IEEE Instruction BAT Institute of Electrical and Electronics Engine
18. negative FL or lt 17 oating point greater than or positive FG or gt 18 oating point equal or zero FE or 19 oating point unordered or NaN FU or These are not sticky bits mem 21 VXSOFT Floating point invalid operation exception for software request This is a sticky bit This bit can be altered only by the merfs mtfsfi mtfsf mtfsb0 or mtfsb1 instructions VXSQRT Floating point invalid operation exception for invalid square root This is a sticky bit Floating point invalid operation exception for invalid integer convert This is a sticky bit Floating point invalid operation exception enable This is not a sticky bit IEEE floating point overflow exception enable This is not a sticky bit IEEE floating point underflow exception enable This is not a sticky bit IEEE floating point zero divide exception enable This is not a sticky bit Floating point inexact exception enable This is not a sticky bit Floating point non IEEE mode If this bit is set results need not conform with IEEE standards and the other FPSCR bits may have meanings other than those described here If the bit is set and if all implementation specific requirements are met and if an IEEE conforming result of a floating point operation would be a denormalized number the result produced is zero retaining the sign of the denormalized number Any other effects associated with setting this bit are descri
19. than the complete page index field because at least ten of the low order bits of the page index are used in the hash function to select a PTEG address PTEG addresses define the location of a PTE Therefore these ten lower order bits are not repeated in the PTEs of that PTEG 2 3 3 SDR1 Register Definitions The SDRI register contains the control information for the page table structure in that it defines the highest order bits for the physical base address of the page table and it defines the size of the table The format of the SDRI register differs for 64 bit and 32 bit implementations as shown below PowerPC Microprocessor Family The Programmer s Reference Guide 37 2 3 3 4 5081 Register Definition for 64 Bit Implementations The format of the SDR1 register for a 64 bit implementation is shown in Figure 32 and the bit settings are described in Table 28 Reserved HTABORG 0000000000000 HTABSIZE 0 45 46 58 59 63 Figure 32 SDR1 Register Format 64 Bit Implementations Table 28 SDR1 Register Bit Settings 64 Bit Implementations Bits Name Description 0 45 HTABORG Physical base address of page table 46 58 I Reserved 59 63 HTABSIZE Encoded size of page table used to generate mask The HTABORG field in SDR1 contains the high order 46 bits of the 64 bit physical address of the page table Therefore the beginning of the page table lies on a 218 byte 256 Kbyte boundary
20. the PTE with the segment information The R and C bits maintain history information for the page The WIMG bits define the memory cache control mode for accesses to the page e The PP bits define the remaining access protection constraints for the page Conceptually the page table in memory must be searched to translate the address of every reference 2 3 1 PTE Format for 64 Bit Implementations In 64 bit implementations each PTE is a 128 bit entity two double words that maps a virtual page number VPN to a physical page number RPN Information in the PTE is used in the page table search process to determine a page table hit and provides input to PowerPC Microprocessor Family The Programmer s Reference Guide 35 the memory protection mechanism Figure 30 shows the format of the two double words that comprise a PTE for 64 bit implementations Reserved 0 51 52 56 57 61 62 63 VSID API 00000 RPN 000 0 PP 0 51 52 54 55 56 57 60 61 62 63 Figure 30 Page Table Entry Format 64 Bit Implementations Table 26 lists the corresponding bit definitions for each double word in a PTE as defined above Table 26 PTE Bit Definitions 64 Bit Implementations Double Word Bit Name Description 0 0 51 VSID Virtual segment ID corresponds to the high order bits of the virtual page number VPN 52 56 API Abbreviated page index we 62 H Hash function i
21. 0 fctidx 5 63 D 00000 B 814 Rc fctidzx 63 D 00000 B 815 Rc fctiwx 63 D 00000 B 14 Rc PowerPC Microprocessor Family The Programmer s Reference Guide 45 Name 0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fctiwzx 63 D 00000 B 15 Rc fdivx 63 D A B 00000 18 Rc fdivsx 59 D A B 00000 18 Rc fmaddx 63 D A B 29 Rc fmaddsx 59 D A B e 29 Rc fmrx 63 D 00000 B 72 Rc fmsubx 63 D A B 28 Rc fmsubsx 59 D A B C 28 fmulx 63 D A 00000 C 25 Rc fmulsx 59 D A 00000 C 25 Rc fnabsx 63 D 00000 B 136 Rc fnegx 63 D 00000 B 40 Rc fnmaddx 63 D A B C 31 Rc fnmaddsx 59 D A B C 31 fnmsubx 63 D A B C 30 fnmsubsx 59 D A B C 30 fresx 59 D 00000 B 00000 24 Rc frspx 63 D 00000 B 12 Rc frsqrtex 63 D 00000 B 00000 26 Rc fselx 63 D A B C 23 5 63 00000 B 00000 22 Rc fsqrtsx 5 59 D 00000 B 00000 22 Rc fsubx 63 D A B 00000 20 Rc fsubsx 59 D A B 00000 20 Rc icbi 31 00000 A B 982 0 isync 19 00000 00000 00000 150 0 Ibz 34 D A d Ibzu 35 D A d Ibzux 31 D A B 119 0 Ibzx 31 D A B 87 0 ld 4 58 D A ds 0 Idarx 5 31 D A B 84 0 Idu 4 58 D A ds 1 46 PowerPC Microprocessor Family The Programmer s Reference Guide Name 0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
22. 100001 Ibz 100010 100011 stw 100100 stwu 100101 stb 100110 stbu 100111 Ihz 101000 Ihzu 101001 101010 Ihau 101011 sth 101100 sthu 101101 Imw 101110 stmw 3 101111 Ifs 110000 Ifsu 110001 110010 Ifdu 110011 st s 110100 stfsu 110101 stfd 110110 o o amp amp stfdu 110111 gt gt gt gt P gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt gt UID 010 0 0 0 0 AN VU UO OU 01 NI MN MN 111010 ds 00 Idu 111010 ds 01 111010 ds 10 fdivsx 111011 B 00000 10010 fsubsx 111011 B 00000 10100 56 PowerPC Microprocessor Family The Programmer s Reference Guide Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 faddsx 1011 D A B 00000 10101 Re fsqrtsx 5 1011 D 00000 B 00000 10110 Re fresx 1011 D 00000 B 00000 11000 fmulsx 1011 D A 00000 C 11001 Rc fmsubsx 1011 D A B C 11100 fmaddsx 1011 D A B C 11101 fnmsubsx 1011 D A B C 11110
23. 10011 crbD crbA crbB 0011100001 0 crand 010011 crbD crbA crbB 0100000001 0 creqv 010011 crbD crbA crbB 0100100001 0 010011 crbD crbA crbB 0110100001 0 cror 010011 crbD crbA crbB 0111000001 0 bectrx 010011 BO 00000 1000010000 LK riwimix 010100 S A SH MB ME Rc rlwinmx 010101 5 SH MB ME Rc riwnmx 010111 S A B MB ME Rc 011000 S A UIMM oris 011001 S A UIMM 011010 S A UIMM 011011 S A UIMM and 011100 S A UIMM andis 011101 S A UIMM 011110 S A sh mb 000 sh Rc ridirx 011110 S A sh me 001 sh Rc ridiex 011110 S A sh mb 010 sh Rc rldimx 011110 S A sh mb 011 sh Rc 4 011110 S A B mb 01000 ridcrx 011110 S A B me 01001 011111 B 0000000000 0 tw 011111 TO A B 0000000100 0 subfcx 011111 D A B 0000001000 Rc mulhdux 011111 D A B 0 0000001001 Rc addcx 011111 D A B 0000001010 Rc mulwux 011111 D A B 0 0000001011 Rc 011111 D 00000 00000 0000010011 0 011111 B 0000010100 0 Idx 011111 D A B 0000010101 0 Iwzx 011111 D A B 0000010111 0 slwx 011111 S A B 0000011000 Rc cntizwx 011111 S A 00000 0000011010 Rc 52 PowerPC Microprocessor Family The Programmer s Reference Guide Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
24. 1110010 0 merr 011111 00 00000 00000 1000000000 0 Iswx 011111 D A B 1000010101 0 Iwbrx 011111 D A B 1000010110 0 011111 B 1000010111 0 011111 S A B 1000011000 Rc srdx 011111 S A B 1000011011 Rc tbsync 011111 00000 00000 00000 1000110110 0 011111 B 1000110111 0 m sr 011111 D 0 SR 00000 1001010011 0 Iswi 011111 D A NB 1001010101 0 011111 00000 00000 00000 1001010110 0 011111 D A B 1001010111 0 Kfdux 011111 D A B 1001110111 0 011111 D 00000 B 1010010011 0 stswx 011111 S A B 1010010101 0 stwbrx 011111 S A B 1010010110 0 stfsx 011111 S A B 1010010111 0 011111 S A B 1010110111 0 stswi 011111 S A NB 1011010101 0 stidx 011111 S A B 1011010111 0 sttdux 011111 S A B 1011110111 0 Ihx 011111 D A B 1100010110 0 srawx 011111 S A B 1100011000 Rc sradx 011111 S A B 1100011010 srawix 011111 S A SH 1100111000 Rc eieio 011111 00000 00000 00000 1101010110 0 sthbrx 011111 S A B 1110010110 0 exshx 011111 S A 00000 1110011010 Rc exsbx 011111 S A 00000 1110111010 PowerPC Microprocessor Family The Programmer s Reference Guide 55 Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 icbi 011111 00000 A B 1111010110 0 stfiwx 5 011111 S B 1111010111 0 extsw 011111 S 00000 1111011010 Rc dcbz 011111 00000 B 1111110110 0 Iwz 100000 D d Iwzu
25. 32 bit instruction on Supervisor level ins ruction Supervisor and user level instruction Load and store string or multiple instruction 58 PowerPC Microprocessor Family The Programmer s Reference Guide Motorola Inc 1995 Portions hereof International Business Machines Corp 1991 1995 All rights reserved This document contains information on a new product under development by Motorola and IBM Motorola and IBM reserve the right to change or discontinue this product without notice Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors There are no express or implied copyright or patent licenses granted hereunder by Motorola or IBM to design modify the design of or fabricate circuits based on the information in this document The PowerPC 60x microprocessors embody the intellectual property of Motorola and of IBM However neither Motorola nor IBM assumes any responsibility or liability as to any aspects of the performance operation or other attributes of the microprocessor as marketed by the other party or by any third party Neither Motorola nor IBM is to be considered an agent or representative of the other and neither has assumed created or granted hereby any right or authority to the other or to any third party to assume or create any express or implied obligations on its behalf Information such as data sheets as well as sales terms and c
26. 467 0 mtsr 16 31 S 0 SR 00000 210 0 mtsrin 16 31 S 00000 B 242 0 mulhdx 31 D A B 0 73 mulhdux 31 D A B 0 9 Rc mulhwx 31 D A B 0 75 Rc mulhwux 31 D A B 0 11 Rc 31 D A B 233 Rc mulli 7 D A SIMM mullwx 31 D A B 235 31 S A B 476 Rc negx 31 D A 00000 104 Rc norx 31 S A B 124 Rc orx 31 S A B 444 Rc orcx 31 S A B 412 Rc ori 24 S A UIMM oris 25 S A UIMM 19 00000 00000 00000 50 0 ridelx 30 S A B mb 8 48 PowerPC Microprocessor Family The Programmer s Reference Guide Name 0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 5 30 S A B me 9 Rc ridicx 30 S A sh mb 2 sh Rc ridiclx 5 30 S A sh mb sh Re ridicrx 30 S A sh me 1 sh Rc ridimix 5 30 S A sh mb 3 sh Re rlwimix 20 S A SH MB ME Rc riwinmx 21 S A SH MB ME Rc rlwnmx 23 S A B MB ME Rc sc 17 00000 00000 00000000000000 110 slbia 145 31 00000 00000 00000 498 0 slbie 195 31 00000 00000 B 434 0 sldx 31 S A B 27 Rc slwx 31 S A B 24 Rc sradx 31 S A B 794 Rc sradix 31 S A sh 413 sh Rc srawx 31 S A B 792 Rc srawix 81 S A SH 824 Rc srdx 31 S A B 539 Rc srwx 31 5 B 536 stb 38 S A d stbu 39 S A d stbux 31 S A B 247 0 stbx 31 S A B 215 0 std 62 S A ds 0 stdcx 4 31 S A B 214 1 stdu 62 S A d
27. 7 SPR 528 SPR 529 SPR 1013 TBR 268 TBR 269 Number Table 3 Quick Reference Guide 3 2 Bit Registers 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1511618 19 20 21 22 23 24 25 26 27 28 29 GPRn CRO CR1 CR2 CR4 CR5 CR6 CR7 For the FPSCR bits refer to 1 4 Floating Point Status and Control Register FPSCR on page 9 0000000000000 ILE FE 0 RIJLE T Ks Kp N 0000 VSID T Ks Kp BUID Controller Specific Information 50 0000000000000000000000 Byte Count Branch Address CTR DSISR DAR DEC HTABORG 0000000 HTABMASK SRRO 00 SRR1 SPRGn E 0000000000000000000000000 RID TB L TBU Version Revision BEPI 0000 BL Vs Vp BRPN 0000000 000 WIMG oj PP DAB BT pw DR TB L TBU 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Notes 1 For all SPR numbers refer to Figure 1 2 Write Only 3 Read Only Nama GPRn CR FPSCR MSR SRn SRn XER LR CTR DSISR DAR DEC SDR1 SRRO SRR1 SPRGn EAR TB L TBU PVR XBATnU XBATnL DABR TB L 2 TBU 2 31 PowerPC Microprocessor Family The Programmer s Reference Guide Number SPR8 SPR9 SPR 19 SPR 25 SPR 26 SPR 27 SPR 272 SPR 280 SPR 528 SPR 529 SPR 101
28. 9 S A UIMM bx 18 LI AALK bcx 16 BO BI BD AALK bectrx 19 BO BI 00000 528 LK belrx 19 BO BI 00000 16 LK cmp 31 A B 0 0 cmpi 11 011 A SIMM cmpl 31 011 A B 32 0 cmpli 10 O L A UIMM cntlzdx 4 31 S A 00000 58 Rc cntlzwx 31 5 00000 26 Rc crand 19 crbD crbA crbB 257 0 44 PowerPC Microprocessor Family The Programmer s Reference Guide This document was created with FrameMaker 4 0 4 Name 0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 crandc 19 crbD crbA crbB 129 0 creqv 19 crbD crbA crbB 289 0 crnand 19 crbD crbA crbB 225 0 crnor 19 crbD crbA crbB 33 0 cror 19 crbD crbA crbB 449 0 crorc 19 crbD crbA crbB 417 0 crxor 19 crbD crbA crbB 193 0 dcbf 31 00000 A B 86 0 debi 31 00000 B 470 0 dcbst 31 00000 A B 54 0 dcbt 31 00000 A B 278 0 dcbtst 31 00000 A B 246 0 dcbz 31 00000 A B 1014 0 divdx 31 D A B 489 divdux 5 31 D A B 457 divwx 31 D A B 491 divwux 31 D A B 459 eciwx 31 D A B 310 0 ecowx 31 S A B 438 0 eieio 31 00000 00000 00000 854 0 eqvx 31 5 B 284 extsbx 31 S A 00000 954 Rc extshx 31 S A 00000 922 Rc extswx 5 31 S A 00000 986 Rc fabsx 63 D 00000 B 264 Rc faddx 63 D A B 00000 21 Rc faddsx 59 D A B 00000 21 Rc fcfidx 63 D 00000 B 846 Rc fcmpo 63 crfD 00 A B 32 0 fcmpu 63 00 B 0
29. B OE 0011101001 Rc addmex 01 D A 00000 0011101010 Rc mullwx 01 B OE 0011101011 Rc 16 01 S 00000 B 0011110010 0 dcbtst 01 00000 A B 0011110110 0 01 S A B 0011110111 0 addx 01 D A B 0100001010 dcbt 01 00000 B 0100010110 0 Inzx 01 D A B 0100010111 0 01 S A B 0100011100 Rc 15 01 00000 00000 B 0100110010 0 eciwx 01 D A B 0100110110 0 Ihzux 01 D A B 0100110111 0 xorx 01 S A B 0100111100 Rc m spr 01 D spr 0101010011 0 Iwax4 01 D A B 0101010101 0 lhax 01 D A B 0101010111 0 tibia 01 00000 00000 00000 0101110010 0 mftb 01 D tbr 0101110011 0 Iwaux 01 D A B 0101110101 0 lhaux 01 D A B 0101110111 0 sthx 01 S A B 0110010111 0 01 S A B 0110011100 Rc sradix 01 S A sh 1100111011 sh Rc slbie 145 01 00000 00000 B 0110110010 0 01 S A B 0110110110 0 01 S A B 0110110111 0 01 S A B 0110111100 Rc divdux 01 D A B OE 0111001001 Rc divwux 01 D A B OE 0111001011 Rc mtspr 01 S spr 0111010011 0 01 00000 A B 0111010110 0 54 PowerPC Microprocessor Family The Programmer s Reference Guide Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 011111 S A B 0111011100 Rc divdx 011111 D A B OE 0111101001 Rc divwx 011111 D A B OE 0111101011 Rc slbia 011111 00000 00000 00000 011
30. MPCPRG D 10 95 MPRPPCPRG 01 PowerPC Microprocessor Family The Programmer s Reference Guide ocwerPc Mj MOTOROLA 2 a Motorola Inc 1995 Portions hereof International Business Machines Corp 1991 1995 All rights reserved This document contains information on a new product under development by Motorola and IBM Motorola and IBM reserve the right to change or discontinue this product without notice Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors There are no express or implied copyright or patent licenses granted hereunder by Motorola or IBM to design modify the design of or fabricate circuits based on the information in this document The PowerPC 60x microprocessors embody the intellectual property of Motorola and of IBM However neither Motorola nor IBM assumes any responsibility or liability as to any aspects of the performance operation or other attributes of the microprocessor as marketed by the other party or by any third party Neither Motorola nor IBM is to be considered an agent or representative of the other and neither has assumed created or granted hereby any right or authority to the other or to any third party to assume or create any express or implied obligations on its behalf Information such as data sheets as well as sales terms and conditions such as prices schedules and support for the product may vary as between parti
31. PC Microprocessor Family The Programmer s Reference Guide Table 14 State of MSR at Power Up Continued 64 Bit 32 Bit 64 Bit EL Description Description s C Notes 1 Unspecified can be either 0 or 1 2 1 is typical but might be 0 1 9 Processor Version Register PVR The processor version register PVR is a 32 bit read only register that contains a value identifying the specific version model and revision level of the PowerPC processor see Figure 11 The contents of the PVR can be copied to a GPR by the mfspr instruction Read access to the PVR is supervisor level only write access is not provided Version Revision 0 1516 Figure 11 Processor Version Register PVR The PVR consists of two 16 bit fields e Version bits 0 15 A 16 bit number that uniquely determines a particular 31 processor version and version of the PowerPC architecture This number can be used to determine the version of a processor it may not distinguish between different product models if more than one model uses the same processor Revision bits 16 31 16 bit number that distinguishes between various releases of a particular version that is an engineering change level The value of the revision portion of the PVR is implementation specific The processor revision level is changed for each revision of the device PowerPC Microprocessor Family The Programmer s Reference Gu
32. SPRGO SPRG1 SPRG2 SPRG3 Figure 17 SPRGO SPRGS3 Table 17 provides a description of conventional uses of SPRGO SPRG3 Table 17 Conventional Uses of SPRGO SPRG3 Register Description SPRGO Software may load a unique physical address in this register to identify an area of memory reserved for use by the first level exception handler This area must be unique for each processor in the system This register may be used as a scratch register by the first level exception handler to save the content of a GPR That GPR then can be loaded from SPRGO and used as a base register to save other GPR s to memory SPRG2 This register may be used by the operating system as needed SPRGS3 This register may be used by the operating system as needed 1 16 DSISR The 32 bit DSISR shown in Figure 18 identifies the cause of DSI and alignment exceptions DSISR Figure 18 DSISR 1 17 Machine Status Save Restore Register 0 SRRO The SRRO is a 64 bit register in 64 bit implementations and a 32 bit register in 32 bit implementations SRRO is used to save machine status on exceptions and restore machine PowerPC Microprocessor Family The Programmer s Reference Guide 23 status when an rfi instruction is executed It also holds the EA for the instruction that follows the System Call sc instruction The format of SRRO is shown in Figure 19 For 32 bit implementations the format of SRRO follows the
33. TBR 268 TBR 269 Table 4 provides a quick method by which to reference the SPR and TBR numbers and bit fields for all 64 bit PowerPC registers Note that reserved bits are shaded Table 4 Quick Reference Guide 64 Bit Registers 0123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051Name amp 54 555657 GPRn FPRn FPRn For the MSR bits refer to 1 8 Machine State Register MSR on page 16 MSR Branch Address LR CTR CTR DAR DAR HTABORG 00000000 0 OHTABSIZE SDR1 SRRO 0 0 SRRO SRR1 SRR1 SPRGn SPRGn Physical Address of Segment Table 000000000 9 ASRO BEPI 9 0 ojo BL sVp xBATnU BRPN 0000000 dWIMG o xBATnL 3 DAB PR TB L TB L 2 00000000000000000000000p0000000 TBU TBU 012345 6 7 8 9 101112131415161718192021 22 232425 26272829 30 3132 33 34 35 36 37 38 3940 4142 4344 454647 48 49 50 51M tf e54 555657 Notes 1 For all SPR numbers refer to Figure 1 2 Read only 1 1 General Purpose Registers GPRs Integer data is manipulated in the processor s 32 GPRs shown in Figure 2 These registers are 64 bit registers in 64 bit implementations and 32 bit registers in 32 bit implementations The GPRs are accessed as source and destination registers in the instruction syntax GPRO GPR1 GPR31 0 63 31 Figure 2 General Purpose Registers GPRs 1 2 Floating Point Regis
34. This is a copy of the final state of FPSCR OX at the completion of the instruction Note For more information on the FPSCR refer to Section 1 4 Floating Point Status and Control Register FPSCR PowerPC Microprocessor Family The Programmer s Reference Guide 13 Table 10 CRn Field Bit Settings for Compare Instructions Description Less than or floating point less than LT FL For integer compare instructions rA SIMM or rB signed comparison or UIMM or rB unsigned comparison For floating point compare instructions frA frB Greater than or floating point greater than GT FG For integer compare instructions rA SIMM or rB signed comparison or rA UIMM or rB unsigned comparison For floating point compare instructions frA frB Equal or floating point equal EQ FE For integer compare instructions rA SIMM UIMM or rB For floating point compare instructions frA Summary overflow or floating point unordered SO FU For integer compare instructions This is a copy of the final state of XER SO at the completion of the instruction For floating point compare instructions One or both of frA and frB is a Not a Number NaN Notes 1 Here the bit indicates the bit number any one of the four bit subfields 7 2 For a complete description of instruction syntax conventions refer to Table 31 1 6 Link
35. at a minimum If the processor does not support 64 bits of physical address software should write zeroes to those unsupported bits in the HTABORG field as the implementation treats them as reserved Otherwise a machine check exception can occur A page table can be any size 24 bytes where 18 n lt 46 The HTABSIZE field in SDR1 contains an integer value that specifies how many bits from the output of the hashing function are used as the page table index HTABSIZE is used to generate a mask of the form 0500 011 1 a string of HTABSIZE 28 0 bits followed by a string of 1 bits As the table size increases more bits are used from the output of the hashing function to index into the table The 1 bits in the mask determine how many additional bits beyond the minimum of 11 from the hash are used in the index the HTABORG field must have this same number of lower order bits equal to 0 2 3 3 2 SDR1 Register Definition for 32 Bit Implementations The format of SDR1 for 32 bit implementations is similar to that of 64 bit implementations except that the register size is 32 bits and the HTABMASK field is programmed explicitly into SDR1 Additionally the address ranges correspond to a 32 bit physical address and the range of page table sizes is smaller Figure 33 shows the format of the SDR1 register for 32 bit implementations the bit settings are described in Table 29 38 PowerPC Microprocessor Family The Programmer s Reference Guide
36. bed in the user s manual for the implementation Effects of the setting of this bit is implementation dependent This is not a sticky bit 30 31 RN Floating point rounding control 00 Round to nearest 01 Round toward zero 10 Round toward infinity 11 Round toward infinity These are not sticky bits Table 7 illustrates the floating point result flags used by PowerPC processors The result flags correspond to FPSCR bits 15 19 PowerPC Microprocessor Family The Programmer s Reference Guide 11 Table 7 Floating Point Result Flags in FPSCR Result Flags Bits 15 19 Result Value Class 1 Quiet NaN 0 Infinity 0 Normalized number Denormalized number Zero Denormalized number 0 0 Normalized number 0 1 Infinity 1 5 Condition Register CR The format of the condition register CR is shown in Figure 6 CRO CR1 CR2 CR4 CRS CR6 CR7 34 78 1112 1516 19 20 23 24 27 28 31 Figure 6 Condition Register CR The CR fields can be set in one of the following ways Specified fields of the CR can be set by a move instruction mterf to the CR from a GPR A specified field of the CR can be moved to another CR field with the merf instruction A specified field of the XER can be copied to the CR by the instruction A specified field of the FPSCR can be copied to the CR by the merfs instruction Condition register logical instr
37. by the operating system Each STE is a 128 bit entity two double words that maps one effective segment ID to one virtual segment ID Information in the STE controls the segment table search process and provides input to the memory protection 30 PowerPC Microprocessor Family The Programmer s Reference Guide mechanism Figure 25 shows the format of both double words that comprise a 0 segment descriptor or STE in a 64 bit implementation Reserved ESID 000000000000000000000 V T Ks Kp 000 0 35 36 55 56 57 58 59 6061 63 VSID 00000000000 0 51 52 63 Figure 25 STE Format 64 Bit Implementations Table 21 lists the bit definitions for each double word in an STE Table 21 STE Bit Definitions for Page Address Translation 64 Bit Implementations e ESID Effective segment ID FEN V Entry valid V 1 or invalid V 0 T 0 selects this format No execute protection bit VSID Virtual segment ID Reserved The Ks and Kp bits partially define the access protection for the pages within the segment The virtual segment ID field is used as the high order bits of the virtual page number VPN Supervisor state protection key User state protection key The segment descriptors are programmed by the operating system and placed into segment tables in memory although some processors may additionally have on chip segment lookaside buffers SLBs These SLBs store copies of recently use
38. d STEs that can be accessed quickly providing increased overall performance 2 2 1 1 Address Space Register ASR The ASR contains the control information for the segment table structure in that it defines the highest order bits for the physical base address of the segment table The format of the PowerPC Microprocessor Family The Programmer s Reference Guide 31 ASR is shown in Figure 26 The ASR contains bits 0 51 of the 64 bit physical base address of the segment table Bits 52 56 of the STEG address are derived from the hashing function and bits 57 63 are zero at the beginning of a segment table search operation to point to the beginning of an STEG Therefore the beginning of the segment table lies on 2 byte 4 Kbyte boundary Note that unless all accesses to be performed by the processor can be translated by the BAT mechanism when address translation is enabled MSR DR or MSR IR 1 the ASR must point to a valid segment table If the processor does not support 64 bits of physical address software should write zeros to those unsupported bits in the ASR Otherwise a machine check exception can occur Additionally values x0 0x1000 and 0x2000 should not be used as segment table addresses as they correspond to areas of the exception vector table reserved for implementation specific purposes Reserved Physical Address of Segment Table 000000000000 0 51 52 63 Figure 26 ASR Register For
39. dentifier 63 V Entry valid V 1 or invalid V 0 1 0 51 Physical page number wu 55 R Referenced bit 56 C Changed bit 57 60 WIMG Memory cache access control bits a 62 63 PP Page protection bits The PTE contains an abbreviated page index rather than the complete page index field because at least 11 of the low order bits of the page index are used in the hash function to select a PTE group PTEG address PTEG addresses define the location of a PTE Therefore these 11 lower order bits are not repeated in the PTEs of that PTEG 36 PowerPC Microprocessor Family The Programmer s Reference Guide 2 3 2 PTE Format for 32 Bit Implementations Figure 31 shows the format of the two words that comprise a PTE for 32 bit implementations Reserved 0 1 24 25 26 31 V VSID H API RPN 000 R C WIMG 0 PP 0 19 20 22 23 24 25 28 29 30 31 Figure 31 Page Table Entry Format 32 Bit Implementations Table 27 lists the corresponding bit definitions for each word in a PTE as defined above Table 27 PTE Bit Definitions 32 Bit Implementations 0 ry valid V 1 or invalid V 0 irtual segment ID Hash function identifier breviated page index 1 Physical page number Reserved Referenced bit Changed bit 25 28 WIMG Memory cache control bits 29 Reserved 30 31 Page protection bits In this case the PTE contains an abbreviated page index rather
40. depends on the driving frequency The TB is implemented such that the following requirements are satisfied 1 Loading a GPR from the time base has no effect on the accuracy of the time base 2 Storing a GPR to the time base replaces the value in the time base with the value in the GPR The PowerPC VEA does not specify a relationship between the frequency at which the time base is updated and other frequencies such as the processor clock The TB update frequency is not required to be constant however for the system software to maintain time of day and operate interval timers one of two things is required The system provides an implementation dependent exception to software whenever the update frequency of the time base changes and a means to determine the current update frequency or The system software controls the update frequency of the time base Note that if the operating system initializes the TB to some reasonable value and the update frequency of the TB is constant the TB can be used as a source of values that increase at a constant rate such as for time stamps in trace entries PowerPC Microprocessor Family The Programmer s Reference Guide 25 Even if the update frequency is not constant values read from the TB are monotonically increasing except when the TB wraps from 294 _ 1 to 0 If a trace entry is recorded each time the update frequency changes the sequence of TB values can be post processed to beco
41. e If the conditions that cause the exception also cause the processor state to be corrupted such that the contents of SRRO and SRR1 are no longer valid or such that other processor resources are so corrupted that the processor cannot reliably resume execution the copy of the RI bit copied from the MSR to SRR1 is cleared DSI 00300 A DSI exception occurs when a data memory access cannot be performed Such accesses can be generated by load store instructions certain memory control instructions and certain cache control instructions For more detailed information refer to Chapter 6 Exceptions in The Programming Environments Manual ISI 00400 An ISI exception occurs when an instruction fetch cannot be performed For more detailed information refer to Chapter 6 Exceptions in The Programming Environments Manual External 00500 An external interrupt is generated only when an external exception is pending interrupt typically signaled by a signal defined by the implementation and the interrupt is enabled MSR EE 1 Alignment 00600 An alignment exception may occur when the processor cannot perform a memory access because of alignment or endian reasons Note that an implementation is allowed to perform the operation correctly and not cause an alignment exception For more detailed information refer to Chapter 6 Exceptions in The Programming Environments Manual Program 00700 A program exception is caused conditions which correspond
42. e T bit is set for 32 bit implementations T Ks Kp BUID Controller Specific Information 0123 1112 31 Figure 29 Segment Register Format for Direct Store Segments 32 Bit Implementations 34 PowerPC Microprocessor Family The Programmer s Reference Guide Table 25 shows the bit definitions for the segment registers when the T bit is set for 32 bit implementations Table 25 Segment Register Bit Definitions for Direct Store Segments om 00 0 T 1 selects this format 1 Ks Supervisor state protection key User state protection key BUID Bus unit ID 12 31 Device specific data for controller 2 3 Page Table Entry PTE Definitions Page table entries PTEs are generated and placed in page tables in memory by the operating system The PowerPC OEA defines similar PTE formats for both 64 and 32 bit implementations in that the same fields are defined However 64 bit implementations define PTEs that are 128 bits in length while 32 bit implementations define PTEs that are 64 bits in length Additionally care must be taken when programming for both 64 and 32 bit implementations as the bit placements of some fields are different Some of the fields are defined as follows The virtual segment ID field corresponds to the high order bits of the virtual page number VPN and along with the H V and API fields it is used to locate the PTE used as match criteria in comparing
43. e exception handler Bits 0 23 are status bits Bits 24 31 are control bits Status bits in the FPSCR are updated at the completion of the instruction execution Except for the floating point enabled exception summary FEX and floating point invalid operation exception summary VX the exception condition bits in the FPSCR bits 0 12 and 21 23 are sticky Once set sticky bits remain set until they are cleared by an merfs mtfsf mtfsbO instruction FEX and VX are the logical ORs of other FPSCR bits Therefore these two bits are not listed among the FPSCR bits directly affected by the various instructions PowerPC Microprocessor Family The Programmer s Reference Guide 9 FPSCR bit settings are shown in Table 6 Table 6 FPSCR Bit Settings ating point exception summary Every floating point instruction except mtfsfi and mtfsf sets FPSCR FX if that instruction causes any of the floating point exception bits in the FPSCR to transition from 0 to 1 The merfs mtfsfi mtfsf mtfsb0 and mtfsb1 instructions can alter FPSCR FX explicitly This is a sticky bit oating point enabled exception summary This bit signals the occurrence of any of the enabled exception conditions It is the logical OR of all the floating point exception bits masked by their respective enable bits The merfs mtfsf mtfsfi mtfsb0 and mtfsb1 instructions cannot alter FPSCR FEX explicitly This is not a sticky bit ing point invalid ope
44. e processor can execute floating point instructions Machine check enable 0 Machine check exceptions are disabled 1 Machine check exceptions are enabled Floating point exception mode 0 see Table 13 Single step trace enable Optional O0 The processor executes instructions normally 1 The processor generates a single step trace exception upon the successful execution of the next instruction Note If the function is not implemented this bit is treated as reserved execution of a branch instruction regardless of whether or not the branch was taken Note If the function is not implemented this bit is treated as reserved Floating point exception mode 1 see Table 13 Reserved Full function Exception prefix The setting of this bit specifies whether an exception vector offset is prepended with Fs or Os In the following description nnnnn is the offset of the exception See Table 30 0 Exceptions are vectored to the physical address 0x000n nnnn in 32 bit implementations and 0x0000 0000 000n nnnn in 64 bit implementations 1 Exceptions are vectored to the physical address nnnn in 32 bit implementations and OxFFFF_FFFF_FFFn_nnnn in 64 bit implementations Branch trace enable Optional 0 The processor executes branch instructions normally 1 The processor generates a branch trace exception after completing the Instruction address translation 0 Instruction address translation is disabled
45. ementation specific exceptions Part 4 PowerPC Instruction Set The following sections include an instruction field summary a list of split field notation and conventions and the entire PowerPC instruction set sorted by mnemonic and opcode 4 1 Instruction Field Summary Table 31 describes the instruction fields used in the various instruction formats Table 31 Instruction Syntax Conventions Description Absolute address bit 0 The immediate field represents an address relative to the current instruction address CIA The effective logical address of the branch is either the sum of the LI field sign extended to 64 bits and the address of the branch instruction or the sum of the BD field sign extended to 64 bits and the address of the branch instruction 1 The immediate field represents an absolute address The effective address EA of the branch is the LI field sign extended to 64 bits or the BD field sign extended to 64 bits Note The LI and BD fields are sign extended to 32 bits in 32 bit implementations Immediate field specifying a 14 bit signed two s complement branch displacement that is concatenated on the right with 0600 and sign extended to 64 bits 32 bits in 32 bit implementations Field used to specify a bit in the CR to be used as the condition of a branch conditional instruction Field used to specify options for the branch conditional instructions PowerPC Microprocessor Family The Programme
46. er level instruction 3 Load and store string or multiple instruction 64 bit instruction 5 Optional instruction 6 32 bit instruction only Table 34 lists the instructions defined in the PowerPC architecture in numeric order by opcode Key Reserved bits Table 34 Complete Instruction List Sorted by Opcode Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 tdi 000010 TO A SIMM twi 000011 TO A SIMM mulli 000111 D A SIMM subfic 001000 D A SIMM cmpli 001010 c D 1011 A UIMM cmpi 001011 1011 A SIMM addic 001100 D A SIMM addic 001101 D A SIMM addi 001110 D A SIMM addis 001111 D A SIMM bcx 010000 BO BI BD sc 010001 00000 00000 000000000000000 110 bx 010010 LI mcrf 010011 crfD 00 5 00 00000 0000000000 0 belrx 010011 BO BI 00000 0000010000 LK crnor 010011 crbD crbA crbB 0000100001 0 rfi 010011 00000 00000 00000 0000110010 0 crandc 010011 crbD crbA crbB 0010000001 0 isync 010011 00000 00000 00000 0010010110 0 crxor 010011 crbD crbA crbB 0011000001 0 PowerPC Microprocessor Family The Programmer s Reference Guide 51 Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 crnand 0
47. ernational Business Machines Corp is an Equal Opportunity Affirmative Action Employer This document was created with FrameMaker 4 0 4
48. ers c Integer unit Link register Memory management unit msb Vost significant bit MSR Machine state register NaN Not a number No Op OEA No operation Operating environment architecture PTE PTEG Page table entry Page table entry group PVR Processor version register RISC Reduced instruction set computing SDR1 Register that specifies the page table base address for virtual to physical address translation SIMM SLB Signed immediate value Segment lookaside buffer PowerPC Microprocessor Family The Programmer s Reference Guide Table 1 Acronyms and Abbreviated Terms Continued Term Meaning SPR Special purpose register SPRGn Registers available for general purposes n 2 Segment register SRRO Machine status save restore register 0 SRR1 Machine status save restore register 1 TB Time base register TLB Translation lookaside buffer UIMM Unsigned immediate value UISA User instruction set architecture VEA Virtual environment architecture XER Register used for indicating conditions such as carries and overflows for integer operations Table 2 describes instruction field notation conventions used in this document Table 2 Instruction Field Conventions The Architecture Specification Equivalent to BA BB BT CrbA crbB crbD respectively BF BFA crfS respectively FRA FRB FRC FRT FRS frA frB frC frD frS respectively FXM
49. es selling the product Accordingly customers wishing to learn more information about the products as marketed by a given party should contact that party Both Motorola and IBM reserve the right to modify this manual and or any of the products as described herein without further notice NOTHING IN THIS MANUAL NOR IN ANY OF THE ERRATA SHEETS DATA SHEETS AND OTHER SUPPORTING DOCUMENTATION SHALL BE INTERPRETED AS THE CONVEYANCE BY MOTOROLA OR IBM OF AN EXPRESS WARRANTY OF ANY KIND OR IMPLIED WARRANTY REPRESENTATION OR GUARANTEE REGARDING THE MERCHANTABILITY OR FITNESS OF THE PRODUCTS FOR ANY PARTICULAR PURPOSE Neither Motorola nor IBM assumes any liability or obligation for damages of any kind arising out of the application or use of these materials Any warranty or other obligations as to the products described herein shall be undertaken solely by the marketing party to the customer under a separate sale agreement between the marketing party and the customer In the absence of such an agreement no liability is assumed by Motorola IBM or the marketing party for any damages actual or otherwise Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Neither Motorola nor IBM convey any license under their respective intellectual property rights nor the rights of others Neither Motorola nor IBM makes any claim warran
50. es to 4 Kbyte pages in physical memory page address translation while providing the programming flexibility afforded by a large virtual address space 80 or 52 bits The page address translation uses segment descriptors which provide virtual address and protection information and page table entries PTEs which provide the physical address and page protection information The segment descriptors are programmed by the operating system to provide the virtual ID for a segment In addition the operating system also creates the page tables in memory that provide the virtual to physical address mappings in the form of PTEs for the pages in memory Segments in the OEA are defined as one of the following two types Memory segment An effective address in these segments represents a virtual address that is used to define the physical address of the page e Direct store segment References made to direct store segments do not use the virtual paging mechanism of the processor The T bit in the segment descriptor selects between memory segments and direct store segments as shown in Table 20 28 PowerPC Microprocessor Family The Programmer s Reference Guide Table 20 Segment Descriptor Types Segment piod Segment Type Direct store segment accesses generated by the processor map to a segment descriptor If MSR IR 0 or MSR DR 0 for an instruction or data access respectively then real addressing mode translation is perfo
51. exception Some SPRs are implementation specific In some cases not all of a register s bits are implemented in hardware When a PowerPC microprocessor detects SPR encodings other than those defined in this document it either takes a program exception if bit 0 of the SPR encoding is set or it treats the instruction as a no op if bit 0 of the SPR encoding is clear Note that the general purpose registers GPRs link register LR count register CTR machine state register MSR data address register DAR SDRI save and restore registers 0 and 1 SRRO and SRR1 SPRGO SPRG3 and data address breakpoint register DABR are 64 bits in length in 64 bit implementations and 32 bits in length in 32 bit implementations 4 PowerPC Microprocessor Family The Programmer s Reference Guide SUPERVISOR MODEL y N Configuration Registers USER MODEL Machine State Register Processor Version Register MSR PVR SPR 287 General Purpose Registers GPRO Memory Management Registers GPRI Instruction BAT Registers Data BAT Registers 4 IBATOU SPR 528 DBATOU SPR 536 2 IBATOL SPR 529 DBATOL SPR 537 IBAT1U SPR 530 DBAT1U SPR 538 IBATIL SPR 531 DBATIL SPR 539 Floating Point Registers IBAT2U SPR 532 DBAT2U SPR 540
52. ide 1 10 BAT Registers Figure 12 and Figure 13 show the format of the upper and lower BAT registers for 64 bit PowerPC processors Reserved BEPI 0000 BL Vs Vp 0 46 47 50 51 61 62 63 Figure 12 Upper BAT Register 64 Bit Implementations Reserved BRPN 0000000000 WIMG o PP 0 46 47 56 57 60 61 62 63 Figure 13 Lower BAT Register 64 Bit Implementations Figure 14 and Figure 15 show the format of the upper and lower BAT registers for 32 bit PowerPC processors Reserved BEPI 0000 BL Vs Vp 0 14 15 1819 29 30 31 Figure 14 Format of Upper BAT Registers 32 Bit Implementations Reserved BRPN 0000000000 0 14 15 WIMG 0 PP 24 25 28 29 30 31 Figure 15 Format of Lower BAT Registers 32 Bit Implementations 20 PowerPC Microprocessor Family The Programmer s Reference Guide Table 15 describes the bits in the BAT registers Table 15 BAT Registers Field and Bit Descriptions Upper Bits Lower Description BAT 64 Bit 32 Bit Upper 0 46 0 14 BEPI Block effective page index This field is compared with high order bits BAT of the logical address to determine if there is a hit in that BAT array Register entry The architecture specification refers to logical address as effective address 46 50 15 18 Reserved 51 61 19 29 BL Block length BL is a mask that encodes the
53. low order bits 32 63 of Figure 19 Reserved SRRO 00 0 61 62 63 Figure 19 Machine Status Save Restore Register 0 SRRO When an exception occurs SRRO is set to point to an instruction such that all prior instructions have completed execution and no subsequent instruction has begun execution When rfi is executed the contents of SRRO are copied to the next instruction address NIA the 64 or 32 bit address of the next instruction to be executed The instruction addressed by SRRO may not have completed execution depending on the exception type SRRO addresses either the instruction causing the exception or the instruction that immediately follows The instruction addressed can be determined from the exception type and status bits If the exception occurs in 32 bit mode of the 64 bit implementation the high order 32 bits of SRRO are cleared and the high order 32 bits of the NIA are cleared when returning to 32 bit mode Note that in some implementations every instruction fetch when MSR IR 1 and every instruction execution requiring address translation when MSR DR 1 may modify SRRO 1 18 Machine Status Save Restore Register 1 SRR1 The SRRO is a 64 bit register in 64 bit implementations and a 32 bit register in 32 bit implementations 5 1 is used to save machine status on exceptions and to restore machine status when an rfi instruction is executed The format of SRR1 is shown in Figure 20
54. mat 64 Bit Implementations Only 2 2 2 Segment Descriptor Format 32 Bit Implementations In 32 bit implementations the segment descriptors are 32 bits long and reside in one of 16 segment registers Figure 27 shows the format of a segment register used in page address translation T 0 in a 32 bit implementation Reserved T Ks Kp N 0000 VSID 01234 78 31 Figure 27 Segment Register Format for Page Address Translation 32 Bit Implementations Table 22 provides the corresponding bit definitions of the segment register in 32 bit implementations 32 PowerPC Microprocessor Family The Programmer s Reference Guide Table 22 Segment Register Bit Definition for Page Address Translation 32 Bit Implementations 0 T T 0 selects this format 1 Ks Supervisor state protection key 2 Kp User state protection key 3 N No execute protection bit f 8 31 VSID Virtual segment ID The Ks and Kp bits partially define the access protection for the pages within the segment The virtual segment ID field is used as the high order bits of the virtual page number VPN The segment register instructions are summarized in Table 23 These instructions are privileged in that they are executable only while operating in supervisor mode Table 23 Segment Register Instructions 32 Bit Implementations Only Instruction Description mtsr SR rS Move to Segment Register SR SR rS mtsrin
55. mber within the segment these are concatenated with the VSID from the segment descriptor to form the virtual page number VPN The VPN is used to search for the PTE in either an on chip TLB or the page table The PTE then provides the physical page number RPN Bits 52 63 of the effective address are the byte offset within the page these concatenated with the RPN field of a PTE to form the physical address used to access memory PowerPC Microprocessor Family The Programmer s Reference Guide 29 The translation of effective addresses to physical addresses for 32 bit implementations is similar to that for 64 bit implementations except that 32 bit implementations index into an array of 16 segment registers instead of segment tables in memory to locate the segment descriptor and the address ranges are obviously different Thus the address translation is as follows Bits 0 3 of the effective address comprise the segment register number used to select a segment descriptor from which the virtual segment ID VSID is extracted Bits 4 19 of the effective address correspond to the page number within the segment these are concatenated with the VSID from the segment descriptor to form the virtual page number VPN The VPN is used to search for the PTE in either an on chip TLB or the page table The PTE then provides the physical page number RPN Bits 20 31 of the effective address are the byte offset within the page these a
56. me actual time values For information on reading writing and computing time of day on the time base refer to Chapter 2 PowerPC Register Set The Programming Environments Manual 1 20 Decrementer Register DEC The DEC shown in Figure 22 is a 32 bit decrementing counter that provides a mechanism for causing a decrementer exception after a programmable delay The DEC frequency is based on the same implementation dependent frequency that drives the time base DEC Figure 22 Decrementer Register DEC For information on writing and reading the DEC refer to Chapter 2 PowerPC Register Set The Programming Environments Manual 1 21 Data Address Breakpoint Register DABR The data address breakpoint facility is controlled by the DABR a 64 bit register in 64 bit implementations and a 32 bit register in 32 bit implementations The data address breakpoint facility is optional to the PowerPC architecture as is the DABR However if the data address breakpoint facility is implemented it is recommended but not required that it be implemented as described in this section The data address breakpoint facility provides a means to detect accesses to a designated double word The address comparison is done on an effective address and it applies to data accesses only It does not apply to instruction fetches The DABR is shown in Figure 23 DAB BT DWIDR 0 60 61 62 63 Figure 23 Data Address B
57. onditions such as prices schedules and support for the product may vary as between parties selling the product Accordingly customers wishing to learn more information about the products as marketed by a given party should contact that party Both Motorola and IBM reserve the right to modify this manual and or any of the products as described herein without further notice NOTHING IN THIS MANUAL NOR IN ANY OF THE ERRATA SHEETS DATA SHEETS AND OTHER SUPPORTING DOCUMENTATION SHALL BE INTERPRETED AS THE CONVEYANCE BY MOTOROLA OR IBM OF AN EXPRESS WARRANTY OF ANY KIND OR IMPLIED WARRANTY REPRESENTATION OR GUARANTEE REGARDING THE MERCHANTABILITY OR FITNESS OF THE PRODUCTS FOR ANY PARTICULAR PURPOSE Neither Motorola nor IBM assumes any liability or obligation for damages of any kind arising out of the application or use of these materials Any warranty or other obligations as to the products described herein shall be undertaken solely by the marketing party to the customer under a separate sale agreement between the marketing party and the customer In the absence of such an agreement no liability is assumed by Motorola IBM or the marketing party for any damages actual or otherwise Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Neither Motorola nor IBM convey any license under their respective intellectual
58. priately coded BO field If the value in is 0 before being decremented it is 1 afterward The can also provide the branch target address for the Branch Conditional to Count Register bectrx instruction The CTR is shown in Figure 8 CTR 0 63 31 Figure 8 Count Register CTR Fetching instructions along the target path is also possible provided the count register is loaded sufficiently ahead of the branch instruction The count register can be accessed by the mtspr and mfspr instructions by specifying SPR9 In branch conditional instructions the BO field specifies the conditions under which the branch is taken The first four bits of the BO field specify how the branch is affected by or affects the CR and the CTR The encoding for the BO field is shown in Table 11 Table 11 BO Operand Encodings BO Description 0000y Decrement the CTR then branch if the decremented CTR 0 and the condition is FALSE 0001y Decrement the then branch if the decremented 0 and the condition is FALSE 001zy Branch if the condition is FALSE 0100y Decrement the CTR then branch if the decremented CTR gt 0 and the condition is TRUE 0101y Decrement the then branch if the decremented 0 and the condition is TRUE 0112 Branch if the condition is TRUE 1200 Decrement the CTR then branch if the decremented 0 1201 Decrement the CTR then branch if
59. property rights nor the rights of others Neither Motorola nor IBM makes any claim warranty or representation express or implied that the products described in this manual are designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the product could create a situation where personal injury or death may occur Should customer purchase or use the products for any such unintended or unauthorized application customer shall indemnify and hold Motorola and IBM and their respective officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola or IBM was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer IBM and IBM logo are registered trademarks and IBM Microelectronics is a trademark of International Business Machines Corp The PowerPC name PowerPC logotype and PowerPC 601 are trademarks of International Business Machines Corp used by Motorola under license from International Business Machines Corp Int
60. r s Reference Guide 41 Table 31 Instruction Syntax Conventions Continued CrbA 11 15 i specify a bit in the CR to be used as a source crbB 16 20 i specify a bit in the CR to be used as a source crbD 6 10 ield used to specify a bit in the CR or in the FPSCR as the destination of the result of an instruction crfD 6 8 i o specify one of the CR fields or one of the FPSCR fields as a destination crfS 11 13 i o specify one of the CR fields or one of the FPSCR fields as a source ield mask used to identify the CR fields that are to be updated by the mterf instruction Immediate field specifying a 16 bit signed two s complement integer that is sign extended to 64 bits 32 bits in 32 bit implementations Immediate field specifying a 14 bit signed two s complement integer which is concatenated on the right with 0600 and sign extended to 64 bits This field is defined in 64 bit implementations only FM 7 14 i used to identify the FPSCR fields that are to be updated by the mtfsf instruction frA 11 15 o specify an FPR as a source frB 16 20 eld used to specify an FPR as a source frC 21 25 eld used to specify an FPR as a source frD 6 10 specify FPR as the destination frS 6 10 i specify an FPR as a source IMM 16 19 mmediate field used as the data to be placed into a field in the FPSCR L 10 Field used to specify whether an integer compare inst
61. rS rB Move to Segment Register Indirect SR rB 0 3 garS mfsr rD SR Move from Segment Register rD lt SR SR Move from Segment Register Indirect rD lt SR rB 0 3 2 2 3 Segment Descriptors for Direct Store Segments The format of many of the fields in the segment descriptors depends on the value of the T bit Figure 28 shows the format of segment descriptors residing as STEs in segment tables that define direct store segments for 64 bit implementations T bit is set PowerPC Microprocessor Family The Programmer s Reference Guide 33 R Double Word 0 eserved ESID 000000000000000000000 V T Ks Kp 0000 0 35 36 55 56 57 58 59 60 63 Double Word 1 Controller Specific Information Figure 28 Segment Descriptor Format for Direct Store Segments 64 Bit Implementations Table 24 shows the bit definitions for the segment descriptors when the T bit is set for 64 bit implementations Table 24 Segment Descriptor Bit Definitions for Direct Store Segments 64 Bit Implementations Double Word Bit Name Description Effective segment ID Reserved Entry valid V 1 or invalid V 0 T 0 selects this format Supervisor state protection key User state protection key Reserved Device specific data for controller In 32 bit implementations the segment descriptors reside in one of 16 segment registers Figure 29 shows the register format for the segment registers when th
62. ration exception summary This bit signals the occurrence of any id operation exception It is the logical OR of all of the invalid operation exceptions The s mtfsf mtfsfi mtfsb0 and mtfsb1 instructions cannot alter FPSCR VX explicitly This t a sticky bit ing poin low exception This is a sticky bit ing point underflow exception This is a sticky bit ing point zero divide exception This is a sticky bit loating point inexact exception This is a sticky bit FPSCR XX is the sticky version of FPSCR FIJ The following rules describe how FPSCR XX is set by a given instruction If the instruction affects FPSCR FI the new value of FPSCR XX is obtained by logically ORing the old value of FPSCR XX with the new value of FPSCR FI If the instruction does not affect FPSCR FI the value of FPSCR XX is unchanged 7 VXSNAN ing point invalid operation exception for SNaN This is a sticky bit ing point invalid operation exception for This is a sticky bit o vxo ing point invalid operation exception for This is a sticky bit ing point invalid operation exception for 0 0 This is a sticky bit ing point invalid operation exception for 0 This is a sticky bit ing point invalid operation exception for invalid compare This is a sticky bit ing point fraction rounded The last arithmetic or rounding and conversion instruction that unded the intermediate result inc
63. re concatenated with the RPN field of a PTE to form the physical address used to access memory 2 1 2 Direct Store Segment Address Translation As described for memory segments all accesses generated by the processor with translation enabled that do not map to a BAT area map to a segment descriptor If T 1 for the selected segment descriptor the access maps to the direct store interface invoking a specific bus protocol for accessing some special purpose I O devices Direct store segments are provided for POWER compatibility As the direct store interface is present only for compatibility with existing I O devices that used this interface and the direct store interface protocol is not optimized for performance its use is discouraged Applications that require low latency load store access to external address space should use memory mapped I O rather than the direct store interface 2 2 Segment Descriptor Definitions The format of the segment descriptors is different for 64 bit and 32 bit implementations Additionally the fields in the segment descriptors are interpreted differently depending on the value of the T bit within the descriptor When T 1 the segment descriptor defines a direct store segment 2 2 1 STE Format 64 Bit Implementations In 64 bit implementations the segment descriptors reside as segment table entries STEs in hashed segment tables in memory These STEs are generated and placed in segment tables in memory
64. reakpoint Register 64 Bit Implementations 26 PowerPC Microprocessor Family The Programmer s Reference Guide Table 18 describes the fields in the DABR Table 18 DABR Field Descriptions Description Data address breakpoint Breakpoint translation enable Data write enable 63 31 DR Data read enable A data address breakpoint match is detected for a load or store instruction if the three following conditions are met for any byte accessed e EA 0 60 DABR DAB MSR DR DABR BT The instruction is a store and DABR DW 1 or the instruction is a load and DABR DR 1 In 32 bit mode of 64 bit implementation the high order 32 bits of the EA are treated as zero for the purpose of detecting a match 1 22 External Access Register EAR The EAR is an optional 32 bit SPR that controls access to the external control facility and identifies the target device for external control operations The external control facility provides a means for user level instructions to communicate with special external devices The EAR is shown in Figure 24 Note that the EAR is an optional register Reserved E 0000000000000000000000000 RID 0 1 25 26 31 Figure 24 External Access Register EAR The high order bits of the resource ID RID field that correspond to bits of the RID beyond the width of the RID supported by a particular implementation are treated as reserved bits The
65. remented the fraction This bit is not sticky oating point fraction inexact The last arithmetic or rounding and conversion instruction either rounded the intermediate result producing an inexact fraction or caused a disabled overflow exception This is not a sticky bit For more information regarding the relationship between FPSCR FI and FPSCR XX see the description of the FPSCR XX bit 10 PowerPC Microprocessor Family The Programmer s Reference Guide Table 6 FPSCR Bit Settings Continued Bit s Name Description 15 19 FPRF Floating point result flags For arithmetic rounding and conversion instructions the field is based on the result placed into the target register except that if any portion of the result is undefined the value placed here is undefined 15 loating point result class descriptor C Arithmetic rounding and conversion instructions may set this bit with the FPCC bits to indicate the class of the result see Table 7 16 19 Floating point condition code FPCC Floating point compare instructions always set one of the FPCC bits to one and the other three FPCC bits to zero Arithmetic rounding and conversion instructions may set the FPCC bits with the C bit to indicate the class of the result Note that in this case the high order three bits of the FPCC retain their relational significance indicating that the value is less than reater than or equal to zero 16 oating point less than or
66. rmed Otherwise if T 0 in the corresponding segment descriptor and the address is not translated by the BAT mechanism the access maps to memory space and page address translation is performed After a memory segment is selected the processor creates the virtual address for the segment and searches for the PTE that dictates the physical page number to be used for the access Note that I O devices can be easily mapped into memory space and used as memory mapped I O 2 1 Address Translation Overview The following sections provide a brief overview of the page and direct store segment address translation For more information refer to Chapter 7 Memory Management in The Programming Environments Manual 2 1 1 Page Address Translation The first step in page address translation for 64 bit implementations is the conversion of the 64 bit effective address of an access into the 80 bit virtual address The virtual address is then used to locate the PTE in the page tables in memory The physical page number is then extracted from the PTE and used in the formation of the physical address of the access The translation of an effective address to a physical address for 64 bit implementations is described briefly Bits 0 35 of the effective address comprise the effective segment ID used to select a segment descriptor from which the virtual segment ID VSID is extracted Bits 36 51 of the effective address correspond to the page nu
67. ruction is to compare 64 bit numbers or 32 bit numbers This field is defined in 64 bit implementations only LI 6 29 Immediate field specifying a 24 bit signed two s complement integer that is concatenated on the right with 0000 and sign extended to 64 bits 32 bits in 32 bit implementations 29 K 31 Link bit 0 Does not update the link register LR 1 Updates the LR If the instruction is a branch instruction the address of the instruction following the branch instruction is placed into the LR MB 21 25 and Fields used in rotate instructions to specify a 64 bit mask 32 bits in 32 bit implementations ME 26 30 consisting of 1 bits from bit MB 32 through bit ME 32 inclusive and 0 bits elsewhere NB 16 20 eld used to specify the number of bytes to move in an immediate string load or store OE 21 Used for extended arithmetic to enable setting OV and SO in the XER OPCD 0 5 Primary opcode field rA 11 15 used to specify GPR to be used as a source or destination rB 16 20 ield used to specify a GPR to be used as a source 42 PowerPC Microprocessor Family The Programmer s Reference Guide Table 31 Instruction Syntax Conventions Continued Id Description Fiel Rc 31 Record bit 0 Does not update the condition register CR 1 Updates the CR to reflect the result of the operation For integer instructions CR bits 0 2 are set to reflect the result as a signed quantity
68. s stdux 31 S A B 181 0 stdx 31 S A B 149 0 54 S A d stfdu 55 S A d stfdux 31 S A B 759 0 stfdx 31 S A B 727 0 stfiwx 31 S A B 983 0 PowerPC Microprocessor Family The Programmer s Reference Guide 49 Name 0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 52 8 4 stfsu 53 S A d stfsux 31 S A B 695 0 stfsx 31 S A B 663 0 sth 44 S A d sthbrx 31 S A B 918 0 sthu 45 S A d sthux 31 S A B 439 0 sthx 31 S A B 407 0 stmw 47 S A d stswi 31 S A NB 725 0 stswx 3 31 S A B 661 0 stw 36 S A d stwbrx 31 S A B 662 0 stwcx 31 S A B 150 1 stwu 37 5 stwux 31 S A B 183 0 stwx 31 S A B 151 0 subfx 31 D A B 40 subfcx 31 D A B 8 subfex 31 D A B 136 subfic 08 D A SIMM subfmex 31 D A 00000 232 Rc subfzex 31 D A 00000 200 Rc sync 31 00000 00000 00000 598 0 td 31 TO A B 68 0 tdi 02 TO A SIMM tlbia 15 31 00000 00000 00000 370 0 tlbie 15 31 00000 00000 B 306 0 tlbsync 31 00000 00000 00000 566 0 tw 31 TO A B 4 0 twi 03 TO A SIMM 31 5 B 316 50 PowerPC Microprocessor Family The Programmer s Reference Guide Name 0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 xori 26 S A UIMM xoris 27 S A UIMM Supervisor level instruction Supervisor and us
69. s to specify the last 1 bit of a 64 bit mask 32 bits in 32 bit implementations This field is defined in 64 bit implementations only sh 16 20 and ields used to specify a shift amount 64 bit implementations only sh 30 spr 11 20 ield used to specify a special purpose register for the mtspr and mfspr instructions tbr 11 20 ield used to specify either the time base lower TBL or time base upper TBU PowerPC Microprocessor Family The Programmer s Reference Guide 43 4 2 PowerPC Instruction Set Listings This section lists the PowerPC architecture s instruction set Instructions are sorted by mnemonic and opcode Note that split fields that represent the concatenation of sequences from left to right are shown in lowercase Table 33 lists the instructions implemented in the PowerPC architecture in alphabetical order by mnemonic Key Reserved bits Table 33 Complete Instruction List Sorted by Mnemonic Name 0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addx 31 D A B 266 Rc addcx 31 D A B 10 Rc addex 31 D A B 138 addi 14 D A SIMM addic 12 D A SIMM addic 13 D A SIMM addis 15 D A SIMM addmex 31 D A 00000 234 Rc addzex 31 D A 00000 202 Rc andx 31 S A B 28 Rc andcx 31 5 B 60 andi 28 S A UIMM andis 2
70. size of the block Values or this field are listed in Table 16 62 30 Vs Supervisor mode valid bit This bit interacts with MSR PR to determine if there is a match with the logical address 63 31 Vp User mode valid bit This bit also interacts with MSR PR to determine if there is a match with the logical address Lower 0 46 0 14 BRPN This field is used in conjunction with the BL field to generate high BAT order bits of the physical address of the block Register 47 56 15 24 Reserved 57 60 25 28 WIMG Memory cache access mode bits Write through Caching inhibited M Memory coherence G Guarded 61 29 Reserved 62 63 30 31 Protection bits for block Table 16 lists the BAT area lengths encoded in the BL field of the upper BAT registers Table 16 BAT Area Lengths BAT Area Length BL Encoding 000 0000 0000 256 Kbytes 000 0000 0001 512 Kbytes 000 0000 0011 000 0000 0111 000 0000 1111 000 0001 1111 000 0011 1111 16 Mbytes 000 0111 1111 32 Mbytes 000 1111 1111 PowerPC Microprocessor Family The Programmer s Reference Guide 21 Table 16 BAT Area Lengths Continued BAT Area Length BL Encoding 64 Mbytes 001 1111 1111 128 Mbytes 011 1111 1111 256 Mbytes 111 1111 1111 1 11 SDR1 The SDRI is a 64 bit register in 64 bit implementations and a 32 bit register in 32 bit implementations Refer to Section 2 3 3 SDRI Register Definitions for a complete
71. ters FPRs The PowerPC architecture provides thirty two 64 bit FPRs as shown in Figure 3 These registers are accessed as source and destination registers for floating point instructions Each FPR supports the double precision floating point format Every instruction that interprets the contents of an FPR as a floating point value uses the double precision floating point format for this interpretation PowerPC Microprocessor Family The Programmer s Reference Guide T floating point arithmetic instructions operate on data located in FPRs and with the exception of compare instructions place the result into an FPR Information about the status of floating point operations is placed into the FPSCR and in some cases into the CR after the completion of instruction execution The floating point arithmetic instructions produce intermediate results that may be regarded as infinitely precise After normalization or denormalization if the precision of the intermediate result cannot be represented in the destination format single or double precision it is rounded to the specified precision before being placed in the target FPR The final result is then placed into the FPR in the double precision format FPRO FPR1 FPR31 Figure 3 Floating Point Registers FPRs 1 3 XER Register XER The XER register XER is shown in Figure 4 Reserved SOJOV CA 0000000000000000000000 Byte count 01 23 24 25 31
72. the decremented CTR 0 12122 Branch always The z indicates a bit that is ignored The z bits should be cleared to zero as they may be assigned a meaning in some future version of the PowerPC architecture The y bit provides a hint about whether a conditional branch is likely to be taken and is used by some PowerPC implementations to improve performance Other implementations may ignore the y bit PowerPC Microprocessor Family The Programmer s Reference Guide 15 1 8 Machine State Register MSR The machine state register MSR is a 64 bit register on 64 bit implementations see Figure 9 and a 32 bit register in 32 bit implementations see Figure 10 Reserved SF 0000000000000000000000 0 ILEEEPR FPMEFEOSEBEFE1 0 IRDR 00 01 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 6162 63 Figure 9 Machine State Register MSR 64 bit Implementations Reserved 0000000000000 POW 0 FE1 0 00 0 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 2728 29 30 31 Figure 10 Machine State Register MSR 32 bit Implementations Table 12 shows the bit definitions for the MSR Full function reserved bits are saved in SRRI when an exception occurs partial function reserved bits are not saved Table 12 MSR Bit Settings Description
73. to bit settings in SRR1 and arise during execution of an instruction For more detailed information refer to Chapter 6 Exceptions in The Programming Environments Manual Floating point A floating point unavailable exception is caused by an attempt to execute a 40 PowerPC Microprocessor Family The Programmer s Reference Guide Table 30 Exceptions and Conditions Continued Exception Vector Offset i m Type Causing Conditions Decrementer 00900 The decrementer interrupt exception is taken if the interrupt is enabled and the exception is pending The exception is created when the most significant bit changes from 0 to 1 If itis not enabled the exception remains pending until it is taken Reserved 00A00 Reserved for implementation specific exceptions For example the PowerPC 601 microprocessor uses this vector offset for direct store exceptions Reserved 00B00 System call 00 00 A system call exception occurs when a System Call sc instruction is executed 00000 The trace exception is optional It occurs if either MSR SE 1 and any instruction except rfi successfully completed or MSR BE 1 and a branch instruction is completed Floating Point 00E00 The floating point assist exception is optional This exception can be used to Assist provide software assistance for infrequent and complex floating point operations such as denormalization Reserved 00E10 00FFF Reserved 01000 02FFF Reserved for impl
74. ty or representation express or implied that the products described in this manual are designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the product could create a situation where personal injury or death may occur Should customer purchase or use the products for any such unintended or unauthorized application customer shall indemnify and hold Motorola and IBM and their respective officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola or IBM was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer IBM and IBM logo are registered trademarks and IBM Microelectronics is a trademark of International Business Machines Corp The PowerPC name PowerPC logotype and PowerPC 601 are trademarks of International Business Machines Corp used by Motorola under license from International Business Machines Corp International Business Machines Corp is an Equal Opportunity Affirmative Action Employer
75. uctions can be used to perform logical operations on specified bits in the condition register CRO can be the implicit result of an integer instruction CRI can be the implicit result of a floating point instruction A specified CR field can indicate the result of either an integer or floating point compare instruction Note that branch instructions are provided to test individual CR bits PowerPC Microprocessor Family The Programmer s Reference Guide The following tables Table 8 Table 10 provide bit setting information for CRO and the CRz fields respectively CRO Bit Table 8 Bit Settings for CRO Field of CR Description Negative LT This bit is set when the result is negative Positive GT This bit is set when the result is positive and not zero Zero EQ This bit is set when the result is zero Summary overflow SO This is a copy of the final state of XER SO at the completion of the instruction Table 9 Bit Settings for CR1 Field of CR CR1 Bit Description Floating point exception FX This is a copy of the final state of FPSCR FX at the completion of the instruction Floating point enabled exception FEX This is a copy of the final state of FPSCR FEX at the completion of the instruction Floating point invalid exception VX This is a copy of the final state of FPSCR VX at the completion of the instruction Floating point overflow exception OX
76. wing instructions Add carrying subtract from carrying add extended and subtract from extended instructions set CA if there is a carry out of the msb and clear it otherwise Shift right algebraic instructions set CA if any 1 bits have been shifted out of a negative operand and clear it otherwise The CA bit is not altered by compare instructions nor by other instructions that cannot carry except shift right algebraic mtspr to the XER and merxr 3 24 Reserved 25 31 This field specifies the number of bytes to be transferred by a Load String Word Indexed Iswx or Store String Word Indexed stswx instruction 1 4 Floating Point Status and Control Register FPSCR Figure 5 shows the format of the floating point status and control register FPSCR Reserved VXIDI VXZDZ VXSOFT VXISI 7 VXIMZ VXSQRT VXSNAN VXVC UX ZX XX FR FI FPRF 0 2 NI RN 012 3 4 5 6 7 8 9 10 11 12 13 1415 1920 21 22 23 24 25 26 27 28 29 30 31 Figure 5 Floating Point Status and Control Register FPSCR The FPSCR contains bits to do the following Record exceptions generated by floating point operations Record the type of the result produced by a floating point operation Control the rounding mode used by floating point operations Enable or disable the reporting of exceptions invoking th

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PowerPC&trade; Microprocessor Family: The Programmer`s Reference

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PowerPC™ Microprocessor Family: The Programmer`s Reference