Home

DAQ NI PCI-6110/6111 User Manual

Contents

1. ee EN 55011 Class A at 10m FCC Part 15A above 1 GHz Electrical immunity Evaluated to EN 61326 1997 A1 1998 Table 1 ER Note For full EMC compliance you must operate this device with shielded cabling In addition all covers and filler panels must be installed Refer to the Declaration of Conformity DoC for this product for any additional regulatory compliance information To obtain the DoC for this product click Declaration of Conformity at ni com hardref nsf This Web site lists the DoCs by product family Select the appropriate product family followed by the product and a link to the DoC appears in Adobe Acrobat format Click the Acrobat icon to download or read the DoC National Instruments Corporation A 13 NI PCI 6110 6111 User Manual Cable Connector Descriptions This appendix describes the cable connectors on the NI PCI 6110 6111 Figure B 1 shows the pin assignments for the 68 pin NI PCI 6110 6111 connector This connector is available when you use the SH6868EP cable assemblies with the NI PCI 6110 6111 Figure B 2 shows the pin assignments for the NI PCI 6110 6111 when used with 50 pin accessories National Instruments Corporation B 1 NI PCI 6110 6111 User Manual Appendix B Cable Connector Descriptions ACHO ACH1 ACH1GND ACH2 ACH3 1 ACH3GND1 NC NC NC NC NC NC DACOOUT DAC1OUT NC DIO4 DGND DIO1 DIO6 DGND 45V DGND
2. CONVERT la SCANCLK 4 c 1 4 ty ty 50 100 ns tw 450 ns Figure 4 20 SCANCLK Signal Timing EXTSTROBE Signal EXTSTROBE is an output only signal that generates either a single pulse or a sequence of eight pulses in the hardware strobe mode An external device can use this signal to latch signals or to trigger events In the single pulse mode software controls the level of EXTSTROBE A 10 us and a 1 2 us clock are available for generating a sequence of eight pulses in the hardware strobe mode 3 Note EXTSTROBE cannot be enabled through NI DAQ Figure 4 21 shows the timing for the hardware strobe mode EXTSTROBE signal tw 600 ns or 5 us Figure 4 21 EXTSTROBE Signal Timing Waveform Generation Timing Connections The analog group defined for the NI PCI 6110 6111 is controlled by WFTRIG UPDATE and UISOURCE National Instruments Corporation 4 27 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals NI PCI 6110 6111 User Manual WFTRIG Signal Any PFI pin can externally input the WFTRIG signal which is available as an output on the PFI6 WFTRIG pin As an input WFTRIG is configured in the edge detection mode You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge The selected edge of WFTRIG starts the waveform generation for the DACs
3. eene Impedance to ground ACH lt 0 3 gt to ground Input bias current esses Input offset current s Dynamic Characteristics Interchannel skew ee amp 0 5 LSB typ 1 LSB max 0 3 LSB typ 0 75 LSB max Refer to Table A 2 Analog Input Characteristics 11 0 bits DC to 100 kHz Refer to Table A 1 NI PCI 6110 6111 Accuracy Information 1 MQ in parallel with 100 pF 1 MQ minimum 1 MQ 10 nF 200 pA 100 pA Refer to Table A 2 Analog Input Characteristics 1 ns typ fin 100 kHz input range 10 V Bandwidth Range Small Signal 3 dB 200 mV 4 MHz 500 mV to 50 V 5MHz A 4 ni com Appendix A Specifications ER Note Bandwidth specifications are for signals on the input with the input at DC ground The input is slew rate limited to 24 V usec and has an additional 10 nF capacitance to ground System noise sese See Table A 2 Analog Input Characteristics C rosstalk iii iia 80 dB DC to 100 kHz Table A 2 Analog Input Characteristics Bandwidth SFDR Typ SFDR Max CMRR System Noise Input Range MHz dB dB dB LSB ms 50 V 5 5 78 70 34 0 5 20 V 4 4 78 70 40 0 5 10 V 12 81 75 46 0 5 45V 4 8 81 75 52 0 5 2 V 4 8 85 75 60 0 5 1V 4 4 85 75 66 0 5 500 mV 4 4 85 75 70 0 6 200 mV 4 1 81 70 72 1 0 123
4. Rising edge polarity 1 Falling edge polarity ty 10 ns minimum Figure 4 24 UPDATE Input Signal Timing ty 50 75 ns Figure 4 25 UPDATE Output Signal Timing The DACS are updated within 100 ns of the leading edge Separate the UPDATE pulses with enough time that new data can be written to the DAC latches The NI PCI 6110 6111UI normally generates UPDATE unless you select some external source The WFTRIG signal starts the UI and the UI can be stopped by software or the internal Buffer Counter National Instruments Corporation 4 29 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software command register gate UISOURCE Signal Any PFI pin can externally input the UISOURCE signal which is not available as an output on the I O connector The UI uses UISOURCE as a clock to time the generation of the UPDATE signal You must configure the PFI pin you select as the source for UISOURCE in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low Figure 4 26 shows the timing requirements for the UISOURCE signal tp 2 50 ns minimum ty 10 ns minimum Figure 4 26 UISOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 1
5. eere 12 bits 1 in 4 096 Pipeline uso nasan 3 Sampling rate MAXIMUM cooocccccononnnnncnonanonanoconanonnnoos 5 MS s Minimum coccccccnononnnononononanancnonanonanoss 1 kS s Input coupling eeeee DC or AC Max working voltage for all AI channels Maximum Working Voltage Input Channels Range Signal Common Mode ACH lt 0 3 gt 20 mV to 10 V Should remain within 11 V of ground 20 to 50 V Should remain within 42 V of ground ACH lt 0 3 gt All Should remain within 11 V of ground Overvoltage protection 42 V Inputs protected Positive input seeeeess All channels Negative input esee All channels O National Instruments Corporation A 1 NI PCI 6110 6111 User Manual Appendix A Specifications FIFO buffer size 8 192 samples Data transfers occcccccncnnnnnanananannnnnnnnonon DMA interrupts programmed I O DMA modes ee Scatter gather single transfer demand transfer Accuracy Information Refer to Table A 1 NI PCI 6110 6111 User Manual A 2 ni com Specifications Appendix A pepueururoooi1 eA19 UI UOTJeIqI e2 IeoK ouQ ounje1eduro uomeqipeo JOJ98J JO VUIOIXE JO Do OTF pue ounje1eduro uoneuqipeo eurojur JO D TF UYIM seunje1oduro euoreuodo 107 PASH oe soroenooe juouromnseopq sSurpeor ouueqo o 8urs Qo Jo Surge1oAe pue SULIOYJIP eurnsse srequinu peSe1oAV uoneJqipeo eu1o
6. mN AB N wo N N N N o c 18 N o er al A ak w c ye 2 w o 5 omox o oo zi ACHO ACHOGND ACH1 ACH2 1 ACH2GND1 ACH3 1 NC NC NC NC NC NC NC AOGND AOGND DGND DIOO DIO5 DGND DIO2 DIO7 DIO3 SCANCLK EXTSTROBE DGND PFI2 CONVERT PFI3 GPCTR1_SOURCE PFI4 GPCTR1_GATE GPCTR1_OUT DGND PFI7 STARTSCAN PFI8 GPCTRO_SOURCE DGND DGND 1 NC on NI PCI 6111 NC No Connect Figure 4 1 68 Pin I O Connector Pin Assignment for the NI PCI 6110 6111 4 2 ni com Chapter 4 Connecting Signals DIOO 25 50 FREQ OUT DGND 24 49 GPCTRO OUT AOGND 23 48 PFI9 GPCTRO GATE NC 22 47 PFI8 GPCTRO SOURCE DAC1OUT 21 46 PFI7 STARTSCAN DACOOUT 20 45 PFI6 WFTRIG NC 19 44 PFI5 UPDATE NC 18 43 GPCTR1_OUT NC 17 42 PFI4 GPCTR1_GATE NC 16 41 PFIS GPCTR1 SOURCE NC 15 40 PFI2 CONVERT NC 14 39 PFH TRIG2 NC 13 38 PFIO TRIG1 NC 12 37 EXTSTROBE PFIO TRIG1 11 36 SCANCLK ACH3 1 10 35 5V ACH3 9 34 45V ACH2 8 33 DGND ACH2 1 7 32 DIO7 ACH1 6 31 DIO6 ACH1 5 30 DIO5 ACHO 4 29 DIO4 ACHO 3 28 DIO3 ACH lt 0 3 gt GND 2 27 DIO2 ACH lt 0 3 gt GND 1 26 DIO1 1 NC on NI PCI 6111 Figure 4 2 50 Pin Connector Pin Assignments for the
7. Any PFI pin can externally input the GPCTRO GATE signal which is available as an output on the PFIJ GPCTRO GATE pin As an input GPCTRO GATE is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform actions such as starting and stopping the counter generating interrupts and saving the counter contents As an output GPCTRO GATE reflects the actual gate signal connected to general purpose counter 0 even if the gate is being externally generated by another PFI This output is set to high impedance at startup National Instruments Corporation 4 31 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals Figure 4 28 shows the timing requirements for the GPCTRO GATE signal Rising edge polarity Falling edge polarity ty 2 10 ns minimum Figure 4 28 GPCTRO GATE Signal Timing GPCTRO OUT Signal This signal is available only as an output on the GPCTRO OUT pin The GPCTRO OUT signal reflects the terminal count TC of general purpose counter 0 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to high impedance at startup Figure 4 29 shows the timing of GPCTRO OUT GPCTRO SOURCE
8. 45 RES o 44 E 43 Aa N 42 A o 41 E al 40 EM A 39 Aa wo 38 n 37 36 35 34 33 32 31 30 29 28 27 wm o n ocj o olo z 26 FREQ OUT GPCTRO OUT PFIS GPCTRO GATE PFIB GPCTRO SOURCE PFI7 STARTSCAN PFI6 WFTRIG PFI5 UPDATE GPCTR1_OUT PFI4 GPCTR1_GATE PFIS GPCTR1 SOURCE PFI2 CONVERT PFH TRIG2 PFIO TRIG1 EXTSTROBE SCANCLK 5 V 5 V DGND DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 1 NC on NI PCI 6111 Figure B 2 50 Pin Connector Pin Assignment for the NI PCI 6110 6111 B 3 NI PCI 6110 6111 User Manual Cable Connector Descriptions Common Questions This appendix contains a list of commonly asked questions and answers relating to usage and special features of the NI PCI 6110 6111 General Information What is the NI PCI 6110 6111 The NI PCI 6110 6111 is a switchless and jumperless enhanced Multifunction DAQ device that uses the DAQ STC for timing What is the DAQ STC The DAQ STC is the system timing control application specific integrated circuit ASIC designed by NI and is the backbone of the NI PCI 6110 6111 The DAQ STC contains seven 24 bit counters and three 16 bit counters The counters are divided into the following three groups e Al two 24 bit two 16 bit counters e AO three 24 bit one 16 bit counters e General purpose
9. STARTSCAN ep L Ea CONVERT i ww E o Scan Counter Figure 4 9 Typical Posttriggered Acquisition Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest in addition to data acquired after the trigger Figure 4 10 shows a typical pretriggered DAQ sequence The description for each signal shown in these figures appears later in this chapter NI PCI 6110 6111 User Manual 4 18 ni com Chapter 4 Connecting Signals TRIG1 TRIG2 STARTSCAN CONVERT Scan Counter NA Figure 4 10 Typical Pretriggered Acquisition TRIG1 Signal Any PFI pin can receive as an input the TRIGI signal which is available as an output on the PFIO TRIGI pin Refer to Figures 4 9 and 4 10 for the relationship of TRIGI to the DAQ sequence As an input the TRIGI signal is configured in the edge detection mode You can select any PFI pin as the source for TRIGI and configure the polarity selection for either rising or falling edge The selected edge of the TRIGI starts the DAQ sequence for both posttriggered and pretriggered acquisitions The NI PCI 6110 6111 supports analog triggering on the PFIO TRIGI pin See Chapter 3 Hardware Overview for more information on analog triggering As an output TRIGI reflects the action that initiates a
10. real time system integration bus the National Instruments timing bus that connects DAQ devices directly by means of connectors on top of the devices for precise timing synchronization between multiple devices RTSI Oscillator RTSI bus master clock seconds samples samples per second used to express the rate at which a DAQ device samples an analog signal scan counter controls how often a scan is initialized the scan interval is regulated by STARTSCAN G 11 NI PCI 6110 6111 User Manual Glossary scan rate SCANCLK SCSI settling time SFDR SD signal conditioning SISOURCE SOURCE STARTSCAN system noise tout THD NI PCI 6110 6111 User Manual reciprocal of the scan interval scan clock signal small computer system interface a high speed peripheral connect interface primarily used for hard disks CD ROM drives tape drives and other mass storage devices to PCs the amount of time required for a voltage to reach its final value within specified limits spurious free dynamic range the dynamic range from full scale deflection to the highest spurious signal in the frequency domain sample interval counter the manipulation of signals to prepare them for digitizing SI counter clock signal source signal start scan signal a measure of the amount of noise seen by an analog circuit or an ADC when the analog inputs are grounded terminal count the ending value of a counter delay time gate ho
11. Any PFI pin can receive as an input the SISOURCE signal which is not available as an output on the I O connector The SI2 uses SISOURCE as a clock to time the generation of the STARTSCAN signal You must configure the PFI pin you select as the source for SISOURCE in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low The maximum allowed frequency is 20 MHz with a minimum pulse width of 23 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase generates SISOURCE unless you select some external source Figure 4 19 shows the timing requirements for SISOURCE 50 ns minimum 23 ns minimum tp Figure 4 19 SISOURCE Signal Timing SCANCLK Signal SCANCLK is an output only signal that generates a pulse with the leading edge occurring approximately 50 to 100 ns after an A D conversion begins The polarity of this output is software selectable but it is typically configured so that a low to high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed This signal has a 450 ns pulse width and is software enabled Note SCANCLK polarity is low to high and cannot be changed programmatically using NI DAQ NI PCI 6110 6111 User Manual 4 26 ni com Chapter 4 Connecting Signals Figure 4 20 shows the timing for SCANCLK
12. GPCTRO OUT Pulse on TC TC i GPCTRO OUT Toggle output on TC NI PCI 6110 6111 User Manual Figure 4 29 GPCTRO OUT Signal Timing GPCTRO UP DOWN Signal This signal can be externally input on the DIO6 pin and is not available as an output on the I O connector The general purpose counter 0 counts down when this pin is at a logic low and counts up when it is at a logic high You can disable this input so that software controls the up down functionality and leaves the DIO6 pin free for general use 4 32 ni com Chapter 4 Connecting Signals GPCTR1 SOURCE Signal Any PFI pin can externally input the GPCTR1 SOURCE signal which is available as an output on the PFI3 GPCTR1 SOURCE pin As an input GPCTR1 SOURCE is configured in the edge detection mode You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity selection for either rising or falling edge As an output GPCTR1 SOURCE monitors the actual clock connected to general purpose counter 1 even if the source clock is being externally generated by another PFI This output is set to tri state at startup Figure 4 30 shows the timing requirements for GPCTR1 SOURCE tp 2 50 ns minimum ty 10 ns minimum Figure 4 30 GPCTR1 SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 10 ns high or low Th
13. O 1997 2002 National Instruments Corporation All rights reserved Important Information Warranty The NI PCI 6110 and the NI PCI 6111 are warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for techni
14. The update interval counter UD is started if you select internally generated UPDATE As an output WFTRIG reflects the trigger that initiates waveform generation even if the waveform generation is being externally triggered by another PFI The output is an active high pulse with a pulse width of 25 to 50 ns This output is set to high impedance at startup Figures 4 22 and 4 23 show the timing requirements for WFTRIG Rising edge polarity Falling edge polarity ty 10 ns minimum Figure 4 22 WFTRIG Input Signal Timing f ty 25 50 ns I Figure 4 23 WFTRIG Output Signal Timing 4 28 ni com Chapter 4 Connecting Signals UPDATE Signal Any PFI pin can externally input the UPDATE signal which is available as an output on the PFIS UPDATE pin As an input UPDATE is configured in the edge detection mode You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of UPDATE updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode As an output UPDATE reflects the actual update pulse that is connected to the DACs even if the updates are being externally generated by another PFI The output is an active low pulse with a pulse width of 50 to 75 ns This output is set to high impedance at startup Figures 4 24 and 4 25 show the timing requirements for UPDATE
15. questions about C 4 timing I O connections figure 4 17 waveform generation timing connections overview 4 27 UISOURCE signal 4 30 UPDATE signal 4 29 WFTRIG signal 4 28 timing I O questions about C 4 specifications A 9 timing signal routing 3 8 device and RTSI clocks 3 10 programmable function inputs 3 9 RTSI triggers 3 11 STARTSCAN signal routing figure 3 9 training customer D 1 transfer characteristics specifications analog input A 4 analog output A 6 TRIGI signal See also PFIO TRIGI signal input timing figure 4 20 output timing 4 20 timing connections 4 19 NI PCI 6110 6111 User Manual 1 10 typical posttriggered acquisition figure 4 18 typical pretriggered acquisition figure 4 19 TRIG2 signal See also PFI1 TRIG2 signal input timing figure 4 21 output timing figure 4 21 timing connections 4 20 trigger analog See analog trigger trigger digital See digital trigger troubleshooting resources D 1 U UISOURCE signal timing connections 4 30 timing diagram 4 30 unpacking the NI PCI 6110 6111 1 5 UPDATE signal See also PFIS UPDATE signal timing connections 4 29 using with UISOURCE signal 4 30 using with WFTRIG signal 4 28 V VCC signal signal summary table 4 6 VI Logger application software 1 4 voltage output specifications A 7 voltage working range 4 13 W waveform generation timing connections overview 4 27 questions about C 3 UISOURCE signal 4 30 U
16. ADC ADC Mux Analog Trigger Circuit DAQ STC Figure 3 4 Analog Trigger Block Diagram for the NI PCI 6111 Five analog triggering modes are available as shown in Figures 3 5 through 3 9 You can independently set lowValue and highValue in software National Instruments Corporation 3 5 NI PCI 6110 6111 User Manual Chapter 3 Hardware Overview In below low level analog triggering mode the trigger is generated when the signal value is less than lowValue as shown in Figure 3 5 HighValue is unused lowValue Trigger A ami Figure 3 5 Below Low Level Analog Triggering Mode In above high level analog triggering mode the trigger is generated when the signal value is greater than highValue as shown in Figure 3 6 LowValue is unused highValue Trigger Figure 3 6 Above High Level Analog Triggering Mode In inside region analog triggering mode the trigger is generated when the signal value is between the lowValue and the highValue as shown in Figure 3 7 NI PCI 6110 6111 User Manual 3 6 ni com Chapter 3 Hardware Overview highValue X ecd orte ee AN WOMEN lowValue Trigger Figure 3 7 Inside Region Analog Triggering Mode In high hysteresis analog triggering mode the trigger is generated when the signal value is greater than highValue with the h
17. Select Signal deviceNumber ND PFI 5 ND OUT UPDATE ND HIGH TO LOW e Ifyou are using LabVIEW invoke Route Signal vi with signal name set to PFI5 and signal source set to AO Update National Instruments Corporation C 3 NI PCI 6110 6111 User Manual Appendix C Common Questions 2 Setup acquisition timing so that the timing signal for A D conversion comes from PFI5 as follows e If you are using NI DAQ call Select Signal deviceNumber ND IN SCAN START ND PFI 5 ND HIGH TO LOW e If you are using LabVIEW invoke AI Clock Config vi with clock source code set to PFI pin high to low and clock source string set to 5 3 Initiate AI data acquisition which starts only when the AO waveform generation starts 4 Initiate AO waveform generation Timing and Digital 1 0 What types of triggering can be hardware implemented on the NI PCI 6110 6111 Hardware digital and analog triggering are both supported on the NI PCI 6110 6111 What added functionality does the DAQ STC make possible in contrast to the Am9513 The DAQ STC incorporates much more than just 10 Am9513 style counters within one chip In fact the DAQ STC has the complexity of more than 24 chips The DAQ STC makes possible PFI lines analog triggering selectable logic level and frequency shift keying The DAQ STC also makes buffered operations possible such as direct up down control single or pulse train generation equivalent time sampling buffered peri
18. a DIFF input signal but the readings are random and drift rapidly What s wrong Check the ground reference connections The signal may be referenced to a level that is considered floating with reference to the device ground reference Even if you are in differential mode the signal must still be referenced to the same ground level as the device reference There are various methods of achieving this while maintaining a high common mode rejection ratio CMRR These methods are outlined in Chapter 4 Connecting Signals I m using the DACs to generate a waveform but I discovered with a digital oscilloscope that there are glitches on the output signal Is this normal When it switches from one voltage to another any DAC produces glitches due to released charges The largest glitches occur when the most significant bit MSB of the D A code switches You can build a low pass deglitching filter to remove some of these glitches depending on the frequency and nature of the output signal Can I synchronize a one channel AI data acquisition with a one channel AO waveform generation on the NI PCI 6110 6111 Yes One way to accomplish this is to use the waveform generation timing pulses to control the analog input data acquisition To do this follow steps 1 through 4 below in addition to the usual steps for data acquisition and waveform generation configuration 1 Enable the PFI5 line for output as follows e If you are using NI DAQ call
19. are relevant to your application are linked in while those object modules that are not relevant are not linked the adherence of device response to the equation R KS where R response S stimulus and K a constant least significant bit meter megabytes of memory a controlled centralized configuration environment that allows you to configure all of your National Instruments DAQ GPIB IMAQ IVI Motion VISA and VXI devices megahertz multifunction I O MXI Interface to Everything most significant bit G 8 ni com mux mV NC NI NI DAQ noise OUT PCI pd PFI PFIO TRIGI PFII TRIG2 National Instruments Corporation Glossary multiplexer a switching device with multiple inputs that sequentially connects each of its inputs to its output typically at high speeds in order to measure several signals with a single analog input channel millivolts not connected National Instruments National Instruments driver software for DAQ hardware an undesirable electrical signal Noise comes from external sources such as the AC power line motors generators transformers fluorescent lights CRT displays computers electrical storms welders radio transmitters and internal sources such as semiconductors resistors and capacitors Noise corrupts signals you are trying to send or receive output pin a counter output pin where the counter can generate various TTL pulse waveforms Peripheral Compon
20. bus to another device that is programmed to receive this timebase signal This clock source whether local or from the RTSI bus is used directly by the device as the primary frequency source The default configuration at startup is to use the internal timebase without driving the RTSI bus timebase signal This timebase is software selectable 3 10 ni com RTSI Triggers National Instruments Corporation Chapter 3 Hardware Overview The seven RTSI trigger lines on the RTSI bus provide a flexible interconnection scheme for the device sharing the RTSI bus These bidirectional lines can drive any of eight timing signals onto the RTSI bus and can receive any of these timing signals This signal connection scheme is shown in Figure 3 11 AS 9 8 gen E Trigger z o n 7 5 tr E tr Clock switch DAQ STC TRIG1 TRIG2 CONVERT UPDATE WFTRIG GPCTRO SOURCE GPCTRO GATE GPCTRO OUT STARTSCAN AIGATE SISOURCE UISOURCE GPCTR1 SOURCE GPCTR1_GATE RTSI_OSC 20 MHz 3y Figure 3 11 RTSI Bus Signal Connection Refer to the Timing Connections section of Chapter 4 Connecting Signals for a description of the signals shown in Figure 3 11 NI PCI 6110 6111 User Manual Connecting Signals This chapter describes how to make input and output signal connections to the NI PCI 6110 6111 through the device I O connector Table 4 1 shows the cables that can be
21. counter timer functions two 24 bit counters The groups can be configured independently with timing resolutions of 50 ns or 10 us With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is quite flexible and completely software configurable New capabilities such as buffered pulse generation equivalent time sampling and seamless changes to the sampling rate are possible What does the maximum sampling rate mean to me Sampling rate is the fastest you can acquire data on the device and still achieve accurate results The NI PCI 6110 6111 has a sampling rate of 5 MS s This sampling rate is at 5 MS s regardless if 1 or 4 channels are acquiring data National Instruments Corporation C 1 NI PCI 6110 6111 User Manual Appendix C Common Questions What type of 5 V protection does the NI PCI 6110 6111 have The NI PCI 6110 6111 has 5 V lines equipped with a self resetting 1 A fuse How do I use the NI PCI 6110 6111 with the NI DAQ C API The NI DAQ User Manual for PC Compatibles describes the general programming flow and provides example code for using the NI DAQ API For a list of functions that support the NI PCI 6110 6111 you can refer to the NI DAQ Function Reference Help for NI DAQ version 6 7 or later or the NI DAQ Function Reference Manual for NI DAQ version 6 6 or earlier Installing and Configuring NI PCI 6110 6111 User Manual How do
22. gating DAQ sequences 4 23 overview 4 25 amplifier characteristic specifications A 4 analog input input coupling 3 4 input mode 3 2 input polarity and input range 3 3 questions about C 3 signal connections 4 8 specifications amplifier characteristics A 4 dynamic characteristics A 4 input characteristics A 1 stability A 5 transfer characteristics A 4 analog output number of channels 3 4 output range 3 4 questions about C 3 signal connections 4 14 1 1 NI PCI 6110 6111 User Manual Index specifications dynamic characteristics A 7 output characteristics A 6 stability A 8 transfer characteristics A 6 voltage output A 7 analog trigger above high level analog triggering mode figure 3 6 avoiding false triggering note 3 4 below low level analog triggering mode figure 3 6 block diagram 3 5 block diagrams NI PCI 6110 3 5 NI PCI 6111 3 5 high hysteresis analog triggering mode figure 3 7 inside region analog triggering mode figure 3 7 low hysteresis analog triggering mode figure 3 7 specifications A 10 AOGND signal analog output signal connections 4 14 description table 4 4 signal summary table 4 6 avoiding false triggering note 3 4 below low level analog triggering mode 3 6 bipolar input 3 3 block diagrams NI PCI 6110 3 1 analog trigger 3 5 NI PCI 6111 3 2 analog trigger 3 5 bus interface specifications A 11 NI PCI 6110 6111 User Manual 1 2 PCI overview 1
23. high electromagnetic interference Route signals to the device carefully Keep cabling away from noise sources The most common noise source in a PCI DAQ system is the video monitor Separate the monitor from the analog signals as far as possible Separate the NI PCI 6110 6111 signal lines from high current or high voltage lines These lines can induce currents in or voltages on the NI PCI 6110 6111 signal lines if they run in parallel paths at a close distance To reduce the magnetic coupling between lines separate them by a reasonable distance if they run in parallel or run the lines at right angles to each other Do not run signal lines through conduits that also contain power lines Protect signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running them through special metal conduits For more information refer to the NI Developer Zone tutorial Field Wiring and Noise Consideration for Analog Signals available at ni com zone National Instruments Corporation 4 37 NI PCI 6110 6111 User Manual Calibration This chapter discusses the calibration procedures for the NI PCI 6110 6111 NI DAQ includes calibration functions for performing all of the steps in the calibration process Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments On the NI PCI 6110 6111 these adjustments take the form of wri
24. hysteresis analog triggering mode 3 7 highValue 3 5 3 6 3 7 O National Instruments Corporation 1 5 Index I O connectors cable options for the NI PCI 6110 6111 1 4 connector details table 4 1 exceeding maximum ratings caution 4 1 pin assignments 50 pin connector figure 4 3 B 3 68 pin connector figure 4 2 B 2 signal descriptions table 4 3 signal summary table 4 6 input coupling 3 4 input mode See differential measurements input polarity 3 3 input range 3 3 actual range and measurement precision table 3 3 considerations for selecting input ranges 3 4 inside region analog triggering mode 3 7 installation hardware 2 1 questions about C 2 software 2 1 unpacking the NI PCI 6110 6111 1 5 instrument drivers D 1 K KnowledgeBase D 1 L LabVIEW application software 1 3 loading calibration constants 5 1 lowValue 3 5 3 6 3 7 NI PCI 6110 6111 User Manual Index manual See documentation MAX configuration instructions 2 2 questions about C 2 Measurement and Automation Explorer See MAX Measurement Studio application software 1 4 National Instruments customer education D 1 professional services D 1 system integration services D 1 technical support D 1 worldwide offices D 1 National Instruments ADE software LabVIEW 1 3 Measurement Studio 1 4 VI Logger 1 4 NI PCI 6110 6111 See also hardware overview block diagram NI PCI 6110 3 1 NI PCI 6111 3 2 custom cablin
25. signal 4 22 TRIGI signal 4 19 TRIG2 signal 4 20 general purpose timing signal connections FREQ OUT signal 4 36 GPCTRO GATE signal 4 31 GPCTRO OUT signal 4 32 GPCTRO SOURCE signal 4 30 GPCTRO UP DOWN signal 4 32 GPCTR1_GATE signal 4 33 GPCTR1_OUT signal 4 34 GPCTR1_SOURCE signal 4 33 GPCTR1_UP_DOWN signal 4 35 overview 4 30 programmable function input connections 4 17 signal overview 4 16 waveform generation timing connections overview 4 27 UISOURCE signal 4 30 UPDATE signal 4 29 WFTRIG signal 4 28 types of signal sources floating 4 9 ground referenced 4 9 SISOURCE signal timing connections 4 26 timing diagram 4 26 software drivers D 1 software installation 2 1 software programming choices LabVIEW 1 3 ni com Measurement Studio 1 4 National Instruments application software 1 3 NI DAQ 1 2 overview 1 2 VI Logger 1 4 software programmable gain 3 3 actual range and measurement precision table 3 3 specifications analog input accuracy information table A 3 amplifier characteristics A 4 dynamic characteristics A 4 input characteristics A 1 stability A 5 transfer characteristics A 4 analog output dynamic characteristics A 7 output characteristics A 6 stability A 8 transfer characteristics A 6 voltage output A 7 bus interface A 11 digital I O A 8 electromagnetic compatibility A 13 environmental A 12 maximum working voltage A 12 physical A 12 power req
26. timing connections 4 30 relation to GPCTRO_OUT signal 4 32 timing diagram 4 31 GPCTRO_UP_DOWN signal digital I O lines 3 8 general purpose timing connections 4 32 GPCTR1_GATE signal general purpose counter timing summary figure 4 35 general purpose signal connections 4 33 timing diagram 4 34 GPCTRI OUT signal description table 4 5 general purpose counter timing summary figure 4 35 general purpose timing connections 4 34 signal summary table 4 7 GPCTRI SOURCE signal general purpose counter timing summary figure 4 35 general purpose timing connections 4 33 relation to GPCTR1 OUT signal 4 34 timing diagram 4 33 ni com GPCTRI UP DOWN signal digital I O lines 3 8 general purpose timing connections 4 35 ground referenced signal sources description 4 9 differential connections 4 11 recommended configuration table 4 10 H hardware installation procedure 2 1 unpacking the NI PCI 6110 6111 1 5 hardware overview analog input input coupling 3 4 input mode 3 2 input polarity and input range 3 3 overview 3 2 selection considerations 3 4 analog output 3 4 analog trigger block diagram 3 5 overview 3 4 block diagrams NI PCI 6110 3 1 NI PCI 6111 3 2 digital I O 3 8 timing signal routing device and RTSI clocks 3 10 overview 3 8 programmable function inputs 3 9 RTSI triggers 3 11 STARTSCAN signal routing figure 3 9 help professional services D 1 technical support D 1 high
27. volts output low reference voltage volts root mean square ground referenced signal source waveform generation trigger signal ni com Index Symbols 5 V signal description table 4 4 power connections 4 16 self resetting fuse 4 16 C 2 Numerics 50 pin connector pin assignment figure 4 3 B 3 68 pin connector pin assignment figure 4 2 B 2 A above high level analog triggering mode 3 6 AC input coupling 3 4 ACH lt 0 3 gt signal analog input connections 4 8 common mode signal rejection 4 12 description table 4 4 differential connections ground referenced signal sources figure 4 11 nonreferenced or floating signal sources figure 4 12 signal summary table 4 6 specifications A 1 working voltage range 4 13 ACH lt 0 3 gt signal analog input connections 4 8 common mode signal rejection 4 12 description table 4 3 differential connections ground referenced signal sources figure 4 11 National Instruments Corporation nonreferenced or floating signal sources figure 4 12 signal summary table 4 6 specifications A 1 working voltage range 4 13 ACH lt 0 3 gt GND signal common mode signal rejection 4 12 description table 4 3 differential connections ground referenced signal sources figure 4 11 nonreferenced or floating signal sources figure 4 12 power connections caution 4 16 signal summary table 4 6 working voltage range 4 13 AIGATE signal
28. x f CH3 ly o o oO m gt Calibrati Al Control c gt Mux c o Trigger Trigger Level 2 Analog gt Trigger O DACs rigg Circuitry T T o r i Analog Input 1 PFI Trigger Trigger Timing Control 1 DMA IRQ Counter Bus Timing VO DAQ STC interface ds 1 Analog Output RTSI Bus Digital VO 8 PRO Timing Control Interface PCI Bus Analog IEEPROM DMA de 1 Control Interface FPGA Interface vo Bus Analog Interface Output Control DAC FIFO DACO Data 16 AO Control DAC1 Calibration 4 DACs K Data 32 National Instruments Corporation Figure 3 1 NI PCI 6110 Block Diagram 3 1 NI PCI 6110 6111 User Manual Chapter 3 Hardware Overview CHO CH0 T AI CHO CHO Calibration Mux CHO 12 CHO Mux amples TS 12 Bit ADC Latch Data 16 m AL CH1 PG CH1 mux f lt gt gt Trigger Trigger Level 2 DACs Generic us Interface Address Data Y CH1 12 PA 12 Bit ADC Al Control Analog Trigger Circuitry T T f Trigger log Input i DMAa RQ i PCI Bus PFI Trigger Timing Control ae EEPROM DMA A e Ce Fn Contre Control Interface Counter Bus 3 Ss Timing vo DAQ STC interface MESS Interface 1 O Connector MM DIRE EE ene jh d Vo 1 Analog
29. you set the base address for the NI PCI 6110 6111 The base address of the NI PCI 6110 6111 is assigned automatically through the PCI bus protocol This assignment is completely transparent to you What jumpers should I be aware of when configuring the NI PCI 6110 6111 The NI PCI 6110 6111 is jumperless and switchless Which NI document should I read first to get started using DAQ software The DAQ Quick Start Guide and the NI DAQ or application software release notes documentation are good places to start Refer to ni com manuals to download these documents What is the best way to test the NI PCI 6110 6111 without programming the device If you are using Windows Measurement and Automation Explorer MAX has a test panel option that is available by selecting Devices and Interfaces in the left hand panel and then selecting the NI PCI 6110 6111 The test panels are excellent tools for performing simple functional tests of the device such as AI DIO and counter timer tests If you are using Mac OS the NI DAQ Configuration Utility provides the same functionality as MAX C 2 ni com Appendix C Common Questions Analog Input and Output Why is there a minimum sampling rate on the NI PCI 6110 6111 The NI PCI 6110 6111 makes use of a pipelined ADC in order to achieve its high sampling rates Sampling at rates below 20 kS s can result in improper digitalization which would appear as noise in the acquired data I connected
30. 0 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase normally generates the UISOURCE signal unless you select some external source General Purpose Timing Signal Connections NI PCI 6110 6111 User Manual The general purpose timing signals are GPCTRO SOURCE GPCTRO GATE GPCTRO OUT GPCTRO UP DOWN GPCTRI1 SOURCE GPCTR1_GATE GPCTR1_OUT GPCTRI UP DOWN and FREQ OUT GPCTRO SOURCE Signal Any PFI pin can externally input the GPCTRO SOURCE signal which is available as an output on the PFIS GPCTRO SOURCE pin 4 30 ni com Chapter 4 Connecting Signals Asaninput GPCTRO SOURCE is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO SOURCE and configure the polarity selection for either rising or falling edge As an output GPCTRO SOURCE reflects the actual clock connected to general purpose counter 0 even if another PFI is externally inputting the source clock This output is set to high impedance at startup Figure 4 27 shows the timing requirements for GPCTRO SOURCE tp 2 50 ns minimum ty 10 ns minimum Figure 4 27 GPCTRO SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 10 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTRO SOURCE signal unless you select some external source GPCTRO GATE Signal
31. 1 PCI Local Bus Specification Revision 2 0 2 2 RTSI device and RTSI clocks 3 10 overview 1 1 RTSI triggers 3 11 timing signal routing 3 8 C cables See also I O connectors custom cabling 1 4 field wiring considerations 4 36 optional equipment 1 4 calibration external calibration 5 2 loading calibration constants 5 1 self calibration 5 2 clocks device and RTSI 3 10 commonly asked questions See questions and answers common mode signal rejection 4 12 configuring NI PCI 6110 6111 2 2 questions about C 2 connectors See I O connectors contacting National Instruments D 1 conventions used in the manual xi CONVERT signal See also PFI2 CONVERT signal input timing figure 4 24 output timing figure 4 25 typical posttriggered acquisition figure 4 18 typical pretriggered acquisition figure 4 19 counter timer applications C 5 custom cabling 1 4 ni com customer education D 1 professional services D 1 technical support D 1 D DACOOUT signal analog output signal connections 4 14 description table 4 4 signal summary table 4 6 DACIOUT signal analog output signal connections 4 14 description table 4 4 signal summary table 4 6 DAQ timing connections AIGATE signal 4 25 CONVERT signal 4 24 EXTSTROBE signal 4 27 SCANCLK signal 4 26 SISOURCE signal 4 26 STARTSCAN signal 4 22 TRIGI signal 4 19 TRIG2 signal 4 20 typical posttriggered acquisition figure 4 18 typical pr
32. Bus Interface TYPO P Master slave National Instruments Corporation A 11 NI PCI 6110 6111 User Manual Appendix A Specifications Power Requirement 5 VDC 5 NI PCI 61 O cion 2 5 A NEPCT 6111 IR 2 0A Power available at I O connector 4 65 to 45 25 VDCat 1 A Physical Dimensions not including connectors 31 2 by 10 6 cm 12 3 by 4 2 in I O connector seen 68 pin male SCSI II type Maximum Working Voltage Maximum working voltage refers to the signal voltage plus the common mode voltage Channel to earth esses x10 V installation category I Channel to channel x10 V installation category I Environmental Operating temperature seess 0 to 45 C Storage temperature esses 20 to 70 C Hugndity A aet 5 to 90 RH noncondensing Maximum altitude 2000 meters Pollution degree indoor use only 2 Safety The NI PCI 6110 6111 meets the requirements of the following standards for safety and electrical equipment for measurement control and laboratory use e EN 61010 1 1993 A2 1995 IEC 61010 1 1990 A2 1995 e UL3111 1 1994 e CAN CSA c22 2 no 1010 1 1992 A2 1997 NI PCI 6110 6111 User Manual A 12 ni com Appendix A Specifications Electromagnetic Compatibility CE C Tick and FCC Part 15 Class A Compliant Electrical emissions
33. C National Instruments Corporation Glossary the Canadian Department of Communications Declaration of Conformity a technique that locates an edge of an analog signal such as the edge of a square wave electrically erasable programmable read only memory ROM that can be erased with an electrical signal and reprogrammed electromechanical compliance effective number of bits a measure of the actual performance of an A D converter after its various noise sources and nonlinearities are included The ENOB is computed as the signal to noise ratio of the A D converter in dB minus 1 76 divided by 6 02 Also called effective bits electrostatic discharge a high voltage low current discharge of static electricity that can damage sensitive electronic components Electrostatic discharge voltage can easily range from 1 000 to 10 000 V external strobe signal farads Federal Communications Commission G 5 NI PCI 6110 6111 User Manual Glossary FIFO floating signal sources FREQ OUT ft G gain GATE GPCTR GPCTRO GATE GPCTRO OUT GPCTRO SOURCE GPCTRO UP DOWN GPCTRI GATE GPCTRI OUT GPCTRI SOURCE NI PCI 6110 6111 User Manual first in first out memory buffer FIFOs are often used on DAQ devices to temporarily store incoming or outgoing data until that data can be read or written For example an analog input FIFO stores the results of A D conversions until the data can be read into system memory P
34. COOUT DACIOUT DAQ DAQ STC dB DC DGND DI DIFF DIO DIP dithering DMA DNL DO NI PCI 6110 6111 User Manual digital to analog digital to analog converter an electronic device often an integrated circuit that converts a digital number into a corresponding analog voltage or current analog channel 0 voltage output signal analog channel 1 voltage output signal data acquisition a system that uses the computer to collect receive and generate electrical signals data acquisition system timing controller an application specific integrated circuit ASIC for the system timing requirements of a general A D and D A system decibel the unit for expressing a logarithmic measure of the ratio of two signal levels dB 20log10 V1 V2 for signals in volts direct current digital ground signal digital input differential mode digital input output dual inline package the addition of Gaussian noise to an analog input signal direct memory access a method by which data can be transferred to from computer memory from to a device or memory on the bus while the processor does something else DMA is the fastest method of transferring data to from computer memory differential nonlinearity a measure in least significant bit of the worst case deviation of code widths from their ideal value of 1 LSB digital output G 4 ni com DOC DoC E edge detection EEPROM EMC ENOB ESD EXTSTROBE FC
35. DAQ NI PCI 6110 6111 User Manual Mulitfunction 1 0 Devices for PCI Bus Computers Y NATIONAL April 2002 Edition y INSTRUMENTS Part Number 321759D 01 Worldwide Technical Support and Product Information ni com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 683 0100 Worldwide Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 011 3262 3599 Canada Calgary 403 274 9391 Canada Montreal 514 288 5722 Canada Ottawa 613 233 5949 Canada Qu bec 514 694 8521 Canada Toronto 905 785 0085 China Shanghai 021 6555 7838 China ShenZhen 0755 3904939 Czech Republic 02 2423 5774 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Greece 30 1 42 96 427 Hong Kong 2645 3186 India 91 80 4190000 Israel 03 6393737 Italy 02 413091 Japan 03 5472 2970 Korea 02 3451 3400 Malaysia 603 9596711 Mexico 001 800 010 0793 Netherlands 0348 433466 New Zealand 09 914 0488 Norway 32 27 73 00 Poland 0 22 3390 150 Portugal 351 210 311 210 Russia 095 238 7139 Singapore 6 2265886 Slovenia 386 3 425 4200 South Africa 11 805 8197 Spain 91 640 0085 Sweden 08 587 895 00 Switzerland 056 200 51 51 Taiwan 02 2528 7227 United Kingdom 01635 523545 For further support information see the Technical Support and Professional Services appendix To comment on the documentation send email to techpubseni com
36. DAQ sequence even if another PFI is externally triggering the acquisition The output is an active high pulse with a pulse width of 25 to 50 ns This output is set to high impedance at startup Figures 4 11 and 4 12 show the timing requirements for TRIGI National Instruments Corporation 4 19 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals NI PCI 6110 6111 User Manual Rising edge polarity Falling edge polarity ty 10 ns minimum Figure 4 11 TRIG1 Input Signal Timing i 1 i tw 25 50 ns i I Figure 4 12 TRIG1 Output Signal Timing The device also uses TRIGI to initiate pretriggered DAQ operations In most pretriggered applications TRIGI is generated by a software trigger Refer to the TRIG2 signal description for a complete description of the use of TRIGI and TRIG2 in a pretriggered DAQ operation TRIG2 Signal Any PFI pin can receive as an input the TRIG2 signal which is available as an output on the PFII TRIG2 pin Refer to Figure 4 10 for the relationship of TRIG2 to the DAQ sequence As an input TRIG2 is configured in the edge detection mode You can select any PFI pin as the source for TRIG2 and configure the polarity selection for either rising or falling edge The selected edge of TRIG2 initiates the posttriggered phase of a pretriggered DAQ sequence In pretriggered mode the TRIGI signal initiates the data acquisition The scan counter SC indicate
37. DATE WFTRIG AO Start Trigger ND OUT START TRIGGER A Caution If you enable a PFI line for output do not connect any external signal source to it Connecting external signals to enabled PFI lines can damage the device the computer and the connected equipment NI PCI 6110 6111 User Manual What are the power on states of the PFI and DIO lines on the I O connector At system power on and reset both the PFI and DIO lines are set to high impedance by the hardware This means that the device circuitry is not actively driving the output either high or low However these lines may have pull up or pull down resistors connected to them as shown in Table 4 3 I O Signal Summary for the NI PCI 6110 6111 These resistors weakly pull the output to either a logic high or logic low state For example DIO 0 is in the high impedance state after power on and Table 4 3 shows that there is a 50 kQ pull up resistor This pull up resistor sets the DIO 0 pin to a logic high when the output is in a high impedance state C 6 ni com Technical Support and Professional Services Visit the following sections of the NI Web site at ni com for technical support and professional services e Support Online technical support resources include the following Self Help Resources For immediate answers and solutions visit our extensive library of technical support resources available in English Japanese and Spanish at ni com suppo
38. DGND PFIO TRIG1 PFH TRIG2 DGND 5 V DGND PFI5 UPDATE PFI6 WFTRIG DGND PFI9 GPCTRO_GATE GPCTRO_OUT FREQ_OUT w o wj A 68 67 C2 nv 66 wo hurt 65 ww o 64 N c 63 Nm 00 62 n Y 61 N o 60 Nh al 59 Nm A 58 N wo 57 N N 56 n iri 55 N o 54 E c 53 a 52 Em 51 o 50 E al 49 A 48 A w 47 D 46 45 A o 44 o 43 42 41 40 39 38 37 36 v BR OH o joo 35 ACHO ACHOGND ACH1 ACH2 1 ACH2GND ACH3 1 NC NC NC NC NC NC NC AOGND AOGND DGND DIOO DIO5 DGND DIO2 DIO7 DIO3 SCANCLK EXTSTROBE DGND PFI2 CONVERT PFI3 GPCTR1_SOURCE PFI4 GPCTR1_GATE GPCTR1_OUT DGND PFI7 STARTSCAN PFI8 GPCTRO_SOURCE DGND DGND 1 NC on NI PCI 6111 Figure B 1 68 Pin Connector Pin Assignment for the NI PCI 6110 6111 NI PCI 6110 6111 User Manual B 2 ni com Appendix B National Instruments Corporation DIOO DGND AOGND NC DAC1OUT DACOOUT NC NC NC NC NC NC NC NC PFIO TRIG1 ACH3 1 ACH3 1 ACH2 1 ACH2 1 ACH1 ACH1 ACHO ACHO ACH lt 0 3 gt GND ACH lt 0 3 gt GND Nm al 50 m ES 49 N 9v 48 M N 47 m A 46 N o
39. FCC rules have restrictions regarding the locations where FCC Class A products can be operated FCC Class B products display either a FCC ID code starting with the letters EXN Trade Name Model Number or the FCC Class B compliance mark that appears as shown here on the right Fe Tested to Comply with FCC Standards Consult the FCC Web site at fcc gov for more information FCC DOC Warnings This equipment generates and uses radio frequency energy and if not installed and used in strict accordance with the instructions in this manual and the CE Mark Declaration of Conformity may cause interference to radio and television reception Classification requirements are the same for the FCC and the Canadian DOC FOR HOME OR OFFICE USE Changes or modifications not expressly approved by National Instruments could void the user s authority to operate the equipment under the FCC Rules Class A Federal Communications Commission This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residentia
40. I PCI 6110 6111 NI DAQ carries out many of the complex interactions such as programming interrupts between the computer and the DAQ hardware NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to the code Whether you use LabVIEW Measurement Studio or other ADEs your application uses NI DAQ as illustrated in Figure 1 1 1 2 ni com Chapter 1 Introduction Conventional Programming Environment LabVIEW Measurement Studio or VI Logger NI DAQ Personal DAQ Hardware I gt Computer or Workstation Figure 1 1 The Relationship Between the Programming Environment NI DAQ and the Hardware To download a free copy of the most recent version of NI DAQ click Download Software at ni com National Instruments ADE Software LabVIEW features interactive graphics a state of the art interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of virtual instruments for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW Measurement Studio which includes LabWindows CVI tools for Visual C and tools for Visual Basic is a development suite that allows you to use ANSI C Visual C and Visual Basic to design test and measurement software For C developers Measurement Studio includes LabWindows CVL a f
41. I PCI 6110 6111 has bipolar inputs only Bipolar input means that the input voltage range is between V sef 2 and V ief 2 These devices have a bipolar input range of 20 V x10 V You can program range settings on a per channel basis so that you can uniquely configure each AI channel The software programmable gain on these devices increases flexibility by matching the input signal ranges to those that the ADC can accommodate The NI PCI 6110 6111 has gains of 0 2 0 5 1 2 5 10 20 and 50 and it is suited for a wide variety of signal levels With the proper gain setting you can use the full resolution of the ADC to measure the input signal Table 3 1 shows the overall input range and precision according to the chosen gain Table 3 1 Actual Range and Measurement Precision Range Configuration Gain Actual Input Range Precision 10 to 10 V 0 2 50 to 50 V 24 4 mV 0 5 20 to 20 V 9 77 mV 1 0 10 to 10 V 4 88 mV 2 0 5 to 5 V 2 44 mV 5 0 2to 42 V 976 56 uV 10 0 to 41 V 488 28 uV 20 0 500 to 500 mV 244 14 u V 50 0 200 to 200 mV 97 66 uV 1 Caution The NI PCI 6110 6111 is not designed for input voltages greater than 42 V even if a user installed voltage divider reduces the voltage to within the input range of the device Input voltages greater than 42 V can damage the NI PCI 6110 6111 any device connected to it and the host computer Overvoltage can also cause an electric shock ha
42. LUDING THE ABOVE RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE IMPAIRED BY ADVERSE FACTORS INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY COMPUTER HARDWARE MALFUNCTIONS COMPUTER OPERATING SYSTEM SOFTWARE FITNESS FITNESS OF COMPILERS AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION INSTALLATION ERRORS SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES TRANSIENT FAILURES OF ELECTRONIC SYSTEMS HARDWARE AND OR SOFTWARE UNANTICIPATED USES OR MISUSES OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER COLLECTIVELY TERMED SYSTEM FAILURES ANY APPLICATION WHERE A SYSTEM FAILURE WOULD CREATE A RISK OF HARM TO PROPERTY OR PERSONS INCLUDING THE RISK OF BODILY INJURY AND DEATH SHOULD NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE TO AVOID DAMAGE INJURY OR DEATH THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES INCLUDING BUT NOT LIMITED TO BACK UP OR SHUT DOWN MECHANISMS BECAUSE EACH END USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS TESTING PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL INSTRUMENTS THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESP
43. NI PCI 6110 6111 1 0 Connector Signal Descriptions Table 4 2 Signal Descriptions for 1 0 Connector Pins Signal Name Reference Direction Description ACH lt 0 3 gt GND Analog Input Channels 0 through 3 ground These pins are the bias current return point for differential measurements ACH lt 2 3 gt GND signals are no connects on the NI PCI 6111 ACH lt 0 3 gt ACH lt 0 3 gt GND Input Analog Input Channels 0 through 3 These pins are routed to the terminal of the respective channel amplifier ACH lt 2 3 gt signals are no connects on the NI PCI 6111 National Instruments Corporation 4 3 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals Table 4 2 Signal Descriptions for I O Connector Pins Continued Signal Name Reference Direction Description ACH lt 0 3 gt ACH lt 0 3 gt GND Imput Analog Input Channels 0 through 3 These pins are routed to the terminal of the respective channel amplifier ACH lt 2 3 gt signals are no connects on the NI PCI 6111 DACOOUT AOGND Output Analog Channel 0 Output This pin supplies the voltage output of AO channel 0 DACIOUT AOGND Output Analog Channel 1 Output This pin supplies the voltage output of AO channel 1 AOGND Analog Output Ground The AO voltages are referenced to this node DGND Digital Ground This pin supplies the referen
44. ONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE INCORPORATED IN A SYSTEM OR APPLICATION INCLUDING WITHOUT LIMITATION THE APPROPRIATE DESIGN PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION Compliance FCC Canada Radio Frequency Interference Compliance Determining FCC Class The Federal Communications Commission FCC has rules to protect wireless communications from interference The FCC places digital electronics into two classes These classes are known as Class A for use in industrial commercial locations only or Class B for use in residential or commercial locations Depending on where it is operated this product could be subject to restrictions in the FCC rules In Canada the Department of Communications DOC of Industry Canada regulates wireless interference in much the same way Digital electronics emit weak signals during normal operation that can affect radio television or other wireless products By examining the product you purchased you can determine the FCC Class and therefore which of the two FCC DOC Warnings apply in the following sections Some products may not be labeled at all for FCC if so the reader should then assume these are Class A devices FCC Class A products only display a simple warning statement of one paragraph in length regarding interference and undesired operation Most of our products are FCC Class A The
45. Output RTSI Bus Analog Bus Digital 1 0 8 Digital VO 1 Timing Control Interface Output Interface DACO AO Control DAC 4 FIFO Data 32 DAC1 Analog Input Input Mode Calibration i l 4 DACs Figure 3 2 NI PCI 6111 Block Diagram The AI section for the NI PCI 6110 6111 is software configurable You can select different AI configurations through application software The following sections describe in detail each AI setting The NI PCI 6110 6111 supports only differential DIFF inputs DIFF input mode provides up to four channels on the NI PCI 6110 and up to two channels on the NI PCI 6111 3 Note The inputs are differential only in the sense that the ground loops are broken The negative input is not intended to carry signals of interest rather it provides a DC reference point for the positive input which may be different than ground NI PCI 6110 6111 User Manual A channel configured in DIFF input mode uses two AI channel lines One line connects to the positive input of the device programmable gain instrumentation amplifier PGIA and the other connects to the negative 3 2 ni com Chapter 3 Hardware Overview input of the PGIA For more information about DIFF input mode refer to the Connecting Analog Input Signals section of Chapter 4 Connecting Signals which contains diagrams showing the signal paths for DIFF input mode Input Polarity and Input Range The N
46. PDATE DIO Voc 0 5 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PFI6 WFTRIG DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 kQ pu PFI7 STARTSCAN DIO Vec 0 5 3 5 at Vcc 0 4 5at0 4 1 5 50 KQ pu PFIS GPCTRO_SOURCE DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 kO pu PFI9 GPCTRO GATE DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 kQ pu GPCTRO_OUT DO 3 5 at Vec 0 4 5at0 4 1 5 50 kO pu FREQ OUT DO 3 5 at Vec 0 4 5at0 4 1 5 50 KQ pu 1 Applies to gain lt 1 impedance refers to ACH lt 0 3 gt Applies to gain gt 1 impedance refers to ACH lt 0 3 gt AI DIO Analog Input Digital I O DO Digital Output pd pull down pu pull up The tolerance on the 50 KQ pull up and pull down resistors is very large Actual value may range between 17 and 100 KQ National Instruments Corporation 4 7 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals Connecting Analog Input Signals The NI PCI 6110 6111 channels are configured as pseudodifferential inputs The input signal of each channel ACH lt 0 3 gt is tied to the positive input of the PGIA and each reference signal ACH lt 0 3 gt is tied to the negative input of the PGIA The inputs are differential only in the sense that ground loops are broken The reference signal ACH lt 0 3 gt is not intended to carry signals of interest but only to provide a DC reference point for ACH lt 0 3 gt that may be different from grou
47. PDATE signal 4 29 WFTRIG signal 4 28 ni com Index Web professional services D 1 technical support D 1 WFTRIG signal See also PFI6 WFTRIG signal timing connections 4 28 using with UPDATE signal 4 29 wiring considerations 4 36 working voltage range 4 13 worldwide technical support D 1 O National Instruments Corporation 1 11 NI PCI 6110 6111 User Manual
48. Q hardware documentation This documentation has detailed information about the DAQ hardware that plugs into or is connected to the computer Use this documentation for hardware installation and configuration instructions specification information about the DAQ hardware and application hints e Software documentation You may have both application software and NI DAQ documentation NI application software includes LabVIEW Measurement Studio and others After you set up the hardware system use either the application software documentation or the NI DAQ documentation to help you write your application If you have a large complicated system it is worthwhile to look through the software documentation before you configure the hardware Xii ni com About This Manual Related Documentation The following documents contain information that you might find helpful O National Instruments Corporation The NI Developer Zone tutorial Field Wiring and Noise Considerations for Analog Signals located at ni com zone PCI Local Bus Specification Revision 2 2 DAQ Quick Start Guide located at ni com manuals DAQ STC Technical Reference Manual located at ni com manuals NI DAQ User Manual for PC Compatibles located at ni com manuals NI DAQ Function Reference Manual for NI DAQ versions 6 6 or earlier located at ni com manuals NI DAQ Function Reference Help for NI DAQ versions 6 7 or later which is accessible from Start Program
49. Sign l terr e te Baayen seers Waveform Generation Timing Connections eeeeeee WPETRIG Signal rre ge t eo to e UPDATES Signal wins inh epe EHE ee ee pene VISOURCE Signalo e tror repe ee RS General Purpose Timing Signal Connections see GPCTRO SOURCE Sitnal music ee eee GPCTRO GATE Signal eben GPCTRO OUT Signal ttr e ett pete ep GPCTRO UP DOWN Signal eere GPCTRI SOURCE Siena until en GPCTRI GATE Signal 5 52 nitet Rte GPCTRI OUT Signal eie dt NI PCI 6110 6111 User Manual Viii ni com Contents GPCTRI UP DOWN Signal eee 4 35 FREQ OUT Signal ete erento eee 4 36 Field Wiring Considerations eese eene enne 4 36 Chapter 5 Calibration Loading Calibration Constant seeseeeseeseeeeeee nennen rennen nennen 5 1 Self Calibration Her e a id 5 2 External Calibration eee a a a Dee Ee ER ans 5 2 Appendix A Specifications Appendix B Cable Connector Descriptions Appendix C Common Questions Appendix D Technical Support and Professional Services Glossary Index National Instruments Corporation ix NI PCI 6110 6111 User Manual About This Manual Conventions This manual describes the electrical and mechanical aspects of the National Instruments PCI 6110 6111 data acquisition DAQ device and contains information concerning its operation and programming The device is a high perform
50. al Stability Offset temperature coefficient Gain temperature coefficient Internal reference External reference Onboard calibration reference Level e eR dex Temperature coefficient Long term stability Number of channels Compatibility eese Digital logic levels 500 uV C 50 ppm C 25 ppm C 5 000 V 22 5 mV actual value stored in EEPROM 0 6 ppm C max 6 ppm 1 000 h 8 input output TTL CMOS Level Min Max Input low voltage 0 0 V 0 8 V Input high voltage 2 0V 5 0 V Input low current Vin 0 V 320 WA Input high current V 2 5 V 10 uA Output low voltage Io 24 mA 0 4 V Output high voltage oy 13 mA 4 35 V Power on state ccccccccnnnninnnnnnnnanananononos Data transfers cccccccncnnnnnnnanananannnononons A 8 Input high impedance Programmed I O ni com Timing 1 0 Appendix A Specifications General Purpose Up Down Counter Timers Number of channels 2 Resolution eeee 24 bits Compatibility eee TTL CMOS Digital logic levels Level Minimum Maximum Input low voltage OV 0 8 V Input high voltage 2V 5V Input low current Vi 0 V 320 uA Input high
51. ance multifunction analog digital and timing I O device for PCI bus computers Supported functions include analog input AJ analog output AO digital I O DIO and timing I O TIO lt gt Pg bold italic monospace The following conventions appear in this manual Angle brackets that contain numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example DBIO lt 3 0 gt The symbol leads you through nested menu items and dialog box options to a final action The sequence File Page Setup Options directs you to pull down the File menu select the Page Setup item and select Options from the last dialog box This icon denotes a note which alerts you to important information This icon denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash When this symbol is marked on the product see the Unpacking section of Chapter 1 Introduction for precautions to take Bold text denotes items that you must select or click on in the software such as menu items and dialog box options Bold text also denotes parameter names and hardware labels Italic text denotes variables emphasis a cross reference or an introduction to a key concept This font also denotes text that is a placeholder for a word or value that you must supply Text in this font denotes text or characters that you should enter from the keyboard se
52. and a maximum timing resolution of 50 ns The DAQ STC makes possible such applications as buffered pulse generation equivalent time sampling and seamless changes to the sampling rate The NI PCI 6110 6111 uses the Real Time System Integration RTSI bus to easily synchronize several measurement functions to a common trigger or timing event The RTSI bus consists of the RTSI bus interface and a ribbon cable to route timing and trigger signals between several functions on as many as five DAQ devices in the computer Detailed specifications of the NI PCI 6110 6111 are in Appendix A Specifications National Instruments Corporation 1 1 NI PCI 6110 6111 User Manual Chapter 1 What You Need to Get Started To set up and use the NI PCI 6110 6111 you will need the following items Q NIPCI 6110 6111 NI PCI 6110 6111 User Manual NI DAQ a a C The computer a Optional One of the following software packages and documentation LabVIEW Windows or Mac OS Measurement Studio Windows VI Logger Windows Software Programming Choices NI DAQ NI PCI 6110 6111 User Manual When programming the National Instruments DAQ hardware you can use NI application development environment ADE software or other ADEs In either case you use NI DAQ NI DAQ which ships with the NI PCI 6110 6111 has an extensive library of functions that you can call from the ADE These functions allow you to use all the features of the N
53. cal accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow th
54. ce for the digital signals at the I O connector as well as the 5 VDC supply DIO lt 0 7 gt DGND Input or Output Digital I O signals DIO6 and 7 can control the up down signal of general purpose counters 0 and 1 respectively 5 V DGND Output 5 VDC Source These pins are fused for up to 1 A of 5 V supply The fuse is self resetting SCANCLK DGND Output Scan Clock This pin pulses once for each A D conversion when enabled The low to high edge indicates when the input signal can be removed from the input or switched to another signal EXTSTROBE DGND Output External Strobe This output can be toggled under software control to latch signals or trigger events on external devices PFIO TRIG1 DGND Input Output PFIO Trigger 1 As an input this is either a PFI or the source for the hardware analog trigger PFI signals are explained in the Timing Connections section Refer to the Analog Trigger section of Chapter 3 Hardware Overview for more information about the hardware analog trigger As an output this is the TRIGI signal In posttrigger DAQ sequences a low to high transition indicates the initiation of the DAQ sequence In pretrigger applications a low to high transition indicates the initiation of the pretrigger conversions PFII TRIG2 DGND Input Output PFI1 Trigger 2 As an input this is a PFL As an output this is the TRIG2 s
55. ctions of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions and code excerpts National Instruments Corporation Xi NI PCI 6110 6111 User Manual About This Manual NI DAQ NI PCI 6110 6111 PCI Platform NI DAQ refers to the NI DAQ driver software for Macintosh or PC compatible computers unless otherwise noted This phrase refers to either the NI PCI 6110 or NI PCI 6111 device PCI stands for Peripheral Component Interconnect PCI is a high performance expansion bus architecture originally developed by Intel to replace ISA and EISA Text in this font denotes a specific platform and indicates that the text following it applies only to that platform National Instruments Documentation NI PCI 6110 6111 User Manual The NI PCI 6110 6111 User Manual is one piece of the documentation set for the DAQ system You could have any of several types of documentation depending on the hardware and software in the system Refer to ni com manuals to download the following documents e Accessory installation guides or manuals If you use accessory products read the terminal block and cable assembly installation guides They explain how to physically connect the relevant pieces of the system Consult these guides when you make the connections DA
56. current Vin 5 V 10 uA Output low voltage IOL 24 mA 0 4 V Output high voltage IOH 13 mA 4 35 V Base clocks available 20 MHz 100 kHz Base clock accuracy 0 01 Max source frequency se 20 MHz Min source pulse duration 10 ns edge detect mode Min gate pulse duration 10 ns edge detect mode Data transfers occccccccncnoninncnnnanananononons DMA interrupts programmed I O DMA modes ee Scatter gather single transfer demand transfer Frequency Scaler Number of channels 1 RESOLUCION tidad 4 bits 1 in 16 Compatibility eee TTL CMOS National Instruments Corporation A 9 NI PCI 6110 6111 User Manual Appendix A Specifications Triggers NI PCI 6110 6111 User Manual Digital logic levels Level Minimum Maximum Input low voltage OV 0 8 V Input high voltage 2V 5V Output low voltage Iou 5 mA 0 4 V Output low voltage Iut 3 5 mA 4 35 V Base clocks available Base clock accuracy Data transfers cccccccccncninnnanananannnnnnnos Analog Trigger Number of triggers sess Purpose Analog input sessss Analog output esses General purpose counter
57. d as a transducer for linear or rotary position parts per million the measure of the stability of an instrument and its capability to give the same measurement over and over again for the same input signal the technique used on a DAQ device to keep a continuous buffer filled with data so that when the trigger conditions are met the sample includes the data leading up to the trigger condition pseudodifferential input channels are all referred to a common ground but this ground is not directly connected to the computer ground pull up G 10 ni com RAM range referenced signal sources resolution RH rms RTD RTSI bus RTSI OSC S s SC scan interval O National Instruments Corporation Glossary random access memory the maximum and minimum parameters between which a sensor instrument or device operates with a specified set of characteristics signal sources with voltage signals that are referenced to a system ground such as the earth or a building ground Also called grounded signal sources the smallest signal increment that can be detected by a measurement system Resolution can be expressed in bits in proportions or in percent of full scale For example a system has 12 bit resolution one part in 4 096 resolution and 0 0244 of full scale relative humidity root mean square resistive temperature detector a metallic probe that measures temperature based upon its coefficient of resistivity
58. d configuring C 2 timing and digital I O C 4 R Real Time System Integration See RTSI related documentation xiii requirements for getting started 1 2 RTSI bus overview 1 1 signal connection figure 3 11 timing signal routing 3 8 device and RTSI clocks 3 10 trigger lines 3 11 signal connection figure 3 11 specifications A 11 NI PCI 6110 6111 User Manual Index S safety overview 1 5 specifications A 12 safety information 1 5 safety specifications A 12 SCANCLK signal description table 4 4 signal summary table 4 6 timing connections 4 26 timing diagram 4 27 self calibration 5 2 self resetting fuse 4 16 C 2 signal connections analog input 4 8 analog output 4 14 differential measurements common mode signal rejection 4 12 connection considerations 4 10 floating signal sources 4 12 ground referenced signal sources 4 11 overview 4 10 recommended configuration table 4 10 digital I O 4 15 field wiring considerations 4 36 I O connector connector details table 4 1 exceeding maximum ratings caution 4 1 pin assignments 50 pin connector figure 4 3 68 pin connector figure 4 2 signal descriptions table 4 3 signal summary table 4 6 power connections 4 16 timing connections DAQ timing connections AIGATE signal 4 25 NI PCI 6110 6111 User Manual 1 8 CONVERT signal 4 24 EXTSTROBE signal 4 27 overview 4 18 SCANCLK signal 4 26 SISOURCE signal 4 26 STARTSCAN
59. dB frequency for input amplitude at 96 of the input range 0 3 dB 2 Measured at 100 kHz 3100 production tested at 100 kHz 4All input ranges DC to 60 Hz SLSB ms not including quantization Stability Recommended warm up time 15 minutes Offset temperature coefficient PHOS AID aeree eine 5 wV C POSUG AI aiii etre 50 uV C Gain temperature coefficient 20 ppm C National Instruments Corporation A 5 NI PCI 6110 6111 User Manual Appendix A Specifications Analog Output NI PCI 6110 6111 User Manual Onboard calibration reference Level acte NO ss Temperature coefficient Long term stability Output Characteristics Number of channels Resolution eee Max update rate 1 channel eene 2 channel d ssi FIFO buffer size Data transfers DMA modes occccccccccncnnnnncnanananananononnnns Transfer Characteristics Relative accuracy INL DN ista iaa Offset error occccccccnnnnnnnnnnananananananononos Gain error relative to internal reference A 6 UT 5 000 V 22 5 mV actual value stored in EEPROM suis 0 6 ppm C max 6 ppm 1 000 h 2 voltage 16 bits 1 in 65 536 4 MS s system dependent 2 5 MS s system dependent 2 048 samples DMA interrupts programmed I O Scatter ga
60. dealer or an experienced radio TV technician for help Canadian Department of Communications This Class B digital apparatus meets all requirements of the Canadian Interference Causing Equipment Regulations Cet appareil num rique de la classe B respecte toutes les exigences du R glement sur le mat riel brouilleur du Canada Compliance to EU Directives Readers in the European Union EU must refer to the Manufacturer s Declaration of Conformity DoC for information pertaining to the CE Mark compliance scheme The Manufacturer includes a DoC for most every hardware product except for those bought for OEMs if also available from an original manufacturer that also markets in the EU or where compliance is not required as for electrically benign apparatus or cables To obtain the DoC for this product click Declaration of Conformity at ni com hardref nsf This Web site lists the DoCs by product family Select the appropriate product family followed by your product and a link to the DoC appears in Adobe Acrobat format Click the Acrobat icon to download or read the DoC Certain exemptions may apply in the USA see FCC Rules 815 103 Exempted devices and 15 105 c Also available in sections of CFR 47 The CE Mark Declaration of Conformity will contain important supplementary information and instructions for the user or installer Contents About This Manual Gn IBI EE xi National Instruments Documentation cecceecesecec
61. derived from MAINS and specially protected internal MAINS derived circuits e Installation category II is for measurements performed on circuits directly connected to the low voltage installation This category refers to local level distribution such as that provided by a standard wall outlet MAINS is defined as the electricity supply system to which the equipment concerned is designed to be connected either for powering the equipment or for measurement purposes NI PCI 6110 6111 User Manual 1 6 ni com Chapter 1 Introduction Examples of installation category II are measurements on household appliances portable tools and similar equipment Installation category III is for measurements performed in the building installation This category is a distribution level referring to hardwired equipment that does not rely on standard building insulation Examples of installation category III include measurements on distribution circuits and circuit breakers Other examples of installation category III are wiring including cables bus bars junction boxes switches socket outlets in the building fixed installation and equipment for industrial use such as stationary motors with a permanent connection to the building fixed installation Installation category IV is for measurements performed at the source of the low voltage 1 000 V installation Examples of category IV are electric meters and measurements on primary overcurrent pr
62. devices and hardware 1 2 3 4 National Instruments Corporation Power off and unplug the computer Remove the top cover or access port to the I O channel Remove the expansion slot cover on the back panel of the computer Ground yourself using a grounding strap or by holding a grounded object Follow the ESD protection precautions described in the Unpacking section of Chapter 1 Introduction Insert the NI PCI 6110 6111 into a PCI system slot Gently rock the device to ease it into place It may be a tight fit but do not force the device into place 2 1 NI PCI 6110 6111 User Manual Chapter 2 Installing and Configuring the NI PCI 6110 6111 6 Ifrequired screw the mounting bracket of the NI PCI 6110 6111 to the back panel rail of the computer 7 Visually verify the installation by making sure the device is not touching other devices or components and is fully inserted into the slot Replace the cover 9 Plugin and power on the computer The NI PCI 6110 6111 is now installed You are now ready to configure the device Refer to the software documentation for configuration instructions Configuring the Device The NI standard architecture for data acquisition and the PCI bus specification make the NI PCI 6110 6111 completely software configurable You must perform two types of configuration on the NI PCI 6110 6111 bus related and data acquisition related configuration The NI PCI 6110 6111 is fully compat
63. e Select Signal call in NI DAQ to configure the output line By default all timing I O lines except EXTSTROBE are high impedance What are the PFIs and how do I configure these lines PFIs are Programmable Function Inputs These lines serve as connections to almost all internal timing signals If you are using NI DAQ or LabWindows CVI use the Select Signal function to route internal signals to the I O connector route external signals to internal timing sources or tie internal timing signals together If you are using NI DAQ with LabVIEW and you want to connect external signal sources to the PFI lines you can use AI Clock Config AI Trigger Config AO Clock Config AO Trigger and Gate Config and Counter Set Attribute advanced level VIs to indicate which function the connected signal serves Use the Route Signal VI to enable the PFI lines to output internal signals National Instruments Corporation C 5 NI PCI 6110 6111 User Manual Appendix C Common Questions Table C 1 Signal Name Equivalencies Hardware LabVIEW Signal Name Route Signal NI DAQ Select Signal AIGATE ND IN EXTERNAL GATE AOGATE ND OUT EXTERNAL GATE CONVERT AI Convert ND IN CONVERT SISOURCE ND IN SCAN CLOCK TIMEBASE STARTSCAN AI Scan Start ND IN SCAN START TRIGI AI Start Trigger ND IN START TRIGGER TRIG2 AI Stop Trigger ND IN STOP TRIGGER UISOURCE ND OUT UPDATE CLOCK TIMEBASE UPDATE AO Update ND OUT UP
64. e from any PFI when you want external control This flexible routing scheme reduces the need to change the physical wiring to the device I O connector for applications requiring alternative wiring You can individually enable each PFI pin to output a specific internal timing signal For example if you need the STARTSCAN signal as an output on the I O connector software can turn on the output driver for the PFI2 STARTSCAN pin UN Caution Be careful not to externally drive a PFI signal when it is configured as an output National Instruments Corporation 4 17 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals In edge detection mode the minimum pulse width required is 10 ns This setting applies for both rising edge and falling edge polarity settings Edge detect mode does not have a maximum pulse width requirement In level detection mode the PFIs themselves do not impose a minimum or maximum pulse width requirement but the particular timing signal being controlled can impose limits These requirements are listed later in this chapter DAQ Timing Connections The DAQ timing signals are TRIG1 TRIG2 STARTSCAN CONVERT AIGATE SISOURCE SCANCLK and EXTSTROBE Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received A typical posttriggered DAQ sequence is shown in Figure 4 9 On the NI PCI 6110 6111 each STARTSCAN pulse initiates one CONVERT pulse TRIG1
65. e National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks CVI DAQ STC LabVIEW Measurement Studio MITE National Instruments NI ni com NI DAQ and RTSI are trademarks of National Instruments Corporation Product and company names mentioned herein are trademarks or trade names of their respective companies Patents For patents covering National Instruments products refer to the appropriate location Help Patents in your software the patents txt file on your CD or ni com patents WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS 1 NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN 2 IN ANY APPLICATION INC
66. elf using a grounding strap or by holding a grounded object e Touch the antistatic package to a metal part of the computer chassis before removing the device from the package Remove the device from the package and inspect the device for loose components or any sign of damage Notify NI if the device appears damaged in any way Do not install a damaged device into the computer Store the NI PCI 6110 6111 in the antistatic envelope when not in use Safety Information The following section contains important safety information that you must follow when installing and using the product Do not operate the product in a manner not specified in this document Misuse of the product can result in a hazard You can compromise the safety protection built into the product if the product is damaged in any way If the product is damaged return it to NI for repair Do not substitute parts or modify the product except as described in this document Use the product only with the chassis modules accessories and cables specified in the installation instructions You must have all covers and filler panels installed during operation of the product National Instruments Corporation 1 5 NI PCI 6110 6111 User Manual Chapter 1 Introduction Do not operate the product in an explosive atmosphere or where there may be flammable gases or fumes Operate the product only at or below the pollution degree stated in the Appendix A Specifications Polluti
67. ences a low to high transition indicates the initiation of the waveform generation PFI7 STARTSCAN DGND Input PFI7 Start of Scan As an input this is a PFI Output As an output this is the STARTSCAN signal This pin pulses once at the start of each AI scan in the interval scan A low to high transition indicates the start of the scan PFI8 GPCTRO_SOURCE DGND Input PFI8 Counter 0 Source As an input this is a PFI Output As an output this is the GPCTRO_SOURCE signal This signal reflects the actual source connected to the general purpose counter 0 PFI9 GPCTRO_GATE DGND Input PFI9 Counter 0 Gate As an input this is a PFI Output As an output this is the GPCTRO_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 0 National Instruments Corporation 4 5 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals Table 4 2 Signal Descriptions for I O Connector Pins Continued Signal Name Reference Direction Description GPCTRO OUT DGND Output Counter 0 Output This output is from the general purpose counter O output FREQ OUT DGND Output Frequency Output This output is from the frequency generator output Table 4 3 1 0 Signal Summary for the NI PCI 6110 6111 Signal Impedance Protection Rise Typeand Input Volts Source S
68. ent Interconnect a high performance expansion bus architecture originally developed by Intel to replace ISA and EISA Itis achieving widespread acceptance as a standard for PCs and work stations it offers a theoretical maximum transfer rate of 132 MB s pull down Programmable Function Input PFIO trigger 1 PFI1 trigger 2 6 9 NI PCI 6110 6111 User Manual Glossary PFI2 CONVERT PFI3 GPCTR1 SOURCE PFI4 GPCTR1_GATE PFIS UPDATE PFI6 WFTRIG PFI7 STARTSCAN PFI8 GPCTRO_SOURCE PFI9 GPCTRO_GATE PGIA Plug and Play devices port posttriggering potentiometer ppm precision pretriggering pseudodifferential input pu NI PCI 6110 6111 User Manual PFI2 convert PFI3 general purpose counter 1 source PFI4 general purpose counter 1 gate PFIS update PFI6 waveform trigger PFI7 start of scan PFI8 general purpose counter 0 source PFI9 general purpose counter 0 gate Programmable Gain Instrumentation Amplifier devices that do not require DIP switches or jumpers to configure resources on the devices also called switchless devices 1 a communications connection on a computer or a remote controller 2 a digital port consisting of four or eight lines of digital input and or output the technique used on a DAQ device to acquire a programmed number of samples after trigger conditions are met an electrical device the resistance of which can be manually adjusted used for manual adjustment of electrical circuits an
69. ere is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTRI SOURCE unless you select some external source GPCTR1 GATE Signal Any PFI pin can externally input the GPCTR1_GATE signal which is available as an output on the PFI4 GPCTR1_GATE pin As an input GPCTR1 GATE is configured in edge detection mode You can select any PFI pin as the source for GPCTR1_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform such actions as starting and stopping the counter generating interrupts saving the counter contents and so on National Instruments Corporation 4 33 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals As an output GPCTR1_GATE monitors the actual gate signal connected to general purpose counter 1 even if the gate is being externally generated by another PFI This output is set to high impedance at startup Figure 4 31 shows the timing requirements for the GPCTR1 GATE signal Rising edge polarity Falling edge polarity tw 2 10 ns minimum Figure 4 31 GPCTR1_GATE Signal Timing GPCTR1 OUT Signal This signal is available only as an output on the GPCTR1_OUT pin The GPCTR1_OUT signal monitors the TC of general purpose counter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity i
70. eseeesceceseeeseeeeseceeeeseeeeareceeeeeaeeeaees xii Related Documentation ssnin nere Re ed ee ERR Bobi inte ine geatdvecsesvesdvvede xiii Chapter 1 Introduction Abo ttlie NI PCL 6110 6111 5 une Hed ditt 1 1 What You Need to Get Started eene eene e entren nenne nane nno rnnt 1 2 Software Programming Choices ssessesesseeseeeeeeeeneee nennen ren emeret enne 1 2 NEDAQ iii een IU d ts 1 2 National Instruments ADE Software ooooocnnoccnocccoonconcnonnnconncnonaconcconanconncnnnaranos 1 3 Optional Equipment eerte cate ri ente v EFE e pce es 1 4 Custom Cabin cian OR Ee e NER e PETRA S 1 4 Unpacking a er eed o exi RO E Ae deste eR e tec dal be ERU CS 1 5 Safety Information Ri ere EHE REPRE EHE RUN 1 5 Chapter 2 Installing and Configuring the NI PCI 6110 6111 Installing the Software tee e ttp eta det ep ts 2 1 Installing the Hardware ere id 2 1 Configuring the Device eoe em ee co e i eite 2 2 Chapter 3 Hardware Overview Analog Input 2 ue rema p menie elei 3 2 Input MOde 4 petere dae RT t ira ette 3 2 Input Polarity and Input Range seen 3 3 Considerations for Selecting Input Ranges esses 3 4 Input Coupling eie eremo re 3 4 An alog OUtplUt RN 3 4 Analog TtIgg r ste ii ad 3 4 Digital O t tite etti ts 3 8 Timing Signal Routing x tute did 3 8 Programmable Function Inputs eee 3 9 Device and RTSECIOGKS nope ondo war E i wie ag
71. etriggered acquisition figure 4 19 DAQ STC system timing controller overview 1 1 questions about C 4 DAQ STC See DAQ STC system timing controller data acquisition timing connections See DAQ timing connections DC input coupling 3 4 device clocks 3 10 device configuration 2 2 DGND signal description signal 4 4 digital I O connections 4 15 O National Instruments Corporation F3 Index power connections 4 16 signal summary table 4 6 timing connections 4 15 diagnostic resources D 1 differential measurements common mode signal rejection 4 12 connection considerations 4 10 ground referenced signal sources 4 11 nonreferenced signal sources 4 12 recommended configuration table 4 10 digital I O See also DGND signal See also DIO O 7 signal overview 3 8 questions about C 4 signal connections 4 15 specifications A 8 digital trigger overview 3 8 specifications A 11 DIO lt 0 7 gt signal description table 4 4 digital I O connections 4 15 signal summary table 4 6 documentation conventions xi National Instruments documentation xii online library D 1 related documentation xiii drivers instrument D 1 software D 1 dynamic characteristics specifications analog input A 4 analog output A 7 E EEPROM storage of calibration constants 5 1 electromagnetic compatibility specifications A 13 NI PCI 6110 6111 User Manual Index environmental noise avoiding 4 36 environmental speci
72. eturn is tied to the negative input of the PGIA Each differential signal uses two inputs one for the signal and one for its reference signal Differential signal connections reduce noise pickup and increase common mode noise rejection Differential signal connections also allow input signals to float within the common mode limits of the PGIA 4 10 ni com Chapter 4 Connecting Signals Differential Connections for Ground Referenced Signal Sources Figure 4 4 shows how to connect a ground referenced signal source to a channel on the NI PCI 6110 6111 Instrumentation Amplifier ACHO Ground Referenced Signal Source Measured Voltage ACHO Common Mode Noise and Ground Potential 7 7 7 C 0 v ACHOGND 1 0 Connector ACHO Connections Shown Figure 4 4 Differential Input Connections for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the device ground shown as V in Figure 4 4 National Instruments Corporation 4 11 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals Differential Connections for Nonreferenced or Floating Signal Sources Figure 4 5 shows how to connect a floating signal source to a channel on the NI PCI 6110 6111 Floating Signal Source ACHO o Inst
73. fications A 12 equipment optional 1 4 example code D 1 external calibration 5 2 EXTSTROBE signal description table 4 4 programming considerations note 4 27 signal summary table 4 6 timing connections 4 27 F field wiring considerations 4 36 FIFO analog DAQ sequences 4 23 specifications A 2 floating signal sources description 4 9 differential connections 4 10 recommended configuration table 4 10 FREQ_OUT signal description table 4 6 general purpose timing connections 4 36 signal summary table 4 7 frequently asked questions D 1 See also questions and answers fuse self resetting 4 16 C 2 G general purpose timing signal connections FREQ_OUT signal 4 36 GPCTRO_GATE signal 4 31 GPCTRO_OUT signal 4 32 GPCTRO_SOURCE signal 4 30 GPCTRO_UP_DOWN signal 4 32 GPCTR1_GATE signal 4 33 GPCTR1_OUT signal 4 34 GPCTR1_SOURCE signal 4 33 GPCTR1_UP_DOWN signal 4 35 NI PCI 6110 6111 User Manual 1 4 overview 4 30 getting started equipment 1 2 GPCTRO_GATE signal See also PFI9 GPCTRO_GATE signal general purpose counter timing summary figure 4 35 general purpose timing connections 4 31 timing diagram 4 32 GPCTRO_OUT signal description table 4 6 general purpose counter timing summary figure 4 35 general purpose timing connections 4 32 signal summary table 4 7 GPCTRO_SOURCE signal See also PFIS GPCTRO SOURCE general purpose counter timing summary figure 4 35 general purpose
74. g 1 4 optional equipment 1 4 overview 1 1 questions about analog input and output C 3 general information C 1 installing and configuring C 2 timing and digital I O C 4 requirements for getting started 1 2 software programming choices 1 2 unpacking 1 5 NI DAQ overview 1 2 questions about C 2 NI PCI 6110 6111 User Manual noise avoiding 4 36 rejecting common mode 4 12 0 online technical support D 1 optional equipment 1 4 output characteristics specifications A 6 output analog See analog output output voltage See 5 V signal See also voltage output specifications P PCI bus overview 1 1 PCI Local Bus Specification Revision 2 0 2 2 PCI 6110 6111 See NI PCI 6110 6111 PFIO TRIGI pin analog triggering 3 4 PFIO TRIGI signal See also TRIGI signal analog triggering 3 4 description table 4 4 signal summary table 4 6 PFII TRIG2 signal See also TRIG2 signal description table 4 4 signal summary table 4 6 PFI2 CONVERT signal See also CONVERT signal description table 4 5 signal summary table 4 6 PFI3 GPCTR1 SOURCE signal See also GPCTR1 SOURCE signal description table 4 5 signal summary table 4 7 PFI4 GPCTR1_GATE signal See also GPCTR1_GATE signal ni com description table 4 5 signal summary table 4 7 PFIS UPDATE signal See also UPDATE signal description table 4 5 signal summary table 4 7 PFI6 WFTRIG signal See also WFTRIG signal de
75. gering to initiate a DAQ sequence these devices also support analog triggering You can configure the analog trigger circuitry to accept either a direct analog input from the PFIO TRIGI pin on the I O connector or a postgain signal from the output of the PGIA on any of the channels as shown in Figures 3 3 and 3 4 The trigger level range for the direct analog channel is 10 V in 78 mV steps for the NI PCI 6110 6111 The range for the post PGIA trigger selection is simply the full scale range of the selected channel and the resolution is that range divided by 256 3 Note PFIO TRIGI pin is an analog input when configured as an analog trigger Therefore it is susceptible to crosstalk from adjacent pins which can result in false triggering when the pin is unconnected To avoid false triggering make sure this pin is connected to a low impedance signal source less than 1 kQ source impedance if you plan to enable this input using software NI PCI 6110 6111 User Manual 3 4 ni com Chapter 3 Hardware Overview Analog Input CHO Analog Input CH1 Analog Input CH2 Analog Input CH3 PFIO TRIG1 Mux Analog Trigger Circuit Lr DAQ STC Figure 3 3 Analog Trigger Block Diagram for the NI PCI 6110 Analog Input CHO PGIA Analog Input CH1 PGIA PFIO TRIG1
76. ges The same timing diagram but with the source signal inverted and referenced to the falling edge of the source signal applies when the counter is programmed to count falling edges The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on the NI PCI 6110 6111 Figure 4 33 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or low National Instruments Corporation 4 35 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by t and ty in Figure 4 33 The gate signal is not required to be held after the active edge of the source signal If you use an internal timebase clock the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the NI PCI 6110 6111 Figure 4 33 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 80 ns after the rising or falling edge of
77. ible with the industry standard PCI Local Bus Specification Revision 2 2 This allows the PCI system to automatically perform all bus related configurations Bus related configuration includes setting the device base memory address and interrupt channel Data acquisition related configuration which you must perform includes such settings as AI coupling and range and others You can modify these settings using NI DAQ or application level software such as LabVIEW Measurement Studio and VI Logger To configure the device using Measurement and Automation Explorer MAX refer to either the DAQ Quick Start Guide or to the NI DAQ User Manual for PC Compatibles For operating system specific installation and troubleshooting instructions refer to ni com support daq NI PCI 6110 6111 User Manual 2 2 ni com Hardware Overview This chapter presents an overview of the hardware functions on the NI PCI 6110 6111 Figures 3 1 and 3 2 show block diagrams for the NI PCI 6110 and the NI PCI 6111 respectively Generic Bus Interface Address Data CHO AL CHO CHO 12 CHO mx I lt gt lt 12 Bit ADC Latch Data 16 p CH1 p ALCH1 CHI 12 CH1 cH Mux lt 12 Bit ADC Latch Data 19 gt CH2 p AI CH2 CH2 12 CH2 Daum 6 H Mux K 12 Bit ADC Latch QOO gt CH3 p AI CH3 p CH3 Data 16 Mux 12 Bit ADC
78. ice generates the STARTSCAN signal If you are using internally generated conversions the first CONVERT appears when SI2 reaches zero If you select an external CONVERT the first external pulse after STARTSCAN generates a conversion The STARTSCAN pulses should be separated by at least one scan period A counter on the NI PCI 6110 6111 device internally generates STARTSCAN unless you select some external source This counter is started by the TRIGI signal and is stopped by either software or the SC Scans generated by either an internal or external STARTSCAN signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence may be gated by either the hardware AIGATE signal or software command register gate The NI PCI 6110 6111 uses a three point analog FIFO to digitize the input Although the point is digitized on the appropriate edge of STARTSCAN internally supplied unless you pass O for the scanTimebase it is not sent to NI DAQ until three additional edges of STARTSCAN clock the point Consequently you may not see the last three points of the acquisition If you are performing an internally timed acquisition NI DAQ generates three extra points to clock the data for you However if you perform an National Instruments Corporation 4 23 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals NI PCI 6110 6111 User Manual externally clocked acquisition NI DAQ does not know when the last poi
79. ignal In pretrigger applications a low to high transition indicates the initiation of the posttrigger conversions TRIG2 is not used in posttrigger applications NI PCI 6110 6111 User Manual ni com Chapter 4 Connecting Signals Table 4 2 Signal Descriptions for I O Connector Pins Continued Signal Name Reference Direction Description PFI2 CONVERT DGND Input PFI2 Convert As an input this is a PFI Output As an output this is the CONVERT signal A high to low edge on CONVERT indicates that an A D conversion is occurring PFI3 GPCTRI SOURCE DGND Input PFI3 Counter 1 Source As an input this is a PFI Output As an output this is the GPCTRI SOURCE signal This signal reflects the actual source connected to the general purpose counter 1 PFI4 GPCTR1_GATE DGND Input PFI4 Counter 1 Gate As an input this is a PFI Output As an output this is the GPCTR1_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 1 GPCTR1_OUT DGND Output Counter 1 Output This output is from the general purpose counter 1 output PFIS UPDATE DGND Input PFI5 Update As an input this is a PFI Output As an output this is the UPDATE signal A high to low edge on UPDATE indicates that the AO primary group is being updated PFI6 WFTRIG DGND Input PFI6 Waveform Trigger As an input this is a PFI Output As an output this is the WFTRIG signal In timed AO sequ
80. ignal sources are floating or ground referenced The following sections describe these two signal types Floating Signal Sources A floating signal source is not connected in any way to the building ground system but rather has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolator outputs and isolation amplifiers An instrument or device that has an isolated output is a floating signal source You must tie the ground reference of a floating signal to the NI PCI 6110 6111 AI ground to establish a local or onboard reference for the signal Otherwise the measured input signal varies as the source floats out of the common mode input range Ground Referenced Signal Sources A ground referenced signal source is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the NI PCI 6110 6111 assuming that the computer is plugged into the same power system Nonisolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between 1 and 100 mV but can be much higher if power distribution circuits are not properly connected If a grounded signal source is improperly measured this difference may appear as a measu
81. iming signals are also available as outputs on the RTSI pins as indicated in the RTSI Triggers section and on the PFI pins as indicated in Chapter 4 Connecting Signals Programmable Function Inputs The 10 PFIs are connected to the signal routing multiplexer for each timing signal and software can select a PFI as the external source for a given timing signal Any PFI can be used as an input by any timing signal and multiple timing signals can simultaneously use the same PFI This flexible routing scheme reduces the need to change physical connections to the I O connector for different applications You can also individually enable each PFI pin to output a specific internal timing signal For example if you need National Instruments Corporation 3 9 NI PCI 6110 6111 User Manual Chapter 3 Hardware Overview the UPDATE signal as an output on the I O connector software can turn on the output driver for the PFIS UPDATE pin Device and RTSI Clocks NI PCI 6110 6111 User Manual Many functions performed by the NI PCI 6110 6111 require a frequency timebase to generate the necessary timing signals for controlling A D conversions DAC updates or general purpose signals at the I O connector The NI PCI 6110 6111 can use either its internal 20 MHz timebase or a timebase received over the RTSI bus In addition if you configure the device to use the internal timebase you can program the device to drive its internal timebase over the RTSI
82. ink Time Signal Name Direction Output On Off mA at V mA at V ns Bias ACH lt 0 3 gt AI 1MQ 42N in parallel with 100 pF 1MQ in parallel with 10 pF ACH lt 0 3 gt AI 10 nF 42N 200 pA ACH lt 0 3 gt GND AI DACOOUT AO 500 Short circuit 5at 10 Sat 10 300 to ground V Us DACIOUT AO 500 Short circuit 5at 10 5at 10 300 to ground V Us AOGND AO DGND DO VCC DO 0 1 Q Short circuit 1A to ground DIO lt 0 7 gt DIO Vec 0 5 13 at Vec 0 4 24at0 4 1 1 50 kQ pu SCANCLK DO 3 5 at Vec 0 4 5at0 4 1 5 50 KQ pu EXTSTROBE DO 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu PFIO TRIG1 AI DIO 10 kQ 35 Vec 40 5 3 5 at Vec 0 4 5at0 4 1 5 9 kO pu and 10kQ pd PFI1 TRIG2 DIO Voc 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 KQ pu PFI2 CONVERT DIO Vec 0 5 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu NI PCI 6110 6111 User Manual 4 6 ni com Chapter 4 Connecting Signals Table 4 3 1 0 Signal Summary for the NI PCI 6110 6111 Continued Signal Impedance Protection Rise Type and Input Volts Source Sink Time Signal Name Direction Output On Off mA at V mA at V ns Bias PFI3 GPCTR1 SOURCE DIO Vec 0 5 3 5 at Vec 0 4 5at0 4 1 5 50 kQ pu PFI4 GPCTR1_GATE DIO Voc 0 5 3 5 at Voc 0 4 5at0 4 1 5 50 KQ pu GPCTR1_OUT DO 3 5 at Vec 0 4 5at0 4 1 5 50 kQ pu PFIS U
83. it 3 10 RUST Tel Sci ii 3 11 O National Instruments Corporation vii NI PCI 6110 6111 User Manual Contents Chapter 4 Connecting Signals VO Connector nh t era a mq i edt tede T O Connector Signal Descriptions essere Connecting Analog Input Signals esee eee Types ot Signal SOUfGeSss o nri eret tdt Floating Signal Sources sess rennen Ground Referenced Signal Sources eene Differential Measuremennts seesesseseeseeeeeeerenee eee en eene nennennre teens Differential Connection Considerations eese Differential Connections for Ground Referenced Signal SourceS eet dp ERR a ERES Differential Connections for Nonreferenced or Floating Signal Sources tidad Common Mode Signal Rejection Considerations eese Working Voltage Range viii utero e teh Y Dite HERO Analog Output Signal Connections eese enne Digital I O Signal Connections sdonis aneor e opi eene Power Connections iet ree ie ipi aee ee e ies Timing Connections ii Reg I pU E D ate ER Programmable Function Input Connections eeeeeeeee DAQ Timing Connectioris 2 rhe tet ert ds TRIGI Signal ope Seed ee TRIG2 SPD ute ao adria STARTSCAN Signal inicia te eee le eee CONVERT Somalia reete ge AIGATE Signal eene art te e ee SISOURCE Si n l moria eei iem SCANCGEK Signal dabas n EXTSTROBE
84. jur ue SULMO O sjuouremiseoui 10 PILA ae soroe1nooy 9JON AU 9p0 0 AU 86070 25S 000 0 AU 00 AU 6 0 AUI C0 650 0 850 0 LSO 0 TOF AU LLO O AU pTO 92550000 AU 650 0 AU 970 AW p0 256600 258600 95LS0 0 S OF Au ZTO AU Gp 0 92550000 AU 88070 AW AW 0 256600 258600 95LS0 0 IF AU C O AU 860 92550000 Au 8T 0 AU z AU ETI 256600 258600 LSO 0 TF AW 8S 0 AU p 25S 000 0 AU pp AU T S AU 650 0 850 0 LSO 0 oF AU C AU Gp 25S 000 0 AU 880 AU QT AU L S 991V0 2510 2510 OLF AUI ET AW 8 6 25 000 0 Aw gI AU Jc AUI 07 20190 20190 20190 OTF AU gs AW pC 92550000 AU y AU C AUI SE 251670 251670 951670 OSF poSeioAy Tepo 24 25 pa3u may Md agus Au 189A I s eq 06 s moH pz apes MA AUI uonnjosaq yuq duor Aur uorjezuen asIoN PSIO Surpeos JO A asuey JeumuoN Ka3 n32y 2Ane oo Azen y ajn osqy uonewoju Aoe1no9v 119 01 L9 19d IN L V 81081 NI PCI 6110 6111 User Manual A 3 National Instruments Corporation Appendix A NI PCI 6110 6111 User Manual Specifications Transfer Characteristics Ip DNE iier t rt eet euet Spurious free dynamic range SFDR Effective number of bits ENOB Offset and gain error Amplifier Characteristics Input impedance ACH lt 0 3 gt to ACH lt 0 3 gt Normal powered on Powered off Overload
85. l 1 0 Connections NI PCI 6110 6111 National Instruments Corporation 4 15 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals Figure 4 7 shows DIO lt 0 3 gt configured for digital input and DIO lt 4 7 gt configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the switch state shown in Figure 4 7 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 4 7 Power Connections Two pins on the I O connector supply 5 V from the computer power supply using a self resetting fuse The fuse resets automatically within a few seconds after the overcurrent condition is removed These pins are referenced to DGND and can be used to power external digital circuitry Power rating 4 65 to 45 25 VDC at 1 A UN Caution Under no circumstances should you connect these 5 V power pins directly to analog or digital ground or to any other voltage source on the NI PCI 6110 6111 or any other device Doing so can damage the device and the computer NI is not liable for damage resulting from such a connection Timing Connections UN Caution Exceeding the maximum input voltage ratings which are listed in Table 4 3 can damage the NI PCI 6110 6111 and the computer NI is not liable for any damage resulting from such signal connections NI PCI 6110 6111 User Manual All external control over the
86. l area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense Canadian Department of Communications This Class A digital apparatus meets all requirements of the Canadian Interference Causing Equipment Regulations Cet appareil num rique de la classe A respecte toutes les exigences du R glement sur le mat riel brouilleur du Canada Class B Federal Communications Commission This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures Reorient or relocate the receiving antenna Increase the separation between the equipment and receiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the
87. ld time gate setup time gate pulse width output delay time total harmonic distortion the ratio of the total rms signal due to harmonic distortion to the overall rms signal in decibel or a percentage G 12 ni com thermocouple TIO tote t out tp TRIG trigger UI UISOURCE unipolar UPDATE V V VDC VI National Instruments Corporation Glossary a temperature sensor created by joining two dissimilar metals the junction produces a small voltage as a function of the temperature timing I O an offset delayed pulse the offset is t nanoseconds from the falling edge of the CONVERT signal output delay time pulse period trigger signal any event that causes or starts some form of data capture source clock period source pulse width transistor transistor logic pulse width update interval counter update interval counter clock signal a signal range that is always positive for example 0 to 10 V update signal volts volts direct current virtual instrument 1 a combination of hardware and or software elements typically used with a PC that has the functionality of a classic stand alone instrument 2 a LabVIEW software module VI which consists of a front panel user interface and a block diagram program 6 13 NI PCI 6110 6111 User Manual Glossary WFTRIG NI PCI 6110 6111 User Manual volts input high volts input low volts in measured voltage volts output high
88. n input STARTSCAN is configured in the edge detection mode You can select any PFI pin as the source for STARTSCAN and configure the polarity selection for either rising or falling edge The selected edge of STARTSCAN initiates a scan The sample interval counter SI2 starts if you select internally triggered CONVERT As an output STARTSCAN reflects the actual start pulse that initiates a scan even if another PFI is externally triggering the starts You have two output options The first is an active high pulse with a pulse width of 25 to 50 ns which indicates the start of the scan The second action is an active high pulse that terminates at the start of the last conversion in the scan which indicates a scan in progress STARTSCAN is deasserted t after the last conversion in the scan is initiated This output is set to high impedance at startup Figures 4 15 and 4 16 show the input and output timing requirements for STARTSCAN Rising edge polarity Falling edge polarity tw 10 ns minimum Figure 4 15 STARTSCAN Input Signal Timing 4 22 ni com Chapter 4 Connecting Signals STARTSCAN Start Pulse CONVERT STARTSCAN 4 gt ty 25 50 ns a Start of Scan LJ NN tog 10 ns minimum o dor b Scan in Progress Two Conversions per Scan Figure 4 16 STARTSCAN Output Signal Timing The CONVERT pulses are masked off until the dev
89. nd Pseudodifferential signal connections reduce noise pickup and increase common mode noise rejection This connection type also allows input signals to float within the common mode limits of the PGIA UN Caution Exceeding the differential and common mode input ranges distorts the input signals Exceeding the maximum input voltage rating can damage the device and the computer NI is not liable for any damage resulting from such signal connections The maximum input voltage ratings are listed in the Protection column of Table 4 3 NI PCI 6110 6111 User Manual You can use the PGIA in different ways when using different input configurations Figure 4 3 shows a diagram of the PGIA Instrumentation Amplifier Vins O Vm Measured Voltage Vin Vins Vis Gain Figure 4 3 NI PCI 6110 6111 PGIA 4 8 ni com Chapter 4 Connecting Signals The PGIA applies gain and common mode voltage rejection and presents high input impedance to the AI signals connected to the NI PCI 6110 6111 Signals are routed to the positive and negative inputs of the PGIA The PGIA converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier The amplifier output voltage is referenced to the device ground The ADC measures this output voltage when it performs A D conversions Types of Signal Sources When making signal connections first determine whether the s
90. nection is to provide an impedance for this choke to work against at high frequency thus improving the high frequency CMRR Depending upon your application and the type of common noise at your source further common noise rejection might be gained by placing a 0 1 uF ceramic bypass capacitor between ACH lt 0 3 gt and ACH lt 0 3 gt GND Working Voltage Range The PGIA operates normally by amplifying signals of interest while rejecting common mode signals as long as the following three conditions are met 1 The common mode voltage V m which is equivalent to subtracting ACH lt 0 3 gt GND from ACH lt 0 3 gt and which is shown in Figure 4 5 must be less than 11 V This V4 is a constant for all range selections 2 The signal voltage V which is equivalent to subtracting ACH lt 0 3 gt from ACH lt 0 3 gt and which is shown in Figure 4 5 must be less than or equal to the range selection of the given channel If V is greater than the range selected the signal clips and information 1s lost 3 The total working voltage of the positive input which can be thought of as Vem Vs or simply as subtracting ACH lt 0 3 gt GND from ACH lt 0 3 gt must be less than 11 V for ranges 10 V or less than 42 V for ranges gt 10 V If any of these conditions are exceeded current limiters limit the input current to 20 mA maximum into any input until the fault condition is removed yi Note All inputs are protected a
91. nformation about these products refer to the NI catalog atni com catalog Custom Cabling NI PCI 6110 6111 User Manual NI offers cables and accessories for you to prototype your application or to use if you frequently change device interconnections When developing custom cabling refer to the following guidelines e Forthe AI signals shielded twisted pair wires for each AI pair yield the best results assuming that you use differential inputs Tie the shield for each signal pair to the ground reference at the source e Route the analog lines separately from the digital lines e When using a cable shield use separate shields for the analog and digital halves of the cable Failure to do so results in noise coupling into the analog signals from transient digital signals Mating connectors and a backshell kit for making custom 68 pin cables are available from NI 1 4 ni com Chapter 1 Introduction The following list gives recommended part numbers for connectors that mate to the I O connector on the NI PCI 6110 6111 e Honda 68 position solder cup female connector Honda backshell Unpacking The NI PCI 6110 6111 is shipped in an antistatic package to prevent electrostatic damage to the device Electrostatic discharge ESD can damage several components on the device UN Caution Never touch the exposed pins of connectors To avoid such damage in handling the device take the following precautions e Ground yours
92. nt is taken so you must provide the three extra pulses CONVERT Signal Any PFI pin can receive as an input the CONVERT signal which is available as an output on the PFI2 CONVERT pin Refer to Figures 4 9 and 4 10 for the relationship of CONVERT to the DAQ sequence As an input CONVERT is configured in the edge detection mode You can select any PFI pin as the source for CONVERT and configure the polarity selection for either rising or falling edge The selected edge of CONVERT initiates an A D conversion As an output CONVERT reflects the actual convert pulse that is connected to the ADC even if another PFI is externally generating the conversions The output is an active low pulse with a pulse width of 50 to 100 ns This output is set to high impedance at startup Figures 4 17 and 4 18 show the timing requirements for CONVERT Rising edge polarity Falling edge polarity ty 10 ns minimum Figure 4 17 CONVERT Input Signal Timing 4 24 ni com Chapter 4 Connecting Signals i tw 50 100 ns l Figure 4 18 CONVERT Output Signal Timing The ADC switches to hold mode within 20 ns of the selected edge This hold mode delay time is a function of temperature and does not vary from one conversion to the next The SI2 on the NI PCI 6110 6111 normally generates CONVERT unless you select some external source The counter is started by the STARTSCAN signal and continues to coun
93. od and buffered semiperiod measurement Whatis the difference in timebases between the Am9513 counter timer and the DAQ STC The DAQ STC based MIO devices have a 20 MHz timebase The Am09513 based MIO devices have a 1 MHz or 5 MHz timebase NI PCI 6110 6111 User Manual C 4 ni com Appendix C Common Questions Do the counter timer applications that I wrote previously work with the DAQ STC If you are using NI DAQ with LabVIEW some applications that were built using the CTR VIs still run However there are many differences between the counters of the NI PCI 6110 6111 and those of other devices the counter numbers are different timebase selections are different and the DAQ STC counters are 24 bit counters unlike the 16 bit counters on devices without the DAQ STC If you are using NI DAQ or Measurement Studio the counter timer applications that you wrote previously do not work with the DAQ STC You must use the GPCTR functions because ICTR and CTR functions do not work with the DAQ STC The GPCTR functions have the same capabilities as the ICTR and CTR functions plus more but you must first rewrite the application using GPCTR function calls I m using one of the general purpose counter timers on the NI PCI 6110 6111 but I do not see the counter timer output on the I O connector What am I doing wrong If you are using NI DAQ or LabWindows CVI you must configure the output line to output the signal to the I O connector Use th
94. ommon mode range common mode signal common mode voltage CONVERT counter timer CTR O National Instruments Corporation Glossary Celsius calibration DAC channel pin or wire lead to which you apply or from which you read the analog or digital signal Analog signals can be single ended or differential For digital signals you group channels to form ports Ports usually consist of either four or eight digital channels reciprocal of the interchannel delay centimeter complementary metal oxide semiconductor common mode rejection ratio a measure of an instrument s ability to reject interference from a common mode signal usually expressed in decibels dB unwanted signals that appear in equal phase and amplitude on both the inverting and noninverting input in a differential measurement system Ideally but not completely in practice the measurement device ignores this noise because the measurement device is designed to respond to the difference between the inverting and noninverting inputs the input range over which a circuit can handle a common mode signal the mathematical average voltage relative to the ground of the computer of the signals from a differential input any voltage present at both instrumentation amplifier inputs with respect to amplifier ground convert signal a circuit that counts external pulses or clock pulses timing counter G 3 NI PCI 6110 6111 User Manual Glossary D A DAC DA
95. on D 1 NI PCI 6110 6111 User Manual Glossary Prefix Meaning Value p pico 10 2 n nano 107 u micro 10 6 m milli 10 3 k kilo 10 M mega 10 G giga 10 Numbers Symbols degrees gt greater than 2 greater than or equal to less than lt less than or equal to per percent plus or minus positive of or plus negative of or minus Q ohms O National Instruments Corporation G 1 NI PCI 6110 6111 User Manual Glossary 5 V A D AC ACH ACHOGND ADC ADE AI AIGATE AIGND ANSI AO AOGND ASIC bipolar NI PCI 6110 6111 User Manual square root of 5 VDC source signal amperes analog to digital alternating current analog input channel signal analog input channel ground signal analog to digital converter an electronic device often an integrated circuit that converts an analog voltage to a digital number application development environment analog input analog input gate signal analog input ground signal American National Standards Institute analog output analog output ground signal Application Specific Integrated Circuit a proprietary semiconductor component designed and manufactured to perform a set of specific functions a signal range that includes both positive and negative values for example 5 V to 5 V G 2 ni com C e CalDAC CH channel rate cm CMOS CMRR common mode noise c
96. on is foreign matter in a solid liquid or gaseous state that can reduce dielectric strength or surface resistivity The following is a description of pollution degrees e Pollution degree 1 means no pollution or only dry nonconductive pollution occurs The pollution has no influence e Pollution degree 2 means that only nonconductive pollution occurs in most cases Occasionally however a temporary conductivity caused by condensation must be expected Pollution degree 3 means that conductive pollution occurs or dry nonconductive pollution occurs that becomes conductive due to condensation Clean the product with a soft nonmetallic brush Make sure that the product is completely dry and free from contaminants before returning it to service You must insulate signal connections for the maximum voltage for which the product is rated Do not exceed the maximum ratings for the product Remove power from signal lines before connecting them to or disconnecting them from the product Operate this product only at or below the installation category stated in Appendix A Specifications The following is a description of installation categories e Installation category I is for measurements performed on circuits not directly connected to MAINS This category is a signal level such as voltages on a printed wire board PWB on the secondary of an isolation transformer Examples of installation category I are measurements on circuits not
97. otection devices and ripple control units Below is a diagram of a sample installation Category IV Category III Category II Category Source of Low Voltage lt 1000 V Installation Circuit Breaker Plug in Equipment Electric Meter Building Fixed Secondary 2 Local Level is Installation wor Windings of oen Distribution Such Distribution Isolation as Wall Sockets Panel Transformers National Instruments Corporation 1 7 NI PCI 6110 6111 User Manual Installing and Configuring the NI PCI 6110 6111 This chapter explains how to install and configure the NI PCI 6110 6111 Installing the Software E Note It is important to install the software before installing the NI PCI 6110 6111 to ensure that the device is properly detected Install the ADE such as LabVIEW or Measurement Studio according to the instructions on the CD and the release notes Install NI DAQ according to the instructions on the CD and in the DAQ Quick Start Guide included with the device Installing the Hardware The following are general installation instructions Consult the computer or chassis user manual or technical reference manual for specific instructions and warnings about installing new devices You can install the NI PCI 6110 6111 in any available expansion slot in the computer However to achieve best noise performance leave as much room as possible between the NI PCI 6110 6111 and other
98. red at the factory and stored in the EEPROM for subsequent self calibrations This voltage is stable enough for most applications but if you are using the device at an extreme temperature or if the onboard reference has not been measured for a year or more you may wish to externally calibrate the device An external calibration refers to calibrating the device with a known external reference rather than relying on the onboard reference Redetermining the value of the onboard reference is part of this process and the results can be saved in the EEPROM so you should not have to perform an external calibration very often You can externally calibrate the device by calling the NI DAQ calibration function To externally calibrate the device be sure to use a very accurate external reference The reference should be several times more accurate than the device itself For example to calibrate a 16 bit device the external reference should be at least 0 00146 10 ppm accurate For a detailed calibration procedure for the NI PCI 6110 6111 click Manual Calibration Procedures at ni com calibration 5 2 ni com Specifications Analog Input This appendix lists the specifications of the NI PCI 6110 6111 These specifications are typical at 25 C unless otherwise noted Input Characteristics Number of channels NI PCI 6110 nme 4 pseudodifferential NIPCEO61I1I eme 2 pseudodifferential Type of ADC Resolution
99. rement error The connection instructions for grounded signal sources are designed to eliminate this ground potential difference from the measured signal National Instruments Corporation 4 9 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals Differential Measurements The following sections discuss the use of differential DIFF measurements and considerations for measuring both floating and ground referenced signal sources Table 4 4 summarizes the recommended DIFF signal connections and includes input examples for both types of signal sources Table 4 4 Signal Source Types DIFF Input Examples and Floating Signal Source Signal Source Not Connected to Building Ground Grounded Signal Source Input Examples Ungrounded thermocouples Plug in cards with nonisolated Signal conditioning with isolated outputs outputs Battery devices Differential DIFF ACHOG s ACHO G t v acho t v ACHO a L ACHOGND ill ACHOGND See text for information on bias resistors Differential Connection Considerations NI PCI 6110 6111 User Manual A differential connection is one in which the NI PCI 6110 6111 AI signal has its own reference signal or signal return path The device channels are always configured in DIFF input mode The input signal is tied to the positive input of the PGIA and its reference signal or r
100. rogramming the DMA controller and servicing interrupts can take several milliseconds in some cases During this time data accumulates in the FIFO for future retrieval With a larger FIFO longer latencies can be tolerated In the case of analog output a FIFO permits faster update rates because the waveform data can be stored in the FIFO ahead of time This again reduces the effect of latencies associated with getting the data from system memory to the DAQ device signal sources with voltage signals that are not connected to an absolute reference or system ground Also called nonreferenced signal sources Some common example of floating signal sources are batteries transformers or thermocouples frequency output signal feet the factor by which a signal is amplified sometimes expressed in decibels gate signal general purpose counter signal general purpose counter 0 gate signal general purpose counter 0 output signal general purpose counter 0 clock source signal general purpose counter 0 up down signal general purpose counter 1 gate signal general purpose counter 1 output signal general purpose counter 1 clock source signal G 6 ni com GPCTRI UP DOWN ground ICTR INL interchannel delay I O Ios Io lour IRQ National Instruments Corporation Glossary general purpose counter up down signal an electrically neutral wire that has the same potential as the surrounding earth a common reference poin
101. rt These resources are available for most products at no cost to registered users and include software drivers and updates a KnowledgeBase product manuals step by step troubleshooting wizards hardware schematics and conformity documentation example code tutorials and application notes instrument drivers discussion forums a measurement glossary and so on Assisted Support Options Contact NI engineers and other measurement and automation professionals by visiting ni com ask Our online system helps you define your question and connects you to the experts by phone discussion forum or email e Training Visitni com custed for self paced tutorials videos and interactive CDs You also can register for instructor led hands on courses at locations around the world e System Integration lf you have time constraints limited in house technical resources or other project challenges NI Alliance Program members can help To learn more call your local NI office or visit ni com alliance If you searched ni com and could not find the answers you need contact your local office or NI corporate headquarters Phone numbers for our worldwide offices are listed at the front of this manual You also can visit the Worldwide Offices section of ni com niglobal to access the branch office Web sites which provide up to date contact information support phone numbers email addresses and current events National Instruments Corporati
102. rumentation Amplifier 100pf ACHO Measured Bias Current Return Paths Bias Resistor see text 1 0 Connector Voltage ACHOGND ACHO Connections Shown Figure 4 5 Differential Input Connections for Nonreferenced Signals Figure 4 5 shows a bias resistor connected between ACHO and the floating signal source ground If you do not use the resistor and the source is truly floating the source often floats outside the common mode signal range of the PGIA and the PGIA saturates causing erroneous readings You must reference the source to the respective channel ground Common Mode Signal Rejection Considerations NI PCI 6110 6111 User Manual Figure 4 4 shows connections for signal sources that are already referenced to some ground point with respect to the NI PCI 6110 6111 In theory the PGIA can reject any voltage caused by ground potential differences between the signal source and the device In addition with pseudodifferential input connections the PGIA can reject common mode noise pickup in the leads connecting the signal sources to the device ni com Chapter 4 Connecting Signals Like any amplifier the common mode rejection ratio CMRR of the PGIA is limited at high frequency This limitation has been compensated for in the design of the NI PCI 6110 6111 by using a common mode choke on each channel The purpose of the 10 nF capacitance on the ACH lt 0 3 gt con
103. s National Instruments NI DAQ NI DAQ Help xiii NI PCI 6110 6111 User Manual Introduction This chapter describes the NI PCI 6110 6111 lists what you need to get started describes the optional software and optional equipment and explains how to unpack the device About the NI PCI 6110 6111 Thank you for buying an NI PCI 6110 6111 The NI PCI 6110 6111 is a Plug and Play multifunction analog digital and timing I O device for PCI bus computers The NI PCI 6110 6111 features a 12 bit A D converter ADC per channel with four or two simultaneously sampling analog inputs 16 bit D A converters DACs with voltage outputs eight lines of TTL compatible DIO and two 24 bit counter timers for TIO Because the NI PCI 6110 6111 has no DIP switches jumpers or potentiometers it is easily software configured and calibrated The NI PCI 6110 6111 is a completely switchless and jumperless DAQ device for the PCI bus This feature is made possible by the NI MITE bus interface chip that connects the device to the PCI I O bus The MITE implements the PCI Local Bus Specification so that the interrupts and base memory addresses are all software configured The NI PCI 6110 6111 uses the National Instruments DAQ STC system timing controller for time related functions The DAQ STC consists of three timing groups that control AI AO and general purpose counter timer functions These groups include a total of seven 24 bit and three 16 bit counters
104. s software selectable for both options This output is set to high impedance at startup Figure 4 32 shows the timing requirements for GPCTR1 OUT i TC i GPCTR1_SOURCE GPCTR1_OUT Pulse on TC GPCTR1_OUT Toggle output on TC LL Figure 4 32 GPCTR1_OUT Signal Timing NI PCI 6110 6111 User Manual 4 34 ni com Chapter 4 Connecting Signals GPCTR1 UP DOWN Signal This signal can be externally input on the DIO7 pin and is not available as an output on the I O connector General purpose counter 1 counts down when this pin is at a logic low and counts up at a logic high This input can be disabled so that software can control the up down functionality and leave the DIO7 pin free for general use Figure 4 33 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the NI PCI 6110 6111 OUT output signals V SOURCE H V IL GATE IH IL O Vou UT V OL tow 4 tout Source Clock Period to 50 ns minimum Source Pulse Width top 23 ns minimum Gate Setup Time tgsu 10 ns minimum Gate Hold Time tgn Ons minimum Gate Pulse Width tow 10 ns minimum Output Delay Time tout 80 ns maximum Figure 4 33 GPCTR Timing Summary The GATE and OUT signal transitions shown in Figure 4 33 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising ed
105. s the minimum number of scans before TRIG2 can be recognized After the SC decrements to zero it is loaded with the number of posttrigger scans to acquire while the acquisition continues The device ignores TRIG2 if it is asserted prior to the SC decrementing to zero After the selected edge of TRIG2 is received the device acquires a fixed number 4 20 ni com Chapter 4 Connecting Signals of scans and the acquisition stops This mode acquires data both before and after receiving TRIG2 As an output TRIG2 reflects the posttrigger in a pretriggered acquisition sequence even if another PFI is externally triggering the acquisition TRIG2 is not used in posttriggered data acquisition The output is an active high pulse with a pulse width of 25 to 50 ns This output is set to high impedance at startup Figures 4 13 and 4 14 show the timing requirements for TRIG2 A e Rising edge polarity i Falling edge polarity tw 10 ns minimum Figure 4 13 TRIG2 Input Signal Timing tw 25 50 ns Figure 4 14 TRIG2 Output Signal Timing National Instruments Corporation 4 21 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals NI PCI 6110 6111 User Manual STARTSCAN Signal Any PFI pin can receive as an input the STARTSCAN signal which is available as an output on the PFI7 STARTSCAN pin Refer to Figures 4 9 and 4 10 for the relationship of STARTSCAN to the DAQ sequence As a
106. scription table 4 5 signal summary table 4 7 PFI7 STARTSCAN signal See also STARTSCAN signal description table 4 5 signal summary table 4 7 PFIS GPCTRO SOURCE signal See also GPCTRO SOURCE signal description table 4 5 signal summary table 4 7 PFI9 GPCTRO GATE signal See also GPCTRO GATE signal description table 4 5 signal summary table 4 7 PFIs programmable function inputs connecting to external signal source caution C 6 overview 4 16 questions about C 5 signal routing 3 9 timing input connections 4 17 PGIA analog input connections common mode signal rejection considerations 4 12 differential connections connection considerations 4 10 ground referenced signal sources 4 11 nonreferenced or floating signal sources 4 12 overview 4 8 National Instruments Corporation 1 7 Index definition 3 2 working voltage range 4 13 phone technical support D 1 physical specifications A 12 pin assignments 50 pin connector figure 4 3 B 3 68 pin connector figure 4 2 B 2 polarity selection analog input 3 3 power connections 5 V power pins 4 16 self resetting fuse 4 16 power requirement specifications A 12 professional services D 1 programmable function inputs PFIs See PFIs programmable function inputs programmable gain instrumentation amplifier See PGIA programming examples D 1 Q questions and answers analog input and output C 3 general information C 1 installing an
107. t down and reload itself until the scan is finished It then reloads itself in preparation for the next STARTSCAN pulse A D conversions generated by either an internal or external CONVERT signal are inhibited unless they occur within a DAQ sequence Scans occurring within a DAQ sequence may be gated by either the hardware AIGATE signal or software command register gate AIGATE Signal Any PFI pin can receive as an input the AIGATE signal which is not available as an output on the I O connector The AIGATE signal can mask off scans in a DAQ sequence You can configure the PFI pin you select as the source for the AIGATE signal in either the level detection or edge detection mode You can configure the polarity selection for the PFI pin for either active high or active low In the level detection mode if AIGATE is active the STARTSCAN signal is masked off and no scans can occur In the edge detection mode the first active edge disables the STARTSCAN signal and the second active edge enables STARTSCAN AIGATE can neither stop a scan in progress nor continue a previously gated off scan Once a scan has started AIGATE does not gate off conversions until the beginning of the next scan and conversely if National Instruments Corporation 4 25 NI PCI 6110 6111 User Manual Chapter 4 E Connecting Signals conversions are being gated off AIGATE does not gate them back on until the beginning of the next scan SISOURCE Signal
108. t for an electrical system hour hexadecimal hertz 8253 Programmable Interval Timer applies to legacy DAQ products such as the 1200 series integral nonlinearity for an ADC deviation of codes of the actual transfer function from a straight line amount of time that passes between sampling consecutive channels The interchannel delay must be short enough to allow sampling of all the channels in the channel list within the scan interval The greater the interchannel delay the more time the PGIA is allowed to settle before the next channel is sampled The interchannel delay is regulated by CONVERT input output the transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces current output high current output low current out interrupt request G 7 NI PCI 6110 6111 User Manual Glossary kHz L LabVIEW LED library linearity LSB m MB Measurement amp Automation Explorer MAX MHz MIO MITE MSB NI PCI 6110 6111 User Manual kilohertz a graphical programming language light emitting diode a file containing compiled object modules each comprised of one of more functions that can be linked to other object modules that make use of these functions NIDAQ32 LIB is a library that contains NI DAQ functions The NI DAQ function set is broken down into object modules so that only the object modules that
109. t up to 42 V National Instruments Corporation 4 13 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals Analog Output Signal Connections The AO signals are DACOOUT DACIOUT and AOGND DACOOUT is the voltage output signal for AO channel 0 DAC1OUT is the voltage output signal for AO channel 1 and AOGND is the ground reference signal for the AO channels Figure 4 6 shows how to make AO connections to the NI PCI 6110 6111 m DACOOUT Channel 0 Load VOUT 0 Load VOUT 1 DAC1OUT Channel 1 Analog Output Channels NI PCI 6110 6111 Figure 4 6 Analog Output Connections NI PCI 6110 6111 User Manual 4 14 ni com Chapter 4 Connecting Signals Digital 1 0 Signal Connections The DIO signals are DIO lt 0 7 gt and DGND DIO lt 0 7 gt are the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program all lines individually to be inputs or outputs UN Caution Exceeding the maximum input voltage ratings which are listed in Table 4 3 can damage the NI PCI 6110 6111 and the computer NI is not liable for any damage resulting from such signal connections Figure 4 7 shows signal connections for three typical DIO applications DIO lt 4 7 gt TTL Signal o DIO lt 0 3 gt 5 V WN T gt Switch 1 0 Connector ii Figure 4 7 Digita
110. the source signal FREQ OUT Signal This signal is available only as an output on the FREQ OUT pin The frequency generator for the NI PCI 6110 6111 outputs the FREQ OUT pin The frequency generator is a 4 bit counter that can divide its input clock by the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 KHz timebases The output polarity is software selectable This output is set to high impedance at startup Field Wiring Considerations NI PCI 6110 6111 User Manual Environmental noise can seriously affect the measurement accuracy of the NI PCI 6110 6111 if you do not take proper care when running signal wires between signal sources and the device The following recommendations apply mainly to AI signal routing to the device although they also apply to signal routing in general Minimize noise pickup and maximize measurement accuracy by taking the following precautions e Use differential AI connections to reject common mode noise e Use individually shielded twisted pair wires to connect AI signals to the device With this type of wire the signals attached to the ACH and ACH inputs are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground 4 36 ni com Chapter 4 Connecting Signals This kind of connection is required for signals traveling through areas with large magnetic fields or
111. ther single transfer demand transfer 4 LSB typ 8 LSB max 2 LSB typ 8 LSB max ee 5 0 mV max iis 0 1 of output range max ni com Appendix A Specifications Table A 3 NI PCI 6110 6111 Analog Output DC Accuracy Information Absolute Accuracy of Readi Nominal PE Offset Temp Drift Absolute Accuracy Range V 24 Hrs 1 Year mV 9o C at Full Scale mV x10 0 018 0 022 5 933 0 0005 8 133 Note Temp Drift applies only if ambient is greater than 10 C of previous external calibration Voltage Output Raids eres Output coupling esses Output impedance Short circuit current sss Current drive cheer a aa Output stability sess Protection iieri Power on output voltage Dynamic Characteristics Settling time and slew rate 10 V m 50 Q 5 TEN 27 mA typ m 5 mA min EN Any passive load siete Short circuit to ground Stent 400 mV before software loads calibration values Settling Time for Full Scale Step Slew Rate 300 ns to 0 01 300 V us Spurious free dynamic range Glitch energy eee National Instruments Corporation A 7 ues 1 mV ms DC to 5 MHz 75 dB DC to 10 kHz ues 30 mV for 1 us NI PCI 6110 6111 User Manual Appendix A Specifications Digital 1 0 NI PCI 6110 6111 User Manu
112. timers silicon A a Level Internal source ACH lt 0 3 gt External source PFIO TRIGI Resolution Histeria Bandwidth 3 dB Internal source ACH O 3 External source PFIO TRIGI 10 MHz 100 kHz 0 0196 DMA interrupts programmed I O Start and stop trigger gate clock Start trigger gate clock Source gate ACH lt 0 3 gt external trigger PFIO TRIG1 Full scale 10 V external Positive or negative software selectable 8 bits 1 in 256 Programmable 5 MHz 5 MHz ni com Appendix A Specifications Digital Trigger Number of triggers c e 2 Purpose Analog input cece eeeeeeeeeeee Start and stop trigger gate clock Analog output esee Start trigger gate clock General purpose counter timers Source gate Source edited eig eine lt PFIO PFI9 gt lt RTSIO RTSI6 gt Slope Bana eles Positive or negative software selectable Compatibility eene 5 V TTL RESPONSE estt etes Rising or falling edge Pulse width 2 iere 10 ns min External Input for Digital or Analog Trigger PFIO TRIG1 Output impedance 0 0 eects 10 KQ Source impedance recommended 1kQ Coupling pe DC or AC Protection Digital trigger eee 0 5 V to Vee 0 5 V Analog trigger On disabled 35 V Powered off sss 35 V RTSI Trigger Lines mee 7
113. timing of the NI PCI 6110 6111 is routed through the 10 PFIs labeled PFIO through PFI9 These signals are explained in the next section Programmable Function Input Connections These PFIs are bidirectional as outputs they are not programmable and reflect the state of many DAQ waveform generation and general purpose timing signals There are five other dedicated outputs for the remainder of the timing signals As inputs the PFI signals are programmable and can control any DAQ waveform generation and general purpose timing signals The DAQ signals are explained in the DAQ Timing Connections section The waveform generation signals are explained in the Waveform Generation Timing Connections section The general purpose timing signals are explained in the General Purpose Timing Signal Connections section 4 16 ni com Chapter 4 Connecting Signals All digital timing connections are referenced to DGND Figure 4 8 illustrates how to connect an external TRIG1 source and an external CONVERT source to two NI PCI 6110 6111 PFI pins PFIO TRIG1 L PFI7 STARTSCAN E DA TRIG1 STARTSCAN Source Source DGND v 1 0 Connector NI PCI 6110 6111 Figure 4 8 Timing I O Connections Programmable Function Input Connections There are a total of 13 internal timing signals that you can externally control from the PFI pins The source for each signal is software selectabl
114. ting values to onboard calibration DACs CalDACs Most applications require some form of device calibration If you do not calibrate the device the signals and measurements could have very large offset gain and linearity errors Three levels of calibration are available to you and described in this chapter The first level is the fastest easiest and least accurate whereas the last level is the slowest most difficult and most accurate Loading Calibration Constants The NI PCI 6110 6111 is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored in the onboard nonvolatile memory EEPROM Because the CalDACs have no memory capability they do not retain calibration information when the device is unpowered Loading calibration constants refers to the process of loading the CalDACs with the values stored in the EEPROM NI DAQ determines when this is necessary and does it automatically If you are not using NI DAQ you must load these values yourself In the EEPROM there is a user modifiable calibration area in addition to the permanent factory calibration area This means that you can load the CalDACs with values either from the original factory calibration or from a calibration that you subsequently performed This method of calibration is not
115. to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control those counters The up down control signals GPCTRO UP DOWN and GPCTR1 UP DOWN are input only and do not affect the operation of the DIO lines Routing NI PCI 6110 6111 User Manual The DAQ STC provides a flexible interface for connecting timing signals to other devices or external circuitry The NI PCI 6110 6111 uses the RTSI bus to connect timing signals between devices and the Programmable Function Input PFD pins on the I O connector to external circuitry These connections enable the NI PCI 6110 6111 to both control and be controlled by other devices and circuits You can control 13 timing signals internal to the DAQ STC with an external source These timing signals can also be controlled by signals generated internally to the DAQ STC and these selections are fully software configurable For example the signal routing multiplexer for controlling the STARTSCAN signal is shown in Figure 3 10 3 8 ni com Chapter 3 Hardware Overview RTSI Trigger lt 0 6 gt lt gt gt STARTSCAN PFI 0 9 lt Scan Interval Counter TC GPCTRO OUT ET d Figure 3 10 STARTSCAN Signal Routing This figure shows that STARTSCAN can be generated from a number of sources including the external signals RTSI lt 0 6 gt and PFI lt 0 9 gt and the internal signals Sample Interval Counter TC and GPCTRO OUT Many of these t
116. uirements A 12 RTSI A 11 safety A 12 stability analog input A 5 analog output A 8 timing I O frequency scaler A 9 general purpose up down counter timers A 9 National Instruments Corporation 1 9 Index triggers analog trigger A 10 digital trigger A 11 external input for digital or analog trigger PFIO TRIG1 A 11 STARTSCAN signal See also PFI7 STARTSCAN signal FIFO considerations 4 24 input timing figure 4 22 output timing figure 4 23 signal routing figure 3 9 typical posttriggered acquisition figure 4 18 typical pretriggered acquisition figure 4 19 using the SISOURCE signal 4 26 support technical D 1 system integration services D 1 T technical support D 1 telephone technical support D 1 timing connections DAQ timing connections AIGATE signal 4 25 CONVERT signal 4 24 EXTSTROBE signal 4 27 overview 4 18 SCANCLK signal 4 26 SISOURCE signal 4 26 STARTSCAN signal 4 22 TRIGI signal 4 19 TRIG2 signal 4 20 typical posttriggered acquisition figure 4 18 typical pretriggered acquisition figure 4 19 NI PCI 6110 6111 User Manual Index general purpose timing signal connections FREQ OUT signal 4 36 GPCTRO GATE signal 4 31 GPCTRO OUT signal 4 32 GPCTRO SOURCE signal 4 30 GPCTRO UP DOWN signal 4 32 GPCTR1_GATE signal 4 33 GPCTR1_OUT signal 4 34 GPCTR1_SOURCE signal 4 33 GPCTR1_UP_DOWN signal 4 35 overview 4 30 programmable function input connections 4 17
117. ully integrated ANSI C application development environment that features interactive graphics and the LabWindows CVI Data Acquisition and Easy I O libraries For Visual Basic developers Measurement Studio features a set of ActiveX controls for using National Instruments DAQ hardware These ActiveX controls provide a high level programming interface for building virtual instruments For Visual C National Instruments Corporation 1 3 NI PCI 6110 6111 User Manual Chapter 1 Introduction developers Measurement Studio offers a set of Visual C classes and tools to integrate those classes into Visual C applications The libraries ActiveX controls and classes are available with Measurement Studio and NI DAQ VI Logger is an easy to use yet flexible tool specifically designed for data logging applications Using dialog windows you can configure data logging tasks to easily acquire log view and share your data VI Logger does not require any programming it is a stand alone configuration based software Using LabVIEW Measurement Studio or VI Logger greatly reduces the development time for your data acquisition and control application Optional Equipment NI offers a variety of products to use with the NI PCI 6110 6111 including the following cables connector blocks and other accessories e Shielded cables and cable assemblies e Connector blocks shielded 50 and 68 pin screw terminals RTSI bus cables For more specific i
118. used with the I O connectors to connect to different accessories Table 4 1 1 0 Connector Details Cable for Cable for Cable for Connecting to Connecting to Connecting to Device with Number of 100 Pin 68 Pin 50 Pin T O Connector Pins Accessories Accessories Accessories NI PCI 6110 68 N A SH68 68EP SH6850 NI PCI 6111 SH68 68R1 EP 1 0 Connector Caution Figure 4 1 shows the pin assignments for the 68 pin I O connector on the NI PCI 6110 6111 A signal description follows the connector pinouts Figure 4 2 shows the pin assignments for the NI PCI 61 10 6111 when used with a 50 pin accessory Connections that exceed any of the maximum ratings of input or output signals on the NI PCI 6110 6111 can damage the device and the computer Maximum input ratings for each signal are given in the Protection column of Table 4 3 NI is not liable for any damage resulting from such signal connections National Instruments Corporation 4 1 NI PCI 6110 6111 User Manual Chapter 4 Connecting Signals NI PCI 6110 6111 User Manual ACHO ACH1 ACH1GND ACH2 1 ACH3 1 ACH3GND1 NC NC NC NC NC NC DACOOUT DAC1OUT NC DIO4 DGND DIO1 DIO6 DGND 5 V DGND DGND PFIO TRIG1 PFH TRIG2 DGND 45V DGND PFI5 UPDATE PFI6 WFTRIG DGND PFI9 GPCTRO_GATE GPCTRO_OUT FREQ_OUT 69 AB C2 wo C2 N ww ber wo o N c m 00 n Y N o M al
119. very accurate because it does not take into account the fact that the device measurement and output voltage errors can National Instruments Corporation 5 1 NI PCI 6110 6111 User Manual Chapter 5 Calibration vary with time and temperature It is better to self calibrate when the device is installed in the environment in which it is used Self Calibration The NI PCI 6110 6111 can measure and correct for almost all of its calibration related errors without any external signal connections NI DAQ provides a self calibration method This self calibration process which generally takes less than a minute is the preferred method of assuring accuracy in your application Initiate self calibration to minimize the effects of offset gain and linearity drifts particularly those due to warmup Immediately after self calibration the only significant residual calibration error could be gain error due to time or temperature drift of the onboard voltage reference This error is addressed by external calibration which is discussed in the following section If you are interested primarily in relative measurements you can ignore a small amount of gain error and self calibration should be sufficient External Calibration NI PCI 6110 6111 User Manual The NI PCI 6110 6111 has an onboard calibration reference to ensure the accuracy of self calibration The specifications are listed in Appendix A Specifications The reference voltage is measu
120. ysteresis specified by lowValue as shown in Figure 3 8 highValue lowValue Trigger Figure 3 8 High Hysteresis Analog Triggering Mode In low hysteresis analog triggering mode the trigger is generated when the signal value is less than lowValue with the hysteresis specified by highValue as shown in Figure 3 9 highValue lowValue a LL m Sas Ste de io de a TRS Trigger zB Figure 3 9 Low Hysteresis Analog Triggering Mode National Instruments Corporation 3 7 NI PCI 6110 6111 User Manual Chapter 3 Hardware Overview Digital 1 0 The analog trigger circuit generates an internal digital trigger based on the Al signal and user defined trigger levels This digital trigger can be used by any DAQ STC timing section including the AI AO and general purpose counter timer sections For example the AI section can be configured to acquire n scans after the AI signal crosses a specific threshold As another example the AO section can be configured to update its outputs whenever the AI signal crosses a specific threshold Timing Signal The NI PCI 6110 6111 contains eight lines of DIO for general purpose use You can individually software configure each line for either input or output At system startup and reset the DIO ports are all high impedance The hardware up down control for general purpose counters 0 and 1 are connected onboard
121. zard for the operator NI is not liable for damage or injury resulting from such misuse 2The value of 1 least significant bit LSB of the 12 bit ADC that is the voltage increment corresponding to a change of one count in the ADC 12 bit count Note See Appendix A Specifications for absolute maximum ratings National Instruments Corporation 3 3 NI PCI 6110 6111 User Manual Chapter 3 Hardware Overview Considerations for Selecting Input Ranges The range you select depends on the expected range of the incoming signal A large input range can accommodate a large signal variation but reduces the voltage resolution Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range For best results match the input range as closely as possible to the expected range of the input signal Input Coupling You can configure the NI PCI 6110 6111 for either AC or DC input coupling on a per channel basis Use AC coupling when the AC signal contains a large DC component If you enable AC coupling you remove the large DC offset for the input amplifier and amplify only the AC component This configuration makes effective use of the ADC dynamic range Analog Output The NI PCI 6110 6111 supplies two channels of AO voltage at the I O connector The range is fixed at bipolar 10 V Analog Trigger In addition to supporting internal software triggering and external digital trig

Download Pdf Manuals

Related Search

Related Contents

Behringer Europack UB1622FX-Pro Quick Start Guide  SUSPENSION FORKS  東芝蛍光灯器具用木製枠取扱説明書  

Copyright © All rights reserved. Failed to retrieve file