Home

MPC603e RISC Microprocessor User`s Manual

1. Bits Name Function 0 EMCP Enable MCP The primary purpose of this bit is to mask out further machine check exceptions caused by assertion of MCP similar to how MSR EE can mask external interrupts 0 Masks MCP Asserting MCP does not generate a machine check exception or a checkstop 1 Asserting MCP causes checkstop if MSR ME 0 or a machine check exception if ME 1 1 Reserved do not clear 2 EBA Enable 60x bus address parity checking EBA and EBD allow the processor to operate with memory subsystems that do not generate parity 0 Disables address parity checking 1 Allows a address parity error to cause a checkstop if MSR ME 0 or a machine check exception if MSR ME 1 3 EBD Enable 60x bus data parity checking EBA and EBD allow the processor to operate with memory subsystems that do not generate parity 0 Disables data parity checking 1 Allows a data parity error to cause a checkstop if MSR ME 0 or a machine check exception if MSR ME 1 4 BCLK CLK_OUT output enable and clock type selection Used in conjunction with HIDO ECLK and HRESET to configure CLK_OUT See Table 2 3 5 EICE Enables in circuit emulator outputs for pipeline tracking See Section 7 2 11 Pipeline Tracking Support 6 ECLK CLK_OUT output enable and clock type selection Used in conjunction with HIDO BCLK and the HRESET signal to configure CLK_OUT See Table 2 3 7 PAR Disable precharge of ARTRY 0 Pr
2. UISA VEA OEA Supervisor Level Optional 64 Bit Form V X V V X V X V X V X V X y V xO y J xO xO J XO 4 J J J y y y y Lj ej ej e ej e e 2 lt Se Sa lt E SY lt F OS e 2j 2 P gt D X D El D D X X X X X X X El El X X X X X X X Xx Appendix A PowerPC Instruction Set Listings For More information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Legend Table A 46 PowerPC Instruction Set Legend continued UISA VEA OEA Supervisor Level Optional 64 Bit Form a gt fmulsx fnabsx fnegx fnmaddx fnmaddsx fnmsubx fnmsubsx fresx3 frspx frsqrtex 3 fselx 3 fsqrtx 3 e fsqrtsx 3 fsubx lt lt 2 2 2 e 2 Sy 2 fsubsx x gt gt D D gt D X S El D S D X X icbi x lt Z isync V Ibz el Ibzu Ibzux Ibzx Id Idarx Idu Idux 1 ell ell eech 22 2 g Wei Idx 1 lfd lfdu Ifdux lfdx lfs Heu lfsux Hey Lej ej ej e ej e 2 2 lt See o CH H SM o x lt x o oj X X UO UO x Xx Iha MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to
3. 1 Load and store string or multiple instruction MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semi onduct er Ing Functional Categories Table A 18 Memory Synchronization Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 eieio 31 00000 00000 00000 854 0 isync 19 00000 00000 00000 150 0 Idarx 1 31 D A B 84 0 Iwarx 31 D A B 20 0 stdex 31 S A B 214 1 stwcx 31 S A B 150 1 sync 31 00000 00000 00000 598 0 1 64 bit instruction Table A 19 Floating Point Load Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lfd 50 D A d lfdu 51 D A d lfdux 31 D A 631 0 lfdx 31 D A 599 0 lfs 48 D A d lfsu 49 D A d lfsux 31 D A 567 0 lfsx 31 D A 535 0 Table A 20 Floating Point Store Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 stfd 54 S A d stfdu 55 S A d stfdux 31 S A 759 0 stfdx 31 S A 727 0 stfiwx 1 31 S A 983 0 stfs 52 S A d stfsu 53 S A d stfsux 31 S A 695 0 stfsx 31 S A 663 0 1 Optional in the PowerPC architecture Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com Instructions Gro
4. Reserved HTABORG Hashed Page Address 000000 0 6 7 25 26 31 Figure 5 13 HASH1 and HASH2 Registers Table 5 12 describes the bit settings of the HASH1 and HASH2 registers Table 5 12 HASH1 and HASH2 Bit Settings Bits Name Description 0 6 HTABORG 0 6 Copy of the upper 7 bits of the HTABORG field from SDR1 7 25 Hashed page address Address bits 7 25 of the PTEG to be searched 26 31 Reserved 5 5 2 1 4 Required Physical Address Register RPA The RPA is shown in Figure 5 14 During a page table search operation the software must load the RPA with the second word of the correct PTE When the tlbld or tlbli instruction is executed data from the IMISS and ICMP or DMISS and DCMP and the RPA registers is merged and loaded into the selected TLB entry The TLB entry is selected by the effective address of the access loaded by the table search software from the DMISS or IMISS register and SRR1 WAY Reserved RPN RIC WIMG PP 0 19 20 22 23 24 25 28 29 30 31 Figure 5 14 Required Physical Address RPA Register Table 5 13 describes the bit settings of the RPA register Table 5 13 RPA Bit Settings Bits Name Description 0 19 RPN Physical page number from PTE 20 22 Reserved 23 R Referenced bit from PTE 24 C Changed bit from PTE 25 28 WIMG Memory cache access attribute bits 29 Reserved 30 31 PP Page protection bits from PTE
5. Chapter 6 Instruction Timing For More information On This Product Go to www freescale com Fr Instruction Latency Summar y eescale Semiconductor Inc Table 6 6 Load and Store Instructions continued Mnemonic Primary Extended Unit acre Iwbrx 31 534 LSU 2 1 Hex 31 535 LSU 2 1 tlbsync 31 566 LSU 2 amp lfsux 31 567 LSU 2 1 Iswi 31 597 LSU 2 m lfdx 31 599 LSU 2 1 lfdux 31 631 LSU 2 1 stswx 31 661 LSU 1 n amp stwbrx 31 662 LSU 2 1 stfsx 31 663 LSU 2 1 stfsux 31 695 LSU 2 1 stswi 31 725 LSU 1 n amp stfdx 31 727 LSU 2 1 stfdux 31 759 LSU 2 1 Ihbrx 31 790 LSU 2 1 sthbrx 31 918 LSU 2 1 tibid 31 978 LSU 2 amp icbi 31 982 LSU 3 amp stfiwx 31 983 LSU 2 1 tlbli 31 1010 LSU 3 amp dcbz 31 1014 LSU 10 amp Iwz 32 LSU 2 1 lwzu 33 LSU 2 1 Ibz 34 LSU 2 1 Ibzu 35 LSU 2 1 stw 36 LSU 2 1 stwu 37 LSU 2 1 stb 38 LSU 2 1 stbu 39 LSU 2 1 Ihz 40 LSU 2 1 Ihzu 41 LSU 2 1 Iha 42 LSU 2 1 Ihau 43 LSU 2 1 sth 44 LSU 2 1 sthu 45 LSU 2 1 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc truction Latency Summary Table 6 6 Load and Store Instructions continued Mnemonic Primary Extended Unit mci Imw 46 LSU
6. 1 3 5 Memory Management The following sections describe the memory management features of the PowerPC architecture and the MPC603e implementation respectively 1 3 5 1 PowerPC Memory Management The primary functions of the MMU are to translate logical effective addresses to physical addresses for memory accesses and to provide access protection on blocks and pages of memory There are two types of accesses generated by the MPC603e that require address translation instruction accesses and data accesses to memory generated by load and store instructions MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc snecitic Information The PowerPC MMU and exception model support demand paged virtual memory Virtual memory management permits execution of programs larger than the size of physical memory demand paged implies that individual pages are loaded into physical memory from system memory only when they are first accessed by an executing program The hashed page table is a variable sized data structure that defines the mapping between virtual page numbers and physical page numbers The page table size is a power of two and its starting address is a multiple of its size The page table contains a number of page table entry groups PTEGs A PTEG contains 8 page table entries PTEs of 8 bytes each therefore each PTEG is 64 bytes long
7. 1 64 bit instruction Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Legend A 5 Instruction Set Legend Table A 46 provides general information on the PowerPC instruction set such as the architectural level privilege level and form Table A 46 PowerPC Instruction Set Legend UISA VEA OEA Supervisor Level Optional 64 Bit Form addx V XO addcx V XO addex V XO addi V D addic V D addic V D addis V D addmex V XO addzex V XO andx V X andcx V X andi V D andis V D bx V l bcx V B bectrx V XL belrx V XL cmp V X cmpi V D cmpl V X cmpli V D cntlzdx1 V V X cntlzwx V X crand V XL crandc V XL creqv V XL crnand V XL crnor V XL cror V XL crorc V XL crxor V XL MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com dcbf debi 2 dcbst dcbt dcbist dcbz divdx divdux divwx divwux eciwx ecowx eieio eqvx extsbx extshx extswx fabsx faddx faddsx fefidx Tempo fempu fctidx1 fctidzx 1 fctiwx fctiwzx fdivx fdivsx fmaddx fmaddsx fmrx fmsubx fmsubsx fmulx Freescale Semiconductor Inc Instruction Set Legend Table A 46 PowerPC Instruction Set Legend continued
8. MPC603e Bus Transaction 60x Bus Master Source TTO TT1 TT2 TT3 TT4 Specification Transaction Transaction Command Single beat write Caching inhibited 0 0 0 1 O Write with flush Single beat write or write through or burst store Burst nonGBL Cast out or snoop 0 0 d 1 O Write with kill Single beat write copy back or burst Single beat read Caching inhibited 0 1 0 1 0 Read Single beat read load or instruction or burst fetch Burst Load miss store 0 1 1 1 0 Read with intent to Burst miss or instruction modify fetch Single beat write stwex 1 0 0 1 O Write with flush Single beat write atomic N A N A 1 0 1 1 0 Reserved N A Single beat read war 1 1 0 1 0 Read atomic Single beat read caching inhibited or burst load Burst lwarx 1 1 1 1 0 Read with intent to Burst load miss modify atomic N A N A 0 0 0 1 1 Reserved N A N A 0 0 1 1 1 Reserved N A N A 0 1 0 1 1 Read with no intent Single beat read to cache or burst N A N A 0 1 1 1 1 Reserved N A N A 1 X X 1 1 Reserved Table 7 2 describes the 60x bus specification transfer encodings and the MPC603e bus snoop response on an address hit Table 7 2 Snoop Hit Response 60x Bus Specification MFC6036 Bus Ce d Transaction TTO TT1 TT2 TT3 TT4 Snooper Action on Hit Clean block Address only 0 0 0 0 0 N A Flush block Address only 0 0 1 0 0 N A sync Address only 0 1 0 0 0
9. User Read Supervisor Read User Supervisor Option Write Write I Fetch Data I Fetch Data Supervisor only N N Supervisor only no execute N Ni Supervisor write only H d Ni N af Supervisor write only no execute V y Both user supervisor V V V V V y Both user supervisor no execute V V V y Both read only N y Both read only no execute y D e Note vV access permitted protection violation The operating system programs whether instructions can be fetched from an area of memory by appropriately using the no execute option provided in the segment descriptor Each of the remaining options is enforced based on a combination of information in the segment descriptor and the page table entry Thus the supervisor only option allows only read and write operations generated while the processor is operating in supervisor mode corresponding to MSR PR 0 to access the page User accesses that map into a supervisor only page cause an exception to be taken Finally there is a facility in the VEA and OEA that allows pages or blocks to be designated as guarded preventing out of order accesses that may cause undesired side effects For example areas of the memory map that are used to control I O devices can be marked as guarded so that accesses for example instruction prefetches do not occur unless they are explicitly required by the program For more information on memo
10. Chapter 5 Memory Management For More Information On This Product Go to www freescale com Page Table Search Operathreeseale Semiconductor Inc 5 5 2 2 Software Table Search Operation When a TLB miss occurs the instruction or data MMU loads IMISS or DMISS with the effective address of the access The processor completes all instructions ahead of the instruction that caused the exception status information is saved in SRR1 and one of the three TLB miss exceptions is taken In addition the processor loads ICMP or DCMP with the value to be compared with the first word of PTEs in the tables in memory The software should then access the first PTE at the address pointed to by HASH1 The first word of the PTE should be loaded and compared to the contents of DCMP or ICMP If there is a match the required PTE has been found and the second word of the PTE is loaded from memory into RPA Then the tlbli or tlbld instruction is executed which loads the contents of ICMP or DCMP and RPA into the selected TLB entry The TLB entry is selected by the effective address of the access and SRRI WAY If the comparison does not match the PTEG address is incremented to point to the next PTE in the table and the above sequence is repeated If none of the eight PTEs in the primary PTEG matches the sequence is then repeated using the secondary PTEG at the address contained in HASH2 If the PTE is also not found in the eight entries of the secondar
11. Chapter 8 System Interface Operation For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Bus Tenure 0 1 2 3 Bus Clock Se Cite qual_dbg Ke S f Figure 8 7 Data Bus Arbitration 8 4 1 1 Using the DBB Signal The DBB signal should be connected between masters if data tenure scheduling is left to the masters Optionally the memory system can control data tenure scheduling directly with DBG However it is possible to ignore the DBB signal in the system if the DBB input is not used as the final data bus allocation control between data bus masters and if the memory system can track the start and end of the data tenure If DBB is not used to signal the end of a data tenure DBG is only asserted to the next bus master the cycle before the cycle that the next bus master may actually begin its data tenure rather than asserting it earlier usually during another master s data tenure and allowing the negation of DBB to be the final gating signal for a qualified data bus grant Even if DBB is ignored in the system the MPC603e always recognizes its own assertion of DBB and requires one cycle after data tenure completion to negate its own DBB before recognizing a qualified data bus grant for another data tenure If DBB is ignored in the system it must still be connected to a pull up resistor on the MPC603e to ensure proper operation
12. Segment Registers _ _IBATOU ii EAO EA14 a g Ke st UI IBAT3U IBAT3L Cache PAO PA19 Cache Hit Miss IMISS SPR980 ICMP SPR981 SPR25 SPR978 SPR979 SPR982 PAO PA31 Figure 5 2 IMMU Block Diagram MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MMU Features Load Store Unit EAO EA19 EAO EA3 Segment Registers DBAT Array DBATOU DBATOL DBAT3U DBAT3L EA0 EA19 D Cache DMISS SPR976 DCMP SPR977 PAO PA19 D Cache Hit Miss PAO PA31 Figure 5 3 DMMU Block Diagram Chapter 5 Memory Management For More Information On This Product Go to www freescale com MMU Features Freescale Semiconductor Inc 5 1 3 Address Translation Mechanisms Processors that implement the PowerPC architecture support the following four types of address translation e Page address translation translates the page frame address for a 4 Kbyte page size e Block address translation translates the block number for blocks that range in size from 128 Kbytes to 256 Mbytes e Direct store interface address translation used to generate direct store interface accesses on the external bus not implemented in the MPC603e e Real addressing mode translation when address translation is disabled the physical address is identical to the effective address Figu
13. 13 POW Power management enable MPC603e specific 0 Disables programmable power modes normal operation mode 1 Enables programmable power modes nap doze or sleep mode This bit controls the programmable power modes only it has no effect on dynamic power management DPM MSR POW may be altered with an mtmsr instruction only Also when altering the POW bit software may alter only this bit in the MSR and no others The mtmsr instruction must be followed by a context synchronizing instruction See Chapter 9 Power Management for more information 14 TGPR Temporary GPR remapping MPC603e specific 0 Normal operation 1 TGPR mode GPRO GPR3 are remapped to TGPRO TGPR3 for use by TLB miss routines The contents of GPRO GPR3 remain unchanged while MSR TGPR 1 Attempts to use GPR4 GPR31 with MSR TGPR 1 yield undefined results Temporarily replaces TGPRO TGPR3 with GPRO GPR3 for use by TLB miss routines The TGPR bit is set when either an instruction TLB miss data read miss or data write miss exception is taken The TGPR bit is cleared by an rfi instruction 15 ILE Exception little endian mode When an exception occurs this bit is copied into MSR LE to select the endian mode for the context established by the exception 16 EE External interrupt enable 0 The processor ignores external interrupts system management interrupts and decrementer interrupts 1 The processor is enable
14. Chapter 4 Exceptions For More Information On This Product Go to www freescale com Exception Classes Freescale Semiconductor Inc Table 4 2 Exceptions and Conditions Exception Type Vector Offset Causing Conditions hex Reserved 00000 System reset 00100 A system reset is caused by the assertion of either SRESET or HRESET Machine check 00200 A machine check is caused by the assertion of the TEA signal during a data bus transaction assertion of MCP or an address or data parity error DSI 00300 The cause of a DSI exception can be determined by the bit settings in the DSISR listed as follows 1 Set if the translation of an attempted access is not found in the primary hash table entry group HTEG or in the rehashed secondary HTEG or in the range of a DBAT register otherwise cleared 4 Set if a memory access is not permitted by the page or DBAT protection mechanism otherwise cleared 5 Set by an eciwx or ecowx instruction if the access is to an address that is marked as write through or execution of a load store instruction that accesses a direct store segment Set for a store operation and cleared for a load operation 11 Set if eciwx or ecowx is used and EAR E is cleared ISI 00400 An ISI exception is caused when an instruction fetch cannot be performed for any of the following reasons e The effective logical address cannot be translated That is there is a page fault for this portion
15. Explicitly altering certain MSR bits using the mtmsr instruction PTEs or certain system registers may have the side effect of changing the effective or physical addresses from which the current instruction stream is being fetched This kind of side effect is defined as an implicit branch Implicit branches are not supported and an attempt to perform one causes boundedly undefined results Therefore PTEs must not be changed in a manner that causes an implicit branch Chapter 2 Register Set in the Programming Environments Manual lists the possible implicit branch conditions that can occur when system registers and MSR bits are changed 5 5 4 Segment Register Updates Synchronization requirements for using the move to segment register instructions mtsr and mtsrin are described in Synchronization Requirements for Special Registers and for Lookaside Buffers in Chapter 2 Register Set in the Programming Environments Manual Chapter 5 Memory Management For More Information On This Product Go to www freescale com Page Table Search Operathreeseale Semiconductor Inc MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 6 Instruction Timing This chapter describes how the MPC603e microprocessor fetches dispatches and executes instructions and how it reports the results of instruction execution It gives detailed d
16. MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Latency Summary Table 6 5 Floating Point Instructions continued Mnemonic Primary Extended Unit Latency in Cycles mtfsf 63 711 FPU 1 1 18 Notes Cycle times marked with amp require a variable number of cycles due to completion serialization Cycle times marked with immediately forward their CR results to the BPU for fast branch resolution Cycle times marked with a specify the number of clock cycles in each pipeline stage Instructions with a single entry in the cycles column are not pipelined Table 6 6 provides latencies for the load and store instructions Table 6 6 Load and Store Instructions Mnemonic Primary Extended Unit AA Iwarx 31 020 LSU 2 1 Iwzx 31 023 LSU 2 1 dcbst 31 054 Sie SE Iwzux 31 055 LSU 2 1 dcbf 31 086 LSU 2 58 Ibzx 31 087 LSU 2 1 Ibzux 31 119 LSU 2 1 stwcx 31 150 LSU 8 stwx 31 151 LSU 2 1 stwux 31 183 LSU 2 1 stbx 31 215 LSU a dcbtst 31 246 LSU S stbux 31 247 LSU 2 1 dcbt 31 278 LSU 2 Ihzx 31 279 LSU ie tlbie 31 306 LSU 3 amp eciwx 31 310 LSU 2 1 Ihzux 31 311 LSU a Ihax 31 343 LSU 2 1 Ihaux 31 375 LSU 2 1 sthx 31 407 LSU 2 1 ecowx 31 438 LSU aA sthux 31 439 LSU ed debi 31 470 ee eS Kee 31 533 LSU 2 n amp
17. e Nap tThe nap mode further reduces power consumption by disabling bus snooping leaving only the time base register and the PLL in a powered state The MPC603e returns to the full power state upon receipt of an external asynchronous interrupt system management interrupt decrementer exception hard or soft reset or machine check input MCP signal A return to full power state from a nap state takes only a few processor clock cycles e Sleep Sleep mode reduces power consumption to a minimum by disabling all internal functional units after which external system logic may disable the PLL and SYSCLK Returning the MPC603e to the full power state requires the enabling of the PLL and SYSCLK followed by the assertion of an external asynchronous interrupt system management interrupt hard or soft reset or MCP signal after the time required to relock the PLL Note that the MPC603e cannot switch from one power management mode to another without first returning to full on mode The nap and sleep modes disable bus snooping therefore a hardware handshake is provided to ensure coherency before the MPC603e enters these power management modes Table 9 1 summarizes the four power states for the core MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING mmable E Table 9 1 MPC603e Programmable Power Modes PM Mode Functioning Units Ac
18. Following are the state meaning and timing comments for the TT 0 3 inputs State Meaning Asserted Negated Indicates the type of transfer in progress see Table 7 2 Timing Comments Assertion Negation The same as A 0 31 Table 7 1 describes the transfer encodings for a MPC603e bus master Table 7 1 Transfer Encoding for the Bus Master MPC603e Bus Transaction 60x Bus Master Source TTO TT1 TT2 TT3 TT4 Specification Transaction Transaction Command N A N A 0 0 0 0 0 Clean block Address only N A N A 0 0 1 0 0 Flush block Address only N A N A 0 1 0 0 0 sync Address only Address only dcbz 0 1 1 0 0 Kill block Address only N A N A 1 0 0 0 O eieio Address only Single beat write ecowx 1 0 1 0 O0 External control word Single beat write nonGBL write N A N A 1 1 0 0 0 TLB invalidate Address only Single beat read eciwx 1 1 1 0 0 External control word Single beat read nonGBL read N A N A 0 0 0 0 1 war Address only Reservation set N A N A 0 0 1 0 1 Reserved N A N A 0 1 0 0 1 tlbsync Address only N A N A 0 1 1 0 1 ich Address only N A N A 1 X X 0 1 Reserved Chapter 7 Signal Descriptions For More information On This Product Go to www freescale com Signal Descriptions Freescale Semiconductor Inc Table 7 1 Transfer Encoding for the Bus Master continued
19. describes the MSR which controls some of the critical functionality of the MMUs 5 1 MMU Features The MPC603e implements the memory management specification of the PowerPC OEA for 32 bit implementations Thus it provides 4 Gbytes of effective address space accessible to supervisor and user programs with a 4 Kbyte page size and 256 Mbyte segment size In addition the MMUs of 32 bit processors use an interim virtual address 52 bits and hashed page tables in the generation of 32 bit physical addresses These processors also have a BAT mechanism for mapping large blocks of memory Block sizes range from 128 Kbytes to 256 Mbytes and are software programmable The MPC603e completely implements all features required by the MMU specifications of the PowerPC architecture OEA for 32 bit implementations Table 5 1 summarizes all MPC603e MMU features including the architectural features of PowerPC MMUs defined by the OEA for 32 bit processors and the implementation specific features provided by the MPC603e Table 5 1 MMU Features Summary Architecturally Defined Feature Category MPC603e Specific Feature Address ranges Architecturally defined 2 2 bytes of effective address 2 2 bytes of virtual address 232 bytes of physical address Page size Architecturally defined 4 Kbytes Segment size Architecturally defined 256 Mbytes Block address Architecturally defined Range of 128 Kbytes 256 Mbytes sizes translati
20. 128 Sets Block 0 Kees ees y ea y Tra Hee r L Trsno bal etor L ena li bal n L Le 8 Words Block Figure 1 3 Data Cache Organization Block 1 Block 2 Block 3 The instruction cache also consists of 128 sets of four blocks and each block consists of 32 bytes an address tag and a valid bit The instruction cache may not be written to except through a block fill operation In the PID7t 603e the instruction cache is blocked only until the critical load completes The PID7t 603e supports instruction fetching from other instruction cache lines following the forwarding of the critical first double word of a cache line load operation Successive instruction fetches from the cache line being loaded are forwarded and accesses to other instruction cache lines can proceed during the cache line load operation The instruction cache is not snooped and cache coherency must be maintained by software A fast hardware invalidation capability is provided to support cache maintenance The organization of the instruction cache is very similar to the data cache shown in Figure 1 3 Each cache block contains eight contiguous words from memory that are loaded from an 8 word boundary that is bits A 27 31 of the effective addresses are zero thus a cache block never crosses a page boundary Misaligned accesses across a page boundary can incur a performance penalty The MPC603e cache blocks are loaded in four
21. Name Mnemonic Operand Syntax Move from Machine State Register mfmsr rD Move to Machine State Register mtmsr rs 2 3 6 2 2 Move To From Special Purpose Register Instructions Simplified mnemonics are provided for the mtspr and mfspr instructions so they can be coded with the SPR name as part of the mnemonic rather than as a numeric operand See Appendix F Simplified Mnemonics in the Programming Environments Manual for simplified mnemonic examples The mtspr and mfspr instructions are shown in Table 2 39 Table 2 39 Move To From Special Purpose Register Instructions Name Mnemonic Operand Syntax Move from Special Purpose Register mfspr rD SPR Move to Special Purpose Register mtspr SPR rS For mtspr and mfspr instructions the SPR number coded in assembly language does not appear directly as a 10 bit binary number in the instruction The number coded is split into two 5 bit halves that are reversed in the instruction encoding with the high order 5 bits appearing in bits 16 20 of the instruction encoding and the low order 5 bits in bits 11 15 If the SPR field contains any value other than one of the values shown in Table 2 40 either the program exception handler is invoked or the results are boundedly undefined Table 2 40 Implementation Specific SPR Encodings mfspr SPR Register Name Decimal spr 5 9 spr 0 4 976 11110 10000 DMISS 977 11110 10001 DCMP 978 111
22. Real address Physical address Relocation Translation Storage locations Memory Storage the act of Access Store in Write back Store through Write through About This Book For More Information On This Product Go to www freescale com __Freescale Semiconductor Inc Terminology Conventions Table iii describes instruction field notation used in this manual Table iii Instruction Field Conventions The Architecture Specification Equivalent to BA BB BT crbA crbB crbD respectively BF BFA crfD erfS respectively D d DS ds FLM FM FRA FRB FRC FRT FRS frA frB frC frD frS respectively FXM CRM RA RB RT RS rA rB rD rS respectively SI SIMM U IMM UI UIMM 11 AN 0 0 shaded MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 1 Overview This chapter provides an overview of features for the MPC603e microprocessor and PowerPC architecture and information about how the MPC603e implementation complies with the architectural definitions Note that the MPC603e microprocessor is implemented in both a 2 5 volt version PID 0007t MPC603e microprocessor abbreviated as PID7t 603e and a 3 3 volt version PID 0006 MPC603e microprocessor abbreviated as PID6 603e Note that the PID6 603e is end of life and not rec
23. The same as A 0 31 Table 7 4 Data Transfer Size TBST TSIZ 0 2 Transfer Size Asserted 010 Burst 82 bytes Negated 000 8 bytes Negated 001 1 byte Negated 010 2 bytes Negated 011 3 bytes Negated 100 4 bytes Negated 101 5 bytes Negated 110 6 bytes Negated 111 7 bytes 7 2 4 3 Transfer Burst TBST The TBST signal is an input output signal 7 2 4 3 1 Transfer Burst TBST Output Following are the state meaning and timing comments for the TBST output State Meaning Asserted Indicates that a burst transfer is in progress Negated Indicates that a burst transfer is not in progress For external control instructions eciwx and ecowx TBST is used to output EAR 28 which is used to form the resource ID TBSTIITSIZ 0 2 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc i D Signal Descriptions Timing Comments Assertion Negation The same as A 0 31 High Impedance The same as A 0 31 7 2 4 3 2 Transfer Burst TBST Input Following are the state meaning and timing comments for the TBST input State Meaning Asserted Negated Used when snooping for single beat reads read with no intent to cache Timing Comments Assertion Negation The same as A 0 31 7 2 4 4 Transfer Code TC 0 1 Output The TC 0 1 consists of two output signals on the MPC603e Fo
24. eee eceeeeeeseceseeeeeeeeseeeeeens Floating Point Rounding and Conversion Instructions seers Floating Point Compare Instructions 0 e eee eeseceseceeeeeeseecesecnteeeseeeenees Floating Point Move Instructons cc eeeeeseceeceeseeeseecsaeeeseeseeeesaeeeaeens Integer Load Hoster ees Integer Store InstruCu d nsdes EE Integer Load and Store with Byte Reverse Instructtong eee Integer Load and Store Multiple Instructons eee eeeeeeeeeeereeeeeeees Integer Load and Store String Instructions 0 00 0 eeeeeseeeseceeeeeeneeenaeeees Floating Point Load Instructions ee eeeeeseceseceseeeeeeeeacecsaeeneeeseeeeaeees Floating Point Store Instructions cece ceseceeeeeereeeseeceeeceeeeseeeesaeeenaeens Branch Tt een deed Tables For More Information On This Product Go to www freescale com Page Number XX Freescale Semiconductor Inc Tables Table Number Title 2 29 Condition Register Logical Instructons cece eeseesseceseeeeeeeeseeseaeeneeeeees 2 30 Trap Otter 2 31 Move To From Condition Register Instructons 2 32 Memory Synchronization Instructions UISA 0 cece ese ceseeeseeeeeeeenees 2 33 Move From Time Base Instructions 12 esughrdeieh ee edd gue 2 34 Memory Synchronization Instructons NEA eee eeeeeeeeeeseeceteeneeeeeeeeeaees 2 35 User Level Cache Luten Sa eee ee 2 36 External Control Instructions eege so cents tease the cceaa eege eegen 2 37 System Linkage Instructions ica cuteness EEN 2 38 Move To Fr
25. s manuals These books provide details about individual implementations and are intended for use with the Programming Environments Manual Addenda errata to user s manuals Because some processors have follow on parts an addendum is provided that describes the additional features and functionality changes These addenda are intended for use with the corresponding user s manual Implementation Variances Relative to Rev 1 of The Programming Environments Manual is available at http www freescale com Hardware specifications Hardware specifications provide specific data regarding bus timing signal behavior and AC DC and thermal characteristics as well as other design considerations Technical Summaries Each device has a technical summary that provides an overview of its features This document is roughly the equivalent to the overview Chapter 1 of an implementation s user s manual The Programmer s Reference Guide for the PowerPC Architecture MPCPRG D This concise reference includes the register summary memory control model exception vectors and the PowerPC instruction set The Programmer s Pocket Reference Guide for the PowerPC Architecture MPCPRGREF D This foldout card provides an overview of PowerPC registers instructions and exceptions for 32 bit implementations Application notes These short documents contain useful information about specific design issues useful to programmers and engineers working wi
26. 0 0 0 0 0 0 0 ILE Alignment 0 0 0 0 0 0 0 0 0 0 0 0 ILE Program 0 0 0 0 0 0 0 0 0 0 0 0 ILE Floating point 0 0 0 0 0 0 0 0 0 0 0 0 ILE unavailable Decrementer 0 0 0 0 0 0 0 0 0 0 0 0 ILE System call 0 0 0 0 0 0 0 0 0 0 0 0 ILE Trace 0 0 0 0 0 0 0 0 0 0 0 0 ILE exception ITLB miss 0 1 0 0 0 0 0 0 0 0 0 0 ILE DTLB miss on 0 1 0 0 0 0 0 0 0 0 0 0 ILE load DTLB miss on 0 1 0 0 0 0 0 0 0 0 0 0 ILE store Instruction 0 0 0 0 0 0 0 0 0 0 0 0 ILE address breakpoint MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ee Exception Definitions Table 4 8 MSR Setting Due to Exception continued Exception MSR Bit Type POW TGPR ILE EE PR FP ME FEO SE BE FE1 IP IR DR RI LE System 0 0 0 0 0 0 0 0 0 0 0 0 ILE management interrupt Note 0 Bit is cleared 1 Bit is set ILE Bit is copied from the ILE bit in the MSR Bitis not altered Reserved bits are read as if written as 0 4 5 1 Reset Exceptions 0x00100 The system reset exception is a nonmaskable asynchronous exception signaled to the MPC603e either through the assertion of the reset
27. 0 V Valid bit Set by the processor on a TLB miss exception 1 24 VSID Virtual segment ID Copied from VSID field of corresponding segment register 25 Reserved should be cleared 26 31 JAPI Abbreviated page index Copied from API of effective address 2 1 2 4 Primary and Secondary Hash Address Registers HASH1 and HASH2 HASH1 and HASH2 shown in Figure 2 6 contain the physical addresses of the primary and secondary PTEGs for the access that caused the TLB miss exception For convenience the MPC603e automatically constructs the full physical address by routing SDR1 0 6 into HASH1 and HASH2 and clearing the lower 6 bits These read only registers are constructed from the DMISS or IMISS contents the register choice is determined by which miss most recently occurred HTABORG 0 6 Hashed Page Address 000000 0 67 25 26 31 Figure 2 6 HASH1 and HASH2 Registers Table 2 6 describes the bit settings of the HASH1 and HASH registers Table 2 6 HASH1 and HASH2 Bit Settings Bits Name Description 0 6 HTABORG O 6 Copy of the upper 7 bits of the HTABORG field from SDR1 7 25 Hashed page address Address bits 7 25 of the PTEG to be searched 26 31 Reserved Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Register Set 2 1 2 5 Required Physical Address Register RPA Du
28. 4 Out of order store operation for instructions that will Maybe No No No cause no other kind of precise exception in the absence of system caused imprecise or floating point assist exceptions 5 All other out of order store operations Maybe No Maybe No 6 Zero length load Iswx Maybe Yes No No 7 Zero length store stswx Maybe Yes Maybe Yes 8 Store conditional stwcx that does not store Maybe Yes Maybe Yes 9 In order instruction fetch Yes 2 Yes No No 10 Load instruction or eciwx Yes Yes No No 11 Store instruction ecowx or debz instruction Yes Yes Yes Yes 12 dcbt dcbtst dcbst or debf instruction Maybe Yes No No 13 icbi instruction Maybe 1 No No 1 No 14 debi instruction Maybe 1 Yes Maybe Yes 1 f C is set R is guaranteed to also be set 2 This includes the case when the instruction was fetched out of order and R was not set does not apply for the MPC603e For more information see Page History Recording in Chapter 7 Memory Management of the Programming Environments Manual 5 4 2 Page Memory Protection The MPC603e implements page memory protection as it is defined in Chapter 7 Memory Management in the Programming Environments Manual 5 4 3 TLB Description This section describes the hardware resources provided in the MPC603e to facilitate the page address translation process Note that the hardware implementation of the MMU is not specifi
29. 6 r2 update page table Replace the third line from the top of the page with the following dsi2 if little endian then The second part of the DBG bullet should be edited to read as follows The DBB signal is driven by the current bus master DRTRY is only driven from the bus ARTRY is driven from the bus but only for the address bus tenure The cross references at the end of this section should be to Table 7 1 and Table 7 2 instead of Table 8 1 and Table 8 2 The fifth entry in the TSIZ O 2 column second access for the second misaligned entry should be 010 instead of 011 Replace sentences 3 5 with the following Although AACK can be asserted as early as the bus clock cycle following TS see Figure 8 7 which allows a minimum address tenure of two bus cycles when the 603e clock is configured for 1 1 or 1 5 1 processor to bus clock mode the ARTRY snoop response cannot be determined in the minimum allowed address tenure period Thus in a system with two or more 603e processors using 1 1 or 1 5 1 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com 8 4 4 1 8 27 8 7 4 8 42 8 8 1 8 42 9 2 9 2 9 2 1 4 9 4 9 2 1 5 9 5 Freescale Semicond uctor doe Revision 1 to Revision 2 clock mode AACK must not be asserted until the third clock of the address tenure one address wait state to allow the snooping 603e processors an opportunity t
30. CLK_OUT Output State 0 0 High impedance 0 1 Processor clock frequency 1 0 Half bus clock frequency 1 1 Bus clock frequency The CLK_OUT signal is an output only signal on the MPC603e Following are the state meaning and timing comments for the CLK_OUT output State Meaning Asserted Negated Provides PLL clock output for PLL testing and monitoring The CLK_OUT signal clocks at either the processor clock frequency bus clock frequency or half bus clock frequency if enabled by the appropriate bits in the HIDO register the default state of CLK_OUT is high impedance CLK_OUT is provided for testing purposes only Timing Comments Assertion Negation Refer to the appropriate hardware specifications for timing comments 7 2 12 3 PLL Configuration PLL_CFG 0 3 Input The PLL is configured by PLL_CFG 0 3 For a given SYSCLK bus frequency the PLL configuration signals set the internal CPU frequency of operation Table 7 10 shows the PLL configuration Following are the state meaning and timing comments for the PLL_CFG 0 3 input State Meaning Asserted Negated Configures the operation of the PLL and the internal processor clock frequency Settings are based on the desired bus and internal frequency of operation MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Signal Descriptions Timing Comments Assertion Negation Must
31. If I O devices require load and store accesses to occur in strict program order strongly ordered translation must be enabled so that the corresponding I bit can be set Also for instruction accesses the default memory access mode bits WIMG are 0b0001 That is instruction accesses are considered cacheable I 0 and the memory is guarded Again instruction cache accesses are considered cacheable even if the instruction cache is disabled in the HIDO register as it is out of hard reset The W and M bits have no effect on the instruction cache Chapter 5 Memory Management For More Information On This Product Go to www freescale com GE e Translatio TEE Seale Semiconductor Inc For information on the synchronization requirements for changes to MSR IR and MSR DR refer to Synchronization Requirements for Special Registers and for Lookaside Buffers in Chapter 2 Register Set in the Programming Environments Manual 5 3 Block Address Translation The block address translation BAT mechanism in the OEA provides a way to map ranges of effective addresses larger than a single page into contiguous areas of physical memory Such areas can be used for data that is not subject to normal virtual memory handling paging such as amemory mapped display buffer or an extremely large array of numerical data The software model for block address translation in the MPC603e is described in Chapter 7 Memory Management in the
32. Inc Glossary of Terms and Abbreviations The glossary contains an alphabetical list of terms phrases and abbreviations used in this book Some of the terms and definitions included in the glossary are reprinted from IEEE Standard 754 1985 IEEE Standard for Binary Floating Point Arithmetic copyright 1985 by the Institute of Electrical and Electronics Engineers Inc with the permission of the IEEE A Architecture A detailed specification of requirements for a processor or computer system It does not specify details of how the processor or computer system must be implemented instead it provides a template for a family of compatible implementations Asynchronous exception Exceptions that are caused by events external to the processor s execution In this document the term asynchronous exception is used interchangeably with the word interrupt Atomic access A bus access that attempts to be part of a read write operation to the same address uninterrupted by any other access to that address the term refers to the fact that the transactions are indivisible The PowerPC architecture implements atomic accesses through the Iwarx stwex instruction pair B BAT block address translation mechanism A software controlled array that stores the available block address translations on chip Beat A single state on the MPC603 e bus interface that may extend across multiple bus cycles A MPC603e transaction can be composed of multi
33. MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Mes able De E entry Not Found synthesize an ISI exception guarded memory protection violation synthesize an ISI exception Entry id r0 is saved counter ri is junk ia r2 is pointer to pteg H r3 is current compare value i doISIp mfspr r3 SEL get srrl andi r2 xr3 0xfffFf clean upper srrl addis r2 r2 0x0800 or in srr lt 4 gt 1 to flag prot violation b isil doISI mfspr E37 28 rl get srrl andi ro T3 OXPL LT clean srrl addis r2 r2 0x4000 or in srrl lt 1l gt 1 to flag pte not found isil mtctr r0 restore counter mtspr SE lt 2 set srrl mfmsr ro get msr xoris r0 r0 0x8000 flip the msr lt tgpr gt bit mtcrf 0x80 r3 restore CRO mtmsr ro flip back to the native gprs b vec400 go to instr access exception Data TLB miss flow Entry Vec 1100 srro gt address of instruction that caused data tlb miss i srrl gt 0 3 cr0 4 lru way bit 5 1 if store 16 31 saved MSR msr lt tgpr gt gt 1 dMiss gt ea that missed dCmp gt the compare value for the va that missed F hashl gt pointer to first hash pteg hash2 gt pointer to second hash pteg Register usage F r0 is saved counter rl is junk r2 is pointer to pteg r3 is current compare value Ht csect tlbmiss PR sorg vec0 0x1100 tlbDataMiss mfspr r2 hashi get first pointer addi Le 28
34. MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timing Considerations Fetch in IQ In Dispatch Entry 1Q0 IQ1 a Execute SE Complete In CQ a In Retirement Entry CQ0 CQ1 12 fadd 13 add 14 fadd Instruction Queue 11 14 10 12 13 14 Completion Queue 11 13 3 6 9 10 10 12 14 2 3 3 8 8 9 9 11 13 14 14 1 1 2 2 6 7 7 8 8 10 12 13 13 0 0 1 1 3 6 6 7 7 9 11 12 12 14 Figure 6 5 Instruction Timing Cache Hit Chapter 6 Instruction Timing For More Information On This Product Go to www freescale com Timing Considerations Oo OAD OB YA OB WNEF CH Freescale Semiconductor Inc br 6 fsub fadd fadd add add and and fadd add fadd The instruction timing for this example is described cycle by cycle as follows 0 In cycle 0 instructions 0 and 1 are fetched from the instruction cache and are placed in the two entries in the instruction queue IQO and IQ1 where they can be
35. Many of these instructions execute in a single clock cycle The integer unit has one execute stage so when a multiple cycle integer instruction is executed no other integer instructions can also begin to execute See Table 6 4 for integer instruction execution timing 6 4 3 Floating Point Unit Execution Timing The FPU on the MPC603e executes all floating point computational instructions The LSU performs integer floating point loads and stores Execution of most floating point instructions is pipelined within the FPU allowing up to three instructions to be executing in the FPU concurrently While most floating point instructions execute with 3 or 4 cycle latency and 1 or 2 cycle throughput 3 instructions fdivs fdiv and fres execute with latencies of 18 to 33 cycles The fdivs fdiv fres mtfsb0 mtfsb1 mtfsfi mffs and mtfsf instructions block the floating point unit pipeline until they complete execution and thereby inhibit the dispatch of additional floating point instructions With the exception of the merfs instruction all floating point instructions will immediately forward their CR results to the BPU for fast branch resolution without waiting for the instruction to be retired by the completion unit and the CR updated See Table 6 5 for floating point instruction execution timing Chapter 6 Instruction Timing For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Performance Co
36. PTE V 1 cannot be located Page table A table in memory is comprised of page table entries or PTEs It is further organized into eight PTEs per PTEG page table entry group The number of PTEGs in the page table depends on the size of the page table as specified in the SDR1 register Page table entry PTE Data structures containing information used to translate effective address to physical address on a 4 Kbyte page basis A PTE consists of 8 bytes of information in a 32 bit processor and 16 bytes of information in a 64 bit processor Park The act of allowing a bus master to maintain bus mastership without having to arbitrate Glossary of Terms and Abbreviations For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Physical memory The actual memory that can be accessed through the system s memory bus Pipelining A technique that breaks operations such as instruction processing or bus transactions into smaller distinct stages or tenures respectively so that a subsequent operation can begin before the previous one has completed Precise exceptions A category of exception for which the pipeline can be stopped so instructions that preceded the faulting instruction can complete and subsequent instructions can be flushed and redispatched after exception handling has completed See mprecise exceptions Primary opcode The most significant 6 bits bits 0 5 of the instruction
37. SR SR lt rS misrin rS rB Move to Segment Register Indirect SR rB O 3 lt rS mfsr rD SR Move from Segment Register rD lt SR SR mfsrin rD rB Move from Segment Register Indirect rD lt SR rB 0 3 tlbie rB TLB Invalidate Entry For effective address specified by rB TLB V 0 The tlbie instruction invalidates both TLB entries indexed by the EA and operates on both the instruction and data TLBs simultaneously invalidating four TLB entries The index corresponds to bits 15 19 of the EA Software must ensure that instruction fetches or memory references to the virtual pages specified by the tlbie instruction have been completed prior to executing the tlbie instruction tlbsync 1 TLB Synchronize Synchronizes the execution of all other tlbie instructions in the system In the MPC603e when the TLBISYNC signal is negated instruction execution may continue or resume after the completion of a tlbsync instruction When the TLBISYNC signal is asserted instruction execution stops after the completion of a tlbsync instruction For a complete description of the TLBISYNC signal refer to Section 8 8 2 TLBISYNC Input Chapter 5 Memory Management For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MMU Features Table 5 5 Instruction Summary MMU Control continued Instruction Description tlbli Load Instruction TLB Entry MPC603e specific Loads th
38. Subsequent instructions should include a sync and tlbsync instruction before any MMU table changes are performed This prevents the MPC603e from making table changes disruptive to the other master during the DMA period 8 9 IEEE 1149 1 Compliant Interface The MPC603e boundary scan interface is a fully compliant implementation of the IEEE 1149 1 standard This section describes the MPC603e IEEE 1149 1 JTAG interface 8 9 1 IEEE 1149 1 Interface Description The MPC603e has five dedicated JTAG signals described in Table 8 11 The TDI and TDO scan ports are used to scan instructions as well as data into the various scan registers for JTAG operations The scan operation is controlled by the test access port TAP controller which in turn is controlled by the TMS input sequence The scan data is latched in at the rising edge of TCK Table 8 11 IEEE Interface Pin Descriptions Signal Name Input Output Wee IEEE 1149 1 Function TDI Input Yes Serial scan input signal TDO Output No Serial scan output signal TMS Input Yes TAP controller mode signal TCK Input Yes Scan clock TRST Input Yes TAP controller reset TRST is a JTAG optional signal used to reset the TAP controller asynchronously The TRST signal assures that the JTAG logic does not interfere with the normal operation of the chip and can be asserted coincident with the HRESET The PID7t 603e implements the JTAG COP in the same manner as does the P
39. When SRESET is asserted the processor attempts to reach a recoverable state by allowing the next instruction to either complete or cause an exception blocking the completion of subsequent instructions and allowing the completed store queue to drain Unlike a hard reset no registers or latches are initialized however the instruction cache is disabled HIDO ICE 0 After SRESET is recognized as asserted the processor begins fetching instructions from the system reset routine at offset 0x0100 When a soft reset MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Can Exception Definitions occurs registers are set as shown in Table 4 10 A soft reset is recoverable provided that attaining the recoverable state does not cause a machine check exception This interrupt case is third in priority following hard reset and machine check When a soft reset occurs registers are set as shown in Table 4 10 in addition to the clearing of HIDO ICE Table 4 10 Soft Reset Exception Register Settings Register Setting Description SRRO Set to the effective address of the instruction that the processor would have attempted to complete next if no exception conditions were present SRR1 0 15 Cleared 16 31 Loaded from MSR 16 31 Note that if the processor state is corrupted to the extent that execution cannot be reliably restarted SRR1 30 is cleare
40. cmpi addic addic addi addis bcx sc bx mcrf bclrx crnor rfi crandc isync crxor crnand crand creqv crorc cror bectrx rlwimix rlwinmx rlwnmx ori oris xori xoris Instructions Sorted by Opcode Table A 2 lists the instructions defined in the PowerPC architecture in numeric order by Instructions Sorted by oe EC ale Semiconductor Inc Table A 2 Complete Instruction List Sorted by Opcode 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 000010 TO A SIMM 000011 TO A SIMM 000111 D A SIMM 001000 A SIMM 001010 crfD JOJL A UIMM 001011 crfD JOJL A SIMM 001100 D A SIMM 001101 D A SIMM 001110 D A SIMM 001111 D A SIMM 010000 BO BI BD AA LK 010001 00000 00000 000000000000000 110 010010 LI AA LK 010011 crfD 00 crfS 00 00000 0000000000 0 010011 BO BI 00000 0000010000 LK 010011 crbD crbA crbB 0000100001 0 010011 00000 00000 00000 0000110010 0 010011 crbD crbA crbB 0010000001 0 010011 00000 00000 00000 0010010110 0 010011 crobD crbA crbB 0011000001 0 010011 crobD crbA crbB 0011100001 0 010011 crobD crbA crbB 0100000001 0 010011 crobD crbA crbB 0100100001 0 010011 crbD crbA crbB 0110100001 0 010011 crobD crbA crbB 0111000001 0 010011 BO BI 00000 1000010000 LK 010100 S A SH MB ME Rc 010101 S A SH MB ME Rc 010111 S A B MB ME Rc 011000 S A UIMM 011001 S A UIMM 011
41. load 8 for counter mfctr ro save counter mfspr r3 dCmp get first compare value addi r2 r2 8 pre dec the pointer Chapter 5 Memory Management For More information On This Product Go to www freescale com i Inc Page Table Search operai eescale Semiconductor e dm0 mtctr rl load counter dml lwzu rl 8 r2 get next pte cmp Oy 22 3 see if found pte bdnzft D dml dec count br if cmp ne and if count not zero bne dataSecHash if not found set up second hash or exit 1 rl 4 r2 load tlb entry lower word mtctr ro restore counter mfspr r0 dMiss get the miss address for the tlbld mfspr 3 SEY1 get the saved cr0 bits mtcrf 0x80 r3 restore CRO mtspr rpa rl set the pte ori ri St 0xXL00 set reference bit srw ri EL BS get byte 7 of pte tlbld ro load the dtlb stb rl 6 r2 update page table rfi return to executing program 4 Register usage rO is saved counter H rl is junk r2 is pointer to pteg r3 is current compare value dataSecHash andi rl r3 0x0040 s if we have done second hash bne doDSI if so go to DSI exception mfspr r2 hash2 get the second pointer ori r3 r3 0x0040 change the compare value addi IL 0 8 load 8 for counter addi 2 2 8 pre dec for update on load b Om try second hash C 0 in dtlb and dtlb miss on store flow Entry Vec 1200 i srro gt address of store that caused the exception srrl gt 0 3 cr0 4 lru way bit 5 1 16 31 saved MSR F msr lt
42. page marked global through the WIM bits an address only bus transaction is run The function of this instruction is independent of the write through and caching inhibited caching allowed modes of the block containing the byte addressed by the EA This instruction is treated as a load to the addressed byte with respect to address translation and protection 3 7 6 Data Cache Block Flush dcbf Instruction The action taken depends on the memory mode associated with the target and on the state of the cache block The following list describes the action taken for the various cases These actions are executed regardless of whether the page containing the addressed byte is in caching inhibited or caching allowed mode The following actions occur in both coherency required WIM Obxx1 and coherency not required mode WIM Obxx0 The debf instruction causes the following cache activity e Unmodified block invalidates the block in the processor s cache e Modified block copies the block to memory and invalidates data cache block e Absent block does nothing The MPC603e treats this instruction as a load to the addressed byte with respect to address translation and protection 3 7 7 Enforce In Order Execution of I O Instruction eieio As defined by the PowerPC architecture the eieio instruction provides an ordering function for the effects of load and store instructions executed by a given processor Executing eieio ensures that all m
43. performance the MPC603e has two TLBs to store recently used PTEs on chip If an access hits in the appropriate TLB the page translation occurs and the physical address bits are forwarded to the memory subsystem If the required PTE is not resident the MMU requires a search of the page table In this case the MPC603e traps to one of three exception handlers for the system software to perform the page table search If the PTE is successfully matched a new TLB entry is created and the page translation is once again attempted This time the TLB is guaranteed to hit Once the PTE is located the access is qualified with the appropriate protection bits If the access is a protection violation not allowed an exception instruction access or data access is generated If the PTE is not found by the table search operation a page fault condition exists and the TLB miss exception handlers synthesize either an ISI or DSI exception to handle the page fault 5 1 7 MMU Exceptions Summary In order to complete any memory access the effective address must be translated to a physical address In the MPC603e an MMU exception condition occurs if this translation fails for one of the following reasons e Page fault There is no valid entry in the page table for the page specified by the effective address and segment descriptor and there is no valid BAT translation e An address translation is found but the access is not allowed by the memory protect
44. reservation does not exist e Accesses that cause exceptions and are not completed 5 4 1 2 Changed Bit The changed bit of a page is located both in the PTE in the page table and in the copy of the PTE loaded into the TLB if a TLB is implemented as in the MPC603e Whenever a data store instruction is executed successfully if the TLB search for page address translation results in a hit the changed bit in the matching TLB entry is checked If it is already set the processor does not change the C bit If the TLB changed bit is zero it is set and a table search operation is performed to also set the C bit in the corresponding PTE in the page table The MPC603e causes a data TLB miss on store exception for this case so that the software can perform the table search operation for setting the C bit Refer to Section 5 5 2 Implementation Specific Table Search Operation for an example code sequence that handles these conditions MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Segment Model The changed bit in both the TLB and PTE in the page tables is set only when a store operation is allowed by the page memory protection mechanism and all conditional branches occurring earlier in the program have been resolved such that the store is guaranteed to be in the execution path Furthermore the following conditions may cause the C bit to be
45. rest addis ri rl 0x0800 or in dsisr lt 4 gt 1 to flag prot violation dsil mtctr ro restore counter andi C2 23 OxXEFEE clear upper bits of srrl mtspr srrl r set srrl mtspr dsisr 1 load the dsisr mfspr rl dMiss get miss address rlwinm EI 31 31 test LE bit beq dsi2 if little endian then xor rl rl 0x07 de mung the data address dsi2 mtspr dar rl put in dar mfmsr r0 get msr xoris r0 r0 0x2 flip the msr lt tgpr gt bit mtcrf 0x80 x3 restore CRO mtmsr ro flip back to the native gprs b vec300 branch to DSI exception MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Mes able BCEE 5 5 3 Page Table Updates TLBs are defined as noncoherent caches of the PTEs TLB entries must be flushed explicitly with the TLB invalidate entry instruction bie whenever the corresponding PTE is modified Because the MPC603e is intended primarily for uniprocessor environments it does not provide coherency checking for TLBs between multiple processors If the MPC603e is used in a multiprocessor environment where TLB coherency is required synchronization must be implemented in software Processors may write referenced and changed bits with unsynchronized atomic byte store operations Note that each V R and C bits reside in a distinct byte of a PTE Therefore extreme care must be taken to use byte writes when updating only one of these bits
46. set msr pow bit to go into sleep mode sync mfmsr addis ori or mtmsr isync addis ori stay_here addic r5 r3 r0 0x0004 CZ r37 0x0000 344 844 GS rh r20 CD 0x0000 r20 r20 0x0002 r20 r20 zl bgt cr0 stay_here restore corrupted registers LWZ mtcrf r23 0x05e4 Oxff r23 r23 0x05e8 r22 0x05ec srrl r22 r21 0x05f0 get MSR turn on POW bit turn on ME bit 19 subtract 1 from r20 and set cc loop if positive JO CU FEO EH Chapter 9 Power Management For More Information On This Product Go to www freescale com Example Code Sequence Freescale Sem mtspr lwz lwz sync rfi rr r21 r20 0x05f4 r0 CD Da O05fc r0 conductor Inc HE A He Ie A A A I AA AA A I I A A I I He to get out of sleep mode do a Soft Reset EK A Hk I A I AA I AAA I AA A I A I A A I I Hk ke orig 0x00000100 force big endian mode stw stw mfmsr ori ori ori xori ori mtmsr ori isync ori r0 0x r0 0x ro CU CU r0 x0 r0 x0 CU CU r0 xr0 ro r0 x0 CU CU O5 8 r0 05 G 70 ED 0x0001 x0 0x0001 SEH x0 x0 Reset handler in low memory need nop every second inst force big endian LE bit force big endian LE bit save off additional registers to be corrupted stw stw stw stw mfcr stw xor restore corrupted lwz mtcrft lwz lwz lwz lwz lwz sync rfi r20
47. www freescale com Freescale Semiconductor Inc Instruction Set Legend Table A 46 PowerPC Instruction Set Legend continued UISA VEA OEA Supervisor Level Optional 64 Bit Form Ihau V D Ihaux V x Ihax V x Ihbrx V x Ihz V D Ihzu V D Ihzux V X Ihzx y x Imw 4 V D Iswi 4 V x Iswx 4 V X Iwa V V DS lwarx V X Iwaux V V X Iwax V V X Iwbrx V x Iwz V D Iwzu V D Iwzux V X lwzx V X merf V XL merfs V X merxr V X mfcr V X mffsx V x mfmsr 2 V V X mfspr gt V V V XFX mfsr 2 V x mfsrin 2 V V X mftb V XFX mtcrf V XFX mtfsb0x V X mtfsb1x V x mtfstx V XFL mtfsfix V x Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Legend Table A 46 PowerPC Instruction Set Legend continued UISA VEA OEA Supervisor Level Optional 64 Bit Form mtmsr 2 V V xX mtspr gt d d V XFX mtsr V V D mtsrin 2 V V x mulhwx y XO 2 xX O mulhwux mulli V D mullwx V XO nandx V X negx V XO norx V X orx V X orcx V X ori V D oris V D rfi 2 V V XL Freescale Semiconductor nc rlwimix V M rlwinmx V M riwnmx V M sc V V SC MPC603e RISC Microproc
48. 0 0 ee eesceseeereeeeseceeeeeeeeeeneees 2 28 Floating Point Status and Control Register Instructions ee 2 28 Floating Point Move Instructions eeesesssecsseeeeeeeeseeeaecneeeseeeeneees 2 29 Load and Store Instructions eegenen deene Eeer 2 29 Self Modifying Goda nennen p s aaia 2 30 Integer Load and Store Address Generapon 2 30 Contents vi For More information On This Product Go to www freescale com Paragraph Number 2 3 4 3 3 2 3 4 3 4 2 3 4 3 5 2 3 4 3 6 2 3 4 3 7 2 3 4 3 8 2 3 4 3 9 2 3 4 3 10 2 3 4 4 2 3 4 4 1 2 3 4 4 2 2 3 4 4 3 2 3 4 5 2 3 4 6 2 3 4 6 1 2 3 4 7 2 3 5 2 3 5 1 2 3 5 2 2 3 5 3 2 3 5 4 2 3 6 2 3 6 1 2 3 6 2 2 3 6 2 1 2 3 6 2 2 2 3 6 3 2 3 6 3 1 2 3 6 3 2 2 3 6 3 3 2 3 7 2 3 8 3 1 3 1 1 3 1 2 3 1 3 3 1 3 1 3 1 3 2 Freescale Semiconductor Inc Contents Page Title Number Register Indirect Integer Load Instructions 0 0 cee eee eee eeseceseeeeeeeeeeees 2 30 Integer Store MStuUctons iesst eege 2 31 Integer Load and Store with Byte Reverse Instructons eee 2 32 Integer Load and Store Multiple Instructions 0 0 0 0 eee eeeeeeeeeeeeeneees 2 32 Integer Load and Store String Instructions eee eeeeeseceeeeeeeeeeneees 2 33 Floating Point Load and Store Address Generaton 2 34 Floating Point Load Instructions 0 cee eeseeseceseceeeeeeseeeaeceseeeseeeeneees 2 34 Floating Point Store Instructions ee eeeeseseceseceeeeeeseecseeeneeeseeeeaeees 2 3
49. 0b000 for burst transfers by the MPC603e U and L represent the upper and lower word of the double word respectively 8 3 2 4 Effect of Alignment in Data Transfers 64 Bit Bus Table 8 5 lists the aligned transfers that can occur on the MPC603e bus when configured with a 64 bit width These are transfers in which the data is aligned to an address that is an integer multiple of the size of the data For example Table 8 5 shows that 1 byte data is always aligned however for a 4 byte word to be aligned it must be oriented on an address that is a multiple of 4 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Address Bus Tenure Table 8 5 Aligned Data Transfers 64 Bit Bus Data Bus Byte Lanes Transfer Size TSIZO TSIZ1 TSIZ2 A 29 31 0 1 2 3 4 5 6 7 Byte 0 0 1 000 A 0 0 1 001 E A SE aa 0 0 1 010 A 0 0 1 011 e EES Se A il peste EA 0 0 1 100 A Z 0 0 1 101 DEED eee See ee te ih Soll 0 0 1 110 _ A T 0 0 1 111 Kiisa ee eg ee resch e A Halt word 0 1 0 000 A A 0 1 0 010 A A a 0 1 0 100 A A 0 1 0 110 A A Word 1 0 0 000 A A A A 1 0 0 100 A A A Double word 0 0 0 000 A A A A A A
50. 11 Integer Compare Instructions Name Mnemonic Operand Syntax Compare cmp crfD L rA rB Compare Immediate cmpi crfD L rA SIMM Compare Logical cmpl crfD L rA rB Compare Logical Immediate cmpli crfD L rA UIMM The crfD operand can be omitted if the result of the comparison is to be placed in CRO Otherwise the target CR field must be specified in the instruction erfD field For more information refer to Appendix F Simplified Mnemonics in the Programming Environments Manual 2 3 4 1 3 Integer Logical Instructions The logical instructions shown in Table 2 12 perform bit parallel operations Logical instructions with the CR update enabled and instructions andi and andis set CR field CRO to characterize the result of the logical operation These fields are set as if the sign extended low order 32 bits of the result were algebraically compared to zero Logical instructions without CR update and the remaining logical instructions do not modify the CR Logical instructions do not affect the XER SO XER OV and XER CA bits For simplified mnemonics examples for the integer logical operations see Appendix F Simplified Mnemonics in the Programming Environments Manual Table 2 12 Integer Logical Instructions Name Mnemonic Operand Syntax AND and and rA rS rB AND Immediate andi rA rS UIMM AND Immediate Shifted andis rA rS UIMM AND with Complement andc andc rA rS rB Count
51. 1149 1 compliant interface 8 42 IFEM instruction fetch enable bit 1 19 Illegal instruction class 2 18 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ILOCK control bit 3 5 Instruction address breakpoint exception 4 32 Instruction cache cache control bits 3 4 cache fill operations 3 4 configuration 3 2 organization 3 4 Instruction timing examples cache hit 6 11 6 14 execution unit 6 17 instruction flow 6 8 memory performance considerations 6 22 overview 1 32 6 3 terminology 6 1 Instruction TLB miss exception 4 30 Instruction unit 1 8 Instructions branch address calculation 2 36 branch instructions 2 36 A 22 cache management instructions 2 41 2 45 3 22 A 23 classes 2 17 condition register logical 2 37 A 22 defined instructions 2 17 external control 2 43 A 24 floating point arithmetic 2 26 A 17 compare 2 28 A 18 FP load instructions 2 34 A 21 FP move instructions 2 29 A 22 FP status and control register 2 28 FP store instructions 2 35 A 21 FPSCR isntructions 2 28 A 18 multiply add 2 27 A 18 rounding and conversion 2 28 A 18 illegal instructions 2 18 integer arithmetic 2 23 A 15 compare 2 24 A 16 load A 19 logical 2 24 A 16 multiple 2 32 A 20 rotate and shift 2 25 A 16 store 2 31 A 19 latency summary 6 26 load and store address generation floating point 2 34 address generation integer 2 30 byte reverse ins
52. 7 2 6 7 2 6 1 72 6 2 7 2 6 3 7 2 6 3 1 7 2 6 3 2 7 2 1 7 2 1 1 7 2 7 1 1 T2412 K N ch E Ee Ee 7 2 1 4 7 2 8 7 2 8 1 7 2 8 2 7 2 8 3 7 2 9 LD 7 2 9 2 7 2 9 3 7 2 9 4 12 93 7 2 9 6 7 2 9 6 1 7 2 9 6 2 7 2 9 7 7 2 9 7 1 71 2 9 1 2 1 2 9 1 3 71 2 9 1 4 Freescale Semiconductor Inc Contents Page Title Number Global GB e 7 14 Global E EE 7 14 Cache Set Entry CSE 0 1 Output Agen Eege Eed 7 14 Address Transfer Termination Sugenals 7 15 Address Acknowledge A ACKV Jnput eee ceeeeeseeeeseeceseceseensneeenees 7 15 Address Retry ARTRY sccssissiseccaesayeavcaneiessnecassncessasdevedeacpavacdesseccedassucaaters 7 15 Address Retry ARTRY Olutput E 7 15 Address Retry ARTRY Input 7 16 Data Bus Arbitration Signals 2 dutciccuienin Qied ue deser 7 16 Data Bus Grant D BG Input sss veensevediossaanncccauctovadeeasbnacsavensedganenventereyess 7 17 Data Bus Write Only DB WO Inptt 0000 0 ee eceeeeeeeceeeeeceteeeesteeeenaes 7 17 IB Eee ER a KEE 7 18 Data Bus Busy DBB Output seess 7 18 Data Bus Busy DBB Input ett 7 18 RN 7 18 Data Bus DH 0 31 DUI0 321h A N aR E 7 18 Data Bus DH 0 31 DL 0 31 Olutput 00 eee eeeseeeenteeeenteeees 7 19 Data Bus DH 0 31 DL 0 31 Input eee eeeceeeeneeeenteeeenteeees 7 19 Data Bus Parity EI LK ENEE 7 19 Data Bus Parity DP 0 7 Output 0 0 00 eeeceeeeceeceeeeeceteeeeeteeeeeteeeees 7 19 Data Bus Parity DP 0 7 Input
53. 8 4 2 Data Bus Write Only As a result of address pipelining the MPC603e may have up to two data tenures queued to perform when it receives a qualified DBG Generally the data tenures should be performed in strict order the same order as their address tenures were performed The MPC603e however also supports a limited out of order capability with the data bus write only DBWO input When recognized on the clock of a qualified DBG DBWO may direct the MPC603e to perform the next pending data write tenure even if a pending read tenure MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Bus Tenure would have normally been performed first For more information on the operation of DBWO refer to Section 8 10 Using DBWO If the MPC603e has any data tenures to perform it always accepts data bus mastership to perform a data tenure when it recognizes a qualified DBG If DBWO is asserted with a qualified DBG and no write tenure is queued to run the MPC603e still takes mastership of the data bus to perform the next pending read data tenure Generally DBWO should only be used to allow a copy back operation burst write to occur before a pending read operation If DBWO is used for single beat write operations it may negate the effect of the eieio instruction by allowing a write operation to precede a program scheduled read operat
54. 8 43 V Virtual environment architecture VEA xxvii 1 15 2 40 Ww WIMG bits 3 10 8 28 Write back 6 3 Write back mode 3 12 Write through mode W bit cache interactions 3 10 timing considerations 6 23 W bit setting 3 11 Write with atomic operation 3 20 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Write with flush operation 3 20 Write with kill operation 3 20 WT signal 7 14 X XATS signal MPC603 specific 1 6 Index For More information On This Product Go to www freescale com Freescale Semiconductor Inc MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Overview Programming Model Instruction and Data Cache Operation Exceptions Memory Management Instruction Timing Signal Descriptions System Interface Operation Power Management PowerPC Instruction Set Listings Instructions Not Implemented Revision History Glossary of Terms and Abbreviations Index For More Information On This Product Go to www freescale com Q O L IND aCe S t ye de amp C gt N on EN O fey e Q GG INID Freescale Semiconductor Inc Overview Programming Model Instruction and Data Cache Operation Exceptions Memory Management Instruction Timing Signal Descriptions System Inter
55. Access Protected Permitted see Figure 5 6 Access Faulted Translate Address Continue Access to Memory Subsystem Figure 5 5 General Flow of Address Translation Real Addressing Mode and Block 5 1 6 2 Page Address Translation Selection If address translation is enabled real addressing mode not selected and the effective address information does not match with a BAT array entry then the segment descriptor must be located Once the segment descriptor is located the T bit in the segment descriptor selects whether the translation is to a page or to a direct store interface segment as shown in Figure 5 6 Note that the MPC603e does not implement the direct store interface and accesses to these segments cause a DSI exception In addition Figure 5 6 also shows the way the no execute protection is enforced if the N bit in the segment descriptor is set and the access is an instruction fetch the access is faulted as described in Chapter 7 Memory Management in the Programming Environments Manual Note that the figure shows the flow for these cases as described by the PowerPC OEA and therefore the TLB references are shown as optional Since the MPC603e implements TLBs these branches are valid and described in more detail throughout this chapter MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Address Translation with Segment Desc
56. Acknowledge QACK Following are the state meaning and timing comments for the QACK input State Meaning Asserted Indicates that all bus activity that requires snooping has terminated or paused and that the MPC603e may enter the quiescent or low power state Negated Indicates that the MPC603e may not enter a quiescent state and must continue snooping the bus Timing Comments Assertion Negation May occur on any cycle following the assertion of QREQ and must be held asserted for a minimum of one bus clock cycle Start Up QACK is sampled at the negation of HRESET to select reduced pinout mode if QACK is asserted at start up reduced pinout mode is disabled MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc i Ka Signal Descriptions 7 2 9 7 3 Reservation RSRV Output Following are the state meaning and timing comments for the RSRV output State Meaning Timing Comments Asserted Negated Represents the state of the reservation coherency bit in the reservation address register that is used by the Iwarx and stwex instructions See Section 8 8 1 Support for the Iwarx stwex Instruction Pair Assertion Negation Occurs synchronously with respect to bus clock cycles The execution of an Iwarx instruction sets the internal reservation condition 7 2 9 7 4 Time Base Enable TBEN Input Following are the state
57. Address Bus Arbitration When the MPC603e needs access to the external bus and is not parked BG is negated it asserts bus request BR until it is granted mastership of the bus and the bus is available see Figure 8 3 The external arbiter must grant master elect status to the potential master by asserting the bus grant BG signal The MPC603e requesting the bus determines that the bus is available when the ABB input is negated the address bus is not busy BG is asserted and the address retry ARTRY input is negated This is referred to as a qualified bus grant The potential master assumes address bus mastership by asserting ABB when it receives a qualified bus grant External arbiters must allow only one device at a time to be the address bus master In implementations where no other device can be a master BG can be grounded always asserted to continually grant mastership of the address bus to the MPC603e If the MPC603e asserts BR before the external arbiter asserts BG the MPC603e is considered to be unparked as shown in Figure 8 3 Figure 8 4 shows the parked case where a qualified bus grant exists on the clock edge following a need_bus condition Notice that the bus clock cycle required for arbitration is eliminated if the MPC603e is parked reducing overall memory latency for a transaction The MPC603e always negates ABB for at least one bus clock cycle after AACK is asserted even if it is parked and has another transaction
58. Arbitration Showing Bus Parking eceeecceeeereeeeteeeeeee 8 5 Address Bus Transter 2 i2 20218 getcentetiietceni atta gieieanatied alata 8 6 Snooped Address Cycle with ARTRY AAA 8 7 EAU EE ee 8 8 Normal Single Beat Read Termination 0 eecceeeseeeeeececeeeeeeeteeeeeteeeees 8 9 Normal Single Beat Write Termination 0 cecceeecceeeeececeeeeeceeeeeeeteeeees 8 10 Normal Burst Transact ons c sec2cced scree etevece tateeceieecliaaitree einai teenies 8 11 Termination with DRIGR Y ssszsuiverstivcnscest ioanen nanasi 8 12 Read Burst with TA Wait States and DRTRY c ceccecccceeeseeeseseseseseees 8 13 MEI Cache Coherency Protocol State Diagram WIM 001 8 14 Fastest Single Beat Reads iii o Gre ai nate iene E aer etic 8 15 Fastest Single Beat Wteg 4e ONE saasacsidanddasasdeecdenassdacehontdenesaesouanes 8 16 Single Beat Reads Showing Data Delay Control 8 17 Single Beat Writes Showing Data Delay Controls 000 0 cee eeeeeeeeeeeeeees 8 18 Burst Transfers with Data Delay Controls 0 eee eeeceeeseeeseeeeeeeteeeeeneees 8 19 Use of Transfer Error Acknowledge TEA sesessessssssssssesssssserssersssseessees 8 20 32 Bit Data Bus Transfer Eight Beat Burst 0 eee eee ee eeeeeseeeneeeeeeeeee 8 21 32 Bit Data Bus Transfer Two Beat Burst with DRTRY 005 8 22 DB WO Transaction 9 eceiecs ei vegieties ahedactariedea neetedee epic s i MPC603e RISC Microprocessor User s Manual Fo
59. B 00000 24 Re frspx 63 D 00000 B 12 Re frsqrtex 63 D 00000 B 00000 26 Rc fselx 3 63 D A B C 23 Rc fsqrtx 63 D 00000 B 00000 22 Rc fsqrtsx 59 D 00000 B 00000 22 Rc fsubx 63 D A B 00000 20 Rc fsubsx 59 D A B 00000 20 Rc icbi 31 00000 A B 982 0 isync 19 00000 00000 00000 150 0 Ibz 34 D A d Ibzu 35 D A d Ibzux 31 D A B 119 0 Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instructions Sorted by Mnemonic Table A 1 Complete Instruction List Sorted by Mnemonic continued Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Ibzx 31 D A B 87 0 Id 58 D A ds 0 Idarx 1 31 D A B 84 0 Idu 58 D A ds 1 Idux 1 31 D A 53 0 Idx 1 31 D A 21 0 lfd 50 D A d Ifdu 51 D A d Ifdux 31 D A 631 0 lfdx 31 D A 599 0 Ifs 48 D A d Weu 49 D A d Ifsux 31 D A 567 0 lfsx 31 D A 535 0 Iha 42 D A d Ihau 43 D A d Ihaux 31 D A 375 0 Ihax 31 D A 343 0 Ihbrx 31 D A 790 0 Ihz 40 D A d Ihzu 41 D A d Ihzux 31 D A 311 0 Ihzx 31 D A 279 0 Imw 4 46 D A d Iswi 4 31 D A NB 597 0 Iswx 4 31 D A B 533 0 Iwa 1 58 D A ds 2 Iwarx 31 D A B 20 0 Iwaux 1 31 D A B 373 0 Iwax 1 31 D A B 341 0 Ilwbrx 31 D A B 534 0 lwz 32 D A d lwzu 33 D A d lwzux 31 D A B 55 0 lwzx 31 D A B 23 0 mer
60. CH Chapter 6 Instruction Timing For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Execution Unit Timings Lo add cb Fetch in IQ Tadd In Dispatch Entry 1Q0 IQ1 L 2 be a Execute Sm Fc wm In CO 4 bc l Ee i In Retirement Entry CQ0 CQ1 5 fadd TO add T1 add T2 add T3 add T4 add T5 or sro eg Cand LR Instruction Queue T5 T3 T4 3 5 T1 T2 T3 1 2 4 To T1 T2 6 0 1 3 5 To T1 5 Completion Queue 2 3 1 2 TO 6 0 0 1 3 3 5 Figure 6 7 Branch Instruction Timing 0 During clock cycle 0 instructions 0 and 1 are dispatched in the beginning of clock cycle 1 1 Inclock cycle 1 instructions 2 and 3 are fetched in the IQ Instruction 2 is a branch instruction that updates the CTR and instruction 3 is a mulhw instruction on which instruction 4 depends Instruction 0 enters the IU Instruction has a single cycle stall MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc siete Execution Unit Timings 2
61. CR7 that reflect the results of certain arithmetic operations and provides a mechanism for testing and branching Floating point status and control register FPSCR The FPSCR contains all floating point exception signal bits exception summary bits exception enable bits and rounding control bits needed for compliance with the IEEE 754 standard MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Register Set SUPERVISOR MODEL Configuration Registers USER MODEL Hardware Implementation Machine State Processor Version 1 D General Purpose Registers Register Register Registers HIDO SPR 1008 MSR SPR 287 HID1 SPR 1009 Memory Management Registers Instruction BAT Software Table Registers Data BAT Registers Search Registers 1 IBATOU SPR 528 DBATOU SPR 536 SPR 976 IBATOL SPR 529 DBATOL SPR 537 SPR 977 IBAT1U SPR 530 DBAT1U SPR 538 SPR 978 IBAT1L SPR 531 DBATIL SPR 539 SPR 979 IBAT2U SPR 532 DBAT2U SPR 540 SPR 980 IBAT2L SPR 533 DBAT2L SPR 541 SPR 981 IBAT3U SPR 534 DBAT3U SPR 542 SPR 982 IBAT3L SPR 535 DBAT3L_ SPR 543 Floating Point Registers SDR1 SDR1 SPR 25 Condition Register CR Floating Point Status Exception Handling Registers and Control Register Data Address Register DSISR FESOR DAR sPR19 SPR 18 XER SPRGs Save and Restore Registers SPR 272 SRRO SPR 26 SPR 273 SRR1 SP
62. Cache Block Touch dcbt Instruction This instruction provides a method for improving performance through the use of software initiated prefetch hints The MPC603e performs the fetch when the address hits in the TLB or BAT registers and when it is a permitted load access from the addressed page The operation is treated similarly to a byte load operation with respect to coherency If the address translation does not hit in the TLB or BAT mechanism or if it does not have load access permission the instruction is treated as a no op If the cache is locked or disabled or if the access is to a page that is marked as guarded the dcbt instruction is treated as a no op If the access is directed to a write through or caching inhibited page the instruction is treated as a no op The debt instruction never affects the referenced or changed bits in the hashed page table A successful debt instruction affects the state of the TLB and cache LRU bits as defined by the LRU algorithm The touch load buffer will be marked invalid if the contents of the touch buffer have been moved to the cache if any data cache management instruction has been executed if a dcbz instruction is executed that matches the address of the cache block in the touch buffer or if another debt instruction is executed 3 7 3 Data Cache Block Touch for Store dcbtst Instruction The debtst instruction like the data cache block touch instruction debt allows software to p
63. Count Leading Zeros Double Word divd Divide Double Word divdu Divide Double Word Unsigned extsw Extend Sign Word fcfid Floating Convert From Integer Double Word fctid Floating Convert to Integer Double Word fctidz Floating Convert to Integer Double Word with Round toward Zero Id Load Double Word Idarx Load Double Word and Reserve Indexed Idu Load Double Word with Update Idux Load Double Word with Update Indexed Appendix B Instructions Not Implemented For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table B 2 64 Bit Instructions Not Implemented by the MPC603e continued Mnemonic Instruction Idx Load Double Word Indexed lwa Load Word Algebraic lwaux Load Word Algebraic with Update Indexed lwax Load Word Algebraic Indexed mulld Multiply Low Double Word mulhd Multiply High Double Word mulhdu Multiply High Double Word Unsigned del Rotate Left Double Word then Clear Left der Rotate Left Double Word then Clear Right ridic Rotate Left Double Word Immediate then Clear ridicl Rotate Left Double Word Immediate then Clear Left ridicr Rotate Left Double Word Immediate then Clear Right rildimi Rotate Left Double Word Immediate then Mask Insert slbia SLB Invalidate All slbie SLB Invalidate Entry sid Shift Left Double Word srad Shift Right Algebraic Double Word sradi Shift Right Algebraic Double Word Immediate srd
64. Count register DABR Data address breakpoint register DAR Data address register DBAT Data BAT DCMP Data TLB compare DEC Decrementer register DLL Delay locked loop DMISS Data TLB miss address DMMU Data MMU DSISR Register used for determining the source of a DSI exception DTLB Data translation lookaside buffer MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc SC cronyms and Abbreviations Table i Acronyms and Abbreviated Terms continued Term Meaning EA Effective address EAR External access register ECC Error checking and correction FIFO First in first out FPR Floating point register FPSCR Floating point status and control register FPU Floating point unit GPR General purpose register HASH1 Primary hash address HASH2 Secondary hash address IABR Instruction address breakpoint register IBAT Instruction BAT ICMP Instruction TLB compare IEEE Institute for Electrical and Electronics Engineers IMISS Instruction TLB miss address IQ Instruction queue ITLB Instruction translation lookaside buffer IU Integer unit JTAG Joint Test Action Group L2 Secondary cache level 2 cache LIFO Last in first out LR Link register LRU Least recently used LSB Least significant byte Isb Least significant bit LSU Load store unit MEI Modified exclusive i
65. D tibl 2 6 V x tlbli 2 6 V x tlbsyne 2 3 y y X tw V X twi V D xorx V X xori V D xoris V D 64 bit instruction Supervisor level instruction Optional in the PowerPC architecture Load and store string or multiple instruction Supervisor and user level instruction MPC603 implementation specific instruction oa A OON MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix B Instructions Not Implemented This appendix provides a list of the 32 and 64 bit instructions that are not implemented in the MPC603e microprocessor It also provides a list of the 64 bit SPR encodings not implemented by the MPC603e Note that any attempt to execute unimplemented instructions generates an illegal instruction exception Table B 1 lists the 32 bit instructions that are optional to the PowerPC architecture and not implemented by the MPC603e Table B 1 32 Bit Instructions Not Implemented by the MPC603e Mnemonic Instruction fsqrt Floating Square Root Double Precision fsqrts Floating Square Root Single tlbia TLB Invalidate All Table B 2 provides a list of 64 bit instructions that are not implemented by 32 bit implementation such as the MPC603e microprocessor Table B 2 64 Bit Instructions Not Implemented by the MPC603e Mnemonic Instruction entlizd
66. Data Termination Interrupts Checkstops Reset Processor Status JTAG COP Interface LSSD Test Control Freescale Semiconductor Inc Implementation Specific Information MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 2 Programming Model This chapter describes the PowerPC programming model with respect to the MPC603e microprocessor It consists of three major sections that describe the following e Registers implemented in the MPC603e e Operand conventions e MPC603e instruction set 2 1 Register Set This section describes the register organization in the MPC603e as defined by the three levels of the PowerPC architecture user instruction set architecture UISA virtual environment architecture VEA and operating environment architecture OEA as well as the MPC603e implementation specific registers Full descriptions of the basic register set defined by the PowerPC architecture are provided in Chapter 2 Register Set in the Programming Environments Manual The PowerPC architecture defines register to register operations for all computational instructions Source data for these instructions is accessed from the on chip registers or is provided as an immediate value embedded in the opcode The three register instruction format allows specification of a target register distinct from the two source registers t
67. I and M Bits continued WIM Setting Meaning 011 Caching is inhibited The access is performed to external memory completely bypassing the cache Memory coherency must be enforced by external hardware processor provides hardware indication that access is global 100 Data may be cached Load operations whose target hits in the cache use that entry in the cache Stores are written to external memory The target location of the store may be cached and is updated on a hit Memory coherency is not enforced by hardware 101 Data may be cached Load operations whose target hits in the cache use that entry in the cache Stores are written to external memory The target location of the store may be cached and is updated on a hit Memory coherency is enforced by hardware 3 5 5 1 Out of Order Execution and Guarded Memory Out of order execution occurs when the MPC603e performs operations in advance in case the result is needed Typically these operations are performed by otherwise idle resources thus if a result is not required it is ignored and the out of order operation incurs no time penalty typically Supervisor level programs designate memory as guarded on a block or page level Memory is designated as guarded if it may not be well behaved with respect to out of order operations For example the memory area that contains a memory mapped I O device may be designated as guarded if an out of order load
68. Inclock cycle 2 instructions 4 a second be instruction and 5 are fetched The second be instruction is predicted as taken It can be folded but it cannot be resolved until instruction 3 writes back Instruction 0 completes at the end of this cycle Instruction 1 is dispatched to the IU Instruction 2 takes entry in the CQ 3 Inclock cycle 3 target instructions TO and T1 are fetched Instructions 1 and 2 complete instruction 4 has been folded and instruction 5 has been flushed from the IQ Instruction 3 is assigned to CQ2 4 Inclock cycle 4 target instructions T2 and T3 are fetched IU instructions TO and T1 have multiple stalls as one execution possible in a clock cycle Instruction 3 is assigned to CQO 5 In clock cycle 5 instruction 3 on which the second branch instruction depended writes back and the branch prediction is proven incorrect Even though TO is in CQO where it could be written back it is not because the prediction was incorrect All target instructions are flushed from their positions in the pipeline at the end of this clock cycle as there are many results in the rename registers After one clock cycle required to refetch the original instruction stream instruction 5 the same instruction that was fetched in clock cycle 2 is brought back into the IQ from the instruction cache along with one other 6 4 2 Integer Unit Execution Timing The integer unit executes all integer and bit field computational instructions
69. Information On This Product Go to www freescale com Freescale Semiconductor Inc Timing Considerations 6 3 3 Instruction Dispatch and Completion Considerations Several factors affect the ability of the MPC603e to dispatch instructions at a peak rate of two per cycle the availability of the execution unit destination rename registers and completion queue as well as the handling of completion serialized instructions Several of these limiting factors are illustrated in the previous instruction timing examples To reduce dispatch unit stalls due to instruction data dependencies the MPC603e provides a single entry reservation station for the FPU SRU and each IU and a two entry reservation station for the LSU If a data dependency keeps an instruction from starting execution that instruction is dispatched to the reservation station associated with its execution unit and the rename registers are assigned thereby freeing the positions in the instruction queue so instructions can be dispatched to other execution units Execution begins during the same clock cycle that the rename buffer is updated with the data the instruction is dependent on If both instructions in IQO and IQ1 require the same execution unit the instruction in IO cannot be dispatched until the first instruction proceeds through the pipeline and provides the subsequent instruction with a vacancy in the requested execution unit The completion unit maintains program
70. Leading Zeros Word cntlzw cntizw rA rS Equivalent eqv eqv rA rS rB MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Table 2 12 Integer Logical Instructions continued Inc Gastruction Set Summary Name Mnemonic Operand Syntax Extend Sign Byte extsb extsb rA rs Extend Sign Half Word extsh extsh rA rS NAND nand nand rA rS rB NOR nor nor rA rS rB OR or or rA rS rB OR Immediate ori rA rS UIMM OR Immediate Shifted oris rA rS UIMM OR with Complement orc orc rA rS rB XOR xor xor rA rS rB XOR Immediate xori rA rS UIMM XOR Immediate Shifted xoris rA rS UIMM 2 3 4 1 4 Rotation operations are performed on data from a GPR and the result or a portion of the result is returned to a GPR See Appendix F Simplified Mnemonics in the Programming Environmments Manual for a complete list of simplified mnemonics that allows simpler coding of often used functions such as clearing the leftmost or rightmost bits of a register left justifying or right justifying an arbitrary field and simple rotates and shifts Integer Rotate and Shift Instructions Integer rotate instructions rotate the contents of a register The result of the rotation is either inserted into the target register under control of a mask if a mask bit is 1 the associated bit of the rotated data
71. Manual See the Programming Environments Manual Access permitted Access prohibited Page memory protection violation PA O 31J RPNIIA 20 31 Continue access to memory subsystem with WIMG bits from PTE Store access with PTE C 0 otherwise Page table search operation See Figure 5 9 Figure 5 8 Page Address Translation Flow TLB Hit Appendix C Revision History For More Information On This Product Go to www freescale com e Semiconductor Inc F Revision Changes From narsescale Se 5 5 2 2 2 5 46 doISI mfspr andi addis isil mtctr mtspr mfmsr xoris mtcrf mtmsr b 5 5 2 2 2 5 47 banz 5 5 2 2 2 5 49 andis 5 5 2 2 2 5 49 sth 5 5 2 2 2 5 50 beq 8 2 1 8 8 8 3 2 2 1 8 13 8 3 2 4 8 17 8 3 3 8 20 Replace the doISI segment with the following ro SEET get srrl r2 r Oxffff clean srrl r2 r2 0x4000 or in srrl lt 1l gt 1 to flag pte not found ro restore counter SEI ES set srrl ro get msr r0 r0 0x8000 flip the msr lt tgpr gt bit QOx80 r3 restore CRO ro flip back to the native gprs vec400 go to instr access exception Replace the third line of the dm1 segment with the following D dml dec count br if cmp ne and if count not zero Replace the comment of the second line of the chkO segment with the following r3 xr3 0x0008 test the KEY bit SRR1I bit 12 Replace the second line in the chk2 segment with the following rl
72. May be negated two bus cycles after assertion 7 2 9 4 Checkstop Input CKSTP_IN Input Following are the state meaning and timing comments for the CKSTP_IN input State Meaning Asserted Indicates that the MPC603e must terminate operation by internally gating off all clocks and release all outputs except CKSTP_OUT to the high impedance state Once CKSTP_IN is asserted it must remain asserted until the system has been reset Negated Indicates that normal operation should proceed See Section 8 7 2 Checkstops Timing Comments Assertion May occur at any time and may be asserted asynchronously to the input clocks Negation May occur anytime after CKSTP_OUT is asserted 7 2 9 5 Checkstop Output CKSTP_OUT Output The CKSTP_OUT signal is output only on the MPC603e Note that CKSTP_OUT is an open drain type output and requires an external pull up resistor for example 10 kQ to Vpp to assure proper negation of CKSTP_OUT Following are the state meaning and timing comments for the CKSTP_OUT output MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc i Ka Signal Descriptions State Meaning Asserted Indicates that the MPC603e has detected a checkstop condition and has ceased operation Negated Indicates that the MPC603e is operating normally See Section 8 7 2 Checkstops Timing Comments Assertion May occur
73. Memory Coherency Actions on Load Operations Cache State Bus Operation ARTRY Action M None Don t care Read from cache E None Don t care Read from cache l Read Negated Load data and mark E l Read Asserted Retry read operation Table 3 5 provides an overview of memory coherency actions on store operations This table does not include noncacheable or write through cases The read with intent to modify RWITM examples involve selecting a replacement class and casting out modified data that may have resided in that replacement class Chapter 3 Instruction and Data Cache Operation For More information On This Product Go to www freescale com Cache Coherency MEI ph regseale Semiconductor Inc Table 3 5 Memory Coherency Actions on Store Operations Cache State Bus Operation ARTRY Action M None Don t care Modify cache E None Don t care Modify cache mark M l RWITM Negated Load data modify it mark M l RWITM Asserted Retry the RWITM 3 6 6 Atomic Memory References The Load Word and Reserve Indexed wars and Store Word Conditional Indexed stwex instructions provide an atomic update function for a single aligned word of memory While an lwarx instruction will normally be paired with an stwex instruction with the same effective address an stwex instruction to any address will cancel the reservation For detailed information on these instructions re
74. N A Kill block Address only 0 1 1 0 O Kill cancel reservation eieio Address only 1 0 0 0 0 N A MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Ka Signal Descriptions Table 7 2 Snoop Hit Response continued 60x Bus Specification UE Command Transaction TTO TT1 TT2 TTS TT4 Snooper Action on Hit External control word write Single beat write 1 0 1 0 o N A TLB Invalidate Address only 1 1 0 0 0 N A External control word read Single beat read 1 1 1 0 0 N A lwarx reservation set Address only 0 0 0 0 1 N A Reserved 0 0 1 0 1 N A tlosync Address only 0 1 0 0 1 N A icbi Address only 0 1 1 0 1 N A Reserved 1 X X 0 1 N A Write with flush Single beat write or burst 0 1 O0 Flush cancel reservation Write with kill Single beat write or burst 0 0 1 1 O Kill cancel reservation Read Single beat read or burst 0 1 0 1 0 Clean or flush Read with intent to modify Burst 0 1 1 1 0 Flush Write with flush atomic Single beat write 1 0 0 1 O0 Flush cancel reservation Reserved N A 1 0 1 1 0 N A Read atomic Single beat read or burst 1 1 0 1 0 Clean or flush Read with intent to modify Burst 1 1 1 1 0 Flush atomic Reserved 0 0 0 1 1 N A Reserved 0 0 1 1 1 N A Read with no intent to cache Single beat read or burst 0 1 0 1 1 Clean Reserv
75. Note that the following sections are intended to provide a quick summary of signal functions Chapter 8 System Interface Operation describes many of these signals in greater detail both with respect to how individual signals function and how groups of signals interact 7 2 1 Address Bus Arbitration Signals The address arbitration signals are a collection of input and output signals the MPC603e uses to request the address bus recognize when the request is granted and indicate to other devices when mastership is granted For a detailed description of how these signals interact see Section 8 3 1 Address Bus Arbitration MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc es Signal Descriptions BR DBG Address BG DBWO Data l Arbitration ABB DBB Arbitration Address TS Start DH 0 31 DL 0 31 DP 0 7 Data A 0 31 DPE Transfer DBDIS Address Bus AP 0 3 APE TA i DRTRY Data MPC603e TEA Termination TT 0 4 5 r bes TBST 1 INT SMI lt _____ _ TSIZ 0 2 3 MCP Interrupts GBL CKSTP_IN CKSTP_OUT Checkstops tansy col l HRESET SRESET Reset Attribute 1 an 1 RSRV TC 0 1 QREQ QACK 2 TBEN Processor Status TLBISYNC AACK Address T ARTAY Termination Kess TRST TCK TMS TDI TDO JTAG COP Interface SYSCLK Clocks CLK_OUT TEST LSSD Test PLL_CFG 0 3 Control 43 3V 7 Figure 7 1 Signal Grou
76. PTE R in Memory in Memory L Page Table Search Complete PTE R lt 1 Update PTE R in Memory QO Page Table Search Complete r q H Optional O Memory Protection Violation Figure 5 9 Primary Page Table Search Conceptual Flow MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor In Cc d age Table Search Operation Secondary Page Table Search Generate PA using Secondary Hash Function PA lt Base PA of PTEG Fetch PTE from PTEG PA lt PA 8 Fetch PTE 64 Bits Fetch Next PTE in PTEG from PA Otherwise PTE VSID API H V Segment Descriptor VSID EA API 1 1 Otherwise Secondary Page Table Search Hit Last PTE in PTEG See Figure 5 9 DG Fault Instruction Access Data Access Set SRR1 1 1 ISI Exception Figure 5 10 Secondary Page Table Search Flow Conceptual Flow Set DSISR 1 1 DSI Exception 5 5 2 Implementation Specific Table Search Operation The MPC603e has a set of implementation specific registers exceptions and instructions that facilitate very efficient software searching of the page tables in memory This section describes those resources and provides three example code sequences that can be used in a MPC603e system for an efficient search of the translation tables in software These three code sequences can be used as handlers for the three exceptions requiring
77. Programming Environments Manual for 32 bit implementations Implementation Note The MPC603e BAT registers are not initialized by the hardware after the power up or reset sequence Consequently all valid bits in both instruction and data BAT areas must be explicitly cleared before setting any BAT area for the first time and before enabling translation Also note that software must avoid overlapping blocks while updating a BAT area or areas Even if translation is disabled multiple BAT area hits with the valid bits set can corrupt the remaining portion any bits except the valid bits of the BAT registers Thus multiple BAT hits with valid bits set are considered a programming error whether translation is enabled or disabled and can lead to unpredictable results if translation is enabled or if translation is disabled when translation is eventually enabled For the case of unused BATs if translation is to be enabled it is sufficient precaution to simply clear the valid bits of the unused BAT entries 5 4 Memory Segment Model The MPC603e adheres to the memory segment model as defined in Chapter 7 Memory Management in the Programming Environments Manual for 32 bit implementations Memory in the PowerPC OEA is divided into 256 Mbyte segments This segmented memory model provides a way to map 4 Kbyte pages of effective addresses to 4 Kbyte pages in physical memory page address translation while providing the programming flexi
78. RISC Microprocessor Hardware Specifications for exact timing information Table 8 1 Timing Diagram Legend Feature Example Description Gray APO MPC603e input while the MPC603e is the bus master Bold BR MPC603e output while the MPC603 e is the bus master Plain Data MPC603e input or output while the MPC603e is the bus master ADDR MPC603e output grouped here address plus attributes lowercase qual_bg Internal MPC603e signal inaccessible to the user but used in diagrams to clarify operations Curled arrow Dependency Zig zag Indication that some clocks may have been skipped Unshaded A valid output or input signal or bus that can be in any of the possible states indicated Shaded MPC603e nonsampled input or indeterminately driven output among the possible states indicated Dot Signal with sample point Dot on dotted vertical line A sampled condition dot on high or low state with multiple dependencies Dotted signal ENT H K Zelt e Timing for a signal had it been asserted 8 1 2 1 Optional 32 Bit Data Bus Mode The MPC603e supports an optional 32 bit data bus mode which differs from the 64 bit data bus mode only in the byte lanes involved in the transfer and the number of data beats performed A data tenure in the 32 bit data bus mode takes one two or eight beats Chapter 8 System Interface Operation For More Information On This Product Go to w
79. Register 0 SSRO The save restore register 1 SRR1 is used to save machine status the contents of the MSR on exceptions and to restore those values when rfi is executed SRR1 is shown in Figure 4 2 Exception Specific Information and MSR Bit Values Figure 4 2 Machine Status Save Restore Register 1 SSR1 Chapter 4 Exceptions For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Exception Processing Typically when an exception occurs bits 0 15 of SRR1 are loaded with exception specific information and bits 16 31 of MSR are placed into the corresponding bit positions of SRR1 The MPC603e loads SRR1 with specific bits for handling machine check exceptions as shown in Table 4 4 Table 4 4 SRR1 Bit Settings for Machine Check Exceptions Bits Name Description 0 MSR 0 Copy of MSR bit 0 1 4 Reserved 5 9 MSR 5 9 Copy of MSR bits 5 9 10 11 j Reserved 12 MCP Machine check 13 TEA TEA error 14 DPE Data parity error 15 APE Address parity error 16 31 MSR 16 31 Copy of MSR bits16 31 The MPC603e loads SRR1 with specific bits for handling the three TLB miss exceptions as shown in Table 4 5 Table 4 5 SRR1 Bit Settings for Software Table Search Operations Bits Name Description 0 3 CRFO Copy of condition register field 0 CRO 4 Reserved 5 9 MSR 5 9 Copy of MSR bits 5 9 1
80. See Section 7 2 12 2 Test Clock CLK_OUT Output for more information Table 2 3 HIDO BCLK and HIDO ECLK CLK_OUT Configuration HRESET HIDO ECLK HIDO BCLK CLK_OUT Asserted D D Bus Negated 0 0 High impedance Negated 0 1 Core clock frequency Negated 1 0 Bus Negated 1 1 Core clock frequency Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Register Set HIDO can be accessed with mtspr and mfspr using SPR1008 Reserved PCO PC1 PC2 PC3 0000000000000000000000000000 012 3 4 31 Figure 2 3 Hardware Implementation Register 1 HID1 Table 2 4 shows the bit definitions for HID1 Table 2 4 HID1 Bit Settings Bits Name Description 0 PCO PLL configuration bit 0 read only 1 PC1 PLL configuration bit 1 read only 2 PC2 PLL configuration bit 2 read only 3 PC3 PLL configuration bit 3 read only 4 31 Reserved should be cleared Note The clock configuration bits reflect the state of the PLL_CFG 0 3 signals HID1 can be accessed with mfspr using SPR1009 2 1 2 2 Data and Instruction TLB Miss Address Registers DMISS and IMISS DMISS and IMISS shown in Figure 2 4 are loaded automatically upon a data or instruction TLB miss DMISS and IMISS contain the effective page address of the access that caused the TLB miss exception The
81. Sequence for Entering Processor Sleep Mode A 9 6 Appendix A PowerPC Instruction Set Listings Instructions Sorted by Mnemonic degen aaeteaete caer ads Eege egen A 1 Instructions Sorted by lee tee adele laden dels A 8 Instructions Grouped by Functional Categories 2 0 0 0 eee eeeeeseeeeneeeseeeeeeeeeees A 15 Instructions Sorted Dy Form eat dreigfugetredd added deed sucsddevads duces dE A 25 Instruction SEW EEN A 36 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Contents Paragraph Number Title Appendix B Instructions Not Implemented Appendix C Revision History C 1 Revision Changes From Revision 2 to Revision 3 C2 Revision Changes From Revision 1 to Revision Un Glossary of Terms and Abbreviations Index Contents For More Information On This Product Go to www freescale com Page Number XV Freescale Semiconductor Inc Contents MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Figures Figure Number Title 1 1 MPC603e Microprocessor Block Dagram 1 2 Programming Mode Repgisters ssnsssessesseessereessetssresseesseessseesssressresseessee 1 3 Data Cache Organizon E 1 4 ee 1 5 Signal COU EE 2 1 Programming Model Re ister 00 ecscceesssecesceceeeeeceeeeeceeceecsneeeeneeeenaeeeenas 2 2 Hardware Implementa
82. State Meaning Asserted Initiates processing for a reset exception as described in Section 4 5 1 2 Soft Reset Chapter 7 Signal Descriptions For More Information On This Product Go to www freescale com ae Freescale Semiconductor Inc Signal Descriptions Negated Indicates that normal operation should proceed See Section 8 7 3 Reset Inputs Timing Comments Assertion May occur at any time and may be asserted asynchronously to the MPC603e input clock SRESET is negative edge sensitive Negation May be negated two bus cycles after assertion This input has additional functionality in certain test modes 7 2 9 7 Processor Status Signals Processor status signals indicate the state of the processor This includes the memory reservation machine quiesce control time base enable and TLBISYNC signals 7 2 9 7 1 Quiescent Request QREQ Following are the state meaning and timing comments for the QREQ signal State Meaning Asserted Indicates that the MPC603e is requesting all bus activity normally required to be snooped to terminate or to pause so the MPC603e may enter a quiescent low power state Once the MPC603e enters a quiescent state it no longer snoops bus activity Negated Indicates that the MPC603e is not making a request to enter the quiescent state Timing Comments Assertion Negation May occur on any cycle QREQ remains asserted for the duration of the quiescent state 7 2 9 7 2 Quiescent
83. Store Multiple Instructions The integer load store multiple instructions are used to move blocks of data to and from the GPRs In some implementations these instructions are likely to have greater latency and take longer to execute perhaps much longer than a sequence of individual load or store instructions that produce the same results MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING _ suction P Implementation Notes The following describes the MPC603e implementation of the load store multiple instruction The load multiple and store multiple instructions may have operands that require memory accesses crossing a 4 Kbyte page boundary As a result these instructions may be interrupted by a DSI exception associated with the address translation of the second page In this case the MPC603e performs some or all of the memory references from the first page and none of the memory references from the second page before taking the exception On return from the DSI exception the load or store multiple instruction will re execute from the beginning For additional information refer to DSI Exception 0x00300 in Chapter 6 Exceptions in the Programming Environments Manual The PowerPC architecture defines the load multiple word Imw instruction with rA in the range of registers to be loaded as an invalid form It defines the load multiple a
84. Table 5 4 Other MMU Exception Conditions Condition Description Exception TLB miss for an instruction fetch No matching entry found in ITLB Instruction TLB miss exception SRR1 13 1 MSR 14 1 TLB miss for a data load access No matching entry found in DTLB for data load access Data TLB miss on load exception SRR1 13 0 SRR1 15 1 MSR 14 1 TLB miss for a data store or store andC 0 No matching entry found in DTLB for data store access or matching DLTB Data TLB miss on store exception or store and C 0 entry has C 0 and the access is a SRR1 13 0 store SRR1 15 0 MSR 14 1 TLB miss for an instruction fetch No matching entry found in ITLB Instruction TLB miss exception SRR1 13 1 MSR 14 1 debz with W 1 orl 1 debz instruction to write through or cache inhibited segment or block Alignment exception not required by architecture for this condition dcbz when the data cache is locked The debz instruction takes an alignment exception if the data cache is locked HIDO bits 18 and 19 when it is executed Alignment exception lwarx stwex eciwx or ecowx instruction to direct store segment Reservation instruction or external control instruction when SR T 1 DSI exception DSISR 5 1 Floating point load or store to direct store segment FP memory access when SR T 1 See data access to direct store segment in Table 5 3 Load or
85. The execute stage consists of the time between dispatch to the execution unit or reservation station and the point at which the instruction vacates the execution unit Most integer instructions have a one cycle latency results of these instructions can be used in the clock cycle after an instruction enters the execution unit However Chapter 6 Instruction Timing For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Timing Overview integer multiply and divide instructions take multiple clock cycles to complete The IU can process all integer instructions The LSU and FPU are pipelined as shown in Figure 6 2 The complete complete write back pipeline stage maintains the correct architectural machine state and commits it to the architectural registers at the proper time If the completion logic detects an instruction containing an exception status all following instructions are canceled their execution results in rename registers are discarded and the correct instruction stream is fetched The complete stage ends when the instruction is retired Two instructions can be retired per cycle Instructions are retired only from the two lowest CQ entries CQO and CQ1 The notation conventions used in the instruction timing examples are as follows Fetch The fetch stage includes the time between when an instruction is requested and when it is brought into the instruction q
86. These signals consisting of data bus data parity and data parity error signals are used to transfer the data and to ensure the integrity of the transfer Data transfer termination signals Data termination signals are required after each data beat in a data transfer In a single beat transaction the data termination signals also indicate the end of the tenure In burst accesses the data termination signals apply to individual beats and indicate the end of the tenure only after the final data beat They also indicate whether a condition exists that requires the data phase to be repeated System status signals These signals include the interrupt signal checkstop signals and soft and hard reset signals They are used to interrupt and under various conditions to reset the processor Processor state signals These signals indicate the state of the reservation coherency bit enable the time base provide machine quiescence control and can be used to cause a machine halt on execution of a tlbsync instruction JTAG COP interface signals The JTAG IEEE 1149 1 interface and common on chip processor COP unit provides a serial interface to the system for performing monitoring and boundary tests Test interface signals These signals are used for production testing Chapter 1 Overview For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Implementation Specific Information e Clock signa
87. a modified cache block that is already in the process of being written to the copy back buffer for replacement purposes If this happens the MPC603e retries the snoop and raises the priority of the cast out operation to allow it to go to the bus before the cache block fill The global GBL signal asserted as part of the address attribute field during a bus transaction enables the snooping hardware of the MPC603e Address bus masters assert GBL to indicate that the current transaction is a global access that is an access to memory shared by more than one device If GBL is not asserted for the transaction that transaction is not snooped by the MPC603e Note that the GBL signal is not asserted for instruction fetches and that GBL is asserted for all data read or write operations when using direct address translation Note that direct address translation is referred to as the real addressing mode not the direct store segment in the architecture specification Normally GBL reflects the M bit value specified for the memory reference in the corresponding translation descriptor s Care must be taken to minimize the number of pages marked as global because the retry protocol enforces coherency and can use considerable bus bandwidth if a lot of data is shared Therefore available bus bandwidth can decrease as more traffic is marked global The MPC603e snoops a transaction if the transfer start TS and GBL signals are asserted toge
88. a write transaction or which portion of the bus should contain valid data for a read transaction Note that for a burst transaction as indicated by the assertion of TBST TSIZ 0 2 are always set to 0b010 Therefore if TBST is asserted the memory system should transfer a total of 8 words 32 bytes regardless of the TSIZ 0 2 encoding Table 8 2 Transfer Size Signal Encodings TBST TSIZO TSIZ1 TSIZ2 Transfer Size Asserted 0 1 0 8 word burst Negated 0 0 0 8 bytes Negated 0 0 1 1 byte Negated 0 1 0 2 bytes Negated 0 1 1 3 bytes Negated 1 0 0 4 bytes Negated 1 0 1 5 bytes N A Negated 1 1 0 6 bytes N A Negated 1 1 1 7 bytes N A The basic coherency size of the bus is defined to be 32 bytes corresponding to one cache line Data transfers that cross an aligned 32 byte boundary either must present a new address onto the bus at that boundary for coherency consideration or must operate as noncoherent data with respect to the MPC603e The MPC603e never generates a bus transaction with a transfer size of 5 6 or 7 bytes 8 3 2 3 Burst Ordering During Data Transfers During burst data transfer operations 32 bytes of data one cache line are transferred to or from the cache in order Burst write transfers are always performed zero double word first but because burst reads are performed critical double word first a burst read transfer may not start with the first double
89. access to the PTEs in the page tables in memory instruction TLB miss data TLB miss on load and data TLB miss on store exceptions 5 5 2 1 Resources for Table Search Operations In addition to setting up the translation page tables in memory the system software must assist the processor in loading PTEs into the on chip TLBs When a required TLB entry is not found in the appropriate TLB the processor vectors to one of the three TLB miss exception handlers so that the software can perform a table search operation and load the Chapter 5 Memory Management For More Information On This Product Go to www freescale com Page Table Search Operathreeseale Semiconductor Inc TLB When this occurs the processor automatically saves information about the access and the executing context Table 5 9 provides a summary of the implementation specific exceptions registers and instructions that can be used by the TLB miss exception handler software in MPC603e systems Refer to Chapter 4 Exceptions for more information about exception processing Table 5 9 Implementation Specific Resources for Table Search Operations Resource Name Description Exceptions Instruction TLB miss No matching entry found in ITLB exception vector offset 0x1000 Data TLB miss on load No matching entry found in DTLB for a load data access exception vector offset 0x1100 Data TLB miss on store No matching entry found in DTLB for a store data acce
90. activity and other conditions that affect memory accesses The MPC603e implements many features to improve throughput such as pipelining superscalar instruction dispatch branch folding removal of fall through branches two level speculative branch handling and multiple execution units that operate independently and in parallel As an instruction of load store and floating point units passes from stage to stage in a pipelined system the following instruction can follow through the stages as the former instruction vacates them allowing several instructions to be processed simultaneously While it may take several cycles for an instruction to pass through all the stages when the pipeline has been filled one instruction can complete its work on every clock cycle Chapter 6 Instruction Timing For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Timing Overview Figure 6 1 represents a generic pipelined execution unit Stage 1 Stage 2 Stage 3 Clock OU Instruction A Clock 1 Instruction B Clock 2 Instruction C Instruction A Clock 321 Instruction D Instruction B Figure 6 1 Pipelined Execution Unit i The entire path that instructions take through the fetch decode dispatch execute complete and write back stages is considered the MPC603e master pipeline and two of the MPC603e execution units FPU and LSU are also multiple stage pipelines The MPC6
91. additional information about illegal and invalid instruction exceptions The following types of instructions are included in this class e Implementation specific instructions for example Load Data TLB Entry tlbld and Load Instruction TLB Entry tlbli instructions e Optional instructions defined by the PowerPC architecture but not implemented by the MPC603e for example Floating Square Root fsqrt and Floating Square Root Single fsqrts instructions 2 3 2 Addressing Modes This section provides an overview of conventions for addressing memory and calculating effective addresses as defined by the PowerPC architecture for 32 bit implementations For more detailed information see Conventions in Chapter 4 Addressing Modes and Instruction Set Summary of the Programming Environments Manual 2 3 2 1 Memory Addressing A program references memory using the effective logical address computed by the processor when it executes a memory access or branch instruction or when it fetches the next sequential instruction Bytes in memory are numbered consecutively starting with zero Each number is the address of the corresponding byte 2 3 2 2 Memory Operands Memory operands may be bytes half words words or double words or for the load store multiple and load store string instructions a sequence of bytes or words The address of a memory operand is the address of its first byte that is of its lowest numbered byte O
92. allocates a cache block in the cache and may not verify that the physical address is valid If a cache block is created for an invalid physical address a machine check condition may result when an attempt is made to write that cache block back to memory The cache block could be written back as a result of the execution of an instruction that causes a cache miss and the invalid addressed cache block is the target for replacement or a Data Cache Block Store dcbst instruction Note that any cache control instruction that generates an effective address that corresponds to a direct store segment SR T 1 is treated as a no op Table 2 35 lists the cache instructions that are accessible to user level programs Note that incoherency may occur if a write through store is followed by a debz instruction that is in turn followed by a snoop all to the same cache block This occurs when the logical address for the debz and the write through store are different but aliased to the same physical page To avoid potential adverse effects dcbz should not address write through memory that can be accessed through multiple logical addresses Explicit store instructions that write all zeroes should be used instead Note that broadcasting a sequence of dcbz instructions may cause snoop accesses to be retried indefinitely which may cause the snoop originator to time out or the snooped transaction to not complete This can be avoided by disabling the broadcasti
93. allow adequate address access time for slow devices For example if an implementation supports slow snooping devices an external arbiter can postpone the assertion of AACK Negation Must occur one bus clock cycle after the assertion of AACK 7 2 5 2 Address Retry ARTRY The ARTRY signal is both an input and output signal on the MPC603e 7 2 5 2 1 Address Retry ARTRY Output Following are the state meaning and timing comments for the ARTRY output State Meaning Asserted lIndicates that the MPC603e detects a condition in which a snooped address tenure must be retried If the MPC603e needs to update memory as a result of the snoop that caused the retry the Chapter 7 Signal Descriptions For More Information On This Product Go to www freescale com Signal Descriptions Timing Comments Freescale Semiconductor Inc MPC603e asserts BR the second cycle after AACK if ARTRY is asserted High Impedance Indicates that the MPC603e does not need the snooped address tenure to be retried Assertion Asserted the third bus cycle following the assertion of TS if a retry is required Negation Occurs the second bus cycle after the assertion of AACK Since this signal may be simultaneously driven by multiple devices it negates in a unique fashion First the buffer goes to high impedance for a minimum of one half processor cycle dependent on the clock mode then it is driven negated for one bus cycle before retu
94. and Block Address Translation Selection When an instruction or data access is generated and the corresponding instruction or data translation is disabled MSR IR 0 or MSR DR 0 real addressing mode translation is used physical address equals effective address and the access continues to the memory subsystem as described in Section 5 2 Real Addressing Mode Figure 5 5 shows the flow used by the MMUs in determining whether to select real addressing mode block address translation or to use the segment descriptor to select page address translation Note that if the BAT array search results in a hit the access is qualified with the appropriate protection bits If the access violates the protection mechanism an exception ISI or DSI exception is generated Chapter 5 Memory Management For More Information On This Product Go to www freescale com MMU Features Freescale Semiconductor Inc Effective Address Generated l Access D Access Instruction D Data Translation Disabled EE ata Translation Disabled MSRIIR 0 Translation Enabled Translation Enabled MSR DR 0 MSR IR 1 o MSR DR 1 Perform Real Perform Real Addressing Mode Translation Addressing Mode Compare Address with Translation Instruction or Data BAT Array As Appropriate BAT Array BAT Array see the Programming Miss Hit Environments Manual Perform Address Translation with Segment Descriptor Access
95. at any time and may be asserted asynchronously to the input clocks Negation Is negated upon assertion of HRESET 7 2 9 6 Reset Signals There are two reset signals on the MPC603e hard reset HRESET and soft reset SRESET Descriptions of the reset signals are as follows 7 2 9 6 1 Hard Reset HRESET Input The HRESET input must be used at power on to properly reset the processor Following are the state meaning and timing comments for the HRESET input State Meaning Asserted Initiates a complete hard reset operation when this input transitions from asserted to negated Causes a reset exception as described in Section 4 5 1 1 Hard Reset and Power On Reset Output drivers are released to high impedance within five clocks after the assertion of HRESET Negated Indicates that normal operation should proceed See Section 8 7 3 Reset Inputs Timing Comments Assertion May occur at any time and may be asserted asynchronously to the MPC603e input clock must be held asserted for a minimum of 255 clock cycles after the PLL lock time has been met Refer to the appropriate hardware specifications for further timing comments Negation May occur any time after the minimum reset pulse width has been met This input has additional functionality in certain test modes 7 2 9 6 2 Soft Reset SRESET Input The SRESET signal is input only Following are the state meaning and timing comments for the SRESET input
96. burst transfers the address bus presents the double word aligned address containing the critical code or data that missed the cache on a read operation or the first double word of the cache line on a write operation Note that the address output during burst operations is not incremented See Section 8 3 2 Address Transfer Timing Comments Assertion Negation Occurs on the bus clock cycle after a qualified bus grant coincides with assertion of ABB and TS High Impedance Occurs one bus clock cycle after AACK is asserted 7 2 3 1 2 Address Bus A 0 31 Input Following are the state meaning and timing comments for the A 0 31 inputs State Meaning Asserted Negated Represents the physical address of a snoop operation Timing Comments Assertion Negation Must occur on the same bus clock cycle as the assertion of TS is sampled by MPC603e only on this cycle 7 2 3 2 Address Bus Parity AP 0 3 The AP 0 3 signals are both input and output signals reflecting 1 bit of odd byte parity for each of the 4 bytes of address when a valid address is on the bus 7 2 3 2 1 Address Bus Parity AP 0 3 Output Following are the state meaning and timing comments for the AP 0 3 outputs State Meaning Asserted Negated Represents odd parity for each of 4 bytes of the physical address for a transaction Odd parity means that an odd number of bits including the parity bit are driven high The signal assignments correspond to t
97. by the PID7v 603e Refer to Section 3 2 3 Data Cache Control for more information 29 30 Reserved 31 NOOPTI No op the data cache touch instructions 0 The debt and debtst instructions are enabled 1 The debt and debtst instructions are no oped globally 1 See Chapter 9 Power Management for more information 2 See Chapter 3 Instruction and Data Cache Operation for more information 2 1 2 1 2 8 Also add to this section the following Table 2 3 the paragraph preceding it and the sentence immediately following it Table 2 3 shows how HIDO BCLK HIDO ECLK and HRESET are used to configure CLK_OUT See Section 7 2 12 2 Test Clock CLK_OUT Output for more information Table 2 3 HIDO BCLK and HIDO ECLK CLK_OUT Configuration HRESET HIDO ECLK HIDO BCLK CLK_OUT Asserted D D Bus Negated 0 0 High impedance Negated 0 1 Core clock frequency Negated 1 0 Bus Negated 1 1 Core clock frequency HIDO can be accessed with mtspr and mfspr using SPR1008 Then after Figure 2 3 add the following HID1 can be accessed with mfspr using SPR1009 2 1 2 7 2 12 Remove this section The Run_N counter is not an SPR 2 3 5 3 2 41 Add the following text to the end of this section Note that incoherency may occur if the following sequence of accesses hits the same cache block a write through a dcbz instruction a snoop This occurs when the logical addre
98. byte Memory operands may be bytes half words words or double words or for the load store multiple and move assist instructions a sequence of bytes or words The address of a memory operand is the address of its first byte that is of its lowest numbered byte Operand length is implicit for each instruction 2 2 3 Alignment and Misaligned Accesses The operand of a single register memory access instruction has a natural alignment boundary equal to the operand length In other words the natural address of an operand is an integral multiple of the operand length A memory operand is said to be aligned if it is aligned at its natural boundary otherwise it is misaligned Operands for single register memory access instructions have the characteristics shown in Table 2 9 Although not permitted as memory operands quad words are shown because quad word alignment is desirable for certain memory operands Table 2 9 Memory Operands Operand Length At Angie Byte 8 bits XXXX Half word 2 bytes xxx0 Word 4 bytes xx00 Double word 8 bytes x000 Quad word 16 bytes 0000 Note An xin an address bit position indicates that the bit can be 0 or 1 independent of the state of other address bits The concept of alignment is also applied more generally to data in memory For example a 12 byte data item is said to be word aligned if its address is a multiple of 4 Implementation Notes The following describes how
99. cache block The other device can then attempt an access to the updated address See Chapter 3 Instruction and Data Cache Operation Copy back mode provides complete cache memory coherency as well as maximizing available external bus bandwidth 6 5 2 Write Through Mode Store operations to memory in write through mode always update memory as well as the on chip cache on cache hits Write through mode is used when the data in the cache must always agree with external memory for example video memory when shared global data may be used frequently or when allocation of a cache line on a cache miss is undesirable Automatic copy back of cached data is not performed if that data is from a memory page marked as write through mode because valid cache data always agrees with memory Stores to memory that are in write through mode may cause a decrease in performance Each time a store is performed to memory in write through mode the bus is busy for the extra clock cycles required to update memory therefore load operations that miss the on chip cache must wait while the external store operation completes 6 5 3 Cache Inhibited Accesses Data for a page marked cache inhibited cannot be stored in the on chip cache Areas of the memory map can be cache inhibited by the operating system If a cache inhibited access hits in the on chip cache the corresponding cache line is Chapter 6 Instruction Timing For More Information On This Pro
100. checkstop To prevent a checkstop in this case a sync instruction must be placed between two stores that can result in assertion of TEA Software can use the machine check exception in a recoverable mode to probe memory For this case a sync load sync instruction sequence is used If the load access results in a system error for example the assertion of TEA the processor can handle this in a recoverable state If the sync instruction is not used a second access to the same address as the first load could cause the processor to enter the checkstop state Chapter 4 Exceptions For More Information On This Product Go to www freescale com mor Freescale Semiconductor Inc Exception Definitions If the MSR ME bit is set the exception is recognized and handled otherwise the MPC603e attempts to enter an internal checkstop Note that the resulting machine check exception has priority over any exceptions caused by the instruction that generated the bus operation Machine check exceptions are only enabled when MSR ME 1 this is described in Section 4 5 2 1 Machine Check Exception Enabled MSR ME 1 If MSR ME 0 and a machine check occurs the processor enters the checkstop state Checkstop state is described in 4 5 2 2 Checkstop State MSR ME 0 4 5 2 1 Machine Check Exception Enabled MSR ME 1 When a machine check exception is taken registers are updated as shown in Table 4 11 When a machine ch
101. clear the valid bits of the unused BAT entries The second part of the second sentence in the first paragraph of that page should be deleted so that the sentence should read as follows ITLB miss exception conditions are reported when there are no more instructions to be dispatched or retired the pipeline is empty The very last sentence on this page should be edited as follows In order to uniquely identify a TLB entry as the required PTE the TLB entry also contains The phrase the valid entries are loaded and should be deleted from the second sentence in the last paragraph of section 5 4 3 1 Figure 5 8 in the published manual incorrectly shows the loopback arrow on the left side pointing to the node above the word otherwise Replace Figure 5 8 with the following MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semicon uctor vision Change Effective address generated 1 See Figure 5 6 fine Revision 1 to Revision 2 otherwise y Instruction fetch with N bit setin segment descriptor Page address no execute translation Generate 52 bit virtual address from segment descriptor Compare virtual address with TLB entries TLB hit case debz instruction with W orl 1 otherwise Alignment exception Check page memory protection violation conditions See the Programming Environments
102. describes the memory model for an environment in which multiple processors or other devices can access external memory and defines aspects of the cache model and cache control instructions from a user level perspective The resources defined by the VEA are particularly useful for optimizing memory accesses and managing resources in an environment in which other processors and devices can access external memory Implementations that conform to the VEA also conform to the UISA but may not necessarily adhere to the OEA e Operating environment architecture OEA The OEA defines supervisor level resources typically required by an operating system The OEA defines the memory management model supervisor level registers and exception model Implementations that conform to the OEA also conform to the UISA and VEA About This Book For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Audience Note that some resources are defined more generally at one level in the architecture and more specifically at another For example conditions that cause a floating point exception are defined by the UISA while the exception mechanism is defined by the OEA Because it is important to distinguish between the levels of the architecture to ensure compatibility across multiple platforms those distinctions are shown clearly throughout this book For ease in reference topics in this book are arranged to build on o
103. directly by the program If there are areas of memory that are not fully populated in other words there are holes in the memory map within this area this setting can protect the system from undesired accesses caused by out of order load operations or instruction prefetches that could lead to the generation of the machine check exception Also the guarded bit can be used to prevent out of order load operations or prefetches from occurring to certain peripheral devices that produce undesired results when accessed in this way 3 5 5 W I and M Bit Combinations Table 3 1 summarizes the six combinations of the WIM bits Note that either a zero or one setting for the G bit is allowed for each of these WIM bit combinations Table 3 1 Combinations of W I and M Bits WIM Setting Meaning 000 Data may be cached Loads or stores whose target hits in the cache use that entry in the cache Memory coherency is not enforced by hardware 001 Data may be cached Loads or stores whose target hits in the cache use that entry in the cache Memory coherency is enforced by hardware 010 Caching is inhibited The access is performed to external memory completely bypassing the cache Memory coherency is not enforced by hardware Chapter 3 Instruction and Data Cache Operation For More information On This Product Go to www freescale com Memory ManagementCache Reece Mt se Bemisand gtor Inc Table 3 1 Combinations of W
104. e Snoop attempt during the cycle that a debf or debst instruction is updating the tag If the EA of a debf or debst instruction hits in the cache the tag will be changed to its new state During that clock the tag is not accessible and snoop transactions during that cycle will cause the assertion of ARTRY 3 6 9 Enveloped High Priority Cache Block Push Operation In cases where the MPC603e has completed the address tenure of a read operation and then detects a snoop hit to a modified cache block by another bus master the MPC603e provides a high priority push operation If the address snooped is the same as the address of the data to be returned by the read operation ARTRY is asserted one or more times until the data tenure of the read operation is completed The cache block push transaction can be enveloped within the address and data tenures of a read operation This feature prevents deadlocks in system organizations that support multiple memory mapped buses More specifically the MPC603e internally detects the scenario where a load request is outstanding and the processor has pipelined a write operation on top of the load Normally when the data bus is granted to the MPC603e the resulting data bus tenure is used for the load operation The enveloped high priority cache block push feature defines a bus signal the data bus write only qualifier DBWO which when asserted with a qualified data bus grant indicates that the resulting data
105. eco ie aacaeeasoecasavertssenseanee sen 7 20 Data Parity Error DPE Output cccccscssssesscscescssssssessssassesseseacesesees 7 20 Data Bus Disable DBDIS Input 00 0 ececeeeeeceeeeeceeeeeesteeeetteeeenaes 7 21 Data Transfer Termination Signals ceccceescecesceeeeececeeeeeeeeeeeeseeeenaeeees 7 21 Transfer Acknowledge TA Input ccccccsccscscscscscsescsesesesesesesesesesescsees 7 21 Data Retry CDORTRY niputs i eatin date eae a 7 22 Transfer Error Acknowledge TEA Inptt s ss ssssessississrissirssiesrereeen 7 22 System Status Signals censis ne dee AER 7 23 Interrupt EE ee 7 23 System Management Interrupt GM Input 7 23 Machine Check Interrupt OMCPk Jnput 7 24 Checkstop Input CKSTP_IN Input 000 0c eeeeeceeececeeeeeceneeeesteeeeeaes 7 24 Checkstop Output CKSTP OUTTk Outmut 7 24 LE EE 7 25 Hard Reset HRESET Im put isis csaacetadeceis cagesassavsdaatsansceaestedecaracessaeeoaes 7 25 Soft Reset SRESE DT lt eege KEREN deeg 7 25 Processor Status Signals 20 3 65 Coes a Gate ees 7 26 Quiescent Request EECH eege 7 26 Quiescent Acknowledge QA CK 2 ccas sssccdascegeante tp eeacatesacdetganvandacceeess 7 26 Reservation RSRV Output 3 2s secsccseseadecssecceds segeeeteavessceuatecnenssnaveauesens 7 27 Time Base Enable CT BEN Input eege ed seassaeetvensaiogecdgueenccehaetyous 7 27 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go
106. efficient snooping protocol for systems with multiple memory systems including caches that must remain coherent 8 2 1 Arbitration Signals Arbitration for both address and data bus mastership is performed by a central external arbiter and minimally by the arbitration signals shown in Section 7 2 1 Address Bus Arbitration Signals Most arbiter implementations require additional signals to coordinate bus master slave snooping activities Note that address bus busy ABB and data bus busy DBB are bidirectional signals These signals are inputs unless the MPC603e has mastership of one or both of the respective buses they must be connected high through pull up resistors so that they remain negated when no devices have control of the buses The following list describes the address arbitration signals e BR bus request Assertion indicates that the MPC603e is requesting mastership of the address bus e BG bus grant Assertion indicates that the MPC603e may with the proper qualification assume mastership of the address bus A qualified bus grant occurs when BG is asserted and ABB and ARTRY are negated If the MPC603e is parked BR need not be asserted for the qualified bus grant e ABB address bus busy Assertion by the MPC603e indicates that the MPC603e is the address bus master The following list describes the data arbitration signals e DBG data bus grant Indicates that the MPC603e may with the prope
107. encoding that identifies the type of instruction Program order The order of instructions in an executing program More specifically this term is used to refer to the original order in which program instructions are fetched into the instruction queue from the cache Protection boundary A boundary between protection domains Protection domain A protection domain is a segment a virtual page a BAT area or a range of unmapped effective addresses It is defined only when the appropriate relocate bit in the MSR IR or DR is 1 Quiesce To come to rest The processor is said to quiesce when an exception is taken or a Sync instruction is executed The instruction stream is stopped at the decode stage and executing instructions are allowed to complete to create a controlled context for instructions that may be affected by out of order parallel execution See Context synchronization Quiet NaN A type of NaN that can propagate through most arithmetic operations without signaling exceptions A quiet NaN is used to represent the results of certain invalid operations such as invalid arithmetic operations on infinities or on NaNs when invalid See Signaling NaN rA The rA instruction field is used to specify a GPR to be used as a source or destination rB The rB instruction field is used to specify a GPR to be used as a source MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescal
108. execute from the beginning For more information refer to DSI Exception 0x00300 in Chapter 6 Exceptions in the Programming Environments Manual Implementation Note If rA is in the range of registers to be loaded for a Load String Word Immediate Iswi instruction or if either rA or rB is in the range of registers to be loaded for a Load String Word Indexed Iswx instruction the PowerPC architecture defines the instruction to be of an invalid form In addition the Iswx and stswx instructions that specify a string length of zero are defined to be invalid by the PowerPC architecture However none of these cases hold true for the MPC603e the MPC603e treats these cases as valid forms 2 3 4 3 8 Floating Point Load and Store Address Generation Floating point load and store operations generate effective addresses using the register indirect with immediate index addressing mode and register indirect with index addressing mode details are described below Floating point loads and stores are not supported for direct store accesses The use of the floating point load and store operations for direct store accesses results in a DSI exception 2 3 4 3 9 Floating Point Load Instructions Separate floating point load instructions are used for single precision and double precision operands Because FPRs support only double precision format the FPU converts MPC603e RISC Microprocessor User s Manual For More Information On This Produ
109. for DH and DL State Meaning The data bus has two halves data bus high DH and data bus low DL See Table 7 6 for the data bus lane assignments Timing Comments The data bus is driven once for noncached transactions and four times for cache transactions bursts MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc i Ka Signal Descriptions Table 7 6 Data Bus Lane Assignments Data Bus Signals Byte Lane DH 0 7 0 DH 8 15 i DH 16 23 DH 24 31 DL 0 7 DL 8 15 DL 16 23 NI oi oO BY WO h DL 24 31 7 2 7 1 1 Data Bus DH 0 31 DL 0 31 Output Following are the state meaning and timing comments for the DH and DL outputs State Meaning Asserted Negated Represents the state of data during a data write Byte lanes not selected for data transfer will not supply valid data Timing Comments Assertion Negation Initial beat coincides with DBB and for bursts transitions on the bus clock cycle following each assertion of TA High Impedance Occurs on the bus clock cycle after the final assertion of TA 7 2 7 1 2 Data Bus DH 0 31 DL 0 31 Input Following are the state meaning and timing comments for the DH and DL inputs State Meaning Asserted Negated Represents the state of data during a data read transaction Timing Comments Assertion Negation Data mus
110. for this exception are described in Chapter 6 Exceptions in the Programming Environments Manual When a decrementer exception is taken instruction execution for the handler begins at offset 0x00900 from the physical base address indicated by MSR IP 4 5 10 System Call Exception 0x00C00 The MPC603e implements the system call exception as it is defined by the PowerPC architecture A system call exception request is made when a system call sc instruction is completed If no higher priority exception exists the system call exception is taken with SRRO being set to the EA of the instruction following the sc instruction Register settings for this exception are described in Chapter 6 Exceptions in the Programming Environments Manual When a system call exception is taken instruction execution for the handler begins at offset 0x00C00 from the physical base address indicated by MSR IP 4 5 11 Trace Exception 0x00D00 The trace exception is taken under one of the following conditions e When MSR SE is set a single step instruction trace exception is taken when no higher priority exception exists and any instruction other than rfi or isync is successfully completed Note that other processors will take the trace exception on isync instructions when MSR SE is set the MPC603e does not take the trace exception on isync instructions Single step instruction trace mode is described in Section 4 5 11 1 Single Step Inst
111. inhibited accesses The cache inhibited CI signal is asserted if a cache access misses into a locked cache The setting of DLOCK must be preceded by a sync instruction to prevent the cache from being locked during an access 3 2 3 4 Data Cache Operations and Address Broadcasts Executing a dcbz instruction generates an address only broadcast on the bus Additionally if HIDO ABE is set on a PID7t 603e processor the execution of the debf debi and dcbst instructions also causes an address only broadcast The ability of the PID7t 603e to optionally perform address only broadcasts when executing the debi dcht and dcbst instructions allows the coherency management of an external copy back L2 cache Note that these cache control instruction broadcasts are not snooped by the PID7t 603e Chapter 3 Instruction and Data Cache Operation For More Information On This Product Go to www freescale com Ge operati eescale Semiconductor Inc 3 2 4 Data Cache Touch Load Support Touch load operations allow an instruction stream to prefetch data from memory prior to a cache miss The MPC603e supports touch load operations through a temporary cache block buffer located between the BIU and the data cache The cache block buffer is essentially a floating cache block that is loaded by the BIU on a touch load operation and is then read by a load instruction that requests that data After a touch load completes on the bus the BIU continues to compare the t
112. is no hits under misses The critical double word is simultaneously written to the cache and forwarded to the requesting unit minimizing stalls due to load delays Cache lines are selected for replacement based on an LRU algorithm Each time a cache line is accessed it is tagged as the most recently used line of the set When a miss occurs if all lines in the set are marked as valid the LRU line is replaced with the new data When data to be replaced is in the modified state the modified data is written into a write back buffer while the missed data is being read from memory When the load completes the MPC603e then pushes the replaced line from the write back buffer to main memory in a burst write operation 8 1 2 Operation of the System Interface Memory accesses can occur in single beat 1 to 8 bytes and four beat 32 bytes burst data transfers when the MPC603e is configured with a 64 bit data bus When the MPC603e is in the optional 32 bit data bus mode memory accesses can occur in single beat 1 to 4 bytes two beat 8 bytes and eight beat 32 bytes bursts The address and data buses are independent for memory accesses to support pipelining and split transactions The MPC603e can pipeline as many as two transactions and has limited support for out of order split bus transactions Access to the system interface is granted through an external arbitration mechanism that allows devices to compete for bus mastership This arbitration
113. is issued that marks the state of each data cache block as invalid without writing back modified cache blocks to memory Cache access is blocked during this time Bus accesses to the cache are signaled as a miss during invalidate all operations Setting DCFI clears all the valid bits of the blocks and the PLRU bits to point to way LO of each set For 603e processors the proper use of the ICFI and DCFI bits is to set them and clear them with two consecutive mtspr operations 22 23 Reserved 24 IFEM Instruction fetch enable M PID7v 603e only Enables the M bit on the bus Used for instruction fetches 25 26 Reserved 27 FBIOB Force branch indirect on bus 0 Register indirect branch targets are fetched normally 1 Forces register indirect branch targets to be fetched externally MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semicond Heger doe Revision 1 to Revision 2 Table 2 2 HIDO Bit Functions continued Bit Name Function 28 ABE Address broadcast enable controls whether certain address only operations such as cache operations are broadcast on the 60x bus 0 Address only operations affect only local caches and are not broadcast 1 Address only operations are broadcast on the 60x bus Affected instructions are debi dcbf and dcebst Note that these cache control instruction broadcasts are not snooped
114. it is asserted after the last or only data beat the MPC603e negates DBB but still considers the data beat active and waits for another assertion of TA DRTRY is ignored on write operations TEA indicates a nonrecoverable bus error event Upon receiving a final or only termination condition the MPC603e always negates DBB for one cycle If DRTRY is asserted by the memory system to extend the last or only data beat past the negation of DBB the memory system should three state the data bus on the clock after the final assertion of TA even though it will negate DRTRY on that clock This is to prevent a potential momentary data bus conflict if a write access begins on the following cycle The TEA signal is used to signal a nonrecoverable error during the data transaction It may be asserted on any cycle during DBB or on the cycle after a qualified TA during a read operation except when no DRTRY mode is selected where no DRTRY mode cancels checking the cycle after TA The assertion of TEA terminates the data tenure immediately even if in the middle of a burst however it does not prevent incorrect data that has just been acknowledged with TA from being written into the MPC603e cache or GPRs The assertion of TEA initiates either a machine check exception or a checkstop condition based on the setting of the MSR An assertion of ARTRY causes the data tenure to be terminated immediately if the ARTRY is for the address tenure as
115. meanings and timing comments for the TBEN input State Meaning Timing Comments Asserted Indicates that the time base should continue clocking This input is essentially a count enable control for the time base counter Negated Indicates the time base should stop clocking Assertion Negation May occur on any cycle 7 2 9 7 5 TLBI Sync TLBISYNC Following are the state meaning and timing comments for the TLBISYNC input State Meaning Timing Comments Asserted Indicates that instruction execution should stop after execution of a tlbsync instruction Negated Indicates that the instruction execution may continue or resume after the completion of a tlbsync instruction Assertion Negation May occur on any cycle Start Up TLBISYNC is sampled at the negation of HRESET to select the 32 bit data bus mode if TLBISYNC is negated at start up the 32 bit mode is disabled and the default 64 bit mode is selected 7 2 10 COP Scan Interface The MPC603e has extensive on chip test capability including the following e Built in instruction and data cache self test BIST e Debug control observation COP e Boundary scan IEEE 1149 1 compliant interface e LSSD test control Chapter 7 Signal Descriptions For More Information On This Product Go to www freescale com ae Freescale Semiconductor Inc Signal Descriptions The BIST hardware is not exercised as part of the power on reset POR sequence The COP and boun
116. of the bus Once the MPC603e is granted the bus it no longer needs to perform the copy back operation therefore the MPC603e does not assert ABB and does not use the bus for the copy back operation Note that the MPC603e asserts BR for at least 1 clock cycle in these instances 8 3 2 Address Transfer During the address transfer the physical address and all attributes of the transaction are transferred from the bus master to slave devices Snooping logic may monitor the transfer to enforce cache coherency see discussion about snooping in Section 8 3 3 Address Transfer Termination The signals used in the address transfer include the following signal groups e Address transfer start signal Transfer start TS e Address transfer signals Address bus A 0 31 address parity AP 0 3 and address parity error APE e Address transfer attribute signals Transfer type TT 0 4 transfer code TC 0 1 transfer size TSIZ 0 2 transfer burst TBST cache inhibit CI write through WT global GBL and cache set element CSE 0 1 Figure 8 5 shows that the timing for all of these signals except TS and APE is identical All of the address transfer and address transfer attribute signals are combined into the ADDR grouping in Figure 8 5 The TS signal indicates that the MPC603e has begun an address transfer and that the address and transfer attributes are valid within the context of a synchronous bus The MPC603e alway
117. of the optional bus configurations are described in the following sections 8 6 1 32 Bit Data Bus Mode The MPC603e supports an optional 32 bit data bus mode which differs from the 64 bit data bus mode only in the byte lanes involved in the transfer and the number of data beats performed When in 32 bit data bus mode only byte lanes O through 3 are used corresponding to DHO DH31 and DPO DP3 Byte lanes 4 through 7 corresponding to DLO DL31 and DP4 DP7 are never used in this mode The unused data bus signals are not sampled by the MPC603e during read operations and they are driven low during write operations A data tenure in the 32 bit data bus mode takes one two or eight beats depending on the transfer size and the cache mode for the address Data transactions of one or two data beats are performed for caching inhibited load store or write through store operations These transactions do not assert the TBST signal even though a two beat burst may be performed having the same TBST and TSIZ 0 2 encodings as the 64 bit data bus mode Single beat data transactions are performed for bus operations of 4 bytes or less and double beat data transactions are performed for 8 byte operations only The MPC603e only generates an 8 byte operation for a double word aligned load or store double operation to or from the floating point GPRs All cache inhibited instruction fetches are performed as word single beat operations Data transactions
118. of the translation so an ISI exception must be taken to load the PTE and possibly the page into memory e The fetch access is to a direct store segment indicated by SRR1 3 set e The fetch access violates memory protection indicated by SRR1 4 set If the key bits Ks and Kp in the segment register and the PP bits in the PTE are set to prohibit read access instructions cannot be fetched from this location External interrupt 00500 An external interrupt is caused when MSR EE 1 and the INT signal is asserted Alignment 00600 An alignment exception is caused when the MPC603e cannot perform a memory access for any of the reasons described below e The operand of a floating point load or store instruction is not word aligned e The operand of Imw stmw Iwarx and stwex instructions are not aligned e The operand of a single register load or store operation is not aligned and the MPC603e is in little endian mode PID6 603e only e The execution of a floating point load or store instruction to a direct store segment e The operand of a load store load multiple store multiple load string or store string instruction crosses a segment boundary into a direct store segment or crosses a protection boundary e Execution of a misaligned eciwx or ecowx instruction PID7t 603e only e The instruction is Imw stmw Iswi Iswx stswi stswx and the MPC603e is in little endian mode e The operand of dcbz is in
119. operating environment architecture common among processors that implement the PowerPC architecture and describes the programming model It also describes the additional registers that are unique to the MPC603e e Section 1 3 2 Instruction Set and Addressing Modes describes the PowerPC instruction set and addressing modes for the OEA and defines and describes the PowerPC instructions implemented in the MPC603e e Section 1 3 3 Cache Implementation describes the cache model that is defined generally for processors that implement the PowerPC architecture by the VEA It also provides specific details about the MPC603e cache implementation e Section 1 3 4 Exception Model describes the exception model of the OEA and the differences in the MPC603e exception model e Section 1 3 5 Memory Management describes generally the conventions for memory management among these processors This section also describes the MPC603e implementation of the 32 bit PowerPC memory management specification e Section 1 3 6 Instruction Timing provides a general description of the instruction timing provided by the superscalar parallel execution supported by the PowerPC architecture and the MPC603e e Section 1 3 7 System Interface describes the signals implemented on the MPC603e The MPC603e is a high performance superscalar microprocessor The PowerPC architecture allows optimizing compilers to schedule instructions
120. or LR from the branch instruction performing the evaluation Separation of the branch and mtspr instruction by more than nine instructions ensures the register values will be immediately available for use by the branch instruction e Schedule instructions such that they can dual dispatch e Schedule instructions to minimize stalls when an execution unit is busy e Avoid using serializing instructions e Schedule instructions to avoid dispatch stalls due to renamed resource limitations Only five instructions can be in execute complete stage at any one time Only five GPR destinations can be in execute complete deallocate stage at any one time Note that load with update address instructions use two destination registers Only four FPR destinations can be in execute complete deallocate stage at any one time MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Scheduling Guidelines 6 6 1 Branch Dispatch and Completion Unit Resource Requirements This section describes the specific resources required to avoid stalls during branch resolution instruction dispatching and instruction completion 6 6 1 1 Branch Resolution Resource Requirements The following is a list of branch instructions and the resources required to avoid stalling the fetch unit in the course of branch resolution e The belr instruction requires LR availability e Th
121. or instruction fetch performed to such a device might cause the device to perform unexpected or incorrect operations Another example of memory that should be designated as guarded is the area that corresponds to the device that resides at the highest implemented physical address as it has no successor and out of order sequential operations such as instruction prefetching may result in a machine check exception In addition areas that contain holes in the physical memory space may be designated as guarded 3 5 5 2 Effects of Out of Order Data Accesses Most data operations may be performed out of order as long as the machine appears to follow a simple sequential model However the following out of order operations do not occur e Out of order loading from guarded memory G 1 does not occur However when a load or store operation is required by the program the entire cache block s containing the referenced data may be loaded into the cache e Out of order store operations that alter the state of the target location do not occur MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor INg erency ME Protocol e No errors except machine check exceptions are reported due to the out of order execution of an instruction until it is known that execution of the instruction is required Machine check exceptions resulting solely from out of order execution f
122. order after instructions are dispatched guaranteeing in order completion and a precise exception model Completing an instruction implies committing execution results to the architected destination registers In order completion ensures the correct architectural state when the MPC603e must recover from a mispredicted branch or an exception The MPC603e can execute instructions out of order but in order completion by the completion unit ensures a precise exception mechanism Program related exceptions are signaled when the instruction causing the exception reaches the last position in the completion queue Prior instructions are allowed to complete before the exception is taken 6 3 3 1 Rename Register Operation To avoid contention for a given register file location the MPC603e provides rename registers for holding instruction results before the completion commits them to the architected register There are five GPR rename registers four FPR rename registers and one each for the CR LR and CTR When an instruction dispatches to its execution unit any required rename registers are allocated for the results of that instruction If an instruction is dispatched to the reservation station associated with an execution unit due to a data dependency the dispatcher also provides a tag to the execution unit identifying the rename register that forwards the required data at completion When the source data reaches the rename register execution can beg
123. order execution from nonguarded memory may be reported When an out of order instruction result is abandoned only one side effect other than a possible machine check may occur the referenced bit R in the corresponding page table entry and TLB entry can be set due to an out of order load operation See Chapter 4 Exceptions for more information on the machine check exception Instruction fetching from guarded memory is not permitted 3 6 Cache Coherency MEI Protocol The primary objective of a coherent memory system is to provide the same image of memory to all devices using the system Coherency allows synchronization and cooperative use of shared resources Otherwise multiple copies of a memory location some containing stale values could exist in a system resulting in errors when the stale values are used Each potential bus master must follow rules for managing the state of its cache Chapter 3 Instruction and Data Cache Operation For More Information On This Product Go to www freescale com Cache Coherency MEI ph regseale Semiconductor Inc The MPC603e cache coherency protocol is a coherent subset of the standard MESI four state cache protocol that omits the shared state Since data cannot be shared the MPC603e signals all cache block fills as if they were write misses read with intent to modify flushing the corresponding copies of the data in all caches external to the MPC603e prior to the MPC603e cache bl
124. pipeline its own transactions to a depth of one level intraprocessor pipelining however the MPC603e bus protocol does not constrain the maximum number of levels of pipelining that can occur on the bus between multiple masters interprocessor MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Address Bus Tenure pipelining The external arbiter must control the pipeline depth and synchronization between masters and slaves In a pipelined implementation data bus tenures are kept in strict order with respect to address tenures However external hardware can further decouple the address and data buses allowing the data tenures to occur out of order with respect to the address tenures This requires some form of system tag to associate the out of order data transaction with the proper originating address transaction not defined for the MPC603e interface Individual bus requests and data bus grants from each processor can be used by the system to implement tags to support interprocessor out of order transactions The MPC603e supports a limited intraprocessor out of order split transaction capability via the data bus write only DBWO signal For more information concerning the use of DBWO see Section 8 10 Using DBWO 8 3 Address Bus Tenure This section describes the address bus arbitration transfer and termination phases 8 3 1
125. ranges appear in brackets For example MSR LE refers to the little endian mode enable bit in the machine state register In some contexts such as signal encodings an unitalicized x indicates a don t care An italicized x indicates an alphanumeric variable An italicized n indicates an numeric variable A bar over a signal name indicates that the signal is active low NOT logical operator AND logical operator OR logical operator About This Book For More Information On This Product Go to www freescale com _ Freescale Semiconductor Inc Acronyms and Abbreviations Indicates reserved bits or bit fields in a register Although these bits can be written to as ones or zeros they are always read as zeros Acronyms and Abbreviations Table i contains acronyms and abbreviations that are used in this document Table i Acronyms and Abbreviated Terms Term Meaning ALU Arithmetic logic unit BAT Block address translation BHT Branch history table BIST Built in self test BIU Bus interface unit BPU Branch processing unit BSDL Boundary scan description language BTIC Branch target instruction cache BUC Bus unit controller BUID Bus unit ID CAR Cache address register CIA Current instruction address CMOS Complementary metal oxide semiconductor COP Common on chip processor CQ Completion queue CR Condition register CRTRY Cache retry queue CTR
126. register user privilege bit MSR PR is set In the MPC603e this exception is generated for mtspr or mfspr with an invalid SPR field if SPR O 1 and MSR PR 1 This may not be true for all processors that implement the PowerPC architecture e Trap A trap type program exception is generated when any of the conditions specified in a trap instruction is met 4 5 7 1 IEEE Floating Point Exception Program Exceptions Floating point exceptions are signaled by condition bits set in the floating point status and control register FPSCR They can cause the system floating point enabled exception handler to be invoked The MPC603e handles all floating point exceptions precisely The MPC603e implements the FPSCR as it is defined by the PowerPC architecture for more information about the FPSCR see the Programming Environments Manual Floating point operations that change exception sticky bits in the FPSCR may suffer a performance penalty When an exception is disabled in the FPSCR and MSR FE 0 updates to the FPSCR exception sticky bits are serialized at the completion stage This serialization may result in a one or two cycle execution delay The penalty is incurred only Chapter 4 Exceptions For More Information On This Product Go to www freescale com ES Freescale Semiconductor Inc Exception Definitions when the exception bit is changed and not on subsequent operations with the same exception See Chapter 6 Instruction Tim
127. sciaciciscaseisectiniee SSES EES 8 11 Address Bus Parity eers aean EE ERC 8 12 Address Transfer Attribute Senses ereregene Eder 8 12 Transfer Type TT 0 4 ateliers 8 12 Transfer Size T SIZ UR 8 13 Burst Ordering During Data Transfers 00 0 ee eee eeeeceeeceeeeeeeeeenneeneeeeees 8 13 Effect of Alignment in Data Transfers 64 Bit Bush 8 14 Effect of Alignment in Data Transfers 32 Bit Bus 0 eee eeeeeeeeeeee 8 16 Alignment of External Control Instructions 00 0 0 eee eeeeeeeeeeeneeeeeeees 8 18 Jeekelen deeg 8 19 Address Transfer Termination iiss acess ee ME EE 8 19 D ta B tee 8 21 Data Bus Arbitration cic0 couches eerie in se eae 8 21 Using the UE erer saved eet eeneg ed eener 8 22 MDa a B s Write E 8 22 Kean ee 8 23 Data Transfer Fett DEE ere escola ess coos eassees psa aeee ay este on ddcase eeeseaover es 8 24 Normal Single Beat Termmaton cee eeeeeeeeseecseceeeeeeeeeeaeecnaeeneeeeees 8 25 Normal Burst Ken EN EE 8 26 Data Transfer Termination Due to a Bus Error 8 27 Contents XV For More Information On This Product Go to www freescale com Paragraph Number 8 4 5 8 5 8 6 8 6 1 8 6 2 8 6 3 8 7 8 7 1 8 7 2 8 7 3 8 7 4 8 8 8 8 1 8 8 2 8 9 8 9 1 8 10 9 1 9 2 9 3 9 3 1 9 3 1 1 9 3 1 2 9 3 1 3 9 3 1 4 9 3 1 5 9 32 9 4 A l A 2 A AA A3 Freescale Semiconductor Inc Contents Page Title Number Memory Coherency MEI Protocol AAA 8 28 Juge Elei 8 30 Optional Bus Configur
128. set e The execution of an stwex instruction is allowed by the memory protection mechanism but a store operation is not performed because no reservation exists e The execution of an stswx instruction is allowed by the memory protection mechanism but a store operation is not performed because the specified length is zero e The store operation is not performed because an exception occurs before the store is performed Again note that although the execution of the debt and debtst instructions may cause the R bit to be set they never cause the C bit to be set 5 4 1 3 Scenarios for Referenced and Changed Bit Recording This section provides a summary of the model defined by the OEA that is used by processors for maintaining the referenced and changed bits In some scenarios the bits are guaranteed to be set by the processor in some scenarios the architecture allows that the bits may be set not absolutely required and in some scenarios the bits are guaranteed to not be set In implementations that do not maintain the R and C bits in hardware such as the MPC603e software assistance is required For these processors the information in this section still applies except that the software performing the updates is constrained to the rules described that is must set bits shown as guaranteed to be set and must not set bits shown as guaranteed to not be set Table 5 8 defines a prioritized list of the R and C bit settings for all
129. signal is an input signal on the MPC603e Following are the state meaning and timing comments for the BG input State Meaning Asserted Indicates that the MPC603e may with the proper qualification assume mastership of the address bus A qualified bus grant occurs when BG is asserted and ABB and ARTRY after AACK are not asserted ABB and ARTRY are driven by the MPC603e or other bus masters If the MPC603e is parked BR need not be asserted for the qualified bus grant See Section 8 3 1 Address Bus Arbitration Negated Indicates that the MPC603e is not the next potential address bus master Timing Comments Assertion May occur at any time to indicate the MPC603e is free to use the address bus After the MPC603e assumes bus mastership it does not check for a qualified bus grant again until the cycle during which the address bus tenure is completed assuming it has another transaction to run The MPC603e does not accept a BG in the cycles between the assertion of any TS and AACK Negation May occur anytime to indicate the MPC603e cannot use the bus The MPC603e may still assume bus mastership on the bus clock cycle of the negation of BG because during the previous cycle BG indicated to the MPC603e that it was free to take mastership if qualified 7 2 1 3 Address Bus Busy ABB The ABB signal is both an input and output signal MPC603e RISC Microprocessor User s Manual For More Information On This Produc
130. signals SRESET or HRESET or internally during the power on reset POR process The assertion of the soft reset signal SRESET as described in Section 7 2 9 6 2 Soft Reset SRESET Input causes the soft reset exception to be taken and the physical base address of the handler is determined by the MSR IP bit The assertion of the hard reset signal HRESET as described in Section 7 2 9 6 1 Hard Reset HRESET Input causes the hard reset exception to be taken and the physical address of the handler is always OxFFFO_0100 4 5 1 1 Hard Reset and Power On Reset As described in Section 4 1 2 Summary of Front End Exception Handling the hard reset exception is a nonrecoverable nonmaskable asynchronous exception maskable interrupt When HRESET is asserted or at power on reset POR the MPC603e immediately branches to OxFFFO_0100 without attempting to reach a recoverable state A hard reset has the highest priority of any exception and is always nonrecoverable Table 4 9 shows the state of the machine just before it fetches the first instruction of the system reset handler after a hard reset Table 4 9 Settings Caused by Hard Reset Register Setting Register Setting GPRs Unknown PVR 0003000n FPRs Unknown HIDO 00000000 FPSCR 00000000 HID1 00000000 CR All Os DMISS and IMISS All Os SRs Unknown DCMP and ICMP All Os MSR 00000040 RPA All Os Chapter 4 Exceptions For More Inf
131. store that results ina direct store error Does not occur in MPC603e Does not apply eciwx or ecowx attempted when external control facility disabled eciwx or ecowx attempted with EAR E 0 DSI exception DSISR 11 1 Imw stmw Iswi Iswx stswi or stswx instruction attempted in little endian mode Imw stmw Iswi Iswx stswi or stswx instruction attempted while MSR LE 1 Alignment exception Operand misalignment Translation enabled and operand is misaligned as described in Chapter 4 Exceptions Alignment exception some of these cases are implementation specific Note that some exception conditions depend upon whether the memory area is set up as write though W 1 or cache inhibited I 1 These bits are described fully in Memory Cache Access Attributes in Chapter 5 Cache Model and Memory Coherency of the Programming Environments Manual Refer to Chapter 4 Exceptions and to Chapter 6 Exceptions in the Programming Environments Manual for a complete description of the SRRI1 and DSISR bit settings for these exceptions MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MMU Features 5 1 8 MMU Instructions and Register Summary The MMU instructions and registers provide the operating system with the ability to set up the block address translation areas and
132. systems that contain four state caches With the exception of the debz instruction the MPC603e does not broadcast cache control instructions The cache control instructions are intended for the management of the local cache but not for other caches in the system MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Overview 64 Bit 2 Instructions E Sequential Branch Fetcher Processing F Unit 64 Bit Instruction Queue System Register Unit Instruction Unit 64 Bit Load Store FPR File Floating Point Unit GP Rename Unit FP Rename Registers Registers FPSCR Completion Unit Power Time Base Dissipation Counter Control Decrementer m 16 Kbyte 16 Kbyte JTAG COP Clock D Cache Cache Interface Multiplier OS Touch Load Buffer Processor Bus Copy Back Buffer Interface 32 Bit Address Bus 32 64 Bit Data Bus Figure 8 1 MPC603e Microprocessor Block Diagram Chapter 8 System Interface Operation For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Overview Cache lines in the MPC603e are loaded in four beats of 64 bits each or eight beats of 32 bits each when operating in a 32 bit bus mode The burst load is performed as a critical double word first operation The cache that is being loaded is blocked to internal accesses until the load completes that
133. tenure should be used for the store operation instead This signal is described in Section 8 10 Using DBWO Note that the enveloped copy back operation is an internally pipelined bus operation 3 7 Cache Control Instructions Software must use the appropriate cache management instructions to ensure that caches are kept consistent when data is modified by the processor When a processor alters a memory location that may be contained in an instruction cache software must ensure that updates MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor INGA Control Instructions to memory are visible to the instruction fetching mechanism Although the instructions to enforce coherency vary among implementations and hence operating systems should provide a system service for this function the following sequence is typical 1 dcbst update memory 2 sync wait for update 3 icbi invalidate copy in cache 4 isync invalidate copy in own instruction buffer These operations are necessary because the processor does not maintain instruction memory coherent with data memory Software is responsible for enforcing coherency of instruction caches and data memory Since instruction fetching may bypass the data cache changes made to items in the data cache may not be reflected in memory until after the instruction fetch completes The PowerPC architecture
134. the following bus clock cycle or for parity or ECC checked memory systems Note that DRTRY may not be implemented on other processors 8 4 4 3 Data Transfer Termination Due to a Bus Error The TEA signal indicates that a bus error occurred It may be asserted while DBB and or DRTRY for read operations is asserted Asserting TEA to the MPC603e terminates the transaction that is further assertions of TA and DRTRY are ignored and DBB is negated see Figure 8 12 Assertion of the TEA signal causes a machine check exception and possibly a checkstop condition within the MPC603e For more information see Section 4 5 2 Machine Check Exception 0x00200 Note also that the MPC603e does not implement a synchronous error capability for memory accesses This means that the exception instruction pointer does not point to the memory operation that caused the assertion of TEA but to the instruction about to be executed perhaps several instructions later However assertion of TEA does not invalidate data entering the GPR or the cache Additionally the corresponding address of the access that caused TEA to be asserted is not latched by the MPC603e To recover the exception handler must determine and remedy the cause of the Chapter 8 System Interface Operation For More information On This Product Go to www freescale com Freescale Semiconductor Inc Data Bus Tenure TEA or the MPC603e must be reset therefore this func
135. the point of completion the time needed to drain the completed store queue and the time waiting for a correct empty state so that a valid Chapter 4 Exceptions For More Information On This Product Go to www freescale com mor Freescale Semiconductor Inc Exception Definitions MSR IP may be saved For lower priority externally generated interrupts a delay may be incurred waiting for another interrupt generated while reaching a recoverable state to be serviced Further delays are possible for other types of exceptions depending on the number and type of instructions that must be completed before those exceptions may be serviced See Section 4 1 2 Summary of Front End Exception Handling to determine possible maximum latencies for different exceptions 4 5 Exception Definitions Table 4 8 shows all the types of exceptions that can occur with the MPC603e and the MSR bit settings when the processor transitions to supervisor mode The state of these bits prior to the exception is typically stored in SRR1 Table 4 8 MSR Setting Due to Exception Exception MSR Bit Type POW TGPR ILE EE PR FP ME FEO SE BE FE1 IP IR DR RI LE System reset 0 0 0 0 0 0 0 0 0 1 0 0 0 ILE Machine check 0 0 0 0 0 0 0 0 0 0 0 0 0 ILE DSI 0 0 0 0 0 0 0 0 0 0 0 0 ILE ISI 0 0 0 0 0 0 0 0 0 0 0 0 ILE External 0 0 0 0 0
136. the tlbInstrMiss sectionwith the following bdnzf 0 iml dec count br if cmp ne and if count not zero Replace the third line of the ceq1 segment in the tlbCeq0 section with the following bdnzf 0 ceql dec count br if cmp ne and if count not zero Replace the Implementation Note for Block Address Translation with The 603e BAT registers are not initialized by the hardware after the power up or reset sequence Consequently all valid bits in both instruction and data BAT areas must be explicitly cleared before setting any BAT area for the first time and before enabling translation Also note that software must avoid overlapping blocks while updating a BAT area or areas Even if translation is disabled multiple Appendix C Revision History For More Information On This Product Go to www freescale com e Semiconductor Inc F Revision Changes From narsescale Se 5 4 3 1 5 26 5 4 3 1 5 26 5 4 3 1 5 27 5 4 4 5 29 BAT area hits with the valid bits set can corrupt the remaining portion any bits except the valid bits of the BAT registers Thus multiple BAT hits with valid bits set are considered a programming error whether translation is enabled or disabled and can lead to unpredictable results if translation is enabled or if translation is disabled when translation is eventually enabled For the case of unused BATs if translation is to be enabled it is sufficient precaution to simply
137. through the use of two independent instruction and data block address translation IBAT and DBAT arrays of four entries each Effective addresses are compared simultaneously with all four entries in the BAT array during block translation In accordance with the PowerPC architecture if an effective address hits in both the TLB and BAT array the BAT translation takes priority The MPC603e has a selectable 32 or 64 bit data bus and a 32 bit address bus The MPC603e interface protocol allows multiple masters to compete for system resources through a central external arbiter The MPC603e provides a three state exclusive modified and invalid coherency protocol which is a compatible subset of a four state modified exclusive shared invalid MESI protocol This protocol operates coherently in systems that contain four state caches The MPC603e supports single beat and burst data transfers for memory accesses and supports memory mapped I O operations The MPC603e is fabricated using an advanced CMOS process technology and is fully compatible with TTL devices 1 1 1 Features This section describes the major features of the MPC603e noting where the PID6 603e and PID7t 603e implementations differ e High performance superscalar microprocessor As many as three instructions issued and retired per clock As many as five instructions in execution per clock Single cycle execution for most instructions Pipelined FPU for all single precision a
138. to hold the return address after branch and link instructions The LR is 32 bits wide in 32 bit implementations e Count register CTR The CTR is decremented and tested automatically as a result of branch and count instructions The CTR is 32 bits wide in 32 bit implementations e XER register The 32 bit XER contains the summary overflow bit integer carry bit overflow bit and a field specifying the number of bytes to be transferred by a Load String Word Indexed Iswx or Store String Word Indexed stswx instruction MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc specitic Information 1 3 1 9 2 Supervisor Level SPRs The MPC603e also contains SPRs that can be accessed only by supervisor level software These registers consist of the following The DSISR defines the cause of data access and alignment exceptions The data address register DAR holds the address of an access after an alignment or DSI exception Decrementer register DEC is a 32 bit decrementing counter that provides a mechanism for causing a decrementer exception after a programmable delay SDR1 specifies the page table format used in virtual to physical address translation for pages Note that physical address is referred to as real address in the architecture specification The machine status save restore register 0 SRRO is used for saving the address of the ins
139. to TGPRO TGPR3 respectively The TGPR bit is set when either an instruction TLB miss data TLB miss on load or data TLB miss on store exception is taken The TGPR bit is cleared by an rfi instruction 2 1 2 1 2 8 Replace Table 2 2 with the HIDO bits descriptions as follows Table 2 2 HIDO Bit Functions Bit Name Function EMCP Enable MCP The primary purpose of this bit is to mask out further machine check exceptions caused by assertion of MCP similar to how MSR EE can mask external interrupts 0 Masks MCP Asserting MCP does not generate a machine check exception or a checkstop 1 Asserting MCP causes checkstop if MSR ME 0 or a machine check exception if ME 1 Reserved EBA Enable disable 60x bus address parity checking 0 Disables address parity checking 1 Allows a address parity error to cause a checkstop if MSR ME 0 or a machine check exception if MSR ME 1 EBA and EBD allow the processor to operate with memory subsystems that do not generate parity EBD Enable 60x bus data parity checking 0 Disables data parity checking 1 Allows a data parity error to cause a checkstop if MSR ME 0 or a machine check exception if MSR ME 1 EBA and EBD allow the processor to operate with memory subsystems that do not generate parity MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semicond uct
140. translation is enabled MSR IR 1 or MSR DR 1 In the MPC603e the referenced and changed bits are updated as follows e For TLB hits the C bit is updated according to Table 5 7 e For TLB misses when a table search operation is in progress to locate a PTE the R and C bits are updated set if required to reflect the status of the page based on this access Table 5 7 Table Search Operations to Update History Bits TLB Hit Case R and C Bits in e TLB Entry Processor Action 00 Combination does not occur 01 Combination does not occur 10 Read No special action Write Table search operation required to update C Causes a data TLB miss on store exception 11 No special action for read or write Table 5 7 shows that the status of the C bit in the TLB entry in the case of a TLB hit is what causes the processor to update the C bit in the PTE the R bit is assumed to be set in the page tables if there is a TLB hit Therefore when software clears the R and C bits in Chapter 5 Memory Management For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Segment Model the page tables in memory it must invalidate the TLB entries associated with the pages whose referenced and changed bits were cleared The MPC603e causes the R bit to be set for the execution of the debt or debtst instruction to that page by causing a TLB miss exception to load the TLB ent
141. user s manual is to define the functionality of the MPC603e microprocessor for use by software and hardware developers It is important to note that this book is to be used with the PowerPC Microprocessor Family The Programming Environments referred to as the Programming Environments Manual Contact your sales representative to obtain a copy Because the PowerPC architecture is designed to be flexible to support a broad range of processors the Programming Environments Manual provides a general description of features common to PowerPC processors and indicates those features that are optional or that may be implemented differently in the design of each processor This document describes in detail the MPC603e features not defined by the architecture This document and the Programming Environments Manual distinguish between the three levels or programming environments of the PowerPC architecture which are as follows e User instruction set architecture UISA The UISA defines the architecture level to which user level software should conform The UISA defines the base user level instruction set user level registers data types memory conventions and the memory and programming models seen by application programmers e Virtual environment architecture VEA The VEA which is the smallest component of the PowerPC architecture defines additional user level functionality that falls outside typical user level software requirements The VEA
142. was a flush or clean request If the snooped transaction was a kill request ARTRY will not be asserted e Snoop attempt during the last TA of a cache line fill In No DRTRY mode during the cycle that the last TA is asserted to the MPC603e on a cache line fill the tag is being written to its new state by the MPC603e and is not accessible This will result in a collision being signaled by asserting ARTRY With DRTRY enabled the cache tags are inaccessible to a snoop operation one cycle after the last TA Chapter 3 Instruction and Data Cache Operation For More Information On This Product Go to www freescale com __ Freescale Semiconductor Inc Cache Control Instructions e Snoop hit after the first TA of a burst load operation After the first TA of a burst load operation the data tags are committed to being written snoop operations cannot be serviced until the load completes thereby causing the assertion of ARTRY e Snoop hits to line in the cast out buffer The MPC603e cast out buffer is kept coherent with main memory and snoop operations that hit in the cast out buffer will cause the assertion of ARTRY e Snoop attempt during cycles that dcbz instruction or load or store operation is updating the tag During the execution of a debz instruction or during a load or store operation that requires a cache line cast out the cache tags will be inaccessible during the first and last cycle of the operation
143. 0 0 29 30 31 Figure 2 8 Instruction Address Breakpoint Register IABR The bits in the IABR are defined in Table 2 8 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operand Conventions Table 2 8 Instruction Address Breakpoint Register Bit Settings Bits Description 0 29 Word address to be compared 30 IABR enabled Setting this bit indicates that the IABR exception is enabled 31 Reserved 2 2 Operand Conventions This section describes the operand conventions as they are represented in two levels of the PowerPC architecture It also provides detailed descriptions of conventions used for storing values in registers and memory accessing the MPC603e registers and representation of data in these registers 2 2 1 Floating Point Execution Models UISA The IEEE 754 standard includes 64 and 32 bit arithmetic The standard requires that single precision arithmetic be provided for single precision operands The standard permits double precision arithmetic instructions to have either or both single precision or double precision operands but states that single precision arithmetic instructions should not accept double precision operands The PowerPC UISA follows these guidelines e Double precision arithmetic instructions may have single precision operands but always produce double precision result
144. 0 r21 0 r22 0 r23 0 r23 r23 0 r0 x0 x05f4 r0 x05f0 r0 x05ec r0 x05e8 r0 x05e4 r0 ic registers r23 0 Oxff r23 0 r22 0 r21 0 r20 0 x05e4 r0 r23 x05e8 r0 x05ec r0 x05f0 r0 x05f4 r0 r0 0x05fc r0 HE Hk ee A A AA I AA I AA A I A I I I Hk MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix A PowerPC Instruction Set Listings This appendix lists the MPC603e microprocessor s instruction set as well as the additional PowerPC instructions not implemented in the MPC603e Instructions are sorted by mnemonic opcode function and form Also included is a quick reference table that contains general information such as the architecture level privilege level and form and indicates if the instruction is 64 bit and optional Note that split fields representing the concatenation of sequences from left to right are shown in lowercase For more information refer to Chapter 8 Instruction Set in the Programming Environments Manual The following key applies to the tables in this appendix Key Reserved Bits Instruction Not Implemented in the MPC603e A1 Instructions Sorted by Mnemonic Table A 1 lists the instructions implemented in the PowerPC architecture in alphabetical order by mnemonic Table A 1 Complete Instruction List Sorted by Mnemonic N
145. 0 11 E Reserved 12 KEY TLB miss protection key 13 I D Instruction data TLB miss 0 DTLB miss 1 ITLB miss 14 WAY Bit 14 indicates which TLB associativity set should be replaced 0 Seto 1 Set1 15 S L Store load protection instruction 0 Load miss 1 Store miss 16 31 MSR 16 31 Copy of MSR bits 16 31 Note that in some implementations every instruction fetch when MSR IR 1 and every instruction execution requiring address translation when MSR DR 1 may modify SRR1 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Exception Processing 4 2 1 2 MSR Bit Settings The MSR is shown in Figure 4 3 When an exception occurs MSR bits as described in Table 4 6 are altered as determined by the exception TGPR POW Reserved 0000000000000 ILE EE PR FP ME FE0 SE BE FE1 O IP IR DR 0 O RI LE 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Figure 4 3 Machine State Register MSR Table 4 6 shows the bit definitions for the MSR Full function reserved bits are saved in SRR1 when an exception occurs partial function reserved bits are not saved Table 4 6 MSR Bit Settings Name Description Reserved Full function Reserved Partial function Reserved Full function 10 12 Reserved Partial function
146. 0 18 Re 59 D A B 00000 18 Re 63 D A B C 29 Rc 59 D A B C 29 Rc 63 D A B C 28 Rc 59 D A B C 28 Rc 63 D A 00000 C 25 Rc 59 D A 00000 C 25 Rc 63 D A B C 31 Rc 59 D A B C 31 Rc 63 D A B C 30 Rc 59 D A B C 30 Rc 59 D 00000 B 00000 24 Rc 63 D 00000 B 00000 26 Rc 63 D A B C 23 Rc 63 D 00000 B 00000 22 Rc 59 D 00000 B 00000 22 Rc 63 D A B 00000 20 Rc 59 D A B 00000 20 Rc 1 Optional in the PowerPC architecture Table A 43 M Form 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OPCD S A SH MB ME Rc OPCD S A B MB ME Rc Specific Instructions 20 A SH MB ME Rc 21 A SH MB ME Rc 23 A B MB ME Rc riwnmx MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Table A 44 MD Form Inc PSructions Sorted by Form Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OPCD S A sh mb XO sh Rc OPCD S A sh me XO sh Rc Specific Instructions ridicx 1 30 S A sh mb 2 sh Rce rldiclx 30 S A sh mb 0 sh Re ridicrx 30 S A sh me 1 sh Rc ridimix 30 S A sh mb 3 sh Re 1 64 bit instruction Table A 45 MDS Form Name 0 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OPCD A B mb XO Rc OPCD A B me XO Rc Specific Instructions ridelx 1 30 A mb 8 Re riderx 30 A me Re
147. 0 Rc andex 011111 S A B 0000111100 Rc td 011111 TO A B 0001000100 0 mulhdx 011111 D A B 0 0001001001 Re mulhwx 011111 D A B 0 0001001011 Re mfmsr 011111 D 00000 00000 0001010011 0 Idarx 011111 D A B 0001010100 0 dcbf 011111 00000 A B 0001010110 0 Ibzx 011111 A B 0001010111 0 negx 011111 A 00000 JOE 0001101000 Re Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com Instructions Sorted by ophngescale Semiconductor Inc Table A 2 Complete Instruction List Sorted by Opcode continued Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Ibzux 011111 D A B 0001110111 0 norx 011111 S A B 0001111100 Rc subfex 011111 D A B OE 0010001000 Rc addex 011111 D A B OE 0010001010 Re mtcrf 011111 S 0 CRM 0 0010010000 0 mtmsr 011111 S 00000 00000 0010010010 0 stdx 011111 S A B 0010010101 0 stwex 011111 S A B 0010010110 1 stwx 011111 S A B 0010010111 0 stdux 011111 S A B 0010110101 0 stwux 011111 S A B 0010110111 0 subfzex 011111 D A 00000 JOE 0011001000 Re addzex 011111 D A 00000 JOE 0011001010 Re mtsr 011111 S 0 SR 00000 0011010010 0 stdcex 011111 S A B 0011010110 1 stbx 011111 S A B 0011010111 0 subfmex 011111 D A 00000 JOE 0011101000 Rc mulld 011111 D A B OE 0011101001 R
148. 0000 50 0 1 Supervisor level instruction Name mfspr 1 mftb mtcrf mtspr 1 Table A 38 XFX Form 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OPCD spr XO 0 OPCD D 0 CRM XO 0 OPCD S spr XO 0 OPCD D tbr XO 0 Specific Instructions 31 D spr 339 0 31 D tbr 371 0 31 S 0 CRM 144 0 31 D spr 467 0 1 Supervisor and user level instruction Name mtfstx Name sradix 1 Table A 39 XFL Form 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OPCD 0 FM 0 B XO Re Specific Instructions 63 0 FM 0 B 711 Re Table A 40 XS Form 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OPCD S A sh XO sh Rc Specific Instructions 31 S A sh 413 sh Rc 1 64 bit instruction MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Name addx addcx addex addmex addzex divdx divdux divwx divwux mulhdx mulhdux mulhwx mulhwux mulldx mullwx negx subfx subfcx subfex subfmex subfzex Freescale Semiconductor Table A 41 XO Form 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Inc PSructions Sorted by Form OPCD D A
149. 0000 B 659 0 mtsr 31 S 0 SR 00000 210 0 mtsrin 1 31 S 00000 B 242 0 1 Supervisor level instruction Table A 29 Lookaside Buffer Management Instructions Name 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 slbia 1 2 3 31 00000 00000 00000 498 0 slbie 1 2 3 31 00000 00000 B 434 0 tlbia 1 3 31 00000 00000 00000 370 0 tlbie 1 3 31 00000 00000 B 306 0 tlbld 1 4 31 00000 00000 B 978 0 tlbli 14 31 00000 00000 B 1010 0 tlbsync 1 3 31 00000 00000 00000 566 0 1 Supervisor level instruction 2 64 bit instruction 3 Optional in the PowerPC architecture 4 MPC603e implementation specific instruction Table A 30 External Control Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 eciwx 31 D A B 310 0 ecowx 31 S A B 438 0 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING tions SE AA Instructions Sorted by Form Table A 31 through Table A 45 list the PowerPC instructions grouped by form Table A 31 l Form Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OPCD LI AA LK Specific Instruction bx 18 LI AA LK Table A 32 B Form Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 2
150. 01 Re divwux 011111 D A B OE 0111001011 Re mtspr4 011111 S spr 0111010011 0 debi 011111 00000 A B 0111010110 0 nandx 011111 S A B 0111011100 Rc divdx 011111 A B OE 0111101001 Re divwwx 011111 D A B OE 0111101011 Re slbia 23 011111 00000 00000 00000 0111110010 0 merxr 011111 crfD 00 00000 00000 1000000000 0 Iswx gt 011111 D A B 1000010101 0 wirs 011111 D A B 1000010110 0 Ifsx 011111 D A B 1000010111 0 srwx 011111 S A B 1000011000 Rc srdax 011111 S A B 1000011011 Re tlbsyne 23 011111 00000 00000 00000 1000110110 0 Ifsux 011111 D A B 1000110111 0 mer 011111 D 0 SR 00000 1001010011 0 Iswi5 011111 D A NB 1001010101 0 sync 011111 00000 00000 00000 1001010110 0 Ifdx 011111 D A B 1001010111 0 Ifdux 011111 D A B 1001110111 0 mfsrin 0111141 D 00000 B 1010010011 0 stswx 011111 S A B 1010010101 0 stwbrx 011111 S A B 1010010110 0 stfsx 011111 S A B 1010010111 0 stfsux 011111 S A B 1010110111 0 stswi5 011111 S A NB 1011010101 0 stfdx 011111 S A B 1011010111 0 stfdux 011111 S A 1011110111 0 Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com Fr Instructions Sorted by Opeous escale Semiconductor Inc Table A 2 Complete Instruction List Sorted by Opcode continued Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19
151. 010 S A UIMM 011011 S A UIMM MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Sorted by Opcode Table A 2 Complete Instruction List Sorted by Opcode continued Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 andi 011100 S A UIMM andis 011101 S A UIMM ridicix 011110 S A sh mb 000 ebe ridicrx 011110 S A sh me 001 sh Rc rldicx 011110 S A sh mb 010 ebe rldimix 011110 S A sh mb 011 ebe ridclix 011110 S A B mb 01000 pe riderx 011110 S A B me 01001 Be cmp 011111 crfD O L A B 0000000000 0 tw 011111 TO A B 0000000100 0 subfex 011111 D A B OE 0000001000 Re mulhdux 0111141 D A B 0 0000001001 Re addex 011111 D A B OE 0000001010 Rc mulhwux 011111 D A B 0 0000001011 Re mfcr 011111 D 00000 00000 0000010011 0 wars 011111 D A B 0000010100 0 ldax 011111 D A B 0000010101 0 Iwzx 011111 D A B 0000010111 0 slwx 011111 S A B 0000011000 Rc cntlzwx 011111 S A 00000 0000011010 Rc sldax 011111 S A B 0000011011 Re andx 011111 S A B 0000011100 Rc cmpl 011111 crfD O L A B 0000100000 0 subfx 011111 A B OE 0000101000 Re ldux 011111 D A B 0000110101 0 debst 011111 00000 A B 0000110110 0 lwzux 011111 D A B 0000110111 0 cntlzdx 011111 A 00000 000011101
152. 03e contains the following execution units that operate independently and in parallel Branch processing unit BPU 32 bit integer unit IU executes all integer instructions 64 bit floating point unit FPU Load store unit LSU System register unit SRU The MPC603e can retire two instructions on every clock cycle In general the MPC603e processes instructions in four stages fetch decode dispatch execute and complete as shown in Figure 6 2 Note that the example of a pipelined execution unit in Figure 6 1 is similar to the three stage FPU pipeline in Figure 6 2 The instruction pipeline stages are described as follows The instruction fetch stage includes the clock cycles necessary to request instructions from the memory system and the time the memory system takes to respond to the request Instruction fetch timing depends on many variables such as whether the instruction is in the branch target instruction cache or in the on chip instruction cache Instruction fetch timing increases when it is necessary to fetch instructions from system memory The variables that affect fetch timing include the processor to bus clock ratio the amount of bus traffic and whether any cache coherency operations are required MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING ction Timing Overview Fetch Maximum Two lInstruction Fetch Per Glock Cycle Maxim
153. 03e is in sleep mode the time base contents must be updated from an external time base following sleep mode if accurate time of day maintenance is required Before entering sleep mode the MPC603e asserts QREQ to indicate that it is ready to disable bus snooping When the system has ensured that snooping is no longer necessary the system logic allows the MPC603e to enter sleep mode by asserting QACK for the duration of the sleep mode period Sleep mode is characterized by the following features e All functional units disabled including bus snooping and time base e All nonessential input receivers disabled e Internal clock regenerators disabled e PLL and SYSCLK can be disabled To enter sleep mode the following conditions must occur e Set sleep bit HIDO 10 1 MSR POW is set e MPC603e asserts QREQ e System logic asserts QACK e MPC603e enters sleep mode after several processor clocks To return to full power mode the following conditions must occur e Assert INT MCP or SMI e Hard reset or soft reset To return to full power mode after PLL and SYSCLK are disabled in sleep mode the following conditions must occur e Enable SYSCLK e Reconfigure PLL into desired processor clock mode e System logic waits for PLL startup and relock time 100 usec e System logic asserts one of the sleep recovery signals for example INT or SMI Chapter 9 Power Management For More Information On This Product Go to www freescale com Ex
154. 10 10010 HASH1 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING uction PE Table 2 40 Implementation Specific SPR Encodings mfspr continued SPR Register Name Decimal spr 5 9 spr 0 4 979 11110 10011 HASH2 980 11110 10100 IMISS 981 11110 10101 ICMP 982 11110 10110 RPA 1008 11111 10000 HIDO 1009 11111 10001 HID1 1010 11111 10010 IABR 1 Note that the order of the two 5 bit halves of the SPR number is reversed compared with actual instruction coding For mtspr and mfspr instructions the SPR number coded in assembly language does not appear directly as a 10 bit binary number in the instruction The number coded is split into two 5 bit halves that are reversed in the instruction with the high order 5 bits appearing in bits 16 20 of the instruction and the low order 5 bits in bits 11 15 Implementation Note The MPC603e ignores the extended opcode differences between mftb and mfspr by ignoring TB 25 and treating both instructions identically 2 3 6 3 Memory Control Instructions OEA This section describes memory control instructions which include the following types e Cache management instructions e Segment register manipulation instructions e Translation lookaside buffer management instructions 2 3 6 3 1 Supervisor Level Cache Management Instruction The supervisor leve
155. 19 Condition Register OR sciosg ceca seg ule Sei Saas eae ees 1 19 Floating Point Status and Control Register FPSCR esseere 1 19 Machine State Register MSR aeetieggegge desse ee deeg 1 20 Segment Registers SRS pocadscslatsnziaccecssecheuaseyonttecaaesabarauasudeasedtoeaseueshbonsaeaas 1 20 Special Purpose Registers SPRS sesssssesssesssssesssressessseesseresseessseesseesse 1 20 BE RE 1 20 SUPERVISOM ER 1 21 Instruction Set and Addressing Modes A 1 22 PowerPC Instruction Set and Addressing Modes ss nsseesseesseessereseeeeseee 1 22 Implementation Specific Instruction Set 1 24 Cache Implementations netin ere eege Ed eege 1 24 PowerPC Cache Characteristics eeeeeseeseeeeeeseeseeseessesreeseesrrsrresresseseresreses 1 24 Implementation Specific Cache Implementation sesseeeeeereeeeereesererereese 1 24 Eet Model Euren AGE aa GRIN eae i aaa 1 26 PowerPC Exception Modelis ienen niniiiee e aiii 1 26 Implementation Specific Exception Model 1 28 Memory Mana Sement e iis coscstcsdicacsivsaviaaisegeadeaspavceve teepenterveraceusdeeasensporaateveds 1 30 PowerPC Memory Management 1 30 Implementation Specific Memory Management 1 31 WS CUCL nn Kit 1 32 Syst m Eeer 1 33 Memory EE 1 34 LOM Al Se actcaccsute ties tind atlanta EE 1 35 Signal Configuration esie e ANE eege 1 36 Chapter 2 Programming Model Register Set 2283 ati tected rete et EE 2 1 POWEEPG TEE Eeer Mate igen alas 2 2 Implementation Specific Regis
156. 2 m stmw 47 LSU ae ifs 48 peu SS Ifsu 49 LSU S ifd 50 ate zl ou d Eu eH stfs 52 i e ai stfsu 53 i af stfd 54 LSU g stfdu 55 me Notes Cycle times marked with amp require a variable number of cycles due to serialization Cycle times marked with a specify hit and miss times for cache management instructions that require conditional bus activity Cycle times marked with a specify cycles of total latency and throughput Load and store multiple and string instruction cycles are shown as a fixed number of cycles plus a variable number of cycles where n is the number of words accessed by the instruction Chapter 6 Instruction Timing For More information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Latency Summary MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 7 Signal Descriptions This chapter describes the MPC603e microprocessor s external signals It contains a concise description of individual signals showing behavior when the signal is asserted and negated and when the signal is an input and an output NOTE A bar over a signal name indicates that the signal is active low for example ARTRY address retry and TS transfer start Active low signals are referred to as asserted active when they are low and negated when they a
157. 2 4 31 00000 00000 00000 370 0 tlbie 2 4 31 00000 00000 B 306 0 tlbld 2 5 31 00000 00000 B 978 0 tlbli 25 31 00000 00000 B 1010 0 tlbsync 4 31 00000 00000 00000 566 0 tw 31 TO A B 4 0 xorx 31 S A B 316 Rc 1 64 bit instruction 2 Supervisor and user level instruction 3 Load and store string or multiple instruction 4 Optional in the PowerPC architecture 5 MPC603e implementation specific instruction Table A 37 XL Form Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OPCD BO BI 00000 XO LK OPCD crbD crbA crbB XO 0 OPCD crfD 00 crfS 00 00000 XO 0 OPCD 00000 00000 00000 XO 0 Specific Instructions bectrx 19 BO BI 00000 528 LK belrx 19 BO BI 00000 16 LK crand 19 crbD crbA crbB 257 0 crandc 19 crbD crbA crbB 129 0 creqv 19 crbD crbA crbB 289 0 crnand 19 crbD crbA crbB 225 0 crnor 19 crbD crbA crbB 33 0 cror 19 crbD crbA crbB 449 0 Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com Name crorc crxor isync mert rfi 1 F Instructions Sorted by Form reescale Semiconductor Inc Table A 37 XL Form continued 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 19 crbD crbA crbB 417 0 19 crbD crbA crbB 193 0 19 00000 00000 00000 150 0 19 crfD 00 crfS 00 00000 0 0 19 00000 00000 0
158. 20 21 22 23 24 25 26 27 28 29 30 31 Ihbrx 011111 D A B 1100010110 0 srawx 011111 S A B 1100011000 Rc sradx 011111 S A B 1100011010 Rc srawix 011111 S A SH 1100111000 Rc eieio 011111 00000 00000 00000 1101010110 0 sthbrx 011111 S A B 1110010110 0 extshx 011111 S A 00000 1110011010 Rc extsbx 011111 S A 00000 1110111010 Rc tlbld 011111 00000 00000 B 1111010010 0 icbi 011111 00000 A B 1111010110 0 stfiwx 011111 S A B 1111010111 0 extsw 011111 S A 00000 1111011010 Rc tlblid6 011111 00000 00000 B 1111110010 0 dcbz 011111 00000 A B 1111110110 0 Wel 100000 D A d lwzu 100001 D A d Ibz 100010 D A d Ibzu 100011 D A d stw 100100 S A d stwu 100101 S A d stb 100110 S A d stbu 100111 S A d Ihz 101000 D A d Ihzu 101001 D A d Ilha 101010 D A d bau 101011 D A d sth 101100 S A d sthu 101101 S A d Imw gt 101110 D A d stmw5 101111 S A d Wel 110000 D A d Weu 110001 D A d lfd 110010 D A d lfdu 110011 D A d stfs 110100 S A d stfsu 110101 S A d stfd 110110 S A d MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Table A 2 Complete Instruction List Sorted by Opcode continued Name stfdu Id Idu Iwa fdivsx fsubsx faddsx fsqrtsx fresx 3 fmulsx fmsubsx fmaddsx fnmsubsx fnmaddsx std stdu 1 fcmpu frspx fctiwx fctiwzx fdivx fsubx faddx fsqrtx 8 fselx 3 fmulx frsqrtex 2 fmsubx fmad
159. 22 Memory Performance Considerations eeceeeeeseecseceseeeeeeesseeseaeenseeeeeeeenees 6 22 Copy Back E 6 23 Write Thro gh EE 6 23 Cache Inhibited EE 6 23 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Paragraph Number 6 6 6 6 1 6 6 1 1 6 6 1 2 6 6 1 3 6 7 7 1 T2 7 2 1 7 2 1 1 E 7 2 1 3 poe ee 7 2 1 3 2 1 2 2 7 2 2 1 Tad 7 2 2 1 2 7 2 3 EE 7 2 3 1 1 1 23 12 123 2 7 2 3 2 1 EE 7 2 3 3 71 2 4 7 2 4 1 7 2 4 1 1 71 2 4 1 2 1 2 4 2 7 2 4 3 7 2 4 3 1 1 2 4 3 2 7 2 4 4 7 2 4 5 7 2 4 6 7 2 4 1 Freescale Semiconductor Inc Contents Page Title Number Instruction Scheduling EE ENT 6 24 Branch Dispatch and Completion Unit Resource Requirements 6 25 Branch Resolution Resource Requirements c cceeescecseceecseeeeeeteeeeeaes 6 25 Dispatch Unit Resource Regumrements 6 25 Completion Unit Resource Requirements eecceesceeesseceeeteeeesteeeeaees 6 26 Instruction Latency Summary zisisscpevasviseceesaseaeiatesdesndeasyadeaests dvensaaveraceesdacetonsec 6 26 Chapter 7 Signal Descriptions Signal COMP UTALOM sgs cievsscessaveuesaceivaeeesaaaeesadedageadaseaeaasisdeendeaeoedesealedeedvaasedaceasens 7 2 e ENK eene EE 7 2 Address Bus Arbitration Sigmals cccccccssccccssccecssccecneccecssacecssccecneceesceeenaes 7 2 Bus Request BRJ Output 2 casscsssensettasievesiesendursrsdaotaistense rata deeene
160. 232 of physical memory referred to as real memory in the architecture specification for instruction and data The MMUs also control access privileges for these spaces on block and page granularities Referenced and changed status is maintained by the processor for each page to assist implementation of a demand paged virtual memory system A key bit is implemented to provide information about memory protection violations prior to page table search operations The LSU calculates effective addresses EAs for data loads and stores performs data alignment to and from cache memory and provides the sequencing for load and store string and multiple word instructions The instruction unit calculates effective addresses for instruction fetching After an EA is generated its higher order bits are translated by the appropriate MMU into physical address bits The lower order EA bits are the same on the physical address and form the index into the four way set associative tag array After translating the address the MMU passes the higher order physical address bits to the cache and the cache lookup completes For caching inhibited accesses or accesses that miss in the cache the Chapter 1 Overview For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Overview untranslated lower order address bits are concatenated with the translated higher order address bits the resulting 32 bit physical address is then used
161. 3 primary opcodes 30 and 62 are illegal for all 32 bit implementations but as 64 bit opcodes they have some unused extended opcodes An instruction consisting entirely of zeros is guaranteed to be an illegal instruction This increases the probability that an attempt to execute data or uninitialized memory invokes the system illegal instruction error handler a program exception Note that if only the primary opcode consists of all zeros the instruction is considered a reserved instruction This is further described in Section 2 3 1 4 Reserved Instruction Class An attempt to execute an illegal instruction invokes the illegal instruction error handler a program exception but has no other effect Section 4 5 7 Program Exception 0x00700 describes illegal and invalid instruction exceptions MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor In ten Serums Except for an instruction consisting entirely of binary zeros illegal instructions are available for further additions to the PowerPC architecture 2 3 1 4 Reserved Instruction Class Reserved instructions are allocated to specific implementation dependent purposes not defined by the PowerPC architecture An attempt to execute an unimplemented reserved instruction invokes the illegal instruction error handler a program exception See Section 4 5 7 Program Exception 0x00700 for
162. 3 are mapped to TGPRO TGPR3 respectively TGPR is set when an instruction TLB miss data TLB miss on load or data TLB miss on store exception is taken TGPR is cleared by an rfi instruction 0 Normal operation 1 TGPR mode GPRO GPR3 are remapped to TGPRO TGPR3 for use by TLB miss routines Memory management registers Block address translation BAT registers The MPC603e includes eight block address translation registers BATs four pairs of instruction BATs IBATOU IBAT3U and IBATOL IBAT3L and four pairs of data BATs DBATOU DBAT3U and DBATOL DBAT3 L Figure 2 1 lists SPR numbers for the BAT registers SDR1 The SDR1 register specifies the page table base address used in virtual to physical address translation Note that physical address is referred to as real address in the architecture specification Segment registers SRs The PowerPC OEA defines sixteen 32 bit segment registers SRO SR15 The fields in the segment register are interpreted differently depending on the value of bit 0 Exception handling registers Data address register DAR After a data access or an alignment exception the DAR is set to the effective address generated by the faulting instruction SPRGO SPRG3 The SPRGO SPRG3 registers are provided for operating system use DSISR The DSISR defines the cause of data access and alignment exceptions Machine status save restore register 0 SRRO The SRRO is used to save machine status
163. 4 14 summary 2 21 system call 4 29 system management interrupt 4 34 trace exception 4 29 Execution synchronization 2 21 Execution units 1 9 External control instructions 2 43 8 18 A 24 F Features list 1 3 Finish cycle definition 6 2 Floating point model FEO FE1 bits 4 13 FP arithmetic instructions 2 26 A 17 FP compare instructions 2 28 A 18 FP execution models 2 13 FP load instructions 2 34 A 21 FP move instructions 2 29 A 22 FP multiply add instructions 2 27 A 18 FP rounding conversion instructions 2 28 A 18 FP store instructions 2 35 A 21 FP unavailable exception 4 28 FPSCR instructions 2 28 A 18 Floating point unit execution timing 6 21 latency FP instructions 6 30 overview 1 10 Flow control instructions branch instruction address calculation 2 36 branch instructions 2 37 condition register logical 2 37 Flush block operation 3 20 FPRO FPR31 2 2 FPSCR instructions 2 28 A 18 G GBL signal 7 14 GPRO GPR31 2 2 Guarded memory bit G bit cache interactions 3 10 G bit setting 3 13 H HASH1 and HASH2 registers 5 34 Hashing functions primary PTEG 5 30 secondary PTEG 5 31 HIDO hardware implementation dependent 0 registers nap bit 9 4 HIDO register DCFI DCE DLOCK bits 3 6 doze bit 9 4 DPM enable bit 9 3 ICFI ICE ILOCK bits 3 4 PID7t specific bits 1 19 3 23 HID1 register bit settings 2 10 PLL configuration 2 10 7 30 HRESET signal 7 25 I TEEE
164. 5 Branch and Flow Control Instructons 2 36 Branch Instruction Address Calculaton ccc ceeeecessecsneceseeeeeeeeneees 2 36 Branch InstructiOms e Zusteeug deed feed dd 2 37 Condition Register Logical Instrucnons cece eeseeeseceseeeeeeeeeeenaeees 2 37 eege 5556 a5 9 203 6 A wou A E A A seceded 2 38 Processor Control Instructions icc cso ace sd eed 2 38 Move To From Condition Register Instructons eeeeeeeereeereees 2 38 Memory Synchronization Instructions UISA 0 eee eeeeeseeeeeeneeeeeees 2 38 PowerPC VEA TS tO Ctl OTIS ics soca Eegeregie 2 40 Processor Control Instruectons eee eesceseceseeeeseecssecsseeeseeesseecsaeesseeesees 2 40 Memory Synchronization Instructions VEA 0 0 eee eeeeeeeeeeseeeseeenteeeeeee 2 41 Memory Control Instructions VEA ou cee eeceeeneeeseeceneeeeeeeeseecnaeenseeesees 2 41 External Control Dette eege ed ees 2 43 PowerPC ECHO 2 43 System Linkage INStructiOns csscctesscissascecedeassenacdesncceetessacdacestesadeetavcanadeds 2 43 Processor Control Instructions OEA 00 eee eeceeeseceeeeeeeeeeseecnnecneensneeenees 2 44 Move To From Machine State Register Instrucpons 2 44 Move To From Special Purpose Register Instructtong eee 2 44 Memory Control Instructions OEA eee eeeeeeeeeseeceseeeeeeeeseecnaecnseensees 2 45 Supervisor Level Cache Management Instruction eee eeeeeeeeeereees 2 45 Segment Register Manipulation Instructions 2 0 0 eeeeeeeeeereeeeeeeees 2 46 Translation Lookaside Buffer Management
165. 5 S A d stmw 47 S A d stw 36 S A d stwu 37 S A d MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Name subfic tdi twi xori xoris Freescale Semiconductor Table A 34 D Form continued Inc PSructions Sorted by Form 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 08 D A SIMM 02 TO A SIMM 03 TO A SIMM 26 S A UIMM 27 S A UIMM 1 Load and store string or multiple instruction 2 64 bit instruction Name Id 1 Idu Iwa std stdu Table A 35 DS Form 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 64 bit instruction Name OPCD D A ds XO OPCD S A ds XO Specific Instructions 58 D A ds 0 58 D A ds 1 58 D A ds 2 62 S A ds 0 62 S A ds 1 Table A 36 X Form 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OPCD D A B XO 0 OPCD D A NB XO 0 OPCD D 00000 B XO 0 OPCD D 00000 00000 XO 0 OPCD D 0 SR 00000 XO 0 OPCD S A B XO Re OPCD S A B XO 1 OPCD S A B XO 0 OPCD S A NB XO 0 OPCD S A 00000 XO Rc OPCD S 00000 B XO 0 OPCD S 00000 00000 XO 0 OPCD S 0 SR 00000 XO 0 Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com Name andx andcx cm
166. 64 entry two way set associative ITLB and DTLB Four entry data and instruction BAT arrays providing 128 Kbyte to 256 Mbyte blocks Software table search operations and updates supported through fast trap mechanism 52 bit virtual address 32 bit physical address e Facilities for enhanced system performance A 32 or 64 bit split transaction external data bus with burst transfers Support for one level address pipelining and out of order bus transactions Hardware support for misaligned little endian accesses PID7t 603e e Integrated power management Low power 2 5 volt and 3 3 volt designs Internal processor bus clock multiplier ratios as follows 1 1 1 5 1 2 1 2 5 1 3 1 3 5 1 and 4 1 PID6 603e 2 1 2 5 1 3 1 3 5 1 4 1 4 5 1 5 1 5 5 1 and 6 1 PID7t 603e Three power saving modes doze nap and sleep Automatic dynamic power reduction when internal functional units are idle e In system testability and debugging features through JTAG boundary scan capability MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc i Overview Features specific to the PID7t 603e follow Enhancements to the register set The PID7t 603e adds two HIDO bits The address bus enable ABE bit HIDO 28 gives the PID7t 603e microprocessor the ability to broadcast debf debi and dcbst onto the 60x bus Th
167. 7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 faddx 63 D A B 00000 21 Re faddsx 59 D A B 00000 21 Rc fdivx 63 D A B 00000 18 Rc fdivsx 59 D A B 00000 18 Rc fmulx 63 D A 00000 C 25 Rc fmulsx 59 D A 00000 C 25 Rc fresx 59 D 00000 B 00000 24 Re frsqrtex 63 D 00000 B 00000 26 Re fsubx 63 D A B 00000 20 Re fsubsx 59 D A B 00000 20 Re fselx 1 63 D A B C 23 Rc fsqrtx 63 D 00000 B 00000 22 Re fsqrtsx 59 D 00000 B 00000 22 Re 1 Optional in the PowerPC architecture Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com Instructions Grouped by Freescale Semiconductor Inc Table A 9 Floating Point Multiply Add Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fmaddx 63 D A B C 29 Rc fmaddsx 59 D A B C 29 Rc fmsubx 63 D A B C 28 Rc fmsubsx 59 D A B C 28 Rc fnmaddx 63 D A B C 31 Rc fnmaddsx 59 D A B C 31 Rc fnmsubx 63 D A B C 30 Rc fnmsubsx 59 D A B C 30 Rc Table A 10 Floating Point Rounding and Conversion Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fcfidx 63 00000 B 846 Re fctidx 63 D 00000 B 814 Re fctidzx 63 D 00000 B 815 Rc fctiwx 63 D 00000 B 14 Re fctiwzx 63 D 00000 B 15 Re frspx 63 D 00000 B 12 Re 1 64 bit instruction Table A 11 Floating Point Compare Instr
168. 7 28 29 30 31 mffsx 63 D 00000 00000 583 Re mfmsr 2 31 D 00000 00000 83 0 mfsr 2 31 D 0 SR 00000 595 0 mfsrin 2 31 D 00000 B 659 0 mtfsb0x 63 crbD 00000 00000 70 Rc mtfsb1x 63 er 00000 00000 38 Rc mtfsfix 63 crbD 00 00000 IMM 134 Re mtmsr 2 31 S 00000 00000 146 0 mtsr 2 31 S 0 SR 00000 210 0 mtsrin 2 31 S 00000 B 242 0 nandx 31 S A B 476 Rc norx 31 S A B 124 Rc orx 31 S A B 444 Rc orcx 31 S A B 412 Rc slbia 1 2 4 31 00000 00000 00000 498 0 slbie 1 2 4 31 00000 00000 B 434 0 sldx 31 S B 27 Rc slwx 31 S A B 24 Rc sradx 31 S A B 794 Rc srawx 31 S A B 792 Rc srawix 31 S A SH 824 Rc srdx 31 S A B 539 Rc srwx 31 S A B 536 Rc stbux 31 S A B 247 0 stbx 31 S A B 215 0 stdex 31 S A B 214 1 stdux 31 S A B 181 0 stdx 31 S A B 149 0 stfdux 31 S A B 759 0 stfdx 31 S A B 727 0 stfiwx 4 31 S A B 983 0 stfsux 31 S A B 695 0 stfsx 31 S A B 663 0 sthbrx 31 S A B 918 0 sthux 31 S A B 439 0 sthx 31 S A B 407 0 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING tions SE Table A 36 X Form continued Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 stswi 31 S A NB 725 0 stswx 3 31 S A B 661 0 stwbrx 31 S A B 662 0 stwex 31 S A B 150 1 stwux 31 S A B 183 0 stwx 31 S A B 151 0 sync 31 00000 00000 00000 598 0 td 31 TO A B 68 0 tlbia
169. 9 30 31 OPCD BO BI BD AA LK Specific Instruction bcx 16 BO BI BD AA LK Table A 33 SC Form Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OPCD 00000 00000 000000000000000 1 0 Specific Instruction sc 17 00000 00000 000000000000000 1 0 Table A 34 D Form Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OPCD D A d OPCD D A SIMM OPCD S A d OPCD S A UIMM OPCD crfD JOJL A SIMM OPCD crfD O L A UIMM OPCD TO A SIMM Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instructions Sorted by Form Table A 34 D Form continued Specific Instruction addi 14 D A SIMM addic 12 D A SIMM addic 13 D A SIMM addis 15 D A SIMM andi 28 S A UIMM andis 29 S A UIMM cmpi 11 crfD OIL A SIMM cmpli 10 crfD OIL A UIMM Ibz 34 D A d Ibzu 35 D A d lfd 50 D A d lfdu 51 D A d lfs 48 D A d Heu 49 D A d Iha 42 D A d Ihau 43 D A d Ihz 40 D A d Ihzu 41 D A d Imw 46 D A d Iwz 32 D A d Iwzu 33 D A d mulli 7 D A SIMM ori 24 S A UIMM oris 25 S A UIMM stb 38 S A d stbu 39 S A d stfd 54 S A d stfdu 55 S A d stfs 52 S A d stfsu 53 S A d sth 44 S A d sthu 4
170. A 1 A These entries indicate the byte portions of the requested operand that are read or written during that bus transaction These entries are not required and are ignored during read transactions and are driven with undefined data during all write transactions The MPC603e supports misaligned memory operations although their use may substantially degrade performance Misaligned memory transfers address memory that is not aligned to the size of the data being transferred such as a word read of an odd byte address Although most of these operations hit in the primary cache or generate burst memory operations if they miss the MPC603e interface supports misaligned transfers within a word 32 bit aligned boundary as shown in Table 8 6 Note that the 4 byte transfer in Table 8 6 is only one example of misalignment As long as the attempted transfer does not cross a word boundary the MPC603e can transfer the data on the misaligned address for example a half word read from an odd byte aligned address An attempt to address data that crosses a word boundary requires two bus transfers to access the data Note that an attempt to load or store a floating point operand that is not word aligned will result in a floating point alignment exception For more information refer to Section 4 5 6 Alignment Exception 0x00600 Chapter 8 System Interface Operation For More Information On This Product Go to www f
171. A rS SH Shift Right Word srw srw rA rS rB 2 3 4 2 Floating Point Instructions This section describes the floating point instructions which include the following e Floating point arithmetic instructions e Floating point multiply add instructions e Floating point rounding and conversion instructions e Floating point compare instructions e Floating point status and control register instructions e Floating point move instructions See Section 2 3 4 3 Load and Store Instructions for information about floating point loads and stores The PowerPC architecture supports a floating point system as defined in the IEEE 754 standard but requires software support to conform with that standard All floating point operations conform to the IEEE 754 standard except if software sets the non IEEE mode bit ND in the FPSCR The MPC603e is in the nondenormalized mode when the NI bit is set in the FPSCR If a denormalized result is produced a default result of zero is generated The generated zero has the same sign as the denormalized number The MPC603e performs single and double precision floating point operations compliant with the IEEE 754 floating point standard Implementation Note Single precision denormalized results require two additional processor clock cycles to round When loading or storing a single precision denormalized number the load store unit may take up to 24 processor clock cycles to convert between the internal double pr
172. As bus operations are performed on the bus by other bus masters the MPC603e bus snooping logic monitors the addresses that are referenced These addresses are compared with the addresses resident in the data cache If there is a snoop hit the MPC603e bus snooping logic responds to the bus interface with the appropriate snoop status for example an ARTRY Additional snoop action may be forwarded to the cache as a result of a snoop hit in some cases a cache push of modified data or cache block invalidation The MPC603e supports a fully coherent 4 Gbyte physical memory address space Bus snooping is used to drive the MEI three state cache coherency protocol that ensures the coherency of global memory with respect to the processor s cache See Section 3 6 1 MEI State Definitions This chapter describes the organization of the MPC603e on chip instruction and data caches the MEI cache coherency protocol cache control instructions various cache operations and the interaction between the cache LSU and BIU PID7t 603e specific information is noted where applicable 3 1 Instruction Cache Organization and Control The instruction fetcher accesses the instruction cache frequently in order to sustain the high throughput provided by the six entry instruction queue 3 1 1 Instruction Cache Organization The instruction cache organization is shown in Figure 3 1 Each cache block contains eight contiguous words from memory that are loaded
173. B OE XO Rc OPCD D A B 0 XO Rc OPCD D A 00000 OE XO Rc Specific Instructions 31 D B OE 266 Rc 31 D A B OE 10 Rc 31 D A B OE 138 Re 31 D A 00000 OE 234 Re 31 D A 00000 OE 202 Re 31 D A B OE 489 Re 31 D A B OE 457 Re 31 D A B OE 491 Re 31 D A B OE 459 Re 31 D A B 0 73 Rc 31 D A B 0 9 Re 31 D A B 0 75 Re 31 D A B 0 11 Re 31 D A B OE 233 Rc 31 D A B OE 235 Rc 31 D A 00000 OE 104 Rc 31 D A B OE 40 Rc 31 D A B OE 8 Rc 31 D A B OE 136 Re 31 D A 00000 OE 232 Re 31 D A 00000 OE 200 Re 1 64 bit instruction Name Table A 42 A Form 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OPCD D A B 00000 XO Rc OPCD D A B C XO Rc OPCD D A 00000 C XO Rc OPCD D 00000 B 00000 XO Rc Appendix A PowerPC Instruction Set Listings Go to www freescale com For More information On This Product Name faddx faddsx fdivx fdivsx fmaddx fmaddsx fmsubx fmsubsx fmulx fmulsx fnmaddx fnmaddsx fnmsubx fnmsubsx fresx frsqrtex fselx fsqrtx fsqrtsx fsubx fsubsx Name rlwimix rlwinmx Table A 42 A Form continued Freescale Semiconductor Inc Instructions Sorted by Form 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Specific Instructions 63 D A B 00000 21 Re 59 D A B 00000 21 Re 63 D A B 0000
174. Bus Arbitration Signals 8 2 2 Address Pipelining and Split Bus Transactions The MPC603e protocol provides independent address and data bus capability to support pipelined and split bus transaction system organizations Address pipelining allows the address tenure of a new bus transaction to begin before the data tenure of the current transaction has finished Split bus transaction capability allows other bus activity to occur either from the same master or from different masters between the address and data tenures of a transaction While this capability does not inherently reduce memory latency support for address pipelining and split bus transactions can greatly improve effective bus memory throughput For this reason these techniques are most effective in shared memory multiprocessor implementations where bus bandwidth is an important measurement of system performance External arbitration is required in systems in which multiple devices must compete for the system bus The design of the external arbiter affects pipelining by regulating address bus grant BG data bus grant DBG and address acknowledge AACK signals For example a one level pipeline is enabled by asserting AACK to the current address bus master and granting mastership of the address bus to the next requesting master before the current data bus tenure has completed Two address tenures can occur before the current data bus tenure completes The MPC603e can
175. C603e also provides independent four entry BAT arrays for instructions and data that maintain address translations for blocks of memory These entries define blocks that can vary from 128 Kbytes to 256 Mbytes The BAT arrays are maintained by system software As specified by the PowerPC architecture the hashed page table is a variable sized data structure that defines the mapping between virtual page numbers and physical page numbers The page table size is a power of two and its starting address is a multiple of its size Chapter 1 Overview For More information On This Product Go to www freescale com Freescale Semiconductor Inc Implementation Specific Information Also as specified by the PowerPC architecture the page table contains a number of PTEGs A PTEG contains 8 PTEs of 8 bytes each therefore each PTEG is 64 bytes long PTEG addresses are entry points for table search operations 1 3 6 Instruction Timing The MPC603e is a pipelined superscalar processor The processing of an instruction is reduced into discrete stages by a pipelined processor Because the processing of an instruction is broken into a series of stages an instruction does not require the entire resources of an execution unit For example after an instruction completes the decode stage it can pass on to the next stage while the subsequent instruction can advance into the decode stage This improves the throughput of the instruction flow For example it
176. Definitions Section 2 1 2 6 Instruction Address Breakpoint Register IABR provides more information about the instruction breakpoint facility 4 5 16 System Management Interrupt 0x01400 The system management interrupt behaves like an external interrupt except for the signal asserted and the vector taken A system management interrupt is signaled to the MPC603e by the assertion of the SMI signal The interrupt may not be recognized if a higher priority exception occurs simultaneously or if MSR EE is cleared when SMI is asserted Note that SMI takes priority over INT if they are recognized simultaneously After the SMI is detected and provided that MSR EE is set the MPC603e generates a recoverable halt to instruction completion The MPC603e requires the next instruction in program order to complete or except block completion of any following instructions and allow the completed store queue to drain If any higher priority exceptions are encountered in this process they are taken first and the system management interrupt is delayed until a recoverable halt is achieved At this time the MPC603e saves state information and takes the system management interrupt The register settings for the external interrupt exception are shown in Table 4 20 Table 4 20 System Management Interrupt Register Settings Register Setting Description SRRO Set to the effective address of the instruction that the processor would have atte
177. ESET signal 8 41 reset exception 4 17 settings caused by hard reset 4 17 SRESET signal 7 25 8 41 Retirement definition 6 2 Rotate and shift instructions 2 25 A 16 RPA required physical address 5 35 RSRV signal 7 27 8 41 C 15 S Segment registers SR manipulation instructions 2 46 A 24 T bit Glossary 4 Segmented memory model see Memory management unit Self modifying code 2 30 Serializing instructions 6 16 Signals AACK 7 15 ABB 7 4 8 7 address arbitration 7 2 8 7 address transfer 8 11 address transfer attribute 8 12 An 7 6 APE 7 8 APn 7 7 ARTRY 7 15 8 24 BG 7 4 8 7 BR 7 3 8 7 checkstop 8 40 CI 7 13 CKSTP_IN 7 24 CKSTP_OUT 7 24 CLK_OUT 7 30 configuration 7 2 COP scan interface 7 27 CSEn 7 14 8 29 data arbitration 8 7 8 21 data transfer termination 8 24 DBB 7 18 8 8 8 22 DBDIS 7 21 DBG 7 17 8 7 DBWO 7 17 8 8 8 22 8 43 DHn DLn 7 18 DPE 7 20 DPn 7 19 DRTRY 7 22 8 24 8 27 GBL 7 14 HRESET 7 25 INT 7 23 8 40 MCP 7 24 PLL_CFGan 7 30 QACK 7 26 8 37 8 40 QREQ 7 26 8 41 Reset 8 41 RSRYV 7 27 8 41 C 15 SMI 4 34 7 23 SRESET 7 25 8 41 TA 7 21 TBEN 7 27 TBST 7 12 8 23 TCn 7 13 8 19 TEA 7 22 8 24 8 27 TLBISYNC 7 27 TS 7 6 TSIZn 7 12 8 13 TTn 7 9 8 12 WT 7 14 XATS MPC603 specific 1 6 Single beat reads with data delays timing 8 34 Single beat transactions 3 9 Single beat transfer rea
178. For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary e Floating point instructions These include floating point arithmetic instructions as well as instructions that affect the floating point status and control register FPSCR For more information see Section 2 3 4 2 Floating Point Instructions e Load and store instructions These include integer and floating point load and store instructions For more information see Section 2 3 4 3 Load and Store Instructions e Flow control instructions These include branching instructions condition register logical instructions and other instructions that affect the instruction flow For more information see Section 2 3 4 4 Branch and Flow Control Instructions e Trap instructions These are used to test for a specified set of conditions see Section 2 3 4 5 Trap Instructions e Processor control instructions These are used for synchronizing memory accesses and managing caches TLBs and segment registers For more information see Section 2 3 4 6 Processor Control Instructions Section 2 3 5 1 Processor Control Instructions and Section 2 3 6 2 Processor Control Instructions OEA e Memory synchronization instructions These are used for synchronizing memory accesses See Section 2 3 4 7 Memory Synchronization Instructions UISA and Section 2 3 5 2 Memory Synchro
179. Freescale Semiconductor MPC603EUM AD Q2 02 REV 3 MPC603e RISC Microprocessor User s Manual Tu ve foa freescale For More ee oe On This een Go to www freescale co Freescale Semiconductor Inc Home Page www freescale com email support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 800 521 6274 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 81 2666 8080 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 800 441 2447 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to
180. H WH Bus Transactions SH Snoop Hit pD Snoop Push RH Read Hit RM Read Miss p Cache Line Fill WH Write Hit WM Write Miss SH CRW Snoop Hit Cacheable Read Write SH CIR Snoop Hit Cache Inhibited Read Figure 3 4 MEI Cache Coherency Protocol State Diagram WIM 001 Section 3 10 MEI State Transactions provides a detailed list of MEI transitions for various operations and WIM bit settings 3 6 3 MEI Hardware Considerations While the MPC603e provides the hardware required to monitor bus traffic for coherency the MPC603e data cache tags are single ported and a simultaneous load or store and snoop access represent a resource conflict In general the snoop access has highest priority and is given first access to the tags The load or store access will then occur on the clock following the snoop The snoop is not given priority into the tags when the snoop coincides with a tag write for example validation after a cache block load In these situations the snoop is retried and must re arbitrate before the lookup is possible Occasionally cache snoops cannot be serviced and must be retried These retries occur if the cache is busy with a burst read or write when the snoop operation takes place Chapter 3 Instruction and Data Cache Operation For More Information On This Product Go to www freescale com Cache Coherency MEl ph regseale Semiconductor Inc Note that it is possible for a snoop to hit
181. ID6 603e implementation with the exception of the introduction of the 33 bit Run_N counter register MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Using DBWO in which the most significant 32 bits form a 32 bit counter The function of the least significant bit remains unchanged The Run_N counter is used by the COP to control the number of processor cycles that the processor runs before halting 8 10 Using DBWO The MPC603e supports split transaction pipelined transactions It supports a limited out of order capability for its own pipelined transactions through the DBWO signal When recognized on the clock of a qualified DBG the assertion of DB WO directs the MPC603e to perform the next pending data write tenure if any even if a pending read tenure would have normally been performed because of address pipelining The DBWO signal does not reorder write tenures with respect to other write tenures from the same MPC603e It only allows that a write tenure be performed ahead of a pending read tenure from the same MPC603e In general an address tenure on the bus is followed strictly in order by its associated data tenure Transactions pipelined by the MPC603e complete strictly in order However the MPC603e can run bus transactions out of order only when the external system allows the MPC603e to perform a cache line snoop push out operation o
182. Ihaux Ihax Ihbrx Ihzux Ihzx Iswi 3 Iswx 3 lwarx lwaux Iwax Iwbrx lwzux lwzx merfs merxr mfcr Freescale Semiconductor Table A 36 X Form continued 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Inc PSructions Sorted by Form wo a 63 crfD 00 A B 32 0 63 crfD 00 A B 0 0 63 D 00000 B 814 He 63 D 00000 B 815 He 63 D 00000 B 14 Re 63 D 00000 B 15 Re 63 D 00000 B 72 Re 63 D 00000 B 136 Re 63 D 00000 B 40 Re 63 D 00000 B 12 Re 31 00000 A B 982 0 31 D A B 119 0 31 D A B 87 0 31 D A B 84 0 31 D A B 53 0 31 D A B 21 0 31 D A B 631 0 31 D A B 599 0 31 D A B 567 0 31 D A B 535 0 31 D A B 375 0 31 D A B 343 0 31 D A B 790 0 31 D A B 311 0 31 D A B 279 0 31 D A NB 597 0 31 D A B 533 0 31 D A B 20 0 31 D A B 373 0 31 D A B 341 0 31 D A B 534 0 31 D A B 55 0 31 D A B 23 0 63 crfD 00 crfS 00 00000 64 0 31 crfD 00 00000 00000 512 0 31 D 00000 00000 19 0 Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com F Instructions Sorted by Form Table A 36 X Form continued reescale Semiconductor Inc Name 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 2
183. Instructions 0 0000000000 2 46 Recommended Simplified Mnemontcs eee eeeeeeeeeseeceseceeeeseeeeseeeaeenes 2 47 Implementation Specific Instructpons eeeeeseeessecseceeeeeeeeesseeesaeenseeees 2 47 Chapter 3 Instruction and Data Cache Operation Instruction Cache Organization and Control 3 3 Instruction Cache Ore ani ations ere 3 3 Instruction Cache Fill Operations 2 2246 25 626 nei aa adieu 3 4 Instruction Cache Controlere Ble ite Aas geese Rind ees gence 3 4 Instruction Cache Inwalid ation s 1 3 cc c042 occas cea des ege Es 3 4 Instruction Cache Disabling s s cc cc s cnsceisasceseaspeeadteseacncsesnaceadendeenawesooraavesssens 3 4 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Paragraph Number 3 1 3 3 3 2 3 2 1 3 22 323 3 2 3 1 ae Bes 3 2 3 3 3 2 3 4 3 2 4 3 3 3 3 1 3 3 2 3 3 3 3 4 3 4 1 3 4 2 3 4 3 3 5 3 5 1 3 5 2 3 5 3 3 5 4 3 5 5 3 5 5 1 3 5 5 2 3 5 5 3 3 6 3 6 1 3 6 2 3 6 3 3 6 4 3 6 4 1 3 6 5 3 6 6 3 6 7 3 6 8 3 6 9 3 7 3 7 1 31 2 Freescale Semiconductor Inc Contents Page Title Number Instruction Cache Locking ssesesessseeesseessseesseesseeeserssseessresseesseeeseeesssees 3 5 Data Cache Organization and Control 3 5 D ta Cache Organization E 3 5 Data Cache Pill Operations jcccicsissd caieccssaaties jodeia ENNEN EEN 3 6 Data Cache e EE 3 6 Data Cache Invalid ation nccsicdsscrscdassccesaeacssnasdesnae
184. KEY 1 Setup for Protection Violation See Figure 5 18 Otherwise Set R C Bits temp lt temp OR 0x180 Store Bytes 6 7 of PTE to Memory ptr 2 lt temp Bytes 6 7 Return to TLB Miss Exception Flow See Figure 5 15 Figure 5 16 Check and Set R and C Bit Flow MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Oe tie BEE Figure 5 17 shows the flow for synthesizing a page fault exception when no PTE is found Setup for Page Fault Exception O Data TLB Miss Handlers Instruction TLB Miss Handlers DSISR 6 SRR1 15 Clear Upper Bits of SRR1 SRR1 SRR1 AND OxFFFF DSISR 1 lt 1 dtemp DMISS Clear Upper Bits of SRR1 SRR1 lt SRR1 AND OxFFFF SRR1 1 lt 1 Restore CRO Bits MSR TGPR lt 0 Branch to ISI Exception Handler SRR1 31 1 Little Endian Mode Otherwise dtemp dtemp XOR 0x07 DAR lt dtemp Restore CRO Bits MSR TGPR lt 0 Branch to DSI Exception Handler Figure 5 17 Page Fault Setup Flow Figure 5 18 shows the flow for managing the cases of a TLB miss on an instruction access to guarded memory and a TLB miss when C 0 and a protection violation exists The setup Chapter 5 Memory Management For More Information On This Product Go to www freescale com Page Table Search Operathreeseale Semiconductor Inc for these
185. L 0 31 7 2 7 3 Data Parity Error DPE Output The DPE signal is an output signal output only on the MPC603e Note that DPE is an open drain type output and requires an external pull up resistor for example 10 kQ to Vpp to assure proper negation of DPE Following are the state meaning and timing comments for the DPE output State Meaning Asserted Indicates incorrect data bus parity Negated Indicates correct data bus parity Timing Comments Assertion Occurs on the second bus clock cycle after TA is asserted to the MPC603e unless TA is canceled by an assertion of DRTRY High Impedance Occurs on the third bus clock cycle after TA is asserted to the MPC603e MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc i Ka Signal Descriptions 7 2 7 4 Data Bus Disable DBDIS Input The DBDIS signal is an input signal input only on the MPC603e Following are the state meaning and timing comments for the DBDIS input State Meaning Asserted lIndicates for a write transaction that the MPC603e must release the data bus and the data bus parity to high impedance during the following cycle The data tenure remains active DBB remains driven and the transfer termination signals are still monitored by the MPC603e Negated Indicates the data bus should remain normally driven DBDIS is ignored during read transactions Timing C
186. M bit e Guarded memory G bit These bits allow both uniprocessor and multiprocessor system designs to exploit numerous system level performance optimizations Careless specification and use of these bits may create situations where coherency paradoxes are observed by the processor In particular this can happen when the state of these bits is changed without appropriate precautions being taken for example when MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Frees aAlg Se eos bag IM Fade Bits w m and G flushing the pages that correspond to the changed bits from the caches of all processors in the system is required or when the address translations of aliased physical addresses referred to as real addresses in the architecture specification specify different values for any of the WIM bits The MPC603e considers any of these cases to be a programming error that may compromise the coherency of memory These paradoxes can occur within a single processor or across several devices as described in Section 3 6 4 1 Coherency in Single Processor Systems The WIMG attributes are programmed by the operating system for each page and block The W and I attributes control how the processor performing an access uses its own cache The M attribute ensures that coherency is maintained for all copies of the addressed memory location The G attribute prevents out of order loadin
187. MEI State ere ee Ee EE 3 16 MEI State Dias E 3 16 MEI Hardware Considerations suey ee E ee 3 17 Cohereney Precautions sco 2s ct cho occ ee tee 3 19 Coherency in Single Processor Systems cceeseeesseceseeeeeeeeseeesaeeeseeeeees 3 19 Load and Store Coherency Summary cceesceceeseeceseeeceeeeeceeeeeceeeeeesteeeees 3 19 Atomic Memory References eege Ed EZE sncseneadasececaantecs See Eeer 3 20 Cache Reaction to Specific Bus Operations 0 eeeceeeececseececeeeeeeeteeeenteeees 3 20 Operations Causing ARTRY Assertion 0 eccceeeccecseececeteeecseeeeeseeeenaeeeenes 3 21 Enveloped High Priority Cache Block Push Operation 0 00 0 ceeseeeseeeeteeees 3 22 Cache Control ste EE 3 22 Data Cache Block Invalidate debi Instruction ccc cc ccccceeeesesseceeeeees 3 24 Data Cache Block Touch debt Instruction ccceccccccceceeeesessnseceeeeeees 3 24 Contents ix For More Information On This Product Go to www freescale com Paragraph Number 3 7 3 3 7 4 3 7 5 3 7 6 3 7 7 3 7 8 3 7 9 3 8 3 9 3 10 4 1 4 1 1 4 1 2 4 2 4 2 1 4 2 1 1 4 2 1 2 4 2 2 4 2 3 4 2 4 4 2 5 4 3 4 4 4 5 4 5 1 4 5 1 1 4 5 1 2 4 5 2 4 5 2 1 4 5 2 2 4 5 3 4 5 4 4 5 5 4 5 6 4 5 6 1 4 5 6 2 4 5 7 4 5 7 1 Freescale Semiconductor Inc Contents Page Title Number Data Cache Block Touch for Store debtst Instruction cece eeeeeeeee 3 24 Data Cache Block Clear to Zero debz Instruction sssoos
188. MP Read Lower Word of Next PTE from Memory temp lt ptr O temp compare_value Otherwise Otherwise Read Upper Word of PTE temp lt ptr 4 compare_value H Otherwise Secondary Hash Complete Setup for Page Fault Exception See Figure 5 17 Setup for Protection Violation Exception See Figure 5 18 RPA lt temp Load Secondary PTEG Pointer ptr HASH2 8 compare_value H lt 1 Set Counter cnt e 8 Instruction Access and temp G 1 Otherwise lt ea gt lt IMISS DMISS Check R C Bits and Set as Needed See Figure 5 16 Load TLB Entry tlbli lt ea gt or tlbId lt ea gt Restore Old Counter and CRO Bits Return to Executing Program rfi Figure 5 15 Flow for Example Software Table Search Operation Chapter 5 Memory Management For More information On This Product Go to www freescale com Page Table Search OperathFeeseale Semiconductor Inc The flow for checking the R and C bits and setting them appropriately is shown in Figure 5 16 Check R C Bits and Set as Needed Handler for Data Store Op Otherwise temp C 0 Check Protection pp D Otherwise Set R Bit temp lt temp OR 0x100 10 pe Store Byte 7 of PTE to Memory pp 00 ptr 2 lt temp Byte 7 pp 11 01 Setup for Return to TLB Miss Protection Violation Exception Flow See Figure 5 18 See Figure 5 15 SRRI1
189. Memory Sesment Model arson r a Eeer 5 20 P ge History R cordn EN 5 21 Referenced Bit mesinin inin on en E 5 22 Changed E e e e E A aE 5 22 Scenarios for Referenced and Changed Bit Recording eeeeeeeeeeeee 5 23 Page M mory Protection sissiescyceiire iensor see ie e ceai ni 5 24 TEB Description EE 5 24 TEB RE EE 5 25 TLB Entry Areler 5 26 Page Address Translation Summary cccceceeececeseceesseeeeseceeseeeeneeeenaeeees 5 27 Page Table Search Operation erter EE 5 27 Page Table Search Operation Conceptual FIOW s ssssssssesesssesessseessresseesse 5 27 Contents xi For More Information On This Product Go to www freescale com Paragraph Number 5 5 2 55 21 5 5 2 1 1 5 5 2 1 2 5 5 2 1 3 5 5 2 1 4 5 5 2 2 5 5 2 2 1 K 5 5 3 5 5 4 6 1 6 2 6 3 6 3 1 6 3 2 6 3 2 1 6 3 2 2 6 3 2 3 6 3 3 6 3 3 1 6 3 3 2 6 3 3 3 6 4 6 4 1 6 4 1 1 6 4 1 2 6 4 1 2 1 6 4 2 6 4 3 6 4 4 6 4 5 6 5 6 5 1 6 5 2 6 5 3 Freescale Semiconductor Inc Contents Page Title Number Implementation Specific Table Search Operation eee eeeeeeeeeeeseeeeeeeees 5 31 Resources for Table Search Operations eeceesceeeseceseeeseeeeseecnaeeneeees 5 31 Data and Instruction TLB Miss Address Registers COMISS and Meute eege dee Eege eege 5 33 Data and Instruction TLB Compare Registers DCMP and ICMP 5 34 Primary and Secondary Hash Address Registers HASHT and A STD EE 5 34 Required Physical A
190. Not Implemented Revision History Glossary of Terms and Abbreviations Index For More Information On This Product Go to www freescale com Paragraph Number 1 1 1 1 1 1 1 2 1 1 2 1 1 1 2 1 1 LEE LE 1 1 2 2 1 EN Ee 1 1 2 2 3 1 1 3 1 1 3 1 1 1 3 2 1 1 4 1 1 4 1 1 1 4 2 1 1 4 3 1 1 4 4 1 1 4 5 1 1 5 1 1 5 1 1 1 5 2 1 1 6 1 1 7 1 1 7 1 LAT 1 1 7 3 1 1 7 4 1 2 Freescale Semiconductor Inc Contents Page Title Number About This Book Chapter 1 Overview OVE Ws ee 1 1 ele 1 3 System Design and Programming Considerations cccccesseceesseeeenteeeennees 1 6 Hardware Features cesececteces iether eceaties Sian Eelere 1 6 Replacement of XATS Signal by CSE Signal s es 1 6 Addition of Half Clock Bus Muloplterz A 1 7 Software Feature Srey cacti cte a gol ccs sae e nate E A aS 1 7 16 Kbyte Instruction and Data Cache ce eeccceeeseceeseeceesseceenteeeenaeeeeaes 1 7 Clock Configuration Available in HID1 Register 1 7 Performance Enhancements 2 aee ug erg wees keeedet geed Egger 1 7 MTV SET LS e SI TON nay on E cts aly aN eas Gesu E ae 1 8 Instruction Queue and Dispatch Unit eee eseeceeeeeeeecneecnneeeseeeeneees 1 8 Branch Processing Unit CES taeda coh aca 1 9 Independent Execution Heel Ateggegtdeggter ien Sec gies sane oder DEn ege et etg 1 9 Integer Unit U EE 1 9 Floating Point Unit FPU eeeeseeessseeesesssesresseseresresseseresresseesreseeseeseesereses 1 10 Load Store Me EE e
191. OP logic If trace and breakpoint conditions occur simultaneously the breakpoint conditions receive higher priority When a trace exception is taken instruction execution for the handler begins as offset 0x00D00 from the base address indicated by MSR IP 4 5 11 1 Single Step Instruction Trace Mode The single step instruction trace mode is enabled by setting MSR SE Encountering the single step breakpoint causes one of the following actions e Trap to address vector 0x00D00 e Soft stop wait for quiescence The single step trace action traps after an instruction execution and completion 4 5 11 2 Branch Trace Mode The branch trace mode is enabled by setting MSR BE Encountering the branch trace breakpoint causes one of the following actions e Trap to interrupt vector OxOOD00 e Soft stop e Hard stop The branch trace action is to trap after the completion of any branch instruction whenever MSR BE is set 4 5 12 Instruction TLB Miss Exception 0x01000 When the effective address for an instruction load store or cache operation cannot be translated by the ITLB an instruction TLB miss exception is generated Register settings for the instruction and data TLB miss exceptions are described in Table 4 17 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Caen Exception Definitions If the instruction TLB miss exception handler fai
192. P 0 3 inputs If there is an error and address parity checking is enabled HIDO EBA is set the APE output is asserted An address bus parity error causes a checkstop condition if MSR ME is cleared For more information about checkstop conditions see Chapter 4 Exceptions 8 3 2 2 Address Transfer Attribute Signals The transfer attribute signals include several encoded signals such as the transfer type TT 0 4 signals transfer burst TBST signal transfer size TSIZ 0 2 signals and transfer code TC O0 1 signals Section 7 2 4 Address Transfer Attribute Signals describes the encodings for the address transfer attribute signals 8 3 2 2 1 Transfer Type TT 0 4 Signals Snooping logic should fully decode the transfer type signals if the GBL signal is asserted Slave devices can sometimes use the individual transfer type signals without fully decoding MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Address Bus Tenure the group For a complete description of the encoding for transfer type signals TT 0 4 refer to Table 7 1 and Table 7 2 8 3 2 2 2 Transfer Size TSIZ 0 2 Signals The transfer size signals TSIZ 0 2 indicate the size of the requested data transfer as shown in Table 8 2 The TSIZ 0 2 signals may be used along with TBST and A 29 31 to determine which portion of the data bus contains valid data for
193. PC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc i ba Signal Descriptions Note that CSE 0 1 are not meaningful during data cache touch load operations Timing Comments Assertion Negation The same as A 0 31 High Impedance The same as A 0 31 7 2 5 Address Transfer Termination Signals The address transfer termination signals are used to indicate either that the address phase of the transaction has completed successfully or must be repeated and when it should be terminated For detailed information about how these signals interact see Section 8 3 3 Address Transfer Termination 7 2 5 1 Address Acknowledge AACK Input Following are the state meaning and timing comments for the AACK input State Meaning Asserted Indicates that the address phase of a transaction is complete The address bus will go to a high impedance state on the next bus clock cycle The MPC603e samples ARTRY on the bus clock cycle following the assertion of AACK Negated During ABB indicates that the address bus and transfer attributes must remain driven Timing Comments Assertion May occur as early as the bus clock cycle after TS is asserted unless MPC603e is configured for 1 1 or 1 5 1 clock modes when AACK can be asserted no sooner than the second cycle following the assertion of TS one address wait state assertion can be delayed to
194. PC603e specific Required physical address register RPA The system software loads a TLB entry by loading the second word of the matching PTE entry into the RPA register and then executing the tlbli or tlbld instruction for loading the ITLB or DTLB respectively This register is MPC603e specific MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc DEEN Note that the MPC603e contains other features that do not specifically control the MPC603e MMU but are implemented to increase performance and flexibility These are e Complete set of shadow segment registers for the instruction MMU These registers are invisible to the programming model as described in Section 5 4 3 TLB Description e Temporary GPRO GPR3 These registers are available as r0 r3 when MSR TGPR is set The MPC603e automatically sets MSR TGPR whenever one of the three TLB miss exceptions occurs allowing these exception handlers to have four registers that are used as scratchpad space without having to save or restore this part of the machine state that existed when the exception occurred Note that MSR TGPR is restored to the value in SRR1 when the rfi instruction is executed Refer to Section 5 5 2 Implementation Specific Table Search Operation for code examples that take advantage of these registers In addition the MPC603e also automatically sa
195. PTE 5 27 Performance considerations memory 6 22 Physical address generation memory management unit 5 1 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PID7t 603e features 1 5 Pipeline instruction timing definition 6 2 pipeline stages 6 7 superscalar pipeline diagram 6 5 Pipelined execution unit 6 4 PLL configuration 7 31 Power management doze mode 9 3 doze nap sleep DPM bits 2 10 full power mode 9 3 nap mode 9 4 programmable power modes 9 3 sleep mode 9 5 software considerations 9 6 Power management modes 1 14 Power on reset settings 4 17 PowerPC architecture instruction list A 1 A 8 A 15 levels of implementation 1 15 operating environment architecture OEA xxvii 1 15 2 43 user instruction set architecture UISA xxvii 1 15 2 2 virtual environment architecture VEA xxvii 1 15 2 40 Privilege levels supervisor level cache instruction 2 45 Privileged state see Supervisor mode Problem state see User mode Process switching 4 15 Processor control instructions 2 38 2 40 2 44 A 23 Processor identification PID number definition 1 1 Program exception 4 27 Program order definition 6 2 Programmable power states doze mode 9 3 full power mode DPM enabled disabled 9 3 nap mode 9 4 sleep mode 9 5 Protection of memory areas no execute protection 5 12 options available 5 10 protection violations 5 14 PTEGs PTE groups 5 27 PTEs p
196. PTEG addresses are entry points for table search operations Address translations are enabled by setting bits in the MSR MSR IR enables instruction address translations and MSR DR enables data address translations 1 3 5 2 Implementation Specific Memory Management The instruction and data memory management units in the MPC603e provide 4 Gbytes of logical address space accessible to supervisor and user programs with a 4 Kbyte page size and 256 Mbyte segment size Block sizes range from 128 Kbytes to 256 Mbytes and are software selectable In addition the MPC603e uses an interim 52 bit virtual address and hashed page tables for generating 32 bit physical addresses The MMUs in the MPC603e rely on the exception processing mechanism for the implementation of the paged virtual memory environment and for enforcing protection of designated memory areas Instruction and data TLBs provide address translation in parallel with the on chip cache access incurring no additional time penalty in the event of a TLB hit A TLB is a cache of the most recently used page table entries Software is responsible for maintaining the consistency of the TLB with memory The MPC603e TLBs are 64 entry two way set associative caches that contain instruction and data address translations The MPC603e provides hardware assist for software table search operations through the hashed page table on TLB misses Supervisor software can invalidate TLB entries selectively The MP
197. Parity State Meaning Asserted Indicates incorrect address bus parity has been detected by the MPC603e on a snoop GBL asserted Negated Indicates that the MPC603e has not detected a parity error even parity on the address bus Timing Comments Assertion Occurs on the second bus clock cycle after TS is asserted High Impedance Occurs on the third bus clock cycle after TS is asserted 7 2 4 Address Transfer Attribute Signals The transfer attribute signals are a set of signals that further characterize the transfer such as the size of the transfer whether it is a read or write operation and whether it is a burst or single beat transfer For a detailed description of how these signals interact see Section 8 3 2 Address Transfer MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com 7 2 4 1 Freescale Semiconductor Inc Transfer Type TT 0 4 Signal Descriptions The TT 0 4 signals consist of five input output signals on the MPC603e For a complete description of TT 0 4 signals and for transfer type encodings see Table 7 1 7 2 4 1 1 Transfer Type TT 0 4 Output Following are the state meaning and timing comments for the TT 0 4 outputs State Meaning Asserted Negated Indicates the type of transfer in progress Timing Comments Assertion Negation High Impedance The same as A 0 31 7 2 4 1 2 Transfer Type TT 0 4 Input
198. R 27 SPR 274 SPR 275 XER SPR 1 Link Register LR SPR 8 Count Register Miscellaneous Registers CTR SPR9 Time Base Facility For Writing Decrementer au TBL PR 284 Time Base Facility S S Dc SPR 22 For Reading TBU SPR 285 TBL TBR 268 Instruction Address External Address Breakpoint Register 1 Register Optional IABR SPR 1010 EAR SPR 282 1 These registers are MPC603e specific PID6 603e and PID7t 603e They may not be supported by other processors of this family TBU TBR 269 Figure 2 1 Programming Model Registers Chapter 2 Programming Model For More Information On This Product Go to www freescale com Register Set Freescale Semiconductor Inc The remaining user level registers are SPRs Note that the PowerPC architecture provides a separate mechanism for accessing SPRs the mtspr and mfspr instructions These instructions are commonly used to explicitly access certain registers while other SPRs may be accessed as the side effect of executing other instructions XER register XER The 32 bit XER indicates overflow and carries for integer operations It is set implicitly by many instructions Link register LR The 32 bit LR provides the branch target address for the Branch Conditional to Link Register belrx instruction and can optionally be used to hold the logical address referred to as the effective address in the architecture specification of the instruction that follow
199. R 5 1 Note This is an MPC603e specific condition Instruction fetch from guarded Attempt to fetch instruction when MSR IR 1 ISI exception memory with MSR IR 1 and either matching xBAT G 1 or no matching SRR1 3 1 BAT entry and PTE G 1 1 The MPC603e hardware does not vector to these exceptions automatically It is assumed that the software that performs the table search operations vectors to these exceptions and sets the appropriate bits when a page fault condition occurs 2 The table search software can also vector to these exception conditions In addition to the translation exceptions there are other MMU related conditions some of them defined as implementation specific and therefore not required by the architecture that can cause an exception to occur in the MPC603e These exception conditions map to the processor exception as shown in Table 5 4 For example the MPC603e also defines three exception conditions to support software table searching The only exception conditions that occur when MSR DR 0 are the conditions that cause the alignment exception for data accesses For more detailed information about the conditions that cause the alignment exception in particular for string multiple instructions see Section 4 5 6 Alignment Exception 0x00600 Chapter 5 Memory Management For More Information On This Product Go to www freescale com MMU Features Freescale Semiconductor Inc
200. SI exception mfspr r2 hash2 get the second pointer ori r3 r3 0x0040 change the compare value addi rl O8 load 8 for counter addi C2 2y sec pre dec for update on load b ceq0 try second hash 4 Register rO is rl is r2 is Ht r3 is cEqOChkProt rlwinm bge entry found and PTE c bit check protection before setting PT usage saved counter PTE entry pointer to pteg trashed 35201 3007 1 chk0 Gl c bit test PP if PP 00 or PP 01 goto chk0 Chapter 5 Memory Management For More Information On This Product Go to www freescale com Page Table Search Operathreeseale Semiconductor Inc andi Zye test PP 0 beq chk2 return if PP 0 0 b doDSIp else DSIp chk0 mfspr r3 srrl get old msr andis 1r3 4r3 0x0008 test the KEY bit SRR1 bit 12 beq chk2 if KEY 0 goto chk2 b doDSIp else DSIp chk2 ori rl FL OSLO set reference and change bit sth ri BEES update page table b ceq2 and back we go i 4 entry Not Found synthesize a DSI exception Entry ii r0 is saved counter ri is junk ij r2 is pointer to pteg r3 is current compare value j doDSI mfspr r3 srrl get srrl rlwinm rl r 9 6 6 get srri lt flag gt to bit 6 for load store zero rest addis rl rl 0x4000 or in dsisr lt 1l gt 1 to flag pte not found b dsil doDSIp mfspr 3 STEE get srrl rlwinm rl r3 9 6 6 get srri lt flag gt to bit 6 for load store zero
201. SIMM addis 15 D A SIMM addmex 31 D A 00000 OE 234 Rc addzex 31 D A 00000 OE 202 Rc divdx 31 D A B OE 489 Re divdux 31 D A B OE 457 Re divwx 31 D A B OE 491 Re divwux 31 D A B OE 459 Re mulhdx 1 31 D A B 0 73 Re mulhdux 31 D A B 0 9 Re mulhwx 31 D A B 0 75 Rc mulhwux 31 D A B 0 11 Rc mulld 1 31 D A B OE 233 Re mulli 07 D A SIMM mullwx 31 D A B OE 235 Re negx 31 D A 00000 JOE 104 Re subfx 31 D A B OE 40 Re subfcx 31 D A B OE 8 Re subficx 08 D A SIMM subfex 31 D A B OE 136 Re subfmex 31 D A 00000 OE 232 Rc subfzex 31 D A 00000 OE 200 Rc 1 64 bit instruction Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com Instructions Grouped by hrsescale Semiconductor Inc Table A 4 Integer Compare Instructions Name 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 cmp 31 CD Oj L A B 0000000000 0 cmpi 11 crfD OIL A SIMM cmpl 31 crfD OIL A B 32 0 cmpli 10 crfD OIL A UIMM Table A 5 Integer Logical Instructions Name 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 andx 31 S A B 28 Rc andcx 31 S A B 60 Re andi 28 S A UIMM andis 29 S A UIMM cntlzdx 1 31 S A 00000 58 Rc cntlzwx 31 S A 00000 26 Rc eqvx 31 S A B 284 Rc extsbx 31 S A 00000 954 Rc exts
202. Shift Right Double Word std Store Double Word stdcx Store Double Word Conditional Indexed stdu Store Double Word with Update stdux Store Double Word Indexed with Update stdx Store Double Word Indexed td Trap Double Word tdi Trap Double Word Immediate Table B 3 provides the 64 bit SPR encoding that is not implemented by the MPC603e microprocessor Table B 3 64 Bit SPR Encoding Not Implemented by the MPC603e SPR Register So Access Decimal spr 5 9 spr 0 4 280 01000 11000 ASR Supervisor MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix C Revision History This appendix provides a list of the major differences between the MPC603e amp EC603e RISC Microprocessor User s Manual Revision 0 and the MPC603e RISC Microprocessor User s Manual Revision 3 Note that the list only covers the major changes to the user s manual C 1 Revision Changes From Revision 2 to Revision 3 Major changes to the MPC603e RISC Microprocessor User s Manual from Revision 2 to Revision 3 are as follows Section Page 4 5 2 4 19 Change Replace the second paragraph in Section 4 5 2 Machine Check Exception 0x00200 Note that the 603e makes no attempt to force recoverability however it does guarantee the machine check exception is always taken immediately upon request with a nonpredicte
203. Sixth Floor San Francisco CA provides useful information about the PowerPC architecture and computer architecture in general The PowerPC Architecture A Specification for a New Family of RISC Processors Second Edition by International Business Machines Inc For updates to the specification see http www austin ibm com tech ppc chg html About This Book For More Information On This Product Go to www freescale com Suggested Reading Freescale Semiconductor Inc PowerPC Microprocessor Common Hardware Reference Platform A System Architecture by Apple Computer Inc International Business Machines Inc and Freescale Semmiconductor Inc Computer Architecture A Quantitative Approach Second Edition by John L Hennessy and David A Patterson Computer Organization and Design The Hardware Software Interface Second Edition David A Patterson and John L Hennessy Inside Macintosh PowerPC System Software Addison Wesley Publishing Company One Jacob Way Reading MA 01867 Tel 800 282 2732 U S A 800 637 0029 Canada 716 871 6555 International Related Documentation Freescale documentation is available from the sources listed on the back cover of this manual the document order numbers are included in parentheses for ease in ordering Programming Environments Manual for 32 Bit Implementations of the PowerPC Architecture MPCFPE32B AD Describes resources defined by the PowerPC architecture User
204. User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timing Considerations IU SRU Instructions In Dispatch Fetch Entry Execute Complete Retire a m LSU Instructions Execute In Dispatch EA Fetch Entry Calculation Cache Align Complete Retire Lo mc FPU Instructions Execute In Dispatch Round Fetch Entry Multiply Add Normalize Complete Retire OOo m BPU Instructions Fetch In Dispatch In Completion Fetch Predict Entry Queue 2 Complete Retire 2 OOo o T E mn 1 Several integer instructions such as multiply and divide instructions require multiple cycles in the execute stage 2 Only those branch instructions that update the LR or CTR take an entry in the completion queue Figure 6 3 MPC603e Microprocessor Pipeline Stages 6 3 Timing Considerations The MPC603e is a superscalar processor as many as three instructions can be dispatched to the execution units one branch instruction to the branch processing unit and two instructions dispatched from the dispatch queue to the other execution units during each clock cycle Only one instruction can be dispatched to each execution unit Although instructions appear to the programmer to execute in program order the MPC603e improves performance by executing multiple instructions at a time using hardware to manage dependencies When an instruction is dispatched the register file provides the source data
205. a read operation occurs when TA is asserted by a responding slave The TEA and DRTRY signals must remain negated during the transfer see Figure 8 8 0 1 2 3 4 Bus Clock ER KA Te qual_dbg DBB E E Data EE E hee Figure 8 8 Normal Single Beat Read Termination The DRTRY signal is not sampled during data writes as shown in Figure 8 9 0 1 2 3 Bus Clock N TS e qual_dbg DRTRY AACK es Figure 8 9 Normal Single Beat Write Termination Chapter 8 System Interface Operation For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Bus Tenure 8 4 4 2 Normal Burst Termination Normal termination of a burst transfer occurs when TA is asserted for four bus clock cycles as shown in Figure 8 10 The bus clock cycles in which TA is asserted need not be consecutive thus allowing pacing of the data transfer beats For read bursts to terminate successfully TEA and DRTRY must remain negated during the transfer For write bursts TEA must remain negated for a successful transfer DRTRY is ignored during data writes 1 2 Bus Clock 3 e qual_dbg DBB Data Figure 8 10 Normal Burst Transaction For read bursts DRTRY may be asserted one bus clock cycle after TA is asserted to signal that the data presented with TA is invalid and that the processor must wait for the negation of DRTRY before f
206. access a sync instruction should be issued before before changing the value of DCE Note that while snooping is not performed when the data cache is disabled cache operations caused by the dcbz dcbf dcbst and dcbi instructions are not affected by disabling the cache causing potential coherency errors An example of this would be a dcht instruction that hits a modified cache block in the disabled cache causing a copy back to memory of potentially stale data Regardless of the state of HIDO DCE load and store operations are assumed to be weakly ordered Thus the LSU can perform load operations that occur later in the program ahead of store operations even when the data cache is disabled However strongly ordered load and store operations can be enforced through the setting of the I bit of the page WIMG bits when address translation is enabled Note that when address translation is disabled the default WIMG bits cause the I bit to be cleared accesses are assumed to be cacheable and thus the accesses are weakly ordered Refer to Section 3 5 2 Caching Inhibited Attribute 1 for a description of the operation of the I bit and Section 5 2 Real Addressing Mode for a description of the WIMG bits when address translation is disabled 3 2 3 3 Data Cache Locking The contents of the data cache may be locked through the HIDO DLOCK A locked data cache supplies data normally on a cache hit but cache misses are treated as cache
207. actions to a depth of one level Access to the system interface is granted through an external arbitration mechanism that allows devices to compete for bus mastership This arbitration is flexible allowing the MPC603e to be integrated into systems that implement various fairness and bus parking procedures to avoid arbitration overhead Typically memory accesses are weakly ordered sequences of operations including load store string and multiple instructions do not necessarily complete in the order they begin maximizing the efficiency of the bus without sacrificing coherency of the data The MPC603e allows read operations to precede store operations except when a dependency exists or in cases where a noncacheable access is performed and provides support for a write operation to proceed a previously queued read data tenure for example allowing a snoop push to be enveloped by the address and data tenures of a read operation Because the processor can dynamically optimize run time ordering of load store traffic overall performance is improved Chapter 1 Overview For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Overview 1 1 7 System Support Functions The MPC603e implements several support functions that include power management time base decrementer registers for system timing tasks an IEEE 1149 1 JTAG common on chip processor COP test interface and a phase locked loop PLL clo
208. aeeraans 7 3 Bu s Grant ere EE 7 4 Address BUS Busy EE 7 4 Address Bus Busy LADB Output 7 5 Address Bus Busy AB np 7 5 Address Transter Start EE 7 5 Transfer e ER Er 7 6 Transfer Start 1S e EE 7 6 Transfer d 1S TEE 7 6 Address Transfer Siomals ii isssevsssideatsassasinesyedets snaa ed 7 6 Address Bus AA MAUEREN 7 6 Address Bus ET HEEN 7 7 Address Bus A 0 31 Input ssa oa aaces te lee ae sees 7 7 Address Bus Parity AP 0 3 EE 7 7 Address Bus Parity AP 0 3 Output seeesneeeseeessensseessesessseessressesssee 7 7 Address Bus Parity AP 0 3 Input 00 0 eee eeeceeceeeecseeeeceeeeeeeteeeenaes 7 8 Address Parity Error APE Outmut 7 8 Address Transfer Attribute Sugnals AAA 7 8 Transiter Type CET AD E 7 9 Transfer Type TT 0 4 Outputt 00 oe eeeeeececneeceeeeseeeeneeenaeenes 7 9 Transfer Ty pe C TT OA mt geed Ee 7 9 Transfer Size TSIZ 0 2 Output sccccsscccccdeascccsecasvseccesnsccedesedeestedensecnenees 7 12 Transfer Burst NR EE 7 12 Transfer Burst PB SP Ont ageseent gedd SaeE An 7 12 Transfer Burst GERS opt seeei tg ee teeter atiie irae 7 13 Transfer Code 1 C 0 1 Output enee ee deed 7 13 hett 7 13 Write Through WT Output 0 c cccscsssssssssssssssssessssessesseeseseseseeseseeees 7 14 Global GBE EE EE 7 14 Contents xi For More Information On This Product Go to www freescale com Paragraph Number TDA A 1 2 4 1 2 7 2 4 8 7 2 5 ete a 7 2 5 2 7 2 5 2 1 71 2 5 2 2
209. age table entries 5 27 Q QACK signal 7 26 8 37 8 40 QREQ signal 7 26 8 41 Qualified bus grant 8 7 Qualified data bus grant 8 21 R Read operation 3 20 Read with intent to modify operation 3 20 Read atomic operation 3 20 Real address RA see Physical address generation Real addressing mode see Direct address translation Reduced pinout mode 8 40 Referenced R bit maintenance recording 5 11 5 21 5 23 5 29 Registers configuration registers MSR 2 4 PVR 2 4 exception handling registers DAR 2 5 DSISR 2 5 SPRGO SPRG3 2 5 SRRO 2 5 SRR1 2 5 implementation specific registers DCMP ICMP 2 10 DMISS IMISS 2 10 HASH1 HASH2 2 11 HIDO HID1 1 19 2 6 IABR 2 12 RPA 2 12 memory management registers BAT 2 5 SDR1 2 5 SR 2 5 supervisor level BAT 2 5 DAR 2 5 DCMP and ICMP 2 10 5 34 DEC 2 6 DMISS and IMISS 2 10 5 33 DSISR 2 5 EAR 2 6 HASH 1 and HASH2 2 11 5 34 HIDO and HID 1 1 19 2 6 IABR 2 12 MSR 2 4 PVR 2 4 RPA 2 12 SDR1 2 5 SPRGO SPRG3 2 5 SR 2 5 SRRO 2 5 SRR1 2 5 TB 2 6 user level CR 2 2 CTR 2 4 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc FPRO FPR31 2 2 FPSCR 2 2 GPRO GPR31 2 2 LR 2 4 TB 2 4 TGPRO TGPR3 5 32 XER 2 4 Rename buffer 6 2 Rename register operation 6 15 Reservation station 6 2 Reserved instruction class 2 19 Reset HRESET signal 7 25 HR
210. al Descriptions provides descriptions of individual signals of the MPC603e Chapter 8 System Interface Operation describes signal timings for various operations It also provides information for interfacing to the MPC603e Chapter 9 Power Management provides information about power saving modes for the MPC603e Appendix A PowerPC Instruction Set Listings lists all the PowerPC instructions while indicating those instructions that are not implemented by the MPC603e it also includes the instructions that are specific to the MPC603e Instructions are grouped according to mnemonic opcode function and form Also included is a quick reference table that contains general information such as the architecture level privilege level and form and indicates if the instruction is 64 bit and optional Appendix B Instructions Not Implemented provides a list of PowerPC instructions not implemented by the MPC603e Appendix C Revision History lists the major differences between Revision 1 Revision 2 and Revision 3 of the MPC603e RISC Microprocessor User s Manual This manual also includes a glossary and an index Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture General Information The following documentation available through Morgan Kaufmann Publishers 340 Pine Street
211. als maintain an orderly process for determining data bus mastership Note that there is no data bus arbitration signal MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc i Ka Signal Descriptions equivalent to the address bus arbitration signal BR bus request because except for address only transactions TS implies data bus requests For a detailed description on how these signals interact see Section 8 4 1 Data Bus Arbitration One special signal DBWO allows the MPC603e to be configured dynamically to write data out of order with respect to read data For detailed information about using DBWO see Section 8 10 Using DBWO 7 2 6 1 Data Bus Grant DBG Input Following are the state meaning and timing comments for the DBG input State Meaning Timing Comments Asserted Indicates that the MPC603e may with the proper qualification assume mastership of the data bus The MPC603e derives a qualified data bus grant when DBG is asserted and DBB DRTRY and ARTRY are negated that is the data bus is not busy DBB is negated there is no outstanding attempt to retry the current data tenure DRTRY is negated and there is no outstanding attempt to perform an ARTRY of the associated address tenure Negated Indicates that the MPC603e must hold off its data tenures Assertion May occur any time to indicate
212. ame 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addx 31 D A B OE 266 Re addcx 31 D A B OE 10 Re addex 31 D A B OE 138 Re addi 14 D A SIMM addic 12 D A SIMM addic 13 D A SIMM addis 15 D A SIMM addmex 31 D A 00000 OE 234 Re addzex 31 D A 00000 OE 202 Re andx 31 S A B 28 Rc andcx 31 S A B 60 Rc andi 28 S A UIMM Appendix A PowerPC Instruction Set Listings For More information On This Product Go to www freescale com Instructions Sorted by Mnemonic Table A 1 Complete Instruction List Sorted by Mnemonic continued Freescale Semiconductor Inc Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 andis 29 S A UIMM bx 18 LI AA LK bcx 16 BO BI BD AA LK bectrx 19 BO BI 00000 528 LK belrx 19 BO BI 00000 16 LK cmp 31 criD O L A B 0 0 cmpi 11 crfD OIL A SIMM cmpl 31 crfD OIL A B 32 0 cmpli 10 crfD OIL A UIMM cntlzdx 1 31 S A 00000 58 Rc cntlzwx 31 S A 00000 26 Rc crand 19 crbD crbA crbB 257 0 crandc 19 crbD crbA crbB 129 0 creqv 19 croD crbA crbB 289 0 crnand 19 crbD crbA crbB 225 0 crnor 19 croD crbA crbB 33 0 cror 19 croD crbA crbB 449 0 crorc 19 crbD crbA crbB 417 0 crxor 19 croD crbA crbB 193 0 dcbf 31 00000 A B 86 0 dcbi 2 31 00000 A B 470 0 debst 31 00000 A B 54 0 dcbt 31 00000 A B 278 0 debist 31 00000 A B 246 0 d
213. ample Code Sequence Freescale Semiconductor Inc 9 3 2 Power Management Software Considerations Because the MPC603e is a dual issue processor with out of order execution capability care must be taken in how the power management modes are entered Furthermore nap and sleep modes require all outstanding bus operations to be completed before the power management mode is entered Section9 4 Example Code Sequence for Entering Processor Sleep Mode provides an example software sequence for putting the MPC603e into sleep mode Normally during system configuration time one of the power management modes would be selected by setting the appropriate HIDO mode bit Later on the power management mode is invoked by setting MSR POW To ensure a clean transition into and out of the power management mode set MSR EE and execute the following code sequence sync mtmsr POW 1 isync loop b loop 9 4 Example Code Sequence for Entering Processor Sleep Mode The following is a sample code sequence for entering MPC603e sleep mode 1 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK set up MPC603e HIDO power management bits EK A He I A I AA I AA A Ie AA A I I AA I I I kkk pO rocessor HID ahd external Interrupt Init Lalizations Asse eer area ea ne set up HID registers for the various processors of this family hid setup taken from minix s mpxPowerPC s mfspr
214. and made available to the snooping device Split transaction A transaction with independent request and response tenures Split transaction bus A bus that allows address and data transactions from different processors to occur independently Stage The term stage is used in two different senses depending on whether the pipeline is being discussed as a physical entity or a sequence of events In the latter case a stage is an element in the pipeline during which certain actions are performed such as decoding the instruction performing an arithmetic operation or writing back the results Typically the latency of a stage is one processor clock cycle Some events such as dispatch write back and completion happen instantaneously and may be thought to occur at the end of a stage An instruction can spend multiple cycles in one stage An integer multiply for example takes multiple cycles in the execute stage When this occurs subsequent instructions may stall An instruction may also occupy more than one stage simultaneously especially in the sense that a stage can be seen as a physical resource for example when instructions are dispatched they are assigned a place in the CQ at the same time they are passed to the execute stage They can be said to occupy both the complete and execute stages in the same clock cycle Stall An occurrence when an instruction cannot proceed to the next stage Static branch prediction Mechanism by whi
215. andwidth The frequent use of misaligned accesses is discouraged because they can compromise the overall performance 2 2 4 Floating Point Operands The MPC603e provides hardware support for all single and double precision floating point operations for most value representations and all rounding modes The PowerPC architecture provides for hardware to implement a floating point system as defined in ANSI IEEE Standard 754 1985 IEEE Standard for Binary Floating Point Arithmetic For detailed information about the floating point execution model refer to Chapter 3 Operand Conventions in the Programming Environments Manual 2 2 5 Effect of Operand Placement on Performance The VEA states that the placement location and alignment of operands in memory affect the relative performance of memory accesses The best performance is guaranteed if memory operands are aligned on natural boundaries To obtain the best performance from the MPC603e the programmer should assume the performance model described in Chapter 3 Operand Conventions in the Programming Environments Manual 2 3 Instruction Set Summary This section describes instructions and addressing modes defined for the MPC603e These instructions are divided into the following functional categories e Integer instructions These include arithmetic and logical instructions For more information see Section 2 3 4 1 Integer Instructions Chapter 2 Programming Model
216. anism by which all instructions in execution are architecturally complete before beginning execution appearing to begin execution of the next instruction Similar to context synchronization but doesn t force the contents of the instruction buffers to be deleted and refetched Exponent In the binary representation of a floating point number the exponent is the component that normally signifies the integer power to which the value two is raised in determining the value of the represented number See also Biased exponent Feed forwarding A MPC603e feature that reduces the number of clock cycles that an execution unit must wait to use a register When the source register of the current instruction is the same as the destination register of the previous instruction the result of the previous instruction is routed to the current instruction at the same time that it is written to the register file With feed forwarding the destination bus is gated to the waiting execution unit over the appropriate source bus saving the cycles which would be used for the write and read Fetch Retrieving instructions from either the cache or main memory and placing them into the instruction queue Floating point register FPR Any of the 32 registers in the floating point register file These registers provide the source operands and destination results for floating point instructions Load instructions move data from memory to FPRs and store instructions
217. ansaction Cache High speed memory containing recently accessed data or instructions subset of main memory Cache block A small region of contiguous memory that is copied from memory into a cache The size of a cache block may vary among processors the maximum block size is one page In PowerPC processors cache coherency is maintained on a cache block basis Note that the term cache block is often used interchangeably with cache line Cache coherency An attribute wherein an accurate and common view of memory is provided to all devices that share the same memory system Caches are coherent if a processor performing a read from its cache is supplied with data corresponding to the most recent value written to memory or to another processor s cache Cache flush An operation that removes from a cache any data from a specified address range This operation ensures that any modified data within the specified address range is written back to main memory This operation is generated typically by a Data Cache Block Flush debf instruction Caching inhibited A memory update policy in which the cache is bypassed and the load or store is performed to or from main memory Cast out A cache block that must be written to memory when a cache miss causes a cache block to be replaced Changed bit One of two page history bits found in each page table entry PTE The processor sets the changed bit if any store is performed into the pag
218. anual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc VEA virtual environment architecture The level of the architecture that describes the memory model for an environment in which multiple devices can access memory defines aspects of the cache model defines cache control instructions and defines the time base facility from a user level perspective Implementations that conform to the PowerPC VEA also adhere to the UISA but may not necessarily adhere to the OEA Virtual address An intermediate address used in the translation of an effective address to a physical address Virtual memory The address space created using the memory management facilities of the processor Program access to virtual memory is possible only when it coincides with physical memory Way A location in the cache that holds a cache block its tags and status bits Word A 32 bit data element Write back A cache memory update policy in which processor write cycles are directly written only to the cache External memory is updated only indirectly for example when a modified cache block is cast out to make room for newer data Write through A cache memory update policy in which all processor write cycles are written to both the cache and memory Glossary of Terms and Abbreviations For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MPC603e RISC Microproc
219. apter assumes that the table search software emulates this exception and refers to this condition as an exception The translation exception conditions defined by the OEA for 32 bit implementations cause either the ISI or the DSI exception to be taken as shown in Table 5 3 Table 5 3 Translation Exception Conditions Condition Description Exception Page fault no PTE found No matching PTE found in page tables and no access ISI exception 1 matching BAT array entry SRR1 1 1 D access DSI exception DSISR 1 1 Block protection violation Conditions described for block in Block Memory access ISI exception Protection in Chapter 7 Memory Management SRR1 4 1 in the Programming Environments Manual S g g D access DSI exception DSISR 4 1 Page protection violation Conditions described for page in Page Memory access ISI exception 2 Protection in Chapter 7 Memory Management SRR1 4 1 in the Programming Environments Manual g g D access DSI exception 2 DSISR 4 1 No execute protection violation Attempt to fetch instruction when SR N 1 ISI exception SRR1 3 1 Instruction fetch from direct store Attempt to fetch instruction when SR T 1 ISI exception segment SRR1 3 1 Data access to direct store segment Attempt to perform load or store including DSI exception including floating point accesses floating point load or store when SR T 1 DSIS
220. ardware Implementation Machine State Processor Version eh General Purpose Registers Register Register Registers HIDO SPR 1008 MSR SPR 287 up SPR 1009 Memory Management Registers Instruction BAT A Software Table Registers Data BAT Registers Search Registers SPR 528 DBATOU SPR 536 SPR 976 SPR 529 DBATOL SPR 537 SPR 977 SPR 530 DBATiU SPR 538 SPR 978 BEE SPR 531 DBATIL SPR539 SPR 979 SPR 532 DBAT2U SPR 540 SPR 980 SPR 533 DBAT2L SPR541 SPR 981 SPR 534 DBAT3U SPR 542 SPR 982 IBAT3L SPR 535 DBAT3L SPR 543 Segment Registers SDR1 Condition Register O ba Floating Point Status Exception Handling Registers Data Address Register DSISR FPSCR DAR SPR 19 Deep SPR 18 SPRGs Save and Restore XER SPR1 SPR 272 SRRO SPR 26 SPR 273 SRR1 SPR 27 Link Register SPR 274 LR SPR 275 o gt lt 5 5 2 O fe 5 3 Q by D Q m Ei SS ine Miscellaneous Registers Time Base Facility For Writing Decrementer SPR 284 DEC SPR 22 USER MODEL VEA SPR 285 TBL TBR 268 Instruction Address External Address TBU TBR 269 Breakpoint Register Register Optional app SPR 1010 SPR 282 Notes These registers are 603e specific PID6 603e and PID7v 603e registers They may not be supported by other PowerPC processors 2Not supported on the EC603e microprocessor Appendix C Revision History For More Information On This Product Go to www freescale com e Semiconducto
221. are set to write back caching allowed and coherency enforced modes WIM 001 The MPC603e on chip data cache is implemented as a four way set associative cache To facilitate external monitoring of the internal cache tags the cache set entry CSE 0 1 signals indicate which cache set is being replaced on read operations Note that these signals are valid only for MPC603e burst operations for all other bus operations CSE 0 1 should be ignored Chapier 8 System Interface Operation For More Information On This Product Go to www freescale com D Freescale Semiconductor Inc Timing Examples p SH CRW Modified Bus Transactions SH Snoop Hit Snoop Push RH Read Hit RM Read Miss CA Cache Line Fill WH Write Hit WM Write Miss SH CRW Snoop Hit Cacheable Read Write SH CIR Snoop Hit Cache Inhibited Read Figure 8 13 MEI Cache Coherency Protocol State Diagram WIM 001 Table 8 10 shows the CSE encodings Table 8 10 CSE 0 1 Signals CSE 0 1 Cache Set Element 00 Set 0 01 Set 1 10 Set 2 11 Set 3 8 5 Timing Examples This section shows timing diagrams for various scenarios Figure 8 14 illustrates the fastest single beat reads possible for the MPC603e This figure shows both minimal latency and maximum single beat throughput By delaying the data bus tenure the latency increases but because of split transaction pipelining the overall throughput is not affec
222. ata dependency the branch is executed by means of static branch prediction and instruction fetching proceeds down the predicted path If the prediction is incorrect when the branch is resolved the IQ and all subsequently executed instructions are purged instructions executed before the predicted branch are allowed to complete and instruction fetching resumes down the correct path There are several situations where instruction sequences create dependencies that prevent a branch instruction from being resolved immediately thereby causing execution of the subsequent instruction stream based on the predicted outcome of the branch instruction The instruction sequences and the resulting action of the branch instruction is described as follows e Anmtspr LR followed by a belr Fetching is stopped and the branch waits for the mtspr to execute e Anmtspr CTR followed by a bectr Fetching is stopped and the branch waits for the mtspr to execute e Anmtspr CTR followed by a be CTR Fetching is stopped and the branch waits for the mtspr to execute e A be CTR followed by another be CTR Fetching is stopped and the second branch waits for the first to be completed e A be CTR followed by a bectr Fetching is stopped and the bectr waits for the first to be completed e A branch LK 1 followed by a branch LK 1 Fetching is stopped and the second branch waits for the first to be completed Note A bl instruction does not have to wait f
223. ata transfer interface between the data cache and the GPRs and FPRs The LSU provides all logic required to calculate effective addresses handle data alignment to and from the data cache and provides sequencing for load and store string and multiple operations As shown in Figure 1 1 the caches provide a 64 bit interface to the instruction fetcher and LSU Write operations to the data cache can be performed on a byte half word word or double word basis The MPC603e bus interface unit BIU receives requests for bus operations from the instruction and data caches and executes the operations according to the MPC603e bus protocol The BIU provides address queues prioritization and bus control logic The BIU also captures snoop addresses for data cache address queue and memory reservation wars and stwex instruction operations The BIU also contains a touch load address buffer used for address compares during load or store operations All the data for the corresponding address queues load and store data queues is located in the data cache The data queues are considered temporary storage for the cache and not part of the BIU On a cache miss the MPC603e cache blocks are loaded in 4 beats of 64 bits each when the MPC603e is configured with a 64 bit data bus when the MPC603e is configured with a 32 bit bus cache block loads are performed with 8 beats of 32 bits each The burst load is performed as critical double word first The data cache is
224. ate MSR ME 0 deiere ch ueceatenseqecnaidaccesassecetnatenseods 4 20 DSI Exception 0x00300 ennesneeesneossessseerseeerosesssesssessserrssorrsoesssseesesssernseo 4 21 KAREN ee CR EE 4 23 External Interrupt UU OUT sssisisssiacsssvedeasasdesaesade secede scaeanteavsd cacanusees enasees 4 23 Alignment Exception Ox00600 ceeseescesesseesseeeeteesceetaneeseeneeneeecaneaes 4 24 Integer Alignment Exceptions 2 2 4 2021eii kale ese 4 25 Load Store Multiple Alignment Exceptions 0 ceeseeseeeeeeeeseeesseenseeeeees 4 26 Program Exception OxOG 70D EE 4 27 IEEE Floating Point Exception Program Exceptions 4 27 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Paragraph Number 4 5 7 2 4 5 8 4 5 9 4 5 10 4 5 11 4 5 11 1 4 5 11 2 4 5 12 4 5 13 4 5 14 4 5 15 4 5 16 5 1 5 1 1 5 1 2 5 1 3 5 1 4 5 1 5 5 1 6 5 1 6 1 5 1 6 2 5 1 7 5 1 8 5 2 5 3 5 4 5 4 1 5 4 1 1 5 4 1 2 5 4 1 3 5 4 2 5 4 3 5 4 3 1 5 4 3 2 5 4 4 5 5 5 5 1 Freescale Semiconductor Inc Contents Page Title Number Illegal Reserved and Unimplemented Instructions Program Eugene 4 28 Floating Point Unavailable Exception Ox00800 ee ceeeeeeeeeseeeseeeeeeeees 4 28 Decrementer Exception Ox00900 sccccssscdeataccsesacsecdedetasaceseraessantansseedenanees 4 28 System Call Exception OXOOCO0 occ eeececeeececseeeeceeeeeceeeeeceneeecneeeeeeeeees 4 29 T
225. ates that no bus error was detected Assertion May be asserted while DBB is asserted and the cycle after TA during a read operation TEA should be asserted for one cycle only Negation TEA must be negated no later than the negation of DBB 7 2 9 System Status Signals Most system status signals are input signals that indicate when exceptions are received when checkstop conditions have occurred and when the MPC603e must be reset The MPC603e generates the output signal CKSTP_OUT when it detects a checkstop condition For a detailed description of these signals see Section 8 7 Interrupt Checkstop and Reset Signals 7 2 9 1 Interrupt INT Input Following are the state meaning and timing comments for the INT input State Meaning Timing Comments Asserted The MPC603e initiates an interrupt if MSR EE is set otherwise the MPC603e ignores the interrupt To guarantee that the MPC603e takes the external interrupt INT must be held asserted until the MPC603e takes the interrupt Negated Indicates that normal operation should proceed See Section 8 7 1 External Interrupts Assertion May occur at any time and may be asserted asynchronously to the input clocks The INT input is level sensitive Negation Should not occur until interrupt is taken 7 2 9 2 System Management Interrupt SMI Input Following are the state meaning and timing comments for the SMI input State Meaning Asserted Th
226. ath may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part ey 2 freescale For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Overview Programming Model Instruction and Data Cache Operation Exceptions Memory Management Instruction Timing Signal Descriptions System Interface Operation Power Management PowerPC Instruction Set Listings Instructions Not Implemented Revision History Glossary of Terms and Abbreviations Index For More Information On This Product Go to www freescale com Q O L IND aCe S t ye de amp C gt N on EN O fey e Q GG INID Freescale Semiconductor Inc Overview Programming Model Instruction and Data Cache Operation Exceptions Memory Management Instruction Timing Signal Descriptions System Interface Operation Power Management PowerPC Instruction Set Listings Instructions
227. ation low cost and the high performance attributes of the MPC603 It also provides the system designer additional capabilities through higher processor clock speeds to 100 MHz increases in cache size 16 Kbyte instruction and data caches and set associativity four way and greater system clock flexibility The following sections describe the differences between the MPC603 and MPC603e that affect the system designer and programmer already familiar with the operation of the MPC603 The design enhancements to the MPC603e are described in the following sections as changes that can require a modification to the hardware or software configuration of a system designed for the MPC603 1 1 2 1 Hardware Features The following hardware features of the MPC603e may require modifications to MPC603 systems 1 1 2 1 1 Replacement of XATS Signal by CSE1 Signal The MPC603e employs four way set associativity for both the instruction and data caches in place of the two way set associativity used in the MPC603 This change requires the use of an additional cache set entry CSE1 signal to indicate which member of the cache set is being loaded during a cache line fill CSE1 on the MPC603e is in the same pin location as XATS on the MPC603 Note that XATS is no longer needed by the MPC603e because support for access to direct store segments has been removed Table 1 1 shows the CSE 0 1 signal encoding indicating the cache set element selected during a ca
228. ations are required because the data cache is a write back cache Since instruction fetching bypasses the data cache changes to items in the data cache may not be reflected in memory until the fetch operations complete Special care must be taken to avoid coherency paradoxes in systems that implement unified secondary caches and designers should carefully follow the guidelines for maintaining cache coherency that are provided in the VEA and discussed in Chapter 5 Cache Model and Memory Coherency in the Programming Environments Manual Because the MPC603e does not broadcast the M bit for instruction fetches external caches are subject to coherency paradoxes 2 3 4 3 2 Integer Load and Store Address Generation Integer load and store operations generate effective addresses using register indirect with immediate index mode register indirect with index mode or register indirect mode See Section 2 3 2 3 Effective Address Calculation Note that the MPC603e is optimized for load and store operations that are aligned on natural boundaries and operations that are not naturally aligned may suffer performance degradation Refer to Section 4 5 6 1 Integer Alignment Exceptions 2 3 4 3 3 Register Indirect Integer Load Instructions For integer load instructions the byte half word word or double word addressed by the EA is loaded into rD Many integer load instructions have an update form in which rA is updated with the generate
229. ations i ccsac cecal caceccdycseceivsaseceaseestdesancaceenduceesadecatestes 8 37 32 Bit Data Bus Mod vici cc cejedetsnntainged nti neni died ASSEN 8 37 No DRIRY EE 8 39 Reduced Pimnout Mode ug sgei ged ee des seers iaeiaiai 8 40 Interrupt Checkstop and Reset Signals 4 2 eae geed 8 40 te Interrupts eege eege Eege Ee 8 40 CHEE RSIODS EE 8 40 LEE 8 41 System Quiesce Control Sigtials 1 2335 usssecvessccees secdaaselesiadepsuside sees Ode 8 41 Processor st te Signals 4 5 ceat outs ee 8 41 Support for the Iwarx stwex Instruction Par 8 41 PEBISYNG e EE 8 42 IEEE 1149 1 Compliant Aug E 8 42 IEEE 1149 1 Interface Description c cccccsssesssccsesescesssstsensncssseccesasecenseess 8 42 Using DBWO EE 8 43 Chapter 9 Power Management ON BATA EE TEE EEEE E E E EE TE 9 1 Dynamic Power Manageme nt i sccceassceseiccssesscesvsscdentacesteacs sntecesesecsaaneaesdcctasecees 9 1 Programmable Power Moes geseet geit Seege dude ue Eege 9 2 Power Management Modes sivscissscacsissevcasisessadsaspaccseatscseusnavevaceustceedenseaveaneteases 9 3 Full Power Mode with DPM Disabled 00 0 0 cee eeeeeeeeeeeeeeeeeceeeeeeeteeeesaeees 9 3 Full Power Mode with DPM Enabled 00 eeecceeecceeeseceeetececeeeeeeeteeeeeaeees 9 3 Doze MOE samsa e atta cn laa tan tia at a N sede 9 3 Wap MOUS terrenora or Eo aT EEEE o groe 9 4 Sleep Mole sapeaceuviedeeatuag laces n a e e R S E AA steeds Ea 9 5 Power Management Software Constderatons 9 6 Example Code
230. beats of 64 bits each when the MPC603e is configured with a 64 bit data bus When the MPC603e is configured with a 32 bit bus cache block loads are performed with eight beats of 32 bits each The burst load is performed as critical double word first The data cache is blocked to internal accesses until the load completes the instruction cache allows sequential fetching during a cache block Chapter 1 Overview For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Implementation Specific Information load In the PID7t 603e the critical double word is simultaneously written to the cache and forwarded to the requesting unit thus minimizing stalls due to load delays To ensure coherency among caches in a multiprocessor or multiple caching device implementation the MPC603e implements the MEI protocol The following three states indicate the state of the cache block e Modified The cache block is modified with respect to system memory that is data for this address is valid only in the cache and not in system memory e Exclusive This cache block holds valid data that is identical to the data at this address in system memory No other cache has this data e Invalid This cache block does not hold valid data Cache coherency is enforced by on chip bus snooping logic Because the MPC603e data cache tags are single ported a simultaneous load or store and snoop access represents a resource con
231. bility afforded by a large virtual address space 52 bits MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Segment Model The segment page address translation mechanism may be superseded by the BAT mechanism described in Section 5 3 Block Address Translation If not the translation proceeds in the following two steps 1 From effective address to the virtual address which never exists as a specific entity but can be considered to be the concatenation of the virtual page number and the byte offset within a page 2 From virtual address to physical address This section highlights those areas of the memory segment model defined by the OEA that are specific to the MPC603e 5 4 1 Page History Recording Referenced R and changed C bits reside in each PTE to keep history information about the page They are maintained by a combination of the MPC603e hardware and the table search software The operating system uses this information to determine which areas of memory to write back to disk when new pages must be allocated in main memory Referenced and changed recording is performed only for accesses made with page address translation and not for translations made with the BAT mechanism or for accesses that correspond to direct store interface T 1 segments Furthermore R and C bits are maintained only for accesses made while address
232. bited WIM x1x Potential cache accesses from the bus snoop and cache operations are ignored In the disabled state for the L1 caches the cache tag state bits are ignored and all accesses are propagated to the L2 cache or bus as single beat transactions For those transactions however CI reflects the original state determined by address translation regardless of cache disabled status DCE is zero at power up 1 The data cache is enabled Appendix C Revision History For More information On This Product Go to www freescale com e Semiconductor Inc F Revision Changes From narsescale Se Table 2 2 HIDO Bit Functions continued Bit Name Function 18 ILOCK2 Instruction cache lock 0 Normal operation 1 Instruction cache is locked A locked cache supplies data normally on a hit but are treated as a cache inhibited transaction on a miss On a miss the transaction to the bus or the L2 cache is single beat however Cl still reflects the original state as determined by address translation independent of cache locked or disabled status To prevent locking during a cache access an isync instruction must precede the setting of ILOCK 19 DLOCK2 Data cache lock 0 Normal operation 1 Data cache is locked A locked cache supplies data normally on a hit but is treated as a cache inhibited transaction on a miss On a miss the transaction to the bus or the L2 cache is single beat however Cl still re
233. bled and disabled through bits in the HIDO register as described in Table 2 2 e System reset exceptions cannot be masked 4 2 3 Steps for Exception Processing After it is determined that the exception can be taken by confirming that any instruction caused exceptions occurring earlier in the instruction stream have been handled and by confirming that the exception is enabled for the exception condition the processor does the following 1 The machine status save restore register 0 SRRO is loaded with an instruction address that depends on the type of exception See the individual exception description for details about how this register is used for specific exceptions 2 SRRI1 1 4 10 15 are loaded with information specific to the exception type Chapter 4 Exceptions For More Information On This Product Go to www freescale com Exception Processing Freescale Semiconductor Inc 3 SRR1 5 9 16 31 are loaded with a copy of the corresponding bits of the MSR 4 The MSR is set as described in Table 4 6 The new values take effect beginning with the fetching of the first instruction of the exception handler routine located at the exception vector address Note that MSR IR and MSR DR are cleared for all exception types therefore address translation is disabled for both instruction fetches and data accesses beginning with the first instruction of the exception handler routine Instruction fetch and execution resum
234. bled for the invalidation to occur 1 An invalidate operation is issued that marks the state of each instruction cache block as invalid without writing back modified cache blocks to memory Cache access is blocked during this time Bus accesses to the cache are signaled as a miss during invalidate all operations Setting ICFI clears all the valid bits of the blocks and the PLRU bits to point to way LO of each set For MPC603e processors the proper use of the ICFI and DCFI bits is to set them and clear them with two consecutive mtspr operations MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Register Set Table 2 2 HIDO Bit Functions continued Bits Name Function 21 DCFI Data cache flash invalidate 0 The data cache is not invalidated The bit is cleared when the invalidation operation begins usually the next cycle after the write operation to the register The data cache must be enabled for the invalidation to occur 1 An invalidate operation is issued that marks the state of each data cache block as invalid without writing back modified cache blocks to memory Cache access is blocked during this time Bus accesses to the cache are signaled as a miss during invalidate all operations Setting DCFI clears all the valid bits of the blocks and the PLRU bits to point to way LO of each set For MPC603e processors the p
235. block corresponding to that address was used least recently See Set associative Set associative Aspect of cache organization in which the cache space is divided into sections called sets The cache controller associates a particular main memory address with the contents of a particular set or region within the cache Shadowing Shadowing allows a register to be updated by instructions that are executed out of order without destroying machine state information Signaling NaN A type of NaN that generates an invalid operation program exception when it is specified as arithmetic operands See Quiet NaN Significand The component of a binary floating point number that consists of an explicit or implicit leading bit to the left of its implied binary point and a fraction field to the right Simplified mnemonics Assembler mnemonics that represent a more complex form of a common operation Slave The device addressed by a master device The slave is identified in the address tenure and is responsible for supplying or latching the requested data for the master during the data tenure Snooping Monitoring addresses driven by a bus master to detect the need for coherency actions MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Snoop push Response to a snooped transaction that hits a modified cache block The cache block is written to memory
236. block is transferred in order oct word aligned Critical double word first fetching on a cache miss applies to both the data and instruction cache Chapter 3 Instruction and Data Cache Operation For More Information On This Product Go to www freescale com Memory ManagementCache EE SE Mt se Bemisond tor Inc MPC603e Cache Address Bits 27 28 00 01 10 11 A B C D If the address requested is in double word A the address placed on the bus is that of double word A and the four data beats are ordered in the following manner Beat If the address requested is in double word C the address placed on the bus will be that of double word C and the four data beats are ordered in the following manner Beat C D A B Figure 3 3 Double Word Address Ordering Critical Double Word First 3 4 3 Access to Direct Store Segments The MPC603e does not provide support for access to direct store segments Operations attempting to access a direct store segment will invoke a DSI exception See Section 4 5 3 DSI Exception 0x00300 3 5 Memory Management Cache Access Mode Bits W I M and G Some memory characteristics can be set on either a block or page basis by using the WIMG bits in the BAT registers or page table entry PTE respectively The WIMG attributes control the following functionality e Write through W bit e Caching inhibited I bit e Memory coherency
237. blocked to internal accesses until the load completes the instruction cache allows sequential fetching during a cache block load In the PID7t 603e the critical double word is simultaneously written to the cache and forwarded to the requesting unit thus minimizing stalls due to load delays Note that the cache being filled cannot be accessed internally until the fill completes When address translation is enabled the memory access is performed under the control of the page table entry used to translate the effective address Each page table entry and BAT contains four mode control bits W I M and G that specify the storage mode for all accesses translated using that particular page table entry The W write through and I caching inhibited bits control how the processor executing the access uses its own cache The M memory coherence bit specifies whether the processor executing the access must MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Ings nization and Conirol use the MEI modified exclusive or invalid cache coherence protocol to ensure all copies of the addressed memory location are kept consistent The G guarded memory bit controls whether out of order data and instruction fetching is permitted 3 The MPC603e maintains data cache coherency in hardware by coordinating activity between the data cache memory system and bus interface logic
238. by the memory unit and the system interface to access external memory The MMU also directs the address translation and enforces the protection hierarchy programmed by the operating system in relation to the supervisor user privilege level of the access and in relation to whether the access is a load or store For instruction fetches the IMMU looks for the address in the ITLB and in the IBAT array If an address hits both the IBAT array translation is used Data accesses cause a lookup in the DTLB and DBAT array In most cases the translation is in a TLB and the physical address bits are readily available to the on chip cache The DBAT also is chosen if the translation is in both a DBAT and TLB When the EA misses in the TLBs the MPC603e provides hardware assistance for software to perform a search of the translation tables in memory The hardware assist consists of the following features e Automatic storage of the missed effective address in IMISS and DMISS e Automatic generation of the primary and secondary hashed real address of the page table entry group PTEG which are readable from the HASH1 and HASH register locations The HASH data is generated from the contents of the IMISS or DMISS register The register that is selected depends on the miss instruction or data that was last acknowledged e Automatic generation of the first word of the page table entry PTE of the tables being searched e Areal page address RPA registe
239. c addmex 011111 D A 00000 JOE 0011101010 Rc mullwx 011111 D A B OE 0011101011 Rc mtsrin 011111 S 00000 B 0011110010 0 debtst 011111 00000 A B 0011110110 0 stbux 011111 S A B 0011110111 0 addx 011111 D A B OE 0100001010 Rc dcbt 011111 00000 A B 0100010110 0 Ihzx 011111 D A B 0100010111 0 eqvx 011111 S A B 0100011100 Rc tlbbie 3 011111 00000 00000 B 0100110010 0 eciwx 011111 D A B 0100110110 0 Ihzux 011111 D A B 0100110111 0 xorx 011111 S A B 0100111100 Rc mfspr4 011111 D spr 0101010011 0 Iwax 011111 D A B 0101010101 0 Ihax 011111 D A B 0101010111 0 tlbbia 3 011111 00000 00000 00000 0101110010 0 mftb 011111 D tbr 0101110011 0 Iwaux 011111 D A B 0101110101 0 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Sorted by Opcode Table A 2 Complete Instruction List Sorted by Opcode continued Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Ihaux 011111 D A B 0101110111 0 sthx 011111 S A B 0110010111 0 orex 011111 S A B 0110011100 Rc sradix 011111 S A sh 1100111011 sh Re slbie 23 011111 00000 00000 B 0110110010 0 ecowx 011111 S A B 0110110110 0 sthux 011111 S A B 0110110111 0 orx 011111 S A B 0110111100 Rc divdux 011111 D A B OE 01110010
240. cale com Fre Instructions Sorted by Opcode escale Semiconductor Inc Table A 2 Complete Instruction List Sorted by Opcode continued Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mtfsfix 11111 crfD 00 00000 IMM 0 0010000110 Rc fnabsxv 11111 00000 B 0010001000 Rc fabsx 11111 00000 B 0100001000 Rc mffsx 11111 00000 000 1001000111 Rc mtfsfx 11111 0 FM B 1011000111 Rc fctidx UA 00000 B 1100101110 Rc fctidzx 11113 00000 B 1100101111 Rc fcfidx 1 11111 00000 B 1101001110 Rc 1 64 bit instruction 2 Supervisor level instruction 3 Optional in the PowerPC architecture 4 Supervisor and user level instruction 5 Load and store string or multiple instruction 6 MPC603e RISC Microprocessor User s Manual MPC603e implementation specific instruction For More Information On This Product Go to www freescale com Freescale Semi onduct er ing Functional Categories A 3 Instructions Grouped by Functional Categories Table A 3 through Table A 30 list the PowerPC instructions grouped by function Table A 3 Integer Arithmetic Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 addx 31 D A B OE 266 Re addcx 31 D A B OE 10 Re addex 31 D A B OE 138 Re addi 14 D A SIMM addic 12 D A SIMM addic 13 D A
241. cbz 31 00000 A B 1014 0 divdx 31 A B OE 489 Re divdux 31 D A B OE 457 Re divwx 31 D A B OE 491 Re divwux 31 D A B OE 459 Rc eciwx 31 D A B 310 0 ecowx 31 S A B 438 0 eieio 31 00000 00000 00000 854 0 eqvx 31 S A B 284 Rc extsbx 31 S A 00000 954 Rc extshx 31 S A 00000 922 Rc extswx 31 S A 00000 986 Re fabsx 63 D 00000 B 264 Re MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor In Sorted by Mnemonic Table A 1 Complete Instruction List Sorted by Mnemonic continued Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 faddx 63 D A B 00000 21 Rc faddsx 59 D A B 00000 21 Rc fcfidx 63 D 00000 B 846 Rc Tempo 63 crfD 00 A B 32 0 fcmpu 63 crfD 00 A B 0 0 fctidx 63 D 00000 B 814 Re fctidzx 63 D 00000 B 815 Re fctiwx 63 D 00000 B 14 Re fctiwzx 63 D 00000 B 15 Re fdivx 63 D A B 00000 18 Re fdivsx 59 D A B 00000 18 Re fmaddx 63 D A B C 29 Rc fmaddsx 59 D A B C 29 Rc fmrx 63 D 00000 B 72 Rc fmsubx 63 D A B C 28 Rc fmsubsx 59 D A B C 28 Rc fmulx 63 D A 00000 C 25 Rc fmulsx 59 D A 00000 C 25 Rc fnabsx 63 D 00000 B 136 Rc fnegx 63 D 00000 B 40 Rc fnmaddx 63 D A B C 31 Rc fnmaddsx 59 D A B C 31 Rc fnmsubx 63 D A B C 30 Rc fnmsubsx 59 D A B C 30 Rc fresx3 59 D 00000
242. centralized control of instruction flow to the execution units The instruction unit determines the address of the next instruction to be fetched based on information from the sequential fetcher and from the BPU The instruction unit fetches the instructions from the instruction cache into the instruction queue The BPU receives branch instructions from the fetcher and uses static branch prediction to allow to fetching from a predicted instruction stream while a conditional branch is evaluated The BPU folds out for unconditional branch instructions and conditional branch instructions unaffected by instructions in the execution pipeline Instructions issued beyond a predicted branch cannot complete execution until the branch is resolved preserving the programming model of sequential execution If any of these are branch instructions they are decoded but not issued Instructions to be executed by the FPU IU LSU and SRU are issued and allowed to progress up to the register write back stage Write back is allowed when a correctly predicted branch is resolved and execution continues along the predicted path If branch prediction is incorrect the instruction unit flushes all predicted path instructions and instructions are issued from the correct path 1 1 3 1 Instruction Queue and Dispatch Unit The instruction queue IQ shown in Figure 1 1 holds as many as six instructions and loads up to two instructions from the instruction unit during a s
243. ception is caused when the effective address for an instruction fetch cannot be translated by the ITLB Data load 01100 A data load translation miss exception is caused when the effective address for a translation miss data load operation cannot be translated by the DTLB Data store 01200 A data store translation miss exception is caused when the effective address for translation miss a data store operation cannot be translated by the DTLB or where a DTLB hit occurs and the change bit in the PTE must be set due to a data store operation Instruction 01300 An instruction address breakpoint exception occurs when the address bits 0 29 address in the IABR matches the next instruction to complete in the completion unit and breakpoint the IABR enable bit bit 30 is set Chapter 4 Exceptions For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Exception Classes Table 4 2 Exceptions and Conditions continued Exception Type Vector Offset Causing Conditions hex System 01400 A system management interrupt is caused when MSR EE 1 and the SMI input management signal is asserted interrupt Reserved 01500 02FFF Exceptions are roughly prioritized by exception class as follows 1 Nonmaskable asynchronous exceptions have priority over all other exceptions system reset and machine check exceptions although the machine check exception condi
244. ch software for example compilers can hint to the machine hardware about the direction a branch is likely to take Superscalar machine A machine that can issue multiple instructions concurrently from a conventional linear instruction stream Supervisor mode The privileged operation state of a processor In supervisor mode software typically the operating system can access all control registers and can access the supervisor memory space among other privileged operations Synchronization A process to ensure that operations occur strictly in order See Context synchronization and Execution synchronization Glossary of Terms and Abbreviations For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Synchronous exception An exception that is generated by the execution of a particular instruction or instruction sequence There are two types of synchronous exceptions precise and imprecise System memory The physical memory available to a processor Tenure The period of bus mastership For the MPC603e there can be separate address bus tenures and data bus tenures A tenure consists of three phases arbitration transfer and termination TLB translation lookaside buffer A cache that holds recently used page table entries Throughput The measure of the number of instructions that are processed per clock cycle Transaction A complete exchange between two bus devices A transacti
245. che Block Push Operation 3 4 Data Cache Transactions on Bus The MPC603e transfers data to and from the data cache in single beat transactions of two words or in four beat transactions of eight words which fill a cache block 3 4 1 Single Beat Transactions Single beat bus transactions can transfer from 1 to 8 bytes to or from the MPC603e Single beat transactions can be caused by cache write through accesses caching inhibited accesses I bit of the WIMG bits for the page is set or accesses when the cache is disabled HIDO DCE bit is cleared and can be misaligned 3 4 2 Burst Transactions Burst transactions on the MPC603e always transfer eight words of data at a time and are aligned to a double word boundary The MPC603e transfer burst TBST output signal indicates to the system whether the current transaction is a single beat transaction or four beat burst transfer Burst transactions have an assumed address order For cacheable read operations or cacheable non write through write operations that miss the cache the MPC603e presents the double word aligned address associated with the load or store instruction that initiated the transaction As shown in Figure 3 3 this quad word contains the address of the load or store that missed the cache This minimizes latency by allowing the critical code or data to be forwarded to the processor before the rest of the block is filled For all other burst operations however the entire
246. che load operation MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc i Overview Table 1 1 CSE 0 1 Signals CSE 0 1 Cache Set Element 00 Set 0 01 Set 1 10 Set 2 11 Set 3 1 1 2 1 2 Addition of Half Clock Bus Multipliers Some of the reserved clock configuration signal settings of the MPC603 are redefined to allow more flexible selection of higher internal and bus clock frequencies The MPC603e provides programmable internal processor clock rates of 1x 1 5x 2x 2 5x 3x 3 5x and 4x multiples of the externally supplied clock frequency For additional information refer to the appropriate device specific hardware specifications 1 1 2 2 Software Features The features of the MPC603e described in the following sections affect software originally written for the MPC603 1 1 2 2 1 16 Kbyte Instruction and Data Caches The MPC603e instruction and data caches are 16 Kbytes twice the size of the MPC603 caches The increase in cache size may require modification of cache flush routines The increase is also reflected in four way set associativity of both caches in place of the two way set associativity in the MPC603 1 1 2 2 2 Clock Configuration Available in HID1 Register HID1 0 3 provides software read only access to the configuration of the PLL_CFG signals HID1 is not implemented in the MPC603 1 1 2 2 3 Perfo
247. chitecture should not assume the existence of mnemonics not described in this document For a complete list of simplified mnemonics see Appendix F Simplified Mnemonics in the Programming Environments Manual 2 3 8 Implementation Specific Instructions This section provides a detailed look at the two MPC603e implementation specific instructions tlbld and tlbli Chapter 2 Programming Model For More information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary tibid tibid Load Data TLB Entry Integer Unit tlbld rB Reserved 31 00000 00000 B 978 0 0 5 6 10 11 15 16 20 21 30 31 EA rB TLB entry created from DCMP and RPA DTLB entry selected by EA 15 19 and SRR1 WAY lt created TLB entry The EA is the contents of rB The tlbld instruction loads the contents of the data PTE compare DCMP and required physical address RPA registers into the first word of the selected data TLB entry The specific DTLB entry to be loaded is selected by the EA and SRRI WAY bit The tlbld instruction should only be executed when address translation is disabled MSR IR 0 and MSR DR 0 Note that it is possible to execute the tlbld instruction when address translation is enabled however extreme caution should be used in doing so If data address translation is set MSR DR 1 tlbld must be preceded by a sync instruction and succeeded by a con
248. ck multiplier These system support functions are described in the following sections 1 1 7 1 Power Management The MPC603e provides four power modes selectable by setting the appropriate control bits in the machine state register MSR and hardware implementation register 0 HIDO The four power modes are as follows e Full power This is the default power state of the MPC603e The MPC603e is fully powered and the internal functional units are operating at the full processor clock speed If the dynamic power management mode is enabled functional units that are idle will automatically enter a low power state without affecting performance software execution or external hardware e Doze All the functional units of the MPC603e are disabled except for the time base decrementer registers and the bus snooping logic When the processor is in doze mode an external asynchronous interrupt system management interrupt decrementer exception hard or soft reset or machine check brings the MPC603e into the full power state The MPC603e in doze mode maintains the PLL in a fully powered state and locked to the system external clock input SYSCLK so a transition to the full power state takes only a few processor clock cycles e Nap tThe nap mode further reduces power consumption by disabling bus snooping leaving only the time base register and the PLL in a powered state The MPC603e returns to the full power state upon receipt of an external asynch
249. contents are used by the MPC603e when calculating the values of HASH1 and HASH2 and by the tlbld and tlbli instructions when loading a new TLB entry Note that the MPC603e always loads DMISS with a big endian address even when MSR LE is set These registers are read and write to the software Effective Page Address Figure 2 4 DMISS and IMISS Registers 2 1 2 3 Data and Instruction TLB Compare Registers DCMP and ICMP DCMP and ICMP shown in Figure 2 5 contain the first word in the required PTE The contents are constructed automatically from the contents of the segment registers and the effective address DMISS or IMISS when a TLB miss exception occurs Each PTE read from the tables during the table search process should be compared with this value to determine if the PTE is a match Upon execution of a tlbld or tlbli instruction the upper MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Register Set 25 bits of the DCMP or ICMP register and 11 bits of the effective address are loaded into the first word of the selected TLB entry These registers are read and write to the software Reserved V VSID 0 API 0 1 24 25 26 31 Figure 2 5 DCMP and ICMP Registers Table 2 5 describes the bit settings for the DCMP and ICMP registers Table 2 5 DCMP and ICMP Bit Settings Bits Name Description
250. ct Go to www freescale com Freescale Semiconductor ING uction S single precision data to double precision format before loading the operands into the target FPR This conversion is described fully in Floating Point Load Instructions in Appendix D Floating Point Models in the Programming Environments Manual Implementation Note The PowerPC architecture defines load with update instructions with rA 0 as an invalid form however the MPC603e treats this case as a valid form Table 2 26 provides a list of the floating point load instructions Table 2 26 Floating Point Load Instructions Name Mnemonic Operand Syntax Load Floating Point Double lfd frD d rA Load Floating Point Double Indexed Ifdx frD rA rB Load Floating Point Double with Update lfdu frD d rA Load Floating Point Double with Update Indexed Ifdux frD rA rB Load Floating Point Single lfs frD d rA Load Floating Point Single Indexed Hey frD rA rB Load Floating Point Single with Update Heu frD d rA Load Floating Point Single with Update Indexed Ifsux frD rA rB 2 3 4 3 10 Floating Point Store Instructions There are three basic forms of the store instruction single precision double precision and integer The integer form is supported by the optional stfiwx instruction Because the FPRs support only double precision format for floating point data the FPU converts double precision data to single precision format befo
251. ct Go to www freescale com Freescale Semiconductor Inc Overview rename registers The MPC603e writes the contents of the rename registers to the appropriate GPR when integer instructions are retired by the completion unit 1 1 4 2 Floating Point Unit FPU The FPU contains a single precision multiply add array and the floating point status and control register FPSCR The multiply add array allows the MPC603e to efficiently implement multiply and multiply add operations The FPU is pipelined so that single and double precision instructions can be issued back to back The 32 FPRs are provided to support floating point operations Stalls due to contention for FPRs are minimized by the automatic allocation of rename registers The MPC603e writes the contents of the rename registers to the appropriate FPR when floating point instructions are retired by the completion unit The MPC603e supports all IEEE 754 floating point data types normalized denormalized NaN zero and infinity in hardware eliminating the latency incurred by software exception routines The term exception is also referred to as interrupt in the architecture specification 1 1 4 3 Load Store Unit LSU The LSU executes all load and store instructions and provides the data transfer interface between the GPRs FPRs and the cache memory subsystem The LSU calculates effective addresses performs data alignment and provides sequencing for load store stri
252. ct operational performance and is transparent to software or any external hardware Chapter 2 Programming Model For More information On This Product Go to www freescale com Register Set Freescale Semiconductor Inc Table 2 2 HIDO Bit Functions continued Bits Name Function 12 15 Reserved should be cleared 16 ICE 2 Instruction cache enable 0 The instruction cache is neither accessed nor updated All pages are accessed as if they were marked cache inhibited WIM x1x Potential cache accesses from the bus Snoop and cache operations are ignored In the disabled state for the L1 caches the cache tag state bits are ignored and all accesses are propagated to the 60x bus as single beat transactions For those transactions however Cl reflects the original state determined by address translation regardless of cache disabled status ICE is zero at power up 1 The instruction cache is enabled 17 DCE Data cache enable 0 The data cache is neither accessed nor updated All pages are accessed as if they were marked cache inhibited WIM x1x Potential cache accesses from the bus Snoop and cache operations are ignored In the disabled state for the L1 caches the cache tag state bits are ignored and all accesses are propagated to the 60x bus as single beat transactions For those transactions however Cl reflects the original state determined by address translation regardless of cache d
253. ction Some registers are accessed both explicitly and implicitly The number to the right of the register name indicates the number that is used in the syntax of the instruction operands to access the register for example the number used to access the XER is SPR1 For more information on the PowerPC register set refer to Chapter 2 Register Set in the Programming Environments Manual The MPC603e user level registers are described as follows e User level registers UISA The user level registers can be accessed by all software with either user or supervisor privileges The user level register set includes the following General purpose registers GPRs The GPR file consists of thirty two 32 bit GPRs designated as GPRO GPR31 This register file serves as the data source or destination for all integer instructions and provides data for generating addresses Floating point registers FPRs The FPR file consists of thirty two 64 bit FPRs designated as FPRO FPR31 which serves as the data source or destination for all floating point instructions These registers can contain data objects of either single or double precision floating point format Before the stfd instruction is used to store the contents of an FPR to memory the FPR must have been initialized after reset explicitly loaded with any value by using a floating point load instruction Condition register CR The CR consists of eight 4 bit fields CRO
254. cution timing 6 5 Memory Performance Considerations Due to the MPC603e instruction throughput of three instructions per clock cycle lack of data bandwidth can become a performance bottleneck For the MPC603e to approach its potential performance levels it must be able to read and write data quickly and efficiently If there are many processors in a system environment one processor may experience long memory latencies while another bus master for example a direct memory access controller is using the external bus To alleviate this possible contention the MPC603e provides three memory update modes copy back write through and cache inhibit Each page of memory is specified to be in one of these modes If a page is in copy back mode data being stored to that page is written only to the on chip cache If a page is in write through mode writes to that page update the on chip cache on hits and always update main memory If a page is cache inhibited data in that page will never be stored in the on chip cache All three of these modes of operation have advantages and disadvantages A decision as to which mode to use depends on the system environment as well as the application The following sections describe how performance is impacted by each memory update mode For details about the operation of the on chip cache and the memory update modes see Chapter 3 Instruction and Data Cache Operation MPC603e RISC Microprocessor User s Ma
255. cycle 7 instruction 6 completes instruction 7 is in the second FPU execute stage and although instruction 8 has executed it must wait for instruction 7 to complete Instruction 9 dispatches to the IU Instructions 10 and 11 move down in the IQ Fetching resumes with instructions 13 and 14 8 Incycle 8 instruction 7 is in the third FPU execute stage Instructions 8 and 9 have executed and they remain in the CQ until instruction 7 completes Instruction 10 is dispatched to the IU 9 Incycle 9 instruction 7 completes allowing instruction 8 to complete Because the CQ is full instructions 12 and 13 cannot be dispatched 10 In cycle 10 instructions 9 and 10 complete Instruction 11 has executed but cannot exit the CQ from CQ2 Instructions 12 and 13 are dispatched to the FPU and IU respectively Instruction 14 drops into IQO 11 In cycle 11 instruction 11 completes and instruction 12 is in the second FPU execute stage Instruction 13 has executed but must remain in the CQ until instruction 12 completes Instruction 14 enters the first FPU execute stage 6 3 2 3 Cache Miss Figure 6 6 shows an instruction fetch that misses the on chip cache and shows how that fetch affects the instruction dispatch Note that a processor bus clock ratio of 1 2 is used The same instruction sequence is used as in Section 6 3 2 2 Cache Hit A cache miss extends the latency of the fetch stage so in this example the fetch stage represents not only th
256. cycles necessary to execute an instruction and make ready the results of that execution for a subsequent instruction e Pipeline In the context of instruction timing the term pipeline refers to the interconnection of the stages The events necessary to process an instruction are broken into several cycle length tasks to allow work to be performed on several instructions simultaneously analogous to an assembly line As an instruction is processed it passes from one stage to the next When it does the stage becomes available for the next instruction Although an individual instruction may take many cycles to complete the number of cycles is called instruction latency pipelining makes it possible to overlap the processing so that the throughput number of instructions completed per cycle is greater than if pipelining were not implemented e Program order tThe order of instructions in an executing program More specifically this term is used to refer to the original order in which program instructions are fetched into the instruction queue from the cache e Rename register Temporary buffers used by instructions that have finished execution but have not completed e Reservation station A buffer between the dispatch and execute stages that allows instructions to be dispatched even though the results of instructions on which the dispatched instruction may depend are not available e Retirement Removal of the completed instruction f
257. d MSR POW 0 EE 0 FEO 0 IR 0 TGPR 0 PR 0 SE 0 DR 0 ILE FP 0 BE 0 RI 0 IP ME FE1 0 LE Set to value of ILE 4 5 2 Machine Check Exception 0x00200 The MPC603e conditionally initiates a machine check exception after detecting the assertion of the TEA or MCP signals on the MPC603e bus assuming the machine check is enabled with MSR ME 1 The assertion of one of these signals indicates that a bus error occurred and the system terminates the current transaction One clock cycle after the signal is asserted the data bus signals go to the high impedance state however data entering the GPR or the cache is not invalidated Note that if HIDO EMCP is cleared the processor ignores the assertion of the MCP signal A machine check exception also occurs when an address or data parity error is detected on the bus and the address or data parity error is enabled in HIDO See Section 2 1 2 1 Hardware Implementation Registers HIDO and HID1 for more information Note that the MPC603e makes no attempt to force recoverability on a machine check however it does guarantee that the machine check exception is always taken immediately upon request with a nonpredicted address saved in SRRO regardless of the current machine state Because pending stores in the completed store queue are not canceled when a machine check exception occurs two consecutive stores that result in the assertion of TEA can cause the processor to
258. d After the INT is recognized the MPC603e generates a recoverable halt to instruction completion The MPC603e allows the next instruction in program order to complete including handling any exceptions that instruction may generate However the MPC603e blocks subsequent instructions from completing and allows any outstanding stores to occur to system memory If any other exceptions are encountered in this process they are taken first and the external interrupt is delayed until a recoverable halt is achieved At this time the MPC603e saves the state information and takes the external interrupt as defined by the PowerPC architecture The register settings for the external interrupt are shown in Table 4 13 Chapter 4 Exceptions For More Information On This Product Go to www freescale com Se Freescale Semiconductor Inc Exception Definitions Table 4 13 External Interrupt Register Settings Register Setting SRRO Set to the effective address of the instruction that the processor would have attempted to execute next if no interrupt conditions were present SRR1 0 15 Cleared 16 31 Loaded from MSR 16 31 MSR POW 0 EE 0 FEO 0 IR 0 TGPR 0 PR 0 SE 0 DR 0 ILE FP 0 BE 0 RI 0 IP ME FE1 0 LE Set to value of ILE When an external interrupt is taken instruction execution for the handler begins at offset 0x00500 from the physical base address indicated by MSR IP The MPC603e only recognizes the in
259. d e A little endian access MSR LE 1 is misaligned e A multiple or string access is attempted with the MSR LE bit set e The operand of a floating point load or store operation is to a direct store segment e The operand of an elementary multiple or string load or store crosses a segment boundary with a change to the direct store attribute T bit different e The operand of a eciwx or ecowx instruction is not aligned PID7t 603e only MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc utes Exception Definitions e The operand of a debz instruction is in a page that is write through or caching inhibited The register settings for alignment exceptions are shown in Table 4 13 The architecture does not support the use of a misaligned EA by Iwarx or stwex instructions If one of these instructions specifies a misaligned EA the exception handler should not emulate the instruction but should treat the occurrence as a programming error Table 4 14 Alignment Interrupt Register Settings Register Setting SRRO Set to the effective address of the instruction that caused the exception SRR1 0 15 Cleared 16 31 Loaded from MSR 16 31 MSR POW 0 FE 0 FEO 0 IR 0 TGPR 0 PR 0 SE 0 DR 0 ILE FP 0 BE 0 RI 0 IP ME FE1 0 LE Set to value of ILE DSISR 0 11 Cleared 12 13 Cleared Note that these bits can be set by several 64 b
260. d address saved in SRRO regardless of the current machine state Any pending stores in the completed store queue are canceled when the exception is taken Software can use the machine check exception in a recoverable mode for checking bus configuration For this case a syne load syne instruction sequence is used A subsequent machine check exception at the load address indicates a bus configuration problem and the processor is in a recoverable state With the following three paragraphs A machine check exception also occurs when an address or data parity error is detected on the bus and the address or data parity error is enabled in HIDO See Section 2 1 2 1 Hardware Implementation Registers HIDO and HID1 for more information Note that the MPC603e makes no attempt to force recoverability on a machine check however it does guarantee that the machine check exception is always taken immediately upon request with a Appendix C Revision History For More Information On This Product Go to www freescale com e Semiconductor Inc F Revision Changes From narsescale Se 5 5 2 2 2 5 42 5 5 2 2 2 5 45 nonpredicted address saved in SRRO regardless of the current machine state Because pending stores in the completed store queue are not canceled when a machine check exception occurs two consecutive stores that result in the assertion of TEA can cause the processor to checkstop To prevent a checkstop in this case a syn
261. d ecowx may be interrupted by an eciwx bus operation and vice versa The MPC603e does guarantee that the two operations associated with a misaligned ecowx will not be interrupted by another ecowx operation and likewise for eciwx Because a misaligned external control address is considered a programming error the system may choose to assert TEA or otherwise cause an exception when a misaligned external control bus operation occurs 8 3 2 6 Transfer Code TC 0 1 Signals The TCO and TC1 signals provide supplemental information about the corresponding address Note that the TCx signals can be used with the TT 0 4 and TBST signals to further define the current transaction Table 8 9 shows the encodings of the TCO and TC1 signals Table 8 9 Transfer Code Encoding TC 0 1 Read Write 00 Data transaction Any write 01 Touch load N A 10 Instruction fetch N A 11 Reserved N A 8 3 3 Address Transfer Termination The address tenure of a bus operation is terminated when completed with the assertion of AACK or retried with the assertion of ARTRY The MPC603e does not terminate the address transfer until the AACK address acknowledge input is asserted therefore the system can extend the address transfer phase by delaying the assertion of AACK to the MPC603e AACK can be asserted as early as the bus clock cycle following TS see Figure 8 6 which allows a minimum address tenure of two bus cycles However whe
262. d effective address For these forms the EA is placed into rA and the memory element byte half word word or double word addressed by EA is loaded into rD Implementation Note In some implementations the load half word algebraic instructions lha and has and the load with update Ibzu Ibzux Ihzu lhzux Ihau lhaux Iwu and Iwux instructions may execute with greater latency than other types of load instructions In the MPC603e these instructions operate with the same latency as other load instructions Table 2 21 lists the integer load instructions MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING uction E Table 2 21 Integer Load Instructions Name Mnemonic Operand Syntax Load Byte and Zero Ibz rD d rA Load Byte and Zero Indexed Ibzx rD rA rB Load Byte and Zero with Update Ibzu rD d rA Load Byte and Zero with Update Indexed Ibzux rD rA rB Load Half Word Algebraic Iha rD d rA Load Half Word Algebraic Indexed Ihax rD rA rB Load Half Word Algebraic with Update Ihau rD d rA Load Half Word Algebraic with Update Indexed Ihaux rD rA rB Load Half Word and Zero Ihz rD d rA Load Half Word and Zero Indexed Ihzx rD rA rB Load Half Word and Zero with Update Ihzu rD d rA Load Half Word and Zero with Update Indexed Ihzux rD rA rB Load Word and Zero Iwz rD d rA Load Word and Zero I
263. d to take an external interrupt system management interrupt or decrementer interrupt 17 PR Privilege level 0 The processor can execute both user and supervisor level instructions 1 The processor can only execute user level instructions Chapter 4 Exceptions For More Information On This Product Go to www freescale com Exception Processing Freescale Semiconductor Inc Table 4 6 MSR Bit Settings continued Bits Name Description 18 FP Floating point available 0 The processor prevents dispatch of floating point instructions including floating point loads stores and moves 1 The processor can execute floating point instructions and can take floating point enabled exception type program exceptions 19 ME Machine check enable 0 Machine check exceptions are disabled 1 Machine check exceptions are enabled 20 FEO Floating point exception mode 0 see Table 4 7 21 SE Single step trace enable 0 The processor executes instructions normally 1 The processor generates a trace exception upon the successful completion of the next instruction 22 BE Branch trace enable 0 The processor executes branch instructions normally 1 The processor generates a trace exception upon the successful completion of a branch instruction 23 FE1 Floating point exception mode 1 see Table 4 7 24 Reserved 25 Exception prefix The set
264. dary scan logic are not used under typical operating conditions Detailed discussion of the MPC603e test functions is beyond the scope of this document however sufficient information has been provided to allow the system designer to disable the test functions that would impede normal operation The COP scan interface is shown in Figure 7 2 For more information see Section 8 9 IEEE 1149 1 Compliant Interface gt TDI Test Data Input gt TMS Test Mode Select gt TCK Test Clock Input _ TDO Test Data Output gt TRST Test Reset Figure 7 2 IEEE 1149 1 Compliant Boundary Scan Interface 7 2 11 Pipeline Tracking Support The MPC603e provides for nonintrusive instruction pipeline tracking Setting HIDO EICE causes the address parity and data parity signals to be redefined as outputs providing pipeline tracking information These signals toggle at the CPU clock rate and have special loading and timing requirements when in this mode Table 7 8 shows the outputs when HIDO EICE is set Table 7 8 Pipeline Tracking Outputs Bits Function Encoding DP 0 1 Fetch 00 None 01 Two 10 One 11 Branch DP 2 3 Retire 00 None 01 Two 10 One 11 Exception DP 4 5 Fold 00 None 01 First 10 Second 11 Both MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Se
265. data cache transactions 3 9 instruction cache fill operations 3 4 overview 1 13 3 1 response to bus transactions 3 20 Cache unit memory performance 6 22 operation of the cache 8 2 overview 3 1 Cache inhibited accesses I bit cache interactions 3 10 I bit setting 3 12 timing considerations 6 23 Changed C bit maintenance recording 5 11 5 21 5 23 Checkstop signal 7 24 8 40 state 4 21 CI signal 7 13 Classes of instructions 2 17 Clean block operation 3 20 Clock signals CLK_OUT 7 30 PLL_CFGan 7 30 SYSCLK 7 29 Compare instructions 2 28 A 16 Completion definition 6 1 Completion considerations 6 15 Context synchronization 2 21 Conventions xxxi XXXV 2 13 COP scan interface 7 27 Copy back mode 6 23 CR logical instructions 2 37 CSEn signals 7 14 8 29 D Data bus 32 bit data bus mode 8 37 arbitration signals 7 16 8 7 bus arbitration 8 21 data tenure 8 7 data transfer 7 18 8 23 data transfer termination 7 21 8 24 Data cache basic operations 3 8 broadcasting 3 7 bus transactions 3 9 cache control 3 6 configuration 3 1 DCFI DCE DLOCK bits 3 6 disabling 3 7 fill operations 3 8 locking 3 7 organization 3 6 touch load operations 3 8 touch load support 3 8 Data storage interrupt DSI see DSI exception Data TLB miss on load exception 4 31 Data TLB miss on store exception 4 32 Data transfers alignment 2 14 8 14 burst ordering 8 13 eciwx and
266. dcbst LE No change None dcbst M E Write Block is pushed dcbz l M Write with kill dcbz E M M Kill block Writes over modified data dcbt l No change Read Fetched cache block is stored in touch load queue dcbt E M No change None dcbtst l No change Read with intent Fetched cache block is stored in touch load to modify queue dcbtst E M No change None Note that Table 3 7 assumes that the WIM bits are set to 001 that is since the cache is operating in write back mode caching is permitted and coherency is enforced Table 3 7 does not include noncacheable or write through cases nor does it completely describe the mechanisms for the operations described For more information see Section 3 10 MEI State Transactions For detailed information on the cache control instructions refer to Chapter 2 Programming Model in this book and Chapter 8 Instruction Set in the Programming Environments Manual The MPC603e contains snooping logic to monitor the bus for these commands and the control logic required to keep the cache and the memory queues coherent For additional details about the specific bus operations performed by the MPC603e see Chapter 8 System Interface Operation 3 9 Bus Interface The bus interface buffers bus requests from the instruction and data caches and executes the requests per the MPC603e bus protocol It includes address register queues prioritization logic and bus control logic T
267. ddress Register RPA ceceeeeeseceeeeeseeereeenneee 5 35 Software Table Search Operation cee ceeeeeseesseceseeeseeesseessaeceseeeseeeenees 5 36 Flow for Example Exception Handlers A 5 36 Code for Example Exception Handlers AA 5 40 Pare Table Be EE 5 47 Segment Register Bee E 5 47 Chapter 6 Instruction Timing Terminology and Conventions is00h tiaeiek ceased au nei ade needles 6 1 Instruction Timing COVERY LOW eg eer enee 6 3 THming COnmsiderati gece tege R a TA a R EEEE aE 6 7 General Instruction EE 6 8 Instruction Fetch TMINE eegene 6 10 Cach Arbitration EE 6 10 Cache DEE 6 10 CACC MISS 22h cies os eet EE 6 13 Instruction Dispatch and Completion Considerations sseeeeeeeeeseeeeeeeeeeeeee 6 15 Rename Register EE 6 15 Gute Te EE e 6 16 Execution Unit Considerations egen eet Age ee 6 17 Execution Unit Timings fsjccccascasbacassuaeaccuds EE deele dee a a xs 6 17 Branch Processing Unit Execution Tmmg cee ceeesseeesseceseceeeeeeseeenaeenes 6 17 Branch ee WE 6 17 Static Branch e i oriee ete ote Res 6 18 Predicted Branch Timing Examples 1i 3 i cocteccecisettadidealcccueisecees 6 19 Integer Unit Execution Timing eeseseeseesreeseeressereresressersresrreseesersereseesreseresee 6 21 Floating Point Unit Execution Timing eeseeeseeeeesesssseressresresressersresressessresees 6 21 Load Store Unit Execution Tmmng 6 22 System Register Unit Execution Timing cesccesoresscereeecenseeseeeeseeteees 6
268. ddress bus masters assert GBL to indicate that the current transaction is a global access that is an access to memory shared by more than one device If GBL is not asserted for the transaction that transaction is not snooped When other devices detect the GBL input asserted they must respond by snooping the broadcast address MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Bus Tenure Normally GBL reflects the M bit value specified for the memory reference in the corresponding translation descriptor Note that care must be taken to minimize the number of pages marked as global because the retry protocol discussed in the previous section is used to enforce coherency and can require significant bus bandwidth When the MPC603ce is not the address bus master GBL is an input The MPC603e snoops a transaction if TS and GBL are asserted together in the same bus clock cycle this is a qualified snooping condition No snoop update to the MPC603e cache occurs if the snooped transaction is not marked global This includes invalidation cycles When the MPC603e detects a qualified snoop condition the address associated with the TS is compared against the data cache tags Snooping completes if no hit is detected However if the address hits in the cache the MPC603e reacts according to the MEI protocol shown in Figure 8 13 assuming the WIM bits
269. defines instructions for controlling both the instruction and data caches when they exist The MPC603e interprets the cache control instructions icbi debi dcbt dcbz dcbst as if they pertain only to the MPC603e caches They are not intended for use in managing other caches in the system The debz instruction causes an address only broadcast on the bus if the contents of the block are from a page marked global through the WIMG bits This broadcast is performed for coherency reasons the debz instruction is the only cache control instruction that can allocate and take new ownership of a line Note that if the HIDO ABE bit is set on a PID7t 603e processor the execution of the debf debi and debst instructions will also cause an address only broadcast The debz instruction is also the only cache operation that is snooped by the MPC603e The cache instructions are intended primarily for the management of the on chip cache and do not perform address only broadcasts for the maintenance of other caches in the system The ability of the PID7t 603e to optionally perform address only broadcasts when executing the debi dcbf and the debst instructions allows the coherency management of an external copy back L2 cache The other instructions do not broadcast either for the purpose of invalidating or flushing other caches in the system or for managing system resources Any bus activity caused by these instructions is the direct result of performing the operat
270. dex to select a set Bits A27 A31 select a byte within a block The tags consists of bits PAO PA19 Address translation occurs in parallel such that higher order bits the tag bits in the cache are physical Note that the replacement algorithm is strictly an LRU algorithm that is the least recently used block is filled with new data on a cache miss Chapter 3 Instruction and Data Cache Operation For More Information On This Product Go to www freescale com Data Cache Organization Frees cale Semiconductor Inc 128 Sets Block 0 Address Tag 0 i ae Words 0 7 R eee eat veer H pe weaker TTL voie L Ee 8 Words Block Figure 3 2 Data Cache EE Block 1 Block 2 Block 3 3 2 2 Data Cache Fill Operations When the MPC603e is configured with a 64 bit data bus cache blocks are loaded in 4 beats of 64 bits each When the MPC603e is configured with a 32 bit bus cache block loads are performed with 8 beats of 32 bits each The burst load is performed as critical double word first The data cache is blocked to internal accesses until the load completes In the PID7t 603e the critical double word is simultaneously written to the cache and forwarded to the requesting unit thus minimizing stalls due to load delays 3 2 3 Data Cache Control The MPC603e provides several means of data cache control through the use of the WIMG bits in the page tables control bits in the HIDO register and user and superv
271. direct mtsrin rS rB 2 3 6 3 3 Translation Lookaside Buffer Management Instructions The address translation mechanism is defined in terms of segment descriptors and page table entries PTEs used by the processors to locate the effective to physical address mapping for a particular access The PTEs reside in page tables in memory As defined for 32 bit implementations by the PowerPC architecture segment descriptors reside in 16 on chip segment registers Implementation Note The MPC603e provides the ability to invalidate a TLB entry The TLB Invalidate Entry tlbie instruction invalidates the TLB entry indexed by the EA and operates on both the instruction and data TLBs simultaneously invalidating four TLB entries both sets in each TLB The index corresponds to bits 15 19 of the EA To invalidate all entries within both TLBs 32 tlbie instructions should be issued incrementing this field by one each time The MPC603e provides two implementation specific instructions tlbld and tlbli that are used by software table search operations following TLB misses to load TLB entries on chip For more information on tlbld and tlbli refer to Section 2 3 8 Implementation Specific Instructions Note that the tlbia instruction is not implemented on the MPC603e Refer to Chapter5 Memory Management for more information about the TLB operations for the MPC603e Table 2 42 lists the TLB instructions MPC603e RISC Microproce
272. dispatched on the next clock cycle In cycle 1 instructions 0 and 1 are dispatched to the IU and FPU respectively Notice that for instructions to be dispatched they must be assigned positions in the CQ In this case because the CQ is empty instructions 0 and 1 take the two lowest CQ entries CQO and CQ1 Instructions 2 and 3 are fetched from the instruction cache At least two IQ positions were available in the IQ in cycle 1 so in cycle 2 instructions 4 and 5 are fetched Instruction 4 is a branch unconditional instruction that resolves immediately as taken Because the branch is taken and does not update CTR or LR it can be folded from the IQ Instruction 0 completes writes back its results and vacates the CQ by the end of the clock cycle Instruction 1 enters the second FPU execute stage instruction 2 enters the single stage IU and instruction 3 is dispatched into the first FPU stage In cycle 3 target instructions 6 and 7 are fetched replacing the folded b instruction 4 and instruction 5 Instruction 1 enters the last FPU execute stage instruction 2 has executed but must remain in the CQ until instruction 1 completes Note that it can make its results available to subsequent instructions but cannot be removed from the CQ Instruction 3 passes into the last FPU execute stage Note that all three FPU stages are full To allow for the potential need for denormalization the dispatch logic prevents instruction 7 fadd from be
273. dition register logical instructions e Processor control instructions These instructions are used for synchronizing memory accesses and management of caches TLBs and the segment registers Move to from SPR instructions Move to from MSR Synchronize Instruction synchronize e Memory control instructions These instructions provide control of caches TLBs and segment registers Supervisor level cache management instructions User level cache instructions Segment register manipulation instructions e Translation lookaside buffer management instructions Note that this grouping of instructions does not indicate the execution unit that executes a particular instruction or group of instructions Integer instructions operate on byte half word and word operands Floating point instructions operate on single precision one word and double precision one double word floating point operands The PowerPC architecture uses instructions that are 4 bytes long and word aligned It provides for byte half word and word operand loads and stores between memory and a set of 32 GPRs It also provides for word and double word operand loads and stores between memory and a set of 32 FPRs Computational instructions do not modify memory To use a memory operand in a computation and then modify the same or another memory location the memory contents must be loaded into a register modified and then written back to the target location w
274. ds with data delays timing 8 33 reads timing 8 31 termination 8 25 writes timing 8 32 SMI signal 4 34 7 23 Snoop operation 3 20 6 23 Split bus transaction 8 8 SPR encodings not implemented in MPC603e B 2 SRESET signal 7 25 SRRO SRRI status save restore registers bit settings for machine check exception 4 10 bit settings for table search operations 4 10 Stall definition 6 3 Static branch prediction 6 18 Store operations memory coherency actions 3 19 single beat writes 8 32 String instructions 2 33 A 20 Superscalar 6 3 Supervisor mode see Privilege levels Supervisor level registers summary 2 4 sync operation 3 20 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Synchronization context execution synchronization 2 20 execution of rfi 4 14 memory synchronization instructions 2 38 2 41 A 21 SYSCLK signal 7 29 System call exception 4 29 System interface overview 1 33 System linkage instructions 2 43 A 22 System management interrupt 4 34 9 2 System quiesce control signals 8 41 System register unit execution timing 6 22 latency CR logical instructions 6 27 latency system register instructions 6 27 System status CKSTP_IN 7 24 CKSTP_OUT 7 24 HRESET 7 25 INT 7 23 MCP 7 24 QACK 7 26 QREQ 7 26 RSRV 7 27 SMI 7 23 SRESET 7 25 TBEN 7 27 TLBISYNC 7 27 T TA signal 7 21 Table search operations algori
275. duct Go to www freescale com Freescale Semiconductor Inc Memory Segment Model As TLB entries are on chip copies of PTEs in the page tables in memory they are similar in structure TLB entries consist of two words the high order word contains the VSID and API fields of the high order word of the PTE and the low order word contains the RPN the C bit the WIMG bits and the PP bits as in the low order word of the PTE In order to uniquely identify a TLB entry as the required PTE the TLB entry also contains five more bits of the page index EA 10 14 in addition to the API bits of the PTE When an instruction or data access occurs the effective address is routed to the appropriate MMU EA 0 3 select 1 of the 16 segment registers and the remaining effective address bits and the virtual address from the segment register is passed to the TLB EA 15 19 then select two entries in the TLB the valid bit is checked and EA 10 14 the VSID and API fields EA 4 9 for the access are then compared with the corresponding values in the TLB entries If one of the entries hits the PP bits are checked for a protection violation and the C bit is checked If these bits do not cause an exception the RPN value is passed to the memory subsystem and the WIMG bits are then used as attributes for the access Although address translation is disabled on a reset condition the valid bits of the BAT array and TLB entries are not automatically cleared T
276. duct Go to www freescale com Instruction Scheduling oufitRescale Semiconductor Inc invalidated If the line is marked modified it is copied back to memory before being invalidated In summary the copy back mode allows both load and store operations to use the on chip cache The write through mode allows load operations to use the on chip cache but store operations cause a memory access and a cache update if the data is already in the cache Lastly the cache inhibited mode causes memory access for both loads and stores 6 6 Instruction Scheduling Guidelines The performance of the MPC603e can be improved by avoiding resource conflicts and promoting parallel utilization of execution units through efficient instruction scheduling Instruction scheduling on the MPC603e can be improved by observing the following guidelines e Implement good static branch prediction setting of y bit in BO field e When branch prediction is uncertain or an even probability predict fall through e To reduce mispredictions separate the instruction that sets CR bits from the branch instruction that evaluates them separation by more than nine instructions ensures that the CR bits will be immediately available for evaluation e When branching conditionally to a location specified by count registers CTRs or link registers LRs or when branching conditionally based on the value in the count register separate the mtspr instruction that initializes the CTR
277. dx fnmsubx fnmaddx Tempo mtfsb1x fnegx mcrfs mtfsb0x fmrx 0 Inc Insttactions Sorted by Opcode 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 110111 S A d 111010 D A ds 00 111010 D A ds 01 111010 D A ds 10 111011 D A B 00000 10010 Rc 111011 D A B 00000 10100 Rc 111011 D A B 00000 10101 Rc 111011 D 00000 B 00000 10110 Re 111011 D 00000 B 00000 11000 Re 111011 D A 00000 C 11001 Rc 111011 D A B C 11100 Rc 111011 D A B C 11101 Rc 111011 D A B C 11110 Rc 111011 D A B C 11111 Rc 111110 S A ds 00 111110 S A ds 01 111111 crfD 00 A B 0000000000 0 111111 D 00000 B 0000001100 Rc 111111 D 00000 B 0000001110 111111 D 00000 B 0000001111 Rc 111111 D A B 00000 10010 Rc 111111 D A B 00000 10100 Rc 111111 D A B 00000 10101 Rc 111111 D 00000 B 00000 10110 Re 111111 D A B C 10111 Rc 111111 D A 00000 C 11001 Rc 111111 D 00000 B 00000 11010 Rc 111111 D A B C 11100 Rc 111111 D A B C 11101 Rc 111111 D A B C 11110 Rc 111111 D A B C 11111 Rc 111111 crfD 00 A B 0000100000 0 111111 crbD 00000 00000 0000100110 Re 111111 D 00000 B 0000101000 Re 111111 crfD 00 crfS 00 00000 0001000000 0 111111 crbD 00000 00000 0001000110 Re 111111 D 00000 B 0001001000 Re Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www frees
278. e See also Page access history bits and Referenced bit Clean An operation that causes a cache block to be written to memory if modified and then left in a valid unmodified state in the cache Clear To cause a bit or bit field to register a value of zero See also Set Context synchronization An operation that ensures that all instructions in execution complete past the point where they can produce an exception that all instructions in execution complete in the context in which they began execution and that all subsequent instructions are fetched and executed in the new context Context Glossary of Terms and Abbreviations For More Information On This Product Go to www freescale com Freescale Semiconductor Inc synchronization may result from executing specific instructions such as isyne or rfi or when certain events occur such as an exception Copy back operation A cache operation in which a cache line is copied back to memory to enforce cache coherency Copy back operations consist of snoop push out operations and cache cast out operations Denormalized number A nonzero floating point number whose exponent has a reserved value usually the format s minimum and whose explicit or implicit leading significand bit is zero Direct mapped cache A cache in which each main memory address can appear in only one location within the cache operates more quickly when the memory request is a cache hit Direct store s
279. e instruction must be placed between two stores that can result in assertion of TEA Software can use the machine check exception in a recoverable mode to probe memory For this case a sync load sync instruction sequence is used If the load access results in a system error for example the assertion of TEA the processor can handle this in a recoverable state If the sync instruction is not used a second access to the same address as the first load could cause the processor to enter the checkstop state Replace the third line of the im1 segment in the tlbInstrMiss section with the following bdnzf 0 iml dec count br if cmp ne and if count not zero Replace the third line of the ceq1 segment in the tlbCeq0 section with the following bdnzf 0 ceql dec count br if cmp ne and if count not zero C 2 Revision Changes From Revision 1 to Revision 2 Major changes to the MPC603e RISC Microprocessor User s Manual from Revision 1 to Revision 2 are as follows Section Page 1 1 1 1 6 2 1 1 2 3 Change The bus connecting the LSU to the GPRs should be 32 bits wide Figure 2 1 in Revision 1 of the published manual should be replaced by the following figure MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semicon uctor nc vision Change fine Revision 1 to Revision 2 SUPERVISOR MODEL OEA Configuration Registers USER MODEL UISA H
280. e 2 17 UE Instruction Classin uronin a aSa S aS aS 2 18 Reserved Instruction Class ssseeessseeessesesseesreeressessessressteseseresresseseeesreses 2 19 Addressing Modes sriain e ea i a e eg a i ES 2 19 Memory Addressing s sacssssccsastees3sctssastea es sesedazasussaccvaned cade nacsedeacasecedasstecd ease 2 19 Memory Operands sacian ede tient ect teen 2 19 Effective Address Calculation 2 5 0 c40ialaecaeaneaedieie 2 20 Synchronization 2 a eel te Ube aided Gath E E ae as eRe OU Es 2 20 Context Synchronization EE 2 21 Execution Symchromization ccsssccsssccssssccssssscsensscesseccessceesnascsensecens 2 21 Instruction Related Exceptions s sssessesssesssesessseessresserssereseressseesseese 2 21 Instruction Set e TEE 2 22 PowerPG Ee le EE 2 22 PLS BET MSU UCIIONS ee ee 2 22 Integer Arithmetic Instructons 2 23 Integer Compare Instructions 3x c05 285 sca5ccadennssdadeeesectacede ands RRC 2 24 Integer Logical Instructions 2c ssccsedseacsaraseusaceasnaceevasosenaterveranensttaceenseasd 2 24 Integer Rotate and Shift Instructions 0 eee eeeeeseceseceeeeeeeeeeneeenaeens 2 25 Floating Point Instructions ege di sa cea geed AE cated 2 26 Floating Point Arithmetic Instructions 00 0 eeeeeeeeeeseeeseeeeseeeeeeeeneees 2 26 Floating Point Multiply Add Instructions 20 0 0 ceeeseeceseeeeseeeeeeteeeeeees 2 27 Floating Point Rounding and Conversion Instructions ee eee 2 28 Floating Point Compare Instructions 00
281. e Half Word with Update sthu rS d rA Store Half Word with Update Indexed sthux rS rA rB Store Word stw rS d rA Store Word Indexed stwx rS rA rB Store Word with Update stwu rS d rA Store Word with Update Indexed stwux rS rA rB 2 3 4 3 5 Integer Load and Store with Byte Reverse Instructions Table 2 23 describes integer load and store with byte reverse instructions When used in a system operating with the default big endian byte order these instructions have the effect of loading and storing data in little endian order Likewise when used in a system operating with little endian byte order these instructions have the effect of loading and storing data in big endian order For more information about big endian and little endian byte ordering see Byte Ordering in Chapter 3 Operand Conventions in the Programming Environments Manual Table 2 23 Integer Load and Store with Byte Reverse Instructions Name Mnemonic Operand Syntax Load Half Word Byte Reverse Indexed Ihbrx rD rA rB Load Word Byte Reverse Indexed lwbrx rD rA rB Store Half Word Byte Reverse Indexed sthbrx rS rA rB Store Word Byte Reverse Indexed stwbrx rS rA rB Implementation Note In some implementations load byte reverse instructions Ihbrx and Iwbrx may have greater latency than other load instructions however these instructions operate with the same latency as other load instructions in the MPC603e 2 3 4 3 6 Integer Load and
282. e Information On This Product Go to www freescale com Freescale Semiconductor Ine Sorted by Mnemonic Table A 1 Complete Instruction List Sorted by Mnemonic continued Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sthx 31 S A B 407 0 stmw 4 47 S A d stswi 4 31 S A NB 725 0 stswx 4 31 S A B 661 0 stw 36 S A d stwbrx 31 S A 662 0 stwex 31 S A B 150 1 stwu 37 S A d stwux 31 S A B 183 0 stwx 31 S A B 151 0 subfx 31 D A B OE 40 Re subfcx 31 D A B OE 8 Re subfex 31 D A B OE 136 Re subfic 08 D A SIMM subfmex 31 D A 00000 OE 232 Re subfzex 31 D A 00000 OE 200 Re sync 31 00000 00000 00000 598 0 td 31 TO A B 68 0 tdi 1 02 TO A SIMM tlbia 2 3 31 00000 00000 00000 370 0 tlbie 2 3 31 00000 00000 B 306 0 tlbld2 P 31 00000 00000 B 978 0 tlbli 2 6 31 00000 00000 B 1010 0 tlbsync 2 3 31 00000 00000 00000 566 0 tw 31 TO A B 4 0 twi 03 TO A SIMM xorx 31 S A B 316 Rc xori 26 A UIMM xoris 27 S A UIMM 1 64 bit instruction 2 Supervisor level instruction 3 Optional in the PowerPC architecture 4 Load and store string or multiple instruction 5 Supervisor and user level instruction 6 Implementation specific instruction Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com A 2 opcode Name tdi twi mulli subfic cmpli
283. e MPC603e implements the MSR as a 32 bit register 1 3 1 8 Segment Registers SRs For memory management 32 bit processors implement sixteen 32 bit SRs To speed access the MPC603e implements the SRs as two arrays a main array for data memory accesses and a shadow array for instruction memory accesses Loading a segment entry with the Move to Segment Register mtsr instruction loads both arrays 1 3 1 9 Special Purpose Registers SPRs The OEA defines numerous SPRs that serve a variety of functions such as providing controls indicating status configuring the processor and performing special operations During normal execution a program can access the registers as shown in Figure 1 2 depending on the program s access privilege supervisor or user determined by the privilege level bit MSR PR Note that GPRs and FPRs are accessed through operands that are part of the instructions Access to registers can be explicit that is through the use of specific instructions for that purpose such as Move to Special Purpose Register mtspr and Move from Special Purpose Register mfspr instructions or implicit as the part of the execution of an instruction Some registers are accessed both explicitly and implicitly In the MPC603e all SPRs are 32 bits wide 1 3 1 9 1 User Level SPRs The following MPC603e SPRs are accessible by user level software e Link register LR The LR can be used to provide the branch target address and
284. e MPC603e initiates a system management interrupt exception if MSR EE is set otherwise the MPC603e ignores the exception condition The system must hold SMI asserted until the exception is taken Negated Indicates that normal operation should proceed See Section 8 7 1 External Interrupts Chapter 7 Signal Descriptions For More Information On This Product Go to www freescale com ae Freescale Semiconductor Inc Signal Descriptions Timing Comments Assertion May occur at any time and may be asserted asynchronously to the input clocks The SMI input is level sensitive Negation Should not occur until exception is taken 7 2 9 3 Machine Check Interrupt MCP Input Following are the state meaning and timing comments for the MCP input State Meaning Asserted The MPC603e initiates a machine check interrupt exception if MSR ME and HIDO EMCP are set if MSR ME is cleared and HIDO EMCP is set the MPC603e terminates operation by internally gating off all clocks and releasing all outputs except CKSTP_OUT to the high impedance state If HIDO EMCP is cleared the MPC603e ignores the interrupt condition MCP must be held asserted for two bus clock cycles Negated Indicates that normal operation should proceed See Section 8 7 1 External Interrupts Timing Comments Assertion May occur at any time and may be asserted asynchronously to the input clocks MCP is negative edge sensitive Negation
285. e SDR1 register specifies the variable used in accessing the page tables in memory SDR1 is defined as a 32 bit register for 32 bit implementations This is a special purpose register that is accessed by the mtspr and mfspr instructions Instruction TLB miss address and data TLB miss address registers IMISS and DMISS When a TLB miss exception occurs the IMISS or DMISS register contains the 32 bit effective address of the instruction or data access respectively that caused the miss Note that the MPC603e always loads a big endian address into the DMISS register These registers are MPC603e specific Primary and secondary hash address registers HASH1 and HASH2 The HASH1 and HASH2 registers contain the primary and secondary PTEG addresses that correspond to the address causing a TLB miss These PTEG addresses are automatically derived by the MPC603e by performing the primary and secondary hashing function on the contents of IMISS or DMISS for an ITLB or DTLB miss exception respectively These registers are MPC603e specific Instruction and data PTE compare registers ICMP and DCMP The ICMP and DCMP registers contain the word to be compared with the first word of a PTE in the table search software routine to determine if a PTE contains the address translation for the instruction or data access The contents of ICMP and DCMP are automatically derived by the MPC603e when a TLB miss exception occurs These registers are M
286. e VEA describes the semantics of the memory model that can be assumed by software processes and includes descriptions of the cache model cache control instructions address aliasing and other related issues 2 3 5 1 Processor Control Instructions The VEA defines the Move from Time Base mftb instruction for reading the contents of the time base register The mftb is a user level instruction as shown in Table 2 33 Table 2 33 Move From Time Base Instruction Name Mnemonic Operand Syntax Move from Time Base mftb rD TBR Simplified mnemonics are provided for the mftb instruction so it can be coded with the TBR name as part of the mnemonic rather than requiring it to be coded as an operand The mftb instruction serves as both a basic and simplified mnemonic Assemblers recognize an mftb mnemonic with two operands as the basic form and an mftb mnemonic with one operand as the simplified form Simplified mnemonics are also provided for Move from Time Base Upper mftbu a variant of the mftb instruction rather than of mfspr The MPC603e ignores the extended opcode differences between mftb and mfspr by ignoring bit 25 of both instructions and treating them identically Refer to Appendix F Simplified Mnemonics in the Programming Environments Manual MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc uction Sesame 2 3 5 2 Me
287. e architecture specification The physical address bits are then compared with the corresponding cache tag bits to determine if a cache hit occurred If the access misses in the corresponding cache the physical address is used to access system memory In addition to loads stores and instruction fetches the MPC603e performs software table search operations following TLB misses cache cast out operations when least recently used LRU cache lines are written to memory after a cache miss and cache line snoop Chapter 8 System Interface Operation For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Overview push out operations when a modified cache line experiences a snoop hit from another bus master Figure 8 1 shows the address path from the execution units and instruction fetcher through the translation logic to the caches and system interface logic The MPC603e uses separate address and data buses and a variety of control and status signals for performing reads and writes The address bus is 32 bits wide and the data bus can be configured to be 32 or 64 bits wide The interface is synchronous all MPC603e inputs are sampled at and all outputs are driven from the rising edge of the bus clock The bus can run at the full processor clock frequency or at an integer division of the processor clock speed Although the MPC603e operates at 3 3 V all the I O signals are 5 0 V TTL compatible 8 1 1 O
288. e bectr instruction requires CTR availability e Branch and link instructions require shadow LR availability e The branch conditional on counter decrement and CR condition requires CTR availability or the CR condition must be false and the MPC603e cannot be executing instructions following an unresolved predicted branch when the branch is encountered by the BPU e The branch conditional on CR condition cannot be executed following an unresolved predicted branch instruction 6 6 1 2 Dispatch Unit Resource Requirements The following is a list of resources required to avoid stalls in the dispatch unit Note that the two dispatch buffers IQO and IQ1 are at the bottom of the dispatch queue e Requirements for dispatching from IQO are as follows Needed execution unit available Needed GPR rename registers available Needed FPR rename registers available Completion queue is not full Instruction is dispatch serialized and completion buffer is empty A dispatch serialized instruction is not currently being executed e Requirements for dispatching from IQ are as follows Instruction in IQO must dispatch Instruction dispatched by IQO is not dispatch serialized Needed execution unit is available after dispatch from IO Needed GPR rename registers are available after dispatch from IQO Needed FPR rename register is available after dispatch from IQO Chapter 6 Instruction Timing For More Information On Thi
289. e com Freescale Semiconductor Inc rD The rD instruction field is used to specify a GPR to be used as a destination rS The rS instruction field is used to specify a GPR to be used as a source Real address mode An MMU mode when no address translation is performed and the effective address specified is the same as the physical address The processor s MMU is operating in real address mode if its ability to perform address translation has been disabled through the MSR registers IR and or DR bits Record bit Bit 31 or the Rc bit in the instruction encoding When it is set updates the condition register CR to reflect the result of the operation Referenced bit One of two page history bits found in each page table entry The processor sets the referenced bit whenever the page is accessed for a read or write See also Page access history bits Register indirect addressing A form of addressing that specifies one GPR that contains the address for the load or store Register indirect with immediate index addressing A form of addressing that specifies an immediate value to be added to the contents of a specified GPR to form the target address for the load or store Register indirect with index addressing A form of addressing that specifies that the contents of two GPRs be added together to yield the target address for the load or store Rename register Temporary buffers used by instructions that have finished execution but
290. e contents of the ICMP and RPA registers into the ITLB tlbld Load Data TLB Entry MPC603e specific Loads the contents of the DCMP and RPA registers into the DTLB 1 These instructions are defined by the PowerPC architecture but are optional Table 5 6 summarizes the registers that the operating system uses to program the MPC603e MMUs These registers are accessible to supervisor level software only These registers are described in Chapter 2 Register Set in the Programming Environments Manual For MPC603e specific registers see Chapter 2 Programming Model of this book Table 5 6 MMU Registers Register Description Segment registers The sixteen 32 bit segment registers are present only in 32 bit implementations of the IBATOU IBAT3U IBATOL IBATSL DBATOU DBAT3U and DBATOL DBATS3L SRO SR15 PowerPC architecture The fields in the segment register are interpreted differently depending on the value of bit 0 The segment registers are accessed by the mtsr mtsrin mfsr and mfsrin instructions BAT registers There are 16 BAT registers organized as 4 pairs of instruction BAT registers IBATOU IBAT3U paired with IBATOL IBAT3L and 4 pairs of data BAT registers DBATOU DBAT3U paired with DBATOL DBAT3L The BAT registers are defined as 32 bit registers in 32 bit implementations These are special purpose registers that are accessed by the mtspr and mfspr instructions SDR1 Th
291. e directory tags If neither of the indexed tags matches the result is a cache miss If a tag matches a cache hit occurred and the directory indicates the state of the cache block through two state bits kept with the tag The three possible states for a cache block in the cache are the modified state M the exclusive state E and the invalid state I The three MEI states are defined in Table 3 2 Table 3 2 MEI State Definitions MEI State Definition Modified M The addressed cache block is valid only in the cache The cache block is modified with respect to system memory that is the modified data in the cache block has not been written back to memory Exclusive E The addressed block is in this cache only The data in this cache block is consistent with system memory Invalid 1 This state indicates that the addressed cache block is not resident in the cache 3 6 2 MEI State Diagram The MPC603e provides dedicated hardware to provide memory coherency by snooping bus transactions The address retry capability of the MPC603e enforces the MEI protocol as MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor INg erency ME Protocol shown in Figure 3 4 Figure 3 4 assumes that the WIM bits for the page or block are set to 001 that is write back caching not inhibited and memory coherency enforced Modified R
292. e facility TBL Time base lower register TBU Time base upper register TLB Translation lookaside buffer TTL Transistor to transistor logic MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc K Conventions Table i Acronyms and Abbreviated Terms continued Term Meaning UIMM Unsigned immediate value UISA User instruction set architecture UTLB Unified translation lookaside buffer UUT Unit under test VEA Virtual environment architecture WAR Write after read WAW Write after write WIMG Write through caching inhibited memory coherency enforced guarded bits XATC Extended address transfer code XER Register used for indicating conditions such as carries and overflows for integer operations Terminology Conventions Table ii describes terminology conventions used in this manual and the equivalent terminology used in the PowerPC architecture specification Table ii Terminology Conventions The Architecture Specification This Manual Data storage interrupt DSI DSI exception Extended mnemonics Simplified mnemonics Fixed point unit FXU Integer unit IU Instruction storage interrupt ISI ISI exception Interrupt Exception Privileged mode or privileged state Supervisor level privilege Problem mode or problem state User level privilege
293. e instruction fetch enable M IFEM bit HIDO 24 allows the PID7t 603e to reflect the value of the M bit onto the 60x bus during instruction translation The Run_N counter register Run_N has been extended from 16 to 32 bits Enhancements to cache implementation The instruction cache is blocked only until the critical load completes hit under reloads allowed The critical double word is simultaneously written to the cache and forwarded to the requesting unit thus minimizing stalls due to load delays Provides for an optional data cache operation broadcast feature enabled by HIDO ABE that allows for correct system management using an external copy back L2 cache All of the cache control instructions icbi debi deht and dcbst excluding dcbz require that HIDO ABE be enabled in order to execute Exceptions The PID7t 603e now offers hardware support for misaligned little endian accesses Little endian load store accesses that are not on a word boundary with the exception of strings and multiples generate exceptions under the same circumstances as big endian accesses The PID7t 603e removed misalignment support for eciwx and ecowx graphics instructions These instructions cause an alignment exception if the access is not on a word boundary Bus clock New bus multipliers of 4 5x 5x 5 5x and 6x that are selected by the unused encodings of PLL_CFG 0 3 Bus multipliers of 1x and 1 5x are not suppor
294. e next instruction in program order to complete including handling any exceptions that instruction may generate However the 603e blocks subsequent instructions from completing and allows any outstanding stores to occur to system memory The last sentence of this section should be appended as follows The interrupt handler must send a command to the device that asserted INT acknowledging the interrupt and instructing the device to negate INT before the handler re enables recognition of external interrupts Remove the heading 4 5 6 1 1 Page Address Translation Access The text that follows this heading should just be part of section 4 5 6 1 In Table 4 16 the KEY bit was omitted and the polarity of bit 15 was reversed Therefore replace the SRR1 row with the following Table 4 16 Instruction and Data TLB Miss Exceptions Register Settings Partial SRR1 0 3 4 11 12 13 15 Loaded from condition register CRO field Cleared KEY Key for TLB miss SR Ks or SR Kp depending on whether the access is a user or supervisor access D I Data or instruction access 0 Data TLB miss 1 Instruction TLB miss WAY Next TLB set to be replaced set per LRU 0 Replace TLB associativity set 0 1 Replace TLB associativity set 1 S L Store or load data access 0 Data TLB miss on load 1 Data TLB miss on store or C 0 16 31 Loaded from MSR 16 31 MPC603e RISC Microprocessor User s Manual For More Infor
295. e possible 8 3 2 5 Effect of Alignment in Data Transfers 32 Bit Bus The aligned data transfer cases for 32 bit data bus mode are shown in Table 8 7 All of the transfers require a single data beat if caching inhibited or write through except for double word cases which require two data beats The double word case is only generated by the MPC603e for load or store double operations to from the floating point GPRs All caching inhibited instruction fetches are performed as word operations MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Address Bus Tenure Table 8 7 Aligned Data Transfers 32 Bit Bus Mode eo Tsizo TSIZ1 TsIz2 A 29 31 GE 0 1 2 3 4 5 6 7 Byte 0 0 1 000 A x x x x 0 0 1 001 A D D D D xX 0 0 1 010 A D D D xX 0 0 1 011 A D D D xX 0 0 1 100 A D D D D 0 0 1 101 A Es D D D xX 0 0 1 110 A D D D xX 0 0 1 111 A D D D xX Half word 0 1 0 000 A A D D D D 0 1 0 010 A A D D D D 0 1 0 100 A A D D D D 0 1 0 110 A A D D D D Word 1 0 0 000 A A A A D D D D 1 0 0 100 A A A A D D D D Double word 0 0 0 000 A A A A D D D D Second beat 0 0 0 000 A A A A D D D D Notes A Byte lane used Byte lane not used x Byte lane not used in 32 bit bu
296. e shown as optional because TLBs are not required by the architecture Figure 5 9 shows the case of a debz instruction that is executed with W 1 or I 1 and that the R bit may be updated in memory if required before the operation is performed or the alignment exception occurs The R bit may also be updated by a memory protection violation Chapter 5 Memory Management For More Information On This Product Go to www freescale com Page Table Search Operathreeseale Semiconductor Inc Primary Page Table Search Generate PA Using Primary Hash Function PA lt Base PA of PTEG Fetch PTE from PTEG PA lt PA 8 Fetch Next PTE in PTEG Fetch PTE 64 Bits from PA Otherwise PTE VSID API H V Segment Descriptor VSID EA API 0 1 Otherwis Secondary Page Last PTE in PTEG Table Search Hit i PTE R 1 PTE R 0 from Figure 5 10 PTE R lt 1 R_Flag 1 M ad kd Write PTE into TLB Guc H An debz Instruction Oth Ste with W orl 1 oe Check Memory Protection R_Flag 1 Otherwise Violation Conditions e Byte Write to Update PTE R in Access Permitt d Gs Memory F ya Access Prohibited Otherwise Store Operation with BIE Perform Operation to Otherwise Otherwise Memory or Take 45 eo Alignment Exception R_Flag 1 TUBIPTE C lt 1 R_Flag 1 er ve aa ay gone ee Ll PTE C lt 1 PTE R lt 1 Update PTE C Update
297. e soft reset input provides warm reset capability This input can be used to avoid forcing the MPC603e to complete the cold start sequence When either reset input is negated the processor attempts to fetch code from the system reset exception vector The vector is located at offset 0x00100 from the exception prefix all zeros or ones depending on the setting of the exception prefix bit in the machine state register MSR IP The IP bit is set for HRESET 8 7 4 System Quiesce Control Signals The system quiesce control signals QREQ and QACK allow the processor to enter a low power state and bring bus activity to a quiescent state in an orderly fashion The system quiesce state is entered by configuring the processor to assert the QREQ output This signal allows the system to terminate or pause any bus activities that are normally snooped When the system is ready to enter the system quiesce state it asserts QACK At this time the MPC603e may enter a quiescent low power state during which it stops snooping bus activity 8 8 Processor State Signals This section describes the MPC603e support for atomic update and memory through the use of the Iwarx stwex instruction pair and includes a description of the MPC603e TLBISYNC input 8 8 1 Support for the lwarx stwcx Instruction Pair The Load Word and Reserve Indexed Iwarx and the Store Word Conditional Indexed stwex instructions provide a means for atomic memory updating Memo
298. e the MPC603e regardless of the SYSCLK input Chapter 7 Signal Descriptions For More Information On This Product Go to www freescale com ae Freescale Semiconductor Inc Signal Descriptions 7 2 13 Power and Ground Signals The MPC603e provides the following connections for power and ground Vpp and OVpp The Vpp and OVpp signals provide the connection for the supply voltage On the MPC603e there is no electrical distinction between the Vpp and OVpp signals e AVpp The AVpp power signal provides power to the clock generation PLL See the appropriate hardware specifications for information on how to use this signal e GND and OGND The GND and OGND signals provide the connection for grounding the MPC603e On the MPC603e there is no electrical distinction between the GND and OGND signals MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 8 System Interface Operation This chapter describes the MPC603e microprocessor s bus interface and its operation It shows how the MPC603e signals defined in Chapter 7 Signal Descriptions interact to perform address and data transfers 8 1 Overview The system interface prioritizes requests for bus operations from the instruction and data caches and performs bus operations per the MPC603e bus protocol It includes address register queues prioritization logic and the bus contr
299. e time the instruction spends in the IQ but also the time required for the instruction to be loaded from system memory beginning in clock cycle 3 Chapter 6 Instruction Timing For More Information On This Product Go to www freescale com rae EN Freescale Semiconductor Inc Timing Considerations D fac Fetch in IQ In Dispatch Entry l1Q0 IQ1 mu Xecute brand Es E Complete in CO ie 12 fadd 13 add In Retirement Entry CQ0 CQ1 1 1 1 1 Instruction Queue Completion Queue 3 9 10 2 3 3 8 8 9 11 13 1 1 2 2 7 7 8 10 12 13 13 13 0 0 1 1 3 6 6 6 6 7 9 11 12 12 12 Figure 6 6 Instruction Timing Cache Miss During clock cycle 2 the target instruction for the b instruction is not in the instruction cache therefore a memory access must occur During clock cycle 5 the address of the block of instructions is sent to the system bus During clock cycle 9 two instructions 64 bits are returned from memory on the first beat and are forwarded both to the cache and instruction fetcher MPC603e RISC Microprocessor User s Manual For More
300. e used to prevent invalid data from being used by the processor otherwise assertion may occur at any time during the assertion of DBB The system can withhold Chapter 7 Signal Descriptions For More Information On This Product Go to www freescale com Signal Descriptions Freescale Semiconductor Inc assertion of TA to indicate that the MPC603e should insert wait states to extend the duration of the data beat Negation Miust occur after the bus clock cycle of the final or only data beat of the transfer For a burst transfer the system can assert TA for one bus clock cycle and then negate it to advance the burst transfer to the next beat and insert wait states during the next beat Note When the MPC603e is configured for 1 1 clock mode and is performing a burst read into the data cache the MPC603e requires one wait state between the assertion of TS and the first assertion of TA for that transaction If no DRTRY mode is also selected the MPC603e requires two wait states for 1 1 clock mode or one wait state for 1 5 1 clock mode 7 2 8 2 Data Retry DRTRY Input Following are the state meaning and timing comments for the DRTRY input State Meaning Timing Comments Asserted Indicates that the MPC603e must invalidate the data from the previous read operation Negated Indicates that data presented with TA on the previous read operation is valid Note that DRTRY is ignored for write transactions Asse
301. echarge of ARTRY enabled 1 Alters bus protocol slightly by preventing the processor from driving ARTRY to high negated state If this is done the system must restore the signals to the high state 8 DOZE Doze mode enable Operates in conjunction with MSR POW 0 Doze mode disabled 1 Doze mode enabled Doze mode is invoked by setting MSR POW while this bit is set In doze mode the PLL time base and snooping remain active 9 NAP Nap mode enable Operates in conjunction with MSR POW 0 Nap mode disabled 1 Nap mode enabled Doze mode is invoked by setting MSR POW while this bit is set In nap mode the PLL and the time base remain active 10 SLEEP Sleep mode enable Operates in conjunction with MSR POW 0 Sleep mode disabled 1 Sleep mode enabled Sleep mode is invoked by setting MSR POW while this bit is set QREQ is asserted to indicate that the processor is ready to enter sleep mode If the system logic determines that the processor may enter sleep mode the quiesce acknowledge signal QACK is asserted back to the processor Once QACK assertion is detected the processor enters sleep mode after several processor clocks At this point the system logic may turn off the PLL by first configuring PLL_CFG 0 3 to PLL bypass mode then disabling SYSCLK 11 DPM Dynamic power management enable 0 Dynamic power management is disabled 1 Functional units enter a low power mode automatically if the unit is idle This does not affe
302. ecision format and the external single precision format 2 3 4 2 1 Floating Point Arithmetic Instructions The floating point arithmetic instructions are listed in Table 2 15 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING ten E Table 2 15 Floating Point Arithmetic Instructions Name Mnemonic Operand Syntax Floating Add Double Precision fadd fadd frD frA frB Floating Add Single fadds fadds frD frA frB Floating Divide Double Precision fdiv fdiv frD frA frB Floating Divide Single fdivs fdivs frD frA frB Floating Multiply Double Precision fmul fmul frD frA frC Floating Multiply Single fmuls fmuls frD frA frC Floating Reciprocal Estimate Single fres fres frD frB Floating Reciprocal Square Root Estimate frsqrte frsqrte frD frB Floating Select fsel fsel frD frA frC frB Floating Subtract Double Precision fsub fsub frD frA frB Floating Subtract Single fsubs fsubs frD frA frB 2 3 4 2 2 Floating Point Multiply Add Instructions These instructions combine multiply and add operations without an intermediate rounding operation The fractional part of the intermediate product is 106 bits wide and all 106 bits take part in the add subtract portion of the instruction The floating point multiply add instructions are listed in Table 2 16 Table 2 16 Floating Point Mul
303. eck exception is taken instruction execution for the handler begins at offset 0x00200 from the physical base address indicated by MSR IP In order to return to the main program the exception handler should do the following 1 SRRO and SRR1 should be given the values to be used by the rfi instruction 2 Execute rfi Table 4 11 Machine Check Exception Register Settings Register Setting Description SRRO Set to the address of the next instruction that would have been completed in the interrupted instruction stream Neither this instruction nor any others beyond it will have been completed All preceding instructions will have been completed SRR1 0 11 Cleared 12 MCP Machine check signal caused exception 13 TEA Transfer error acknowledge signal caused exception 14 DPE Data parity error condition and signal assertion caused exception 15 APE Address parity error condition and signal assertion caused exception 16 31 Loaded from MSR 16 31 MSR POW 0 EE 0 FEO 0 IR 0 TGPR 0 PR 0 SE 0 DR 0 ILE FP 0 BE 0 RI 0 IP ME 0 FEI 0 LE Set to value of ILE Note When a machine check exception is taken the exception handler should set MSR ME as soon as it is practical to handle another TEA assertion Otherwise subsequent TEA assertions cause the processor to automatically enter the checkstop state 4 5 2 2 Checkstop State MSR ME 0 When the MPC603e enters the checkstop state it asserts the checkstop
304. ecowx instructions alignment 8 18 signals 8 23 DBB signal 7 18 8 8 8 22 DBDIS signal 7 21 DBG signal 7 17 8 7 DBWO signal 7 17 8 8 8 22 8 43 DCMP and ICMP registers 5 34 Decrementer interrupt 4 28 9 2 Defined instruction class 2 17 DHn DLn signals 7 18 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Direct address translation translation disabled data accesses 3 11 5 9 5 11 5 19 instruction accesses 3 11 5 9 5 11 5 19 Direct store access on the MPC603e 3 10 Dispatch considerations 6 15 DMISS and IMISS registers 5 33 DPE signal 7 20 DPn signals 7 19 DRTRY signal 7 22 8 24 8 27 DSI exception 4 21 E Effective address calculation address translation 5 3 branches 2 20 2 36 loads and stores 2 20 2 30 2 34 Error termination 8 27 Exceptions alignment exception 4 24 data TLB miss on load 4 31 data TLB miss on store 4 32 decrementer interrupt 4 28 DSI exception 4 21 enabling and disabling 4 13 exception classifications 4 2 exception processing 4 9 4 13 external interrupt 4 23 FP unavailable exception 4 28 instruction address breakpoint 4 32 instruction related 2 21 instruction TLB miss 4 30 machine check exception 4 19 overview 1 26 program exception 4 27 register settings FPSCR 4 27 MSR 4 16 SRRO SRR1 4 10 reset 4 17 returning from an exception handler
305. ecture and may not be supported in all processors that implement the OEA 2 1 2 Implementation Specific Registers The MPC603e defines the DMISS IMISS DCMP ICMP HASH1 HASH2 RPA HIDO HID1 and IABR SPRs for software table search operations These registers should be accessed only when address translation is disabled MSR IR and MSR DR are both zero For a complete discussion refer to Section 5 5 2 Implementation Specific Table Search Operation Also the HIDO HID1 and IABR SPRs are defined and described in this section These registers can be accessed by supervisor level instructions only using the SPR numbers shown in Figure 2 1 2 1 2 1 Hardware Implementation Registers HIDO and HID1 The HIDO and HID1 registers shown in Figure 2 2 and Figure 2 3 respectively define enable bits for various MPC603e specific features Reserved EICE DLOCK EMCP SS ECLK DOZE SLEEP RISEG ILOCK FBIOB NOOPTI D EBA EBD PAR NAP DPM 00 NHR ICE DCE ICFI DCFI 00000 000 0 1 23 456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 26 27 28 30 31 Figure 2 2 Hardware Implementation Register 0 HIDO MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Register Set Table 2 2 shows the bit definitions for HIDO Table 2 2 HIDO Bit Functions
306. ed 0 1 1 1 1 N A Reserved 1 X X 1 1 N A When HIDO ABE is set the PID7t 603e performs address only bus transactions with the encodings shown in Table 7 3 Table 7 3 Implementation Specific Transfer Encoding TTO mn TT2 TT3 TT4 RER Transaction ea 0 0 0 0 0 Clean block Address only dcbst 0 0 1 0 0 Flush block Address only dcbf 0 1 1 0 0 Kill block Address only dcbz dch Chapter 7 Signal Descriptions For More Information On This Product Go to www freescale com Signal Descriptions Freescale Semiconductor Inc 7 2 4 2 Transfer Size TSIZ 0 2 Output The TSIZ 0 2 signals consist of three output signals on the MPC603e Following are the state meaning and timing comments for the TSIZ 0 2 outputs State Meaning Timing Comments Asserted Negated For memory accesses these signals along with TBST indicate the data transfer size for the current bus operation as shown in Table 7 4 Table 8 5 shows how the transfer size signals are used with the address signals for aligned transfers Table 8 6 shows how the transfer size signals are used with the address signals for misaligned transfers For external control instructions eciwx and ecowx TSIZ 0 2 are used to output bits 29 31 of the external access register EAR which are used to form the resource ID TBSTIITSIZ 0 2 Assertion Negation The same as A 0 31 High Impedance
307. ed In the case of a cache hit the cache returns two words to the requesting unit Because the data cache tags are single ported simultaneous load or store and snoop accesses cause resource contention Snoop accesses have the highest priority and are given first access to the tags unless the snoop access coincides with a tag write in this case the snoop is retried and must rearbitrate for cache access Loads or stores deferred due to snoop accesses are performed on the clock cycle following the snoop 1 1 6 Processor Bus Interface Because the caches are on chip write back caches the most common transactions are burst read memory operations burst write memory operations and single beat noncacheable or write through memory read and write operations There can also be address only operations variants of the burst and single beat operations for example global memory operations that are snooped and atomic memory operations and address retry activity for example when a snooped read access hits a modified cache block Memory accesses can occur in single beat 1 8 bytes and four beat burst 32 bytes data transfers when the bus is configured as 64 bits and in single beat 1 4 bytes two beat 8 bytes and eight beat 32 bytes data transfers when the bus is configured as 32 bits The address and data buses operate independently to support pipelining and split transactions during memory accesses The MPC603e can pipeline its own trans
308. ed address order For load or store operations that miss in the cache and are marked as cacheable and for stores write back by the MMU the MPC603e uses the double word aligned address associated with the critical code or data that initiated the transaction This minimizes latency by allowing the critical code or data to be forwarded to the processor before the rest of the cache line is filled For all other burst operations however the cache line is transferred beginning with the eight word aligned data The MPC603e does not directly support dynamic interfacing to subsystems with less than a 64 bit data path It does however provide a static 32 bit data bus mode for more information see Section 8 1 2 1 Optional 32 Bit Data Bus Mode Chapter 8 System Interface Operation For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Bus Tenure 8 4 4 Data Transfer Termination Four signals are used to terminate data bus transactions TA DRTRY data retry TEA transfer error acknowledge and ARTRY The TA signal indicates normal termination of data transactions It must always be asserted on the bus cycle coincident with the data that itis qualifying It may be withheld by the slave for any number of clocks until valid data is ready to be supplied or accepted DRTRY indicates invalid read data in the previous bus clock cycle DRTRY extends the current data beat and does not terminate it If
309. ed by the architecture and while this description applies to the MPC603e it does not necessarily apply to other processors that implement the PowerPC architecture MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Segment Model 5 4 3 1 TLB Organization Because the MPC603e has two MMUs IMMU and DMMU that operate in parallel some of the MMU resources are shared and some are actually duplicated shadowed in each MMU to maximize performance Figure 5 7 shows the relationships between these resources within both the IMMU and DMMU and how the various portions of the effective address are used in the address translation process EAO EA31 Segment Registers EAO EA3 EA4 EA14 Kc 1 Kai 0 EA15 EA19 Select tt oO oO E D E PAO PA19 Figure 5 7 Segment Register and TLB Organization While both MMUs can be accessed simultaneously both sets of segment registers and TLBs can be accessed in the same clock when there is an exception condition only one exception is reported at a time ITLB miss exceptions are reported when there are no more instructions to be dispatched or retired the pipeline is empty Refer to Chapter 6 Instruction Timing for more detailed information about the internal pipelines and the reporting of exceptions Chapter 5 Memory Management For More Information On This Pro
310. eee ee ea ee hes A 16 Ite per Shift E ONS is 90 ds ast cca iste lees T te dena tome a a iiie A 17 Floating Point Arithmetic Instructions 000 0 eee eseceseceeeeeencecneceseeeseeeeneecaaecnseensees A 17 Floating Point Multiply Add Instructions 00 0 0 cee eeceeseeeseceseeeeeeesaeecsueeneenseeesnees A 18 Floating Point Rounding and Conversion Instructons A 18 Floating Point Compare Instructions es ceseeseeesceeseeceseceseeeeeeeeaeecsaecnseeeseeenaees A 18 Floating Point Status and Control Register Instructons eee eeeesseeeeeeeeeeeenees A 18 Integer Load Tnstrocti nS eebe ote ie eer ee A 19 Inte ser tee tee A 19 Integer Load and Store with Byte Reverse Instructions ce ceeeeeeeseeeeneeeeeeeeee A 20 Integer Load and Store Multiple Instructions 00 0 0 eee eeeeceseeeeeeeeseeesneceseeeseeeenees A 20 Integer Load and Store String Instructions 20 0 0 eeeeeeneecneeceeeeeseeeeaeeesaeenseeees A 20 Memory Synchronization Instructions e cc eeeeeseceseeeseeeeeceseceeeeeeeeesaeeesaeenseeesees A 21 Floating Point Load Instructions ege Ain eee SA es A 21 Floating Point Store Instructions 2 4 0 2 64 Gio eee oe ee e A 21 Floating Point Move Instructions eet A 22 Branch Detten See deen A 22 Condition Register Logical Instructions eee eeseeeseceseeeeeecnseceeceeeeesaeeenaeeneensees A 22 System Ee A 22 Trap OS ege ee A 23 Processor Control Inistrictions 322 424 0240 a AEN A 23 Cache Management Instructions 44 isies
311. eeeeeeeesteeeenteeeeaees 4 11 Machine Check Exception Register Settings eeeseresrrereerersrrsrrrreesees 4 12 DSI Exception Register Settings seseseeesssessesesereseeeesseessresseesseessseeessees 4 13 External Interrupt Register Settings sssesesesseessessessseeesstesseesseesseresseee 4 14 Alignment Interrupt Register Settings s eeseeeeseeeeeseessiseresresrrrererrersesere 4 15 KE 4 16 Trace Exception Repister Settings seid Gaede 4 17 Instruction and Data TLB Miss Exceptions Register Settings 4 18 Instruction Address Breakpoint Exception Register Settings 06 4 19 Breakpoint Action for Multiple Modes Enabled for the Same Address MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Page Number Table Number 4 20 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 5 10 5 11 5 12 5 13 6 1 6 2 6 3 6 4 6 5 6 6 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 7 10 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 8 10 8 11 Freescale Semiconductor Inc Tables Page Title Number System Management Interrupt Register Settings 00 0 0 cee eeeeeceereeceeeeeeeeeeeeeteeeees 4 34 MMU F at res Summary EE 5 2 Access Protection Options for Pages esssessssssesseesseessesserssseessseessresseesserssseesssees 5 10 Translation Exception Conditions sss ssssssessseeeseeeesseesseesserssetesseeessressesseessee
312. efore enabling external interrupts The PowerPC architecture supports four types of exceptions e Synchronous precise These are caused by instructions All instruction caused exceptions are handled precisely that is the machine state at the time the exception occurs is known and can be completely restored This means that excluding the trap and system call exceptions the address of the faulting instruction is provided to the exception handler and neither the faulting instruction nor subsequent instructions in the code stream will complete execution before the exception is taken Once the exception is processed execution resumes at the address of the faulting instruction or at an alternate address provided by the exception handler When an exception is taken due to a trap or system call instruction execution resumes at an address provided by the handler e Synchronous imprecise The PowerPC architecture defines two imprecise floating point exception modes recoverable and nonrecoverable Even though the MPC603e provides a means to enable the imprecise modes it implements these modes identically to the precise mode that is all enabled floating point enabled exceptions are always precise on the MPC603e e Asynchronous maskable The external system management interrupt SMI and decrementer interrupts are maskable asynchronous exceptions When these exceptions occur their handling is postponed until the next instruction and any
313. egment access An access to an I O address space The MPC603 defines separate memory mapped and I O address spaces or segments distinguished by the corresponding segment register T bit in the address translation logic of the MPC603 If the T bit is cleared the memory reference is a normal memory mapped access and can use the virtual memory management hardware of the MPC603 If the T bit is set the memory reference is a direct store access Effective address EA The 32 bit address specified for a load store or an instruction fetch This address is then submitted to the MMU for translation to either a physical memory address or an I O address Exception A condition encountered by the processor that requires special supervisor level processing Exception handler A software routine that executes when an exception is taken Normally the exception handler corrects the condition that caused the exception or performs some other meaningful task that may include aborting the program that caused the exception The address for each exception handler is identified by an exception vector offset defined by the architecture and a prefix selected via the MSR Exclusive state MEI state E in which only one caching device contains data that is also in system memory MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Execution synchronization A mech
314. egment register manipulation instructions e Translation lookaside buffer management instructions This section describes the user level cache management instructions defined by the VEA See Section 2 3 6 3 Memory Control Instructions OEA for information about supervisor level cache segment register manipulation and translation lookaside buffer management instructions The instructions listed in Table 2 35 provide user level programs the ability to manage on chip caches when they exist Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary Table 2 35 User Level Cache Instructions Name Mnemonic Operand Syntax Data Cache Block Flush dcbf rA rB Data Cache Block Set to Zero dcbz rA rB Data Cache Block Store dcbst rA rB Data Cache Block Touch dcbt rA rB Data Cache Block Touch for Store dcbist rA rB Instruction Cache Block Invalidate icbi rA rB As with other memory related instructions the effect of the cache management instructions on memory are weakly ordered If the programmer needs to ensure that cache or other instructions have been performed with respect to all other processors and system mechanisms a sync instruction must be placed in the program following those instructions Note that when data address translation is disabled MSR DR 0 the Data Cache Block Set to Zero debz instruction
315. em register unit SRU Floating point instructions that access or modify the FPSCR or CR mtfsb1 merfs mtfsfi mffs and mtfsf Instructions that manage caches and TLBs Instructions that directly access the GPRs load and store multiple word and load and store string instructions Instructions defined by the architecture to have synchronizing behavior e Dispatch serialized inhibit the dispatching of subsequent instructions until the serializing instruction is retired Dispatch serialization is used for instructions that access renamed resources used by the dispatcher and for instructions requiring refetch serialization including the following The load multiple instructions Imw Iswi and Ilswx The mtspr XER and merxr instructions The synchronizing instructions sync isync mtmsr rfi and sc e Refetch serialized instructions inhibit dispatching of subsequent instructions and force the refetching of subsequent instructions after the serializing instructions are retired The context synchronizing instruction isyne is refetch serializing MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc hee Execution Unit Timings 6 3 3 3 Execution Unit Considerations As previously noted the MPC603e can dispatch and retire two instructions per clock cycle The peak dispatch rate is affected by the availability of execution units o
316. ement When a data TLB miss on store exception is taken instruction execution for the handler begins at offset 0x01200 from the physical base address indicated by MSR IP 4 5 15 Instruction Address Breakpoint Exception 0x01300 The instruction address breakpoint is controlled by the IABR special purpose register IABR 0 29 holds an effective address to which each instruction s address is compared The exception is enabled by setting IABR 30 Note that the MPC603e ignores the translation enable bit TABR 31 The exception is taken when an instruction breakpoint address matches on the next instruction to complete The instruction tagged with the match is not completed before the instruction address breakpoint exception is taken The breakpoint action can be one of the following e Trap to interrupt vector 0x01300 default e Soft stop The bit settings for when an instruction address breakpoint exception is taken are shown in Table 4 18 Table 4 18 Instruction Address Breakpoint Exception Register Settings Register Setting Description SRRO Set to the address of the next instruction to be executed in the program for which the TLB miss exception was generated SRR1 0 15 Cleared 16 31 Loaded from MSR 16 31 MSR POW 0 EE 0 FEO 0 IR 0 TGPR 0 PR 0 SE 0 DR 0 ILE FP 0 BE 0 RI 0 IP ME FE1 0 LE Set to value of ILE The default breakpoint action is to trap before the execution of the matching instr
317. ement or instruction encoding Most significant byte MSB The highest order byte in an address registers data element or instruction encoding NaN An abbreviation for not a number a symbolic entity encoded in floating point format There are two types of NaNs signaling NaNs and quiet NaNs No op No operation A single cycle operation that does not affect registers or generate bus activity Normalization A process by which a floating point value is manipulated such that it can be represented in the format for the appropriate precision single or double precision For a floating point value to be representable in the single or double precision format the leading implied bit must be a 1 OEA operating environment architecture The level of the architecture that describes PowerPC memory management model supervisor level registers synchronization requirements and the exception model It also defines the time base feature from a supervisor level perspective Implementations that conform to the PowerPC OEA also conform to the PowerPC UISA and VEA Optional A feature such as an instruction a register or an exception that is defined by the PowerPC architecture but not required to be implemented MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Out of order An aspect of an operation that allows it to be performed ahead o
318. emory accesses previously initiated by the given processor are completed with respect to main memory before any memory accesses subsequently initiated by the Chapter 3 Instruction and Data Cache Operation For More Information On This Product Go to www freescale com Bus Operations Caused mz ceescale Semiconductor Inc processor access main memory The eieio instruction orders loads and stores to caching inhibited memory only The eieio instruction is intended for use only in performing memory mapped I O operations It enforces strong ordering of cache inhibited memory accesses during I O operations between the processor and I O devices When executed by the MPC603e the eieio instruction is treated as a no op caching inhibited load and store operations inhibited by the WIMG bits for the page are performed in strict program order 3 7 8 Instruction Cache Block Invalidate ch Instruction The execution of an icbi instruction causes all four cache sets indexed by the EA to be marked invalid No cache hit is required and no MMU translation is performed 3 7 9 Instruction Synchronize isync Instruction The isync instruction waits for all previous instructions to complete and then discards any previously fetched instructions causing subsequent instructions to be fetched or refetched from memory and to execute in the context established by the previous instructions This instruction has no effect on other processors or on the
319. ends in OxFF9 FFF e The dcbz instruction causes an alignment exception if the access is to a page or block with the W write through or I cache inhibit bit set in the TLB or BAT respectively A misaligned memory access that does not cause an alignment exception will not perform as well as an aligned access of the same type The resulting performance degradation due to misaligned accesses depends on how well each individual access behaves with respect to the memory hierarchy At a minimum additional cache access cycles are required that can delay other processor resources from using the cache More dramatically for an access to a noncacheable page each discrete access involves individual processor bus operations that reduce the effective bandwidth of that bus Finally note that when the MPC603e is in page address translation mode there is no special handling for accesses that fall into BAT regions 4 5 6 2 Load Store Multiple Alignment Exceptions Most alignment exceptions store the address as computed by the instruction in the DAR However when the operand of an Imw stmw Iwarx or stwex instruction is not word aligned that address value 4 is stored into the DAR MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc utes Exception Definitions 4 5 7 Program Exception 0x00700 The MPC603e implements the program exception as it is defined b
320. eneneesossssese0eee 3 24 Data Cache Block Store dcbst Instructpon 3 25 Data Cache Block Flush debf Instrueton 3 25 Enforce In Order Execution of I O Instruction eieio cccsccceeeeeeees 3 25 Instruction Cache Block Invalidate icbi Instruction 0 0 0 0 ceceecesseeeeeeeee 3 26 Instruction Synchronize isymc Instruction 2 0 0 cece eeeeseeeeeeeeeeeceseeneeees 3 26 Bus Operations Caused by Cache Control Instructions 0 0 0 cee eeeeeeeeeeseeeeeeee 3 26 PSS EE 3 27 MEI State Ee 3 28 Chapter 4 Exceptions ek PUL WEE 4 2 epes 4 6 Summary of Front End Exception Handling 4 8 Exception Processing eege eege 4 9 Exception Processing Ressel dan tvcciasdelcadeasdeccsdea ghey sdevenenddesgnesdawedcceatseaoedes 4 9 SRRO and SRR1 Bit Stns TEE 4 9 MSR EE 4 11 Enabling and Disabling Exceptions 0 00 0 ceeeeeseesseceseceeeeeeneecnaeeneeneeeeeneees 4 13 Steps for Exception Processing 2i cs sdcdacasasiaceeswedcadasacdensedagudedasesdadeeaesdaatavans 4 13 s tt ng ESR RE EE 4 14 Returning from an Exception Handler 4 14 PROCESS E 4 15 ek Pint AEM C ISS EE 4 15 Exception Define seein i e opted ul ee eal tet EASi 4 16 Reset Exceptions COx001 00 vxsc2 ccceciveccadacantvecdacyetevscseuceuscayecad avon eegenen Stage 4 17 Hard Reset and Power On Reset AA 4 17 Soft Ose EE 4 18 Machine Check Exception Ox00200 eecceeesseceeseeceeeeceeeeeceeeeeceeeeeesteeeees 4 19 Machine Check Exception Enabled MSR ME In 4 20 Checkstop St
321. ent Set for a store operation and cleared for a load operation Set if eciwx or ecowx is used and EAR E is cleared MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconduct In moleinemstion Specific Information Table 1 5 Exceptions and Conditions continued Exception Type Vector Offset hex Causing Conditions ISI 00400 An ISI exception is caused when an instruction fetch cannot be performed for any of the following reasons e The effective logical address cannot be translated That is there is a page fault for this portion of the translation so an ISI exception must be taken to load the PTE and possibly the page into memory e The fetch access is to a direct store segment indicated by SRR1 3 set e The fetch access violates memory protection indicated by SRR1 4 set If the key bits Ks and Kp in the segment register and the PP bits in the PTE are set to prohibit read access instructions cannot be fetched from this location External interrupt 00500 An external interrupt is caused when MSR EE 1 and the INT signal is asserted Alignment 00600 An alignment exception is caused when the MPC603e cannot perform a memory access for any of the reasons described below e The operand of a floating point load or store instruction is not word aligned e The operand of Imw stmw Iwarx and stwe
322. er Optional Gg E Breakpoint Register g Op SPR 1010 SPR 282 1 These registers are MPC603e specific PID6 603e and PID7t 603e They may not be supported by other processors of this family Figure 1 2 Programming Model Registers MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc necitic Information The HIDO bits with changed bit assignments are shown in Table 1 3 The HIDO bits that are not shown here are implemented as shown in Section 2 1 2 1 Hardware Implementation Registers HIDO and HID1 Table 1 3 Additional Changed HIDO Bits Bits Description 24 Enable M bit on bus for instruction fetches IFEM PID7t 603e only 0 Mbit disabled Instruction fetches are treated as nonglobal on the bus 1 Instruction fetches reflect the M bit from the WIM settings 25 26 Reserved 28 Address broadcast enable Controls whether certain address only operations such as cache operations are broadcast on the 60x bus 0 Address only operations affect only local caches and are not broadcast 1 Address only operations are broadcast on the 60x bus Affected instructions are debi dcbf and dcbst Note that these cache control instruction broadcasts are not snooped by the PID7t 603e Refer to Section 1 3 3 Cache Implementation 29 30 Reserved 1 3 1 3 General Purpose Registers GPRs The PowerPC architec
323. er Set of the Programming Environments Manual e The isync instruction which waits for all previous instructions to complete and then discards any fetched instructions causing subsequent instructions to be fetched or refetched from memory and to execute in the context privilege translation protection etc established by the previous instructions e The stwex instruction to clear any outstanding reservations which ensures that an Iwarx instruction in the old process is not paired with an stwex instruction in the new process The operating system should set the MSR RI bit as described in Section 4 2 4 Setting MSR RI 4 4 Exception Latencies Latencies for taking various exceptions depend on the state of the machine when the exception conditions occur This latency may be as short as one cycle in which case an exception is signaled in the cycle following the appearance of the exception condition The latencies are as follows e Hard reset and machine check In most cases a hard reset or machine check exception will have a single cycle latency A two to three cycle delay may occur only when a predicted instruction is next to complete and the branch guess that forced this instruction to be predicted was resolved to be incorrect e Soft reset The latency of a soft reset exception is affected by recoverability The time to reach a recoverable state may depend on the time needed to complete or except an instruction at
324. erialization Table 6 3 provides the latencies for the condition register logical instructions Table 6 3 Condition Register Logical Instructions Mnemonic Primary Extended Unit ae mert 19 000 SRU 1 crnor 19 033 SRU 1 crandc 19 129 SRU 1 crxor 19 193 SRU 1 crnand 19 225 SRU 1 crand 19 257 SRU 1 creqv 19 289 SRU 1 crorc 19 417 SRU 1 cror 19 449 SRU 1 mfcr 31 019 SRU 1 Chapter 6 Instruction Timing For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Latency Summary Table 6 3 Condition Register Logical Instructions continued Mnemonic Primary Extended Unit Latency in Cycles mterf 31 144 SRU 1 merxr 31 512 SRU 1 amp Note Cycle times marked with amp require a variable number of cycles due to serialization Table 6 4 provides the latencies for the integer instructions Table 6 4 Integer Instructions Mnemonic Primary Extended Unit wed twi 03 Integer 2 mulli 07 Integer 2 3 subfic 08 Integer 1 cmpli 10 Integer amp SRU 1 cmpi 11 Integer amp SRU 1 addic 12 Integer 1 addic 13 Integer 1 addi 14 Integer amp SRU 1 addis 15 Integer amp SRU 1 rlwimi 20 Integer 1 riwinm 21 Integer 1 rlwnm 23 Integer 1 ori 24 Integer 1 or
325. erwise Instruction Fetch with N Bit Set in Segment Descriptor Page Address No Execute Translation Generate 52 Bit Virtual Address From Segment Descriptor Compare Virtual Address with TLB Entries TLB Hit Case O debz Instruction d withWorl 1 Otherwise Alignment Exception Check Page Memory Protection Violation Conditions See the Programming Environments Manual See the Programming Environments Access Permitted Access Prohibited Manual Store Access with PTE C 0 Otherwise Page Table Search Operation See Figure 5 9 Page Memory Protection Violation PA 0 31 RPN A 20 31 Continue Access to Memory Subsystem with WIMG Bits from PTE Figure 5 8 Page Address Translation Flow for 32 Bit Implementations TLB Hit MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Mes able BEE 4 Ifa match is not found step 3 is repeated for each of the other seven PTEs in the primary PTEG If a match is found the table search process continues as described in step 8 If a match is not found within the eight PTEs of the primary PTEG the address of the secondary PTEG is generated 5 The first PTE PTEO in the secondary PTEG is read from memory Again because PTE reads typically have a WIM bit combination of 0b001 an entire cache line is burst into the on chip cache 6 The PTE in the selected secondar
326. es using the new MSR value at a location specific to the exception type The location is determined by adding the exception s vector see Table 4 2 to the base address determined by MSR IP If IP is cleared exceptions are vectored to the physical address Ox000n_nnnzn If IP is set exceptions are vectored to the physical address OxFFFn_nnnn For a machine check exception that occurs when MSR ME 0 machine check exceptions are disabled the processor enters the checkstop state the machine stops executing instructions See Section 4 5 2 Machine Check Exception 0x00200 4 2 4 Setting MSR RI The operating system should handle MSR RI as follows In the machine check and system reset exceptions If SRR1 RI is cleared the exception is not recoverable If it is set the exception is recoverable with respect to the processor In each exception handler When enough state information has been saved that a machine check or system reset exception can reconstruct the previous state set MSR RI In each exception handler Clear MSR RI set the SRRO and SRR1 registers appropriately and then execute rfi Note that the RI bit being set indicates that with respect to the processor enough processor state data is valid for the processor to continue but it does not guarantee that the interrupted process can resume 4 2 5 Returning from an Exception Handler The Return from Interrupt rfi instruction performs context synchroniza
327. escriptions of how the MPC603e execution units work and how those units interact with other parts of the processor such as the instruction fetching mechanism register files and caches It gives examples of instruction sequences showing potential bottlenecks and how to minimize their effects Finally it includes tables that identify the unit that executes each instruction implemented on the MPC603e the latency for each instruction and other information that is useful for the assembly language programmer 6 1 Terminology and Conventions This section provides an alphabetical glossary of terms used in this chapter These definitions are provided as a review of commonly used terms and as a way to point out specific ways these terms are used in this chapter e Branch prediction The process of guessing whether a branch will be taken Such predictions can be correct or incorrect the term predicted as it is used here does not imply that the prediction is correct successful The PowerPC architecture defines a means for static branch prediction as part of the instruction encoding e Branch resolution The determination of whether a branch is taken or not taken A branch is said to be resolved when the processor can determine which instruction path to take If the branch is resolved as predicted the instructions following the predicted branch that may have been speculatively executed can complete see completion If the branch is not resolved as
328. ess for which a normal store operation would cause a DSI exception the MPC603e takes the DSI exception without checking for the reservation If the XER indicates that the byte count for an Iswi or stswi instruction is zero a DSI exception does not occur regardless of the effective address The condition that caused the exception is defined in the DSISR These conditions also use the data address register DAR as shown in Table 4 12 When a DSI exception is taken instruction execution for the handler begins at offset 0x00300 from the physical base address indicated by MSR IP The architecture permits certain instructions to be partially executed when they cause a DSI exception These are as follows e Load multiple or load string instructions some registers in the range of registers to be loaded may have been loaded e Store multiple or store string instructions some bytes of memory in the range addressed may have been updated In these cases the number of registers and amount of memory altered are instruction and boundary dependent However memory protection is not violated Furthermore if some of the data accessed is in direct store space SR T 1 and the instruction is not supported for direct store accesses the locations in direct store space are not accessed MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ee Exception Defin
329. ess memory directly that is reads and writes when caching is disabled caching inhibited accesses and stores in write through mode Four beat burst transactions which MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc necitic Information always transfer an entire cache block 32 bytes are initiated when a line is read from or written to memory 1 3 7 2 Signals The MPC603e signals are grouped as follows Address arbitration signals The MPC603e uses these signals to arbitrate for address bus mastership Address transfer start signals These signals indicate that a bus master has begun a transaction on the address bus Address transfer signals These signals consisting of address bus address parity and address parity error signals are used to transfer the address and to ensure the integrity of the transfer Transfer attribute signals These signals provide information about the type of transfer such as the transfer size and whether the transaction is bursted write through or caching inhibited Address transfer termination signals These signals are used to acknowledge the end of the address phase of the transaction They also indicate whether a condition exists that requires the address phase to be repeated Data arbitration signals The MPC603e uses these signals to arbitrate for data bus mastership Data transfer signals
330. essor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc A AACK signal 7 15 ABB signal 7 4 8 7 ABE address broadcast enable bit 3 23 Address bus address tenure 8 6 address transfer An 7 6 APE 7 8 8 12 APn 7 7 address transfer attribute CI 7 13 CSEn 7 14 GBL 7 14 TBST 7 12 8 13 TCn 7 13 8 19 TSIZn 7 12 8 13 TTn 7 9 8 12 WT 7 14 address transfer start TS 7 6 8 11 XATS MPC603 specific 1 6 address transfer termination AACK 7 15 ARTRY 3 21 7 15 terminating address transfer 8 19 arbitration signals 7 2 8 7 bus arbitration ABB 7 4 8 7 BG 7 4 8 7 BR 7 3 8 7 bus parking 8 10 Address calculation branch instructions 2 36 effective address 2 20 floating point load and store 2 34 integer load and store 2 30 Address translation see Memory management unit Addressing conventions addressing modes 2 19 alignment 2 14 Aligned data transfer 2 14 8 14 8 18 Index Alignment data transfers 2 14 8 14 exception 4 24 5 15 rules 2 14 An signals 7 6 APE signal 7 8 8 12 APn signals 7 7 Arbitration system bus 8 9 8 21 ARTRY signal 3 21 7 15 Atomic memory references stwex 2 39 using lwarx stwex 3 20 B BG signal 7 4 8 7 Block address translation block address translation flow 5 11 selection of block address translation 5 9 Boundedly undefined definition 2 17 BR signal 7 3 8 7 Branch
331. essor User s Manual For More information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Legend Table A 46 PowerPC Instruction Set Legend continued UISA VEA OEA Supervisor Level Optional 64 Bit Form a x lt srawx srawix srdx srwx stb stbu stbux x x UO oj x XxX ze stbx std stdex el We stdu stdux 1 ll cl cl ll lt 2 el Wei stdx stfd stfdu stfdux stfidx stfiwx 3 stfs stfsu stfsux stfsx sth sthbrx sthu sthux sthx stmw 4 stswi 4 stswx 4 stw stwbrx stwcx stwu lt lt ej e j SH HS Sy Sy e Ss HS Ss 2 2 2 lt SS a ses a Ses Ss Ss Ss OS Ss OS el eS Ot a x oj XxX x o X X UO XxX X UO xX O X x UO UO X X x J of X Xx stwux Appendix A PowerPC Instruction Set Listings For More information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Legend Table A 46 PowerPC Instruction Set Legend continued UISA VEA OEA Supervisor Level Optional 64 Bit Form stwx V X subfx V XO subfcx V XO subfex V XO subfic V D subfmex V XO subfzex V XO sync V X td V V X tdi V V D tlbia 2 3 V V V X tlbie 2 3 V V V
332. essor state signals Test and control signals provide diagnostics for selected internal circuits The system interface supports bus pipelining allowing the address tenure of one transaction to overlap the data tenure of another The extent of the pipelining depends on external arbitration and control circuitry Similarly the MPC603e supports split bus transactions for systems with multiple potential bus masters one device can have mastership of the address bus while another has mastership of the data bus Allowing multiple bus transactions to occur simultaneously increases the available bus bandwidth for other activity and as a result improves performance Chapter 1 Overview For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Implementation Specific Information Address lt Data Address Arbitration lt _ Data Arbitration Address Start Le Data Transfer Address Transfer MPC603e LL gt Data Termination Transfer Attribute Lage Processor State Address Termination lt Test And Control Clocks 3 3V T Figure 1 4 System Interface The MPC603e supports multiple masters through a bus arbitration scheme that allows various devices to compete for the shared bus resource Arbitration logic can implement priority protocols such as fairness and can park masters to avoid arbitration overhead The MEI protocol ensures coherency among multiple devices and system memo
333. esssees 5 15 Other MMU Exception Conditions seseseseeesseeesseesseesseseseessstesseessersseessseesssresseesse 5 16 Instruction Summary MMU Control 5 17 KIEREN 5 18 Table Search Operations to Update History Bits TLB Hit Case eee 5 21 Model for Guaranteed R and C Bit Seng 5 24 Implementation Specific Resources for Table Search Operations ce eeeeeeeees 5 32 Implementation Specific SRR1 Bits oe eee esseceseeeeeeesseeceaeceseeeseeeeseecnaeeneensees 5 33 DCMP and ICMP Bit Settings ee e Eege EE 5 34 HASH and HASH2 Bit Seti eiioy ces fo 5 Gos eedeecuesasccsycansecavacndacsined oosanaenieess 5 35 EE EE 5 35 BANC Tee tee 6 26 System Register Instructions t11 3 2 scscsdie ene ieee A Ae 6 27 Condition Register Logical Instructons ices ceseesseeeseeceseceeeeeseeeeseecnaecseessneeenees 6 27 Integer Instructions 322 i 4ci0i eteeiieieed nce ikea ncieoleds ee SERA SEELEN 6 28 Floating Pom burg gedeelter Eege 6 30 Load and Store IisinictiOns eege Ee 6 31 Transfer Encoding for the Bus Master 22 25 05 2 cats Bolan oes 7 9 Snoop Hit RESPONSES ee ee teens EE 7 10 Implementation Specific Transfer Encodmg ces ceeesesceesseceseceeeeeeeeesseecnaeenseensees 7 11 Data Tratten eh eeh EE e Ee 7 12 Encodings for PCOS Sis tals E 7 13 Data Bus lane Assigniment c24 22235 lati oti late Acie dianlas tedden 7 19 DP O37 Signa Assi sews ee de 7 20 Pipeline Tracking Outputs s2 c 42 2 nieen teed ele aan nl ane 7 28 CLK_OUT Signal Configu
334. evice configuration parameters and put the device into a power saving mode Furthermore every time the device driver is called it needs to check the power status of the device and restore the device to the full on state if the device is in a power saving mode 9 2 Dynamic Power Management Dynamic power management DPM automatically powers up and down the individual execution units of the MPC603e based on the contents of the instruction stream For example if no floating point instructions are being executed the floating point unit is automatically powered down Power is not actually removed from the execution unit instead each execution unit has an independent clock input which is automatically controlled on a clock by clock basis Because CMOS circuits consume negligible power when they are not switching stopping the clock to an execution unit effectively eliminates its power consumption The operation of DPM is completely transparent to software or any external hardware Dynamic power management is enabled by setting HIDO 11 on power up following a hard reset sequence HRESET Chapter 9 Power Management For More Information On This Product Go to www freescale com reescale Semiconductor Inc Programmable Power Modes 9 3 Programmable Power Modes Hardware can enable a power management state through external asynchronous interrupts The hardware interrupt causes the transfer of program flow to interrupt handler code The app
335. exceptions associated with that instruction completes execution If there are no instructions in the execution units the exception is taken immediately on determination of the correct restart address for loading SRRO e Asynchronous nonmaskable There are two nonmaskable asynchronous exceptions system reset and the machine check exception These exceptions may not be recoverable or may provide a limited degree of recoverability All exceptions report recoverability through MSR RI Chapter 1 Overview For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Implementation Specific Information 1 3 4 2 As specified by the PowerPC architecture all MPC603e exceptions can be described as either precise or imprecise and either synchronous or asynchronous Asynchronous exceptions some of which are maskable are caused by events external to the processor s execution synchronous exceptions which are all handled precisely by the MPC603e are caused by instructions The MPC603e exception classes are shown in Table 1 4 Implementation Specific Exception Model Table 1 4 Exception Classifications Synchronous Asynchronous Precise Imprecise Exception Type Asynchronous nonmaskable Imprecise Machine check System reset Asynchronous maskable Precise External interrupt Decrementer System management interrupt Synchronous Precise Instruction caused exceptions Although e
336. executes through one level of prediction The microprocessor may not predict a branch if a prior branch instruction is still unresolved The number of instructions that can be executed after branch prediction is limited by the fact that instructions in the predicted stream cannot update the register files or memory until the branch is resolved That is instructions may be dispatched and executed but cannot reach the write back stage in the completion unit instead it stalls in the completion queue When CQ is full no more instructions can be dispatched In the case of a misprediction the MPC603e is able to redirect the machine state rather effortlessly because the programing model has not been updated When a branch is found to be mispredicted all instructions that were dispatched subsequent to the predicted branch instruction are simply flushed from the completion queue and their results flushed from the rename registers No architected register state needs to be restored because no architected register state was modified by the instructions following the unresolved predicted branch 6 4 1 2 1 Predicted Branch Timing Examples Figure 6 7 shows how both taken and non taken branches are handled and how the MPC603e handles both correct and incorrect predictions The example shows the timing for the following instruction sequence add add be mulhw be TO fadd and add add add add and or IOO B GA AA CH H J J a H d d d d d Op WBNR
337. f 19 crfD 00 crfS 00 00000 0 0 merfs 63 crfD 00 crfS 00 00000 64 0 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Ing Sorted by Mnemonic Table A 1 Complete Instruction List Sorted by Mnemonic continued Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 merxr 31 crfD 00 00000 00000 512 0 mfcr 31 D 00000 00000 19 0 mffsx 63 D 00000 00000 583 Re mfmsr 2 31 D 00000 00000 83 0 mfspr gt 31 D spr 339 0 mfsr 2 31 D SR 00000 595 0 mfsrin 2 31 D 00000 B 659 0 mftb 31 D tor 371 0 mtcerf 31 S CRM 0 144 0 mtfsb0x 63 crbD 00000 00000 70 Re mtfsb1 x 63 crbD 00000 00000 38 Re mtfsfx 63 0 F 0 B 711 Re mtfsfix 63 crfD 00 00000 IMM 0 134 Re mtmsr 2 31 S 00000 00000 146 0 mtspr gt 31 S spr 467 0 mtsr 2 31 S SR 00000 210 0 mtsrin 2 31 S 00000 B 242 0 mulhdx 1 31 D A B 0 73 Re mulhdux 31 D A B 0 9 Re mulhwx 31 D A B 0 75 Re mulhwux 31 D A B 0 11 Re mulldx 31 D A B OE 233 Rc mulli 7 D A SIMM mullwx 31 D A B OE 235 Rc nandx 31 S A B 476 Rc negx 31 D A 00000 OE 104 Rc norx 31 S A 124 Rc orx 31 S A 444 Rc orcx 31 S A 412 Rc ori 24 S A UIMM oris 25 S A UIMM rfi 2 19 00000 00000 00000 50 0 ridelx 1 30 S A B mb Re rldcrx 1 30 S A B me Re ridic
338. f one that may have preceded it in the sequential model for example speculative operations An operation is said to be performed out of order if at the time that it is performed it is not known to be required by the sequential execution model See In order Out of order execution A technique that allows instructions to be issued and completed in an order that differs from their sequence in the instruction stream Overflow An condition that occurs during arithmetic operations when the result cannot be stored accurately in the destination register s For example if two 32 bit numbers are multiplied the result may not be representable in 32 bits Since the 32 bit registers of the MPC603e cannot represent this sum an overflow condition occurs Page A region in memory The OEA defines a page as a 4 Kbyte area of memory aligned on a 4 Kbyte boundary Page access history bits The changed and referenced bits in the PTE keep track of the access history within the page The referenced bit is set by the MMU whenever the page is accessed for a read or write operation The changed bit is set when the page is stored into See Changed bit and Referenced bit Page fault A page fault is a condition that occurs when the processor attempts to access a memory location that does not reside within a page not currently resident in physical memory On PowerPC processors a page fault exception condition occurs when a matching valid page table entry
339. face Operation Power Management PowerPC Instruction Set Listings Instructions Not Implemented Revision History Glossary of Terms and Abbreviations Index For More Information On This Product Go to www freescale com
340. fective address computations for both data and instruction accesses use 32 bit unsigned binary arithmetic A carry from bit 0 is ignored Load and store operations have three categories of effective address generation e Register indirect with immediate index mode e Register indirect with index mode e Register indirect mode Section 2 3 4 3 2 Integer Load and Store Address Generation describes effective address generation for load and store operations Branch instructions have three categories of effective address generation e Immediate e Link register indirect e Count register indirect Section 2 3 4 4 1 Branch Instruction Address Calculation describes branch instruction effective address generation 2 3 2 4 Synchronization The sychronization described in this section refers to the state of the processor performing the sychronization MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING ten Sa 2 3 2 4 1 Context Synchronization The System Call sc and Return from Interrupt rfi instructions perform context synchronization by allowing previously issued instructions to complete before performing a change in context Execution of one of these instructions ensures the following e No higher priority exception exists sc e All previous instructions have completed to a point where they can no longer cause an exception If a prior
341. fer to Chapter 2 Programming Model in this book and Chapter 8 Instruction Set in the Programming Environments Manual 3 6 7 Cache Reaction to Specific Bus Operations There are several bus transaction types defined for the MPC603e bus The MPC603e must snoop these transactions and perform the appropriate action to maintain memory coherency as shown in Table 3 6 A processor may assert ARTRY for any bus transaction due to internal conflicts that prevent the appropriate snooping The transactions in Table 3 6 correspond to the transfer type signals TT 0 4 described in Section 7 2 4 1 Transfer Type TT 0 4 Table 3 6 Response to Bus Transactions Snooped Transaction MPC603e Response Clean block No action is taken Flush block No action is taken Write with flush Write with flush and write with flush atomic operations occur after the processor issues a Write with flush atomic store or stwex instruction respectively e If the addressed block is in the exclusive state the address snoop forces the state of the addressed block to invalid e If the addressed block is in the modified state the address snoop causes ARTRY to be asserted and initiates a push of the modified block out of the cache and changes the state of the block to invalid e The execution of an stwex instruction cancels the reservation associated with any address Kill block The kill block operation is an address only bus transaction init
342. flects the original state as determined by address translation independent of cache locked or disabled status A snoop hit to a locked L1 data cache performs as if the cache were not locked A cache block invalidated by a snoop remains invalid until the cache is unlocked To prevent locking during a cache access a sync instruction must precede the setting of DLOCK 20 ICFI2 Instruction cache flash invalidate 0 The instruction cache is not invalidated The bit is cleared when the invalidation operation begins usually the next cycle after the write operation to the register The instruction cache must be enabled for the invalidation to occur 1 An invalidate operation is issued that marks the state of each instruction cache block as invalid without writing back modified cache blocks to memory Cache access is blocked during this time Bus accesses to the cache are signaled as a miss during invalidate all operations Setting ICFI clears all the valid bits of the blocks and the PLRU bits to point to way LO of each set For 603e processors the proper use of the ICFI and DCFI bits is to set them and clear them with two consecutive mtspr operations 21 DCFI2 Data cache flash invalidate 0 The data cache is not invalidated The bit is cleared when the invalidation operation begins usually the next cycle after the write operation to the register The data cache must be enabled for the invalidation to occur 1 An invalidate operation
343. folding 6 17 Branch instructions address calculation 2 36 branch instructions 2 36 A 22 condition register logical 2 37 A 22 system linkage 2 43 A 22 trap 2 38 A 23 Branch prediction 6 1 6 18 Branch processing unit branch instruction timing 6 20 execution timing 6 17 latency branch instructions 6 26 overview 1 9 Branch resolution definition 6 1 Burst data transfers 32 bit data bus 8 14 64 bit data bus 8 13 transfers with data delays timing 8 35 Burst transactions 3 9 Bus arbitration see Data bus Bus configurations 8 37 8 39 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bus interface unit BIU 3 2 Byte ordering default 2 19 Byte reverse instructions 2 32 A 20 C Cache cache miss 6 13 characteristics 3 1 instructions 2 41 2 45 3 22 A 23 MEI state definition 3 16 organization instruction data 3 3 3 8 overview 1 24 Cache arbitration 6 10 Cache block push operation 3 9 Cache block definition 3 1 Cache cast out operation 3 8 Cache coherency actions on load operations 3 19 actions on store operations 3 19 copy back operation 3 12 in single processor systems 3 19 MET protocol 3 15 out of order execution 3 14 overview 3 3 reaction to bus operations 3 20 WIMG bits 3 10 3 14 8 28 write back mode 3 12 Cache hit 6 10 Cache management instructions 2 41 2 45 3 22 A 23 Cache operations basic data cache operations 3 8
344. from the data bus that is output by the special device The section should be completely replaced with the following The supervisor level cache management instruction in the PowerPC architecture debi should not be used on the 603e The user level dcht instruction described in Section 2 3 5 3 Memory Control Instructions VEA and in Section 3 7 Cache Control Instructions should be used when the program needs to invalidate cache blocks Note that the debf instruction causes modified blocks to be flushed to system memory if they are the target of a dcbf instruction whereas by definition in the PowerPC architecture the debi instruction only invalidates modified blocks Change the last sentence of the paragraph to the following To prevent the cache from being enabled or disabled in the middle of a data access an isync instruction should be issued before changing the value of ICE Change the last sentence of the first paragraph to the following To prevent the cache from being enabled or disabled in the middle of a data access a sync instruction should be issued before changing the value of DCE MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com 3 5 5 2 3 14 4 1 4 3 4 1 4 4 4 1 4 5 4 1 4 6 4 2 4 13 4 2 2 4 15 4 5 4 17 4 5 4 18 Freescale Semicond uctor doe Revision 1 to Revision 2 Remove the third condition of the out of order load o
345. from an eight word boundary that is bits A27 A31 of the effective addresses are zero thus a cache block never crosses a page boundary Misaligned accesses across a page boundary can incur a performance penalty Note that address bits A20 A26 provide an index to select a set Bits A27 A31 select a byte within a block The tags consists of bits PAO PA19 Address translation occurs in parallel such that higher order bits the tag bits in the cache are physical Note that the replacement algorithm is strictly an LRU algorithm that is the least recently used block is filled with new instructions on a cache miss Chapter 3 Instruction and Data Cache Operation For More Information On This Product Go to www freescale com le Semiconductor Inc Instruction Cache organiza Saba 128 Sets Block 0 Ke Words 0 7 i ES E State e 0 7 Se Address Tag 2 i e D Words Block Figure 3 1 Instruction Cache i Address Tag 0 i Address Tag 1 e Block 1 Block 2 Block 3 3 1 2 Instruction Cache Fill Operations The MPC603e instruction cache blocks are loaded in four 64 bit beats with the critical double word loaded first The instruction cache allows sequential fetching during a cache block load On a cache miss the critical and following double words read from memory are simultaneously written to the instruction cache and forwarded to the dispatch queue thus minimizing stalls due to cache fill latency There is
346. g and prefetching from the addressed memory location When an access requires coherency the processor performing the access must inform the coherency mechanisms throughout the system that the access requires memory coherency The M attribute determines the kind of access performed on the bus global or local The WIMG attributes occupy 4 bits in the BAT registers for block address translation and in the PTEs for page address translation The WIMG bits are programmed as follows e The operating system uses the mtspr instruction to program the WIMG bits in the BAT registers for block address translation The IBAT register pairs do not have a G bit and all accesses that use the IBAT register pairs are considered not guarded e The operating system writes the WIMG bits for each page into the PTEs in system memory as it sets up the page tables Note that for accesses performed with direct address translation MSR IR 0 or MSR DR 0 for instruction or data access respectively the WIMG bits are automatically generated as Ob0011 the data is write back caching is enabled memory coherency is enforced and memory is guarded 3 5 1 Write Through Attribute W When an access is designated as write through W 1 if the data is in the cache a store operation updates the cached copy of the data In addition the update is written to the external memory location as described below While the PowerPC architecture permits multiple store ins
347. ge address translation 5 8 5 11 5 27 page history status 5 11 5 21 5 24 page table search operation 5 27 segment model 5 20 software table search operation 5 31 5 36 5 37 Memory synchronization instructions 2 38 2 41 A 21 stwex 2 39 Memory cache access modes performance impact of copy back mode 6 23 see also WIMG bits Misaligned accesses 2 14 Misaligned data transfer 8 16 Move instructions 2 29 MPC603e features hardware 1 6 list of features 1 3 PID7t specific 1 5 instructions 2 47 overview 1 1 1 16 PID7t features 1 5 HIDO bits PID7t specific 3 23 processor identification PID number definition 1 1 MPC603 specific features 1 6 MSR machine state register bit settings 4 11 DR IR bit 4 12 EE bit 4 11 FEO FE1 bits 4 13 POW bit 2 5 4 11 C 4 RI bit 4 14 settings due to exception 4 16 TGPR bit 2 5 4 11 C 4 N No DRTRY mode 8 39 Nondenormalized mode support 2 26 O Operand conventions 2 13 Operand placement and performance 2 15 Operating environment architecture OEA xxvii 1 15 2 43 Optional instructions A 36 P Page address translation page address translation flow 5 27 page size 5 20 selection of page address translation 5 8 5 13 table search operation 5 27 TLB organization 5 25 Page history status R and C bit recording 5 11 5 21 5 24 Page tables resources for table search operations 5 31 software table search operation 5 31 5 36 table search for
348. gister for loading TLBs tlbli rB instruction for loading ITLB entries tlbId rB instruction for loading DTLB entries Shadow registers for GPRO GPR3 can use r0 r3 in table search handler without corruption of r0 r3 in context that was previously executing 5 1 1 Memory Addressing A program references memory using the effective logical address computed by the processor when it executes a load store or cache instruction and when it fetches the next instruction The effective address is translated to a physical address according to the procedures described in Chapter 7 Memory Management in the Programming Environments Manual augmented with information in this chapter The memory subsystem uses the physical address for the access For a complete discussion of effective address calculation see Section 2 3 2 3 Effective Address Calculation 5 1 2 MMU Organization Figure 5 1 shows the conceptual organization of a PowerPC MMU in a 32 bit implementation note that it does not describe the specific hardware used to implement the memory management function for a particular processor Processors may optionally implement on chip TLBs and may optionally support the automatic search of the page tables for PTEs In addition other hardware features invisible to the system software not depicted in the figure may be implemented Figure 5 2 and Figure 5 3 show the conceptual organization of the MPC603e instruc
349. h 1 10 System Restster Unit SRU EE 1 10 Completion Wi 01 EE 1 11 Memory Subsystem Support cstsscssscvssyensccesncccusaaseosatissusnceespavcavasecpeteaseractese 1 11 Memory Management Units OMMUe 1 11 Cache Eege gids ise eee ege ede eas eee eee 1 12 Processor Bus eenegen 1 13 System Support Functions EE 1 14 Power Management nienie E E E a E G RS 1 14 June B se D crementer e eege EE de 1 15 IEEE 1149 1 JTAG COP Test Interface cccccsssercecessercecesssreccesees 1 15 Clock WIIG HR tengchiaet ge iert ee Aug eet 1 15 PowerPC Architecture Implementation scesecssecceeeeeeeeteecerteccetseeeoneees 1 15 Contents v For More information On This Product Go to www freescale com Paragraph Number 1 3 1 3 1 1 3 1 1 1 3 1 2 1 3 1 3 1 3 1 4 1 3 1 5 1 3 1 6 1 3 1 7 1 3 1 8 1 3 1 9 1 3 1 9 1 1 3 1 9 2 1 3 2 1 3 2 1 1 3 2 2 1 3 3 1 3 3 1 1 3 3 2 1 3 4 1 3 4 1 1 3 4 2 1 3 5 1 3 5 1 1 3 5 2 1 3 6 1 3 7 1 3 7 1 E re 1 3 7 3 2 1 2 1 1 2 1 2 22 1 212 2 21 23 Freescale Semiconductor Inc Contents Page Title Number Implementation Specific Intormapon cee eeeeeseecsseceseeeeeeesseeceaeceseesseeennees 1 16 Programming Mega ee 1 17 Processor Version Reseter ENVKt EEN Eed 1 17 Hardware Implementation Register 0 HIDO cece eeeeeceeeseeeenteeeenee 1 17 General Purpose Registers GPRS cc 0 3 0 ceeeepeidecetagees ales ieee aes 1 19 Floating Point Registers FPRS AAA 1
350. h Instruction Address Calculation Branch instructions can change the instruction sequence Instruction addresses are always assumed to be word aligned the processor ignores the two low order bits of the generated branch target address Branch instructions compute the effective address EA of the next instruction address using the following addressing modes e Branch relative e Branch conditional to relative address e Branch to absolute address MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc nstruction Set Summary e Branch conditional to absolute address e Branch conditional to link register e Branch conditional to count register 2 3 4 4 2 Branch Instructions Table 2 28 lists the branch instructions provided by the processors that implement the PowerPC architecture To simplify assembly language programming a set of simplified mnemonics and symbols is provided for the most frequently used forms of branch conditional compare trap rotate and shift and certain other instructions See Appendix F Simplified Mnemonics in the Programming Environments Manual for a list of simplified mnemonic examples Table 2 28 Branch Instructions Name Mnemonic Operand Syntax Branch b ba bl bla target_addr Branch Conditional bc bca bel bcla BO Bl target_addr Branch Conditional to Count Register bcctr bccirl BO BI Branch Conditi
351. hat caused the exception SRR1 0 15 Cleared 16 31 Loaded with MSR 16 31 MSR POW 0 EE 0 FEO 0 IR 0 TGPR 0 PR 0 SE 0 DR 0 ILE FP 0 BE 0 RI 0 IP ME FE1 0 LE Set to value of ILE DSISR 0 Set if a load or store instruction results in a direct store error exception 1 Set by the data TLB miss exception handler if the translation of an attempted access is not found in the primary hash table entry group HTEG or in the rehashed secondary HTEG or in the range of a DBAT register otherwise cleared 2 3 Cleared 4 Set if a memory access is not permitted by the page or BAT protection mechanism otherwise cleared 5 Set if the lwarx or stwex instruction is attempted to direct store space 6 Set for a store operation and cleared for a load operation 7 31 Cleared DAR Set to the effective address of a memory element as described in the following list e A byte in the first word accessed in the page that caused the DSI exception for a byte half word or word memory access e A byte in the first word accessed in the BAT area that caused the DSI exception for a byte half word or word access to a BAT area e A byte in the block that caused the exception for icbi dcbz dcbst dcbf or debi instructions e Any EA in the memory range addressed for direct store exceptions DSI exceptions can occur for any of the following reasons e The instruction is not supported for the type of memory addressed e Any access to a direct
352. have not completed Reservation The processor establishes a reservation on a cache block of memory space when it executes an Iwarx instruction to read a memory semaphore into a GPR Reservation station A buffer between the dispatch and execute stages that allows instructions to be dispatched even though the results of instructions on which the dispatched instruction may depend are not available RISC reduced instruction set computing An architecture characterized by fixed length instructions with nonoverlapping functionality and by a separate set of load and store instructions that perform memory accesses Glossary of Terms and Abbreviations For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Scan interface The MPC603e test interface Secondary cache A cache memory that is typically larger and has a longer access time than the primary cache A secondary cache may be shared by multiple devices Also referred to as L2 or level 2 cache Set v To write a nonzero value to a bit or bit field the opposite of clear The term set may also be used to generally describe the updating of a bit or bit field Set n A subdivision of a cache Cacheable data can be stored in a given location in one of the sets typically corresponding to its lower order address bits Because several memory locations can map to the same location cached data is typically placed in the set whose cache
353. have up to two transactions operating on the bus at any given time through the use of address pipelining Instruction Cache BIU I Cache Control LD Addr Control System Bus Address Address Data Figure 3 5 Bus Interface Address Buffers For additional information about the MPC603e bus interface and the bus protocols refer to Chapter 8 System Interface Operation 3 10 MEI State Transactions Table 3 8 shows MEI state transitions for various operations Bus operations are described in Table 3 6 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 3 8 MEI State Transitions MEI State Transactions e Cache Bus Current Next Operation Operation Sync WIM State State Cache Actions Bus Operation Load Read No x0x l Same 1 Cast out of modified Write with kill T 0 block as required 2 Pass four beat read to Read memory queue Load Read No x0x EM Same Read data from cache T 0 Load T 0 Read No x1x l Same Pass single beat read to Read memory queue Load T 0 Read No x1x E l CRTRY read Load T 0 Read No x1x M l CRTRY read push sector Write with kill to write queue lwarx Read Acts like other reads but bus operation uses special encoding Store Write No 00x Same 1 Cast out of modified Write with kill T 0 block if nece
354. he BPU calculates the return pointer for subroutine calls and saves it into the LR for certain types of branch instructions The LR also contains the branch target address for the Branch Conditional to Link Register belrx instruction The CTR contains the branch target address for the Branch Conditional to Count Register bectrx instruction The contents of the LR and CTR can be copied to or from any GPR Because the BPU uses dedicated registers rather than GPRs or FPRs execution of branch instructions is largely independent from execution of integer and floating point instructions 1 1 4 Independent Execution Units The PowerPC architecture s support for independent execution units allows implementation of processors with out of order instruction execution For example because branch instructions do not depend on GPRs or FPRs branches can often be resolved early eliminating stalls caused by taken branches The four other execution units and completion unit are described in the following sections 1 1 4 1 Integer Unit IU The IU executes all integer instructions The IU executes one integer instruction at a time performing computations with its arithmetic logic unit ALU multiplier divider and XER register Most integer instructions are single cycle instructions The 32 GPRs hold integer operands Stalls due to contention for GPRs are minimized by the automatic allocation of Chapter 1 Overview For More Information On This Produ
355. he GPRs or FPRs rather than rename buffers If a single instruction encounters multiple exception conditions those exceptions are taken and handled sequentially Likewise exceptions that are asynchronous are recognized when they occur but are not handled until the next instruction to complete in program order successfully completes Throughout this chapter the phrase next instruction implies the next instruction to complete in program order Note that exceptions can occur while an exception handler routine is executing and multiple exceptions can become nested It is up to the exception handler to save the states to allow control to ultimately return to the original excepting program Chapter 4 Exceptions For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Exception Classes Unless a catastrophic condition causes a system reset or machine check exception only one exception is handled at a time If for example a single instruction encounters multiple exception conditions those conditions are handled sequentially After the exception handler handles an exception the instruction execution continues until the next exception condition is encountered However in many cases there is no attempt to re execute the instruction This method of recognizing and handling exception conditions sequentially guarantees that exceptions are recoverable To prevent loss of state information exception handlers s
356. he address bus is not owned by another bus master and that it is available to the MPC603e when accompanied by a qualified bus grant Assertion May occur when the MPC603e must be prevented from using the address bus and the processor is not currently asserting ABB Negation May occur whenever the MPC603e can use the address bus 7 2 2 Address Transfer Start Signals Address transfer start signals are input and output signals that indicate that an address bus transfer has begun The transfer start TS signal identifies the operation as a memory transaction Chapter 7 Signal Descriptions For More Information On This Product Go to www freescale com ae Freescale Semiconductor Inc Signal Descriptions For detailed information about how TS interacts with other signals refer to Section 8 3 2 Address Transfer 7 2 2 1 Transfer Start TS The TS signal is both an input and output signal on the MPC603e 7 2 2 1 1 Transfer Start TS Output Following are the state meaning and timing comments for the TS output State Meaning Asserted Indicates that the MPC603e has begun a memory bus transaction and that the address bus and transfer attribute signals are valid When asserted with the appropriate TT 0 4 signals it is also an implied data bus request for a memory transaction unless it is an address only operation Negated Indicates that no bus transaction is occurring during normal operation Timing Co
357. he bus interface also captures snoop addresses for snooping in the cache and in the address register queues snoops for reservations and holds the touch load address for the cache All data storage for the address register buffers load and store data buffers are located in the cache section The data buffers are considered temporary storage for the cache and not part of the bus interface The general functions and features of the bus interface are as follows e Address register buffers that include Instruction cache load address buffer Chapter 3 Instruction and Data Cache Operation For More Information On This Product Go to www freescale com TE EE Freescale Semiconductor Inc Data cache load address buffer Data cache touch load address buffer associated data block buffer located in cache Data cache castout store address buffer associated data line buffer located in cache Data cache snoop copy back address buffer associated data line buffer located in cache Reservation address buffer for snoop monitoring e Pipeline collision detection for data cache buffers e Reservation address snooping for lwarx stwex instructions e One level address pipelining e Load ahead of store capability Figure 3 5 is a conceptual block diagram of the bus interface The address register queues hold transaction requests that the bus interface may issue on the bus independently of the other requests The bus interface may
358. he following APO A 0 7 AP1 A 8 15 AP2 A 16 23 AP3 A 24 31 For more information see Section 8 3 2 1 Address Bus Parity Chapter 7 Signal Descriptions For More Information On This Product Go to www freescale com ae Freescale Semiconductor Inc Signal Descriptions Timing Comments Assertion Negation The same as A 0 31 High Impedance The same as A 0 31 7 2 3 2 2 Address Bus Parity AP 0 3 Input Following are the state meaning and timing comments for the AP 0 3 inputs State Meaning Asserted Negated Represents odd parity for each of 4 bytes of the physical address for snooping operations Detected even parity causes the processor to take a machine check exception or enter the checkstop state if address parity checking is enabled in the HIDO register see Section 2 1 2 1 Hardware Implementation Registers HIDO and HID1 See also the APE signal description Timing Comments Assertion Negation The same as A 0 31 7 2 3 3 Address Parity Error APE Output The APE signal is an output signal on the MPC603e Note that APE is an open drain type output and requires an external pull up resistor for example 10 KQ to Vpp to assure proper negation of APE Following are the state meaning and timing comments for the APE signal on the MPC603e The APE signal will not be asserted if address parity checking is disabled HIDO EBA cleared to 0 For more information see Section 8 3 2 1 Address Bus
359. her may cause components of the system software to be invoked Exceptions can be caused directly by the execution of an instruction as follows e An attempt to execute an illegal instruction causes the illegal instruction program exception handler to be invoked An attempt by a user level program to execute the supervisor level instructions listed below causes the privileged instruction program exception handler to be invoked The MPC603e provides the following supervisor level instructions debi mfmsr mfspr mfsr mfsrin mtmsr mtspr mtsr mtsrin rfi tlbie tlbsync tlbld and tlbli Note that the privilege level of the mfspr and mtspr instructions depends on the SPR encoding Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary e An attempt to access memory that is not available page fault causes the ISI exception handler to be invoked e An attempt to access memory with an effective address alignment that is invalid for the instruction causes the alignment exception handler to be invoked e The execution of an sc instruction invokes the system call exception handler that permits a program to request the system to perform a service e The execution of a trap instruction invokes the program exception trap handler e The execution of a floating point instruction when floating point instructions are disabled or unavailable invokes
360. his chapter the term multiprocessor is used in the context of maintaining cache coherency These multiprocessor devices could be actual processors or other devices that can access system memory maintain their own caches and function as bus masters requiring cache coherency Both the instruction and data caches have 32 byte blocks and data cache blocks can be snooped or cast out when the cache block is reloaded The data cache is designed to adhere to a write back policy but the MPC603e allows control of cacheability write back policy and memory coherency at the page and block level Both caches use a least recently used LRU replacement policy Burst fill operations to the caches result from cache misses or in the case of the data cache cache block write back operations to memory Note that in the PowerPC architecture the term cache block or simply block when used in the context of cache implementations refers to the unit of memory at which coherency is maintained For the MPC603e the block size is equivalent to the eight word cache line This value may be different for other implementations that support the PowerPC architecture The data cache is configured as 128 sets of 4 blocks Each block consists of 32 bytes 2 state bits and an address tag The 2 state bits implement the three state MEI modified exclusive invalid protocol a coherent subset of the standard four state MESI protocol Cache coherency is enforced by on chi
361. hould save the information stored in SRRO and SRR1 soon after the exception is taken This prevents loss of information due to a system reset or machine check exception or to an instruction caused exception in the exception handler before enabling external interrupts In this chapter the following terminology is used to describe the various stages of exception processing Recognition Exception recognition occurs when the condition that can cause an exception is identified by the processor Taken An exception is said to be taken when control of instruction execution is passed to the exception handler that is the context is saved and the instruction at the appropriate vector offset is fetched and the exception handler routing is executed in supervisor mode Handling Exception handling is performed by the software linked to the appropriate vector offset Exception handling is performed at supervisor level 4 1 Exception Classes The PowerPC architecture supports four types of exceptions e Synchronous precise These are caused by instructions All instruction caused exceptions are handled precisely that is the machine state at the time the exception occurs is known and can be completely restored This means that excluding the trap and system call exceptions the address of the faulting instruction is provided to the exception handler and that neither the faulting instruction nor subsequent instructions in the code stream will complete e
362. hus TLB entries must be explicitly cleared by the system software with the tlbie instruction before address translation is enabled Also note that the segment registers do not have a valid bit and so they should also be initialized before translation is enabled 5 4 3 2 TLB Entry invalidation For processors such as the MPC603e that implement TLB structures to maintain on chip copies of the PTEs that are resident in physical memory the optional tlbie instruction provides a way to invalidate the TLB entries Note that the execution of the tlbie instruction in the MPC603e invalidates four entries both the ITLB entries indexed by EA 15 19 and both the indexed entries of the DTLB The architecture allows tlbie to optionally enable a TLB invalidate signaling mechanism in hardware so that other processors also invalidate their resident copies of the matching PTE The MPC603e does not signal the TLB invalidation to other processors and does not perform any action when a TLB invalidation is performed by another processor The tlbsync instruction causes instruction execution to stop if the TLBISYNC signal is also asserted If TLBISYNC is negated instruction execution may continue or resume after the completion of a tlbsync instruction Section 8 8 2 TLBISYNC Input describes the TLB synchronization mechanism in further detail The tlbia instruction is not implemented on the MPC603e and when its opcode is encountered an illegal instruct
363. hus preserving the original data for use by other instructions and reducing the number of instructions required for certain operations Data is transferred between memory and registers with explicit load and store instructions only Note that there may be registers common to other processors of this family that are not implemented in the MPC603e When the MPC603e detects special purpose register SPR encodings other than those defined in this document it either takes an exception or it treats the instruction as a no op Note that exceptions are referred to as interrupts in the architecture specification Conversely some SPRs in the MPC603e may not be implemented in other processors or may not be implemented in the same way Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Register Set 2 1 1 PowerPC Register Set The PowerPC UISA registers shown in Figure 2 1 can be accessed by either user or supervisor level instructions the architecture specification refers to user and supervisor level as problem state and privileged state respectively The general purpose registers GPRs and floating point registers FPRs are accessed through instruction operands Access to registers can be explicit that is through the use of specific instructions for that purpose such as the mtspr and mfspr instructions or implicit as part of the execution or side effect of an instru
364. hx 31 S A 00000 922 Rc extswx 31 S A 00000 986 Rc nandx 31 S A B 476 Rc norx 31 S A B 124 Rc orx 31 S A B 444 Rc orcx 31 S A B 412 Rc ori 24 S A UIMM oris 25 S A UIMM xorx 31 S A B 316 Rc xori 26 S A UIMM xoris 27 S A UIMM 1 64 bit instruction Table A 6 Integer Rotate Instructions Name 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rldcix1 30 S A B mb 8 Rc rldcrx 1 30 S A B me 9 Re ridicx 1 30 S A sh mb 2 sh Rc ridiclx 1 30 S A sh mb 0 sh Re ridicrx 1 30 S A sh me 1 sh Re ridimix 30 S A sh mb 3 sh Rc MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconduct er ing Functional Categories Table A 6 Integer Rotate Instructions continued rlwimix 22 S A SH MB ME Rc rlwinmx 20 S A SH MB ME Rc rlwnmx 21 S A SH MB ME Rc 1 64 bit instruction Table A 7 Integer Shift Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sldx 31 S A B 27 Rc slwx 31 S A B 24 Rc sradx 31 S A B 794 Rc sradix 31 S A sh 413 sh Re srawx 31 S A B 792 Rc srawix 31 S A SH 824 Rc srdx 31 S A 539 Rc srwx 31 S A 536 Rc 1 64 bit instruction Table A 8 Floating Point Arithmetic Instructions Name 0 5 6 7 8 9 10 11 12 13 14 15 16 1
365. i rpa t gpr r0 r3 are shadowed there are thr flows tlbDataMiss i tlbCeqd 0 ij tlbInstrMiss place labels for rel branches machine PPC_MPC603e set ro OU set rl ail Set EE set Ee set dMiss 1010 Se dCmp 1011 set hash1 1012 set hash2 1013 set iMiss 1014 Set icmp 1015 set rpa 1010 set elt 40 set dar 19 set dsisr 18 set srr0 26 Set Che eg EE csect tlbmiss PR vec0 globl vec0d Oorg vec0 0x300 vec300 Org vec0 0x400 vec400 Instruction TB miss flow Entry Vec 1000 srro i srrl msr lt tgpr gt gt 1 write the itlb with the pte in rpa reg address address address returns returns returns of dstream miss of istream miss primary hash PTEG address secondary hash PTEG the primary istream the primary dstream the second word of pte used tlb miss on data load tlb miss on instruction fetch gt address of instruction that missed gt 0 3 cr0 4 lru way bit 16 31 saved MSR Chapter 5 Memory Management For More Information On This Product Go to www freescale com address compare value compare value by tlblx tlb miss on data store or store with tlb change bit Freescale Semiconductor Inc Page Table Search Operation i iMiss iCmp hash1 j hash2 rO is i ri is r2 is r3 is gt ea that missed gt the compare value for the va that missed gt poi
366. iated when a debz instruction is executed when snooped by the MPC603e the addressed cache block is invalidated if in the E state or flushed to memory and invalidated if in the M state and any associated reservation is canceled MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING erency ME Protocol Table 3 6 Response to Bus Transactions continued Snooped Transaction MPC603e Response Write with kill In a write with kill operation the processor snoops the cache for a copy of the addressed block If one is found an additional snoop action is initiated internally and the cache block is forced to the state killing modified data that may have been in the block Any reservation associated with the block is also canceled Read The read operation is used by most single beat and burst read operations on the bus All Read atomic burst reads observed on the bus are snooped as if they were writes causing the addressed cache block to be flushed A read on the bus with the GBL signal asserted causes the following responses e If the addressed block in the cache is invalid the MPC603e takes no action e If the addressed block in the cache is in the exclusive state the block is invalidated e f the addressed block in the cache is in the modified state the block is flushed to memory and the block is invalidated If the snoo
367. ibed in Table 2 1 Processor version register PVR This read only register identifies the version model and revision level of this processor Implementation Note The processor version number is 6 for the PID6 603e and 7 for the PID7t 603e The processor revision level starts at 0x0100 and changes for each chip revision The revision level is updated on all silicon revisions MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Register Set Table 2 1 MSR POW and MSR TGPR Bits Bits Name Description 13 POW Power management enable MPC603e specific Controls the programmable power modes only it has no effect on dynamic power management DPM MSR POW may be altered with an mtmsr instruction only Also when altering the POW bit software may alter only this bit in the MSR and no others The mtmsr instruction must be followed by a context synchronizing instruction See Chapter 9 Power Management for more information on power management 0 Disables programmable power modes normal operation mode 1 Enables programmable power modes nap doze or sleep mode 14 TGPR Temporary GPR remapping MPC603e specific The contents of GPRO GPR3 remain unchanged while MSR TGPR 1 Attempts to use GPR4 GPR31 with MSR TGPR 1 yield undefined results When this bit is set all instruction accesses to GRPRO GPR
368. icate of the first word in the page table entry PTE for which the table search is looking The required physical address RPA register is loaded by the processor with the second word of the correct PTE during a page table search Chapter 1 Overview For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Implementation Specific Information e The hardware implementation HIDO and HID1 registers provide the means for enabling MPC603e checkstops and features and allows software to read the configuration of the PLL configuration signals e The instruction address breakpoint register IABR is loaded with an instruction address that is compared to instruction addresses in the dispatch queue When an address match occurs an instruction address breakpoint exception is generated Figure 1 2 shows all the MPC603e registers available at the user and supervisor level The numbers to the right of the SPRs indicate the number that is used in the syntax of the instruction operands to access the register 1 3 2 Instruction Set and Addressing Modes The following sections describe the PowerPC instruction set and addressing modes in general 1 3 2 1 PowerPC Instruction Set and Addressing Modes All PowerPC instructions are encoded as single word 32 bit opcodes Instruction formats are consistent among all instruction types permitting efficient decoding to occur in parallel with operand accesses This fi
369. ies Table A 25 Trap Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 td 31 TO A B 68 0 tdi 1 03 TO A SIMM tw 31 TO A B 4 0 twi 03 TO A SIMM 1 64 bit instruction Table A 26 Processor Control Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 merxr 31 crfS 00 00000 00000 512 0 mfcr 31 D 00000 00000 19 0 mfmsr 1 31 D 00000 00000 83 0 mfspr 2 31 D spr 339 0 mftb 31 D tpr 371 0 mtcrf 31 S 0 CRM 0 144 0 mimsr 31 S 00000 00000 146 0 mtspr 2 31 D spr 467 0 1 Supervisor level instruction 2 Supervisor and user level instruction Table A 27 Cache Management Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dcbf 31 00000 A B 86 0 debi 31 00000 A B 470 0 dcbst 31 00000 A B 54 0 debt 31 00000 A B 278 0 dcbtst 31 00000 A B 246 0 dcbz 31 00000 A B 1014 0 icbi 31 00000 A B 982 0 1 Supervisor level instruction Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com Instructions Grouped by frsescale Semiconductor Inc Table A 28 Segment Register Manipulation Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mfsr 31 D 0 SR 00000 595 0 mfsrin 1 31 D 0
370. ific information is noted where applicable 1 3 3 1 PowerPC Cache Characteristics The PowerPC architecture does not define hardware aspects of cache implementations The MPC603e controls the following memory access modes on a page or block basis e Write back write through mode e Caching inhibited mode e Memory coherency Note that in the MPC603e a cache block is defined as eight words The VEA defines cache management instructions that provide a means by which the application programmer can affect the cache contents 1 3 3 2 Implementation Specific Cache Implementation The MPC603e has two 16 Kbyte four way set associative instruction and data caches The caches are physically addressed and the data cache can operate in either write back or write through mode as specified by the PowerPC architecture MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc snecitic Information The data cache is configured as 128 sets of four blocks each Each block consists of 32 bytes 2 state bits and an address tag The 2 state bits implement the three state MEI modified exclusive invalid protocol Each block contains eight 32 bit words Note that the PowerPC architecture defines the term block as the cacheable unit For the MPC603e the block size is equivalent to a cache line A block diagram of the data cache organization is shown in Figure 1 3
371. im virtual addresses are stored as on chip segment registers on 32 bit implementations such as the MPC603e In addition two translation lookaside buffers TLBs are implemented on the MPC603e to keep recently used page address translations on chip Although the PowerPC OEA describes one MMU conceptually the MPC603e hardware maintains separate TLBs and table search resources for instruction and data accesses that can be accessed independently and simultaneously Therefore the MPC603e is described as having two MMUs one for instruction accesses IMMU and one for data accesses DMMU The block address translation BAT mechanism is a software controlled array that stores the available block address translations on chip BAT array entries are implemented as Chapter 5 Memory Management For More Information On This Product Go to www freescale com MMU Features Freescale Semiconductor Inc pairs of BAT registers that are accessible as supervisor level special purpose registers SPRs There are separate instruction and data BAT mechanisms and in the MPC603e they reside in the instruction and data MMUs respectively The MMUs together with the exception processing mechanism provide the necessary support for the operating system to implement a paged virtual memory environment and for enforcing protection of designated memory areas Exception processing is described in Chapter 4 Exceptions Section 4 2 Exception Processing
372. ime immediately forwards their CR results to the BPU for fast branch resolution 1 The SRU can only execute the add and add o instructions Chapter 6 Instruction Timing For More Information On This Product Go to www freescale com Fr Instruction Latency Summar Table 6 5 provides the latencies for the floating point instructions Table 6 5 Floating Point Instructions y eescale Semiconductor Inc Mnemonic Primary Extended Unit aca fdivs 59 018 FPU 18 fsubs 59 020 FPU 1 1 14 fadds 59 021 FPU 1 1 14 fres 59 024 FPU 184 fmuls 59 025 FPU 1 1 14 fmsubs 59 028 FPU 1 1 1 fmadds 59 029 FPU 1 1 14 fnmsubs 59 030 FPU 1 1 1 fnmadds 59 031 FPU 1 1 14 fempu 63 000 FPU 1 1 14 frsp 63 012 FPU 1 1 14 fctiw 63 014 FPU 1 1 14 fetiwz 63 015 FPU 1 1 14 fdiv 63 018 FPU 334 fsub 63 020 FPU 1 1 14 fadd 63 021 FPU 1 1 14 fsel 63 023 FPU 1 1 1 fmull 63 025 FPU 2 1 14 frsqrte 63 026 FPU 1 1 14 fmsub 63 028 FPU 2 1 14 fmadd 63 029 FPU 2 1 14 fnmsub 63 030 FPU 2 1 1 fnmadd 63 031 FPU 2 1 14 Tempo 63 032 FPU 1 1 14 mtfsb1 63 038 FPU 1 1 184 fneg 63 040 FPU 1 1 14 merfs 63 064 FPU 1 1 1 amp mtfsb0 63 070 FPU 1 1 184 Im 63 072 FPU 1 1 14 mtfsfi 63 134 FPU 1 1 18 fnabs 63 136 FPU 1 1 14 fabs 63 264 FPU 4 1 14 mffs 63 583 FPU 1 1 184
373. in Chapter 6 Instruction Timing For More Information On This Product Go to www freescale com rae EE Freescale Semiconductor Inc Timing Considerations Instruction results are transferred from rename registers to architected registers when an instruction is retired from the CQ after any associated exceptions are handled and any predicted branch conditions preceding it in the CQ are resolved If a branch prediction is incorrect the instructions following the branch are flushed from the CQ and any results of those instructions are flushed from the rename registers 6 3 3 2 Instruction Serialization Although the MPC603e can dispatch and complete two instructions per cycle serializing instructions can be used to limit dispatch and completion to one instruction per cycle Serialization falls into three categories completion dispatch and refetch serialization which are described as follows e Completion serialized instructions are held in the execution unit until all prior instructions in the completion unit have been retired Completion serialization is used for instructions that access or modify a resource for which no rename register exists Results from these instructions are not available or forwarded for subsequent instructions until the serializing instruction is retired Instructions that are completion serialized are as follows Instructions with the exception of integer add and compare instructions executed by the syst
374. ing for a full description of completion serialization When an exception is enabled in the FPSCR the instruction traps to the emulation trap exception vector without updating the FPSCR or the target FPR The emulation trap exception handler is required to complete the instruction The emulation trap exception handler is invoked regardless of the FE setting in the MSR The two IEEE floating point imprecise modes defined by the PowerPC architecture when MSR FE0 MSR FE1 are treated as precise exceptions that is MSR FEO MSR FE1 1 This is regardless of the setting of MSR NI For the highest and most predictable floating point performance all exceptions should be disabled in the FPSCR and MSR For more information about the program exception see the Programming Environments Manual 4 5 7 2 Illegal Reserved and Unimplemented Instructions Program Exceptions In accordance with the PowerPC architecture the MPC603e considers all instructions defined for 64 bit implementations and unimplemented optional instructions such as fsqrt eciwx and ecowx as illegal and takes a program exception when one of these instructions is encountered Likewise if a supervisor level instruction is encountered when the processor is in user level mode a privileged instruction type program exception is taken The MPC603e implements some instructions such as double precision floating point and load store string instructions in software These inst
375. ing Point Move Instructions Name Mnemonic Operand Syntax Floating Absolute Value fabs fabs frD frB Floating Move Register fmr fmr frD frB Floating Negate fneg fneg frD frB Floating Negative Absolute Value fnabs fnabs frD frB 2 3 4 3 Load and Store Instructions Load and store instructions are issued and translated in program order however the accesses can occur out of order Synchronizing instructions are provided to enforce strict ordering This section describes the load and store instructions of the MPC603e which consist of the following e Integer load instructions e Integer store instructions e Integer load and store with byte reverse instructions e Integer load and store multiple instructions e Integer load and store string instructions e Floating point load instructions e Floating point store instructions Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary 2 3 4 3 1 Self Modifying Code When a processor modifies a memory location that may be contained in the instruction cache software must ensure that memory updates are visible to the instruction fetching mechanism This can be achieved by the following instruction sequence dcbst update memory sync wait for update icbi remove invalidate copy in instruction cache isync remove copy in own instruction buffer These oper
376. ing dispatched in the next clock cycle In cycle 4 target instructions 8 and 9 are fetched Instruction 1 completes in cycle 4 allowing instruction 2 which had finished executing in the previous clock cycle to be removed from the CQ Instruction 6 replaces instruction 3 in the first stage of the FPU Also as will be shown in cycle 5 a single cycle stall occurs when the FPU pipeline is full MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timing Considerations 5 Incycle 5 instruction 3 completes instruction 6 continues through the FPU pipeline and although the first stage of the FPU pipeline is free instruction 7 cannot be dispatched because of the potential need for one of the previous floating point instructions to require denormalization Because instruction 7 cannot be dispatched neither can instruction 8 This dispatch stall causes the instruction queue to become full when instructions 10 and 11 are fetched 6 In cycle 6 instruction 12 is fetched Instruction 7 is dispatched to the first FPU stage so instruction 8 can also be dispatched to the IU Instructions 9 and 10 move to IQO and IQ1 but because instructions 9 10 and 11 are integer instructions only one instruction is dispatched in each of the next 2 clock cycles Note that moving instruction 12 fadd up further in the program flow would improve dispatch throughput 7 In
377. ingle cycle The instruction fetch unit continuously loads as many instructions as space in the IQ allows Instructions MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc i Overview are dispatched to their respective execution units from the dispatch unit at a maximum rate of two instructions per cycle Dispatching is facilitated to the IU FPU LSU and SRU by the provision of a reservation station at each unit The dispatch unit performs source and destination register dependency checking determines dispatch serializations and inhibits subsequent instruction dispatching as required For a more detailed overview of instruction dispatch see Section 1 3 6 Instruction Timing 1 1 3 2 Branch Processing Unit BPU The BPU receives branch instructions from the fetch unit and performs CR lookahead operations on conditional branches to resolve them early achieving the effect of a zero cycle branch in many cases The BPU uses a bit in the instruction encoding to predict the direction of the conditional branch Therefore when an unresolved conditional branch instruction is encountered the MPC603e fetches instructions from the predicted target stream until the conditional branch is resolved The BPU contains an adder to compute branch target addresses and three user control registers the link register LR the count register CTR and the CR T
378. instructions as described in Section 6 4 1 1 Branch Folding Branch instructions that update the LR or CTR are treated as if they require dispatch even through they are not dispatched to an execution unit in the process They are assigned a position in the CQ to ensure that the CTR and LR are updated sequentially All other instructions are dispatched from IQO and IQ1 The dispatch rate depends on the availability of resources such as the execution units rename registers and CQ entries and on the serializing behavior of some instructions Instructions are dispatched in program order an instruction in IQ1 can be dispatched at the same time as one in IQO but it cannot be dispatched ahead of one in IQO MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Timing Considerations Figure 6 4 shows the paths taken by instructions Fetch Maximum Two Instruction Fetch per Clock Cycle Branch Processing Unit Instruction Queue IER EE ee ee ee e a LS Sarah a E in Program Order Maximum Two Instruction Dispatch per Clock Cycle Dispatch Completion Buffer Assignment Reservation Stations SRU 2 Entry Store Queue SM Completion Queue in Program Order Maximum Two Instruction Completion per Clock Cycle Complete Retire Figure 6 4 Instruction Flow Diagram Instruction state and all information req
379. ion 8 4 3 Data Transfer The data transfer signals include DH 0 31 DL 0 31 DP 0 7 and DPE For memory accesses the DH and DL signals form a 64 bit data path for read and write operations The MPC603e transfers data in either single or four beat burst transfers when configured with a 64 bit data bus when configured with a 32 bit data bus the MPC603e performs one two and eight beat data transfers Single beat operations can transfer from 1 to 8 bytes at a time and can be misaligned see Section 8 3 2 4 Effect of Alignment in Data Transfers 64 Bit Bus Burst operations always transfer eight words and are aligned on eight word address boundaries Burst transfers can achieve significantly higher bus throughput than single beat operations The type of transaction initiated by the MPC603e depends on whether the code or data is cacheable and for store operations whether the cache is considered in write back or write through mode which software controls on either a page or block basis Burst transfers support cacheable operations only that is memory structures must be marked as cacheable and write back for data store operations in the respective page or block descriptor to take advantage of burst transfers The MPC603e output TBST indicates to the system whether the current transaction is a single or four beat transfer except during eciwx ecowx transactions when it signals the state of EAR 28 A burst transfer has an assum
380. ion Flow for 32 Bit Implementations TLB Hit 5 9 Primary Page Table Search Conceptual FLOW 00 ec eeseeseceeeeeeneeenseceeetees 5 10 Secondary Page Table Search Flow Conceptual FlOW 0 eee eeeeeeeeeeeeeeeee 5 11 DMISS and IMISS Registers x cssscisccceviuiaseatasnstadevcesscaue arininn 5 12 EE We LEE 5 13 HASHT and HASH EN 5 14 Required Physical Address RPA Register ceeceeeceesseceseceeeeeeseeenaeeeseeees Figures For More Information On This Product Go to www freescale com Page Number xi Freescale Semiconductor Inc Figures Figure Number Title 5 15 Flow for Example Software Table Search Operation eee eeneeeeee 5 16 Check and Set Rand C Oe A a 5 17 Page Fault Semi FOW i024 Aere 5 18 Setup for Protection Violation Exceptions eee eeeseceseceseeeseecsseeeeenees 6 1 Pipelined Execution EE 6 2 Superscalar Pipeline Diagram ic ssssisecsesissevecstavsvacavseacateaspavaataseessedessaceevases 6 3 MPC603e Microprocessor Pipeline btages 6 4 Instruction Flow Diagram ege dee eg 6 5 Instruction aenneren Edge 6 6 Instruction Timing Cache Miss 6 7 Branch Instruction Timing s ic jsicisaegiecisnsiaias Eed AANEREN 7 1 SEKR e EE 7 2 IEEE 1149 1 Compliant Boundary Scan Interface 8 1 MPC603e Microprocessor Block Daeram 8 2 Overlapping Tenures on the Bus for a Single Beat Transfer 8 3 Address Bus Arbitration 22 0 ie eceenaeetueeavecedet ieaehaecedauineta cee 8 4 Address Bus
381. ion Processing MSR bits are guaranteed to be written to SRR1 when the first instruction of the exception handler is encountered Table 4 7 IEEE Floating Point Exception Mode Bits FEO FE1 Mode 0 0 Floating point exceptions disabled 0 1 Floating point imprecise nonrecoverable 1 0 Floating point imprecise recoverable 1 1 1 Floating point precise mode 1 Not implemented in the MPC603e 4 2 2 Enabling and Disabling Exceptions When a condition exists that may cause an exception to be generated it must be determined whether the exception is enabled for that condition as follows e TIEFE floating point enabled exceptions a type of program exception are ignored when both MSR FEO and MSR FE1 are cleared If either of these bits are set all IEEE enabled floating point exceptions are taken and cause a program exception e Asynchronous maskable exceptions that is the external system management and decrementer interrupts are enabled by setting the MSR EE bit When MSR EE 0 recognition of these exception conditions is delayed MSR EE is cleared automatically when an exception is taken to delay recognition of conditions causing those exceptions e A machine check exception can occur only if the machine check enable bit MSR ME is set If MSR ME is cleared the processor goes directly into checkstop state when a machine check exception condition occurs Individual machine check exceptions can be ena
382. ion in the MPC603e cache Note that a data access exception is generated if the effective address of a debi dcbst dcebf or dcbz instruction cannot be translated due to the lack of a TLB entry Note that exceptions are referred to as interrupts in the architecture specification Note that in the PowerPC architecture the term cache block or block when used in the context of cache implementations refers to the unit of memory at which coherency is maintained For the MPC603e this is the eight word cache line This value may be different for other implementations that support the PowerPC architecture In depth descriptions of coding these instructions is provided in Chapter 3 Addressing Modes and Instruction Set Summary and Chapter 10 Instruction Set in the Programming Environments Manual Chapter 3 Instruction and Data Cache Operation For More Information On This Product Go to www freescale com __ Freescale Semiconductor Inc Cache Control Instructions 3 7 1 Data Cache Block Invalidate dcbi Instruction If the block containing the byte addressed by the EA is in the data cache the cache block is invalidated regardless of whether the block is in the exclusive or modified state If HIDO ABE is set on a PID7t 603e when a debi instruction is executed the PID7t 603e will perform an address only bus transaction The debi instruction can only be executed when the MPC603e is in the supervisor state 3 7 2 Data
383. ion mechanism Additionally because the MPC603e relies on software to perform table search operations the processor also takes an exception when e There is a miss in the corresponding instruction or data TLB e The page table requires an update to the changed C bit The state saved by the processor for each of these exceptions contains information that identifies the address of the failing instruction Refer to Chapter 4 Exceptions for a more detailed description of exception processing Because a page fault condition PTE not found in the page tables in memory is detected by the software that performs the table search operation and not the MPC603e hardware it does not cause MPC603e exception in the strictest sense in that exception processing as described in Chapter 4 Exceptions does not occur However in order to maintain architectural compatibility with software written for other devices that implement the PowerPC architecture the software that detects this condition should synthesize an exception by setting the appropriate bits in the DSISR or SRR1 and branching to the ISI or DSI exception handler Refer to Section 5 5 2 Implementation Specific Table Search MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MMU Features Operation for more information and examples of this exception software The remainder of this ch
384. ion program exception is generated To invalidate all entries of both TLBs 32 tlbie instructions must be executed incrementing the value in EA 15 19 by 1 each time See Chapter 8 Instruction Set in the Programming Environments Manual for detailed information about the tlbie instruction MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Mes able E 5 4 4 Page Address Translation Summary Figure 5 8 provides the detailed flow for the page address translation mechanism The figure includes the checking of the N bit in the segment descriptor and then expands on the TLB Hit branch of Figure 5 6 The detailed flow for the TLB Miss branch is described in Section 5 5 1 Page Table Search Operation Conceptual Flow Note that as in the case of block address translation if the debz instruction is attempted to be executed either in write through mode or as cache inhibited W 1 or I 1 the alignment exception is generated The checking of memory protection violation conditions for page address translation is described in Chapter 7 Memory Management in the Programming Environments Manual for 32 bit implementations 5 5 Page Table Search Operation As stated earlier the operating system must synthesize the table search algorithm for setting up the tables The MPC603e TLB miss exception handlers also use this algorithm with the assistance of s
385. ion type program exception is generated when the execution of a privileged instruction is attempted and the MSR register user privilege bit MSR PR is set In the MPC603e this exception is generated for mtspr or mfspr with an invalid SPR field if SPR 0 1 and MSR PR 1 This may not be true for all processors that implement the PowerPC architecture e Trap A trap type program exception is generated when any of the conditions specified in a trap instruction is met Floating point unavailable 00800 A floating point unavailable exception is caused by an attempt to execute a floating point instruction including floating point load store and move instructions when the floating point available bit is cleared MSR FP 0 Decrementer 00900 The decrementer exception occurs when DEC 31 changes from 0 to 1 This exception is enabled with MSR EE Reserved 00A00 00BFF System call 00C00 A system call exception occurs when a System Call sc instruction is executed Trace 00D00 A trace exception is taken when MSR SE 1 or when the currently completing instruction is a branch and MSR BE 1 Reserved 00E00 The MPC603e does not generate an exception to this vector Other processors that implement the PowerPC architecture may use this vector for floating point assist exceptions Reserved 00E10 00FFF Instruction translation miss 01000 An instruction translation miss ex
386. ion with the same effective address used for both instructions of the pair Note that the reservation granularity is 32 bytes The concept behind the use of the lwarx and stwex instructions is that a processor may load a semaphore from memory compute a result based on the value of the semaphore and conditionally store it back to the same location only if that location has not been modified since it was first read and determine if the store was successful The conditional store is performed based on the existence of a reservation established by the preceding lwarx instruction If the reservation exists when the store is executed the store is performed which sets a bit in the CR If the reservation does not exist when the store is executed the target memory location is not modified and a bit is cleared in the CR If the store was successful the sequence of instructions from the read of the semaphore to the store that updated the semaphore appear to have been executed atomically that is no other processor or mechanism modified the semaphore location between the read and the update thus providing the equivalent of a real atomic operation However in reality other processors may have read from the location during this operation In the MPC603e the reservations are made on behalf of aligned 32 byte sections of the memory address space The lwarx and stwex instructions require the EA to be aligned Exception handling software should not atte
387. ir caches 3 8 Bus Operations Caused by Cache Control Instructions Table 3 7 provides an overview of the bus operations initiated by cache control instructions The cache control TLB management and synchronization instructions supported by the MPC603e may affect or be affected by the operation of the bus None of the instructions will actively broadcast through address only transactions on the bus except for dcbz and no broadcasts by other masters are snooped by the MPC603e except for kills The operation of the instructions however may indirectly cause bus transactions to be performed or their completion may be linked to the bus Table 3 7 summarizes how these instructions may operate with respect to the bus Table 3 7 Bus Operations Caused by Cache Control Instructions WIM 001 Operation Cache State Next Cache State Bus Operations Comment sync Don t care No change None Waits for memory queues to complete bus activity icbi Don t care l None dcbi Don t care l None dcbf LE l None MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bus Interface Table 3 7 Bus Operations Caused by Cache Control Instructions WIM 001 continued Operation Cache State Next Cache State Bus Operations Comment dcbf M l Write with kill Block is pushed
388. is 25 Integer 1 xori 26 Integer 1 xoris 27 Integer 1 andi 28 Integer 1 andis 29 Integer 1 cmp 31 000 Integer amp SRU 1 tw 31 004 Integer 2 subfc o 31 008 Integer 1 addc o 31 010 Integer 1 mulhwul 31 011 Integer 2 3 4 5 6 slw 31 024 Integer 1 entlzw 31 026 Integer 1 and 31 028 Integer 1 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Latency Summary Table 6 4 Integer Instructions continued Mnemonic Primary Extended Unit meres cmpl 31 032 Integer amp SRU 1 subf 31 040 Integer 1 andc 31 060 Integer 1 mulhw 31 075 Integer 2 3 4 5 neg o 31 104 Integer 1 nol 31 124 Integer 1 subfe o 31 136 Integer 1 adde o 31 138 Integer 1 subfze o 31 200 Integer 1 addze o 31 202 Integer 1 subfmef o 31 232 Integer 1 addmef o 31 234 Integer 1 mull o 31 235 Integer 2 3 4 5 add o 31 266 Integer amp SRU 1 eqv 31 284 Integer 1 voll 31 316 Integer 1 orc 31 412 Integer 1 orl 31 444 Integer 1 divwu o 31 459 Integer 20 nand 31 476 Integer 1 divw o 31 491 Integer 20 srw 31 536 Integer 1 sraw 31 792 Integer 1 srawi 31 824 Integer 1 extsh 31 922 Integer 1 extsb 31 954 Integer 1 Note indicates that the cycle t
389. is asserted to indicate that the processor is ready to enter sleep mode If the system logic determines that the processor may enter sleep mode the quiesce acknowledge signal QACK is asserted back to the processor Once QACK assertion is detected the processor enters sleep mode after several processor clocks At this point the system logic may turn off the PLL by first configuring PLL_CFG 0 3 to PLL bypass mode then disabling SYSCLK 11 DPM Dynamic power management enable 0 Dynamic power management is disabled 1 Functional units enter a low power mode automatically if the unit is idle This does not affect operational performance and is transparent to software or any external hardware 12 15 Reserved 16 ICE Instruction cache enable 0 The instruction cache is neither accessed nor updated All pages are accessed as if they were marked cache inhibited WIM x1x Potential cache accesses from the bus snoop and cache operations are ignored In the disabled state for the L1 caches the cache tag state bits are ignored and all accesses are propagated to the L2 cache or bus as single beat transactions For those transactions however CI reflects the original state determined by address translation regardless of cache disabled status ICE is zero at power up 1 The instruction cache is enabled 17 DCE Data cache enable 0 The data cache is neither accessed nor updated All pages are accessed as if they were marked cache inhi
390. is placed into the target register and if the mask bit is 0 the associated bit in the target register is unchanged or ANDed with a mask before being placed into the target register The integer rotate instructions are listed in Table 2 13 Table 2 13 Integer Rotate Instructions Name Mnemonic Operand Syntax Rotate Left Word Immediate then AND with Mask rlwinm rlwinm rA rS SH MB ME Rotate Left Word Immediate then Mask Insert rlwimi rlwimi rA rS SH MB ME Rotate Left Word then AND with Mask rlwnm rlwnm rA rS rB MB ME The integer shift instructions perform left and right shifts Immediate form logical unsigned shift operations are obtained by specifying masks and shift values for certain rotate instructions Simplified mnemonics are provided making coding of such shifts simpler and easier to understand Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary Multiple precision shifts can be programmed as shown in Appendix C Multiple Precision Shifts in the Programming Environments Manual The integer shift instructions are listed in Table 2 14 Table 2 14 Integer Shift Instructions Name Mnemonic Operand Syntax Shift Left Word slw slw rA rS rB Shift Right Algebraic Word sraw sraw rA rS rB Shift Right Algebraic Word Immediate srawi srawi r
391. isabled status DCE is zero at power up 1 The data cache is enabled 18 ILOCK Instruction cache lock 0 Normal operation 1 Instruction cache is locked A locked cache supplies data normally on a hit but the access is treated as a cache inhibited transaction on a miss On a miss the transaction to the 60x bus is single beat however Cl still reflects the original state as determined by address translation independent of cache locked or disabled status To prevent locking during a cache access an isync instruction must precede the setting of ILOCK 19 DLOCK Data cache lock 0 Normal operation 1 Data cache is locked A locked cache supplies data normally on a hit but is treated as a cache inhibited transaction on a miss On a miss the transaction to the 60x bus is single beat however CI still reflects the original state as determined by address translation independent of cache locked or disabled status A snoop hit to a locked L1 data cache performs as if the cache were not locked A cache block invalidated by a snoop remains invalid until the cache is unlocked To prevent locking during a cache access a sync instruction must precede the setting of DLOCK 20 ICH Instruction cache flash invalidate 0 The instruction cache is not invalidated The bit is cleared when the invalidation operation begins usually the next cycle after the write operation to the register The instruction cache must be ena
392. isor level cache control instructions While memory page level cache control is provided by the WIMG bits the on chip data cache can be invalidated disabled locked or broadcast by the control bits in the HIDO register described in this section Note that user and supervisor level are referred to as problem and privileged state respectively in the architecture specification 3 2 3 1 Data Cache Invalidation While the data cache is automatically invalidated when the MPC603e is powered up and during a hard reset assertion of the soft reset signal does not cause data cache invalidation Software may invalidate the contents of the data cache using the data cache flash invalidate DCFD control bit in the HIDO register Flash invalidation of the data cache is accomplished by setting and clearing the DCFI bit in two consecutive store operations MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semicondugtor Ing nization and Conirol 3 2 3 2 Data Cache Disabling The data cache may be disabled through the use of the data cache enable DCE control bit in the HIDO register When the data cache is in the disabled state the cache tag state bits are ignored and all accesses are propagated to the bus as single beat transactions The DCE bit is cleared on power up causing the data cache to be disabled To prevent the cache from being enabled or disabled in the middle of a data
393. isssicsssasseaarasessaasedesccecantcsedsnaussadeaantean es ENEE A 23 Segment Register Manipulation Instructions 0 0 0 ee eee eeseceeeeeeeeeeneecnaeeeeesseeeeneees A 24 Lookaside Buffer Management Instructions ec eeeceeeceesseceeceeeeeeeeesseeenaeenseensees A 24 ExtemalControlMsipu cons nessie a oh eae ee as a ee aan A 24 Etgen ee E A 25 eu A 25 SC OTN E E A 25 LR EE A 25 OTA DEE A 27 X FOM E A 27 KE e cose ee aa ad ese E E Es A 31 SEET eege E A 32 PoP FOU ioi ia en EN sbeeyaeisiynuses Uessneuityes Eat A 32 XS FoM anan e n EE Eege A 32 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Tables Table Number Title A 41 EE A 42 beet ere A 43 NEE sas ian aA seed anced a ee e A a ARE A ER eea A ia A 44 IVE Kee A 45 TVET S EE A 46 PowerPC Instruction Set Legend s cscissucecasasesssccassaccevaseeceunadearaccesecceeeess B 1 32 Bit Instructions Not Implemented by the MPC603e eee B 2 64 Bit Instructions Not Implemented by the MPC603e uu eee B 3 64 Bit SPR Encoding Not Implemented by the MPC603e Tables For More Information On This Product Go to www freescale com Page Number XX Freescale Semiconductor Inc Tables MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc About This Book The primary objective of this
394. it occurs a memory transaction is required in which case fetch latency is affected by bus traffic bus clock speed and memory translation These conditions are discussed in the following sections 6 3 2 1 Cache Arbitration When the fetcher requests instructions from the cache two things may happen If the instruction cache is idle and the requested instructions are present they are provided on the next clock cycle However if the instruction cache is busy due to a cache line reload operation instructions cannot be fetched until that operation completes 6 3 2 2 Cache Hit An instruction fetch that hits the instruction cache takes only one clock cycle after the request for as many as two instructions to enter the IQ Note that the cache is not blocked to internal accesses until a cache reload completes hits under misses The critical double word is written simultaneously to the cache and forwarded to the requesting unit minimizing stalls due to load delays Figure 6 5 shows a simple example of instruction fetching that hits in the on chip cache This example uses a series of integer add and and double precision floating point add instructions to show how the number of instructions to be fetched is determined how program order is maintained by the IQ and CQ how instructions are dispatched and retired in pairs maximum and how the FPU pipeline functions The following instruction sequence is examined 0 add 1 fadd 2 add 3 fadd
395. it PowerPC instructions that are not supported in the MPC603e 14 Cleared 15 16 For instructions that use register indirect with index addressing set to bits 29 30 of the instruction For instructions that use register indirect with immediate index addressing cleared 17 For instructions that use register indirect with index addressing set to bit 25 of the instruction For instructions that use register indirect with immediate index addressing set to bit 5 of the instruction 18 21 For instructions that use register indirect with index addressing set to bits 21 24 of the instruction For instructions that use register indirect with immediate index addressing set to bits 1 4 of the instruction 22 26 Set to bits 6 10 identifying either the source or destination of the instruction Undefined for dcbz 27 31 Set to bits 11 15 of the instruction rA Set to either bits 11 15 of the instruction or to any register number not in the range of registers loaded by a valid form instruction for Imw Iswi and Iswx instructions Otherwise undefined DAR Set to the EA of the data access as computed by the instruction causing the alignment exception When the operand of an Imw stmw Iwarx or stwex instruction is not word aligned that address value 4 is stored into the DAR 4 5 6 1 Integer Alignment Exceptions The MPC603e is optimized for load and store operations that are aligned on natural boundaries Operatio
396. ited Attribute I If I 1 the memory access is completed by referencing the location in main memory bypassing the on chip cache During the access the addressed location is not loaded into the cache nor is the location allocated in the cache It is considered a programming error if a copy of the target location of an access to caching inhibited memory is resident in the cache Software must ensure that the location has not been previously loaded into the cache or if it has that it has been flushed from the cache The PowerPC architecture permits data accesses from more than one instruction to be combined for cache inhibited operations except when the accesses are separated by a syne instruction or by an eieio instruction when the page or block is also designated as guarded This combined access capability is not implemented on the MPC603e Note that the eieio is treated as a no op by the MPC603e The caching inhibited I bit in the MPC603e controls whether load and store operations are strongly or weakly ordered If an I O device requires load and store accesses to occur in program order then the I bit for the page must be set 3 5 3 Memory Coherency Attribute M This attribute is provided to allow improved performance in systems where hardware enforced coherency is relatively slow and software is able to enforce the required coherency When M 0 the processor does not enforce data coherency When M 1 the processor enforce
397. ith distinct instructions The MPC603e follows the program flow when it is in the normal execution state However the flow of instructions can be interrupted directly by the execution of an instruction or by an asynchronous event Either kind of exception may cause one of several components of the system software to be invoked Chapter 1 Overview For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Implementation Specific Information 1 3 2 2 Implementation Specific Instruction Set The MPC603e instruction set is defined as follows e The MPC603e provides hardware support for all 32 bit PowerPC instructions e The MPC603e provides two implementation specific instructions used for software table search operations following TLB misses Load Data TLB Entry tlbld Load Instruction TLB Entry tlbli e The MPC603e implements the following instructions which are defined as optional by the PowerPC architecture External Control In Word Indexed eciwx External Control Out Word Indexed ecowx Floating Select fsel Floating Reciprocal Estimate Single Precision fres Floating Reciprocal Square Root Estimate frsqrte Store Floating Point as Integer Word stfiwx 1 3 3 Cache Implementation The following sections describe the general cache characteristics as implemented in the PowerPC architecture and the MPC603e implementation specifically PID7t 603e spec
398. itions For update forms the update register rA is not altered 4 5 4 ISI Exception 0x00400 The ISI exception is implemented as it is defined by the PowerPC architecture An ISI exception occurs when no higher priority exception exists and an attempt to fetch the next instruction fails for any of the following reasons e If an instruction TLB miss fails to find the desired PTE then a page fault is synthesized The ITLB miss handler branches to the ISI exception handler to retrieve the translation from a storage device e An attempt is made to fetch an instruction from a direct store segment while instruction translation is enabled MSR IR 1 e An attempt is made to fetch an instruction from no execute memory e An attempt is made to fetch an instruction from guarded memory when MSR IR 1 e The fetch access violates memory protection Register settings for this exception are described in Chapter 6 Exceptions in the Programming Environments Manual When an ISI exception is taken instruction execution for the handler begins at offset 0x00400 from the physical base address indicated by MSR IP 4 5 5 External Interrupt 0x00500 An external interrupt is signaled to the MPC603e by the assertion of the INT signal as described in Section 7 2 9 1 Interrupt INT Input The interrupt may not be recognized if a higher priority exception occurs simultaneously or if the MSR EE bit is cleared when INT is asserte
399. kill block flush dcbst Data cache No XXX LE Same 1 CRTRY debst block store 2 Pass clean Clean Same Same 3 No action dcbst Data cache No XXX M E Push block to write queue Write with kill block store dcbz Data cache No x1x D D Alignment trap block set to zero dcbz Data cache No 10x D D Alignment trap block set to zero dcbz Data cache Yes 00x l Same 1 CRTRY dcbz block set to en 8 3 zero 2 Cast out of modified Write with kill block 3 Pass kill Kill Same M 4 Clear block dcbz Data cache No 00x E M Clear block block set to zero dcbt Data cache No x1x l Same Pass single beat read to Read block touch memory queue dcbt Data cache No x1x E CRTRY read block touch dcbt Data cache No x1x M l 1 CRTRY read block touch 7 8 7 2 Push block to write Write with kill queue dcbt Data cache No x0x Same 1 Cast out of modified Write with kill block touch block as required 2 Pass four beat read to Read memory queue dcbt Data cache No x0x E M Same No action block touch Single beat read Reloaddump No XXX l Same Forward data_in 1 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 3 8 MEI State Transitions continued MEI State Transactions Cache Bus Current Next Operation Operation Sync WIM State State Cache Actio
400. l cache management instruction in the PowerPC architecture dcbi should not be used on the MPC603e The user level debf instruction described in Section 2 3 5 3 Memory Control Instructions VEA and in Section 3 7 Cache Control Instructions should be used when the program needs to invalidate cache blocks Note that the dcbf instruction causes modified blocks to be flushed to system memory if they are the target of a debf instruction whereas by definition in the PowerPC architecture the debi instruction only invalidates modified blocks Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary 2 3 6 3 2 Segment Register Manipulation Instructions The instructions listed in Table 2 41 provide access to the segment registers for the MPC603e These instructions operate completely independent of the MSR IR and MSR DR bit settings Refer to Synchronization Requirements for Special Registers and TLBs in Chapter 2 Register Set in the Programming Environments Manual for serialization requirements and other recommended precautions to observe when manipulating the segment registers Table 2 41 Segment Register Manipulation Instructions Name Mnemonic Operand Syntax Move from Segment Register mfsr rD SR Move from Segment Register Indirect mfsrin rD rB Move to Segment Register mtsr SR rS Move to Segment Register In
401. l to indicate that it is ready to disable bus snooping When the system logic has ensured that snooping is no longer necessary it allows the processor to enter the nap or sleep mode and causes the assertion of the MPC603e QACK output signal for the duration of the nap mode period Nap mode is characterized by the following features e Time base decrementer still enabled e Most functional units disabled including bus snooping e PLL running and locked to SYSCLK To enter the nap mode the following conditions must occur e Set nap bit HIDO 9 1 MSR POW is set e MPC603e asserts QREQ e System asserts QACK e The processor enters nap mode after several processor clocks To return to full power mode the following conditions must occur e Assert INT MCP SMI or decrementer interrupts MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING mmable E e Transition to full power takes only a few processor cycles e Hard reset or soft reset 9 3 1 5 Sleep Mode Sleep mode consumes the least amount of power of the four modes since all functional units are disabled To conserve the maximum amount of power the PLL and internal SYSCLK signals can be disabled Due to the fully static design of the MPC603e the internal processor state is preserved when no internal clock is present Because the time base and decrementer are disabled while the MPC6
402. lements an extra key bit in the SRR1 register that simplifies the table search software In addition because the MPC603e does not support direct store bus accesses it causes a DSI exception when a direct store segment is encountered The primary function of the MMU processor is the translation of logical effective addresses to physical addresses referred to as real addresses in the architecture specification for memory accesses and I O accesses I O accesses are assumed to be memory mapped In addition the MMU provides access protection on a segment block or page basis This chapter describes the specific hardware used to implement the MMU model of the OEA in the MPC603e Refer to Chapter 7 Memory Management in the Programming Environments Manual for a complete description of the conceptual model Two general types of accesses generated by processors that implement the PowerPC architecture require address translation instruction accesses and data accesses to memory generated by load and store instructions Generally the address translation mechanism is defined in terms of segment descriptors and page tables used by processors to locate the effective to physical address mapping for instruction and data accesses The segment information translates the effective address to an interim virtual address and the page table information translates the virtual address to a physical address The segment descriptors used to generate the inter
403. lid MEI cache states This protocol is a compatible subset of the MESI four state protocol and operates coherently in systems that contain four state caches In addition the MPC603e does not broadcast cache operations caused by cache instructions They are intended for the management of the local cache but not for other caches in the system 3 6 4 1 Coherency in Single Processor Systems The following situations concerning coherency can be encountered within a single processor system e Load or store to a caching inhibited page WIM Obx1x and a cache hit occurs Caching is inhibited for this page I 1 Load or store operations to a caching inhibited page that hit in the cache cause boundedly undefined results e Store to a page marked write through WIM 0b10x and a cache read hit to a modified cache block This page is marked as write through W 1 The MPC603e pushes the modified cache block to memory and the block remains marked modified M Note that when WIM bits are changed it is critical that the cache contents reflect the new WIM bit settings For example if a block or page that had allowed caching becomes caching inhibited software should ensure that the appropriate cache blocks are flushed to memory and invalidated 3 6 5 Load and Store Coherency Summary Table 3 4 provides a summary of memory coherency actions performed by the MPC603e on load operations Noncacheable cases are not part of this table Table 3 4
404. little endian byte order execution of a load or store string instruction causes the system alignment error handler to be invoked see Byte Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary Ordering in Chapter 3 Operand Conventions in the Programming Environments Manual for more information Table 2 25 lists the integer load and store string instructions Table 2 25 Integer Load and Store String Instructions Name Mnemonic Operand Syntax Load String Word Immediate Iswi rD rA NB Load String Word Indexed Iswx rD rA rB Store String Word Immediate stswi rS rA NB Store String Word Indexed stswx rS rA rB Load string and store string instructions may involve operands that are not word aligned As described in Alignment Exception 0x00600 in Chapter 6 Exceptions in the Programming Environments Manual a misaligned string operation suffers a performance penalty compared to a word aligned operation of the same type When a string operation crosses a 4 Kbyte boundary the instruction may be interrupted by a DSI exception associated with the address translation of the second page In this case the MPC603e performs some or all memory references from the first page and none from the second before taking the exception On return from the DSI exception the load or store string instruction will re
405. llowing are the state meaning and timing comments for the TC 0 1 outputs State Meaning Asserted Negated Represents a special encoding for the transfer in progress see Table 7 5 Timing Comments Assertion Negation The same as A 0 31 High Impedance The same as A 0 31 Table 7 5 Encodings for TC 0 1 Signals TC 0 1 Read Write 00 Data transaction Any write 01 Touch load 10 Instruction fetch 11 Reserved 7 2 4 5 Cache Inhibit Cl Output Following are the state meaning and timing comments for the CI output State Meaning Asserted Indicates that a single beat transfer is not cached reflecting the setting of the I bit for the block or page that contains the address of the current transaction Negated Indicates that a burst transfer allocates a line in the MPC603e data cache Timing Comments Assertion Negation The same as A 0 31 High Impedance The same as A 0 31 Chapter 7 Signal Descriptions For More Information On This Product Go to www freescale com ae Freescale Semiconductor Inc Signal Descriptions 7 2 4 6 Write Through WT Output Following are the state meaning and timing comments for the WT output State Meaning Asserted Indicates that a single beat transaction is write through reflecting the value of the W bit for the block or page that contains the address of the current transaction Negated Indicates that a transaction is n
406. llowing section describes this process in greater detail 6 3 1 General Instruction Flow As many as two instructions can be fetched into the instruction queue IQ in a single clock cycle Instructions enter the IQ and are dispatched to the various execution units from the dispatch queue The IQ is a six entry queue which together with the CQ is the backbone of the master pipeline for the microprocessor The MPC603e tries to keep the IQ full at all times The number of instructions requested in a clock cycle is determined by the number of vacant spaces in the IQ during the previous clock cycle This is shown in the examples in this chapter Although the IQ can accept as many as two new instructions in a single clock cycle and even if there are more than two spaces available on the current clock cycle if only one IQ entry was vacant on the previous cycle only one instruction is fetched Typically instructions are fetched from the on chip instruction cache If the instruction request hits in the on chip instruction cache it can usually present the first two instructions of the new instruction stream in the next clock cycle giving enough time for the next pair of instructions to be fetched from the cache with no idle cycles Instructions not in the instruction cache are fetched from system memory Branch instructions that do not update the LR or CTR are removed from the instruction stream either by branch folding or removal of fall through branch
407. loads stores and moves default to The processor prevents dispatch of floating point instructions including floating point loads stores and moves default Bit 24 is Reserved rather than Reserved Full Function The first sentence of step 4 should be The MSR is set as described in Table 4 7 In Table 4 7 the setting for the IP bit in the System reset row should be a 1 instead of the shown in the table The first note for Table 4 7 should read as The floating point available bit is always cleared to 0 on the EC603e microprocessor Appendix C Revision History For More Information On This Product Go to www freescale com e Semiconductor Inc F Revision Changes From narsescale Se 4 5 1 2 4 20 4 5 5 4 25 4 5 5 4 26 4 5 6 1 1 4 28 4 5 12 4 34 The first sentence in the second paragraph should read as follows Unlike a hard reset no registers or latches are initialized however the instruction cache is disabled HIDO ICE 0 The second sentence in the second paragraph should read as follows After SRESET is recognized as asserted the processor beings fetching instructions from the system reset routine at offset 0x0100 The third sentence should read as follows When a soft reset occurs registers are set as shown in Table 4 9 and HIDO ICE is cleared Replace the second sentence in the second paragraph with the following The 603e allows th
408. ls These signals determine the system clock frequency and can be used to synchronize multiprocessor systems NOTE A bar over a signal name indicates that the signal is active low for example ARTRY address retry and TS transfer start Active low signals are referred to as asserted active when they are low and negated when they are high Signals that are not active low such as AP 0 3 address bus parity signals and TT 0 4 transfer type signals are referred to as asserted when they are high and negated when they are low 1 3 7 3 Signal Configuration Figure 1 5 illustrates the MPC603e logical pin configuration showing how the signals are grouped MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc snecitic Information BR DBG Address BG DBWO Arbitration ABB DBB Address TS Start DH 0 31 DL 0 31 DP 0 7 A 0 31 DPE DBDIS Address Bus AP 0 3 APE TA DRTRY 1 TEA a MMA E 4 5 MPC603e ea EE Ee INT SMI rees 2 3 MCP GBL CKSTP_IN CKSTP_OUT Transfer e 1 Attribute Cl 1 HRESET SRESET WT 1 CSE 0 1 2 RSRV TC 0 1 2 QREQ QACK TBEN TLBISYNG AACK Address 1 Gees e TRST TCK TMS TDI TDO SYSCLK CLK_OUT PLL_CFG 0 3 Clocks d 3 3 V TEST Figure 1 5 Signal Groups Chapter 1 Overview For More Information On This Product Go to www freescale com Data Arbitration Data Transfer
409. ls to find the desired PTE then a page fault must be synthesized The handler must restore the machine state and clear MSR TGPR before invoking the ISI exception 0x00400 Software table search operations are discussed in Chapter 5 Memory Management When an instruction TLB miss exception is taken instruction execution for the handler begins at offset 0x01000 from the physical base address indicated by MSR IP 4 5 13 Data TLB Miss on Load Exception 0x01100 When the effective address for a data load or cache operation cannot be translated by the DTLB a data TLB miss on load exception is generated Register settings for the instruction and data TLB miss exceptions are described in Table 4 17 If a data TLB miss exception handler fails to find the desired PTE then a page fault must be synthesized The handler must restore the machine state and clear MSR TGPR before invoking the DSI exception 0x00300 Table 4 17 Instruction and Data TLB Miss Exceptions Register Settings Register Setting Description SRRO Set to the address of the next instruction to be executed in the program for which the TLB miss exception was generated SRR1 0 3 Loaded from condition register CRO field 4 11 Cleared 12 KEY Key for TLB miss SR Ks or SR Kp depending on whether the access is a user or supervisor access 13 D I Data or instruction access 0 Data TLB miss 1 Instruction TLB miss 14 WAY Next TLB set to be replaced set pe
410. lt E AACK A ARTRY EE W DH 0 31 TA DRTRY TEA y E Figure 8 21 32 Bit Data Bus Transfer Two Beat Burst with DRTRY The MPC603e selects a 64 or 32 bit data bus mode at startup by sampling the state of the TLBISYNC signal at the negation of HRESET If the TLBISYNC signal is negated at the MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING nal SE EEN negation of HRESET 64 bit data mode is entered by the MPC603e If TLBISYNC is asserted at the negation of HRESET 32 bit data mode is entered 8 6 2 No DRTRY Mode The MPC603e supports an optional mode to disable the use of the data retry function provided through DRTRY The no DRTRY mode allows the forwarding of data during load operations to the processor core one bus cycle sooner than in the normal bus protocol The bus protocol specifies that during load operations the memory system can normally cancel data that was read by the master on the bus cycle after TA was asserted This late cancellation protocol requires the MPC603e to hold any loaded data at the bus interface for one additional bus clock to verify that the data is valid before forwarding it to the processor core For systems that do not implement the DRTRY function the MPC603e provides an optional no DRTRY mode that eliminates this one cycle stall during all load operations and allows fo
411. m Freescale Semiconductor Inc Signal Configuration e Data transfer termination signals Data termination signals are required after each data beat in a data transfer In a single beat transaction the data termination signals also indicate the end of the tenure In burst accesses the data termination signals apply to individual beats and indicate the end of the tenure only after the final data beat They also indicate whether a condition exists that requires the data phase to be repeated e System status signals These signals include the external interrupt signal checkstop signals and both soft and hard reset signals These signals are used to interrupt and under various conditions to reset the processor e JTAG COP interface signals The JTAG IEEE 1149 1 interface and common on chip processor COP unit provides a serial interface to the system for performing monitoring and boundary tests e Processor status These signals include the memory reservation machine quiesce control time base enable and TLBISYNC signals e Clock signals These signals provide for system clock input and frequency control 7 1 Signal Configuration Figure 7 1 shows how the MPC603e microprocessor s signals are grouped NOTE A pinout showing actual pin numbers is included in the MPC603e RISC Microprocessor Hardware Specifications 7 2 Signal Descriptions This section describes individual MPC603e signals grouped according to Figure 7 1
412. m 0 to 1 Must also be enabled with MSR EE Reserved 00A00 00BFF System call 00C00 A system call exception occurs when a System Call sc instruction is executed Trace 00D00 A trace exception is taken when MSR SE 1 or when the currently completing instruction is a branch and MSR BE 1 Reserved 00E00 The MPC603e does not generate an exception to this vector Other processors may use this vector for floating point assist exceptions Reserved 00E10 00FFF Instruction 01000 An instruction translation miss exception is caused when an effective address for translation miss an instruction fetch cannot be translated by the ITLB Data load 01100 A data load translation miss exception is caused when an effective address for a translation miss data load operation cannot be translated by the DTLB Data store 01200 A data store translation miss exception is caused when an effective address for a translation miss data store operation cannot be translated by the DTLB or where a DTLB hit occurs and the change bit in the PTE must be set due to a data store operation Instruction 01300 An instruction address breakpoint exception occurs when the address bits 0 29 address in the IABR matches the next instruction to complete in the completion unit and breakpoint IABR 30 is set System 01400 A system management interrupt is caused when MSR EE 1 and the SMI input management signal is asserted interrupt Reserved 01500 02FFF
413. master clock may be set to an integer or half integer multiple 1 1 1 5 1 2 1 2 5 1 3 1 3 5 1 or 4 1 of the SYSCLK frequency allowing the CPU core to operate at an equal or greater frequency than the bus interface State Meaning Asserted Negated The SYSCLK input is the primary clock input for the MPC603e and represents the bus clock frequency for MPC603e bus operation Internally the MPC603e may be operating at an integer or half integer multiple of the bus clock frequency Timing Comments Duty cycle Refer to the appropriate hardware specifications for timing comments Chapter 7 Signal Descriptions For More Information On This Product Go to www freescale com ae Freescale Semiconductor Inc Signal Descriptions Note SYSCLK is used as the frequency reference for the internal PLL clock generator and must not be suspended or varied during normal operation to ensure proper PLL operation 7 2 12 2 Test Clock CLK_OUT Output The MPC603e provides a CLK_OUT signal for test purposes that allows the monitoring of the processor and bus clock frequencies The frequency of the CLK_OUT signal is determined by the configuration of HIDO SBCLK ECLK as shown in Table 7 9 Note that the PID7t 603e CLK_OUT signal is driven at the processor frequency during the assertion of HRESET when HRESET is negated CLK_OUT enters the default high impedance state Table 7 9 CLK_OUT Signal Configuration HIDO SBCLK HIDO ECLK
414. mation On This Product Go to www freescale com 5 1 7 5 16 Freescale Semicond uctor doe Revision 1 to Revision 2 In Table 5 4 replace the first three rows with the following table and delete the sixth row Iwarx or stwex with W 1 Table 5 4 Other MMU Exception Conditions Condition Description Exception TLB miss for an instruction fetch No matching entry found in ITLB Instruction TLB miss exception SRR1 13 1 MSR 14 1 TLB miss for a data load access No matching entry found in DTLB for Data TLB miss on load exception data load access SRR1 13 0 SRR1 15 1 MSR 14 1 andC 0 TLB miss for a data store or store No matching entry found in DTLB for Data TLB miss on store exception data store access or matching DLTB or store and C 0 entry has C 0 and the access is a SRR1 13 0 store SRR1 15 0 MSR 14 1 5 1 8 5 18 5 1 8 5 18 5 5 2 2 2 5 42 5 5 2 2 2 5 45 5 3 5 20 In Table 5 5 add the following paragraph at the end of the tlbie description Software must ensure that instruction fetches or memory references to the virtual pages specified by the tlbie instruction have been completed prior to executing the tlbie instruction In Table 5 5 add the following sentence at the end of the tlbsyne description For a complete description of the TLBISYNC signal refer to Section 8 8 2 TLBSYNC Input Replace the third line of the ml segment in
415. may take three cycles for a floating point instruction to complete but if there are no stalls in the floating point pipeline a series of floating point instructions can have a throughput of one instruction per cycle The MPC603e instruction pipeline has four major pipeline stages described as follows e The fetch pipeline stage primarily involves retrieving instructions from the memory system and determining the location of the next instruction fetch Additionally if possible the BPU decodes branches during the fetch stage and folds out branch instructions before the dispatch stage e The dispatch pipeline stage is responsible for decoding the instructions supplied by the instruction fetch stage and determining which of the instructions are eligible to be dispatched in the current cycle In addition the source operands of the instructions are read from the appropriate register file and dispatched with the instruction to the execute pipeline stage At the end of the dispatch pipeline stage the dispatched instructions and their operands are latched by the appropriate execution unit e In the execute pipeline stage each execution unit with an executable instruction executes the selected instruction perhaps over multiple cycles writes the instruction s result into the appropriate rename register and notifies the completion stage when the execution has finished In the case of an internal exception the execution unit reports the exception
416. mechanism is flexible allowing the MPC603e to be integrated into systems that implement various fairness and bus parking procedures to avoid arbitration overhead Typically memory accesses are weakly ordered sequences of operations including load store string and multiple instructions do not necessarily complete in the order they begin maximizing the bus efficiency without sacrificing data coherency The MPC603e allows load operations to precede store operations except when a dependency exists In addition the MPC603e can be configured to reorder high priority store operations ahead of lower priority store operations Because the processor can dynamically optimize run time ordering of load store traffic overall performance is improved Note that the Synchronize sync instruction can be used to enforce strong ordering The following sections describe how the MPC603e interface operates providing detailed timing diagrams that illustrate how the signals interact A collection of more general timing diagrams are included as examples of typical bus operations Table 8 1 is a legend of the conventions used in the timing diagrams MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Overview This is a synchronous interface all MPC603e input signals are sampled and output signals are driven on the rising edge of the bus clock cycle see the MPC603e
417. memory access instruction causes direct store error exceptions the results are guaranteed to be determined before this instruction is executed e Previous instructions complete execution in the context privilege protection and address translation under which they were issued e The instructions following the sc or rfi instruction execute in the context established by these instructions 2 3 2 4 2 Execution Synchronization An instruction is execution synchronizing if all previously initiated instructions appear to have completed before the instruction is initiated or in the case of the Synchronize sync and Instruction Synchronize isync instructions before the instruction completes For example the Move to Machine State Register mtmsr instruction is execution synchronizing It ensures that all preceding instructions have completed execution and will not cause an exception before the instruction executes but does not ensure subsequent instructions execute in the newly established environment For example if the mtmsr sets MSR PR unless an isyne immediately follows the mtmsr instruction a privileged instruction could be executed or privileged access could be performed without causing an exception even though MSR PR indicates user mode 2 3 2 4 3 Instruction Related Exceptions There are two kinds of exceptions in the MPC603e those caused directly by the execution of an instruction and those caused by an asynchronous event Eit
418. memory that is write through required or caching inhibited MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Exception Classes Table 4 2 Exceptions and Conditions continued Exception Type Vector Offset hex Causing Conditions Program 00700 A program exception is caused by one of the following exception conditions which correspond to bit settings in SRR1 and arise during execution of an instruction Floating point enabled exception A floating point enabled exception condition is generated when the following condition is met MSR FEO MSR FE1 amp FPSCR FEX is 1 e FPSCR FEX is set by the execution of a floating point instruction that causes an enabled exception or by the execution of one of the move to FPSCR instructions that results in both an exception condition bit and its corresponding enable bit being set in the FPSCR e Illegal instruction An illegal instruction program exception is generated when execution of an instruction is attempted with an illegal opcode or illegal combination of opcode and extended opcode fields including PowerPC instructions not implemented in the MPC603e or when execution of an optional instruction not provided in the MPC603e is attempted these do not include those optional instructions that are treated as no ops e Privileged instruction A privileged instruct
419. miconductor Inc es Signal Descriptions Table 7 8 Pipeline Tracking Outputs continued Bits Function Encoding DP 6 7 Prediction 00 Nonspec 01 Spec_2nd 10 Spec_both 11 Flush_spec AP 0 3 FEA FEA 20 23 Given the object code these signals provide sufficient information to track instruction execution except for register indirect branches Register indirect branches may be tracked either by examining and matching potential target streams nonintrusive but not always resolvable or by forcing register indirect branch targets to be fetched externally by setting HIDO FBIOB Setting HIDO EICE also directs the processor clock to the CLK_OUT signal providing a synchronizing clock to the pipeline tracking outputs 7 2 12 Clock Signals The clock signal inputs of the MPC603e determine the system clock frequency and provide a flexible clocking scheme that allows the processor to operate at an integer multiple of the system clock frequency Refer to the appropriate hardware specifications for exact timing relationships of the clock signals 7 2 12 1 System Clock SYSCLK Input The MPC603e requires a single system clock SYSCLK input This input sets the frequency of operation for the bus interface Internally the MPC603e uses a phase locked loop PLL circuit to generate a master clock for all of the CPU circuitry including the bus interface circuitry which is phase locked to the SYSCLK input The
420. mments Assertion Coincides with the assertion of ABB Negation Occurs one bus clock cycle after TS is asserted High Impedance Coincides with the negation of ABB 7 2 2 1 2 Transfer Start TS Input Following are the state meaning and timing comments for the TS input State Meaning Asserted Indicates that another master has begun a bus transaction and that the address bus and transfer attribute signals are valid for snooping see GBL Negated Indicates that no bus transaction is occurring Timing Comments Assertion May occur during the assertion of ABB Negation Must occur one bus clock cycle after TS is asserted 7 2 3 Address Transfer Signals The address transfer signals are used to transmit the address and to generate and monitor parity for the address transfer For a detailed description of how these signals interact refer to Section 8 3 2 Address Transfer 7 2 3 1 Address Bus A 0 31 The address bus A 0 31 consists of 32 signals that are both input and output signals MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc i Ka Signal Descriptions 7 2 3 1 1 Address Bus A 0 31 Output Following are the state meaning and timing comments for the A 0 31 outputs State Meaning Asserted Negated Represents the physical address real address in the architecture specification of the data to be transferred On
421. mode is set e Software hardware and performance transparent 9 3 1 3 Doze Mode Doze mode disables most functional units but maintains cache coherency by enabling the bus interface unit and snooping A snoop hit causes the MPC603e to enable the data cache copy the data back to memory disable the cache and fully return to the doze mode Chapter 9 Power Management For More Information On This Product Go to www freescale com DEE Freescale Semiconductor Inc Doze mode is characterized by the following features e Most functional units disabled e Bus snooping and time base decrementer still enabled e PLL running and locked to SYSCLK To enter the doze mode the following conditions must occur e Set doze bit HIDO 8 1 MSR POW is set e MPC603e enters doze mode after several processor clocks To return to full power mode the following conditions must occur e Assert INT MCP SMI or decrementer interrupts e Hard reset or soft reset e Transition to full power state occurs only after a few processor cycles 9 3 1 4 Nap Mode The nap mode disables the MPC603e except for the processor PLL and time base decrementer The time base can be used to restore the core to a full on state after a specified period Because bus snooping is disabled for nap and sleep mode a hardware handshake using the quiesce request QREQ and quiesce acknowledge QACK signals are required to maintain data coherency The MPC603e will assert the QREQ signa
422. mory Synchronization Instructions VEA Memory synchronization instructions control the order in which memory operations are performed with respect to asynchronous events and the order in which memory operations are seen by other processors or memory access mechanisms See Chapter 3 Instruction and Data Cache Operation for additional information about these instructions and about related aspects of memory synchronization Implementation Notes The following describes how the MPC603e handles memory synchronization in the VEA e The Instruction Synchronize isync instruction causes the MPC603e to discard all prefetched instructions wait for any preceding instructions to complete and then branch to the next sequential instruction having the effect of clearing the pipeline behind the isync instruction e The Enforce In Order Execution of I O eieio instruction is used to ensure memory reordering of noncacheable memory access Because the MPC603e does not reorder noncacheable memory accesses the eieio instruction is treated as a no op Table 2 34 lists the VEA memory synchronization instructions for the MPC603e Table 2 34 Memory Synchronization Instructions VEA Name Mnemonic Operand Syntax Enforce In Order Execution of I O eieio Instruction Synchronize isync 2 3 5 3 Memory Control Instructions VEA Memory control instructions include the following types e Cache management instructions e S
423. move data from FPRs to memory The FPRs are 64 bits wide and store floating point values in double precision format Floating point unit The functional unit in the MPC603e processor responsible for executing all floating point instructions Flush An operation that causes a cache block to be invalidated and the data if modified to be written to memory Fraction In the binary representation of a floating point number the field of the significand that lies to the right of its implied binary point General purpose register GPR Any of the 32 registers in the general purpose register file These registers provide the source operands and destination results for all integer data manipulation Glossary of Terms and Abbreviations For More Information On This Product Go to www freescale com Freescale Semiconductor Inc instructions Integer load instructions move data from memory to GPRs and store instructions move data from GPRs to memory Guarded The guarded attribute pertains to out of order execution When a page is designated as guarded instructions and data cannot be accessed out of order Harvard architecture An architectural model featuring separate caches and other memory management resources for instructions and data Hashing An algorithm used in the page table search process IEEE 754 A standard written by the Institute of Electrical and Electronics Engineers that defines operations and representations
424. mpt to emulate a misaligned Iwarx or stwex instruction because there is no correct way to define the address associated with the reservation In general the lwarx and stwex instructions should be used only in system programs which can be invoked by application programs as needed At most one reservation exists simultaneously on any processor The address associated with the reservation can be changed by a subsequent Iwarx instruction The conditional store is performed based on the existence of a reservation established by the preceding Iwarx regardless of whether the address generated by the Ilwarx matches that generated by Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary the stwex instruction A reservation held by the processor is cleared by one of the following e Executing an stwex instruction to any address e Attempt by some other device to modify a location in the reservation granularity 32 bytes The Iwarx and stwex instructions to write through memory do not cause a DSI exception Table 2 32 lists the UISA memory synchronization instructions for the MPC603e Table 2 32 Memory Synchronization Instructions UISA Name Mnemonic Operand Syntax Load Word and Reserve Indexed lwarx rD rA rB Store Word Conditional Indexed stwex rS rA rB Synchronize sync SH 2 3 5 PowerPC VEA Instructions Th
425. mpted to complete next if no interrupt conditions were present SRR1 0 15 Cleared 16 31 Loaded from MSR 16 31 MSR POW 0 FE 0 FEO 0 IR 0 TGPR 0 PR 0 SE 0 DR 0 ILE FP 0 BE 0 RI 0 IP ME FE1 0 LE Set to value of ILE When a system management interrupt is taken instruction execution for the handler begins at offset 0x01400 from the physical base address indicated by MSR IP The MPC603e recognizes the interrupt condition SMI asserted only if the MSR EE bit is set otherwise the interrupt condition is ignored To guarantee that the external interrupt is taken the SMI signal must be held active until the MPC603e takes the interrupt If the SMI signal is negated before the interrupt is taken the MPC603e is not guaranteed to take a system management interrupt The interrupt handler must send a command to the device that asserted SMI acknowledging the interrupt and instructing the device to negate SMI MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 5 Memory Management This chapter describes the MPC603e microprocessor s implementation of the memory management unit MMU specifications provided by the PowerPC operating environment architecture OEA for processors that implement the PowerPC architecture The MPC603e MMU implementation is very similar to that of the MPC603 microprocessor except that the MPC603e imp
426. mpting to execute the given instruction Branch folding The replacement with target instructions of a branch instruction and any instructions along the not taken path when a branch is either taken or predicted as taken Branch prediction The process of guessing whether a branch will be taken Such predictions can be correct or incorrect the term predicted as it is used here does not imply that the prediction is correct successful The PowerPC architecture defines a means for static branch prediction as part of the instruction encoding Branch resolution The determination of whether a branch is taken or not taken A branch is said to be resolved when the processor can determine which instruction path to take If the branch is resolved as predicted the instructions following the predicted branch that may have been speculatively executed can complete If the branch is not resolved as predicted instructions on the mispredicted path and any results of speculative execution are purged from the pipeline and fetching continues from the nonpredicted path Burst A multiple beat data transfer whose total size is typically equal to a cache block Bus clock Clock that causes the bus state transitions MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bus master The owner of the address or data bus the device that initiates or requests the tr
427. multiple instructions concurrently from a conventional linear instruction stream In a superscalar implementation multiple instructions can be in the same stage at the same time e Throughput A measure of the number of instructions that are processed per cycle For example a series of double precision floating point multiply instructions has a throughput of one instruction per clock cycle e Write back Write back in the context of instruction handling occurs when a result is written from the rename registers into the architectural registers typically the GPRs and FPRs Results are written back at completion time or are moved into the write back buffer Results in the write back buffer cannot be flushed If an exception occurs these buffers must write back before the exception is taken 6 2 Instruction Timing Overview The MPC603e design minimizes average instruction execution latency the number of clock cycles it takes to fetch decode dispatch and execute instructions and make the results available for a subsequent instruction Some instructions such as loads and stores access memory and require additional clock cycles between the execute phase and the write back phase These latencies vary depending on whether the access is to cacheable or noncacheable memory whether it hits in the L1 cache whether the cache access generates a write back to memory whether the access causes a snoop hit from another device that generates additional
428. n Data bus arbitration uses the data arbitration signal group DBG DBWO and DBB Additionally the combination of TS and TT 0 4 provides information about the data bus request to external logic The TS signal is an implied data bus request from the MPC603e the arbiter must qualify TS with the transfer type TT encodings to determine if the current address transfer is an address only operation which does not require a data bus transfer see Figure 8 6 If the data bus is needed the arbiter grants data bus mastership by asserting the DBG input to the MPC603e As with the address bus arbitration phase the MPC603e must qualify the DBG input with a number of input signals before assuming bus mastership as shown in Figure 8 7 A qualified data bus grant can be expressed as the following Qualified data bus grant DBG asserted while DBB DRTRY and ARTRY associated with the data bus operation are negated When a data tenure overlaps with its associated address tenure a qualified ARTRY assertion coincident with a data bus grant signal does not result in data bus mastership DBB is not asserted Otherwise the MPC603e always asserts DBB on the bus clock cycle after recognition of a qualified data bus grant Since the MPC603e can pipeline transactions there may be an outstanding data bus transaction when a new address transaction is retried In this case the MPC603e becomes the data bus master to complete the previous transaction
429. n On This Product Go to www freescale com Overview E Sequential Fetcher 64 Bit Instruction Queue System Register Unit Dispatch Unit Load Store GP Rename Unit Registers D MMU DBAT Completion Unit Power Dissipation Control Array DTLB Time Base Counter Decrementer Clock Multiplier Touch Load Buffer 16 Kbyte JTAG COP D Cache Interface Copy Back Buffer 32 Bit Address Bus 32 64 Bit Data Bus Freescale Semiconductor Inc 64 Bit 2 Instructions Branch Processing Unit Instruction Unit FPR File Floating Point Unit FP Rename Registers I MMU BAT Array 16 Kbyte Cache Processor Bus Interface Figure 1 1 MPC603e Microprocessor Block Diagram MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc i Overview The MPC603e provides independent on chip 16 Kbyte four way set associative physically addressed caches for instructions and data and on chip instruction and data memory management units MMUs The MMUs contain 64 entry two way set associative data and instruction translation lookaside buffers DTLB and ITLB that provide support for demand paged virtual memory address translation and variable sized block translation The TLBs and caches use a least recently used LRU replacement algorithm The MPC603e also supports block address translation
430. n a computation and then modify the same or another memory location the memory contents must be loaded into a register modified and then written to the target location using load and store instructions MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor In uction Serna The description of each instruction includes the mnemonic and a formatted list of operands To simplify assembly language programming a set of simplified mnemonics extended mnemonics in the architecture specification and symbols is provided for some of the frequently used instructions see Appendix F Simplified Mnemonics in the Programming Environments Manual for acomplete list of simplified mnemonic examples 2 3 1 Classes of Instructions The MPC603e instructions belong to one of the following three classes e Defined e Illegal e Reserved Note that although the definitions of these terms are consistent among the processors of this family the assignment of these classifications is not For example an instruction that is specific to 64 bit implementations is considered defined for 64 bit implementations but illegal for 32 bit implementations such as the MPC603e The class is determined by examining the primary opcode and the extended opcode if any If either is not that of a defined instruction or of a reserved instruction the instruction is illegal In future versions of
431. n each clock cycle For an instruction to be dispatched the required execution unit must be available The dispatcher monitors the availability of all execution units and suspends instruction dispatch if the required execution unit is unavailable An execution unit may not be available if it can accept and execute only one instruction per cycle or if an execution unit s pipeline becomes full which may occur if instruction execution takes more clock cycles than the number of pipeline stages in the unit and additional instructions are dispatched to that unit to fill the remaining pipeline stages 6 4 Execution Unit Timings The following sections describe instruction timing considerations for each execution unit 6 4 1 Branch Processing Unit Execution Timing Flow control operations conditional branches unconditional branches and traps are typically expensive to execute in most machines because they disrupt normal flow in the instruction stream When a change in program flow occurs the IQ must be reloaded with the target instruction stream During this time the execution units will be idle However previously dispatched instructions will continue to execute while the new instruction stream makes its way into the IQ Performance features such as branch folding and static branch prediction help minimize penalties associated with flow control operations The timing for branch instruction execution is determined by many factors including the f
432. n the MPC603e clock is configured for 1 1 or 1 5 1 processor to bus clock mode the ARTRY snoop response cannot be determined in the minimum allowed address tenure period Thus in a system with two or more MPC603e processors using 1 1 or 1 5 1 clock mode AACK must not be asserted until the third clock of the address tenure one address wait state to allow the snooping MPC603e processors an opportunity to assert ARTRY on the bus For other clock configurations 2 1 2 5 1 3 1 3 5 1 and 4 1 the ARTRY snoop response can be determined in the minimum address tenure period and AACK may be asserted as early as the second bus clock of the address tenure As shown in Figure 8 6 these signals are asserted for one bus clock cycle three stated for half of the next bus clock cycle driven high until the following bus cycle and finally three stated Note that AACK must be asserted for only one bus clock cycle Chapier 8 System Interface Operation For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Address Bus Tenure 1 2 3 4 5 6 7 8 pusclock LI Ir F EN E OLE III TS Sr e e s AACK qual_bg ABB The address transfer can be terminated with the requirement to retry if ARTRY is asserted anytime during the address tenure and through the cycle following AACK The assertion causes the entire transaction address and data tenure to be rerun A
433. nd most double precision operations e Five independent execution units and two register files BPU featuring static branch prediction A 32 bit IU Fully IEEE 754 compliant FPU for both single and double precision operations LSU for data transfer between data cache and GPRs and FPRs SRU that executes condition register CR special purpose register SPR and integer add compare instructions Chapter 1 Overview For More Information On This Product Go to www freescale com EES Freescale Semiconductor Inc Thirty two GPRs for integer operands Thirty two FPRs for single or double precision operands e High instruction and data throughput Zero cycle branch capability branch folding Programmable static branch prediction on unresolved conditional branches Instruction fetch unit capable of fetching two instructions per clock from the instruction cache A six entry instruction queue IQ that provides lookahead capability Independent pipelines with feed forwarding that reduces data dependencies in hardware 16 Kbyte data cache and 16 Kbyte instruction cache four way set associative physically addressed LRU replacement algorithm Cache write back or write through operation programmable on a per page or per block basis BPU that performs CR lookahead operations Address translation facilities for 4 Kbyte page size variable block size and 256 Mbyte segment size A
434. nd store multiple instructions with misaligned operands that is the EA is not a multiple of four to cause an alignment exception The MPC603e defines the load multiple word Imw instruction with rA in the range of registers to be loaded as an invalid form The PowerPC architecture describes some preferred instruction forms for the integer load and store multiple instructions that may perform better than other forms in some implementations None of these preferred forms affect instruction performance in the MPC603e When the MPC603e is operating with little endian byte order execution of a load or store multiple instruction causes the system alignment error handler to be invoked see Byte Ordering in Chapter 3 Operand Conventions in the Programming Environments Manual for more information Table 2 24 lists the integer load and store multiple instructions for the MPC603e Table 2 24 Integer Load and Store Multiple Instructions Name Mnemonic Operand Syntax Load Multiple Word Imw rD d rA Store Multiple Word stmw rS d rA 2 3 4 3 7 Integer Load and Store String Instructions The integer load and store string instructions allow movement of data from memory to registers or from registers to memory without concern for alignment These instructions can be used for a short move between arbitrary memory locations or to initiate a long move between misaligned memory fields When the MPC603e is operating with
435. ndexed lwzx rD rA rB Load Word and Zero with Update lwzu rD d rA Load Word and Zero with Update Indexed lwzux rD rA rB 2 3 4 3 4 Integer Store Instructions For integer store instructions the contents of rS are stored into the byte half word word or double word in memory addressed by the effective address Many store instructions have an update form in which rA is updated with the EA For these forms the following rules apply e IfrA 0 the EA is placed into rA e IfrS rA the contents of rS are copied to the target memory element then the generated EA is placed into rA rS The MPC603e defines store with update instructions with rA O and integer store instructions with the CR update option enabled Rc field bit 31 in the instruction encoding 1 to be invalid forms Table 2 22 provides a list of the integer store instructions for the MPC603e Table 2 22 Integer Store Instructions Name Mnemonic Operand Syntax Store Byte stb rS d rA Store Byte Indexed stbx rS rA rB Store Byte with Update stbu rS d rA Store Byte with Update Indexed stbux rS rA rB Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary Table 2 22 Integer Store Instructions continued Name Mnemonic Operand Syntax Store Half Word sth rS d rA Store Half Word Indexed sthx rS rA rB Stor
436. ne another beginning with a description and complete summary of MPC603e specific registers and progressing to more specialized topics such as MPC603e specific details regarding the cache exception and memory management models As such chapters may include information from multiple levels of the architecture For example the discussion of the cache model uses information from both the VEA and the OEA The PowerPC Architecture A Specification for a New Family of RISC Processors defines the architecture from the perspective of the three programming environments and remains the defining document for the PowerPC architecture The information in this book is subject to change without notice as described in the disclaimers on the title page As with any technical documentation it is the readers responsibility to be sure they are using the most recent version of the documentation For updates to this document refer to http www freescale com Audience This manual is intended for system software and hardware developers and applications programmers who want to develop products using the MPC603e microprocessors It is assumed that the reader understands operating systems microprocessor system design basic principles of RISC processing and details of the PowerPC architecture Organization The following summary briefly describes the major sections of this manual e Chapter 1 Overview is useful for readers who want a general unders
437. negation to delay the third data beat e The final read burst shows the use of DRTRY on the third data beat e The address for the third transfer is delayed until the first transfer completes ij 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Ajo 31 _opua yH rua yH a WI Figure 8 18 Burst Transfers with Data Delay Controls Chapier 8 System Interface Operation For More Information On This Product Go to www freescale com D Freescale Semiconductor Inc Timing Examples Figure 8 19 shows the use of the TEA signal Note that all bidirectional signals are three stated between bus tenures Note the following e The first data beat of the read burst in clock 0 is the critical quad word e The TEA signal truncates the burst write transfer on the third data beat e The MPC603e eventually causes an exception to be taken on the TEA event 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A 0 31 _cPUA_ _PUA CEA TT 0 4 Read Read Figure 8 19 Use of Transfer Error Acknowledge TEA MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING nal Bina EEN 8 6 Optional Bus Configurations The MPC603e supports three optional bus configurations that are selected by the assertion or negation of DRTRY TLBISYNC and QACK during the negation of HRESET The operation and selection
438. ng and multiple instructions Load and store instructions are issued and executed in program order however the memory accesses can occur out of order Synchronizing instructions are provided to enforce strict ordering Cacheable loads when free of data dependencies can execute out of order with a maximum throughput of one per cycle and a two cycle total latency Data returned from the cache is held in a rename register until the completion logic commits the value to a GPR or FPR Stores cannot be executed in a predicted manner and are held in the store queue until the completion logic signals that the store operation is to be completed to memory The MPC603e executes store instructions with a maximum throughput of one per cycle and a three cycle total latency The time required to perform the actual load or store depends on whether the operation involves the cache system memory or an I O device 1 1 4 4 System Register Unit SRU The SRU executes various system level instructions including condition register logical operations and move to from special purpose register instructions It also executes integer add compare instructions In order to maintain system state most instructions executed by the SRU are completion serialized that is the instruction is held for execution in the SRU MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Overview
439. ng of dcbz by marking the memory space being addressed by the debz instruction as not global in the BAT or PTE MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING uction Ee Note that incoherency may occur if the following sequence of accesses hits the same cache block a write through a dcbz instruction a snoop This occurs when the logical address for the dchz and the write through store are different but aliased to the same physical page 2 3 5 4 External Control Instructions The eciwx instruction provides an alternative way to map special devices The MMU translation of the EA is not used to select the special device as it is used in loads and stores Rather it is used as an address operand that is passed to the device over the address bus Four other signals the burst and size signals on the 60x bus are used to select the device these four signals output the 4 bit resource ID RID field in the EAR register The eciwx instruction also loads a word from the data bus that is output by the special device Executing these instructions when MSR DR 0 causes a programming error and the physical address on the bus is undefined Executing these instructions to a direct store segment causes a DSI exception The external control instructions are listed in Table 2 36 Table 2 36 External Control Instructions Name Mnemonic Operand Syntax Exte
440. nization Instructions VEA e Memory control instructions These provide control of caches TLBs and segment registers For more information see Section 2 3 5 3 Memory Control Instructions VEA and Section 2 3 6 3 Memory Control Instructions OEA e System linkage instructions These include the System Call sc and Return from Interrupt rfi instructions See Section 2 3 6 1 System Linkage Instructions e External control instructions These include instructions for use with special input output devices See Section 2 3 5 4 External Control Instructions Note that this grouping of instructions does not necessarily indicate the execution unit that processes a particular instruction or group of instructions This information which is useful in taking full advantage of the MPC603e superscalar parallel instruction execution is provided in Chapter 8 Instruction Set of the Programming Environments Manual Integer instructions operate on word operands Floating point instructions operate on single and double precision floating point operands The PowerPC instructions are 4 byte words The UISA provides for byte half word and word operand loads and stores between memory and a set of 32 GPRs It also provides for word and double word operand loads and stores between memory and a set of 32 FPRs Arithmetic and logical instructions do not read or modify memory To use the contents of a memory location i
441. no snooping of the instruction cache In the PID7t 603e the critical double word is simultaneously written to the cache and forwarded to the requesting unit thus minimizing stalls due to load delays 3 1 3 Instruction Cache Control In addition to instruction cache control instructions the MPC603e provides several HIDO bits to control invalidating disabling and locking the instruction cache The WIMG bits in the page tables and the IBATs also affect the cacheability of pages and whether the pages are considered guarded 3 1 3 1 Instruction Cache Invalidation Although the MPC603e instruction cache is automatically invalidated during a power on or hard reset asserting SRESET does not invalidate the instruction cache Software can invalidate the contents of the instruction cache using the instruction cache flash invalidate control bit HIDO ICFI Flash invalidation of the instruction cache is accomplished by setting and clearing ICFI with two consecutive mtspr HIDO instructions 3 1 3 2 Instruction Cache Disabling The instruction cache may be disabled through the use of the instruction cache enable control bit HIDO ICE When the instruction cache is in the disabled state the cache tag MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Ing nization and Conirol state bits are ignored and all accesses are propagated to the bus as single beat transaction
442. ns Bus Operation Four beat read Reload dump No XXX E Write data_in to cache double word aligned Four beat write Reloaddump No XXX l M Write data_in to cache double word aligned EA Snoop No XXX E l State change only write or kill committed M gt I Snoop No XXX M l State change only kill committed Push Snoop No XXX M l Conditionally push Write with kill M gt I flush Push Snoop No XXX M E Conditionally push Write with kill M gt E clean tlbie TLB No XXX D xX 1 CRTRY TLBI invalidate 2 Pass TLBI 3 No action sync Synchroni No XXX X X 1 CRTRY sync zation 2 Pass sync 3 No action Note Single beat writes are not snooped in the write queue Chapter 3 Instruction and Data Cache Operation For More information On This Product Go to www freescale com TE EE Freescale Semiconductor Inc MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 4 Exceptions The PowerPC exception mechanism allows the processor to change to supervisor state as a result of external signals errors or unusual conditions arising in the execution of instructions and differ from the arithmetic exceptions defined by the IEEE for floating point operations When exceptions referred to as interrupts in the architecture specification occur information about the state of the processor is
443. ns that are not naturally aligned may suffer performance degradation depending on the type of operation the boundaries crossed and the mode that the processor is in during execution More specifically these operations may either cause an alignment exception or they may cause the processor to break the memory access into multiple smaller accesses with respect to the cache and the memory subsystem Chapter 4 Exceptions For More Information On This Product Go to www freescale com mor Freescale Semiconductor Inc Exception Definitions The MPC603e can initiate an alignment exception for the access shown in Table 4 15 In this case the appropriate range check is performed before the instruction begins execution As a result if an alignment exception is taken it is guaranteed that no portion of the instruction has been executed Table 4 15 Access Types MSR DR SR T Access Type 1 0 Page address translation access A page address translation access occurs when MSR DR is set SR T is cleared and there is not a match in the BAT Note the following points e The following is true for all loads and stores except strings multiples Byte operands never cause an alignment exception Half word operands can cause an alignment exception if the EA ends in OxFFF Word operands can cause an alignment exception if the EA ends in 0xFFD FFF Double word operands cause an alignment exception if the EA
444. nsiderations 6 4 4 Load Store Unit Execution Timing The LSU executes all floating point and integer loads and stores It also executes other instructions that address memory The execution of most load and store instructions is pipelined The LSU has two pipeline stages the first is for effective address calculation and MMU translation and the second is for accessing the physically addressed memory Load and store instructions have a 2 cycle latency and 1 cycle throughput If operands are misaligned additional latency may be required either for an alignment exception to be taken or for additional bus accesses Load instructions that miss in the cache prevent subsequent cache accesses during the cache line refill See Table 6 6 for load and store instruction execution timing 6 4 5 System Register Unit Execution Timing Most SRU instructions access or modify nonrenamed registers or directly access renamed registers They generally execute in a serial manner Results from these instructions are not available or forwarded for use by subsequent instructions until the instruction completes and is retired The SRU can also execute the integer instructions addi addis add addo cmpi cmp cmpli and cmpl without serialization and in parallel with another integer instruction Refer to Section 6 3 3 2 Instruction Serialization for additional information on serializing instructions and Table 6 2 Table 6 3 and Table 6 4 for SRU instruction exe
445. nter to first hash pteg gt pointer to second hash pteg Register usage saved counter junk pointer to pteg current compare value Oorg vec0 0x1000 tlbInstrMiss mfspr addi mfctr mfspr addi imos mtctr imis lwzu cmp bdnzf bne 1 andi bne mtctr mfspr mfspr mtcrft mtspr ori srw tlbli stb BEL eO is ri is r2 is i EILS instrSecHash andi bne mfspr ori addi addi b r2 hashl get first pointer rl 0 8 load 8 for counter ro Save counter r3 iCmp get first compare value Ay Dee 8 pre dec the pointer GL load counter rl 8 r2 get next pte Cl ol 3 see if found pte O iml dec count br if cmp ne and if count not zero instrSecHash if not found set up second hash or exit rl 4 r2 load tlb entry lower word 3 L 8 check G bit doISIp if guarded take an ISI ro restore counter r0 iMiss get the miss address for the tlbli r3 srrl get the saved crO bits 0x80 rz restore CRO rpa rl set the pte rl rl 0x100 set reference bit rl rl 8 get byte 7 of pte ro load the itlb rl 6 r2 update page table return to executing program Register usage saved counter junk pointer to pteg current compare value rl r3 0x0040 s if we have done second hash doISI if so go to ISI exception r2 hash2 get the second pointer r3 r3 0x0040 change the compare value CL 1 05 8 load 8 for counter E2627 8 pre dec for update on load im0 try second hash
446. nual For More Information On This Product Go to www freescale com Freescale Semicondugtor In ormance Considerations 6 5 1 Copy Back Mode When data is stored in a location marked as copy back store operations for cacheable data do not necessarily cause an external bus cycle to update memory Instead memory updates only occur on modified line replacements cache flushes or when another processor attempts to access a specific address for which there is a corresponding modified cache entry For this reason copy back mode may be preferred when external bus bandwidth is a potential bottleneck for example in a multiprocessor environment Copy back mode is also well suited for data that is closely coupled to a processor such as local variables If more than one device uses data stored in a page marked as copy back snooping must be enabled to allow copy back operations and cache invalidations of modified data The MPC603e implements snooping hardware to prevent other devices from accessing invalid data When bus snooping is enabled the processor monitors the transactions of the other devices For example if another device accesses a memory location and its memory coherent M bit is set and the MPC603e on chip cache has a modified value for that address the processor preempts the bus transaction and updates memory with the cache data If the cache contents associated with the snooped address are unmodified the MPC603e invalidates the
447. nvalid MESI Modified exclusive shared invalid cache coherency protocol MMU Memory management unit MQ MQ register MSB Most significant byte msb Most significant bit MSR Machine state register About This Book For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Acronyms and Abbreviations Table i Acronyms and Abbreviated Terms continued Term Meaning NaN Not a number No op No operation OEA Operating environment architecture PEM Programming Environments Manual PID Processor identification tag PIM Programming Interface Manual PIR Processor identification register PLL Phase locked loop POR Power on reset POWER Performance Optimized with Enhanced RISC architecture PTE Page table entry PTEG Page table entry group PVR Processor version register RAW Read after write RISC Reduced instruction set computing RPA Required physical address RTL Register transfer language RWITM Read with intent to modify SDR1 Register that specifies the page table base address for virtual to physical address translation SIMM Signed immediate value SLB Segment lookaside buffer SMI System management interrupt SPR Special purpose register SRn Segment register SRRO Machine status save restore register 0 SRR1 Machine status save restore register 1 SRU System register unit TAP Test access port TB Time bas
448. o assert ARTRY on the bus For other clock configurations 2 1 2 5 1 3 1 3 5 1 and 4 1 the ARTRY snoop response can be determined in the minimum address tenure period and AACK may be asserted as early as the second bus clock of the address tenure Insert a new section heading 8 4 4 2 Normal Burst Termination immediately after Figure 8 10 Replace the first sentence of the second paragraph with the following The system quiesce state is entered by configuring the processor to assert the QREQ output The first sentence of the second paragraph should read as follows The reservation RSRV output signal is driven synchronously with the bus clock and reflects the status of the reservation coherency bit in the reservation address buffer see Section 3 9 Instruction and Data Cache Operation for more information In the third sentence of the last paragraph on this page the SMI should have an overbar SMI Change the fourth second level bullet under the Nap mode sequence bullet to the following The processor enters nap mode after several processor clocks The last sub bullet should have overbars on INT and SMI Appendix C Revision History For More Information On This Product Go to www freescale com Revision Changes From anrseseale Semiconductor Inc MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor
449. o gain address bus mastership Transfer After the MPC603e is the address bus master it transfers the address on the address bus The address signals and the transfer attribute signals control the address transfer The address parity and address parity error signals ensure the integrity of the address transfer MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Ines E Termination After the address transfer the system signals that the address tenure is complete or that it must be repeated e Data tenure Arbitration To begin the data tenure the MPC603e arbitrates for data bus mastership Transfer After the MPC603e is the data bus master it samples the data bus for read operations or drives the data bus for write operations The data parity and data parity error signals ensure the integrity of the transfer Termination Data termination signals are required after each beat Note that ina single beat transaction the data termination signals also indicate the end of the tenure while in burst accesses the data termination signals apply to individual beats and indicate the end of the tenure only after the final data beat The MPC603e generates an address only bus transfer during the execution of the dcbz instruction and uses only the address bus with no data transfer involved Additionally the MPC603e retry capability provides an
450. ock fill operation Following the cache block load the MPC603e is the exclusive owner of the data and may write to it without a bus broadcast transaction To maintain this coherency all global reads observed on the bus by the MPC603e are snooped as if they were writes causing the MPC603e to write a modified cache block back to memory and invalidate the cache block or simply invalidate the cache block if it is unmodified The exception to this rule occurs when a snooped transaction is a caching inhibited read either burst or single beat where TT 0 4 0x1010 see Table 7 1 for clarification in which case the MPC603e does not invalidate the snooped cache block If the cache block is modified the block is written back to memory and the cache block is marked exclusive unmodified If the cache block is marked exclusive unmodified when snooped no bus action is taken and the cache block remains in the exclusive unmodified state This treatment of caching inhibited reads decreases the possibility of data thrashing by allowing noncaching devices to read data without invalidating the entry from the MPC603e data cache 3 6 1 MEI State Definitions The MPC603e data cache characterizes each 32 byte block it contains as being in one of three MEI states Addresses presented to the cache are indexed into the cache directory with bits A20 A26 and the upper order 20 bits from the physical address translation PAO PA19 are compared against the indexed cach
451. oduces conditions for another type of interrupt that exception is taken and the post instruction execution exception is forgotten for that instruction 4 2 Exception Processing When an exception is taken the processor uses the save restore registers SRRO and SRR1 to save the contents of the machine state register for user level mode and to identify where instruction execution should resume after the exception is handled 4 2 1 Exception Processing Registers The MPC603e implements the SRRO and SRR1 registers that are used for saving processor state on an exception Also many exception parameters are determined by MSR bits 4 2 1 1 SRRO and SRR1 Bit Settings When an exception occurs SRRO is set to point to the instruction at which instruction processing should resume when the exception handler returns control to the interrupted process All instructions in the program flow preceding this one will have completed and no subsequent instruction will have completed This may be the address of the instruction that caused the exception or the next one as in the case of a system call exception The instruction addressed can be determined from the exception type and status bits This address is used to resume instruction processing in the interrupted process typically when an rfi instruction is executed The SRRO register is shown in Figure 4 1 SRRO Holds EA for Resuming Program Execution Figure 4 1 Machine Status Save Restore
452. of binary floating point numbers Illegal instructions A class of instructions that are not implemented for a particular PowerPC processor These include instructions not defined by the PowerPC architecture In addition for 32 bit implementations instructions that are defined only for 64 bit implementations are considered to be illegal instructions For 64 bit implementations instructions that are defined only for 32 bit implementations are considered to be illegal instructions Implementation A particular processor that conforms to the PowerPC architecture but may differ from other architecture compliant implementations for example in design feature set and implementation of optional features The PowerPC architecture has many different implementations Imprecise exception A type of synchronous exception that is allowed not to adhere to the precise exception model see Precise exception The PowerPC architecture allows only floating point exceptions to be handled imprecisely Instruction queue A holding place for instructions fetched from the current instruction stream Integer unit The functional unit in the MPC603e responsible for executing all integer instructions In order An aspect of an operation that adheres to a sequential model An operation is said to be performed in order if at the time that it is performed it is known to be required by the sequential execution model See Out of order MPC603e RISC Microprocess
453. of eight data beats are performed for burst operations that load into or store from the MPC603e internal caches These transactions transfer 32 bytes in the same way as in 64 bit data bus mode asserting the TBST signal and signaling a transfer size of 2 TSIZ 0 2 0b010 The same bus protocols apply for arbitration transfer and termination of the address and data tenures in the 32 bit data bus mode as they apply to the 64 bit data bus mode Late ARTRY cancellation of the data tenure applies on the bus clock after the first data beat is acknowledged after the first TA for word or smaller transactions or on the bus clock after the second data beat is acknowledged after the second TA for double word or burst operations or coincident with respective TA if no DRTRY mode is selected An example of an eight beat data transfer while the MPC603e is in 32 bit data bus mode is shown in Figure 8 20 Chapter 8 System Interface Operation For More Information On This Product Go to www freescale com _Freescale Semiconductor Inc Optional Bus Configurations TS ctf ADDR _Xx_ gt msr o ACK lt AAA ARTRY Im em DBB _ DH 0 31 aa Ge seht NNN TEA Ty T a Figure 8 20 32 Bit Data Bus Transfer Eight Beat Burst An example of a two beat data transfer with DRTRY asserted during each data tenure is shown in Figure 8 21 LI LOF LOF LONI LNI LN LT L ADDR
454. of memory synchronization The sync instruction delays execution of subsequent instructions until previous instructions have completed to the point that they can no longer cause an exception and until all MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor In ten S previous memory accesses are performed globally the syne operation is not broadcast onto the MPC603e bus interface Additionally all load and store cache bus activities initiated by prior instructions are completed Touch load operations debt and dcbtst are required to complete at least through address translation but are not required to complete on the bus The functions performed by the sync instruction normally take a significant amount of time to complete as a result frequent use of this instruction may adversely affect performance In addition the number of cycles required to complete a sync instruction depends on system parameters and on the processor s state when the instruction is issued The proper paired use of the lwarx and stwex instructions allows programmers to emulate common semaphore operations such as test and set compare and swap exchange memory and fetch and add Examples of these operations can be found in Appendix E Synchronization Programming Examples in the Programming Environments Manual Typically the lwarx instruction should be paired with an stwex instruct
455. oherency protocol used to manage caches on different devices that share a memory system Note that the PowerPC architecture does not specify the implementation of a MEI protocol to ensure cache coherency Memory access ordering The specific order in which the processor performs load and store memory accesses and the order in which those accesses complete Memory mapped accesses Accesses whose addresses use the page or block address translation mechanisms provided by the MMU and that occur externally with the bus protocol defined for memory Glossary of Terms and Abbreviations For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory coherency An aspect of caching in which it is ensured that an accurate view of memory is provided to all devices that share system memory Memory consistency Refers to agreement of levels of memory with respect to a single processor and system memory for example on chip cache secondary cache and system memory Memory management unit MMU The functional unit that is capable of translating an effective logical address to a physical address providing protection mechanisms and defining caching methods Modified state MEI state M in which one and only one caching device has the valid data for that address The data at this address in external memory is not valid Most significant bit msb The highest order bit in an address registers data el
456. oint store instructions 2 35 A 21 integer load instructions 2 30 A 19 integer store instructions 2 31 A 19 load store multiple instructions 2 32 A 20 memory synchronization instructions 2 38 2 41 A 21 string instructions 2 33 A 20 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Load store unit execution timing 6 22 latency load and store instructions 6 31 Logical addresses translation into physical addresses 5 1 Iwarx stwex atomic memory references 3 20 support 8 41 M Machine check exception checkstop state 4 21 register settings 4 20 SRR1 bit settings 4 10 machine check exception enabled 4 20 MCP signal 7 24 MEI protocol definition MEI states 3 16 enforcing memory coherency 8 28 hardware considerations 3 17 Memory accesses 8 4 Memory coherency bit M bit cache interactions 3 10 I bit setting 3 12 M bit setting 3 12 timing considerations 6 23 Memory control instructions segment register manipulation 2 46 TLB management 2 46 user level cache 2 41 2 45 3 22 Memory management unit address translation flow 5 11 address translation mechanisms 5 7 5 11 block address translation 5 9 5 11 5 20 block diagram 5 5 5 7 direct address translation 3 11 5 9 5 11 5 19 exceptions 5 14 features summary 5 2 instructions and registers 5 17 memory protection 5 10 overview 1 11 1 30 pa
457. ol unit The system interface latches snoop addresses for snooping in the data cache and address register queues snoops for direct store reply operations and reservations controlled by the Load Word and Reserve Indexed Iwarx and Store Word Conditional Indexed stwex instructions and maintains the touch load address for the cache The interface allows one level of pipelining that is with certain restrictions discussed later there can be two outstanding transactions at any given time Accesses are prioritized with load operations preceding store operations Instructions are automatically fetched from the memory system into the instruction unit where they are dispatched to the execution units or forwarded to the branch processing unit at a peak rate of three instructions per clock see Section 6 3 Timing Considerations Conversely load and store instructions explicitly specify the movement of operands to and from the integer and floating point register files and the memory system When the MPC603e encounters an instruction or data access it calculates the logical address effective address in the architecture specification and uses the low order address bits to check for a hit in the on chip 16 Kbyte instruction and data caches During cache lookup the instruction and data memory management units MMUs use the higher order address bits to calculate the virtual address allowing them to calculate the physical address real address in th
458. ollowing e Whether the branch requires prediction e Whether the branch is predicted as taken or not taken e Whether the branch is taken e Whether the target instruction stream is in the on chip cache e Whether the prediction is correct 6 4 1 1 Branch Folding When a branch instruction is encountered by the fetcher the BPU immediately tries to pull that instruction out of the instruction stream and resolve it When the BPU removes the branch instruction from the stream the subsequent instruction is shifted down to take the place of the removed branch instruction This technique is called branch folding Often it eliminates the penalties of flow control instructions because instruction execution proceeds as though the branch were never there Chapter 6 Instruction Timing For More Information On This Product Go to www freescale com 3 Sekten Freescale Semiconductor Inc Execution Unit Timings If the folded branch instruction changes program flow the branch is said to be taken the BPU immediately requests the instructions at the new target from the on chip cache In most cases the new instructions arrive in the IQ before any bubbles are introduced into the execution units If the folded branch does not change program flow the branch is not taken the branch instruction is already removed and execution continues as if there were never a branch in the original sequence When a conditional branch cannot be resolved due to a CR d
459. om Machine State Register Instrucpons 2 39 Move To From Special Purpose Register Instructons 2 40 Implementation Specific SPR Encodings mfspr ceeeeeeeeeeeeeeeeeee 2 41 Segment Register Manipulation Instructions 00 0 0 cee eeeeeeeeesseceseeeeeeeeneees 2 42 Translation Lookaside Buffer Management Instructions 0 0 0 0 cesses 3 1 Combinations of W I and M Bits wo eeccccecccccsesseeescecceccessseeeesecceseeees 3 2 MEL State Definitions echte bereede engel 3 3 CSEL Signal Encoding s hinns oera reiege tie Denge At een 3 4 Memory Coherency Actions on Load Operations eeeseeeeeeeeereeeeseeree 3 5 Memory Coherency Actions on Store Operatons 3 6 Response to Bus Tramen 3 7 Bus Operations Caused by Cache Control Instructions WIM 001 3 8 MEI State EE 4 1 Exception Classifications ssseseeeseeseseseeressteeresresstsetesresseserestessersresreeseeseee 4 2 Exceptions Kern WEE 4 3 Exception Priorities si asi ege Ee Aaen 4 4 SRRI Bit Settings for Machine Check Exceptions 00 0 eeeeeseceseeeeeeeeeees 4 5 SRRI Bit Settings for Software Table Search Operations cee eee 4 6 MSR Bit Rettung sde geed AE Eed ege geg 4 7 IEEE Floating Point Exception Mode Bits 0 eee eeeeeeeceeeeeeneeesseenseeeeees 4 8 MSR Setting Due to Exceptioni sccisssssscsstacencntussaiassdszedsanscocasetebonedoasnscsenneeee 4 9 Settings Caused by Klara eee te eae Aer 4 10 Soft Reset Exception Register Settings ceeeeescceessec
460. ome hardware generated values to load TLB entries when TLB misses occur as described in Section 5 5 2 Implementation Specific Table Search Operation 5 5 1 Page Table Search Operation Conceptual Flow The table search process for a processor that implements the PowerPC architecture varies slightly for 64 and 32 bit implementations The main differences are the address ranges and PTE formats specified An outline of the page table search process performed by a 32 bit implementation is as follows 1 The 32 bit physical address of the primary PTEG is generated as described in Chapter 7 Memory Management in the Programming Environments Manual for 32 bit implementations 2 The first PTE PTEO in the primary PTEG is read from memory PTE reads should occur with an implied WIM memory cache mode control bit setting of Ob001 Therefore they are considered cacheable and burst in from memory and placed in the cache 3 The PTE in the selected PTEG is tested for a match with the virtual page number VPN of the access The VPN is the VSID concatenated with the page index field of the virtual address For a match to occur the following must be true PTE H 0 PTE V 1 PTE VSID VA 0 23 PTE API VA 24 29 Chapter 5 Memory Management For More Information On This Product Go to www freescale com TE Table Search Operathreeseale Semiconductor Inc Effective Address Generated 1 See Figure 5 6 Oth
461. ommended for new designs 1 1 Overview This section describes the details of the MPC603e provides a block diagram showing the major functional units see Figure 1 1 and briefly describes how these units interact Any differences between the PID6 603e and PID7t 603e implementations are noted The MPC603e is a low power implementation of this microprocessor family of reduced instruction set computing RISC microprocessors The MPC603e implements the 32 bit portion of the PowerPC architecture which defines 32 bit effective addresses integer data types of 8 16 and 32 bits and floating point data types of 32 and 64 bits The MPC603e is a superscalar processor that can issue and retire as many as three instructions per clock cycle Instructions can execute out of program order for increased performance however the MPC603e makes completion appear sequential The MPC603e integrates five execution units an integer unit IU a floating point unit FPU a branch processing unit BPU a load store unit LSU and a system register unit SRU The ability to execute five instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput for MPC603e based systems Most integer instructions execute in one clock cycle On the MPC603e the FPU is pipelined so a single precision multiply add instruction can be issued and completed every clock cycle Chapter 1 Overview For More Informatio
462. omments Assertion Negation May be asserted on any clock cycle when the MPC603e is driving or will be driving the data bus may remain asserted multiple cycles 7 2 8 Data Transfer Termination Signals Data termination signals are required after each data beat in a data transfer Note that in a single beat transaction the data termination signals also indicate the end of the tenure While in burst accesses the data termination signals apply to individual beats and indicate the end of the tenure only after the final data beat For a detailed description of how these signals interact see Section 8 4 4 Data Transfer Termination 7 2 8 1 Transfer Acknowledge TA Input Following are the state meaning and timing comments for the TA input State Meaning Asserted Indicates that a single beat data transfer completed successfully or that a data beat in a burst transfer completed successfully unless DRTRY is asserted on the next bus clock cycle Note that TA must be asserted for each data beat in a burst transaction and must be asserted during assertion of DRTRY For more information see Section 8 4 4 Data Transfer Termination Negated During DBB indicates that until TA is asserted the MPC603e must continue to drive the data for the current write or must wait to sample the data for reads Timing Comments Assertion Must not occur before AACK for the current transaction if the address retry mechanism is to b
463. on Implemented with IBAT and DBAT registers in BAT array Memory protection Architecturally defined Segments selectable as no execute Pages selectable as user supervisor and read only Blocks selectable as user supervisor and read only Page history Architecturally defined Referenced and changed bits defined and maintained Page address Architecturally defined Translations stored as PTEs in hashed page tables in memory translation Page table size determined by mask in SDR1 register MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MMU Features Table 5 1 MMU Features Summary continued Architecturally Defined Feature Category MPC603e Specific Feature TLBs Architecturally defined Instructions for maintaining optional TLBs bie instruction in MPC603e MPC603e specific 64 entry two way set associative ITLB 64 entry two way set associative DTLB Segment descriptors Architecturally defined Stored as segment registers on chip Page table search MPC603e specific Three MMU exceptions defined ITLB miss exception DTLB miss support on load exception and DTLB miss on store or C 0 exception MMU related bits set in SRR1 for these exceptions IMISS and DMISS registers missed effective address HASH1 and HASH2 registers PTEG addr ICMP and DCMP registers for comparing PTEs RPA re
464. on is typically comprised of an address tenure and one or more data tenures which may overlap or occur separately from the address tenure A transaction may be minimally comprised of an address tenure only Transfer termination Signal that refers to both signals that acknowledge the transfer of individual beats of both single beat transfer and individual beats of a burst transfer and to signals that mark the end of the tenure UISA user instruction set architecture The level of the architecture to which user level software should conform The UISA defines the base user level instruction set user level registers data types floating point memory conventions and exception model as seen by user programs and the memory and programming models Underflow A condition that occurs during arithmetic operations when the result cannot be represented accurately in the destination register For example underflow can happen if two floating point fractions are multiplied and the result requires a smaller exponent and or mantissa than the single precision format can provide In other words the result is too small to be represented accurately User mode The operating state of a processor used typically by application software In user mode software can access only certain control registers and can access only user memory space No privileged operations can be performed Also referred to as problem state MPC603e RISC Microprocessor User s M
465. on exceptions and to restore machine status when an rfi instruction is executed Machine status save restore register 1 SRR1 The SRR1 is used to save machine status on exceptions and to restore machine status when an rfi instruction is executed Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Register Set Implementation Note The MPC603e implements the KEY bit bit 12 in the SRR1 register to simplify the table search software For more information refer to Chapter 5 Memory Management Miscellaneous registers The time base facility TB for writing The TB is a 64 bit register pair that can be used to provide time of day or interval timing It consists of two 32 bit registers time base upper TBU and time base lower TBL The TB is incremented once every four clock cycles on the MPC603e Decrementer DEC The DEC register is a 32 bit decrementing counter that provides a mechanism for causing a decrementer exception after a programmable delay The DEC is decremented once every four bus clock cycles External access register EAR The EAR is a 32 bit register used in conjunction with the eciwx and ecowx instructions Although the PowerPC architecture specifies that EAR 26 31 are used to select a device the MPC603e implements only bits 28 31 Note that EAR and the eciwx and ecowx instructions are optional in the PowerPC archit
466. onal to Link Register belr bcirl BO BI 2 3 4 4 3 Condition Register Logical Instructions Condition register logical instructions shown in Table 2 29 and the Move Condition Register Field merf instruction are also defined as flow control instructions although they are executed by the system register unit SRU Most instructions executed by the SRU are completion serialized to maintain system state that is the instruction is held for execution in the SRU until all prior instructions issued have completed Table 2 29 Condition Register Logical Instructions Name Mnemonic Operand Syntax Condition Register AND crand crbD crbA crbB Condition Register AND with Complement crandc crbD crbA crbB Condition Register Equivalent creqv crbD crbA crbB Condition Register NAND crnand crbD crbA crbB Condition Register NOR crnor crbD crbA crbB Condition Register OR cror crbD crbA crbB Condition Register OR with Complement crorc crbD crbA crbB Condition Register XOR crxor crbD crbA crbB Move Condition Register Field merf crfD crfS Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary Note that if the LR update option is enabled for any of these instructions these forms of the instructions are invalid in the MPC603e 2 3 4 5 Trap Instructions The trap instructions shown in Table 2 30 are pro
467. onto the data bus out of order with respect to the address pipeline The write transaction concludes with the MPC603e negating DBB 4 The next qualified data bus grant signals the MPC603e to complete the outstanding read transaction by latching the data on the bus This assertion of DBG should not be accompanied by an asserted DBWO Any number of bus transactions by other bus masters can be attempted between any of these steps Note the following regarding DBWO e DBWO can be asserted if no data bus read is pending but it has no effect on write ordering e The ordering and presence of data bus writes is determined by the writes in the write queues at the time BG is asserted for the write address not DBG If a particular write is desired for example a cache line snoop push out operation then BG must be asserted after that particular write is in the queue and it must be the highest priority write in the queue at that time A cache line snoop push out operation may be the highest priority write but more than one may be queued e Because more than one write may be in the write queue when DBG is asserted for the write address more than one data bus write may be enveloped by a pending data bus read The arbiter must monitor bus operations and coordinate the various masters and slaves with respect to the use of the data bus when DBWO is used Individual DBG signals associated with each bus device should allow the arbiter
468. or doe Revision 1 to Revision 2 Table 2 2 HIDO Bit Functions continued Bit Name Function 4 BCLK CLK _OUT output enable and clock type selection Used in conjunction with HIDO ECLK and the HRESET signal to configure CLK_OUT See 5 EICE Enables in circuit emulator outputs for pipeline tracking See Section 7 2 11 Pipeline Tracking Support for more information 6 ECLK CLK_OUT output enable and clock type selection Used in conjunction with HIDO BCLK and the HRESET signal to configure CLK_OUT See 7 PAR Disable precharge of ARTRY 0 Precharge of ARTRY enabled 1 Alters bus protocol slightly by preventing the processor from driving ARTRY to high negated state If this is done the system must restore the signals to the high state 8 DOZE Doze mode enable Operates in conjunction with MSR POW 0 Doze mode disabled 1 Doze mode enabled Doze mode is invoked by setting MSR POW while this bit is set In doze mode the PLL time base and snooping remain active 9 NAP Nap mode enable Operates in conjunction with MSR POW 0 Nap mode disabled 1 Nap mode enabled Doze mode is invoked by setting MSR POW while this bit is set In nap mode the PLL and the time base remain active 10 SLEEP Sleep mode enable Operates in conjunction with MSR POW 0 Sleep mode disabled 1 Sleep mode enabled Sleep mode is invoked by setting MSR POW while this bit is set QREQ
469. or User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction latency The total number of clock cycles necessary to execute an instruction and make ready the results of that instruction Interrupt An external signal that causes the MPC603e to suspend current execution and take a predefined exception Key bits A set of key bits referred to as Ks and Kp in each segment register and each BAT register The key bits determine whether supervisor or user programs can access a page within that segment or block Kill An operation that causes a cache block to be invalidated without writing any modified data to memory Latency The number of clock cycles necessary to execute an instruction and make ready the results of that execution for a subsequent instruction L2 cache See Secondary cache Least significant bit Isb The bit of least value in an address register field data element or instruction encoding Least significant byte LSB The byte of least value in an address register data element or instruction encoding Little endian A byte ordering method in memory where the address n of a word corresponds to the least significant byte In an addressed memory word the bytes are ordered left to right 3 2 1 0 with 3 being the most significant byte See Big endian Mantissa The decimal part of logarithm MEI modified exclusive invalid Cache c
470. or a branch LK 1 to complete e A be based on CR waiting for resolution due to a CR dependency followed by a be based on CR Fetching is stopped and the second branch waits for the first CR dependency to be resolved Note Branch conditions can be a function of the CTR and CR if the CTR condition is sufficient to resolve the branch then a CR dependency is ignored 6 4 1 2 Static Branch Prediction Static branch prediction allows software for example compilers to give a hint to the machine hardware about the direction the branch is likely to take When a branch instruction encounters a data dependency the BPU waits for the required condition code to MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc hee Execution Unit Timings become available Rather than stalling instruction dispatch until the source operand is ready the MPC603e predicts the likely path and instructions are fetched and executed along that path When the branch operand becomes available the branch is evaluated If the prediction is correct program flow continues along that path uninterrupted otherwise the processor backs up and program flow resumes along the correct path If the target address of the branch link or count register is modified by an instruction that appears before the branch instruction the BPU waits until the target address is available The MPC603e
471. ormation On This Product Go to www freescale com ebe Freescale Semiconductor Inc Exception Definitions Table 4 9 Settings Caused by Hard Reset continued Register Setting Register Setting XER 00000000 IABR All Os TBU 00000000 DSISR 00000000 TBL 00000000 DAR 00000000 LR 00000000 DEC FFFFFFFF CTR 00000000 HASH1 00000000 SDR1 00000000 HASH2 00000000 SRRO 00000000 TLBs Unknown SRR1 00000000 Cache All cache blocks invalidated SPRGs 00000000 BATs Unknown Tag directory All Os However LRU bits are initialized so each side of the cache has a unique LRU value The HRESET signal can be asserted for the following reasons e System power on reset e System reset from a panel switch For information on the HRESET signal see Section 7 2 9 6 1 Hard Reset HRESET Input The following is also true after a hard reset operation e External checkstops are enabled e The on chip test interface has given control of the I Os to the rest of the chip for functional use e Since the reset exception has data and instruction translation disabled MSR DR and MSR IR both cleared the chip operates in real addressing mode as described in Section 5 2 Real Addressing Mode 4 5 1 2 Soft Reset As described in Section 4 1 2 Summary of Front End Exception Handling the soft reset exception is a type of system reset exception that is recoverable nonmaskable and asynchronous
472. orwarding data to the processor see Figure 8 11 Thus a data beat can be terminated by a predicted branch with TA and then one bus clock cycle later confirmed with the negation of DRTRY The DRTRY signal is valid only for read transactions TA must be asserted on the bus clock cycle before the first bus clock cycle of the assertion of DRTRY otherwise the results are undefined The DRTRY signal extends data bus mastership such that other processors cannot use the data bus until DRTRY is negated Therefore in the example shown in Figure 8 11 DBB cannot be asserted until bus clock cycle 5 This is true for both read and write operations even though DRTRY does not extend bus mastership for write operations MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Bus Tenure 1 2 Il 3 4 5 Bus Clock mL TNH TEA EN Figure 8 11 Termination with DRTRY Figure 8 12 shows the effect of using DRTRY during a burst read It also shows the effect of using TA to pace the data transfer rate Notice that in bus clock cycle 3 of Figure 8 12 TA is negated for the second data beat The MPC603e data pipeline does not proceed until bus clock cycle 4 when TA is reasserted Note that DRTRY is useful for systems that implement predicted forwarding of data such as those with direct mapped second level caches where hit miss is determined on
473. ot another load for example an instruction fetch A 0 31 TT 0 4 TBST GBL AACK ARTRY DBB D 0 63 DRTRY TEA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CPUA CPU A CPU A Figure 8 16 Single Beat Reads Showing Data Delay Controls Chapter 8 System Interface Operation For More information On This Product Go to www freescale com D Freescale Semiconductor Inc Timing Examples Figure 8 17 shows data delay controls in a single beat write operation Note that all bidirectional signals are three stated between bus tenures Data transfers are delayed in the following ways e The TA signal is held negated to insert wait states in clocks 3 and 4 e Inclock 6 DBG is held negated delaying the start of the data tenure The last access is not delayed DRTRY is valid only for read operations A 0 31 TT 0 4 TBST TEA Figure 8 17 Single Beat Writes Showing Data Delay Controls MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Get Timing Examples Figure 8 18 shows the use of data delay controls with burst transfers Note that all bidirectional signals are three stated between bus tenures Note the following e The first data beat of bursted read data clock 0 is the critical quad word e The write burst shows the use of TA signal
474. ot write through Timing Comments Assertion Negation The same as A 0 31 High Impedance The same as A 0 31 7 2 4 7 Global GBL The GBL signal is an input output signal on the MPC603e 7 2 4 7 1 Global GBL Output Following are the state meaning and timing comments for the GBL output State Meaning Asserted Indicates that a transaction is global reflecting the setting of the M bit for the block or page that contains the address of the current transaction except in the case of copy back operations and instruction fetches which are nonglobal Negated Indicates that a transaction is not global Timing Comments Assertion Negation The same as A 0 31 High Impedance The same as A 0 31 7 2 4 7 2 Global GBL Input Following are the state meaning and timing comments for the GBL input State Meaning Asserted Indicates that a transaction must be snooped by the MPC603e Negated Indicates that a transaction is not snooped by the MPC603e Timing Comments Assertion Negation The same as A 0 31 7 2 4 8 Cache Set Entry CSE 0 1 Output Following are the state meaning and timing comments for the CSE 0 1 outputs State Meaning Asserted Negated Represents the cache replacement set element for the current transaction reloading into or writing out of the cache Can be used with the address bus and the transfer attribute signals to externally track the state of each cache line in the MPC603e cache M
475. ouch load address with subsequent load requests from the data cache If the load address matches the touch load address in the BIU the data is forwarded to the data cache from the touch load buffer the read from memory is canceled and the touch load address buffer is invalidated To avoid the storage of stale data in the touch load buffer touch load requests that are mapped as write through or caching inhibited by the MMU are treated as no ops by the BIU Also subsequent load instructions after a touch load that are mapped as write through or caching inhibited do not hit in the touch load buffer and cause the touch load buffer to be invalidated on a matching address While the MPC603e provides only a single cache block buffer other microprocessor implementations may provide buffering for more than one cache block Programs written for other implementations may issue several debt or dcbtst instructions sequentially reducing the performance if executed on the MPC603e To improve performance in these situations HIDO NOOPT T bit 31 can be set This causes the debt and debtst instructions to be treated as no ops cause no bus activity and incur only one processor clock cycle of execution latency NOOPTI is cleared at a power on reset enabling the use of the debt and dcbtst instructions 3 3 Basic Data Cache Operations This section describes the three types of operations that can occur to the data cache and how these operations are implemen
476. output signal CKSTP_OUT The following events will cause the MPC603e to enter the checkstop state e Machine check exception occurs with MSR ME cleared e External checkstop input CKSTP_IN is asserted MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc utes Exception Definitions When a processor is in the checkstop state instruction processing is suspended and generally cannot be restarted without resetting the processor The contents of all latches are frozen within two cycles upon entering the checkstop state so that the state of the processor can be analyzed as an aid in problem determination Note that not all processors that implement the PowerPC architecture provide the same level of error checking The reasons a processor can enter checkstop state are implementation dependent 4 5 3 DSI Exception 0x00300 A DSI exception occurs when no higher priority exception exists and a data memory access cannot be performed The condition that caused the DSI exception can be determined by reading the DSISR register a supervisor level SPR SPR18 that can be read by using the mfspr instruction Bit settings are provided in Table 4 12 Table 4 12 also indicates the memory element that is saved to the DAR Table 4 12 DSI Exception Register Settings Register Setting Description SRRO Set to the effective address of the instruction t
477. overable or may provide a limited degree of recoverability All exceptions report recoverability through the MSR RI bit The MPC603e exception classes are shown in Table 4 1 Table 4 1 Exception Classifications Synchronous Asynchronous Precise Imprecise Exception Type Asynchronous nonmaskable Imprecise Machine check System reset Asynchronous maskable Precise External interrupt Decrementer System management interrupt Synchronous Precise Instruction caused exceptions Table 4 1 define categories of exceptions that the MPC603e handles uniquely Note that Table 4 1 includes no synchronous imprecise exceptions While the PowerPC architecture supports imprecise handling of floating point exceptions the MPC603e implements floating point exception modes as precise exceptions Although the PowerPC architecture specifies that the recognition of the machine check exception is nonmaskable on the MPC603e the stimuli that cause this exception are maskable For example the machine check exception is caused by the assertion of TEA APE DPE or MCP However MCP APE and DPE can be disabled by bits 0 2 and 3 respectively in HIDO Therefore the machine check caused by asserting TEA is the only truly nonmaskable machine check exception The MPC603e exceptions and conditions that cause them are listed in Table 4 2 Exceptions that are specific to either the PID6 603e or PID7t 603e are also noted in Table 4 2
478. p cmpl cntlzdx 1 entlzwx dcbf debi 2 dcbst debt dcbist dcbz eciwx ecowx eieio eqvx extsbx extshx extswx fabsx fcfidx Table A 36 X Form continued Freescale Semiconductor Inc Instructions Sorted by Form 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 OPCD S A SH XO Rc OPCD crfD OIL A B XO 0 OPCD crfD 00 A B XO 0 OPCD crfD 00 crfS 00 00000 XO 0 OPCD crfD 00 00000 00000 XO 0 OPCD crfD 00 00000 IMM XO Re OPCD TO A B XO 0 OPCD D 00000 B XO Re OPCD D 00000 00000 XO Re OPCD crbD 00000 00000 XO Re OPCD 00000 A B XO 0 OPCD 00000 00000 B XO 0 OPCD 00000 00000 00000 XO 0 Specific Instructions 31 A B 28 Re 31 A B 60 Re 31 crfD OIL A B 0 0 31 crfD OIL A B 32 0 31 S A 00000 58 Re 31 S A 00000 26 Rc 31 00000 A B 86 0 31 00000 A B 470 0 31 00000 A B 54 0 31 00000 A B 278 0 31 00000 A B 246 0 31 00000 A B 1014 0 31 D A B 310 0 31 S A B 438 0 31 00000 00000 00000 854 0 31 A B 284 Re 31 S A 00000 954 Rc 31 S A 00000 922 Rc 31 S A 00000 986 Re 63 D 00000 B 264 Rc 63 D 00000 B 846 Rc MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Name Tempo fempu fetidx fetidzx fctiwx fctiwzx fmrx fnabsx fnegx frspx icbi Ibzux Ibzx Idarx Idux Idx Ifdux Hds lfsux lfsx
479. p bus snooping logic Since the MPC603e data cache tags are single ported a simultaneous load or store and snoop access represent a resource contention The snoop access is given first access to the tags Load or store operations can be performed to the cache on the clock cycle immediately following a snoop access if the Chapter 3 Instruction and Data Cache Operation For More Information On This Product Go to www freescale com Freescale Semiconductor Inc snoop misses snoop hits may block the data cache for two or more cycles depending on whether a copy back to main memory is required The instruction cache also consists of 128 sets of 4 blocks and each block consists of 32 bytes an address tag and a valid bit The instruction cache is only written as a result of a block fill operation on a cache miss In the PID7t 603e the instruction cache is blocked only until the critical load completes The PID7t 603e supports instruction fetching from other instruction cache lines following the forwarding of the critical first double word of a cache line load operation Successive instruction fetches from the cache line being loaded are forwarded and accesses to other instruction cache lines can proceed during the cache line load operation The instruction cache is not snooped and cache coherency must be maintained by software A fast hardware invalidation capability is provided to support cache maintenance The load store unit provides the d
480. ped transaction is a caching inhibited read and the block in the cache is in the exclusive state the snoop causes no bus activity and the block remains in the exclusive state If the block is in the cache in the modified state the MPC603e initiates a push of the modified block out to memory and marks the cache block as exclusive Read atomic operations appear on the bus in response to Iwarx instructions and generate the same snooping responses as read operations Read with intent to modify RWITM RWITM atomic A RWITM operation is issued to acquire exclusive use of a memory location for the purpose of modifying it e If the addressed block is invalid the MPC603e takes no action e If the addressed block in the cache is in the exclusive state the MPC603e initiates an additional snoop action to change the state of the cache block to invalid e f the addressed block in the cache is in the modified state the block is flushed to memory and the block is invalidated The RWITM atomic operations appear on the bus in response to stwex instructions and are snooped like RWITM instructions sync No action is taken TLB invalidate No action is taken 3 6 8 Operations Causing ARTRY Assertion The following scenarios cause the MPC603e to assert the ARTRY signal e Snoop hits to a block in the M state flush or clean This case is a normal snoop hit and will result in ARTRY being asserted if the snooped transaction
481. pending Chapter 8 System Interface Operation For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Address Bus Tenure Bus Clock need bus E SN wall qual_bg i oe ABB Figure 8 3 Address Bus Arbitration 1 0 1 Bus Clock need_bus BR SH Al Sb ABB Figure 8 4 Address Bus Arbitration Showing Bus Parking MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Address Bus Tenure Typically bus parking is provided to the device that was the most recent bus master However system designers may choose other schemes such as providing unrequested bus grants in situations where it is easy to correctly predict the next device requesting bus mastership When the MPC603e receives a qualified bus grant it assumes address bus mastership by asserting ABB and negating BR Meanwhile the MPC603e drives the address for the requested access onto the address bus and asserts TS to indicate the start of a new transaction When designing external bus arbitration logic note that the MPC603e may assert BR without using the bus after it receives the qualified bus grant For example in a system using bus snooping if the MPC603e asserts BR to perform a replacement copy back operation another device can invalidate that line before the MPC603e is granted mastership
482. pending The exception is taken when a recoverable state is reached Instruction fetch ITLB ISI When this type of exception is detected dispatch is halted and the current instruction stream is allowed to drain If completing any instructions in this stream causes an exception that exception is taken and the instruction fetch exception is forgotten Otherwise as soon as the machine is empty and a recoverable state is reached the instruction fetch exception is taken Instruction dispatch execution program DSI alignment emulation trap system call DTLB miss on load or store IABR This type of exception is determined at dispatch or execution of an instruction The exception remains pending until all instructions in program order before the exception causing instruction are MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Exception Processing completed The exception is then taken without completing the exception causing instruction If any other exception condition is created in completing these previous instructions in the machine that exception takes priority over the pending instruction dispatch execution exception which will then be forgotten e Post instruction execution trace This type of exception is generated following execution and completion of an instruction while a trace mode is enabled If executing the instruction pr
483. perand length is implicit for each instruction The PowerPC architecture supports both big endian and little endian byte ordering The default byte and bit ordering is big endian See Byte Ordering in Chapter 3 Operand Conventions in the Programming Environments Manual for more information about big endian and little endian byte ordering Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary The operand of a single register memory access instruction has a natural alignment boundary equal to the operand length In other words the natural address of an operand is an integral multiple of the operand length A memory operand is said to be aligned if it is aligned at its natural boundary otherwise it is misaligned For a detailed discussion about memory operands see Chapter 3 Operand Conventions in the Programming Environments Manual 2 3 2 0 Effective Address Calculation An effective address EA is the 32 bit sum computed by the processor when executing a memory access or branch instruction or when fetching the next sequential instruction For a memory access instruction if the sum of the effective address and the operand length exceeds the maximum effective address the memory operand is considered to wrap around from the maximum effective address through effective address 0 as described in the following paragraphs Ef
484. peration of the Instruction and Data Caches The MPC603e provides independent instruction and data caches Each cache is a physically addressed 16 Kbyte cache with four way set associativity Both caches consist of 128 sets of four 8 word cache lines Because the on chip data cache is a write back primary cache the predominant type of transaction is burst read memory operations followed by burst write memory operations and single beat noncacheable or write through memory read and write operations Additionally there can be address only operations variants of the burst and single beat operations such as global memory operations that are snooped and atomic memory operations and address retry activity such as when a snooped read access hits a modified line in the cache Because the MPC603e data cache tags are single ported simultaneous load or store and snoop accesses cause resource contention Snoop accesses have the highest priority and are given first access to the tags unless the snoop access coincides with a tag write In this case the snoop is retried and must re arbitrate for cache access Loads or stores deferred due to snoop accesses are performed on the clock cycle following the snoop The MPC603e supports a three state coherency protocol that implements the modified exclusive and invalid MEI cache states The protocol is a subset of the MESI modified exclusive shared invalid four state protocol and operates coherently in
485. ple address or data beats Biased exponent An exponent whose range of values is shifted by a constant bias Typically a bias is provided to allow a range of positive values to express a range that includes both positive and negative values Big endian A byte ordering method in memory where the address n of a word corresponds to the most significant byte In an addressed Glossary of Terms and Abbreviations For More Information On This Product Go to www freescale com Freescale Semiconductor Inc memory word the bytes are ordered left to right 0 1 2 3 with O being the most significant byte See Little endian Block An area of memory that ranges from 128 Kbytes to 256 Mbytes whose size translation and protection attributes are controlled by the BAT mechanism Boundedly undefined A characteristic of certain operation results that are not rigidly prescribed by the PowerPC architecture Boundedly undefined results for a given operation may vary among implementations and between execution attempts in the same implementation Although the architecture does not prescribe the exact behavior for when results are allowed to be boundedly undefined the results of executing instructions in contexts where results are allowed to be boundedly undefined are constrained to ones that could have been achieved by executing an arbitrary sequence of defined instructions in valid form starting in the state the machine was in before atte
486. predicted instructions on the mispredicted path and any results of speculative execution are purged from the pipeline and fetching continues from the nonpredicted path e Completion Completion occurs when an instruction has finished executing written back any results and is removed from the completion queue CQ When an instruction completes it is guaranteed that this instruction and all previous instructions can cause no exceptions e Fall through branch fall through A not taken branch On the MPC603e fall through branch instructions are removed from the instruction stream at dispatch That is these instructions are allowed to fall through the instruction queue through Chapter 6 Instruction Timing For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Terminology and Conventions the dispatch mechanism without either being passed to an execution unit and or given a position in the CQ e Fetch The process of bringing instructions from memory such as a cache or system memory into the instruction queue e Finish Finishing occurs in the last cycle of execution In this cycle the CQ entry is updated to indicate that the instruction has finished executing e Folding branch folding The replacement of a branch instruction with target instructions and any instructions along the not taken path when a branch is either taken or predicted as taken e Latency The number of clock
487. processor appear to have completed before the FPSCR instruction is initiated and that no subsequent floating point instructions appear to be initiated by the given processor until the FPSCR instruction has completed The FPSCR instructions are listed in Table 2 19 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Gastruction Set Summary Table 2 19 Floating Point Status and Control Register Instructions Name Mnemonic Operand Syntax Move from FPSCR mffs mffs frD Move to Condition Register from FPSCR merfs crfD crfS Move to FPSCR Bit 0 mtfsb0 mtfsb0 crbD Move to FPSCR Bit 1 mtfsb1 mtfsb1 crbD Move to FPSCR Field Immediate mifsfi mtfsfi crfD IMM Move to FPSCR Fields mifsf mtfsf FM frB Implementation Note The architecture notes that in some implementations the Move to FPSCR Fields mtfsfx instruction may perform more slowly when only a portion of the fields are updated as opposed to all of the fields This is not the case in the MPC603e 2 3 4 2 6 Floating Point Move Instructions Floating point move instructions copy data from one floating point register to another The floating point move instructions do not modify the FPSCR The CR update option in these instructions controls the placing of result status into CR1 Floating point move instructions are listed in Table 2 20 Table 2 20 Float
488. protection violation exceptions is very similar to that of page fault conditions as shown in Figure 5 17 except that different bits in SRR1 and DSISR are set Setup for Protection Violation Exceptions Data TLB Miss Handlers Instruction TLB Instruction Access to Miss Handler Data Access Guarded Memory ee DSISR 6 SRR1 15 Memory C 0 Clear Upper Bits of SRR1 Clear Upper Bits of SRR1 SRR1 SRR1 AND OxFFFF SRR1 lt SRR1 AND OxFFFF DSISR 4 lt 1 SRR1 4 lt 1 dtemp DMISS Restore CRO Bits MSR TGPR 0 SRR1 31 1 Little Endian Mode dtemp dtemp XOR 0x07 Branch to ISI Exception Handler Otherwise DAR lt dtemp Restore CRO Bits MSR TGPR lt 0 Branch to DSI Exception Handler Figure 5 18 Setup for Protection Violation Exceptions 5 5 2 2 2 Code for Example Exception Handlers This section provides assembly language examples that implement the flow diagrams described above Note that although these routines fit into a few cache lines they are supplied only as functional examples they could be further optimized for faster performance TLB software load for MPC603e New Instructions tlbld write the dtlb with the pte in rpa reg MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Mes able BCEE j tlbli New SPRS dmiss imiss hashl hash2 j icmp dcmp
489. ps 7 2 1 1 Bus Request BR Output The BR signal is an output signal on the MPC603e Following are the state meaning and timing comments for the BR output State Meaning Asserted Indicates that the MPC603e is requesting mastership of the address bus Note that BR may be asserted for one or more cycles and then negated due to an internal cancellation of the bus request such as a load hit in the touch load buffer See Section 8 3 1 Address Bus Arbitration Negated Indicates that the MPC603e is not requesting the address bus The MPC603e may have no bus operation pending it may be Chapter 7 Signal Descriptions For More Information On This Product Go to www freescale com ae Freescale Semiconductor Inc Signal Descriptions parked or the ARTRY input was asserted on the previous bus clock cycle Timing Comments Assertion Occurs when the MPC603e is not parked and a bus transaction is needed This may occur even if the two possible pipeline accesses have occurred BR is also asserted for one cycle during the execution of a debz instruction and during the execution of a load instruction that hits in the touch load buffer Negation Occurs for at least one bus clock cycle after an accepted qualified bus grant see BG and ABB even if another transaction is pending It is also negated for at least one bus clock cycle when the assertion of ARTRY is detected on the bus 7 2 1 2 Bus Grant BG Input The BG
490. r Inc F Revision Changes From narsescale Se 2 1 1 2 4 2 1 1 2 5 Add the following text after the first paragraph of the sub bullet for Floating point registers FPRs Before the stfd instruction is used to store the contents of an FPR to memory the FPR must have been initialized after reset explicitly loaded with any value by using a floating point load instruction Replace Table 2 1 with the following Table 2 1 MSR POW and MSR TGPR Bits Bit Name Description 13 POW Power management enable 603e specific 0 Disables programmable power modes normal operation mode 1 Enables programmable power modes nap doze or sleep mode This bit controls the programmable power modes only it has no effect on dynamic power management DPM MSR POW may be altered with an mtmsr instruction only Also when altering the POW bit software may alter only this bit in the MSR and no others The mtmsr instruction must be followed by a context synchronizing instruction See Chapter 9 Power Management for more information on power management TGPR Temporary GPR remapping 603e specific 0 Normal operation 1 TGPR mode GPRO GPR3 are remapped to TGPRO TGPR3 for use by TLB miss routines The contents of GPRO GPR3 remain unchanged while MSR TGPR 1 Attempts to use GPR4 GPR31 with MSR TGPR 1 yield undefined results When this bit is set all instruction accesses to GPRO GPR3 are mapped
491. r qualification assume mastership of the data bus A qualified data bus grant occurs when DBG is asserted while DBB DRTRY and ARTRY are negated Chapter 8 System Interface Operation For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Access Protocol DBB is driven by the current bus master DRTRY is driven only from the bus and ARTRY is driven from the bus but only for the address tenure associated with the current data tenure that is not from another address tenure e DBWO data bus write only Assertion indicates that the MPC603e may perform the data bus tenure for an outstanding write address even if a read address is pipelined before the write address If DBWO is asserted the MPC603e assumes data bus mastership for a pending data bus write operation the MPC603e takes the data bus for a pending read operation if this input is asserted along with DBG and no write is pending Care must be taken with DBWO to ensure the desired write is queued for example a cache line snoop push out operation e DBB data bus busy Assertion by the MPC603e indicates that the MPC603e is the data bus master The MPC603e always assumes data bus mastership if it needs the bus and is given a qualified data bus grant see DBG For more detailed information on the arbitration signals refer to Section 7 2 1 Address Bus Arbitration Signals and Section 7 2 6 Data
492. r LRU 0 Replace TLB associativity set 0 1 Replace TLB associativity set 1 15 S L Store or load data access 0 Data TLB miss on load 1 Data TLB miss on store or C 0 16 31 Loaded from MSR 16 31 MSR POW 0 EE 0 FEO 0 IR 0 TGPR 1 PR 0 SE 0 DR 0 ILE FP 0 BE 0 RI 0 IP ME FEI 0 LE Set to value of ILE Software table search operations are discussed in Chapter 5 Memory Management When a data TLB miss on load exception is taken instruction execution for the handler begins at offset 0x01100 from the physical base address indicated by MSR IP Chapter 4 Exceptions For More Information On This Product Go to www freescale com BS Freescale Semiconductor Inc Exception Definitions 4 5 14 Data TLB Miss on Store Exception 0x01200 When the effective address for a data store or cache operation cannot be translated by the DTLB a data TLB miss on store exception is generated The data TLB miss on store exception is also taken when the changed bit C 0 for a DTLB entry needs to be updated for a store operation Register settings for the instruction and data TLB miss exceptions are described in Table 4 17 If a data TLB miss exception handler fails to find the desired PTE then a page fault must be synthesized The handler must restore the machine state and clear MSR TGPR before invoking the DSI exception 0x00300 Software table search operations are discussed in Chapter 5 Memory Manag
493. r More Information On This Product Go to www freescale com Page Number Table Number i ii iii 1 1 1 2 1 3 1 4 1 5 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 20 2 21 2 22 2 23 2 24 2 25 2 26 2 27 2 28 Freescale Semiconductor Inc Tables Acronyms and Abbreviated Terms Terminology Conventions E Instruction Field Conventions enee dee dee God BA LR Generated SRRI KEY Bu Additional Changed HIDO Rate eseu deet Seege EEN ek eut EE Exceptions and Conditions icissiiassciscvacesdansdesandecsasves soaceassaceneslecddaatsdsecetoss MSR POW and MSR TGPR Ps 0 eeeeeeceeeecceeeeesceeeeceetenceneres HIDO Bit et aena eau eee ieee le ee asec HIDO BCLK and HIDO ECLK CLK_OUT Configuration 000 HIDI Meet DCMP and ICMP Bit Setungs ccc cccsstecsdsasscoasseiesnacceasacctennesvecnaavesaceesetecers HASH 1 and HASH2 Bit Settings 0 0 eccccseceecssececesecesssecesseeeeesseeeees RPA Bit SOUS ee eege Eege Eege Instruction Address Breakpoint Register Bit Settmnge eee Meio HEES Integer Arithmetic Instructions cc eeceeeeesscecseceseeeeeeeeseecsaeceeenseeeenees Integer Compare Instructions ici eat cold EA Integer Logical Instructions eege Integer Rotate usteet Bate i Geta ee eae Integer Shift Instr cows eege Age gege Soe cece odes Floating Point Arithmetic Instructions 00 ee eeeeeeeseeeseeceeceseeeeeeeeneees Floating Point Multiply Add Instructions 00
494. r or not the PTE is a match Upon execution of a tlbld or tlbli instruction the contents of the DCMP or ICMP register is loaded into the first word of the selected TLB entry V VSID H API O 1 24 25 26 31 Figure 5 12 DCMP and ICMP Registers Table 5 11 describes the bit settings for the DCMP and ICMP registers Table 5 11 DCMP and ICMP Bit Settings Bits Name Description 0 V Valid bit Set by the processor on a TLB miss exception 1 24 VSID Virtual segment ID Copied from VSID field of corresponding segment register 25 H Hash function identifier Cleared by the processor on a TLB miss exception 26 31 API Abbreviated page index Copied from API of effective address 5 5 2 1 3 Primary and Secondary Hash Address Registers HASH1 and HASH2 HASH1 and HASH contain the physical addresses of the primary and secondary PTEGs for the access that caused the TLB miss exception Only bits 7 25 differ between them For convenience the processor automatically constructs the full physical address by routing bits 0 6 of SDR1 into HASH1 and HASH2 and clearing the lower six bits These registers are read only and are constructed from the contents of the DMISS or IMISS register The format for HASH1 and HASH2 is shown in Figure 5 13 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Mes able EE
495. r other write transaction if pending in the MPC603e write queues between the address and data tenures of a read operation through the use of DBWO This effectively envelopes the write operation within the read operation Figure 8 22 shows how DBWO is used to perform an enveloped write transaction Read Address Write Address 1 2 BG We je _ ABB IT IT AACK TLF TI Write Data Read Data 2 1 DG LIT DBB E DBWO LI Figure 8 22 DBWO Transaction Enveloped Write Transaction Note that although the MPC603e can pipeline any write transaction behind the read transaction special care should be used when using the enveloped write feature It is envisioned that most system implementations will not need this capability for these Chapter 8 System Interface Operation For More Information On This Product Go to www freescale com Using DBWO Freescale Semiconductor Inc applications DBWO should remain negated In systems where this capability is needed DBWO should be asserted under the following scenario 1 The MPC603e initiates a read transaction either single beat or burst by completing the read address tenure with no address retry 2 Then the MPC603e initiates a write transaction by completing the write address tenure with no address retry 3 At this point if DBWO is asserted with a qualified data bus grant to the MPC603e the MPC603e asserts DBB and drives the write data
496. r store instruction to access guard memory The target memory is cache inhibited I 1 the load or store instruction is in the execution path and it is guaranteed that no prior instructions can cause an exception The parenthetical clause in the second sentence of the first bullet should be that is all enabled floating point exceptions are always precise on the 603e Figure 4 1 should be re labeled as Table 4 1 At the end of the first sentence in the description of the floating point unavailable exception change when the floating point available bit is disabled to when the floating point available bit is cleared Also change Note that the EC603e microprocessor execution of a floating point to Note that the EC603e microprocessor execution of any floating point Also the description for instruction translation miss should change from miss exception is caused when an effective address for an to miss exception is caused when the effective address for an The descriptions for Data load translation miss and Data store translation miss should change from miss exception is caused when an effective address for a to miss exception is caused when the effective address for a In Table 4 5 change the description of the FP bit from The processor prevents dispatch of floating point instructions including floating point
497. r that matches the format of the lower word of the PTE e TLB access instructions tlbli and tlbld that are used to load an address translation into the instruction or data TLBs e Shadow registers for GPRO GPR3 that allow miss code to execute without corrupting the state of any of the existing GPRs Shadow registers are used only for servicing a TLB miss See Section 1 3 5 2 Implementation Specific Memory Management for more information about memory management for the MPC603e 1 1 5 2 Cache Units The MPC603e provides independent 16 Kbyte four way set associative instruction and data caches The cache block is 32 bytes long The caches adhere to a write back policy but the MPC603e allows control of cacheability write policy and memory coherency at the page and block levels The caches use an LRU replacement policy MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc i Overview As shown in Figure 1 1 the caches provide a 64 bit interface to the instruction fetch unit and LSU The surrounding logic selects organizes and forwards the requested information to the requesting unit Write operations to the cache can be performed on a byte basis and a complete read modify write operation to the cache can occur in each cycle The load store and instruction fetch units provide the caches with the address of the data or instruction to be fetch
498. r the forwarding of data to the internal CPU immediately when TA is recognized When the MPC603e is in no DRTRY mode data can no longer be canceled the cycle after it is acknowledged by an assertion of TA Data is immediately forwarded to the processor core and any attempt at late cancellation by the system may cause improper operation by the MPC603e When the MPC603e is following normal bus protocol data may be canceled the bus cycle after TA by either of two means late cancellation by DRTRY or late cancellation by ARTRY When no DRTRY mode is selected both cancellation cases must be disallowed in the system design for the bus protocol When no DRTRY mode is selected the system must ensure that DRTRY is not asserted to the MPC603e which may cause improper operation of the bus interface The system must also ensure that an assertion of ARTRY by a snooping device must occur before or coincident with the first assertion of TA to the MPC603e but not on the cycle after the first assertion of TA Other than the inability to cancel data that was read by the master on the bus cycle after TA was asserted the bus protocol for the MPC603e is identical to that for the basic transfer bus protocols described in this chapter as well as for 32 bit data bus mode The MPC603e selects the desired DRTRY mode at startup by sampling the state of the DRTRY signal itself at the negation of HRESET If DRTRY is negated at the negation of HRESET no
499. r31 pvr pvr reg srawi r31 31 T resetTest603 cmpi Or AE eh bne cr0 endHIDSetup addi CD CD O oris ro r0 0x8000 enable machine check pin EMCP oris r0 r0 0x0010 enable dynamic power mgmt DPM oris CD r0 0x0020 enable SLEEP power mode ori ro r0 0x8000 enable the Icache ICE ori ro r0 0x4000 enable the Dcache DCE ori ro r0 0x0800 invalidate Icache ICFI ori r0 r0 0x0400 invalidate Dcache DCFI mtspr Hidr isync EK eK A A A Ke then when the processor is in a loop force an SMI interrupt MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconduc or ne Processor Sleep Mode HE I A I AA I AA AAA A I A I I He orig 0x00001400 force big endian mode stw stw mfmsr ori ori ori xori ori mtmsr ori isync ori r0 0x05f8 r0 System Management Interrupt r0 0x05fc r0 ro r0 r0 xr0 need nop every second inst r0 r0 0x0001 force big endian LE bit r0 r0 xr0 r0 r0 0x0001 force big endian LE bit r0 r0 xr0 ro r0 r0 xr0 r0 r0 xr0 save off additional registers to be corrupted stw mfspr stw mfspr stw s m s r20 0x05f4 r21 ep r21 0x05f0 r227 srrl r22 0x05ec r23 0x05e8 r23 r23 0x05e4 r0 r0 xr0 ro put siro in r2l ro put r21 in 0x05f0 put srrl in r22 ro put r22 in 0x05ec ro ro HE I AA I AA I AA A I A I A I I He
500. rD as undefined when executing the Floating Convert to Integer Word fctiw and Floating Convert to Integer Word with Round toward Zero fetiwz instructions Examples of uses of these instructions to perform various conversions can be found in Appendix D Floating Point Models in the Programming Environments Manual The floating point rounding instructions are shown in Table 2 17 Table 2 17 Floating Point Rounding and Conversion Instructions Name Mnemonic Operand Syntax Floating Convert to Integer Word fctiw fctiw frD frB Floating Convert to Integer Word with Round Toward Zero fetiwz fctiwz frD frB Floating Round to Single Precision frsp frsp frD frB 2 3 4 2 4 Floating Point Compare Instructions Floating point compare instructions compare the contents of two floating point registers The comparison ignores the sign of zero that is 0 0 The floating point compare instructions are listed in Table 2 18 Table 2 18 Floating Point Compare Instructions Name Mnemonic Operand Syntax Floating Compare Ordered fcmpo crfD frA frB Floating Compare Unordered fempu crfD frA frB 2 3 4 2 5 Floating Point Status and Control Register Instructions Every FPSCR instruction appears to synchronize the effects of all floating point instructions executed by a given processor Executing an FPSCR instruction ensures that all floating point instructions previously initiated by the given
501. race Exception OxOQ DOO iiscscissseacsivssctasiseyssdsacsaceedathesenteauavaceesteceeeaseevaanesdes 4 29 Single Step Instruction Trace Mode sccesscesoeeseetseecensersoneessettenee 4 30 Branch Kee EE 4 30 Instruction TLB Miss Exception Ox01000 0 0 ceeeeseesseceseceseeeeseeesaeenes 4 30 Data TLB Miss on Load Exception OsO IO0 4 3 Data TLB Miss on Store Exception UO 200 4 32 Instruction Address Breakpoint Exception UNO 200 4 32 System Management Interrupt sl AO 4 34 Chapter 5 Memory Management MMU POA DUES octal esis atetusnr entails iar thai Ea a e eth teat a Eo TENSA tease eee 5 2 Memory EE eer Ee 5 3 IVI Ore ait AUN EE 5 3 Address Translation Mechanisms eet iere g s acegeeanneas se paneenves 5 8 Memory Protection Paci ties cs csccciwastelstaveesveegdehcsgivedcedadaycees ben eege geg 5 10 Page History Information as iscsccsvssdcaiscacsascacssededasagessssaesdaccvsnsdeaessegedaraceseacrvans 5 11 General Flow of MMU Address Translation cceescceesseceeseeeeeeteeeeneeees 5 11 Real Addressing Mode and Block Address Translation Selection 5 11 Page Address Translation eleng cased vec deu 5 12 MMU Exceptions Summary xcieecsaeaceqssnssstscatasaveach s seacouessunedaassoncededararcvaateaca 5 14 MMU Instructions and Register Summary 5 17 Real Addressing Mol u tetaenedeiemsneet e Egeter Dag Dee EE aE 5 19 Block Address Translation 2 3 j t20icdisieneieahaed neice Edel 5 20
502. rating system Section 4 2 Exception Processing describes the MSR which controls some of the critical functionality of the MMUs The figures show how the A20 A26 address bits index into the on chip instruction and data caches to select a cache set The remaining physical address bits are then compared with the tag fields comprised of bits PAO PA19 of the four selected cache blocks to determine if a cache hit has occurred In the case of a cache miss the instruction or data access is then forwarded to the bus interface unit which then initiates an external memory access MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Instruction Accesses Accesses MMU Features EAO EA19 MMU 32 Bit EA4 EA19 EA15 EA19 EAO EA3 IBATOU EAO EA14 IBATOL IBAT3L Re 1 e oes Upper 24 Bits of Virtual Address pe DBATOU On Chip EAO EA14 DBATOL es E Optional E HE DBAT3U DBAT3L Eo E ET Page Table Search Logic Optional a PAO PA14 PA15 PA19 SDRI SPR25 amp PA0 PA19 Optional PAO PA31 Figure 5 1 MMU Conceptual Block Diagram 32 Bit Implementations Chapter 5 Memory Management For More Information On This Product Go to www freescale com MMU Features Freescale Semiconductor Inc Instruction Unit A20 A31 BPU EAO EA19 EA0O EA3 IBAT Array
503. ration EE 7 30 PLL eg e EE 7 31 Timing KEE 8 5 Transfer Size Signal e 8 13 Burst Ordering O4 Bit erer ege eeng 8 14 Burst Ordering 32 Bil EE 8 14 Aligned Data Transfers 64 Bit Bus 8 15 Misaligned Data Transfers 4 Byte Examples c ceesccecesceeceeeeeceeeeeceeeeecsteeeeeaes 8 16 Aligned Data Transfers 32 Bit Bus Mode AAA 8 17 Misaligned 32 Bit Data Bus Transfer 4 Byte Examples ceceeeeeeseeeseeereeenees 8 18 Transfer Code Ee EE 8 19 CSE OF Si Smalls sesyucssascuseraadivasion cetehangacnecwiea tau Ee Ehe 8 30 TREE Int rface Pin Descriptions sierot eegene TE EA e ege eege 8 42 Tables XX For More Information On This Product Go to www freescale com Table Number 9 1 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19 A 20 A 21 A 22 A 23 A 24 A 25 A 26 A 27 A 28 A 29 A 30 A 31 A 32 A 33 A 34 A 35 A 36 A 37 A 38 A 39 A 40 Freescale Semiconductor Inc Tables Page Title Number MPC603e Programmable Power Modes egec iete nieggesgkrgietgrSdgdegrbgetetaturgesgir giereg 9 3 Complete Instruction List Sorted by Mnemonic eee ceeceeesceeseeceeeeeeeeseeeeseeesaeenes A 1 Complete Instruction List Sorted by Opcode A 8 Integer Arithmetic Instructions essesesseeeeserssesreesetssrseresteseserestesstseresressesseesreeseset A 15 Integer EES ee EE A 16 Integer Logical Instructions ideen SEAN A 16 Integer Rotate Lt nese event Bade A Sos
504. re 5 4 shows the three implemented address translation mechanisms provided by the MPC603e MMUs The segment descriptors shown in the figure control the page address translation mechanism When an access uses page address translation the appropriate segment descriptor is required In 32 bit implementations one of the 16 on chip segment registers which contain segment descriptors is selected by the 4 highest order effective address bits A control bit in the corresponding segment descriptor then determines if the access is to memory memory mapped or to the direct store interface space selected when the direct store translation control bit T bit in the corresponding segment descriptor is set Note that the direct store interface is present only for compatibility with existing I O devices that use this interface When an access is determined to be to the direct store interface space the MPC603e takes a DSI exception as described in Section 4 5 3 DSI Exception 0x00300 if it is a data access and takes an ISI exception as described in Section 4 5 4 ISI Exception 0x00400 if it is an instruction access For memory accesses translated by a segment descriptor the interim virtual address is generated using the information in the segment descriptor Page address translation corresponds to the conversion of this virtual address into the 32 bit physical address used by the memory subsystem In most cases the physical address for the page
505. re high Signals that are not active low such as AP 0 3 address bus parity signals and TT 0 4 transfer type signals are referred to as asserted when they are high and negated when they are low The MPC603e signals are grouped as follows Address arbitration signals The MPC603e uses these signals to arbitrate for address bus mastership Address transfer start signals These signals indicate that a bus master has begun a transaction on the address bus Address transfer signals These signals consisting of the address bus address parity and address parity error signals are used to transfer the address and to ensure the integrity of the transfer Transfer attribute signals These signals provide information about the type of transfer such as the transfer size and whether the transaction is bursted write through or cache inhibited Address transfer termination signals These signals are used to acknowledge the end of the address phase of the transaction They also indicate whether a condition exists that requires the address phase to be repeated Data arbitration signals The MPC603e uses these signals to arbitrate for data bus mastership Data transfer signals These signals consisting of the data bus data parity and data parity error signals are used to transfer the data and to ensure the integrity of the transfer Chapter 7 Signal Descriptions For More Information On This Product Go to www freescale co
506. re storing the operands The conversion steps are described in Floating Point Store Instructions in Appendix D Floating Point Models in the Programming Environments Manual Implementation Note The PowerPC architecture defines store with update instructions with rA 0 as an invalid form however the MPC603e treats this case as valid Table 2 27 lists the floating point store instructions Table 2 27 Floating Point Store Instructions Name Mnemonic Operand Syntax Store Floating Point as Integer Word Indexed stfiwx frS rA rB Store Floating Point Double stfd frS d rA Store Floating Point Double Indexed stfdx frS rA rB Store Floating Point Double with Update stfdu frS d rA Store Floating Point Double with Update Indexed stfdux frS rA rB Store Floating Point Single stfs frS d rA Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary Table 2 27 Floating Point Store Instructions continued Name Mnemonic Operand Syntax Store Floating Point Single Indexed stfsx frS rA rB Store Floating Point Single with Update stfsu frS d rA Store Floating Point Single with Update Indexed stfsux frS rA rB 2 3 4 4 Branch and Flow Control Instructions Branch instructions are executed by the branch processing unit BPU The BPU receives branch instructions from the fetch unit and pe
507. reescale com Freescale Semiconductor Inc Address Bus Tenure Table 8 6 Misaligned Data Transfers 4 Byte Examples Transfer Size Data Bus Byte Lanes 4 Bytes TSIZ 0 2 A 29 31 0 1 2 3 4 5 6 7 Aligned 100 000 A A A A Misaligned First access 011 001 A A A Second access 001 100 A Misaligned First access 010 010 A A Second access 010 100 A A Misaligned First access 001 011 A Second access 011 100 A A Aligned 100 100 A A Misaligned First access 011 101 A A Second access 001 000 A Misaligned First access 010 110 A A Second access 010 000 A A Misaligned First access 001 111 A Second access 011 000 A A A Notes A Byte lane used Byte lane not used Due to the performance degradations associated with misaligned memory operations they are best avoided In addition to the double word straddle boundary condition the address translation logic can generate substantial exception overhead when the load store multiple and load store string instructions access misaligned data It is strongly recommended that software attempt to align code and data wher
508. refetch a cache block in anticipation of a store operation read with intent to modify 3 7 4 Data Cache Block Clear to Zero dcbz Instruction If the block containing the byte addressed by the EA is in the data cache all bytes are cleared If the block containing the byte addressed by the EA is not in the data cache and the corresponding page is caching allowed the block is established in the data cache without fetching the block from main memory and all bytes of the block are cleared If the contents MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor INGA Control Instructions of the cache block are from a page marked global through the WIM bits an address only bus transaction is run If the page containing the byte addressed by the EA is caching inhibited or write through then the system alignment exception handler is invoked The dcbz instruction is treated as a store to the addressed byte with respect to address translation and protection 3 7 5 Data Cache Block Store dcbst Instruction If the block containing the byte addressed by the EA is in coherency required mode and a block containing the byte addressed by the EA is in the data cache of any processor and has been modified the writing of it to main memory is initiated On a PID7t 603e if the cache block is unmodified HIDO ABE is set and if the contents of the cache block are from a
509. remain stable during operation should only be changed during the assertion of HRESET or during sleep mode These bits may be read through HID1 PCO PC3 Table 7 10 PLL Configuration 1 2 Bus CPU and PLL Frequencies PLL_CFG 0 3 de Bus Bus Bus Bus Bus Bus Bus Ratio 16 6 MHz 20 MHz 25 MHz 33 3 MHz 40 MHz 50 MHz 66 6 MHz 0000 1 1 66 6 133 0001 1 1 33 3 40 50 133 160 200 0010 1 1 16 6 20 25 133 160 200 1100 1 5 1 75 100 150 200 0100 2 1 66 6 80 100 133 160 200 0101 2 1 33 3 40 50 133 160 200 0110 2 5 1 83 3 100 166 200 1000 3 1 75 100 150 200 1110 3 5 1 70 87 5 140 175 1010 4 1 66 6 80 100 133 160 200 0011 PLL bypass 1111 Clock off 1 Some PLL configurations may select bus CPU or PLL frequencies that are not useful not supported or not tested for by the MPC603e For complete up to date information refer to the appropriate hardware specifications PLL frequencies shown in parentheses should not fall below 133 MHz and should not exceed 200 MHz 2 In PLL bypass mode the SYSCLK input signal clocks the internal processor directly and the bus is set for 1 1 mode operation In clock off mode no clocking occurs insid
510. resides in an on chip TLB and is available for quick access However if the page address translation misses in an on chip TLB the MMU causes a search of the page tables in memory using the virtual address information and a hashing function to locate the required physical address When this occurs the MPC603e vectors to exception handlers that search the page tables with software MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MMU Features Address Translation Disabled Effective Address MSRIIR 0 or MSR DR 0 Match with BAT Registers Page Address Block Address Translation Translation see Section 5 3 Virtual Address Direct Store Interface Translation DSI ISI Exception Real Addressing Mode Effective Address Physical Address see Section 5 2 Real Addressing Mode Look Up in Page Table 0 31 0 31 0 31 Physical Address Physical Address Physical Address Figure 5 4 Address Translation Types Block address translation occurs in parallel with page address translation and is similar to page address translation however fewer higher order effective address bits are translated into physical address bits more lower order address bits at least 17 are untranslated to form the offset into a block Also instead of segment descriptors and a TLB block address translations use the on chip BAT registe
511. rforms CR look ahead operations on conditional branches to resolve them early achieving the effect of a zero cycle branch in many cases Some branch instructions can redirect instruction execution conditionally based on the value of bits in the CR When the branch processor encounters one of these instructions it scans the execution pipelines to determine whether an instruction in progress may affect the particular CR bit If no interlock is found the branch can be resolved immediately by checking the bit in the CR and taking the action defined for the branch instruction If an interlock is detected the branch is considered unresolved and the direction of the branch is predicted using static branch prediction as described in Conditional Branch Control in Chapter 4 Addressing Modes and Instruction Set Summary in the Programming Environments Manual The interlock is monitored while instructions are fetched for the predicted branch When the interlock is cleared the branch processor determines whether the prediction was correct based on the value of the CR bit If the prediction is correct the branch is considered completed and instruction fetching continues If the prediction is incorrect the fetched instructions are purged and instruction fetching continues along the alternate path See Chapter 8 Instruction Timing in the Programming Environments Manual for more information about how branches are executed 2 3 4 4 1 Branc
512. ribes the memory model for a multiprocessor environment defines cache control instructions and describes other aspects of virtual environments Implementations that conform to the VEA also adhere to the UISA but may not necessarily adhere to the OEA e Operating environment architecture OEA Defines the memory management model supervisor level registers synchronization requirements and exception model Implementations that conform to the OEA also adhere to the UISA and VEA Chapter 1 Overview For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Implementation Specific Information The PowerPC architecture allows a wide range of designs for such features as cache and system interface implementations 1 3 Implementation Specific Information The PowerPC architecture is derived from the IBM POWER architecture Performance Optimized with Enhanced RISC architecture The PowerPC architecture shares the benefits of the POWER architecture optimized for single chip implementations The PowerPC architecture design facilitates parallel instruction execution and is scaleable to take advantage of future technological gains This section describes the PowerPC architecture in general and specific details about the implementation of the MPC603e as a low power 32 bit member of this family The main topics addressed are as follows e Section 1 3 1 Programming Model describes the registers for the
513. ring a page table search operation the software must load the RPA shown in Figure 2 7 with the second word of the correct PTE When the tlbld or tlbli instruction is executed the RPA and DMISS or IMISS register are merged and loaded into the selected TLB entry The referenced R bit is ignored when the write occurs no location exists in the TLB entry for this bit The RPA register is read and write to the software Reserved RPN 000 RIC WIMG 0 PP 0 19 20 22 23 24 25 28 29 30 31 Figure 2 7 Required Physical Address Register RPA Table 2 7 describes the bit settings of the RPA register Table 2 7 RPA Bit Settings Bits Name Description 0 19 RPN Physical page number from PTE 20 22 Reserved 23 R Referenced bit from PTE 24 C Changed bit from PTE 25 28 WIMG Memory cache access attribute bits 29 Reserved 30 31 PP Page protection bits from PTE 2 1 2 6 Instruction Address Breakpoint Register IABR The IABR shown in Figure 2 8 controls the instruction address breakpoint exception IABR CEA holds an effective address to which each instruction is compared The exception is enabled by setting IABR BE The exception is taken when there is an instruction address breakpoint match on the next instruction to complete The instruction tagged with the match does not complete before the breakpoint exception is taken Reserved CEA IE
514. riptor Use EAO EA3 to Select 1 of 16 On Chip Segment Registers Check T Bit in Segment Descriptor MMU Features Page Address a SE Direct Store Segment Address T 1 Otherwise DSI ISI Exception I Fetch with N Bit Set in Generate 52 Bit Virtual Segment Descriptor Address from Segment No Execute Descriptor Compare Virtual Address with TLB Entries Ea eS ee ee ee i DI Ow Gs xN N TLB TLB A Miss Hit See Figure 5 8 x D Perform Page Table See Figure 5 9 res Search Operation Access Access O Permitted Protected O Translate Address Access Faulted PTE Not PTE Found Found Continue Access r 7 to Memory Subsystem Access Faulted Load TLB Entry Le ee ee Sl Optional to the PowerPC architecture Implemented in the MPC603e In the case of instruction accesses causes ISI exception Figure 5 6 General Flow of Page and Direct Store Interface Address Translation If the T bit in the corresponding segment descriptor is zero page address translation is selected The information in the segment descriptor is then used to generate the 52 bit Chapter 5 Memory Management For More Information On This Product Go to www freescale com MMU Features Freescale Semiconductor Inc virtual address The virtual address is then used to identify the page address translation information stored as page table entries PTEs in a page table in memory For increased
515. rmal operation is selected If DRTRY is asserted at the negation of HRESET no DRTRY mode is selected Chapter 8 System Interface Operation For More Information On This Product Go to www freescale com Interrupt Checkstop and Ereesce le Semiconductor Inc 8 6 3 Reduced Pinout Mode The MPC603e provides an optional reduced pinout mode which idles the switching of numerous signals for reduced power consumption The DL 0 31 DP 0 7 AP 0 3 APE DPE and RSRV signals are disabled when the reduced pinout mode is selected Note that the 32 bit data bus mode is implicitly selected when the reduced pinout mode is enabled In reduced pinout mode the bidirectional and output signals disabled are always driven low during the periods when they would normally have been driven by the MPC603e The open drain outputs APE and DPE are always three stated The bidirectional inputs are always turned off at the input receivers of the MPC603e and are not sampled The MPC603e selects either full pinout or reduced pinout mode at startup by sampling the state of the QACK signal at the negation of HRESET If QACK is asserted at the negation of HRESET full pinout mode is selected by the MPC603e If QACK is negated at the negation of HRESET reduced pinout mode is selected 8 7 Interrupt Checkstop and Reset Signals This section describes external interrupts checkstop operations and hard and soft reset inputs 8 7 1 External Inte
516. rmance Enhancements The following enhancements improve performance without requiring changes to software other than compiler optimization or hardware designed for the MPC603 e Support for single cycle store e Addition of adder comparator in the SRU allows dispatch and execution of multiple integer add and compare instructions on each cycle e Addition of SRRI KEY to provide information about memory protection violations prior to page table search operations This bit is set when the combination of the settings in the appropriate SR Kx and in the MSR PR bit indicate that when Chapter 1 Overview For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Overview the PTE PP bits are either 00 or 01 a protection violation exists If this is the case for a data write operation with a DTLB miss the changed C bit in the page tables should not be updated see Table 1 2 This reduces the time required to execute the page table search routine because the software no longer has to explicitly read both SR Kx and MSR PR to determine whether a protection violation exists before updating the C bit Table 1 2 Generated SRR1 KEY Bit Segment Register Ks Kp Note SRR1 KEY indicates a protection violation if the PTE pp bits are 00 or 01 1 1 3 Instruction Unit As shown in Figure 1 1 the MPC603e instruction unit containing a fetch unit instruction queue dispatch unit and BPU provides
517. rnal Control In Word Indexed eciwx rD rA rB External Control Out Word Indexed ecowx rS rA rB 2 3 6 PowerPC OEA Instructions The OEA includes the structure of the memory management model supervisor level registers and the exception model 2 3 6 1 System Linkage Instructions This section describes the system linkage instructions see Table 2 37 The se instruction is a user level instruction that permits a user program to call on the system to perform a service and causes the processor to take an exception The Return from Interrupt rfi instruction is a supervisor level instruction that is useful for returning from an exception handler Table 2 37 System Linkage Instructions Name Mnemonic Operand Syntax Return from Interrupt rfi System Call sc Z Chapter 2 Programming Model For More information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary 2 3 6 2 Processor Control Instructions OEA Processor control instructions are used to read from and write to the condition register CR machine state register MSR and special purpose registers SPRs and to read from the time base register TBU or TBL 2 3 6 2 1 Table 2 38 lists the instructions provided by the MPC603e for reading from or writing to the MSR Move To From Machine State Register Instructions Table 2 38 Move To From Machine State Register Instructions
518. rning to high impedance This special method of negation may be disabled by setting precharge disable in HIDO 7 2 5 2 2 Address Retry ARTRY Input Following are the state meaning and timing comments for the ARTRY input State Meaning Timing Comments Asserted If the MPC603e is the address bus master ARTRY indicates that the MPC603e must retry the preceding address tenure and immediately negate BR if asserted If the associated data tenure has already started the MPC603e will also abort the data tenure immediately even if the burst data has been received If the MPC603e is not the address bus master this input indicates that the MPC603e should immediately negate BR for one bus clock cycle following the assertion of ARTRY by the snooping bus master to allow an opportunity for a copy back operation to main memory Note that the subsequent address presented on the address bus may not be the same one associated with the assertion of ARTRY Negated High Impedance Indicates that the MPC603e does not need to retry the last address tenure Assertion May occur as early as the second cycle following the assertion of TS and must occur by the bus clock cycle immediately following the assertion of AACK if an address retry is required Negation Must occur during the second cycle after the assertion of AACK 7 2 6 Data Bus Arbitration Signals Like the address bus arbitration signals data bus arbitration sign
519. ro 1 1 7 3 IEEE 1149 1 JTAG COP Test Interface The MPC603e provides IEEE 1149 1 and COP functions for facilitating board testing and chip debugging The IEEE 1149 1 test interface provides a means for boundary scan testing the MPC603e and the attached board The COP function shares the IEEE 1149 1 test port providing a means for executing test routines and facilitating chip and software debugging 1 1 7 4 Clock Multiplier The internal clocking of the MPC603e is generated from and synchronized to the external clock signal SYSCLK by means of a voltage controlled oscillator based PLL The PLL provides programmable internal processor clock rates of 1x 1 5x 2x 2 5x 3x 3 5x and 4x multiples of the externally supplied clock frequency The bus clock is the same frequency and is synchronous with SYSCLK The configuration of the PLL can be read by software from the hardware implementation register 1 HID 1 1 2 PowerPC Architecture Implementation The PowerPC architecture consists of the following layers and adherence to the PowerPC architecture can be measured in terms of which of the following levels of the architecture is implemented e User instruction set architecture UISA Defines the base user level instruction set user level registers data types floating point exception model memory models for a uniprocessor environment and programming model for a uniprocessor environment e Virtual environment architecture VEA Desc
520. rom nonguarded memory may be reported When an out of order instruction result is abandoned only one side effect other than a possible machine check may occur the referenced bit R in the corresponding page table entry and TLB entry can be set due to an out of order load operation See Chapter 4 Exceptions for more information on the machine check exception Thus an out of order load or store instruction will not access guarded memory unless one of the following conditions exist e The target memory item is resident in an on chip cache In this case the location may be accessed from the cache or main memory e The target memory item is cacheable I 0 and it is guaranteed that the load or store is in the execution path assuming there are no intervening exceptions In this case the entire cache block containing the target may be loaded into the cache 3 5 5 3 Effects of Out of Order Instruction Fetches To avoid instruction fetch delay the processor typically fetches instructions ahead of those currently being executed Such instruction prefetching is said to be out of order in that prefetched instructions may not be executed due to intervening branches or exceptions During instruction prefetching no errors except machine check exceptions are reported due to the out of order fetching of an instruction until it is known that execution of the instruction is required Machine check exceptions resulting solely from out of
521. rom the CQ e Stage The term stage is used in two different senses depending on whether the pipeline is being discussed as a physical entity or a sequence of events In the latter case a stage is an element in the pipeline during which certain actions are performed such as decoding the instruction performing an arithmetic operation or writing back the results A stage is typically described as taking a processor clock cycle to perform its operation however some events such as dispatch and write back happen instantaneously and may be thought to occur at the end of the stage MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING ction Timing Overview An instruction can spend multiple cycles in one stage An integer multiply for example takes multiple cycles in the execute stage When this occurs subsequent instructions may stall In some cases an instruction may also occupy more than one stage simultaneously especially in the sense that a stage can be seen as a physical resource for example when instructions are dispatched they are assigned a place in the CQ at the same time they are passed to the execute stage They can be said to occupy both the complete and execute stages in the same clock cycle e Stall An occurrence when an instruction cannot proceed to the next stage e Superscalar A superscalar processor is one that can dispatch
522. ronous interrupt system management interrupt decrementer exception hard or soft reset or machine check input MCP signal A return to full power state from a nap state takes only a few processor clock cycles e Sleep Sleep mode reduces power consumption to a minimum by disabling all internal functional units then external system logic may disable the PLL and SYSCLK Returning the MPC603e to the full power state requires the enabling of the PLL and SYSCLK followed by the assertion of an external asynchronous interrupt system management interrupt hard or soft reset or MCP signal after the time required to relock the PLL The PID7t 603e implementation offers the following enhancements to the MPC603e family e Lower power design e 2 5 volt core and 3 3 volt I O MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semicondugto d se Implementation 1 1 7 2 Time Base Decrementer The time base is a 64 bit register accessed as two 32 bit registers that is incremented once every four bus clock cycles external control of the time base is provided through the time base enable TBEN signal The decrementer is a 32 bit register that generates a decrementer interrupt exception after a programmable delay The contents of the decrementer register are decremented once every four bus clock cycles and the decrementer exception is generated as the count passes through ze
523. roper use of the ICFI and DCFI bits is to set them and clear them with two consecutive mtspr operations 22 23 Reserved should be cleared 24 IFEM Enable M bit on 60x bus for instruction fetches PID7t 603e only 0 Mbit not reflected on bus for instruction fetches Instruction fetches are treated as nonglobal on the bus 1 Instruction fetches reflect the M bit from the WIM settings 25 26 Reserved should be cleared 27 FBIOB Force branch indirect on bus 0 Register indirect branch targets are fetched normally 1 Forces register indirect branch targets to be fetched externally 28 ABE Address broadcast enable Controls whether certain address only operations such as cache operations are broadcast on the 60x bus 0 Address only operations affect only local caches and are not broadcast 1 Address only operations are broadcast on the 60x bus Affected instructions are debi dcbf and dcbst Note that these cache control instruction broadcasts are not snooped by the PID7t 603e Refer to Section 3 2 3 Data Cache Control for more information 29 30 Reserved 31 NOOPTI No op the data cache touch instructions 0 The debt and debtst instructions are enabled 1 The debt and debtst instructions are no oped globally 1 See Chapter 9 Power Management 2 See Chapter 3 Instruction and Data Cache Operation Table 2 3 shows how HIDO BCLK HIDO ECLK and HRESET are used to configure CLK_OUT
524. ropriate mode is then set by the software The MPC603e provides a separate interrupt and interrupt vector for power management the system management interrupt SMI The MPC603e also contains a decrement timer that allows it to enter the nap or doze mode for a predetermined period and then return to full power operation through the decrementer interrupt exception The MPC603e provides four power modes selectable by setting the appropriate control bits in the MSR and HIDO The four power modes are described briefly as follows e Full power This is the default power state of the MPC603e The MPC603e is fully powered and the internal functional units are operating at the full processor clock speed If the dynamic power management mode is enabled functional units that are idle will automatically enter a low power state without affecting performance software execution or external hardware e Doze All the functional units of the MPC603e are disabled except for the time base decrementer registers and the bus snooping logic When the processor is in doze mode an external asynchronous interrupt system management interrupt decrementer exception hard or soft reset or machine check brings the MPC603e into the full power state The MPC603e in doze mode maintains the phase locked loop PLL in a fully powered state and is locked to the system external clock input SYSCLK so a transition to the full power state takes only a few processor clock cycles
525. rrupts Asserting the external interrupt input signals INT SMI and MCP of the MPC603e eventually forces the processor to take the external interrupt vector or the system management interrupt vector if the MSR EE is set or the machine check interrupt if MSR ME and HIDO EMCP are set 8 7 2 Checkstops Asserting the MPC603e has two checkstop input signals CKSTP_IN non maskable and MCP enabled when MSR ME is cleared and HIDO EMCP is set and a checkstop output CKSTP_OUT If CKSTP_IN or MCP is asserted the MPC603e halts operations by gating off all internal clocks The MPC603e asserts CKSTP_OUT if CKSTP_IN is asserted If CHECKSTOP is asserted by the MPC603e it has entered the checkstop state and processing has halted internally The CHECKSTOP signal can be asserted for various reasons including receiving a TEA signal and detection of external parity errors For more information about checkstop state see Section 4 5 2 2 Checkstop State MSR ME 0 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Processor State Signals 8 7 3 Reset Inputs The MPC603e has two reset inputs described as follows e HRESET hard reset HRESET is used for power on reset sequences or for situations in which the MPC603e must go through the entire cold start sequence of internal hardware initializations e SRESET soft reset Th
526. rs PowerPC instructions that have not been implemented The instructions can be emulated in software as required A defined instruction can have invalid forms as described in the following section 2 3 1 3 Illegal Instruction Class Illegal instructions are grouped into the following categories Instructions not defined in the PowerPC architecture These opcodes are available for future extensions of the PowerPC architecture that is future versions of the architecture may define any of these instructions to perform new functions The following primary opcodes are defined as illegal but may be used in future extensions to the architecture 1 4 5 6 9 22 56 57 60 61 Instructions defined in the PowerPC architecture but not implemented in a specific implementation For example instructions that can be executed on 64 bit processors are considered illegal by 32 bit processors The following primary opcodes are defined for 64 bit implementations only and are illegal on the MPC603e 2 30 58 62 All unused extended opcodes are illegal The unused extended opcodes can be determined from information in Section A 2 Instructions Sorted by Opcode and Section 2 3 1 4 Reserved Instruction Class Notice that extended opcodes for instructions that are defined only for 64 bit implementations are illegal in 32 bit implementations and vice versa The following primary opcodes have unused extended opcodes 17 19 31 59 6
527. rs as a BAT array If an effective address matches the corresponding field of a BAT register the information in the BAT register is used to generate the physical address in this case the results of the page translation occurring in parallel are ignored even if the segment corresponds to the direct store interface space Real addressing mode translation occurs when address translation is disabled in this case the physical address generated is identical to the effective address Instruction and data address translation is enabled with the MSR IR and MSR DR bits respectively Thus when the processor generates an access and the corresponding address translation enable Chapter 5 Memory Management For More Information On This Product Go to www freescale com MMU Features Freescale Semiconductor Inc bit in MSR MSR IR for instruction accesses and MSR DR for data accesses is cleared the resulting physical address is identical to the effective address and all other translation mechanisms are ignored 5 1 4 Memory Protection Facilities In addition to the translation of effective addresses to physical addresses the MMUs provide access protection of supervisor areas from user access and can designate areas of memory as read only as well as no execute or guarded Table 5 2 shows the eight protection options supported by the MMUs for pages Table 5 2 Access Protection Options for Pages
528. rtion Must occur during the bus clock cycle immediately after TA is asserted if a retry is required DRTRY may be held asserted for multiple bus clock cycles When DRTRY is negated data must have been valid on the previous clock with TA asserted Negation Must occur during the bus clock cycle after a valid data beat This may occur several cycles after DBB is negated effectively extending the data bus tenure Start Up DRTRY is sampled at the negation of HRESET if DRTRY is asserted no DRTRY mode is selected If DRTRY is negated at start up DRTRY is enabled 7 2 8 3 Transfer Error Acknowledge TEA Input Following are the state meaning and timing comments for the TEA input State Meaning Asserted Indicates that a bus error occurred Causes a machine check exception and possibly causes the processor to enter checkstop state if machine check enable bit is cleared MSR ME 0 For more information see Section 4 5 2 2 Checkstop State MSR ME 0 Assertion terminates the current transaction that is assertion of TA and DRTRY are ignored The MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Timing Comments Freescale Semiconductor Inc i Ka Signal Descriptions assertion of TEA causes the negation high impedance of DBB in the next clock cycle However data entering the GPR or the cache are not invalidated Negated Indic
529. ruction Trace Mode e When MSR BE is set the branch trace exception is taken after each branch instruction is completed e The MPC603e deviates from the architecture by not taking trace exceptions on isyne instructions Single step instruction trace mode is described in Section 4 5 11 2 Branch Trace Mode Successful completion implies that the instruction caused no other exceptions A trace exception is never taken for an sc or trap instruction that takes a trap exception MSR SE and MSR BE are cleared when the trace exception is taken In the normal use of this function MSR SE and MSR BE are restored when the exception handler returns to the interrupted program using an rfi instruction Register settings for the trace mode are described in Table 4 16 Chapter 4 Exceptions For More Information On This Product Go to www freescale com Se Freescale Semiconductor Inc Exception Definitions Table 4 16 Trace Exception Register Settings Register Setting Description SRRO Set to the address of the instruction following the one for which the trace exception was generated SRR1 0 15 Cleared 16 31 Loaded from MSR 16 31 MSR POW 0 EE 0 FEO 0 IR 0 TGPR 0 PR 0 SE 0 DR 0 ILE FP 0 BE 0 RI 0 IP ME FE1 0 LE Set to value of ILE Note that a trace or instruction address breakpoint exception condition generates a soft stop instead of an exception if soft stop has been enabled by the JTAG C
530. ructions The IU and the FPU each have dedicated register files for maintaining operands GPRs and FPRs respectively allowing integer and floating point calculations to occur simultaneously without interference Integer division performance of the PID7t 603e has been improved with the divwux and divwx instructions executing in 20 clock cycles instead of the 37 cycles required in the PID6 603e The MPC603e provides support for single cycle store and it provides an adder comparator in the system register unit that allows the dispatch and execution of multiple integer add and compare instructions on each cycle Refer to Chapter 6 Instruction Timing for more information Because the PowerPC architecture can be applied to such a wide variety of implementations instruction timing among various processors varies accordingly 1 3 7 System Interface The system interface is specific for each processor implementation The MPC603e provides a versatile system interface that allows for a wide range of implementations The interface includes a 32 bit address bus a 32 or 64 bit data bus and 56 control and information signals see Figure 1 4 The system interface allows for address only transactions as well as address and data transactions The MPC603e control and information signals include the address arbitration address start address transfer transfer attribute address termination data arbitration data transfer data termination and proc
531. ructions take the MPC603e specific emulation trap exception 0x01600 rather than a program exception 4 5 8 Floating Point Unavailable Exception 0x00800 A floating point unavailable exception occurs when no higher priority exception exists an attempt is made to execute a floating point instruction including floating point load store and move instructions and the floating point available bit in the MSR is disabled MSR FP 0 Register settings for this exception are described in Chapter 6 Exceptions in the Programming Environments Manual When a floating point unavailable exception is taken instruction execution for the handler begins at offset Ox00800 from the physical base address indicated by MSR IP 4 5 9 Decrementer Exception 0x00900 The MPC603e implements the decrementer interrupt exception as it is defined in the PowerPC architecture A decrementer exception request is made when the decrementer counts down through zero The request is held until there are no higher priority exceptions MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Caen Exception Definitions and MSR EE 1 At this point the decrementer exception is taken If multiple decrementer exception requests are received before the first can be reported only one exception is reported The occurrence of a decrementer exception cancels the request Register settings
532. ry Also the MPC603e on chip caches TLBs and optional second level caches can be controlled externally The MPC603e clocking structure allows the bus to operate at integer multiples of the processor cycle time The following sections describe the MPC603e bus support for memory operations Note that some signals perform different functions depending on the addressing protocol used 1 3 7 1 Memory Accesses The MPC603e bus is configured at power up to either a 32 or 64 bit width e When the processor is configured with a 32 bit data bus memory accesses allow transfer sizes of 8 16 24 or 32 bits in one bus clock cycle Data transfers occur in either single beat transactions two beat or eight beat burst transactions with a single beat transaction transferring as many as 32 bits Single or double beat transactions are caused by noncached accesses that access memory directly that is reads and writes when caching is disabled caching inhibited accesses and stores in write through mode Eight beat burst transactions which always transfer an entire cache block 32 bytes are initiated when a line is read from or written to memory e When the MPC603e is configured with a 64 bit data bus memory accesses allow transfer sizes of 8 16 24 32 40 48 56 or 64 bits in one bus clock cycle Data transfers occur in either single beat transactions or four beat burst transactions Single beat transactions are caused by noncached accesses that acc
533. ry can be updated atomically by setting a reservation on the load and checking that the reservation is still valid before the store is performed In the MPC603e the reservations are made on behalf of aligned 32 byte sections of the memory address space The reservation RSRV output signal is driven synchronously with the bus clock and reflects the status of the reservation coherency bit in the reservation address buffer see Section 3 9 Instruction and Data Cache Operation for more information See Section 7 2 9 7 3 Reservation RSRV Output for information about timing Chapter 8 System Interface Operation For More Information On This Product Go to www freescale com IEEE 1149 1 Compliant ine eee scale Semiconductor Inc 8 8 2 TLBISYNC Input The TLBIS YNC input allows for the hardware synchronization of changes to MMU tables when the MPC603e and another DMA master share the same MMU translation tables in system memory It is asserted by a DMA master when it is using shared addresses that could be changed in the MMU tables by the MPC603e during the DMA master s tenure Asserting the TLBISYNC input to the MPC603e prevents it from completing any instructions past a tlbsync instruction Generally during the execution of an eciwx or ecowx instruction by the MPC603e the selected DMA device should assert the MPC603e TLBISYNC signal and keep it asserted during its DMA tenure if it is using a shared translation address
534. ry in the case of a TLB miss However neither of these instructions causes the C bit to be set As defined by the PowerPC architecture the referenced and changed bits are updated as if address translation were disabled real addressing mode translation Additionally these updates should be performed with single beat read and byte write transactions on the bus 5 4 1 1 Referenced Bit The referenced R bit of a page is located in the PTE in the page table Every time a page is referenced with a read or write access and the R bit is zero the R bit is then set in the page table The OEA specifies that the referenced bit may be set immediately or the setting may be delayed until the memory access is determined to be successful Because the reference to a page is what causes a PTE to be loaded into the TLB the referenced bit in all MPC603e TLB entries is effectively always set The processor never automatically clears the referenced bit The referenced bit is only a hint to the operating system about the activity of a page At times the referenced bit may be set although the access was not logically required by the program or even if the access was prevented by memory protection Examples of this in these systems include the following e Fetching of instructions not subsequently executed e Accesses generated by an Iswx or stswx instruction with a zero length e Accesses generated by a stwex instruction when no store is performed because a
535. ry protection see Memory Protection Facilities in Chapter 7 Memory Management in the Programming Environments Manual MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MMU Features 5 1 5 Page History Information The MMUs of processors that support the PowerPC architecture also define referenced R and changed C bits in the page address translation mechanism that can be used as history information relevant to the page This information can then be used by the operating system to determine the areas of memory to write back to disk when new pages must be allocated in main memory While these bits are initially programmed by the operating system into the page table the architecture specifies that the R and C bits may be maintained either by the processor hardware automatically or by some software assist mechanism that updates these bits when required The software table search routines used by the MPC603e set the R bit when a PTE is accessed the MPC603e causes an exception to vector to the software table search routines when the C bit in the corresponding TLB entry requires updating 5 1 6 General Flow of MMU Address Translation The following sections describe the general flow used by processors that implement the PowerPC architecture to translate effective addresses to virtual and then physical addresses 5 1 6 1 Real Addressing Mode
536. s e Single precision arithmetic instructions require all operands to be single precision and always produce single precision results For arithmetic instructions conversions from double to single precision must be done explicitly by software while conversions from single to double precision are done implicitly All implementations of the Power PC architecture provide the equivalent of the following execution models to ensure that identical results are obtained The definition of the arithmetic instructions for infinities denormalized numbers and NaNs follow conventions described in the following sections Although the double precision format specifies an 11 bit exponent exponent arithmetic uses two additional bit positions to avoid potential transient overflow conditions An extra bit is required when denormalized double precision numbers are prenormalized A second bit is required to permit computation of the adjusted exponent value in the following examples when the corresponding exception enable bit is one e Underflow during multiplication using a denormalized factor Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Operand Conventions e Overflow during division using a denormalized divisor 2 2 2 Data Organization in Memory and Data Transfers Bytes in memory are numbered consecutively starting with 0 Each number is the address of the corresponding
537. s The ICE bit is cleared during a power on reset causing the instruction cache to be disabled To prevent the cache from being enabled or disabled in the middle of a data access an isyne instruction should be issued before changing the value of ICE 3 1 3 3 Instruction Cache Locking The contents of instruction cache may be locked through the use of HIDO ILOCK A locked instruction cache supplies instructions normally on a cache hit but cache misses are treated as cache inhibited accesses The cache inhibited CI signal is asserted if a cache access misses into a locked cache The setting of the ILOCK bit must be preceded by an isync instruction to prevent the instruction cache from being locked during an instruction access 3 2 Data Cache Organization and Control The LSU transfers data between the data cache and the GPRs and FPRs and provides buffers for load and store bus operations The data cache also provides storage for the cache tags required for memory coherency and performs the cache block replacement LRU function 3 2 1 Data Cache Organization The organization of the data cache is shown in Figure 3 2 Each cache block contains eight contiguous words from memory that are loaded from an eight word boundary that is bits A27 A31 of the effective addresses are zero thus a cache block never crosses a page boundary Misaligned accesses across a page boundary can incur a performance penalty Note that bits A20 A26 provide an in
538. s These instructions will trap to an illegal instruction exception handler when encountered Recall that the term latency is defined as the total time it takes to execute an instruction and make ready the results of that instruction Table 6 1 provides the latencies for the branch instructions Table 6 1 Branch Instructions Mnemonic Primary Extended Unit ined 1 bettel 16 ene Uu 18 i bcir i 19 016 BPU 1 bcctr l 19 528 BPU 1 1 These operations may be folded for an effective cycle time of 0 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Latency Summary Table 6 2 provides the latencies for the system register instructions Table 6 2 System Register Instructions Mnemonic Primary Extended Unit er sc 17 1 SRU 3 rfi 19 050 SRU 3 isync 19 150 SRU 1 amp mfmsr 31 083 SRU 1 mtmsr 31 146 SRU 2 mtsr 31 210 SRU 2 mtsrin 31 242 SRU 2 mfspr not I DBATs 31 339 SRU 1 mfspr DBATs 31 339 SRU 3 amp mfspr IBATs 31 339 SRU 3 amp mtspr not IBATs 31 467 SRU 2 XER amp mtspr DATS 31 467 SRU 2 amp mfsr 31 595 SRU 3 amp sync 31 598 SRU 1 amp mfsrin 31 659 SRU 3 amp eieio 31 854 SRU 1 mftb 31 371 SRU 1 mttb 31 467 SRU 1 Note Cycle times marked with amp require a variable number of cycles due to s
539. s isync or rfi Also note that care should be taken to avoid modification of the instruction TLB entries that translate current instruction prefetch addresses This is a supervisor level instruction it is also a MPC603e specific instruction and not part of the PowerPC instruction set Other registers altered es None Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 3 Instruction and Data Cache Operation The MPC603e microprocessor provides two 16 Kbyte four way set associative caches to allow the registers and execution units rapid access to instructions and data Both the instruction and data caches are tightly coupled to the MPC603e bus interface unit BIU to allow efficient access to the system memory controller and other bus masters The MPC603e load store unit LSU is also directly coupled to the data cache to allow the efficient movement of data to and from the general purpose and floating point registers This chapter describes the organization of the cache cache coherency protocols cache control instructions and various cache operations It describes the interaction between the caches the load store unit the instruction unit and the memory subsystem Note that in t
540. s Product Go to www freescale com Freescale Semiconductor Inc Instruction Latency Summary Completion queue is not full after dispatch from IQO Instruction dispatched from IQ1 is not dispatch serialized 6 6 1 3 Completion Unit Resource Requirements The following is a list of resources required to avoid stalls in the completion unit note that the two completion buffers are described as CQO and CQ1 where CQO is the entry at the end of the queue e Requirements for completing an instruction from CQO are as follows Instruction in CQO must be finished Instruction in CQO must not follow an unresolved predicted branch Instruction in CQO must not cause an exception e Requirements for completing an instruction from CQ are as follows Instruction in CQO must complete in same cycle Instruction in CO must be finished Instruction in CQ1 must not follow an unresolved predicted branch Instruction in CQ must not cause an exception Instruction in CQ1 must be an integer or load instruction Number of CR updates from both CQO and CQ1 must not exceed one Number of GPR updates from both CQO and CQ1 must not exceed two Number of FPR updates from both CQO and CQ1 must not exceed one 6 7 Instruction Latency Summary Table 6 1 through Table 6 6 list the latencies associated with each instruction executed by the MPC603e Note that the instruction latency tables contain no 64 bit architected instruction
541. s a branch and link instruction typically used for linking to subroutines Count register CTR The 32 bit CTR can be used to hold a loop count that can be decremented during execution of appropriately coded branch instructions It can also provide the branch target address for the Branch Conditional to Count Register bectrx instruction User level registers VEA The VEA introduces the time base facility TB for reading The TB is a 64 bit register pair whose contents are incremented once every four bus clock cycles The TB consists of two 32 bit registers time base upper TBU and time base lower TBL Note that the time base registers are read only in user state The MPC603 e supervisor level registers are described as follows Supervisor level registers OEA The OEA defines the registers an operating system uses for memory management configuration and exception handling The PowerPC architecture defines the following supervisor level registers Configuration registers Machine state register MSR The MSR defines the state of the processor The MSR can be modified by the Move to Machine State Register mtmsr System Call sc and Return from Exception rfi instructions It can be read by the Move from Machine State Register mfmsr instruction Implementation Note The MPC603e defines MSR 13 as the power management enable POW bit and MSR 14 as the temporary GPR remapping TGPR bit These bits are descr
542. s a snooping device the MPC603e asserts ARTRY for a snooped transaction that hits modified data in the data cache that must be written back to memory or if the snooped transaction could not be serviced As a bus master the MPC603e responds to an assertion of ARTRY by aborting the bus transaction and re requesting the bus Note that after recognizing an assertion of ARTRY and aborting the transaction in progress the MPC603e is not guaranteed to run the same transaction the next time it is granted the bus due to internal reordering of load and store operations Figure 8 6 Snooped Address Cycle with ARTRY If an address retry is required the ARTRY response is asserted by a bus snooping device as early as the second cycle after the assertion of TS or until the third cycle following TS if 1 1 or 1 5 1 processor to bus clock ratio is selected Once asserted ARTRY must remain asserted through the cycle after the assertion of AACK The assertion of ARTRY during the cycle after the assertion of AACK is referred to as a qualified ARTRY An earlier assertion of ARTRY during the address tenure is referred to as an early ARTRY As a bus master the MPC603e recognizes either an early or qualified ARTRY and prevents the data tenure associated with the retried address tenure If the data tenure has already begun the MPC603e aborts and terminates the data tenure immediately even if the burst data has been received If the as
543. s asserts TS coincident with ABB As an input TS need not coincide with the assertion of ABB on the bus that is TS can be asserted with or on a subsequent clock cycle after ABB is asserted the MPC603e tracks this transaction correctly In Figure 8 5 the address transfer occurs during bus clock cycles 1 and 2 arbitration occurs in bus clock cycle 0 and the address transfer is terminated in bus clock 3 In this diagram Chapier 8 System Interface Operation For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Address Bus Tenure the address bus termination input AACK is asserted to the MPC603e on the bus clock following assertion of TS as shown by the dependency line This is the minimum duration of the address transfer for the MPC603e the duration can be extended by delaying the assertion of AACK for one or more bus clocks l 0 l 1 l 2 l 3 l 4 l Bus Clock qual_bg TS ABB ADDR AACK ARTRY Figure 8 5 Address Bus Transfer 8 3 2 1 Address Bus Parity The MPC603e always generates 1 bit of correct odd byte parity for each of the 4 bytes of address when a valid address is on the bus The calculated values are placed on the AP 0 3 outputs when the MPC603e is the address bus master If the MPC603e is not the master and TS and GBL are asserted together qualified condition for snooping memory operations the calculated values are compared with the A
544. s attempted with an illegal opcode or illegal combination of opcode and extended opcode fields including PowerPC instructions not implemented in the MPC603e or when execution of an optional instruction not provided in the MPC603e is attempted these do not include those optional instructions that are treated as no ops e Privileged instruction A privileged instruction type program exception is generated when the execution of a privileged instruction is attempted and the MSR register user privilege bit MSR PRI is set In the MPC603e this exception is generated for mtspr or mfspr with an invalid SPR field if SPR O 1 and MSRI PR 1 This may not be true for all processors e Trap A trap type program exception is generated when any of the conditions specified in a trap instruction is met Chapter 1 Overview For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Implementation Specific Information Table 1 5 Exceptions and Conditions continued Exception Vector Offset Causing Conditions Type hex Floating point 00800 A floating point unavailable exception is caused by an attempt to execute a unavailable floating point instruction including floating point load store and move instructions when the floating point available bit is disabled MSR FP 0 Decrementer 00900 The decrementer exception occurs when DEC 31 changes fro
545. s data coherency and the corresponding access is considered to be a global access When the M attribute is set and the access is performed the global signal is asserted to indicate that the access is global Snooping devices affected by the access must then MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Frees aAlg Sees bag IM Fade Bits w 1 m and G respond to this global access if their data is modified by asserting ARTRY and updating the memory location Because instruction memory does not have to be consistent with data memory the MPC603e ignores the M attribute for instruction accesses 3 5 4 Guarded Attribute G When the guarded bit is set the memory area block or page is designated as guarded meaning that the processor will perform out of order accesses to this area of memory only as follows e Out of order load operations from guarded memory areas are performed only if the corresponding data is resident in the cache e The processor prefetches from guarded areas but only when required and only within the memory boundary dictated by the cache block That is if an instruction is certain to be required for execution by the program it is fetched and the remaining instructions in the block may be prefetched even if the area is guarded This setting can be used to protect certain memory areas from read accesses made by the processor that are not dictated
546. s mode Misaligned data transfers when the MPC603e is configured with a 32 bit data bus operate in the same way as when configured with a 64 bit data bus with the exception that only the DH 0 31 data bus is used See Table 8 8 for an example of a 4 byte misaligned transfer starting at each possible byte address within a double word Chapter 8 System Interface Operation For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Address Bus Tenure Table 8 8 Misaligned 32 Bit Data Bus Transfer 4 Byte Examples Transfer Size Data Bus Byte Lanes 4 Bytes TSIZ 0 2 A 29 31 0 1 2 3 4 5 6 7 Aligned 100 000 A A A A x x x x Misaligned First access 011 001 A A A x x x x Second access 001 100 A D D D D Misaligned First access 010 010 A A x x x x Second access 010 100 A A D D D D D Misaligned First access 001 011 A x x x x Second access 011 100 A A D D D D Aligned 100 100 A A x x x x Misaligned First access 011 101 A A x x x x Second access 001 000 A D D D D Misaligned First access 010 110 A A x x x D Second access 010 000 A A D D D D Misaligned First access 001 111 A x D x x Second access 011 000 A A A D D D D Notes A Byte lane used Byte lane not used x Byte lane not used in 32 bit bus mode 8 3 2 5 1 Alignmen
547. s shascava tecsenseaveracesdecedenteaes 3 6 Data Cache Kehmen 3 7 Data Cache Locking ienn ee eege EE 3 7 Data Cache Operations and Address Broadcasts 3 7 Data Cache Touch Load Support eegene d iert Edel die 3 8 Basic Data Cache Operations s51 lt ic 42sscassasjeeessuaten Neie sedeant leveaaeastaens 3 8 D t Cache Pills sneha neti t otto os EE 3 8 Data Cache Cast Out Operation acs 2cssccvs deavesas acs acedcacar ts uceovanssenusecadorsvcztecadeass 3 8 Cache Block Push Operation seenen 3 9 Data Cache Transactions on E 3 9 Single Beat Transactions si lt 2cc lt c sesscanasdceacoaavacaeds soesnucaaveranegoaceedonavccaate EEN 3 9 B rst PraniSaCuiOns Zeene ete ented al Seka ere Egger 3 9 Access to Direct Store SeSments vsiccsscccecias cesssassevsdcntssccsencacesocacvanncaevsansdeatacane 3 10 Memory Management Cache Access Mode Bits W I M and 3 10 Werite Through Attribute W ee eege 3 11 Caching Inhibited Attribute I ee eege ee 3 12 Memory Coherency Attribute OM 3 12 Guarded Attribute Gjersa n a E 3 13 W I and M Bit Combinations cccc cc cececcececcccccesssesssceccccsesessesescesceseseees 3 13 Out of Order Execution and Guarded Memory c cccescceesseeeeeteeeeees 3 14 Effects of Out of Order Data ACCESSES ue 3 14 Effects of Out of Order Instruction Fetches 0 ceeceeesseeesseceesseeeesneeeenes 3 15 Cache Coherency MEI Protocol scsicsivacs ices suacea ss cccsdinasvasacsounddeees seasaavecestcceasees 3 15
548. saved to certain registers and the processor begins execution at an address exception vector predetermined for each exception Processing of exceptions occurs in supervisor mode Although multiple exception conditions can map to a single exception vector a more specific condition may be determined by examining a register associated with the exception for example the DSISR or FPSCR Additionally certain exception conditions can be explicitly enabled or disabled by software The PowerPC architecture requires that exceptions be handled in program order therefore although a particular implementation may recognize exception conditions out of order they are handled strictly in order with respect to the instruction stream When an instruction caused exception is recognized any unexecuted instructions that appear earlier in the instruction stream including any that have not yet entered the execute state are required to complete before the exception is taken Any exceptions caused by those instructions are handled first Likewise exceptions that are asynchronous and precise are recognized when they occur but are not handled until the instruction currently in the completion stage successfully completes execution or generates an exception and the completed store queue is emptied An instruction is said to have completed when the results of that instruction s execution have been committed to the registers defined by the architecture for example t
549. scenarios The entries in the table are prioritized from top to bottom such that a matching scenario occurring closer to the top of the table takes precedence over a matching scenario closer to the bottom of the table For example if an stwex instruction causes a protection violation and there is no reservation the C bit is not altered as shown for the protection violation case Note that in the table load operations include those generated by load instructions by the eciwx instruction and by the cache management instructions that are treated as a load with respect to address translation Similarly store operations include those operations generated by store instructions by the ecowx instruction and by the cache management instructions that are treated as a store with respect to address translation In the columns for the MPC603e the combination of the MPC603e itself and the software used to search the page tables described in Section 5 5 2 Implementation Specific Table Search Operation is assumed Chapter 5 Memory Management For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Memory Segment Model Table 5 8 Model for Guaranteed R and C Bit Settings R Bit Set C Bit Set Priority Scenario OEA MPC603e OEA MPC603e 1 No execute protection violation No No No No 2 Page protection violation Maybe Yes No No 3 Out of order instruction fetch or load operation Maybe No No No
550. selected by lt ea gt and SRR1 WAY In addition the MPC603e contains the following features that do not specifically control the MPC603e MMU but that are implemented to increase performance and flexibility in the software table search routines whenever one of the three TLB miss exceptions occurs e Temporary GPRO GPR3 These registers are available as r0 r3 when MSR TGPR is set The MPC603e automatically sets MSR TGPR for these cases allowing these exception handlers to have four registers that are used as scratchpad space without having to save or restore this part of the machine state that existed when the exception occurred Note that MSR TGPR is cleared when the rfi instruction is MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Mes able BEE executed because the old MSR value with MSR TGPR 0 saved in SRRI is restored Refer to Section 5 5 2 2 Software Table Search Operation for code examples that take advantage of these registers e Also the MPC603e automatically saves the values of CR CRO of the executing context to SRR1 0 3 Thus the exception handler can set CR CRO bits and branch accordingly in the exception handler routine without having to save the existing CR CRO bits However the exception handler must restore these bits to CR CRO before executing the rfi instruction e SRR1 D I identifies an instruc
551. serted Indicates that the MPC603e is the data bus master The MPC603e always assumes data bus mastership if it needs the data bus and is given a qualified data bus grant see DBG Negated Indicates that the MPC603e is not using the data bus Timing Comments Assertion Occurs during the bus clock cycle following a qualified DBG Negation Occurs for a minimum of one half bus clock cycle dependent on clock mode following the assertion of the final TA High Impedance Occurs after DBB is negated 7 2 6 3 2 Data Bus Busy DBB Input Following are the state meaning and timing comments for the DBB input State Meaning Asserted lIndicates that another device is the bus master Negated Indicates that the data bus is free with proper qualification see DBG for use by the MPC603e Timing Comments Assertion Must occur when the MPC603e must be prevented from using the data bus Negation May occur whenever the data bus is available 7 2 7 Data Transfer Signals Like the address transfer signals the data transfer signals are used to transmit data and to generate and monitor parity for the data transfer For a detailed description of how the data transfer signals interact see Section 8 4 3 Data Transfer 7 2 7 1 Data Bus DH 0 31 DL 0 31 The data bus DH 0 31 and DL 0 31 consists of 64 signals that are both input and output on the MPC603e Following are the state meaning and timing comments
552. sertion of ARTRY is received up to or on the bus cycle following the first or only assertion of TA for the data tenure the MPC603e ignores the first data beat and if it is a load operation does not forward data internally to the cache and MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Bus Tenure execution units If ARTRY is asserted after the first or only assertion of TA improper operation of the bus interface may result During the clock of a qualified ARTRY the MPC603e also determines if it should negate BR and ignore BG on the following cycle On the following cycle only the snooping master that asserted ARTRY and needs to perform a snoop copy back operation is allowed to assert BR This guarantees the snooping master an opportunity to request and be granted the bus before the just retried master can restart its transaction Note that a nonclocked bus arbiter may detect the assertion of address bus request by the bus master that asserted ARTRY and return a qualified bus grant one cycle earlier than shown in Figure 8 6 8 4 Data Bus Tenure This section describes the data bus arbitration transfer and termination phases defined by the MPC603e memory access protocol The phases of the data tenure are identical to those of the address tenure underscoring the symmetry in the control of the two buses 8 4 1 Data Bus Arbitratio
553. several miscellaneous registers The MPC603e microprocessor also has its own unique set of hardware implementation HID registers Having access to privileged instructions registers and other resources allows the operating system to control the application environment providing virtual memory and protecting operating system and critical machine resources Instructions that control the state of the MPC603e the address translation mechanism and supervisor registers can be executed only when the processor is operating in supervisor mode Figure 1 2 shows all the MPC603e registers available at the user and supervisor level The numbers to the right of the SPRs indicate the number that is used in the syntax of the instruction operands for the move to from SPR instructions The following sections describe the PID7t 603e implementation specific features as they apply to registers 1 3 1 1 Processor Version Register PVR The processor version number is 6 for the PID6 603e and 7 for the PID7t 603e The processor revision level starts at 0x0100 and changes for each chip revision The revision level is updated on all silicon revisions 1 3 1 2 Hardware Implementation Register 0 HIDO PID7t 603e designated by PVR level 0x0200 defines additional bits in the hardware implementation register 0 HIDO a supervisor level register that provides the means for enabling MPC603e checkstops and features and allows software to read the configuration of
554. sociated with the data tenure in operation If ARTRY is connected for the MPC603e the earliest allowable assertion of TA to the MPC603e is directly dependent on the earliest possible assertion of ARTRY to the MPC603e see Section 8 3 3 Address Transfer Termination If the MPC603e clock is configured for 1 1 or 1 5 1 processor clock to bus clock ratio mode and the MPC603e is performing a burst read into its data cache at least one wait state must be provided between the assertion of TS and the first assertion of TA for that transaction If no DRTRY mode is also selected at least two wait states must be provided The wait states are required due to possible resource contention in the data cache caused by a block replacement or cast out required in connection with the new linefill These wait states may be provided by withholding the assertion of TA to the MPC603e for that data tenure or by withholding DBG to the MPC603e thereby delaying the start of the data tenure This restriction applies only to burst reads into the data cache when configured in 1 1 or 1 5 1 clock modes It does not apply to instruction fetches write operations noncachable read operations or non 1 1 or non 1 5 1 clock modes MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Data Bus Tenure 8 4 4 1 Normal Single Beat Termination Normal termination of a single beat dat
555. ss for the debz and the write through store are different but aliased to the same physical page Appendix C Revision History For More Information On This Product Go to www freescale com e Semiconductor Inc F Revision Changes From narsescale Se 2 3 5 4 2 42 2 3 6 3 1 2 44 3 1 3 2 3 4 3 2 3 2 3 6 To avoid potential adverse effects dcbz should not address write through memory that can be accessed through multiple logical addresses Explicit store instructions that write all zeroes should be used instead Note that broadcasting a sequence of dcbz instructions may cause snoop accesses to be retried indefinitely which may cause the snoop originator to time out or may cause the snooped transaction to not complete This can be avoided by disabling the broadcasting of debz by marking the memory space being addressed by the debz instruction as not global in the BAT or PTE Replace the first four sentences of this section with the following The eciwx instruction provides an alternative way to map special devices The MMU translation of the EA is not used to select the special device as it is used in loads and stores Rather it is used as an address operand that is passed to the device over the address bus Four other signals the burst and size signals on the 60x bus are used to select the device these four signals output the 4 bit resource ID RID field in the EAR register The eciwx instruction also loads a word
556. ss or matching DLTB exception also caused entry has C 0 and access is a store when changed bit must be updated vector offset 0x1200 Registers IMISS and DMISS When a TLB miss exception occurs the IMISS or DMISS register contains the 32 bit effective address of the instruction or data access that caused the miss exception ICMP and DCMP The ICMP and DCMP registers contain the word to be compared with the first word of a PTE in the table search software routine to determine if a PTE contains the address translation for the instruction or data access The contents of ICMP and DCMP are automatically derived by the MPC603e when a TLB miss exception occurs HASH1 and HASH2 The HASH1 and HASH2 registers contain the primary and secondary PTEG addresses that correspond to the address causing a TLB miss These PTEG addresses are automatically derived by the MPC603e by performing the primary and secondary hashing function on the contents of IMISS or DMISS for an ITLB or DTLB miss exception respectively RPA The system software loads a TLB entry by loading the second word of the matching PTE entry into the RPA register and then executing the tlbli or tlbId instruction for loading the ITLB or DTLB respectively Instructions tlbli rB Loads the contents of the ICMP and RPA registers into the ITLB entry selected by lt ea gt and SRR1 WAY tlbId rB Loads the contents of the DCMP and RPA registers into the DTLB entry
557. ssary 2 Pass RWITM to RWITM memory queue Store Write No 00x E M M Write data to cache T 0 Store stwex Write No 10x l Same Pass single beat write to Write with flush T 0 memory queue Store stwex Write No 10x E Same 1 Write data to cache T 0 2 Pass single beat write Write with flush to memory queue Store stwex Write No 10x M Same 1 CRTRY write T 0 2 Push block to write Write with kill queue Store T 0 Write No x1x Same Pass single beat write to Write with flush or stwex memory queue WIM 10x Store T 0 Write No x1x E l CRTRY write or stwex WIM 10x Store T 0 Write No x1x M 1 CRTRY write or stwex 7 S 8 7 WIM 10x 2 Push block to write Write with kill queue stwcx Conditional If the reserved bit is set this operation is like other writes except the bus operation write uses a special encoding Chapter 3 Instruction and Data Cache Operation For More Information On This Product Go to www freescale com MEI State Transactions Freescale Semiconductor Inc Table 3 8 MEI State Transitions continued 3 Cache Bus Current Next f Operation Operation Sync WIM State State Cache Actions Bus Operation dcbf Data cache No XXX LE Same 1 CRTRY debf block flush 2 Pass flush Flush Same l 3 State change only dcbf Data cache No XXX M l Push block to write queue Write with
558. ssor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING _ suction Serenity Table 2 42 Translation Lookaside Buffer Management Instructions Name Mnemonic Operand Syntax Load Data TLB Entry tlbId rB Load Instruction TLB Entry tibli rB TLB Invalidate Entry tlbie rB TLB Synchronize tlbsync Because the presence and exact semantics of the translation lookaside buffer management instructions is implementation dependent system software should incorporate uses of the instructions into subroutines to maximize compatibility with programs written for other processors For more information on the PowerPC instruction set refer to Chapter 4 Addressing Modes and Instruction Set Summary and Chapter 8 Instruction Set in the Programming Environments Manual 2 3 7 Recommended Simplified Mnemonics To simplify assembly language programs a set of simplified mnemonics is provided for some of the most frequently used operations such as no op load immediate load address move register and complement register PowerPC compliant assemblers provide the simplified mnemonics listed in Recommended Simplified Mnemonics in Appendix F Simplified Mnemonics in the Programming Environments Manual and listed with some of the instruction descriptions in this chapter Programs written to be portable across the various assemblers for the PowerPC ar
559. ssor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Exception Classes Table 4 3 Exception Priorities continued Exception Se Category Priority Exception Cause Instruction 0 IABR Instruction address breakpoint exception dispatch 8 1 Program Program exception due to the following execution S e Illegal instruction e Privileged instruction e Trap 2 System call System call exception 3 Floating point unavailable Floating point unavailable exception 4 Program Program exception due to a floating point enabled exception 5 Alignment Alignment exception due to the following e Floating point not word aligned e Imw stmw wars or stwex not word aligned Little endian access is misaligned e eciwx or ecowx with misaligned operand PID7T 603e only e Multiple or string access with little endian bit set 6 Data access Data access exception due to a BAT page protection violation 7 Data access Data access exception due to the following eciwx ecowx lwarx or stwex to direct store segment bit 5 of DSISR e Crossing from memory segment to direct store segment bit 0 of DSISR e Crossing from direct store segment to memory segment e Any access to direct store SR T 1 eciwx or ecowx with EAR E 0 bit 11 of DSISR 8 DTLB miss Data TLB miss exception due to e Store miss e Load miss 9 Alignment Alignment exception due
560. store segment SR T 1 Chapter 4 Exceptions For More Information On This Product Go to www freescale com mor Freescale Semiconductor Inc Exception Definitions e The attempted access violates the memory protection defined by SR Ks Kp PTE PP or DBATn PP Note that the OEA specifies an additional case that may cause a DSI exception when an effective address for a load store or cache operation cannot be translated by the TLBs On the MPC603e this condition causes a TLB miss exception instead These scenarios are common among all processors that implement the PowerPC architecture The following additional scenarios can cause a DSI exception in the MPC603e e A bus error indicates crossing from a direct store segment to a memory segment e The execution of any load store instruction to a direct store segment SR T 1 e A data access crosses from a memory segment SR T 0 into a direct store segment SR T 1 DSI exceptions can be generated by load store instructions and the cache control instructions debi dcbz dcbst and debf The MPC603e supports the crossing of page boundaries However if the second page has a translation error or protection violation associated with it the MPC603e takes the DSI exception in the middle of the instruction In this case the data address register DAR always points to a byte address in the first word of the offending page If an stwex instruction has an effective addr
561. structions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 stb 38 S A d stbu 39 S A d stbux 31 S A 247 0 stbx 31 S A 215 0 std 62 S A ds 0 stdu 62 S A ds 1 stdux 31 S A 181 0 stdx 31 S A 149 0 Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com Instructions Grouped by Freescale Semiconductor Inc Table A 14 Integer Store Instructions continued sth 44 S A d sthu 45 S A d sthux 31 S A 439 0 sthx 31 S A 407 0 stw 36 S A d stwu 37 S A d stwux 31 S A 183 0 stwx 31 S A 151 0 1 64 bit instruction Table A 15 Integer Load and Store with Byte Reverse Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Ihbrx 31 D A B 790 0 Iwbrx 31 D A B 534 0 sthbrx 31 S A B 918 0 stwbrx 31 S A B 662 0 Table A 16 Integer Load and Store Multiple Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Imw 1 46 D A d stmw 1 47 S A d 1 Load and store string or multiple instruction Table A 17 Integer Load and Store String Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Iswi 1 31 D A NB 597 0 Iswx 1 31 D A B 533 0 stswi 1 31 S A NB 725 0 stswx 31 S A B 661 0
562. t Go to www freescale com Freescale Semiconductor Inc i Ka Signal Descriptions 7 2 1 3 1 Address Bus Busy ABB Output Following are the state meaning and timing comments for the ABB output State Meaning Timing Comments Asserted Indicates that the MPC603e is the address bus master See Section 8 3 1 Address Bus Arbitration Negated Indicates that the MPC603e is not using the address bus If ABB is negated during the bus clock cycle following a qualified bus grant the MPC603e did not accept mastership even if BR was asserted This can occur if a potential transaction is aborted internally before the transaction is started Assertion Occurs on the bus clock cycle following a qualified BG that is accepted by the processor see Negated Negation Occurs for a minimum of one half bus clock cycle following the assertion of AACK If ABB is negated during the bus clock cycle following a qualified bus grant the MPC603e did not accept mastership even if BR was asserted High Impedance Occurs after ABB is negated 7 2 1 3 2 Address Bus Busy ABB Input Following are the state meaning and timing comments for the ABB input State Meaning Timing Comments Asserted Indicates that the address bus is in use This condition effectively blocks the MPC603e from assuming address bus ownership regardless of the BG input see Section 8 3 1 Address Bus Arbitration Negated Indicates that t
563. t be valid on the same bus clock cycle that TA is asserted 7 2 7 2 Data Bus Parity DP 0 7 The eight DP 0 7 signals on the MPC603e are both output and input signals 7 2 7 2 1 Data Bus Parity DP 0 7 Output Following are the state meaning and timing comments for the DP outputs State Meaning Asserted Negated Represents odd parity for each of 8 bytes of data write transactions Odd parity means that an odd number of bits Chapter 7 Signal Descriptions For More Information On This Product Go to www freescale com ae Freescale Semiconductor Inc Signal Descriptions including the parity bit are driven high The signal assignments are listed in Table 7 7 Timing Comments Assertion Negation The same as DL 0 31 High Impedance The same as DL 0 31 Table 7 7 DP 0 7 Signal Assignments Signal Name Signal Assignments DPO DH 0 7 DP1 DH 8 15 DP2 DH 16 23 DP3 DH 24 31 DP4 DL 0 7 DP5 DL 8 15 DP6 DL 16 23 DP7 DL 24 31 7 2 7 2 2 Data Bus Parity DP 0 7 Input Following are the state meaning and timing comments for the DP inputs State Meaning Asserted Negated Represents odd parity for each byte of read data Parity is checked on all data byte lanes regardless of the size of the transfer Detected even parity causes a checkstop if data parity errors are enabled in the HIDO register See DPE Timing Comments Assertion Negation The same as D
564. t of External Control Instructions The size of the data transfer associated with the eciwx and ecowx instructions is always 4 bytes However if either is misaligned and crosses any word boundary the MPC603e generates two bus operations each smaller than 4 bytes For the first bus operation bits A 29 31 equal bits 29 31 of the effective address of the instruction which is 0b101 0b110 or Ob111 The size associated with the first bus operation will be 3 2 or 1 bytes respectively For the second bus operation bits A 29 31 equal 0b000 and the size associated with the operation is 1 2 or 3 bytes respectively For both operations TBST and TSIZ 0 2 are redefined to specify the resource ID RID The resource ID is copied from bits 28 31 of the EAR For eciwx ecowx operations TBST is high if EAR 28 is set The size of the second bus operation cannot be deduced from the operation itself the system must determine how many bytes were transferred on the first bus operation to determine the size of the second operation Furthermore the two bus operations associated with such a misaligned external control instruction are not atomic That is the MPC603e may initiate other types of memory operations between the two transfers Also the two bus operations associated with a MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Address Bus Tenure misaligne
565. tanding of the features and functions of the PowerPC architecture and the MPC603e This chapter describes the flexible nature of the PowerPC architecture definition and provides an overview of how the PowerPC architecture defines the register set operand conventions addressing modes instruction set cache model exception model and memory management model e Chapter 2 Programming Model provides a brief synopsis of the registers implemented on the MPC603e operand conventions an overview of the PowerPC addressing modes and a list of the instructions implemented by the MPC603e Instructions are organized by function MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Suggested Reading Chapter 3 Instruction and Data Cache Operation provides a discussion of the cache and memory model as implemented on the MPC603e Chapter 4 Exceptions describes the exception model defined in the OEA and the specific exception model implemented on the MPC603e Chapter 5 Memory Management describes MPC603e implementation of the memory management unit specified by the OBA Chapter 6 Instruction Timing provides information about latencies interlocks special situations and various conditions to help make programming more efficient This chapter is of special interest to software engineers and system designers Chapter 7 Sign
566. ted by PID7t 603e Power management Internal voltage supply changed from 3 3 volts to 2 5 volts The core logic of the chip now uses a 2 5 volt supply Instruction timing The integer divide instructions divwu o and divw o execute in 20 clock cycles execution of these instructions in the PID6 603e takes 37 clock cycles Support for single cycle store An adder comparator added to system register unit that allows dispatch and execution of multiple integer add and compare instructions on each cycle Chapter 1 Overview For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Overview Figure 1 1 provides a block diagram of the MPC603e that shows how the execution units IU FPU BPU LSU and SRU operate independently and in parallel Note that this is a conceptual diagram and does not attempt to show how these features are physically implemented on the chip The MPC603e provides address translation and protection facilities including an ITLB DTLB and instruction and data BAT arrays Instruction fetching and issuing is handled in the instruction unit Translation of addresses for cache or external memory accesses are handled by the MMUs Both units are discussed in more detail in Section 1 1 3 Instruction Unit and Section 1 1 5 1 Memory Management Units MMUs 1 1 2 System Design and Programming Considerations The MPC603e is built on the low power dissip
567. ted in the MPC603e 3 3 1 Data Cache Fill A cache block is filled after a read miss or write miss read with intent to modify occurs in the cache The cache block that corresponds to the missed address is updated by a burst transfer of the data from system memory Note that if a read miss occurs in a system with multiple bus masters and the data is modified in another cache the modified data is first written to external memory before the cache fill occurs 3 3 2 Data Cache Cast Out Operation The MPC603e uses an LRU replacement algorithm to determine which of the four possible cache locations should be used for a cache update on a cache miss Adding a new block to MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Ata Cache Transactions on Bus the cache causes any modified data associated with the least recently used element to be written back or cast out to system memory to maintain memory coherence 3 3 3 Cache Block Push Operation When a cache block in the MPC603e is snooped and hit by another bus master and the data is modified the cache block must be written to memory and made available to the snooping device The cache block that is hit is pushed out onto the bus The MPC603e supports two kinds of push operations normal push operations and enveloped high priority push operations described in Section 3 6 9 Enveloped High Priority Ca
568. ted unless the data bus latency causes the third address tenure to be delayed MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Get Timing Examples Note that all bidirectional signals are three stated between bus tenures 1 2 3 4 5 6 7 8 9 10 11 12 Figure 8 14 Fastest Single Beat Reads Chapier 8 System Interface Operation For More Information On This Product Go to www freescale com D Freescale Semiconductor Inc Timing Examples Figure 8 15 illustrates the fastest single beat writes supported by the MPC603e All bidirectional signals are three stated between bus tenures 1 2 3 4 5 6 7 8 9 10 11 12 Figure 8 15 Fastest Single Beat Writes MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc W Timing Examples Figure 8 16 shows three ways to delay single beat reads showing data delay controls e The TA signal can remain negated to insert wait states in clock cycles 3 and 4 e For the second access DBG could have been asserted in clock cycle 6 e In the third access DRTRY is asserted in clock cycle 11 to flush the previous data Note that all bidirectional signals are three stated between bus tenures The pipelining shown in Figure 8 16 can occur if the second access is n
569. tention The snoop access is given first access to the tags The load or store then occurs on the clock following the snoop 1 3 4 Exception Model This section describes the PowerPC exception model and the MPC603e implementation specifically PID7t 603e specific information is noted where applicable 1 3 4 1 PowerPC Exception Model The PowerPC exception mechanism allows the processor to change to supervisor state as a result of external signals errors or unusual conditions arising in the execution of instructions and differs from the arithmetic exceptions defined by the IEEE for floating point operations When exceptions occur information about the state of the processor is saved to certain registers and the processor begins execution at an address exception vector predetermined for each exception type Processing of exceptions occurs in supervisor mode Although multiple exception conditions can map to a single exception vector a more specific condition may be determined by examining a register associated with the exception for example the DSISR and the FPSCR Additionally some exception conditions can be explicitly enabled or disabled by software The PowerPC architecture requires that exceptions be handled in program order therefore although a particular implementation may recognize exception conditions out of order they are presented strictly in order When an instruction caused exception is recognized any unexecuted instruc
570. ter 2 6 Hardware Implementation Registers HIDO and HIDI eee 2 6 Data and Instruction TLB Miss Address Registers RA ER EE 2 10 Data and Instruction TLB Compare Registers DCMP and ICMP 2 10 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Paragraph Number 2 1 2 4 2 1 2 5 2 1 2 6 2 2 GN See 222 2 2 4 225 2 3 2 3 1 2 3 1 1 2 3 1 2 2 3 1 3 2 3 1 4 23 2 2 3 2 1 2 3 2 2 E 2 3 2 4 2 3 2 4 1 2 3 2 4 2 2 3 2 4 3 2 3 3 2 3 4 2 3 4 1 2 3 4 1 1 2 3 4 1 2 2 3 4 1 3 2 3 4 1 4 2342 2 3 4 2 1 2A De 2 3 4 2 3 2 3 4 2 4 2 3 4 2 5 2 3 4 2 6 2 3 4 3 2 3 4 3 1 Didone Freescale Semiconductor Inc Contents Page Title Number Primary and Secondary Hash Address Registers CLAS HUY cari EAS AD EE EE 2 11 Required Physical Address Register RPA 2 12 Instruction Address Breakpoint Register OABR 2 12 Oper nd Conventions aooiee EE 2 13 Floating Point Execution Models UTISA 2 13 Data Organization in Memory and Data Transfers 2 14 Alignment and Misaligned Accesses csscesseceeneeceeeeeceeeeeceeeeecnteeeseeeeees 2 14 Floating Point e EE 2 15 Effect of Operand Placement on Performance cceeeesseceseeeseeeneeeeeeenees 2 15 Instruction Set Summary sicsccdssccalvc siaacaevsiad suas AEN ed de dE ERAN 2 15 Classes 0 INES ERC EE 2 17 Definition of Boundedly Undefned AA 2 17 Defined Instruction Jager ee sd ee Gee B
571. terrupt condition INT asserted if the MSR EE bit is set it ignores the interrupt condition if the MSR EE bit is cleared To guarantee that the external interrupt is taken the INT signal must be held asserted until the MPC603e takes the interrupt If the INT signal is negated before the interrupt is taken the MPC603e is not guaranteed to take an external interrupt The interrupt handler must send a command to the device that asserted INT acknowledging the interrupt and instructing the device to negate INT before the handler re enables recognition of external interrupts 4 5 6 Alignment Exception 0x00600 This section describes conditions that can cause alignment exceptions in the MPC603e The MPC603e implements the alignment exception as it is defined in the PowerPC architecture For information on bit settings and how exception conditions are detected refer to the Programming Environments Manual Note that the PowerPC architecture allows individual processors to determine whether an exception is required to handle various alignment conditions Similar to DSI exceptions alignment exceptions use the SRRO and SRR1 to save the machine state and the DSISR to determine the source of the exception The MPC603e initiates an alignment exception when it detects any of the following conditions e The operand of a floating point load or store operation is not word aligned e The operand of an Imw stmw Iwarx or stwex instruction is not word aligne
572. text synchronizing instruction Also note that care should be taken to avoid modification of the instruction TLB entries that translate current instruction prefetch addresses This is a supervisor level instruction it is also a MPC603e specific instruction and not part of the PowerPC instruction set Other registers altered es None MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc uction Sa tlbli tlbli Load Instruction TLB Entry Integer Unit tibld rB Reserved 31 00000 00000 B 1010 0 0 5 6 10 11 15 16 20 21 30 31 EA rB TLB entry created from ICMP and RPA ITLB entry selected by EA 15 19 and SRR1I WAY lt created TLB entry The EA is the contents of rB The tlbli instruction loads the contents of the instruction PTE compare ICMP and required physical address RPA registers into the first word of the selected instruction TLB entry The specific ITLB entry to be loaded is selected by the EA and SRR1 WAY bit The tlbli instruction should only be executed when address translation is disabled MSR IR 0 and MSR DR 0 Note that it is possible to execute the tlbld instruction when address translation is enabled however extreme caution should be used in doing so If instruction address translation is set MSR IR 1 tlbli must be followed by a context synchronizing instruction such a
573. tgpr gt gt 1 dMiss gt ea that missed j dCmp gt the compare value for the va that missed hashl gt pointer to first hash pteg i hash2 gt pointer to second hash pteg Register usage rO is saved counter ia rl ois junk r2 is pointer to pteg H r3 is current compare value MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor In Ne Table Search Operation csect tlbmiss PR org vec0 0x1200 tlbCeq0 mfspr r2 hashi get first pointer addi ral e O 8 load 8 for counter mfctr ro save counter mfspr r3 dCmp get first compare value addi r2 r2 8 pre dec the pointer ceq0 mtctr rl load counter ceql lwzu rl 8 r2 get next pte cmp ef e e see if found pte bdnzf 0 ceql dec count br if cmp ne and if count not zero bne cEqO0SecHash if not found set up second hash or exit 1 rl 4 r2 load tlb entry lower word andi r3 r1 0x80 check the C bit beq cEqOChkProt if C 0 go check protection modes ceq2 mtctr ro restore counter mfspr r0 dMiss get the miss address for the tlbld mfspr r3 srrl get the saved cr0 bits mtcrf 0x80 r3 restore CRO mtspr rpa r1 set the pte tlbld ro load the dtlb rfi return to executing program 4 Register usage rO is saved counter H rl is junk r2 is pointer to pteg r3 is current compare value cEqO0SecHash andi rl r3 0x0040 s if we have done second hash bne doDSI if so go to D
574. th Freescale processors MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Conventions e Documentation for support chips These include the following MPC106 PCI Bridge Memory Controller User s Manual MPC106UM AD MPC107 PCI Bridge Memory Controller Technical Summary MPC107TS D MPCI107 PCI Bridge Memory Controller User s Manual MPC107UM AD Additional literature is published as new processors become available For a current list of documentation refer to http www mot com semiconductors Conventions This document uses the following notational conventions cleared set mnemonics italics 0x0 0b0 rA rB FA rD frA frB frC frD REG FIELD When a bit takes the value zero it is said to be cleared when it takes a value of one it is said to be set Instruction mnemonics are shown in lowercase bold Italics indicate variable command parameters for example bectrx Book titles in text are set in italics Prefix to denote hexadecimal number Prefix to denote binary number Instruction syntax used to identify a source GPR Contents of a specified GPR or the value zero Instruction syntax used to identify a destination GPR Instruction syntax used to identify a source FPR Instruction syntax used to identify a destination FPR Abbreviations for registers are shown in uppercase text Specific bits fields or
575. that an mtspr instruction that updates the IABR be followed by a context synchronizing instruction If the mtspr instruction enables the instruction address breakpoint exception the context synchronizing instruction cannot generate a breakpoint response The MPC603e also cannot block a breakpoint response on the context synchronizing instruction if the breakpoint was disabled by the mtspr instruction See Synchronization Requirements for Special Registers and TLBs in Chapter 2 Register Set in the Programming Environments Manual for more information on this requirement Table 4 19 Breakpoint Action for Multiple Modes Enabled for the Same Address IABR IE MSR BE MSR SE First Action Next Action Comments 1 1 0 Instruction Trace branch Enabling both modes is useful only if both address trace and address breakpoint interrupts are needed 1 0 1 Instruction Trace Enabling both modes is useful only if different address single step breakpoint actions are required breakpoint 0 1 1 Trace branch None The action for branch trace and single step trace is the same Enabling both trace modes is redundant except for hard stop on branches 1 1 1 Instruction Trace Enabling all modes is redundant This entry is address for clarification only breakpoint Chapter 4 Exceptions For More Information On This Product Go to www freescale com mor Freescale Semiconductor Inc Exception
576. the MPC603e handles alignment and misaligned accesses e The MPC603e provides hardware support for some misaligned memory accesses However misaligned accesses suffer a performance degradation compared to aligned accesses of the same type MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor ING uction PE e The MPC603e does not provide hardware support for floating point load store operations that are not word aligned In such a case the MPC603e invokes an alignment exception and the exception handler must break up the misaligned access For this reason floating point single and double word accesses should always be word aligned Note that a floating point double word access on a word aligned boundary requires an extra cycle to complete Any half word word double word and string reference access that crosses an alignment boundary must be broken into multiple discrete accesses For string accesses the hardware makes no attempt to get aligned to reduce the number of accesses Multiple word accesses are architecturally required to be aligned The resulting performance degradation depends upon how well each individual access behaves with respect to the memory hierarchy At a minimum additional cache access cycles are required More dramatically each discrete access to a noncacheable page involves an individual bus operation that reduces the effective bus b
577. the MPC603e is free to take data bus mastership It is not sampled until TS is asserted Negation May occur at any time to indicate the MPC603e cannot assume data bus mastership 7 2 6 2 Data Bus Write Only DBWO Input Following are the state meaning and timing comments for the DBWO input State Meaning Timing Comments Asserted Indicates that the MPC603e may run the data bus tenure for an outstanding write address even if a read address is pipelined before the write address Refer to Section 8 10 Using DBWO for detailed instructions for using DBWO Negated Indicates that the MPC603e must run the data bus tenures in the same order as the address tenures Assertion Must occur no later than a qualified DBG for an outstanding write tenure DBWO is only recognized by the MPC603e on the clock of a qualified DBG If no write requests are pending the MPC603e ignores DBWO and assumes data bus ownership for the next pending read request Negation May occur any time after a qualified DBG and before the next assertion of DBG Chapter 7 Signal Descriptions For More Information On This Product Go to www freescale com ae Freescale Semiconductor Inc Signal Descriptions 7 2 6 3 Data Bus Busy DBB The DBB signal is both an input and output signal on the MPC603e 7 2 6 3 1 Data Bus Busy DBB Output Following are the state meaning and timing comments for the DBB output State Meaning As
578. the PLL configuration signals Chapter 1 Overview For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Implementation Specific Information SUPERVISOR MODEL Configuration Registers Hardware Implementation Registers Register HIDO SPR 1008 SPR 287 HID1 SPR 1009 Memory Management Registers Software Table Search Registers SPR 976 SPR 977 SPR 978 SPR 979 SPR 980 SPR 981 SPR 982 USER MODEL Machine State Processor Version Register MSR General Purpose Registers Instruction BAT Registers IBATOU IBATOL IBAT1U IBATIL IBAT2U IBAT2L IBAT3U IBAT3L Data BAT Registers SPR 528 SPR 529 SPR 530 SPR 531 SPR 532 SPR 533 SPR 534 SPR 535 DBATOU DBATOL DBAT1U DBAT1L DBAT2U DBAT2L DBAT3U DBAT3L SPR 536 SPR 537 SPR 538 SPR 539 SPR 540 SPR 541 SPR 542 SPR 543 Floating Point Registers Segment Registers SDR1 SDR1 SPR 25 Condition Register CR Floating Point Status and Control Register FPSCR Exception Handling Registers DSISR DSISR SPR18 Save and Restore Registers zs Data Address Register DAR SPR 19 SPRGs XER XER SPR 272 SPR 273 SPR 274 SPR 275 SPR 1 SRR1 SPR 27 Link Register LR SPR 8 Count Register CTR SPR 9 Time Base Facility For Reading Time Base Facility For Writing Instruction Address Miscellaneous Registers Decrementer External Address TBL TBR 268 i i 1 Regist
579. the PowerPC architecture instruction codings that are now illegal may become assigned to instructions in the architecture or may be reserved by being assigned to processor specific instructions 2 3 1 1 Definition of Boundedly Undefined If instructions are encoded with incorrectly set bits in reserved fields the results on execution can be said to be boundedly undefined If a user level program executes the incorrectly coded instruction the resulting undefined results are bounded in that a spurious change from user to supervisor state is not allowed and the level of privilege exercised by the program in relation to memory access and other system resources cannot be exceeded Boundedly undefined results for a given instruction may vary between implementations and between execution attempts in the same implementation 2 3 1 2 Defined Instruction Class Defined instructions are guaranteed to be supported in all implementations of the Power PC architecture except as stated in the instruction descriptions in Chapter 8 Instruction Set in the Programming Environments Manual The MPC603e provides hardware support for all instructions defined for 32 bit implementations Chapter 2 Programming Model For More Information On This Product Go to www freescale com Instruction Set Summary Freescale Semiconductor Inc A processor of this family invokes the illegal instruction error handler part of the program exception when it encounte
580. the floating point unavailable exception handler e The execution of an instruction that causes a floating point exception while exceptions are enabled in the MSR invokes the program exception handler Exceptions caused by asynchronous events are described in Chapter 4 Exceptions 2 3 3 Instruction Set Overview This section provides a brief overview of the PowerPC instructions implemented in the MPC603e and highlights any special information with respect to how the MPC603e implements a particular instruction Note that the categories used in this section correspond to those used in Chapter 4 Addressing Modes and Instruction Set Summary in the Programming Environments Manual These categorizations are somewhat arbitrary and are provided for the convenience of the programmer and do not necessarily reflect the PowerPC architecture specification Note that some of the instructions have the following optional features e CR Update tThe dot suffix on the mnemonic enables the update of the CR e Overflow option The o suffix indicates that the overflow bit in the XER is enabled 2 3 4 PowerPC UISA Instructions The UISA includes the base user level instruction set excluding a few user level cache control synchronization and time base instructions user level registers programming model data types and addressing modes This section discusses the instructions defined in the UISA 2 3 4 1 Integer Instructions This sec
581. the page tables in memory Note that because the implementation of TLBs is optional the instructions that refer to these structures are also optional However because these structures serve as caches of the page table the architecture specifies a software protocol for maintaining coherency between these caches and the tables in memory whenever changes are made to the tables in memory When the tables in memory are changed the operating system purges these caches of the corresponding entries allowing the translation caching mechanism to refetch from the tables when the corresponding entries are required Note that the MPC603e implements all TLB related instructions except tlbia which is treated as an illegal instruction The MPC603e also uses some implementation specific instructions to load two on chip TLBs Because the MMU specification for these processors is so flexible it is recommended that the software that uses these instructions and registers be encapsulated into subroutines to minimize the impact of migrating across the family of implementations Table 5 5 summarizes MPC603e instructions that specifically control the MMU For more detailed information about the instructions refer to Chapter 2 Programming Model in this book and Chapter 8 Instruction Set in the Programming Environments Manual Table 5 5 Instruction Summary MMU Control Instruction Description misr SR rS Move to Segment Register
582. ther in the same bus clock this is a qualified snooping condition No snoop update to the MPC603e cache occurs if the snooped transaction is not marked global Also because cache block cast outs and snoop pushes do not require snooping the GBL signal is not asserted for these operations When the MPC603e detects a qualified snoop condition the address associated with the TS signal is compared with the cache tags Snooping finishes if no hit is detected If however the address hits in the cache the MPC603e reacts according to the MEI protocol shown in Figure 3 4 To facilitate external monitoring of the internal cache tags the cache set entry signals CSE 0 1 represent in binary the cache set being replaced on read operations including read with intent to modify operations The CSE 0 1 signals do not apply for write operations to memory or during noncacheable or touch load operations Note that these signals are valid only for MPC603e burst operations Table 3 3 shows the CSE 0 1 cache set entry encodings Table 3 3 CSE 0 1 Signal Encoding CSE 0 1 Cache Set Element 00 Set 0 01 Set 1 10 Set 2 11 Set 3 MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor INg orency ME Protocol 3 6 4 Coherency Precautions The MPC603e supports a three state coherency protocol that supports the modified exclusive and inva
583. thm 5 27 software routines 5 31 software routines for the MPC603e 5 36 5 46 SRR1 bit settings 4 10 table search flow primary and secondary 5 29 TBEN signal 7 27 TBST signal 7 12 8 13 8 23 TCn signals 7 13 8 19 TEA signal 7 22 8 27 Termination 8 19 8 24 TGPRO GPR3 registers 5 32 Throughput 6 3 Timing diagrams interface address transfer signals 8 11 burst transfers with data delays 8 35 single beat reads 8 31 single beat reads with data delays 8 33 single beat writes 8 32 single beat writes with data delays 8 34 use of TEA 8 36 using DBWO 8 43 Timing instruction BPU execution timing 6 17 branch timing example 6 20 cache arbitration 6 10 cache hit 6 10 6 11 6 14 FPU execution timing 6 21 instruction dispatch 6 15 instruction flow 6 8 instruction scheduling guidelines 6 24 IU execution timing 6 21 latency summary 6 26 load store unit execution timing 6 22 overview 6 3 SRU execution timing 6 22 stage definition 6 2 TLB description 5 24 invalidate A 24 invalidate tlbie instruction 5 26 5 47 TLB management instructions 2 47 A 24 TLBISYNC signal 7 27 Trace exception 4 29 Transactions data cache 3 9 Transfer 8 11 8 23 Trap instructions 2 38 TS signal 7 6 8 11 TSIZn signals 7 12 8 13 TTn signals 7 9 8 12 U Use of TEA timing 8 36 User mode 4 1 User instruction set architecture UISA xxvii 1 15 2 2 User level registers summary 2 2 Using DBWO timing
584. ting of this bit specifies whether an exception vector offset is prepended with Fs or Os In the following description nnnnn is the offset of the exception See Table 4 2 0 Exceptions are vectored to the physical address 0x000n_nnnn 1 Exceptions are vectored to the physical address OxFFFn_nnnn 26 Instruction address translation 0 Instruction address translation is disabled 1 Instruction address translation is enabled See Chapter 5 Memory Management 27 DR Data address translation 0 Data address translation is disabled 1 Data address translation is enabled See Chapter 5 Memory Management 28 29 Reserved Full function 30 RI Recoverable exception for system reset and machine check exceptions 0 Exception is not recoverable 1 Exception is recoverable 31 LE Little endian mode enable 0 The processor runs in big endian mode 1 The processor runs in little endian mode The IEFE floating point exception mode bits FEO and FE1 together define whether floating point exceptions are handled precisely imprecisely or if they are taken at all The possible settings and default conditions for the MPC603e are shown in Table 4 7 For further details see Chapter 6 Exceptions of the Programming Environments Manual MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Except
585. tion and data MMUs respectively The instruction addresses shown in Figure 5 2 are generated by the processor for sequential instruction fetches and addresses that correspond to a Chapter 5 Memory Management For More Information On This Product Go to www freescale com MMU Features Freescale Semiconductor Inc change of program flow Data addresses shown in Figure 5 3 are generated by load and store instructions and by cache instructions As shown in the figures after an address is generated the higher order bits of the effective address EAOQ EA 19 or a smaller set of address bits EAO EAn in the cases of blocks are translated into physical address bits PAO PA19 The lower order address bits A20 A31 are untranslated and therefore identical for both effective and physical addresses After translating the address the MMUs pass the resulting 32 bit physical address to the memory subsystem In addition to the higher order address bits the MMUs automatically keep an indicator of whether each access was generated as an instruction or data access and a supervisor user indicator that reflects the state of the PR bit of the MSR when the effective address was generated In addition for data accesses there is an indicator of whether the access is for a load or a store operation This information is then used by the MMUs to appropriately direct the address translation and to enforce the protection hierarchy programmed by the ope
586. tion Register 0 HIDO 00 ee ceeeeeeeeereeenneeeeenees 2 3 Hardware Implementation Register 1 HID oo eee eeeeeeneeeneeeeeeetees 2 4 DMISS and IMISS Registers jc Aud a at nii o E ERTA 2 5 DCMP E 2 6 HASH1 and HASH2 ett eer eege EE 2 7 Required Physical Address Register RPA ceeeceesceesseceseceseeeeseeceneenseesees 2 8 Instruction Address Breakpoint Register OARR 3 1 Instruction Cache Organization Sesteeee dees eetaeeitet deaveuassdenyhcsdeaedonntdedqued Sevecceeades 3 2 Data ache Organiza OU ess ees dE 3 3 Double Word Address Ordering Critical Double Word First ee 3 4 MEI Cache Coherency Protocol State Diagram WIM 001 eee 3 5 Bus Interface Elend EEN 4 Machine Status Save Restore Register 0 SSRO c ce eeeeeeeecceceeeeeeeneeeenteeeenes 4 2 Machine Status Save Restore Register 1 SSR1 oo eee eeeeceeeeeeeeeeseeeenteeeenes 4 3 Machine State Register MSR 532 cahivege eats Gia ee BA ae ee 5 1 MMU Conceptual Block Diagram 32 Bit Implementatons eee 5 2 IMMU Block Dette eegene eege e 5 3 DIMMU Block Dias tains EE 5 4 Address Translation Types lt icisccicdasdesstacsidscddacasveniedvsaccees Eed shaaaeabteceevaessacts 5 5 General Flow of Address Translation Real Addressing Mode and Block 5 6 General Flow of Page and Direct Store Interface Address Translation 5 7 Segment Register and TLB Organization ee eee esseceseeeseeeeeeceaeceseesseeeenees 5 8 Page Address Translat
587. tion by allowing previously issued instructions to complete before returning to the interrupted process In general execution of the rfi instruction ensures the following All previous instructions have completed to a point where they can no longer cause an exception If a previous instruction causes a direct store interface error exception the results must be determined before this instruction is executed MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc EA Process Switching e Previous instructions complete execution in the context privilege protection and address translation under which they were issued e The rfi instruction copies SRR1 bits back into the MSR e The instructions following this instruction execute in the context established by this instruction For a complete description of context synchronization refer to Chapter 6 Exceptions of the Programming Environments Manual 4 3 Process Switching The operating system should execute one of the following when processes are switched e The sync instruction which orders the effects of instruction execution All instructions previously initiated appear to have completed before the syne instruction completes and no subsequent instructions appear to be initiated until the sync instruction completes For an example showing use of the sync instruction see Chapter 2 Regist
588. tion can be disabled so the condition causes the processor to go directly into the checkstop state These exceptions cannot be delayed and do not wait for the completion of any precise exception handling 2 Synchronous precise exceptions are caused by instructions and are taken in strict program order 3 Maskable asynchronous exceptions for example external interrupt and decrementer exceptions are delayed until higher priority exceptions are taken System reset and machine check exceptions may occur at any time and are not delayed even if an exception is being handled As a result state information for the interrupted exception may be lost therefore these exceptions are typically nonrecoverable All other exceptions have lower priority than system reset and machine check exceptions and the exception may not be taken immediately when it is recognized 4 1 1 Exception Priorities The exceptions are listed in Table 4 3 in order of highest to lowest priority Table 4 3 Exception Priorities Ga Priority Exception Cause Asynchronous 0 System reset HRESET or power on reset 1 Machine check TEA MCP APE or DPE 2 System reset SRESET 3 System management SMI interrupt 4 External interrupt INT 5 Decrementer exception Decrementer passed through 0x00000000 Instruction fetch 0 ITLB miss Instruction TLB miss 1 Instruction access Instruction access exception MPC603e RISC Microproce
589. tion describes the integer instructions These consist of the following e Integer arithmetic instructions e Integer compare instructions MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor e Integer logical instructions e Integer rotate and shift instructions Integer instructions use the content of the GPRs as source operands and place results into GPRs into the XER and into condition register CR fields 2 3 4 1 1 Table 2 10 lists the integer arithmetic instructions for the MPC603e Table 2 10 Integer Arithmetic Instructions Integer Arithmetic Instructions Inc Gastruction Set Summary Name Mnemonic Operand Syntax Add add add addo addo rD rA rB Add Carrying addc addc addco addco rD rA rB Add Extended adde adde addeo addeo rD rA rB Add Immediate addi rD rA SIMM Add Immediate Carrying addic rD rA SIMM Add Immediate Carrying and Record addic rD rA SIMM Add Immediate Shifted addis rD rA SIMM Add to Minus One Extended addme addme addmeo addmeo rD rA Add to Zero Extended addze addze addzeo addzeo rD rA Divide Word divw divw divwo_ divwo rD rA rB Divide Word Unsigned divwu divwu divwuo divwuo rD rA rB Multiply High Word mulhw mulhw rD rA rB Multiply High Word Unsigned mulhwu mulhwu rD rA rB Multiply Low mullw mullw mullwo mull
590. tion or data miss and SRR1 L S identifies a load or store miss SRR1I WAY identifies the associativity class of the TLB entry selected for replacement by the LRU algorithm The software can change this value effectively overriding the replacement algorithm The SRR1I KEY bit is used by the table search software to determine if there is a protection violation associated with the access useful on data write misses for determining if the C bit should be updated in the table Table 5 10 summarizes the SRR1 bits updated whenever one of the three TLB miss exceptions occurs Table 5 10 Implementation Specific SRR1 Bits Bits Name Function 0 3 CRFO Condition register field 0 bits 12 KEY Key for TLB miss either Ks or Kp from segment register depending on whether the access is a user or Supervisor access 13 DI Set if instruction TLB miss 14 WAY Next TLB set to be replaced set per LRU 15 S L Set if data TLB miss was for a load instruction The key bit saved in SRR1 is derived as follows Select KEY from segment register If MSR PR 0 KEY Ks If MSR PR 1 KEY Kp The rest of this section describes the format of the implementation specific SPRs used by the TLB miss exception handlers These registers can be accessed by supervisor level instructions only Because DMISS IMISS DCMP ICMP HASH1 HASH2 and RPA are used to access the translation tables for software table search operations they should onl
591. tion should only be used to flag fatal system conditions to the processor such as parity or uncorrectable ECC errors D ehr 2 3 4 5 6 7 8 amp 8 3 Bus Clock ST qual_dbg os aK AD ee TA DRTRY Figure 8 12 Read Burst with TA Wait States and DRTRY After the MPC603e has committed to run a transaction that transaction must eventually complete Address retry causes the transaction to be restarted TA wait states and DRTRY assertion for reads delay termination of individual data beats Eventually however the system must either terminate the transaction or assert the TEA signal and vector the MPC603e into a machine check exception For this reason care must be taken to check for the end of physical memory and the location of certain system facilities to avoid memory accesses that result in the generation of machine check exceptions Note that TEA generates a machine check exception depending on MSR ME Clearing the machine check exception enable control bits leads to a true checkstop condition instruction execution halted and processor clock stopped 8 4 5 Memory Coherency MEIl Protocol The MPC603e provides dedicated hardware to provide memory coherency by snooping bus transactions The address retry capability enforces the three state MEI cache coherency protocol see Figure 8 13 The global GBL output signal indicates whether the current transaction must be snooped by other snooping devices on the bus A
592. tions that appear earlier in the instruction stream including any that have not yet entered the execute stage are required to complete before the exception is taken Any exceptions caused by those instructions are handled first Likewise exceptions that are asynchronous and precise are recognized when they occur but are not handled until the MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc snecitic Information instruction currently in the completion stage successfully completes execution or generates an exception and the completed store queue is emptied Unless a catastrophic condition causes a system reset or machine check exception only one exception is handled at a time If for example a single instruction encounters multiple exception conditions those conditions are handled sequentially After the exception handler handles an exception the instruction execution continues until the next exception condition is encountered However in many cases there is no attempt to re execute the instruction This method of recognizing and handling exception conditions sequentially guarantees that exceptions are recoverable Exception handlers should save the information stored in SRRO and SRR1 early to prevent the program state from being lost due to a system reset or machine check exception or to an instruction caused exception in the exception handler and b
593. tiply Add Instructions Name Mnemonic Operand Syntax Floating Multiply Add Double Precision fmadd fmadd frD frA frC frB Floating Multiply Add Single fmadds fmadds frD frA frC frB Floating Multiply Subtract Double Precision fmsub fmsub frD frA frC frB Floating Multiply Subtract Single fmsubs fmsubs frD frA frC frB Floating Negative Multiply Add Double Precision fnmadd fnmadd frD frA frC frB Floating Negative Multiply Add Single fnmadds fnmadds frD frA frC frB Floating Negative Multiply Subtract fnmsub fnmsub frD frA frC frB Double Precision Floating Negative Multiply Subtract Single fnmsubs fnmsubs frD frA frC frB Implementation Note Single precision multiply type instructions operate faster than their double precision equivalents See Chapter 6 Instruction Timing for more information Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary 2 3 4 2 3 Floating Point Rounding and Conversion Instructions The Floating Round to Single Precision frsp instruction is used to truncate a 64 bit double precision number to a 32 bit single precision floating point number The floating point conversion instructions convert a 64 bit double precision floating point number to a 32 bit signed integer number The PowerPC architecture defines bits 0 31 of floating point register f
594. tivation Method Full Power Wake Up Method Full power All units active Full power Requested logic by demand By instruction dispatch with DPM Doze e Bus snooping Controlled by SW External asynchronous exceptions e Data cache as needed Decrementer interrupt e Decrementer timer Reset Nap Decrementer timer Controlled by hardware and External asynchronous exceptions software Decrementer interrupt Reset Sleep None Controlled by hardware and External asynchronous exceptions software Reset 9 3 1 Power Management Modes The following sections describe the characteristics of the MPC603e power management modes the requirements for entering and exiting the various modes and the system capabilities provided by the MPC603e while the power management modes are active 9 3 1 1 Full Power Mode with DPM Disabled Full power mode with DPM disabled is selected when the DPM enable bit in HIDO 11 is cleared The following characteristics apply e Default state following power up and HRESET e All functional units are operating at full processor speed at all times 9 3 1 2 Full Power Mode with DPM Enabled Full power mode with DPM enabled HIDO 11 1 provides on chip power management without affecting the functionality or performance of the MPC603e as follows e Required functional units are operating at full processor speed e Functional units are clocked only when needed e No software or hardware intervention required after
595. to www freescale com Paragraph Number T 2913 7 2 10 7 2 11 7 2 12 7 2 12 1 7 2 12 2 7 2 12 3 7 2 13 8 1 8 1 1 8 1 2 8 1 2 1 8 1 3 8 2 8 2 1 8 2 2 8 3 8 3 1 8 3 2 8 3 2 1 8 3 2 2 8 3 2 2 1 8 3 2 2 2 8 3 2 3 8 3 2 4 8 3 2 5 8 3 2 5 1 8 3 2 6 8 3 3 8 4 8 4 1 8 4 1 1 8 4 2 8 4 3 8 4 4 8 4 4 1 8 4 4 2 8 4 4 3 Freescale Semiconductor Inc Contents Page Title Number TEBI Syne MEBESY ING EEN 7 27 COP Scan et EE 7 27 Pipeline Tracking Support E 7 28 ClOCK Signal Sirenian nnn n SEENEN a 7 29 System Clock SYSCLK In put eee ceeceeceeneeceeeeeceneeeceneeeenteeeenaeeees 7 29 Test Clock CLK_OUT Outputs cesicisecssccassncdssascevedaatoevacdatsaceetassecetace 7 30 PLL Configuration PLL_CFG 0 3 Input eee eee eeeeeeeeseeeeeteeeeeees 7 30 Power and Ground EE 7 32 Chapter 8 System Interface Operation huerteg tere EE Eed 8 1 Operation of the Instruction and Data Caches ccceescceeeseeeesteceesteeeenteeeenes 8 2 Operation oF the System Interface eegene dee 8 4 Optional 32 Bit Data Bus Mode ysis sisissssecssaccsssasaesssesdeaeasdensdevarscceds Ed de 8 5 Dir ct Stor ACCESSCS eeleren 8 6 Memory Access Protocoles eannan Deele 8 6 Arbitration Sis tial Shon 2 sheets ee eeeleg 8 7 Address Pipelining and Split Bus Transactons 8 8 PCORE SS HEEN 8 9 Address Bus Arbitration 2i e des say ese dueectet cats Cezeseysatonytaviccehivegted suyacseet dea sheluagetnees 8 9 Address Transfer
596. to a dcbz to a write through or caching inhibited page 10 Data access Data access exception due to TLB page protection violation 11 DTLB miss Data TLB miss exception due to a change bit not set ona store operation Post instruction 0 Trace Trace exception due to the following execution e MSR SE 1 e MSR BE 1 for branches Exception priorities are described in detail in Exception Priorities in Chapter 6 Exceptions in the Programming Environments Manual Chapter 4 Exceptions For More Information On This Product Go to www freescale com Exception Classes Freescale Semiconductor Inc 4 1 2 Summary of Front End Exception Handling The following list of interrupt categories describes how the MPC603e handles exceptions up to the point of signaling the appropriate exception to occur Note that a recoverable state is reached if the completed store queue is empty drained not canceled and any instruction that is next in program order and has been signaled to complete has completed If MSR RI is clear the MPC603e is in a nonrecoverable state by default Also completion of an instruction is defined as performing all architectural register writes associated with that instruction and then removing that instruction from the completion buffer queue Asynchronous nonmaskable nonrecoverable system reset caused by the assertion of either HRESET or internally during power on reset POR These exceptions ha
597. to maximize performance through efficient use of the PowerPC instruction set and register model The multiple independent execution units allow compilers to optimize instruction throughput Compilers that take advantage of the flexibility of the PowerPC architecture can additionally optimize system performance MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc specitic Information The following sections summarize the features of the MPC603e including both those that are defined by the architecture and those that are unique to the various MPC603e implementations Specific features of the MPC603e are listed in Section 1 1 1 Features 1 3 1 Programming Model The PowerPC architecture defines register to register operations for most computational instructions Source operands for these instructions are accessed from the registers or are provided as immediate values embedded in the instruction opcode The three register instruction format allows specification of a target register distinct from the two source operands Load and store instructions transfer data between registers and memory The MPC603e has two levels of privilege supervisor mode of operation typically used by the operating system and user mode of operation used by the application software The programming models incorporate 32 GPRs 32 FPRs special purpose registers SPRs and
598. to synchronize both pipelined and split transaction bus organizations Individual DBG and DBWO signals provide a primitive form of source level tagging for the granting of the data bus Note that use of DBWO allows some operation level tagging with respect to the MPC603e and the use of the data bus MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 9 Power Management The MPC603e microprocessor is the first microprocessor specifically designed for low power operation It provides both automatic and program controllable power reduction modes for progressive reduction of power consumption This chapter describes the hardware support provided by the MPC603e for power management 9 1 Overview The MPC603e has explicit power management features that are described in this chapter Note that the design of the MPC603e is fully static allowing the internal processor state to be preserved when no internal clock is present The PID7t 603e implementation offers the following enhancements to the original MPC603e family e Lower power design e 2 5 volt core and 3 3 volt I O The device drivers must be modified for power management as operating systems service T O requests by system calls to the device drivers When a device driver is called to reduce the power of a device it needs to be able to check the power state of the device save the d
599. to the completion writeback pipeline stage and discontinues instruction execution until the exception is handled The exception is not signaled until that instruction is the next to be completed Execution of most floating point instructions is pipelined within the FPU allowing up to three instructions to be executing in the FPU concurrently The FPU pipeline stages are multiply add and round convert The LSU has two pipeline stages The first stage is for effective address calculation and MMU translation and the second is for accessing data in the cache e The complete writeback pipeline stage maintains the correct architectural machine state and transfers the contents of the rename registers to the GPRs and FPRs as MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc necitic Information instructions are retired If the completion logic detects an instruction causing an exception all following instructions are canceled their execution results in rename registers are discarded and instructions are fetched from the correct instruction stream A superscalar processor issues multiple independent instructions into multiple pipelines allowing instructions to execute in parallel The MPC603e has five independent execution units one each for integer instructions floating point instructions branch instructions load store instructions and system register inst
600. to the execution unit The register files and rename register have sufficient bandwidth to allow dispatch of two instructions per clock under most conditions The MPC603e BPU decodes and executes branches immediately after they are fetched When a conditional branch cannot be resolved due to a CR data dependency the branch direction is predicted and execution continues from the predicted path If the prediction is incorrect the following steps are taken 1 The instruction queue is purged and fetching continues from the correct path 2 Any instructions ahead of the predicted branch in the CQ are allowed to complete Chapter 6 Instruction Timing For More Information On This Product Go to www freescale com rae EN Freescale Semiconductor Inc Timing Considerations 3 Instructions after the mispredicted branch are purged 4 Dispatching resumes from the correct path After an execution unit executes an instruction it places resulting data into the appropriate GPR or FPR rename register The results are then stored into the correct GPR or FPR during the write back stage If a subsequent instruction needs the result as a source operand it is made available simultaneously to the appropriate execution unit which allows a data dependent instruction to be decoded and dispatched without waiting to read the data from the register file Branch instructions that update either the LR or CTR write back their results in a similar fashion The fo
601. truction that caused the exception and the address to return to when a Return from Interrupt rfi instruction is executed The machine status save restore register 1 SRR1 is used to save machine status on exceptions and to restore machine status when an rfi instruction is executed The SPRGO SPRG3 registers are provided for operating system use The external access register EAR controls access to the external control facility through the External Control In Word Indexed eciwx and External Control Out Word Indexed ecowx instructions The time base register TB is a 64 bit register that maintains the time of day and operates interval timers It consists of two 32 bit fields time base upper TBU and time base lower TBL The processor version register PVR is a read only register that identifies the version model and revision level of the processor Block address translation BAT arrays The PowerPC architecture defines 16 BAT registers four pairs of data BATs DBATs and four pairs of instruction BATs IBATs See Figure 1 2 for a list of the SPR numbers for the BAT arrays The following supervisor level SPRs are implementation specific not defined in the PowerPC architecture DMISS and IMISS are read only registers that are loaded automatically on an instruction or data TLB miss HASH1 and HASH contain the physical addresses of the primary and secondary page table entry groups PTEGs ICMP and DCMP contain a dupl
602. tructions 2 32 A 20 integer load 2 30 integer multiple instructions 2 32 A 20 integer store 2 31 string instructions 2 33 A 20 memory control 2 41 2 45 3 22 A 23 memory synchronization 2 38 2 41 A 21 MPC603e instructions not implemented B 1 MPC603e specific instructions 2 47 PowerPC instructions list form format A 25 function A 15 legend A 36 mnemonic A 1 opcode A 8 processor control 2 38 2 40 2 44 A 23 reserved instructions 2 19 segment register manipulation 2 46 A 24 simplified mnemonics 2 47 supervisor level cache management 2 45 support for lwarx stwex 8 41 system linkage 2 43 A 22 TLB management instructions 2 46 A 24 trap instructions 2 38 A 23 INT signal 7 23 8 40 Integer arithmetic instructions 2 23 A 15 Integer compare instructions 2 24 A 16 Integer load instructions 2 30 A 19 Integer logical instructions 2 24 A 16 Integer multiple instructions 2 32 A 20 Integer rotate and shift instructions 2 25 A 16 Integer store instructions 2 31 A 19 Integer unit execution timing 6 21 latency integer instructions 6 28 overview 1 9 Interrupt external 4 23 Interrupt see Exceptions K Kill block operation 3 20 L Latency 6 2 6 26 8 23 Load operations memory coherency actions 3 19 Load store address generation 2 30 2 34 byte reverse instructions 2 32 A 20 floating point load instructions 2 34 A 21 floating point move instructions 2 29 A 22 floating p
603. tructions to be combined for write through accesses except when the store instructions are separated by a sync or eieio instruction the MPC603e does not implement this combined store capability Note that a store operation that uses the write through attribute may cause any part of valid data in the cache to be written back to main memory Chapter 3 Instruction and Data Cache Operation For More Information On This Product Go to www freescale com Memory ManagementCache EES Mt se Semaine tor Inc The definition of the external memory location to be written to in addition to the on chip cache depends on the implementation of the memory system and can be illustrated by the following examples e RAM The store is sent to the RAM controller to be written into the target RAM e HO device The store is sent to the memory mapped I O control hardware to be written to the target register or memory location In systems with multilevel caching the store must be written to at least a depth in the memory hierarchy that is seen by all processors and devices Accesses that correspond to W 0 are considered write back For this case although the store operation is performed to the cache it is only made to external memory when a copy back operation is required Use of the write back mode W 0 can improve overall performance for areas of the memory space that are seldom referenced by other masters in the system 3 5 2 Caching Inhib
604. ture defines 32 user level GPRs These registers are either 32 bits wide in 32 bit microprocessors or 64 bits wide in 64 bit microprocessors The GPRs serve as the data source or destination for all integer instructions 1 3 1 4 Floating Point Registers FPRs The PowerPC architecture also defines 32 user level 64 bit FPRs The FPRs serve as the data source or destination for floating point instructions These registers can contain data objects of either single or double precision floating point formats 1 3 1 5 Condition Register CR The CR is a 32 bit user level register that provides a mechanism for testing and branching It consists of eight 4 bit fields that reflect the results of certain operations such as move integer and floating point comparisons arithmetic and logical operations 1 3 1 6 Floating Point Status and Control Register FPSCR The user level FPSCR contains all floating point exception signal bits exception summary bits exception enable bits and rounding control bits needed for compliance with the IEEE 754 standard Chapter 1 Overview For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Implementation Specific Information 1 3 1 7 Machine State Register MSR The MSR is a supervisor level register that defines the state of the processor The contents of this register are saved when an exception is taken and restored when the exception handling completes Th
605. uction MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc utes Exception Definitions The soft stop feature can be enabled only through the COP interface With soft stop enabled the MPC603e stops in a restartable state while with hard stop enabled the MPC603e stops immediately without attempting to reach a restartable state Upon restarting from a soft stop the matching instructions are executed and completed unless it generates an exception For soft stops the next ten instructions that could have passed the IABR check can be monitored only by single stepping the processor When soft stops are used the address compare must be separated by at least ten instructions If soft stop is enabled only one soft stop is generated before completion of an instruction with an IABR match regardless of whether a soft stop is generated before that instruction for any other reason such as trace mode on for the preceding instruction or a COP soft stop request Table 4 19 shows the priority of actions taken when more than one mode is enabled for the same instruction Note that a trace or instruction address breakpoint exception condition generates a soft stop instead of an exception if soft stop has been enabled by the JTAG COP logic If trace and breakpoint conditions occur simultaneously the breakpoint conditions receive higher priority The MPC603e requires
606. uctions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fcmpo 63 crfD 00 A B 32 0 fempu 63 crfD 00 A B 0 0 Table A 12 Floating Point Status and Control Register Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mcrfs 63 crfD 00 crfS 00 00000 64 0 mffsx 63 D 00000 00000 583 Re mtfsb0x 63 crbD 00000 00000 70 Re mtfsb1x 63 crbD 00000 00000 38 Rc mtfsfx 31 0 0 B 711 Rc mtfsfix 63 ei 00 00000 IMM lo 134 Re MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semi onduct er Ing Functional Categories Table A 13 Integer Load Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Ibz 34 D A d Ibzu 35 D A d Ibzux 31 D A 119 0 Ibzx 31 D A 87 0 Id 58 D A ds 0 Idu 1 58 D A ds 1 Idux 1 31 D A 53 0 Idx 1 31 D A 21 0 Iha 42 D A d Ihau 43 D A d Ihaux 31 D A 375 0 Ihax 31 D A 343 0 Ihz 40 D A d Ihzu 41 D A d Ihzux 31 D A 311 0 Ihzx 31 D A 279 0 Iwa 1 58 D A ds 2 Iwaux 1 31 D A 373 0 Iwax 31 D A 341 0 lwz 32 D A d lwzu 33 D A d lwzux 31 D A 55 0 lwzx 31 D A 23 0 1 64 bit instruction Table A 14 Integer Store In
607. ueue This latency can vary greatly depending on whether the instruction is in the on chip cache or system memory in which case latency can be affected by bus speed and traffic on the system bus and address translation dispatches Therefore in the examples in this chapter the fetch stage is usually idealized that is an instruction is usually shown to be in the fetch stage when it is a valid instruction in the instruction queue The instruction queue has six entries 1Q0 1Q5 In dispatch entry IQ0 IQ1 Instructions can be dispatched from IQO and IQ1 Because dispatch is instantaneous it is perhaps more useful to describe it as an event that marks the point in time between the last cycle in the fetch stage and the first cycle in the execute stage Execute The operations specified by an instruction are being performed by the appropriate execution unit The black stripe is a reminder that the Legd instruction occupies an entry in the CQ described in Figure 6 3 Complete The instruction is in the CQ In the final stage the results of the executed instruction are written back and the instruction is retired The CQ has five entries CQO CQ4 In retirement entry Completed instructions can be retired from CQO and CQ1 Like dispatch retirement is an event that in this case occurs at the end of the final cycle of the complete stage Figure 6 3 shows the stages of MPC603e execution units MPC603e RISC Microprocessor
608. uired for completion is kept in the five entry FIFO completion queue A completion queue entry is allocated for each instruction when it is dispatched to an execute unit if no entry is available the dispatch unit stalls A maximum Chapter 6 Instruction Timing For More Information On This Product Go to www freescale com rae EE Freescale Semiconductor Inc Timing Considerations of two instructions per cycle may be completed and retired from the completion queue and the flow of instructions can stall when a longer latency instruction reaches the last position in the completion queue Store instructions and instructions executed by the FPU and SRU with the exception of integer add and compare instructions can only be retired from the last position in the completion queue Subsequent instructions cannot be completed and retired until that longer latency instruction completes and retires Examples of this are shown in Section 6 3 2 2 Cache Hit and Section 6 3 2 3 Cache Miss The rate of instruction completion is also affected by the ability to write instruction results from the rename registers to the architected registers The MPC603e can perform two write back operations from the rename registers to the GPRs each clock cycle but can perform only one write back per cycle to the CR FPR LR and CTR 6 3 2 Instruction Fetch Timing Instruction fetch latency depends on the fetch hits of the on chip instruction cache If no h
609. um Two Instruction Dispatch Decode Dispatch Per Clock Cycle p TEREE EE EEA a LE E E ee Execute Stage i r q Reservation 5 ola ln L 4 Stations 4 L 4 ree g D SRU FPU2 LSU1 Maximum Two Instruction Complete Write Back Completion Per Clock Cycle Figure 6 2 Superscalar Pipeline Diagram Because there are so many variables unless otherwise specified the instruction timing examples below assume optimal performance and that the instructions are available in the instruction queue in the same clock cycle that they are requested The fetch stage ends when the instruction is dispatched The decode dispatch stage consists of the time it takes to fully decode the instruction and dispatch it from the instruction queue to the appropriate execution unit Instruction dispatch requires the following Instructions can be dispatched only from the two lowest instruction queue entries IQO and IQ1 A maximum of two instructions can be dispatched per clock cycle Only one instruction can be dispatched to each execution unit per clock cycle There must be a vacancy in the specified execution unit Arename register must be available for each destination operand specified by the instruction For an instruction to dispatch the appropriate execution unit must be available and there must be an open position in the CQ If no entry is available the instruction remains in the IQ
610. until all prior instructions issued have completed Results from completion serialized instructions executed by the SRU are not available or forwarded for subsequent instructions until the instruction completes 1 1 4 5 Completion Unit The completion unit tracks instructions in program order from dispatch through execution and then completes Completing an instruction commits the MPC603e to any architectural register changes caused by that instruction In order completion ensures the correct architectural state when the MPC603e must recover from a mispredicted branch or any exception Instruction state and other information required for completion is kept in a five entry FIFO completion queue A single completion queue entry is allocated for each instruction once it enters the execution unit from the dispatch unit An available completion queue entry is a required resource for dispatch if no completion entry is available dispatch stalls A maximum of two instructions per cycle are completed in order from the queue 1 1 5 Memory Subsystem Support The MPC603e provides both separate instruction and data caches and MMUs The MPC603e also provides an efficient processor bus interface to facilitate access to main memory and other bus subsystems The memory subsystem support functions are described in the following sections 1 1 5 1 Memory Management Units MMUs The MPC603e MMUs support up to 4 Petabytes 252 of virtual memory and 4 Gigabytes
611. uped by frsescale Semiconductor Inc Table A 21 Floating Point Move Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fabsx 63 D 00000 B 264 Re fmrx 63 D 00000 B 72 Re fnabsx 63 D 00000 B 136 Re fnegx 63 D 00000 B 40 Re Table A 22 Branch Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bx 18 LI AA LK bcx 16 BO BI BD AAILK bectrx 19 BO BI 00000 528 LK belrx 19 BO BI 00000 16 LK Table A 23 Condition Register Logical Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 crand 19 crbD crbA crbB 257 0 crandc 19 crbD crbA crbB 129 0 creqv 19 crbD crbA crbB 289 0 crnand 19 crbD crbA crbB 225 0 crnor 19 crbD crbA crbB 33 0 cror 19 crbD crbA crbB 449 0 crorc 19 crbD crbA crbB 417 0 crxor 19 crbD crbA crbB 193 0 mert 19 crfD 00 crfS 00 00000 0000000000 0 Table A 24 System Linkage Instructions Name 0 56 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rfi 1 19 00000 00000 00000 50 0 sc 17 00000 00000 000000000000000 1 0 1 Supervisor level instruction MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semi onduct er Ing Functional Categor
612. use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or de
613. ve highest priority and are taken immediately regardless of other pending exceptions or recoverability A nonpredicted address is guaranteed Asynchronous maskable nonrecoverable machine check A machine check exception takes priority over any other pending exception except a nonrecoverable system reset caused by the assertion of either HRESET or internally during POR A machine check exception is taken immediately regardless of recoverability A machine check exception can occur only if the machine check enable bit MSR ME is set If MSR ME is cleared the processor goes directly into checkstop state when a machine check exception condition occurs A nonpredicted address is guaranteed Asynchronous nonmaskable recoverable system reset caused by the assertion of SRESET This interrupt takes priority over any other pending exceptions except nonrecoverable exceptions listed above This exception is taken immediately when a recoverable state is reached Asynchronous maskable recoverable system management interrupt external interrupt decrementer exception Before handling this type of exception the next instruction in program order must complete or except If this action causes another type of exception that exception is taken and the asynchronous maskable recoverable exception remains pending Once an instruction can complete without causing an exception further instruction completion is halted while the exception not taken remains
614. ves the values of CR CRO of the executing context to SRR1 0 3 whenever one of the three TLB miss exceptions occurs Thus the exception handler can set CR CRO bits and branch accordingly in the exception handler routine without having to save the existing CR CRO bits However the exception handler must restore these bits to CR CRO before executing the rfi instruction There are also four other bits saved in SRR1 whenever a TLB miss exception occurs that give information about whether the access was an instruction or data access and if it was a data access whether it was for a load or a store instruction Also these bits give some information related to the protection attributes for the access and which set in the TLB will be replaced when the next TLB entry is loaded Refer to Section 5 5 2 1 Resources for Table Search Operations for more information on these bits and their use 5 2 Real Addressing Mode If address translation is disabled MSR IR 0 or MSR DR 0 for a particular access the effective address is treated as the physical address and is passed directly to the memory subsystem as described in Chapter 7 Memory Management in the Programming Environments Manual Note that the default WIMG bits Ob0011 cause data accesses to be considered cacheable I 0 and thus load and store accesses are weakly ordered This is the case even if the data cache is disabled in the HIDO register as it is out of hard reset
615. vided to test for a specified set of conditions If any of the conditions tested by a trap instruction are met the system trap handler is invoked If the tested conditions are not met instruction execution continues normally Table 2 30 Trap Instructions Name Mnemonic Operand Syntax Trap Word tw TO rA rB Trap Word Immediate twi TO rA SIMM See Appendix F Simplified Mnemonics in the Programming Environments Manual for a complete set of simplified mnemonics 2 3 4 6 Processor Control Instructions UISA level processor control instructions are used to read from and write to the condition register CR 2 3 4 6 1 Move To From Condition Register Instructions Table 2 31 lists the instructions provided by the MPC603e for reading from or writing to the CR Table 2 31 Move To From Condition Register Instructions Name Mnemonic Operand Syntax Move from Condition Register mfcr rD Move to Condition Register Fields mtcrf CRM rS Move to Condition Register from XER merxr crfD 2 3 4 7 Memory Synchronization Instructions UISA Memory synchronization instructions control the order in which memory operations are completed with respect to asynchronous events and the order in which memory operations are seen by other processors or memory access mechanisms See Chapter 3 Instruction and Data Cache Operation for additional information about these instructions and about related aspects
616. wo rD rA rB Multiply Low Immediate mulli rD rA SIMM Negate neg neg nego nego rD rA Subtract From subf subf subfo subfo rD rA rB Subtract From Carrying subfc subfc subfco subfco rD rA rB Subtract From Extended subfe subfe subfeo subfeo rD rA rB Subtract From Immediate Carrying subfic rD rA SIMM Subtract From Minus One Extended subfme subfme subfmeo subfmeo rD rA Subtract From Zero Extended subfze subfze subfzeo subfzeo rD rA Although there is no Subtract Immediate instruction its effect can be achieved by using an addi instruction with the immediate operand negated Simplified mnemonics are provided that include this negation The subf instructions subtract the second operand rA from the third operand rB Simplified mnemonics are provided in which the third operand is Chapter 2 Programming Model For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Instruction Set Summary subtracted from the second operand See Appendix F Simplified Mnemonics in the Programming Environments Manual for examples 2 3 4 1 2 Integer Compare Instructions The integer compare instructions algebraically or logically compare the contents of rA with either the UIMM operand the SIMM operand or the contents of rB The comparison is signed for the cmpi and cmp instructions and unsigned for the cmpli and cmpl instructions Table 2 11 lists the integer compare instructions Table 2
617. word of the cache line and the cache line fill may wrap around the end of the cache line This section describes the burst ordering for the MPC603e when operating in either the 64 or 32 bit bus mode Chapter 8 System Interface Operation For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Address Bus Tenure Table 8 3 describes the burst ordering when the MPC603e is configured with a 64 bit data bus Table 8 3 Burst Ordering 64 Bit Bus For Starting Address Data Transfer A 27 28 00 A 27 28 01 A 27 28 10 A 27 28 11 First data beat DWO DW1 DW2 DW3 Second data beat DW1 DWe2 DW3 DWO Third data beat DW2 DW3 DWO DW1 Fourth data beat DW3 DWO DW1 DW2 Note A 29 31 are always 0b000 for burst transfers by the MPC603e Table 8 4 describes the burst ordering when the MPC603e is configured with a 32 bit bus Table 8 4 Burst Ordering 32 Bit Bus For Starting Address Data Transfer A 27 28 00 A 27 28 01 A 27 28 10 A 27 28 11 First data beat DWO0 U DW1 U DW2 U DW3 U Second data beat DWO0 L DW1 L DWe L DW3 L Third data beat DW1 U DW2 U DW3 U DWO U Fourth data beat DW1 L DWe2 L DW3 L DWO L Fifth data beat DW2 U DW3 U DWO0 U DW1 U Sixth data beat DWe L DW3 L DWO L DW1 L Seventh data beat DW3 U DWO U DW1 U DW2 U Eighth data beat DW3 L DW0 L DW1 L DW2 L Note A 29 31 are always
618. ww freescale com Freescale Semiconductor Inc Memory Access Protocol depending on the transfer size and the cache mode for the address For additional information see Section 8 6 1 32 Bit Data Bus Mode 8 1 3 Direct Store Accesses The MPC603e does not support the extended transfer protocol for accesses to the direct store storage space If SR T is set the memory access is a direct store access An attempt to access to a direct store segment results in a DSI exception 8 2 Memory Access Protocol Figure 8 2 shows that the address and data tenures are distinct from one another and that both consist of three phases arbitration transfer and termination Address and data tenures are independent indicated in Figure 8 2 by the fact that the data tenure begins before the address tenure ends which allows split bus transactions to be implemented at the system level in multiprocessor systems Figure 8 2 shows a data transfer that consists of a single beat transfer of as many as 64 bits Four beat burst transfers of 32 byte cache lines require data transfer termination signals for each beat of data Address Tenure Independent Address and Data Data Tenure Arbitration Single Beat Transfer Figure 8 2 Overlapping Tenures on the Bus for a Single Beat Transfer The basic functions of the address and data tenures are as follows e Address tenure Arbitration During arbitration address bus arbitration signals are used t
619. x instructions are not aligned e The operand of a single register load or store operation is not aligned and the MPC603e is in little endian mode PID6 603e only e The execution of a floating point load or store instruction to a direct store segment e The operand of a load store load multiple store multiple load string or store string instruction crosses a segment boundary into a direct store segment or crosses a protection boundary e Execution of a misaligned eciwx or ecowx instruction PID7t 603e only e The instruction is Imw stmw Iswi Iswx stswi stswx and the MPC603 e is in little endian mode e The operand of debz is in memory that is write through required or caching inhibited Program 00700 A program exception is caused by one of the following exception conditions which correspond to bit settings in SRR1 and arise during execution of an instruction e Floating point enabled exception A floating point enabled exception condition is generated when the following condition is met MSR FEO MSR FE1 A FPSCR FEX is 1 e FPSCR FEX is set by the execution of a floating point instruction that causes an enabled exception or by the execution of one of the move to FPSCR instructions that results in both an exception condition bit and its corresponding enable bit being set in the FPSCR e Illegal instruction An illegal instruction program exception is generated when execution of an instruction i
620. x 1 30 S A sh mb sh Re ridiclx 1 30 S A sh mb sh Re ridicrx 1 30 S A sh me sh Re Appendix A PowerPC Instruction Set Listings For More Information On This Product Go to www freescale com Instructions Sorted by Mnemonic Table A 1 Complete Instruction List Sorted by Mnemonic continued Freescale Semiconductor Inc Name 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ridimix 1 30 s A sh mb 3 Ish Rc rlwimix 20 S A SH MB ME Rc rlwinmx 21 S A SH MB ME Rc rlwnmx 23 S A B MB ME Rc sc 17 00000 00000 00000000000000 110 slbia 1 2 3 31 00000 00000 00000 498 0 slbie 123 31 00000 00000 B 434 0 sidx 31 A B 27 Rc slwx 31 S A B 24 Rc sradx 31 S A B 794 Rc sradix 31 S A sh 413 sh Rc srawx 31 S A B 792 Rc srawix 31 S A SH 824 Rc srdx 31 S A 539 Rc srwx 31 S A 536 Rc stb 38 S A d stbu 39 S A d stbux 31 S A 247 0 stbx 31 S A 215 0 std 62 S A ds 0 stdex 31 S A B 214 1 stdu 1 62 S A ds stdux 31 S A 181 0 stdx 1 31 S A 149 0 stfd 54 S A d stfdu 55 S A d stfdux 31 S A 759 0 stfdx 31 S A 727 0 stfiwx 3 31 S A 983 0 stfs 52 S A d stfsu 53 S A d stfsux 31 S A B 695 0 stfsx 31 S A 663 0 sth 44 S A d sthbrx 31 S A B 918 0 sthu 45 S A d sthux 31 S A B 439 0 MPC603e RISC Microprocessor User s Manual For Mor
621. xceptions have other characteristics as well such as whether they are maskable or nonmaskable the distinctions shown in Table 1 4 define categories of exceptions that the MPC603e handles uniquely Note that Table 1 4 includes no synchronous imprecise instructions While the PowerPC architecture supports imprecise handling of floating point exceptions the MPC603e implements floating point exception modes as precise exceptions The MPC603e exceptions and conditions that cause them are listed in Table 1 5 Table 1 5 Exceptions and Conditions Exception Vector Offset Causing Conditions Type hex Reserved 00000 System reset 00100 A system reset is caused by the assertion of either SRESET or HRESET Machine check 00200 A machine check is caused by the assertion of TEA during a data bus transaction assertion of MCP or an address or data parity error DSI 00300 The cause of a DSI exception can be determined by the bit settings in the DSISR listed as follows 1 Set if the translation of an attempted access is not found in the primary hash table entry group HTEG or in the rehashed secondary HTEG or in the range of a DBAT register otherwise cleared Set if a memory access is not permitted by the page or DBAT protection mechanism otherwise cleared Set by an eciwx or ecowx instruction if the access is to an address that is marked as write through or execution of a load store instruction that accesses a direct store segm
622. xecution before the exception is taken Once the exception is processed execution resumes at the address of the faulting instruction or at an alternate address provided by the exception handler When an exception is taken due to a trap or system call instruction execution resumes at an address provided by the handler e Synchronous imprecise The PowerPC architecture defines two imprecise floating point exception modes recoverable and nonrecoverable Even though the MPC603e provides a means to enable the imprecise modes it implements these MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Exception Classes modes identically to the precise mode that is all enabled floating point exceptions are always precise on the MPC603e e Asynchronous maskable The external interrupt INT system management interrupt SMI and decrementer exceptions are maskable asynchronous exceptions When these exceptions occur their handling is postponed until the next instruction and any exceptions associated with that instruction completes execution If there are no instructions in the execution units the exception is taken immediately upon determination of the correct restart address for loading SRRO e Asynchronous nonmaskable There are two nonmaskable asynchronous exceptions system reset and the machine check exception These exceptions may not be rec
623. xed instruction length and consistent format greatly simplifies instruction pipelining The PowerPC instructions are divided into the following categories e Integer instructions These include computational and logical instructions Integer arithmetic instructions Integer compare instructions Integer logical instructions Integer rotate and shift instructions e Floating point instructions These include floating point computational instructions as well as instructions that affect the FPSCR Floating point arithmetic instructions Floating point multiply add instructions Floating point rounding and conversion instructions Floating point compare instructions Floating point status and control instructions e Load store instructions These include integer and floating point load and store instructions Integer load and store instructions Integer load and store multiple instructions MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc specitic Information Floating point load and store Primitives used to construct atomic memory operations wars and stwex instructions e Flow control instructions These include branching instructions condition register logical instructions trap instructions and other instructions that affect the instruction flow Branch and trap instructions Con
624. y be accessed when address translation is disabled MSR IR 0 and MSR DR 0 Note that MSR IR and MSR DR are cleared whenever an exception occurs 5 5 2 1 1 Data and Instruction TLB Miss Address Registers DMISS and IMISS The DMISS and IMISS registers have the same format as shown in Figure 5 11 They are loaded automatically upon a data or instruction TLB miss The DMISS and IMISS contain Chapter 5 Memory Management For More Information On This Product Go to www freescale com Page Table Search Operathreeseale Semiconductor Inc the effective page address of the access which caused the TLB miss exception The contents are used by the processor when calculating the values of HASH1 and HASH2 and by the tlbld and tlbli instructions when loading a new TLB entry Note that the MPC603e always loads a big endian address into the DMISS register These registers are read only to the software Effective Page Address Figure 5 11 DMISS and IMISS Registers 5 5 2 1 2 Data and Instruction TLB Compare Registers DCMP and ICMP The DCMP and ICMP registers are shown in Figure 5 12 These registers contain the first word in the required PTE The contents are constructed automatically from the contents of the segment registers and the effective address DMISS or IMISS when a TLB miss exception occurs Each PTE read from the tables in memory during the table search process should be compared with this value to determine whethe
625. y PTEG is tested for a match with the virtual page number VPN of the access For a match to occur the following must be true PTE H 1 PTE V 1 PTE VSID VA 0 23 PTE API VA 24 29 7 Ifa match is not found step 6 is repeated for each of the other seven PTEs in the secondary PTEG 8 Ifa match is found the PTE is written into the on chip TLB and the R bit is updated in the PTE in memory if necessary If there is no memory protection violation the C bit is also updated in memory and the table search is complete 9 Ifno match is found in the eight PTEs of the secondary PTEG the search fails and a page fault exception condition occurs either an ISI exception or a DSI exception Note that the software routines that implement this algorithm must synthesize this condition by appropriately setting the SRR1 or DSISR and branching to the ISI or DSI handler routine Reads from memory for table search operations should be performed as global but not exclusive cacheable operations and can be loaded into the on chip cache Figure 5 9 and Figure 5 10 provide conceptual flow diagrams of primary and secondary page table search operations as described in the OEA for 32 bit processors Recall that the architecture allows implementations to perform the page table search operations automatically in hardware or with software assistance as is the case with the MPC603e Also the elements in the figure that apply to TLBs ar
626. y page table a page fault condition exists and a page fault exception must be synthesized Thus the appropriate bits must be set in SRR1 or DSISR and the TLB miss handler must branch to either the ISI or DSI exception handler which handles the page fault condition This section provides a flow diagram outlining some example software that can be used to handle the three TLB miss exceptions and sample assembly language that implements that flow 5 5 2 2 1 Flow for Example Exception Handlers Figure 5 15 shows the flow for the example TLB miss exception handlers The flow shown is common for the three exception handlers except that the IMISS and ICMP registers are used for the instruction TLB miss exception while the DMISS and DCMP registers are used for the two data TLB miss exceptions Also for the cases of store instructions that cause either a TLB miss or require a table search operation to update the C bit the flow shows that the C bit is set in both the TLB entry and PTE in memory Finally in the case of a page fault no PTE found in the table search operation the setup for the ISI or DSI exception is slightly different for these two cases MPC603e RISC Microprocessor User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Mes able Dee TLB Miss Exception Save Old Counter and CRO Bits Set Counter cnt e 8 Load Primary PTEG Pointer ptr HASH1 8 compare_value ICMP DC
627. y the PowerPC architecture OEA A program exception occurs when no higher priority exception exists and one or more of the exception conditions defined in the OEA occur When a program exception is taken instruction execution for the handler begins at offset 0x00700 from the physical base address indicated by MSR IP The exception conditions are as follows e Floating point enabled exception These exceptions correspond to IEEE defined exception conditions such as overflows and divide by zeros that may occur during the execution of a floating point arithmetic instruction As a group these exceptions are enabled by the FEO and PET bits in the MSR Individual conditions are enabled by specific bits in the FPSCR For general information about this exception see the Programming Environments Manual For more information about how these exceptions are implemented in the MPC603e see Section 4 5 7 1 IEEE Floating Point Exception Program Exceptions e Illegal instruction An illegal instruction program exception is generated when execution of an instruction is attempted with an illegal opcode or illegal combination of opcode and extended opcode fields including PowerPC instructions not implemented in the MPC603e These do not include those optional instructions treated as no ops e Privileged instruction A privileged instruction type program exception is generated when the execution of a privileged instruction is attempted and the MSR

MPC603e RISC Microprocessor User`s Manual

Contents

Download Pdf Manuals

Related Search

Related Contents