NetFusion Libero Starter Project Helper
Contents
1. ad 18 54 ub a EI e Lu aaa an apa TL 19 elec dcs 20 5 6 COUNTER GPIO ES aa aaa Ga alaa an aapa a iS 22 LAM aka ana 23 GROSS UI RATEN aa a daa Ga alaa an aapa aa 24 5 0 CORESPIO Tau sara aana a aa a NA a baan aga a aa aa aa aaa kana aan aaa A aja baan ee 25 5 10 BIBUR 26 5 11 CORESFE2CONFIG sasabana a a es alta aa aa NS nd aaa 27 5 12 CORE AXI AFIBLITE tiri it it Do osea ee habito a ia naa eat 28 5 13 UNUSED LOGIC BLOCK 00 ii eee di a a a esca dak alae Pod censi ga aod dual 32 5 14 SMARTFUSION2Z MSS 33 6 NETFUSION ARM CORTEX MSS DEFAULT CONFIGURATION eere nennen nnn nnne 34 Ic MEME IBID 35 02 naga a a POP aa gag na ES aa aga 36 6 3 ETHERNET ocio DM aan UAE ILLE ER A aaa 37 MEMO 38 6 5 RESET 38 6 6 O 39 6 1 40 68 FIC 2 PERIPHERAL 2 7 41 7 ADDING IP CORES FROM anana anan naun awanan anenun nono naaa ara anana nen 42 7 1 IMPORTING SOURCE2. 020 0 42 7 2 INSTANTIATING INTO THE 4 10000 43 00072 and Q development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 7 2 1 Building and Synthesizing the NetFusion Design sse 44 8 46 9 CONTACT 11 I 47 10 DOCUMENT HISTORY e 48 000 QO research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 List of Figures Figure 1 Libero IDE Boot Up Screen ss 8 Figure 2 Libero Updating IP Core in the Vault ses 12 Figure Example of Top List I O Ball Assignments nennen 13 Figure 4 Example of Bottom List I O Ball Assignments ss 14 Figure 5 Selecting the Constraints ss 14 Figure 6 NetFusion Top Level Sheet ses 15 Figure 7 Screenshot of Lower Level SOM sheet ss 16 Figure 8 AMBA DMA Controller seen 17 Figure 9 ULPI UTMI USB Converter IP Core seen 18 Figure 10 SmartFusion2 Reset Controller IP Core ss 19 Figure 11 Clock PLL Macro Corentin teen eel inea xu ede ea ANAN ee Eve REV aa REP re ERU 20 Figure 12 Clock Macro Settings niendo cias 21 Figure 13 Temperature Sensor Logic ss
3. SESSION END g UTMI HOST DISCONNECT JE JE 2 g 4 UTMI_ID_DIG Figure 27 USB OTG UTMI Host Controller NetFusion does utilize on the PCB hardware an OTG USB interface In the fabric the ULPI is converted to UTMI and then connected to this MSS internal block The ARM uClinux application code will be able to access this USB block as a block of memory registers and device drivers will be able to control the USB OTG as a USB stack Note the UTMI signals do not get routed to the I O pins directly but the fabric for the use of the ULPI UTMI converter IP core 36 101 000 research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 6 3 Ethernet EX MSS Ethernet MAC Configurator p Connectivity Preview Interface Fabric Line Speed 100 Management Interface Main MII_TXD 3 0 MIL TX EN y MII ER MII_RXD 3 0 MII RX ER MII DV Click on a signal row to see the preview 4 CRS 4 COL ET peo 4 MII_TX_CLK Figure 28 MSS MAC for 10 100 Ethernet Using SOM PHY This is a very strategic and important module in the MSS of the SmartFusion2 of NetFusion The 4th RJ45 Ethernet connector on the NetFusion PCB is routed directly to the PHY on the M2S SOM F484 which in turn con
4. Data Width 16 SECDED Enabled Arbitration Scheme mp3 rz HghstPiotyD j 7 Address Mapping ROWBANK COLUMN Fabric Interface Settings Use an ANI interface Use an AHBLite Interface C Use two AHBLite Interfaces Figure 26 MDDR MSS Controlling LPDDR Memory with AXI from Fabric The MDDR has been configured to use a single data rate LPDDR SDRAM device on the M2S SOM F484 using 16 bit data width Priority has been given to the AXI master interface from the fabric where the default connection is to the AMBA DMA Controller for 3rd party MACs and Ethernet SWITCH If you do not wish to keep the DMA Controller or any AXI interface for that matter then you can de select the Fabric Interface and the SOM sheet will adjust accordingly You will have to remove and delete the instantiated DMA Controller however Note NetFusion has to follow the architecture of the SOM F484 so this is primarily based upon the Emcraft starter project for this block development NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 6 2 USB EX MSS USB Configurator r Configuration Interface Selection 71 options IO Group Selection Y UTMI LINE STATE UTMI RX DATA g UTMI TX READY UTMI RX VALID UTMI RX ACTIVE H Click on a signal row to see the preview UTMI RX ERROR g 5 VALID UTMI AVALID
5. constraintM2S SOM FG484 TOP designer constraintM2S SOM FG484 TOP synthesis 9 Floorplan Constraints 4 gt Implement Design A lt gt Synthesize v 4 Verify Post Synthesis Implementation Bl Simulate Compile Configure Flash Freeze Pi Place and Route 4 M Edit Constraints VO Constraints Timing Constraints 9 Floorplan Constraints 4 gt Verify Post Layout Implementation Generate Back Annotated Files Bl Simulate Q Verify Timing Verify Power 4 M Edit Design Hardware Configuration Programming Connectivity and Interface 8 Programmer Settings Device VO States During Programming 15 Desgnr DesignHierar StimulusHierar Catalog Files Messages 3 Errors 4 Warnings Info The 1 0 modules located in these banks cannot be assigned any I O macro hsarning IOPRL2 1 1 0 Bank s have been assigned a Vccr voltage but no Vref pins The 1 0 modules located in these banks cannot be assigned any voltage referenced 1 0 macro The set device command succeeded The set input cfg command succeeded The set output cfg command succeeded The gen envm command succeeded The Execute Script command succeeded Fam SmartFusion2 250507 Pkg 484FBGA Verilog Figure 6 NetFusion Top Level Sheet When lower level SOM sheets are built and prepared they propagate information up automatically to this higher sheet New ports sudd
6. 1 106 Downloading Actel DirectCore COREQEI 2 0 111 Fam SmartFusion2 M2S050T Pkg 484FBGA Verilog Figure 2 Libero Updating IP Core in the Vault When you first load the NetFusion starter project into the IDE the most likely occurrence to happen is that the system will warn you to update New IP Cores This is because the design includes cores that you possibly do not have on your vault on your local hard drive Click YES to proceed and let the download process complete Note this may take several minutes and you MUST have a network connection and gateway to the internet 12 000 research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 3 NetFusion Libero I O Assignments The NetFusion Libero starter project is delivered already with the I O balls of the FPGA assigned ready for the user These all correspond with the pin out tracking assignments on the NetFusion PCB product This means that you will not have to consider any of these assignments unless you are planning any major changes to the inherent default design This is very unlikely as you would need then to request changes to the PCB design However this section highlights the assignments in case you also want to make minor changes to the direction of the port default output values and or change internal SmartFusion2 FPGA pull up values eei jamban File Edit View Tools H
7. 22 Figure 14 Main PCB GPIO Interface with the ARM Processor 23 Figure 15 lt RS485 UART iiri e E eR Hed ROLE ini na wa due WEE eee ean nese 24 Figure 16 Stereo Audio Line IN amp Line OUT sise 25 Figure 17 Bi Directional Fabric Macro entere etienne ea eben th inae ek ete ebore ANAA 26 Figure 18 APB feedback Bus for Peripheral Configuration by 27 Figure 19 AMBA Memory Interfaces from ARM sise 28 Figure 20 Default AXI Configuration rene eene ener nennen rennen 29 Figure 21 Default AHB Lite Configuration enne ener ener nne 30 Figure 22 Default APB Conflg tatlof ertet rettet rentre terret A rete ete 31 Figure 23 Unused Block NetFusion SOM iii 32 Figure 24 SOM Module of the ARM MSS eee 33 Figure 25 Exploded View of the Modules in the NetFusion ARM 34 Figure 26 MDDR MSS Controlling LPDDR Memory with AXI from 35 Figure 27 USB UTMI Host Controller ss 36 Figure 28 MSS MAC for 10 100 Ethernet Using SOM PHY sien 37 Figure 29 MSS CCC Divider from the CLK BASE with in ARM Sub System 38 Figure 30 Reset MSS Module citerne 38 Figure 31 AHB APB Fabric Interface 39 Figure 32 A
8. 258847 44 0 1332 258823 iol 47 Q research 00072 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 10 Document History Document Change Notices DCO Version Description Created Changed By Date Version 1 0 Initial Release according to Paul Bates Nine Ways 17th July 2014 Version 1 0 Copyright Nine Ways R amp D Ltd 2014 All Rights Reserved Table 1 Document History Entry Log 48
9. Configure Flash Freeze Place and Route Place and Route 25 SOM gp report 4 Edit Constraints Ay Generate Programmin PE VO Constraints M2S SOM generatePr Timing Constraints Run PROGRAM Action Y Floorplan Constraints M2S SOM PROGR 4 b Verify Post Layout Implementation 21 Generate Back Annotated Files Simulate Verify Timing Verify Power gt Edit Design Hardware Configuration Progra Figure 5 Selecting the IJO Constraints 14 doy 000 OG research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 4 NetFusion Libero IDE SoC Top Level Within the NetFusion starter Libero project the 25 SOM Top Level sheet illustrates the lower modules to the design just before the I O ports go out to the real world PCB The ports labeled in this sheet correspond to the I O assignments shown in the previous section This sheet is effectively the linkage from the inner SOM design see next section up to the I O balls of the SmartFusion2 FPGA Libero CAMorethaniplSmartFusion_ SOM Project Project File Edit View Design Tools SmartDesign Help SHLSSOE Design Flow 6 EJ 25050 sow 484 amp x 64 25 som Mss x Mas 5 HORS Ban n 2 3 Tool constraintioM2S SOM FG484 synth 4 Timing Constraints 8 ynthesis M25_ SOM sdc sdc
10. Guide for Software v10 0 Integrated Development Environment installation Libero IDE and Software Installation and Licensing Guide Libero IDE License Troubleshooting Guide Note Press CNTL and click to download the links 1 3 1 Libero IDE First Launch libero 8 Project File Edit View Design Tools Help StartPage E Libefo System on Chip Welcome To Microsemi s Libero SoC v11 3 Software Libero SoC is a comprehensive software suite for designing with Microsemi s SmartFusion2 and SmartFusion SoC FPGAs and IGLOO2 IGLOO ProASIC3 and Fusion FPGA families Visit the Documents tab on your device page at www microsemi com to obtain silicon Datasheets Silicon User s Guides Tutorials and Application Notes Development Kits and Starter Kits are available from the Microsemi website Welcome to Libero SoC Libero SoC Quickstart Libero SoC Interface Description 002 Build designs targeting the newest Microsemi FPGA device using the 2 System Builder Libero SoC Release Notes on the Web SmartFusion2 This new SoC FPGA combines a powerful Cortex M3 microcontroller with programmable FPGA logic System Builder A powerful new tool that allows you to describe your design using high level specifications see the System Builder documentation PDF link for Libero Tutorials details Product Tutorials Libero SoC delivers an updated Design Flow for IGLOO2 and SmartFusion2 link opens Help This includ
11. a configuration file that can be included by software in either bare metal programming or the u boot from Emcraft uClinux environment Only when the boot up code access the APB feedback bus CoreSF2Config 0 and manipulates hardware peripheral memory address does the peripherals in the MSS get the correct mode of operation intended for them Figure 18 APB feedback Bus for Peripheral Configuration by Software ol 27 000 O research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 5 12 Core AXI AHBLite The DMA Controller for the ability to connect to a MAC SWITCH uses AXI and AHB Lite for communication with the MSS sub system and the LPDDR memory Also an APB master core allows for all of the above APB cores to connect to the MSS This is all handled by the COREAXI 0 CoreAHBLite 0 and CoreAPB 0 that are instantiated in the SmartFusion2 fabric for the NetFusion starter project Figure 19 AMBA Memory Interfaces from ARM 28 000 research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 Configuration Memory space Memory space pipa kj t Na aan AXI data width r Enable master access MO can access slave slot 0 MO can access slave slot 1 MO can access slave slot2 MO can access slave slot 3 MO can acc
12. logic design is scattered around Bi Directional macros These convert conveniently any IN OUT data flow when the RX and TX are kept separate in the IP cores The output side always routes up out of the SmartFusion2 FPGA to the NetFusion PCB hardware where the signals are capable of input output operation using pull up resistors combining tri state operation The instantiated BIBUFs are illustrated in the Figure below They are controlled by an output enable signal that drives the state of the output pin An example of the need for bi directional signal operation is MDIO for the Marvell PHY and the SDA data line for ALL I2C buses on the NetFusion PCB Figure 17 Bi Directional Fabric Macros 000 research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 5 11 CoreSF2Config The SmartFusion2 MSS processor sub system always as standard has a default CoreSF2Config block that loops back an APB bus out and then back into the MSS block This seems at first strange and can be very confusing However it is the inherent architecture of the FPGA ASIC area that most of the peripheral devices inside the MSS ARM processor core are not actually controlled by the selections made in the Libero IDE It is the software in U boot during boot up that configures If say for instance an AHB Lite interface is selected in Libero then this does not configure the SmartFusion2 FPGA itself It saves
13. terminate here Most of these are the Ethernet signals and pathways of the GMII In order to make it easier for a user to instantiate their own IP cores and then connect the unused signals this starter project has had to include the unused signals at the I O level of the FPGA bring them down through the Top Level then into the SOM sheet They then terminate at the unsused block 0 A23 GAO ASS H RESET QUI HEIR RE EERE Figure 23 Unused Block in NetFusion SOM Libero and SynplifyPro do not like un terminated signals and it will remove them from the I O assignments if they were not routed by default to this block 32 000 9 research and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 As you require a signal terminated at this block simply un route it from the unused block and then re assign to your new IP core using the quick connect option However make sure that if it was an output of the unused block to assign the pin left vacant as unused or if an input then set the attribute to tie LOW The output signal REGSPR is just a necessary signal that is not assigned any ball of the FPGA and is used internally with in the core to stop Libero optimization occurring and removing the inputs of this block from the I O assignments Do not remove this output 5 14 SmartFusion2 MSS
14. 000 MSS 0 1 Sub busses Clocks 0 2 7 83 000 MHz amiak 2 x 83 000 MHz FPGA Fabric Interface Clocks v 2 7 83 000 MHz Ficidk M3_CIK 2 7 83 000 MHz Figure 29 MSS CCC Divider from the CLK BASE with in ARM Sub System The main 166MHz clock into the MSS from the fabric is configured to be split up and if necessary divided down to the different areas of the sub system In the case of NetFusion and the starter Libero IDE project all peripherals memory controllers and fabric interfaces run at half the base clock frequency at 83MHz 6 5 RESET Controller E Configuring RESET MSS RESET 1 0 100 Configuration Enable FPGA Fabric to MSS Reset MSS RESET F2M M Enable FPGA Fabric to M3 Reset M3 RESET N Iv Enable MSS to FPGA Fabric Reset MSS_RESET_N_M2F Figure 30 Reset MSS Module NetFusion by default enables the M88 RESET F2M RESET and the MSS RESET M2F negative reset signals to come in from the SmartFusion2 FPGA fabric This gives more functionality to the user However if it is not a required functionality when the design is customized then they can be de selected iol 38 606 development NetFusion Libero Starter Project Helper V1 0 July 2014 6 6 FIC 0 EX Mss Fabric Interface Controller FIC 0 Configurator MSS To FPGA Fabric Inte
15. 21 Default AHB Lite Configuration 30 d 000 research 000 and Q development NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 Configuration Data Width Configuration Master Data Bus Width 6 32bit 16 bit C r Address Configuration Number of address bits driven by master 28 Position in slave address of upper 4 bits of master address 27 24 Ignored if master address width gt 32 bits Indirect Addressing Not inuse X r Allecate memory space to combined region slave Slot 0 Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 Slot 11 Slot 12 Slot 13 Slot 14 Slot 15 Enabled APB Slave Slots Slot 0 Slot 2 Slot3 Slot 4 Slot 6 Sotz Slot 8 Slot 10 Slot 11 Slot 12 Slot 14 Slot 15 Figure 22 Default APB Configuration As a Libero designer and developer the user may change these defaults and added or remove memory accessible IP cores to from the fabric 000 0200 research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 5 13 Unused Logic Block Specifically to the NetFusion starter project is the instantiated dummy block that allows all of the wires and signals coming into the SmartFusion2 FPGA fabric from the outside PCB that are not connected to IP cores to
16. In the SOM layer sheet of the NetFusion starter project the MSS ARM processor main core is situated in the middle and is shown below If you double click on the MSS block it will expanded and create another window in Libero on screen Note Refer to the next section for the MSS documentation 933 i n 2 52 9 LEP 2586 PRA Figure 24 SOM Module of the ARM MSS 33 doy 000 research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 6 NetFusion ARM Cortex MSS Default Configuration Figure 25 Exploded View of the Modules in the NetFusion ARM MSS The MSS in the heart of the SmartFusion2 NetFusion design is defaulted and set to the exact current needs of the PCB product Modules I2C1 12C2 CAN GPIO RTC and PDMA are disabled currently but there is nothing stopping the user from enabling and wiring out the modules to the SOM sheet The blue modules are currently enabled for the NetFusion design as they have functional requirements and the signals are wired out to the SOM sheet then if necessary up to the I O assignments then out of the FPGA device itself 000 research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 6 1 MDDR Import Configuration Export Configuration Restore Defaults General Memory Initialization Memory Timing Memory Type
17. PB3 AHB Lite Fabric Interface 2 enne nnne nennen 40 Figure 33 APB Peripheral Hardware Configuration ss 41 Figure 34 Importing a single Verilog VHDL file into the NetFusion Libero 42 Figure 35 Instantiating an Imported IP Core in your Fabric Design 43 Figure 36 Selecting Full NetFusion Synthesis and FPGA Programming 45 000 O research 0007 and Q development NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 About This Document This specification introduces the NetFusion baseboard s Libero IDE starter project Whilst this is provided as a downloadable target to the PCB using the open source IP project as a start point will aid and help the user s intended functional product Intended Audience This document is fully intended to be viewed and reference by Nine Ways customers using the technology for larger designs and projects 000 0 research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 1 Introduction Microsemi is part of Actel Corporation It designed and manufactured the SmartFusion2 FPGA Libero is the IDE software for programming and synthesizing IP cores Along with the bundle of uClinux firmware compilation tools this is the heart of the NetFusion design process for Users Microsemi 1 1 Libero SoC IDE 11 3 Microsemi s Libero amp IDE software release for desi
18. antiating into the Fabric Libero C NetFusion M25 SOM F484 CAT5NetFusion F484 prix Project File Edit View Design Tools SmartDesign Help 0 0 Design Hierarchy Ems som E M2s050 5 484 x ELM Em ES SEMI 555 o 42 9 LIIS A XTLOSC_FAB osc_comps v B RCOSC_1MHZ_FAB osc_comps v E RCOSC 1MHZ osc comps v 25050 SOM FG484 TOP Eg 25 som 25 SOM 0 COREAXI cor B CoreGPIO coregpio v CoresF2Config coresf2config v A CoreSF2Reset coresf2reset v CORESPI corespi v 25 SOM CoreUARTapb 0 CoreUAR Set As Root Instantiate in M25 SOM Open HDL File Check HDL File Create I O Constraint from Module COREAHBLITE Remove Core Definition COREAPB3_LIE COREAXI OFF Delete from Project CORESPI Delete from Disk and Project Properties Figure 35 Instantiating an Imported IP Core in your Fabric Design Whether you wish to instantiate into the SmartFusion2 fabric an imported 3rd party source code core from VHDL Verilog or it is from the vault downloaded from ACTEL the process to get the core into the design sheets is the same and relatively simple In fact even if the core is a macro as part of the ASIC area of the FPGA the process is the same no matter what area of the design it involves Simply move the left panel to select Design Hierarchy and then right click on the listed core of your choic
19. ch 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 FlashPro User s Guide Contains information about how to program your devices using the FlashPro software and device programmer FlashPro is not available on UNIX SmartFusion2 and IGLOO2 Macro Library Guide Provides descriptions of Microsemi library elements for the Microsemi SmartFusion2 and IGLOO2 device families Symbols truth tables and module counts if appropriate are included for all macros IGLOO ProASIC3 SmartFusion and Fusion Macro Library Guide Provides descriptions of Microsemi library elements for Microsemi SmartFusion Fusion ProASIC3 and ProASIC3E device families Symbols truth tables and module counts if appropriate are included for all macros SmartFusion2 and IGLOO2 Block Flow User s Guide Describes how to create and integrate Blocks in Libero SoC for SmartFusion2 and IGLOO2 VHDL Vital Simulation Guide Contains information about using the ModelSim to simulate designs for Microsemi SoC devices Verilog Simulation Guide Contains information about interfacing the FPGA development software with Verilog simulation tools ViewDraw User s Guide Describes how to create designs in ViewDraw using menu commands toolbar buttons and by selecting and entering information on dialog boxes ViewDraw for Microsemi is not available on UNIX ModelSim ME Book Case Contains a User s Manual Command Reference and Tutorial Th
20. development NetFusion Libero Starter Project Helper V1 0 July 2014 NetFusion Libero Starter Project Helper User Guide iol 000 research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 Table of Contents 1 INTRODUCTION a a ina aan daa aa 6 1 4 5 113 6 1 2 5 aaa naa a aa a a a aa a aaa a a aaa na a naa TO aa aa a Ba aaa TG Ga aaa 7 1 3 STARTING PROJECT AND BASIC UNDERSTANDING 00 0 6 8 1 3 1 Libero IDE First aU is access dia a 8 14 NETPUSION CERES 9 1 5 PRODUCT nena nn anna sti 9 1 6 DOCUMENTATION 5 aa 10 2 DOWNLOADING NEW CORE S INTO THE LIBERO IDE INSTALLATION 12 3 NETFUSION LIBERO 55 5 1 1 anam nana dd dada sau NGE 13 4 NETFUSION LIBERO IDE SOC _ 15 5 NETFUSION LIBERO IDE SOC SOM _ naun awanan anan ewan rasa ad dada nan nan 16 JEMGRAFEI SYSTEMS unid Ie te Ee tea eect dto cn Date ee at 17 5 2 AMBA DMA esti eee ce DOES EEEE EE ennenen nnne 17 5 3 ULPVUTMIOTGUSB cua erase eet
21. e Programmer Settings i Device I O States During Programming Configure Security and Programming Security Policy Manager Bitstream Configuration K Update eNVM Memory Content Program Design Generate Programming Data Debug De Update and Run MA Identify Run SmartDe Clean and Run All Clean View Report E Messages Reading file Figure 36 Selecting Full NetFusion Synthesis and FPGA Programming Once you are ready to synthesize and program the SmartFusion2 FPGA on the M2S SOM F484 housed on NetFusion select the option shown above Note This should take around 90 minutes on a standard Windows 7 8 PC 45 development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 8 References Please refer to online documented support at the Microsemi reference center For M2S SOM F484 hardware documents please visit the Emcraft hardware for the SOM F484 If you need Libero references from Emcraft this will illustrate the default designs that NetFusion was built from in order to achieve the baseboard functionality iol 46 Q development e NINE WAYS NetFusion Libero Starter Project Helper 9 Contact Nine Ways Research amp Development Ltd V1 0 July 2014 E Mail pbates nineways co uk Internet WWW nineways co uk UK Unit G 15 iDCentre Lathkill House rtc Business Park London Road Derby DE24 8UP United Kingdom 44 0 1332
22. e Select Instantiate in M2S_ SOM or whichever sheet is displayed on the right pane of Libero IDE The core will appear in the design for you to move and anchor ready for connection routing 43 000 0200 research 0007 and Q development NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 Note f the core has errors the error report page will appear and the instantiation will not occur 7 2 1 Building and Synthesizing the NetFusion Design Open the Top Level SOM and the MSS sheets Start with the MSS and right click Generate Component If errors eliminate then perform previous instruction over again Once successful move to the SOM sheet Right click Generate Component If errors eliminate then perform previous instruction over again Once successful move to the Top Level sheet Right click Generate Component If errors eliminate then perform previous instruction over again 1012 44 NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 Libero C NetFusion M2S SOM F484 CAT5 NetFusion F484 prix Project File Edit View Design Tools SmartDesign Help H 1 abaan Ed 50 x ES SE Ded 25 5 0 Y Floorplan Constraints b Verify Post Layout Implementation L Generate Back Annotated Files B simulate Ch Verify Timing verify Power b Edit Design Hardware Configuration JPI Programming Connectivity and Interfac
23. elp E PortName A Direction 1 0 Standard Pin Number Locked BankName 1 0 state in Flash Freeze mode Resistor Pull 1 0 available Flash Freeze mode Schmitt Trigger Odt Static Odtimp Ohm LowPowerExit InputDelay Sew DEVRST_N Input RIS EXT RESET OUT Output wm D5 TRISTATE REC GMII1GTCK Output LVCMOS25 Input GMIIIRCK Input K6 TRISTATE TRISTATE off off TRISTATE off off GMITIRDO Input B1 TRISTATE off off GMILIRD1 Input 82 TRISTATE off off GMITIRD2 Input c3 TRISTATE off off GMITIRD3 Input A2 GMIIIRD4 Input C4 GMILIRDS Input 83 off off TRISTATE TRISTATE off off TRISTATE off off GMITIRDS Input E4 Input D4 H7 TRISTATE off off TRISTATE off off TRISTATE off off LVCMOS25 wii off off LIL K7 TRISTATE LL F5 LVCMOS25 Y9 G6 LVCMOS25 ws LL F6 LVCMOS25 Y10 67 LVCMOS25 w10 GMIT ITEN 26 PEER ERE EERE EERE EE EE GMITITER LVCMOS25 vii Ports Package Pins Package Viewer J Ready Fam SmartFusion2 Die M2S050T Pkg 484 FBGA Figure 3 Example of Top List I O Ball Assignments research 6667 and d
24. enly appear and you must then compile this sheet before the main synthesis Note you can instantiate normal IP cores into this top sheet if you wish and it makes sense according to your design requirements This is just the starter project so everything by default is kept in the lower SOM module But this can change rapidly as your customization starts to take effect development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 5 NetFusion Libero IDE SoC SOM Level The inner SOM sheet of the NetFusion starter Libero project contains all of the default designs and linkage The below overview screenshot shows a rats nest but the following sub sections illustrates the different parts in more detail Note ncidentally the highlighted module in the darker blue below is the MSS ARM cortex processor aL ME Figure 7 Screenshot of Lower Level SOM sheet Q research 00072 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 5 1 Emcraft Systems The above figure overview encapsulates the whole of the NetFusion SOM sheet However it was built on the basic project supplied currently by Emcraft They designed and developed the M2S SOM F484 that is housed on the NetFusion baseboard PCB Various IP cores were added to accommodate the need to support and facilitate the vast multitude of NetFusion s PCB hardware avai
25. ermining the temperature incredibly simple Note the memory interface from the ARM MSS is an APB interface counter16 0 clkout reset counter 15 0 Figure 13 Temperature Sensor Logic 22 000 O research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 5 7 CoreGPIO The vast majority of the hardware on the NetFusion PCB is connected through this core The obvious exceptions are the Ethernet pathways RS485 UART and the SPI audio input output However all of the 12C Relays I O expanders Real Time clock IC voltage monitor expansion I O and all other slow speed communications are handled through this 0 instantiated block It is visible to the ARM MSS processor via an APB interface memory bus Lines can be configured as inputs or outputs and are all individually controlled and observed by the uClinux UIO device driver C code bit Dalla al Oe Le Lt Jabatan Figure 14 Main PCB GPIO Interface with the ARM Processor 23 000 research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 5 8 CoreUARTapb As there is no way in the SmartFusion2 ARM MSS block for standard UART connections dev ttySO and dev ttyS1 already used the RS484 PCB hardware has to be controlled and handled from a fabric UART core This was instantiated as CoreUARTabp 0 and has an APB connect
26. es o Improved constraints file management in the Libero SoC Project Manager constraints and Floorplan constraints are managed in separate PDC files for Training Webcasts SmartFusion2 links open Help o Improvements in constraint implementation with an updated Smart Time O Editor and Floorplanner links open Help o Advanced programming features available in the new Security Policy Manager link opens Help to Security Policy Manager topic o Anintegrated programming flow link opens Help to SmartFusion2 Programming Tutorial SmartFusion nerinherals documentation is available from within the tool and on the web What s New in Libero SoC Microsemi SoC Website Qe Warrings Checking for software updates inzo software Update Your software is up to date Figure 1 Libero IDE Boot Up Screen 000 research 00072 and development NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 1 4 NetFusion When purchasing NetFusion an important component of the overall product is the Libero starter project that is provided by Nine Ways Research amp Development Ltd This is downloadable from Nine Ways R amp D Ltd and when expanded into a target directory on your development PC provides an immediate project for your needs Instead of having to start and debug creating an ARM sub system with all of the supporting IP cores required to have a functioning NetFusion PCB just use
27. ese guides contain details about using ModelSim ME Libero s integrated simulation tool Refer to the documentation included with ModelSim ME for more information ModelSim ME documentation is also available at http www microsemi com products fpga soc design resources design software liberosoc Documents Synopsys Synplify Pro ME Documents include release notes user s guide tutorial reference manual and license configuration and set up Refer to the documentation included with Synopsys Synplify Pro for more information Synopsys Synplify Pro ME documentation is also available at http www microsemi com products fpga soc design resources design software libero soc documents iol 11 000 eve research and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 2 Downloading New IP Core s into the Libero IDE Installation Reports 25 sow E 25050 SOM FG484 amp X ES 22522242 AQ gt Arithmetic _ Bus Interfaces Clock amp Managem DSP Vo Macro Library Memory amp Contro Peripherals Processors Tamper downloading core 10 of 67 P Desgnr Design Hierar Stimulus Catalog og E Gens Aere One Downloading Actel DirectCore COREDES 3 0 106 OK Downloading Actel DirectCore CORESDR 4 0 115 OK Downloading Actel DirectCore corepwm 4
28. ess slave slot 4 MO can access slave slot 5 can access slave slot6 MO can access slave slot 7 MO can access slave slot8 can access slave slot9 can access slave slot 10 MO can access slave slot 11 MO can access slave slot 12 MO can access slave slot 13 MO can access slave slot 14 MO can access slave slot 15 Select AXI channel ID width Testbench User License RTL 7 Figure 20 Default AXI Configuration 29 0 research 00072 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 Configuration r Memory space Memory space Address rani 0 00000000 OX7FFFFEET 0 80000000 OXFFFFFFET r Allocate memory space to combined region slave Soto Slot 2 Slot 3 Slot 4 Slot6 Slot7 Slot8 Slot 10 Slot 11 Slot 12 Slot 14 Slot 15 Enable Master access MO can access slot 0 M1 can access slot 0 M2 can access slot 0 M3 can access slot 0 MO can access slot 1 M1 can access slot 1 M2 can access slot 1 M3 can access slot 1 MO can access slot 2 M1 can access slot 2 M2 can access slot 2 M3 can access slot 2 MO can access slot 3 M1 can access slot 3 M2 can access slot 3 M3 can access slot 3 MO can access slot 4 M1 can access slot 4 M2 can access slot 4 M3 can access slot 4 Hep Figure
29. evelopment NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 Hzc Es 1 O Editor PortName A Direction Standard Pin Number Locked BankName 1 0 state in Flash Freeze mode Resistor Pull 1 0 available in Flash Freeze mode Schmitt Trigger static Odtimp Ohm Low Power Exit InputDelay Slew TRISTATE None No off off off Off Off Input OTG DATAO Inout OTG_DATAL Inout OTG DATA2 OTG_DATA3 OTG_DATA4 TRISTATE None None off None off off None off off None off off None off off SS LUIS SE LE ST off off off off off off None None None None off SIS None None off off off off off off off EE EE EE EE EE off ISTE SE S USE ajajaj Die M2S050T Pkg 484FBGA constraint M2S_SOM_FG484_TOP_designer constraint M2S_SOM_FG484_TOP_synthesis g Floorplan Constraints gt Implement Design Ay synplify log 25 SOM srr run options txt Compile lt gt Synthesize M2S SOM rwnetlist log 4 b Verify Post Synthesis Implementation 25 SOM compil Bl Simulate 25 SOM Compile 25 SOM combinatio a
30. gning with Microsemi Rad Tolerant FPGAs Antifuse FPGAs and Legacy amp Discontinued Flash FPGAs and managing the entire design flow from design entry synthesis and simulation through place and route timing and power analysis PCN 1108 Silicon Family Support in Libero IDE Libero IDE Software Features Powerful project and design flow management e Full suite of integrated design entry tools and methodologies e SmartDesign graphical SoC design creation with automatic abstraction to HDL e P Core Catalog and configuration e User defined block creation flow for design re use e Synplify Pro ME synthesis fully optimizes Microsemi FPGA device performance and area utilization Synphony Model Compiler ME performs high level synthesis optimizations within a Simulink amp environment 000 research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 e Modelsim ME VHDL or Verilog behavioral post synthesis and post layout simulation capability Physical design implementation floor planning physical constraints and layout e Timing driven and power driven place and route SmartTime environment for timing constraint management and analysis SmartPower provides comprehensive power analysis for actual and what if power scenarios Interface to FlashPro programmers e Post route On Chip Debug Tools and Identify ME debugging software for Microsemi flash designs Silicon Exp
31. he developer knowing that all the NetFusion traces coming into the M2S SOM F484 are wired into the SOM level of the fabric design Changes are therefore quick and easy to then re assign in that lower level sheet to new instantiated IP cores of the user s choice The category of wires left terminated and not used are the GMII Ethernet pathways Users can download and use Vendor specific MAC SWITCH cores or chose to privately purchase cores from reputable design houses such as MorethanlP All other used hardware on the NetFusion PC is wired and connected in the SOM layer to GPIO SPI UART USB I2C etc as standard in the starter project If you decide to write and author your own IP cores in Verilog or VHDL you can drop and place the code into the Project Dir hdl directory Note Once you have started to customize and tailor the project to your own needs and functionality obviously renaming the project is easy just rename the project directory and inside that directory just rename the prj file Close and re open the Libero IDE 000 research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 1 6 Documentation Checklist Libero SoC User s Guide Explains how to use the Libero SoC Project Manager including Designer and SmartDesign SmartFusion2 and IGLOO2 SmartTime I O Editor and ChipPlanner User s Guide Provides details about using SmartTime for timing analysis placing macro
32. ion to the MSS block The uClinux device driver for this hardware access the core as a block of memory and the FIFO RX and TX data is stored in the fabric core The RX ad TX signals to the NetFusion PCB hardware are TTL levels and then get converted to RS485 voltage signals in the electronics Figure 15 RS485 UART 24 or 000 OG research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 5 9 CoreSPIO 1 Running as separated IP cores instantiated in the fabric to achieve higher speed sampling by SPI software SPI blocks These are CORESPI_0 CORESPI_1 and use an APB interface to the ARM MSS sub system Each core has a 4 wire SPI bus routed out of the FPGA to the wider NetFusion PCB hardware These SPI interfaces connect to DAC and ADC stereo IC devices This allows for audio to be sent and received from the PCB and the digital samples can be processed by the ARM processor from network traffic if necessary SPI is used as it is full duplex and runs at over 1MHz during operation However bottlenecks in the processor application code and also human audible hearing limitations keep realistic sampling operations around lt 10KHz Figure 16 Stereo Audio Line IN amp Line OUT 25 doy 000 research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 5 10 BIBUF Throughout the NetFusion starter project s fabric
33. it View Tools cx I E 25 50 x m25050_sOM_FG484_TOP amp x gt Create Design System Builder 4 amp Configure MSS Create Constraints 1 0 Constraints constraint jo M2S050_SOM_FG484_ constraint io M2S_SOM io pdc 9 constraint io M2S_SOM_FG484_TO Timing Constraints synthesis M2S_SOM_sdc sdc constraint M2S_SOM_FG484_TOP_ S constraint M2S_SOM_FG484_TOP_ Qi Floorplan Constraints Design gt Synthesize gt Verify Post Synthesis Implement Figure 34 Importing a single Verilog VHDL file into the NetFusion Libero Project From time to time you may want to deviate from the default NetFusion Libero starter project If you need to add catalogue cores especially for the fabric macros then download using the vault Also as illustrated above you also may wish to import 3rd party source IP cores To do this on the panel on the left of the Libero IDE right click on Create HDL and then select mport Files This will bring the Verilog VHDL into the main system You can check if the source code has syntax errors and is valid for the synthesizer Libero Synplify Pro that Libero uses This mechanism enables the NetFusion project to be customized and built on for a users system requirements iol 42 000 research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 7 2 Inst
34. lable to the ARM MSS sub system in the SmartFusion2 FPGA on the Emcraft M2S SOM F484 housed on NetFusion as one product As the MSS can only drive and support some of the pins on the SOM unit there was a requirement therefore to add more IP cores in the fabric to interface through the I O assignments to the PCB hardware not connected directly to the MSS These additional cores and the default statutory parts of the SOM design in the Fabric are described in the sub sections below 5 2 AMBA DMA Controller mtip amba controller 0 core is instantiated to provide 3 party MAC and SWITCH IP cores that the user may instantiate themselves with FIFO interface The DMA core will act as a DMA Master in the fabric on behalf of a connected FIFO MAC Refer to AMBA DMA Controller documentation For the Technical PDFs refer to Nine Ways support mtip amba dma controller 0 5 a uH D bb tt H Figure 8 AMBA DMA Controller 17 000 research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 5 3 ULPI UTMI OTG USB On the SmartFusion2 F484 package that is used with Emcraft s M2S SOM F484 System On Module the ULPI MSS interface is not supported However the UTMI OTG USB signals are supported As the track routing and the IC USB device on the NetFusion PCB support ULPI an IP core in the fabric is require to convert between the two different USB On The Go p
35. lorer debugging software for Microsemi antifuse designs 1 2 Installation Libero software is downloadable for free from http www microsemi com products fpga soc designresources design software libero soc downloads Some Libero features are optional during installation You can minimize the disk space required by only installing tools you use You must have a license to run Libero the license type that you obtain determines what devices you can use and what IP is included The following license types exist for Libero Libero Platinum All devices and RTL IP Bundle Libero Gold Limited devices and Obfuscated IP Bundle View the complete descriptions of the above Libero installations at http www microsemi com products fpga soc design resources design software libero soc licensing View the IP Bundle contents at http www microsemi com products fpga soc design resources ip cores Libero installation is covered in Installing Libero Software on page 16 Note You must have Admin rights on the installation machine to install Libero SoC 000 research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 1 3 Starting a Project and Basic Understanding Before attempting to modify or implement any project in Libero it is advised that you download and read the following PDF references System on Chip installation Libero SoC v11 3 User s Guide Libero SoC Quick Start
36. nects into the SmartFusion2 FPGA and directly into the ARM MSS Special Note on the SFP SERDES variant of NetFusion PCB the dedicated SOM RJ45 is the 27 port on the dual HALO Once in the MSS the Ethernet MAC receives the connections which then provide a memory interface internally for the ARM uClinux device drivers for the network interfaces Note The connections route to the fabric before going up through to the I O assignments It is important to emphasize that with NetFusion three of the RJ45 10 100 1000 ports use a separate Marvell PHY that routes into the SOM sheet of the starter project and terminates at unused block 01 Special Note on the SFP SERDES variant two of the 1Gb s ports are 1 25Gb s SERDES However the dedicated 4th port always allows MSS and ARM gateway access to the network Benefits of this architecture can provide IP routing functionality for the user This is due to the link between the MSS MAC and the fabric MACs only being visible to each other in the uClinux IP stack of the kernel iol 37 000 research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 64 MSS CCC Clock Source CLK_BASE 83 000 MHz IV Monitor FPGA Fabric PLL Lock CLK_BASE_PLL_LOCK r Cortex M3 and MSS Main Clock CLK 166 MHz 166 000 MHz MSS CCC MDDR Clocks MDDR CLK M3_CLK 1 y 166 000 MHz Uso DDR SMC FIC 2 83
37. ous this MSS module enables the APB interface to access the GPIO SPI and UART in the NetFusion SmartFusion2 fabric Note this is also an APB Master as the ARM processor has complete control jo 40 NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 6 8 FIC 2 Peripheral Initialization cortex y Fabric DDR and or SERDES Blocks Iv wok li ONFIG PRESET Figure 33 APB Peripheral Hardware Configuration As described earlier in this document the SmartFusion2 FPGA is setup and primarily configured by boot up software executed by the ARM processor This can be bare metal code or early boot code from uClinux called u boot This MSS module block enables the signals to connect a feedback APB interface from the ARM processor to the other peripherals in the MSS itself It seems an overkill but that is the architecture we are ruled by it seems In the case of NetFusion we configure the 0 and FIC 1 fabric interface controllers and also select the AXI Slave interface for the MDDR block Important Note do not ever remove this feature from the design of NetFusion The system will not operate if deleted 101 41 000 0200 research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 7 Adding IP Cores from Verilog VHDL 7 4 Importing Source Files Libero C NetFusion M2S SOM F484 CAT5 NetFusion F484 prjx n Ed
38. rface Interface Type Use Master Interface Use Slave Interface Advanced AHBLite Options Use Bypass Mode AHBLite only Expose Master Identity Port FPGA Fabric Address Regions MSS Master View c c r Figure 31 AHB APB Fabric Interface 1 The NetFusion FIC_0 has been chosen to be assigned for the AHB Lite fabric interface It is a MASTER which connects to the SLAVES in the fabric as the ARM processor has complete control By default the AHB Lite only interfaces to the AMBA DMA Controller used for 3rd party Ethernet IP cores Although the DMA Controller uses AXI for the main data throughput the AHB Lite is used to access the configuration registers Note you will observe that Fabric Region 2 0x7000000 Ox7FFFFFF has been allocated to the next FIC 1 block next sub section The configuration on the left panel above selects mapping for both FIC 0 and FIC 1 NetFusion assigns Fabric Region 2 to the APB memory interface so that the UART SPI and GPIO can be accessed in the fabric otherwise only this AHB Lite interface would be mapped which would severely limit the NetFusion functionality and capability 39 2000000 2 60 Ot NetFusion Libero Starter Project Helper V1 0 July 2014 6 7 FIC 1 EX Mss Fabric Interface Controller FIC 1 Configurator Figure 32 APB3 AHB Lite Fabric Interface 2 Using the configuration from the previous 0 block previ
39. rotocols and signals This has been instantiated as ulpi port 0 This OTG core was used from OpenCores at http www opencores com and resides in the NetFusion starter project s hdl sub directory SIRE Figure 9 ULPI UTMI USB Converter IP Core 7 10 000 research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 5 4 CoreSF2Reset This core is used to co ordinate the reset across all of the FPGA in strict timed sequence It is important for the peripheral logic to be released after the MSS ARM processor and then the fabric logic following the MSS This is a standard Libero ACTEL core from the vault The EXT RESET OUT signal is routed out of the FPGA device to the NetFusion PCB The input to this core is the POWER ON RESET This core was instantiated as CoreSF2Reset 0 Figure 10 SmartFusion2 Reset Controller IP Core 000 0 research 000 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 5 5 FCCC The entire FPGA sub system comprising of the MSS ARM processor and the main fabric run on clocks all generated from this core It is the main coordination of the clock lines that are distributed The input is 12MHz from an off chip crystal IC The CCC PLL divides down the 12MHz source by 12 to 1MHz Then this is multiplied up by differing amounts for GLO GL1 and GL2 You can add more clock PLL lines as you
40. s floor planning and viewing chip resources for SmartFusion2 MultiView Navigator User s Guide includes documentation for ChipPlanner PinEditor IJO Attribute Editor and NetlistViewer in MVN Provides details about placing macros floor planning and viewing chip resources contains information about using NetlistViewer in the MultiView Navigator to view your netlist describes how to use the PinEditor in MVN describes how to use the I O Attribute Editor tool Design Constraints User s Guide Provides a complete reference for creating and modifying timing physical and netlist optimization constraints in Libero SoC including families and file formats supported for each constraint It also describes how to create and modify I O constraints with the I O Attribute Editor before compiling your design SmartPower User s Guide Describes how to use SmartPower for power analysis SmartTime User s Guide Describes how to use SmartTime for timing analysis and how to set clock constraints Tcl Command Reference Lists all the Tcl commands and parameters for the Microsemi software tools Analog System Builder FlashROM and Flash Memory System Builder User s Guide Describes how to use the FlashROM generator the Analog System Builder and the Flash Memory System Builder SmartGen Cores Reference Guide Provides descriptions of cores that can be generated from the Catalog using the SmartGen Core Builder 101 10 000 resear
41. the provided project From installation you can program the IDE project once synthesized into your NetFusion product using the FlashPro4 USB device This will provide the standard functionality in the Smartfusion2 FPGA fabric on the M2S SOM F484 System On Module to see normalized operation In the software bundle to this product the uClinux device drivers will drive and control the hardware on the NetFusion PCB through the IP cores in this project for the FPGA fabric Users can contact Nine Ways R amp D for special functionality to be developed and deployed but this serves as an addition to this starter Libero IDE project Moreover in conjunction with MorethanIP GmbH customized and locked down projects can be tailored for customer requests but that also is separate to this project 1 5 Product Development At the point where the Libero IDE SoC has been installed the NetFusion starter project has been downloaded and exploded into a target directory on your PC the project has been loaded synthesized programmed and shown to be running on the NetFusion PCB product you are ready to begin your development As standard the main fast Ethernet pathways into the SmartFusion2 FPGA fabric are wired in through the FPGA balls assigned in the I O editor brought down through the Top Level and then into the SOM level of the design in the project They then terminate at a dummy IP core for all un assigned wires this makes life a lot easier for t
42. wish when you are modifying the design Figure 11 Clock PLL Macro Core The core as been instantiated as CCC 0 There is also a LOCK output signal that is used by the MSS to determine when the PLL has settled and locked onto the desired output frequencies All clock outputs are digital square waves 000 e oe research 0007 and development e NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 A Advanced options have been modified The information displayed in this tab might be inaccurate please use the advanced tab for the Figure 12 PLL Clock Macro Settings Output signals GLO and are distributed to the memory bus and the DMA Controller GL2 is the main base clock frequency for the 166MHz ARM processor which that divides down internally 21 000 OG research 000 and development NINE WAYS NetFusion Libero Starter Project Helper V1 0 July 2014 5 6 Counter GPIO NetFusion PCB has an on board temperature sensor The output of which is a square wave signal who s frequency is equivalent to degrees Kelvin down to absolute zero This signal is routed into the SmartFusion2 FPGA fabric and clocks the 16 bit counter counterf6 0 The counter s 16 bit output value is wired into GPIO input coreGPIO_ 1 which is memory addressable from the ARM uClinux applications This serves as a simple 32 bit memory location to read and makes the software algorithm for det
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