Full report - ECE - Cornell University
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1. ij WA Hill dell UN W i IN NAHEN ATH HAH HOTTIE IM dl Zeil 42 i Figure 3 1 SD Read Write Speed Test Multiple tests are executed to fully validate the SD RW performance The results 1s shown in Figure 3 2 Test Read Speed KB s Write Speed KB s 0 1356 1391 2 1270 3 1396 Average 1353 25 Figure 3 2 Multiple Pressure Testing Results 20 3 2 Firmware Transmission Speed PC to Upgrader This test s an enhanced test that covers the test in previous section plus the USB transmission speed test The firmware transmission speed can directly impact user experience The expected write and read speed should be lower than direct SDIO R W speed since USB is involved In real test the R W speed is actually limited by the FS USB interface 12Mbps Before doing this test the SD card is formatted with official formatting tool to guarantee the accuracy of testing results The test includes single file and scattered files R W test with different size The result is shown n Figure 3 3 Si Single File Scattered Files 8 Files ize Read Speed KB s Write S peed KB s Read S peed KB s Write Speed KB s 512 KB 450 1 MB 671 502 2 MB 1017 519 oo r O OO SEN IS 4 MB 1123 704 90 517 USB Virtual Disk Performance 1200 1000 8 6 4 200 f 0 Read Speed KB s Write Speed KB s Read Speed KB s Write Speed KB s c c pus C3 oS C3 Single File Scatt2. AVR GNU Linker 2 Miscellaneous 7X General Bee ee T OutputFiles Other Linker Flags WI section start 4 B AVR GNU C Compiler 7X General Preprocessor F Symbols 74 Directories Ff Optimization 3 Debugging Bootloader Start Address Warnings 74 Miscellaneous 4 B AVR GNU Linker 7X General 7X Libraries Ff Optimization F Memory Settings Miscellaneous The last problem needs to solve is how to jump from bootloader to application There exists two ways to perform this action One way is to use assembly function asm jmp 0x0000 n another way is to define a null application function which starts from 0x0000 These two ways are both valid except for that the second solution actually performs a function call which will push intermediate variables into stack and it will also slightly increase the bootloader size In this project the first solution 1s applied An important note here 1s that all initialized peripherals must be de initialized to perform a clean jump so that the application will run without register contamination After the bootloader is set up a simple test application which simply blinks the LED is created to verify the bootloader functionality 2 2 4 Simple GUI Design using TFT LCD with Touch Function To make it much easier to use a simple GUI 1s created to allow users to operate the firmware upgrader easily The basic functionalities designed in this demo includes Browse SD Connect PC
3. Create directory Remove file and Directory SD card speed test via SDIO interface Remove U Disk Enabel U Disk Write Read File Test egin to Write File SpeedO00 txt 2048KB 0 2 3 4 5 6 7 5 B Write Time 4545ms Average Write Speed 461419B S 450KB S Begin to Read File 2048KB Read Time 687ms Average Read Speed 3052622B S 2981KB S Figure 2 13 SDIO Read Write Speed Test The result shown above is expected the reason that write speed is much slower than read is because Write operation requires file system to search free space to store new data which consumes a lot of time What s more the write operation also needs to read file allocation table and perform verification process after the write operation is over 2 2 3 Slave Bootloader Design AVR To verify the upgrader a test bootloader must be designed In this project the AVR board ATmegal6 used in ECE4760 to verify the basic functionalities of firmware upgrader This AVR bootloader is also a demonstration on how to use Smart Link protocol To start with the AVR bootloader region and size must be clarified The flash region allocation for ATmegal284p is shown in Figure 2 14 15 Program Memory 0x0000 Application Flash Section Boot Flash Section Ox1FFF OxSFFF Ox7FFF OxFFFF From the figure above we can see that the boot flash section is at the bottom of the flash All we need to do is to make sure the bootloader
4. msg buff pkg len 1 pkg_crc16 amp OxFF00 gt gt 8 uinti6 t amp msg buff pkg len 2 pkg crc16 return J SMTLINK Firmware Update Response Message SOF VERLEN HDRCRC8 SND RCV SEQ CMDTP CMDID DAT PKGCRC16 Request Message Length Byte 12 1 ij inline void SMTLINK PackFWUpdRespMsg SMT Ver TypeDef smt ver uints t sdr id uints t rcv id uints t msg buff uint16 t pkg_crci16 uint16 t pkg len uint8 t dat st loc dat st loc smt ver SMTLINK P2P VER SMTLINK P2P DAT START LOC SMTLINK BUS DAT START LOC pkg len smt ver SMTLINK P2P VER SMTLINK P2P FWUPDRESPMSG LEN SMTLINK BUS FWUPDRESPMSG LEN SMTLINK PackMsgHead smt ver SMTLINK PKG TP RESP SMTLINK PKG NO ACK SMTLINK CMD REQ FW UPD sdr id rcv id msg buff pkg len msg buff dat st loc 09 00 pkg_crc16 crci16 update SMTLINK CRC16 KEY msg buff pkg len 2 msg buff pkg len 2 pkg_crc16 amp 0Ox00FF LSB Firstly msg buff pkg len 1 pkg_crc16 amp OxFF00 gt gt 8 uint16 t amp msg buff pkg len 2 pkg crc16 return SMTLINK Firmware Data Receive Request Message SOF VERLEN HDRCRC8 SND RCV SEQ CMDTP CMDID DAT PKGCRC16 Request Message Length Byte 12 13 inline void SMTLINK_PackFWDataRcvReqMsg SMT Ver TypeDef smt ver uint8_t sdr id uint8_t rcv_id uint32 t fw_size ui
5. SD Speed Test Connect Device and Upgrade Device The whole GUI s color scheme is designed based on WinXP style Shows the simple GUI interface 17 A Figure 2 17 Simple GUI Design for Firmware Upgrader The TFT LCD main controller used in this project is RA8875 which owns 768KB DDRAM Generally operating the LCD equals to operating the display RAM STM32F407 owns hardware FSMC Flexible Static Memory Interface which can be used to efficiently write to or read from the DRAM All we need to do 1s to assign the address for the display RAM The address for display RAM is actually defined by hardware connection and the BANK region of FSMC mapped memory In this project the RS signal write register or write RAM data of RA8875 is connected to FSMC_A18 note that in 16 bit mode the internally generated hardware address HADDR 25 1 is actually the value of hardware FSMC address line A 24 0 See Figure 2 18 In this scenario FSMC A18 is corresponding to the address HADDR 19 Also we selected address 0x6C00 0000 of FSMC Bank 1 starts from 0x6000 0000 for display address STM32F4xx User Manual Table 168 Note Then the actual address for RA8875 registers is Ox6COO 0000 1 lt lt 18 1 18 Address Banks Supported memory type 6000 0000h NOR PSRAM 6FFF FFFFh 7000 0000h 7FFF FFFFh 8000 0000h 8FFF FFFFh 9000 0000h 9FFF FFFFh In actual programming we can simply define the register RAM
6. protocol design master firmware design slave bootloader design and s mple GUI design After the hardware platform is selected the first step 1s to design the communication protocol and then use the simplest hardware interface to verify its basic functionality Then the bootloader for AVR is designed to quickly check the stability of communication The final step is to finalize the protocol and exploit high speed data transmission via DMA 2 1 Hardware Design The hardware design includes core MCU selection and interface level conversion circuit design Note that in this project to save time a development board 1s used to implement the firmware upgrader but it can definitely re designed in the future to reduce cost and size 2 1 1 Hardware Platform Selection The hardware of this firmware upgrader should own many common communication interface meanwhile it must own fast storage interface such as SDIO USB HOST In this case the storage media will be SDHC TF card since it 1s very common and can be embedded on board A good product should put user experience as the most important factor even though t may be tough for hardware and firmware design Based on considerations above the core MCU Micro controller 1s chosen from ST Cortex M4 Series take STM32F407IGH for example it has abundant peripheral devices except for the common communication interface above t owns USB OTG Host Slave FSMC Flexible Static Memory Interf
7. Message n5 HD H4 51 55 ES HH HH 8H H2 HH 37 62 Press any key to continue Figure 2 6 Test Outputs from VC Test Bench Figure 2 6 shows the results of P2P message Protocol Version B validation As soon as it passed the validation the next step 1s to utilize the Smart Link It must be lightweight be compatible to most popular C compilers and be efficient To achieve this a Header File Only Smart Link 1s further designed to meet these requirements Specifically inline functions are widely used in Smart Link The purpose of inline functions is to achieve the same performance as macro function and it can also be further utilized based on different C compilers For instance to avoid the compiler not to inline the functions some C compilers let users to use some special assignments to force the function to be inlined attribute always inline The core function that will affect the protocol efficiency would be the function which is used to decode the message Considering the compatibility and mobility the function should be called continuously as long as the interface receive buffer is not empty The state machine of decode function is shown in Figure 2 7 To verify real bootloader application size with Smart Link a AVR bootloader based on Smart Link is designed to explicitly validate the protocol from the perspective of generated code size and RAM consumption Smart Link need buffer for package decoding and bootloa
8. MsgInfo TypeDef inline SMT Ver TypeDef SMTLINK GetPkgVer uinti6 t pkg verlen return SMT Ver TypeDef pkg verlen amp xFC gt gt 10 inline uint16_t SMTLINK GetPkgLen uinti6 t pkg verlen return pkg verlen amp x 3FF FW UPD CHECK HDR CRC 1 inline uint16_t SMTLINK PackVerLen SMT Ver TypeDef version uinti16 t len return uint16_t version amp x1F lt lt 10 len 8 x3FF __inline SMT Pkg TypeDef SMTLINK GetPkgType uint8 t cmd tp return SMT_Pkg_TypeDef cmd_tp amp 1 lt lt 7 inline SMT PkgAck TypeDef SMTLINK GetPkgAckType uint8 t cmd tp return SMT PkgAck TypeDef cmd tp 8 1 lt lt 6 inline uint8 t SMTLINK PackPkgAckTp SMT Pkg TypeDef pkg tp SMT PkgAck TypeDef ack tp return uint8 t pkg tp lt lt 7 ack_tp lt lt 5 inline void SMTLINK PackMsgHead SMT Ver TypeDef smt ver SMT Pkg TypeDef pkg tp SMT PkgAck TypeDef ack tp SMT CmdID TypeDef cmd id uints8 t sdr id uint8 t rcv id uints t msg buff uinti6 t msg len uint16 t pkg_verlen uint8 t pkg ack tp uint16 t pkg_seqnum uint8 t cmd id loc pkg verlen SMTLINK PackVerLen SMTLINK P2P VER msg len pkg ack tp SMTLINK PackPkgAckTp pkg tp ack tp Request Package Need ACK cmd id loc smt ver SMTLINK P2P VER SMTLINK P2P CMD ID LOC SMTLINK BUS CMD ID LOC pkg seqnum 0x0000 msg buff SMTLINK STX LOC SMT
9. RW operation address shown n Figure 2 19 define define define define RA8875_BASE RA8875_REG RA8875_RAM RA8875_RAM_ADDR uint32 t execeoeoeo exeooo0000 IO uint16 t RA8875 BASE 1 lt lt 18 1 Ze FSMC 16bit Mode A18 is mapped to HA19 IO uinti16 t RA8875 BASE FSMC 16bit Mode normal address wi RA8875_BASE With this kind of definition we can simply RW either RA8875 s RAM or registers by simply reading or writing to corresponding address There still exists so many utilization that can be applied to efficiently operate the LCD which will not be further discussed due to document space limitation 19 3 Testing and Results To fully verify the whole system appropriate testing s also very important The test includes Internal SD card R W Test PC to upgrader R W speed test UART to AVR firmware upgrading test and CAN to STM32 firmware upgrading test 3 1 Internal SD card R W Test This test aims to validate both SDIO 4 bit mode and Fat FS performance The test program is designed to recursively write natural numbers to SD card by creating a test text file 2MB and then read it out By using internal System Tick to count the read write time RW speed can be explicitly calculated in a very accurate way As mentioned above user can test SD card any time Figure 3 1 shows the one of the testing results 02 d Al An d 1 X T1 lief ti INNE THEE d
10. code 1s within appropriate size Once we define the bootloader start address memory location should be assigned for ISP programming According to ATmegal284p datasheet the maximum bootloader size is 4096 bytes 4KB this means that the size of bootloader application cannot exceed 4KB It is a good way to validate the Smart Link protocol to see whether it is light enough or not Figure 2 15 shows the FUSE configuration for bootloader size selection Boot reset address Application Boot loader End application start boot BOOTSZ1 BOOTSZO Boot size Pages flash section flash section section loader section 1 1 T owas 4 oowm ororr ortm oerrr ororr orem IT o Leen s oowo orerr orom orrrr orerr eco e 1 Leg 1 10000 0576 lan sem oere omo e 0 006 wanae s oowo nerrr orwo orrrr werrr exo Note that if we program the BOOTRST fuse bit to 0 the program counter after reset will always be the start address of bootloader To make sure that the AVR Studio can correctly program the bootloader into configured flash region its linker must be 16 configured to bootloader start address Also note that Figure 2 15 shows the address in WORD format and GNU linker use BYTE address to specify programming location so if the boot reset address is OxFOOO then corresponding linker byte address is Ox 1 E000 The linker configuration is shown in Figure 2 16 2 AVR GNU Common
11. data After slave successfully receives the data and program the firmware data into flash it should response to the master to report the programming results Note that the difference between Master and Slave is not absolute If module B is connected to the upgrader indirectly via Module A then Module A should be able to perform all master functionalities to Module B in order to perform indirect firmware upgrade Now that all the basic functionalities are defined the protocol package format must be carefully designed to meet encryption and package checksum requirements Also it must be able to be applied in either Peer to Peer or Bus connection The package anatomy is shown in Figure 2 4 and Figure 2 5 Ver Len HDR CRC 3 Payload TOT CRC 16 Ver Len HDR CRC 8 Sender Receiver Payload TOT CRC 16 Protocol Version A is suitable for those interfaces which support Multi Host and the low layer protocol itself can distinguish different communication peers For instance CAN low layer protocol contains Arbitration Field which is composed of Identifier and RTR Remote Transmission Request bit With this field we can easily identifier the message sender even though this field is actually used for communication arbitration CAN Specification 2 0B Compared to protocol version A version B is kind of verbose However this kind of protocol format is necessary for those Peer to Peer communication interface
12. service routine to be handled and current Smart Link may need to be modified to cooperate with this kind of design As mentioned in the abstract a PC Client application can be designed to achieve Hardware Customization user can define system module inter connection interface type and more important automatically fetch the latest stable firmware from GIT software management system It indeed needs to be carefully designed to make the upgrader much more easy to use Another improvement is upgrader s own GUI design Current project implemented a TFT LCD to improve user experience it can be replaced with small OLED module and simple buttons 23 5 Acknowledgements I would like to thank my advisor Professor Bruce Land for his trust and encouragement His trust always give me power to overcome one difficulty after another also he gave me so many valuable suggestions that make this project much easier to finish I also learned a lot from his class his bottomless knowledge always brings me to an unknown field I feel so lucky to be one of his students I also want to thank Cornell ECE for providing me with such a great place to learn share and move forward Learning in Cornell would be an indelible experience for me Sincere thanks to all my professors and excellent classmates 24 6 Reference 7 8 LL 9 ST Microelectronics STM32F4 Series User Manual Rev 2 http www st com SI Microelectronic
13. that t can only perform unidirectional level conversion To solve this problem MOS FETs with backward diode between D and G was implemented to realize voltage level shift This level shifter Figure 2 3 1s also widely applied in I2C circuit to realize voltage conversion Vpp1 3 3 V Vpp2 5 V Pe Ro Un SDA AJA SDA gt SCL Zeil SCL2 3 3 V DEVICE 3 3 V DEVICE 5 V DEVICE 5 V DEVICE 2 2 Software Design As mentioned in previous section the software design contains communication protocol design SMARTLINK Protocol master upgrader firmware design and slave bootloader design This section will merge design and software evaluation if exists any together to describe each software part n detail 2 2 1 Smart Link Protocol Design The communication protocol should be able to perform basic master and slave messages functionalities described below Request Response firmware upgrade This message is used to check device connection or device status when slave receive this message it should response to master based on specific command Request Response firmware transmission This message tells slave device that the firmware data is about to transmit when slave receives this message t should respond with the maximum firmware segment size internal RAM size it supports Request Response firmware raw data transmission Master send this message to inform slave device to prepare to receive firmware
14. to Slave i Decode Firmware Upgrade Message verbatim include lt stdint h gt include crc_check h ifdef __cplusplus extern C endif SMTLINK Protocol Definition x SZ X Hr N SOF VERLEN HDRCRC8 SND RCV SEQ CMDTP CMDID DAT PKGCRC16 342 1 2 4 3 E E S Message Length Byte 12 n x BUS Interface Protocol Such as CAN DU IN e E WEE uisus a Se Te E musei oe i Ri P2P Interface Protocol Such as USART SPI etc 26 Message Length Byte 7 n Private define define SMTLINK HOST ID OxE5 define SMTLINK CRC8 KEY OxFE define SMTLINK CRC16 KEY OxFEFE define SMTLINK STX 0x55 define SMTLINK STX LOC 0 define SMTLINK VER LEN LOC 1 define SMTLINK VER WIDTH 6 Version 6 Bit define SMTLINK LEN WIDTH 10 Length 10 Bit y define SMTLINK GET VER dat dat amp xFC gt gt 10 dat is 16 Bit VERLEN region define SMTLINK GET LEN dat dat amp x 3FF dat is 16 Bit VERLEN region define SMTLINK HDR CRC8 LOC 3 define SMTLINK SNDR LOC 4 define SMTLINK RCVR LOC 5 define SMTLINK SEQ NUM LOC 6 define SMTLINK CMD TP LOC 8 define SMTLINK P2P CMD ID LOC 9 define SMTLINK BUS CMD ID LOC 4 define SMTLINK P2P DAT START LOC 10 define SMTLINK BUS DAT START LOC SMTLINK P2P DAT START LOC 5 define SMTLINK P2P
15. A8875 Address Definition ENEE 19 Figure 5 1 SD Read Write Speed Test anne a ae 20 Figure 3 2 Multiple Pressure Testing Resultsu a eet dt 02a 20 Figure 5 5 Firmware Transmission Speed Test acer 21 Figure 3 4 Different Interface Speed Test ann 22 1 Introduction 1 1 Problems and Motivation With the development of robot technology robotic systems are becoming more and more complex with various kinds of embedded components such as sensor camera motion control etc From the perspective of R amp D engineers it is often difficult to implement complete software version control because of different test firmware versions not to mention the Firmware Upgrading Process even if we can take good care of software version management On the other hand it is also hard to make sure each component in every robotic system has the same software firmware version In complex Robot System design software version control is vital since these components are not totally independent with each other and we need to make sure that every embedded component has the workable firmware to cooperate with other components Figure 1 1 shows the traditional way to upgrade complex system Aide Spatz GIT SW FW Version Control Component D Component C R amp D Groups Component B Component A Figure 1 1 Traditional Firmware Upgrade Process Assume that we own a good version control system firmware upgrading process is also a p
16. COMPACT FIRMWARE UPGRADER FOR ROBOT SYSTEM BASED ON IAP METHODOLOGY A Design Project Report Presented to the School of Electrical and Computer Engineering of Cornell University In Partial Fulfillment of the Requirements for the Degree of Master of Engineering Electrical and Computer Engineering Submitted by Wancheng Zhou wz233 MEng Field Advisor Prof Bruce Robert Land Degree Date May 2015 ABSTRACT Master of Engineering Program School of Electrical and Computer Engineering Cornell University Design Project Report Project Title Compact Firmware Upgrader for Robot System Based on IAP Methodology Author Wancheng Zhou Abstract This project is designed to realize fast easy firmware upgrade for complex robot systems It explores a solution for convenient firmware upgrade process based on In Application Programing IAP method With this system engineers are able to upgrade the whole complex system by simply pressing a button instead of using different kinds of programmers It can be further connected to GIT software version management system so that the latest stable firmware can be upgrade anytime In this way engineers can avoid unnecessary time lost on finding correct firmware during the R amp D process EXECUTIVE SUMMARY This project is designed to realize fast easy firmware upgrade for complex robot systems It explores a solution for convenient firmware upgrade process based on In Application Programing IAP
17. FWRCVRESPMSG LEN SMTLINK BUS FWRCVRESPMSG LEN SMTLINK PackMsgHead smt ver SMTLINK PKG TP RESP SMTLINK PKG NO ACK SMTLINK CMD REQ FW DAT sdr id rcv id msg buff pkg len msg buff dat st loc 0x0 uinti16 t amp msg buff dat st loc 1 fw seg size pkg_crc16 crci16 update SMTLINK CRC16 KEY msg buff pkg len 2 uinti6 t amp msg buff pkg len 2 pkg crc16 return inline uint16 t SMTLINK_GetFWData_SegmentSize SMT Ver TypeDef smt ver uint8 t msg buff uint8 t dat st loc uinti16 t fw seg size dat st loc smt ver SMTLINK P2P VER SMTLINK P2P DAT START LOC SMTLINK BUS DAT START LOC fw seg size uinti16 t amp msg buff dat st loc 1 return fw seg size SMTLINK Firmware Data Transmit Request Message SOF VERLEN HDRCRC8 SND RCV SEQ CMDTP CMDID DAT PKGCRC16 jt 2 4 J 2 5 9 J 2 1 41 m 3 Request Message Length Byte 12 n n 7 fw seg size NOTE Prepare firmware data before calling this function and make sure the i buffer size is sufficient T inline void SMTLINK PackFWDataTXReqMsg SMT Ver TypeDef smt ver uint8 t sdr id uint8 t rev id uinti16 t fw seq num uint16_t fw_seg_size uint8_t msg buff naw uint16_t pkg crci6 uint16 t pkg len uint8 t dat st loc dat st loc smt ver SMTLINK P2P VER SMTLINK P2P DAT START LOC SMTLINK BUS DAT START LOC pkg len
18. FWUPDREQMSG LEN 21 define SMTLINK BUS FWUPDREQMSG LEN SMTLINK P2P FWUPDREQMSG LEN 5 define SMTLINK P2P FWUPDRESPMSG LEN 13 define SMTLINK BUS FWUPDRESPMSG LEN SMTLINK P2P FWUPDRESPMSG LEN 5 define SMTLINK P2P FWRCVREQMSG LEN 25 define SMTLINK BUS FWRCVREQMSG LEN SMTLINK P2P FWRCVREQMSG LEN 5 define SMTLINK P2P FWRCVRESPMSG LEN 15 define SMTLINK BUS FWRCVRESPMSG LEN SMTLINK P2P FWRCVRESPMSG LEN 5 define SMTLINK_P2P_FWDAT_START_LOC SMTLINK_P2P_DAT_START_LOC 7 define SMTLINK_BUS_FWDAT_START_LOC SMTLINK BUS DAT START LOC 7 define SMTLINK_P2P_FWTXREQMSG_LEN segsz 12 7 segsz define SMTLINK_P2P_FWTXRESPMSG_LEN 13 define SMTLINK BUS FWTXREQMSG LEN segsz SMTLINK P2P FWTXREQMSG LEN segsz 5 define SMTLINK BUS FWTXRESPMSG LEN SMTLINK P2P FWTXRESPMSG LEN 5 typedef enum SMTLINK BUS VER 0 SMTLINK P2P VER 1 SMTLINK ERR VER 3 SMT Ver TypeDef typedef enum SMTLINK CMD REQ FW UPD 0 SMTLINK CMD REQ FW DAT 1 SMTLINK CMD TX FW DAT 2 SMTLINK CMD TX FW DONE 3 SMT CmdID TypeDef typedef enum EN UPD CHECK STX 0 EN UPD CHECK PKG CRC 2 FW PkgCheck TypeDef typedef enum SMTLINK PKG TP REQ 0 SMTLINK PKG TP RESP 1 SMT Pkg TypeDef typedef enum SMTLINK PKG NO ACK 0 SMTLINK PKG NEED ACK 1 SMT PkgAck TypeDef typedef struct SMT Ver TypeDef pkg ver uint8 t sender SMT CmdID TypeDef cmd id SMTLINK
19. LINK STX uinti16 t amp msg buff SMTLINK VER LEN LOC pkg verlen msg buff SMTLINK HDR CRC8 LOC crc8 update SMTLINK CRC8 KEY msg buff 3 if smt_ver SMTLINK_P2P_VER msg buff SMTLINK SNDR LOC sdr id msg buff SMTLINK RCVR LOC rcv id msg buff SMTLINK SEQ NUM LOC pkg seqnum amp OxFF00 gt gt 8 msg buff SMTLINK SEQ NUM LOC 1 pkg seqnum amp 0Ox00FF msg buff SMTLINK CMD TP LOC pkg ack tp msg buff cmd id loc cmd id return j SMTLINK Firmware Update Request Message SOF VERLEN HDRCRC8 SND RCV SEQ CMDTP CMDID DAT PKGCRC16 Request Message Length Byte 12 9 a inline void SMTLINK PackFWUpdReqMsg SMT Ver TypeDef smt ver uints8 t sdr id uints t rcv id uints t msg buff uint8 t idx uint16 t pkg crci6 uint16 t pkg len uint8 t dat st loc pkg len smt ver SMTLINK P2P VER SMTLINK P2P FWUPDREQMSG LEN SMTLINK BUS FWUPDREQMSG LEN SMTLINK PackMsgHead smt ver SMTLINK PKG TP REQ SMTLINK PKG NEED ACK SMTLINK CMD REQ FW UPD sdr id rcv id msg buff pkg len dat st loc smt ver SMTLINK P2P VER SMTLINK P2P DAT START LOC SMTLINK BUS DAT START LOC for idx 0 idx 9 idx msg buff dat st loc idx x5E Reserved for other requirements pkg_crc16 crci16 update SMTLINK CRC16 KEY msg buff pkg len 2 msg buff pkg len 2 pkg_crc16 amp 0Ox00FF J LSB Firstly
20. NK P2P DAT START LOC SMTLINK BUS DAT START LOC pkg len smt ver SMTLINK P2P VER 12 1 7 1 SMTLINK PackMsgHead smt ver SMTLINK PKG TP RESP SMTLINK PKG NO ACK SMTLINK CMD TX FW DAT sdr id rcv id msg buff pkg len d msg buff dat st loc 09 00 pkg_crc16 crci16 update SMTLINK CRC16 KEY msg buff pkg len 2 uint16 t amp msg buff pkg len 2 pkg crc16 return inline bool SMTLINK UnPackMsg uints t rcv dat uints8 t msg buff uinti16 t buff_ptr SMTLINK_MsgInfo_TypeDef msg_info static uint16_t pkg_len static SMT_Ver_TypeDef pkg ver Static FW PkgCheck TypeDef pkg chk stage FW UPD CHECK STX bool check reslt false uint16 t pkg verlen uint16 t pkg crci6 switch pkg chk stage case FW UPD CHECK STX if rcv dat SMTLINK STX pkg chk stage FW UPD CHECK HDR CRC else buff ptr 0 case FW UPD CHECK HDR CRC if buff ptr 4 if rcv dat crc8 update SMTLINK CRC8 KEY msg buff 3 pkg verlen uinti16 t amp msg buff 1 pkg len SMTLINK GetPkgLen pkg verlen pkg ver SMTLINK GetPkgVer pkg verlen msg info pkg ver pkg ver pkg chk stage FW UPD CHECK PKG CRC else buff ptr 6 pkg chk stage FW UPD CHECK STX i break case FW UPD CHECK PKG CRC if buff ptr pkg len pkg_crc16 crci16 update SMTLINK CRC16 KEY msg buff pkg len 2 if uinti16 t amp msg buff pkg len 2 pkg crci16 c
21. ace DMA Direct Memory Access makes data transmission more efficient not to mention that it also owns hardware encrypt decrypt units which are definitely essential for firmware release See Figure 2 1 for more information Note that Ethernet is not a common firmware upgrade interface furthermore the Ethernet physical chip is large and expensive From the Cost Effective purpose it is excluded from the block diagram but it can be added at any time since STM32F4 itself owns hardware Ethernet even though it needs external PHY TFT LCD STM32F4xx SPIx4 WITT WARTx 7 FAN Firmware Upgrade Interface Figure 2 1 Hardware Block Diagram 2 1 2 Level Conversion Circuit Design Considering that the voltage level of different modules inside the complex system may differ from each other normal TTL voltage levels are 5V and 3 3V For instance the firmware upgrader works with 3 3V power supply while the target AVR platform is powered with 5V The rationale of the level conversion circuit 1s pretty simple With discrete bipolar transistor we can easily realize voltage level conversion 10 kOhm 100 kOhm Figure 2 2 Voltage level conversion using an NPN bipolar transistor Figure 2 2 can convert a voltage swing of 0 3V to a voltage swing of 0 5V This method was applied earlier in this project since it is very simple Note that the pull up resistor value will affect the switching speed The defect of this circuit is
22. ard SD card can be directly mounted as a disk This is designed to make user can store the latest firmware to upgrader s on board SD card easily It also provides the possibility to let the upgrader to be able to connected to GIT software management system and retrieve the latest stable firmware automatically Figure 2 10 shows the USB host and device library organization Device HID USB device mass storage Host HID keyboard mouse Device MSC FAT FS file system I USB device library USB host library l I Host MSC CDC virtual COM Dual core MSC HID Stacks and libraries Note that the USB interface speed selected in this project is USB FS Full Speed 12 0 Mbps since for STM32F407 if we want to achieve USB HS High Speed 480Mbps an external ULPI chip such as Microchip USB3300 must be implemented However it is not necessary in this project even though we obviously want to store the firmware from PC to upgrader quickly it is not the bottleneck of upgrade speed 12Mbps is fast enough for normal firmware size less than 12MB 12 Note that the original USB library should be modified to increase USB transmission speed Refer to Section 3 2 for details Furthermore we can turn on DMA DMA2 Stream 6 acceleration for SDIO to dramatically improve the SDIO performance Another important note is actual USB VBUS hardware design STM32 offers the ability to trigger USB initia
23. decryption If the target device has no corresponding hardware units then software solution must be applied thus it will also hurt firmware upgrade efficiency 22 4 Conclusions In this project an efficient firmware upgrader was designed and could perform firmware upgrade to target device based on IAP methodology Multiple interface drivers are designed to verify system efficiency From this project I learned that a good embedded system is not only composed of high quality hardware firmware design is also important Good firmware design sometimes can make up hardware defects while slight hardware modifications can make the software design easier For embedded system design both hardware and software are scalable Even though this system can perform required standard firmware upgrade process it still exists some defects and so much space for further modifications and improvements 4 1 Future Work Currently when multiple device are connected to this system t can only perform firmware upgrade process in order However it is possible to upgrade all connected systems simultaneously using interrupt based data transmission strategy Once the protocol version target device ID and firmware segment size 1s identified firmware data transmission can be automatically triggered by interface transmission interrupt However with this kind of architecture the software design will become much more complicate since there exists multiple interrupt
24. der needs buffer to program internal flash Figure 2 8 shows the compiler output information with ATMEL Studio v6 2 1563 Note that the firmware data buffer size is 512 bytes while package segment buffer size is 256 bytes plus the debug buffer 256 bytes exclude these buffer consumption Smart Link roughly use 435 bytes Note that implementing software encryption decryption functions will make the bootloader size exceed boot region limitation so it is not included Output Show output from Build m Al y Task RunfutputFileVerifyTask Frosram Memory Usage 3674 bytes 3 0 Full Data Memory Usage 1469 bytes 8 9 Full 2 2 2 Master Upgrader Firmware Design The master upgrader firmware is composed of interface driver design USB Virtual Disk with FAT 16 32 driver design and simple GUI design A Interface Driver Design The interface driver should be designed with a good structure To guarantee the firmware transmission efficiency a interrupt based architecture is implemented meanwhile considering that all communication interfaces can be mapped to RX and TX subject interfaces and most MCUs contain separate Transmit and Receive ISRs Interrupt Service Routine including DMA contains TX DMA and RX DMA Based on this point of view the driver architecture 1s shown n Figure 2 9 left block diagram shows abstracted interface for user while the right block diagram provides data source for the abstracted layer
25. ehlis a 24 WA 25 SCHER ie 26 Smart Link Draft Version u a 26 IN Figure 1 1 Traditional Firmware Upgrade Process wwwwnnewmmananawemwawanww l Figure 1 2 Block Diagram of Firmware Upgrader Application System 2 Figure 1 3 Bootloader and JAP Rational na e d ce R 3 Figure 2 1 Hardware Block Dide ann en na EE EEE 5 Figure 2 2 Voltage level conversion using an NPN bipolar transistor 5 Figure 2 3 Bi directional level shifter le 6 Figure 2 4 Protocol Version A BUS rennan E EE 7 Figur 2 5 Protocol Version BA PA araninroin ana aE E ET 7 Figure 2 6 Test Outputs from VC Test Bench ee a 8 Figure 2 7 Smart Link D code State Machine susanne a 9 Figure 2 8 Bootloader based on Smart Link with AVR Studio GCC Compiler 10 Figure 29 Driver MMI AS UIUC Ce AA a a S 10 Figure 2 10 USB host and device library organization sss 12 Figure 2 11 Ditferent speed class Of SD 6atd nu 13 Figure 2 12 Fat Fs Module Implementaton nennen 14 Fi6ure 2 15 SDIO Read Write Speed Test ae ae aa 15 Figure 2 14 ATmegal284p Flash Region Assignment nnnsssssssssssssssesserrereessee 16 Figure 2 15 Bootloader size configuration getest na a 16 Figure 2 16 AVR Studio GNU Linker Confoeuraton 17 Figure 2 17 Simple GUI Design for Firmware Upgerader 18 Fome 2 18 PSMC Bank Address Map a inte to ae 19 Figure 2 19 R
26. ered Files 8 Files M 512KB BIME E2 ME SAM Note that the STM32 USB library is modified to achieve this performance original library can only achieve 33KB s EP OUT Master to Slave performance By modifying the maximum transfer size from 64 to 65536 Increase internal data buffer size and use PING PONG buffer strategy to implement BULK transmission the USB transmission speed can be increased up to 1215 KB s 21 3 1 Interface Speed Test This test aims to verify the firmware upgrading efficiency in this test USART USART with DMA and CAN interface are tested with different firmware size Shows the testing results Interface Speed Test 3000 _ 2500 amp 2000 O 1500 O E 1000 oF 5 p 8 E Im E 11 dm 24 Ae mUART 600 5 1265 74 2450 82 m UART DMA 272 37 593 42 1234 28 2395 82 CAN 30 62 79 612 131 675 275 392 BUART MUART DMA ECAN From the result above we can see that DMA can indeed save time If the receiver AVR Board also support DMA then the performance would definitely be better Note that STM32 USART can achieve 10 5Mbps transmission speed while the maximum BAUD configuration for ATmegal284p is only 115200bps From This point of view the firmware transmission speed s actually limited by target device This limitation can also be observed from the comparison of USART and CAN 10Mbps Note that there also exists a factor that may affect transmission speed CRC8 CRC16 package verification and
27. gee SSeS eee Se See eee Ban Sa Se aS eee SSeS SSS a eS SSeS RSS a a lll BRS SSSR EE a H Drv Init Driver Layer Board Layer Bsp Init Drv_Special Bsp Control Drv TX cbISR Drv RX cbISRO Bsp TX ISRO Ben RX ISRO Clear IF Communication Protocol Layer Drv TX cbISR Drv RX cbISR 10 As shown n Figure 2 9 the driver layer and BSP Board Support Package layer are clearly separated All user functions are named as Drv xx cbISR which means it is a call back function from low layer ISR Except for considerations above there still exists many notes for different interfaces gt SPI and USART are the most common communication interface And the DMA function is pretty easy to be implemented with buffer pointer and user specified data length For implementation purpose all the hardware addresses are defined in macro which can be easily ported to any platform gt 2C isa well known illness for STMicroelectronics and this illness started from CM3 famous STM32F103 Even though CM4 platform fixed this problem official I2C library CPAL 1s not so efficient for firmware upgrading In this project DC and DMA interrupt are combined together to achieve high performance gt CAN is largely used in industrial embedded applications plus it supports Multi Host thus it is a very important firmware upgrade interface In this project cooperated with PC Client Software use
28. he SD card chosen in this project is manufactured by Kingston UHS I SD card SDHC Class 4 speed gt 4MB s Please note that the clock speed doesn t stands for actual data transmission speed we can quickly forward the data stream via SDIO but SD card still need time to program the data stream into internal storage After the SDIO configuration the next step is to implement low level SDIO control with Fat Fs hardware layer The FatFs version used in this project is RO 10b It is fairly easy to transplant the Fat Fs module the only thing needs to do is change the low layer file aiskio n specifically re map the SD disk initialize disk initialize disk read and disk write functions to corresponding STM32F4 SDIO functions The mapping table is shown in Figure 2 12 disksd if initializeQ j SD Init 0 disk_initialize c SD disk initialize disk read e SD ReadBlock SD ReadMultiBlocks SE disk_write mam SD WriteBlock SD WriteMultiBlocks FatFs Low Layer diskio c As soon as the Fat Fs is implemented and SD card can be successfully initialized a speed test function is designed to explicitly validate the performance of SDIO 4 bit mode when the upgrader is connected to PC Figure 2 13 shows the SD card Read Write Speed Test results 14 System Initialized Please input command Display root directory in SD card Create a new text file CornellMEng txt Read the file content
29. heck reslt true if pkg ver SMTLINK P2P VER msg info sender msg buff SMTLINK SNDR LOC msg info cmd id SMT CmdID TypeDef msg buff SMTLINK P2P CMD ID LOC else msg info cmd id SMT CmdID TypeDef msg buff SMTLINK BUS CMD ID LOC buff ptr 0 pkg len 60 pkg chk stage FW UPD CHECK STX break default break return check_reslt ifdef __cplusplus endif endif
30. lization process via enabling the hardware VBUS sensing function But it is an ignorable function even though it can avoid un necessary USB connection polling process the reason 1s that the SDIO interface is only enabled when the upgrader is connected to PC it is definitely fine to check PC connection via polling method since it is the only running task Now that we have USB hardware support the next important step 1s to implement the Fat Fs open source file system using SDIO 4 bit interface Compared to normal SPI interface SDIO is much faster and 1t consumes more CPU resource Compared to SPI operation mode the biggest advantage to use SDIO 1s that it separates command line and data lines With SDIO interface commands can be sent concurrently with data it is definitely much faster than SPI The speed class of SD is as important as interface speed Shows different speed class of different SD cards Bus Spec Normal SD SDHC and eed C 12 5MB s SD SDHC and enc 25MB s M 50MB s SDR50 SDHC and es mg DDR SDXC 104MB s SDR104 SDHC and I Sm em 156MBis SDXC fan xcu 312MB s From this table there actually exists a difference between the maximum SDIO interface speed and actual SD card speed In other words the actual data transmission 13 speed s limited by SDIO interface S nce the SDIO clock frequency of STM32F407 s fixed at 45MHZ this means that SD card must support SDIO high speed SOMHz T
31. method With this system engineers are able to upgrade the whole complex system by simply pressing a button instead of using different kinds of programmers It can be further connected to GIT software version management system so that the latest stable firmware can be upgrade anytime In this way engineers can avoid unnecessary time lost on finding correct firmware during the R amp D process A Cortex M4 based MCU 1s selected to perform the firmware upgrade operation It is equipped with abundant hardware communication interface and hardware DMA resources meanwhile it also contains hardware encryption decryption and CRC modules which can secure and validate the firmware data stream very efficiently Also it owns USB OTG and SDIO interface which provides a convenient way to fetch firmware from PC via mounting a USB Virtual Disk using with FAT16 32 Appropriate hardware platform is clearly not enough to realize stable firmware upgrading A lightweight communication protocol must also be designed which should be able to realize handshake normal request and response functionalities for both master and slave Considering that it 15 impossible to connect all internal modules to a single lumped upgrade interface since they may be installed in different locations due to structural design considerations In other words internal modules may be connected to the upgrade interface either directly or indirectly This means that the protocol should sup
32. n etc The IAP rationale is be shown in Figure 1 3 Normally MCUs execute the program n application region when it receives an upgrade request message from HOST upgrader it will clean internal registers and jump to bootloader region then execute the bootloader program Ifthe HOST receives the response message sending from bootloader it will begin to transmit RAW firmware data continuously After the bootloader receives a complete firmware package it then programs itself Specifically it begins to program the raw firmware data into application region After the whole firmware is completely programmed into the application region bootloader either performs a software reset or directly modify the program counter to run program in application region EEE EEE b i l Firmware Upgrader HOST e J Image Stream Upgrade Request from UPGRADER o a from UPGRADER Pl a A ace P c Bootloader Application Region A Program Application Flash Region Target Device SLAVE m rem m umm en e pe zen zen e en zen RS zem en en pe ren Seen pen pe zent re HE en pe au rem en Ln BEE zm ze ze au en ren TE en ren zent nmi en rem mum meni em en 377 NEE EE ee pen an an em em an em emm am m m m em emm G Figure 1 3 Bootloader and IAP Rationale 2 Design and Implementation The system design involves in hardware design hardware platform selection hardware interface level conversion and software design including communication
33. nts t msg buff uint8 t idx uint16 t pkg crci6 uint16 t pkg len uint8 t dat st loc dat st loc smt ver SMTLINK P2P VER SMTLINK P2P DAT START LOC SMTLINK BUS DAT START LOC pkg len smt ver SMTLINK P2P VER SMTLINK P2P FWRCVREQMSG LEN SMTLINK BUS FWRCVREQMSG LEN SMTLINK PackMsgHead smt ver SMTLINK PKG TP REQ SMTLINK PKG NEED ACK SMTLINK CMD REQ FW DAT sdr id rcv id msg buff pkg len msg buff dat st loc 09 00 DAT is reserved for encryption type TI uint32 t amp msg buff dat st loc 1 fw size DAT 1 DAT 4 is firmware size Si for idx 0 idx lt 8 idx DAT 5 DAT 12 reserved a msg buff dat st loc 5 idx 0x00 Handshake validation for further extension pkg crci6 crci16 update SMTLINK CRC16 KEY msg buff pkg len 2 uint16 t amp msg buff pkg len 2 pkg crc16 return SMTLINK Firmware Data Receive Response Message SOF VERLEN HDRCRC8 SND RCV SEQ CMDTP CMDID DAT PKGCRC16 Request Message Length Byte 12 3 S inline void SMTLINK PackFWDataRcvRespMsg SMT Ver TypeDef smt ver uints t sdr id uints t PEN id uinti16 t fw seg size uints8 t msg buff uint16_t pkg crci6 uint16 t pkg len uint8 t dat st loc dat st loc smt ver SMTLINK P2P VER SMTLINK P2P DAT START LOC SMTLINK BUS DAT START LOC pkg len smt ver SMTLINK P2P VER SMTLINK P2P
34. port indirect firmware upgrade via other modules To expand a simple user interface 1s presented by TFT LCD with touch panel to allow users to observe firmware upgrade status including all connected modules status online offline upgradable etc In order verify the system functionality USART and CAN bootloaders for AVR and STM32 platform are created The final results show that the system can successfully upgrade both AVR and STM32 platform 111 Table of Contents ABSTRACT euer i EXECUTIVESUMNELIA R Y E iii Table Ol E E EE iv he Introduchon uses u OE ENE SSi eaS 1 1 1 Problems and M t Vaton nennen nenne enne nnne nnn nnns nnn nnns l 1 2 IAP Techn0l00y es 2 2 Design and Implementation sssss 4 Zt Hardware Din sans nenne 4 2 1 k Hardware Platon Selecti n nenne speak 4 2 1 2 Level Conversion Circuit Desom 5 EEN 6 2 2 1 Smart Link Protocol Desidia es eet 6 2 2 2 Master Upgrader Firmware Desisn san a EE ees 10 A Interface Driver be EE 10 B USB Virtual Disk with FAT 16 32 Driver Desen 11 2 2 9 Slave Bootloader Desion AV R un ee E Sead tein 15 2 2 4 Simple GUI Design using TFT LCD with Touch Function 17 SEP NI E 20 3 1 Internal SD Card RW TeSt eeneg 20 3 2 Firmware Transmission Speed PC to Upgrader 21 Se tee ee est ae 22 s m TUTE 23 dT DEE 23 S Acknowledsem
35. r can freely assign CAN ID to the upgrader target board components with CAN interface It 1s very flexible and stable due to its robust low layer communication protocol gt USB and FSMC Flexible Static Memory Controller are two famous interfaces in STM32F series and these two interfaces are very important in this project USB is responsible for data transmission between PC client and storage media while FSMC is responsible for fast display TFT USB interface 1s assigned with DMA channels to ensure transmission speed will be further verified FSMC has no DMA support therefore software utilization mainly on memory operation is essential B USB Virtual Disk with FAT 16 32 Driver Design Considering the system integrity and user experience user don t need to pull the SD card out of upgrader in order to store latest firmware instead just connect the upgrader to PC and drag raw firmware file into it Furthermore in the future eMMC 11 can be directly embedded SDIO S bt interface to upgrader Obviously users would not like to spend a lot of time to store firmware to upgrader thus high speed R W performance of USB Virtual Disk implementation s very important STMicroelectronics provide an easy way to implement USB Device or Host functionalities In this project USB 1s implemented as a device Specifically USB Device MSC Mass Storage Class is used in this project Also a FAT 16 32 is implemented so that the on bo
36. roblem since each component may have different hardware programming interface or different IAP protocols What s more we need to take the robot system apart in order to upgrade some internal tiny modules which is definitely suffering for engineers Note that all components are connected with each other via serial ports USART SPI I2C USB etc we can design a cost effective device connected to all modules inside the robotic system which 1s only responsible for firmware upgrading and once the upgrading task finishes it can be removed as if it never exists From Figure 1 2 we can see that the upgrader totally remove human factors from the Firmware Upgrade process In this way a convenient and safe firmware upgrade process can be guaranteed Complex System GIT SW FW Version Control Component D 28504015 Component C R amp D Component B Groups 22nf429 u apv dy parfiuy 32142 apv4sd Component A sy wm wm wm wm wm wm mmm mm mm em mmm es ee pm mm mm Figure 1 2 Block Diagram of Firmware Upgrader Application System 1 2 IAP Technology In Application Programming IAP is widely applied in embedded systems The rationale of IAP is pretty simple However it needs hardware support allow self programming allow users to change the program counter any time Currently most intelligent devices support IAP with extra support such as independent bootloader flash section software reset functio
37. s Production programming solutions for the STM32 STMicroelectronics USB On The Go host and device library User Manual RA8875 Character Graphic TFT LCD Controller Specification SD Group and SD Card Association SD Specifications Part I Physical Layer Specification SD Group and SD Card Association SD Specifications Part El SDIO Specification NXP Semiconductors Level shifting techniques in I2C bus design v 01 Specification Universal Serial Bus Rev 2 0 ARM http www arm com 2000 FatFs Module Specification http elm chan org 10 Specification C A N v2 0 Common Public Radio Interface CPRI 2004 1 75 25 7 Appendix Smart Link Draft Version ifndef _SMARTLINK_H_ define _SMARTLINK_H_ AK OK ok K CK AK OK PE PE K CK CE CE OK OK OK OK OK CE CE OK OK OK OK CE CE K CE K OK CE CE OK K K K OK CE FF K K K K K K K K K K K K OK K K K K K K K K K K CE K K K K K CE K K K K K K xK EE m 2K 2K K 2K OK OK CE CE K OK CK CE K OK CE CE K CK CK CE K OK CK CE CE K OK CE CE K K CE K K K OK CE CE K OK CE CE K K CK CE CE K CK CK CE K OK OK CE CE CE OK CE CE K CE CE CE CE K OK CE CE K OK CE CE KKK xx file smartlink h author Wancheng Zhou version beta date 88 November 2014 brief This file provides firmware functions to manage the following T functionalities of Firmware Upgrader Package Request Message from Master Package Response Message
38. s Furthermore this protocol can be used for Sub Module Firmware Upgrade For instance if a module module X is impossible to be connected to the external interface but it communicates with one of the modules module Y that connects to the upgrader In this way upgrader can send X firmware to Y and Y upgrades X indirectly Both Protocol A and Protocol B are implemented with CRC 8 16 checksum filed to enhance the communication safety What s more it is also designed for software convenience if the Header CRC8 1s wrong the whole package can be ignored After the package format and functionalities are defined It must be verified to make sure that all request response message can be correctly generated To achieve this a software Test Bench based on Visual Studio VC is created to explicitly verify Smart Link CRCS Value of test data is Hx23 CRC1i6 Value of test data is Hx4f47 crcl6 ESCH P2P FW Update Request Message package length 21 55 15 H4 AE ES 55 HR BH 28 BB 5E 5E SE SE SE SE SE SE SE CH EB P2P FW Update Response Message 55 HD H4 51 55 ES HH HH 8H HH BA 36 BA P2P FW Data Receive Request Message 55 19 H4 52 E5 55 HH BA 26 HI BA AA 55 AA 55 HB BA Hp BA Hp BA BA BA DD 5C P2P FW Data Receive Response Message 55 HF H4 7B 55 ES BA HB 8H HI BH BA HI P2P FW Data Transmit Request Message 55 1B H4 78 ES 55 HH HH ZA H2 HH 34 12 BA BA H8 BA 1E 2E 3E 4E 5E 6E VE BE 39 13 P2P FW Data Transmit Response
39. smt ver SMTLINK P2P VER SMTLINK P2P FWTXREQMSG LEN fw seg size SMTLINK BUS FWTXREQMSG LEN fw seg size SMTLINK PackMsgHead smt ver SMTLINK PKG TP REQ SMTLINK PKG NEED ACK SMTLINK CMD TX FW DAT sdr id rcv id msg buff pkg len msg buff dat st loc 09 00 uint32 t amp msg buff dat st loc 1 fw seq num uinti16 t amp msg buff dat st loc 5 fw seg size pkg_crc16 crci16 update SMTLINK CRC16 KEY msg buff pkg len 2 uinti6 t amp msg buff pkg len 2 pkg crc16 return _ inline void SMTLINK PackFWData StuffBuff SMT Ver TypeDef smt ver uint8 t msg buff uints t data pool uinti16 t fw seg size uinti6 t idx uint8 t fw dat st loc fw dat st loc smt ver SMTLINK P2P VER SMTLINK P2P DAT START LOC 7 SMTLINK BUS DAT START LOC 7 for idx 0 idx fw seg size idx msg buff fw dat st loc idx data pool idx return rt SMTLINK Firmware Data Transmit Response Message SOF VERLEN HDRCRC8 SND RCV SEQ CMDTP CMDID DAT PKGCRC16 E Request Message Length Byte 12 1 NOTE Prepare firmware data before calling this function and make sure the buffer size is sufficient inline void SMTLINK_PackFWDataTXRespMsg SMT_Ver_TypeDef smt_ver uints t sdr id uint8_t rcv_id uint8_t msg buff uint16 t pkg crci6 uint16 t pkg len uint8 t dat st loc dat st loc smt ver SMTLINK P2P VER SMTLI
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