Example User Manual
Contents
1. lt Counter Reg 1 473 else 474 Counter Reg lt Counter Reg 475 end if 476 end if 477 and process Acromag Inc Tel 248 295 0310 10 www acromag com Getting Started with the XMC SLX Engineering Design Kit 14 Add the following lines of red 579 PEAP_DATA O lt 5 536 Counter Reg O and Counter Ade or code to the READ_DATA 537 IO DIFF O and DiffReg31to0 Adr or MUX This will allow the read 536 IO DIGITAL O and Digkegisctoe0 Ade or 539 Diffbie RegiO and DiffbirReg Ade or and write commands to 540 DigDir Reg O and DigDirReg Adr or access the counter address at 5 1 S42 IntEnA Reg O and Int Enable Ade of 8020H 543 IntTypA_Reg 0 and Int Type Ader or s44 IntPolA Feg O and nt Polarity Ader 545 S46 Bits 3 0 will hold the four bits of 547 READ _DATA 1 lt 48 Counter Reg l and Counter Ade of the counter bit 4 will hold the 549 IO DIFF i and DiffReg itoO_Adr or increment line and bit 5 will hold sso IO DIGITAL 1 and DigRegiStoO_Adr or S51 Dittbic Regii and DittDirReg Adr or the enable 552 Dig ir_Reg 1 and DigbirReg_Adr Or 553 554 IntEn A Regil and Int Enable Adre or 555 IntTypA Reg 1 and Int Type Adr or 556 IntPolA Reg 1 and Int Polarity Adr 559 READ DATA 2 lt 50 Counter Reg 2 and Counter Adr or S61 Io DIFF 2 and DiffReg3ito0 Adr or 562 IO DIGITAL 2 and DigRegiStoO Adr or S63 DiffDir Reg 2 and Diffbirkeg Adr or S64 DigDir Reg 2 and Digbir2. 0j lt ooooo000 elsif CLE event and CLE 1 then if DPiffPirReg SthO 1 then DiffDir Reg downto O lt LD Y downto 0j If there is a Counter sth pre config the direction CO Channel 4 as an input and channels 3 0 as outputs elsif Counter Sth 1 then DiffDir_ Reg downto O lt 00001111 else DiffLir_ Reg downto j lt D iffb ir Reg downto 0j end if end if end processa 435 Counter EN Register Oxs02 0 bit 5 436 Turns on the functionality of the Counter aly process CLE RESET 4355 begin 439 if RESET 1 then 440 Counter EN lt O 41 elsif CLE event and CLE 1 then 442 if Counter sth 1 then 443 Counter EN lt LD 5 444 else 445 Counter EN lt Counter EWN 46 end if 447 end if 446 end process 450 Counter Inc determine when to load the counter 451 Register Ox6020 bit 4 452 process CLE RESET 453 begin 454 if RESET 1 then 455 Counter Ine lt O 456 elsif CLE event and CLE 1 then 457 if Counter EN 1 then 458 Counter Inc lt IG DIGITAL 4 459 else 7 7 460 Counter Inc lt Counter Inc 461 end if 7 462 end if 463 end process 465 Counter Reg determine when to increment the counter 466 process CLE RESET 467 begin 4g if RESET 1 then 469 Counter Reg lt 0000 elsif CLE event and CLE 1 then 471 if Counter EN 1 and Counter Ine 1 then 472 Counter Reg
3. or use the address of the SRAM must have two extra bits The majority of these registers are defined via a constant declaration on line 93 of DP_SRAM vhd The declaration is constant addr_max integer 19 or 17 for the base model The registers affected are listed below Counter with the current address of the SRAM Can be set and read via SRAM ADD C t A oun 0x8038 amp 0x803C ADD RESET VALUE Counter that contains a reset value for the SRAM which could from either of the RESET registers above In addition there are some minor changes to the read logic All differences are shown on the following page Please note that there are no differences in the top level x6s x150 vhd file DMA1_RESET Register corresponding to 0x8054 Acromag Inc Tel 248 295 0310 16 www acromag com Getting Started with the XMC SLX Engineering Design Kit DP_SRAM vhd for XMC SLX150 DP_SRAM vhd for XMC SLX150 1M C Design Spartan6 EDK MC SLX1 50 X65L 1 50 DP_SRAM vhd C Design Spartan6 E DK XMC SLX150 1M X6SL 1 50 DP_SRAM vhd constant addr max integer ihe Es ADD _RESET_VALUE 18 lt SRA IntAdr_StbAll and EDITS or DMAOQ_EVENT and SRAM _ Reset0O_EN and DMAO RESET 18 or DMA1_ EVENT and SRAM Reset1 _EN and pae _RESET 18 ADD _RESET_VALUE 19 lt SRAM IntAdr_ StbAll and dL aiso DMAOQ_EVENT and SRAM _ Reset0_EN and DHAO CRESETC19 oF DMAl EVENT and SRAM Reset1 EN and DMA1 RESET 19 constant addr max integer ZES ADD RE
4. project by selecting File gt New Project Acromag Inc Tel 248 295 0310 3 www acromag com Getting Started with the XMC SLX Engineering Design Kit 5 In the Project Name field type SLX150 In the E New Project Wizard Create New Project Location field type the path Specify project location and type name where to find the XC6SLX150 folder Make Enter a name locations and comment For the project See Te Type field IS HDL and click Location Cr Design Spartan EDK XxMIC SL 15018605L 150151150 Lizz Next Working Directory CiDesign Spartan EDK S MC 5L4 1 S0 46SL4150 5L4150 Description sME 5L4150 Example Design Firmware Revision 4 Select the type of top level source For the project Top level source tpe HOL 6 Enter the following information if using the l l n Project Settings SLX150 Then click Next and Specify device and project properties then Finish E New Project Wizard Select the device and design Flow for the project Property Mame Family Spartan6 iit SESS sce Family Spartan Device XC6SLX150 Device XC6SLX150 Package Package FGG676 Speed AF a oi cm T lt lt lt lt lt CTETETETES at Speed 3 Top Level Source Type DL Synthesis Tool M57 VHDL verilog Simulator TSim VHDL verilog Preferred Language Property Specification in Project File Store all values Manual Compile Order VHDL Source Analysis Standard OW j O 2 8 lt 4 444 Enable Messag
5. the VHDL file associated with the rear I O for editing Acromag Inc Tel 248 295 0310 www acromag com Getting Started with the XMC SLX Engineering Design Kit Example Change 1 Open XC6SLX150 vhd and scroll down to around line 205 Add the line of code and accompanying comments as indicated by the box to the right This creates a new address strobe for our counter It will be located in register Ox8020 2 Around line 388 insert these two lines of code to the declaration of the AXM_D component We will soon be changing the AXM_D vhd file to match this declaration 3 Add the following around line 725 our mapping of the Counter_Adr strobe to the AXM_D instantiation Now the AXM_D component will receive all the information it needs for the design 4 We will now replace a previously unused memory address Uncomment line 887 and 888 and replace the NU with Counter_Adr This will be the location in memory to access the counter Acromag Inc Tel 248 295 0310 Below is a simple example of some VHDL that could be used to control five of the SLX150 s Front I O differential channels via the AXM DO2 or AXM D04 It is included to show how the code supplied with the Engineering Design Kit can be modified for personal use 200 Signal Int Polarity idr ATD LOGIC Oxaeoic Here we add the decode signal for the new counter address that we are going to send to the AFM Signal Counter Adr HTD LOGI
6. your carrier Insert the carrier into an empty slot in your computer When restarting your computer you will be prompted to insert a CD with the drivers on it At this point insert the PCISW API WIN CD software product sold separately from this EDK into your CD ROM drive When the plug and play installation has completed follow the steps to install the additional PCISW API WIN software on your computer When finished insert the CD titled XMC SLX Engineering Design Kit and copy the SLX150 folder to your computer Before you start familiarize yourself with the XMC SLX User s Manual included on the EDK CD and the PCleSLX Driver Function Reference included on the PCI Win32 Driver Software CD The user s manual gives the memory addresses of all the registers and their purposes The function reference gives information on how to use the DLL file in C C Visual Basic and LabView we will be focusing only on using the C C demo program The Configuration Xilinx steps 1 13 following are also given in the Readme SLX150 txt file included on the EDK CD This file also contains detailed information on the contents of the CD including a description of the contents of the VHDL files Read this file prior to reading this manual This manual assumes that Xilinx ISE Version 12 3 in used Note that earlier versions are not supported and later versions may have alternate procedures Also note that VHDL line numbers in this manual may not match the li
7. Acromag d THE LEADER IN INDUSTRIAL 1 O Series XMC SLX150 Spartan 6 Based FPGA XMC Module Getting Started with the XMC SLX Engineering Design Kit ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 2011 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 894 A11B000 Getting Started with the XMC SLX Engineering Design Kit Table of Contents TING oo FAB D aaa AEA EAEE ENEE 2 Installing the Board and Device Drivers cscscsscscscsccccccscsccccccscsccccccscsceccecscnceccccecsceceecess 2 Starting a New Xilinx Project sesessesessssessssesescecesoesescecessecessecesosoesescecesoecssoesesoecsesseceseeceeee 3 Modifying the Provided VHDL Code sesessesessesessecessecoessscecsscesesoecescesescecesoscesoscesseoesesoesssoeoe 7 DS E I EE A A EEA E A E A E E E 8 Generating a Programming MCS File sessesessssesessesescecescecessecesoscessecoessececsscecessesesoeseeses 12 Differences in VHDL between the XMC SLX150 and the XMC SLX150 1M scsscsscsseees 16 Xilinx ISE 12 3 Compiler Warnings sessesessssessssecescesesoecessecesoscesescoecssoecssoesesoecsessecesseseseeceeee 17 All trademarks are the property of their respective owners You must consider the possible negative effects of power wiring component sensor or software failure in the design of
8. C Ox8020 z207 Rear J4 Connector Address Decode Signals 356 Int StatClear Sthb in STD LOGIC Interrupt Status Clear Reg Write 366 OllrL address strobe for the counter 369 Counter Adr in TD LOGIC g 391 IQ DIGITAL inout STD LOGIC VECTOR 15 downto 0j Front Digital I Gas Int Polarity Adr gt Int Polarity Adr a4 Our address strobe Counter Adr gt Counter dr 726 Eite SLobes 886 LA 3 and LA 2 and Base Address 0x801C 887 NU lt not LA 8 and not LA 7 and not LA 6 and LA 5 and not LA 4 and 888 not LA 3 and not LA 2 and Base Address 0x8020 889 NU lt not LA 8 and not LA 7 and not LA 6 and LA S and not LA 4 and 890 not LA 3 and LA 2 and Base_Address Oxs024 666 LA 3 and LA 2 and Base Address 0x801C 887 Counter Adr lt not LA 8 and not LA and not LA 6 and LA S and not LA 4 and 0x8020 LA 5 and not LA 4 and 558 not LA 3 and not LA 2 and Base Address 889 NU lt not LA 8 and not LA and not LA 6 and WWW acromag comMm Getting Started with the XMC SLX Engineering Design Kit 950 5 To line 952 add the code in 951 AXM Strobe lt DiffReg31to0 Adr or DigRegiStoO Adr or DiffDirReg Adr or DigDirReg Adr or 952 Int Enable Adr or Int_Type_Adr or Int Polarity dr the red box This is added to 953 strobe the AXM where the rest of the counter code will be located when the Counter_Adr has received a read or write
9. Reg Adr or S65 S66 IntEnA Reg z and Int Enable Adr or S67 IntTypA Reg 2 and Int Type Adr or 568 IntPolsA Reg 2 and Int Polarity Adr 262 570 ofl READ DATA 3 lt 572 Counter Reg 3 and Counter Adr or Siz IO DIFF 3 and DittRegsitod Ader or 574 10 DIGITAL 3 and DigRegl5to0_Adr or 575 DiftPir Reg 3 and DiffDirReg Adr or 576 DigDir Reg 3 and DigbicReg Adr or si 570 IntEni Reg 3 and Int Enable Adr or 5793 IntTypA Reg 3 and Int Type Adr or 380 IntPolsA Reg 3 and Int Polarity Adr S63 READ DATA 4 lt 564 Counter Inc and Counter Adr or S85 IO_DIFF 4 and DiffRegsitoO_Adr or S86 IO DIGITAL 4 and DigRegilstoO Adr or 587 Diftfbic Reg 4 and DiffbicReg_Adr or S86 Digbir Reg 4 and DigbirReg Adr or 569 590 IntEnA Reg 4 and Int Enable Ader or S91 IntTypaA_Reg 4 and Int_Type_Adr or 592 IntPolA Reg 4 and Int Polarity Adr 593 594 READ DATA S lt 595 Counter EN and Counter Adc or 596 IO DIFF 5 and DiffReg3ito0_Adr or 597 IO_DIGITAL 5 and DigRegistoO0_Adr or 598 DiffDir_Reg 5 and DiffDirReg Adr or 599 DigDir Reg 5 and DigbirReg_Adr or 600 601 IntEndA Reg 5 and Int Enable Adr or 602 Int TypaA Reg 5 and Int Type Adc or 603 IntPolA Reg 5 and Int Polarity _Adr Acromag Inc Tel 248 295 0310 11 www acromag com Getting Started with the XMC SLX Engineering Design Kit Generating a Programming MCS File The Xilinx MCS contains the information to prog
10. SET_VALUE 18 lt SRA IntAdr StbAll and LD 18 or required for 1M model DMAO_EVENT and SRAM ResetO_EN and DMAO RESET 18 or DMA1_ EVENT and SRAM Reset1_EN and DMA1_RESET 18 Sanne RESET_VALUE 19 lt SRAM IntAdr_ StbAll and LD 19 or required for 1M mdoel DHAO_EVENT and SRAM ResetO_EN and DMAO_RESET 19 or DMAl EVENT and SRAM Reset1 EN and DMAl RESET 19 SRR_A 18 lt O remove for 1M model SRR_A 19 lt O remove for 1M model SRAM Read_Adr2 and SRR_IO_RD 50 or SRAM IntAdr and SRAM _ADD Count 18 or Required for 1M model SRAM DMAQThr_Adr and DMAO_THRESHOLD 18 or ee SRAM DMA1Thr_Adr and DMAl_THRESHOLD 18 or SRAM ResetO_Adr and DMAOQ_RESET 18 or SRAM Resetl Adr and DMAl RESET 183 SRAM Read_Adr2 and SRR_IO_RD 51 or SRAM IntAdr and SRAM _ ADD Count 19 or required for 1M model SRAM DMAQThr_Adr and DMAO_THRESHOLD 19 or SRAM DMA1Thr_Adr and DMAl_THRESHOLD 19 or SRAM ResetO_Adr and DMAQ_RESET 19 or SRAM Reseti_ dr and DMA1_RESET 19 SRAM Read_Adr2 and SRR_IO_RD 50 jor SRAM IntAdr and SRAM ADD Count 18 or SRAM DMAQThr_Adr and DMAO_THRESHOLD 18 or SRAM DMA1Thr_Adr and DMAl_THRESHOLD 18 or SRAM Reset0_Adr and DMAOQ RESET 18 or SRAM Reseti Adr and DMAl RESET 183 3 SRAM Read_Adr2 and SRR_IO_RD 51 or SRAM IntAdr and SRAM ADD Count 19 or SRAM DMAOThr_Adr and DMAO_THRESHOLD 19
11. any type of control or monitoring system This is very important where property loss or human life is involved It is important that you perform satisfactory overall system design and it is agreed between you and Acromag that this is your responsibility Acromag Inc Tel 248 295 0310 1 www acromag com Getting Started with the XMC SLX Engineering Design Kit Getting Started Installing the Board and Device Drivers The purpose of this document is to provide basic instructions on using the XMIC SLX Engineering Design Kit with the XMC SLX Boards It will focus on programming the FPGA of the XMC SLX150 using VHDL but can be easily modified to use with any model of the SLX line This document also shows how to use the supplied dll files with a MFC application It is assumed that the user has a working knowledge of Xilinx VHDL and Visual C Note that this document assumes Windows is used as the operating systems Linux users can follow the same general procedure but be aware that differences exist that are not noted in this document There are small differences in the VHDL between the XMC SLX150 E and the XMC SLX150 E 1M models due to differences in the SRAM size Refer to the appendix at the end of this manual for further information on the VHDL differences For first time users turn off your computer and unplug the power cord Before touching either board make sure to discharge all static electricity Then attach the SLX150 to
12. command We are finished editing the XC5VLX110T vhd file and will now be editing the AXM_D vhd file 6 After opening AXM D vhd 29 Int Polarity dr in STDP LOGIC Interr _v j Z 30 scroll down to line 31 and add S il The Counter Register s Address Strobe the Counter_Adr port This is 32 Counter Adr in STD LOGIC how the counter will be ae 34 Int StatClear sthO in STD_LOGIC Interr receiving the address strobe from the main vhdl code 7 To line 64 add the write strobe Da Signal Int Polarity sthO STD _ LOGIC 63 for the counter This will pulse 64 The Write Strobe signal for the Counter when a write command is 65 Signal Counter sth ATD LOGIC 66 issued the counter address a a a a ar 8 At line 78 add the signals 76 Signal IOA STD LOGIC VECTOR 7 downto Oj Te registers that the counter will 48 The counter s Signals be using Counter_EN will E Enable the counter for use bl th t o0 Signal Counter EN STD LOGIC enable e counter ol Increment the counter by one Counter_Inc will determine if 52 signal Counter Ince STD LOGIC the counter is incrementing or The Sounter s Register o4 signal Counter Reg STD LOGIC Vector 3 downto Oj not and Counter_Reg is the binary counter o6 T O component for detection of Change of State Ir 9 At around line 231 we will The Counter Register s Write strobes B process CLE insert the counter s write begin strobe T
13. cromag Inc Tel 248 295 0310 17 www acromag com
14. e Filtering Acromag Inc Tel 248 295 0310 4 www acromag com Getting Started with the XMC SLX Engineering Design Kit The Following allows you bo see the status of the source files being added to the project Ik sources Which are successfully added to the project Association Library k 4 ki k 7 We will next add the files we ES Adding Source Files copied from the CD Follow these ste ps also allows you to specify the Design View association and For HDL sources the library For a Select Project gt Add File Mame Source b Select the ucf and all the 2 axm_p vhd vhd files 3 dIG_Io_s vhd 4 DP_sRaM vhd c Click the Open button EO renos d The association for all 6 51x150 ucF files should be All for the 7 5P1_Temp_Sensor vhd vhd files and Implement for the ucf files There are a total of 6 vhd files and one ucf file e Click the OK button Adding Files to project k G ga xc sl150 3fgg676 8 In the Heirarchy Window Design 0 8X click on XC6SLX150_arch pj view f Implementation C Simulation XC6SLX150 vhd to fe Hierarchy highlight it ra SLx150 tha oit Tri Tri Hal DPSRAM DP_SRAM DP_SRAM_ARCH DP_SR 9 In the Processes Window click on Generate Programming File so it is also highlighted Generate E ee 10 Click on Process from the menu bar and click on Properties Acromag Inc Tel 248 295 0310 5 t Implement Desi
15. gn A Programming File Configure Target Device Analyze Design Using ChipScope eM Module AsM_D AxM_D_arch XM D vhd Rear TO RearWDS Rearlv0S arch RearlyvDs Temp sensor SPI Temp Sensor SPI Temp Se SL 150 uck No Processes Running a at Processes SC6SL 150 C65L4150_arch E Design Summary Reports Design Utilities User Constraints Synthesize OT WWW acromag comMm Getting Started with the XMC SLX Engineering Design Kit 11 Click on the Startup FPGA Start up Clock CCLK Options tab and verify the Enable Internal Done Pipe Not Checked following options are Done 6 selected Enable Outputs 5 Release Write Enable 5 Wait for DCM and PLL Lock NoWait Drive Done Pin High Checked Note that if not all properties are shown change the Property gt Process Properties Startup Options display level from Standard to Advanced Category Switch Name Property Mame General Options g StartUpClk FPGA Start Up Clock Configuration Options Startup Options Readback Options g DONE cycle Done Output Events Encryption Options Suspend Wake Options g DonePipe Enable Internal Done Pipe g S75 oc cle Enable Outputs Output Events g GWE cycle Release Write Enable Output Events gLCK cycle Wait For DCM and PLL Lock Output Events Default Nowait g DriveDone Drive Done Pin High Property display level Display switch names Default m 12 Click on the Co
16. his will pulse if CLE event and CLE 1 then Counter_Stb when there is a write command to the end if Counter_Adr AnA pEOCESS 241 Interrupt Registers Write Strobes Counter sth lt Counter dr and not ADS on and not LBEO n and LW Ron Acromag Inc Tel 248 295 0310 9 www acromag com Getting Started with the XMC SLX Engineering Design Kit 10 11 12 13 At line 350 there is the process statement to control the Differential Direction Control Register Add the red code to cause channels 0 3 to become outputs when there is a write to the counter address and make sure that channel 4 is an input to handle the increment line Add this process statement at line 434 to handle the enable for the counter Notice that Counter_EN receives its information from the local data bus LD bit 5 Add this process statement at line 449 to handle the external increment line for the counter Notice that the Counter_Inc receives its information from channel 4 The counter is stopped and started using this input line Add this process statement at line 464 to handle the counter When the counter is enabled it will check the Counter_Inc line to see if it has a positive logic equivalence of 1 every positive clock edge If it does then the counter will be incremented Front I O Differential Direction Control Register 0x800 process CLE RESET heqin if RESET 1 ther DifttPir Fegi downto
17. ne numbers of the files provided in the EDK due to revisions Acromag Inc Tel 248 295 0310 2 www acromag com Getting Started with the XMC SLX Engineering Design Kit Starting a New Xilinx Project 1 Make a new directory on your computer and call it XC6SLX150 S X6SLX150 File Edit View Favorites Tools Help ae O Back gt Bi fp Search ear Folders EBk Address C Design Spartan EDK xMC SLXLSOV65L 150 i aa 2 From the XC6SLX150 folder z Folders Mame Size Type Date Modified aes the all the vhdl files in Randel Programming A H AXM_D vhd 22KB VHDL File 12 11 2006 3 22 PM into the new XC6SLX150 E Research Projects o GUDIG_IO_8 vhd 11KB VHDL File 5 14 2006 12 54 PM folder Then from the a Spartan DP_SRAM vhd 36KB VHDL File 11 4 2010 11 32 AM XC6SLX150 folder copy the CS Business Plan wil RearLvDS vhd 10KB VHDL File 11 3 2010 9 20 4M E Datasheets 3 SLY150 uct 26KB UCF File 11 3 2010 3 10 PM XC6SLX150 ucf file to the a eck WISPITemp_Sensorvhd SKE VHDLFile 11 11 2010 10 33 AM XC6SLX150 folder Note S B xMc sLx150 mil NC6SLX150 vhd 57KB VHDL File 11 29 2010 10 25 AM that all of the files are CD X65L 150 shown in the adjacent a XMC SLX1S0 1M O 65L 150 figure E EEPROM IPMI Excel _ Functional Spec 3 Start Xilinx s Project Manual l MyDat Navigator from your start C MyData menu Xilinx ISE Design Suite 12 3 gt ISE Design Tools gt Project Navigator 4 Open a new
18. nfiguration Process Properties Configuration Options Opt ions tab Verify that all ee ee eee O pti ons are set to d efa u It General Options g ConfigRate Configuration Rate Configuration Options ass h own in t h e screens h ot Startup Options g ProgPin Configuration Pin Program Pull Up Readback Options g DonePin Configuration Pin Done Pull Up to the right mean chet ae g TekPin JTAG Pin TCK Pull Up Suspend Wake Options g TdiPin JTAG Pin TDI Pull Up 1 3 CI i c k OK g TdoPin JTAG Pin TDO Pull Up g TmsPin JTAG Pin TMS Pull Up g UnusedPin Unused IOB Pins Pul Down OOOO g UserID UserID Code 8 Digit Hexadecimal OxFFFFFFFF g ExtMasterCclk_en Enable External Master Clock F g ExtMasterCclk_divide Setup External Master Clock Division 1 g SPI_buswidth Set SPI Configuration Bus Width 1 g TIMER_CFG Watchdog Timer Value OXFFFF Place MultiBoot Settings into Bitstream F g next_config_addr MultiBoot Starting Address for Next Configuration AAAI EAA cas g next_config_new_mode MultiBoot Use New Mode For Next Configuration g next_config_boot_mode MultiBoot Next Configuration Mode g golden_config_addr g Failsafe_user Property display level Advanced w Display switch names Default m Acromag Inc Tel 248 295 0310 6 www acromag com Getting Started with the XMC SLX Engineering Design Kit Modifying the Provided VHDL C
19. ode To revise or add to the provided VHDL code begin by double clicking on the XC6SLX150 XC6SLX150 _arch XC6SLX150 vhd file located in the Hierarchy window This will open the VHDL file for editing aoe Tenperature ensor Signals lt lt lt lt lt lt 2596 Signal TEMP Sen Strobe STD LOGIC 267 Signal TEMP DATA STD LOGIC VECTOR 1le downto QO Additional components and signals may be added between the current definitions at line 258 288 289 component DP SRAM 290 291 porti age 293 L LODO SiGe oss SS SSSSSse ss SS SS SSeS SSS Sess 294 CLK in STD LOGIC 295 RESET in STD LOGIC 208 g After the begin keyword line 455 TEMP SDO in STD LOGIC SPI Data Input 456 491 additional instantiations for components may be added e E 4585 end component 469 SSS SSS SS SS Se a SSS SS SS SS SS 491 begin oe tee SRR INTn lt SR_OINTn or Ska INTn oe ARR COLn lt SR COLn or Ska COLn et 496 HRS CEL lt 1 sE JARI CEL lt 1 ads For simplicity we suggest starting by adding to or revising the provided VHDL code that is associated with the front I O To use the front I O begin by double clicking on the AXM_Module AXM_D_arch AXM_D vhd file located in the Hierarchy window This will open the VHDL file for editing To use the rear I O begin by double clicking on the Rear_lO RearLVDS_arch RearLVDS vhd file located in the Hierarchy window This will likewise open
20. or SRAM DMA1Thr_Adr and DMAl_THRESHOLD 19 or SRAM ResetO_Adr and DMAOQ_RESET 19 or SRAM Reset1l_Adr and DMAl RESET 193 Xilinx ISE 12 3 Compiler Warnings Note that ISE 12 3 will generate the following warnings when compiling the example design These warnings can be safety ignored as they reference unused signals e WARNING Xst 647 Input lt LD lt 20 30 gt gt is never used This port will be preserved and left unconnected if it belongs to a top level block or it belongs to a sub block and the hierarchy of this sub block is preserved e WARNING Xst 647 Input lt LD lt 31 30 gt gt is never used This port will be preserved and left unconnected if it belongs to a top level block or it belongs to a sub block and the hierarchy of this sub block is preserved e WARNING Xst 2677 Node lt Latch_data_0 gt of sequential type is unconnected in block lt Temp_sensor gt e WARNING Xst 2677 Node lt Latch_data_1 gt of sequential type is unconnected in block lt Temp_sensor gt e WARNING Xst 2677 Node lt Latch_data_2 gt of sequential type is unconnected in block lt Temp_sensor gt e WARNING Xst 2677 Node lt Latch_data_0O gt of sequential type is unconnected in block lt SPl_Temp_Sensor gt e WARNING Xst 2677 Node lt Latch_data_1 gt of sequential type is unconnected in block lt SPl_Temp_Sensor gt e WARNING Xst 2677 Node lt Latch_data_2 gt of sequential type is unconnected in block lt SPIl_Temp_Sensor gt A
21. ram the X6SLX150 through either FLASH or JTAG These instructions will talk you through the procedure for creating a MCS file 1 Select XCSVLX110T E Design Summary Reports XC5VLX110T_arch Design Utilities XC5VLX110T vhd in the User Constraints Hierarchy Window Synthesize AST Implement Design Generate Programming File Configure Target Device Analyze Design Using Chipscope P E qene E E 2 Select Generate Programming File in the Processes Window Then select Process gt Run Note If there are any errors correct them and repeat steps 1 and 2 There may be a few warnings 3 Right click on Generate B Design Summary Reports Target PROM ACE File and E Design Utilities click on Run E3 rA User Constraints PO 0 Synthesize X5T PO 00 Implement Design f 0 Translate POP Map PO 0 Place amp Route P Generate Programming File er Configure Target Device E Generate Target PROMIACE File gt Manage Configuration Project iMPACT gu Analyze Design Using ChipScope 4 Select OK ES Warning No iMPACT project file exists Click OK to open iMPACT You will then need to add complete programming details to PROM File formatter or SystemAce and then save the IMPACT project file Once this step is completed subsequent runs of the senerate Target PROMACE File process can generate the File without needing to open the iMPACT UI Acromag Inc Tel 248 295 0310 12 www acromag com Getting S
22. tarted with the XMC SLX Engineering Design Kit 5 Double select Create PROM IMPACT Flaws O x File PROM File Formatter j Boundary Scan SystemAce 3 Create PROM File PROM File Formatter E WebTalk Data Double Click to Launch Mode 6 Select Generic Parallel PROM and the select the step f select Storage Target green arrow Storage Device Type siine Flash PROM B Non Volatile FPA Spartan M B SPI Flash Configure Single FPGA Configure MultiBoot FPGA BPI Flash Configure Single FPGA Configure MultiBoot FPGA Configure From Paralleled PROMS Generic Parallel PROM Acromag Inc Tel 248 295 0310 13 www acromag com Getting Started with the XMC SLX Engineering Design Kit 7 Select 8M and then select Add Storage Device Then select the next green arrow Sfap A Add Storage Device s Parallel PROM Bytes Add Storage Device Remove Storage Device location and enter an Output File Name For example SLX150 Leave all Checksum Fill Value other default options and select OK Output File Mame SL 1iS0 Output File Location General File Detail Loading Direction Mumber OF Revisions Revision O Start Address 4dd Non Configuration Data Files 9 Click OK Add Device i Start adding device File to J Revision O Acromag Inc Tel 248 295 0310 14 www acromag com Getting Started with the XMC SLX Engineering Design Kit 10 Select xc6sIx150 bit file and
23. then clickOpen Add Device Look in 4 S150 My Recent Documents ninmi E Desktop Mu Computer My Network Places 11 Click NO Add Device _iseconfig isim O znz auto _0_xdb C xst cisb lt 1 50 bit File name Files of type Revision O 7 OOOO FPGA Bit Files bit d Cancel 3 Would you like to add another device File to i 12 Click OK Add Device Click Ok to continue 13 Click OK again 14 In the left pane iMPACT Process Windows Double click Generate File Acromag Inc Tel 248 295 0310 IMPACT Processes Available Operations are Generate File s15 i You have completed the device File entry O x WWW acromag comMm Getting Started with the XMC SLX Engineering Design Kit Of the process completed with no errors the Generate Generate Succee de d Succeeded message will be displayed The SLX150 mcs file now resides in the targeted directory From here the file can be downloaded to FLASH or directly to the FPGA using Acromag s software demonstration program for Windows or Linux The file can also be downloaded via JTAG via the AXM EDK adapter board when used in conjunction with a compatible Xilinx download cable Differences in VHDL between the XMC SLX150 and the XMC SLX150 1M The Dual Port SRAM on the XMC SLX150 1M is four times the size as on the base model The result is that all registers that manage
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