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C166S V1 SubSystem

1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ALE CSW CSR RDY BSW EW MTT RWD ENO ENO ENO Co ACT CIL ENo BTYP Co Co METE rw rw rw rw wh mwh rw rwh rw rw rw BUSCON1 Bus Control Register 1 SFR FF14y 8A y Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ALE CSW CSR RDY BSW EW MTT RWD EN1 EN1 EN1 C1 AGT CTL En BTYP cy c1 MCTC rw rw rw rw rw rw rw rw rw rw rw BUSCON2 Bus Control Register 2 SFR FF16 8Bj Reset value 0000y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ALE CSW CSR RDY BSW EW MTT RWD EN2 EN2 EN2 C2 AGT CTL En2 BTYP ca c2 MCTC rw rw rw rw rw rw rw rw rw rw rw BUSCON3 Bus Control Register 3 SFR FF18y 8C Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ALE CSW CSR RDY BSW EW MTT RWD EN3 EN3 EN3 C3 ACT CIL eN3 BTYP 3 C3 MCTC rw rw rw rw rw rw rw rw rw rw rw BUSCON4 Bus Control Register 4 SFR FF1Ap 8Dp Reset value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ALE CSW CSR RDY BSW EW MTT RWD EN4 EN4 EN4 C4 ACT CIL EN4 BTYP ca c4 METE rw rw rw rw rw rw rw rw rw rw rw Note BUSCONO is initialized with 00CO0 if conf start external i is high during reset If conf start external i is low during reset bits BUSACTO and ALECTLO are set 1
2. Mnemonic Description Bytes Return Operations RET Return from intra segment subroutine RETS Return from inter segment subroutine RETP reg Return from intra segment subroutine and pop direct word register from system stack RETI Return from interrupt service subroutine 2 System Control SRST Software Reset IDLE Enter Idle Mode PWRDN Enter Power Down Mode supposes NMI pin being low SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End of Initialization on RSTOUT pin 4 ATOMIC irang2 Begin ATOMIC sequence 2 EXTR irang2 Begin EXTended Register sequence de a EXTP Rw irang2 Begin EXTended Page sequence 2 EXTP pag10 irang2 Begin EXTended Page sequence 4 EXTPR Rw irang2 Begin EXTended Page and Register sequence ras EXTPR pag10 irang2 Begin EXTended Page and Register sequence 4 EXTS Rw irang2 Begin EXTended Segment sequence ea EXTS seg8 irang2 Begin EXTended Segment sequence 4 EXTSR Rw irang2 Begin EXTended Segment and Register sequence 2 EXTSR Aseg8 irang2 Begin EXTended Segment and Register sequence 14 Miscellaneous NOP Null operation 2 User s Manual 5 15 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Instruction Set 5 3 Instruction Opcodes The following pages list the instructions of the C166S ordered by their hexadecimal opcodes Thi
3. REG NAME Short Description SFR ESFR A16y A8y Reset value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bitfield bit bit bit 0 0 0 0 0 0 A 0 0 C B A r r r r r r rwh r r rw rw rwh A byte register looks like this REG NAME Short Description SFR ESFR A16y A8H Reset value y 7 6 5 4 3 2 1 0 bitfield bit bit bit a A 9 C B A r rwh r rw rw rwh Field Bits Type Description bitfieldX m n type Description value Function off Default value Enable Function 1 bitX n type Description 0 Function off Default 1 Enable Function Elements REG NAME Name of this register bitX Name of bit bitfieldX Name of bitfield A16 A8 Long 16 bit address Short 8 bit address SFR ESFR Register space SFR or ESFR Register Register contents after reset 0 1 defined value User s Manual 3 3 V 1 6 2001 08 e Infineon technologies n m n type value User s Manual User s Manual C166S V1 SubSystem x ossz 355 c mb Central Processing Unit unchanged undefined X after power up defined by reset configuration bit number of bit bit number of first bit of the bitfield bit number of last bit of the bitfield readable by software writable by software writable by hardware defined value undefined reserved for future purpose read access delivers 0 must not be set to 1 3 4 V 1 6
4. SYSCON System Control Register SFR FF12y 891 Reset value Oxx0y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ROM SGTD ROM ISE S1 IS EN rw rw rw Field Bits Type Description ROMEN 10 rwh Internal ROM ENable Set according to pin EA during reset O Internal local memory disabled Accesses to the Local memory area use the external bus 1 Internal local memory enabled SGTDIS 11 rw SeGmenTation DISable enable control 0 Segmentation enabled CSP is saved restored during interrupt entry exit 1 Segmentation disabled Only IP is saved restored ROMS1 12 rw Internal local memory mapping 0 Internal local memory area mapped to segment 0 00 0000 00 7 FFF 1 Internal Local Memory area mapped to segment 1 01 0000H 01 7FFFH STKSZ 15 13 rw System STacK SiZe Selects the size of the system stack in the internal DPRAM from 32 to 1536 words Note The CPU SYSCON bits cannot be changed after execution of the EINIT instruction User s Manual 3 17 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 4 Interrupt and Exception Execution An Interrupt and Exception Handler is responsible for managing all system and core exceptions There are four different kinds of exceptions that are executed in a similar way Interrupts generated by the InTerrupt Controller ITC DMA trans
5. CON Control Register Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN MS 0 BSY BE PE RE TE BC rw rw r rh rwh rwh rwh rwh r rw User s Manual 11 6 V 1 6 2001 08 _ e Infineon technologies User s Manual C166S V1 SubSystem High Speed Synchronous Serial Interface SSC Field Bits Type Description BC 3 0 Bit Count Field 0001 1111 Shift counter is updated with every shifted bit Do not write to TE rwh Transmit Error Flag 0 No error 1 Transfer starts with the slave s transmit buffer not being updated RE rwh Receive Error Flag 0 No error 1 Reception completed before the receive buffer was read PE 19 rwh Phase Error Flag 0 No error 1 Received data changes around sampling clock edge BE 11 rwh Baudrate Error Flag 0 No error 1 More than factor 2 or 0 5 between slave s actual and expected baudrate BSY 12 Busy Flag Set while a transfer is in progress Do not write to MS 14 Master Select Bit 0 Slave Mode Operate on shift clock received via SCLK 1 Master Mode Generate shift clock and output it via SCLK EN 15 Enable Bit 1 Transmission and reception enabled Access to status flags and M S control 7 4 Reserved 0 13 r Reserved returns 0 if read should be writte
6. B Pointer SFR FE12y 09 Reset value FC00 15 14 13 42 11 10 9 8 7 6 5 4 3 2 1 0 1111 SP 0 r mh r User s Manual 3 61 V 1 6 2001 08 1 fi User s Manual nrineon M a C166S V1 SubSystem Central Processing Unit Field Bits Type Description 1111 15 12 r Fixed at 1111 SP 11 1 rwh Modifiable portion of register SP Specifies the top of the system stack 0 0 r Fixed at 0 3 6 3 1 Stack Overflow and Underflow Detection of stack overflow underflow is supported by two registers STKOV STacK OVerflow pointer and STKUN STacK UNderflow pointer Specific system traps Stack Overflow trap Stack Underflow trap will be entered whenever the SP reaches either boundary specified in these registers In many cases the user will place a Software ReSeT instruction SRST into the stack underflow and overflow trap service routines This is an easy approach that does not require special programming However this approach assumes that the defined internal stack is sufficient for the current software and that exceeding its upper or lower boundary represents a fatal error see Linear Stack It is also possible to use the stack underflow and stack overflow traps to cache portions of a larger external stack Only the portion of the system stack currently being used is placed into the internal memory thus allowing a greater portion of the internal RAM to be us
7. Name Physical Type 8 bit Description Reset Address Addr Value 2 PECSN5 FEDA SFR 6Dy PEC Segment No Register 0000y PECSN6 FEDC SFR 6E PEC Segment No Register 00004 PECSN7 FEDE SFR 6Fy PEC Segment No Register 00004 PECSN8 FEEOy SFR 70H PEC Segment No Register 0000y PECSN9 FEE2 SFR 714 PEC Segment No Register 0000 PECSN10 FEE4 SFR 724 PEC Segment No Register 0000y PECSN11 FEE6 SFR 734 PEC Segment No Register 00004 PECSN12 FEB8 SFR 5C PEC Segment No Register 00004 PECSN13 FEBA SFR 5D PEC Segment No Register 0000 PECSN14 FEBC SFR 5E PEC Segment No Register 0000 PECSN15 FEBE SFR 5Fyy PEC Segment No Register 0000 PECXCO FEFOy SFR 784 PEC Channel 0 Extended 0000 Control Register PECXC2 FEF2 SFR 79 PEC Channel 2 Extended 00004 Control Register PECXISNC FFBA SFR b DD PEC Extended Interrupt 0000 Subnode Control Register PSW FF10y SFR b 88 CPU Program Status Word 0000y RWDATA FOGA y ESFR 354 Cerberus RW Mode Data 0000y Register SOBG FEB4y SFR 5AH Serial Channel 0 Baud Rate 00004 Generator Reload Register SOCON FFBOy SFR b D8y Serial Channel 0 Control 0000 Register SOEIC FF70y SFR b B84 ASCO Error Interrupt Control 00004 Register SORBUF FEB2 SFR 594 Serial Channel 0 Receive Buffer 0000 Register RO SORIC FF6E SFR b B74 ASCO Receive Interrupt Control 0000 Register User s Manual 4
8. FEBA SOBG SFR SAH Serial Channel 0 Baud Rate 0000 Generator Reload Register FEB6y FDV SFR 5Bh Fractional Divider Register 0000 FEB8y PECSN12 SFR 5Cy PEC Segment No Register 00004 FEBA PECSN13 SFR 5Dy PEC Segment No Register 0000 FEBC PECSN14 SFR SEy PEC Segment No Register 00004 FEBE PECSN15 SFR SFy PEC Segment No Register 00004 FECO PECCO SFR 60H PEC Channel 0 Control Register 0000 FEC2 PECC1 SFR 61H PEC Channel 1 Control Register 0000 FEC4 PECC2 SFR 62H PEC Channel 2 Control Register 0000 FEC6 PECC3 SFR 63H PEC Channel 3 Control Register 0000 FEC8 PECC4 SFR 644 PEC Channel 4 Control Register 00004 FECA PECC5 SFR 65H PEC Channel 5 Control Register 0000 FECC PECC6 SFR 66h PEC Channel 6 Control Register 00004 FECE PECC7 SFR 67h PEC Channel 7 Control Register 0000 FEDO PECSNO SFR 68H PEC Segment No Register 0000 FED2 PECSN1 SFR 694 PEC Segment No Register 0000 FED4 PECSN2 SFR 6A PEC Segment No Register 0000 FED6 PECSN3 SFR 6By PEC Segment No Register 0000 User s Manual 4 25 V 1 6 2001 08 1 fi User s Manual a C166S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value FED8 PECSN4 SFR 6Cy PEC Segment No Register 0000 FEDA PECSN5 SFR 6D PEC Segment No Register 0000 FEDC PEC
9. Bit Function P1X y Port data register P1H or P1L bit y DP1L P1L Direction Ctrl Register ESFR F104 82 Reset Value 00y 15 14 13 12 Y 10 9 8 7 6 5 4 3 2 1 0 L 7 L 6 L 5 L 4 L 3 L 2 L 1 rw rw rw rw rw rw rw rw DP1 DP1 DP1 DP1 DP1 DP1 DP To DP1H P1H Direction Ctrl Register ESFR F106y 83H Reset Value 00y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H 4 H 3 H 2 H 1 rw rw rw rw rw rw rw rw DP1 DP1 DP1 DP1 DP1 DP1 DP1 DP1 H 7 H 6 H 5 H 0 User s Manual 7 7 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Parallel Ports Bit Function DP1X y Port direction register DP1H or DP1L bit y DP1X y 0 Port line P1X y is an input high impedance DP1X y 1 Port line P1X y is an output Alternate Functions of PORT1 When a demultiplexed external bus is enabled PORT1 is used as address bus Note that demultiplexed bus modes use PORT1 as a 16 bit port Otherwise all 16 port lines can be used for general purpose IO Alternate Function gt a T 2a C U7UUUUUUUUUUUUU h o o oL I lA lA lA lA lA lA lA lk rrr rrr IIIIIII SO NWAUONOUDWAUD v v General Purpose 8 16 bit Input Output Demux Bus Figure 7 4 PORT1 IO and Alternate Functio
10. MCTO2225 ALECTL Figure 8 8 Programmable External Bus Cycle 8 3 1 ALE Length Control The length of the ALE signal and the address hold time after its falling edge are controlled by the ALECTLx bits in the BUSCON registers When bit ALECTL is set to 1 User s Manual 8 16 V 1 6 2001 08 7 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface external bus cycles accessing the appropriate address window will have their ALE signal prolonged by half a CPU clock 1 TCL Also the address hold time after the falling edge of ALE on a multiplexed bus will be prolonged by half a CPU clock so the data transfer within a bus cycle refers to the same CLKOUT edges as usual i e the data transfer is delayed by one CPU clock This allows more time for the address to be latched Note ALECTLO is 1 after reset to select the slowest possible bus cycle the other ALECTLx bits are 0 after reset 8 3 2 Programmable Memory Cycle Time The C166S allows the user to adjust the controller s external bus cycles to the access time of the respective memory or peripheral This access time is the total time required to move the data to the destination It represents the period of time during which the controller s signals do not change The external bus cycles of the C166S can be extended by introducing waitstates during access see Figure 8 8 to compensate for a memory or peripheral that cann
11. 1 fi User s Manual n Infineon C1 66S V1 SubSystem High Speed Synchronous Serial Interface SSC Baudrat is BR EK E 2 lt BR gt 1 2 Baudrate Field Bits Type Description BR VALUE 15 0 rw Baudrate Timer Reload Register Value Reading BR returns the 16 bit content of the baudrate timer Writing BR loads the baudrate timer reload register with BR VALUE BR represents the contents of the reload register taken as unsigned 16 bit integer while Baudrate is equal to fus ci kiss cu as shown in Figure 11 7 The maximum baudrate that can be achieved when using a module clock of 60 MHz is 30 MBaud in Master Mode with lt BR gt 0000p or 15 MBaud in Slave Mode with lt BR gt 0001 yy Table 11 1 lists some possible baudrates together with the required reload values and the resulting bit times assuming a module clock of 60 MHz Table 11 1 Typical Baudrates of the SSC feik 60 MHz Reload Value Baudrate fus cLk ss_CLK Deviation 0000 30 MBaud only in Master Mode 0 0 0001 15 MBaud 0 096 001Dy 1 MBaud 0 0 0027 y 750 kBaud 0 0 003By 500 kBaud 0 0 0095y 200 kBaud 0 0 012By 100 kBaud 0 0 FFFFy 457 76 Baud 0 0 User s Manual 11 16 V 1 6 2001 08 pan 7 fi User s Manual n Infineon C1 66S V1 SubSystem High Speed Synchronous Serial Interface SSC 11 2 6 Error Detection Mechanisms The SSC is able to detect four
12. User s Manual 4 48 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 5 Interrupt Vector Table cont d sorted by signal name Signal Name Source of Interrupt Interrupt Control Vector Trap Interrupt IF Register Location No irq_i 40 Product Interrupt Request 40 IRQ40IC 00F4y 3DH irq_i 41 Product Interrupt Request 41 IRQ411C 00F8y EN irq_i 42 Product Interrupt Request 42 IRQ421C 0120 484 irq_i 43 Product Interrupt Request 43 IRQ43IC 01244 494 irq_i 44 Product Interrupt Request 44 IRQ44IC 0128 4A irq_i 45 Product Interrupt Request 45 IRQ45IC 0134 4Dy irq_i 46 Product Interrupt Request 46 IRQ46IC 0138 4Ey irq_i 47 Product Interrupt Request 47 IRQ47I1C 013Cy 4Fuy irq_i 48 Product Interrupt Request 48 IRQ48IC 00C0 30H irq_i 49 Product Interrupt Request 49 IRQ49IC 00C4 31H irq_i 50 Product Interrupt Request 50 IRQ50IC 00C8y 32H irq_i 51 Product Interrupt Request 51 IRQ51IC 00CC 33H irq_i 52 Product Interrupt Request 52 IRQ52IC 00DOy 344 irq_i 53 Product Interrupt Request 53 IRQ53IC 00D4 35H irq_i 54 Product Interrupt Request 54 IRQ54IC 00D8y 36H irq_i 55 Product Interrupt Request 55 IRQ55IC 00DCy 37H irq_i 56 Product Interrupt Request 56 IRQ56IC 00E0y 38H irq_i 57 Product Interrupt Request 57 IRQ57IC 00E4y 394 irq_i 58
13. 0 2 00 eee 2 14 3 Central Processing Unit 0 00 3 1 3 1 Register Description Format 22 2 24 RRERER teaver de ened 3 3 3 2 CPU Special Function Registers a aaaea 3 5 3 3 Instruction Fetch and Program Flow Control o oo ooooo 3 7 3 3 1 Branch Target Addressing Modes 0000 cee eee eee 3 7 3 3 2 Sequential and Non Sequential Instruction Flow 3 9 3 3 3 ATOMIC and EXTended Instructions o ooccooooo 3 13 3 3 4 Code Addressing via Code Segment and Instruction Pointer 3 14 3 3 5 The CPU System Configuration Register SYSCON 3 17 3 4 Interrupt and Exception Execution 00000 0c eee eee 3 18 3 4 1 Interrupt System Structure 2s csdedee todd 344 8454 cg eI des 3 19 3 4 2 Interrupt Arbitration cosita crepes preseas 3 19 3 4 3 Interrupt Vector Table 0 0 eee ees 3 22 3 4 4 Interrupt Control Functions in the Processor Status Word 3 22 3 4 4 1 Saving the Status during Interrupt Service 3 24 3 4 4 2 Context Switching ax reste rd vest iaeeses 3 24 3 4 5 i MUT PKT 3 26 3 4 5 1 Software Traps excita 3 26 User s Manual l 1 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Table of Contents Page 3 4 5 2 Hardware Taps seuesxesussizeesar uw tis beXud eda 3 26 3 4 6 Peripheral Event Controller oo o o o oocooooooooo 3 32 3 4 6 1 The PEC Source and De
14. User s Manual 7 3 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Parallel Ports POH PORTO High Register SFR FF02 81 Reset value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POH POH POH POH POH POH POH POH af 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Bit Function POX y Port data register POH or POL bit y DPOL POL Direction Ctrl Register ESFR F100 80 Reset value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DPOL DPOL DPOL DPOL DPOL DPOL DPOL DPOL T4 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DPOH POH Direction Ctrl Register ESFR F102 81 y Reset Value 00y 15 14 13 12 1i 10 9 8 7 6 5 4 3 2 1 0 DPOH DPOH DPOH DPOH DPOH DPOH DPOH DPOH 4 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Bit Function DPOX y Port direction register DPOH or DPOL bit y DPOX y 0 Port line POX y is an input high impedance DPOX y 1 Port line POX y is an output Alternate Functions of PORTO When an external bus is enabled PORTO is used as data bus or address data bus Note that an external 8 bit demultiplexed bus only uses POL while POH is free for IO provided that no other bus mode is enabled During external accesses in multiplexed bus modes PORTO first outputs the 16 bit intra segment addres
15. Request RXD _ Samp Receive Shift Transmit Shift TXD Register ling Register Receive Buffer Reg Transmit Buffer Reg RBUF TBUF Internal Bus Figure 10 4 Asynchronous Mode of Serial Channel ASC User s Manual 10 9 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Asynchronous Synchronous Serial Interface ASC 10 3 1 1 Asynchronous Data Frames 8 Bit Data Frames 8 bit data frames consist of either eight data bits D7 DO CON_M 001 or seven data bits D6 DO plus an automatically generated parity bit CON Mz 011g Parity may be odd or even depending on bit CON ODD An even parity bit will be set if the modulo 2 sum of the 7 data bits is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit CON PEN always OFF in 8 bit data mode The parity error flag CON PE will be set along with the error interrupt request flag if a wrong parity bit is received The parity bit itself will be stored in bit RBUF 7 CON M 001g 10 11 Bit UART Frame 7 Data Bits CON M 7011g Figure 10 5 Asynchronous 8 Bit Frames 9 Bit Data Frames 9 bit data frames consist of either nine data bits D8 DO CON_M 100p eight data bits D7 DO plus an automatically generated parity bit CON Mz 111g or eight data bits D7 DO plus wake up bit CON Mz 1015g Parity may be odd or even depending on bit CON ODD An even parity bit will
16. 26 cee ee 8 3 8 2 2 Demultiplexed Bus Modes esssslless 8 6 8 2 3 Switching Among the Bus Modes ooooccccoccc o 8 9 8 3 Programmable Bus Characteristics llle 8 16 8 3 1 ALE Length Control uuu na otra ae dee ie she ada 8 16 8 3 2 Programmable Memory Cycle Time sess 8 17 8 3 3 Programmable Memory Tri State Time o oo o 8 17 8 3 4 Read Write Signal Delay llle 8 18 8 3 5 Early WR C M 8 18 8 3 6 READY Controlled Bus Cycles 000 8 18 8 4 Controlling the External Bus Controller o oo oooo 8 21 User s Manual l 3 V 1 6 2001 08 1 fi User s Manual nrineon M C166S V1 SubSystem Table of Contents Page 8 5 EBC Idle Stat esperar ro EA erup 8 30 8 6 External Bus Arbitration iuusesse rue es oe EERREEER OS EAR REY 8 31 8 7 The XBUS Interface ooooooooccccrnnnr es 8 35 8 7 1 XBUS Access Control i c ecc Rr RR RR a Ry 8 37 9 Watchdog Timer vec 4 ecu ker E ERR SEG Ue Do eres 2 eee 9 1 9 1 Operation of the Watchdog Timer 000 0c eee eee eee 9 2 10 Asynchronous Synchronous Serial Interface ASC 10 1 10 1 Innes Peel M ERE TIS CETTE OL EDU T TI 10 1 10 2 Operational Overview 000 cee lees 10 4 10 3 General Operation Bx ev rud ee vev ies CREER EXE Re 10 5 10 3 1 Asynchronous Operation i4 RRREE EE ERG RE ER 10 9 10 3 1 1 Asynchronous Data Frames sssa
17. Infineon technologies User s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary cont d Mnemonic Description Bytes Shift and Rotate Instructions cont d SHR Rw data4 Shift right direct word GPR 2 number of shift cycles specified by immediate data ROL Rw Rw Rotate left direct word GPR 2 number of shift cycles specified by direct GPR ROL Rw data4 Rotate left direct word GPR 2 number of shift cycles specified by immediate data ROR Rw Rw Rotate right direct word GPR 2 number of shift cycles specified by direct GPR ROR Rw data4 Rotate right direct word GPR 2 number of shift cycles specified by immediate data ASHR Rw Rw Arithmetic sign bit shift right direct word GPR 2 number of shift cycles specified by direct GPR ASHR Rw data4 Arithmetic sign bit shift right direct word GPR 2 number of shift cycles specified by immediate data Data Movement MOV Rw Rw Move direct word GPR to direct GPR 2 MOV Rw data4 Move immediate word data to direct GPR 2 MOV reg ttdata16 Move immediate word data to direct register 4 MOV Rw Rw Move indirect word memory to direct GPR 2 MOV Rw Rw Move indirect word memory to direct GPR and 2 post increment source pointer by 2 MOV Rw Rw Move direct word GPR to indirect memory 2 MOV Rw Rw Pre decrement destination pointer by 2 and move direct word GPR to ind
18. Jump and Call Operations JMPA CC caddr Jump absolute if condition is met 4 JMPI cc Rw Jump indirect if condition is met 2 JMPR cc rel Jump relative if condition is met 2 JMPS seg caddr Jump absolute to a code segment 4 JB bitaddr rel Jump relative if direct bit is set 4 JBC bitaddr rel Jump relative and clear bit if direct bit is set 4 JNB bitadar rel Jump relative if direct bit is not set 4 JNBS bitaddr rel Jump relative and set bit if direct bit is not set 4 CALLA cc caddr Call absolute subroutine if condition is met 4 CALLI cc Rw Call indirect subroutine if condition is met 2 CALLR rel Call relative subroutine 2 CALLS seg caddr Call absolute subroutine in any code segment 4 PCALL reg caddr Push direct word register onto system stack and call 4 absolute subroutine TRAP trap7 Call interrupt service routine via immediate trap number 2 System Stack Operations POP reg Pop direct word register from system stack PUSH reg Push direct word register onto system stack SCXT reg datai6 Push direct word register onto system stack und update register with immediate data SCXT reg mem Push direct word register onto system stack und update 4 register with direct memory User s Manual 5 14 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary cont d
19. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r r r r r r r Field Bits Type Description 0 all r Fixed at Zero The Constant Ones Register ONES All bits of this bit addressable register are fixed at 1 by hardware This register is read only Register ONES can be used as a register addressable constant of all ones for bit manipulation or mask generation It can be accessed via any instruction which is capable of accessing an SFR ONES Constant Ones Register SFR FF1Ep 8Fp Reset value FFFFy 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r r r r r r r r r r r r r r r r Field Bits Type Description 1 all r Fixed at 1 User s Manual 3 89 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem CPU Identification register CPUID Central Processing Unit This 16 bit register contains the module and revision number of the implemented C166S module CPUID CPU Identification Register ESFR FOO0C E 06 Reset value 04 y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CPUREVNO CPUMODNO r r Field Bits Type Description CPUREVNO 15 8 r Module Number 044 C166S core module number CPUMODNO 7 0 r Version Number Version Number starts with 014 and is increm
20. D6 4 SCXT reg mem F6 4 MOV mem reg D7 4 EXTP R pag10 irang2 F7 4 MOVB mem reg EXTS R seg8 irang2 D8 2 MOV Rw Rw F8 D9 2 MOVB Rw Rw F9 DA 4 CALLS seg caddr FA 4 JMPS seg caddr DB 2 RETS FB 2 RETI DC 2 EXTP R Rw irang2 FC 12 POP reg EXTS R DD 2 JMPR cc_SGE rel FD 2 JMPR cc_ULE rel DE 2 BCLR bitoff 13 FE 2 BCLR bitoff 15 DF 2 BSET bitoff 13 FF 2 BSET bitoff 15 User s Manual 5 20 V 1 6 2001 08 1 fi User s Manual nrineon M s C166S V1 SubSystem Instruction Set 5 4 Instruction Description This chapter describes each instruction in details The instructions are listed alphabetically and the description contains the following elements Instruction Name Specifies the mnemonic opcode of the instruction in oversized bold lettering for easy reference The mnemonics have been chosen with regard to the particular operation performed by the instruction Syntax Specifies the mnemonic opcode and the required formal operands of the instruction as used in the following subsection Operation There are instructions with either none one two or three operands which must be separated from each other by commas MNEMONIC op1 op2 0p3 The syntax for the actual operands of an instruction depends on the selected addressing mode All of the available addressing modes are summarized at the end of each single instruction description In contrast to the syntax for the instru
21. Field Bits Type Description BSWCx 11 rw BUSCON Switch Control 0 Address windows are switched immediately 1 A tristate waitstate is inserted if the next bus cycle accesses a different window than the one controlled by this BUSCON register RDYENx 12 rw READY Input Enable 0 External bus cycle is controlled by bit field MCTC only 1 External bus cycle is controlled by the READY input signal CSRENx 14 rw Read Chip Select Enable 0 The CS signal is independent of the read command RD 1 The CS signal is generated for the duration of the read command CSWENx 15 rw Write Chip Select Enable 0 The CS signal is independent of the write cmd WR WRL WRH 1 The CS signal is generated for the duration of the write command 1 When the READY function is selected RDYENx 1 only the lower 3 bits of the respective MCTC bit field define the number of inserted waitstates 0 7 while the MSB of bit field MCTC is unused A BUSCON switch waitstate is enabled by bit BUSCONx BSWCx of the address window that is left ADDRSEL1 Address Select Register 1 SFR FE18y 0Cy Reset value 0000 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ IW rw ADDRSEL2 Address Select Register 2 SFR FE1Ay 0Dy Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ rw rw User s Manual 8 26 V 1 6 2001 08 an 7 fi User s Manual n Infineon C1 6
22. 1 fi User s Manual nrineon M C166S V1 SubSystem Memory Organization 4 5 Crossing Memory Boundaries The address space of the C166S CPU is divided implicitly into equally sized blocks of different granularity and into logical memory areas Crossing the boundaries between these blocks code or data or areas requires special attention to ensure that the controller executes the desired operations Memory Areas are partitions of the address space that represent different kinds of memory if provided at all These memory areas are the DPRAM the internal lO the internal LM if available and the external memory Accessing subsequent data locations that belong to different memory areas is not fully supported and may therefore lead to erroneous results There is no problem if the memory boundaries are word aligned However when executing code the different memory areas internal memory areas and external memory must be switched explicitly via branch instructions Sequential boundary crossing is not supported and may lead to erroneous results Segments are contiguous 64 KByte blocks They are referenced via the Code Segment Pointer CSP for code fetches and via an explicit segment number for data accesses overriding the standard DPP scheme During code fetching segments are not changed automatically but rather must be switched explicitly The instructions JMPS CALLS and RETS will do this Larger sequential programs make sure t
23. 3 6 2 Long and Indirect Addressing Modes These addressing modes use one of the 4 DPP registers to specify a 24 bit address Any word or byte data within the entire address space can be accessed with these modes Any long or indirect 16 bit address contains two parts that have different meanings Bits 13 0 specify a 14 bit data page offset while bits 15 14 specify the Data Page Pointer DPP 1 of 4 register which is used to generate the full 24 bit address see figure below The C1665 also supports an override mechanism for the DPP addressing scheme EXTP R and EXTS R instructions 15 14 13 16 bit Long Address Figure 3 8 Interpretation of a 16 bit Long Address Note Word accesses on odd byte addresses are not executed A hardware trap will be triggered User s Manual 3 54 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 6 2 4 Addressing via Data Page Pointer The 4 non bit addressable DPP registers select up to 4 different data pages The lower 10 bits of each DPP register select one of the 1024 possible 16 KByte data pages while the upper 6 bits are reserved for the future use The DPP registers provide access to the entire memory space in 16 KByte pages The DPP registers are used implicitly whenever data accesses to any memory location are made via indirect or direct long 16 bit addressing modes except for override accesses via EXTended instructions
24. 6 30 CPL tt ceeead 6 31 CPLB ii kun 6 32 DISWDT 6 33 pp M 6 34 User s Manual DIVL 6 35 DIVLU 2234626 6 36 DIVU osi cree oh 6 37 EINIT 6 38 EXTP iusti 6 39 EXT A eos 6 41 EXTR 6 43 EXIS 262 cen 6 44 EXISH 2224245 6 46 IDEE see eae wie 6 48 JB g ete vos wets 6 49 JBC 22222625 6 50 JMPA 6 52 JMPI 6 53 JMPR 2202 62 6 54 JMPS 22 2 ses 6 55 JNB oun teeea 6 56 JNBS 6 57 MOV 6 58 MOVB 6 60 MOVBS 6 62 MOVBZ 6 63 MUL 6 64 MULU 6 65 NEG exec 6 66 NEGB 6 67 NOP 6 68 OR A I 6 69 ORB coses 6 70 PCALL 6 71 POP sevielee 5 6 73 PRIOR ie her 6 74 13 1 Instruction Index PUSH siames 6 75 PWRDN 6 76 A 6 77 EEE 6 78 RETP 23s 6 79 REIS sai 6 80 e 6 81 Beeson e 6 83 7 A 6 85 DTE 6 86 sh ger 6 88 SRST 22233 6 90 SRVWDT 6 91 me 6 92 SUBB ii 6 93 SUBO 2 2 6 94 SUBCB 6 95 TRAP 6 96 TNT 6 98 XORB 00d ce 6 99 V 1 6 2001 08 pae 1 fi User s Manual SUE NN C166S V1 SubSystem Instruction Index User s Manual 13 2 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem 14 Keyword Index Keyword Index This section lists a number of keywords which refer to specific details of the C166S V1 SubS R1 in terms of its architecture its functional units or functions This helps to quickly find
25. Table 10 4 Typical Asynchronous Baudrates using the Fractional Input Clock Divider feik Desired BG FDV Resulting Deviation Baudrate Baudrate 40 MHz 115 2 kBaud 154 1F74 115 214 kBaud 0 01 57 6 kBaud 26H 1F7y 57 607 kBaud 0 01 38 4 kBaud 41y 1F7y 38 404 kBaud 0 01 19 2 kBaud 83H 1F7y 19 202 kBaud 0 01 60 MHz 115 2 kBaud 204 1F7y 115 214 kBaud 0 01 57 6 kBaud 41y 1F7y 57 607 kBaud 0 01 38 4 kBaud 614 1FDy 38 415 kBaud 0 04 19 2 kBaud C5H 1FDy 19 207 kBaud 0 04 Note ApNote AP2423 provides a program ASC EXE which allows calculation of values for the FDV and BG registers depending on fo the requested bauarate and the maximum deviation 10 3 3 2 Baudrate in Synchronous Mode For synchronous operation the baudrate generator provides a clock with four times the rate of the established baudrate see Figure 10 10 User s Manual 10 21 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Asynchronous Synchronous Serial Interface ASC 13 Bit Reload Register Shift Sample Clock BRS BRS Selected Divider 0 2 1 3 Figure 10 10 ASC Baudrate Generator Circuitry in Synchronous Mode The baudrate for synchronous operation of serial channel ASC can be determined by the formulas as shown in Table 10 5 Table 10 5 Synchronous Baudrate Formulas SBRS BG Formula 0 0 8191 so folk
26. Physical Name Type 8 bit Description Reset Address Addr Value FF70y SOEIC SFR b B8y ASCO Error Interrupt Control 0000 Register FF72y SSCOTIC SFR b B9y SSCO Transmit Interrupt Control 0000 Register FF74 SSCORIC SFR b BAy SSCO Receive Interrupt Control 0000 Register FF76y SSCOEIC SFR b BBy SSCO Error Interrupt Control 00004 Register FF78y IRQ16IC SFR b BCh IRQ16 Interrupt Control Register 0000 FF7Ay IRQ17IC SFR b BDy IRQ17 Interrupt Control Register 0000 FF7Cy IRQ18IC SFR b BEy IRQ18 Interrupt Control Register 0000 FF7Ey IRQ19IC SFR b BFy IRQ19 Interrupt Control Register 0000 FF80y IRQ20IC SFR b COy IRQ20 Interrupt Control Register 0000 FF82y IRQ21IC SFR b C1y IRQ21 Interrupt Control Register 0000 FF84y IRQ221C SFR b C2y IRQ22 Interrupt Control Register 0000 FF86y IRQ23IC SFR b C3y IRQ23 Interrupt Control Register 0000 FF88y IRQ24IC SFR b C4y IRQ24 Interrupt Control Register 0000 FF8A IRQ25IC SFR b C5 IRQ25 Interrupt Control Register 00004 FF8Cy IRQ26IC SFR b C6y IRQ26 Interrupt Control Register 0000 FF8E IRQ27IC SFR b C7y IRQ27 Interrupt Control Register 0000 FF90y IRQ28IC SFR b C8y IRQ28 Interrupt Control Register 0000 FF92y IRQ29IC SFR b C9y IRQ29 Interrupt Control Register 0000 FF94 IRQ30IC SFR b CAy IRQ30 Interrupt Control Register 0000 FF96y IRQ311C SFR b CBy IRQ31
27. User s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary cont d Mnemonic Description Bytes Logical Instructions cont d OR Rw Rw Bitwise OR direct word GPR with direct GPR OR Rw Rw Bitwise OR indirect word memory with direct GPR OR Rw Rw Bitwise OR indirect word memory with direct GPR and post increment source pointer by 2 OR Rw data3 Bitwise OR immediate word data with direct GPR 2 OR reg data16 Bitwise OR immediate word data with direct register 4 OR reg mem Bitwise OR direct word memory with direct register 4 OR mem reg Bitwise OR direct word register with direct memory 4 ORB Rb Rb Bitwise OR direct byte GPR with direct GPR 2 ORB Rb Rw Bitwise OR indirect byte memory with direct GPR 2 ORB Rb Rw Bitwise OR indirect byte memory with direct GPR and 2 post increment source pointer by 1 ORB Rb data3 Bitwise OR immediate byte data with direct GPR 2 ORB reg data8 Bitwise OR immediate byte data with direct register 4 ORB reg mem Bitwise OR direct byte memory with direct register 4 ORB mem reg Bitwise OR direct byte register with direct memory 4 XOR Rw Rw Bitwise XOR direct word GPR with direct GPR 2 XOR Rw Rw Bitwise XOR indirect word memory with direct GPR 2 XOR Rw Rw Bitwise XOR indirect word memory with direct GPR and 2 post increment source pointer by 2 XOR Rw data3 Bitwis
28. User s Manual 7 9 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Parallel Ports 7 4 Port 4 If this 8 bit port is used for general purpose lO the direction of each line can be configured via the corresponding direction register DP4 P4 Port 4 Data Register SFR FFC8y E4y Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P4 7 P4 6 P4 5 P4 4 P4 3 P4 2 P4 1 P4 0 Bit Function P4 y Port data register P4 bit y DP4 P4 Direction Ctrl Register SFR FFCAp E5p Reset Value 00y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP4 DP4 DP4 DP4 DP4 DPA DP4 DP4 af 6 E 4 3 2 1 0 Bit Function DP4 y Port direction register DP4 bit y DP4 y 0 Port line P4 y is an input high impedance DP4 y 1 Port line P4 y is an output Alternate Functions of Port 4 During external bus cycles that use segmentation i e an address space above 64 KByte a number of Port 4 pins may output the segment address lines The number of pins that is used for segment address output determines the external address space which is directly accessible The other pins of Port 4 if any may be used for general purpose lO If segment address lines are selected the alternate function of Port 4 may be necessary to access e g external memory directly after reset For this r
29. XOR Logical Exclusive OR XOR Group Logical Instructions Syntax XOR op1 op2 Source Operand s op1 op2 gt WORD Destination Operand s op1 gt WORD Operation op1 op1 op2 Description Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes XOR Rw data3 58 n 0 2 XOR Rw RWm 50 nm 2 XOR Rw Rw 58 nlii 2 XOR Rw Rwj 58 n 10ii 2 XOR mem reg 54 RR MM MM 4 XOR reg data16 56 RR HH HH 4 XOR reg mem 52 RR MM MM 4 User s Manual 6 98 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set XORB Logical Exclusive OR XORB Group Logical Instructions Syntax XORB opt op2 Source Operand s op1 op2 gt BYTE Destination Operand s op1 gt BYTE Operation op1 op1 op2 Description Performs a bitwise logical EXCLUSIVE OR of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 CPU Flags E Z V C N E Set if the value of op2 repre
30. n Infineon C1 66S V1 SubSystem General Purpose Timer Unit Table 12 13 Timer 5 Input Parameter Selection Timer and Gated Timer Modes T5I Prescaler for fy Prescaler for f Prescaler for fj Prescaler for foi BPS2 00 BPS2 01 BPS2 10 BPS2 11 000 4 2 16 8 001 8 4 32 16 010 16 8 64 32 011 32 16 128 64 100 64 32 256 128 101 128 64 512 256 110 256 128 1024 512 111 512 256 2048 1024 Timer T5 in Counter Mode Counter Mode for auxiliary Timer T5 is selected by setting bitfield T5M in register T5CON to 001p In Counter Mode Timer T5 can be clocked either by a transition at the external input line T5IN or by a transition of the output toggle latch T6OTL on Timer 6 Down TxEUD MCB02221 c Figure 12 21 Block Diagram of Auxiliary Timer T5 in Counter Mode User s Manual 12 37 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at either the input line T5IN or at the toggle latch T6OTL Bitfield T5P in control register T5CON selects the triggering transition see Table 12 14 Table 12 14 Auxiliary Timer Counter Mode Input Edge Selection T5P Triggering Edge for Counter Increment Decrement X00 None Counter T5 is disabled
31. FE18y ADDRSEL1 SFR 0C Address Select Register 1 0000 FE1Ay ADDRSEL2 SFR 0Dy Address Select Register 2 0000 FE1C4 ADDRSEL3 SFR OEY Address Select Register 3 0000 FE1E ADDRSEL4 SFR OF Address Select Register 4 0000 FE20y SFR 104 FE22y SFR 114 FE24y SFR 124 FE26y SFR 134 FE28 SFR 144 FE2Ay SFR 15H FE2Cy SFR 164 FE2E y SFR 174 FE30y SFR 184 User s Manual 4 22 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value FE32y SFR 194 FE344 SFR 1Ay FE36y SFR 1By FE38y SFR 1Cy FE3Ay SFR 1Dy FE3Cy SFR 1Eu FESE y SFR 1Fy FE40y T2 SFR 204 GPT Timer 2 Register 0000 FE42y T3 SFR 21H GPT Timer 3 Register 0000y FE44 T4 SFR 22H GPT Timer 4 Register 0000 FE46y T5 SFR 23H GPT Timer 5 Register 0000y FE48y T6 SFR 244 GPT Timer 6 Register 0000 FE4A CAPREL SFR 25H GPT Capture Reload Register 0000y FE4C GPTIPISEL SFR 26H GPT Port Input Selection 0000y Register FE4E y SFR 274 FE504 SFR 284 FE524 SFR 294 FE54y SFR 2Ay FE56y SFR 2By FE58y SFR 2Cy FE5Ay SFR 2Dy FE5C reserved SFR 2Ey reserved do not use FE5Ey reserved SFR 2Fy reserved do not use FE60y SFR 304 FE624 SFR 31H FE64y SFR 324 FE66y
32. IRQ90 Interrupt Control Register 00004 IRQ91IC F156H ESFR b AB IRQ91 Interrupt Control Register 0000y IRQ92IC F158H ESFR b ACy IRQ92 Interrupt Control Register 00004 IRQ93IC F15Ay ESFR b AD IRQ93 Interrupt Control Register 00004 IRQ94IC F15Cy ESFR b AEy IRQ94 Interrupt Control Register 00004 IRQ95IC P15Ey ESFR b AFy IRQ95 Interrupt Control Register 00004 IRQ96IC FOB8y ESFR 5C4 IRQ96 Interrupt Control Register 00004 IRQ97IC FOBAy ESFR 5Dy IRQ97 Interrupt Control Register 0000y IRQ98IC FOBC ESFR 5Ey IRQSS Interrupt Control Register 0000 IRQ99IC FOBEy ESFR 5Fy_ IRQ99 Interrupt Control Register 0000 IRQ100IC FOCOy ESFR 604 1RQ100 Interrupt Control 0000 Register IRQ1011C FOC2 ESFR 614 IRQ101 Interrupt Control 00004 Register User s Manual 4 36 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Memory Organization Table 4 3 SFR ESFR Table ordered by name cont d Name Physical Type 8 bit Description Reset Address Addr Value 2 IRQ1021C FOC4y ESFR 624 IRQ102 Interrupt Control 0000y Register IRQ103IC FOC6y ESFR 634 IRQ103 Interrupt Control 0000y Register IRQ104IC FOC8y ESFR 644 1IRQ104 Interrupt Control 00004 Register IRQ105IC FOCA ESFR 65 IRQ105 Interrupt Control 0000 Register I
33. Table 3 2 Sequential instruction execution local memory 0 1 waitstate Clock Cycle Ty Te T4 Ta T4 Ta Ty Ta Ty Te Ty Ta FETCH In Inet In 2 In 3 In 4 In 6 DECODE In 1 In Inet In 2 In 3 Ine EXECUTE In 2 In 1 In In 1 In 2 In 3 WRITE BACK ns In 2 In 1 In Inet In 2 Machine Cycle Tm Tm 1 Tm 2 Tm 3 Tm 4 Tm 5 The fetch stage fetches instructions from the Local Memory LM via the 32 bit LM Bus If 16 bit instructions are fetched from the LM Bus instructions can be buffered in the 3 word FIFO The fetch stage always prefetches instructions If the buffer is filled with instructions LM Bus accesses are stopped until the fetched instructions can be loaded into the buffer again User s Manual 3 9 V 1 6 2001 08 1 fi User s Manual nrineon M C166S V1 SubSystem Central Processing Unit Table 3 3 shows the standard unconditional branch branch taken instruction pipeline assuming a fast local memory 0 1 waitstates Table 3 3 Unconditional branches LM Bus 0 1 waitstate Clock Cycle T To T4 To T4 To Ty To T4 To Ty To LM Address lat LM Data 32bit lat lat FETCH In In 1 lt la ho branch DECODE Inet In In 1 7 lt lua branch EXECUTE In 2 In i In In 1 3 lt branch WRITE BACK In 2 In i In In t branch Machine Cycle Tm Tm 1 Tm 2 Tm 3 Tm
34. bitoff FOy FFy GPR Bit word offset bitaddr Word offset as with bitoff bitoff 004 FFi Any single bit immediate bit position bitpos 0 15 Rw Rb Specifies direct access to any GPR in the currently active context Both Rw and Rb require 4 bits in the instruction format The base address of the global register bank is determined by the contents of register CP Rw specifies a 4 bit word GPR address relative to the base address CP while Rb specifies a 4 bit byte GPR address relative to the base address CP User s Manual 3 52 V 1 6 2001 08 1 fi User s Manual nrineon M os C166S V1 SubSystem reg bitoff bitaddr Central Processing Unit Specifies direct access to any E SFR or GPR in the currently active context The reg value requires 8 bits in the instruction format Short reg addresses in the range from 00 to EF yy always specify E SFRs In that case the factor A equals 2 and the base address is 00 FEOO for the standard SFR area or 00 F000 for the extended ESFR area The reg accesses to the ESFR area require a preceding EXT R instruction to switch the base address Depending on the opcode either the total word for word operations or the low byte for byte operations of an SFR can be addressed via reg Note that the high byte of an SFR cannot be accessed via the reg addressing mode Short reg addresses in the range from FOy to FF always specify GPRs In that case onl
35. do not use FIEEy reserved reserved do not use F1FOy reserved reserved do not use F1F24 reserved reserved do not use F1F44 reserved reserved do not use F1F6 reserved reserved do not use F1F8y reserved reserved do not use F1FAy reserved reserved do not use F1FC reserved reserved do not use FIFE reserved reserved do not use FEOO DPPO SFR 004 CPU Data Page Pointer 0 00004 Register 10 bits FE024 DPP1 SFR 01H CPU Data Page Pointer 1 0001 y Register 10 bits User s Manual 4 21 V 1 6 2001 08 1 fi User s Manual a C166S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value FE04y DPP2 SFR 024 CPU Data Page Pointer 2 0002 Register 10 bits FEO6 DPP3 SFR 03 CPU Data Page Pointer 3 0003 Register 10 bits FEO8y CSP SFR 044 CPU Code Segment Pointer 00004 Register 8 bits FEOA reserved SFR 05H reserved do not use 0000y FEOCy MDH SFR 064 CPU Multiply Divide Register 00004 High Word FEOE MDL SFR 074 CPU Multiply Divide Register 0000 Low Word FE10y CP SFR 08H CPU Context Pointer Register FCOO FE12y SP SFR 09h CPU System Stack Pointer FCOO0y Register FE14y STKOV SFR DA y CPU Stack Overflow Pointer FAO0y Register FE16y STKUN SFR 0By CPU Stack Underflow Pointer FCOO0y Register
36. technologies Command RD WR Asynch READY l Figure 8 9 READY Controlled Bus Cycles Section 8 3 4 Read Write Delay Section 8 3 5 Early Write Cycle as programmed including MCTC waitstates Example shows 0 MCTC WS READY sampled HIGH at this sampling point generates a READY controlled waitstate READY sampled LOW at this sampling point terminates the currently running bus cycle Multiplexed bus modes have a MUX waitstate added after a bus cycle and an additional MTTC waitstate may be inserted here For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles for a demultiplexed bus without MTTC waitstate this delay is zero If the next following bus cycle is READY controlled an active READY signal must be disabled before the first valid sample point for the next bus cycle This sample point depends on the MTTC waitstate of the current cycle and on the MCTC waitstates and the ALE mode of the next cycle If the current cycle uses a multiplexed bus the intrinsic MUX waitstate adds another CLKOUT cycle to the READY deactivation time arN 6 The READY function is enabled via the ReaDY ENable RDYENX bits in the BUSCON registers When this function is selected RDYENx 1 only the lower 3 bits of the respective MCTC bit field define the number of inserted waitstates 0 7 while the MSB of bit field MCTC is unused As shown in Figure 8 9 the asychronous READY requires additional wait
37. 0 0 1 Positive transition rising edge on T5IN 010 Negative transition falling edge on T5IN 0 1 1 Any transition rising or falling edge on T5IN 101 Positive transition rising edge on T6OTL 110 Negative transition falling edge on T6OTL 111 Any transition rising or falling edge on TGOTL Note Only state transitions of TEOTL caused by the overflow underflow of T6 will trigger the counter function of T5 Modifications of T6OTL via software will NOT trigger the counter function of T5 The maximum input frequency allowed in Counter Mode is f x 4 BPS2 01 To ensure that a transition of the count input signal applied to T5IN is correctly recognized its level should be held high or low for at least 2 fo cycles BPS2 01 before it changes 12 3 3 Timer Concatenation Using the toggle bit TEOTL as a clock source for the auxiliary Timer of Block 2 in Counter Mode concatenates core Timer T6 with auxiliary Timer T5 Depending on which transition of TGOTL is selected to clock auxiliary Timer T5 this concatenation forms a 32 bit or a 33 bit timer counter e 32 bit Timer Counter If both a positive and a negative transition of TGOTL is used to clock auxiliary Timer T5 this timer is clocked on every overflow underflow of core Timer T6 Thus the two timers form a 32 bit timer e 33 bit Timer Counter If either a positive or a negative transition of TGOTL is selected to clock auxiliary Timer T5 this timer is clocked on every s
38. 1 fi User s Manual neon Infineon C1 66S V1 SubSystem General Purpose Timer Unit Timer Block 2 Capture Reload Register CAPREL in Capture And Reload Mode Because the reload and capture functions of register CAPREL can be enabled individually by bits T5SC and T6SR the two functions can be enabled simultaneously by setting both bits This feature can be used to generate an output frequency that is a multiple of the input frequency BPS2 T5l Up Down Auxiliary Timer T5 T5IRQ Edge Select T5CLR aim T5CC CT3 i T5SC gt CRIRQ CAPREL Register T6CLR BPS2 T l T6SR For pero Core Timer T6 T6IRQ T6R Up Down gt T6OFL MCB02046_c Figure 12 25 Timer Block 2 Register CAPREL in Capture And Reload Mode This combined mode can be used to detect consecutive external events which may occur aperiodically but which require a finer resolution more ticks within the time between two external events For this purpose the time between the external events is measured using Timer T5 and the CAPREL register Timer T5 runs in Timer Mode counting up with a frequency of f x 32 for example The external events are applied to line CAPIN When an external event occurs the contents of Timer T5 are latched into User s Manual 12 42 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem General Purpose Timer Unit register CAPREL and Ti
39. 11 FB By General Purpose byte Register RL11 UU RL6 CP 12 FC Cy General Purpose byte Register RL12 UU RH6 CP 13 FD Dy General Purpose byte Register RL13 UU HL7 CP 14 FE Ey General Purpose byte Register RL14 UU RH7 CP 15 FF Fr General Purpose byte Register RL15 UU User s Manual 3 49 V 1 6 2001 08 1 fi User s Manual nrineon M s C166S V1 SubSystem Central Processing Unit 3 5 1 Context Switch An Interrupt Service Routine ISR or a task scheduler of an operating system usually saves the contents of all used registers into the stack and restores them before returning The more registers a routine uses the more time is wasted by saving and restoring The contents of the register bank are switched by changing the base address of the memory mapped GPR bank The base address is given by the contents of the Context Pointer CP register The Context Pointer The CP register is not bit addressable It can be updated via any instruction capable of modifying SFRs CP Context Pointer SFR FE10 08 Reset value FC00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 CP 0 r r r r rw r Field Bits Type Description 1 15 12 r CP always points in the DPRAM CP 11 1 rw Modifiable portion of register CP Specifies the word base address of the current memory mapped register bank Note When writing a value to register CP wit
40. 2001 08 1 fi User s Manual nrineon M C166S V1 SubSystem Central Processing Unit 3 2 CPU Special Function Registers The core CPU requires a set of CPU Special Function Registers CSFRs to maintain the system state information to control system and bus configuration and to manage code memory segmentation and data memory paging The CPU also uses CSFRs to access the General Purpose Registers GPRs and the System Stack to supply the ALU with register addressable constants and to support multiply and divide ALU operations The access mechanism for these CSFRs in the CPU core is identical to the access mechanism for any other SFR Since all SFRs can be controlled by any instruction that is capable of addressing the SFR CSFR memory space there is no need for special system control instructions However to ensure proper processor operations certain restrictions on the user access to some CSFRs must be applied For example the Instruction Pointer IP and Code Segment Pointer CSP registers cannot be accessed directly at all They can only be changed indirectly via branch instructions The Program Status Word PSW Stack Pointer SP and Multiply Divide Control Register MDC registers can be modified explicitly by the programmer and implicitly by the CPU during normal instruction processing Note Note that any explicit write request via software to a C SFR supersedes a simultaneous modification by hardware
41. 2001 08 User s Manual C166S V1 SubSystem Central Processing Unit technologies e Address Pointer Updating Indirect addressing modes use a GPR value to generate the address of the source and or destination operand If this GPR is updated explicitly by the preceding instruction one NOP instruction is automatically inserted Lg ADD RO 0002h increment address pointer GPR 0 Tinject NOP automatically injected NOP Inyi MOV R2 RO use GPR 0 for indirect addressing To improve performance an instruction not using this new GPR as a destination operand can be inserted between an explicit GPR changing and a subsequent instruction using an indirect addressing mode IQ ADD RO 0002h increment address pointer GPR 0 Tode fedes must not be an instruction updating GPR 0 In MOV R2 RO use GPR O0 for indirect addressing e Context Pointer Updating An instruction that calculates a physical GPR operand address via the CP register is incapable of using a new CP value that is to be updated by the preceding instruction Thus to make sure that the new CP value is used at least two instructions must be inserted between an instruction that changes the CP and a subsequent instruction that uses the GPR as shown in the following example Tz SCXT CP 40FCOOh select a new context Lapi Seres must not be an instruction using a GPR laxo Gases must not be an instruction using a GPR In 3 MOV RO tdataX
42. 24 FC Cy General Purpose word Register R12 UUUU R13 CP 26 FD Dy General Purpose word Register R13 UUUU R14 CP 28 FE Ey General Purpose word Register R14 UUUU R15 CP 30 FF Fi General Purpose word Register R15 UUUU Note The first 8 GPRs R7 RO may also be accessed byte wise Note Writing to a GPR byte does not affect the other byte of the same GPR User s Manual 3 48 V 1 6 2001 08 1 fi User s Manual SUE NN C166S V1 SubSystem Central Processing Unit Each half of the byte wise accessible registers has a special name see table below Table 3 11 Addressing modes to access Byte GPRs Name Physical 8 Bit 4 Bit Description Reset Address Address Address Value RLO CP 0 FO On General Purpose byte Register RLO UU RHO CP 1 Fly lu General Purpose byte Register RL1 UU RL1 CP 2 F2 24 General Purpose byte Register RL2 UU RH1 CP 3 F3 34 General Purpose byte Register RL3 UU HL2 CP 4 F4 4y General Purpose byte Register RL4 UU RH2 CP 5 F5 5H General Purpose byte Register RL5 UU RL3 CP 6 F6y 64 General Purpose byte Register RL6 UU RH3 CP 7 F7y 7H General Purpose byte Register RL7 UU RL4 CP 8 F8 84 General Purpose byte Register RL8 UU RH4 CP 9 F9 9 General Purpose byte Register RL9 UU RL5 CP 410 FA Ay General Purpose byte Register RL10 UU RH5 CP
43. 4 rwh End of table Flag 0 Source operand is neither 8000 nor 80 1 Source operand is 8000 or 80 Z 3 rwh Zero Flag 0 ALU result is not zero 1 ALU result is zero V 2 rwh OVerflow Flag 0 No overflow produced 0 Overflow produced User s Manual 3 76 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit Field Bits Type Description C 1 rwh Carry Flag 0 No carry borrow bit produced 1 Carry borrow bit produced N 0 rwh Negative Result 0 ALU result is not negative 1 ALU result is negative ALU Status N C V Z E MULIP The condition flags N C V Z E within the PSW indicate the ALU status resulting from the ALU operation last performed They are set by the majority of instructions according to specific rules depending on the ALU operation or data movement After execution of an instruction that explicitly updates PSW the condition flags may no longer represent an actual CPU status An explicit write operation to PSW supersedes the condition flag values that are implicitly generated by the CPU An explicit read access to PSW returns the value of PSW after execution of the previous instruction Note After reset all of the ALU status bits are cleared e N Flag For the majority of ALU operations the N flag is set to 1 if the most significant bit of the result contains a 1 Otherwise it is cleared In the cas
44. Auxiliary Timer Tx TxIRQ T Core Timer T3 gt T3IRQ BPS1 T3l xl 0 T3OUT 1 x 2 4 R T3 MCB02038_b T30E Figure 12 15 Auxiliary Timer of Timer Block 1 in Capture Mode Upon a trigger selected transition at the corresponding input line TxIN the contents of the core timer are loaded into the auxiliary timer register and the associated interrupt request line TxIRQ will be driven high Note Port pins associated with T2IN and T4IN must be configured to Input and the level of the capture trigger signal should be held high or low for at least 4 fy BPS1 01 cycles before it changes to ensure correct edge detection Auxiliary in Incremental Interface Mode When auxiliary Timers T2 and T4 are programmed to Incremental Interface Mode their operation is the same as described for core Timer T3 The descriptions figures and tables apply accordingly with two exceptions There is no TxOUT output line for T2 and T4 e Overflow underflow monitoring is not supported no bit TxOTL Table 12 9 Timer x Input Parameter Selection for Incremental Interface Mode Txl Triggering Edge for Counter Update 000 None Counter Tx stops 001 Any transition rising or falling edge on TxIN 010 Any transition rising or falling edge on TXEUD 011 Any transition rising or falling edge on TxIN or TXEUD 1XX Reserved Do not use this combination User s Manual 12 25 V 1 6 2001 08
45. Bytes Bytes 00 2 ADD Rw Rw 20 2 SUB Rw Rw 01 2 ADDB Rb Rb 21 2 SUBB Rb Rb 02 4 ADD reg mem 22 4 SUB reg mem 03 4 ADDB reg mem 23 4 SUBB reg mem 04 4 ADD mem reg 24 4 SUB mem reg 05 4 ADDB mem reg 25 4 SUBB mem reg 06 4 ADD reg data16 26 4 SUB reg data16 07 4 ADDB reg data8 27 4 SUBB reg data8 08 2 ADD Rw Rw or 28 2 SUB Rw Rw or Rw Rw or Rw Rw or Rw data3 Rw data3 09 2 ADDB Rb Rw or 29 2 SUBB Rb Rw or Rb Rw or Rb Rw or Rb data3 Rb data3 OA 4 BFLDL bitoff mask8 2A 4 BCMP bitaddr bitaddr data8 OB 2 MUL Rw Rw 2B 2 PRIOR Rw Rw 0C 2 ROL Rw Rw 2C 2 ROR Rw Rw 0D 2 JMPR cc UC rel 2D 2 JMPR cc_EQ rel or cc_Z rel OE 2 BCLR bitoff 0 2E 2 BCLR bitoff 2 OF 2 BSET bitoff 0 2F 2 BSET bitoff 2 10 2 ADDC Rw Rw 30 2 SUBC Rw Rw 11 2 ADDCB Rb Rb 31 2 SUBCB Rb Rb 12 4 ADDC reg mem 32 4 SUBC reg mem 13 4 ADDCB reg mem 33 4 SUBCB reg mem 14 4 ADDC mem reg 34 4 SUBC mem reg 15 4 ADDCB mem reg 35 4 SUBCB mem reg 16 4 ADDC reg data16 36 4 SUBC reg data16 17 4 ADDCB reg data8 97 4 SUBCB reg data8 18 2 ADDC Rw Rw or 38 2 SUBC Rw Rw or Rw Rw or Rw Rw or Rw data3 Rw data3 19 2 ADDCB Rb Rw or 39 2 SUBCB Rb Rw or Rb Rw or Rb Rw or Rb data3 Rb data3 1A 4 BFLDH bitoff mask8 3A 4 BMOVN bitaddr bitaddr data8 1B 2 MULU Rw Rw 3B 1C 2 ROL Rw data4 3C 2 ROR Rw data4 1D 2 JMPR cc_NET rel 3D 2 JMPR
46. MDCb FFOE 87 Multiply Divide Control Register 0000 MDH FEOC 06 Multiply Divide High Word 00004 MDL FEOE 07y Multiply Divide Low Word 00004 ONESb FF1Ey 8Fy Constant Value 1 s Register read only FFFFy PSWb FF10y 88H Program Status Word 0000y SP FE12 09h Stack Pointer FCO00 STKOV FE14 OAH Stack Overflow Register FAO0y STKUN FE16y 0By Stack Underflow Register FC00 SYSCON FF124 894 System CPU Control Register 20 TFRb FFAC D6y Trap Flag Register 0000 ZEROSb FF1ICy 8Ey Constant Value 0 s Register read only 0000 1 YY defined by implemented CPU version 2 YYYY defined by reset and system configuration User s Manual 3 93 V 1 6 2001 08 1 fi User s Manual a C166S V1 SubSystem Central Processing Unit 3 10 8 Core Special Function Registers ordered by Address The following table lists all CSFRs which are implemented in the C166S ordered by their physical address Bit addressable CSFRs are marked with the letter b in column Name CSFRs within the Extended SFR Space ESFRs are marked with the letter E in column 8 Bit Address Name Physical 8 Bit Description Reset Address Address Value CPUID FOOCy E 06y CPU Identification Register e DPPO FEO0y 00 Data Page Pointer 0 10 bits 0000 DPP1 FE02y 01y Data Page Pointer 1 10 bits 0001 y DPP2 FE044 024 Data Page Pointer 2 10 bits 00024 DPP3 FEO6y 0
47. Please refer to the product User Manual User s Manual 3 39 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Central Processing Unit cleared if EOPINT is set to 1 If EOPINT is 0 the request flag will not be cleared and another interrupt request will be generated on the same priority level The respective PEC channel remains idle and the associated interrupt service routine is activated instead of PEC transfer because COUNT contains the 0000 value User s Manual 3 40 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 4 6 5 Channel Link Mode for Data Chaining Channel linking if enabled links two channels together to serve the data transfer requests of one peripheral The whole data transfer for example a message is divided into separately controlled block transfers The two PEC channels that are linked together handle chained block transfers alternately with one another At the end of a data block transfer controlled by one PEC channel the other linked PEC channel is started automatically to continue the transfer with the next data block Channel linking and data block chaining are supported within pairs of PEC channels channels 0 amp 1 2 amp 3 4 amp 5 etc Each data block is controlled by one PEC channel of the channel pair Channel linking is enabled if the Channel Link CL control bits of both PEC chann
48. SR cLR 9 BPS gr oE JUDE up FER T6M Tel rw rw r rw rwh rw rw rw rw rw rw Field Bits Typ Description T6 15 0 rwh Timer 6 Contains the current value of Timer 6 Field Bits Typ Description T6l 2 0 rw Timer 6 Input Parameter Selection Timer Mode see Table 12 11 for encoding Gated Timer Mode see Table 12 11 for encoding Counter Mode see Table 12 12 for encoding T6M 5 3 rw Timer 6 Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer with gate active high 1XX Reserved Do not use this combination T6R 6 rw Timer 6 Run Bit 0 Timer Counter 6 stops 1 Timer Counter 6 runs User s Manual 12 28 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem General Purpose Timer Unit Field Bits Typ Description T6UD 7 rw Timer 6 Up Down Control when T6UDE 0 0 Counts Up 1 Counts Down T6UDE 8 rw Timer 6 External Up Down Enable 0 Counting direction is internally controlled by software 1 Counting direction is externally controlled by line T6EEUD T6OE 9 rw Overflow Underflow Output Enable 0 T6 overflow underflow can not be externally monitored 1 T6 overflow underflow may be externally monitored via TOUT T6OTL 10 rwh Timer 6 Output Toggle Latch Toggles on each overflow underflow of T6 Can be set or reset
49. The bit has to be reset by SW 0 No count edge was detected 1 A count edge was detected T3CHDIR 14 rwh Timer 3 Count Direction Change The bit is set on a change of the count direction of Timer 3 The bit has to be reset by SW 0 No change in count direction was detected 1 A change in count direction was detected T3RDIR 15 rh Timer 3 Rotation Direction 0 Timer 3 counts up 1 Timer 3 counts down Additionally the timer input frequency can be modified by T3l for Timer Mode Gated Timer Mode and Counter Mode Run Control The timer can be started or stopped by software through bit T3R Setting bit T3R will start the timer clearing T3R stops the timer In Gated Timer Mode the timer will run only if T3R is set and the gate is active high or low as programmed Note When bit T2RC T4RC in timer control register T2CON T4CON is set T3R will also control start and stop auxiliary Timer T2 T4 User s Manual 12 7 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V1 SubSystem General Purpose Timer Unit Count Direction Control The count direction of the core timer can be controlled either by software or by the external input line T3EUD These options are selected by bits T3UD and T3UDE in control register T3CON When the up down control is set by software bit T3UDE is cleared the count direction can be altered by setting or clearing bit T3UD When T3UDE is s
50. User s Manual 3 78 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Central Processing Unit be reasonably used for table search operations In all other cases the E flag value depends on the value of the source operand to signify whether or not the end of a search table is reached If the value of the source operand of an instruction equals the lowest negative number that depends on the data format of the corresponding instruction 8000 for the word data type or 80 for the byte data type the E flag is set to 1 otherwise it is cleared e MULIP Flag The MULIP flag will be set to 1 by hardware upon the entrance into an ISR when a multiply or divide ALU operation was interrupted before completion Depending on the state of the MULIP bit the hardware decides whether a multiplication or division must be continued or not after the end of an interrupt service The MULIP bit is overwritten with the contents of the stacked MULIP flag when RETurn from Interrupt instruction RETI is executed This normally means that the MULIP flag is cleared again after that Note The MULIP flag is a part of the task environment When the ISR does not return to the interrupted multiply divide instruction e g in case of a task scheduler that switches between independent tasks the MULIP flag must be saved as part of the task environment and must be updated accordingly for the new task before this task is ent
51. User s Manual 5 28 V 1 6 2001 08 pae 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Detailed Instruction Set 6 Detailed Instruction Set The following pages of this section contain a detailed description of each instruction in alphabetical order User s Manual 6 1 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set ADD Integer Addition ADD Group Arithmetic Instructions Syntax ADD op1 op2 Source Operand s op1 op2 gt WORD Destination Operand s op1 gt WORD Operation op1 op1 op2 Description Performs a 2 s complement binary addition of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 CPU Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in the word data type Cleared otherwise C Set if a carry is generated from the most significant bit of the word data type Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes ADD Rw data3 08 n 0 2 ADD Rw RWm 00 nm 2 ADD Rw Rw 08 n 11ii 2 ADD Rw Rwj 08 n 10ii 2 ADD mem reg 04 RR MM MM 4 ADD reg
52. V Set if in any cycle of the shift operation a 1 is shifted out of the carry flag Cleared in case of a shift count equal 0 C The carry flag is set according to the last least significant bit shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared otherwise User s Manual 6 8 V 1 6 2001 08 pae e Infineon technologies Encoding Mnemonic ASHR ASHR User s Manual User s Manual C166S V1 SubSystem Rw data4 Rw RWm Format BC n AC nm 6 9 Detailed Instruction Set Bytes 2 2 V 1 6 2001 08 1 fi User s Manual nrineon M a C166S V1 SubSystem Detailed Instruction Set ATOMIC Begin ATOMIC Sequence ATOMIC Group System Control Instructions Syntax ATOMIC op1 Source Operand s op1 gt 2 bit instruction counter Destination Operand s none Operation count op1 1 x op1 x 4 Disable interrupts and Class A traps DO WHILE count z 0 AND Class B Trap Condition z TRUE Next Instruction count lt count 1 END WHILE count 0 Enable interrupts and traps Description Causes standard and PEC interrupts and class A hardware traps to be disabled for a specified number of instructions The ATOMIC instruction becomes immediately active No NOPs are required for normal ATOMIC execution Depending on the value of op1 the period of validity of the ATOMIC sequence extends over the sequence of the ne
53. although there is some overhead for changing the registers and keeping appropriate tables Switching between predefined address windows automatically selects the bus mode that is associated with the respective window Predefined address windows allow the use of different bus modes without any overhead but restrict the number of windows to the number of BUSCONs However as BUSCONO controls all address areas that are not covered by the other BUSCONS there may be gaps between windows that use the bus mode of BUSCONO PORT will output the intra segment address when any of the BUSCON registers selects a demultiplexed bus mode even if the current bus cycle uses a multiplexed bus mode This allows an external address decoder to be connected to PORT1 only while using it for all kinds of bus cycles Note Never change the configuration for an address area that currently supplies the instruction stream Due to internal pipelining it is very difficult to determine the first instruction fetch that will use the new configuration Only change the configuration for address areas that are not currently accessed This applies to BUSCON registers as well as to ADDRSEL registers The usage of the BUSCON ADDRSEL registers is controlled via the addresses issued When an access code fetch or data is initiated the generated physical address determines whether the access is made internally uses one of the address windows defined by ADDRSEL4 1 or uses the d
54. compared to the C166 full custom cores C166S has 5 main units that are listed below All these units have been optimized to achieve maximum performance and flexibility High Performance Instruction Fetch Unit IFU High bandwidth fetch interface Instruction FIFO First In First Out Buffer High performance branch call and loop processing with instruction flow prediction Injection Exception Handler Handling of interrupt requests Handling of hardware failures Instruction PIPeline IPIP User s Manual 3 1 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Central Processing Unit 4 stage execution pipeline 7 Address and Data Unit ADU 16 bit arithmetic unit for address generation 8 Arithmetic and Logic Unit ALU 8 bit and 16 bit arithmetic unit 16 bit barrel shifter Multiplication and division unit 8 bit and 16 bit logic unit Bit manipulation unit User s Manual 3 2 V 1 6 2001 08 1 fi User s Manual a C166S V1 SubSystem Central Processing Unit 3 1 Register Description Format The C166S contains a set of Special Function Registers SFRs and Extended Special Function Registers ESFRs that are described in the respective chapter of this manual The example below shows how to interpret the format and notation that are used to describe SFRs and ESFRs A word register looks like this
55. decrement or increment the indirect address pointers GPR contents by 2 or 1 referring to words or bytes In each case one of the four DPP registers is used to specify physical 24 bit addresses Any word or byte data within the entire memory space can be addressed indirectly Note Indirect addressing may be used with the DPP overriding mechanism EXTP R and EXTS R Some instructions use only the lowest 4 word GPRs R3 RO as indirect address pointers which are then specified via short 2 bit addresses Physical addresses are generated from indirect address pointers using the following algorithm 1 Calculate the physical address of the word GPR which is used as indirect address pointer using the specified short address Rw and GPR Address z CP 2 Short Address 2 If required pre decrement indirect address pointer Rw by the data type dependent value A 1 for byte operations A 2 for word operations before the long 16 bit address is generated GPR Address GPR Address A optional step 3 Calculate the long 16 bit address by adding a constant value Rw const16 if selected to the contents of the indirect address pointer Long Address GPR Pointer Constant Constant is optional 4 Calculate the physical 24 bit address using the resulting long address and the corresponding DPP register contents see long mem addressing modes Physical Address DPPi Page offset 5 If required post in
56. derived from the bus control registers BUSCONA BUSCONO can be output on 5 pins of Port 6 The number of chip select signals is selected via conf rst cssel i 1 0 CSSEL during reset User s Manual 7 13 V 1 6 2001 08 e Infineon technologies The table below summarizes the alternate functions of Port 6 depending on the number User s Manual C166S V1 SubSystem Parallel Ports of selected chip select lines coded via bitfield CSSEL Table 7 3 Alternate Functions of Port 6 Port 6 Pin Altern Function Altern Function Altern Function Altern Function CSSEL 10 CSSEL 01 CSSEL 00 CSSEL 11 P6 0 Gen purpose IO Chip select CSO Chip select CSO Chip select CSO P6 1 Gen purpose IO Chip select CS1 Chip select CS1 Chip select CS1 P6 2 Gen purpose IO Gen purpose IO Chip select CS2 Chip select CS2 P6 3 Gen purpose IO Gen purpose IO Gen purpose IO Chip select CS3 P6 4 Gen purpose IO Gen purpose IO Gen purpose IO Chip select CS4 P6 5 Gen purpose IO Gen purpose IO Gen purpose IO Gen purpose IO P6 6 Gen purpose IO Gen purpose IO Gen purpose IO Gen purpose IO P6 7 Gen purpose IO Gen purpose IO Gen purpose IO Gen purpose lO Alternate Function General Purpose Input Output Figure 7 8 Port 6 lO and Alternate Functions Note The chip select lines of Port 6 should have product specific an internal weak pull up device This device s
57. ie opX is used as pointer to the actual operand The following operands notation will also be used in the operational description CP CSP IP MD MDL MDH PSW SP SYSCON C V SGTDIS count tmp 0 1 2 Context Pointer Code Segment Pointer Instruction Pointer Multiply Divide register 32 bits wide consists of MDH and MDL Multiply Divide Low and High registers each 16 bit wide Program Status Word System Stack Pointer SYSCON Configuration register Carry condition flag in the PSW register Overflow condition flag in the PSW register Segmentation Disable bit in the SYSCON register Temporary variable for an intermediate storage of the number of shift or rotate cycles which remain to complete the shift or rotate operation Temporary variable for an intermediate result Constant values due to the data format of the specified operation Data Types This part specifies the particular data type according to the instruction Basically the following data types are possible BIT BYTE WORD User s Manual 5 22 V 1 6 2001 08 e Infineon technologies Only instructions which extend byte data to word change data type Note that the data types mentioned in this subsection do not cover accesses to indirect address pointers or to the system stack These accesses are always performed with word data Moreover no data type is specified for System Control Instructions and for those of the branch instructio
58. on IP events only simple monitor mode or JTAG based debugging through instruction injection The C166S OCDS is controlled by the debugger through a set of registers accessible from the JTAG interface The OCDS also receives informations such as IP data status from the core for monitoring the activity and generating triggers Finally the OCDS interacts with the core through a break interface to suspend program execution and an injection interface to allow execution of OCDS generated instructions 2 2 7 Core Control Block CCB The Core Control Block supports all central control tasks and all subsystem specific features The following typical sub modules are implemented in this unit Reset Control RC The reset function is controlled by the reset control unit The reset block resets the subsystem itself and provides three reset outputs to reset the complete c166S based system according to the reset source Hardware Reset The system enters the reset state immediately asynchronous to its clock e Software Reset synchronous to the CPU clock Watchdog Timer Reset synchronous to the CPU clock 1 Debugger refers to the tool connected to the emulator and more specifically to the OCDS via the JTAG and which manages the emulation debugging task User s Manual 2 12 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem System Overview Power Saving Control PSC The id
59. stack location register banks etc If they are not followed by a read from the same address the CPU will not recognize the need of holding the pipeline while write is finished So the effect of this operation will not be seen immediately within next instruction After writing to a memory location MEMLOC non critical instruction s must follow before the first instruction which will be affected by that write operation I n Writing to MEMLOC ntl Non critical instruction s MEMLoc still holds the old value Enya Any instruction new MEMLOC VALUE is already effective Non critical instruction means instruction which execution does not depend on the writing to MEMLOC The most non critical is NOP instruction as doing nothing The programmer has to be always aware not to place some critical instruction within that gap of one or more machine cycles while the write operation still has no effect Also the delays caused by pipeline conflicts can be used for other instructions in order to optimize performance 3 8 1 2 Specific cases with core registers When writing to an internal core register the time needed before the new value becomes effective depends only on the pipeline This time is usually one as exception two machine cycles what means one or two non critical instructions to be executed Below are described some specific situations when changing important system registers User s Manual 3 81 V 1 6
60. the I O ports and the on chip peripherals of the C1665 are controlled via a number of SFRs These SFRs are arranged within two 512 Byte areas The first register block the SFR area is located in the 512 Bytes above the DPRAM 00 FFFFy 00 FEO0y The second register block the ESFR area is located in the 512 Bytes below the DPRAM 00 F1FFj4 00 F000 SFRs can be addressed via indirect and long 16 bit addressing modes Using an 8 bit offset together with an implicit base address makes it possible to address word SFRs and their respective low bytes However this does not work for the respective high bytes User s Manual 4 5 V 1 6 2001 08 7 fi User s Manual nfineon technologies C166S V1 SubSystem Memory Organization OO FFFFg OO FFFF RAM SER Area 00 F000 Data Page 3 00 E000 External 00 C000 Data Page 2 00 8000 Data Page 1 Internal Program 00 4000 Memory Data Page 0 00 0000 System Segment 0 64KByte Figure 4 3 DPRAM and SFR Areas Note High byte accesses of SFRs using the 8 bit offset addressing mode are not possible Note Writing to any byte of an SFR causes the non addressed complementary byte to be cleared Note GPRs can be accessed using the 8 bit offset addressing mode but the GPRs are not mapped into the SFR and ESFR memory area Using the corresponding long address instead of a GPR access executes an internal peripheral bus access The upper half o
61. whose priority lies between the Class A trap and the reset function This allows the debugger to interrupt hardware traps and hardware interrupts Exception Condition Trap Trap Trap Trap Flag Vector Number Priority Reset Functions Hardware Reset RESET 001 IV Software Reset RESET 001 IV Watchdog Timer Overflow RESET 004 IV Debug Trap DEBUG DEBTRAP 084 Hl User s Manual 3 28 V 1 6 2001 08 1 fi User s Manual nrineon M s C166S V1 SubSystem Central Processing Unit Exception Condition Trap Trap Trap Trap Flag Vector Number Priority Class A Hardware Traps Non Maskable Interrupt NMI NMITRAP 02H 11 3 STacK OverFlow STKOF STOTRAP 4044 11 2 STacK UnderFlow STKUF STUTRAP 064 11 1 SOFTware BReaK SOFTBRK SBRKTRAP 1084 11 0 Class B Hardware Traps UNDefined OPCode UNDOPC BTRAP OAH PRoTection FauLT PRTFLT BTRAP OA ILLegal word Operand Access ILLOPA BTRAP OAH ILLegal INstruction Access ILLINA BTRAP OAH ILLegal external BUS access ILLBUS BTRAP OAH Class A Trap Class A traps are generated by the high priority system NMI or by special CPU events such as a software break or a stack overflow or underflow event Class A traps are not used to indicate hardware failures After a Class A event a dedicated service routine is called to react to the events Each Class A trap has its own vector location in the vector table After finishing the service routine the remai
62. 0 1 030C 0 2 96 0 0 0207 02084 030Dy 1200 Baud 0 0 0 0 0619 0 1 96 0 0 0410 0411 061A Note CON FDE must be 0 to achieve the bauarates in the table above The deviation errors given in the table above are rounded Using a bauarate crystal will provide correct baudrates without deviation errors Using the Fractional Divider When the fractional divider is selected the input clock fp y for the baudrate timer is derived from the module clock f by a programmable divider If CON FDE is set the fractional divider is activated It divides f i by a fraction of n 512 for any value of n from 0 to 511 If n 0 the divider ratio is 1 which means that fpiyv fo In general the fractional divider allows the baudrate to be programmed with much more accuracy than with the two fixed prescaler divider stages BG represents the contents of the reload register BG BR VALUE taken as an unsigned 13 bit integer FDV represents the contents of the fractional divider register FD VALUE taken as an unsigned 9 bit integer User s Manual 10 20 V 1 6 2001 08 _ e Infineon technologies User s Manual C166S V1 SubSystem Asynchronous Synchronous Serial Interface ASC Table 10 3 Asynchronous Baudrate Formulas using the Fractional Input Clock Divider FDE BRS BG FDV Formula 1 1 8191 1 511 f _ FDV clk pale esi 46x BGA 0 folk Baudrate 16x BG 1
63. 1 before being captured User s Manual 12 35 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem General Purpose Timer Unit Field Bits Typ Description CI 13 12 rw Register CAPREL Capture Trigger Selection depending on bit CT3 00 Capture disabled 01 Positive transition rising edge on CAPIN or any transition on T3IN 10 Negative transition falling edge on CAPIN or any transition on T3EUD 11 Any transition rising or falling edge on CAPIN or any transition on T3IN or T3EUD T5CLR 14 rw Timer 5 Clear Bit 0 Timer 5 is not cleared on a capture event 1 Timer 5 is cleared on a capture event T5SC 15 rw Timer 5 Capture Mode Enable 0 Capture into register CAPREL disabled 1 Capture into register CAPREL enabled Count Direction Control for Auxiliary Timer The count direction of the auxiliary timer can be controlled in the same way as for core Timer T6 The description and the table apply accordingly Timer T5 in Timer Mode or Gated Timer Mode When auxiliary Timer T5 is programmed to Timer or Gated Timer Mode its operation is the same as described for core Timer T6 The descriptions figures and tables apply accordingly with three exceptions There is no T5OUT line for T5 There is no T5OFL line for T5 Overflow underflow monitoring is not supported no bit T5OTL User s Manual 12 36 V 1 6 2001 08 1 fi User s Manual
64. 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem General Purpose Timer Unit 12 3 Functional Description of Timer Block 2 Timer Block 2 includes the two Timers T5 referred to as the auxiliary timer and T6 referred to as the core timer and the 16 bit capture reload register CAPREL Each timer of Block 2 is controlled by a separate control register TxCON Each timer has an input line TxIN associated with it which serves as the gate control in Gated Timer Mode or as the count input in Counter Mode The count direction up down may be programmed via software or may be dynamically altered by a signal at an external control input line An overflow underflow of core Timer T6 is indicated by bit T6OTL whose state may be output on related line TGOUT and on line TeOFL Core Timer T6 may be reloaded with the contents of CAPREL The toggle bit also supports the concatenation of T6 with auxiliary Timer T5 while concatenation of T6 with other timers is provided through line TeOUT Triggered by an external signal the contents of T5 can be captured into register CAPREL and T5 may optionally be cleared Both timer T6 and T5 can count up or down and the current timer value can be read or modified by the CPU in the non bitaddressable SFRs T6 and T5 From a programmer s point of view the GPT2 block is composed of a set of SFRs as summarized below Those registers which are not part of the GPT2 block are shaded Data Registers Con
65. 102 Product Interrupt Request 102 IRQ1021C 01D8y 76H irq_i 103 Product Interrupt Request 103 IRQ103IC 01DCy 77H irq_i 104 Product Interrupt Request 104 IRQ104IC 01E0 78 irq_i 105 Product Interrupt Request 105 IRQ1051C 01E4 79 irq_i 106 Product Interrupt Request 106 IRQ106IC 01E8 7Ay irq_i 107 Product Interrupt Request 107 IRQ1071C 01ECy 7By irq_i 108 Product Interrupt Request 108 IRQ108lIC 01F0 7Cy irq_i 109 Product Interrupt Request 109 IRQ109IC 01F4 7Dy irq_i 110 Product Interrupt Request 110 IRQ1101IC 01F8y 7Ey irq_i 111 Product Interrupt Request 111 IRQ1111C 01FCy 7Fh 1 This signal is part of the general signals interface and is handled by the CPU directly not handled by the interrupt controller 2 User s Manual 4 47 This signals are not part of the subsystem boundary but included in the core macro s interrupt interface V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Memory Organization The following table lists all possible 97 interrupt source entries which are available on product level listed by the interrupt interface signal name Note Depending on the number of interrupt configuration not all entries are available see Page 4 43 Table 4 5 Interrupt Vector Table sorted by signal name Signal Name Source of Interrupt Interrupt Control Ve
66. 39 V 1 6 2001 08 1 fi User s Manual nrineon M os C166S V1 SubSystem Memory Organization Table 4 3 SFR ESFR Table ordered by name cont d Name Physical Type 8 bit Description Reset Address S Value SOTBIC F19Cy ESFR b CE ASCO Transmit Buffer Interrupt 0000y Control Register SOTBUF FEBOy SFR 584 Serial Channel 0 Transmit Buffer 00004 Register WO SOTIC FF6Cy SFR b B6y ASCO Transmit Interrupt Control 0000 Register SP FE12y SFR 09 CPU System Stack Pointer FCOO Register SSCOBR FOB4y ESFR 5Ay SSCO0 Baudrate Register 0000y SSCOCON FFB24 SFR b D9 SSCO Control Register 0000 SSCOEIC FF76y SFR b BBy SSCO Error Interrupt Control 0000 Register SSCOID FFE4 SSCO Identification Register 45xxy SSCOPISEL FOB6 ESFR 5By SSCO Port Input Selection 00004 Register SSCORB FOB2y ESFR 594 SSCO Receive Buffer RO 0000y SSCORIC FF74y SFR b BAy SSCO Receive Interrupt Control 0000 Register SSCOTB FOBOy ESFR 584 SSCO Transmit Buffer WO 0000y SSCOTIC FF72y SFR b B94 SSCO Transmit Interrupt Control 0000 Register STKOV FE14 SFR OA CPU Stack Overflow Pointer FA00 Register STKUN FE16y SFR OB CPU Stack Underflow Pointer FCOO Register SYSCON FF12y SFR b 894 CPU System Configuration XXXXH Register T2 FE40y SFR 20 GPT Timer 2 Register 0000 T2CON FF40y SFR b AO0Oy GPT Timer 2 Control Register
67. 4 Tm 5 In case of a branch to a 32 bit target instruction which is not aligned to a 32 bit address one additional machine cycle T1 T2 is required Table 3 4 shows a standard conditional branch branch taken instruction pipeline assuming a fast local memory 0 1 waitstates Table 3 4 Conditional branches LM Bus 0 1 waitstate Clock Cycle TY To T Ta Ty Ta Ty Ta Ty Ta Ty Ta Address lat Data 32bit lat lat FETCH In ln 1 In 2 li lta branch DECODE In 1 In In 1 In 1 s lt branch branch EXECUTE In 2 In i In In 1 In 1 branch branch WRITE BACK In 3 In 2 In 1 In ln 1 ln 1 branch branch Machine Cycle Tm Tm 1 Tm 2 Tm 3 Tm 4 Tm 5 User s Manual 3 10 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V1 SubSystem Central Processing Unit Cache Jump Instruction Processing The C166S incorporates a jump cache to optimize conditional jumps which are processed repeatedly within a loop Whenever a jump on cache is taken the extra time to fetch the branch target instruction can be saved and thus the corresponding cache jump instruction in most cases takes only one unconditional branch or two conditional branch machine cycles This performance is achieved by the following mechanism Whenever a cache jump instruction passes through the decode stage of the pipeline for the first time and pro
68. 5 6 XBUS Address Selection Reg Reset value XXXXy 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSADx RGSZx rw rw Field Bits Type Description RGSADx 15 4 rw Address Range Start Address Selection RGSZx 3 0 rw Address Range Size Selection The respective SFR addresses of XADRSx registers can be found in list of SFRs Due to the different range size options address mapping of XPERs is possible only within the first MByte of the total address range if XADRS1 to XADRS4 is used The upper four address lines A23 A20 are set to zero Note that the range start address can be located only on boundaries specified by the selected range size The following table shows the definitions of range size selections and range start addresses for the address selection registers XADRS1 2 3 4 User s Manual 8 37 V 1 6 2001 08 pan User s Manual neon Infineon C1 66S V1 SubSystem The External Bus Interface The address range and address range start definition of XADRS5 and XADRS6 registers is identical to the address selection definition for external devices see Address Window Definition It is thus possible to use the whole address range also for internal memories or peripherals Range Selected Relevant R bits Selected Range Start Address Size Address of RGSAD Relevant R bits of RGSAD RGSZ Range 0000 256 Byte R 0000 RRRR RRRR RRRR 0000 0000 0001 512 Bytes R 0000 RRRR RRR
69. 6 D4 nm 4 MOV Rw RWm 98 nm 2 MOV Rw RWml A8 nm 2 MOV RWm RW 88 nm 2 MOV Rw t data16 Rw C4 nm 4 User s Manual 6 58 V 1 6 2001 08 pae e Infineon technologies MOV MOV MOV MOV MOV MOV MOV MOV MOV User s Manual User s Manual C166S V1 SubSystem Rwml Rw Rw RW Rwy RWm Rwp Rw Rw4 mem mem Rw mem reg reg data16 reg mem B8 nm D8 nm E8 nm C8 nm 84 0n MM MM 94 0n MM MM F6 RR MM MM E6 RR F2 RR MM MM 6 59 Detailed Instruction Set RROD A BR MO MDP V 1 6 2001 08 1 fi User s Manual nrineon M a C166S V1 SubSystem Detailed Instruction Set MOVB Move Data MOVB Group Data Movement Instructions Syntax MOVB op1 op2 Source Operand s op2 gt BYTE Destination Operand s op gt BYTE Operation op1 op2 Description Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1 The contents of the moved data is examined and the flags are updated accordingly CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise Encoding Mnemonic Fo
70. 8 1 Summary of External Bus Modes BTYP External Data Bus Width External Address Bus Mode Encoding 00 8 bit Data Demultiplexed Addresses 0 1 8 bit Data Multiplexed Addresses 10 16 bit Data Demultiplexed Addresses 1 1 16 bit Data Multiplexed Addresses The bus configuration BTYP for the address windows BUSCONA BUSCON 1 is selected via software typically during the initialization of the system The bus configuration BTYP for the default address range BUSCONO is selected via conf rst bustyp i 1 0 during reset provided that the signal conf start external n i is low during reset Otherwise BUSCONO may be programmed via software just like the other BUSCON registers The 16 MByte address space of the C166S is divided into 256 segments of 64 KBytes each The 16 bit intra segment address is output on PORTO When segmentation is disabled only one 64 KByte segment can be used and accessed Otherwise additional address lines may be output on Port 4 addressing up to 16 MByte and or several chip select lines may be used to select different memory banks or peripherals These User s Manual 8 2 V 1 6 2001 08 pae 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem The External Bus Interface functions are selected during reset via bitfields SALSEL and CSSEL of register RPOH respectively 8 2 1 Multiplexed Bus Modes In the multiplexed bus modes the 16 bit intra segment address and
71. 94 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set SUBCB Integer Subtraction with Carry SUBCB Group Arithmetic Instructions Syntax SUBCB op1 op2 Source Operand s op1 op2 gt BYTE Destination Operand s op1 gt BYTE Operation op1 lt opi op2 C Description Performs a 2 s complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destination operand specified by op1 The result is then stored in op1 This instruction can be used to perform multiple precision arithmetic CPU Flags E Z V C N S E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and the previous Z flag was set Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the word data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes SUBCB Rb data3 39 n O 2 SUBCB Rb Rom 31 nm 2 SUBCB Rb Rw 39 n 11ii 2 SUBCB Rb Rwj 39 n 10ii 2 SUBCB mem reg 35 RR MM MM 4 SUBCB reg data8 37 RR xx 4 SUBCB reg mem 33 RR MM MM 4 User s Manual 6 95 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detaile
72. BG folk P 8 x BG 1 8 x Baudrate 1 f f ok BG clk Borel eN 12 x Baudrate BG represents the contents of the reload register BR_VALUE taken as an unsigned 13 bit integers The maximum baudrate that can be achieved in synchronous mode when using a module clock of 60 MHz is 7 5 MBaud User s Manual 10 22 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V1 SubSystem Asynchronous Synchronous Serial Interface ASC 10 3 4 Hardware Error Detection Capabilities To improve the safety of serial data exchange the serial channel ASC provides an error interrupt request flag to indicate the presence of an error and three selectable error status flags in register CON to indicate which error has been detected during reception Upon completion of a reception the error interrupt request line EIR will be activated simultaneously with the receive interrupt request line RIR if one or more of the following conditions are met f the framing error detection enable bit CON FEN is set and any of the expected stop bits is not high the framing error flag CON FE is set indicating that the error interrupt request is due to a framing error Asynchronous Mode only f the parity error detection enable bit CON PEN is set in the modes where a parity bit is received and the parity check on the received data bits proves false the parity error flag CON PE is set indicating that the error interrupt request i
73. Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used CPU Flags E Z V C N lo pops psp E Always cleared Z Set if result equals zero Cleared otherwise V Set if in any cycle of the rotate operation a 1 is shifted out of the carry flag Cleared for a rotate count of zero C The carry flag is set according to the last least significant bit shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared otherwise User s Manual 6 83 V 1 6 2001 08 pae e Infineon technologies Encoding Mnemonic ROR ROR User s Manual User s Manual C166S V1 SubSystem Rw data4 Rw RWm Format 3C sin 2C nm 6 84 Detailed Instruction Set Bytes V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Detailed Instruction Set SCXT Switch Context SCXT Group System Stack Instructions Syntax SCXT op1 op2 Source Operand s op1 op2 gt WORD Destination Operand s op1 gt WORD Operation tmp1 op1 tmp2 op2 SP SP 2 SP tmp1 op1 tmp2 Description Switches contexts of any register Switching context is a push and load operation The contents of the register specified by the first operand op1 are pushed onto the stack That register is then loaded with the value specified by the second ope
74. Channel ASC User s Manual 10 14 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Asynchronous Synchronous Serial Interface ASC 10 3 2 1 Synchronous Transmission Synchronous transmission begins within four state times after data has been loaded into TBUF provided that CON R is set and CON REN is cleared half duplex no reception Exception in loopback mode bit CON LB set CON REN must be set for reception of the transmitted byte Data transmission is double buffered When the transmitter is idle the transmit data loaded into TBUF is immediately moved to the transmit shift register thus freeing TBUF for more data This is indicated by the transmit Buffer interrupt request line TBIR being activated TBUF may now be loaded with the next data while transmission of the previous continoues The data bits are transmitted synchronous with the shift clock After the bit time for the eighth data bit both the TXD and RXD lines will go high the transmit interrupt request line TIR is activated and serial data transmission stops Note Pin TXD must be configured for alternate data output in order to provide the shift clock Pin RXD must also be configured for output during transmission 10 3 2 2 Synchronous Reception Synchronous reception is initiated by setting bit CON REN If bit CON Ri is set the data applied at RXD is clocked into the receive shift register synchronous to the clock that is outpu
75. DP1L DP1H 7 7 DP4 7 10 7 13 DPPx Register 3 56 DSTPx Register 3 34 E Early chip select 8 14 Early WR control 8 18 Enable XBUS peripherals 8 36 Error Detection ASCO 10 23 ESFR Table ordered by address 4 12 ESFR Table ordered by name 4 32 External Bus 2 8 Bus Characteristics 8 16 8 20 Bus Idle State 8 30 Bus Modes 8 2 8 11 G GPR 4 10 GPT1 12 3 GPT2 12 26 H Hold State 8 33 l ID Control 2 13 Idle State Bus 8 30 INC 3 36 3 37 Instruction Timing 3 87 Interface External Bus 8 1 User s Manual Keyword Index Internal Bus 2 8 Interrrupt Control Register 3 21 3 44 Interrupt System 2 6 3 19 Interrupt Sources 4 43 4 48 IP Register 3 15 J JTAG 2 12 L Latched chip select 8 14 M Master mode External bus 8 32 MDC Register 3 73 MDH Register 3 72 MDL Register 3 72 Memory External 4 8 ROM 4 4 Tristate time 8 17 Memory Cycle Time 8 17 Multiplexed Bus 8 3 N NMI 3 18 3 29 O OCDS 2 12 ONES Register 3 89 P POL POH 7 3 P1L P1H 7 7 P4 7 10 7 13 PEC 3 32 PEC Control Register 3 36 PEC Pointer Address Handling 3 33 PEC Transfer Count 3 37 PECCx Register 3 36 14 2 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem PECSNXx Register 3 35 Peripheral Summary 2 8 Peripheral Event Controller 3 32 Pipeline Effects 3 80 PLEV 3 36 Power Saving Control 2 13 Protected Bits 3 71 PSW 3 22 PSW Register 3 76 R Read Write De
76. GPR to indirect memory MOVB Rw Rw Move indirect byte memory to indirect memory MOVB Rw Rw Move indirect byte memory to indirect memory and 2 post increment destination pointer by 1 MOVB Rw Rw Move indirect byte memory to indirect memory and 2 post increment source pointer by 1 MOVB Rb Move indirect byte memory by base plus constant to 4 Rw data16 direct GPR MOVB Rw data16 Move direct byte GPR to indirect memory by base plus 4 Rb constant MOVB Rw mem Move direct byte memory to indirect memory 4 MOVB mem Rw Move indirect byte memory to direct memory 4 MOVB reg mem Move direct byte memory to direct register 4 MOVB mem reg Move direct byte register to direct memory 4 MOVBS Rw Rb Move direct byte GPR with sign extension to direct 2 word GPR MOVBS reg mem Move direct byte memory with sign extension to direct 4 word register MOVBS mem reg Move direct byte register with sign extension to direct 4 word memory User s Manual 5 13 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary cont d Mnemonic Description Bytes Data Movement cont d MOVBZ Rw Rb Move direct byte GPR with zero extension to direct 2 word GPR MOVBZ reg mem Move direct byte memory with zero extension to direct 4 word register MOVBZ mem reg Move direct byte register with zero extension to direct 4 word memory
77. IRQ41 Interrupt Control Register 0000 F17Ej IRQ15IC ESFR b BFy IRQ15 Interrupt Control Register 0000 F180y EOPIC ESFR b COy End of PEC Transfer Interrupt 00004 Control Register F182y IRQ421C ESFR b C1y IRQ42 Interrupt Control Register 00004 F184y IRQ61IC ESFR b C2y IRQ61 Interrupt Control Register 0000 F186y IRQ36IC ESFR b C34 IRQ36 Interrupt Control Register 0000 F188H IRQ471C ESFR b C44 IRQ47 Interrupt Control Register 0000 F18A IRQ43IC ESFR b C5 IRQ43 Interrupt Control Register 00004 F18Cy IRQ62IC ESFR b C64 IRQ62 Interrupt Control Register 0000 F18Ey IRQ371C ESFR b C74 IRQ37 Interrupt Control Register 0000 F190y IRQ45IC ESFR b C8 IRQ45 Interrupt Control Register 0000 F192 IRQ44IC ESFR b C94 IRQ44 Interrupt Control Register 0000 F194 IRQ63IC ESFR b CA IRQ63 Interrupt Control Register 00004 F196y IRQ38IC ESFR b CBy IRQ38 Interrupt Control Register 0000 F198 IRQ46IC ESFR b CC IRQ46 Interrupt Control Register 00004 User s Manual 4 19 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value F19Ay WDTIC ESFR b CDy Watchdog Timer Interrupt Control 0000 Register F19Cy SOTBIC ESFR b CEy ASCO Transmit Buffer I
78. IRQ76IC 0170y 5Cy irq_i 77 Product Interrupt Request 77 IRQ77IC 0174 5Dy irq_i 78 Product Interrupt Request 78 IRQ78IC 0178 5Ey irq_i 79 Product Interrupt Request 79 IRQ79IC 017Cy 5Fh irq_i 80 Product Interrupt Request 80 IRQ50IC 0180 604 irq_i 81 Product Interrupt Request 81 IRQ81IC 0184 61h irq_i 82 Product Interrupt Request 82 IRQ82IC 01884 624 irq_i 83 Product Interrupt Request 83 IRQ83IC 018Cy 63H irq_i 84 Product Interrupt Request 84 IRQ84IC 0190 644 irq_i 85 Product Interrupt Request 85 IRQ85IC 0194 65H irq_i 86 Product Interrupt Request 86 IRQ86IC 01984 664 irq_i 87 Product Interrupt Request 87 IRQ87IC 019Cy 67H irq_i 88 Product Interrupt Request 88 IRQ88IC 01A0 68H irq_i 89 Product Interrupt Request 89 IRQ89IC 01A4 69h irq_i 90 Product Interrupt Request 90 IRQ90IC 01A8 6A irq_i 91 Product Interrupt Request 91 IRQ91IC 01ACy 6By irq_i 92 Product Interrupt Request 92 IRQ92IC 01B0y 6Cy irq_i 93 Product Interrupt Request 93 IRQ93IC 01B4 y 6Dy irq_i 94 Product Interrupt Request 94 IRQ94IC 01B8 6Ey irq_i 95 Product Interrupt Request 95 IRQ95IC 01BCy 6Fy irq_i 96 Product Interrupt Request 96 IRQ96IC 01C0y 70H irq_i 97 Product Interrupt Request 97 IRQ97IC 01C4 71h User s Manual 4 50 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 5 Interrupt Vector Table cont d sorted by signal name S
79. M a C166S V1 SubSystem Detailed Instruction Set BFLDH Bit Field High Byte BFLDH Group Boolean Bit Manipulation Instructions Syntax BFLDH op1 op2 op3 Source Operand s op1 gt WORD op2 op3 gt BYTE Destination Operand s op1 gt WORD Operation count 0 DO WHILE count lt 8 IF op2 count 1 op1 count 8 op3 count ENDIF count count 1 END WHILE Description Replaces those bits in the high byte of the destination word operand op1 which are selected by an 1 in the mask specified by op2 with the bits at the corresponding positions in op3 CPU Flags E Z V C N E Always cleared Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes BFLDH bitoffo mask8 data8 1A QQ 4 User s Manual 6 14 V 1 6 2001 08 1 fi User s Manual nrineon M a C166S V1 SubSystem Detailed Instruction Set BFLDL Bit Field Low Byte BFLDL Group Boolean Bit Manipulation Instructions Syntax BFLDL op1 op2 op3 Source Operand s op1 gt WORD op2 op3 gt BYTE Destination Operand s op1 gt WORD Operation count 0 DO WHILE count 8 IF op2 count 1 op1 count lt op3 count ENDIF count count 1 END WHILE Description Replaces those bits in the low byte of the destination word operand op1 which are
80. Not affected C Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise Encoding Mnemonic Format Bytes MOVBS Rw Rom DO mn 2 MOVBS mem reg D5 RR MM MM 4 MOVBS reg mem D2 RR MM MM 4 User s Manual 6 62 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem MOVBZ Move Byte Zero Extend Group Data Movement Instructions Syntax MOVBZ op1 op2 Source Operand s op2 gt BYTE Destination Operand s op1 gt WORD Operation low byte op1 op2 high byte op1 00H Description Detailed Instruction Set MOVBZ Moves and zero extends the contents of the source byte operand specified by op2 to the word location specified by the destination operand op1 The contents of the moved data is examined and the flags are updated accordingly CPU Flags E Z V C N E Always cleared Z Set if the value of the source byte operand op2 equals zero Cleared otherwise V Not affected e Not affected N Always cleared Encoding Mnemonic Format MOVBZ Rw Rom CO mn MOVBZ mem reg C5 RR MM MM MOVBZ reg mem C2 RR MM MM User s Manual 6 63 Bytes V 1 6 2001 08 1 fi User s Manual o C166S V1 SubSystem Detailed Instruction Set MUL Signed Multiplication MUL Group Arithmetic Instructions Syntax MUL op1 op2 Source Operand s op1 op2 gt WORD Destination Operand s MD gt DOUBLEWORD Operation MD
81. PEC Pointer PECSN7 PEC Pointer 7 Segment Address Reg PEC Pointer PECSN8 PEC Pointer 8 Segment Address Reg PEC Pointer PECSN PEC Pointer Segment Address Reg PEC Pointer PECSN15 PEC Pointer 15 Segment Address Reg PEC Pointer PECCO PEC Channel 0 Control Register PEC Control PECC PEC Channel Control Register PEC Control PECC7 PEC Channel 7 Control Register PEC Control PECC8 PEC Channel 8 Control Register PEC Control PECC PEC Channel Control Register PEC Control PECC15 PEC Channel 15 Control Register PEC Control IRQOIC Interrupt O Control Register Arbitration Control IRQ6e3IC Interrupt 63 Control Register Arbitration Control IRQ641C Interrupt 64 Control Register Arbitration Control IRQ651C Interrupt 65 Control Register Arbitration Control IRQ1111C Interrupt 111 Control Register Arbitration Control 1 The implementation and assignment of these Interrupt PEC Control Register is product specific User s Manual 3 95 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Central Processing Unit User s Manual 3 96 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Memory Organization 4 Memory Organization The memory space of the C166S has a Von Neumann architecture This means that code and data are accessed within the same linear address space All of the physically separated memory areas including inte
82. SRVWDT Once either an EINIT or a SRVWDT has been executed the DISWDT instruction will have no effect If the WDTCTL bit is set the DISWDT instruction can always be executed regardless of the execution of EINIT or SRVWDT To insure that this instruction is not accidentally executed it is implemented as a protected instruction CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes DISWDT A5 5A A5 A5 4 User s Manual 6 33 V 1 6 2001 08 1 fi User s Manual nrineon M a C166S V1 SubSystem Detailed Instruction Set DIV 16 by 16 Signed Division DIV Group Arithmetic Instructions Syntax DIV op1 Source Operand s op1 gt WORD MDL gt WORD Destination Operand s MD gt DOUBLEWORD Operation MDL lt MDL op1 MDH lt MDL mod op1 Description Performs a signed 16 bit by 16 bit division of the low order word stored in the MD register by the source word operand op1 The signed quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH CPU Flags E Z V C N o j tj t po E Always cleared Z Set if quotient stored in the MDL register equals zero Cleared otherwise Undefined if the V flag is set V Set if an arithmetic overflow occurred i e the quotient cannot be represented in a word data type or if the divisor op1 w
83. Set Condition Test Description Condition Code Code Number c Mnemonic cc cc SGT Zv N V 0 Signed greater than Ay cc_NET ZvE 0 Not equal AND not end of table 14 Condition Flags This part reflects the state of the N C V Z and E flags in the PSW register which is the state after execution of the corresponding instruction except if the PSW register itself was specified as the destination operand of that instruction see Note The resulting state of the flags is represented by symbols as follows d The flag is set due to the following standard rules for the corresponding flag Il Il Il Il O O Il O MNN lt lt OOo 2 2 Il Il O Il mb MSB of the result is set MSB of the result is not set Carry occurred during operation No Carry occurred during operation Arithmetic Overflow occurred during operation No Arithmetic Overflow occurred during operation Result equals zero Result does not equal zero Source operand represents the lowest negative number either 8000h for word data or 80h for byte data Source operand does not represent the lowest negative number for the specified data type 9 The flag is set due to rules which deviate from the described standard For more details see instruction pages below or the ALU status flags description V The flag is not affected by the operation O The flag is cleared by the operation NOR The flag contains the logical NOR
84. T3Mz 111g is chosen an interrupt request on TSIRQ is generated For Rotation Detection Mode an interrupt is generated each time the count direction of Timer T3 changes For Edge Detection Mode an interrupt is generated each time a count action for Timer T3 occurs Count direction changes in the count direction and count requests are monitored by status bits T3RDIR T3ICHDIR and T3EDGE in register T3CON T3 is modified automatically according to the speed and direction of the incremental encoder Therefore the contents of Timer T3 always represents the encoder s current position Table 12 5 Core Timer T3 Incremental Interface Mode Input Edge Selection T3I Triggering Edge for Counter Increment Decrement 000 None Counter T3 stops 001 Any transition rising or falling edge on T3IN 010 Any transition rising or falling edge on T3EUD 011 Any transition rising or falling edge on any T3 input T3IN or T3EUD 1XX Reserved Do not use this combination User s Manual 12 13 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit The incremental encoder can be connected directly to the microcontroller without external interface logic In a standard system however comparators will be employed to convert the encoder s differential outputs such as A A to digital signals such as A in Figure 12 8 This greatly increases noise immunity Note The
85. This is particularly advantageous in table searching Saving of system state is automatically performed on the internal system stack avoiding the use of instructions to preserve state upon entry and exit of interrupt or trap routines Call instructions push the value of the IP on the system stack and require the same execution time as branch instructions Instructions have also been provided to support indirect branch and call instructions This supports implementation of multiple CASE statement branching in assembler macros and high level languages User s Manual 2 4 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem System Overview 2 1 4 Consistent and Optimized Instruction Formats To obtain optimum performance in a pipelined design an instruction set has been designed which incorporates concepts from Reduced Instruction Set Computing RISC These concepts primarily allow fast decoding of the instructions and operands while reducing pipeline holds These concepts however do not preclude the use of complex instructions which are required by microcontroller users The following goals were used to design the instruction set 1 Provide powerful instructions to perform operations which currently require sequences of instructions and are frequently used Avoid transfer into and out of temporary registers such as accumulators and carry bits Perform tasks in parallel such as saving state upon entry
86. UU RH3 CP 7 F7y 7H General Purpose byte Register RL7 UU RL4 CP 8 F8 84 General Purpose byte Register RL8 UU RH4 CP 9 F9 9 General Purpose byte Register RL9 UU RL5 CP 410 FA Ay General Purpose byte Register RL10 UU RH5 CP 11 FB By General Purpose byte Register RL11 UU RL6 CP 12 FC Cy General Purpose byte Register RL12 UU RH6 CP 13 FD Dy General Purpose byte Register RL13 UU HL7 CP 14 FE Ey General Purpose byte Register RL14 UU RH7 CP 15 FF Fr General Purpose byte Register RL15 UU User s Manual 3 92 V 1 6 2001 08 1 fi User s Manual a C166S V1 SubSystem Central Processing Unit 3 10 2 Core Special Function Registers Ordered by Name The following table lists all CSFRs in alphabetical order Bit addressable CSFRs are marked with the letter b in column Name CSFRs within the Extended CSFR Space ECSFRs are marked with the letter E in column 8 Bit Address Name Physical 8 Bit Description Reset Address Address Value CP FE10y 08H Context Pointer FCOOy CPUID FOOCy E 064 CPU Identification Register adi CSP FEO8y 044 Code Segment Pointer 00004 8 bits not directly writable DPPO FEO0y 00H Data Page Pointer O 10 bits 0000y DPP1 FE02y 01H Data Page Pointer 1 10 bits 0001 y DPP2 FE044 024 Data Page Pointer 2 10 bits 00024 DPP3 FEO6 03h Data Page Pointer 3 10 bits 0003
87. XX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SALSEL CSSEL WRC rh r rh Note RPOH cannot be changed directly via software but rather allows the current configuration to be checked Bitfields CLKCFG SALSEL and CSSEL may be reconfigured via register RSTCON User s Manual 8 29 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface Bit Function WRC Write Configuration 0 Pins WR and BHE operate as WRL and WRH signals 1 Pins WR and BHE operate as WR and BHE signals CSSEL Chip Select Line Selection Number of active CS outputs 00 3CSlines CS2 CS0 01 2 CS lines CS1 CS0 10 NoCSlinesatall 11 4 CS lines CS3 CS0 Default without put downs SALSEL Segment Address Line Selection Nr of active segment addr outputs 00 4 bit segment address A19 A16 01 No segment address lines at all 10 6 bit segment address A21 A16 11 2 bit segment address A17 A16 Default without put downs Precautions and Hints The external bus interface is enabled as long as at least one of the BUSCON registers has its BUSACT bit set e PORT1 will output the intra segment address as long as at least one of the BUSCON registers selects a demultiplexed external bus even for multiplexed bus cycles e The address windows defined via registers ADDRSELx may overlap internal address areas Internal accesses
88. and PEC interrupts and class A hardware traps are locked The EXTS instruction becomes immediately active such that no additional NOPs are required For any long mem or indirect address in an EXTS instruction sequence the value of op1 determines the 8 bit segment address bits A23 A16 valid for the corresponding data access The long or indirect address itself represents the 16 bit segment offset address bits A15 A0 The value of op2 defines the length of the effected instruction sequence CPU Flags E Z V C N poppe E Not affected Z Not affected V Not affected C Not affected N Not affected User s Manual 6 44 V 1 6 2001 08 pae e Infineon technologies User s Manual C166S V1 SubSystem Encoding Mnemonic EXTS seg irang2 EXTS Rwy irang2 User s Manual Detailed Instruction Set Format Bytes D7 00 0 ss 00 4 DC 00 m 2 6 45 V 1 6 2001 08 1 fi User s Manual nrineon M os C166S V1 SubSystem Detailed Instruction Set EXTSR Begin EXTended Segment and Register Sequence EXTSR Group System Control Instructions Syntax EXTSR op1 op2 Source Operand s op1 gt segment number op2 gt 2 bit instruction counter Destination Operand s none Operation count op2 1 lt op2 lt 4 Disable interrupts and Class A traps Data Segment lt 0op1 SFR range Extended DO WHILE count z 0 AND Class B Trap Condition z TRUE Next Instruction count l
89. and PEC data transfers Data paging is performed by concatenating the lower 14 bits of an indirect or direct long 16 bit address with the contents of the DDP register selected by the upper 2 bits of the 16 bit address The contents of the selected DPP register specify one of the 1024 possible data pages This data page base address together with the 14 bit page offset forms the physical 24 bit address 16 Bit Data Address 1514 0 seletis DPP FF 0000 i 0 y DPP3 11 FE 0000 E DPP2 10 DPP1 01 DPPO 00 B UH Page Page offset Segment Segment offset Figure 3 9 Addressing via the Data Page Pointer After reset the DPP registers select data pages 3 0 within segment O If the user does not want to use any data paging no further action is required User s Manual 3 55 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit Ba eae Pointer 0 SFR FE00 00 Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 o oj o o 0 0 DPPOPN r r r r r r rw DPP1 Data Page Pointer 1 SFR FE02y 01 y Reset value 0001 y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 o oj o o 01 0 DPP1PN r r r r r r rw DPP2 Data Page Pointer 2 SFR FE04 02 Reset value 00024 15 14 13 12 11 10 9 8 7 6 5 4 3
90. are available for the required operands The selected addressing mode combination is mostly specified by the opcode of the corresponding instruction However there are some arithmetic and logical instructions where the addressing mode combination is not specified by the identical opcodes but by particular bits within the operand field The addressing mode entries are made up of three elements Mnemonic Shows accepted operands for the respective instruction Format This part specifies the format of the instructions as it is represented in the assembler listing The Figure 5 1 shows the relation between the instruction format representation of the assembler and the corresponding internal organization of such an instruction format N nibble 4 bits The following symbols are used to describe the instruction formats 00y through FFy Instruction Opcodes 0 1 Constant Values Dos Each of the 4 characters immediately following a colon represents a single bit ll 2 bit short GPR address Rwi SS Code segment number HH 2 bit immediate constant irang2 LGHHE 3 bit immediate constant data3 User s Manual 5 25 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Instruction Set E 5 bit immediate constant data5 C 4 bit condition code specification cc n 4 bit short GPR address Rwn or Rbn m 4 bit short GPR address Rwm or Rbm q 4 bit position of the source bit within
91. been transmitted RIR is activated when the received frame is moved to RBUF While the task of the receive interrupt handler is quite clear the transmitter is serviced by two interrupt handlers This provides advantages for the servicing software For single transfers it is sufficient to use the transmitter interrupt TIR which indicates that all the previously loaded data has been transmitted except for the last bit of an asynchronous frame User s Manual 10 23 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Asynchronous Synchronous Serial Interface ASC For multiple back to back transfers it is necessary to load the following piece of data until the time the last bit of the previous frame has been transmitted In Asynchronous Mode this leaves just one bit time for the handler to respond to the transmitter interrupt request in Synchronous Mode it is completly impossible at all if no FIFO is present Using the transmit buffer interrupt TBIR to reload transmit data provides the time to transmit a complete frame for the service routine as TBUF may be reloaded while the previous data is still being transmitted Asynchronous Mode TBIR Idle Synchronous Mode p Idle Idle RIR RIR RIR Figure 10 11 ASC Interrupt Generation As shown in Figure 10 11 TBIR is an early trigger for the reload routine while TIR indicates the completed transmission Therefore softw
92. bit page address seg8 Immediate 8 bit segment address Branch Condition Codes Gc Symbolically specifiable condition codes cc UC Unconditional cc Z Zero cc NZ Not Zero cc V Overflow cc NV No Overflow cc N Negative cc NN Not Negative cc C Carry cc NC No Carry cc EQ Equal cc NE Not Equal cc ULT Unsigned Less Than cc ULE Unsigned Less Than or Equal cc UGE Unsigned Greater Than or Equal cc UGT Unsigned Greater Than cc SLE Signed Less Than or Equal cc SGE Signed Greater Than or Equal cc SGT Signed Greater Than cc NET Not Equal and Not End of Table User s Manual 5 4 Instruction Set V 1 6 2001 08 Infineon technologies User s Manual C166S V1 SubSystem Instruction Set Mnemonic Addressing ModesBytes Mnemonic Addressing ModesBytes ADDIB Rwn Rwm 10 2 CPL B Rwn 12 ADDC B Rwn Rwi A 2 NEG B ANDIB Rwn Rwi 2 oi Ewn 5 OR B Rwn itdata3 Dlal DIVL SUBIB DIVLU SUBCIB reg data16 4 DIVU XOR B reg mem 4 mei reg 4 D Rwn Rwm 2 ASHR Rwn Rwm 2 CMPD1 2 Rwn data4 2 ROL ROR Rwn data4 2 CMPI1 2 Rwn data16 4 SHL SHR Rwn mem 4 BAND bitaddrZ z bitaddrQ q 4 CMP B Rwn Rwm i 2 BCMP Rwn Rwi 2 BMOV Rwn Rwi Dia BMOVN Rwn data3 lo BOR reg data16 2 14 BXOR reg mem 4 BCLR bitaddrQ q 2 CALLA cc caddr 4 BSET JMPA BFLDH bitoffQ m
93. by software BPS2 12 11 rw Timer Block Prescaler 2 The maximum input frequency 00 Timer Block 2 is fy 4 01 Timer Block 2 is fy 2 10 Timer Block 2 is fy 16 11 Timer Block 2 is fq 8 T6CLR 14 rw Timer 6 Clear Bit 0 Timer 6 is not cleared on a capture event 1 Timer 6 is cleared on a capture event T6SR 15 rw Timer 6 Reload Mode Enable 0 Reload from register CAPREL disabled 1 Reload from register CAPREL enabled 0 13 r Reserved for future use reading returns 0 writing to these bit positions has no effect Additionally the timer input frequency can be modified by T6l for Timer Mode Gated Timer Mode and Counter Mode Timer 6 Run Bit The timer can be started or stopped by software through bit T6R Timer T6 Run Bit Setting bit T6R will start the timer clearing T6R stops the timer User s Manual 12 29 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit In Gated Timer Mode the timer will run only if T6R is set and the gate is active high or low as programmed Note When bit T5RC is set bit TER will also control start and stop auxiliary Timer T5 Count Direction Control The count direction of the core timer can be controlled either by software or by the External Up Down control input line TGEUD These options are selected by bits TeUD and T6UDE in control register TeCON When the up down control is done by softwar
94. by the master or slave operation of the individual device Note The shift direction shown in the figure applies for MSB first operation as well as for LSB first operation When initializing the devices in this configuration one device must be selected for master operation while all other devices must be programmed for slave operation Initialization includes the operating mode of the device s SSC and also the function of the respective port lines User s Manual 11 10 V 1 6 2001 08 C Infineon User s Manual technologies C1 66S V1 SubSystem High Speed Synchronous Serial Interface SSC Master Device 1 Device 2 Slave Shift Register Figure 11 5 SSC Full Duplex Configuration The data output pins MRST of all slave devices are connected together onto the one receive line in the configuration shown in Figure 11 5 During a transfer each slave shifts out data from its shift register There are two ways to avoid collisions on the receive line due to different slave data Only one slave drives the line i e enables the driver of its MRST pin All the other slaves must have their MRST pins programmed as input so only one slave can put its data onto the master s receive line Only receiving data from the master is possible The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave The selected slave then switches its MRST
95. cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes CPL Rwy 91 nO 2 User s Manual 6 31 V 1 6 2001 08 1 fi User s Manual o C166S V1 SubSystem Detailed Instruction Set CPLB Integer One s Complement CPLB Group Arithmetic Instructions Syntax CPLB op1 Source Operand s opi gt BYTE Destination Operand s op BYTE Operation op1 op1 Description Performs a 1 s complement of the source operand specified by op1 The result is stored back into op1 CPU Flags E Z V C N E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes CPLB Rb B1 nO 2 User s Manual 6 32 V 1 6 2001 08 pae 1 fi User s Manual nrineon M os C166S V1 SubSystem Detailed Instruction Set DISWDT Disable Watchdog Timer DISWDT Group System Control Instructions Syntax DISWDT Source Operand s none Destination Operand s none Operation Disable the watchdog timer Description This instruction disables the watchdog timer If the WDTCTL bit is cleared the DISWDT instruction can be executed at any time between the Reset and the first execution of either EINIT or
96. cont d Name Physical Type 8 bit Description Reset Address Addr Value 2 IRQ171C FF7Ay SFR b BDy IRQ17 Interrupt Control Register 0000 IRQ18IC FF7Cy SFR b BEy IRQ18 Interrupt Control Register 0000 IRQ19IC FF7Ey SFR b BFy IRQ19 Interrupt Control Register 0000 IRQ20IC FF80y SFR b COy IRQ20 Interrupt Control Register 0000 IRQ21IC FF82y SFR b C1y IRQ21 Interrupt Control Register 0000 IRQ221C FF84y SFR b C2y IRQ22 Interrupt Control Register 0000 IRQ23IC FF86y SFR b C3y IRQ23 Interrupt Control Register 0000 IRQ24IC FF88y SFR b C4y IRQ24 Interrupt Control Register 0000 IRQ25IC FF8Ay SFR b C5y4 IRQ25 Interrupt Control Register 0000 IRQ26IC FF8Cy SFR b C6y IRQ26 Interrupt Control Register 0000 IRQ27IC FFSEy SFR b C7y IRQ27 Interrupt Control Register 00004 IRQ28IC FF90y SFR b C8 IRQ28 Interrupt Control Register 0000 IRQ29IC FF92 SFR b C9y IRQ29 Interrupt Control Register 0000 IRQ30IC FF94 SFR b CAy IRQ30 Interrupt Control Register 0000 IRQ311C FF96y SFR b CBy IRQ31 Interrupt Control Register 0000 IRQ32IC FF9Ch SFR b CEy IRQ32 Interrupt Control Register 0000 IRQ331C FF9Ey SFR b CFy IRQ3S3 Interrupt Control Register 0000 IRQ34IC FF98y SFR b CCy IRQ34 Interrupt Control Register 0000 IRQ35IC FF9A y SFR b CDy IRQ35 Interrupt Control Register 0000 IRQ36IC F186y ESFR b C3 IRQ36 Interrupt Control Register 000
97. contain a 0 or a hardware trap will occur rel This mnemonic represents an 8 bit signed word offset address relative to the current IP contents which point to the instruction after the branch instruction Depending on the offset address range both forward rel 00y to 7Fy and backward rel 80 to FFy branches are possible The branch instruction itself is repeatedly executed when rel 1 FFj4 for a word sized branch User s Manual 3 7 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Rw seg trap7 Central Processing Unit instruction or rel 2 FEy for a double word sized branch instruction In this case the 16 bit branch target instruction address is determined indi rectly by the contents of a word GPR In contrast to indirect data addresses indirectly specified code addresses are NOT calculated via additional pointer registers eg DPP registers Branches MAY NOT be taken to odd code addresses Therefore the least significant bit of the address pointer GPR must always contain a 0 or a hardware trap would occur Specifies an absolute code segment number The C166S supports 256 differ ent code segments so only the 8 lower bits respectively of the seg operand value are used to update the CSP register Specifies a particular interrupt or trap number for branching to the correspond ing interrupt or trap service routine via a jump vector table Trap numbers fr
98. data bits may be shifted with the leading edge or the trailing edge of the shift clock signal The baudrate may be set from 457 76 Baud up to 30 MBaud 60 MHz module clock The shift clock can be generated MS_CLK or can be received SS_CLK These features allow the adaptation of the SSC to a wide range of applications in which serial data transfer is required The Data Width Selection supports the transfer of frames of any data length from 2 bit characters up to 16 bit characters Starting with the LSB CON HB 0 allows communication with SSC devices in Synchronous Mode or with 8051 like serial interfaces for example Starting with the MSB CON HB 1 allows operation compatible with the SPI interface Regardless of the data width selected and whether the MSB or the LSB is transmitted first the transfer data is always right aligned in registers TB and RB with the LSB of the transfer data in bit O of these registers The data bits are rearranged for transfer by the internal shift register logic The unselected bits of TB are ignored the unselected bits of RB will not be valid and should be ignored by the receiver service routine The Clock Control allows the adaptation of transmit and receive behavior of the SSC to a variety of serial interfaces A specific shift clock edge rising or falling is used to shift out transmit data while the other shift clock edge is used to latch in receive data Bit CON PH selects the lead
99. data bus as well as byte accesses on a 16 bit data bus Word accesses on an 8 bit data bus are automatically split into two subsequent byte accesses in which the low byte is accessed first then the high byte The assembly of bytes to words and the disassembly of words into bytes is handled by the EBC and is transparent to the CPU and the programmer Byte accesses on a 16 bit data bus require that the upper and lower half of the memory can be accessed individually In this case the upper byte is selected with the Byte High Enable BHE signal while the lower byte is selected with the AO signal The two bytes of the memory can be enabled independently of each other or together when accessing words When writing bytes to an external 16 bit device that has a single CS input and two WR enable inputs for the two bytes the EBC can generate these two write control signals directly This saves the external combination of the WR signal with AO or BHE In this case pin WR serves as WRL WRite Low byte and pin BHE serves as WRH WRite High byte Bit WRCFG in register SYSCON selects the operating mode for pins WR and BHE The respective byte will be written on both data bus halves When reading bytes from an external 16 bit device whole words may be read and the C166S automatically selects the byte to be input and discards the other However care must be taken when reading devices that change state when being read such as FIFOs interrupt st
100. decrement indirect address pointers Rwz by the data type dependent value A 1 for byte operations A 2 for word operations User s Manual 3 59 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit GPR Pointer GPR Pointer A optional step The following indirect addressing modes are provided Table 3 14 Indirect addressing modes Mnemonic Particularities Rw Most instructions accept any GPR R15 RO as indirect address pointer Some instructions accept only the lower four GPRs R3 RO Rw The specified indirect address pointer is automatically post incremented by 2 or 1 for word or byte data operations after the access Rw The specified indirect address pointer is automatically pre decremented by 2 or 1 for word or byte data operations before the access Rw data16 The specified 16 bit constant is added to the indirect address pointer before the long address is calculated User s Manual 3 60 V 1 6 2001 08 1 fi User s Manual nrineon M s C166S V1 SubSystem Central Processing Unit 3 6 3 The System Stack A system stack is provided to store return vectors segment pointers and processor status for procedures and interrupt routines The internal system stack can also be used to store data temporarily or pass it between subroutines or tasks Instructions are provided to push or pop registe
101. determined by the contents of a DPP register but by the value of op1 itself The 14 bit page offset address bits A13 A0 is derived from the long or indirect address as usual The value of op2 defines the length of the effected instruction sequence CPU Flags fe ow qos aw e E Not affected Z Not affected V Not affected C Not affected N Not affected User s Manual 6 39 V 1 6 2001 08 pae e Infineon technologies User s Manual C166S V1 SubSystem Encoding Mnemonic EXTP pag irang2 EXTP RW Firang2 User s Manual Detailed Instruction Set Format Bytes D7 01 0 pp 0 00pp 4 DC 01 m 2 6 40 V 1 6 2001 08 1 fi User s Manual nrineon M C166S V1 SubSystem Detailed Instruction Set EXTPR Begin EXTended Page and Register Sequence EXTPR Group System Control Instructions Syntax EXTPR op1 op2 Source Operand s op1 gt 10 bit page number op2 gt 2 bit instruction counter Destination Operand s none Operation count op2 1 x op2 x 4 Disable interrupts and Class A traps Data Page lt op1 SFR range Extended DO WHILE count z 0 AND Class B Trap Condition z TRUE Next Instruction count lt count 1 END WHILE count 0 Data Page DPPx SFR range lt Standard Enable interrupts and traps Description Overrides the standard DPP addressing scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the
102. disabled the contents of the direction register last written by the user becomes active User s Manual 7 5 V 1 6 2001 08 User s Manual Infineon M os C166S V1 SubSystem The figure below shows the structure of a PORTO pin Parallel Ports Internal Bus Port Output Direction Register Register AltDir AltDataOut Driver AltDataln lt Input Register POH 7 0 POL 7 0 Figure 7 3 Block Diagram of a PORTO Pin User s Manual 7 6 Port0_1 vsd V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Parallel Ports 7 3 PORT1 The two 8 bit ports P1H and P1L represent the higher and lower part of PORT1 respectively Both halfs of PORT1 can be written e g via a PEC transfer without effecting the other half If this port is used for general purpose lO the direction of each line can be configured via the corresponding direction registers DP1H and DP1L P1L PORT1 Low Register SFR FF04 82 Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P1L P4L PIL P41L Pil P1L P1L P1L 7 5 4 3 2 1 0 rw rw rw rw rw rw rw rw P1H PORT1 High Register SFR FF06 83 Reset Value 00 15 14 13 12 11 10 9 8 Y 6 5 4 3 2 1 0 P1H P1H P1H P1H P1H P1H P1H P1H M 6 9 4 3 2 21 0 rw rw rw rw rw rw rw rw
103. generated if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete 2 2 3 8 General Purpose Timer Unit GPT12E The General Purpose Timer Unit GPT12E represents very flexible multifunctional timer structures which may be used for timing event counting pulse width measurement pulse generation frequency multiplication and other purposes They incorporate five 16 bit timers that are grouped into the two timer blocks GPT1 and GPT2 Each timer in each block may operate independently in a number of different modes such as gated timer or counter mode or may be concatenated with another timer of the same block Block 1 contains 3 timers counters with a maximum resolution of fppgus 4 The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer User s Manual 2 10 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V1 SubSystem System Overview Block 2 contains 2 timers counters with a maximum resolution of fppgus 2 An additional CAPREL register supports capture and reload operation with extended functionality The following enumeration summarizes all features to be supported Timer Block 1 fppgus 4 maximum resolution 3 independent timers counters Timers counters can be concatenated 4 operating modes timer gated timer counter incremental Separate interrupt reques
104. gt BIT Operation op1 0p2 Description Moves the complement of a single bit from the source operand specified by op2 into the destination operand specified by op1 The source bit is examined and the flags are updated accordingly CPU Flags E Z V C N E Always cleared Z Contains the logical negation of the source bit V Always cleared C Always cleared N Contains the state of the source bit Encoding Mnemonic Format Bytes BMOVN bitaddrz z bitaddra q 3A QQ ZZ qz 4 User s Manual 6 17 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set BOR Bit Logical OR BOR Group Boolean Bit Manipulation Instructions Syntax BOR op1 op2 Source Operand s op1 op2 gt BIT Destination Operand s op1 gt BIT Operation op1 op1 v op2 Description Performs a single bit logical OR of the source bit specified by op2 and the destination bit specified by op1 The result is then stored in op1 CPU Flags E Z V C N o non oR anD xon E Always cleared Z Contains the logical NOR of the two specified bits V Contains the logical OR of the two specified bits C Contains the logical AND of the two specified bits N Contains the logical XOR of the two specified bits Encoding Mnemonic Format Bytes BOR bitaddrz z bitaddra y 5A QQ ZZ qz 4 User s Manual 6 18 V 1 6 2001 08 1 fi User s Manual o C166S V1 SubSystem Detailed Inst
105. gt WORD MDL gt WORD Destination Operand s MD gt DOUBLEWORD Operation MDL lt MDL op1 MDH lt MDL mod op1 Description Performs an unsigned 16 bit by 16 bit division of the low order word stored in the MD register by the source word operand op1 The unsigned quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH CPU Flags E Z V C N o j tj t po E Always cleared Z Set if quotient stored in the MDL register equals zero Cleared otherwise Undefined if the V flag is set V Set if the divisor op1 was zero C Always cleared N Set if the most significant bit of the quotient stored in the MDL register is set Cleared otherwise Undefined if the V flag is set Encoding Mnemonic Format Bytes DIVU Rwy 5B nn 2 User s Manual 6 37 V 1 6 2001 08 pae 1 fi User s Manual nrineon M a C166S V1 SubSystem Detailed Instruction Set EINIT End of Initialization EINIT Group System Control Instructions Syntax EINIT Source Operand s none Destination Operand s none Operation End of Initialization Description After a reset the reset output pin RSTOUT is pulled low It remains low until the EINIT instruction has been executed at which time it goes high This enables the software to signal the external circuitry that it has successfully initialized the microcontroller Execution of the Disabl
106. half of the LSB of the result In conjunction with the V flag the C flag allows the rounding error to be evaluated with a finer resolution see table below For Boolean bit operations with only one operand the V flag is always cleared For Boolean bit operations with two operands the V flag represents the logical ORing of the two specified bits Table 3 19 Shift Right Rounding Error Evaluation C Flag V Flag Rounding Error Quantity 0 0 No rounding error 0 1 O lt Rounding error lt 1 3 LSB 1 0 Rounding error 1 3 LSB 1 1 Rounding error gt 1 2 LSB Z Flag The Z flag is normally set to 1 if the result of an ALU operation equals zero otherwise it is cleared For addition and subtraction with carry the Z flag is set to 1 only if the Z flag already contains a 1 as a result of a previous operation and if the result of the current ALU operation equals zero This mechanism supports multiple precision calculations For Boolean bit operations with only one operand the Z flag represents the logical negation of the previous state of the specified bit For Boolean bit operations with two operands the Z flag represents the logical NORing of the two specified bits For the prioritize operation the Z flag indicates whether or not the second operand was zero E Flag End of table flag The E flag can be altered by instructions that perform ALU or data movement operations The E flag is cleared by those instructions that can not
107. have been overwritten by the status information stacked upon servicing the stack overflow trap Automatic system stack flushing allows the system stack to be used as a Stack Cache for a bigger external user stack In this case STKOV should be initialized to a value that represents the desired lowest Top Of Stack TOS address plus an offset based on the selected maximum stack size This offset considers the worst case that will occur when a stack overflow condition is detected just during entry into an ISR or during an ATOMIC EXTend sequence Under these conditions additional stack word locations are required to push IP PSW and CSP for both the ISR and the hardware trap service routine The STacK UNderflow Pointer Register STKUN STKUN is a non bit addressable register that is compared to the SP register after each operation that pops data from the system stack e g POP and RET instructions and after each addition to the SP register If the content of the SP register is greater than the the content of STKUN a stack underflow hardware trap will occur Since the LSB of STKUN is tied to O and bits 15 through 12 are tied to 1 by hardware STKUN register can only contain values from F000 to FFFEy Ub Pointer SFR FE16 0B y Reset value FC00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1111 STKUN 0 r rw r User s Manual 3 63 V 1 6 2001 08 1 fi User s Manual n Infineon
108. incorporated for efficient use of system resources These nodes can be activated by several source requests The C166S provides a vectored interrupt system This system reserves specific vector locations in the memory space for the reset trap and interrupt service functions Whenever a request occurs the CPU branches to the location that is associated with the respective interrupt source The reserved vector locations build a jump table in the C166S s address space The arbitration winner is sent to the CPU together with its priority level and action request The CPU triggers the corresponding action which depends on the required functionality normal interrupt PEC etc of the arbitration winner An action request will be accepted by the CPU if the requesting source has a higher priority than the current CPU priority level and if interrupts are globally enabled If the requesting source has a lower or equal interrupt level priority then the requested interrupt stays pending 3 4 2 Interrupt Arbitration The C166S interrupt arbitration system can handle interrupt requests from up to 112 sources Interrupt requests may be triggered either by the C166S peripherals or by external inputs The End of PEC interrupt for supporting enhanced PEC functionality is connected internally to one of the interrupt request lines The arbitration process starts by an enabled interrupt request and stays active for as long as interrupt request is pend
109. into interrupt routines or subroutines Avoid complex encoding schemes by placing operands in consistent fields for each instruction Also avoid complex addressing modes which are not frequently used This decreases the instruction decode time while also simplifying the development of compilers and assemblers Provide most frequently used instructions with one word instruction formats All other instructions are placed into two word formats This allows all instructions to be placed on word boundaries which alleviates the need for complex alignment hardware It also has the benefit of increasing the range for relative branching instructions The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly functional C166S instruction set which includes the following instruction classes Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions Possible operand types are bits bytes and words Specific instruction support the conversion extension of bytes to words A variety of direct indirect or immediate addressing modes are provided to specify the required operands User s Manual 2 5 V
110. is saved in the system stack Interrupt Processing via the Peripheral Event Controller A faster alternative to normal interrupt processing is servicing an interrupt requesting device by the C166S s integrated PEC Triggered by an interrupt request the PEC performs a single word or byte data transfer between any two memory locations through one of up to 16 programmable PEC service channels During a PEC transfer the normal program execution of the CPU is halted No internal program status information needs to be saved The same prioritization scheme is used for PEC service as for normal interrupt processing User s Manual 3 18 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V1 SubSystem Central Processing Unit 3 4 1 Interrupt System Structure The C166S provides up to 112 separate interrupt nodes that may be assigned to 128 arbitration priority levels with 16 interrupt priority groups and 4 8 priorities inside each group In order to support modular and consistent software design techniques most sources of an interrupt or PEC request are supplied with a separate interrupt control register and interrupt vector The control register contains an interrupt request flag Interrupt Enable IE bit and interrupt priority of the associated source Each source request is activated by one specific event depending on the selected operating mode of the respective device In some cases the multi source interrupt nodes are
111. its level should be held high or low for at least 2 f cycles BPS2 01 before it changes 12 3 2 Auxiliary Timer T5 The auxiliary Timer T5 can be configured for Timer Mode Gated Timer Mode or Counter Mode with the same options for the timer frequencies and the count signal as core Timer T6 In addition to these three counting modes the auxiliary timer can be concatenated with the core timer The individual configuration for Timer T5 is determined by its bitaddressable control register T5CON Note that functions present in both timers of Timer Block 2 are controlled in the same bit positions and in the same manner in each of the specific control registers Run control for auxiliary Timer T5 can be handled by the associated Run Control Bit T5R in register T5CON Alternatively a remote control option T5RC is set may be enabled to start and stop T5 via the run bit T6R of core Timer T6 Note The auxiliary timer has no bit T5OTL Therefore an output line for overflow underflow monitoring is not provided T5 Timer 5 Reset value 0000p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T5 rwh T5CON Timer 5 Control Register Reset value 0000p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T5 T5 T5 T5 T5 T5 SC ctR C cc CT3 nc uDE up TS TM i rw rw rw rw rw rw rw rw rw rw rw Field Bits Typ Description T5 15 0 rwh Timer 5 Contains
112. lt op1 op2 Description Performs a 16 bit by 16 bit signed multiplication using the two words specified by operands op1 and op2 respectively The signed 32 bit result is placed in the MD register CPU Flags E Z V C N E Always cleared Z Set if result equals zero Cleared otherwise V This bit is set if the result cannot be represented in a word data type Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes MUL Rw RWm 0B nm 2 User s Manual 6 64 V 1 6 2001 08 1 fi User s Manual o C166S V1 SubSystem Detailed Instruction Set MULU Unsigned Multiplication MULU Group Arithmetic Instructions Syntax MULU op1 op2 Source Operand s op1 op2 gt WORD Destination Operand s MD gt DOUBLEWORD Operation MD op1 op2 Description Performs a 16 bit by 16 bit unsigned multiplication using the two words specified by operands op1 and op2 respectively The unsigned 32 bit result is placed in the MD register CPU Flags E Z V C N E Always cleared Z Set if result equals zero Cleared otherwise V This bit is set if the result cannot be represented in a word data type Cleared otherwise C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes MULU Rw RWm 1B nm 2 User s Manual 6 65 V 1 6 2001 08 1 fi U
113. performance When using the READY function with so called normally ready peripherals erroneous bus cycles may occur if the READY line is sampled too early These peripherals pull their READY output low while they are idle When they are accessed they deactivate READY until the bus cycle is complete then drive it low again If however the peripheral deactivates READY after the first sample point of the C166S the controller samples an active READY and terminates the current bus cycle too early By inserting predefined waitstates the first READY sample point can be shifted to an interval in which the peripheral has safely controlled the READY line User s Manual 8 20 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface 8 4 Controlling the External Bus Controller A set of registers controls the functions of the EBC General features such as the usage of interface pins WR BHE segmentation and internal memory mapping are controlled via register SYSCON The properties of a bus cycle such as chip select mode length of ALE external bus mode read write delay and waitstates are controlled via registers BUSCON4 BUSCONO Four of these registers BUSCON4 BUSCON1 have an address select register ADDRSEL4 ADDRSEL1 associated with them which makes it possible to specify up to four address areas and the individual bus characteristics within these area
114. pointer has two parts An 8 bit Code Segment Pointer CSP and a 16 bit offset Instruction Pointer IP The concatenation of the CSP and IP results directly in a correct 24 bit physical memory address Memory organized in segments 15 7 CSP 0 254 FE OOOO o cocoon 00 0000 Figure 3 2 Addressing via the Code Segment and Instruction Pointers User s Manual 3 14 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit The Instruction Pointer IP This register determines the 16 bit intra segment address of the currently fetched instruction within the code segment selected by the CSP register The IP register is not mapped into the C166S s address space and thus it is not directly accessible by the programmer The IP can be modified indirectly by return instructions via the stack The IP register is updated implicitly by the C166S for branch instructions and after instruction fetch operations sien Pointer 4 H Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IP 0 r w h r Field Bits Type Description IP 15 1 rwh Specifies the intra segment offset from which the current instruction is to be fetched IP refers to the current segment lt SEGNR gt 0 0 r IP is always word aligned The Code Segment Pointer CSP This non bit addressable register selects the code segment being used at r
115. prp 3 70 3 7 3 The 16 bit Adder Subtracter Barrel Shifter and the 16 bit Logic Unit 3 70 3 7 4 Bit manipulation Unit 23 uuu p eevee tte 3 70 3 7 5 Multiply and Divide Unit 00000 eee ee 3 72 3 7 6 The Processor Status Word Register PSW 3 76 3 8 Instruction Pipeline isse cese hn tardara raras e ERE RS daa 3 80 3 8 1 Particular Pipeline Effects o0oooooooooommmmmoo 3 80 3 8 1 1 General considerations 222 kIse RE Ren arden 3 81 3 8 1 2 Specific cases with core registers ooooooooooooo 3 81 3 8 1 3 Common portable solution naaa asaan 3 86 3 8 2 Instruction State Times asserere ri a wees 3 87 3 9 Dedicated CSFRS cer LpERREEEPEEREERewRXESEEP Id ERE Rd SES 3 89 3 10 Summary of CPU Registers 02 0 cee eee o 3 91 3 10 1 General Purpose Registers 2 cece eee ees 3 91 3 10 2 Core Special Function Registers Ordered by Name 3 93 3 10 3 Core Special Function Registers ordered by Address 3 94 3 10 4 Register Overview C166S Interrupt and Peripheral Event Controller 3 95 User s Manual l 2 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Table of Contents Page 4 Memory Organization oooocccccocco ee 4 1 4 1 Data Organization in Memory ooocccccccco eese 4 3 4 2 Internal Local Memory Area 0 000 eee 4 4 4 3 DPRAM and SFR Area sssseeeeeee 4 5 4 3 1 Data Memories u
116. reg bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked For any long mem or indirect address in the EXTP instruction sequence the 10 bit page number address bits A23 A14 is not determined by the contents of a DPP register but by the value of op1 itself The 14 bit page offset address bits A13 A0 is derived from the long or indirect address as usual The value of op2 defines the length of the effected instruction sequence CPU Flags E Z V C N Fs ose dos cpm E Not affected Not affected V Not affected N User s Manual 6 41 V 1 6 2001 08 pae e Infineon technologies User s Manual C166S V1 SubSystem C Not affected N Not affected Encoding Mnemonic EXTPR pag irang2 EXTPR Rw irang2 User s Manual Detailed Instruction Set Format Bytes D7 11 0 pp 0 00pp 4 DC 11 m 2 6 42 V 1 6 2001 08 pae 1 fi User s Manual a C166S V1 SubSystem Detailed Instruction Set EXTR Begin EXTended Register Sequence EXTR Group System Control Instructions Syntax EXTR op1 Source Operand s op1 gt 2 bit instruction counter Destination Operand s none Operation count op1 1 lt op1 lt 4 Disable interrupts and Class A traps SFR range Extended DO WHILE count z 0 AND Class B Trap Condition z TRU
117. register CAPREL Separate interrupt lines for each timer counter User s Manual 12 1 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem General Purpose Timer Unit Clock T3OUT Control T6OUT T2IN GPT12E TAIN Address TN E a EA Module TIN Port E Decoder Kernel CAPIN Contro T2EUD T3EU T4EU T5EU Interrupt Control T6EU BPI Product Module Interface Interface Figure 12 1 GPT12E Interface Diagram Note Bus Peripheral Interface BPI is the connection to the on chip bus system User s Manual 12 2 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit 12 2 Functional Description of Timer Block 1 All three timers of Block 1 T2 T3 T4 can run in four basic modes Timer Mode Gated Timer Mode Counter Mode and Incremental Interface Mode All timers can count up or down Each timer of Block 1 is controlled by a separate control register TxCON Each timer has an input line TxIN associated with it which serves as the gate control in Gated Timer Mode or as the count input in Counter Mode The count direction up down may be programmed via software or may be dynamically altered by a signal at an external control line External Up Down Control Input TXEUD An overflow underflow of core Timer T3 is indicated by the Output Toggle Latch TSOTL whose state may be output on relate
118. respective output signals HLDA and BREQ This can be avoided by switching one of the controllers into Slave Mode in which pin HLDA is switched to input This allows the slave controller to be connected directly to another master controller without glue logic The Slave Mode is selected by setting bit DP6 7 to 1 DP6 7 0 default after reset selects the Master Mode Note The pins HOLD HLDA and BHEQ keep their alternate function bus arbitration even after the arbitration mechanism has been switched off by clearing HLDEN All three pins are used for bus arbitration after bit HLDEN has been set once Connecting Bus Masters When multiple C166Ss or a C166S and another bus master share external resources some glue logic is required to define the currently active bus master and to enable a User s Manual 8 32 V 1 6 2001 08 7 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface C166S that has surrendered its bus interface to regain control of it in case it must access the shared external resources This glue logic is required if the other bus master does not automatically remove its hold request after having used the shared resources When two C166Ss are to be connected in this way the external glue logic can be left out One of the controllers must be operated in its Master Mode default after reset DP6 7 0 while the other one must be operated in its Slave Mode selected with DP6 7 1 In Slav
119. s Manual a C166S V1 SubSystem Central Processing Unit 3 6 Data Addressing The C166S provides a lot of powerful addressing modes for word wise byte wise and bitwise data accesses short long indirect The different addressing modes use different formats and have different scopes The following major tasks are performed Address generation using short long and indirect addressing modes e Data paging or overwriting mechanism e System stack handling 3 6 1 Short Addressing Modes All of these addressing modes use an implicit base offset address to specify a 24 bit physical address Short addressing modes allow access to the GPRs SFRs or bit addressable memory space Physical Address Base Address A Short Address Note A is 1 for byte wise GPRs A is 2 for word wise GPRs Table 3 12 Short addressing modes Mnemonic Physical Address Short Address Scope of Access Range Rw CP 2 Rw or local Rw 0 15 GPRs Word Rb CP 1 Rb or local Rb 0 15 GPRs Byte reg 00 FEO0 4 2 reg reg 00y EFy SFRs Word Low byte 00 FO000y 2 reg reg 00y EFy ESFRs Word Low byte CP 2 regr0F y reg FOw FFy GPRs Word CP 1 regA OF reg FOy FFy GPRs Bytes bitoff 00 FD00 4 2 bitoff bitoff 004 7Fy DPRAMBit word offset 00 FFO0y 2 bitoffA7F bitoff 80y EFy SFR Bit word offset 00 F100y 2 bitoffA7F bitoff 80y EFy ESFRBit word offset CP 2 bitoffAOF
120. segment 0 or the internal LM may be disabled completely Code and data may be stored in any part of the internal memory areas except for the SFR blocks which may be used for control data but not for instructions Note Accesses to the internal LM area on devices without LM will produce unpredictable results User s Manual 4 2 V 1 6 2001 08 pae 1 fi User s Manual nrineon M a C166S V1 SubSystem Memory Organization 4 1 Data Organization in Memory Bytes are stored at even or odd byte addresses Words are stored in ascending memory locations with the low byte at an even byte address followed by the high byte at the next odd byte address Instruction double words are stored in ascending memory locations as two subsequent words without any restrictions non aligned Single bits are always stored in the specified bit position at a word address The memory and registers store data and instructions in little endian byte order the least significant bytes are at lower addresses The byte ordering is illustrated in Figure 4 2 Bit position O is the least significant bit of the byte at an even byte address and bit position 15 is the most significant bit of the byte at the next odd byte address Bit addressing is supported for a part of the SFRs a part of the DPRAM and for the General Purpose Registers GPRs XXXX XXXAy XXXX XXX9 yy XXXX XXX8 yy XXXX XXX XXXX XXX6 Word High Byte XXXX XXX5H Word Low Byte OO
121. selected by an 1 in the mask specified by op2 with the bits at the corresponding positions in op3 CPU Flags E Z V C N E Always cleared Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes BFLDL bitoffg mask8 data8 0A QQ 4 User s Manual 6 15 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set BMOV Bit to Bit Move BMOV Group Boolean Bit Manipulation Instructions Syntax BMOV op1 op2 Source Operand s op2 gt BIT Destination Operand s op1 gt BIT Operation op1 op2 Description Moves a single bit from the source operand specified by op2 into the destination operand specified by op1 The source bit is examined and the flags are updated accordingly CPU Flags E Z V C N E Always cleared Z Contains the logical negation of the source bit V Always cleared C Always cleared N Contains the state of the source bit Encoding Mnemonic Format Bytes BMOV bitaddrz z bitaddra q 4A QQ ZZ qz 4 User s Manual 6 16 V 1 6 2001 08 1 fi User s Manual nrineon M os C166S V1 SubSystem Detailed Instruction Set BMOVN Bit to Bit Move and Negate BMOVN Group Boolean Bit Manipulation Instructions Syntax BMOVN op1 op2 Source Operand s op2 gt BIT Destination Operand s op1
122. signals aread only timer register that contains the current count e acontrol register for initialization and reset source detection e aconf wdt en i subsystem signal to disable globally the WDT and e awdtint o subsystem signal to signal a watchdog timer overflow The 16 bit watchdog timer is realized as two concatenated 8 bit timers The upper 8 bits of the watchdog timer can be preset to a user programmable value via a watchdog service access in order to vary the watchdog expire time The lower 8 bits are reset upon each service access The watchdog timer is a 16 bit up counter which is clocked with the prescaled PDBus clock fpp The prescaler divides the PDBus clock by 2 WDTIN 0 WDTPRE 0 or by 4 WDTIN 0 WDTPRE 1 or 1 The WDT can be globally disabled by the conf wdt en subsystem signal User s Manual 9 1 V 1 6 2001 08 pae 1 fi User s Manual neon Infineon C1 66S V1 SubSystem Watchdog Timer by 128 WDTIN 1 WDTPRE 0 or by 256 WDTIN 1 WDTPRE 1 9 1 Operation of the Watchdog Timer The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT which is a non bitaddressable read only register The operation of the Watchdog Timer is controlled by its bitaddressable Watchdog Timer Control Register WDTCON This register specifies the reload value for the high byte of the timer selects the input clock prescaling factor and also p
123. specify ONLY GPR registers Once the subtraction has completed the operand op1 is decremented by one Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range CPU Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the word data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes CMPD1 Rw data16 A6 Fn 4 CMPD1 Rw data4 AO n 2 CMPD1 Rw mem A2 Fn MM MM 4 User s Manual 6 27 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set CMPD2 Integer Compare and Decrement by 2 CMPD2 Group Compare and Loop Control Instructions Syntax CMPD2 op1 op2 Source Operand s op1 op2 gt WORD Destination Operand s op1 gt WORD Operation op1 op2 op1 lt opt 2 Description This instruction is used to enhance the performance and flexibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 Operand op
124. specify up to sixteen general purpose registers located anywhere in the internal DPRAM Dual Port RAM A single one machine cycle instruction allows to switch register banks from one task to another 4 Interruptible Multiple Cycle Instructions Reduced interrupt latency is provided by allowing multiple cycle instructions multiply divide to be interruptible 5 Hardware Traps The C166S also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run time so called Hardware Traps Hardware traps cause an immediate non maskable system reaction which is similar to a standard interrupt service branching to a dedicated vector table location The occurrence of a hardware trap is additionally signified by an individual bit in the Trap Flag Register TFR Except for another higher prioritized trap service being in progress a hardware trap will interrupt any current program execution In turn hardware trap services can normally not be interrupted by standard or PEC interrupts 6 Software Traps Software interrupts are supported by means of the TRAP instruction in combination with an individual trap interrupt number User s Manual 2 6 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem System Overview 2 2 The C166S System Resources The C166S based subsystem provides a number of powerful system resources designed around the CPU The
125. table two pages is a compressed cross reference table that quickly identifies a specific hexadecimal opcode with the respective mnemonic The second table lists the instructions by their mnemonic and identifies the addressing modes that may be used with a specific instruction and the instruction length depending on the selected addressing mode This reference helps to optimize instruction sequences in terms of code size and or execution time Note Both ordering schemes hexadecimal opcode and mnemonic are provided in more detailed lists in the following sections of this manual Ox 1x 2x 3X 4x 5x 6x 7X x0 ADD ADDC SUB SUBC CMP XOR AND OR x1 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB x2 ADD ADDC SUB SUBC CMP XOR AND OR x3 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB x4 ADD ADDC SUB SUBC XOR AND OR xb ADDB ADDCB SUBB SUBCB XORB ANDB ORB x6 ADD ADDC SUB SUBC CMP XOR AND OR x7 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB x8 ADD ADDC SUB SUBC CMP XOR AND OR x9 ADDB ADDCB SUBB SUBCB CMPB XORB ANDB ORB xA BFLDL BFLDH BCMP BMOVN BMOV BOR BAND BXOR xB MUL MULU PRIOR l DIV DIVU DIVL DIVLU xC ROL ROL ROR ROR SHL SHL SHR SHR xD JMPR JMPR JMPR JMPR JMPR JMPR JMPR JMPR xE BCLR BCLR BCLR BCLR BCLR BCLR BCLR BCLR xF BSET BSET BSET BSET BSET BSET BSET BSET User s Manual 5 1 V 1 6 2001 08 e Infineon technologies No
126. than when triggered by a real hardware event 3 4 5 2 Hardware Traps Hardware traps are issued by faults or specific system states that occur during runtime not identified at assembly time The C166S distinguishes eight different hardware trap functions When a hardware trap condition has been detected the CPU branches to the trap vector location for the respective trap condition The instruction that caused the trap event is either completed or canceled before the trap handling routine is entered Hardware traps are not maskable and always have a higher priority than any other CPU task If several hardware trap conditions are detected within the same machine cycle the highest priority trap is serviced In the case of a hardware trap the injection unit injects a TRAP instruction into the pipeline The TRAP instruction performs the following actions Push PSW CSP in segmented mode and IP onto the system stack Set CPU level in the PSW register to the highest possible priority level which disables all interrupts and DMA transfers Branch to the trap vector location specified by the trap number of the trap condition The eight hardware functions of the C166S are divided in two Classes Class A traps are External NMIs Stack overflow Stack underflow These traps share the same trap priority but have an individual vector address Class B traps are User s Manual 3 26 V 1 6 2001 08 e Infineon te
127. the answer to specific questions about the C166S V1 SubS R1 A Address Arbitration 8 28 Area Definition 8 28 Boundaries 4 9 Segment 8 12 Addressing Modes Indirect Addressing Mode 3 59 Long Adressing Mode 3 58 Long and Indirect Addressing Modes 3 54 Short Addressing Modes 3 52 ADDRSELx 8 25 8 28 ALE length 8 16 Alternate signals 7 2 Arbitration Address 8 28 External Bus 8 31 ASCO Error Detection 10 23 Auxiliary Timer 5 12 34 B Baudrate ASCO 10 17 BHE 8 12 Bit protected 3 71 Boundaries 4 9 Bus Arbitration 8 31 Demultiplexed 8 6 Idle State 8 30 Mode Configuration 8 2 Multiplexed 8 3 User s Manual 14 1 BUSCONXx 8 23 8 29 BWT 3 37 C CAPREL 12 39 Capture Mode GPT2 12 39 Capture Reload Register 12 39 Central System Control 2 13 CGU 2 14 Chip Select Configuration 8 13 Latched Early 8 14 Clock Generation Unit 2 14 Concatenation of Timers 12 21 12 38 Configuration Address 8 12 Bus Mode 8 2 Chip Select 8 13 Context Pointer 3 50 Context Switch 3 50 Continuous PEC Transfers 3 38 Core Timer T3 12 5 COUNT 3 37 3 38 3 39 Count direction 12 8 12 30 CP Register 3 50 CPU 2 2 CPUID Register 3 90 CSP Register 3 15 D Data Page boundaries 4 9 Data Page Pointer 3 55 Data Types 3 68 Delay V 1 6 2001 08 pae e Infineon technologies User s Manual C166S V1 SubSystem Read Write 8 18 Demultiplexed Bus 8 6 Development Support 1 5 Direction count 12 8 12 30 DPOL DPOH 7 3
128. the current value of Timer 5 User s Manual 12 34 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem General Purpose Timer Unit Field Bits Typ Description T5I 2 0 Timer 5 Input Parameter Selection Timer Mode see Table 12 13 for encoding Gated Timer Mode see Table 12 13 for encoding Counter Mode see Table 12 14 for encoding T5M 5 3 Timer 5 Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 1XX Reserved Do not use this combination T5R 6 rw Timer 5 Run Bit 0 Timer Counter 5 stops 1 Timer Counter 5 runs T5UD 7 rw Timer 5 Up Down Control when T5UDE 0 0 Counts Up 1 Counts Down T5UDE 8 rw Timer 5 External Up Down Enable 0 Counting direction is internally controlled by software 1 Counting direction is externally controlled by line T5EUD T5RC 9 rw Timer 5 Remote Control 0 Timer counter 5 is controlled by its own run bit T5R 1 Timer counter 5 is controlled by the run bit of core Timer 6 CT3 10 Timer 3 Capture Trigger Enable 0 Capture trigger from input line CAPIN 1 Capture trigger from T3 input lines T3IN and or T3EUD T5CC 11 Timer 5 Capture Correction 0 T5 is just captured without any correction 1 T5 is decremented by
129. the receive shift register are transferred to the receive data Buffer register RBUF Simultaneously the receive interrupt request line RIR is activated after the 9th sample in the last stop bit time slot as programmed regardless of whether valid stop bits have been received or not The User s Manual 10 12 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Asynchronous Synchronous Serial Interface ASC receive circuit then waits for the next start bit 1 to O transition at the receive data input line RBUF Receive Buffer Register Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RD_VALUE r rw Field Bits Typ Description RD_VALUE 8 0 rw Receive Data Register Value RBUF contains the received data bits and depending on the selected mode the parity bit in asynchronous and synchronous operating mode of the ASC In asynchronous operating mode with M 011 7 bit data parity the received parity bit is written into RD7 In asynchronous operating mode with M 111 8 bit data parity the received parity bit is written into RD8 Reserved for future use reading returns 0 writing to these bit positions has no effect 0 15 9 Note The receiver input pin RXD must be configured for input Asynchronous reception is stopped by clearing bit CON_REN A currently received frame is completed including the generation of t
130. the selected maximum stack size The next instruction will push register R2 onto the highest physical stack location although the SP is decremented by 2 as for the previous push operation MOV SP 0F802H Set SP before last entry P Of physical stack of 256 words at SP F802H Physical stack addr FA02H PUSH R1 SP F800H Physical stack addr FAOOH PUSH R2 SP F7FEH Physical stack addr FBFEH The effect of the address transformation is that the physical stack addresses wrap around from the end of the defined area to its beginning When flushing and filling the User s Manual 3 66 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Central Processing Unit internal stack this circular stack mechanism only requires moving that portion of stack data that is to be re used i e the upper part of the defined stack area instead of the whole stack area Stack data that remain in the lower part of the internal stack need not be moved by the distance of the space being flushed or filled as the stack pointer automatically wraps around to the beginning of the freed part of the stack area Note This circular stack technique is applicable for stack sizes of 32 to 512 words STKSZ 000g to 100g It does not work with option STKSZ 111g which uses the complete DPRAM for system stack in this case the address transformation mechanism is deactivated When a boundary is reache
131. third encoder output TO which indicates the mechanical zero position may be connected to an external interrupt input to trigger a reset of Timer T3 External Encoder Toinput Microcontroller Interrupt Signal Conditioning Figure 12 8 Interfacing the Encoder to the Microcontroller The following conditions must be met for Incremental Interface Mode operation e Bitfield T3M must be 110g or 111g Pins associated with lines T3IN and T3EUD must be configured as inputs Bit TSUDE must be set to enable external direction control The maximum input frequency allowed in Incremental Interface Mode is f 8 T3BPS 01g To ensure that a transition of any input signal is correctly recognized its level should be held high or low for at least 4 fo cycles T3BPS 01g before it changes In Incremental Interface Mode the count direction is automatically derived from the sequence in which the input signals change corresponding to the rotation direction of the connected sensor Table 12 6 summarizes the possible combinations Table 12 6 Core Timer T3 Incremental Interface Mode Count Direction Level on T3IN Input T3EUD Input respective other Rising Falling Rising Falling input High Down Up Up Down Low Up Down Down Up Figure 12 9 and Figure 12 10 give examples of the operation of T3 to illustrate count signal generation and direction control Each example also shows how input jitter which
132. width measurement pulse generation frequency multiplication and other purposes The GPT12E incorporates five 16 bit timers grouped into two timer blocks Block 1 GPT1 and Block 2 GPT2 Each timer in each block can operate independently in a number of different modes such as Gated Timer Mode or Counter Mode or each timer can be concatenated with another timer of the same block Block 1 contains three timers counters with a maximum resolution of f x 4 The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer Block 2 contains two timers counters with a maximum resolution of f 2 An additional CAPREL register supports capture and reload operation with extended functionality Note Core Timer T6 may be concatenated with timers of other on chip peripherals The following summary identifies all features to be supported by the GPT12E Timer Block 1 Maximum resolution of f x 4 Three independent timers counters Concatenation of timers counters can be done Four operating modes Timer Mode Gated Timer Mode Counter Mode Incremental Interface Mode Separate interrupt lines for each timer counter Timer Block 2 Maximum resolution of fax 2 Two independent timers counters Concatenation of Timers counters can be done Three operating modes Timer Mode Gated Timer Mode Counter Mode Extended capture reload functions via 16 bit capture reload
133. will be executed in this case e For any access to an internal address area the EBC will remain inactive see Section 8 5 EBC Idle State 8 5 EBC Idle State When the external bus interface is enabled but no external access is currently being executed the EBC is idle As long as only internal resources from an architecture point of view such as DPRAM GPRs or SFRs etc are used the external bus interface does not change seeTable 8 7 below Accesses to on chip X Peripherals are also controlled by the EBC However even though an X Peripheral appears to the controller as if it were an external peripheral the accesses do not generate valid external bus cycles User s Manual 8 30 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface Due to timing constraints address and write data of an XBUS cycle are reflected on the external bus interface see Table 8 7 below The address mentioned above includes Port 4 BHE and ALE which also pulses for an XBUS cycle The external CS signals are driven inactive high because the EBC switches to an internal XCS signal The external control signals RD and WR or WRL WRH if enabled remain inactive high Table 8 7 Status Of The External Bus Interface During EBC Idle State Pins Internal accesses only XBUS accesses PORTO Tristated floating Tristated floating for read accesses
134. word memory from direct GPR with 2 Carry and post increment source pointer by 2 SUBC Rw data3 Subtract immediate word data from direct GPR with Carry 2 SUBC reg data16 Subtract immediate word data from direct register with 4 Carry SUBC reg mem Subtract direct word memory from direct register with Carry 4 SUBC mem reg Subtract direct word register from direct memory with Carry 4 SUBCB Rb Rb Subtract direct byte GPR from direct GPR with Carry 2 SUBCB Rb Rw Subtract indirect byte memory from direct GPR with Carry 2 SUBCB Rb Rw Subtract indirect byte memory from direct GPR with Carry 2 and post increment source pointer by 1 SUBCB Rb data3 Subtract immediate byte data from direct GPR with Carry 2 SUBCB reg data8 Subtract immediate byte data from direct register with Carry 4 User s Manual 5 7 V 1 6 2001 08 Infineon technologies User s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary cont d Mnemonic Description Bytes Arithmetic Operations cont d SUBCB reg mem Subtract direct byte memory from direct register with Carry 4 SUBCB mem reg Subtract direct byte register from direct memory with Carry 4 MUL Rw Rw Signed multiply direct GPR by direct GPR 16 16 bit 2 MULU Rw Rw Unsigned multiply direct GPR by direct GPR 16 16 bit 2 DIV Rw Signed divide regist
135. yy Double Word High xxxx xxx3 Double Word Third xxxx xxx2 Double Word xxxx xxxt Double Word Low xxxx xxx0 Xxxx xxxFu Figure 4 2 Storage of Words Byte and Bits in a Byte Organized Memory Note Byte units forming a single word must always be stored within the same physical internal external ROM RAM and organizational page segment memory area User s Manual 4 3 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V1 SubSystem Memory Organization 4 2 Internal Local Memory Area The C166S reserves an address area of variable size depending on the device configuration for on chip Local Memory LM The internal LM can be ROM SRAM flash or DRAM The internal LM may be enabled disabled or mapped into segment O or segment 1 under software control Internal LM accesses are enabled or disabled globally via bit ROMEN in the SYSCON register This bit is set during reset according to the level on external pin EA or may be altered via software If enabled the internal lower 32K of LM area occupies the lower 32 KByte of either segment 0 or segment 1 This mapping is controlled by bit ROMS1 in register SYSCON Note The size of the internal LM area may be independent of the size of the actual implemented LM Devices with less than 32 KBytes of LM or with no LM at all will have this 32 KByte area occupied if the LM is enabled Devices with a larger LM provide the mapping option o
136. 0000y T2IC FF60y SFR b BOy GPT12E Timer 2 Interrupt 0000 Control Register User s Manual 4 40 V 1 6 2001 08 1 fi User s Manual a C166S V1 SubSystem Memory Organization Table 4 3 SFR ESFR Table ordered by name cont d Name Physical Type 8 bit Description Reset Address a Value T3 FE42y SFR 214 GPT Timer 3 Register 0000y T3CON FF424 SFR b Aly GPT Timer 3 Control Register 0000y T3IC FF62H SFR b Biy GPT12E Timer 3 Interrupt 00004 Control Register T4 FE44 y SFR 224 GPT Timer 4 Register 0000y T4CON FF44 y SFR b A2 GPT Timer 4 Control Register 0000y T4IC FF64y SFR b B2y GPT12E Timer 4 Interrupt 0000 Control Register T5 FE46y SFR 234 GPT Timer 5 Register 00004 T5CON FF46y SFR b A3y GPT Timer 5 Control Register 0000 T5IC FF66y SFR b B3y GPT12E Timer 5 Interrupt 0000y Control Register T6 FE48y SFR 244 GPT Timer 6 Register 0000 T6CON FF48y SFR b A44 GPT Timer 6 Control Register 0000y T6IC FF68 SFR b B4 GPT12E Timer 6 Interrupt 00004 Control Register TFR FFAC SFR b D6y Trap Flag Register 0000 WDT FEAE SFR 574 Watchdog Timer Register RO 0000 WDTCON FFAE SFR b D7y Watchdog Timer Control 008xH Register WDTIC F19A ESFR b CD Watchdog Timer Interrupt 0000 Control Register XADRS1 FO14 y ESFR 0Ay XBUS Address Select Register 1 0000 XADRS2 FO16y ESF
137. 001 08 pae i fi User s Manual n Infineon C1 66S V1 SubSystem High Speed Synchronous Serial Interface SSC 11 2 5 Baudrate Generation The serial channel SSC has its own dedicated 16 bit baudrate generator with 16 bit reload capability allowing baudrate generation independent of the timers Figure 11 3 shows the baudrate generator Figure 11 7 shows the baudrate generator of the SSC in more detail 16 Bit Reload Register fus CLK SS CLK fus CLK max Ih Master Mode fok 2 fo 4 IA IA ss CLK max in Slave Mode Figure 11 7 SSC Baudrate Generator The baudrate generator is clocked with the module clock fo The timer counts downwards Register BR is the dual function Baudrate Generator Reload register Reading BR while the SSC is enabled returns the content of the timer Reading BR while the SSC is disabled returns the programmed reload value In this mode the desired reload value can be written to BR Baudrate Timer Reload Register The SSC baudrate timer reload register BR contains the 16 bit reload value for the baudrate timer Brugis Timer Reload Register Reset value 0000p 15 14 13 12 11 i0 9 8 7 6 5 4 3 2 1 0 BR VALUE rw Note Never write to BR while the SSC is enabled The formulas below calculate either the resulting baudrate for a given reload value or the required reload value for a given baudrate User s Manual 11 15 V 1 6 2001 08
138. 00y FFCC P6 SFR b E6y Port 6 Register 8 bits 00 FFCE DP6 SFR b E7y Port 6 Direction Control Register 00y FFDOy SFR b E8y FFD2y SFR b E9y FFD4y SFR b EAy FFD6 y SFR b EBy FFD8y SFR b ECy User s Manual 4 30 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value FFDAy reserved SFR b EDy reserved do not use FFDCy reserved SFR b EEy reserved do not use FFDEy reserved SFR b EFy reserved do not use FFEOy reserved reserved do not use FFE2y ASCOID ASCO Identification Register 44xxy FFE4 SSCOID SSCO Identification Register 45xxy FFE6 GPTID GPT Identification Register 58xXXH FFE8 reserved reserved do not use 00004 FFEAy reserved reserved do not use 0000 FFECH reserved reserved do not use 0000 FFEEy reserved reserved do not use 00004 FFFOy reserved reserved do not use 0000y FFF2y reserved reserved do not use 0000y FFF4y reserved reserved do not use 00004 FFF6y reserved reserved do not use 0000y FFF8y reserved reserved do not use 0000y FFFAy reserved reserved do not use 00004 FFFC reserved reserved do not use 0000 FFFEy reserved reserved do not use 0000 1 The PDBUS chip sel
139. 04 IRQ37IC F18Ey ESFR b C74 IRQ37 Interrupt Control Register 0000 IRQS38IC F196y ESFR b CBy IRQ38 Interrupt Control Register 0000 IRQ39IC F19Ey ESFR b CFy IRQ39 Interrupt Control Register 00004 IRQ40IC F17Ay ESFR b BDy IRQAO Interrupt Control Register 00004 IRQ41IC F17Cy ESFR b BEy IRQ41 Interrupt Control Register 00004 IRQ421C F182y ESFR b C1y IRQ42 Interrupt Control Register 00004 IRQ43IC F18Ay ESFR b C5y 1RQ43 Interrupt Control Register 00004 IRQ44IC F192y ESFR b C9y IRQ44 Interrupt Control Register 0000 IRQ45IC F190y ESFR b C8y IRQ45 Interrupt Control Register 0000 User s Manual 4 34 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 3 SFR ESFR Table ordered by name cont d Name Physical Type 8 bit Description Reset Address a Value IRQ46IC F198j ESFR b CCy IRQ46 Interrupt Control Register 0000 IRQ471C F188 ESFR b C4y IRQ47 Interrupt Control Register 0000 IRQ48IC F160y ESFR b BOy IRQ48 Interrupt Control Register 0000 IRQ49IC F162H ESFR b B1y IRQ49 Interrupt Control Register 0000 IRQ50IC F164y ESFR b B2y IRQ50 Interrupt Control Register 0000 IRQ51IC F166 ESFR b B3 IRQ51 Interrupt Control Regist
140. 1 op2 gt BYTE Destination Operand s op BYTE Operation op1 op1 op2 C Description Performs a 2 s complement binary addition of the source operand specified by op2 the destination operand specified by op1 and the previously generated carry bit The sum is then stored in op1 This instruction can be used to perform multiple precision arithmetic CPU Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and previous Z flag was set Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in the byte data type Cleared otherwise C Set if a carry is generated from the most significant bit of the byte data type Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes ADDCB Rb data3 19 n 0 B ADDCB Rb RO 11 nm 2 ADDCB Rb Rw 19n 11ii 2 ADDCB Rb Rw 19 n 10ii 2 ADDCB mem reg 15 RR MM MM 4 ADDCB reg data8 17 RR xx 4 ADDCB reg mem 13 RR MM MM 4 User s Manual 6 5 V 1 6 2001 08 1 fi User s Manual o C166S V1 SubSystem Detailed Instruction Set AND Logical AND AND Group Logical Instructions Syntax AND op1 op2 Source Operand s op1 op2 gt WORD Destination Operand s op1 gt WORD Operation op1 lt op1 op2 Descript
141. 1 while the data uses PORTO 16 bit data or POL 8 bit data The upper address lines are permanently output on Port 4 if selected via SALSEL during reset No address latches are required The EBC initiates an external access by placing an address on the address bus After a programmable period of time the EBC activates the appropriate command signal RD WR WRL WRH Data is driven onto the data bus either by the EBC for write cycles or by the external memory peripheral for read cycles After a period of time determined by the access time of the memory peripheral data becomes valid Read cycles Input data is latched and the command signal is now deactivated This causes the accessed device to remove its data from the data bus which is then tri stated again Write cycles The command signal is now deactivated If a subsequent external bus cycle is required the EBC places the relevant address on the address bus The data remain valid on the bus until the next external bus cycle is started User s Manual 8 6 V 1 6 2001 08 User s Manual O Infineon M C166S V1 SubSystem The External Bus Interface CLKOUT Normal ALE Cycle Normal ALE Extended LE Cycle 5 Extend ALE CSxL9 A23 AQ BHE CSxE er WRL WRH WR WRCS y D15 DO Normal Wr l D15 DO Early Write a O z 1 Section 8 3 4 Read Write Delay 3 4 Section 8 3 5 Early Write eea ua 3 Se
142. 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem System Overview 2 1 5 Programmable Multiple Priority Interrupt and PEC System The following enhancements have been included to allow processing of a large number of interrupt sources 1 Peripheral Event Controller PEC This processor is used to off load many interrupt requests from the CPU It avoids the overhead of entering and exiting interrupt or trap routines by performing single cycle interrupt driven byte or word data transfers between any two locations with an optional increment of either the PEC source or the destination pointer Just one cycle is stolen from the current CPU activity to perform a PEC service 2 Multiple Priority Interrupt Controller ITC This controller allows all interrupts to be placed at any specified priority Interrupts may also be grouped which provides the user with the ability to prevent similar priority tasks from interrupting each other For each of the possible interrupt sources there is a separate control register which contains an interrupt request flag an interrupt enable flag and an interrupt priority bitfield Once having been accepted by the CPU an interrupt service can only be interrupted by a higher prioritized service request For standard interrupt processing each of the possible interrupt sources has a dedicated vector location 3 Multiple Register Banks This feature allows the user to
143. 1 SubSystem Central Processing Unit 3 4 4 4 Saving the Status during Interrupt Service Before an operating system or ITC can actually service a task switch request or interrupt the CPU must save the current task status The C166S saves the CPU status PSW along with the return address in the system stack The return address defines the point where the execution of the interrupted task is to be resumed after returning from the service routine This return address is specified by the IP and in the case of a segmented memory mode also by the CSP Bit SGTDIS in the SYSCON register defines which mode is used and therefore controls how the return address is stored In the case of non segmented mode the system stack stores the PSW first and then the IP In the segmented mode PSW is followed by CSP and the IP This order optimizes the use of the system stack if segmentation is disabled The CPU priority field ILVL in PSW is updated with the priority of the interrupt request that is to be serviced so the CPU now executes on the new level Status of Interrupted Task E Mc PEN o PSW ERE SP IP NN IP 1 System Stack before 2 System Stack after 3 System Stack after Interrupt Entry Interrupt Entry Interrupt Entry Unsegmented Segmented Figure 3 4 Task Status saved on the System Stack After accepting an interrupt request the C166S sends an acknowledgement to the ITC that the requested interrupt is bein
144. 1 may specify ONLY GPR registers Once the subtraction has completed the operand op1 is decremented by two Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range CPU Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the word data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes CMPD2 Rw data16 B6 Fn 4 CMPD2 Rw data4 BO n 2 CMPD2 Rw mem B2 Fn MM MM 4 User s Manual 6 28 V 1 6 2001 08 1 fi User s Manual a C166S V1 SubSystem Detailed Instruction Set CMPI1 Integer Compare and Increment by 1 CMPI1 Group Compare and Loop Control Instructions Syntax CMPI1 op1 op2 Source Operand s op1 op2 gt WORD Destination Operand s op1 gt WORD Operation op1 gt op2 0p1 lt op1 1 Description This instruction is used to enhance the performance and flexibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 Operand op1
145. 10ii 2 SUBB mem reg 25 RR MM MM 4 SUBB reg data8 27 RR xx 4 SUBB reg mem 23 RR MM MM 4 User s Manual 6 93 V 1 6 2001 08 1 fi User s Manual SUE NN C166S V1 SubSystem Detailed Instruction Set SUBC Integer Subtraction with Carry SUBC Group Arithmetic Instructions Syntax SUBC op1 op2 Source Operand s op1 op2 gt WORD Destination Operand s op1 gt WORD Operation op1 lt opi op2 C Description Performs a 2 s complement binary subtraction of the source operand specified by op2 and the previously generated carry bit from the destination operand specified by op1 The result is then stored in op1 This instruction can be used to perform multiple precision arithmetic CPU Flags E Z V C N S E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and previous Z flag was set Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the word data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes SUBC Rw data3 38 n O 2 SUBC Rw RWm 30 nm 2 SUBC Rw Rw 38 n 11ii 2 SUBC Rw Rwj 38 n 10ii 2 SUBC mem reg 34 RR MM MM 4 SUBC reg data16 36 RR 4 SUBC reg mem 32 RR MM MM 4 User s Manual 6
146. 110 512 256 2048 1024 111 1024 512 4096 2048 Table 12 3 Example for Timer 3 Frequencies and Resolutions f MHz T3l BPS1 fr KHz rra us 40 7 10 9 77 102 4 40 0 01 10000 0 1 50 0 00 6250 0 16 50 4 11 195 31 5 12 50 7 10 12 20 81 97 User s Manual 12 9 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit This formula also applies to T3 in Gated Timer Mode and to the auxiliary timers T2 and T4 in Timer Mode and Gated Timer Mode BPS1 T3l T3IRQ MCB02028 d Figure 12 4 Block Diagram of Core Timer T3 in Timer Mode Timer 3 in Gated Timer Mode Gated Timer Mode for core Timer T3 is selected by setting bitfield T3M in register T3CON to 010g or 011g Bit T3M 0 T3CON 3 selects the active level of the gate input The same options for the input frequency are available in Gated Timer Mode as for the Timer Mode However the input clock to the timer in this mode is gated by the external input line T3IN Timer T3 External Input an associated port pin should be configured as input User s Manual 12 10 V 1 6 2001 08 7 fi User s Manual nrineon Aide C166S V1 SubSystem General Purpose Timer Unit BPS1 TSI T3IRQ MCB02029 d Figure 12 5 Block Diagram of Core Timer T3 in Gated Timer Mode If T3M 010p the timer is enabled when T3IN shows a low level A high level at this line sto
147. 12 31 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem General Purpose Timer Unit Table 12 11 Timer 6 Input Parameter Selection Timer and Gated Timer Modes T6l Prescaler for f Prescaler for foak Prescaler for fa Prescaler for feik BPS2 00 BPS2 01 BPS2 10 BPS2 11 100 64 32 256 128 101 128 64 512 256 110 256 128 1024 512 111 512 256 2048 1024 Timer 6 in Gated Timer Mode Gated Timer Mode for core Timer T6 is selected by setting bitfield T6M in register T6CON to 010 or 011g Bit T6M 0 T6CON 3 selects the active level of the gate input In Gated Timer Mode the same options for the input frequency as for the Timer Mode are available However in this mode the input clock to the timer is gated by the external input line T6IN BPS2 T6l gt T6OFL Prescaler 1 0 MUX T6OUT T6OTL 1 gt I6IRQ MCB02029 e Figure 12 19 Block Diagram of Core Timer T6 in Gated Timer Mode If T6M 0 0 the timer is enabled when T6IN shows a low level A high level at this line stops the timer If T6M O 1 line T6IN must have a high level to enable the timer Additionally the timer can be turned on or off by software using bit T6R The timer will run only if T6R is set and the gate is active It will stop if either T6R is cleared or the gate is inactive Note A transition of the gate signal at line T
148. 16 bit Long Address seg 16 bit segment offset 24 bit Physical Address Figure 3 10 Overriding the DPP Mechanism User s Manual 3 57 V 1 6 2001 08 e Infineon technologies 3 6 2 3 Long Addressing Mode User s Manual C166S V1 SubSystem Central Processing Unit The long addressing mode uses a 16 bit constant value encoded in the instruction format which specifies the data page offset and the DPP The long addressing mode is referred to by the mnemonic mem Table 3 13 Long addressing mode Mnemonic Physical Address Scope of Access mem DPPO mema3FFF y any word or byte DPP1 mema3FFFy DPP2 mema3FFFy DPP3 mema3FFFy mem pag mema3FFF y any word or byte mem seg mem any word or byte Note The long addressing mode may be used with the DPP overriding mechanism EXTP R and EXTS R User s Manual 3 58 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 6 2 4 Indirect Addressing Modes These addressing modes can be considered as a combination of short and long addressing modes This means that a long 16 bit address is provided indirectly by the contents of a word GPR that is specified directly by a short 4 bit address Rw 0 to 15 There are indirect addressing modes which add a constant value to the GPR contents before the long 16 bit address is calculated Other indirect addressing modes can
149. 2 1 0 0 0 0 0 01 0 DPP2PN r r r r r r rw DPP3 Data Page Pointer 3 SFR FE06 03 Reset value 0003 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 DPP3PN r r r r r r rw Field Bits Type Description DPPxPN 9 0 rw Data Page Number of DPP Specifies the data page selected via DPP Note In a non segmented memory mode the whole DPP register is still used for the calculation of the physical 24 bit address A DPP register can be updated via any instruction that is capable of modifying an SFR Note Due to the internal instruction pipeline a new DPP value is not usable for the operand address calculation of the instruction immediately following the instruction updating the DPPx register User s Manual 3 56 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 6 2 2 DPP Override Mechanism in the C166S The C166S provides an override mechanism to temporarily bypass the DPP addressing scheme The EXTP R and EXTS R instructions override this addressing mechanism Instruction EXTP R replaces the contents of the DPP register while instruction EXTS R concatenates the complete 16 bit long address with the specified segment base address The overriding page or segment may be specified directly as a constant pag seg or via a word GPR Rw EXTP R I5 14 13 16 bit Long Address ipag 14 bit page offset 24 bit Physical Address EXTS R
150. 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description PERO 0 rw XPeripheral Enable Control for XCS1 0 XPeripheral disabled 1 XPeripheral enabled PER1 1 rw XPeripheral Enable Control for XCS2 0 XPeripheral disabled 1 XPeripheral enabled PER2 2 rw XPeripheral Enable Control for XCS3 0 XPeripheral disabled 1 XPeripheral enabled PER3 3 rw XPeripheral Enable Control for XCS4 0 XPeripheral disabled 1 XPeripheral enabled User s Manual 8 36 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface Field Bits Type Description PER4 4 rw XPeripheral Enable Control for XCS5 0 XPeripheral disabled 1 XPeripheral enabled PER5 5 rw XPeripheral Enable Control for XCS6 0 XPeripheral disabled 1 XPeripheral enabled PERx 15 6 rw XPeripheral Enable Control for XCSx x 7 16 0 XPeripheral disabled 1 XPeripheral enabled 8 7 1 XBUS Access Control In C166S up to six configurable address ranges with according bus definitions can be programmed for XBUS peripherals including memories Address ranges and thus address mapping of memories or peripherals on XBUS are controlled with the address selection registers XADRSx The respective bus type definitions are controlled with registers XBCONx The XADRS registers are defined as follows XADRS1 2 3 4
151. 2CON Timer 2 Control Register Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T2 T2 T2 T2 T2 T2 T2 CH EDG IR 0 T2R T2M T2I RDIR DIR E DIS RC UDE UD rh rwh rwh rw r w IW w rw rw rw T4CON Timer 4 Control Register Reset value 0000p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T4 T4 T4 T4 T4 T4 T4 CH EDG IR 0 T4R T4M TAI RDIR DIR E DIS RC UDE UD rh rwh rwh rw r w IW w o rw rw rw Field Bits Typ Description Tx 15 0 rwh Timer x Contains the current value of Timer x User s Manual 12 16 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem General Purpose Timer Unit Field Bits Typ Description Txl 2 0 rw Timer x Input Parameter Selection Timer Mode see Table 12 7 for encoding Gated Timer Mode see Table 12 7 for encoding Counter Mode see Table 12 8 for encoding Incremental Interface Mode see Table 12 9 for encoding TxM 5 3 rw Timer x Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 100 Reload Mode 101 Capture Mode 110 Incremental Interface Mode Rotation Detection Mode 111 Incremental Interface Mode Edge Detection Mode TxR 6 rw Timer x Run Bit 0 Timer Counter x stops 1 Timer Counter x runs TxUD 7 rw Timer x Up Down Control when TXUDE 0 0 Counts Up 1 Counts D
152. 2H ESFR b 994 IRQ73 Interrupt Control Register 00004 IRQ74IC F134 ESFR b 9Ay IRQ74 Interrupt Control Register 00004 User s Manual 4 35 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Memory Organization Table 4 3 SFR ESFR Table ordered by name cont d Name Physical Type 8 bit Description Reset Address Addr Value 2 IRQ75IC F136H ESFR b 9By IRQ75 Interrupt Control Register 0000 IRQ76IC F138H ESFR b 9Cy IRQ76 Interrupt Control Register 00004 IRQ77IC F13Ay ESFR b 9Dy IRQ77 Interrupt Control Register 0000y IRQ78IC F13Cy ESFR b 9Ey RQ78 Interrupt Control Register 0000y IRQ79IC F13Ey ESFR b 9Fy IRQ79 Interrupt Control Register 0000 IRQ80IC F140y ESFR b AO IRQ8O0 Interrupt Control Register 00004 IRQ81IC F142 ESFR b Aly 1RQ81 Interrupt Control Register 00004 IRQ821C F144 ESFR b A2 IRQ82 Interrupt Control Register 00004 IRQ83IC F146y ESFR b A3y IRQ83 Interrupt Control Register 0000 IRQ84IC F148 ESFR b A4y IRQB84 Interrupt Control Register 0000 IRQ85IC F14Ay ESFR b A5y IRQ85 Interrupt Control Register 00004 IRQ86IC F14Cy ESFR b A6y IRQ86 Interrupt Control Register 0000 IRQ87IC F14Ey ESFR b A7 IRQ87 Interrupt Control Register 00004 IRQ88IC F150y ESFR b A8y IRQ88 Interrupt Control Register 0000 IRQ89IC F152H ESFR b A9y IRQ89 Interrupt Control Register 00004 IRQ90IC F154y ESFR b AA
153. 3 4 6 7 See Section 3 4 6 6 See Section 3 4 6 3 The Byte Word Transfer bit BWT of the PECCx register selects whether a byte or a word is to be moved during a PEC service cycle and defines an increment step size for the pointer s to be modified The Increment Control Field INC of the PECCx register defines when either one or both of the PEC pointers have to be incremented after the PEC transfer If the pointers are not to be modified INC 00p the respective channel will always move data from the same source to the same destination 2 lt 3 4 User s Manual 3 37 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 4 6 3 Short Transfer Mode If the short transfer mode is enabled by the PT flag PT 2 0 in the PEC control register PECOx the PEC Transfer Count Field COUNT of the PECCx controls directly the action of the respective PEC channel The contents of the bitfield COUNT may specify a certain number of PEC transfers unlimited transfers or no PEC service at all a If the PEC transfer counter COUNT value is set to 00y the normal interrupt requests are processed instead of PEC data transfers and the corresponding PEC channel remains idle b Continuous data transfers are selected by setting the bitfield COUNT to FF In this case COUNT is not decremented by the transfers and the respective PEC channel can serve unlimited number of PEC
154. 308 to Not directly supported 1 797E 308 long double 8 2 225E 308 to Not directly supported 1 797E 308 near pointer 2 16 14bits WORD depending on memory model far pointer 4 14bits 16k in any Not directly supported page huge pointer 4 24bits 16M Not directly supported shuge pointer 4 24bits 16M but Not directly supported arithmetic is done 16 bit wide User s Manual 3 69 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 7 2 Constants In addition to the powerful addressing modes the C166S instruction set also supports word wide or byte wide immediate constants For an optimum utilization of the available code storage these constants are represented in the instruction formats by either 3 4 8 or 16 bits The short constants are always zero extended while the long constants are truncated if necessary to match the data format required for the particular operation see table below Table 3 18 Constant formats Mnemonic Word Operation Byte Operation data3 0000y data3 00y data3 data4 0000 data4 00y data4 data8 0000 data8 data8 data16 data16 data16 FFy mask 0000 mask mask Note Immediate constants are always signified by a leading 3 7 3 The 16 bit Adder Subtracter Barrel Shifter and the 16 bit Logic Unit All standard arithmetic and logical operations are performed by a 1
155. 3H Data Page Pointer 3 10 bits 0003 CSP FEO8y 044 Code Segment Pointer 00004 8 bits not directly writable MDH FEOC 10604 Multiply Divide High Word 0000y MDL FEOE 07y Multiply Divide Low Word 0000y CP FE10y 08H Context Pointer FCOOy SP FE12y 09 Stack Pointer FCOOy STKOV FE14 OAH Stack Overflow Register FAO0y STKUN FE16y 0By Stack Underflow Register FCOO0y MDCb FFOEy 874 Multiply Divide Control Register 0000 PSWb FF10y 88H Program Status Word 0000y SYSCON FF12 894 System CPU Control Register er ZEROSb FF1ICy 8Ey Constant Value 0 s Register read only 00004 ONESb FF1Ey 8Fy Constant Value 1 s Register read only FFFFy TFRb FFAC D6y Trap Flag Register 00004 1 vy defined by implemented CPU version 2 YYYY defined by reset and system configuration User s Manual 3 94 V 1 6 2001 08 e Infineon technologies 3 10 4 User s Manual C166S V1 SubSystem Central Processing Unit Register Overview C166S Interrupt and Peripheral Event Controller The following table lists all xSFRs which are implemented in the C166S Interrupt and Peripheral Event Controller Table 3 23 Register Overview C166S Interrupt and Peripheral Event Controller Register Name Register Description Module Block PECSNO PEC Pointer O Segment Address Reg PEC Pointer PECSN1 PEC Pointer 1 Segment Address Reg PEC Pointer PECSN PEC Pointer Segment Address Reg
156. 4 FO24 y XPERCON ESFR 124 XBUS Peripheral Control 0000 Register F026 ESFR 134 FO28y ESFR 144 FO2Ay ESFR 154 FO2Cy ESFR 164 FO2Ey ESFR 174 User s Manual 4 12 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value FO30y ESFR 18 F032 ESFR 194 FO34 y ESFR 1Ay F036 ESFR 1By FO38 y ESFR 1Ch FO3A y ESFR 1Dy F03C ESFR 1Ey FO3E y ESFR 1F F040 ESFR 20 F042 ESFR 21y F044 ESFR 224 F046 ESFR 234 F048 ESFR 244 FO4Ay ESFR 254 F04C4 ESFR 264 FO4Ey ESFR 27 FO50 y ESFR 28 F052 ESFR 294 F054 ESFR 2Ay FO56y ESFR 2By F058 ESFR 2Cy FO5Ay ESFR 2Dy FO5Cy ESFR 2E FO5Ey ESFR 2Fy F060 ESFR 30 4 F062 ESFR 314 F064 ESFR 324 F066 ESFR 334 User s Manual 4 13 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value F068 COMDATA ESFR 344 Cerberus Communicati
157. 6 5 4 3 2 1 0 0 BR_VALUE r w 10 3 3 1 Baudrate in Asynchronous Mode For asynchronous operation the baudrate generator provides a clock fgrz with sixteen times the rate of the established baudrate Every received bit is sampled at the 7th 8th and 9th cycle of this clock The clock divider circuitry which generates the input clock for the 13 bit baudrate timer is extended by a fractional divider circuitry that allows adjustment for more accurate baudrate and the extension of the baudrate range User s Manual 10 17 V 1 6 2001 08 pae 1 fi User s Manual UE NN C166S V1 SubSystem Asynchronous Synchronous Serial Interface ASC Field Bits Typ Description BR VALUE 12 0 rw Baudrate Timer Reload Value Reading returns the 13 bit contents of the baudrate timer writing loads the baudrate timer reload value Note BG should only be written if R 0 r 0 15 13 Reserved for future use reading returns 0 writing to these bit positions has no effect The baudrate of the baudrate generator depends on the following bits and register values Input clock fg Selection of the baudrate timer input clock fp y by bits CON_FDE and CON BRS If bit CON FDE 1 fractional divider value of register CON FDV Value of the 13 bit reload register BG The output clock of the baudrate timer with the reload register is the sample clock in the asynchronous modes of the AS
158. 6 bit ALU In case of byte operations signals from bits six and seven of the ALU result are used to control the condition flags Multiple precision arithmetic is supported by a CARRY IN signal to the ALU from previously calculated portions of the desired operation A 16 bit barrel shifter provides multiple bit shifts in a single machine cycle Rotations and arithmetic shifts are also supported 3 7 4 Bit manipulation Unit The C1668 offers a large number of instructions for bit processing The special bit manipulation unit was implemented for this purpose The bit manipulation instructions are for efficient control and testing of peripherals Unlike other microcontrollers the C166S has instructions that provide direct access to two operands in the bit addressable space without requiring them to be moved into temporary locations The same logical instructions that are available for words and bytes can also be used for bits The user can compare and modify a control bit for a peripheral in one instruction Multiple bit shift instructions have been included to avoid long instruction streams of single bit shift operations These instructions require a single machine cycle In addition bit field instructions are able to modify multiple bits of one operand in a single instruction User s Manual 3 70 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit All instructions that manipulate si
159. 66S CPU Control Interrupt PEC Pointer PEC Control Control Registers SRCPO DSTPO PECSNO irqole SRCP1 DSTP1 PECSN1 PEC irqt1C it E Control h H i it it i Registers 1 i SRCP15 DSTP15 PECSN15 PECCO irq1121C A PECCI EOPIC Peripheral Event PECC15 Interrupt Controller PECISNG Request PEC Lines irqd SN Arbitr irq1 Winner irq2 Arbitration 1 Internal Priorization LI irg111 irqx Internal Interrupt PEC Handler irg112 1 End of PEC Interrupt EOPINT is connected to one of the interrupt request lines Therefore only up to 111 interrupt lines are available for peripheral request handling Figure 3 3 Interrupt Arbitration The first arbitration stage compares up to 128 priority levels of interrupt request lines The priority level of each request consists of Interrupt priority LeVeL ILVL and Group priority LeVeL GLVL An interrupt priority level is programmed for each interrupt request line by the 4 bit bitfield ILVL of the respective xxIC register The group priority level is programmed for each interrupt request line by the 2 bit bitfield GL VL and the group extension bit xxGP of the register xxIC Note All interrupt request sources that are enabled and programmed to the same ILVL must have different group priority levels Otherwise an i
160. 6IN does not cause an interrupt request User s Manual 12 32 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem General Purpose Timer Unit Timer 6 in Counter Mode Counter Mode for core Timer T6 is selected by setting bitfield T6M in register TECON to 001g In Counter Mode Timer T6 is clocked by a transition at the external input line T6IN The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at this line Bitfield T6l in control register T6CON selects the triggering transition see Table 12 12 gt T6OFL T6OUT Core Timer T6 gt T6GIRQ T6EUD MCB02030_c Figure 12 20 Block Diagram of Core Timer T6 in Counter Mode Table 12 12 Core Timer T6 Counter Mode Input Edge Selection T6l Triggering Edge for Counter Increment Decrement 000 None Counter T6 is disabled 001 Positive transition rising edge on T6IN 010 Negative transition falling edge on T6IN 011 Any transition rising or falling edge on T6IN 1X X Reserved Do not use this combination User s Manual 12 33 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit The maximum input frequency allowed in Counter Mode is f 4 BPS2 01 To ensure that a transition of the count input signal applied to T6IN is correctly recognized
161. 6S V1 SubSystem The External Bus Interface ADDRSEL3 Address Select Register 3 SFR FE1Cy 0E Reset value 0000y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ rw rw ADDRSEL4 Address Select Register 4 SFR FE1Ey 0Fy Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ rw rw Field Bits Type Description RGSZ 0 3 rw Range Size Selection Defines the size of the address area controlled by the respective BUSCONx ADDRSELx register pair See Table 8 6 below RGSAD 15 4 rw Range Start Address Defines the upper bits of the start address of the respective address area See Table 8 6 below Note There is no register ADDRSELO as register BUSCONO controls all external accesses outside the four address windows of BUSCON4 BUSCON within the complete address space User s Manual 8 27 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V1 SubSystem The External Bus Interface Definition of Address Areas The four register pairs BUSCON4 ADDRSEL4 BUSCON1 ADDRSEL1 allow 4 address areas to be defined within the address space of the C166S Within each of these address areas external accesses can be controlled by one of the four different bus modes independent of each other and of the bus mode specified in register BUSCONO Each ADDRSELx register cuts out an address window withi
162. 8 1 fi User s Manual n Infineon C1 66S V1 SubSystem Memory Organization 4 8 Interrupt Vector Table The interrupt vector table is an instruction table For each interrupt a 4 byte range is reserved for instructions Up to 112 interrupt nodes and 16 trap entries are defined for a C166S V1 SubS H1 based product The subsystem itself allocates 15 interrupt nodes All interrupt nodes above them can be used by the product The table below lists all possible 112 interrupts and traps sorted by the trap number The maximum number of interrupt nodes depends on the subsystem configuration Depending on this configured number of interrupts not all below listed interrupts are available on product level Example PARAM IC NODES 16 gt Only one interrupt source is available on product level irq n i 15 PARAM IC NODES 48 gt 23 interrupt sources are available on product level irqg n i 15 47 Table 4 4 Interrupt Vector Table sorted by trap number Signal Name Source of Interrupt Interrupt Control Vector Trap Interrupt IF Register Location No Reset 0000 00 00044 01 nmi trap n i Non maskable interrupt 00084 024 000Cy 03 a Stack overflow 00104 044 00144 05H Stack underflow 00184 061 001C4 074 Software Break 00204 084 00244 09h Class B Trap 00284 OAH s 002Cy OBy 0030 0C 0034 0Dy User
163. BUS peripheral enabled Enables the XBUS and the according chip select XCSx for the respective address window respective XBUS peripheral selected with XADRSx window Note Enable Disable also is controlled with XPERCON and SYSCON registers BSWCx 11 rw BUSCON Switch Control O Address windows are switched immediately 1 A tristate waitstate is inserted if the next bus cycle accesses a different window than the one controlled by this BUSCON register RDYENx 12 rw READY Enable 0 The bus cycle length is controlled by bit field MCTC only 1 The bus cycle length is controlled by the peripheral using READY signal 1 When the READY function is selected RDYENx 1 only the lower 3 bits of the respective MCTC bit field define the number of inserted waitstates 0 7 while the MSB of bit field MCTC is unused 2 A BUSCON switch waitstate is enabled by bit BUSCONx BSWCx of the address window that is left User s Manual 8 39 V 1 6 2001 08 pae e Infineon technologies User s Manual C166S V1 SubSystem User s Manual 8 40 The External Bus Interface V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Watchdog Timer 9 Watchdog Timer To allow recovery from software or hardware failure the User s Manual provides a Watchdog Timer If the software fails to service this timer before an overflow occurs a watchdog timer reset can be initiated and a watchdog ti
164. C For baudrate calculations this baudrate clock fpr is derived from the sample clock fp y by a division by 16 The ASC fractional divider register FDV contains the 9 bit divider value for the fractional divider asynchronous mode only It is also used for reference clock generation of the autobaud detection unit ia Divider Register Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 FD_VALUE r rw Field Bits Typ Description FD_VALUE 8 0 rw Fractional divider register value FD VALUE contains the 9 bit value of the fractional divider which defines the fractional divider ratio n 512 n 0 511 With n 0 the fractional divider is switched off input output frequency fpiy folks see Figure 10 9 0 15 9 m Reserved for future use reading returns 0 writing to these bit positions has no effect User s Manual 10 18 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Asynchronous Synchronous Serial Interface ASC 13 Bit Reload Register vb eel Divider Clock Sample 22 Cloc 2 BRS FDE BRS Selected Divider 0 0 2 0 1 3 1 X Fractional Divider Figure 10 9 ASC Baudrate Generator Circuitry in Asynchronous Modes Using the fixed Input Clock Divider The baudrate for asynchronous operation of serial channel ASC when using the fixed input clock divid
165. C1 66S V1 SubSystem Central Processing Unit Field Bits Type Description 1111 15 12 Fixed at 1111 STKUN 11 1 rw Modifiable portion of register STKUN Specifies the segment offset address of the upper limit of the system stack 0 0 r Fixed at 0 E STKUN can be updated via any instruction capable of modifying an SFR Note When a value is MOVED into the stack pointer NO check against the overflow registers is performed Fatal error indication treats the stack underflow as a system error and executes associated trap service routine Automatic system stack refilling allows the system stack to be used as a Stack Cache for a bigger external user stack In this case STKUN should be initialized to a value that represents the desired highest Bottom of Stack address Scope of Stack Limit Control The stack limit control by the register pair STKOV and STKUN detects cases where SP is moved outside the defined stack area either by ADD or SUB instructions or by PUSH or POP operations explicit or implicit e g CALL or RET instructions This control mechanism is not triggered and no stack trap is generated when the stack pointer SP is directly updated via MOV instructions or the limits of the stack area STKOV STKUN are changed so that SP is outside the new limits 3 6 3 2 Linear Stack The C166S offers a linear stack option STKSZ 111g in which the system stack may use the comp
166. E Next Instruction count lt count 1 END WHILE count 0 SFR range lt Standard Enable interrupts and traps Description Causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The value of op1 defines the length of the effected instruction sequence CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes EXTR irang2 D1 10 0 2 User s Manual 6 43 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set EXTS Begin EXTended Segment Sequence EXTS Group System Control Instructions Syntax EXTS op1 op2 Source Operand s op1 gt segment number op2 gt 2 bit instruction counter Destination Operand s none Operation count op2 1 lt op2 lt 4 Disable interrupts and Class A traps Data Segment lt 0op1 DO WHILE count z 0 AND Class B Trap Condition z TRUE Next Instruction count lt count 1 END WHILE count 0 Data Page DPPx Enable interrupts and traps Description Overrides the standard DPP addressing scheme of the long and indirect addressing modes for a specified number of instructions During their execution both standard
167. ESFR b 984 IRQ72 Interrupt Control Register 0000 F132 IRQ73IC ESFR b 994 IRQ73 Interrupt Control Register 00004 F1344 IRQ74IC ESFR b 9A IRQ74 Interrupt Control Register 00004 F136y IRQ75IC ESFR b 9By IRQ75 Interrupt Control Register 0000 F138H IRQ76IC ESFR b 9C IRQ76 Interrupt Control Register 0000 F13Ay IRQ771C ESFR b 9D IRQ77 Interrupt Control Register 0000 F13Cy IRQ78IC ESFR b 9Ey IRQ78 Interrupt Control Register 0000 F13Ey IRQ79IC ESFR b 9Fy IRQ79 Interrupt Control Register 0000 F140y IRQ80IC ESFR b A0 IRQ80 Interrupt Control Register 0000 F142 IRQ81IC ESFR b Aly IRQ81 Interrupt Control Register 0000 F144 IRQ821C ESFR b A24 IRQ82 Interrupt Control Register 0000 F146y IRQ83IC ESFR b A34 IRQ83 Interrupt Control Register 0000 F148y IRQ84IC ESFR b A44 IRQ84 Interrupt Control Register 0000 F14Ay IRQ85IC ESFR b A54 IRQ85 Interrupt Control Register 00004 F14Cy IRQ86IC ESFR b A64 IRQ86 Interrupt Control Register 00004 F14Ey IRQ87IC ESFR b A7 IRQ87 Interrupt Control Register 00004 F150y IRQ88IC ESFR b A84 IRQ88 Interrupt Control Register 00004 F152H IRQ89IC ESFR b A94 IRQ89 Interrupt Control Register 0000 F154y IRQ90IC ESFR b AAy IRQ90 Interrupt Control Register 0000 F156y IRQ91IC ESFR b ABy IRQ91 Interrupt Control Register 0000 F158H IRQ92IC ESFR b ACy IRQ92 Interrupt Control Register 0000 F15A IRQ93IC ESFR b AD IRQ93 Interrupt Control Register 0000 F15Cy I
168. FCC8y DSTP1 00 FCE6 SRCP1 00 FCE4y DSTP13 00 FCC6 SRCP13 00 FCC4y DSTPO 00 FCE2 SRCPO 00 FCEO DSTP12 00 FCC2y SRCP12 00 FCCO User s Manual 3 34 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit PECSNx PEC Segment Pointer SFR H H Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSTSNx SRCSNx rw rw Field Bits Type Description DSTSNx 15 8 rw Destination Pointer Segment Address of Channel X Destination Address bits 23 16 SRCSNx 7 0 rw Source Pointer Segment Address of Channel x Source Address bits 23 16 User s Manual 3 35 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 4 6 2 PEC Control Registers Each PEC channel is controlled by the respective PEC channel Control register PECCx and a set of source and destination pointers SRCPx DSTPx and PECSNx where x stands for the PEC channel number The PECCx registers control the arbitration priority level assigned to the PEC channels and specifies the action to be performed PECCx PEC Channel Control Register SFR u u Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PT E PLEV CL INC BWT COUNT rw rw rw rw rw rw rwh Field Bits Type Description PT 15 rw Transfer Mode 0 Short Transfer
169. GERIT Rd OR ERRec ipse Eg ds 1 1 1 1 The Members of the 16 bit Microcontroller Family 1 2 1 2 Summary of Basic Features naana aaea 1 3 2 System Overview ooooocccco ens 2 1 2 1 Basic CPU Concepts and Mega Core seus 2 2 2 1 1 High Instruction Bandwidth Fast Execution 2 2 2 1 2 High Function 8 bit and 16 bit Arithmetic and Logic Unit 2 3 2 1 3 Extended Bit Processing and Peripheral Control 2 4 2 1 4 Consistent and Optimized Instruction Formats 2 5 2 1 5 Programmable Multiple Priority Interrupt and PEC System 2 6 2 2 The C166S System Resources o oooooooooo eee 2 7 2 2 1 Memory TOSS cuo ead nedari EROR ww EE Du Edd 2 7 2 2 2 External Bus Interface 0 2 0 2 cee es 2 8 2 2 3 The On chip Peripheral Blocks ooooooooooo 2 8 2 2 3 1 Asynchronous Synchronous Serial Channel ASCO 2 9 2 2 3 2 High Speed Synchronous Serial Channel SSCO 2 10 2 2 3 3 General Purpose Timer Unit GPT12E 2 10 2 2 4 Parallel Ports PPOMS iius sss bre nr kRalwRenrackhi n br a esos 2 11 2 2 5 Periodic Wakeup from Idle or Sleep Mode 2 12 2 2 6 OCDS and JTAG ccsrvsorscracinsprarispesla jairo 2 12 2 2 7 Core Control Block CCB 3a ia cR REV ens RR CER a 2 12 2 2 8 Clock Generation Unit CGU 0 0 0 0 cee 2 14 2 2 9 On chip Bootstrap Loader
170. Group Arithmetic Instructions Syntax ADDC opt op2 Source Operand s op1 op2 gt WORD Destination Operand s op1 gt WORD Operation op1 op1 op2 C Description Performs a 2 s complement binary addition of the source operand specified by op2 the destination operand specified by op1 and the previously generated carry bit The sum is then stored in op1 This instruction can be used to perform multiple precision arithmetic CPU Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero and previous Z flag was set Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in the word data type Cleared otherwise C Set if a carry is generated from the most significant bit of the word data type Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes ADDC Rw data3 18 n 0 B ADDC Rw RWm 10 nm 2 ADDC Rw Rw 18 n 11ii 2 ADDC Rw Rwj 18 n 10ii 2 ADDC mem reg 14 RR MM MM 4 ADDC reg data16 16 RR HH 4 ADDC reg mem 12 RR MM MM 4 User s Manual 6 4 V 1 6 2001 08 1 fi User s Manual nrineon M os C166S V1 SubSystem Detailed Instruction Set ADDCB Integer Addition with Carry ADDCB Group Arithmetic Instructions Syntax ADDCB op op2 Source Operand s op
171. Hz module clock Interrupt generation Ona transmitter empty condition On areceiver full condition Onan error condition receive phase baudrate transmit error User s Manual 11 1 V 1 6 2001 08 m User s Manual Infineon C166S V1 SubSystem High Speed Synchronous Serial Interface SSC Figure 11 1 shows all funtional relevant interfaces associated with the SSC Kernel Kernel Clock Control Address ae Decoder mM PEDIR Interrupt MW Ro Control TIRQ BPI Module Product Interface Interface Figure 11 1 SSC Interface Diagram Figure 11 2 shows all of the registers associated with the SSC Kernel Control Registers Data Registers CON CON Control Register BR Baudrate Timer Reload Register TB Transmit Buffer Register HB Receive Buffer Register Figure 11 2 SSC Kernel Registers All SSC registers are located in the SFR ESFR memory space The respective SFR addresses can be found in list of SFRs User s Manual 11 2 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem High Speed Synchronous Serial Interface SSC 11 2 General Operation The SSC supports full duplex and half duplex synchronous communication up to 30 MBaud 60 MHz module clock The serial clock signal can be generated by the SSC itself Master Mode or can be received from an external master Slave Mode Data width shift direction clock polarity and phase ar
172. IN can be selected to trigger the capture function or transitions on input T3IN User s Manual 12 39 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit or input T3EUD or both inputs T3IN and T3EUD The active edge is controlled by bitfield Cl in register T5CON The maximum input frequency for the capture trigger signal at CAPIN is 2 BPS2 015 To ensure that a transition of the capture trigger signal is correctly recognized its level should be held for at least one fy cycle BPS2 01 before it changes When Timer T3 capture trigger is enabled CT3 is set register CAPREL captures the contents of T5 upon transitions of the selected input s These values can be used to measure input signals of T3 This is useful for example when T3 operates in Incremental Interface Mode to derive dynamic information speed or acceleration from the input signals When a selected transition at the external input line CAPIN is detected the contents of auxiliary Timer T5 are latched into register CAPREL and interrupt request line CRIRQ is driven at high level With the same event Timer T5 can be cleared to 0000y This option is controlled by bit T5CLR in register T5CON If T5CLR is cleared the contents of Timer T5 are not affected by a capture If T5CLR is set Timer T5 is cleared after the current timer value has been latched into register CAPREL Note Bit T5SC only controls w
173. Interrupt Control Register 0000 FF98y IRQ34IC SFR b CC IRQ34 Interrupt Control Register 0000 FF9A y IRQ35IC SFR b CDj IRQ35 Interrupt Control Register 0000 FF9Cy IRQ32IC SFR b CEy IRQ32 Interrupt Control Register 0000 FF9Ey IRQ331C SFR b CFy IRQ33 Interrupt Control Register 0000 FFAOy SFR b DOW FFA2 SFR b Diy User s Manual 4 29 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value FFA4 SFR b D2 FFA6y SFR b D3y FFA8y PECISNC SFR b D4 PEC Interrupt Subnode Control 00004 Register FFAA y SFR b D5 FFAC TFR SFR b D6 Trap Flag Register 00004 FFAE WDTCON SFR b D7y Watchdog Timer Control Register 008xy FFBOy SOCON SFR b D8 Serial Channel 0 Control Register 00004 FFB2y SSCOCON SFR b D9 SSCO Control Register 0000 FFB4 SFR b DA FFB6y SFR b DBy FFB8y SFR b DCy FFBA PECXISNC SFR b DDy PEC Extended Interrupt Subnode 0000 Control Register FFBCy SFR b DEy FFBE y SFR b DFy FFCOy SFR b E0 FFC2H SFR b Ely FFC4y SFR b E2y FFC6H SFR b E3y FFC8y P4 SFR b E4y Port 4 Register 8 bits 004 FFCA DP4 SFR b E5y Port 4 Direction Control Register
174. L may trigger the reload Note When programmed for Reload Mode the respective auxiliary Timer T2 or T4 stops independently of its run flag T2R or T4R Source Edge Select Auxiliary Timer Tx TXIN b4 gt TXIRQ Txl BPS1 T3I m gt Core Timer T3 T3IRQ La T3R 1 x224 MCBO02035 b Figure 12 13 GPT1 Auxiliary Timer in Reload Mode Note Line is affected by over underflow of T3 only but NOT by software modifications of T3OTL Upon a trigger signal T3 is loaded with the contents of the respective timer register T2 or T4 and T2IRQ or T4IRQ is driven high Note When a T3OTL transition is selected for the trigger signal the interrupt request flag T3IR will be set upon a trigger indicating T3 s overflow or underflow Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 User s Manual 12 22 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit The Reload Mode triggered by T3OTL can be used in a number of different configurations Depending on the selected active transition the following functions can be performed If both a positive and a negative transition of T3OTL are selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows This is the standard Reload Mode reload on overflow underflow If either a positiv
175. LO RHO RL7 RH7 reg SFRor GPR in case of a byte operation on an SFR only the low byte can be accessed via reg mem Direct word or byte memory location ndirect word or byte memory location Any word GPR can be used as indirect address pointer except for the arithmetic logical and compare instructions where only RO to R3 are allowed bitaddr Direct bit in the bit addressable memory area bitoff Direct word in the bit addressable memory area data Immediate constant The number of significant bits which can be specified by the user is represented by the respective appendix x mask8 Immediate 8 bit mask used for bit field modifications Multiply and Divide Operations The MDL and MDH registers are implicit source and or destination operands of the multiply and divide instructions Branch Target Addressing Modes cadar Direct 16 bit jump target address Updates the Instruction Pointer Seg Direct 2 bit segment address Updates the Code Segment Pointer rel Signed 8 bit jump target word offset address relative to the Instruction Pointer of the following instruction User s Manual 5 3 V 1 6 2001 08 User s Manual O Infineon technologies C166S V1 SubSystem trap7 Immediate 7 bit trap or interrupt number Extension Operations The EXT instructions override the standard DPP addressing scheme fpag10 Immediate 10
176. Mode 1 Long Transfer Mode EOPINT 14 rw End of PEC Interrupt Selection 0 EOP interrupt with the same level as the PEC transfer is triggered 1 EOP interrupt is serviced by a separate interrupt node with programmable interrupt level EOPIC and interrupt sharing control register PECISNC PLEV 13 12 rw PEC Level Selection This bitfield controls the PEC channel assignment to an arbitration priority level see section below CL 11 rw Channel Link Control 0 PEC channels work independently 1 Pairs of channels are linked together INC 10 9 rw Increment Control Modification of source and destination pointer after PEC transfer 00 No modification 01 Increment of destination pointer DSTPx by 1 BWT 1 or by 2 BWT 0 10 Increment of source pointer SRCPx by 1 BWT 1 or by 2 BWT 0 11 Reserved User s Manual 3 36 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Central Processing Unit Field Bits Type Description BWT 8 rw Byte Word Transfer Selection 0 Transfer a word 1 Transfer a byte COUNT 7 0 rwh PEC Transfer Count Counts PEC transfers and influences the channel s action The long transfer mode is an optional mode If the product does not support the long transfer mode for this specific PEC channel the PT bit is hardwired to zero See Section 3 4 6 3 and Section 3 4 6 4 See Section
177. N 010 Negative transition falling edge on TxIN 0 1 1 Any transition rising or falling edge on TxIN 101 Positive transition rising edge of T3OTL 110 Negative transition falling edge of T3OTL 111 Any transition rising or falling edge of T3OTL Note Only state transitions of T3OTL caused by the overflow underflow of T3 will trigger the counter function of T2 T4 Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 User s Manual 12 20 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit For counter operation an external pin associated with line TxIN must be configured as input The maximum input frequency allowed in Counter Mode is f 8 BPS1 01 To ensure that a transition of the count input signal applied to TxIN is correctly recognized its level should be held for at least 4 fk cycles BPS1 01 before it changes 12 2 3 Timer Concatenation Using T3OTL as a clock source for an auxiliary timer of Block 1 in Counter Mode concatenates core Timer T3 with the respective auxiliary timer Depending on which transition of T3OTL is selected to clock the auxiliary timer this concatenation forms a 32 bit or a 33 bit timer counter e 32 bit Timer Counter If both a positive and a negative transition of TSOTL are used to clock the auxiliary timer this timer is clocked on every overflow underflow of core Timer T3 Thus the tw
178. OE6 ESFR 73y FOE8y ESFR 744 FOEA y ESFR 75y FOEC DCMPSP ESFR 76y Select and Programming 0000 Register for DCMPx FOEEy DCMPDP ESFR 774 Data Programming Register for 00004 DCMPx FOFOy DTREVT ESFR 784 Specifies hardware triggers and 0000 action FOF2y DEXEVT ESFR 794 Specifies action if external break 0000 pin is asserted User s Manual 4 16 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value FOF4y DSWEVT ESFR 7Ay Specifies action if DEBUG 00004 instruction is executed FOF6 reserved ESFR 7By reserved do not use FOF8y DIP ESFR 7Cy Instruction pointer register 0000 FOFA DIPX ESFR 7Dy Instruction pointer register 3000 extension FOFCy DBGSR ESFR 7Ey Debug status register 0000 FOFE reserved ESFR 7Fy reserved do not use F100y DPOL ESFR b 804 POL Direction Control Register 004 F102y DPOH ESFR b 81y POH Direction Control Register 00 F104 DP1L ESFR b 824 P1L Direction Control Register 00 F106y DP1H ESFR b 834 P1H Direction Control Register 00 F108H reserved ESFR b 844 reserved do not use F10Ay reserved ESFR b 85 reserved do not use F10Cy reserved E
179. OH Direction Control Register 00 DPOL F100 ESFR b 804 POL Direction Control Register 00 DP1H F106y ESFR b 834 P1H Direction Control Register 004 DP1L F104y ESFR b 824 P1L Direction Control Register 00 DP4 FFCA SFR b E5y Port4 Direction Control Register 00 DP6 FFCE SFR b E7y Port6 Direction Control Register 00 DPPO FE00 SFR 004 CPU Data Page Pointer O 0000 Register 10 bits DPP1 FEO2 SFR 014 CPU Data Page Pointer 1 0001 y Register 10 bits DPP2 FE044 SFR 024 CPU Data Page Pointer 2 00024 Register 10 bits DPP3 FEO64 SFR 034 CPU Data Page Pointer 3 0003 Register 10 bits DSWEVT FOF4y ESFR 7Ay Specifies action if DEBUG 00004 instruction is executed DTIDR FOD8y ESFR 6Cy Task ID register 0000 DTREVT FOFOy ESFR 784 Specifies hardware triggers and 0000y action EOPIC F180y ESFR b C0y End of PEC Transfer Interrupt 0000 Control Register FDV FEB6y SFR 5B Fractional Divider Register 0000y GPTID FFE6y GPT Identification Register 58xXXH GPTPISEL FE4C SFR 264 GPT Port Input Selection 0000 Register IOSR FO6Cy ESFR 364 Cerberus status register 0000y IRQ15IC F17Ey ESFR b BFy IRQ15 Interrupt Control Register 0000y IRQ16IC FF78y SFR b BCy IRQ16 Interrupt Control Register 0000 User s Manual 4 33 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Memory Organization Table 4 3 SFR ESFR Table ordered by name
180. Product Interrupt Request 58 IRQ58IC 00E8y 3Ay irq_i 59 Product Interrupt Request 59 IRQ59IC OOEC 3By irq_i 60 Product Interrupt Request 60 IRQ60IC OOFO 3Cy irq_i 61 Product Interrupt Request 61 IRQ61IC 0110 444 irq_i 62 Product Interrupt Request 62 IRQ62IC 01144 454 irq_i 63 Product Interrupt Request 63 IRQ63IC 01184 464 irq_i 64 Product Interrupt Request 64 IRQ64IC 0140 50H irq_i 65 Product Interrupt Request 65 IRQ65IC 01444 514 irq_i 66 Product Interrupt Request 66 IRQ66IC 01484 524 irq_i 67 Product Interrupt Request 67 IRQ67IC 014C 53H irq_i 68 Product Interrupt Request 68 IRQ68IC 0150y 544 User s Manual 4 49 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 5 Interrupt Vector Table cont d sorted by signal name Signal Name Source of Interrupt Interrupt Control Vector Trap Interrupt IF Register Location No irq_i 69 Product Interrupt Request 69 IRQ69IC 01544 55H irq_i 70 Product Interrupt Request 70 IRQ70IC 0158 56H irq_i 71 Product Interrupt Request 71 IRQ71IC 015Cy 57H irq_i 72 Product Interrupt Request 72 IRQ721C 0160 58H irq_i 73 Product Interrupt Request 73 IRQ73IC 0164 59h irq_i 74 Product Interrupt Request 74 IRQ74IC 01684 5Ay irq_i 75 Product Interrupt Request 75 IRQ75IC 016Cy 5Bh irq_i 76 Product Interrupt Request 76
181. R xx 4 ORB reg mem 73 RR MM MM 4 User s Manual 6 70 V 1 6 2001 08 1 fi User s Manual nrineon M C166S V1 SubSystem Detailed Instruction Set PCALL Push Word and Call Subroutine Absolute PCALL Group Call Instructions Syntax PCALL op1 op2 Source Operand s opt gt WORD op2 gt 16 bit address offset Destination Operand s none Operation Description Pushes the word specified by operand op1 and the value of the instruction pointer IP onto the system stack and branches to the absolute memory location specified by the second operand op2 Because IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address of the calling routine CPU Flags E Z V C N ES LANA E Set if the value of the pushed operand op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the pushed operand op1 equals zero Cleared otherwise V Not affected Not affected N Set if the most significant bit of the pushed operand op1 is set Cleared otherwise O User s Manual 6 71 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Encoding Mnemonic Format PCALL reg caddr E2 RR MM MM User s Manual 6 72 Detailed Instruction Set Bytes 4 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSyst
182. R 0By XBUS Address Select Register 2 0000 XADRS3 FO18y ESFR 0Cy XBUS Address Select Register 3 00004 XADRS4 FO1Ay ESFR 0Dy XBUS Address Select Register 4 00004 XADRS5 FO1Cy ESFR 0Ey XBUS Address Select Register 5 0000 XADRS6 FO1Ey ESFR 0Fy XBUS Address Select Register 6 00004 XBCON 1 F1144 ESFR b 8Ay XBUS Control register 1 0000 XBCON2 F116 ESFR b 8By XBUS Control register 2 0000 User s Manual 4 41 V 1 6 2001 08 1 fi User s Manual a C166S V1 SubSystem Memory Organization Table 4 3 SFR ESFR Table ordered by name cont d Name Physical Type 8 bit Description Reset Address acer Value XBCON3 F118H ESFR b 8Ch XBUS Control register 3 00004 XBCON4 F11Ay ESFR b 8Dy XBUS Control register 4 0000 XBCON5 F11Cy ESFR b 8Ey XBUS Control register 5 00004 XBCON6 F11Ey ESFR b 8Fy XBUS Control register 6 00004 XPERCON F0244 ESFR 124 XBUS Peripheral Control 0000 Register ZEROS FFICH SFR b 8E Constant Value OsRegister 00004 1 The PDBUS chip select depends on the register type Chip select pd_cs_esfr is used for register types ESFR and ESFR b whereas chip select pd cs sfr valid for register types SFR and SFR b This address is identical to PDBUS address A 8 1 However for address ranges F1E0 to F1FF and FFEO to FFFF there is no 8 bit address but a PDBUS address User s Manual 4 42 V 1 6 2001 0
183. R RRRO 0000 0000 0010 1 KBytes R 0000 RRRR RRRR RROO 0000 0000 0011 2 KBytes R 0000 RRRR RRRR R000 0000 0000 0100 4 KBytes RR 0000 RRRR RRRR 0000 0000 0000 0101 8 KBytes RR 0000 RRRR RRRO 0000 0000 0000 0110 16 KBytes RR 0000 RRRR RROO 0000 0000 0000 0111 32 KBytes RR 0000 RRRR ROOO 0000 0000 0000 1000 64 KBytes RRRR 0000 RRRR 0000 0000 0000 0000 1001 128 KBytes RRRO 0000 RRRO 0000 0000 0000 0000 1010 256 KBytes RROO 0000 RROO 0000 0000 0000 0000 1011 512 KBytes R000 0000 ROOO 0000 0000 0000 0000 11xx reserved Figure 8 14 Address Range and Address Range Start Definition of XADRS1 2 3 4 register The XBCONXx registers are defined as follows XBCONT1 2 3 4 5 6 XBUS Control Register Reset value XXXXy 15 14 13 12 11 10 9 8 7 B 5 4 3 2 1 0 BUS B EN ACT TYP MCTCx rw rw rw rw rw All XBCONx registers are located in the bitaddressable ESFR memory space The respective SFR addresses of XBCON registers can be found in list of SFRs User s Manual 8 38 V 1 6 2001 08 pae e Infineon technologies User s Manual C166S V1 SubSystem The External Bus Interface Field Bits Type Description MCTCx 3 0 rw Memory Cycle Time Control number of wait states See BUSCON BTYPx 7 rw XBUS Type Definition 0 8 bit Demultiplexed Bus 1 16 bit Demultiplexed Bus BUSACTx 10 rw XBUS Active Control 0 XBUS peripheral disabled 1 X
184. RQ106IC FOCC ESFR 66 4 IRQ106 Interrupt Control 0000 Register IRQ1071C FOCE ESFR 674 IRQ107 Interrupt Control 0000 Register IRQ108IC FODOy ESFR 684 1RQ108 Interrupt Control 0000 Register IRQ109IC FOD2y ESFR 694 IRQ109 Interrupt Control 0000y Register IRQ110IC FODA ESFR 6Ay 1RQ110 Interrupt Control 0000 Register IRQ1111C FOD6 y ESFR 6By IRQ111 Interrupt Control 0000 Register MDC FFOE SFR b 874 CPU Multiply Divide Control 0000 Register MDH FEOC SFR 06 CPU Multiply Divide Register 0000 High Word MDL FEOE y SFR 074 CPU Multiply Divide Register 00004 Low Word ONES FF1Ey SFR b 8Fy Constant Value 1sRegister FFFFy POH FF02y SFR b 81 4 Port 0 High Register Upper half OO POL FFOO SFR b 804 _ Port 0 Low Register Lower half OO P1H FFO6y SFR b 183 Port 1 High Register Upper half 00 P1L FF04 SFR b 824 Port 1 Low Register Lower half 00 P4 FFC8y SFR b E44 Port 4 Register 8 bits 00H User s Manual 4 37 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 3 SFR ESFR Table ordered by name cont d Name Physical Type 8 bit Description Reset Address po Value P6 FFCC SFR b E6 Port6 Register 8 bits 00H PECCO FECO SFR 60 PEC Channel 0 Control Register 00004 PECC1 FEC2
185. RQ94IC ESFR b AEy IRQ94 Interrupt Control Register 0000 FI5Ey IRQ95IC ESFR b AF4 IRQ95 Interrupt Control Register 00004 F160y IRQ48IC ESFR b B0y IRQ48 Interrupt Control Register 0000 User s Manual 4 18 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value F162y IRQ49IC ESFR b B1y IRQ49 Interrupt Control Register 0000 F164y IRQ50IC ESFR b B2y IRQ50 Interrupt Control Register 0000 F166y IRQ51IC ESFR b B34 IRQ51 Interrupt Control Register 0000 F168H IRQ52IC ESFR b B44 IRQ52 Interrupt Control Register 0000 F16Ay IRQ5SIC ESFR b B5y IRQ53 Interrupt Control Register 0000 F16Cy IRQ54IC ESFR b B64 IRQ54 Interrupt Control Register 0000 F16Ey IRQ55IC ESFR b B74 IRQ55 Interrupt Control Register 00004 F170y IRQ56IC ESFR b B84 IRQ56 Interrupt Control Register 00004 F1724 IRQ57IC ESFR b B94 IRQ57 Interrupt Control Register 00004 F174 IRQ58IC ESFR b BAy IRQ58 Interrupt Control Register 0000 F176 IRQ59IC ESFR b BB IRQ59 Interrupt Control Register 0000 F178H IRQ60IC ESFR b BCy IRQ60 Interrupt Control Register 0000 F17Ay IRQ40IC ESFR b BD IRQ40 Interrupt Control Register 0000 F17Cy IRQ41IC ESFR b BE
186. Register 0000 FOBCy IRQ98IC ESFR 5Ey IRQ98 Interrupt Control Register 0000 FOBE IRQ99IC ESFR 5Fy IRQ99 Interrupt Control Register 0000 FOCO IRQ100IC ESFR 60 IRQ100 Interrupt Control 00004 Register FOC2 IRQ1011C ESFR 614 IRQ101 Interrupt Control 00004 Register FOC4 IRQ1021C ESFR 624 IRQ102 Interrupt Control 0000 Register FOC6y IRQ103IC ESFR 63 IRQ103 Interrupt Control 0000 Register FOC8y IRQ1041IC ESFR 64 IRQ104 Interrupt Control 0000 Register FOCA IRQ105IC ESFR 65 IRQ105 Interrupt Control 0000 Register User s Manual 4 15 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value FOCC IRQ106IC ESFR 66 IRQ106 Interrupt Control 00004 Register FOCE IRQ107IC ESFR 674 IRQ107 Interrupt Control 0000 Register FODOy IRQ108IC ESFR 68 IRQ108 Interrupt Control 0000 Register FOD2y IRQ109IC ESFR 69 IRQ109 Interrupt Control 0000 Register FODA IRQ110IC ESFR 6Ay IRQ110 Interrupt Control 0000y Register FOD6 y IRQ1111C ESFR 6By IRQ111 Interrupt Control 00004 Register FOD8y DTIDR ESFR 6Cy Task ID register 0000 FODA y ESFR 6Dy FODCy ESFR 6E FODE y ESFR 6Fy FOEO ESFR 704 FOE2y ESFR 71y FOE4y ESFR 724 F
187. Request 54 IRQ54IC 00D8y 36H irq_i 55 Product Interrupt Request 55 IRQ55IC 00DC 37H irq_i 56 Product Interrupt Request 56 IRQ56IC 00E0y 38H irq_i 57 Product Interrupt Request 57 IRQ57IC 00E44 394 irq_i 58 Product Interrupt Request 58 IRQ58IC 00E8y 3Ay irq_i 59 Product Interrupt Request 59 IRQ59IC OOEC 3By irq_i 60 Product Interrupt Request 60 IRQ60IC OOFO 3CH irq_i 40 Product Interrupt Request 40 IRQ40IC 00F4y 3DH irq_i 41 Product Interrupt Request 41 IRQ411C 00F8y 3Ey irq_i 15 Product Interrupt Request 15 IRQ15IC DOFCy 3Fy irq_i 36 Product Interrupt Request 36 IRQ36IC 0100 40H irq_i 37 Product Interrupt Request 37 IRQ37IC 0104 41 irq_i 38 Product Interrupt Request 38 IRQ38IC 0108 424 irq_i 39 Product Interrupt Request 39 IRQ39IC 010Cy 43H irq_i 61 Product Interrupt Request 61 IRQ61IC 0110 444 irq_i 62 Product Interrupt Request 62 IRQ62IC 0114 45H irq_i 63 Product Interrupt Request 63 IRQ63IC 0118 464 per_irq_i 14 ASCO Transmit Buffer SOTBIC 011Cy 47H User s Manual 4 45 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 4 Interrupt Vector Table cont d sorted by trap number Signal Name Source of Interrupt Interrupt Control Vector Trap Interrupt IF Register Location No irq_i 42 Product Interrupt Request 42 IRQ421C 0120 484 irq_i 43 Produc
188. Rw data3 Rw data3 59 2 XORB Rb Rw or 79 2 ORB Rb Rw or Rb Rw or Rb Rw or Rb data3 Rb data3 5A 4 BOR bitaddr bitaddr 7A 4 BXOR bitaddr bitaddr 5B 2 DIVU Rw 7B 2 DIVLU Rw 5C 2 SHL Rw data4 7C 2 SHR Rw data4 5D 2 JMPR cc_NV rel 7D 2 JMPR cc NN rel 5E 2 BCLR bitoff 5 7E 2 BCLR bitoff 7 oF 2 BSET bitoff 5 7F 2 BSET bitoff 7 User s Manual V 1 6 2001 08 Infineon technologies User s Manual C166S V1 SubSystem Instruction Set Hex Num Mnemonic Operands Hex Num Mnemonic Operands code ber of code ber of Bytes Bytes 80 2 CMPI1 Rw data4 AO 2 CMPD1 Rw data4 81 2 NEG Rw Al 2 NEGB Rb 82 4 CMPI1 Rw mem A2 4 CMPD1 Rw mem 83 4 CoXXX XX A3 4 CoXXX XX 84 4 MOV Rw mem A4 4 MOVB Rw mem 85 A5 4 DISWDT 86 4 CMPI1 Rw data16 A6 4 CMPD1 Rw data16 87 4 IDLE A7 4 SRVWDT 88 2 MOV Rw Rw A8 2 MOV Rw Rw 89 2 MOVB Rw Rb A9 2 MOVB Rb Rw 8A 4 JB bitaddr rel AA 14 JBC bitaddr rel 8B AB 2 CALLI cc Rw 8C AC 12 ASHR Rw Rw 8D 2 JMPR cc_C rel or AD 2 JMPR cc_SGT rel cc_ULT rel 8E 2 BCLR bitoff 8 AE 2 BCLR bitoff 10 8F 2 BSET bitoff 8 AF 2 BSET bitoff 10 90 2 CMPI2 Rw data4 BO 2 CMPD2 Rw data4 91 2 CPL Rw B1 2 CPLB Rb 92 4 CMPI2 Rw mem B2 4 CMPD2 Rw mem 93 4 B3 4 94 4 MOV mem Rw B4 4 MOVB mem Rw 95 B5 4 EINIT 96 4 CMPI2 Rw data16 B6 4 CMPD2 Rw
189. SFR 33H FE68y SFR 34 User s Manual 4 23 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value FEGA y SFR 35H FE6C y SFR 36H FEGE y SFR 37H FE70y SFR 38H FE72y SFR 39H FE74y SFR 3Ay FE76y SFR 3By FE78y SFR 3Cy FE7Ay SFR 3Dy FE7Cy SFR EN FE7E y SFR 3Fy FE80y SFR 40H FE82y SFR 41y FE84y SFR 424 FE86y SFR 43H FE88 SFR 44y FE8Ay SFR 44y FE8Cy SFR 46H FE8E SFR 47 FE90y SFR 484 FE92y SFR 49 FE94y SFR 4Ay FE96y SFR 4By FE98 SFR 4Cy FE9A y SFR 4Dy FE9C SFR 4E FE9E y SFR 4Fy FEAOy SFR 50H FEA2 SFR 51H User s Manual 4 24 V 1 6 2001 08 pae 1 fi User s Manual a C166S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value FEA4 SFR 52H FEAGy SFR 53H FEA8y SFR 544 FEAAy SFR 55H FEACu SFR 56H FEAE WDT SFR 574 Watchdog Timer Register RO 00004 FEBO SOTBUF SFR 584 Serial Channel 0 Transmit Buffer 00004 Register WO FEB2 SORBUF SFR 594 Serial Channel 0 Receive Buffer 00004 Register RO
190. SFR 614 PEC Channel 1 Control Register 00004 PECC2 FEC4 SFR 62 PEC Channel 2 Control Register 0000 PECC3 FEC6 SFR 63H PEC Channel 3 Control Register 00004 PECC4 FEC8 SFR 644 PEC Channel 4 Control Register 0000 PECC5 FECA SFR 65 PEC Channel 5 Control Register 0000 PECC6 FECC SFR 66 PEC Channel 6 Control Register 00004 PECC7 FECE SFR 674 PEC Channel 7 Control Register 0000 PECC8 FEE8 SFR 744 PEC Channel 8 Control Register 0000 PECC9 FEEA SFR 754 PEC Channel 9 Control Register 0000 PECC10 FEEC SFR 76H PEC Channel 10 Control 0000y Register PECC11 FEEE SFR 774 PEC Channel 11 Control 0000y Register PECC12 FEFSy SFR 7Cy PEC Channel 12 Control 0000y Register PECC13 FEFA SFR 7Dy PEC Channel 13 Control 0000 Register PECC14 FEFC SFR 7E PEC Channel 14 Control 0000 Register PECC15 FEFE SFR 7Fy PEC Channel 15 Control 0000 Register PECISNC FFA8y SFR b D44 PEC Interrupt Subnode Control 0000y Register PECSNO FEDO SFR 684 PEC Segment No Register 0000 PECSN1 FED2 SFR 69 PEC Segment No Register 0000 PECSN2 FED4 SFR 6Ay PEC Segment No Register 0000 PECSN3 FED6 SFR 6By PEC Segment No Register 0000y PECSN4 FED8 SFR 6Cy PEC Segment No Register 0000 User s Manual 4 38 V 1 6 2001 08 1 fi User s Manual a C166S V1 SubSystem Memory Organization Table 4 3 SFR ESFR Table ordered by name cont d
191. SFR b 864 reserved do not use F10Ey reserved ESFR b 87y reserved do not use F110y reserved ESFR b 884 reserved do not use F112 reserved ESFR b 894 reserved do not use F114 y XBCON1 ESFR b 8A XBUS Control register 1 0000 F116y XBCON2 ESFR b 8By XBUS Control register 2 0000 F118y XBCON3 ESFR b 8Cy XBUS Control register 3 0000y F11Ay XBCON4 ESFR b 8Dy XBUS Control register 4 0000 F11C4 XBCON5 ESFR b 8Ey XBUS Control register 5 0000y FP11Ey XBCON6 ESFR b 8Fy XBUS Control register 6 0000 F120y IRQ64IC ESFR b 904 IRQ64 Interrupt Control Register 0000 F122y IRQ65IC ESFR b 914 IRQ65 Interrupt Control Register 0000 F1244 IRQ66IC ESFR b 924 IRQ66 Interrupt Control Register 0000 F126y IRQ67IC ESFR b 934 IRQ67 Interrupt Control Register 00004 User s Manual 4 17 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value F128H IRQ68IC ESFR b 944 IRQ68 Interrupt Control Register 0000 F12Ay IRQ69IC ESFR b 95 IRQ69 Interrupt Control Register 0000 F12Cy IRQ70IC ESFR b 96 IRQ70 Interrupt Control Register 0000 F12bEj IRQ71IC ESFR b 974 IRQ71 Interrupt Control Register 0000 F130y IRQ721C
192. SN6 SFR 6E PEC Segment No Register 0000 FEDE PECSN7 SFR 6Fy PEC Segment No Register 0000 FEEO PECSN8 SFR 70H PEC Segment No Register 0000 FEE2 PECSN9 SFR 714 PEC Segment No Register 00004 FEE44 PECSN10 SFR 72 PEC Segment No Register 0000y FEE6 PECSN11 SFR 734 PEC Segment No Register 0000y FEESy PECC8 SFR 744 PEC Channel 8 Control Register 00004 FEEA PECC9 SFR 75H PEC Channel 9 Control Register 00004 FEEC PECC10 SFR 76H PEC Channel 10 Control Register 0000 FEEE PECC11 SFR 77H PEC Channel 11 Control Register 00004 FEFOy PECXCO SFR 784 PEC Channel 0 Extended Control 00004 Register FEF2y PECXC2 SFR 79 PEC Channel 2 Extended Control 00004 Register FEF4 reserved SFR 7Ay reserved do not use FEF6y reserved SFR 7Bh reserved do not use FEF8y PECC12 SFR 7Cy PEC Channel 12 Control Register 0000 FEFA PECC13 SFR 7Dy PEC Channel 13 Control Register 0000 FEFC PECC14 SFR 7Egu PEC Channel 14 Control Register 0000 FEFE PECC15 SFR 7Fy PEC Channel 15 Control Register 00004 FF00 POL SFR b 180 Port 0 Low Register Lower half 00 FF024 POH SFR b 81y Port O High Register Upper half OO FF04 P1L SFR b 824 Port 1 Low Register Lower half 00y FFO6y P1H SFR b 834 Port 1 High Register Upper half OO FF08y reserved SFR b 844 reserved do not use FFOAy reserved SFR b 185 reserved do not use FFOC BUSCONO SFR b 864 Bus Configurati
193. Set when register MDL or MDH is written via software or when a multiply or divide instruction is executed I 7 6 rwh Internal Machine Status 5 3 The multiply divide unit uses these bits to control 2 1 internal operations Never modify these bits 0 without saving and restoring register MDC When a division or multiplication was interrupted before its completion and the multiply divide unit is required the MDC register must first be saved along with registers MDH and MDL to be able to restart the interrupted operation later and then it must be cleared for the new calculation After completion of the new division or multiplication the state of the interrupted multiply or divide operation must be restored The MDRIU flag is the only portion of the MDC register that might be of interest for the user The remaining portions of the MDC register are reserved for dedicated use by the hardware and should never be modified by the user other than described above Otherwise correct continuation of an interrupted multiply or divide operation cannot be guaranteed Multiplication or division is performed simply by specifying the correct signed or unsigned version of the multiply or divide instruction The result is then stored in register MD The overflow flag V is set if the result of a multiply or divide instruction is greater than 16 bits This flag can be used to determine whether both word halves must be transfe
194. System The External Bus Interface access to the external bus All actions that just require internal resources such as instruction data memory or on chip peripherals may be executed in parallel When the C166S needs access to its external bus while it is occupied by another bus master it demands it via the BREQ output The external bus arbitration is enabled by setting bit HLDEN in register PSW to 1 The three bus arbitration pins HOLD HLDA and BREQ will be controlled automatically by the EBC independent of their I O configuration Bit HLDEN may be cleared during the execution of program sequences in which the external resources are required but cannot be shared with other bus masters In this case the C166S will not answer to HOLD requests from other external masters If HLDEN is cleared while the C166S is in hold state code execution from internal RAM ROM this hold state is left only after HOLD has been deactivated again The current hold state will continue and only the next HOLD request is not answered PSW Processor Status Word SFR FF10y 88 Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HLD EN rw Field Bits Type Description HLDEN 10 rw External Bus Arbitration Control Oy External arbitration disabled ly External arbitration enabled Connecting two C166Ss in this way would require additional logic to combine the
195. T because an internal connection is provided for this option An overflow or underflow of Timer T6 can also be used to clock other timers For this purpose there is the special output line TGOFL User s Manual 12 30 V 1 6 2001 08 e Infineon technologies Timer 6 in Timer Mode Timer Mode for core Timer T6 is selected by setting bitfield T6M in register T6CON to 000g In this mode T6 is clocked with the module clock divided by a programmable prescaler as selected by bitfield T6l The input frequency frg for Timer T6 and its resolution rre are scaled linearly with lower clock frequencies fik as can be seen from the following formula User s Manual C166S V1 SubSystem General Purpose Timer Unit fox MHz seeing lt BPS2 gt 2 16 T6 7 aii NER ENEMEN lt BPS25 2 lt T6l gt 15 Ex MFZ Note lt BPS2 gt represents the prescaler value of the prescaler part controlled by bitfield BPS2 For the values see the bit description in register T6CON BPS2 Tel gt T6OFL gt T6IRQ Core Timer T6 0 MUX T3OUT 1 MCB02028_e Figure 12 18 Block Diagram of Core Timer T6 in Timer Mode Table 12 11 Timer 6 Input Parameter Selection Timer and Gated Timer Modes T6l Prescaler for fak Prescaler for f 4 Prescaler for fa Prescaler for feik BPS2 00 BPS2 01 BPS2 10 BPS2 11 000 4 2 16 8 001 8 4 32 16 010 16 8 64 32 011 32 16 128 64 User s Manual
196. T Service Watchdog Timer SRVWDT Group System Control Instructions Syntax SRVWDT Source Operand s none Destination Operand s none Operation Service Watchdog Timer Description This instruction reloads the high order byte of the Watchdog Timer with a preset value and clears the low byte Once this instruction has been executed the watchdog timer cannot be disabled To insure that this instruction is not accidentally executed it is implemented as a protected instruction CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes SRVWDT A7 58 A7 A7 4 User s Manual 6 91 V 1 6 2001 08 1 fi User s Manual nrineon M a C166S V1 SubSystem Detailed Instruction Set SUB Integer Subtraction SUB Group Arithmetic Instructions Syntax SUB op1 op2 Source Operand s op1 op2 gt WORD Destination Operand s op1 gt WORD Operation op1 lt op1 op2 Description Performs a 2 s complement binary subtraction of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 CPU Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the word data type Clea
197. TE In 2 In i In In 1 lt la branch WRITE BACK In 3 In 2 Inet In In 1 lt branch Machine Cycle Tm Tm 1 Tm 2 Tm 3 Tm 4 Tm 5 User s Manual 3 11 V 1 6 2001 08 1 fi User s Manual E a C166S V1 SubSystem Central Processing Unit Table 3 6 shows a standard conditional branch branch taken and target cached instruction pipeline assuming a fast local memory 0 1 waitstates Table 3 6 Conditional cached branches LM Bus 0 1 waitstate Clock Cycle Ty Ta Ty Ta Ty Ta Ty Ta Ty Ta Ty Ta Address la t Data 32bit la tet la t4 FETCH In In 1 In 2 lt lta lo branch DECODE Ini In In 1 In 1 li lta branch branch EXECUTE In 2 In i In In 1 In 1 lt branch branch WRITE BACK In 3 In 2 Ini In In 1 In 1 branch branch Machine Cycle Tm Tm 1 Tm 2 Tm 3 Tm 4 Tm 5 User s Manual 3 12 V 1 6 2001 08 1 fi User s Manual nrineon M os C166S V1 SubSystem Central Processing Unit 3 3 3 ATOMIC and EXTended Instructions ATOMIC and EXTended instructions ATOMIC EXTR EXTP EXTS EXTPR EXTSR disable the standard and PEC interrupts and class A traps until the completion of the next sequence of instructions The number of instructions in the sequence may vary from 1 to 4 The instruction number is coded in the 2 bit constant field irang2 and takes values from 0 to 3 The EXTended instructions addit
198. Timer T2 T2IC 0088 22H per irg i 3 GPT12E Timer T3 T3IC 008C 23 per irq i 4 P GPT12E Timer T4 T4IC 0090y 244 per irq ib GPT12E Timer T5 T5IC 0094 25H per irq i6 GPT12E Timer T6 T6IC 0098 26 per_irq_i 7 2 GPT12E Capture Reload CRIC 009Cy 27 irq_i 34 Product Interrupt Request 34 IRQ34IC O0A0y 28H irq_i 35 Product Interrupt Request 35 IRQ35IC 00A4 y 294 per irq i 1 112 ASCO Transmit SOTIC 00A8y 2Ay User s Manual 4 44 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 4 Interrupt Vector Table cont d sorted by trap number Signal Name Source of Interrupt Interrupt Control Vector Trap Interrupt IF Register Location No per irq i 12 ASCO Receive SORIC 00AC 2By per_irq 131 ASCO Error SOEIC 00B0y 2Cy per irq i B SSCO Transmit SSCOTIC 00B4 2Dy per irq i 9 SSCO Receive SSCORIC 00B8y 2Ey per_irq_i 10 SSCO Error SSCOEIC 00BCy 2Fy irq_i 48 Product Interrupt Request 48 IRQ48IC 00C0 30y irq_i 49 Product Interrupt Request 49 IRQ49IC 00C4y 31H irq_i 50 Product Interrupt Request 50 IRQ50IC 00C8y 32H irq_i 51 Product Interrupt Request 51 IRQ51IC 00CC 33H irq_i 52 Product Interrupt Request 52 IRQ52IC 00D0 344 irq_i 53 Product Interrupt Request 53 IRQ53IC 00D4 35H irq_i 54 Product Interrupt
199. User s Manual 8 24 V 1 6 2001 08 pae e Infineon technologies User s Manual C166S V1 SubSystem The External Bus Interface and bit field BTYP is loaded with the bus configuration selected via conf rst bustyp i 1 0 Field Bits Type Description MCTC 3 0 rw Memory Cycle Time Control Number of memory cycle time waitstates 0000 15 waitstates Number 15 lt MCTC gt 1111 No waitstates RWDCx 4 rw Read Write Delay Control for BUSCONx 0 With rd wr delay activate command 1 TCL after falling edge of ALE 1 No rd wr delay activate command with falling edge of ALE MTTCx 5 rw Memory Tristate Time Control O 1 waitstate 1 No waitstate BTYP 7 6 rw External Bus Configuration 00 8 bit Demultiplexed Bus 01 8 bit Multiplexed Bus 10 16 bit Demultiplexed Bus 11 16 bit Multiplexed Bus Note For BUSCONO BTYP is defined via conf_rst_bustyp_i 1 0 during reset EWENx 8 rw Early Write Enable O Normal WR signal 1 Early write The WR signal is deactivated and write data is tristated one TCL earlier ALECTLx 9 rw ALE Lengthening Control O Normal ALE signal 1 Lengthened ALE signal BUSACTx 10 rw Bus Active Control O External bus disabled 1 External bus enabled within respective address window ADDRSEL User s Manual 8 25 V 1 6 2001 08 pae e Infineon technologies User s Manual C166S V1 SubSystem The External Bus Interface
200. User s Manual V 1 6 August 2001 C166S V1 SubSystem C166S V1 SubS R1 Microcontrollers Never stop thinking Edition 2001 08 Published by Infineon Technologies AG St Martin Strasse 53 D 81541 M nchen Germany O Infineon Technologies AG 2001 All Rights Reserved Attention please The information herein is given to describe certain components and shall not be considered as warranted characteristics Terms of delivery and rights to technical change reserved We hereby disclaim any and all warranties including but not limited to warranties of non infringement regarding circuits descriptions and charts stated herein Infineon Technologies is an approved CECC manufacturer Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide see address list Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life su
201. V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value FF444 T4CON SFR b A24 GPT Timer 4 Control Register 0000 FF46y T5CON SFR b A3y GPT Timer 5 Control Register 0000 FF48y T6CON SFR b A4y GPT Timer 6 Control Register 0000 FF4A SFR b A54 FF4Ch SFR b A6y FF4E SFR b A7y FF50 SFR b A8y FF52 SFR b A9y FF54y SFR b AAy FF56H SFR b ABy FF58H SFR b ACy FF5Ay SFR b ADy FF5Cy SFR b AE FF5Eg SFR b AFy FF60y T2IC SFR b BOY GPT12E Timer 2 Interrupt Control 0000 Register FF62y T3IC SFR b Bly GPT12E Timer 3 Interrupt Control 00004 Register FF64y T4IC SFR b B2y GPT12E Timer 4 Interrupt Control 0000 Register FF66y T5IC SFR b B3y GPT12E Timer 5 Interrupt Control 00004 Register FF68y T6IC SFR b B4y GPT12E Timer 6 Interrupt Control 00004 Register FF6A CRIC SFR b BSy GPT12E Capture Reload 00004 Interrupt Control Register FF6C SOTIC SFR b B6y ASCO Transmit Interrupt Control 0000 Register FF6E SORIC SFR b B7y ASCO Receive Interrupt Control 0000 Register User s Manual 4 28 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d
202. XBUS write data for write accesses PORT1 Last used external address Last used XBUS address if used for the bus interface if used for the bus interface Port 4 Last used external segment address Last used XBUS segment address on selected pins on selected pins Active external CS signal Inactive high for selected CS corresponding to last used address signals BHE Level corresponding to last external Level corresponding to last XBUS access access ALE Inactive low Pulses as defined for X Peripheral RD Inactive high Inactive high WR WRL Inactive high Inactive high WRH Inactive high Inactive high 8 6 External Bus Arbitration In high performance systems it may be efficient to share external resources such as memory banks or peripheral devices among more than one controller The C166S supports this approach with the possibility to arbitrate the access to its external bus i e to the external devices This bus arbitration allows an external master to request the C166S s bus via the HOLD input The C166S acknowledges this request via the HLDA output and will float its bus lines in this case The CS outputs provide internal pull up devices The new master may now access the peripheral devices or memory banks via the same interface lines as the C166S During this time the C166S can keep on executing as long as it does not need User s Manual 8 31 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 Sub
203. a small fraction of the chip s address space up to 16 MBytes The external bus interface allows access to external peripherals and additional volatile and non volatile memory The external bus interface has a number of possible configurations so it can be tailored to fit perfectly into a given application system Ports amp Direction Control Address Registers Mode Registers Control Registers Alternate Functions A 23 0 EA BREQ CS 4 0 e BHE WRH De RE WR WRL POL POH PORTO Data Registers ODP6 Port 6 Open Drain Control Register P1L P1H PORT1 Data Registers DP6 Port 6 Direction Control Register Port 3 Direction Control Register P6 Port 6 Data Register Port 3 Data Register ADDRSELx Address Range Select Register 1 4 Port 4 Open Drain Control Register BUSCONx Bus Mode Control Register 0 4 Port 4 Data Register SYSCON System Control Register RPOH Port POH Reset Configuration Register Figure 8 1 SFRs and Port Pins Associated with the External Bus Interface Accesses to external memory or peripherals are executed by the integrated External Bus Controller EBC The function of the EBC is controlled via the SYSCON BUSCONx and ADDRSELx registers The BUSCONx registers specify the external bus cycles in terms of address mux demux data width 16 bit 8 bit chip selects and length waitstates READY control ALE RW delay These parameters are used for accesses within a specific address area that is defined via the correspond
204. aa aaan eee eee 10 10 10 3 1 2 Asynchronous Transmission 000000 0 eee eee 10 11 10 3 1 3 Asynchronous Reception 0 0000 eee 10 12 10 3 2 Synchronous Operation llle 10 14 10 3 2 1 Synchronous Transmission 52222024620 06e 402058422452 08 10 15 10 3 2 2 Synchronous Reception sae eee ERIN 10 15 10 3 2 3 Synchronous Timing essa ess oe ea One Gea eee 10 15 10 3 3 Baudrate Generation 0 0 0 0 cee es 10 17 10 3 3 1 Baudrate in Asynchronous Mode 00000 eee 10 17 10 3 3 2 Baudrate in Synchronous Mode ssss 10 21 10 3 4 Hardware Error Detection Capabilities 10 23 10 3 5 Interrupts buosv Leite Sd ud a auth dd leo 10 23 11 High Speed Synchronous Serial Interface SSC 11 1 11 1 Iit oclo NOTI osse be ede RET HEREIN QS E 11 1 11 2 General Operation isse xxr wx OR YE REGE Rx WE XE ER 11 3 11 2 1 Operating Mode Selection lslllllllssselllssn 11 5 11 2 2 Full Duplex Operation 0 cece eee eee 11 10 11 2 3 Half Duplex Operation 0 00 e ee eee 11 13 11 2 4 Continuous Transfers ussicsysrpispcraldrid darte ica res 11 14 11 2 5 Baudrate Generation 2sevss scene ust EX EEE E EESEGG OE ERE ees 11 15 11 2 6 Error Detection Mechanisms 000 eee eee 11 17 12 General Purpose Timer Unit 0000000 5 12 1 12 1 IMTOdUCUON e seasea aara namda ke a aa e ia ras da de br a se 12 1 12 2 Functional Descript
205. able 12 5 for encoding T3M 5 3 rw Timer 3 Mode Control 000 Timer Mode 001 Counter Mode 010 Gated Timer Mode with gate active low 011 Gated Timer Mode with gate active high 100 Reserved Do not use this combination 101 Reserved Do not use this combination 110 Incremental Interface Mode Rotation Detection Mode 111 Incremental Interface Mode Edge Detection Mode T3R 6 rw Timer 3 Run Bit 0 Stops Timer counter 3 1 Runs Timer counter 3 T3UD 7 rw Timer 3 Up Down Control when T3UDE 0 0 Counts up 1 Counts down T3UDE 8 rw Timer 3 External Up Down Enable 0 Counting direction is internally controlled by software 1 Counting direction is externally controlled by line T3EUD User s Manual 12 6 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit Field Bits Typ Description TSOE 9 rw Overflow Underflow Output Enable 0 T3 overflow underflow cannot be externally monitored via T3IN 1 T3 overflow underflow may be externally monitored via T3IN T3OTL 10 rwh Timer 3 Overflow Toggle Latch Toggles on each overflow underflow of T3 Can be set or reset by software BPS1 12 11 rw Timer Block Prescaler 1 The maximum input frequency 00 Timer Block 1 is fy 8 01 Timer Block 1 is fo 4 10 Timer Block 1 is fy 32 11 Timer Block 1 is fox 16 T3EDGE 13 rwh Timer 3 Edge Detection The bit is set on each successful edge detection
206. acK OVerflow STKOV and STacK UNderflow STKUN are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow Hardware detection of the selected memory space is placed at the internal memory decoders and allows the user to specify any address directly or indirectly and obtain the desired data without using temporary registers or special instructions For Special Function Registers 1024 Bytes of the address space are reserved The standard Special Function Register area SFR uses 512 bytes while the Extended Special Function Register area ESFR uses the other 512 bytes E SFRs are wordwide registers which are used for controlling and monitoring functions of the different on chip units Unused E SFR addresses are reserved for future members of the C166 family with enhanced functionality An optional Local Memory is provided for both code and data storage This memory area is connected to the CPU via a 32 bit wide local memory bus Program execution from Local Memory is the fastest of all possible alternatives The type of the on chip Local Memory Flash ROM SRAM DRAM none depends on the chosen derivative User s Manual 2 7 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem System Overview 2 2 2 External Bus Interface In order to meet the needs of designs where more memory is required than is provided on chip up to 16 MBytes o
207. anipulation Instructions Syntax CMP op1 op2 Source Operand s op1 op2 gt WORD Destination Operand s none Operation op1 op2 Description The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 The flags are set according to the rules of subtraction The operands remain unchanged CPU Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the word data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes CMP Rw data3 48 n O 2 CMP Rw RWm 40 nm 2 CMP Rw Rw 48 n 11ii 2 CMP Rw Rwj 48 n 10ii 2 CMP reg data16 46 RR HH HH 4 CMP reg mem 42 RR MM MM 4 User s Manual 6 25 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set CMPB Integer Compare CMPB Group Boolean Bit Manipulation Instructions Syntax CMPB op1 op2 Source Operand s op1 op2 gt BYTE Destination Operand s none Operation op1 op2 Description The source operand specified by op1 is compared to the source operand
208. ansfer count extension see table below The long transfer mode is only available for PEC channels with an even PEC number Note The channel link mode is independent of the long transfer mode Both modes can be combined Note The PEC Transfer Count Field COUNT of the PECCx register must be set to zero Note Crossing of segment boundaries is not checked during data transfers with long transfer count and is not supported A wrap around occurs when reaching the segment boundary The contents of the bitfield COUNT2 may specify a certain number of PEC transfers or no PEC service at all The 16 bit transfer counter permits servicing up to 65536 byte transfers or up to 32768 word transfers a If the PEC transfer counter COUNT2 value is set to 0000 the normal interrupt requests are processed instead of PEC data transfers and the corresponding PEC channel remains idle b If the bitfield COUNT2 is set to service a specified number of requests by the respective PEC channel it is decremented with each PEC transfer and the request flag is cleared to indicate that the request has been serviced When COUNT2 reaches 0000 it activates the ISR that has the same priority level EOPINT 0 or triggers the EOP ISR with a different priority level EOPINT 1 When COUNT2 is decremented from 0001 y to 0000 after a data transfer the request flag will be 1 The long transfer mode is an optional mode for PEC channels with an even number
209. arantees that only the intended bit s is are affected by the write back operation Note If a conflict occurs between a bit manipulation generated by hardware and an intended software access the software access has priority and determines the final value of the bit User s Manual 3 71 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 7 5 Multiply and Divide Unit The C166S has a separated multiply and divide unit The multiplication is executed within five machine cycles while a division takes 20 machine cycles The multiply and divide process is interruptible by an interrupt that has a higher priority level than the current CPU level The Multiply Divide High Word Register MDH The non bit addressable Multiply Divide High word register contains the high word of the 32 bit Multiply Divide MD register which is used by the CPU when it performs a multiplication or a division using implicit addressing DIV DIVL DIVLU DIVU MUL MULU After an implicitly addressed multiplication this register represents the high order 16 bits of the 32 bit result For long divisions MDH must be loaded with the high order 16 bits of the 32 bit dividend before the division has started After any division MDH represents the 16 bit remainder A High Word SFR FE0Cy 06y Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDH rwh Fi
210. are using handshake should rely on TIR at the end of a data block to ensure that all data has actually been transmitted Note Refer to the general Interrupt Control Register description for an explanation of the control fields User s Manual 10 24 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem High Speed Synchronous Serial Interface SSC 11 High Speed Synchronous Serial Interface SSC 11 1 Introduction The High Speed Synchronous Serial Interface SSC supports both full duplex and half duplex serial synchronous communication up to 30 MBaud 60 MHz module clock The serial clock signal can be generated by the SSC itself Master Mode or can be received from an external master Slave Mode Data width shift direction clock polarity and phase are programmable This allows communication with SPl compatible devices Transmission and reception of data is double buffered A 16 bit baudrate generator provides the SSC with a separate serial clock signal Features Master and Slave Mode operation Full duplex or half duplex operation Flexible data format Programmable number of data bits 2 to 16 bits Programmable shift direction LSB or MSB shift first Programmable clock polarity idle low or high state for the shift clock Programmable clock data phase data shift with leading or trailing edge of the shift clock Baudrate generation from 30 MBaud to 457 76 Baud 60 M
211. ared Z Set if result equals zero Cleared otherwise V Set if in any cycle of the shift operation a 1 is shifted out of the carry flag Cleared in case of a shift count equal 0 User s Manual 6 88 V 1 6 2001 08 1 fi User s Manual SUE NN C166S V1 SubSystem Detailed Instruction Set C The carry flag is set according to the last least significant bit shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes SHR Rw data4 7C n 2 SHR Rw RWm 6C nm 2 User s Manual 6 89 V 1 6 2001 08 pae 1 fi User s Manual o C166S V1 SubSystem Detailed Instruction Set SRST Software Reset SRST Group System Control Instructions Syntax SRST Source Operand s none Destination Operand s none Operation Software Reset Description This instruction is used to perform a software reset A software reset has the same effect on the microcontroller as an externally applied hardware reset To insure that this instruction is not accidentally executed it is implemented as a protected instruction CPU Flags E Z V C N E Always cleared Z Always cleared V Always cleared C Always cleared N Always cleared Encoding Mnemonic Format Bytes SRST B7 48 B7 B7 4 User s Manual 6 90 V 1 6 2001 08 1 fi User s Manual nrineon M os C166S V1 SubSystem Detailed Instruction Set SRVWD
212. ared at the same time Software should not modify CON BSY as this flag is hardware controlled Transmitter Buffer Register The SSC transmitter buffer register TB contains the transmit data value TB Transmitter Buffer Register Reset value 0000p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TB VALUE rw Field Bits Type Description TB_VALUE 15 0 rw Transmit Data Register Value TB_VALUE is the data value to be transmitted Unselected bits of TB are ignored during transmission Receiver Buffer Register The SSC receiver buffer register RB contains the receive data value RB Receiver Buffer Register Reset value 0000p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RB_VALUE User s Manual 11 8 V 1 6 2001 08 pae 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem High Speed Synchronous Serial Interface SSC Field Bits Type Description RB_VALUE 15 0 h Receive Data Register Value RB contains the received data value RB_VALUE Unselected bits of RB will be not valid and should be ignored Note Only one SSC etc can be master at a given time The transfer of serial data bits can be programmed in many respects The data width can be specified from 2 bits to 16 bits Atransfer may start with either the LSB or the MSB The shift clock may be idle low or idle high The
213. arly address chip select signal CS is renamed in CSxE in the protocol diagrams CSCFG 1 becomes active together with the address and BHE if enabled and remains active until the end of the current bus cycle Early address chip select signals are not latched internally and may toggle intermediately while the address is changing Note CSO provides a latched address chip select directly after reset except for single chip mode when the first instruction is fetched Internal pull up devices hold all CS lines high during reset After the end of a reset sequence the pull up devices are switched off and the pin drivers control the pin levels on the selected CS lines Unselected CS lines will enter the high impedance state and be available for general purpose l O User s Manual 8 14 V 1 6 2001 08 7 fi User s Manual nrineon technologies C1 66S V1 SubSystem The External Bus Interface CLKOUT Normal ALE Cycle 9 Normal ALE N se Extended ALE Cycle 5 Extend ALE i E A NE M 5 Section 8 3 1 ALE Length Control Figure 8 7 Latched and Early Chip Select Segment Address versus Chip Select The external bus interface of the C166S supports many configurations for the external memory By increasing the number of segment address lines the C166S can address a linear address space of 256 KByte 1 MByte 4 MByte 8 MByte or 16 MByte This allows implementation of a large sequential memory area and access to a gr
214. as specified by the source operand op2 Bit 15 is rotated into Bit O and into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used CPU Flags E Z V C N lo pr po ps E Always cleared Z Set if result equals zero Cleared otherwise V Always cleared C The carry flag is set according to the last most significant bit shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared otherwise User s Manual 6 81 V 1 6 2001 08 pae e Infineon technologies Encoding Mnemonic ROL ROL User s Manual User s Manual C166S V1 SubSystem Rw data4 Rw RWm Format 1C Zn OC nm 6 82 Detailed Instruction Set Bytes 2 2 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set ROR Rotate Right ROR Group Shift and Rotate Instructions Syntax ROR op1 op2 Source Operand s op1 gt WORD op2 shift counter Destination Operand s op1 gt WORD Operation count op2 C V DO WHILE count 0 V V v C C op1 0 op1 n op1 n 1 n 0 14 op1 15 C count lt count 1 END WHILE 0 0 Description Rotates the destination word operand op1 right by the number of times as specified by the source operand op2 Bit 0 is rotated into Bit 15 and into the
215. as zero Cleared otherwise C Always cleared N Set if the most significant bit of the quotient stored in the MDL register is set Cleared otherwise Undefined if the V flag is set Encoding Mnemonic Format Bytes DIV Rw 4B nn 2 User s Manual 6 34 V 1 6 2001 08 1 fi User s Manual nrineon M os C166S V1 SubSystem Detailed Instruction Set DIVL 32 by 16 Signed Division DIVL Group Arithmetic Instructions Syntax DIVL op1 Source Operand s op1 gt WORD MD DOUBLEWORD Destination Operand s MD gt DOUBLEWORD Operation MDL MD op1 MDH MD mod op1 Description Performs an extended signed 32 bit by 16 bit division of the two words stored in the MD register by the source word operand op1 The signed quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH CPU Flags E Z V C N o j tj t po E Always cleared Z Set if quotient stored in the MDL register equals zero Cleared otherwise Undefined if the V flag is set V Set if an arithmetic overflow occurred i e the quotient cannot be represented in a word data type or if the divisor op1 was zero Cleared otherwise C Always cleared N Set if the most significant bit of the quotient stored in the MDL register is set Cleared otherwise Undefined if the V flag is set Encoding Mnemonic Format Bytes DIVL Rwy 6B nn 2 Use
216. ask8 data8 4 CALLI CC Rwn 2 BFLDL JMPI MOVIB Rwn Rwm a 2 LE Seg caddr 4 Rwn data4 2 JMP ET pm a 2 CALLR rel 2 wn wm JMPR cc rel 2 p E HA Bus bitaddrQ 4 Rwm Rwn 2 itaddr q re Rwn Rwm 2 NE Ran mh NS wn wm PCALL reg caddr 4 reg data16 2 4 POP reg 2 Rwn Rwm td16 i 4 PUSH Rwm d16 Rwn 4 RETP Rwn mem 4 m m Rwn 4 SCXT reg m 6 d reg mem 4 9 MOVBS Rwn Rbm 2 TRAP trap7 2 MOVBZ reg mem i ATOMIC irang2 2 mem reg EXTR EXTS Rwm irang2 2 EXTP Rwm irang2 2 EXTSR seg irang2 4 EXTPR pag irang2 4 NOP 2 SRST IDLE 4 RET PWRDN RETI SRVWDT RETS DISWDT EINIT 1 Byte oriented instructions suffix B use Rb instead of Rw not with Rwn 2 Byte oriented instructions suffix B use data8 instead of data16 User s Manual 5 5 V 1 6 2001 08 Infineon technologies User s Manual C166S V1 SubSystem Instruction Set Summary Instruction Set Mnemonic Description Bytes Arithmetic Operations ADD Rw Rw Add direct word GPR to direct GPR ADD Rw Rw Add indirect word memory to direct GPR ADD Rw Rw Add indirect word memory to direct GPR and post increment source pointer by 2 ADD Rw data3 Add immediate word data to direct GPR 2 ADD reg data16 Add immediate word data to direct register 4 ADD reg mem Add direct word memory to direct register 4 ADD mem reg Add dire
217. ated the slave will shift out the old contents of the shift register which normally is the data received during the last transfer This may lead to corruption of the data on the transmit receive line in half duplex mode open drain configuration if this slave is not selected for transmission This mode requires that slaves not selected for transmission only shift out ones that is their transmit buffers must be loaded with FFFFy prior to any transfer Note A slave with push pull output drivers not selected for transmission will normally have its output drivers switched However in order to avoid possible conflicts or misinterpretations it is recommended to always load the slave s transmit buffer prior to any transfer The cause of an error interrupt request receive phase baudrate transmit error can be identified by the error status flags in control register CON Note In contrast to the error interrupt request line EIR the error status flags CON TE CON RE CON PE and CON BE are not reset automatically upon entry into the error interrupt service routine but must be cleared by software User s Manual 11 18 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem General Purpose Timer Unit 12 General Purpose Timer Unit 12 1 Introduction The General Purpose Timer Unit GPT12E provides very flexible multifunctional timer structures that may be used for timing event counting pulse
218. atus registers etc In this case individual bytes should be selected using BHE and AO Table 8 2 Bus Mode Versus Performance Bus Mode Transfer Rate System Requirements Free lO Speed factor for Lines byte word dword access 8 bit Multiplexed Very low 1 5 3 6 Low 8 bit latch byte bus P1H P1L 8 bit Demultipl Low 1 2 4 Very low no latch byte bus POH 16 bit Multiplexed High 1 5 1 5 3 High 16 bit latch word bus P1H P1L 16 bit Demultipl Very high 1 1 2 Low no latch word bus e Note PORT1 becomes available for general purpose IO when none of the BUSCON registers selects a demultiplexed bus mode PORTOH becomes available for general purpose IO when only the 8 bit demultiplexed bus mode is selected User s Manual 8 11 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface Disable Enable Control for Pin BHE BYTDIS m Bit BYTDIS is provided for controlling the active low Byte High Enable BHE pin The function of the BHE pin is enabled if the BYTDIS bit contains a O Otherwise it is disabled and the pin can be used as a standard l O pin The BHE pin is used implicitly by the EBC to select one of two byte organized memory chips which are connected to the C166S via a word wide external data bus After reset the BHE function is automatically enabled BYTDIS 0 if a 16 bit data bus is selected during reset otherwis
219. ault event detected User s Manual 3 27 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit Field Bits Type Description ILLOPA 2 rwh ILLegal word OPerand Access 0 No illegal word operand access event detected 1 llegal word operand access event detected ILLINA 1 rwh ILLegal INstruction Access 0 No illegal instruction access detected 1 A branch to an odd address has been attempt ILLBUS 0 rwh ILLegal External BUS Access 0 No illegal external bus access detected 1 An external access has been attempted with no bus defined 1 This bit supports bit protection Note The trap service routine must clear the respective trap flag Otherwise a new trap will be requested after exiting the service routine Setting a trap request flag by software causes the same effects as if it had been set by hardware The reset functions hardware software watchdog may be also regarded as a type of trap Reset functions have the highest trap priority trap priority IV The Debug trap has the second highest trap priority trap priority 111 followed by the third highest trap priority traps Class A traps trap priority Il and then by Class B traps trap priority 1 So the Debug trap can interrupt a Class A and B trap and a Class A trap can interrupt a Class B trap The Debug trap is a special kind of interrupt service channel for debug purposes
220. be accessed next switches on its output drivers very fast In systems running on higher frequencies this may lead to a bus conflict switch off delays normally are independent from the clock frequency In such a case an additional waitstate can automatically be inserted when leaving a certain address window i e when the next cycle accesses a different window This waitstate is controlled in the same way as the waitstate when switching from demultiplexed to multiplexed bus mode see Figure 8 6 BUSCON switch waitstates are enabled via bits BSWCx in the BUSCON registers By enabling the automatic BUSCON switch waitstate BSWCx 1 there is no impact on the system performance as long as the external bus cycles access the same address window If the following cycle accesses a different window a waitstate is inserted between the last access to the previous window and the first access to the new window After reset no BUSCON switch waitstates are selected User s Manual 8 10 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem The External Bus Interface External Data Bus Width The EBC can operate on 8 bit or 16 bit wide external memory peripherals A 16 bit data bus uses PORTO while an 8 bit data bus only uses POL the lower byte of PORTO This saves on address latches bus transceivers bus routing and memory related increases in transfer time The EBC can control word accesses on an 8 bit
221. be set if the modulo 2 sum of the 8 data bits is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit CON PEN always OFF in 9 bit data and wake up mode The parity error flag CON PE will be set along with the error interrupt request flag if a wrong parity bit is received The parity bit itself will be stored in bit RBUF 8 User s Manual 10 10 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Asynchronous Synchronous Serial Interface ASC CON M7100g Bit 9 Data Bit D8 CON M7101g Bit 9 Wake up Bit CON M 71115 Bit 9 Parity Bit Figure 10 6 Asynchronous 9 Bit Frames In wake up mode received frames are transferred to the receive buffer register only if the 9th bit the wake up bit is 1 If this bit is O no receive interrupt request will be activated and no data will be transferred This feature may be used to control communication in a multi processor system When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte to identify the target slave An address byte differs from a data byte in that the additional 9th bit is a 1 for an address byte but is a 0 for a data byte so no slave will be interrupted by a data byte An address byte will interrupt all slaves operating in 8 bit data wake up bit mode so each slave can examine the eight LSBs of the received character the a
222. ber of 1 BRS 13 Baudrate Selection 0 Divide clock by reload value constant depending on mode 1 Additionally reduce serial clock to 2 3 Note BRS is don t care if FDE 1 fractional divider selected User s Manual 10 7 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Asynchronous Synchronous Serial Interface ASC Field Bits Typ Description LB 14 rw Loopback Mode Enabled 0 Loopback Mode disabled Standard transmit receive Mode 1 Loopback Mode enabled R 15 rw Baudrate Generator Run Control Bit 0 Baudrate generator disabled ASC inactive 1 Baudrate generator enabled Note BR VALUE should only be written if R 0 User s Manual 10 8 V 1 6 2001 08 User s Manual C166S V1 SubSystem Asynchronous Synchronous Serial Interface ASC technologies 10 3 1 Asynchronous Operation Asynchronous Mode supports full duplex communication in which both transmitter and receiver use the same data frame format and the same baudrate Data is transmitted on line TXD and received on line RXD Figure 10 4 shows the block diagram of the ASC when operating in Asynchronous Mode FDE 13 Bit Reload Register I BR 13 Bit Baudrate Timer 16 Fractional Divider folk fBRT R BRS RIR Receive Int Request TIR Transmit Int Request Serial Port Control TBIR Transmit Buffer Int Request cnn EIR Error Int
223. both signed and unsigned arithmetic is provided through user specifiable branch tests These flags are also preserved automatically by the CPU upon entry into an interrupt or trap routine All targets for branch calculations are also computed in the central ALU A 16 bit barrel shifter provides multiple bit shifts in a single cycle Rotates and arithmetic shifts are also supported User s Manual 2 3 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem System Overview 2 1 3 Extended Bit Processing and Peripheral Control A large number of instructions has been dedicated to bit processing These instructions provide efficient control and testing of peripherals while enhancing data manipulation Unlike other microcontrollers these instructions provide direct access to two operands in the bit addressable space without requiring to move them into temporary flags The same logical instructions available for words and bytes are also supported for bits This allows the user to compare and modify a control bit for a peripheral in one instruction Multiple bit shift instructions have been included to avoid long instruction streams of single bit shift operations These are also performed in a single machine cycle In addition bit field instructions have been provided which allow the modification of multiple bits from one operand in a single instruction High Performance Branch Call and Loop Processing Due to t
224. cc_NE rel or cc_NZ rel TE 2 BCLR bitoff 1 3E 2 BCLR bitoff 3 1F 2 BSET bitoff 1 3F 2 BSET bitoff 3 User s Manual V 1 6 2001 08 Infineon technologies User s Manual C166S V1 SubSystem Instruction Set Hex Num Mnemonic Operands Hex Num Mnemonic Operands code ber of code ber of Bytes Bytes 40 2 CMP Rw Rw 60 2 AND Rw Rw 41 2 CMPB Rb Rb 61 2 ANDB Rb Rb 42 4 CMP reg mem 62 4 AND reg mem 43 4 CMPB reg mem 63 4 ANDB reg mem 44 z 64 4 AND mem reg 45 65 4 ANDB mem reg 46 4 CMP reg data16 66 4 AND reg data16 47 4 CMPB reg data8 67 4 ANDB reg data8 48 2 CMP Rw Rw or 68 2 AND Rw Rw or Rw Rw or Rw Rw or Rw data3 Rw data3 49 2 CMPB Rb Rw or 69 2 ANDB Rb Rw or Rb Rw or Rb Rw or Rb data3 Rb data3 4A 4 BMOV bitaddr bitaddr 6A 4 BAND bitaddr bitaddr 4B 2 DIV Rw 6B 2 DIVL Rw 4C 2 SHL Rw Rw 6C 2 SHR Rw Rw 4D 2 JMPR cc V rel eD 2 JMPR CC N rel 4E 2 BCLR bitoff 4 6E 2 BCLR bitoff 6 4F 2 BSET bitoff 4 6F 2 BSET bitoff 6 50 2 XOR Rw Rw 70 2 OR Rw Rw 91 2 XORB Rb Rb 71 2 ORB Rb Rb 52 4 XOR reg mem 72 4 OR reg mem 53 4 XORB reg mem 73 4 ORB reg mem 54 4 XOR mem reg 74 4 OR mem reg 55 4 XORB mem reg 75 4 ORB mem reg 56 4 XOR reg data16 76 4 OR reg data16 57 4 XORB reg data8 77 4 ORB reg data8 58 2 XOR Rw Rw or 78 2 OR Rw Rw or Rw Rw or Rw Rw or
225. cessed simultaneously additional hardware has been included in the C166S to prevent a loss of performance when dealing with all causal dependencies on instructions in different pipeline stages This extra hardware resolves most of the possible conflicts e g multiple usage of buses in a time optimized way preventing the pipeline dependencies from becoming noticeable to the user in most cases However in some rare cases attention from the programmer is required specifically because the C166S is a pipelined machine User s Manual 3 80 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 8 1 1 General considerations Due to pipeline Read operation performed by next instruction can takes place before a Write operation performed by the earlier instruction While this fact can lead to some general problems an extra CPU hardware the forwarding mechanism deals with the operand read write addresses and also controls the pipeline when needed Especially if there are sequential write and read operations on the same address the read is hold until write is executed Thus in most cases the pipeline behavior is resolved and made transparent So the user is assured that after writing to a location next read from the same location will return the correct result However there are write operations which are changing some important parameters of the system configuration data pages
226. chnologies User s Manual C166S V1 SubSystem Undefined opcode Protection fault Illegal word operand access Illegal instruction access Illegal external bus access Central Processing Unit The Class B traps share the same interrupt node and interrupt vector The bit addressable Trap Flag Register TFR allows a trap service routine to identify the trap that caused the exception The Trap Flag Register TFR Each trap function is indicated by a separate request flag When a hardware trap occurs the corresponding request flag in register TFR is set to 1 TFR Trap Flag Register SFR FFAC D6 Reset value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STK STK UND PRT ILL ILL ILL NM op ur 09 0 0 9 9 lope 0 FLT opa INA BUS rwh rwh rwh r r r r rwh rwh rwh rwh rwh Field Bits Type Description NMI 15 rwh Non Maskable Interrupt flag 0 No non maskable interrupt detected 1 Non maskable interrupt detected STKOF 14 rwh_ STacK OverFlow flag 0 No stack overflow event detected 1 Stack overflow event detected STKUF 13 rwh STacK UnderFlow flag 0 No stack underflow event detected 1 Stack underflow event detected UNDOPC 7 wh UNDefined OPCode 0 No undefined opcode event detected 1 Undefined opcode event detected PRTFLT 3 rwh PRoTection FauLT 0 No protection fault event detected 1 Protection f
227. clock phase the first clock edge generated by the master may already be used to clock in the first data bit Thus the slave s first data bit must already be valid at this time Note On the SSC a transmission and a reception takes place at the same time regardless of whether valid data has been transmitted or received User s Manual 11 12 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V1 SubSystem High Speed Synchronous Serial Interface SSC 11 2 3 Half Duplex Operation In a Half Duplex Mode only one data line is necessary for both receiving and transmitting of data The data exchange line is connected to both the MTSR and MRST pins of each device the shift clock line is connected to the SCLK pin The master device controls the data transfer by generating the shift clock while the slave devices receive it Due to the fact that all transmit and receive pins are connected to the one data exchange line serial data may be moved between arbitrary stations Similar to Full Duplex Mode there are two ways to avoid collisions on the data exchange line only the transmitting device may enable its transmit pin driver the non transmitting devices use open drain output and send only ones Because the data inputs and outputs are connected together a transmitting device will clock in its own data at the input pin MRST for a master device MTSR for a slave By this method any corruptions on the comm
228. combination of CPU and these resources results in the high performance of the members of this controller family 2 2 1 Memory Areas The memory space of the C166S is configured in a Von Neumann architecture which means that code memory data memory registers and I O ports are organized within the same linear address space which covers up to 16 MBytes The entire memory space can be accessed bytewise or wordwise Particular portions of the on chip memory have additionally been made directly bit addressable An up to 3 KByte 16 bit wide internal DPRAM provides fast access to General Purpose Registers GPRs user data variables and system stack The DPRAM may also be used for code A unique decoding scheme provides flexible user register banks in the internal memory while optimizing the remaining RAM for user data The CPU has an actual register context consisting of up to 16 wordwide and or bytewide GPRs at its disposal which are physically located within the on chip RAM area A Context Pointer CP register determines the base address of the active register bank to be accessed by the CPU ata time The number of register banks is only restricted by the available DPRAM space For easy parameter passing a register bank may overlap others A system stack is provided as a storage for temporary data The system stack is also located within the on chip RAM area and it is accessed by the CPU via the stack pointer SP register Two separate SFRs ST
229. ct word register to direct memory 4 ADDB Rb Rb Add direct byte GPR to direct GPR 2 ADDB Rb Rw Add indirect byte memory to direct GPR 2 ADDB Rb Rw Add indirect byte memory to direct GPR and 2 post increment source pointer by 1 ADDB Rb data3 Add immediate byte data to direct GPR 2 ADDB reg data8 Add immediate byte data to direct register 4 ADDB reg mem Add direct byte memory to direct register 4 ADDB mem reg Add direct byte register to direct memory 4 ADDC Rw Rw Add direct word GPR to direct GPR with Carry 2 ADDC Rw Rw Add indirect word memory to direct GPR with Carry 2 ADDC Rw Rw Add indirect word memory to direct GPR with Carry and 2 post increment source pointer by 2 ADDC Rw data3 Add immediate word data to direct GPR with Carry 2 ADDC reg datai6 Add immediate word data to direct register with Carry 4 ADDC reg mem Add direct word memory to direct register with Carry 4 ADDC mem reg Add direct word register to direct memory with Carry 4 ADDCB Rb Rb Add direct byte GPR to direct GPR with Carry 2 ADDCB Rb Rw Add indirect byte memory to direct GPR with Carry 2 ADDCB Rb Rw Add indirect byte memory to direct GPR with Carry and 2 post increment source pointer by 1 ADDCB Rb data3 Add immediate byte data to direct GPR with Carry 2 ADDCB reg data8 Add immediate byte data to direct register with Carry ADDCB reg mem Add direct byte memory to direct register with Carry User s Manual 5 6 V 1 6 2001 08 I
230. ction 8 3 2 Memory Cycle Time Section 8 3 3 Memory Tri State Time Section 8 3 1 ALE Length Control Section 8 2 3 CS Signal Generation 5 6 Figure 8 4 Demultiplexed Bus Write Access User s Manual 8 7 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem CLKOUT Normal ALE Extend ALE 1 Section 8 3 4 Read Write Delay 3 Section 8 3 2 Memory Cycle Time 5 Section 8 3 1 ALE Length Control Section 8 3 3 Memory Tri State Tim 6 Section 8 2 3 CS Signal Generation Nor The External Bus Interface mal ALE C Extended ALE Cycle e Figure 8 5 Demultiplexed Bus Read Access User s Manual 8 8 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface 8 2 3 Switching Among the Bus Modes The EBC allows dynamic switching among different bus modes i e subsequent external bus cycles may be executed in different ways Certain address areas may use an 8 bit or 16 bit data bus or predefined waitstates A change of the external bus characteristics can be initiated in two different ways Reprogramming the BUSCON and or ADDRSEL registers allows the bus mode to be changed for a given address window or changing the size of an address window that uses a certain bus mode Reprogramming makes it possible to use a great number of different address windows more than BUSCONS are available
231. ction Registers SFRs which control the functionality of the peripheral and temporarily store intermediate data results These SFRs are located either within the standard SFR area 00 FE00 00 FFFF or within the extended ESFR area 00 FOO0y 00 F1FFy Each peripheral has an associated set of status flags Interrupt requests are generated by the peripherals based on specific events which occur during their operation e g operation complete error etc For interfacing with external hardware specific pins of the parallel ports are used when an input or output function has been selected for a peripheral During this time the port pins are controlled by the peripheral when used as outputs or by the external hardware which controls the peripheral when used as inputs This is called the alternate input or output function of a port pin in contrast to its function as a general purpose IO pin Peripheral Timing Internal operation of CPU and peripherals is based on the CPU clock fcpu The on chip oscillator derives the CPU clock from the crystal or from the external clock signal The clock signal fppgus which is gated to the peripherals is independent from the clock signal which feeds the CPU During Idle mode the CPU s clock is stopped while the peripherals continue their operation Peripheral SFRs may be accessed by the CPU once per state When an SFR is written to by software in the same state where it is also to be modified b
232. ctions described in the following the assembler provides much more flexibility in writing C166S programs e g by generic instructions and by automatically selecting appropriate addressing modes whenever possible and thus it eases the use of the instruction set For more information about this item please refer to the Assembler manual Operation This part presents a logical description of the operation performed by an instruction as a symbolic formula or a high level language construct The following symbols are used to represent data movement arithmetic or logical operators Diadic operations opX operator opY opX opY is MOVED into opX opX is ADDED to opY opY is SUBTRACTED from opX i opX is MULTIPLIED by opY opX is DIVIDED by opY A opX is logically ANDed with opY V opX is logically ORed with opY opX is logically EXCLUSIVELY ORed with opY opX is COMPARED against opY mod opX is divided MODULO opY User s Manual 5 21 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Monadic operations opX Instruction Set operator opX is logically COMPLEMENTED Parentheses indicate a method of the used operand addressing as follows opX opX opX n opX Specifies the immediate constant value of opX Specifies the contents of opX Specifies the contents of bit n of opX Specifies the contents of the contents of opX
233. ctor Trap Interrupt IF Register Location No irq_i 15 Product Interrupt Request 15 IRQ15IC DOFCy 3Fh irq_i 16 Product Interrupt Request 16 IRQ16IC 0040 104 irq_i 17 Product Interrupt Request 17 IRQ17IC 0044 11 irq_i 18 Product Interrupt Request 18 IRQ18IC 00484 124 irq_i 19 Product Interrupt Request 19 IRQ19IC 004Cy 134 irq_i 20 Product Interrupt Request 20 IRQ20IC 0050 144 irq_i 21 Product Interrupt Request 21 IRQ211C 0054 154 irq_i 22 Product Interrupt Request 22 IRQ221C 00584 164 irq_i 23 Product Interrupt Request 23 IRQ23IC 005Cy 174 irq_i 24 Product Interrupt Request 24 IRQ24IC 0060 184 irq_i 25 Product Interrupt Request 25 IRQ25IC 0064 194 irq_i 26 Product Interrupt Request 26 IRQ26IC 0068 1Ay irq_i 27 Product Interrupt Request 27 IRQ271C 006Cy 1By irq_i 28 Product Interrupt Request 28 IRQ28IC 0070 1Cy irq_i 29 Product Interrupt Request 29 IRQ29IC 00744 1D irq_i 30 Product Interrupt Request 30 IRQ30IC 0078 1Eu irq_i 31 Product Interrupt Request 31 IRQ31IC 007Cy 1Fy irq_i 32 Product Interrupt Request 32 IRQ321C 0080 20H irq_i 33 Product Interrupt Request 33 IRQ33IC 0084 21H irq_i 34 Product Interrupt Request 34 IRQ34IC O0A0y 28H irq_i 35 Product Interrupt Request 35 IRQ35IC 00A4 y 294 irq_i 36 Product Interrupt Request 36 IRQ36IC 0100 404 irq_i 37 Product Interrupt Request 37 IRQ37IC 0104 414 irq_i 38 Product Interrupt Request 38 IRQ38IC 0108 42H irq_i 39 Product Interrupt Request 39 IRQ39IC 010Cy 43H
234. d op2 so that its most significant bit is equal to one If the source operand op2 equals Zero a zero is written to operand op1 and the zero flag is set Otherwise the zero flag is cleared CPU Flags E Z V C N E Always cleared Z Set if the value of the source operand op2 equals zero Cleared otherwise V Always cleared C Always cleared N Always cleared Encoding Mnemonic Format Bytes PRIOR Rw RWm 2B nm 2 User s Manual 6 74 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set PUSH Push Word on System Stack PUSH Group System Stack Instructions Syntax PUSH op1 Source Operand s op1 gt WORD Destination Operand s none Operation tmp op1 SP SP 2 SP tmp Description Moves the word specified by operand op1 to the location in the system stack specified by the Stack Pointer after the Stack Pointer has been decremented by two CPU Flags E Z V C N NENNEN E Set if the value of the pushed operand op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the pushed operand op1 equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the pushed operand op1 is set Cleared otherwise Encoding Mnemonic Format Bytes PUSH reg EC RR 2 User s Manual 6 75 V 1 6 2001 08 pae 1 fi User s Manual o C166S V1 SubSyst
235. d the stack underflow or overflow trap is entered Inside the trap handler a predetermined portion of the internal stack is moved to or from the external stack The amount of data transferred is determined by the average stack space required by routines and the frequency of calls traps interrupts and returns In most cases this will be approximately 1 4 to 1 10 the size of the internal stack Once the transfer is complete the boundary pointers are updated to reflect the newly allocated space on the internal stack Thus the user is free to write code without concern for the internal stack limits Only the execution time required by the trap routines affects user programs The following procedure initializes the controller for usage of the circular stack mechanism 1 Specify the size of the physical system stack area within the DPRAM bitfield STKSZ in register SYSCON 2 Define two pointers that specify the upper and lower boundary of the external stack These values are then tested in the stack underflow and overflow trap routines when moving data 3 Set STKOV to the limit of the defined internal stack area plus six words for the reserved space to store two interrupt entries The internal stack will now fill until the overflow pointer is reached After entry into the overflow trap procedure the top of the stack will be copied to the external memory The internal pointers will then be modified to reflect the newly allocated space After
236. d Instruction Set TRAP Software Trap TRAP Group Call Instructions Syntax TRAP op1 Source Operand s op1 gt 7 bit trap number Destination Operand s none Operation SP SP 2 SP PSW F SYSCON SGTDIS 0 THEN SP SP 2 SP CSP CSP 0 END IF SP SP 2 SP e IP IP zero extended op1 4 Description Invokes a trap or interrupt routine based on the specified operand op1 The invoked routine is determined by branching to the specified vector table entry point This routine has no indication of whether it was called by software or hardware System state is preserved identically to hardware interrupt entry except that the CPU priority level is not affected The RETI Return from Interrupt instruction is used to resume execution after the completion of the trap or interrupt routine The CSP is pushed if the segmentation is enabled This is indicated by the SGTDIS bit of the SYSCON register CPU Flags E Z V C N EGRE ERE E EA E Not affected Z Not affected V Not affected C Not affected N Not affected User s Manual 6 96 V 1 6 2001 08 pae e Infineon technologies Encoding Mnemonic TRAP User s Manual User s Manual C166S V1 SubSystem trap7 Format 9B t tttO 6 97 Detailed Instruction Set Bytes 2 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set
237. d be written to the port register prior to enabling the output drivers in order to avoid undesired transitions on the output pins This applies to single pins as well as to pin groups see examples below OUTPUT ENABLE SINGLE PIN BSET P4 0 Initial output level is high BSET DP4 0 Switch on the output driver OUTPUT ENABLE PIN GROUP BFLDL P4 05H 05H Initial output level is high BFLDL DP4 05H 05H Switch on the output drivers Note When using several BSET pairs to control more pins of one port these pairs must be separated by instructions which do not reference the respective port see Section 3 8 1 Particular Pipeline Effects in chapter The Central Processing Unit Each of these ports and the alternate input and output functions are described in detail in the following subsections 7 2 PORTO The two 8 bit ports POH and POL represent the higher and lower part of PORTO respectively Both halfs of PORTO can be written e g via a PEC transfer without effecting the other half If this port is used for general purpose IO the direction of each line can be configured via the corresponding direction registers DPOH and DPOL POL PORTO Low Register SFR FF00y 80y Reset value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POL POL POL POL POL POL POL POL Ni 6 5 4 3 2 0 s 5 s rw rw rw rw rw rw rw rw
238. d signal line T3OUT Additionally the auxiliary timers T2 and T4 may be concatenated with core Timer T3 or may be used as capture or reload registers for core Timer T3 Concatenation of T3 with other timers is provided through line T3OTL The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer registers T2 T3 or T4 located in the non bitaddressable Special Function Register SFR space When any of the timer registers is written by the CPU in the state immediately before a timer increment decrement reload or capture is to be performed the CPU write operation has priority in order to guarantee correct results From a programmer s point of view the GPT1 block is composed of a set of SFRs as summarized below Those registers which are not part of the GPT1 block are shaded Data Registers Control Registers Interrupt Control T2CONTimer 2 Control Register T2 Timer 2 Register T3CONTimer 3 Control Register T3 Timer 3 Register T4CONTimer 4 Control Register T4 Timer 4 Register T2ICTimer 2 Interrupt Control Register T3ICTimer 3 Interrupt Control Register T4ICTimer 4 Interrupt Control Register Figure 12 2 SFRs associated with Timer Block GPT1 All GPT1 registers are located in the SFR ESFR memory space The respective SFR addresses can be found in list of SFRs User s Manual 12 3 V 1 6 2001 08 technologies User s Manual C166S V1 SubSystem T2 GPT1 Timer T2 Mode Cont
239. dapt to different kind of memories For example this mechanism can be used to Access slower memories Generate a power ramp up phase for flash modules Stall a DRAM access during the refresh cycles Note Additionally the LM Bus provides 16 bit read and write data accesses with and without waitstates to the internal local memory Furthermore read protection is provided by the CPU to protect the internal local memories against illegal data accesses 3 3 1 Branch Target Addressing Modes The target address and the segment of jump or call instructions can be specified by several addressing modes The IP register may be updated using relative absolute or indirect modes The CSP register can be updated only by using an absolute value A special mode is provided to address the interrupt and trap jump vector table which resides in the lowest portion of the code segment 0 Table 3 1 Branch Target Addressing Modes Mnemonic Target Address Target Segment Valid Address Range caddr IP cadar caddr 0000 FFFEy rel IP IP 2 rel rel 00H 7Fy IP IP 2 rel 1 rel 80y FFy Rw IP Rw Rw w 0 15 seg CSP seg seg 0 255 3 trap7 IP 0000y 4 trap7 CSP 00004 trap7 00y 7Fy caddr Specifies an absolute 16 bit code address within the current segment Branches MAY NOT be taken to odd code addresses Therefore the least significant bit of caddr must always
240. data16 97 4 PWRDN B7 4 SRST 98 2 MOV Rw Rw B8 2 MOV Rw Rw 99 2 MOVB Rb Rw B9 2 MOVB Rw Rb 9A 4 JNB bitadar rel BA 4 JNBS bitadar rel 9B 2 TRAP trap7 BB 2 CALLR rel 9C 2 JMPI cc Rw BC 12 ASHR Rw data4 9D 2 JMPR cc NC rel or BD 2 JMPR cc SLE rel cc UGE rel 9E 2 BCLR bitoff 9 BE 2 BCLR bitoff 1 1 9F 2 BSET bitoff 9 BF 2 BSET bitoff 1 1 User s Manual 5 19 V 1 6 2001 08 Infineon technologies User s Manual C166S V1 SubSystem Instruction Set Hex Num Mnemonic Operands Hex Num Mnemonic Operands code ber of code ber of Bytes Bytes CO 2 MOVBZ Rw Rb EO 2 MOV Rw data4 C1 E1 2 MOVB Rb data4 C2 4 MOVBZ reg mem E2 4 PCALL reg caddr C3 4 E3 C4 4 MOV Rw data1 6 E4 MOVB Rw data16 Rw Rb C5 4 MOVBZ mem reg E5 C6 4 SCXT reg data16 E6 4 MOV reg data16 C7 E7 4 MOVB reg data8 C8 2 MOV Rw Rw E8 2 MOV Rw Rw C9 2 MOVB Rw Rw E9 2 MOVB Rw Rw CA 4 CALLA cc addr EA 4 JMPA cc caddr CB 2 RET EB 2 RETP reg CC 2 NOP EC 12 PUSH reg CD 2 JMPR cc_SLT rel ED 2 JMPR cc_UGT rel CE 2 BCLR bitoff 12 EE 2 BCLR bitoff 14 CF 2 BSET bitoff 12 EF 2 BSET bitoff 14 DO 2 MOVBS Rw Rb FO 2 MOV Rw Rw D1 2 ATOMIC or irang2 F1 2 MOVB Rb Rb EXTR D2 4 MOVBS reg mem F2 4 MOV reg mem D3 4 F3 4 MOVB reg mem D4 4 MOV Rw F4 4 MOVB Rb Rw data16 Rw data16 D5 4 MOVBS mem reg F5
241. data16 06 RR 4 ADD reg mem 02 RR MM MM 4 User s Manual 6 2 V 1 6 2001 08 1 fi User s Manual nrineon M a C166S V1 SubSystem Detailed Instruction Set ADDB Integer Addition ADDB Group Arithmetic Instructions Syntax ADDB op1 op2 Source Operand s op1 op2 gt BYTE Destination Operand s op BYTE Operation op1 op1 op2 Description Performs a 2 s complement binary addition of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 CPU Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic overflow occurred i e the result cannot be represented in the byte data type Cleared otherwise C Set if a carry is generated from the most significant bit of the byte data type Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes ADDB Rb data3 09 n 0 2 ADDB Rb RO 01 nm 2 ADDB Rb Rw 09 n 11ii 2 ADDB Rb Rwi 09 n 10ii 2 ADDB mem reg 05 RR MM MM 4 ADDB reg data8 07 RR xx 4 ADDB reg mem 03 RR MM MM 4 User s Manual 6 3 V 1 6 2001 08 1 fi User s Manual nrineon M os C166S V1 SubSystem Detailed Instruction Set ADDC Integer Addition with Carry ADDC
242. ddress The addressed slave will switch to 9 bit data mode such as by clearing bit CON M 0 to enable it to also receive the data bytes that will be coming having the wake up bit cleared The slaves not being addressed remain in 8 bit data wake up bit mode ignoring the following data bytes 10 3 1 2 Asynchronous Transmission Asynchronous transmission begins at the next overflow of the divide by 16 baudrate timer transition of the baudrate clock fgp if bit CON_R is set and data has been loaded into TBUF The transmitted data frame consists of three basic elements Start bit Data field eight or nine bits LSB first including a parity bit if selected Delimiter one or two stop bits Data transmission is double buffered When the transmitter is idle the transmit data loaded in the transmit buffer register TBUF is immediately moved to the transmit shift register thus freeing the transmit buffer for the next data to be sent This is indicated by the transmit Buffer interrupt request line TBIR being activated TBUF may now be loaded with the next data while transmission of the previous data continues User s Manual 10 11 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Asynchronous Synchronous Serial Interface ASC The transmit interrupt request line TIR will be activated before the last bit of a frame is transmitted that is before the first or the second stop bit is shifted out
243. ded by a factor for the baudrate clock 16 in asynchronous modes and 4 in synchronous mode The prescaler is selected by the bits CON_BRS and CON FDE In addition to the two fixed dividers a fractional divider prescaler unit is available in the asynchronous operating modes that allows selection of prescaler divider ratios of n 512 with n 0 511 Therefore the baudrate of ASC is determined by the module clock the content of FDV the reload value of BG and the operating mode asynchronous or synchronous Register BG is the dual function Baudrate Generator Reload register Reading BG returns the contents of the timer BR_VALUE bits 15 13 return zero while writing to BG always updates the reload register bits 15 13 are insignificant An auto reload of the timer with the contents of the reload register is performed each time CON BG is written to However if CON_R is cleared at the time a write operation to CON_BG is performed the timer will not be reloaded until the first instruction cycle after CON_R was set For a clean baudrate initialization CON_BG should be written only if CON _ Ris reset If CON_BG is written while CON Ri is set unpredictable behavior of the ASC may occur during running transmit or receive operations The ASC baudrate timer reload register BG contains the 13 bit reload value for the baudrate timer in Asynchronous and Synchronous modes B det Timer Reload Register Reset value 0000 15 14 13 12 11 10 9 8 7
244. different error conditions Receive Error and Phase Error are detected in all modes Transmit Error and Baudrate Error only apply to Slave Mode When an error is detected the respective error flag is set and an error interrupt request will be generated by activating the EIR line see Figure 11 8 The error interrupt handler may then check the error flags to determine the cause of the error interrupt The error flags are not reset automatically but rather must be cleared by software after servicing This allows servicing of some error conditions via interrupt while the others may be polled by software Note The error interrupt handler must clear the associated enabled error flag s to prevent repeated interrupt requests Bits in Register CON Transmit Receive Error Interrupt EIR Baudrate Figure 11 8 SSC Error Interrupt Control A Receive Error Master or Slave Mode is detected when a new data frame is completely received but the previous data was not read out of the receive buffer register HB This condition sets the error flag CON RE and when enabled via CON REN the error interrupt request line EIR The old data in the receive buffer RB will be overwritten with the new value and is irretrievably lost User s Manual 11 17 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V1 SubSystem High Speed Synchronous Serial Interface SSC A Phase Error Master or Slave Mode is detected
245. displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JNB instruction If the specified bit is set program execution continues normally with the instruction following the JNB instruction CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes JNB bitaddro q rel 9A QU rr q0 4 User s Manual 6 56 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set JNBS Relative Jump if Bit Clear and Set Bit JNBS Group Jump Instructions Syntax JNBS op1 op2 Source Operand s op1 gt BIT op2 gt 8 bit signed displacement Destination Operand s none Operation IF op1 0 THEN 0p1 1 IP IP 2 sign_extend op2 ELSE Next Instruction END IF Description If the bit specified by op1 is clear program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The bit specified by op1 is set allowing implementation of semaphore operations The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JNBS instructi
246. dle Mode IDLE Group System Control Instructions Syntax IDLE Source Operand s none Destination Operand s none Operation Enter Idle Mode Description This instruction causes the part to enter the idle mode In this mode the CPU is powered down while the peripherals remain running It remains powered down until a peripheral interrupt or external interrupt occurs To insure that this instruction is not accidentally executed it is implemented as a protected instruction CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes IDLE 87 78 87 87 4 User s Manual 6 48 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set JB Relative Jump if Bit Set JB Group Jump Instructions Syntax JB op1 op2 Source Operand s op1 gt BIT op2 gt 8 bit signed displacement Destination Operand s none Operation IF op1 1 THEN IP IP 2 sign_extend op2 ELSE Next Instruction END IF Description If the bit specified by op1 is set program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JB instruction If the specif
247. e bit T6UDE is cleared the count direction can be altered by setting or clearing bit T6UD When T6UDE is set line T6EUD is selected to be the controlling source of the count direction However bit T6UD can still be used to reverse the actual count direction as shown in the table below If TGUD is cleared and line T6EUD shows a low level the timer is counting up With a high level at T6EUD the timer is counting down If T6UD is set a high level at line T6EUD specifies counting up and a low level specifies counting down The count direction can be changed whether the timer is running or not Table 12 10 Core Timer T6 Count Direction Control Line T6EUD Bit TEUDE Bit T6UD Count Direction X 0 0 Count Up X 0 1 Count Down 0 1 0 Count Up 1 1 0 Count Down 0 1 1 Count Down 1 1 1 Count Up Note The direction control works the same for core Timer T6 and for auxiliary Timer T5 Timer 6 Overflow Underflow Monitoring An overflow or underflow of Timer T6 will toggle TeOTL in control register T6CON T6OTL can also be set or reset by software Bit T6OE in register TGCON enables the state of TGOTL to be monitored via the external output line T6OUT An associated port pin must be configured as output Additionally T6OTL can be used in conjunction with the timer over underflow as an input for the counter function of auxiliary Timer T5 For this purpose the state of TGOTL does not have to be available at line TOU
248. e instruction be executed WDTCON WDT Control Register SFR FFAEy D7 y Reset value 008X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDT TIM SW WDT WDT WOTREL PRE EN CR R IN rw rw rh rh rw 1 x 0xx1p Bit Function WDTIN Watchdog Timer Input Frequency Select combined with WDTPRE Controls the input clock prescaler WDTR Watchdog Timer Reset Indication Flag SWR Software Reset Indication Flag TIMEN TIMer ENable TIMEN If the TIMEN bit is set only the generation of watchdog timer resets is surpressed after the execution of the DISWDT instruction A watchdog timer overflow event will still be signaled WDTPRE Watchdog Timer Input Prescaler Control combined with WDTIN Controls the input clock prescaler WDTREL Watchdog Timer Reload Value for the high byte of WDT The time period for an overflow of the watchdog timer is programmable in two ways the input frequency to the watchdog timer can be selected via a prescaler controlled by bits WDTPRE and WDTIN in register WDTCON to be fpp 2 fpp 4 fpp 1 28 or fpp 256 the reload value WDTREL for the high byte of WDT can be programmed in register WDTCON User s Manual 9 3 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Watchdog Timer The period Pwpr between servicing the watchdog timer and the next overflow can therefore be determined by the following
249. e Mode the C166S inverts the direction of its HLDA pin and uses it as an input while the master s HLDA pin remains an output This approach does not require any additional glue logic for the bus arbitration see Figure 8 11 below C166S in Slave Mode E SO n O S 3 OR Figure 8 11 Sharing External Resources Using Slave Mode When the bus arbitration is enabled HLDEN 1 the three corresponding pins are controlled automatically by the EBC Normally the respective port direction register bits retain their reset value which is 0 This selects Master Mode Slave Mode is enabled by intentionally switching pin BREQ to output DP6 7 1 Entering the Hold State Access to the C166S s external bus is requested by driving its HOLD input low After synchronizing this signal the C166S will complete a current external bus cycle if any is active release the external bus and grant access to it by driving the HLDA output low During hold state the C166S treats the external bus interface as follows Address and data bus es float to tristate ALE is pulled low by an internal pull down device ee ee Command lines are pulled high by internal pull up devices RD WR WRL BHE WRH CSx outputs are pulled high push pull mode or float to tri state open drain mode User s Manual 8 33 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface Should the C166S req
250. e Watchdog Timer DISWDT instruction after the execution of the EINIT instruction has no effect To insure that this instruction is not accidentally executed it is implemented as a protected instruction CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes EINIT B5 4A B5 B5 4 l User s Manual 6 38 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set EXTP Begin EXTended Page Sequence EXTP Group System Control Instructions Syntax EXTP op1 op2 Source Operand s op1 gt 10 bit page number op2 gt 2 bit instruction counter Destination Operand s none Operation count op2 1 lt op2 lt 4 Disable interrupts and Class A traps Data Page lt op1 DO WHILE count z 0 AND Class B Trap Condition z TRUE Next Instruction count lt count 1 END WHILE count 0 Data Page DPPx Enable interrupts and traps Description Overrides the standard DPP addressing scheme of the long and indirect addressing modes for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The EXTP instruction becomes immediately active such that no additional NOPs are required For any long mem or indirect address in the EXTP instruction sequence the 10 bit page number address bits A23 A14 is not
251. e XOR immediate word data with direct GPR 2 XOR reg data16 Bitwise XOR immediate word data with direct register 4 XOR reg mem Bitwise XOR direct word memory with direct register 4 XOR mem reg Bitwise XOR direct word register with direct memory 4 XORB Rb Rb Bitwise XOR direct byte GPR with direct GPR 2 XORB Rb Rw Bitwise XOR indirect byte memory with direct GPR 2 XORB Rb Rw Bitwise XOR indirect byte memory with direct GPR and 2 post increment source pointer by 1 XORB Rb data3 Bitwise XOR immediate byte data with direct GPR 2 XORB reg data8 Bitwise XOR immediate byte data with direct register 4 XORB reg mem Bitwise XOR direct byte memory with direct register 4 XORB mem reg Bitwise XOR direct byte register with direct memory 4 User s Manual 5 9 V 1 6 2001 08 Infineon technologies User s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary cont d Mnemonic Description Bytes Boolean Bit Manipulation Operations BCLR bitaddr Clear direct bit 2 BSET bitaddr Set direct bit 2 BMOV bitaddr bitaddr Move direct bit to direct bit 4 BMOVN _ bitaddr bitaddr Move negated direct bit to direct bit 4 BAND bitaddr bitaddr AND direct bit with direct bit 4 BOR bitaddr bitaddr OR direct bit with direct bit 4 BXOR bitaddr bitaddr XOR direct bit with direct bit 4 BCMP bitaddr bitaddr C
252. e additional segment address bits A23 19 17 A16 in applications where segmentation is enabled to access more than 64 kBytes of memory Port 6 provides optional bus arbitration signals and chip select signals All port lines that are not used for these alternate functions may be used as general purpose IO lines User s Manual 2 11 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem System Overview 2 2 5 Periodic Wakeup from Idle or Sleep Mode Periodic wakeup from Idle mode or from Sleep mode combines the drastically reduced power consumption in ldle Sleep mode in conjunction with the additional power management features with a high level of system availability External signals and events can be scanned at a lower rate by periodically activating the CPU and selected peripherals which then return to powersave mode after a short time This greatly reduces the system s average power consumption Idle Sleep mode can also be terminated by external interrupt signals 2 2 6 OCDS and JTAG The On Chip Debug Support OCDS provides facilities to the debugger in order to emulate resources and assists in application program debug The main features are real time emulation extended trigger capability including instruction pointer events data events on address and or value external inputs counters chaining of events timers etc software break support break and break before make
253. e channel link interrupt represents a termination interrupt the End of PEC interrupt User s Manual 3 41 V 1 6 2001 08 pae e Infineon technologies User s Manual C166S V1 SubSystem The channel link feature is supported for all PEC channels including the new PEC channels 8 15 The following table shows the channels that can be linked together and Central Processing Unit the channel numbers required to start transfers via linked channels Table 3 8 PEC Channels That Can Be Linked Together Linked PEC Channels PEC PEC Channel Channel A B Linked PEC Start Channel Linked PEC Channels PEC PEC Channel Channel A B Linked PEC Start Channel channel 0 channel 1 channel O channel 8 channel 9 channel 8 channel 2 channel 3 channel 2 channel 10 channel 11 channel 10 channel 4 channel 5 channel 4 channel 12 channel 13 channel 12 channel 6 channel 7 channel 6 channel 14 channel 15 channel 14 The two PEC control registers of a pair are linked to one interrupt control register whereby in this IC register only the even numbered PEC channel is indicated with the priority group bits User s Manual 3 42 V 1 6 2001 08 e Infineon technologies 3 4 6 6 The PEC channels can be assigned to arbitration priority levels All requests with interrupt priority levels 8 to 15 can be associated with the PEC funct
254. e it is disabled BYTDIS 1 It may be disabled if byte access to 16 bit memory is not required and if the BHE signal is not used Segment Address Generation During external accesses the EBC generates a programmable number of address lines on Port 4 which extend the 16 bit address output on PORTO and thus increase the accessible address space The number of segment address lines is selected via conf rst salsel i 1 0 during reset and coded in bit field SALSEL in register RPOH see table below Table 8 3 Decoding of Segment Address Lines SALSEL Segment Address Lines Directly accessible Address Space 11 Two A17 A16 256 KByte Default without pull downs 10 Eight A23 A16 16 MByte Maximum 01 None 64 KByte Minimum 00 Four A19 A16 1 MByte Note The total accessible address space may be increased by accessing several banks that are distinguished by individual chip select lines If Port 4 is used to output segment address lines in most cases the drivers must operate in push pull mode Make sure that OPD4 does not select open drain mode in this case User s Manual 8 12 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface CS Signal Generation During external accesses the EBC can generate a programmable number of CS lines on Port 4 which make it possible to select external peripherals or memory banks directly without requiring an
255. e of integer operations the N flag can be interpreted as the sign bit of the result negative N 1 positive N20 Negative numbers are always represented as the 2 s complement of the corresponding positive number The range of signed numbers extends from 8000 to 7FFFy for the word data type or from 80 to 7Fy for the byte data type For Boolean bit operations with only one operand the N flag represents the previous state of the specified bit For Boolean bit operations with two operands the N flag represents the logical XORing of the two specified bits C Flag After an addition the C flag indicates that a carry from the most significant bit of the specified word or byte data type has been generated After a subtraction or a comparison the C flag indicates a borrow which represents the logical negation of a carry for the addition This means that the C flag is set to 1 if no carry from the Most Significant Bit MSB of the specified word or byte data type has been generated during a subtraction Subtraction is performed by the ALU as a 2 s complement addition The C flag is cleared when this complement addition caused a carry The C flag is always cleared for logical multiply and divide ALU operations because these operations can not cause a carry flag to be set For shift and rotate operations the C flag represents the value of the bit shifted out last If a shift count of zero is specified the C flag will be cleared The C
256. e of the specified bit Always cleared Always cleared Contains the previous state of the specified bit ZO NTITTI User s Manual 6 50 V 1 6 2001 08 pae e Infineon technologies Encoding Mnemonic JBC User s Manual User s Manual C166S V1 SubSystem bitaddro q rel Format AA QQ rr q0 6 51 Detailed Instruction Set Bytes 4 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem JMPA Absolute Conditional Jump Group Jump Instructions Syntax JMPA op1 op2 Source Operand s op1 extended condition code op2 gt 16 bit address offset Destination Operand s none Operation IF op1 1 THEN IP op2 ELSE Next Instruction END IF Description Detailed Instruction Set JMPA If the condition specified by op1 is met a branch to the absolute address specified by op2 is taken If the condition is not met no action is taken and the instruction following the JMPA instruction is executed normally CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes JMPA Xcc caddr EA dOla MM MM 4 User s Manual 6 52 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem JMPI Indirect Conditional Jump Group Jump Instructions Syntax JMPI op1 op2 Source Operand s op1 gt condition code op2 gt 16 bit addre
257. e or a negative transition of T3OTL is selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow Using this single transition mode for both auxiliary timers allows very flexible Pulse Width Modulation PWM One of the auxiliary timers is programmed to reload the core timer on a positive transition of T3OTL the other is programmed for a reload on a negative transition of T3OTL With this combination the core timer is alternately reloaded from the two auxiliary timers The Figure 12 14 shows an example for the generation of a PWM signal using the alternate reload mechanism T2 defines the high time of the PWM signal reloaded on positive transitions and T4 defines the low time of the PWM signal reloaded on negative transitions The PWM signal can be output on line T3OUT if the enable bit T3OE is set Using this method the high and low time of the PWM signal can be varied over a wide range Note T3OTL is accessible via software and may be changed if required to modify the PWM signal However this will NOT trigger the reloading of T3 Note An associated port pin linked to line T3OUT should be configured as output User s Manual 12 23 V 1 6 2001 08 pae C fin n User s Manual Infineon C1 66S V1 SubSystem General Purpose Timer Unit Auxiliary Timer T2 BPS1 T3I 2 T3R Up Down T30E A gt T3IRQ in gt T4IRQ Au
258. e programmable This allows communication with SPl compatible devices Transmission and reception of data is double buffered A 16 bit baudrate generator provides the SSC with a separate serial clock signal The high speed synchronous serial interface can be configured in a very flexible way so it can be used with other synchronous serial interfaces can serve for master slave or multimaster interconnections or can operate compatible with the popular SPI interface Thus the SSC can be used to communicate with shift registers IO expansion peripherals e g EEPROMs etc or other controllers networking The SSC supports half duplex and full duplex communication Data is transmitted or received on lines TXD and RXD normally connected with pins MTSR Master Transmit Slave Receive and MRST Master Receive Slave Transmit The clock signal is output via line MS CLK Master Serial Shift Clock or input via line SS CLK Slave Serial Shift Clock Both lines are normally connoted to pin SCLK These pins are alternate functions of port pins User s Manual 11 3 V 1 6 2001 08 User s Manual C166S V1 SubSystem technologies High Speed Synchronous Serial Interface SSC folk Baudrate Clock 55 CLK Generator Control MS CLK Shift Clock RIR SSC Control Block TIR Register CON EiR Receive Int Request Transmit Int Request Error Int Request Status Control TXD Master RXD Slave Pin E n Control 16 Bit Shift Reg
259. e selected first bit of the transmit data will be placed onto the TXD line on the next clock from the baudrate generator transmission starts only if CON EN 1 Depending on the selected clock phase a clock pulse will also be generated on the MS CLK line At the same time with the opposite clock edge the master latches and shifts in the data detected at its input line RXD This exchanges the transmit data with the receive data Because the clock line is connected to all slaves their shift registers will be shifted synchronously with the master s shift register shifting out the data contained in the registers and shifting in the data detected at the input line After the preprogrammed number of clock pulses via the data width selection the data transmitted by the master is contained in all the slaves shift registers while the master s shift register holds the data of the selected slave In the master and all slaves the content of the shift register are copied into the receive buffer HB and the receive interrupt line RIR is activated A slave device will immediately output the selected first bit MSB or LSB of the transfer data at line RXD when the contents of the transmit buffer are copied into the slave s shift register Bit CON BSY is not set until the first clock edge at SS CLK appears The slave device will not wait for the next clock from the baudrate generator as the master does The reason for this is that depending on the selected
260. eason Port 4 will be switched to this alternate function automatically The number of segment address lines is selected via conf_rst_salsel_i 1 0 SALSEL during reset User s Manual 7 10 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Parallel Ports The table below summarizes the alternate functions of Port 4 depending on the number of selected segment address lines Table 7 2 Alternate Functions of Port 4 Port 4 Std Function Altern Function Altern Function Altern Function Pin SALSEL 01 SALSEL 11 SALSEL 00 SALSEL 10 64 KB 256KB 1 MB 16 MB P4 0 Gen purpose lO Seg Address A16 Seg Address A16 Seg Address A16 P4 1 Gen purpose lO Seg Address A17 Seg Address A17 Seg Address A17 P4 2 Gen purpose lO Gen purpose lO Seg Address A18 Seg Address A18 P4 3 Gen purpose lO Gen purpose lO Seg Address A19 Seg Address A19 P4 4 Gen purpose lO Gen purpose lO Gen purpose IO Seg Address A20 P4 5 Gen purpose lO Gen purpose lO Gen purpose IO Seg Address A21 P4 6 Gen purpose lO Gen purpose lO Gen purpose IO Seg Address A22 P4 7 Gen purpose lO Gen purpose lO Gen purpose IO Seg Address A23 Note Port 4 pins that are not used for segment address output may be used for general Alternate Function Figure 7 6 purpose IO General Purpose Input Output User s Manual Full Segment Addre
261. eat number of external devices using an external decoder By increasing the number of CS lines the C166S can access memory banks or peripherals without external glue logic These two features may be combined to optimize the overall system performance Note If the number of segment address lines and CS lines configured at reset cause overlap e g A18 A16 and CS4 CS0 the segment address line function will take precedence User s Manual 8 15 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface 8 3 Programmable Bus Characteristics Important timing characteristics of the external bus interface have been made user programmable to adapt it to a wide range of external bus and memory configurations with different types of memories and or peripherals The following parameters of an external bus cycle are programmable ALE Control defines the ALE signal length and the address hold time after its falling edge Memory Cycle Time extendable with 1 15 waitstates defines the allowable access time Memory Tri State Time extendable with 1 waitstate defines the time for a data driver to float Read Write Delay Time defines when a command is activated after the falling edge of ALE Note External accesses use the slowest possible bus cycle after reset The bus cycle timing may then be optimized by the initialization software
262. ecify ONLY GPR registers Once the subtraction has completed the operand op1 is incremented by two Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range CPU Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the word data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes CMPI2 Rw data16 96 Fn 4 CMPI2 Rw data4 90 zin 2 CMPI2 Rw mem 92 Fn MM MM 4 User s Manual 6 30 V 1 6 2001 08 1 fi User s Manual o C166S V1 SubSystem Detailed Instruction Set CPL Integer One s Complement CPL Group Arithmetic Instructions Syntax CPL op1 Source Operand s op1 gt WORD Destination Operand s op1 gt WORD Operation op1 op1 Description Performs a 1 s complement of the source operand specified by op1 The result is stored back into op1 CPU Flags E Z V C N E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always
263. econd overflow underflow of core Timer T6 This configuration forms a 33 bit timer 16 bit core timer T6OTL 16 bit auxiliary timer The count directions of the two concatenated timers are not required to be the same This offers a wide variety configurations T6 can operate in Timer Mode Gated Timer Mode or Counter Mode in this case User s Manual 12 38 V 1 6 2001 08 C Infineon User s Manual UE C166S V1 SubSystem General Purpose Timer Unit BPS2 Tel T6R Up Down Edge Select Auxiliary Timer T5 T5IRQ MCB02034 e Up Down Figure 12 22 Concatenation of Core Timer T6 and Auxiliary Timer T5 Note Line is affected by over underflow of T6 only NOT by software modifications of T6OTL Capture Reload Register CAPREL in Capture Mode CAPREL Capture Reload Register Reset value 0000p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAPREL rwh Field Bits Typ Description CAPREL 15 0 rwh Capture Reload Register Value Contains the current value of the CAPREL register This 16 bit register can be used as a capture register for auxiliary Timer T5 This mode is selected by setting bit T5SC in control register T5CON Bit CT3 selects the external input line CAPIN or the input lines T3IN and or T3EUD of Timer T3 as the source for a capture trigger Either a positive a negative or both a positive and a negative transition at line CAP
264. ect Write chip select OoO O Read write chip select User s Manual 8 13 V 1 6 2001 08 1 fi User s Manual nrineon M s C166S V1 SubSystem The External Bus Interface Read or Write Chip Select CS is renamed WRCS or RDCS in the protocol diagrams signals remain active only as long as the associated control signal RD or WR is active This also includes the programmable read write delay Read chip select is activated only for read cycles write chip select is activated only for write cycles and read write chip select is activated for both read and write cycles write cycles are assumed if either of the signals WRH or WRL goes active These modes save external glue logic when accessing external devices such as latches or drivers that have only a single enable input Address Chip Select signals remain active during the complete bus cycle For address chip select signals two generation modes can be selected via bit CSCFG in register SYSCON A latched address chip select signal CS is renamed in CSxL in the protocol diagrams CSCFG 0 becomes active with the falling edge of ALE and becomes inactive at the beginning of an external bus cycle that accesses a different address window No spikes will be generated on the chip select lines and no changes occur as long as locations within the same address window or within internal memory excluding internal bus interface are accessed Ane
265. ect depends on the register type Chip select pd cs esfr is used for register types ESFR and ESFR b whereas chip select pd cs sfr valid for register types SFR and SFR b Y to FFFFy there is no 8 bit address but a PDBUS address This address is identical to PDBUS address A 8 1 However for address ranges F1E0y to F1FFy and FFEO NOTE Reserved addresses are always read as FFFFy except another reset value is explicitly documented in this column However for enabling future enhancements without any compatibility problems this addresses should neither be written nor be used as read value by the software User s Manual 4 31 V 1 6 2001 08 1 fi User s Manual UE NN C166S V1 SubSystem Memory Organization The following table lists all SFRs ESFRs which are implemented in the C166S V1 SubS R1 ordered by their name Table 4 3 SFR ESFR Table ordered by name Name Physical Type 8 bit Description Reset Address Acer Value ADDRSEL1 FE18 SFR OC Address Select Register 1 0000 ADDRSEL2 FE1A SFR OD Address Select Register 2 00004 ADDRSEL3 FE1C SFR OE Address Select Register 3 00004 ADDRSEL4 FE1E SFR OF Address Select Register 4 0000 ASCOID FFE2y ASCO Identification Register 44xxy ASCOPISEL F1B6 SFR b DBy ASCO Port Input Selection 0000 Register BUSCONO FFOCy SFR b 86 Bus Configuration Register 0 0000 BUSCON1 FF14 SFR b 8Ay_ Bus Conf
266. ed for program data or register banking This approach assumes no error but requires a set of control routines see Circular Stack The STacK OVerflow Pointer Register STKOV This non bit addressable STKOV pointer register is compared to the SP register after each operation that pushes data onto the system stack e g PUSH and CALL instructions or interrupts and after each substraction from the SP register If the contents of the SP register is less than the contents of the STKOV pointer register a stack overflow trap will occur STKOV STacK OVerflow Pointer SFR FE14y 0A y Reset value FAO00y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1111 STKOV 0 r rw r User s Manual 3 62 V 1 6 2001 08 1 fi User s Manual nrineon M a C166S V1 SubSystem Central Processing Unit Field Bits Type Description 1111 15 12 Fixed at 1111 STKOV 11 1 rw Modifiable portion of register STKOV Specifies the segment offset address of the lower limit of the system stack 0 0 r Fixed at 0 ms STKOV can be updated via any instruction that is capable of modifying an SFR Note When a value is MOVED into the stack pointer NO check against the overflow registers is performed Fatal error indication treats the stack overflow as a system error and executes associated trap service routine Under these circumstances data in the bottom of the stack may
267. efault configuration in BUSCONO After initializing the active registers they are selected and evaluated automatically by interpreting the physical address No additional switching or selecting is necessary during run time except when more than four address windows plus the default BUSCONO are to be used Switching from demultiplexed to multiplexed bus mode represents a special case The bus cycle is started by activating ALE and driving the address to Port 4 and PORT1 as usual if another BUSCON register selects a demultiplexed bus However in the multiplexed bus modes the address is also required on PORTO In this special case the address on PORTO is delayed by one CPU clock cycle which delays the complete multiplexed bus cycle and extends the corresponding ALE signal see Figure 8 6 User s Manual 8 9 V 1 6 2001 08 p fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface This extra time is required to allow the previously selected device via demultiplexed bus to release the data bus which would be available in a demultiplexed bus cycle demuxed ALE A23 A0 A7 A0 A15 A8 D15 DO A7 A0 A15 A8 D15 DO WR Figure 8 6 Switching from Demultiplexed to Multiplexed Bus Mode Switching between external resources e g different peripherals may create a problem if the previously accessed resource needs some time to switch off its output drivers after a read and if the resource to
268. efined in the standard timing In this case the data output drivers will also be deactivated one TCL earlier This is especially useful in systems that operate on higher CPU clock frequencies and employ external modules memories peripherals etc that switch on their own data drivers very rapidly in response to e g a chip select signal Conflicts between the C166S s and the external peripheral s output drivers can be avoided by selecting early WR for the C166S Note Make sure that the reduced WR low time still meets the requirements of the external peripheral memory Early WR deactivation is controlled via the Early Write EnNable EWENX bits in the BUSCON registers The WR signal will be shortened if bit EWENx is 1 default after reset is a standard WR signal i e EWENXx 0 8 3 6 READY Controlled Bus Cycles For situations in which the programmable waitstates are not enough or the response access time of a peripheral is not constant the C166S has external bus cycles that are terminated via an asynchronous READY input signal In this case the C166S first inserts a programmable number of waitstates 0 7 and then monitors the READY line to determine the actual end of the current bus cycle The external device drives READY low in order to indicate that data have been latched write cycle or are available read cycle User s Manual 8 18 V 1 6 2001 08 User s Manual C166S V1 SubSystem The External Bus Interface
269. eld Bits Type Description MDH 15 0 rwh High part of MD The high order 16 bits of the 32 bit multiply and divide register MD Whenever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control MDC register is set to 1 When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the Interrupt Service Routine ISR the contents of MDH must be saved along with the contents of registers MDL and MDC to avoid erroneous results The Multiply Divide Low Word Register MDL The non bit addressable Multiply Divide Low word register contains the low word of the 32 bit multiply divide MD register which is used by the CPU when it performs a multiplication or a division using implicit addressing DIV DIVL DIVLU DIVU MUL MULU After a multiplication this register represents the low order 16 bits of the 32 bit result For long divisions the MDL register must be loaded with the low order 16 bits of User s Manual 3 72 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit the 32 bit dividend before the division has started After any division MDL represents the 16 bit quotient MDL Multiply Divide Low Word SFR FEOE 07 Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDL r
270. els are set to 1 in their PECCx registers The data transfer of linked channels must always be started always with the even numbered channel of the channel pair If in channel link mode the channel s data block is completely transferred the PEC service request processing is automatically switched to the other PEC channel of the pair CL of the previously active PEC channel is then reset Every channel toggle is indicated to CPU by means of an EOP interrupt This makes it possible to set up multiple buffers for PEC transfers by changing pointer and count values of one channel while the other channel is active Inside the EOP interrupt the Channel Link Control bit CL must be set again before the channel is reactivated or the channel link mode is finished This EOP interrupt is requested indicated and enabled in the respective PEC Interrupt Subnode Control Register PECISNC or PECXISNC Thus all EOP interrupts are controlled with the one EOP interrupt control register EOPIC and therefore with the same interrupt priority level This service request node requests the CPU in case of one or more pending EOP interrupt requests if the respective enable control bit s are set in the according subnode control register and in the interrupt control register EOPIC If CL of the previous PEC channel is set to zero and the count field COUNT 0 or COUNT2 0 dependent on the mode of the active channel is zero as well the whole data transfer is finished and th
271. em Detailed Instruction Set POP Pop Word from System Stack POP Group System Stack Instructions Syntax POP op1 Source Operand s none Destination Operand s op1 gt WORD Operation tmp SP SP SP 2 op1 tmp Description Pops one word from the system stack specified by the Stack Pointer into the operand specified by op1 The Stack Pointer is then incremented by two CPU Flags E Z V C N E Set if the value of the popped word represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the popped word equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the popped word is set Cleared otherwise Encoding Mnemonic Format Bytes POP reg FC RR 2 User s Manual 6 73 V 1 6 2001 08 1 fi User s Manual nrineon M a C166S V1 SubSystem Detailed Instruction Set PRIOR Prioritize Register PRIOR Group Prioritize Instruction Syntax PRIOR op1 op2 Source Operand s op2 gt WORD Destination Operand s op1 gt WORD Operation tmp op2 count 0 DO WHILE tmp 15 1 AND op2 z 0 tmp n tmp n 1 n 15 1 count lt count 1 END WHILE op1 count Description This instruction stores a count value in the word operand specified by op1 This count value indicates the number of single bit shifts required to normalize the word operan
272. em Detailed Instruction Set PWRDN Enter Power Down Mode PWRDN Group System Control Instructions Syntax PWRDN Source Operand s none Destination Operand s none Operation Enter Power Down Mode Description This instruction causes the part to enter the power down mode In this mode all peripherals and the CPU are powered down until the part is externally reset To insure that this instruction is not accidentally executed it is implemented as a protected instruction To further control the action of this instruction the PWRDN instruction is only enabled when the non maskable interrupt pin NMI is in the low state Otherwise this instruction has no effect CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes PWRDN 97 68 97 97 4 l User s Manual 6 76 V 1 6 2001 08 pae User s Manual e Infineon C166S V1 SubSystem Detailed Instruction Set RET Return from Subroutine Group Return Instructions Syntax RET Source Operand s none Destination Operand s none Operation IP lt SP SP SP 2 Description Returns from a subroutine The IP is popped from the system stack CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format RET CB 00 User s Manual 6 77 RET Bytes V 1 6 2001 08 1 fi User s Manua
273. end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the byte data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes NEGB Rb A1 nO 2 User s Manual 6 67 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem NOP No Operation Group Null operation Syntax NOP Source Operand s none Destination Operand s none Operation No Operation Description Detailed Instruction Set NOP This instruction causes a null operation to be performed A null operation causes no change in the status of the flags CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes NOP CC 00 2 User s Manual 6 68 V 1 6 2001 08 1 fi User s Manual nrineon M a C166S V1 SubSystem Detailed Instruction Set OR Logical OR OR Group Logical Instructions Syntax OR op1 op2 Source Operand s op1 op2 gt WORD Destination Operand s op1 gt WORD Operation op1 lt op1 v op2 Description Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 CPU Flags E Set if the value of op2
274. ent of T5 is decremented by 1 before being captured The described deviation is eliminated in the example T5 would now capture 63 99p and the output frequency would be 80 KHz Note The underflow signal of Timer T6 can furthermore be used to clock one ore more timers of other timer units This makes it possible to set compare events based on a finer resolution than that of the external events This connection is accomplished via signal T6OFL User s Manual 12 43 V 1 6 2001 08 _ 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem General Purpose Timer Unit User s Manual 12 44 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem 13 Instruction Index This section lists alphabetically all C166S instructions together with references to respective pages holding the detailed descriptions This helps to quickly find the explanation of any specific core instruction ADD sacarina 6 2 ADOB 2222s 6 3 ADDO Ss viae 6 4 ADDCB 6 5 AND caca REA 6 6 ANDB pia sx dx 6 7 ASHR 6 8 ATOMIC 6 10 BAND 6 11 BCLR 1024404 6 12 BCMP 6 13 BFEDH 6 14 BFLDL cei as 6 15 BMOV 6 16 BMOVN 6 17 BOR rds 204 20d 6 18 BSET ees 6 19 BXOH zz 6 20 CALLA 6 21 CALLI sers 6 22 CALLR 6 23 CALLS 6 24 EMP cue 6 25 CMPB 6 26 CMPD1 6 27 CMPD2 6 28 CMPI1 6 29 CMPI2
275. ented to a value less than the value in the stack overflow register STKOV the STKOF flag in register TFR is set and the CPU will enter the stack overflow trap routine Which IP value will be pushed onto the system stack depends on which operation caused the decrement of the SP When an implicit decrement of the SP is made through a push or call instruction or upon interrupt or trap entry the IP value pushed is the address of the following instruction When the SP is decremented by a subtract instruction the IP value pushed represents the address of the first or second instruction after the instruction following the subtract instruction For recovery from stack overflow there must be enough excess space on the stack for saving the current system state PSW IP and in segmented mode the CSP twice Otherwise a system reset should be generated STacK UnderFlow Trap STKUF Whenever the stack pointer is incremented to a value greater than the value in the stack underflow register STKUN the STKUF flag is set in register TFR and the CPU will enter the stack underflow trap routine Again which IP value will be pushed onto the system stack depends on which operation caused the increment of the SP When an implicit increment of the SP is made through a POP or return instruction the IP value pushed is the address of the following instruction When the SP is incremented by an add instruction the pushed IP value represents the address of the first or
276. ented with every new core version User s Manual 3 90 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Central Processing Unit 3 10 Summary of CPU Registers This section summarizes all registers in the C166S There are two kind of registers the General Purpose Registers GPR and the CPU Special Function Registers CSFR The GPRs are the working registers of the arithmetic and logic operations and may be also used as address pointers indirect addressing modes The CSFRs are the control registers of the C166S For easy reference the CSFRs are listed in this section by address to identify a register at a given address and by name to find an address of a specific register 3 10 1 General Purpose Registers The GPRs are the working registers of the C166S All GPRs are bit addressable Table 3 21 Addressing modes to access Word GPRs Name Physical 8 Bit 4 Bit Description Reset Address Address Address Value RO CP 0 FO 0 General Purpose word Register RO UUUU H1 CP 2 Fly 1 General Purpose word Register R1 UUUU R2 CP 4 F2 2H General Purpose word Register R2 UUUU R3 CP 6 F3 3 General Purpose word Register R3 UUUU R4 CP 8 F4 4 General Purpose word Register R4 UUUU R5 CP 10 F5 5y General Purpose word Register R5 UUUU R6 CP 12 F6 64 General Purpose word Re
277. er 00004 IRQ521C F168y ESFR b B4 IRQ52 Interrupt Control Register 00004 IRQ53IC F16A ESFR b B5 IRQ53 Interrupt Control Register 00004 IRQ5A4IC F16Cy ESFR b B6y _ IRQ54 Interrupt Control Register 00004 IRQ55IC F16Ey ESFR b B7y IRQ55 Interrupt Control Register 0000 IRQ56IC F170y ESFR b B8y _ IRQ56 Interrupt Control Register 00004 IRQ571C F172y ESFR b B94 IRQ57 Interrupt Control Register 00004 IRQ58IC F174 ESFR b BA IRQ58 Interrupt Control Register 00004 IRQ59IC F176y ESFR b BBy IRQ59 Interrupt Control Register 0000 IRQ6OIC F178H ESFR b BCy IRQ60 Interrupt Control Register 00004 IRQ61IC F184y ESFR b C24 IRQ61 Interrupt Control Register 00004 IRQ62IC F18Cy ESFR b C6y IRQ62 Interrupt Control Register 00004 IRQ63IC F194y ESFR b CAy IRQ63 Interrupt Control Register 0000 IRQ64IC F120y ESFR b 904 IRQ64 Interrupt Control Register 00004 IRQ65IC F122 ESFR b 914 IRQ65 Interrupt Control Register 00004 IRQ66IC F124 ESFR b 924 IRQ66 Interrupt Control Register 00004 IRQ67IC F126y ESFR b 934 IRQ67 Interrupt Control Register 0000 IRQ68IC F128H ESFR b 944 IRQ68 Interrupt Control Register 00004 IRQ69IC F12Ay ESFR b 954 IRQ69 Interrupt Control Register 0000 IRQ70IC F12Cy ESFR b 964 IRQ70 Interrupt Control Register 00004 IRQ711C F12Ey ESFR b 974 IRQ71 Interrupt Control Register 0000y IRQ721C F130y ESFR b 984 IRQ72 Interrupt Control Register 0000y IRQ7S3IC F13
278. er MDL by direct GPR 16 16 bit 2 DIVL Rw Signed long divide register MD by direct GPR 32 16 bit 2 DIVLU Rw Unsigned long divide register MD by direct GPR 2 32 16 bit DIVU Rw Unsigned divide register MDL by direct GPR 16 16 bit 2 CPL Rw Complement direct word GPR 2 CPLB Rb Complement direct byte GPR 2 NEG Rw Negate direct word GPR 2 NEGB Rb Negate direct byte GPR 2 Logical Instructions AND Rw Rw Bitwise AND direct word GPR with direct GPR AND Rw Rw Bitwise AND indirect word memory with direct GPR 2 AND Rw Rw Bitwise AND indirect word memory with direct GPR and 2 post increment source pointer by 2 AND Rw data3 Bitwise AND immediate word data with direct GPR 2 AND reg data16 Bitwise AND immediate word data with direct register 4 AND reg mem Bitwise AND direct word memory with direct register 4 AND mem reg Bitwise AND direct word register with direct memory 4 ANDB Rb Rb Bitwise AND direct byte GPR with direct GPR 2 ANDB Rb Rw Bitwise AND indirect byte memory with direct GPR 2 ANDB Rb Rw Bitwise AND indirect byte memory with direct GPR 2 and post increment source pointer by 1 ANDB Rb data3 Bitwise AND immediate byte data with direct GPR 2 ANDB reg data8 Bitwise AND immediate byte data with direct register 4 ANDB reg mem Bitwise AND direct byte memory with direct register 4 ANDB mem reg Bitwise AND direct byte register with direct memory 4 User s Manual 5 8 V 1 6 2001 08 e Infin technologies eon
279. er ratios CON _FDE 0 and the required reload value for a given baudrate can be determined by the following formulas Table 10 1 Asynchronous Baudrate Formulas using the Fixed Input Clock Dividers FDE BRS BG Formula 0 0 0 8191 ae Baudrate 32 x BG 1 BG tok 32 x Baudrate 1 f clk Baudrate 48 x BG 1 BG fkw_clk 48 x Baudrate User s Manual 10 19 V 1 6 2001 08 e Infineon technologies BG represents the contents of the reload register BG BR VALUE taken as unsigned 13 bit integer User s Manual C166S V1 SubSystem Asynchronous Synchronous Serial Interface ASC The maximum baudrate that can be achieved for the asynchronous modes when using the two fixed clock dividers and a module clock of 60 MHz is 1 875 MBaud Table 10 2 lists various commonly used baudrates together with the required reload values and the deviation errors compared to the intended baudrate Table 10 2 Typical Asynchronous Baudrates using the Fixed Input Clock Dividers Baudrate BRS 0 fek 60 MHz BRS 1 foy 60 MHz Deviation Reload Value Deviation Reload Value Error Error 1 875 MBaud 00004 1 25 MBaud 0000 19 2 KBaud 0 7 96 0 4 96 0060y 0061 y 0 2 1 4 00404 0041 9600 Baud 0 2 0 4 00C2y 0 2 0 6 0081 00824 00C3y 4800 Baud 0 2 0 1 01854 01864 0 2 0 2 0104y 0105y 2400 Baud 0 0 926
280. ered CPU Interrupt Status IEN ILVL The Interrupt ENable IEN bit makes it possible to enable IEN 1 or disable IEN 0 interrupts globally The four bit LeVeL field ILVL specifies the priority of the current CPU activity The priority level is updated by hardware upon entry into an ISR but it can also be modified via software to prevent other interrupts from being acknowledged If an priority level 15 has been assigned to the CPU it has the highest possible priority and thus the current CPU operation cannot be interrupted except by hardware traps or external non maskable interrupts For details please refer to Section 3 4 Interrupt and Trap Functions After reset all interrupts are disabled globally and the lowest priority ILVL 0 is assigned to the initial CPU activity User s Manual 3 79 V 1 6 2001 08 1 fi User s Manual nrineon M os C166S V1 SubSystem Central Processing Unit 3 8 Instruction Pipeline The instruction pipeline of the C1665 partitions instruction processing into four stages Each of these has a separate task 1st gt FETCH In this stage the instruction selected by the Instruction Pointer IP and the Code Segment Pointer CSP is fetched from either the internal local memory DPRAM or external memory 2nd DECODE In this stage the instructions are decoded and if required the operand addresses are calculated and the respective operands are fetched For all instructions t
281. eros in the non addressed byte Byte write operations via short 8 bit reg addressing can only access the low byte of an SFR and force zeros in the high byte It is therefore recommended to use the bit field instructions BFLDL and BFLDH to write to any number of bits in either byte of an SFR without disturbing the non addressed byte and the unselected bits Reserved Bits Some of the bits which are contained in the C166S s SFHs are marked as Reserved User software should never write 1s to reserved bits These bits are currently not implemented and may be used in future products to invoke new functions In this case the active state for these functions will be 1 and the inactive state will be O Therefore writing only Os to reserved locations provides portability of the current software to future devices After read accesses reserved bits should be ignored or masked out User s Manual 3 6 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 3 Instruction Fetch and Program Flow Control The C166S can fetch on average one 32 bit or two 16 bit instructions via the 32 bit wide Local Memory Bus LM Bus every machine cycle which equals two clock cycles T1 and T2 to provide a continuous instruction flow The instructions can be fetched via this new internal LM Bus from the internal local memories ROM FLASH OTP SRAM DRAM every clock cycle A waitstate mechanism allows the CPU to a
282. ess locations and occupies a maximum space of 32 bytes The GPRs are accessed via short 2 4 or 8 bit addressing modes using the CP register as base address independent of User s Manual 4 10 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization the current DPP register contents Additionally each bit in the currently active register bank can be accessed individually The C166S supports register bank context switching Multiple memory mapped register banks can physically exist within the DPRAM at the same time Only the register bank selected by the CP register is active at a given time however Selecting a new active register bank is simply done by updating the CP register Figure 4 4 Mapping of General Purpose Registers to DPRAM Addresses DPRAM Address Byte Registers Word Register CP 1Ey R15 CP 1Cy R14 lt CP gt 1Ay HE R13 CP 184 m R12 lt CP gt 164 R11 CP 144 aoe R10 CP 124 ace R9 lt CP gt 104 R8 CP OEy RH7 RL7 R7 CP 0Cy RH6 RL6 R6 lt CP gt OAy RH5 RLS R5 CP 08 RH4 RL4 R4 CP 06y RH3 RL3 R3 CP 044 RH2 RL2 H2 CP 024 RH1 RL1 H1 CP 004 RHO RLO HO A particular Switch ConteXT SCXT instruction performs register bank switching and automatic saving of the previous context The number of imple
283. et line T3EUD is selected to be the controlling source of the count direction However bit T3UD can still be used to reverse the actual count direction as shown in Table 12 1 If T3UD is cleared and line T3EUD shows a low level the timer is counting up With a high level at T3EUD the timer is counting down If T3UD is set a high level at line T3EUD specifies counting up and a low level specifies counting down The count direction can be changed whether or not the timer is running or not Note When line T3EUD is used as external count direction control input its associated port pin must be configured as input Table 12 1 Core Timer T3 Count Direction Control Line T3EUD Bit TSUDE Bit TSUD Count Direction X 0 0 Count Up X 0 1 Count Down 0 1 0 Count Up 1 1 0 Count Down 0 1 1 Count Down 1 1 1 Count Up Note The direction control works the same way for core Timer T3 and for auxiliary Timers T2 and T4 Timer 3 Overflow Underflow Monitoring An overflow or underflow of Timer T3 will set clock bit T3OTL in control register T3CON T3OTL can also be set or reset by software Bit T3OE overflow underflow output enable in register T3CON enables the state of T3OTL to be monitored via an external line T3OUT If this line is linked to an external port pin configured as output TOUT can be used to control external hardware Additionally T3IOTL can be used in conjunction with auxiliary Timers T2 and T4 I
284. exiting the trap procedure the internal stack will wrap around to the top of the internal stack and continue to grow until the new value of the stack overflow pointer is reached When the underflow pointer is reached while the stack is emptied the bottom of stack is reloaded from the external memory and the internal pointers are adjusted accordingly User s Manual 3 67 V 1 6 2001 08 e Infineon technologies 3 7 Data Processing User s Manual C166S V1 SubSystem Central Processing Unit All standard arithmetic shift and logical operations are performed in the 16 bit Arithmetic and Logic Unit ALU In addition to the standard ALU the ALU of the C166S includes bit manipulation and a multiply and divide unit Most internal execution blocks have been optimized to perform operations on either 8 bit or 16 bit numbers Once the pipeline has been filled most instructions are completed in one machine cycle The status flags are automatically updated in the PSW register see Section 3 7 6 after each ALU operation These flags allow branching upon specific conditions Support of both signed and unsigned arithmetic is provided by the user selectable branch test The status flags are also preserved automatically by the CPU upon entry into an interrupt or trap routine 3 7 1 The C166S supports operations on boolean bit bit string character and integer data types Most instructions operate with specific data types while other
285. external bus cycle is started User s Manual 8 3 V 1 6 2001 08 pae 1 fi User s Manual nrineon M C166S V1 SubSystem The External Bus Interface CLKOUT Normal Normal ALE Extended ALE Cycle 5 Extend ALE CSxL9 A23 AQ BHE CSxE9 WRL WRH WR WRCS D15 DO Norm ALE f ai Low actress TRE M DE A D15 DO Extd ALE 1 Section 8 3 4 Read Write Delay 2 Section 8 3 5 Early Write 3 4 3 Section 8 3 2 Memory Cycle Time alike enmi 4 Section 8 3 3 Memory Tri State Time Section 8 3 1 ALE Length Control 6 Section 8 2 3 CS Signal Generation Figure 8 2 Multiplexed Bus Write Access User s Manual 8 4 V 1 6 2001 08 C Infineon User s Manual technologies C1 66S V1 SubSystem The External Bus Interface CLKOUT Normal ALE Extend ALE CSxL A23 A0 BHE CSxE9 o o Ly RD ADOS NE D1 ME Low Address Data In orm E um Low Address Data In xtd Section 8 3 4 Read Write Delay Section 8 3 2 Memory Cycle Time Section 8 3 3 Memory Tri State Time Section 8 3 1 ALE Length Control Section 8 2 3 CS Signal Generation Figure 8 3 Multiplexed Bus Read Access User s Manual 8 5 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface 8 2 2 Demultiplexed Bus Modes In the demultiplexed bus modes the 16 bit intra segment address is permanently output on PORT
286. external decoder The number of CS lines is selected via conf rst cssel i 1 0 during reset and coded in bit field CSSEL in register RPOH see Table 8 4 Table 8 4 Decoding of Chip Select Lines CSSEL Chip Select Lines Note 11 Five CS4 CSO Default without pull downs 10 None 01 Two CS1 CSO 00 Three CS2 CS0 The CSx outputs are associated with the BUSCONx registers and are driven active low for any access within the address area defined for the respective BUSCON register For any access outside this defined address area the respective CSx signal will go inactive high At the beginning of each external bus cycle the corresponding valid CS signal is determined and activated All other CS lines are deactivated driven high at the same time Note The CSx signals will not be updated for an access to any internal address area i e when no external bus cycle is started even if this area is covered by the respective ADDRSELx register An internal bus interface access deactivates all external CS signals uu I Upon accesses to address windows without a selected CS line all selected CS lines are deactivated The chip select signals may be operated in four different modes see Table 8 5 that are selected via bits CSWENx and CSRENx in the respective BUSCONx register Table 8 5 Chip Select Generation Modes CSWENXx CSRENx Chip Select Mode Address chip select default after reset Read chip sel
287. f each register block is bit addressable so the respective control status bits can be modified directly or checked using bit addressing User s Manual 4 6 V 1 6 2001 08 1 fi User s Manual nrineon M s C166S V1 SubSystem Memory Organization When accessing registers in the ESFR area using 8 bit addresses or direct bit addressing the EXTend Register EXTR instruction is required before accessing registers in the ESFR area in order to switch the short addressing mechanism from the standard SFR area to the ESFR area This is not required for 16 bit and indirect addresses The GPRs R15 RO are duplicated i e they are accessible within both register blocks via short 2 4 or 8 bit addresses without switching Example 1 EXTR 4 Switch to ESFR area for the next 4 instructions MOV ODP2 data16 ODP2 ESFR register uses 8 bit reg addressing BFLDL DP6 mask data8 DP6 ESFR register bit addressing for bit fields BSET DP6 7 DP6 ESFR register bit addressing for single bits MOV T8REL R1 T8REL uses 16 bit address R1 is duplicated and also accessible via the ESFR mode EXTR is not required for this access Ian Pr The scope of the EXTR 4 instruction ends here MOV T8REL R1 T8REL uses 16 bit address R1 is duplicated and does not require switching In order to minimize the switching of SFR banks the ESFR area holds registers that are mainly required for initialization and mode selection Regi
288. f external RAM and or ROM can be connected to the microcontroller via its external bus interface The integrated Bus Controller BC allows to access external memory and or peripheral resources in a very flexible way It can be programmed either to Single Chip Mode when no external memory is required or to one of four different external memory access modes which are as follows 16 18 20 24 bit Addresses 16 bit Data Demultiplexed 16 18 20 24 bit Addresses 16 bit Data Multiplexed 16 18 20 24 bit Addresses 8 bit Data Multiplexed 16 18 20 24 bit Addresses 8 bit Data Demultiplexed In the demultiplexed bus modes addresses are output on PORT1 and data is input output on PORTO In the multiplexed bus modes both addresses and data use PORTO for input output Important timing characteristics of the external bus interface Memory Cycle Time Memory Tri State Time Length of ALE Read Write Delay CS and WR have been made programmable to allow the user the adaptation of a wide range of different types of memories In addition different address ranges may be accessed with different bus characteristics Up to 5 external CS signals can be generated in order to save external glue logic Access to very slow memories is supported via a particular Ready function For applications which require less than 16 MBytes of external memory space this address space can be restricted to 1MByte 256 kByte or 64 kByte In this case Po
289. fers issued by the Peripheral Event Controller PEC e Software traps caused by the TRAP instruction Hardware traps issued by faults or specific system states Normal Interrupt Processing The CPU temporarily suspends the current program execution and branches to an Interrupt Service Routine ISR in order to service an interrupt requesting device The current program status Instruction Pointer IP Processor Status Word PSW and in segmentation mode the Code Segment Pointer CSP is saved on the internal system stack A prioritization scheme with 16 priority levels and with 4 8 sub levels 4 8 group levels specifies the order of multiple interrupt request handling The maximum number of interrupt requests is 112 configured in steps of 16 wherein the lowest priority level is reserved for the CPU and cannot be used for interrupts Software and Hardware Traps Trap functions are activated in response to special conditions that occur during the execution of instructions A trap can also be caused externally by the Non Maskable Interrupt NMI pin Several hardware trap functions are provided for handling erroneous conditions and exceptions that arise during the program execution Hardware traps always have highest priority and cause immediate system reaction The software trap function is invoked by the TRAP instruction which generates a software interrupt for a specified interrupt vector For all types of traps the current program status
290. fied by op1 is met a branch to the location specified indirectly by the second operand op2 is taken The value of the instruction pointer IP is placed onto the system stack Because the IP always points to the instruction following the branch instruction the value stored in the system stack represents the return address of the calling routine If the condition is not met no action is taken and the next instruction is executed normally CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes CALLI cc Rw AB cn 2 User s Manual 6 22 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set CALLR Call Subroutine Relative CALLR Group Call Instructions Syntax CALLR op1 Source Operand s op1 gt 8 bit signed displacement Destination Operand s none Operation SP SP 2 SP lt IP IP IP 2 sign_extend op1 Description A branch is taken to the location specified by the instruction pointer IP plus the relative displacement op1 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the instruction pointer IP is placed into the system stack Because the IP always points to the instruction following the branch instruction the value stored in the system stack represents the return address of the calling rout
291. figured as inputs The logic level of a pin is clocked into the input latch once per state time regardless whether the port is configured for input or output Data Input Output Direction Control Data Input Output Direction Control Registers Registers Registers Registers Pa Figure 7 1 SFRs associated with the Parallel Ports A write operation to a port pin configured as an input causes the value to be written into the port output register while a read operation returns the registered state of the pin itself A read modify write operation reads the value of the pin modifies it and writes it back to the output register Writing to a pin configured as an output DPx y 1 causes the output register and the pin to have the written value since the output buffer is enabled Reading this pin returns the value of the output register A read modify write operation reads the value of the output register modifies it and writes it back to the output register thus also modifying the level at the pin User s Manual 7 1 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Parallel Ports 7 1 Alternate Port Functions In order to provide a maximum of flexibility for different applications and their specific IO requirements port lines have programmable alternate input or output functions associated with them Table 7 1 Summary of Alternate Port Functions Port Alternate Function s Alternate Sig
292. flag is also cleared for a prioritize operation because a 1 is never shifted out of the MSB during the normalization of an operand User s Manual 3 77 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit For Boolean bit operations with only one operand the C flag is always cleared For Boolean bit operations with two operands the C flag represents the logical ANDing of the two specified bits V Flag The addition subtraction and 2 s complement operations set the V flag to 1 if the result exceeds the range of 16 bit signed numbers for word operations 8000 to 7FFF j or 8 bit signed numbers for byte operations 80y to 7F Otherwise the V flag is cleared The result of an integer addition integer subtraction or 2 s complement operation is not valid if the V flag indicates an arithmetic overflow For multiplication and division the V flag is set to 1 if the result can not be represented in a word data type otherwise it is cleared A division by zero will always cause an overflow Unlike the division result the result of multiplication is valid regardless of V flag value Since logical ALU operations cannot produce an invalid result the V flag is cleared by these operations The V flag is also used as a sticky bit for rotate right and shift right operations By only using the C flag a rounding error caused by a shift right operation can be estimated as up to one
293. formula o 1 lt WDTPRE gt lt WDTIN gt 6 516 WDTREL gt 28 Feo Note For safety reasons the user is advised to rewrite WDTCON each time before the watchdog timer is serviced Pwpr Table 9 1 Reset Indication Flag Combinations Event Reset Indication Flags SWR WDTR Hardware Reset HWRST 0 0 Software Reset SRST 1 0 Watchdog Timer Reset WDTRST 0 1 HWRST and SRST 0 0 HWRST and WDTRST 0 0 HWRST SRST and WDTRST 0 0 SRST and WDTRST 1 1 1 Description of table entries 1 flag is set 0 flag is cleared Hardware Reset is indicated after a reset was triggered by a hardware event In this case neither the SWR nor the WDTR bit is set In case of a hardware reset the software and watchdog timer reset are surpressed and not visible Software Reset is indicated after a reset was triggered by the execution of instruction SRST Watchdog Timer Reset is indicated after a reset triggered by an overflow of the watchdog timer User s Manual 9 4 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Asynchronous Synchronous Serial Interface ASC 10 Asynchronous Synchronous Serial Interface ASC 10 1 Introduction This document describes the Asynchronous Synchronous Serial Interface ASC The ASC supports a certain protocol to transfer data via a serial interconnection It is also connected to a parallel bus of a microcontroller The i
294. from the instruction decode logic These are summarized below and described in detail in the following sections 1 High Instruction Bandwidth Fast Execution 2 High Function 8 bit and 16 bit Arithmetic and Logic Unit 3 Extended Bit Processing and Peripheral Control 4 High Performance Branch Call and Loop Processing 5 Consistent and Optimized Instruction Formats 6 Programmable Multiple Priority Interrupt Structure 2 1 1 High Instruction Bandwidth Fast Execution Based on the hardware provisions most of the C166S s instructions can be executed in just one machine cycle which requires 2 CPU clock cycles T1 and T2 2 1 fcpu 4 TCL For example shift and rotate instructions are always processed within one machine cycle independent of the number of bits to be shifted Branch multiply and divide instructions normally take more than one machine cycle These instructions however have also been optimized A 32 bit 16 bit division takes 20 CPU clock cycles a 16 bit 16 bit multiplication takes 10 CPU clock cycles The instruction cycle time has been dramatically reduced through the use of instruction pipelining This technique allows the core CPU to process portions of multiple sequential instruction stages in parallel The following four stage pipeline provides the optimum balancing for the CPU core FETCH In this stage an instruction is fetched from the internal ROM Read Only Memory or RAM Random Acce
295. g serviced The previous PSW is saved in the system stack before entering the ISR To be serviced any interrupt request must have a higher priority level than the current CPU priority level Any request of the same or a lower level will not be acknowledged The current CPU priority level may be adjusted via software to select interrupt request sources that can be serviced PEC transfers do not really interrupt the CPU but rather steal some CPU cycles so PEC services do not influence the ILVL field in the PSW Hardware traps set the CPU level to the maximum priority i e 15 Therefore no interrupt or PEC requests will be acknowledged while an exception trap service routine is executed The TRAP instruction does not change the CPU level so software trap service routines may be interrupted by higher level requests Interrupt ENable flag IEN globally enables or disables interrupts and PEC operations When IEN is cleared no new interrupt requests are accepted by the CPU after IEN was set to 0 However the requests that have already entered the pipeline will be completed If IEN is set to 1 all interrupt sources are globally enabled Note To generate requests interrupt sources must be also enabled by the IEN bits in their associated control registers Note Traps are non maskable and therefore they are not controlled by the IEN bit User s Manual 3 23 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V
296. g serviced The vector associated with the requesting source is loaded into the IP and CSP and the first instruction of the service routine is fetched All other CPU resources such as data page pointers and the context pointer are not affected When the CPU returns from the ISR RETurn from Interrupt RETI is executed the status information is popped from the system stack in reverse order The status information contents depend on the SGTDIS bit value 3 4 4 2 Context Switching An ISR usually saves all the registers it uses on the stack and restores them before returning The more registers a routine uses the more time is wasted by saving and restoring User s Manual 3 24 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit The C166S makes it possible to switch the complete register bank of CPU registers GPRs with a single instruction so the service routine executes within its own separate context The instruction SCXT CP New Bank pushes the contents of the Context Pointer CP into the system stack and loads the CP with the immediate value New_Bank The new CP value sets a new register bank The service routine may now use its own registers This register bank is preserved when the service routine is terminated i e its contents are available for the next call Before returning RETI the previous CP is simply popped from the system stack which returns
297. g the System Configuration The instruction following an instruction that changes the system configuration via register SYSCON e g the mapping of the internal local memory segmentation stack size cannot use the new resources e g local memory or stack In these cases an instruction that does not access these resources should be inserted Code accesses to the new local memory area are only possible after an absolute branch to this area Note As a rule instructions that change local memory mapping should be executed from DPRAM or external memory e BUSCON ADDRSEL The instruction following an instruction that changes the properties of an external address area cannot access operands within the new area In these cases an instruction that does not access this address area should be inserted Code accesses to the new address area should be made after an absolute branch to this area Note As a rule instructions that change external bus properties should not be executed from the external memory area User s Manual 3 85 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Central Processing Unit 3 8 1 3 Common portable solution When writing to an external memory location the time needed before the new value becomes effective depends also on the overall system performance In general more extra cycle s will be needed in case of lower peripheral bus speed to cover the delay additionally ca
298. gister R6 UUUU R7 CP 14 F7 74 General Purpose word Register R7 UUUU R8 CP 16 F8 84 General Purpose word Register R8 UUUU H9 CP 18 F9 9 General Purpose word Register R9 UUUU R10 CP 20 FA Ay General Purpose word Register R10 UUUU R11 CP 22 FB By General Purpose word Register R11 UUUU R12 CP 24 FC Cu General Purpose word Register R12 UUUU R13 CP 26 FD D General Purpose word Register R13 UUUU R14 CP 28 FE Ey General Purpose word Register R14 UUUU The first 8 GPRs R7 RO may be also accessed byte wise Unlike SFRs writing to a GPR byte does not affect another byte of the GPR User s Manual 3 91 V 1 6 2001 08 1 fi User s Manual UE NN C166S V1 SubSystem Central Processing Unit The following byte wise accessible registers have special names Table 3 22 Addressing modes to access Byte GPRs Name Physical 8 Bit 4 Bit Description Reset Address Address Address Value RLO CP 0 FO On General Purpose byte Register RLO UU RHO CP 1 Fly lu General Purpose byte Register RL1 UU RL1 CP 2 F2 24 General Purpose byte Register RL2 UU RH1 CP 3 F3 34 General Purpose byte Register RL3 UU HL2 CP 4 F4 4y General Purpose byte Register RL4 UU RH2 CP 5 F5 5H General Purpose byte Register RL5 UU RL3 CP 6 F6y 64 General Purpose byte Register RL6
299. h bits CP 11 9 000 bits CP 11 10 are set to 11 by hardware 0 0 r CP is always word aligned Note It is the user s responsibility to ensure that the physical GPR address specified via CP register plus short GPR address must always be an RAM location If this condition is not met unexpected results may occur Do not set CP below the DPRAM start address Note Due to the internal instruction pipeline a new CP value cannot be used for GPR address calculations for the instruction immediately following the instruction updating the CP register User s Manual 3 50 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Central Processing Unit The C166S switches the complete memory mapped GPR bank with a single instruction After switching the service routine executes within its own separate context The instruction SCXT CP New_Bank pushes the value of the current context pointer CP into the system stack and loads CP with the immediate value New_Bank which selects a new register bank The service routine may now use its own registers This memory register bank is preserved when the service routine terminates i e its contents are available on the next call Before returning from the service routine RETI the previous CP is simply popped from the system stack which returns the registers to the original bank User s Manual 3 51 V 1 6 2001 08 1 fi User
300. hat implicitly access the system stack the SP register is either decremented or incremented as specified For branch instructions the IP and the CSP are updated with the desired branch target address provided that the branch is taken 3rd EXECUTE In this stage an operation is performed on the previously fetched operands in the ALU Additionally the condition flags in the PSW register are updated as specified by the instruction All explicit writes to the SFR memory space and all auto increment or auto decrement writes to GPRs used as indirect address pointers are performed during the execute stage of the instruction 4th WRITE BACK In this stage all external operands and the remaining operands within the DPRAM space are written back A particularity of the C166S are the so called injected instructions These injected instructions are generated internally by the machine to provide the time needed to process instructions that cannot be processed within one machine cycle They are automatically injected into the decode stage of the pipeline and then they pass through the remaining stages like every standard instruction Program interrupts are performed by means of injected instructions too Although these internally injected instructions will not be noticed in reality they are introduced here to ease the explanation of the pipeline in the following 3 8 1 Particular Pipeline Effects Since up to 4 different instructions are pro
301. hat the highest used code location of a segment contains an unconditional branch instruction to the next following segment to prevent the prefetcher from trying to leave the current segment Data Pages are contiguous 16 KByte blocks They are referenced via the Data Page Pointers DPP3 0 and via an explicit data page number for data accesses overriding the standard DPP scheme Each DPP register can select one of the possible 1024 data pages The DPP register that is used for the current access is selected via the two upper bits of the 16 bit data address Subsequent 16 bit data addresses that cross the 16 KByte data page boundaries will use different data page pointers while the physical locations need not be contiguous within memory User s Manual 4 9 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V1 SubSystem Memory Organization 4 6 System Stack The system stack must be defined within the DPRAM The size of the system stack is controlled by bitfield STKSZ in register SYSCON see table below Table 4 1 System stack size STKSZ Stack Size Words DPRAM Addresses Words 000p 256 00 FBFE 00 FA00 Default after Reset 001g 128 00 FBFE 00 FB00 010g 64 00 FBFEy 00 FB80y 011g 32 00 FBFEy 00 FBCOy 1008 512 00 FBFEy 00 F800y 101 Reserved Do not use this combination 110p Reserved Do not use this combination 1115 1536 00 FDFEy 00 F200y Note No circ
302. he high percentage of branching in controller applications branch instructions have been optimized to require one extra machine cycle only when a branch is taken This is implemented by precalculating the target address while decoding the instruction To decrease loop execution overhead three enhancements have been provided The first solution provides two cycle branch execution after the first iteration of a loop Thus only one additional machine cycle is lost during the execution of the entire loop In loops which fall through upon completion no additional machine cycles is lost when exiting the loop No special instructions are required to perform loops and loops are automatically detected during execution of branch instructions The second loop enhancement allows the detection of the end of a table and avoids the use of two compare instructions embedded in loops One simply places the lowest negative number at the end of the specific table and specifies branching if neither this value nor the compared value have been found Otherwise the loop is terminated if either condition has been met The terminating condition can then be tested e The third loop enhancement provides a more flexible solution than the Decrement and Skip on Zero instruction which is found in other microcontrollers Through the use of Compare and Increment or Decrement instructions the user can make comparisons to any value This allows loop counters to cover any range
303. he receive interrupt request and an error interrupt request if appropriate Start bits that follow this frame will not be recognized Note In wake up mode received frames are transferred to the receive FIFO register only if the 9th bit the wake up bit is 1 If this bit is 0 no receive interrupt request will be activated and no data will be transferred User s Manual 10 13 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Asynchronous Synchronous Serial Interface ASC 10 3 2 Synchronous Operation Synchronous Mode supports half duplex communication basically for simple I O expansion via shift registers Data is transmitted and received via line RXD while line TXD outputs the shift clock Note These signals are alternate functions of port pins Synchronous Mode is selected with CON M 000g Eight data bits are transmitted or received synchronous to a shift clock generated by the internal baudrate generator The shift clock is active only as long as data bits are transmitted or received 13 Bit Reload Registe f 13 Bit Baudrate Timer ER fBRT RIR Receive Int Shift Clock Request TIR Transmit Int Request Serial Port Control TBIR Transmit Buffer Int Request TXD cu EIR Error Int oc Request RAD b Receive Shift Transmit Shift Register i Register y Receive Buffer Reg IN Transmit Buffer Reg RBUF t TBUF Internal Bus Figure 10 7 Synchronous Mode of Serial
304. he register pairs control integrated peripherals rather than externally connected ones most of the registers are fixed by mask programming rather than being user programmable User s Manual C166S V1 SubSystem The External Bus Interface The XBUS provides byte wide or word wide X Peripheral accesses Because the on chip connection can be very efficient and for performance reasons X Peripherals are implemented only with a separate address bus i e in demultiplexed bus mode Interrupt nodes are provided for X Peripherals to be integrated Enabling XBUS Peripherals After reset all on chip XBUS peripherals are disabled An XBUS peripheral cannot be used unless it has been enabled via the global enable bit XPEN in register SYSCON Additional to the XPEN bit the XPERCON register define which on chip peripherals are enabled or disabled xpercon o 15 0 If a peripheral is disabled all it s addresses are no more visible The XPERCON register is accessible until execution of the EINIT instruction XPER selection with the XPERCON register has to be performed before the selected X peripherals are globally enabled via XPEREN bit in SYSCON Register XPERCON XPeripheral Control Register SFR F024 12 Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PER PER PER PER PER PER PER PER PER PER PER PER PER PER PER PER 15 14 13 12 11 10 9 8 7 6 5 4 3
305. hether a capture is performed or not If T5SC is cleared the input line CAPIN can still be used to clear Timer T5 or as an external interrupt input This interrupt is controlled by the CAPREL interrupt control register CRIC BPS2 T5l Up Down NE Auxiliary Timer T5 Edge Select ET YH 1500 T5SC Cl CRIRQ CAPREL Register MCBO02044 c Figure 12 23 Timer Block 2 Register CAPREL in Capture Mode User s Manual 12 40 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit Timer Block 2 Capture Reload Register CAPREL in Reload Mode This 16 bit register can be used as a reload register for core Timer T6 This mode is selected by setting bit T6SR in register TeCON The event causing a reload in this mode is an overflow or underflow of core Timer T6 When Timer T6 overflows from FFFFy to 0000y when counting up or underflows from 0000 to FFFFy when counting down the value stored in register CAPREL is loaded into Timer T6 This will not drive the interrupt request line CRIRQ associated with the CAPREL register However interrupt request line T6IRQ will be driven at high level to indicate the overflow underflow of T6 CAPREL Register 1 T6SR Core Timer T6 T6IRQ T6OFL MCBO2045 b BPS2 T l Up Down Figure 12 24 Timer Block 2 Register CAPREL in Reload Mode User s Manual 12 41 V 1 6 2001 08
306. hich do not need the same priority level for the termination interrupt One dedicated service request node with a programmable interrupt level is shared among all PEC channels This service request node is controlled by the EOPIC interrupt control register EOPIC Interrupt Control Register bSFR xxxx XXp Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ololol o 0 0 o aP p ee ILVL GLVL r r r r r r r rw rwh rw rw rw 1 The EOPIC register is assigned to one of the 64 interrupt control registers The assignment is product specific Field Bits Type Description xxGP 8 rw Group Priority Extension Defines the value of high order group level bit EOPIR 7 rwh Interrupt Request Flag 0 No request pending 1 his source has raised an interrupt request EOPIE 6 rw Interrupt Enable Control Bit 0 Interrupt request is disabled 1 Interrupt request is enabled ILVL 5 2 rw Interrupt Priority Level Fu Highest priority level Op Lowest priority level GLVL 1 0 rw Group Priority Level 3H Highest priority level Op Lowest priority leve 1 Bit xxIR supports bit protection The Register PECISNC and PECXISN contain flags of the EOP interrupt node This node is used when the enhanced End of PEC interrupt feature is invoked and control bit EOPINT is set to 1 in the corresponding PECCx User s Manual 3 44 V 1 6 2001 08 e Infineon tech
307. high speed RAM an integrated CAN Module Controller Area Network an on chip PLL Phase Locked Loop etc Utilizing integration to design efficient systems may require the integration of application specific peripherals to boost system performance while minimizing the part count These efforts are supported by the so called Internal Bus Interface defined for the Infineon 16 bit microcontrollers XBus second generation This Internal Bus Interface is an internal representation of the External Bus Interface that opens and simplifies the integration of peripherals by standardizing the required interface User s Manual 1 2 V 1 6 2001 08 pae 1 fi User s Manual a C166S V1 SubSystem Introduction 1 2 Summary of Basic Features The C166S is an improved representative of the Infineon family of full featured 16 bit single chip CMOS Complementary Metal Oxide Silicon microcontrollers It combines high CPU performance with high peripheral functionality Several key features contribute to the high performance of the C166S bases subsystem the indicated timings refer to a CPU clock of 50 MHz High Performance 16 Bit CPU With Four Stage Pipeline 40 ns minimum instruction cycle time with most instructions executed in 1 cycle e 200 ns multiplication 16 bit 16 bit 400 ns division 32 bit 16 bit Multiple high bandwidth internal data buses Register based design with multiple variable register banks e Single cycle context s
308. his case the information about how to restart the instruction is contained in this register Register MDC must be cleared to be initialized correctly for a subsequent multiplication or division The old MDC contents must be popped from the stack before the RETI instruction is executed For a division the user must first move the dividend into the MD register If a 16 16 bit division is specified only the low portion of MD must be loaded The result is also stored in MD The low portion MDL contains the integer result of the division while the high portion MDH contains the remainder The following instruction sequence performs a 32 by 16 bit division MOV MDH R1 Move dividend to MD register Sets MDRIU MOV MDL R2 Move low portion to MD DIV R3 Divide 32 16 signed R3 holds divisor JMPR cc V ERROR Test for divide overflow MOV R3 MDH Move remainder to R3 MOV R4 MDL Move integer result to R4 Clears MDRIU Whenever a multiply or divide instruction is interrupted while in progress the address of the interrupted instruction is pushed onto the stack and the MULIP flag in the PSW of the interrupting routine is set When the interrupt routine is exited with the RETI instruction this bit is tested implicitly before the old PSW is popped from the stack If MULIP 1 the multiply divide instruction is re read from the location popped from the stack return address and will be completed after the RETI inst
309. hould be switched on during reset for all potential CS output pins This feature should be implemented to drive the chip select lines high during reset in order to avoid multiple chip selection After reset the CS function must be used if selected so In this case there is no possibility to program any port registers before Thus the alternate function CS is selected automatically in this case User s Manual 7 14 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Parallel Ports Internal Bus Port Output Register AltDir 1 Direction Register AltDataOut AltDataln lt Input Register Port6_1 vsd Figure 7 9 Block Diagram of Port 6 Pins with an alternate output function User s Manual 7 15 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Parallel Ports Internal Bus Port Output Register Direction Register Port6_2 vsd Input Register Figure 7 10 Block Diagram of Port 6 Pins without an alternate output function User s Manual 7 16 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface 8 The External Bus Interface Although the C166S subsystem supports a powerful set of on chip peripherals and on chip RAM and ROM OTP Flash areas these internal units cover only
310. ied bit is cleared program execution continues normally with the instruction following the JB instruction CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes JB bitaddro q rel 8A QQ rr q0 4 User s Manual 6 49 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set JBC Relative Jump if Bit Set and Clear Bit JBC Group Jump Instructions Syntax JBC op1 op2 Source Operand s op1 gt BIT op2 gt 8 bit signed displacement Destination Operand s none Operation IF op1 1 THEN opt 0 IP IP 2 sign_extend op2 ELSE Next Instruction END IF Description If the bit specified by op1 is set program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The bit specified by op1 is cleared allowing implementation of semaphore operations The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JBC instruction If the specified bit was clear program execution continues normally with the instruction following the JBC instruction Note Flags are always updated by this instruction CPU Flags E Z V C N Always cleared Contains the logical negation of the previous stat
311. ies 2 words to provide space for long jumps except for the reset vector and the hardware trap vectors which occupy 4 or 8 words Each vector location has an offset address to the segment base address 00 0000y of the vector table The offset address can be calculated easily The offset is the trap number shifted by 2 3 4 4 Interrupt Control Functions in the Processor Status Word The PSW is divided functionally into 2 parts The lower byte of the PSW represents the arithmetic status of the CPU the upper byte of the PSW controls the interrupt system of the C166S User s Manual 3 22 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit PSW Processor Status Word SFR FF10 88 Reset value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ILVL IEN rwh rw Field Bits Type Description ILVL 15 12 rwh CPU Priority Level O4 Lowest Priority Fu Highest Priority IEN 11 rw Interrupt PEC Enable Flag globally 0 Interrupt PEC requests are disabled 1 Interrupt PEC requests are enabled Note For a summary of the PSW register please refer to Section 3 7 6 CPU Priority ILVL defines the current level for the CPU operation i e this bit field reflects the priority level of the routine currently being executed When the CPU enters an ISR this bitfield is set to the priority level of the request that is bein
312. ignal Name Source of Interrupt Interrupt Control Vector Trap Interrupt IF Register Location No irq_i 98 Product Interrupt Request 98 IRQ98IC 01C8y 72H irq_i 99 Product Interrupt Request 99 IRQ99IC 01CC 73H irq_i 100 Product Interrupt Request 100 IRQ100IC 01D0y 744 irq_i 101 Product Interrupt Request 101 IRQ1011C 01D4 75H irq_i 102 Product Interrupt Request 102 IRQ1021C 01D8y 76H irq_i 103 Product Interrupt Request 103 IRQ103IC 01DCy 77H irq_i 104 Product Interrupt Request 104 IRQ104IC 01E0y 78 irq_i 105 Product Interrupt Request 105 IRQ1051C 01E4y 79 irq_i 106 Product Interrupt Request 106 IRQ106IC 01E8 7Ay irq_i 107 Product Interrupt Request 107 IRQ1071C 01ECy 7By irq_i 108 Product Interrupt Request 108 IRQ108lIC 01F0 7Cy irq_i 109 Product Interrupt Request 109 IRQ109IC 01F4 7Dy irq_i 110 Product Interrupt Request 110 IRQ110IC 01F8y 78H irq_i 111 Product Interrupt Request 111 IRQ1111C 01FCy 7Fh User s Manual 4 51 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Memory Organization User s Manual 4 52 V 1 6 2001 08 e Infineon technologies 5 Instruction Set User s Manual C166S V1 SubSystem Instruction Set 5 1 Short Instruction Summary The following compressed cross reference tables quickly identify a specific instruction and provide basic information about it Two ordering schemes are included The first
313. iguration Register 1 00004 BUSCON2 FF164 SFR b 8By Bus Configuration Register 2 0000y BUSCONS FF184 SFR b 8Cy Bus Configuration Register 3 0000 BUSCON4 FF1A SFR b 8D Bus Configuration Register 4 0000 CAPREL FE4Ay SFR 254 GPT Capture Reload Register 0000y COMDATA F068 ESFR 344 Cerberus Communication Mode 0000 Register CP FE10y SFR 084 CPU Context Pointer Register FCOO CPUID FOOCy ESFR 064 CPU Identification Register 04104 CRIC FF6A SFR b B54 GPT12E Capture Reload 0000 Interrupt Control Register CSP FEO8y SFR 044 CPU Code Segment Pointer 0000y Register 8 bits DBGSR FOFCY ESFR 7E4 Debug status register 0000 DCMPDP FOEE ESFR 774 Data Programming Register for 0000 DCMPx DCMPSP FOEC ESFRH 764 Select and Programming 0000y Register for DCMPx DEXEVT FOF2y ESFR 794 Specifies action if external break 0000y pin is asserted User s Manual 4 32 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 3 SFR ESFR Table ordered by name cont d Name Physical Type 8 bit Description Reset Address Addr Value 2 DIP FOF8y ESFR 7C4 Instruction pointer register 0000y DIPX FOFAy ESFR 7Dy Instruction pointer register 3000 extension DPOH F102 ESFR b 814 P
314. incorporates its strategic tool partners very early into the product development process making sure embedded system developers get reliable well tuned tool solutions which help them unleash the power of Infineon microcontrollers in the most effective way and with the shortest possible learning curve The tool environment for the Infineon 16 bit microcontrollers includes the following tools Compilers C MODULA2 FORTH Macro Assemblers Linkers Locaters Library Managers Format Converters Architectural Simulators HLL debuggers Real Time operating systems VERILOG chip models e In Circuit Emulators based on bondout or standard chips Plug In emulators Emulation and Clip Over adapters production sockets Logic Analyzer disassemblers Starter Kits Evaluation Boards with monitor programs User s Manual 1 5 V 1 6 2001 08 _ 1 fi User s Manual s C166S V1 SubSystem Introduction User s Manual 1 6 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem System Overview 2 System Overview The architecture of the C166S combines the advantages of both RISC Reduced Instruction Set Computing and CISC Complex Instruction Set Computing processors in a very well balanced way The sum of the features which are combined results in a high performance microcontroller which is the right choice not only for today s applications but also for future engineering cha
315. ine The value of the IP used in the target address calculation is the address of the instruction following the CALLR instruction CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes CALLR rel BB rr 2 User s Manual 6 23 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set CALLS Call Inter Segment Subroutine CALLS Group Call Instructions Syntax CALLS op1 op2 Source Operand s op1 gt segment number op2 gt 16 bit address offset Destination Operand s none Operation Description A branch is taken to the absolute location specified by op2 within the segment specified by op1 The previous value of the CSP is placed into the system stack to insure correct return to the calling segment The value of the instruction pointer IP is also placed into the system stack Because the IP always points to the instruction following the branch instruction the value stored on the system stack represents the return address to the calling routine CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes CALLS seg caddr DA SS MM MM 4 User s Manual 6 24 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set CMP Integer Compare CMP Group Boolean Bit M
316. iness excellence mean less idleness and wastefulness for all of us more professional success more accurate information a better overview and thereby less frustration and more satisfaction Dr Ulrich Schumacher http www infineon com Published by Infineon Technologies AG
317. ing If nothing is pending then the arbitration logic switches to the idle state to save power Each interrupt request line is controlled by its interrupt control register xxIC here and below xx stands for the mnemonic of the respective interrupt source An interrupt request event sets the interrupt request flag to 1 in the corresponding interrupt control register bit XxIC xxIR The interrupt request can also be triggered by the software if the program sets the respective interrupt request bit This feature is used by operating systems If the request bit has been set and this interrupt request is enabled by the IE bit of the same control register bit xxIC xxIE then an arbitration cycle starts on the next clock User s Manual 3 19 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V1 SubSystem Central Processing Unit cycle However if an arbitration cycle is currently in progress the new interrupt request will be delayed till the next arbitration cycle If an interrupt request or PEC request is accepted by the core the respective interrupt request flag is cleared automatically All interrupt requests that are pending at the beginning of a new arbitration cycle are considered simultaneously Within the arbitration cycle the arbitration is independent of the actual request time C166S uses a two stage interrupt prioritization scheme for interrupt arbitration as shown in Figure 3 3 Arbitration C1
318. ing edge or the trailing edge for each function Bit CON PO selects the level of the shift clock line in the idle state Thus for an idle high clock the leading edge is a falling one a 1 to 0 transition see Figure 11 4 User s Manual 11 9 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem High Speed Synchronous Serial Interface SSC Shift Clock MS CLK SS CLK Pins MTSR MRST Transmit Data Last Bit Latch Data Shift Data Figure 11 4 Serial Clock Phase and Polarity Options 11 22 Full Duplex Operation The various devices are connected through three lines The definition of these lines is always determined by the master The line connected to the master s data output line TXD is the transmit line the receive line is connected to its data input line RXD the shift clock line is either MS_CLK or SS CLK Only the device selected for master operation generates and outputs the shift clock on line MS CLK All slaves receive this clock so their pin SCLK must be switched to input mode The output of the master s shift register is connected to the external transmit line which in turn is connected to the slaves shift register input The output of the slaves shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave The external connections are hard wired the function and direction of these pins is determined
319. ing error detection allows to recognize data frames with missing stop bits An overrun error will be generated if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete 2 2 3 2 High Speed Synchronous Serial Channel SSCO Serial communication with other microcontrollers processors terminals or external peripheral components is provided by a High Speed Synchronous Serial Channel The SSCO allows full duplex synchronous communication up to 25 MBaud in master mode and 12 5 MBaud in slave mode referred to a PDBUS clock of 50 MHz A dedicated baud rate generator allows to set up all standard baud rates without subsystem clock tuning For transmission reception and erroneous reception three separate interrupt requests are provided The SSCO transmits or receives characters of 2 16 bits length synchronously to a shift clock which can be generated by the SSCO master mode or by an external master slave mode The SSCO can start shifting with LSB or with MSB Fully SPI functionality is supported A loop back option is available for testing purposes A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers A parity bit can automatically be generated on transmission or be checked on reception Framing error detection allows to recognize data frames with missing stop bits An overrun error will be
320. ing of the two specified bit operands AND The flag contains the logical ANDing of the two specified bit operands OR The flag contains the logical ORing of the two specified bit operands XOR The flag contains the logical XORing of the two specified bit operands User s Manual 5 24 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Instruction Set B The flag contains the original value of the specified bit operand B The flag contains the complemented value of the specified bit operand Note If the PSW register was specified as the destination operand of an instruction the condition flags can not be interpreted as just described because the PSW register is modified depending on the data format of the instruction as follows For word operations the PSW register is overwritten with the word result For byte operations the non addressed byte is cleared and the addressed byte is overwritten For bit or bit field operations on the PSW register only the specified bits are modified Supposed that the condition flags were not selected as destination bits they stay unchanged This means that they keep the state after execution of the previous instruction In any case if the PSW was the destination operand of an instruction the PSW flags do NOT represent the condition flags of this instruction as usual Addressing Modes This part specifies which combinations of different addressing modes
321. ing register ADDRSELx The four pairs BUSCON1 ADDRSEL1 BUSCON4 ADDRSEL4 make it possible to define four independent address windows while all external accesses outside these windows are controlled via BUSCONO User s Manual 8 1 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface 8 1 Single chip Mode Single chip mode is entered when the signal conf start external n i is high during reset In this case BUSCONO is initialized with 00004 which also resets bit BUSACTO so no external bus is enabled In single chip mode the C1665 operates only with and out of internal resources No external bus is configured and no external peripherals and or memory can be accessed No port lines are used for the bus interface When running in single chip mode however external access may be enabled by configuring an external bus under software control Single chip mode allows the C166S to start execution out of the internal program memory Mask ROM OTP DRAM SRAM or flash memory Note Any attempt to access a location in the external memory space in single chip mode results in the hardware trap ILLBUS if no external bus has been enabled explicitly by software 8 2 External Bus Modes When the external bus interface is enabled bit BUSACTx 1 and configured bitfield BTYP the C166S uses a subset of its port lines together with some control lines to build the external bus Table
322. ing the proper direction when using an alternate input or output function of a pin This is done by setting or clearing the direction control bit DPx y of the pin before enabling the alternate function There are port lines however where the direction of the port line is switched automatically For instance in the multiplexed external bus modes of PORTO the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data Obviously this cannot be done through instructions In these cases the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled To determine the appropriate level of the port output registers check how the alternate data output is combined with the respective port register output There is one basic structure for all port lines with only an alternate input function Port lines with only an alternate output function however have different structures due to the User s Manual 7 2 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V1 SubSystem Parallel Ports way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode All port lines that are not used for these alternate functions may be used as general purpose IO lines When using port pins for general purpose output the initial output value shoul
323. instruction is fetched from and where possible operands are read from or written to The fastest processing mode of the C166S is to execute a program fetched from the internal code memory In that case most of the instructions can be processed within just one machine cycle which is also the general minimum execution time All external memory accesses are performed by the EBC which works in parallel with the CPU This section summarizes execution times The table below shows the minimum execution times required to process an instruction fetched from the internal local memory the DPRAM or external memory These execution times apply to most instructions except some of the branches the multiplication the division and a special move instruction In case of internal local memory program execution the execution time does not depend on the instruction length except for some special branch situations The numbers in the table are in units of CPU clock cycles and assume no waitstates Table 3 20 Minimum Execution Times Instruction Fetch Word Operand Access Memory Area Word Doubleword Read from Write to Instruction Instruction Internal local memory 10 10 qu i9 DPRAM i 2 10 11 16 bit demux bus 2 4 2 2 16 bit mux bus 3 6 3 3 8 bit demux bus 4 8 4 4 8 bit mux bus 6 12 6 6 1 Minimum execution time for instruction fetch and operand accesses Nevertheless the minimum execution time of an instruction re
324. interrupt entry exit 1 Segmentation disabled Only IP is saved restored Note Forsummary of the SYSCON register please refer to Section 3 3 5 Segmented Mode The CSP register can be only read and may not be written by data operations The CSP is modified either directly by the JMPS and CALLS instructions or indirectly via the stack by the RETS and RETI instructions Upon the acceptance of an interrupt or the execution of a software TRAP instruction the CSP register is automatically loaded with the segment address of the vector location Non Segmented Mode In the non segmented mode the CSP is fixed to segment 0 It is no longer possible to modify the CSP either directly by the JMPS or CALLS instructions or indirectly via the stack by the RETS RETI instruction For non segmented memory mode the contents of this register are not significant because all code accesses are restricted automatically to segment 0 Note When segmentation is disabled the IP value is used directly as the 16 bit address User s Manual 3 16 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Central Processing Unit 3 3 5 The CPU System Configuration Register SYSCON This register is used to configure the C1668 It is bit addressable and provides general system configuration and control functions The reset value of register SYSCON depends on the state of the configuration inputs during reset
325. ion Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 CPU Flags E Z V C N ERASE E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes AND Rw data3 68 n 0 2 AND Rw RWm 60 nm 2 AND Rw Rw 68 nlii 2 AND Rw Rwi 68 n 10ii 2 AND mem reg 64 RR MM MM 4 AND reg data16 66 RR 4 AND reg mem 62 RR MM MM 4 User s Manual 6 6 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set ANDB Logical AND ANDB Group Logical Instructions Syntax ANDB op1 op2 Source Operand s op1 op2 gt BYTE Destination Operand s op BYTE Operation op1 lt op1 op2 Description Performs a bitwise logical AND of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the resul
326. ion of Timer Block 1 oooooococcooooo 12 3 12 2 1 Gore O 12 5 12 2 2 Auxiliary Timers T2 and T4 1 2 ee ee 12 16 12 2 3 Timer Concatenation 00 cee ee 12 21 12 3 Functional Description of Timer Block 2 o o ooo oooooo o 12 26 12 3 1 Core limer T6 scscdcmr creerle tddi cet 12 28 User s Manual l 4 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Table of Contents Page 12 3 2 Auxiliary Timer T5 recrea cesar vee ei aes dee ey 12 34 12 3 3 Timer Concatenation Graaceuck ee ee Sun Med sede ae ec pa 12 38 13 Instruction Index obese 32 acre circa near ica 13 1 14 Keyword Index ocres roads rre ea 14 1 User s Manual I 5 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem User s Manual l 6 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Introduction 1 Introduction The rapidly growing area of embedded control applications is representing one of the most time critical operating environments for today s microcontrollers Complex control algorithms have to be processed based on a large number of digital as well as analog input signals and the appropriate output signals must be generated within a defined maximum response time Embedded control applications also are often sensitive to board space power consumption and overall system cost Embedded control applications therefore require microcontro
327. ion of the monitored time interval Each time it is serviced by the application software the high byte of the Watchdog Timer is reloaded Thus time intervals between 10 us and 336 ms default after reset can be monitored referred to a PDBUS clock of 50 MHz 2 2 8 Clock Generation Unit CGU The C166S clock generation unit generates the system clock based on an oscillator or crystal input A programmable on chip PLL adds a high flexibility on clock generation to the C166S 2 2 9 On chip Bootstrap Loader An on chip bootstrap loader allows to move the start code into internal memories via the serial or other interfaces User s Manual 2 14 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Central Processing Unit 3 Central Processing Unit The C166S Central Processing Unit CPU represents the synthesizable generation of the well known C166 core family It has many powerful enhancements while remaining compatible with the C166 family The new architecture offers a high performance CPU fast and efficient access to different kinds of memories and efficient integration with peripheral units aa 4 Stage DPRAM up to 3KByte Pipeline Instruction Fetch and Injection Exception Handler id Bit Mask Gen Multiply Unit Barrel Shifter e ALU Register Bank d data out Figure 3 1 CPU architecture The new core architecture of the C166S results in higher CPU clock frequencies
328. ionality up to a total of sixteen PEC channels The following formula shows how to program the bitfield PECCx PLEV to set up a link to a certain interrupt priority level and a group priority level PEC channel x x 3 x 2 x 1 x 0 linked to Interrupt priority level 1 PLEV 1 PLEV O x 2 Group priority level x 3 x 1 x 0 User s Manual C166S V1 SubSystem Central Processing Unit PEC Channels Assignment and Arbitration 3 1 The following table lists all possible combinations Table 3 9 PEC interrupt level control with PLEV bits in PECCx registers Priority Level PEC Channel Selection x Interrupt Level Group Level PLEV 1 0 PLEV 1 0 PLEV 1 0 PLEV 1 0 ILVL3 0 xxGP GLVL1 0 00 01 10 11 15 3 0 7 4 14 7 4 11 8 13 7 4 15 12 13 3 0 7 4 12 7 4 11 8 12 3 0 3 0 11 7 4 15 12 11 3 0 7 4 10 7 4 11 8 10 3 0 3 0 9 7 4 15 12 9 3 0 7 4 8 7 4 11 8 8 3 0 3 0 All interrupt requests that are not assigned to a PEC channel go directly to the interrupt handler User s Manual V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 4 6 7 Programmable End of PEC Interrupt Level The programmable EOP interrupt supports PEC transfers which need a high priority level for the transfer request and w
329. ionally change the addressing mechanism during this sequence see instruction description ATOMIC and EXTended instructions become active immediately so no additional NOP instructions are required All instructions requiring multiple cycles or hold states for execution are considered as one instruction ATOMIC and EXTended instructions can be used with any instruction type Note If a class B trap interrupt occurs during an ATOMIC or EXTended sequence then the sequence is terminated an interrupt lock is removed and the standard condition is restored before the trap routine is executed The remaining instructions of the terminated sequence that are executed after returning from the trap routine will run under standard conditions Note Certain precautions are required when using nested ATOMIC and EXTended instructions There is only one counter to control the length of the sequence i e issuing an ATOMIC or EXTended instruction within a sequence will reload the counter with the value of the new instruction User s Manual 3 13 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Central Processing Unit 3 3 4 Code Addressing via Code Segment and Instruction Pointer The C166S provides a total addressable memory space of 16 MBytes This address space is arranged as 256 segments of 64 KBytes each A dedicated 24 bit code address pointer is used to access the memories for instruction fetches This
330. irect memory MOV Rw Rw Move indirect word memory to indirect memory MOV Rw Rw Move indirect word memory to indirect memory and post increment destination pointer by 2 MOV Rw Rw Move indirect word memory to indirect memory and 2 post increment source pointer by 2 MOV Rw Move indirect word memory by base plus constant to 4 Rw data16 direct GPR MOV Rw data16 Move direct word GPR to indirect memory by base plus 4 Rw constant User s Manual 5 12 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary cont d Mnemonic Description Bytes Data Movement cont d MOV Rw mem Move direct word memory to indirect memory 4 MOV mem Rw Move indirect word memory to direct memory 4 MOV reg mem Move direct word memory to direct register 4 MOV mem reg Move direct word register to direct memory 4 MOVB Rb Rb Move direct byte GPR to direct GPR 2 MOVB Rb data4 Move immediate byte data to direct GPR 2 MOVB reg data8 Move immediate byte data to direct register 4 MOVB Rb Rw Move indirect byte memory to direct GPR 2 MOVB Rb Rw Move indirect byte memory to direct GPR and 2 post increment source pointer by 1 MOVB Rw Rb Move direct byte GPR to indirect memory 2 MOVB Rw Rb Pre decrement destination pointer by 1 and move direct byte
331. is cleared by hardware after reception of a byte in Synchronous Mode PEN 5 rw Parity Check Enable All Asynchronous Modes without IrDA Mode 0 Ignore parity 1 Check parity User s Manual 10 6 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Asynchronous Synchronous Serial Interface ASC Field Bits Typ Description FEN 6 rw Framing Check Enable Asynchronous Mode only 0 Ignore framing errors 1 Check framing errors OEN 7 rw Overrun Check Enable 0 Ignore overrun errors 1 Check overrun errors PE 8 rwh Parity Error Flag Set by hardware on a parity error PEN 1 Must be cleared by software FE 9 rwh Framing Error Flag Set by hardware on a framing error FEN 1 Must be cleared by software OE 10 rwh Overrun Error Flag Set by hardware on an overrun error OEN 1 Must be cleared by software FDE 11 Fractional Divider Enable 0 Fractional divider disabled 1 Fractional divider enabled and used as perscaler for baudrate generator bit BRS is don t care ODD 12 Parity Selection 0 Even parity selected parity bit of 1 is included in data stream on odd number of 1 and parity bit of O is included in data stream on even number of 1 1 Odd parity selected parity bit of 1 is included in data stream on even number of 1 and parity bit of O is included in data stream on odd num
332. ister TXD Slave RXD Master Transmit Buffer Receive Buffer Register TB Register RB Internal Bus Figure 11 3 Synchronous Serial Channel SSC Block Diagram User s Manual 11 4 V 1 6 2001 08 e Infineon technologies 11 2 1 The operating mode of the serial channel SSC is controlled by its control register CON This register serves two purposes User s Manual C166S V1 SubSystem High Speed Synchronous Serial Interface SSC Operating Mode Selection During programming SSC disabled by CON EN 0 it provides access to a set of control bits During operation SSC enabled by CON EN 1 it provides access to a set of status flags Configuration Register This register contains control bits for mode and error check selection and status flags for error identification Depending on bit EN either control functions or status flags and master slave control is enabled CON EN 0 Programming Mode CON Control Register Reset value 0000p 15 14 13 12 11 10 9 8 7 6 5 4 1 0 EN MS 0 SEN BEN PEN REN TEN LB PO PH HB BM rw rw r rw rw rw rw rw rw rw rw rw rw Field Bits Type Description BM 3 0 rw Data Width Selection 0000 Reserved Do not use this combination 0001 1111 Transfer Data Width is 2 16 bit lt BM gt 1 HB 4 rw Heading Control 0 Transmit Receive LSB First 1 Transmit Receive MSB First PH 5 rw Clock Phase Control 0 Shift tra
333. ity Level Fu Highest priority level O4 Lowest priority level GLVL 1 0 rw Group Priority Level Defines the internal order for simultaneous requests of the same priority 1 Bit xxIR supports bit protection The arbitration scheme allows nesting of up to 15 ISRs of different priority levels level O cannot be used see note above Note When no interrupt request is active arbitration is stopped to reduce power consumption 3 4 3 Interrupt Vector Table The C166S has a vectored interrupt system This system reserves the specific vector locations in the memory space for the reset trap and interrupt service functions Whenever a request occurs the CPU branches to the location that is associated with the respective interrupt source This vector position directly identifies the source that caused the request Note The Class B hardware traps all share the same interrupt vector The status flags in the Trap Flag Register TFR are used to determine which exception caused the trap For details see Section 3 4 5 2 Hardware Traps The reserved vector locations are assembled into a jump table that is located in the C166S s address space The jump table contains the appropriate jump instructions that transfer control to the interrupt or trap service routines These routines may be located anywhere within the address space The vector table is located at the bottom in segment 0 of the address space Each entry occup
334. ive Buffer Register BG Baudrate Timer Reload Register PISEL Port Input Select Register Figure 10 2 ASC Kernel Registers All ASC registers are located in the SFR ESFR memory space The respective SFR addresses can be found in list of SFRs User s Manual 10 2 V 1 6 2001 08 pae 1 fi User s Manual a C166S V1 SubSystem Asynchronous Synchronous Serial Interface ASC Port Input Select Register The PISEL register controls the receiver input selection of the ASC module PISEL Port Input Select Register Reset value 0000p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RIS r rw Field Bits Typ Description RIS 0 rw Receiver Input Select 0 Receiver input RXDYO selected 1 Receiver input RXDY1 selected 0 15 1 Reserved for future use reading returns 0 writing to these bit positions has no effect User s Manual 10 3 V 1 6 2001 08 User s Manual neon Infineon C1 66S V1 SubSystem Asynchronous Synchronous Serial Interface ASC 10 2 Operational Overview Figure 10 3 shows a block diagram of the ASC with its operating modes asynchronous and synchronous mode Prescaler Baudrate Asynchronous Divider Timer Mode Serial Port Control Receive Transmit RXD buffers and Shift Registers folk Baudrate Timer Serial Port Control TXD Synchronous Mode Shift Clock Receive Trans
335. l n Infineon C1 66S V1 SubSystem Detailed Instruction Set RETI Return from Interrupt Subroutine RETI Group Return Instructions Syntax RETI Source Operand s none Destination Operand s none Operation IP SP SP SP 2 IF SYSCON SGTDIS 0 THEN CSP SP SP SP 2 END IF PSW lt SP SP SP 2 Description Returns from an interrupt routine The IP CSP and PSW are popped off the system stack The CSP is only popped if segmentation is enabled This is indicated by the SGTDIS bit in the SYSCON register CPU Flags E Z V C N E Restored from the PSW popped from stack Z Restored from the PSW popped from stack V Restored from the PSW popped from stack C Restored from the PSW popped from stack N Restored from the PSW popped from stack Encoding Mnemonic Format Bytes RETI FB 88 2 User s Manual 6 78 V 1 6 2001 08 1 fi User s Manual UE NN C166S V1 SubSystem Detailed Instruction Set RETP Return from Subroutine and Pop Word RETP Group Return Instructions Syntax RETP op1 Source Operand s none Destination Operand s op1 gt WORD Operation IP SP SP SP 2 tmp SP SP SP 2 op1 lt tmp Description Returns from a subroutine First the IP is popped from the system stack and then the next word is popped from the system stack into the operand specified by op1 CPU Flags E Z V C N E Set if the
336. lay 8 18 READY 8 18 Register CP 3 50 CPUID 3 90 CSP 3 15 DPPx 3 56 DSTPx 3 34 IP 3 15 MDC 3 73 MDH 3 72 MDL 3 72 ONES 3 89 PECCx 3 36 PECSNx 3 35 PSW 3 76 SP 3 61 SRCPx 3 34 STKOV 3 62 STKUN 3 63 SYSCON 3 17 TFR 3 27 xxlC 3 21 3 44 ZEROS 3 89 Reset Control 2 12 S SOBG 10 17 SOEIC SORIC SOTIC SOTBIC 10 23 User s Manual Keyword Index SORBUF 10 13 10 15 SOTBUF 10 11 10 15 SCU 2 12 Segment Address 8 12 boundaries 4 9 Serial Interface Asynchronous 10 9 Synchronous 10 14 SFR 4 5 SFR Table ordered by address 4 12 SFR Table ordered by name 4 32 Single Chip Mode 8 2 Slave mode External bus 8 32 SP Register 3 61 SRCPx Register 3 34 SSC Baudrate generation 11 15 Block diagram 11 4 Error detection 11 17 Full duplex operation 11 10 Half duplex operation 11 13 Interrupts 11 17 Registers 11 8 BR 11 15 CON 11 5 11 6 Overview 10 2 11 2 RB 11 8 TB 11 8 SSCO_BR 11 15 SSCO_CON 11 5 11 6 SSCO_RB 11 8 SSCO_TB 11 8 SSC1_BR 11 15 SSC1_CON 11 5 11 6 SSC1_RB 11 8 SSC1_TB 11 8 STKOV Register 3 62 STKUN Register 3 63 SYSCON 3 16 3 17 8 21 8 36 SYSCON Register 3 17 System Control Unit 2 12 14 3 V 1 6 2001 08 pan e Infineon technologies User s Manual C166S V1 SubSystem T T2 12 16 T2CON 12 16 T3CON 12 6 T4 12 16 T4CON 12 16 T5 12 34 T5CON 12 34 T6 12 28 T6CON 12 28 TFR Register 3 27 Timer Auxiliary Timer 2 4 12 16 Concatenation 12 21 12 38 Timer 2 12 16 Timer 2 Cap
337. le mode and the power down mode mode are supported by the power saving control block Periodic wakeup from Idle mode combines the drastically reduced power consumption in Idle mode in conjunction with the additional power management features with a high level of system availability External signals and events can be scanned at a lower rate by periodically activating the CPU and selected peripherals which then return to powersave mode after a short time This greatly reduces the system s average power consumption Clock Enable Generator CEG The clock enable generator module generates the clock enable signals used by the different clock gates of the subsystem These clock gates are used for the different clock domains CPU Clock Negative CPU Clock Peripheral Clock PDBUS clock The CPU clock and the negative CPU clock shows the same frequency However both clocks have a phase shift of 180 This behavior is used for running the EBC protocol state machine on two clock edges Also the protocol of the local memory bus LM66 Bus is based on two clock edges and needs this two clock domains The peripheral bus clock is limited to 50 MHz For not limiting the core to this frequency the peripherals are decoupled from the CPU by their own clock domain The frequency of the peripheral clock domain is either equal to or half of the CPU clock domain For generating all this enable signals the clock enable generator needs to be supplied b
338. lete DPRAM area This provides a large system stack without requiring procedures to handle data transfers for a circular stack However this method also leaves less RAM space for variables or code The DPRAM area that may be consumed by the system stack is defined via the STKUN and STKOV pointers The underflow and overflow traps in this case serve for fatal error detection only For the linear stack option all modifiable bits of register SP are used to access the physical stack Although the stack pointer may cover addresses from 00 F000 up to 00 FFFE the physical system stack must be located within the DPRAM and therefore may only use the address range 00 F600y to 00 FDFE It is the user s responsibility to restrict the system stack to the DPRAM range User s Manual 3 64 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Central Processing Unit Note Stack accesses below the DPRAM area ESFR space and reserved area and within address range O00 FEO0 and OO FFFE SFR space will have unpredictable results 3 6 3 3 Circular Virtual Stack This basic technique allows pushing until the overflow boundary of the internal stack is reached At this point a portion of the stacked data must be saved into external memory to create space for further stack pushes This is called stack flushing When executing a number of return or pop instructions the upper boundary since the stack emptie
339. line to output until it gets a de selection signal or command The slaves use open drain output on MRST This forms a wired AND connection The receive line needs an external pull up in this case Corruption of the data on the receive line sent by the selected slave is avoided when all slaves not selected for transmission to the master only send ones 1s Because this high level is not actively driven onto the line but only held through the pull up device the selected slave can pull this line actively to a low level when transmitting a zero bit The User s Manual 11 11 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem High Speed Synchronous Serial Interface SSC master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave After performing the necessary initialization of the SSC the serial interfaces can be enabled For a master device the alternate clock line will now go to its programmed polarity The alternate data line will go to either O or 1 until the first transfer will start After a transfer the alternate data line will always remain at the logic level of the last transmitted data bit When the serial interfaces are enabled the master device can initiate the first data transfer by writing the transmit data into register TB This value is copied into the shift register assumed to be empty at this time and th
340. llenges C166S based derivatives does not only integrate a powerful CPU Central Processing Unit core and a set of peripheral units into one chip but also connects the units in a very efficient way One of the four buses used concurrently on the C166S is the Internal Bus Interface an internal representation of the external bus interface This bus provides a standardized method of integrating application specific peripherals to produce derivatives of the standard C166S This manual specially describes the C166S Subsystem consists of the CPU Interrupt Controller ITC Bus Controller BC On Chip Debug Support OCDS and other system specific peripherals and modules The following figure shows the principles of a C166S based system C166S System Internal Bus Interface Interrupt Controller o JTAG User s Manual 2 1 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem System Overview 2 1 Basic CPU Concepts and Mega Core The main core of the CPU consists of a 4 stage instruction pipeline a 16 bit arithmetic and logic unit ALU and dedicated Special Function Registers SFRs Additional hardware is provided for a separate multiply and divide unit a bit mask generator and a barrel shifter To meet the demand for greater performance and flexibility a number of areas has been optimized in the processor core Functional blocks in the CPU core are controlled by signals
341. llers which offer a high level of system integration eliminate the need for additional peripheral devices and the associated software overhead provide system security and fail safe mechanisms provide effective means to control and reduce the device s power consumption About this Manual This manual describes the functionality of the 16 bit microcontroller subsystem C1668S H1 of the Infineon C166 Family the C166S class User s Manual 1 1 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V1 SubSystem Introduction 1 1 The Members of the 16 bit Microcontroller Family The microcontroller subsystem of the Infineon 16 bit family has been designed to meet the high performance requirements of real time embedded control applications The architecture of this family has been optimized for high instruction throughput and minimum response time to external stimuli interrupts Intelligent peripheral subsystems have been integrated to reduce the need for CPU Central Processing Unit intervention to a minimum extent This also minimizes the need for communication via the external bus interface The high flexibility of this architecture allows to serve the diverse and varying needs of different application areas such as automotive industrial control or data communications The core of the 16 bit family has been developed with a modular family concept in mind All family members execute an efficient control
342. logies Encoding Mnemonic SHL SHL User s Manual User s Manual C166S V1 SubSystem Rw data4 Rw RWm Format 5C n 4C nm 6 87 Detailed Instruction Set Bytes 2 2 V 1 6 2001 08 1 fi User s Manual nrineon M a C166S V1 SubSystem Detailed Instruction Set SHR Shift Right SHR Group Shift and Rotate Instructions Syntax SHR op1 op2 Source Operand s op1 gt WORD op2 shift counter Destination Operand s op1 gt WORD Operation count op2 C 0 V 0 DO WHILE count 0 V C v V C lt op1 0 op1 n op1 n 1 n 0 14 op1 15 0 count lt count 1 END WHILE Description Shifts the destination word operand op1 right by the number of times as specified by the source operand op2 The most significant bits of the result are filled with zeros accordingly Since the bits shifted out effectively represent the remainder the Overflow flag is used instead as a Rounding flag A shift right is a division by a power of two The overflow flag with the carry flag allows to determine whether the fractional part of the division result is greater than less than or equal to one half 0 5 in decimal base This allows to round the division result accordingly Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used CPU Flags E Z V C N Le 9 s E Always cle
343. mains 2 clock cycles one machine cycle Execution from the DPRAM provides flexibility in terms of loadable and modifiable code The execution time from external memory depends strongly on the selected bus mode and the programming of the bus cycles waitstates User s Manual 3 87 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit The operand and instruction accesses listed below can extend the execution time of an instruction Internal Local Memory operand accesses same for byte and word operand accesses DPRAM operand reads via indirect addressing modes nternal SFR operand reads immediately after writing External operand reads External operand writes e Jumps to non aligned double word instructions in the internal local memory space Testing branch conditions immediately after PSW writes User s Manual 3 88 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 9 Dedicated CSFRs The Constant Zeros Register ZEROS All bits of this bit addressable register are fixed at O by hardware This register is read only Register ZEROS can be used as a register addressable constant of all zeros for bit manipulation or mask generation It can be accessed via any instruction capable of accessing an SFR Zeros Constant Zeros Register SFR FF1Cy 8E Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
344. may specify ONLY GPR registers Once the subtraction has completed the operand op1 is incremented by one Using the set flags a branch instruction can then be used in conjunction with this instruction to form common high level language FOR loops of any range CPU Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the word data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes CMPI1 Rw data16 86 Fn 4 CMPI1 Rw data4 80 n 2 CMPI1 Rw mem 82 Fn MM MM 4 User s Manual 6 29 V 1 6 2001 08 1 fi User s Manual a C166S V1 SubSystem Detailed Instruction Set CMPI2 Integer Compare and Increment by 2 CMPI2 Group Compare and Loop Control Instructions Syntax CMPI2 op1 op2 Source Operand s op1 op2 gt WORD Destination Operand s op1 gt WORD Operation op1 e 0p2 op1 lt op1 2 Description This instruction is used to enhance the performance and flexibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 Operand op1 may sp
345. mented register banks arbitrary sizes is limited only by the size of the available DPRAM User s Manual 4 11 V 1 6 2001 08 1 fi User s Manual SUE NN C166S V1 SubSystem Memory Organization 4 7 SFR ESFR Table The following table lists all SFRs ESFRs which are implemented in the C166S V1 SubS R1 ordered by their physical address Table 4 2 SFR ESFR Table ordered by physical address Physical Name Type 8 bit Description Reset Address Addr Value F000 reserved ESFR 00 reserved do not use F0024 reserved ESFR 01g reserved do not use F0044 reserved ESFR 024 reserved do not use FO06y reserved ESFR 03y reserved do not use FO008H reserved ESFR 04 4 reserved do not use FOOA y reserved ESFR 05 4 reserved do not use FOOCy CPUID ESFR 06 CPU Identification Register 0410 FOOE y reserved ESFR 074 reserved do not use FO10y reserved ESFR 08 reserved do not use F012 reserved ESFR 09 reserved do not use F014 XADRS1 ESFR OAy XBUS Address Select Register 1 00004 F016 XADRS2 ESFR OB XBUS Address Select Register 2 00004 F018 XADRS3 ESFR 0Cy XBUS Address Select Register 3 00004 FO1Ay XADRS4 ESFR 0D XBUS Address Select Register 4 00004 FO1Cy XADRS5 ESFR OE XBUS Address Select Register 5 00004 FOIE XADRS6 ESFR OFy XBUS Address Select Register 6 00004 FO20y ESFR 104 F022 ESFR 11
346. mer T5 is cleared T5CLR cleared Thus register CAPREL always contains the correct time between two events measured in Timer T5 increments Timer T6 which runs in Timer Mode counting down with a frequency of 4 for example uses the value in register CAPREL to perform a reload on underflow This means that the value in register CAPREL represents the time between two underflows of Timer T6 now measured in Timer T6 increments Because Timer T6 runs eight times faster than Timer T5 it will underflow eight times within the time between two external events Thus the underflow signal of Timer T6 generates eight ticks Upon each underflow the interrupt request flag T6IR will be set and bit T6OTL will be toggled The state of T6OTL may be output on line T6OUT This signal has eight times more transitions than the signal applied to line CAPIN A certain deviation of the output frequency is generated by the fact that Timer T5 will count actual time units for example T5 running at 1 MHz will capture the value 64 100p for a 10 KHz input signal while T6OTL will only toggle upon an underflow of T6 that is the transition from 0000 to FFFF j In the above mentioned example T6 would count down from 64 so the underflow would occur after 101 T6 timing ticks The actual output frequency then is 79 2 KHz instead of the expected 80 KHz This can be solved by activating the Capture Correction T5CC is set If capture correction is active the cont
347. mer overflow can be signaled by wdtint n o When the watchdog timer reset is enabled default and the software has been designed to service it regularly before it overflows the watchdog timer will supervise the program execution as it only will overflow if the program does not progress properly The watchdog timer will also time out if a software error was due to hardware related failures This prevents the controller from malfunctioning for longer than a user specified time The watchdog timer reset resets the CPU Interruptcontroller the External Bus Controller the Control Block and the WDT itself The wdtint n o always shows the occurrence of a watchdog timer overflow If the watchdog timer reset is disabled the WDTINT signal can be used to trigger an interrupt The wdtint n o signals can be directly connected to one interrupt control node The watchdog timer can be used as a running timer and generates a periodical interrupt request with the occurrence of a timer overflow In case of an overflow the WDT counter is automatically reloaded Nevertheless the automatic reload is overruled in case of a WDT reset wdt reset not disabled The WDT can still be serviced with the execution of the srvwat instruction Note The WDT is automatically reloaded in case of a WDT overflow In case of an enabled WDT reset the generated reset resets the WDT and overrules the reload mechanism The watchdog timer provides two 16 bit registers and two subsystem
348. might occur if the sensor rests near one of its switching points is compensated User s Manual 12 14 V 1 6 2001 08 7 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit Forward Jitter Backward Jitter Forward Contents of T3 Note This example shows the timer behavior assuming that T3 counts upon any transition on any input i e T3l 0115g Figure 12 9 Evaluation of the Incremental Encoder Signals Forward Jitter Backward Jitter Forward Contents of T3 Note This example shows the timer behavior assuming that T3 counts upon any transition on input T3IN i e T3I 001g Figure 12 10 Evaluation of the Incremental Encoder Signals Note Timer T3 operating in Incremental Interface Mode automatically provides information about the sensor s current position Dynamic information speed acceleration deceleration may be obtained by measuring the incoming signal periods User s Manual 12 15 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit 12 2 2 Auxiliary Timers T2 and TA T2 Timer 2 Reset value 0000p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T2 rwh T4 Timer 4 Reset value 0000p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T4 rwh T
349. mit buffers and RXD Shift Registers TXD Figure 10 3 Block Diagram of the ASC User s Manual 10 4 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Asynchronous Synchronous Serial Interface ASC 10 3 General Operation The ASC supports full duplex asynchronous communication up to 3 75 MBaud and half duplex synchronous communication up to 7 5 MBaud 60 MHz module clock In Synchronous Mode data are transmitted or received synchronous to a shift clock that is generated by the microcontroller In Asynchronous Mode either 8 or 9 bit data transfer parity generation and the number of stop bits can be selected Parity framing and overrun error detection is provided to increase the reliability of data transfers Transmission and reception of data is double buffered For multiprocessor communication a mechanism is provided to distinguish address bytes from data bytes Testing is supported by a loop back option A 13 bit baudrate timer with a versatile input clock divider circuitry provides the serial clock signal A transmission is started by writing to the Transmit Buffer register TBUF The selected operating mode determines the number of data bits that will actually be transmitted so that bits written to positions 9 through 15 of register TBUF are always insignificant Data transmission is double buffered so a new character may be written to the transmit buffer register before the transmi
350. mplementation is similar to the implementation in the C166 microcontrollers however its parameters are changeable to work with parallel busses of different width and with different protocols Features Full duplex asynchronous operating modes 8 or 9 bit data frames LSB first Parity bit generation checking One or two stop bits Baudrate from 3 75 MBaud to 0 888 Baud 60 MHz module clock f Multiprocessor Mode for automatic address data byte detection Loop back capability Half duplex 8 bit synchronous operating mode Baudrate from 7 5 MBaud to 764 4 Baud 60 MHz module clock fj Double buffered transmitter receiver Interrupt generation on a transmitter buffer empty condition on a transmit last bit of a frame condition on a receiver buffer full condition on an error condition frame parity overrun error User s Manual 10 1 V 1 6 2001 08 m User s Manual Infineon C1668 V1 SubSystem Asynchronous Synchronous Serial Interface ASC Figure 10 1 shows all funtional relevant interfaces associated with the ASC Kernel Clock Control Address bur Decoder PES Kernel Control BPI Product Module Interface Interface Figure 10 1 ASC Interface Diagram Figure 10 2 shows all of the registers associated with the ASC Kernel Control Registers Data Registers TBUF RBUF CON Control Register TBUF Transmit Buffer Register FDV Fractional Divider Register RBUF Rece
351. n WR acts as WRL pin BHE acts as WRH CLKEN 8 rw System Clock Enable CLKOUT cleard after reset O CLKOUT disabled pin may be used for general purpose lO 1 CLKOUT enabled pin outputs the system clock signal BYTDIS 9 rwh Disable Enable Control for Pin BHE Set according to data bus width 0 Pin BHE enabled n Pin BHE disabled pin may be used for general purpose IO User s Manual 8 22 V 1 6 2001 08 pae 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem The External Bus Interface Field Bits Type Description Note Register SYSCON cannot be changed after execution of the EINIT instruction The layout of the BUSCON registers and ADDRSEL registers is identical Registers BUSCON4 BUSCON1 which control the selected address windows are completely under software control Register BUSCONO which is also used for the very first code access after reset is partly controlled by hardware e it is initialized via dedicated configuration signals during the reset sequence This hardware control allows an appropriate external bus to be defined for systems in which no internal program memory is provided User s Manual 8 23 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem BUSCONO Bus Control Register 0 SFR FF0C 86 The External Bus Interface Reset value OXX0y
352. n multiplexed bus modes implicitly add one tristate time waitstate in addition to the programmable MTTC waitstate User s Manual 8 17 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface 8 3 4 Read Write Signal Delay The C166S allows the user to adjust the timing of the read and write commands to account for timing requirements of external peripherals The read write delay controls the time between the falling edge of ALE and the falling edge of the command Without read write delay the falling edges of ALE and command s are concurrent except for propagation delays With the delay enabled the command s become active half a CPU clock 1 TCL after the falling edge of ALE The read write delay does not extend the memory cycle time and does not slow down the controller In multiplexed bus modes however the data drivers of an external device may conflict with the C166S s address when the early RD signal is used Therefore multiplexed bus cycles should always be programmed with read write delay The read write delay is controlled via the Read Write Delay Control RWDCx bits in the BUSCON registers The command s will be delayed if bit RWDOx is O default after reset 8 3 5 Early WR The duration of an external write access can be shortened by one TCL The WR signal is activated driven low in the standard way but can be deactivated driven high one TCL earlier than d
353. n this case T3OTL serves as input for the counter function or as trigger source for the reload function of T2 and T4 T3OTL is internally connected for this functionality and it is not necessary to enable overflow underflow output on T3OUT for this purpose User s Manual 12 8 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit Timer 3 in Timer Mode Timer Mode for core Timer T3 is selected by setting bitfield T3M in register T3CON to 000p A block diagram of T3 in Timer Mode is shown in Figure 12 4 In this mode T3 is clocked with the module clock f divided by a programmable prescaler block controlled by bitfield T3I and BPS1 The input frequency fr4 for Timer T3 and its resolution rra are scaled linearly with lower module clock frequencies as can be seen from the following formula folk lt BPS1 gt 2 lt 13b rrz ms fpa ul lt BPS1 gt 2 lt sl gt f MHz Note lt BPS1 gt represents the prescaler value of the prescaler part controlled by bitfield BPS1 For the values see the bit description in register T3CON Table 12 2 Timer 3 Input Parameter Selection Timer and Gated Timer Modes T3I Prescaler for f Prescaler for fj Prescaler for f 1 Prescaler for f BPS1 00 BPS1 01 BPS1 10 BPS1 11 000 8 4 32 16 001 16 8 64 32 010 32 16 128 64 011 64 32 256 128 100 128 64 512 256 101 256 128 1024 512
354. n which the parameters in register BUSCONx are used to control external accesses The range start address of such a window defines the upper address bits which are not used within the address window of the specified size see table below For a given window size only those upper address bits of the start address marked R that are not implicitly used for addresses inside the window are used The lower bits of the start address marked x are disregarded Table 8 6 Address Window Definition Bit field RGSZ Resulting Window Size Relevant Bits R of Start Addr 12 0000 4 KByte RRRRRRRRRRRR 0001 8 KByte RRRRRRRRRR R ox 0010 16 KByte RRRRRRRRRR xX x 0011 32 KByte RRRRRRRRRX x x 0100 64 KByte RRRRRRRRX X X X 0101 128 KByte R RRRRR RX xX xX xX X 0110 256 KByte RR RRR RX X xX X xXx x 0111 512 KByte R R RRR xX X X X X xXx X 1000 1 MByte RR R Rx X X X X X X X 1001 2 MByte R R RX X X X X Xx X X X 1010 4 MByte R Rx xx X X X X X X X 1011 8 MByte RX X X X X X X X X X x 11xx Reserved Address Window Arbitration The address windows that can be defined within the C166S s address space may partly overlap each other Thus small areas may be cut out of bigger windows for example in order to utilize external resources effectively especially within segment 0 For each access the EBC compares the current address with all address select registers programmable ADDRSELx and hardwired programmable XADRSx This comparison i
355. n with 0 Note The target of an access to CON control bits or flags is determined by the state of CON EN prior to the access that is writing C0574 to CON in programming mode CON EN 0 will initialize the SSC CON EN was 0 and then turn it on CON EN 1 When writing to CON ensure that reserved locations receive zeros User s Manual 11 7 V 1 6 2001 08 pan 7 fi User s Manual n Infineon C1 66S V1 SubSystem High Speed Synchronous Serial Interface SSC The shift register of the SSC is connected to both the transmit lines and the receive lines via the pin control logic see block diagram in Figure 11 3 Transmission and reception of serial data are synchronized and take place at the same time i e the same number of transmitted bits is also received Transmit data is written into the Transmit Buffer TB It is moved to the shift register as soon as this is empty An SSC master CON MS 1 immediately begins transmitting while an SSC slave CON MS 0 will wait for an active shift clock When the transfer starts the busy flag CON BSY is set and the Transmit Interrupt Request line TIR will be activated to indicate that register TB may be reloaded again When the programmed number of bits 2 16 has been transferred the contents of the shift register are moved to the Receive Buffer RB and the Receive Interrupt Request line RIR will be activated If no further transfer is to take place TB is empty CON BSY will be cle
356. nal Must be within the internal Core RAM area Figure 3 7 Implicit CP Use by logical Short GPR Addressing Modes 24 Bit memory addresses within a range from CP 0 to CP 30 can be used to access GPRs directly Both byte and word GPR accesses are possible The 24 bit memory address is generated according to the rules for long and indirect addressing modes Section 3 6 2 User s Manual 3 47 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit Table 3 10 Addressing modes to Access Word GPRs Name Physical 8 Bit 4 Bit Description Reset Address Address Address Value RO CP 0 FO Op General Purpose word Register RO UUUU R1 CP 2 Fly 1 General Purpose word Register R1 UUUU R2 CP 4 F2 24 General Purpose word Register R2 UUUU R3 CP 6 F3 34 General Purpose word Register R3 UUUU R4 CP 8 F4 4y General Purpose word Register R4 UUUU R5 CP 10 F54 5H General Purpose word Register R5 UUUU R6 CP 12 F6 64 General Purpose word Register R6 UUUU R7 CP 14 F7 74 General Purpose word Register R7 UUUU R8 CP 16 F8 84 General Purpose word Register R8 UUUU R9 CP 18 F94 94 General Purpose word Register R9 UUUU R10 CP 20 FA Ay General Purpose word Register R10 UUUU R11 CP 22 FB By General Purpose word Register R11 UUUU R12 CP
357. nal s PORTO Address and data lines when accessing AD15 ADO external resources e g memory PORT1 Address lines when accessing ext resources A15 AO Port 4 Selected segment address lines in systems A23 A16 with more than 64 KBytes of external resources Port 6 Chip select output signals CS4 CSO If an alternate output function of a pin is to be used the direction of this pin must be programmed for output DPx y 1 except for some signals that are used directly after reset and are configured automatically Otherwise the pin remains in the high impedance state and is not effected by the alternate output function The respective port register should hold a 1 because its output is combined with the alternate output data If an alternate input function of a pin is used the direction of the pin must be programmed for input DPx y 0 if an external device is driving the pin The input direction is the default after reset If no external device is connected to the pin however one can also set the direction for this pin to output In this case the pin reflects the state of the port output register Thus the alternate input function reads the value stored in the port output register This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output register On most of the port lines the user software is responsible for sett
358. ncorrect interrupt vector may be generated In the second arbitration stage the priority level of the first stage winner is compared with the priority of the current CPU task An action request will be accepted by the CPU ifthe requesting source has a higher priority level than the current CPU priority level bits ILVL of the PSW register and if interrupts are enabled globally by the global IEN flag in User s Manual 3 20 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit PSW The CPU denies all requests in case of a cleared IEN flag If the requester has a lower or equal priority level than current CPU task the request stays pending Note Priority level 0000g is the default level of the CPU Therefore a request on ILVL 0000g will be arbitrated but the CPU will never accept an action request on this level However every enabled interrupt request including all denied interrupt requests also priority level 0000g requests triggers a CPU wake up from idle state independent of the setting of the global interrupt enable bit PSW IEN Note The first 16 trap numbers are reserved for the CPU traps The first usable interrupt trap number starts with 104 Therefore the number of interrupt nodes is limited to 112 All interrupt control registers are organized identically The lower 8 bits of an interrupt control register contain the complete interrupt control and status information
359. nd execution of either the EINIT End of Initialization or the SRVWDT Service Watchdog Timer instruction Either one of these instructions disables the execution of DISWDT Note The above described protection using the execution of EINIT or SRVWDT must be implemented inside the WDT block A watchdog reset will not complete a running external bus cycle before starting the internal reset sequence To prevent the watchdog timer from overflowing it must be serviced periodically by the user software The watchdog timer is serviced with the instruction SRVWDT which is a protected 32 bit instruction Servicing the watchdog timer clears the low byte and reloads User s Manual 9 2 V 1 6 2001 08 1 fi User s Manual nrineon M s C166S V1 SubSystem Watchdog Timer the high byte of the watchdog timer register WDT with the preset value from bitfield WDTREL which is the high byte of register WDTCON After being serviced the watchdog timer continues counting up from the value lt WDTREL gt 29 Note SRVWDT always triggers a timer reload independent of the execution of the EINIT and DISWDT instruction Instruction SRVWDT has been encoded in such a way that the chance of unintentionally servicing the watchdog timer e g by fetching and executing a bit pattern from a wrong location is minimized When instruction SRVWDT does not match the format for protected instructions the Protection Fault Trap will be entered rather than th
360. nder of the instruction flow must be executed correctly This explains why Class A traps cannot interrupt atomic extend sequences In case of an atomic extend sequence the execution continues until sequence completion Upon completion the IP of the instruction following the last executed one is pushed onto the stack If more than one Class A trap occurs at a same time they are prioritized internally The NMI trap has the highest priority and the stack underflow trap has the lowest Note When two different Class A traps occur simultaneously both trap flags are set The trap with the higher priority is executed After return from the service routine the IP is popped from the stack and immediately pushed again because of the other pending Class A trap unless the second trap flag in TFR has been cleared by the first trap service routine External NMI Trap NMI Whenever a high to low transition on the dedicated NMI is detected the NMI flag in register TFR is set and the CPU will enter the NMI trap routine The IP value pushed on the system stack is the address of the instruction following the one after which normal processing was interrupted by the NMI trap Note The NMI is sampled with every CPU clock cycle to detect transitions User s Manual 3 29 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit STacK OverFlow Trap STKOF Whenever the stack pointer SP is decrem
361. nfineon technologies User s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary cont d Mnemonic Description Bytes Arithmetic Operations cont d ADDCB mem reg Add direct byte register to direct memory with Carry 4 SUB Rw Rw Subtract direct word GPR from direct GPR 2 SUB Rw Rw Subtract indirect word memory from direct GPR 2 SUB Rw Rw Subtract indirect word memory from direct GPR and 2 post increment source pointer by 2 SUB Rw data3 Subtract immediate word data from direct GPR 2 SUB reg datai6 Subtract immediate word data from direct register 4 SUB reg mem Subtract direct word memory from direct register 4 SUB mem reg Subtract direct word register from direct memory 4 SUBB Rb Rb Subtract direct byte GPR from direct GPR 2 SUBB Rb Rw Subtract indirect byte memory from direct GPR 2 SUBB Rb Rw Subtract indirect byte memory from direct GPR and 2 post increment source pointer by 1 SUBB Rb data3 Subtract immediate byte data from direct GPR 2 SUBB reg data8 Subtract immediate byte data from direct register 4 SUBB reg mem Subtract direct byte memory from direct register 4 SUBB mem reg Subtract direct byte register from direct memory 4 SUBC Rw Rw Subtract direct word GPR from direct GPR with Carry 2 SUBC Rw Rw Subtract indirect word memory from direct GPR with Carry 2 SUBC Rw Rw Subtract indirect
362. ngle bits or bit groups internally use a read modify write sequence that accesses the whole word which contains the specified bit s This method has several consequences Bits can only be modified within the internal address areas i e DPRAM and SFRs External locations cannot be used with bit instructions The upper 256 bytes of the SFR area the ESFR area and the DPRAM are bit addressable see Memory Organization Chapter 4 i e those register bits located within the respective sections can be manipulated directly using bit instructions The other SFRs must be accessed byte or word wise Note All GPRs are bit addressable independent of the allocation of the register bank via the context pointer CP Even GPRs which are allocated to not bit addressable RAM locations provide this feature The read modify write approach may be critical with hardware effected bits In these cases the hardware may change specific bits while the read modify write operation is in progress where the write back would overwrite the new bit value generated by the hardware The solution is either to use the implemented hardware protection see below or through special programming see Particular Pipeline Effects Section 3 8 Protected bits are not changed during the read modify write sequence i e when hardware sets an interrupt request flag between the read and the write of the read modify write sequence for example The hardware protection logic gu
363. nly for the internal LM area Devices with an LM size above 32 KByte expand the LM area from the middle of segment 1 i e starting at address 01 8000 The internal LM can be used for both code instructions and data constants tables etc storage Code fetches are always made on even byte addresses The highest possible code storage location in the internal LM is either xxxxFEy for single word instructions or XX XxXFCy for double word instructions The respective location must contain a branch instruction unconditional because sequential boundary crossing from internal LM to external memory is not supported and causes erroneous results Any word and byte data read accesses may use the indirect or long 16 bit addressing modes There is no short addressing mode for the LM operands Any word data access is made to an even byte address Any double word access is made to a modulo 4 address even word address The highest possible word data storage location in the LM is xxxx xxFEyu the highest double word location is xxxx xxFCy The internal LM is not provided for single bit storage and therefore it is not bit addressable Note The x in the locations above depend on the available internal LM User s Manual 4 4 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Memory Organization 4 3 DPRAM and SFR Area The C166S differentiates between the internal data memory DPRAM and the internal pe
364. nologies User s Manual C166S V1 SubSystem Central Processing Unit PECISNC PEC Interrupt Sub Node Control SFR H H Reset value 0000y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C7IR C7IE C6IR CeIE C5IR CBIE C4IR C4IE C3IR C3IE C2IR C2IE C1IR C1IE COIR COIE rwh rw rwh rw wh rw mwh rw rwh rw wh rw wh rw rwh rw PECXISNC PEC Interrupt Sub Node Control SFR H H Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C15 C15 C14 C14 C13 C13 C12 C12 C11 C11 C10 C10 C9 C9 C8 C8 IR IE IR IE IR IE IR IE IR IE IR IE IR IE IR IE rh rw rwh rw wh rw mwh rw wh rw wh rw wh rw rwh rw Field Bits Type Description CxIR 15 13 rwh Interrupt Sub Node Request Flag of PEC Channel 11 9 x 1 2 7 5 3 0 No special EOP interrupt request is pending 1 for PEC channel x 1 PEC channel x has raised an EOP interrupt request CxIE 14 12 rw Interrupt Sub Node Enable Control Bit 0 8 of PEC Channel x 3 6 4 2 individually enables disables a specific source 0 0 EOP interrupt request of PEC channel x is disabled 1 EOP interrupt request of PEC channel x is enabled 1 x 15 0 2 NOTE The EOP sub node interrupt request flags are not cleared by hardware when entering the ISR interrupt has been accepted by the CPU unlike the interrupt request flags of the in
365. ns During external accesses in demultiplexed bus modes PORT1 outputs the 16 bit intra segment address as an alternate output function During external accesses in multiplexed bus modes when no BUSCON register selects a demultiplexed bus mode PORT1 is not used and is available for general purpose lO When an external bus mode is enabled the direction of the port pin and the loading of data into the port output register are controlled by the bus controller hardware The input of the port output register is disconnected from the internal bus and is switched to the line labeled Alternate Data Output via a multiplexer The alternate data is the 16 bit intrasegment address While an external bus mode is enabled the user software should not write to the port output register otherwise unpredictable results may occur When the external bus modes are disabled the contents of the direction register last written by the user becomes active User s Manual 7 8 V 1 6 2001 08 1 fi User s Manual SUE NN C166S V1 SubSystem Parallel Ports The figures below show the structure of PORT1 pins The upper 4 pins of PORT1 combine internal bus data and alternate data output before the port register input Internal Bus Port Output Direction Register Register AltDir 1 AltDataOut Input Register Porti 1 vsd Figure 7 5 Block Diagram of a PORT1 Pin with Address Function
366. ns which do not access any explicitly addressed data Description This part provides a brief description of the action that is executed by the respective instruction User s Manual C166S V1 SubSystem Instruction Set Condition Code The Condition code indicates that respective instruction is executed if the specified condition exists and is skipped if it does not The table below summarizes the 16 possible condition codes that can be used within Call and Branch instructions The table shows the abbreviations the test that is executed for a specific condition and a 4 bit number associated with condition code Condition Test Description Condition Code Code Number c Mnemonic cc cc UC 123 Unconditional OH cc_Z Z 1 Zero 2H cc_NZ Z 0 Not zero 3H cc_V V 1 Overflow 44 cc_NV V 0 No overflow 5H cc_N N 1 Negative 6h cc_NN N 0 Not negative 7H cc_C C 1 Carry 8H cc_NC C 0 No carry 9H cc_EQ Z 1 Equal 2H cc_NE Z 0 Not equal 3H cc_ULT C 1 Unsigned less than 8H cc_ULE ZvC 1 Unsigned less than or equal Fu cc_UGE C 0 Unsigned greater than or equal 94 cc_UGT ZvC 0 Unsigned greater than En cc_SLT NOV 1 Signed less than Cy cc SLE Zv N V 21 Signed less than or equal Bu cc SGE NOV 0 Signed greater than or equal Dy User s Manual 5 23 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Instruction
367. nsmit data on the leading clock edge latch on trailing edge 1 Latch receive data on leading clock edge shift on trailing edge PO 6 rw Clock Polarity Control 0 Idle clock line is low leading clock edge is low to high transition 1 Idle clock line is high leading clock edge is high to low transition User s Manual 11 5 V 1 6 2001 08 pae e Infineon technologies User s Manual C166S V1 SubSystem High Speed Synchronous Serial Interface SSC Field Bits Type Description LB 7 rw Loop Back Control 0 Normal output 1 Receive input is connected with transmit output half duplex mode TEN 8 rw Transmit Error Enable 0 Ignore transmit errors 1 Check transmit errors REN 9 rw Receive Error Enable 0 Ignore receive errors 1 Check receive errors PEN 10 rw Phase Error Enable 0 Ignore phase errors 1 Check phase errors BEN 11 rw Baudrate Error Enable 0 Ignore baudrate errors 1 Check baudrate errors AREN 12 rw Automatic Reset Enable 0 No additional action upon a baudrate error 1 The SSC is automatically reset upon a baudrate error MS 14 rw Master Select 0 Slave Mode Operate on shift clock received via SCLK 1 Master Mode Generate shift clock and output it via SCLK EN 15 rw Enable Bit 0 Transmission and reception disabled Access to control bits 0 13 r Reserved returns 0 if read should be written with 0 CON EN 1 Operating Mode
368. nterrupt 00004 Control Register F19Ey IRQ39IC ESFR b CF4 IRQ39 Interrupt Control Register 00004 F1A0y ESFR b DO F1A2y ESFR b D1y F1A4y ESFR b D24 F1A6y ESFR b D3y F1A8y ESFR b D4 F1AA ESFR b D54 F1AC ESFR b D6y F1AE ESFR b D7 F1BOy ESFR b D8 F1B2y ESFR b D94 F1B4y ESFR b DA F1B6y ASCOPISEL ESFR b DB ASCO Port Input Selection 00004 Register F1B8j ESFR b DO F1BA ESFR b DD F1BCy ESFR b DE F1BEy ESFR b DFy F1C0y ESFR b EO F1C2y ESFR b Ely F1C4y ESFR b E24 F1C6H ESFR b E3y FiC8y ESFR b E44 F1CA ESFR b E54 FiCCy ESFR b E64 User s Manual 4 20 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value F1CEy ESFR b E7y F1D0y ESFR b E84 F1D2y ESFR b E94 F1D4 ESFR b EAy F1D6y ESFR b EBy F1D8y ESFR b EC F1DAy ESFR b ED F1DCy ESFR b EE F1DEy ESFR b EFy F1E0y reserved reserved do not use F1E24 reserved reserved do not use F1E44 reserved reserved do not use F1E6y reserved reserved do not use F1E8y reserved reserved do not use F1EA reserved reserved do not use F1EC reserved reserved
369. o correctly set the condition flags Multiple precision arithmetic is provided through a CARRY IN signal to the ALU from previously calculated portions of the desired operation Most internal execution blocks have been optimized to perform operations on either 8 bit or 16 bit quantities Once the pipeline has been filled one instruction is completed per machine cycle except for multiply and divide An advanced Booth algorithm has been incorporated to allow four bits to be multiplied and two bits to be divided per machine cycle Thus these operations use two coupled 16 bit registers MDL Multiply Divide Low Word and MDH Multiply Divide High Word and require four and nine machine cycles respectively to perform a 16 bit by 16 bit or 32 bit by 16 bit calculation plus one machine cycle to setup and adjust the operands and the result Even these longer multiply and divide instructions can be interrupted during their execution to allow for very fast interrupt response Instructions have also been provided to allow byte packing in memory while providing sign extension of bytes for word wide arithmetic operations The internal bus structure also allows transfers of bytes or words to or from peripherals based on the peripheral requirements A set of consistent flags is automatically updated in the PSW Program Status Word after each arithmetic logical shift or movement operation These flags allow branching on specific conditions Support for
370. o an odd byte address the ILLOPA flag in register TFR is set and the CPU enters the illegal word operand access trap routine The IP value pushed onto the system stack is the address of the instruction following the one that caused the trap ILLegal INstruction Access Trap ILLINA Whenever a branch is made to an odd byte address the ILLINA flag in register TFR is set and the CPU enters the illegal instruction access trap routine The IP value pushed onto the system stack is the illegal odd target address of the branch instruction ILLegal external BUS access Trap ILLBUS Whenever the CPU requests an external instruction fetch or a data read or a data write and no external bus configuration has been specified the ILLBUS flag in register TFR is set and the CPU enters the illegal bus access trap routine The IP value pushed onto the system stack is the address of the instruction following the one that caused the trap User s Manual 3 31 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Central Processing Unit 3 4 6 Peripheral Event Controller The Peripheral Event Controller PEC decides which CPU action is required to manage an interrupt request It may be either normal interrupt service or fast data transfer between two memory locations The C166S PEC controls up to sixteen fast data transfer channels If a normal interrupt is requested the CPU temporarily suspends the cur
371. o be moved All pointers are 24 bits wide The 24 bit source address is stored in the internal DPRAM location SRCPx lower 16 bits of address and in the low byte of register PECSNx highest 8 address bits PECSNx SRCSNx DSTSNx 15 87 0 23 16 15 0 23 16 15 0 Segment Address Segment Offset Segment Address Segment Offset Data Transfer X 15 0 depending on PEC channel number Figure 3 5 PEC Pointer Address Handling The 24 bit destination address is stored in the DPRAM location DSTPx lower 16 bits of address and in the high byte of register PECSNx highest 8 address bits Only the lower 16 bits of the PEC address pointers segment offset can be modified incremented by the PEC transfer mechanism The highest 8 bits which represent the segment number are not modified by hardware Therefore the PEC pointers may be incremented within the address space of one segment and may not cross the segment border If the offset address pointer has a value of FFFFy in the case of byte transfers BWT 1 or FFFEy in the case of word transfers BWT 0 the next increment will lead to an overflow No explicit error event is generated by the system in case of address pointer s overflow therefore the user must prevent this condition from occurring User s Manual 3 33 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Central Processing Unit Note If a w
372. o the memory location pointed to by the contents of the CP register i e the base of contents of the current register bank Both byte wise and word wise GPR accesses are possible The short 4 bit GPR address is logically added to the contents of register CP if a byte Rb GPR address is specified or multiplied by two and then added to CP if a word Rw GPR address is specified see Figure 3 7 User s Manual 3 46 V 1 6 2001 08 1 fi User s Manual nrineon M os C166S V1 SubSystem Central Processing Unit Note If GPRs are used as indirect address pointers they are always accessed word wise For some instructions only the first 4 GPRs RO R1 R2 and R3 can be used as indirect address pointers These GPRs are specified via short 2 bit GPR addresses The physical address calculation is identical to the one for the short 4 bit GPR addresses Short 8 bit register addresses mnemonic reg or bitoff within a range from FO to FF y interpret the four least significant bits as a short 4 bit GPR address while the four most significant bits are ignored The physical GPR address is calculated in a similar fashion as the short 4 bit GPR addresses For single bit GPR accesses the GPR s word address is calculated in the same way The accessed bit position within the word is specified by a separate additional 4 bit value Specified by reg or bitoff 12 Bit Context Pointer A 11 4 Bit GPR For byte GPR accesses Inter
373. o timers form a 32 bit timer 33 bit Timer Counter If either a positive or a negative transition of TSOTL is selected to clock the auxiliary timer this timer is clocked on every second overflow underflow of core Timer T3 This configuration forms a 33 bit timer 16 bit core timer T3OTL 16 bit auxiliary timer The count directions is not required to be the same in the two concatenated timers This offers a wide variety of different configurations T3 can operate in Timer Mode Gated Timer Mode or Counter Mode in this case BPS1 T3I T3R Up Down Edge Select X224 MCBO02034 d Auxiliary Timer Tx gt TxIRQ TxR Up Down Figure 12 12 Concatenation of Core Timer T3 and an Auxiliary Timer Note Line is affected by over underflow of T3 only but NOT by software modifications of T3OTL User s Manual 12 21 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem General Purpose Timer Unit Auxiliary Timer in Reload Mode Reload Mode for the auxiliary timers T2 and T4 is selected by setting bitfield TxM in the respective register TxCON to 100g In Reload Mode core Timer T3 is reloaded with the contents of an auxiliary timer register triggered by one of two different signals The trigger signal is selected the same way as the clock source for Counter Mode see Table 12 8 That is a transition of the auxiliary timer s input or the output toggle latch TSOT
374. ock 1 fpppus 4 maximum resolution 3 independent timers counters Timer counters can be concatenated 4 operation modes timer gated timer counter incremental Seperate interrupt lines General Purpose Timer Unit Timer Block 2 froBus 2 maximum resolution 2 independent timers counters Timer counters can be concatenated 3 operation modes timer gated timer counter Extendend capture reload functions Seperate interrupt lines Asynchronous Sychronous Serial Channel ASCO with baud rate generator parity framing and overrun error detection High Speed Synchronous Serial Cannel SSCO with baud rate generator programmable data length and shift direction e Watchdog Timer with programmable timer events User s Manual 1 4 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Introduction Complete Development Support For the development tool support of its microcontrollers Infineon follows a clear third party concept Currently around 120 tool suppliers world wide ranging from local niche manufacturers to multinational companies with broad product portfolios offer powerful development tools for the Infineon C166 C166S microcontroller families guaranteeing a remarkable variety of price performance classes as well as early availability of high quality key tools such as compilers assemblers simulators debuggers or in circuit emulators Infineon
375. of a Class A trap service routine any Class B trap will not be serviced until the Class A trap service routine is exited with a RETI instruction In this case the Class B trap condition is stored in the TFR but the IP value of the instruction that caused this trap will be lost UNDefined OPCode Trap UNDOPC When the instruction currently decoded by the CPU does not contain a valid C166S opcode the UNDOPC flag is set in the TFR and the CPU enters the undefined opcode trap routine The IP value pushed onto the system stack is the address of the instruction that caused the trap This can be used to emulate unimplemented instructions The trap service routine can examine the faulting instruction to decode operands for unimplemented opcodes based on the stacked IP In order to resume processing the stacked IP value must be incremented by the size of the undefined instruction which is determined by the user before a RETI instruction is executed PRoTection FauLT Trap PRTFLT DISWDT EINIT IDLE PWRDN SRST and SRVWDT are protected instructions Whenever one protected instruction is executed and the protection is broken the PRTFLT flag in register TFR is set and the CPU enters the protection fault trap routine The IP value pushed onto the system stack for the protection fault trap is the address of the instruction that caused the trap ILLegal word OPerand Access Trap ILLOPA Whenever a word operand read or write access is attempted t
376. of stack and call subroutine User s Manual 3 83 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Central Processing Unit e Controlling Interrupts Software modifications implicit or explicit of the PSW are done in the execute phase of instructions In order to maintain fast interrupt responses however the current interrupt prioritization round does not consider these changes i e an interrupt request may be acknowledged after the instruction that disables interrupts via IEN or ILVL or after the following instructions Therefore time critical instruction sequences should not begin directly after the instruction disabling interrupts as shown in the following examples INTERRUPTS_OFF BCLR TEN globally disable interrupts lt Instr non crit gt non critical instruction Instr lst crit gt begin of uninterruptable critical sequence lt Instr last crit gt end of uninterruptable critical sequence INTERRUPTS_ON BSET TEN globally re enable interrupts CRITICAL SEQUENCE ATOMIC 3 immediately block interrupts BCLR IEN globally disable interrupts a here is the uninterruptable sequence BSET IEN globally re enable interrupts Note The described delay of 1 instruction also applies for enabling the interrupt system i e no interrupt requests are acknowledged until the instruction following the enabling ins
377. of the associated source which is required during one round of prioritization arbitration cycle The upper 8 bits of the respective register are reserved All interrupt control registers are bit addressable and all bits can be read or written via software Therefore each interrupt source can be programmed or modified with just one instruction When reading the interrupt control registers with instructions that operate with word data types the upper 8 bits 15 8 will return zeros Zeros should always be written to these bit positions The layout of the interrupt control registers shown below is applicable to all xxIC registers xxIC Interrupt Control Register PSFR xxxXy XXH Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 xxGP xxlR xxlE ILVL GLVL r r r r r r r rw mwh rw rw rw Field Bits Type Description xxGP 8 rw Group Priority Extension Defines the value of high order group level bit xxIR 7 rwh Interrupt Request Flag 0 No request pending 1 This source has raised an interrupt request xxlE 6 rw Interrupt Enable Control Bit individually enables disables a specific source 0 Interrupt request is disabled 1 Interrupt request is enabled User s Manual 3 21 V 1 6 2001 08 _ 7 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit Field Bits Type Description ILVL 5 2 rw Interrupt Prior
378. of the same register Note All C SFRs may be accessed word wise or byte wise some of them even bitwise Reading bytes from word C SFRs is a non critical operation Any write operation to a single byte of an C SFR clears the non addressed complementary byte within the specified C SFR Non implemented reserved C SFR Bits cannot be modified and will always supply a read value of 0 Non implemented C SFR will always supply a read value of FFFF y Programming Hints Access to SFRs All SFRs reside in dedicated page of the memory space The following addressing mechanisms allow to access the C SFRs indirect or direct addressing with 16 bit mem addresses must guarantee that the used data page pointer DPPO DPP3 selects data page 3 accesses via the Peripheral Event Controller PEC use the SRCPx and DSTPx pointers instead of the data page pointers short 8 bit reg addresses to the standard SFR area do not use the data page pointers but directly access the registers within this 512 Byte area short 8 bit reg addresses to the extended ESFR area require switching to the 512 Byte extended SFR area This is done via the EXTension instructions EXTR EXTP R EXTS R User s Manual 3 5 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit Byte write operations to word wide SFRs via indirect or direct 16 bit mem addressing or byte transfers via the PEC force z
379. of the transmit shift register TBUF Transmit Buffer Register Reset value 0000p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 TD_VALUE r rw Field Bits Typ Description TD_VALUE 8 0 rw Transmit Data Register Value TBUF contains the data to be transmitted in either asynchronous or synchronous operating mode of the ASC Data transmission is double buffered Therefore a new value can be written to TBUF before transmission of the previous value is completed 0 15 9 Reserved for future use reading returns 0 writing to these bit positions has no effect Note The transmitter output pin TXD must be configured for alternate data output 10 3 1 3 Asynchronous Reception Asynchronous reception is initiated by a falling edge 1 to 0 transition on line RXD provided that bits CON_R and CON_REN are set The receive data input line RXD is sampled at 16 times the rate of the selected baudrate A majority decision of the 7th 8th and 9th sample determines the effective bit value This avoids erroneous results that may be caused by noise If the detected value is not a O when the start bit is sampled the receive circuit is reset and waits for the next 1 to 0 transition at line RXD If the start bit proves valid the receive circuit continues sampling and shifts the incoming data frame into the receive shift register When the last stop bit has been received the content of
380. om 00y to 7F yy can be specified to access any double word code location within the address range 00 0000 00 01FC in code segment 0 i e the interrupt jump vector table For the association of trap numbers with the corresponding interrupt or trap sources please refer to Section 3 4 Interrupt and Trap Functions User s Manual 3 8 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 3 2 Sequential and Non Sequential Instruction Flow Since passing through one pipeline stage takes at least one machine cycle which equals two clock cycles T1 and T2 any isolated instruction takes at least four machine cycles to be completed Pipelining however allows parallel i e simultaneous processing of up to four instructions Therefore most instructions will seem to be processed during one machine cycle as soon as the pipeline has been filled once after reset Pipelining increases the average instruction throughput In this manual any execution time specification always refers to the average instruction execution time due to pipelined parallel processing The execution time of a sequential and non sequential instruction flow is mainly given by the instruction fetch from different kind of memories number of waitstates The following pipeline diagram Table 3 2 shows the continuous execution of instruction under the assumption of a fast Local Memory 0 1 waitstate
381. ompare direct bit to direct bit 4 BFLDH bitoff mask8 Bitwise modify masked high byte of bit addressable 4 data8 direct word memory with immediate data BFLDL bitoff mask8 Bitwise modify masked low byte of bit addressable 4 data8 direct word memory with immediate data CMP Rw Rw Compare direct word GPR to direct GPR CMP Rw Rw Compare indirect word memory to direct GPR CMP Rw Rw Compare indirect word memory to direct GPR and post increment source pointer by 2 CMP Rw data3 Compare immediate word data to direct GPR 2 CMP reg datai6 Compare immediate word data to direct register 4 CMP reg mem Compare direct word memory to direct register 4 CMPB Rb Rb Compare direct byte GPR to direct GPR 2 CMPB Rb Rw Compare indirect byte memory to direct GPR 2 CMPB Rb Rw Compare indirect byte memory to direct GPR and 2 post increment source pointer by 1 CMPB Rb data3 Compare immediate byte data to direct GPR 2 CMPB reg data8 Compare immediate byte data to direct register CMPB reg mem Compare direct byte memory to direct register Compare and Loop Control Instructions CMPD1 Rw data4 Compare immediate word data to direct GPR and 2 decrement GPR by 1 CMPD1 Rw data16 Compare immediate word data to direct GPR and 4 decrement GPR by 1 User s Manual 5 10 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Instruction Set Instruction Set Summary cont d Mnemonic Desc
382. on If the specified bit was set program execution continues normally with the instruction following the JNBS instruction Note Flags are always updated by this instruction CPU Flags E Z V C N 0 B 0 0 B E Always cleared Z Contains the logical negation of the previous state of the specified bit V Always cleared C Always cleared N Contains the previous state of the specified bit Encoding Mnemonic Format Bytes JNBS bitaddro q rel BA QQ rr q0 4 User s Manual 6 57 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set MOV Move Data MOV Group Data Movement Instructions Syntax MOV op1 op2 Source Operand s op2 gt WORD Destination Operand s op1 gt WORD Operation op1 op2 Description Moves the contents of the source operand specified by op2 to the location specified by the destination operand op1 The contents of the moved data is examined and the flags are updated accordingly CPU Flags E Z V C N ES ALA E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the source operand op2 equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the source operand op2 is set Cleared otherwise Encoding Mnemonic Format Bytes MOV Rw data4 EO n 2 MOV Rw RWm FO nm 2 MOV Rw Rw data1
383. on Mode 00004 Register FOGA y RWDATA ESFR 35y Cerberus RW Mode Data 0000 Register FO6Cy IOSR ESFR 364 Cerberus status register 0000 FOGEy ESFR 374 FO70y ESFR 38 F072 ESFR 39 F074 ESFR 3Ay F076 ESFR 3By F078 ESFR 30 FO7Ay ESFR 3Dy FO7Cy ESFR 3E FO7Ey ESFR 13Fy FO80 ESFR 404 F082 ESFR 44 F084 y ESFR 42 F0864 ESFR 48 F088 ESFR 444 F08A ESFR 454 FO8Cy ESFR 46 FO8Ey ESFR 474 FO90y ESFR 484 F092 ESFR 49 F094 ESFR 4Aj FO96y ESFR 4By FO98y ESFR 4Cy FO9A y ESFR 4Dy FO9Cy ESFR 4Ey User s Manual 4 14 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value FO9Ey ESFR 4Fy FOAOy ESFR 50 FOA2y ESFR 51y FOA4 ESFR 52y FOA6y ESFR 53y FOA8y ESFR 544 FOAA y ESFR 55 FOACy ESFR 56 FOAEy ESFR 574 FOBOy SSCOTB ESFR 58 SSCO Transmit Buffer WO 00004 FOB2y SSCORB ESFR 59y SSCO Receive Buffer RO 0000 FOB4y SSCOBR ESFR 5Ay SSCO Baudrate Register 0000y FOB6y SSCOPISEL ESFR 5By SSCO Port Input Selection 0000 Register FOB8y IRQ96IC ESFR 5Cy IRQ96 Interrupt Control Register 0000 FOBA y IRQ97IC ESFR 5Dy IRQ97 Interrupt Control
384. on Register 0 0000 User s Manual 4 26 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Memory Organization Table 4 2 SFR ESFR Table ordered by physical address cont d Physical Name Type 8 bit Description Reset Address Addr Value FFOEy MDC SFR b 1874 CPU Multiply Divide Control 0000 Register FF10y PSW SFR b 884 CPU Program Status Word 0000y FF12y SYSCON SFR b 894 CPU System Configuration XXXXH Register FF14 BUSCON1 SFR b 8Ay Bus Configuration Register 1 0000 FF16y BUSCON2 SFR b 8By Bus Configuration Register 2 0000 FF18y BUSCONS SFR b 8Cy Bus Configuration Register 3 0000 FF1Ay BUSCON4 SFR b 8Dy Bus Configuration Register 4 0000 FFIC ZEROS SFR b 8Ey Constant Value OsRegister 0000 FF1E ONES SFR b 8Fy Constant Value 1sRegister FFFFy FF20y SFR b 904 FF22y SFR b 914 FF24 SFR b 924 FF26y SFR b 934 FF28y SFR b 944 FF2Ay SFR b 95 FF2Cy SFR b 964 FF2Ey SFR b 974 FF30y SFR b 984 FF32H SFR b 994 FF34y SFR b 9Ay FF36y SFR b 9By FF38y SFR b 9Cy FF3Ay SFR b 9Dy FF3Cy SFR b 9Ey FF3E SFR b 9Fy FF40y T2CON SFR b A0y GPT Timer 2 Control Register 00004 FF424 T3CON SFR b Aly GPT Timer 3 Control Register 0000 User s Manual 4 27 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S
385. on data exchange line are detected if the received data is not equal to the transmitted data Master Device 1 Shift Register Transmit Device 2 Slave Transmit Receive Line Device 3 Figure 11 6 SSC Half Duplex Configuration User s Manual 11 13 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem High Speed Synchronous Serial Interface SSC 11 2 4 Continuous Transfers When the transmit interrupt request flag is set it indicates that the transmit buffer TB is empty and ready to be loaded with the next transmit data If TB has been reloaded by the time the current transmission is finished the data is immediately transferred to the shift register and the next transmission will start without any additional delay On the data line there is no gap between the two successive frames For example two byte transfers would look the same as one word transfer This feature can be used to interface with devices that can operate with or require more than 16 data bits per transfer It is just a matter of software how long a total data frame length can be This option can also be used to interface to byte wide and word wide devices on the same serial bus for instance Note Of course this can happen only in multiples of the selected basic data width because it would require disabling enabling of the SSC to reprogram the basic data width on the fly User s Manual 11 14 V 1 6 2
386. on popping operands from the system stack In o POP RO pop word value from new top of stack into RO Furthermore none of the RETI RETS or RETP instructions are capable of correctly using a new SP register value which is to be updated by one or both of the two immediately preceding instructions Thus in order to use the new SP register value without erroneously performed stack accesses at least two instructions must be inserted between an instruction that explicitly writes to SP and any of the afore mentioned subsequent instructions that implicitly use the SP as shown in the following example Ta MOV SP 40FAA40H select a new top of stack Lasi o Caes must not be an instruction popping operands from the system stack Lago imus must not be an instruction popping operands E from the system stack In 3 RETP RO return from subroutine and pop word value from new top of stack into RO Most of the potential conflicts if a change of SP value is immediately followed by a writing to the stack instructions PUSH CALL SCXT TRAP are solved internally by CPU logic The only exceptions are CALLS and PCALL instructions which require one preceding instruction not using updated SP as shown below a MOV SP O0FA40H select a new top of stack ve ers must not be an instruction using the new address of system stack Ino PCALL R3 sub addr push R3 value and return address at the new top
387. operation a port pin associated with line T3IN must be configured as input The maximum input frequency allowed in Counter Mode is f5 8 BPS1 01p To ensure that a transition of the count input signal applied to T3IN is correctly recognized its level should be held high or low for at least 4 fy cycles BPS1 01p before it changes Timer 3 in Incremental Interface Mode Incremental Interface Mode for core Timer T3 is selected by setting bitfield T3M in register T3CON to 110g or 111g In Incremental Interface Mode the two inputs associated with Timer T3 T3IN T3EUD are used to interface to an external incremental encoder T3 is clocked by each transition on one or both of the external input lines which gives 2 fold or 4 fold resolution of the encoder input User s Manual 12 12 V 1 6 2001 08 User s Manual neon Infineon C1 66S V1 SubSystem General Purpose Timer Unit Edge j sea T3l T3R T9 gt T3IRQ Edge T3IRQ T3M Change T3 pero Detection CHDIR Taine T3M Phase Detect Figure 12 7 Block Diagram of Core Timer T3 in Incremental Interface Mode MCB03998 b Bitfield T3l in control register T3CON selects the triggering transitions see Table 12 5 The sequence of the transitions of the two input signals is evaluated and generates count pulses as well as the direction signal Depending on whether Rotation Detection Mode TSMz 110g or Edge Detection Mode
388. optimized instruction set additional instructions for members of the second generation This allows an easy and quick implementation of new family members with different internal memory sizes and technologies different sets of on chip peripherals and or different numbers of I O Input Output pins The Internal Bus Interface IBI concept opens a straight forward path for the integration of application specific peripheral modules in addition to the standard on chip peripherals in order to build application specific derivatives As programs for embedded control applications become larger high level languages are favoured by programmers because high level language programs are easier to write to debug and to maintain The 80C166 type microcontrollers were the first generation of the 16 bit controller family These devices have established the C166 architecture The C165 type and C167 type devices are members of the second generation of this family This second generation is even more powerful due to additional instructions for HLL support an increased address space increased internal RAM Random Access Memory and highly efficient management of various resources on the external bus The C166S type devices are members of the third generation of this family This third generation is the synthesizable version of the second generation Enhanced derivatives of this second third generation provide additional features like additional internal
389. ord data transfer is selected for a specific PEC channel i e BWT 0 the respective source and destination pointers must both contain a valid word address that points to an even byte boundary Otherwise the Illegal Word Access trap will be invoked when this channel is used SRCPx PEC Source Pointer DPRAM H H Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SRCPx rwh Field Bits Type Description SRCPx 15 0 rwh Source Pointer Address of Channel x Source Address bits 15 0 DSTPx PEC Destination Pointer DPRAM H H Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DSTPx rwh Field Bits Type Description DSTPx 15 0 rwh Destination Pointer Address of Channel x Destination Address bits 15 0 Table 3 7 DPRAM Addresses of PEC Source and Destination Pointer Pointer Address Pointer Address Pointer Address Pointer Address DSTP7 00 FCFE SRCP7 00 FCFCy DSTP11 00 FCDE SRCP11 00 FCDOC DSTP6 O00FCFA SRCP6 O00 FCF8 DSTP10 00 FCDA SRCP10 00 FCD8 DSTP5 00 FCF6y SRCP5 00 FCF4 DSTP9 00 FCD6 SRCP9 00 FCD4 DSTP4 00 FCF2 SRCP4 00 FCF0 DSTP8 00 FCD2 SRCP8 00 FCDO DSTP3 00 FCEEy SRCP3 00 FCEC DSTP15 00 FCCE SRCP15 00 FCCC DSTP2 00 FCEAy SRCP2 00 FCE8y DSTP14 00 FCCAy SRCP14 00
390. ot keep pace with the controller s maximum speed During these memory cycle time waitstates the CPU is idle if this access is required for the execution of the current instruction The memory cycle time waitstates can be programmed in increments of one CPU clock 2 TCL within a range from O to 15 default after reset via the Memory Cycle Time Control MCTC fields of the BUSCON registers 15 lt MCTC gt waitstates will be inserted 8 3 3 Programmable Memory Tri State Time The C166S allows the user to adjust the time between two subsequent external accesses in order to account for the tri state time of the external device The tristate time defines when the external device has released the bus after deactivation of the read command RD The output of the next address on the external bus can be delayed by introducing a waitstate after the previous bus cycle in order to compensate for a memory or peripheral that needs more time to switch off its bus drivers see Figure 8 8 During this memory tri state time waitstate the CPU is not idle so CPU operations will be slowed down only if a subsequent external instruction or data fetch operation is required during the next instruction cycle The memory tristate time waitstate requires one CPU clock 2 TCL and is controlled via the Memory Tristate Time Control MTTCx bits of the BUSCON registers A waitstate will be inserted if bit MTTCx is O default after reset Note External bus cycles i
391. own TxUDE 8 rw Timer x External Up Down Enable 0 Counting direction is internally controlled by software 1 Counting direction is externally controlled by line TXEUD TxRC 9 rw Timer x Remote Control 0 Timer Counter x is controlled by its own run bit TXR 1 Timer Counter x is controlled by the run bit of core Timer 3 User s Manual 12 17 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit Field Bits Typ Description TxIRDIS 12 rw Timer x Interrupt Disable 0 Interrupt generation for TXCHDIR and TXEDGE interrupts in Incremental Interface Mode is enabled 1 Interrupt generation for TXCHDIR and TXEDGE interrupts in Incremental Interface Mode is disabled TxEDGE 13 rwh Timer x Edge Detection The bit is set on each successful edge detection The bit has to be reset by software 0 No count edge was detected 1 A count edge was detected TxCHDIR 14 rwh Timer x Count Direction Change The bit is set on a change of the count direction of timer x The bit has to be reset by software 0 No change in count direction was detected 1 A change in count direction was detected TxRDIR 15 rh Timer x Rotation Direction 0 Timer x counts up 1 Timer x counts down 0 11 10 Reserved for future use reading returns 0 writing to these bit positions has no effect Both auxiliary timers T2 and T4 have exactly the same functionali
392. pport devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered C166S V1 SubSystem C166S V1 SubS R1 e Infineon technologies thinking C166S V1 SubS R1 Revision History 2001 08 V 1 6 Previous Version V 1 5 Page Subjects major changes since last revision 2 12 Periodic Wake up from Idle or Sleep Mode 2 14 Clock Generation Unit On chip Bootstrap Loader 3 80 3 86 Particular Pipeline Effects 6 21 CALLA Instruction description 6 38 EINIT Instruction description 6 52 JMPA Instruction description 6 78 RETI Instruction description 6 91 SRVWDT Instruction description 6 96 TRAP Instruction description 8 1 8 29 RPOH Register 8 1 8 34 DP3 P3 ODP4 ODP6 Registers 8 22 CLKEN System Clock Enable bit 8 31 External Bus Arbitration We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to ce cmd infineon com I 1 fi User s Manual n Infineon C1 66S V1 SubSystem Table of Contents Page 1 Introduction voL ERE E ERRLbse E
393. ps the timer If T3M 0118 line T3IN must have a high level to enable the timer Additionally the timer can be turned on or off by software using bit T3R The timer will run only if T3R is set and the gate is active It will stop if either T3R is cleared or the gate is inactive Note A transition of the gate signal at line T3IN does not cause an interrupt request Timer 3 in Counter Mode Counter Mode for core Timer T3 is selected by setting bitfield T3M in register T3CON to 001g In Counter Mode Timer T3 is clocked by a transition at the external input line T3IN The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at this line Bitfield T3l in control register T3CON selects the triggering transition see Table 12 4 User s Manual 12 11 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V1 SubSystem General Purpose Timer Unit Core Timer T3 T3IRQ TSEUD MCB02030 b Figure 12 6 Block Diagram of Core Timer T3 in Counter Mode Table 12 4 Core Timer T3 Counter Mode Input Edge Selection T3I Triggering Edge for Counter Increment Decrement 000 None Counter T3 is disabled 001 Positive transition rising edge on T3IN 010 Negative transition falling edge on T3IN 011 Any transition rising or falling edge on T3IN 1XX Reserved Do not use this combination For Counter Mode
394. r s Manual 6 35 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set DIVLU 32 by 16 Unsigned Division DIVLU Group Arithmetic Instructions Syntax DIVLU op1 Source Operand s op1 gt WORD MD DOUBLEWORD Destination Operand s MD gt DOUBLEWORD Operation MDL MD op1 MDH MD mod op1 Description Performs an extended unsigned 32 bit by 16 bit division of the two words stored in the MD register by the source word operand op1 The unsigned quotient is then stored in the low order word of the MD register MDL and the remainder is stored in the high order word of the MD register MDH CPU Flags E Z V C N o j tj t po E Always cleared Z Set if quotient stored in the MDL register equals zero Cleared otherwise Undefined if the V flag is set V Set if an arithmetic overflow occurred i e the quotient cannot be represented in a word data type or if the divisor op1 was zero Cleared otherwise C Always cleared N Set if the most significant bit of the quotient stored in the MDL register is set Cleared otherwise Undefined if the V flag is set Encoding Mnemonic Format Bytes DIVLU Rwy 7B nn 2 User s Manual 6 36 V 1 6 2001 08 1 fi User s Manual nrineon M C166S V1 SubSystem Detailed Instruction Set DIVU 16 by 16 Unsigned Division DIVU Group Arithmetic Instructions Syntax DIVU op1 Source Operand s op1
395. rand op2 CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes SCXT reg data16 C6 RR HH HH 4 SCXT reg mem D6 RR MM MM 4 User s Manual 6 85 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set SHL Shift Left SHL Group Shift and Rotate Instructions Syntax SHL op1 op2 Source Operand s op1 gt WORD op2 gt shift counter Destination Operand s op1 gt WORD Operation count op2 C 0 DO WHILE count z 0 C op1 15 op1 n op1 n 1 n215 1 op1 0 0 count lt count 1 END WHILE Description Shifts the destination word operand op1 the number of times as specified by the source operand op2 The least significant bits of the result are filled with zeros accordingly The least The most significant bit is shifted into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used CPU Flags E Z V C N EEE AA E Always cleared Z Set if result equals zero Cleared otherwise V Always cleared C The carry flag is set according to the last most significant bit shifted out of op1 Cleared for a shift count of zero N Set if the most significant bit of the result is set Cleared otherwise User s Manual 6 86 V 1 6 2001 08 pae e Infineon techno
396. red otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes SUB Rw data3 28 n O 2 SUB Rw RWm 20 nm 2 SUB Rw Rw 28 nlii 2 SUB Rw Rwj 28 n 10ii 2 SUB mem reg 24 RR MM MM 4 SUB reg data16 26 RR 4 SUB reg mem 22 RR MM MM 4 User s Manual 6 92 V 1 6 2001 08 1 fi User s Manual nrineon M a C166S V1 SubSystem Detailed Instruction Set SUBB Integer Subtraction SUBB Group Arithmetic Instructions Syntax SUBB op1 op2 Source Operand s op1 op2 gt BYTE Destination Operand s op1 gt BYTE Operation op1 lt op1 op2 Description Performs a 2 s complement binary subtraction of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in opt CPU Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the word data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes SUBB Rb data3 29 n O 2 SUBB Rb Rom 21 nm 2 SUBB Rb Rw 29 nlii 2 SUBB Rb Rw 29 n
397. rent program execution and branches to an Interrupt Service Routine ISR The current program status and context must be preserved If a PEC channel is selected for servicing an interrupt request a single word or byte data transfer between any two memory locations is to be performed During a PEC transfer the normal program execution of the CPU is halted for just 1 machine cycles No internal program status information needs to be saved The PEC transfer is the fastest possible interrupt response In many cases a PEC transfer is sufficient to service the peripheral request serial channels for example The PEC channels can perform the following actions Byte or word transfer Continuous data transfer PEC channel specific interrupt request upon data transfer completion or for all channels a common End of PEC EOP interrupt for enhanced handling Automatic increment of source or destination pointers Channel linking of two PEC channels Note PEC transfer is executed if its priority level is higher than current CPU priority level 1 The number of PEC channels depends on the configuration of the product Please refer to the product User Manual User s Manual 3 32 V 1 6 2001 08 1 fi User s Manual nrineon M C166S V1 SubSystem Central Processing Unit 3 4 6 1 The PEC Source and Destination Pointers The PEC channels source and destination pointers specify the locations between which the data is t
398. represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes OR Rw data3 78 n O 2 OR Rw RWm 70 nm 2 OR Rw Rw 78 nlii 2 OR Rw Rwi 78 n 10ii 2 OR mem reg 74 RR MM MM 4 OR reg data16 76 RR 4 OR reg mem 72 RR MM MM 4 User s Manual 6 69 V 1 6 2001 08 1 fi User s Manual nrineon M a C166S V1 SubSystem Detailed Instruction Set ORB Logical OR ORB Group Logical Instructions Syntax ORB op1 op2 Source Operand s op1 op2 gt BYTE Destination Operand s op1 gt BYTE Operation op1 op1 v op2 Description Performs a bitwise logical OR of the source operand specified by op2 and the destination operand specified by op1 The result is then stored in op1 CPU Flags E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes ORB Rb data3 79 n O 2 ORB Rb Rbm 71 nm 2 ORB Rb Rw 79 nlii 2 ORB Rb Rw 79 n 10ii 2 ORB mem reg 75 RR MM MM 4 ORB reg data8 77 R
399. requests until it is modified by the program C If the bitfield COUNT is set to service a specified number of requests by the respective PEC channel itis decremented with each PEC transfer and the request flag is cleared to indicate that the request has been serviced When COUNT reaches 00y it activates the ISR that has the same priority level EOPINT 0 or triggers the EOP ISR with a different priority level EOPINT 1 When COUNT is decremented from 01 to 00 after a data transfer the request flag will be cleared if EOPINT is set to 1 If EOPINT is O the request flag will not be cleared and another interrupt request will be generated on the same priority level The respective PEC channel remains idle and the associated ISR is activated instead of PEC transfer because COUNT contains the 00 value User s Manual 3 38 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 4 6 4 Long Transfer Mode If the long transfer mode is enabled by the PT flag PT 1 in the PEC control register PECOx the PEC Transfer Count Field COUNT2 of the PECXOx register directly controls the action of the respective PEC channel PEC Extended Count Register PECXCO 2 4 6 SFR H gt H Reset value 0000p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COUNT2 rwh Field Bits Type Description COUNT2 15 0 rwh PEC Extended Long Transfer Count PEC tr
400. ripheral areas The DPRAM and the SFR areas are located within data page 3 and provide fast accesses using one dedicated Data Page Pointer DPP see Figure 4 3 Note Code accesses are not possible from the SFH areas 4 3 1 Data Memories The DPRAM is a volatile memory available mainly for data storage It serves for GPR banks Variable and other data storage System and user stacks PEC source and destination pointers A 3 KByte memory area 00 F200 00 FE00 is reserved for the DPRAM The upper 256 Bytes of the DPRAM 00 FDOOy 00 FDFFy and the GPRs of the current bank are provided for single bit storage and thus they are bit addressable see shaded blocks in Figure 4 3 Any word and byte data in the DPRAM can be accessed via indirect or long 16 bit addressing modes if the selected DPP register points to data page 3 Any word data access is made on an even byte address The highest possible word data storage location in the DPRAM is O00 FDFE The highest possible code storage location in the DPRAM is either 00 FDFE y for single word instructions or OO FDFCy for double word instructions but this is the bit addressable area which should not be used for code The respective location must contain a branch instruction unconditional because sequential boundary crossing from DPRAM to the SFR area is not supported and causes erroneous results 4 3 2 Special Function Register Areas The functions of the CPU the bus interface
401. ription Bytes Compare and Loop Control Instructions cont d CMPD1 Rw mem Compare direct word memory to direct GPR and 4 decrement GPR by 1 CMPD2 Rw data4 Compare immediate word data to direct GPR and 2 decrement GPR by 2 CMPD2 Rw data16 Compare immediate word data to direct GPR and 4 decrement GPR by 2 CMPD2 Rw mem Compare direct word memory to direct GPR and 4 decrement GPR by 2 CMPI1 Rw data4 Compare immediate word data to direct GPR and 2 increment GPR by 1 CMPI1 Rw data16 Compare immediate word data to direct GPR and 4 increment GPR by 1 CMPI1 Rw mem Compare direct word memory to direct GPR and 4 increment GPR by 1 CMPI2 Rw data4 Compare immediate word data to direct GPR and 2 increment GPR by 2 CMPI2 Rw data16 Compare immediate word data to direct GPR and 4 increment GPR by 2 CMPI2 Rw mem Compare direct word memory to direct GPR and 4 increment GPR by 2 Prioritize Instruction PRIOR Rw Rw Determine number of shift cycles to normalize direct 2 word GPR and store result in direct word GPR Shift and Rotate Instructions SHL Rw Rw Shift left direct word GPR 2 number of shift cycles specified by direct GPR SHL Rw data4 Shift left direct word GPR 2 number of shift cycles specified by immediate data SHR Rw Rw Shift right direct word GPR 2 number of shift cycles specified by direct GPR User s Manual 5 11 V 1 6 2001 08 e
402. rmat Bytes MOVB Rb data4 El n 2 MOVB Rb Rbm F1nm 2 MOVB Rb Rw data1 6 F4 nm 44 4 MOVB Rb RWm 99 nm 2 MOVB Rb RW A9 nm 2 MOVB RwWm Rb 89 nm 2 MOVB Rw data16 Rb E4 nm 4 User s Manual 6 60 V 1 6 2001 08 pae e Infineon technologies MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB MOVB User s Manual User s Manual C166S V1 SubSystem RWml Rb Rw RW Rwy RWm Rwp RW Rw4 mem mem Rw mem reg reg data8 reg mem B9 nm D9 nm E9 nm C9 nm A4 0n MM MM B4 0n MM MM F7 RR MM MM E7 RR xx F3 RR MM MM 6 61 Detailed Instruction Set RR D BAB ROM DY INS V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set MOVBS Move Byte Sign Extend MOVBS Group Data Movement Instructions Syntax MOVBS op op2 Source Operand s op2 gt BYTE Destination Operand s op1 gt WORD Operation low byte op1 op2 IF op2 7 1 THEN high byte op1 lt FFH ELSE high byte op1 lt 00H END IF Description Moves and sign extends the contents of the source byte operand specified by op2 to the word location specified by the destination operand op1 The contents of the moved data is examined and the flags are updated accordingly CPU Flags E Z V C N E Always cleared Z Set if the value of the source byte operand op2 equals zero Cleared otherwise V
403. rnal ROM FLASH DRAM where integrated DPRAM the internal Special Function Register SFR and Extended Special Function Register ESFR areas and external memory are mapped into one common address space 254 129 128 800000 127 Begin of Local Memory 126 65 above 32KB O1 FFFFj 40 0000 Segment 1 OA FFFF yy Alternate Local Memory Area Data Page 3 gt O Y o y D ES e e o Lo o lt m c _ o us x LU Data Page 2 Segment 0 Internal Local Memory 00 0000 Total Address Space Segments 1 and 0 16 MByte Segments 255 0 64 64 KByte Figure 4 1 C166S Address Space Overview User s Manual 4 1 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Memory Organization The C166S has a total addressable memory space of 16 MBytes This address space is arranged as 256 segments of 64 KBytes each and each segment is again subdivided into four data pages of 16 KBytes each see Figure 4 1 Most internal memory areas are mirrored into segment 0 the system segment The upper 4 KBytes of segment 0 00 F000y 00 FFFFy are the SFRs and ESFRs and the DPRAM areas The lower 32 KByte of segment O 00 0000H 00 7FFFH may be occupied by a part of the on chip program memory and is called the internal Local Memory LM area This LM area can be remapped to segment 1 01 0000 01 7FFF to enable external memory access in the lower half of
404. rol General Purpose Timer Unit gt T2IRQ T3 Mode GPT1 Timer T3 Control le T4 Mode gt T3IRQ Control p GPT1 Timer T4 Figure 12 3 Structure of Timer Block 1 User s Manual 12 4 gt T4IRQ MCTO02141 b V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem 12 2 1 Core Timer T3 General Purpose Timer Unit The operation of core Timer T3 is controlled by its bitaddressable control register T3CON T3 Timer 3 Reset value 0000p 15 14 13 12 11 10 9 8 3 2 1 0 T3 rwh Field Bits Typ Description T3 15 0 rwh Timer 3 Contains the current value of Timer 3 User s Manual 12 5 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem T3CON Timer 3 Control Register General Purpose Timer Unit Reset value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T3 CH EDG BPs 13 13 T3 T3 msg T3M T3l RDIR DIR E OTL OE UDE UD rh rwh rwh rw rwh rw rw rw rw rw rw Field Bits Typ Description T3I 2 0 rw Timer 3 Input Parameter Selection Timer Mode see Table 12 2 for encoding Gated Timer Mode see Table 12 2 for encoding Counter Mode see Table 12 4 for encoding Incremental Interface Mode see T
405. rovides flags that indicate the source of a reset After any reset a globally enable watchdog timer conf wdt en active starts counting up from 0000y with the default frequency fwprT fpp 256 The default input frequency may be changed to another frequency fwpt fpp 128 by programming the prescaler bit WDTIN The watchdog timer supports different modes WDT Reset mode When the watchdog timer is not disabled via instruction DISWDT it will continue counting up even during Idle Mode If it is not serviced via the instruction SRVWDT by the time the count reaches FFFFy the watchdog timer will overflow and cause a watchdog timer reset and a wdt overflow will be signaled watint as well But nevertheless the whole subsystem including the WDT itself will be reseted WDT Interrupt mode If the TIMEN bit is set only the generation of watchdog timer resets is surpressed after the execution of the DISWDT instruction A watchdog timer overflow event will still be signaled e WDT Disable mode This mode is enable if the TlMer ENable TIMEN bit in the WDTCON register is not set and the watchdog timer reset generation was stopped with the execution of the DISWDT instruction In this case the whole WDT counter is stopped Neither a watchdog timer reset will be generated nor a watchdog timer overflow wdtint o event will be signaled Instruction DISWDT is a protected 32 bit instruction which will ONLY be executed during the time between a reset a
406. rred from register MD The high portion of MD MDH must be moved into the register file or memory first in order to ensure that the MDRIU flag reflects the correct state The following instruction sequence performs an unsigned 16 by 16 bit multiplication SAVE JNB MDRIU START Test if MD was in use SCXT MDC 0010H Save and clear control register leaving MDRIU set only required for interrupted multiply divide instructions BSET SAVED Indicate the save operation PUSH MDH Save previous MD contents PUSH MDL P On system stack START MULU R1 R2 Multiply 16 16 unsigned Sets MDRIU User s Manual 3 74 V 1 6 2001 08 1 fi User s Manual nrineon M C166S V1 SubSystem Central Processing Unit JMPR cc NV COPYL Test for only 16 bit result MOV R3 MDH Move high portion of MD COPYL MOV R4 MDL Move low portion of MD Clears MDRIU RESTORE JNB SAVED DONE Test if MD registers were saved POP MDL Restore registers POP MDH POP MDC BCLR SAVED Multiplication is completed program continues DONE The above save sequence and the restore sequence after COPYL are required only if the current routine could have interrupted a previous routine that contained a MUL or DIV instruction Register MDC is also saved because it is possible that a previous routine s Multiply or Divide instruction was interrupted while in progress In t
407. rs on from the system stack However in most cases the register banking scheme provides the best performance for passing data between multiple tasks Note The system stack allows the storage of words only Bytes must either be converted to words or the unwanted other byte must be disregarded Register SP can be loaded only with even byte addresses The LSB of SP is always 0 The Stack Pointer SP addresses the stack within the DPRAM area The Stack Pointer Register The non bit addressable Stack Pointer SP register is used to point to the Top Of the System TOS stack The SP register is pre decremented whenever data is to be pushed onto the stack and it is post incremented whenever data is to be popped from the stack Therefore the system stack grows from higher toward lower memory locations Since the Least Significant Bit LSB of register SP is tied to 0 and bits 15 12 are tied to 1 by hardware the SP register can contain values only from F000 to FFFEy This allows access to a physical stack within the DPRAM of the C166S A virtual stack usually bigger can be implemented via software This mechanism is supported by registers STKOV and STKUN see descriptions below Section 3 6 3 1 The SP register can be updated via any instruction that is capable of modifying a 16 bit SFR Note Due to the internal instruction pipeline a POP or RETurn instruction must not immediately follow an instruction updating the SP register
408. rt4 outputs four two or no address segment lines at all It outputs all 8 address if an address space of 16 MByte is used The on chip Internal Bus Interface is an internal representation of the external bus and allows to access integrated application specific peripherals modules in the same way as external components It provides a defined interface for these customized peripherals 2 2 3 The On chip Peripheral Blocks The C166 Family clearly separates peripherals from the core This structure permits the maximum number of operations to be performed in parallel and allows peripherals to be added or deleted from family members without modifications to the core These built in peripherals either allow the CPU to interface with the external world or provide functions on chip that otherwise were to be added externally in the respective system Each functional block processes data independently and communicates information over common buses Individually selected clock signals are generated for each peripheral User s Manual 2 8 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem System Overview Peripheral Interfaces The on chip peripherals generally have two different types of interfaces an interface to the CPU and an interface to external hardware Communication between CPU and peripherals is performed through Special Function Registers SFRs and interrupts Each peripheral contains a set of Special Fun
409. ruction Set BSET Bit Set BSET Group Boolean Bit Manipulation Instructions Syntax BSET op1 Source Operand s none Destination Operand s op1 gt BIT Operation 0p1 1 Description Sets the bit specified by op1 CPU Flags E Z V C N E Always cleared Z Contains the logical negation of the previous state of the specified bit V Always cleared C Always cleared N Contains the previous state of the specified bit Encoding Mnemonic Format Bytes BSET bitaddra y qF QQ 2 User s Manual 6 19 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set BXOR Bit Logical XOR BXOR Group Boolean Bit Manipulation Instructions Syntax BXOR op1 op2 Source Operand s op1 op2 gt BIT Destination Operand s op1 gt BIT Operation op1 op1 op2 Description Performs a single bit logical EXCLUSIVE OR of the source bit specified by op2 and the destination bit specified by op1 The result is then stored in op1 CPU Flags E Z V C N o non oR anD xon E Always cleared Z Contains the logical NOR of the two specified bits V Contains the logical OR of the two specified bits C Contains the logical AND of the two specified bits N Contains the logical XOR of the two specified bits Encoding Mnemonic Format Bytes BXOR bitaddrz z bitaddra y 7A QQ ZZ oz 4 User s Manual 6 20 V 1 6 2001 08 1 fi User s Manual nrineon M C166S V1 SubSy
410. ruction has been executed Note The MULIP flag is part of the context of the interrupted task When the interrupting routine does not return to the interrupted task e g scheduler switches to another task MULIP must be set or cleared according to the context of the task that is switched to User s Manual 3 75 V 1 6 2001 08 pae 1 fi User s Manual SUE NN C166S V1 SubSystem Central Processing Unit 3 7 6 The Processor Status Word Register PSW The bit addressable Processor Status Word register reflects the current status of the microcontroller Two groups of bits represent the current ALU status and the current CPU interrupt status One separate bit USRO within PSW is provided as a general purpose flag i Status Word SFR FF10 884 Reset value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ILVL IEN sto o o uso MOY E zo vi icon rwh wi w r r r rw rwh rwh rwh rwh rwh rwh Field Bits Type Description ILVL 15 12 rwh CPU Priority LeVeL Op Lowest priority Fu Highest priority IEN 11 rw Interrupt PEC ENable Bit globally 0 Interrupt PEC requests are disabled 1 Interrupt PEC requests are enabled S1 10 rw Reserved for system USRO 6 rwh General Purpose Flag May be used by application MULIP 5 r MULtiplication division In Progress 0 No multiplication division in process 1 Multiplication division has been interrupted E
411. rupt Request 83 IRQ83IC 018Cy 63H irq_i 84 Product Interrupt Request 84 IRQ84IC 0190 644 User s Manual 4 46 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 4 Interrupt Vector Table cont d sorted by trap number Signal Name Source of Interrupt Interrupt Control Vector Trap Interrupt IF Register Location No irq_i 85 Product Interrupt Request 85 IRQ85IC 0194 65H irq_i 86 Product Interrupt Request 86 IRQ86IC 01984 664 irq_i 87 Product Interrupt Request 87 IRQ87IC 019Cy 67H irq_i 88 Product Interrupt Request 88 IRQ88IC 01A0y 68H irq_i 89 Product Interrupt Request 89 IRQ89IC 0144 69h irq_i 90 Product Interrupt Request 90 IRQ90IC 01A8y 6Ay irq_i 91 Product Interrupt Request 91 IRQ91IC 01ACy 6By irq_i 92 Product Interrupt Request 92 IRQ92IC 01B0y 6Cy irq_i 93 Product Interrupt Request 93 IRQ93IC 01B4 6Dy irq_i 94 Product Interrupt Request 94 IRQ94IC 01B8y 6Ey irq_i 95 Product Interrupt Request 95 IRQ95IC 01BCy 6Fy irq_i 96 Product Interrupt Request 96 IRQ96IC 01C0y 70H irq_i 97 Product Interrupt Request 97 IRQ97IC 0104 714 irq_i 98 Product Interrupt Request 98 IRQ98IC 01C8y 72H irq_i 99 Product Interrupt Request 99 IRQ99IC 01CC 73H irq_i 100 Product Interrupt Request 100 IRQ100IC 01D0y 744 irq_i 101 Product Interrupt Request 101 IRQ1011C 01D4 75H irq_i
412. s All accesses that are not covered by these four areas are then controlled via BUSCONO This allows the use of memory components or peripherals with different interfaces within the same system while optimizing accesses to each of them SYSCON System Control Register SFR FF12y 89 Reset value OXX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYT CLK WR CS VISI DIS EN CFG CFG XPEN BLE rw wh rw rw rw Field Bits Type Description VISIBLE 1 rw Visible Mode Control O Accesses to XBUS peripherals are done internally 1 XBUS peripheral accesses are made visible on the external pins XPEN 2 rw XBUS Peripheral Enable Bit O Accesses to the on chip X Peripherals and their functions are disabled 1 Theon chip X Peripherals are enabled and can be accessed User s Manual 8 21 V 1 6 2001 08 pae e Infineon technologies User s Manual C166S V1 SubSystem The External Bus Interface Field Bits Type Description CSCFG 6 rw Chip Select Configuration Control O Latched CS mode The CS signals are latched internally and driven to the enabled port pins synchronously m 1 Unlatched CS mode The CS signals are directly derived from the address and driven to the enabled port pins WRCFG 7 rwh Write Configuration Control Set according to pin POH O during reset 0 Pins WR and BHE retain their normal function 1 Pi
413. s upward to higher memory locations is reached The entries that have been previously saved in external memory must now be restored This is called stack filling Because procedure call instructions do not continue to nest infinitely and call and return instructions alternate flushing and filling normally occurs very infrequently If this is not true for a given program environment this technique should not be used because of the overhead of flushing and filling The basic mechanism is the transformation of the addresses of a virtual stack area controlled via SP STKOV and STKUN to a defined physical stack area within the DPRAM via hardware This virtual stack area covers all possible locations that SP can point to i e 00 F000 through 00 FFFEy STKOV and STKUN accept the same 4 KByte address range The size of the physical stack area within the DPRAM that is used for standard stack operations is defined via bitfield STKSZ in register SYSCON see below Table 3 15 Circular Stack Address Transformation STKSZ Stack Size DPRAM Addresses Words Significant Bits Words of Physical Stack of Stack Ptr SP 000g 256 00 FBFEy 00 FAOOy Default after Reset SP 8 SP 0 001g 128 00 FBFEy 00 FBO0y SP 7 SP 0 010g 64 00 FBFEy 00 FB80y SP 6 SP 0 011g 32 00 FBFEy 00 FBCOy SP 5 SP 0 100g 512 00 FBFEy 00 F800y not for 1KByte SP 9 SP 0 DPRAM 101 Reserved Do not use this combination 110g Reserved Do not
414. s Manual 4 43 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Memory Organization Table 4 4 Interrupt Vector Table cont d sorted by trap number Signal Name Source of Interrupt Interrupt Control Vector Trap Interrupt IF Register Location No 0038 OE 003Cy OF irq_i 16 Product Interrupt Request 16 IRQ16IC 0040 104 irq_i 17 Product Interrupt Request 17 IRQ17IC 0044 11 irq_i 18 Product Interrupt Request 18 IRQ18IC 0048 12 irq_i 19 Product Interrupt Request 19 IRQ19IC 004Cy 13H irq_i 20 Product Interrupt Request 20 IRQ20IC 0050 144 irq_i 21 Product Interrupt Request 21 IRQ211C 0054 154 irq_i 22 Product Interrupt Request 22 IRQ221C 0058 164 irq_i 23 Product Interrupt Request 23 IRQ23IC 005Cy 174 irq_i 24 Product Interrupt Request 24 IRQ24IC 0060 184 irq_i 25 Product Interrupt Request 25 IRQ25IC 0064 194 irq_i 26 Product Interrupt Request 26 IRQ26IC 0068 1Ay irq_i 27 Product Interrupt Request 27 IRQ27IC 006Cy 1By irq_i 28 Product Interrupt Request 28 IRQ28IC 0070y 1Cy irq_i 29 Product Interrupt Request 29 IRQ29IC 00744 1Du irq_i 30 Product Interrupt Request 30 IRQ30IC 0078 1Eu irq_i 31 Product Interrupt Request 31 IRQ31IC 007Cy 1F irq_i 32 Product Interrupt Request 32 IRQ321C 0080 20H irq_i 33 Product Interrupt Request 33 IRQ33IC 0084 21h per irg i 2 GPT12E
415. s are useful for manipulating several data types Data Types The C166S data formats support all ANSI C data types In addition some C compilers support new types that allow the efficient use of the bit manipulation instructions in embedded control applications The C166S directly supports the following data formats Table 3 16 CPU data formats CPU data format Size bytes Range BIT 1 bit 0 or 1 BYTE 1 0 to 255U or 128 to 127 WORD 2 0 to 65535U or 32768 to 432767 Table 3 17 ANSI C data types ANSI C data types Size bytes Range CPU data format bit 1bit 0 or 1 BIT sfrbit 1bit 0 or 1 BIT esfrbit 1bit 0 or 1 BIT signed char 1 128 to 127 BYTE unsigned char 1 0 to 255U BYTE User s Manual 3 68 V 1 6 2001 08 1 fi User s Manual a C166S V1 SubSystem Central Processing Unit Table 3 17 ANSI C data types ANSI C data types Size bytes Range CPU data format sfr 1 0 to 65535U WORD esfr 1 0 to 65535U WORD signed short 2 32768 to 432767 WORD unsigned short 2 0 to 65535U WORD bitword 2 0 to 65535U WORD or BIT signed int 2 32768 to 32767 WORD unsigned int 2 0 to 65535U WORD signed long 4 2147483648 to Not directly supported 12147483647 unsigned long 4 0 to 4294967295UL Not directly supported float 4 1 176E 38 to Not directly supported 3 402E 38 double 8 2 225E
416. s as an alternate output function PORTO is then switched to high impedance input mode to read the incoming instruction or data In 8 bit data bus mode two memory cycles are required for word accesses the first for the low byte and the second for the high byte of the word During write cycles PORTO outputs the data byte or word after outputting the address User s Manual 7 4 V 1 6 2001 08 C Infineon User s Manual UE C166S V1 SubSystem Parallel Ports During external accesses in demultiplexed bus modes PORTO reads the incoming instruction or data word or outputs the data byte or word Alternate Function a POH 7 POH 6 POH 5 POH PORTO POL General Purpose 8 bit 16 bit Input Output Demux Bus Demux Bus MUX Bus MUX Bus Figure 7 2 PORTO IO and Alternate Functions When an external bus mode is enabled the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware The input of the port output latch is disconnected from the internal bus and is switched to the line labeled Alternate Data Output via a multiplexer The alternate data can be the 16 bit intrasegment address or the 8 16 bit data information The incoming data on PORTO is read on the line Alternate Data Input While an external bus mode is enabled the user software should not write to the port output latch otherwise unpredictable results may occur When the external bus modes are
417. s done in three levels The XADRSx registers have the highest priority priority I The ADDRSEL registers have the second highest priority priority Il If there is no match with any XADRSx or ADDRSELx register the access to the external bus uses register BUSCONO priority III 1 The XADR registers are the control registers of the internal XBUS interface see Section 8 7 User s Manual 8 28 V 1 6 2001 08 1 fi User s Manual neon Infineon C1 66S V1 SubSystem The External Bus Interface Priority 1 The XADRSx registers are evaluated first A match with one of these registers directs the access to the respective X Peripheral using the corresponding XBCONx register and ignoring all other ADDRSELx registers Priority of the XADRSx registers XADR1 priority 1 1 XADRS2 1 2 XADRS3 1 3 XADR4 1 4 XADRS5 1 5 XADRS6 1 6 Priority 2 A match with one of the registers ADDRSELx directs the access to the respective external area using the corresponding BUSCONx register Priority of the ADDRSELx registers ADDRSEL2 priority 11 1 ADDRSEL4 11 2 ADDRSEL1 11 3 ADDRSELS II 4 Priority 3 If there is no match with any XADRSx or ADDRSELx register the access to the external bus uses BUSCONO XBCON1 XBCON XBCON6 BUSCON2 BUSCON4 BUSCON1 BUSCON3 BUSCONO L Active Window Inactive Window Figure 8 10 Address Window Arbitration Example RPOH Reset Value of POH SFR F108 844 Reset value
418. s due to a parity error Asynchronous Mode only f the overrun error detection enable bit CON OEN is set and the last character received was not read out of the receive buffer by software or by a DMA transfer at the time the reception of a new frame is complete the overrun error flag CON OE is set indicating that the error interrupt request is due to an overrun error Asynchronous and Synchronous Mode 10 3 5 Interrupts Four interrupt sources are provided for serial channel ASC Line TIC indicates a transmit interrupt TBIC indicates a transmit FIFO interrupt RIC indicates a receive interrupt and SEIC indicates an error interrupt of the serial channel The interrupt output lines TBIR TIR RIR and EIR are activated active state for two periods of the module clock feik The cause of an error interrupt request framing parity overrun error can be identified by the error status flags FE PE and OE located in control register CON Note In contrast to the error interrupt request line EIR the error status flags FE PE OE are not reset automatically but must be cleared by software For normal operation other than error interrupt the ASC provides three interrupt requests to control data exchange via this serial channel TBIR is activated when data is moved from TBUF to the transmit shift register TIR is activated before the last bit of an asynchronous frame is transmitted or after the last bit of a synchronous frame has
419. s helps to identify specific instructions when reading executable code ie during the debugging phase Notes for Opcode Lists 1 These instructions are encoded by means of additional bits in the operand field of the instruction xX0y x74 Rw data3 or Rb data3 x8y xBy Rw Rw or Rb Rw XCy XFy Rw Rw or Rb Rw For these instructions only the lowest four GPRs RO to R3 can be used as indirect address pointers 2 These instructions are encoded by means of additional bits in the operand field of the instruction 00xx XXXXp EXTS or ATOMIC 01xx XXXXp EXTP 10xx XXXXp EXTSR or EXTR 11xxo000 EXTPR Notes on the JMPR Instructions The condition code to be tested for the JMPR instructions is specified by the opcode Two mnemonic representation alternatives exist for some of the condition codes Notes on the BCLR and BSET Instructions The position of the bit to be set or to be cleared is specified by the opcode The operand bitoff n n 2 O to 15 refers to a particular bit within a bit addressable word Notes on the Undefined Opcodes A hardware trap occurs when one of the undefined opcodes signified by is decoded by the CPU User s Manual 5 16 V 1 6 2001 08 Infineon technologies User s Manual C166S V1 SubSystem Instruction Set Hex Num Mnemonic Operands Hex Num Mnemonic Operands code ber of code ber of
420. second instruction after the instruction following the add instruction Class B Trap Class B traps are generated by unrecoverable hardware failures In case of hardware failure the CPU must immediately start a failure service routine Class B traps can interrupt an atomic extend sequence After finishing a Class B service routine the interrupted instruction flow cannot be restored Note If a Class A trap and a Class B occur simultaneously both trap flags are set If this occurs during execution of an atomic extend sequence then the presence of the Class B trap breaks the protection of atomic extend operations and the Class A trap will be executed immediately without waiting for the sequence completion After return from the service routine the IP is popped from the system stack and immediately pushed again because of the other pending Class B trap In this situation the interrupted instruction flow cannot be restored All Class B traps have the same trap priority trap priority 1 When several Class B traps are active at the same time the corresponding flags in the TFR are set and the trap service routine is entered Since all Class B traps have the same vector the priority of service of Class B that occur simultaneously is determined by the software in the trap service routine User s Manual 3 30 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit During the execution
421. sents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Always cleared C Always cleared N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes XORB Rb data3 59 n O 2 XORB Rb RO 51 nm 2 XORB Rb Rw 59 n 11ii 2 XORB Rb Rw 59 n 10ii 2 XORB mem reg 55 RR MM MM 4 XORB reg data8 57 RR HH xx 4 XORB reg mem 53 RR MM MM 4 User s Manual 6 99 V 1 6 2001 08 pae e Infineon technologies User s Manual C166S V1 SubSystem User s Manual 6 100 Detailed Instruction Set V 1 6 2001 08 7 fi User s Manual n Infineon C1 66S V1 SubSystem Parallel Ports 7 Parallel Ports In order to accept or generate single external control signals or parallel data the C166S s provides up to 48 parallel IO lines organized into six 8 bit IO ports PORTO made of POH and POL PORT1 made of P1H and P1L Port 4 Port 6 These port lines may be used for general purpose Input Output controlled via software or may be used implicitly by the C166S V1 SubS R1 s integrated peripherals or the External Bus Controller All port lines are bit addressable and all input output lines are individually bit wise programmable as inputs or outputs via direction registers The lO ports are true bidirectional ports which are switched to high impedance state when con
422. ser s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set NEG Integer Two s Complement NEG Group Arithmetic Instructions Syntax NEG op1 Source Operand s op1 gt WORD Destination Operand s op1 gt WORD Operation op1 lt 0 opt Description Performs a binary 2 s complement of the source operand specified by op1 The result is then stored in op1 CPU Flags E Z V C N E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the word data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes NEG Rwy 81 nO 2 User s Manual 6 66 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set NEGB Integer Two s Complement NEGB Group Arithmetic Instructions Syntax NEGB op1 Source Operand s opi BYTE Destination Operand s op1 gt BYTE Operation op1 lt 0 opt Description Performs a binary 2 s complement of the source operand specified by op1 The result is then stored in op1 CPU Flags E Z V C N E Set if the value of op1 represents the lowest possible negative number Cleared otherwise Used to signal the
423. ser s Manual 10 15 V 1 6 2001 08 pae User s Manual Infineon C1668 V1 SubSystem Asynchronous Synchronous Serial Interface ASC Between two consecutive receive or transmit data bytes one shift clock cycle fgg delay is inserted Receive Transmit Timing Shift Shift Shift Clock Shift T T TXD Transmit Data Data Data RXD i Bit n 1 Bit n 2 Receive Data i Valid Valid RXD Data n 1 Data n 2 Continuous Transmit Timing a AAA TXD Transmit Data l xo Meee e O SS A 1 Byte 2 Byte RE Do o1 o2 os oa os oe ov oof o1 o2 os w A ME 1 Byte 2 Byte Figure 10 8 ASC Synchronous Mode Waveforms User s Manual 10 16 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Asynchronous Synchronous Serial Interface ASC 10 3 3 Baudrate Generation The serial channel ASC has its own dedicated 13 bit baudrate generator with reload capability allowing baudrate generation independent of other timers The baudrate generator is clocked with a clock fpyy derived via a prescaler from the ASC input clock fo The baudrate timer counts downwards and can be started or stopped through the baudrate generator run bit CON_R Each underflow of the timer provides one clock pulse to the serial channel The timer is reloaded with the value stored in its 13 bit reload register each time it underflows The resulting clock fgry is again divi
424. specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 The flags are set according to the rules of subtraction The operands remain unchanged CPU Flags E Z V C N E Set if the value of op2 represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if result equals zero Cleared otherwise V Set if an arithmetic underflow occurred i e the result cannot be represented in the byte data type Cleared otherwise C Set if a borrow is generated Cleared otherwise N Set if the most significant bit of the result is set Cleared otherwise Encoding Mnemonic Format Bytes CMPB Rb data3 49 n O 2 CMPB Rb RO 41 nm 2 CMPB Rb Rw 49 n 11ii 2 CMPB Rb Rwi 49 n 10ii 2 CMPB reg data8 47 RR xx 4 CMPB reg mem 43 RR MM MM 4 User s Manual 6 26 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set CMPD1 Integer Compare and Decrement by 1 CMPD1 Group Compare and Loop Control Instructions Syntax CMPD1 op1 op2 Source Operand s op1 op2 gt WORD Destination Operand s op1 gt WORD Operation op1 op2 op1 lt op1 1 Description This instruction is used to enhance the performance and flexibility of loops The source operand specified by op1 is compared to the source operand specified by op2 by performing a 2 s complement binary subtraction of op2 from op1 Operand op1 may
425. ss 16 MB 7 11 Port 4 10 and Alternate Functions V 1 6 2001 08 User s Manual C166S V1 SubSystem Parallel Ports technologies Internal Bus Port Output Direction Register Register AltDir T AItEN AltDataOut Driver AltDataln 4 Input Register Port4 1 vsd Figure 7 7 Block Diagram of a Port 4 Pin User s Manual 7 12 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Parallel Ports 7 5 Port 6 If this 8 bit port is used for general purpose lO the direction of each line can be configured via the corresponding direction register DP6 P6 Port 6 Data Register SFR FFCCy E6y Reset Value 00y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P6 7 P6 6 P6 5 P6 4 P6 3 P6 2 P6 1 P6 0 rw rw rw rw rw rw rw rw Bit Function P6 y Port data register P6 bit y DP6 P6 Direction Ctrl Register SFR FFCEy E7 y Reset Value 00y 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP6 DP6 DP6 DP6 DP6 DP6 DP6 DP6 Ni 6 5 4 3 2 0 rw rw rw rw rw rw rw rw Bit Function DP6 y Port direction register DP6 bit y DP6 y 0 Port line P6 y is an input high impedance DP6 y 1 Port line P6 y is an output Alternate Functions of Port 6 A programmable number of chip select signals CS4 CS0
426. ss Memory or from the external memory based on the current Instruction Pointer IP value DECODE In this stage the previously fetched instruction is decoded and the required operands are fetched EXECUTE In this stage the specified operation is performed on the previously fetched operands WRITE BACK In this stage the result is written to the specified location User s Manual 2 2 V 1 6 2001 08 pae 1 fi User s Manual neon Infineon C1 66S V1 SubSystem System Overview If this technique were not used each instruction would require four machine cycles This increased performance allows a greater number of tasks and interrupts to be processed Instruction Decoder Instruction decoding is primarily generated from PLA Programmable Logic Array outputs based on the selected opcode No microcode is used and each pipeline stage receives control signals staged in control registers from the decode stage PLAs Pipeline holds are primarily caused by waitstates for external memory accesses and cause the holding of signals in the control registers Multiple cycle instructions are performed through instruction injection and simple internal state machines which modify required control signals 2 1 2 High Function 8 bit and 16 bit Arithmetic and Logic Unit All standard arithmetic and logical operations are performed in a 16 bit ALU In addition for byte operations signals are provided from bits six and seven of the ALU result t
427. ss offset Destination Operand s none Operation IF op1 1 THEN IP op2 ELSE Next Instruction END IF Description Detailed Instruction Set JMPI If the condition specified by op1 is met a branch to the absolute address specified by op2 is taken If the condition is not met no action is taken and program execution continues normally with the instruction following the JMPI instruction CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes JMPI cc Rw 9C cn 2 User s Manual 6 53 V 1 6 2001 08 1 fi User s Manual nrineon M os C166S V1 SubSystem Detailed Instruction Set JMPR Relative Conditional Jump JMPR Group Jump Instructions Syntax JMPR op1 op2 Source Operand s op1 gt condition code op2 gt 8 bit signed displacement Destination Operand s none Operation IF op1 1 THEN IP IP 2 sign_extend op2 ELSE Next Instruction END IF Description If the extended condition specified by op1 is met program execution continues at the location of the instruction pointer IP plus the specified displacement op2 The displacement is a two s complement number which is sign extended and counts the relative distance in words The value of the IP used in the target address calculation is the address of the instruction following the JMPR instruction If the specified condition is not met program e
428. sse E ER ARS x REXAAEERXxX AM RA e rige 4 5 4 3 2 Special Function Register Areas ooooocococoooommmoooo 4 5 4 3 3 PEC Source and Destination Pointers oooooccococooooo 4 7 4 4 External Memory Space ooococcccoccnn eee ees 4 8 4 4 1 External dala accesses lt 1 2 euraed e eau ye eee vee 4 8 4 5 Crossing Memory Boundaries 02 cece tees 4 9 4 6 SA cose Jcteeeee A agan eiea paara 4 10 4 6 1 Data Organization in General Purpose Registers 4 10 4 7 SFR ESFR Table yes a acd diese ole Aid atid hace herd ed Sub as armed eben weed 4 12 4 8 Interrupt Vector Table 0 0 ccc ee eee 4 43 5 Instruction Set ecos ect eae eae heed cee E a ny ead 5 1 5 1 Short Instruction Summary uere ERR ERES ER rociar 5 1 5 2 Instruction Set Summary 000 00s 5 3 5 3 Instruction Opcodes 002 ees 5 16 5 4 Instruction Description oooooooccooonn ooo 5 21 6 Detailed Instruction Set 0 0 0 ee 6 1 7 Parallel PONS ose 22 65 6 coria 7 1 7 1 Alternate Port Functions uueusueszekscmeietbkRiBb cdta das 7 2 7 2 PORT td scene ee eee es Se 7 3 7 3 PORTIT PT bass eee bea a eee eee id eee 7 7 7 4 POU sian tee Gun baagekewkixs otentuaeeeees RO exe deg kes 7 10 7 5 A E EXE Pasqua EE E A A xaxa RR 7 13 8 The External Bus Interface Llslssu 8 1 8 1 Single chip Mode AAA 8 2 8 2 External Bus Modes ain va d pe CE A Cae ONE OR 8 2 8 2 1 Multiplexed Bus Modes
429. ssible when the Baudrate Generator Run Bit CON_R is set to 1 Otherwise the serial interface is idle Do not program the mode control field COM_M to one of the reserved combinations to avoid unpredictable behavior of the serial interface User s Manual 10 5 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Asynchronous Synchronous Serial Interface ASC The operating mode of the serial channel ASC is controlled by its control register CON This register contains control bits for mode and error check selection and status flags for error identification CON Control Register Reset value 0000p 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R LB BRS ODD FDE OE FE PE OEN EEN PEN REN STP M w rw rw rw rw rwh rwh mwh rw rw rw ewh rw rw Field Bits Typ Description M 2 0 rw Mode Control 000 8 bit data for synchronous operation 001 8 bit data for asynchronous operation 010 Reserved Do not use this combination 011 7 bit data and parity for asynchronous operation 100 9 bit data for asynchronous operation 101 8 bit data and wake up bit for asynchronous operation 110 Reserved Do not use this combination 111 8 bit data and parity for asynchronous operation STP 3 rw Number of Stop Bits Selection 0 One stop bit 1 Two stop bits REN 4 rwh Receiver Enable Bit 0 Receiver disabled 1 Receiver enabled Note bit
430. ssion of the previous character is complete This allows the transmission of characters back to back without gaps Data reception is enabled by the Receiver Enable Bit CON_REN After reception of a character has been completed the received data can be read from the read only Receive Buffer register RBUF the received parity bit can also be read if provided by the selected operating mode Bits in the upper half of RBUF that are not valid in the selected operating mode will be read as zeros Data reception is double buffered so that reception of a second character may already begin before the previously received character has been read out of the receive buffer register In all modes receive overrun error detection can be selected through bit CON_OEN When enabled the overrun error status flag CON_OE and the error interrupt request line EIR will be activated when the receive buffer register has not been read by the time reception of a ninth character is complete The previously received character in the receive buffer is overwritten The Loop Back option selected by bit CON LB allows the data currently being transmitted to be received simultaneously in the receive buffer This may be used to test serial communication routines at an early stage without having to provide an external network In Loop back Mode the alternate input output functions of the asosiacted Port pins are not necessary Note Serial data transmission or reception is only po
431. states caused by the internal synchronization The asynchronous READY is synchronized internally and programmed waitstates may be necessary to provide proper bus cycles see also notes on normally ready peripherals below An asynchronous READY signal that has been activated by an external device may be deactivated in response to the trailing rising edge of the respective command RD or WR Note When the READY function is enabled for a specific address window each bus cycle within this window must be terminated with an active READY signal Otherwise the controller hangs until the next reset A time out function is provided by the watchdog timer User s Manual 8 19 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem The External Bus Interface Combining the READY function with predefined waitstates is advantageous in two cases Memory components with a fixed access time and peripherals operating with READY may be grouped into the same address window The external waitstate control logic in this case would activate READY either upon the memory s chip select or with the peripheral s READY output After the predefined number of waitstates the C166S will check its READY line to determine the end of the bus cycle For a memory access it will already be low for a peripheral access it may be delayed As memories tend to be faster than peripherals there should be no impact on system
432. stem Detailed Instruction Set CALLA Call Subroutine Absolute CALLA Group Call Instructions Syntax CALLA op1 op2 Source Operand s op1 gt extended condition code op2 16 bit address offset Destination Operand s none Operation IF op1 THEN SP SP 2 SP lt IP IP op2 ELSE next instruction END IF Description If the condition specified by op1 is met a branch to the absolute memory location specified by the second operand op2 is taken The value of the instruction pointer IP is placed into the system stack Because the IP always points to the instruction following the branch instruction the value stored in the system stack represents the return address of the calling routine If the condition is not met no action is taken and the next instruction is executed normally CPU Flags E Z V C N E Not affected F4 Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes CALLA XCC caddr CA d00a MM MM 4 User s Manual 6 21 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set CALLI Call Subroutine Indirect CALLI Group Call Instructions Syntax CALLI op1 op2 Source Operand s op1 gt condition code op2 gt 16 bit address offset Destination Operand s none Operation IF op1 THEN SP SP 2 SP lt IP IP op2 ELSE next instruction END IF Description If the condition speci
433. sters that need to be accessed frequently are allocated to the standard SFR area wherever possible Note The tools are equipped to monitor accesses to the ESFH area and will automatically insert EXTR instructions switch the SFR bank address or issue a warning in case of missing or excessive EXTR instructions 4 3 3 PEC Source and Destination Pointers The 16 24 32 word locations for the 8 12 16 PEC channels in the DPRAM from 00 FCEOh 00 FCDOh 00 FCCOh to 00 FCFEh just below the bit addressable section are provided as source and destination address pointers for data transfers on the PEC channels Each channel uses a pair of pointers stored in two subsequent word locations with the SouRCe Pointer SRCPx on the lower and the DeSTination Pointer DSTPx on the higher word address Whenever a PEC data transfer is performed the pair of SRCPx and DSTPx selected by the specified PEC channel number is accessed independent of the current DPP register contents also the locations referred to by these pointers are accessed independently of the current DPP register contents lf a PEC channel is not used the corresponding pointer location area is available and can be used for word or byte data storage or for instructions For more details about use of SRCPx and DSTPx for PEC data transfer see Interrupt and Exception Execution Section 3 4 User s Manual 4 7 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSys
434. stination Pointers 3 33 3 4 6 2 PEC Control Registers 0 0c cee eee eee 3 36 3 4 6 3 Short Transfer Mode 2222 cbeteouctee dees phon vivero 3 38 3 4 6 4 Long Transfer Mode veveuscexe ese recrear E RS ee 3 39 3 4 6 5 Channel Link Mode for Data Chaining ooooooo 3 41 3 4 6 6 PEC Channels Assignment and Arbitration 3 43 3 4 6 7 Programmable End of PEC Interrupt Level 3 44 3 5 Using General Purpose Registers ooooooocooonmmoo 3 46 3 5 1 Context Switch s sux xs roscar sra 3 50 3 6 Data Addressing i2 ae rag RR a a AUR RR RDR RE ERE 3 52 3 6 1 Short Addressing Modes s eee eee 3 52 3 6 2 Long and Indirect Addressing Modes 3 54 3 6 2 1 Addressing via Data Page Pointer oooooccocococoo ooo 3 55 3 6 2 2 DPP Override Mechanism in the C166S ooooooocooooo 3 57 3 6 2 3 Long Addressing Mode 00 0c eee eee ees 3 58 3 6 2 4 Indirect Addressing Modes 00 cece eee eee 3 59 3 6 3 The System Stack cocaina A eax 3 61 3 6 3 1 Stack Overflow and Underflow 0 020e eee eee 3 62 3 6 3 2 Linear Stack cia ore errs ayers anG ane SS acec atelier ete a ow a Meee o Seapesetice 3 64 3 6 3 3 Circular Virtual Stack 0 0 ec es 3 65 3 7 Data Processing zai2ereesieesheibep cReSi248 versos x de 3 68 3 7 1 Data TYPES 26isetecsevetstseed oes taeda ERU ERE UR TE 3 68 3 7 2 Constants p P
435. supported no bit TxOTL in registers TxCON Table 12 7 Timer x Input Parameter Selection Timer and Gated Timer Modes Txl Prescaler for fj Prescaler for f Prescaler for f Prescaler for foi BPS1 00 BPS1 01 BPS1 10 BPS1 11 000 8 4 32 16 001 16 8 64 32 010 32 16 128 64 011 64 32 256 128 100 128 64 512 256 101 256 128 1024 512 110 512 256 2048 1024 111 1024 512 4096 2048 User s Manual 12 19 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem General Purpose Timer Unit Timers T2 and T4 in Counter Mode In Counter Mode Timers T2 and T4 can be clocked either by a transition at the respective external input line TxIN or by a transition of T3OTL Auxiliary Timer Tx TxIRQ Up Down TxEUD Xx 2 4 MCB02221_b Figure 12 11 Block Diagram of an Auxiliary Timer in Counter Mode The event causing an increment or decrement of a timer can be a positive a negative or both a positive and a negative transition at either the respective input line or at the output toggle latch T3OTL Bitfield Txl in the respective control register TxCON selects the triggering transition see Table 12 8 Table 12 8 Auxiliary Timer Counter Mode Input Edge Selection T21 TAI Triggering Edge for Counter Increment Decrement X00 None Counter Tx is disabled 0 0 1 Positive transition rising edge on TxI
436. t count 1 END WHILE count 0 Data Page DPPx SFR range lt Standard Enable interrupts and traps Description Overrides the standard DPP addressing scheme of the long and indirect addressing modes and causes all SFR or SFR bit accesses via the reg bitoff or bitaddr addressing modes being made to the Extended SFR space for a specified number of instructions During their execution both standard and PEC interrupts and class A hardware traps are locked The EXTSR instruction becomes immediately active such that no additional NOPs are required For any long mem or indirect address in an EXTSR instruction sequence the value of op1 determines the 8 bit segment address bits A23 A16 valid for the corresponding data access The long or indirect address itself represents the 16 bit segment offset address bits A15 A0 The value of op2 defines the length of the effected instruction sequence CPU Flags E Z V C N oce O A ee E Not affected Z Not affected User s Manual 6 46 V 1 6 2001 08 pae e Infineon technologies User s Manual C166S V1 SubSystem V Not affected C Not affected N Not affected Encoding Mnemonic EXTSR seg irang2 EXTSR RW irang2 User s Manual Detailed Instruction Set Format Bytes D7 10 0 ss 00 4 DC 10 m 2 6 47 V 1 6 2001 08 pae 1 fi User s Manual o C166S V1 SubSystem Detailed Instruction Set IDLE Enter I
437. t Interrupt Request 43 IRQ43IC 01244 494 irq_i 44 Product Interrupt Request 44 IRQ44IC 01284 4AH per_irq_i 11 Watchdog Timer WDTIC 01304 4By per_irq_i o End of PEC Transfer EOPIC 012Cy 4Cy irq_i 45 Product Interrupt Request 45 IRQ45IC 0134 4D irq_i 46 Product Interrupt Request 46 IRQ46IC 0138 4Ey irq_i 47 Product Interrupt Request 47 IRQ471C 013Cy 4Fu irq_i 64 Product Interrupt Request 64 IRQ64IC 0140 50h irq_i 65 Product Interrupt Request 65 IRQ65IC 01444 514 irq_i 66 Product Interrupt Request 66 IRQ66IC 01484 524 irq_i 67 Product Interrupt Request 67 IRQ67IC 014C y 53H irq_i 68 Product Interrupt Request 68 IRQ68IC 0150 54y irq_i 69 Product Interrupt Request 69 IRQ69IC 01544 55H irq_i 70 Product Interrupt Request 70 IRQ70IC 01584 56H irq_i 71 Product Interrupt Request 71 IRQ71IC 015Cy 57H irq_i 72 Product Interrupt Request 72 IRQ721C 0160 58H irq_i 73 Product Interrupt Request 73 IRQ73IC 0164 59H irq_i 74 Product Interrupt Request 74 IRQ74IC 01684 5Ay irq_i 75 Product Interrupt Request 75 IRQ75IC 016Cy 5Bh irq_i 76 Product Interrupt Request 76 IRQ76IC 0170 5Ch irq_i 77 Product Interrupt Request 77 IRQ77IC 0174 5Dy irq_i 78 Product Interrupt Request 78 IRQ78IC 0178 5Ey irq_i 79 Product Interrupt Request 79 IRQ79IC 017Cy 5Fh irq_i 80 Product Interrupt Request 80 IRQ50IC 0180 604 irq_i 81 Product Interrupt Request 81 IRQ81IC 0184 61h irq_i 82 Product Interrupt Request 82 IRQ821C 01884 624 irq_i 83 Product Inter
438. t at TXD After the eighth bit has been shifted in the contents of the receive shift register are transferred to the receive data buffer RBUF the receive interrupt request line RIR is activated the receiver enable bit CON REN is reset and serial data reception stops Note Pin TXD must be configured for alternate data output in order to provide the shift clock Pin RXD must be configured as alternate data input Synchronous reception is stopped by clearing bit CON REN A currently received byte is completed including the generation of the receive interrupt request and an error interrupt request if appropriate Writing to the transmit buffer register while a reception is in progress has no effect on reception and will not start a transmission If a previously received byte has not been read out of a full receive buffer at the time the reception of the next byte is complete both the error interrupt request line EIR and the overrun error status flag CON OE will be activated set provided the overrun check has been enabled by bit CON OEN 10 3 2 3 Synchronous Timing Figure 10 8 shows timing diagrams of the ASC Synchronous Mode data reception and data transmission In idle state the shift clock level is high With the beginning of a synchronous transmission of a data byte the data is shifted out at RXD with the falling edge of the shift clock If a data byte is received through RXD data is latched with the rising edge of the shift clock U
439. t is set Cleared otherwise Encoding Mnemonic Format Bytes ANDB Rb data3 69 n 0 2 ANDB Rb Rbm 61 nm 2 ANDB Rb Rw 69 n 11ii 2 ANDB Rb Rw 69 n 10ii 2 ANDB mem reg 65 RR MM MM 4 ANDB reg data8 67 RR xx 4 ANDB reg mem 63 RR MM MM 4 User s Manual 6 7 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem Detailed Instruction Set ASHR Arithmetic Shift Right ASHR Group Shift and Rotate Instructions Syntax ASHR op1 op2 Source Operand s op1 gt WORD op2 gt shift counter Destination Operand s op1 gt WORD Operation count op2 V 0 C 0 DO WHILE count z 0 V C v V C lt op1 0 op1 n op1 n 1 n 0 14 count lt count 1 END WHILE Description Arithmetically shifts the destination word operand op1 right by the number of times as specified by the source operand op2 To preserve the sign of the original operand op1 the most significant bits of the result are filled with zeros if the original most significant bit was a 0 or with ones if the original most significant bit was a 1 The Overflow flag is used as a Rounding flag The least significant bit is shifted into the Carry Only shift values between 0 and 15 are allowed When using a GPR as the count control only the least significant 4 bits are used CPU Flags E Z V C N loa prop pp E Always cleared Z Set if result equals zero Cleared otherwise
440. t lines Timer Block 2 fppgus 2 maximum resolution 2 independent timers counters Timers counters can be concatenated 3 operating modes timer gated timer counter Extended capture reload functions via 16 bit Capture Reload register CAPREL Separate interrupt request lines 2 2 4 Parallel Ports PPorts The C166S V1 SubS H1 provides up to 48 I O lines which are organized into four input output ports All port lines are bit addressable and individually bit wise programmable as inputs or outputs via direction registers The output driver is disabled when an I O line is configured as input This allows true bidirectional ports which are switched to high impedance state when configured as inputs Further features like output driver control input characteristic selection temperature compensation and output mode selection open drain or push pull mode are not supported by the subsystem s port module However these features can be easily added by the product logic because they are controlling the PADs directly and have no influence on the port module The output drivers enable signals are switched asynchronously to inactive level as soon as a subsystem reset occurs In this case all pins are configured as inputs Most port lines have programmable alternate input or output functions associated with them PORTO and PORT1 may be used as address and data lines when accessing external memory while Port 4 outputs th
441. te Both ordering schemes hexadecimal opcode and mnemonic are provided in more detailed lists in the following sections of this manual User s Manual C166S V1 SubSystem Instruction Set 8x 9x Ax Bx Cx Dx Ex Fx xO CMPI1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS MOV MOV x1 NEG CPL NEGB CPLB AT MOVB MOVB EXTR x2 CMPI1 CMPI2 CMPD1 CMPD2 MOVBZ MOVBS PCALL MOV x3 l MOVB x4 MOV MOV MOVB MOVB MOV MOV MOVB MOVB x5 DIS EINIT MOVBZ MOVBS WDT x6 CMPM CMPI2 CMPD1 CMPD2 SCXT SCXT MOV MOV x7 IDLE PWRDN SRV SRST EXTP S MOVB MOVB WDT R x8 MOV MOV MOV MOV MOV MOV MOV x9 MOVB I MOVB MOVB MOVB MOVB MOVB MOVB l xA JB JNB JBC JNBS CALLA CALLS JMPA JMPS xB TRAP CALLI CALLR RET RETS RETP RETI xC JMPI ASHR ASHR NOP EXTP S PUSH POP R xD JMPR JMPR JMPR JMPR JMPR JMPR JMPR JMPR xE BCLR BCLR BCLR BCLR BCLR BCLR BCLR BCLR xF BSET BSET BSET BSET BSET BSET BSET BSET User s Manual 5 2 V 1 6 2001 08 pae 1 fi User s Manual a C166S V1 SubSystem Instruction Set 5 2 Instruction Set Summary This chapter summarizes the instructions by listing them according to their functional class This allows to identify the right instruction s for a specific required function The following notes apply to this summary Data Addressing Modes Rw Word GPR RO R1 R15 Rb Byte GPR R
442. tem Memory Organization 4 4 External Memory Space The C166S CPU can use an address space of up to 16 MBytes Only parts of this address space are occupied by the internal LM DPRAM and the IO SFR area All addresses not used for this kind of on chip memory or for registers may reference external memory locations This external memory space is accessed via the Bus Controller BC The BC is the bus bridge between the C166S CPU and the external internal bus interfaces The external bus interface allows access to external off chip peripherals and additional off chip volatile and non volatile memories The external bus interface may further limit the amount of addressable off chip memory The internal bus interface provides an internal system bus that allows the on chip integration of customer specific peripherals volatile and non volatile memories The availability of the internal and external bus interfaces depends on the functionality of the integrated BC 4 4 1 External data accesses External word and byte data can be accessed only via indirect or long 16 bit addressing modes using one of the four DPP registers There is no short addressing mode for external operands Any word data access is made to an even byte address and double word accesses to modulo 4 byte addresses even word address External memory is not provided for single bit storage and therefore it is not bit addressable User s Manual 4 8 V 1 6 2001 08
443. terrupt nodes request flags xxIC xxIR The ISR has to check the request flags and to clear them before executing the RETI instruction It is recommended that you clear an interrupt request flag CxIR before setting the respective enable flag CxIE Otherwise pending former requests will immediately trigger an interrupt request after setting the enable bit User s Manual 3 45 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 5 Using General Purpose Registers The C166S uses several banks of 16 dedicated General Purpose Registers GPRs RO R1 R2 R15 that can be accessed in one CPU cycle The GPRs are the working registers of the Arithmetic and Logic Units ALU and may also serve as address pointers in indirect addressing modes Several banks of GPRs are memory mapped The banks of these GPRs are located in the DPRAM One bank uses a block of 16 consecutive words A Context Pointer CP register determines the base address of the currently selected bank The C166S can switch the complete GPR bank with a single instruction for time critical tasks After switching the new task is executed within its own separate context Internal DPRAM CP 30 CP 28 15 16 Bit Context Pointer Figure 3 6 Register Bank Selection via Register CP There are 3 different ways to access the GPRs Short 4 bit GPR addresses mnemonic Rw or Rb specify an address relative t
444. the data both use PORTO The address is time multiplexed with the data and has to be latched externally The width of the required latch depends on the selected data bus width For example an 8 bit data bus requires a byte latch the address bits A15 A8 on POH do not change while POL multiplexes address and data a 16 bit data bus requires a word latch the least significant address line AO is not relevant for word accesses The upper segment address lines An A16 are permanently output on Port 4 if segmentation is enabled and do not require latches The EBC initiates an external access by generating the Address Latch Enable ALE signal and then placing an address on the bus The falling edge of ALE triggers an external latch to capture the address After a period of time during which the address must have been latched externally the address is removed from the bus The EBC now activates the appropriate command signal RD WR WRL WRH Data is driven onto the bus either by the EBC for write cycles or by the external memory peripheral for read cycles After a period of time that is determined by the access time of the memory peripheral data become valid Read cycles Input data is latched and the command signal is now deactivated This causes the accessed device to remove its data from the bus which is then tri stated again Write cycles The command signal is now deactivated The data remain valid on the bus until the next
445. the registers to the original register bank Note Resources that are used by the interrupting program must eventually be saved Pointers DPP and the registers of the multiply and divide unit Note The first instruction following the SCXT CP instruction must not use a GPR User s Manual 3 25 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 4 5 Traps 3 4 5 1 Software Traps The TRAP instruction is used to cause a software call to an ISR The trap number that is specified in the operand field of the trap instruction determines which vector location of the vector table will be used The TRAP instruction s effect is similar to that of an interrupt request that uses the same vector PSW CSP in segmentation mode and IP are pushed into the system stack and then a jump is taken to the specified vector location When a software trap is executed the CSP for the trap service routine is loaded with segment address 0 No Interrupt Request flags are affected by the TRAP instruction The ISR called by a TRAP instruction must be terminated with a RETI instruction to ensure correct operation Note The CPU priority level is not modified by the TRAP instruction so the service routine is executed with the same priority level as the interrupt task Therefore the service routine entered by the TRAP instruction can be interrupted by other traps or by higher priority interrupts other
446. the word specified by QQ Z 4 bit position of the destination bit within the word specified by ZZ 4 bit immediate constant data4 t tttO 7 bit trap number trap7 QQ 8 bit word address of the source bit bitoff rr 8 bit relative target address word offset rel HR 8 bit word address reg ZZ 8 bit word address of the destination bit bitoff HH 8 bit immediate constant data8 hoc 8 bitimmediate constant represented by data16 byte xx is not significant 8 bit immediate constant mask8 MMMM 16 bit address mem or caddr low byte high byte 16 bit immediate constant data16 low byte high byte Number of Bytes All C166S instructions are either 2 or 4 bytes According to the instruction size all instructions can be classified as either single word or double word instructions User s Manual 5 26 V 1 6 2001 08 1 fi User s Manual a C166S V1 SubSystem Instruction Set Representation in the N2N1 N4N3 N6N5 N8N7 Assembler Listing Kal Y Ml High Byte 2nd word Low Byte 2nd word High Byte 1st word Low Byte 1st word Internal Organization MSB 44 Bits in ascending order LSB AAA Figure 5 1 Instruction Format Representation The following pages of this section contain a detailed description of each instruction in alphabetical order User s Manual 5 27 V 1 6 2001 08 1 fi User s Manual SUE NN C166S V1 SubSystem Instruction Set
447. to the shared resources and demands this by activating its BREQ output The arbitration logic may then deactivate the other master s HLDA and so free the external bus for the C166S depending on the priority of the different masters Note The Hold State is not terminated by clearing bit HLDEN Other Signals MCD02236 Figure 8 13 External Bus Arbitration Regaining the Bus Note The falling BREQ edge indicates the last chance for BREQ to trigger the regain sequence Even if BREQ is activated earlier the regain sequence is initiated by HOLD going high BREQ and HOLD are connected via an external arbitration circuitry HOLD may also be deactivated without the C166S requesting the bus 8 7 The XBUS Interface The C166S provides an on chip interface the XBUS interface by which integrated customer application specific peripherals can be connected to the standard controller core The XBUS is an internal representation of the external bus interface i e it is operated in the same way For each peripheral on the XBUS X Peripheral there is a separate address window controlled by a register pair XBCONx XADRSx similar to registers BUSCONx and ADDRSELx Because an interface to a peripheral is represented in many cases by just a few registers most of the XADDRSEL registers select smaller address windows than User s Manual 8 35 V 1 6 2001 08 e Infineon technologies the standard ADDRSEL registers As t
448. trol Registers Interrupt Control E CAPREL T6CON T5CON Timer 5 Control Register T5 Timer 5 Register T6CON Timer 6 Control Register T6 Timer 6 Register CAPREL Capture Reload Register T5IC Timer 5 Interrupt Control Register T6IC Timer 6 Interrupt Control Register CRIC Caprel Interrupt Control Register Figure 12 16 SFRs associated with Timer Block GPT2 All GPT2 registers are located in the SFR ESFR memory space The respective SFR addresses can be found in list of SFRs User s Manual 12 26 V 1 6 2001 08 technologies User s Manual C166S V1 SubSystem Prescaler T5 Mode Control GPT2 Timer T5 Clear General Purpose Timer Unit gt T5IRQ Capture GPT2 CAPREL CRIRQ GPT2 Timer T6 T6 Prescaler Mode Control Figure 12 17 Structure of Timer Block 2 User s Manual 12 27 gt TEIRQ TSOE T6OFL MCB03999 b V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit 12 3 1 Core Timer T6 The operation of the core Timer T6 is controlled by its bitaddressable control register T6CON m 6 Reset value 0000p 15 14 13 12 11 fo 9 8 7 6 5 4 3 2 1 0 T6 rwh T6CON Timer 6 Control Register Reset value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T6 T6 T6 T6 T6 T6
449. truction e External Memory Access Sequences The effect described here will only become noticeable when watching the external memory access sequences on the external bus e g by means of a logic analyzer Different pipeline stages can simultaneously put a request on the External Bus Controller EBC The sequence of instructions processed by the CPU may diverge from the sequence of the corresponding external memory accesses performed by the EBC due to the predefined priority of external memory accesses 1 Write data 2 Fetch code 3 Read data User s Manual 3 84 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit e Initialization of Port Pins Modifications of the direction of port pins input or output become effective only after the instruction following the modifying instruction As bit instructions BSET BCLR use internal read modify write sequences accessing the whole port instructions modifying the port direction should be followed by an instruction that does not access the same port see example below PORT INIT WRONG BSET DP3 13 change direction of P3 13 to output BSET P3 9 P3 13 is still input rd mod wr reads pin P3 13 PORT INIT RIGHT BSET DP3 13 change direction of P3 13 to output NOP any instruction not accessing port 3 BSET P3 9 P3 13 is now output rd mod wr reads P3 13 s output latch e Changin
450. ture Mode 12 24 Timer 2 Control Register 12 16 Timer 2 Counter Mode 12 20 Timer 2 Gated Mode 12 19 Timer 2 Incremental Interface 12 25 Timer 2 Reload Mode 12 22 Timer 2 Timer Mode 12 19 Timer 3 Control Register 12 6 Timer 3 Counter Mode 12 11 Timer 3 Gated Timer Mode 12 10 Timer 3 Incremental Interface 12 12 Timer 3 Timer Mode 12 9 Timer 4 Capture Mode 12 24 Timer 4 Control Register 12 16 Timer 4 Counter Mode 12 20 Timer 4 Gated Mode 12 19 Timer 4 Incremental Interface 12 25 Timer 4 Reload Mode 12 22 Timer 4 Timer Mode 12 19 Timer 5 12 34 Timer 5 Control Register 12 34 Timer 5 Counter Mode 12 37 Timer 5 Gated Mode 12 36 Timer 5 Timer Mode 12 36 Timer 6 Core Timer 6 12 28 Timer 6 Control Register 12 28 User s Manual Keyword Index Timer 6 Counter Mode 12 33 Timer 6 Gated Mode 12 32 Timer 6 Timer Mode 12 31 Timer Block 1 12 3 Timer Block 2 12 26 Timer T3 12 5 Timer4 12 16 Tools 1 5 Trap Number 4 43 4 48 Traps 3 28 Tristate Time 8 17 V Vector Location 4 43 4 48 W Waitstate Memory Cycle 8 17 Tristate 8 17 Watchdog Timer 2 13 WDT 2 13 WDTCON 9 3 WDTREL 2 14 X XADRS 8 37 XBCON 8 38 XBUS 8 35 enable peripherals 8 36 Z ZEROS Register 3 89 14 4 V 1 6 2001 08 Infineon goes for Business Excellence Business excellence means intelligent approaches and clearly defined processes which are both constantly under review and ultimately lead to good operating results Better operating results and bus
451. ty They can be configured for Timer Mode Gated Timer Mode Counter Mode or Incremental Interface Mode with the same options for the timer frequencies and the count signal as the core Timer T3 In addition to these 4 counting modes the auxiliary timers can be concatenated with the core timer or they may be used as reload or capture registers in conjunction with the core timer The individual configurations for Timers T2 and T4 are determined by their bitaddressable control registers T2CON and T4CON which are organized identically Note that functions which are present in all 3 timers of Timer Block 1 are controlled in the same bit positions and manner in each of the specific control registers Run control for auxiliary timers T2 and T4 can be handled by the associated run control bit T2R T4R in register T2CON T4CON Alternatively a remote control option T2RC T4RC set may be enabled to start and stop T2 T4 via the run bit T3R of core Timer T3 User s Manual 12 18 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem General Purpose Timer Unit Timers T2 and T4 in Timer Mode or Gated Timer Mode When the auxiliary Timers T2 and T4 are programmed to Timer Mode or Gated Timer Mode their operation is the same as described for the core Timer T3 The descriptions figures and tables apply accordingly with two exceptions e There is no TxOUT output line for T2 and T4 e Overflow underflow monitoring is not
452. uire access to its external bus during hold mode it activates its bus request output BREQ to notify the arbitration circuitry BREQ is activated only during hold mode It will be inactive during normal operation Other Signals jj MCT02238 Figure 8 12 External Bus Arbitration Releasing the Bus Note The C166S will complete the bus cycle that is currently running before granting bus access as indicated by the broken lines in Figure 8 12 This may delay hold acknowledge compared to this figure The Figure 8 12 shows the first possibility for BREQ to go active During bus hold pin P3 12 is switched back to its standard function and is then controlled by DP3 12 and P3 12 DP3 12 should be cleared and held at 0 to ensure floating in hold mode Exiting the Hold State The external bus master returns the access rights to the C166S by driving the HOLD input high After synchronizing this signal the C166S will drive the HLDA output high actively drive the control signals and resume executing external bus cycles if required Depending on the arbitration logic the external bus can be returned to the C166S under two circumstances The external master no longer requires access to the shared resources and gives up its own access rights or User s Manual 8 34 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem The External Bus Interface e the C166S needs access
453. ular stack For all system stack operations the stack memory is accessed via the Stack Pointer SP The system stack implementation in the C166S is from high to low memory The system stack grows downward as it is filled The SP register is decremented first each time data is pushed on the system stack and incremented after each time the data is pulled from the system stack Only word accesses are supported to the system stack The SP points to the address of the latest system stack entry rather than to the next available system stack address A STacK OVerflow STKOV register and a STacK UNderflow STKUN register are provided to control the lower and upper limits of the selected stack area These two stack boundary registers can be used not only for protection against data destruction but also to implement a circular stack with hardware supported system stack flushing and filling except for option STKSZ 1 11 4 6 1 Data Organization in General Purpose Registers The memory mapped GPRs use a block of 16 consecutive words within the DPRAM Segment 0 The Context Pointer CP register determines the base address of the currently active register bank This register bank may consist of up to 16 word GPRs RO R1 R15 and or up to 16 byte GPRs RLO RHO RL7 RH7 The 16 byte GPRs are mapped onto the first 8 word GPRs see table below In contrast to the system stack a register bank grows from lower towards higher addr
454. ulation Instructions Syntax BCLR op1 Source Operand s none Destination Operand s op1 gt BIT Operation opt 0 Description Clears the bit specified by op1 This instruction is primarily used for peripheral and system control CPU Flags E Z V C N E Always cleared Z Contains the logical negation of the previous state of the specified bit V Always cleared C Always cleared N Contains the previous state of the specified bit Encoding Mnemonic Format Bytes BCLR bitaddro q qE QQ 2 User s Manual 6 12 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set BCMP Bit to Bit Compare BCMP Group Boolean Bit Manipulation Instructions Syntax BCMP op1 op2 Source Operand s op1 op2 gt BIT Destination Operand s none Operation op1 op2 Description Performs a single bit comparison of the source bit specified by op1 and the source bit specified by op2 No result is written by this instruction Only the flags are updated CPU Flags E Z V C N o non oR anD xon E Always cleared Z Contains the logical NOR of the two specified bits V Contains the logical OR of the two specified bits C Contains the logical AND of the two specified bits N Contains the logical XOR of the two specified bits Encoding Mnemonic Format Bytes BCMP bitaddrz z bitaddro q 2A QQ ZZ qz 4 User s Manual 6 13 V 1 6 2001 08 1 fi User s Manual nrineon
455. un time to access instructions The lower 8 bits of register CSP select one of up 256 segments of 64 KBytes each while the higher 8 bits are reserved for future use CSP Code Segment Pointer SFR FE084 04p Reset value 000x 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 SEGNR r r r r r r r r r w h 1 The reset value of the bitfield segnr 1 0 is product specific With an alternate boot mode feature the code execution can be started at different segments after reset Field Bits Type Description SEGNR 7 0 rwh _ Specifies the code segment from which the current instruction is to be fetched User s Manual 3 15 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit The actual code memory address is generated by direct extension of the 16 bit contents of the IP register by the lower byte of the CSP register as shown in Figure 3 2 There are two modes Segmented and non segmented The mode is selected with the SGTDIS bit in the SYSCON register After reset the segmented mode is selected SYSCON System Control Register SFR FF12y 894 Reset value 0xx0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SGT DIS rw Field Bits Type Description SGTDIS 11 rw Segmentation Disable Enable Control 0 Segmentation enabled CSP is saved restored during
456. use this combination 111g 1024 00 FDFEy 00 FX00y Note No circular stack SP 11 SP 0 00 FX00y represents the lower DPRAM limit i e 1 KB 00 FA00 2 KB 00 F600y 3 KB 00 F200y User s Manual 3 65 V 1 6 2001 08 e Infineon technologies User s Manual C166S V1 SubSystem Central Processing Unit The virtual stack addresses are transformed to physical stack addresses by concatenating the significant bits of SP see table Table 3 15 with the complementary most significant bits of the upper limit of the physical stack area 00 FBFE This transformation is done via hardware see figure Figure 3 11 The reset values STKOV FAO00y STKUN FCO0y SPZFC00 STKSZ 000p map the virtual stack area directly to the physical stack area and allow using the internal system stack without any changes provided that the 256 word area is not exceeded 1111 1011 1411 1110 1111 1011 1111 1110 1111 1011 1000 0000 Phys A 1111 1010 0000 0000 1111 1011 10000000 1111 1000 0000 0000 After PUSH After PUSH 1111 1011 1111 1110 1111 101 1111 1011 1111 1110 Phys A 1111 1011 1111 1110 EEEEEZENES 11 1110 lt SP gt 1111011111111110 64 words Stack Size 256 words Figure 3 11 Physical Stack Address Generation The following example demonstrates the circular stack mechanism that is also an effect of this virtual stack mapping First register R1 is pushed onto the lowest physical stack location according to
457. used Special attention has to be paid when writing to external SFRs such as peripheral control registers which have effect over the system behavior for example enabling disabling transfer interrupts etc To assure that the critical write operation has been completed before making use of it it is recommended next to make a read operation on the same memory location The reasons are e the CPU will recognize the need of holding pipeline while the write operation is completed e as reading from the same location execution time scales in respect to bus speed So there is no need to think about how fast that bus is and one instruction is enough in all cases to assure effectiveness of that write for the next instructions User s Manual 3 86 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit 3 8 2 Instruction State Times Instruction pipelining usually reduces the average instruction processing time typically within a range of 1 4 machine cycles However there are some rare cases where a particular pipeline situation causes the processing time for a single instruction to be extended either by a half or by one machine cycle Although this additional time represents only a tiny part of the total program execution time it might be of interest to avoid these pipeline caused time delays in time critical program modules The time to execute an instruction depends on where the
458. value of the popped word represents the lowest possible negative number Cleared otherwise Used to signal the end of a table Z Set if the value of the popped word equals zero Cleared otherwise V Not affected C Not affected N Set if the most significant bit of the popped word is set Cleared otherwise Encoding Mnemonic Format Bytes RETP reg EB RR 2 User s Manual 6 79 V 1 6 2001 08 pae 1 fi User s Manual UE NN C166S V1 SubSystem Detailed Instruction Set RETS Return from Inter Segment Subroutine RETS Group Return Instructions Syntax RETS Source Operand s none Destination Operand s none Operation Description Returns from an inter segment subroutine The IP and CSP are popped from the system stack CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes RETS DB 00 2 User s Manual 6 80 V 1 6 2001 08 1 fi User s Manual nrineon M a C166S V1 SubSystem Detailed Instruction Set ROL Rotate Left ROL Group Shift and Rotate Instructions Syntax ROL op1 op2 Source Operand s op1 gt WORD op2 gt shift counter Destination Operand s op1 gt WORD Operation count op2 C 0 DO WHILE count z 0 C op1 15 op1 n op1 n 1 n215 1 op1 0 C count lt count 1 END WHILE Description Rotates the destination word operand op1 the number of times
459. vided that the jump condition is met the jump target instruction is fetched as usual causing a time delay of one machine cycle In contrast to standard branch instructions however the target instruction of a cache jump instruction JMPA JMPR JB JBC JNB JNBS is additionally stored in the cache after having been fetched After each subsequent execution of the same cache jump instruction the jump target instruction is not fetched from program memory but taken from the cache and immediately injected into the fetch decode stage of the pipeline see table below Table 3 5 A time saving jump on cache is always taken after the second and any subsequent occurrences of the same cache jump instruction unless an instruction that has the fundamental capability of changing the CSP register contents JMPS CALLS RETS TRAP RETI or any standard interrupt has been processed during the period of time between two following occurrences of the same cache jump instruction Table 3 5 shows a standard unconditional branch branch taken and target cached instruction pipeline assuming a fast local memory 0 1 waitstates Table 3 5 Unconditional cached branches LM Bus 0 1 waitstate Clock Cycle T4 To T4 To Ty To T4 To T4 To Ty To LM Address la tet LM Data 32bit la tet la t4 FETCH In In 1 lt la l2 lta branch DECODE In i In In 1 It l4 lua branch EXECU
460. wh Field Bits Type Description MDL 15 0 wh Low part of MD The low order 16 bits of the 32 bit multiply and divide register MD Whenever this register is updated via software the MDRIU flag in the MDC register is set to 1 The MDRIU flag is cleared whenever the MDL register is read via software When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the ISR the contents of MDL must be saved along with the contents of registers MDH and MDC to avoid erroneous results The Multiply Divide Control Register MDC The bit addressable 16 bit Multiply Divide Control register is implicitly used by the CPU when it performs a multiplication or a division It is used to store the required control information for the corresponding multiply or divide operation MDC is updated by hardware during each single cycle of a multiply or divide instruction Mur nivona Control SFR FF0E 874 Reset value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ofo o o ojo o o mu MP un on non r r r r r r r r rwh rwh rwh rwh rwh rwh rwh rwh User s Manual 3 73 V 1 6 2001 08 pae 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit Field Bits Type Description MDRIU 4 rwh Multiply Divide Register In Use O Cleared when register MDL is read via software 1
461. when the incoming data at pin MRST Master Mode or MTSR Slave Mode sampled with the same frequency as the module clock changes between one cycle before and two cycles after the latching edge of the shift clock signal SCLK This condition sets the error flag CON PE and when enabled via CON PEN the error interrupt request line EIR A Baudrate Error Slave Mode is detected when the incoming clock signal deviates from the programmed baudrate by more than 100 i e it either is more than double or less than half the expected baudrate This condition sets the error flag CON BE and when enabled via CON BEN the error interrupt request line EIR Using this error detection capability requires that the slave s baudrate generator is programmed to the same baudrate as the master device This feature detects false additional or missing pulses on the clock line within a certain frame Note If this error condition occurs and bit CON REN 1 an automatic reset of the SSC will be performed in case of this error This is done to re initialize the SSC if too few or too many clock pulses have been detected A Transmit Error Slave Mode is detected when a transfer was initiated by the master SS CLK gets active but the transmit buffer TB of the slave was not updated since the last transfer This condition sets the error flag CON TE and when enabled via CON TEN the error interrupt request line EIR If a transfer starts while the transmit buffer is not upd
462. witching support 16 MBytes linear address space for code and data von Neumann architecture System stack cache support with automatic stack overflow underflow detection Control Oriented Instruction Set with High Efficiency Bit byte and word data types Flexible and efficient addressing modes for high code density Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral control and user defined flags Hardware traps to identify exception conditions during runtime HLL support for semaphore operations and efficient data access External Bus Interface Multiplexed or demultiplexed bus configurations Segmentation capability and chip slect signal generation 8 bit or 16 bit data bus e Bus cycle characteristics selectable for five programmable address areas 16 Priority Level Interrupt System Upto 112 interrupt nodes with separate interrupt vectors 16 priority levels and 4 8 group levels Up to 16 Channel Peripheral Event Controller PEC Interrupt driven single cycle data transfer Transfer count option std CPU interrupt after programmable number of PEC transfers Long Transfer Counter Channel Linking Eliminates overhead of saving and restoring system state for interrupt requests User s Manual 1 3 V 1 6 2001 08 1 fi User s Manual SUE NN C166S V1 SubSystem Introduction Intelligent On chip Peripherals General Purpose Timer Unit Timer Bl
463. write to GPR 0 in the new context e Data Page Pointer Updating An instruction that calculates a physical operand address via a particular DPPn n 0 to n 3 register is not capable of using a new DPPn register value that is to be updated by the preceding instruction Thus to make sure that the new DPPn register value is used at least one instruction must be inserted between a DPPn changing instruction and a subsequent instruction that implicitly uses DPPn via a long or indirect addressing mode as shown in the following example La MOV DPPO 4 select data page 4 via DPPO Toup ies must not be an instruction using DPPO In z MOV DPP0 0000H R1 move contents of R1 to address location 01 00004 in data page 4 supposed segment is enabled User s Manual 3 82 V 1 6 2001 08 User s Manual C166S V1 SubSystem Central Processing Unit technologies e Explicit Stack Pointer Updating Neither the RET nor POP instruction is capable of correctly using a new SP register value which is to be updated by an immediately preceding instruction Thus in order to use the new SP register value without erroneously performed stack accesses at least One instruction must be inserted between an instruction that explicitly writes to SP and any of the afore mentioned subsequent instructions that implicitly use the SP as shown in the following example Lg MOV SP 40FAA40H select a new top of stack beti Less must not be an instructi
464. xecution continues normally with the instruction following the JMPR instruction CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes JMPR cc rel cD rr 2 User s Manual 6 54 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set JMPS Absolute Inter Segment Jump JMPS Group Jump Instructions Syntax JMPS op1 op2 Source Operand s op1 segment number op2 gt 16 bit address offset Destination Operand s none Operation CSP lt op1 IP op2 Description Branches unconditionally to the absolute address specified by op2 within the segment specified by op1 CPU Flags E Z V C N E Not affected F4 Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes JMPS seg caddr FA SS MM MM 4 User s Manual 6 55 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set JNB Relative Jump if Bit Clear JNB Group Jump Instructions Syntax JNB op1 op2 Source Operand s op1 gt BIT op2 gt 8 bit signed displacement Destination Operand s none Operation IF op1 0 THEN IP IP 2 sign_extend op2 ELSE Next Instruction END IF Description If the bit specified by op1 is clear program execution continues at the location of the instruction pointer IP plus the specified
465. xiliary Timer T4 TAI Figure 12 14 GPT1 Timer Reload Configuration for PWM Generation MCB02037_b Note Line is affected by over underflow of T3 only NOT by software modifications of T3OTL Note It should be avoided to select the same reload trigger event for both auxiliary timers In this case both reload registers would try to load the core timer at the same time If this combination is selected T2 is disregarded and the contents of T4 is reloaded Auxiliary Timer in Capture Mode Capture Mode for the auxiliary Timers T2 and T4 is selected by setting bitfield TxM in the respective register TXCON to 101g In Capture Mode the contents of the core timer are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer s external input line TxIN The capture trigger signal can be a positive a negative or both a positive and a negative transition The two Least Significant Bits of bitfield Txl are used to select the active transition see Table 12 8 while the most significant bit Txl 2 is irrelevant for Capture Mode It is recommended to keep this bit cleared Txl 2 0 Note When programmed for Capture Mode the respective auxiliary Timer T2 or T4 stops independently of its run flag T2R or T4R User s Manual 12 24 V 1 6 2001 08 1 fi User s Manual nrineon technologies C1 66S V1 SubSystem General Purpose Timer Unit
466. xt 1 to 4 instructions being executed after the ATOMIC instruction All instructions requiring multiple cycles or hold states to be executed are regarded as one instruction in this sense Any instruction type can be used with the ATOMIC instruction CPU Flags E Z V C N E Not affected Z Not affected V Not affected C Not affected N Not affected Encoding Mnemonic Format Bytes ATOMIC irang2 D1 00 0 2 User s Manual 6 10 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set BAND Bit Logical AND BAND Group Boolean Bit Manipulation Instructions Syntax BAND op1 op2 Source Operand s op1 op2 gt BIT Destination Operand s op1 gt BIT Operation op1 lt op1 op2 Description Performs a single bit logical AND of the source bit specified by op2 and the destination bit specified by op1 The result is then stored in op1 CPU Flags E Z V C N o non oR anD xon E Always cleared Z Contains the logical NOR of the two specified bits V Contains the logical OR of the two specified bits C Contains the logical AND of the two specified bits N Contains the logical XOR of the two specified bits Encoding Mnemonic Format Bytes BAND bitaddrz z bitaddra y 6A QQ ZZ qz 4 User s Manual 6 11 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Detailed Instruction Set BCLR Bit Clear BCLR Group Boolean Bit Manip
467. y the double frequency of the CPU Watchdog Timer WDT The watchdog timer represents one of the fail safe mechanisms which have been implemented to prevent the controller from malfunctioning However the watchdog timer can only detect long term malfunctioning The watchdog timer is enabled automatically by setting its enable control line It is recommended that any product enables the watchdog timer after internal chip initialization The watchdog timer can only be disabled by software in the time interval until the EINIT end of initialization instruction has been executed Thus the application startup code is always monitored The software has to be designed to service the watchdog timer before it overflows If due to hardware or software related failures the software fails to do so the watchdog timer overflows and generates either an internal subsystem reset which is indicated on the subsystem boundary general signals interface for further product related actions or triggers an interrupt Which action will be triggered depends on a new control bit within the WDTCON register User s Manual 2 13 V 1 6 2001 08 pae 1 fi User s Manual neon Infineon C1 66S V1 SubSystem System Overview The Watchdog Timer is a 16 bit timer which counts the PDBUS clock divided either by 2 4 128 or 256 The high byte of the Watchdog Timer register can be set to a predefined reload value stored in WDTREL in order to allow further variat
468. y the lower 4bits of reg are significant for physical address generation and therefore the address calculation is identical to the address generation proc ess described for the Rb and Rw addressing modes Specifies direct access to any word in the bit addressable memory space The bitoff value requires 8 bits in the instruction format Depending on the speci fied bitoff range different base addresses are used to generate physical addresses Short bitoff addresses in the range from 00 to 7Fy use 00 FDOO as a base address to specify the 128 highest DPRAM word locations in the range from 00 FDOOyh to 00 FDFEy Short bitoff addresses in the range from 80y to EF use base address 00 FF00 to specify the internal SFR word loca tions in the range from 00 FFOOy to 00 FFDE or base address 00 F100 to specify the internal ESFR word locations in the range from 00 F100y to 00 F1DEy The bitoff accesses to the ESFR area require a preceding EXT R instruction to switch the base address For short bitoff addresses from FO to FF only the lowest four bits are used to generate the address of the selected word GPR Any bit address is specified by a word address within the bit addressable memory space see bitoff and by a bit position bitpos within that word Therefore bitaddr requires 12 bits in the instruction format User s Manual 3 53 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem Central Processing Unit
469. y the peripheral the software write operation has priority 2 2 3 1 Asynchronous Synchronous Serial Channel ASCO Serial communication with other microcontrollers processors terminals or external peripheral components is provided by a Asynchronous Synchronous Serial Channel The ASCO supports full duplex asynchronous communication up to 3 125 MBaud and half duplex synchronous communication up to 6 25 MBaud referred to a PDBUS clock of 50 MHZ A versatile baud rate generator allows to set up all standard baud rates without subsystem clock tuning For transmission reception and erroneous reception three separate interrupt requests are provided In asynchronous mode 8 or 9 bit data frames are transmitted or received preceded by a start bit and terminated by one or two stop bits For multiprocessor communication a mechanism to distinguish address from data bytes has been included 8 bit data wake up bit mode User s Manual 2 9 V 1 6 2001 08 1 fi User s Manual n Infineon C1 66S V1 SubSystem System Overview In synchronous mode the ASCO transmits or receives bytes 8 bits synchronously to a shift clock which is generated by the ASCO A loop back option is available for testing purposes A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers A parity bit can automatically be generated on transmission or be checked on reception Fram

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