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TLL5000 User Manual

1. User design Make sure that the Write Protect WP bit is not set 23 Verify that the Operating Mode is set to Slave and the I O Configuration is set to Parallel Mode as shown in Figure 2 10 24 Click on OK to begin programming the PROM 2 3 Using the SDRAM The TLL5000 board is equipped with a single 16Mb SDRAM IC Micron MT48LC4M32B2P which is connected directly to Bank 3 of the FPGA FPGA to SDRAM connection list is shown in Table 2 2 Table 2 2 SDRAM to FPGA connection BALL Name Signal Name BALL Name Signal Name RAM_1028 P25 RAMI01 DQO V24 RAM_IO29 RAM_1030 RAM_1031 U20 4 3 2 0 0 6 5 RAM_1036 Q27 RAM_1037 Q26 U W RAM_1035 11 W W Copyright 2008 The Learning Labs Inc UM 19 R24 RAM I010 DQ11 RAM_IO11 RAM 1012 DQ10 S M_I013 DQ5 S D M_1014 L i M_1016 M_1017 M_IO15 SISS S TLL5000 v1 1 documentation User Manual M_1039 QM2 26 M_1040 5 M_1041 10 M_1042 3 1 0 M_1043 26 M_1044 Q16 M_1045 2 SS S AE 25 S M_1046 M_104 M_1048 M_1049 Q23 M_IO50 Q19 M_IO51 M_1052 M_1018 M 1019 DQMO S S M_1020 M_1021 3 SiS SiS M_1023 DQ8 M 1025 DQM1 20 M_1053 M_1026 C26 M_1054 a C25 C The memory has 1 Meg x 32 x 4 banks It uses 12 address lines A0 A11 for row addressing and 8 address lines A0 A7 for column addressing It has 4 banks maximum operating frequency of 143MHz and CAS latency CL 3 A gene
2. it im tg PS2 Mouse and Keyboard port Ethernet and FPGA USB ports AC97 audio ports 1 2 3 Spartans FPGA XSGA Video and RS232 ports Dual SVHS video port Dual composite video port Component video input port Component video output port U1 is a Xilinx Spartan3 XC3S1500 FPGA device packed in 676 lead fine pitch ball grid array package All XC3S1500 key features can be seen in Table 1 1 Copyright 2008 The Learning Labs Inc UM 8 TLL5000 v1 1 documentation User Manual Table 1 1 XC3S1500 Features Feature Value Equivalent Logic Cells 29952 Distributed RAM 208 Kbits Block RAM 576 Kbits 1 2 4 ARM Housekeeping Processor ARM Housekeeping processor takes care of power up sequencing and monitoring of the supply regulators It also sets up and manages communications with host computer via high USB connection 1 2 5 Power Supplies The TLL5000 Development System is powered from a DC 18Volt 3 5Amp regulated power supply On board switching power supplies generate 5V 3 3V 2 5V 1 8V and 1 2V for the FPGA and peripheral components ARM housekeeping processor is powered all the time and it has control over power distribution to the rest of the board All generated voltage levels are constantly monitored by the housekeeping processor 1 2 6 FPGA Configuration FPGA can be programmed directly using the JTAG chain or indirectly using the onboard Platform Flash T
3. Figure 1 1 TLL5000 Development System Block Diagram Internal Power 12V 10 Supplies tp AC97 Audio CODEC amp Stereo Amp 3 ae a XSGA Video Output q Video Decoder q Video Encoder ARM gt Housekeeping a gt lt lt SD MMC Card slot processor 2 User LEDs 8 CR User Switches 8 p ea User Push button Switches 5 ie 100 MHz Clock amp lt p 10 100 Ethernet PHY Oscillator Divider ee gt lt _ gt RS 232 amp PS 2 Ports 2 D gt eae ee lt _ 16MB SDRAM Zz Oscillator i gt 16MB FLASH gt 16x2 LCD Display Platform Flash Configurations 4 p Mezzanine board connectors 2 Test points Copyright 2008 The Learning Labs Inc UM 7 TLL5000 vi 1 documentation User Manual 1 2 2 Board Components This section contains a concise overview of several important components on the TLL5000 Development System see Figure 1 2 Figure 1 2 TLL5000 Development System Board Photo Housekeeping processor USB port ARM JTAG een port connector SD MMC card slot Power connector Sa ME FO qlee i Men SREY SEL Air EE TTTTTTVTTTTTTTTT mY T S i H copyright 2006 DIP Switches item la af O Ri a TU
4. AD1981BL characteristics include S PDIF output 20 bit data format supporting 48 kHz and 44 1 kHz sample rates Integrated stereo headphone amplifier Variable sample rate audio External audio power down control gt 90 dB dynamic range Stereo full duplex codec 20 bit PCM DAC 3 analog line level stereo inputs for line in AUX and CD Mono line level phone input Dual MIC input with built in programmable preamplifier High quality CD input with ground sense Mono output for speakerphone or internal speaker power management support Stereo MIC preamplifier support Built in digital equalizer function for optimized speaker sound Full duplex variable sample rates from 7040 Hz to 48 kHz with 1 Hz resolution Jack sense pins for automatic output switching Software programmed Veerout output for biasing microphone and external power amplifier Low power 3 3 V operation for analog and digital supplies Multiple codec configuration options The provided IP is a Xilinx IP enabling access to the registers of AD1981BL Additional software functions enable the user to record a 10sec long recording to the SDRAM memory and play it back through the headphones as well as set input and output gains Copyright 2008 The Learning Labs Inc UM 24 TLL5000 vi 1 documentation User Manual Table 2 7 AC97 codec connection with the FPGA BALL Name Name AC97_IO0 SDATA_IN AC97_IO1 BIT CLK AC97_IO2 SDATA_OUT AC97_IO3 ID_1 AC97_IO4 ID_0 AC97
5. _IO_B75 _IO_B76 _IO_B77 _IO_B78 _IO_B79 NIN CON902 64 CON902 66 NIN A12 N Copyright 2008 The Learning Labs Inc UM 30 TLL5000 vi 1 documentation User Manual 2 15 Enabling TLL5000 Board in the Base System Builder Wizard For enabling LL 5000 BoarD to be visible among the other boards such as the predefined Xilinx and other vendor boards its necessary to copy Board Definition File NIT _LL5000_v2_2 O xbd in the proper directory Generally the position of those files must be in board subdirectory of the EDK working folder Typical example is c EDK board Xilinx boards NIT_LL5000 data NIT_LL5000_ v2 2 O xbd That practically means that user first must create directory NIT_LL5000 in c EDK board xilinx boards The next step is to create data subfolder in NIT_LL5000 folder and finally xbd file from installation CD must be copied to it After completion of this procedure LL 5000 is prepared to be chosen from Base System Builder Wizard in which automated instantiation of board peripherals is enabled 3 Document history Date Version Author _ _ Remarks 23 10 2006 DM RTRK 03 11 2006 NP RTRK How to use xbd file explained 20 03 2007 1 2 DM RTRK Board layout and schematic connections updated to match board revision 1 1 06 01 2008 MR MM TLL Minor edits and correction of VGA signal out section Copyright 2008 The Learning Labs Inc UM 31
6. i mec FR f Conf gre Orien f Ergan Certa ri Fies D Lowd Ganfigunet on F ile cl pd a 2 Click on Next and select PROM File in the Prepare Configuration Files option menu shown in Figure 2 4 Copyright 2008 The Learning Labs Inc UM 14 TLL5000 vi 1 documentation User Manual Fi eles 2 4 Selecting oe me Da P p l m se fi L re or Configuration Files werd i ee 4 D Seen Scere E FAME i Benson F 3 Click on Next and then select Xilinx PROM with Design Revisioning Enabled using the MCS PROM File Format Figure 2 5 ce 2 a PROM with Design bone Enabled Prise PERLA His Lou ia Large C Sire Sew PACH Parois PA compis Diem PROM File Porn EME TER Le reat Ea FEN AN im i Mere Ayaan Hipi FF FRERE hans a DESIGH FROM Bart Nets Cei p 4 Give the PROM File a name of your choice in the location of your choice as shown in Figure 2 5 Note Do NOT select Compress Data because the TLL5000 development System hardware does not support this option Copyright 2008 The Learning Labs Inc UM 15 TLL5000 vi 1 documentation User Manual Fi qe 2 6 rue an Ras PROM with 3 Revisions ro ol rh eB CI fen ee 5 Click on Next to bring up the option screen where the type of PROM is specified 6 Select the XCF32P PROM from the drop down men Click on the Add button and specify 3 from the Number of Revisions drop down menu as shown
7. can drive 250 to 37 50 loads corresponding to a doubly terminated 500 to 75Q load The BLANK input overrides the RGB inputs and blanks the display output The provided FPGA IP enables reading the desired output pattern from a memory area inside the SDRAM and outputting it to the D Sub connector The connections with the FPGA are given in Table 2 4 Table 2 4 VGA DAC connections to FPGA Table 2 4 VGA DAC connections to FPGA FPGA Schematic Net Interface Signal BALL Name Name Wi VDAC_IO0 B1 V6 VDAC_IO1 SYNC U7 VDAC_I02 BLANK V5 VDAC_IO3 GO V4 VDAC_IO4 R6 V3 VDAC_IO5 R5 V2 VDAC_IO6 B2 U6 VDAC_IO7 G2 U5 VDAC_IO8 Gl U4 VDAC_IO9 R4 U3 VDAC_IO10 R3 U2 VDAC_IO11 B3 U1 VDAC_IO12 B4 T8 VDAC_IO13 G6 T7 VDAC_IO14 G7 T6 VDAC_IO15 G3 T5 VDAC_IO16 R1 T2 VDAC_IO17 B5 T1 VDAC_IO18 B6 Copyright 2008 The Learning Labs Inc UM 21 TLL5000 v1 1 documentation User Manual R8 VDAC_IO19 G5 R7 VDAC_IO20 R7 R6 VDAC_IO21 G4 R5 VDAC_IO22 PSAVE T4 VDAC_IO23 R2 R3 VDAC_IO24 RO R2 VDAC_IO25 B7 Ri VDAC_IO26 CLOCK P8 VDAC_IQ27 BO 2 6 Using the Video Encoder The board has an ADV7173 video encoder It is an integrated Digital Video Encoder that converts digital CCIR 601 4 2 2 8 bit component video data into a standard analog baseband television signal compatible with world wide standards There are six DACs available on the ADV7173 In addition to the Composite output signal there is the facility to output S VHS Y C Video RGB V
8. in Figure 2 6 7 Click on Next twice to bring up the Add Device File screen shown in Figure 2 7 Fi p lsi 2 7 Adding a device file LEET NEH E iel 5 Syrom ACE FROM Formattor i SWF STAFL XEWF 2j Risain j Sirtig Adimas fii SHa Coyir His ares a cbr dance Pis bei Acid Fis Eux _ Emea Help 8 Click on Add File and navigate to your design directory and select the bit file for your design as shown in Figure 2 8 Copyright 2008 The Learning Labs Inc UM 16 TLL5000 vi 1 documentation User Manual _ Figure 2 8 Adding the design file to revision O OG bl r EHE H a Ee amp tem ACE PROH Formattor svf STAPL ovr Ae Com F i E E LL KE Eee CH CUS Tix yobs Fa for ese le mA eE 9 Click on Open and answer No when prompted to add another design file to Revision 0 10 Note that Revision 0 is highlighted in green this is where the known configuration will be placed in the PROM By selecting your design file for Revision 0 you are just reserving space in the PROM for the known configuration If the design file was created with the Startup Clock set to JTAG iMPACT will issue a warning that the Startup Clock will be changed to CCLK in the bitstream programmed into the PROM This warning can be safely ignored 11 0nce you answer No when prompted to add another design file to Revision 0 the green revision highlight will move to Revision 1 You will be prompted
9. software or applications issues Any updates or patches will be sent to you automatically as long as your registration is current The TLL products are designed to be supported remotely by allowing viewing of the user s desktop It is highly recommended that the PC from which you are using TLL products is connected to an Internet link that allows Web browser access In this way our technical support staff can view your desktop and work with you to understand and solve technical issues Copyright 2008 The Learning Labs Inc UM 2 TLL5000 v1 1 documentation User Manual Table of Contents 1 3 TLL5000 Electronic System Design Base Module cccccecseceeeeeeeeeeeeseeeeeneaeeeesesansesaesenaes 6 kbe Pea ES gucanc aise ate natn gee atin Geta te Gps nan 6 L2 Ge n ral IDeSCrDEOM ss A tanins de nt eee 7 213 lt BIOCK DIAO AMIS Ses an nada meagan aan reed ene banni dance nr a 7 1 2 2 B ard COMPONCHNS Sanaa nae nee en Re nes crea on rene ea desde au 8 Eee Dalal eb GP En A 8 1 2 4 ARM Housekeeping Processor cscscscsccessesccrseseeneueceersesuesearerseseenessarsasesnensars 9 12 53 POWE SUDDIICS ccrois AE E 9 t26 FPGA GCOMTMGUrATION ESS RAR a Re ATA 9 kaa VSE RAM sraa a A ET A AOT Ra an 9 12 60 Sytem Fas ocene suka vate eines a E ones 9 L29 EEE INTel FAR cieie nr en chain tonte 9 1 2 10 Sella INCI AGES SR Rd balances O lens 10 12 11 User LEDs Switches and Push Buttons ss 10 1 2 12 VGA OUU
10. to add your design file to Revision 1 By selecting your design file for Revision 0 you are just reserving space in the PROM for the known configuration 12 Click on Open and answer No when prompted to add another design file to Revision 1 13 Once you answer No when prompted to add another design file to Revision 1 the green revision highlight will move to Revision 2 You will be prompted to add you design file to Revision 2 14 Click on Open and answer No when prompted to add another design file to Revision 1 Click on Finish to start the generation of the MCS 15 After IMPACT successfully creates the MCS file select Configuration Mode from the Mode menu 16 Make sure that TLL5000 is powered up and that a PC4 cable connects the board to the PC that is running the iMPACT software 17 Select the Initialize Chain command The iMPACT software then interrogates the system and reports that there are three devices in the JTAG chain The first device is the XCF32P PROM the second device is the CPLD and the third device is the Spartan 3 FPGA Copyright 2008 The Learning Labs Inc UM 17 TLL5000 vi 1 documentation User Manual 18 Select the MCS file that you created earlier as the configuration file for the XCF32P PROM and click Open as shown in Figure 7 19 Select BYPASS as the configuration files for the CPLD and the Spartan 3 FPGA 20 Right mouse click on the icon for the XCF32P PROM and select Program from the drop down me
11. 000 Board PROLO Re ad en etotee ctetde t te 8 Figure 2 1 TLL5000 Monitor Controller Initial Screen 12 Figure 2 2 TLL5000 Monitor Controller Power On Screen 13 Figure 2 3 Operation Mode Selection Prepare Configuration Files 14 Figure 2 4 Selecting PROM file cscccscsccsesesrevsersesenseucuseeneavrseceseenearsereeneusarsuseeuessarsasensenss 15 Figure 2 5 Selecting a PROM with Design Revisioning Enabled 15 Figure 2 6 Selecting an XCF32P PROM with 3 Revisions ccccceceeeeeeeeeeeeeeeeeeeeeeanaeeeeeeeeaes 16 Figure 2 7 Adding a device file usine tons aa nan o ane dite 16 Figure 2 8 Adding the design file to revision O cccccecsecsesecvsrsecnesearencussensensuseseeueanarseneensars 17 Figure 2 9 Selecting configuration file for XCFS32P cccccceeceescceseesecessesecnseeescneeeeneneceonens 18 Figure 2 10 PROM programming ODUONS 5 ae mie ect ae ete aus 19 Copyright 2008 The Learning Labs Inc UM 4 TLL5000 vi 1 documentation User Manual Tables Table Lil XG3S 1500 Features 222 ni ie naar ia ete in ones 9 Table ZA FPGA TENSIONS ES NN Re US Sd de Le Rd Sie ae ee irene nd 14 1a016 2 2 SDRAM TO FPGA CONNECTION asian nn Mi ide unie did 19 Table 2 3 Flash tO FPGA CONMCCUON riisun e duo due Lindos een eee ee iii er direcnae 20 Table 2 4 VGA DAC connections to FPGA vecccccccccccecccnccnccnccneeeeaneaeuaneaeuaeeaeuaseaneaeeaeeaeeueeaneaeeass 21 Table 2 5 Video encoder connection to FPGA wicccc
12. 1 NO _10_A3 _10_A3 _10_A3 ABI M M M M M M M M M M Z Z Z Z_10_A3 Z Z Z AAS MZ IO_ AD15 MZ_IO_ A52 CON901 51 Z Z TLL5000 vi 1 documentation User Manual AB16 IO_A51 CON901 47 MZ_IO_A60 CON901 71 AA MZ_IO A61 CON901 73 MZ_ IO A62 CON901 75 Z 10 _A63 _IO_A64 _IO_A65 _IO_A66 CON901 28 _IO_A68 _IO_A69 _IO_A70 _IO_A71 _IO_A72 _IO_A73 _IO_A74 _IO_A75 _IO_A76 _IO_A77 _IO_A78 _IO_A79 NIN NIN NIN NUON IN IN Z NIN AE4 N Table 2 16 Mezzanine B connection with the FPGA BALL Name Name MZ_IO_B2 MZ_IO_B3 MZ_IO_B4 MZ_IO_B5 MZ_IO B MZ_IO_B7 M MZ_IO B CON902 43 6 CON902 41 Z_IO_B8 CON902 45 Z 9 Copyright 2008 The Learning Labs Inc BALL Name Name Z_IO_B42 Z_IO_B43 Z_IO_B44 Z_10_B45 Z_10_B46 Z_10_B47 Z_10_B48 Z_I0_B49 Z_10_B50 D8 MZIO B51 CON903 47 D6 M M M M M M M M M UM 29 TLL5000 v1 1 documentation User Manual G12 MZ IO B12 CON902 55 C8 MZ IO B52 CON903 51 D9 _ MZ IO B53 CON903 53 3 Z 4 Z 7 Z 8 9 MZ_IO_B59 Z_IO_ MZ_IO_B1 MZ_IO_B1 MZ_IO_B60 CON903 71 F7 MZ_IO_B21 CON902 77 C13 MZIO B61 CON903 73 G19 MZ IO B22 CON902 26 D13 MZ IO B62 CON903 75 F19 MZ_IO_B23 CON902 28 E13 MZ_IO_B63 CON903 77 CON903 32 Z_I0_B69 _IO_B70 _IO_B71 _IO_B72 _IO_B73 _IO_B74 CON902 48 lt NININININ
13. Net Interface Signal BALL Name Name RS232_RX RS232_RX RS232_TX RS232_TX RS232_CTS RS232_CTS RS232_RTS RS232_RTS 2 12 Using the Ethernet Network Interface The Ethernet interface on TLL5000 is based on Intel s PHY LXT972A chip It s a single Port 10 100 Mbps PHY Transceiver which directly supports both 100BASE TX and 10BASE T applications It supports full duplex operation at 10Mbs and 100Mbs Operating conditions for the LXT972A Transceiver can be set using auto negotiation parallel detection or manual control The transceiver requires only a single 2 5 or 3 3 V power supply with 2 5 V MII interface support The Ethernet interface uses a standard Xilinx IP core opb_ethernetlite which ships with Xilinx EDK software with a hardware evaluation license Additional functions are given which enable verifying the interface functionality using the TLL5000 desktop software There are a number of jumpers around the Ethernet PHY the explanation is given in Table 2 13 Table 2 13 Jumper settings for the Ethernet interface 35202 capability advertising uring negotiation JS203 Connected to GND Device address setting 2 13 Using the SD Card The TLL5000 Development Board has a single SD Card slot directly connected to the FPGA Electrical interface specification along with communication SPI serial bus standard established by Motorola access protocol for SD cards is accomplished with SD Card Physical Layer System Specificati
14. TE a actu 10 1 2 13 Video decode amies a a na cite i 10 1 2 14 WIGEO NC OCC ornan a NA 10 1 2 15 ACO PAU CODEC aa a a a nice 10 1 2 16 EXDalSION CONMCCIONS Se nn ns es demi onda 10 1 2 17 SD CARD Mei aC eas Ein a asus das ac tt aa es 11 LIS ING ENS SYSTEME aa a Ra cms ados na ane rate nan tn tn 12 2 11 Power and Clock DIStrIDUTION sas ue en t etait 12 22 Conngunng TNE FPGA SNS Usa Sn a cesse 14 25 USING Ne SDRAM SE RDA ina a a it entous 19 24 Using tne SYS M FlAS NE A er Adi 20 2 93 USING EAE ASGA OUMU SR ot ae han non 21 2 60 Using the Video ENCOdEf ns enr eannense ss ieee aN 22 2 7 Using the Video Decoder cscccsscstoessectcetsenrsecuecusecnecuseeaesuseeatsaeuetsecutcatsentsanseateas 23 2 0 Using tne AC97 AUGIO COEG SR irinenn AN 24 2 9 Using the LEDs Switches and Buttons RL 25 210 Sin the LCD DISDIQY AS ere RS nana sec dun es 26 2 11 USING TNE Serial PONS annee An a Rendre ee 26 2 12 Using the Ethernet Network Interface ccccscsseccesseneseareecesseneerseseeneuecnersesnensass 27 2 15 USMO Me SD CASSER a ce a aa 27 2 14 Using the Mezzanine Expansion Connectors ss 28 2 15 Enabling TLL5000 Board in the Base System Builder Wizard 31 DOC MENENISLON EE RS nd eee nids de a ee in none 31 Copyright 2008 The Learning Labs Inc UM 3 TLL5000 vi 1 documentation User Manual Figures Figure 1 1 TEES900 BIOCK Diagramme na Area main tue 7 Foure 1 2 TLESO
15. TLL5000 v1 1 documentation User Manual TLL5000 Electronic System Design Base Module v1 1 User Manual Copyright 2008 The Learning Labs Inc UM 1 TLL5000 vi 1 documentation User Manual Copyright Notice The Learning Labs Inc TLL All rights reserved 2008 Reproduction in any form without permission is prohibited Disclaimer Information in this document is subject to change without notice and does not represent a commitment on the part of TLL TLL provides this document as is without warranty of any kind expressed or implied including but not limited to the particular purpose TLL may make improvements and or changes in this manual or in the products s and or the program s described in this manual at any time Information in this manual is intended to be accurate and reliable However TLL assumes no responsibility for its use or for any infringements of rights of other parties which may result from its use This document could include technical or typographical errors Changes are periodically made to the information herein these changes may be incorporated in new editions of the publication This manual is provided solely and exclusively for educational use and this information or related products should not be used nor relied upon for any purpose except for education and training Technical Support Please contact your local TLL authorized product representative for questions regarding hardware
16. _IO5 SYNC AC97_IO6 RESET 2 9 Using the LEDs Switches and Buttons The TLL5000 board has 8 surface mounted LED diodes 5 push button switches and 8 slide switches The LED diodes are illuminated when the user outputs a logical 1 to the appropriate pin of the FPGA Table 2 9 and they are off when a logical 0 is outputted to a pin Series resistors limit the current to about 4mA when the Led is illuminated 5 pushbuttons are in placed on tips of an imaginary diamond form shape giving the user the form of a gamepad When a button is pressed it generates a logic 0 o the pin of the FPGA while logic 1 is generated when a button is not pressed Table 2 8 shows which pins of the FPGA are connected to which push button Table 2 8 Pushbutton connections FPGA Schematic Net l Table 2 9 LED connected to the FPGA FPGA BALL SUE MSIE SL Interface Signal Name Name UI_LEDO UI_LED1 UI_LED2 UI_LED3 UI_LED4 UI_LEDS UI_LED6 UI_LED UI_LEDO UI_LED1 UI_LED2 UI_LED3 UI_LED4 UI_LEDS UI_LED6 UI_LED 8 slide switches are placed in line on the board When the switch is on it generates logic 0 on the pin of the FPGA to which it is connected while logic 1 is generated Copyright 2008 The Learning Labs Inc UM 25 TLL5000 vi 1 documentation User Manual when a switch is off Table 2 10 shows which pins of the FPGA are connected to which DIP switch Table 2 10 DIP switches conn
17. cceccecccceccuceccueccceneceuceenuceuaeeneaneaeeneaneaseneanears 22 Table 2 6 Video Decoder Schematic Connection vecccccccccueccuceccaccuceeceuaceneceeaeeeeaeeneeneaneaseneanears 23 Table 2 7 AC97 codec connection with the FPGA wicccccccccecccccecccccceceneceuaneaeeaeeaeeaeeaeeaeeuesaneneears 25 Table 2 6 PUSNDUTION CONNECTIONS a 208 nee tale nent ana an dede sta ed ere een ete 25 Table Z 9 LED conmect d t0 the FPGA ressidar a a sed deamannduded EAA E 25 Table 2 10 DIP switches connected to the FPGA vecccccccccceccccceccccccecaeeueuaeeueuaeeaeeaesaeeaeeuenareneears 26 Table 2 LT LED connecion W FPGA ieaie e a etat 26 Table 2 12 R9232 CONNCCHON to Mhe FPGA annales a a 27 Table 2 13 Jumper settings for the Ethernet InterlaCe wicccccccccececcceeceeeeeeeeeeeeesesesenenenenenensnsnenas 27 Table 2 14 SD card interface connection to FPGA veccccccccecccccecccccceuaeeceuaeeaeeaeeaeeneuaeeaeeueeaneaeeas 27 Table 2 15 Mezzanine A connections with the FPGA iccccccccecccceccucencccceceneceuaeeneaeeaeeneaneaseneanears 28 Table 2 16 Mezzanine B connection with the FPGA wicccccccccecccceccuceccceueceeuceeaeeneaeeaeeneaneaseneaneats 29 Copyright 2008 The Learning Labs Inc UM 5 TLL5000 vi 1 documentation User Manual 1 TLL5000 Electronic System Design Platform ESDP 1 1 Features e Xilinx Spartan3 FPGA e ARM LPC2144 Housekeeping Processor e 16MB SDRAM on board e 16MB FLASH on board e High speed SelectMAP FPGA configuration from Platform Flash In Sy
18. der outputs settings Divide value and phase offset can be individually adjusted for each channel For Mezzanine clock outputs LVDS or CMOS signal standards can be selected Channel setting is implemented by pressing the corresponding set button Copyright 2008 The Learning Labs Inc UM 13 TLL5000 vi 1 documentation User Manual 2 2 Configuring the FPGA The FPGA is programmed from Xilinx ISE or EDK software during FPGA software development This is done by selecting menu entry Device configuration Download bitstream During power up of the board the FPGA can be programmed by one of four available revisions inside Xilinx Platform flash XCF32P To enable multiple revisions place switch 1 from DIP switch pack S1 to position 1 To select the desired revision use switches 2 and 3 from the same pack Table 2 1 FPGA revisions Position of Position of Revision number Default function 2 switch 3 2 Peripheral tests except video and Ethernet Memory tests 7 3 Video and Ethernet tests C Ad ee eee eee eee No default function To prepare a PROM file with multiple revisions proceed as follows The bit file created by the Xilinx implementation tools must be converted to an MCS file before it can be programmed into the Platform FLASH PROM 1 Start IMPACT and select Prepare Configuration Files as shown in Figure 2 3 Figure 2 3 mm Moce Selection Prepare Configuration Files D A F A Hi
19. ected to the FPGA Interface Signal Name A generic Xilinx IP core opb_gpio is used to access all these peripherals 2 10 Using the LCD Display The LCD display onboard TLL5000 consists of a Display electronic GmbH LCD module SYH 16216 SYH LY which uses a Hitachi HD44780 LCD controller in 4 bit mode A Xilinx IP core opb_gpio_v3_01_b is used to access this peripheral while additional software functions are given which enable resetting the LCD controller and writing on line or line 2 of the LCD Table 2 11 shows FPGA to LCD connection list Table 2 11 LCD connection with FPGA BALL Name Name LCD_IO0 LCD _D3 LCD IO1 LCD _D2 LCD_IO2 LCD_D1 LCD_IO3 LCD_DO LCD_I04 LCD_EN LCD_IO5 LCD_R W LCD_IO6 LCD_RS LCD_IO7 LCD_L 2 11 Using the Serial Port The TLL5000 Development System has a single RS 232 port The RS 232 port is configured as a Data Communication Equipment DCE with hardware handshake using a standard DB 9 serial connector Considering the 12V logic levels on RS232 connectors a ADM3202 high speed RS232 v 28 interface from Analog Devices is used for coupling The FPGA IP core which is used for RS232 is Xilinx opb_uartlite_v1_00_a core Functions are provided which enable sending messages from the TLL5000 to the PC but also receiving user input from the PC Copyright 2008 The Learning Labs Inc UM 26 TLL5000 vi 1 documentation User Manual Table 2 12 RS232 connection to the FPGA FPGA Schematic
20. ectors The includes two 80 pin 2 x 40 mezzanine board connectors Every connector provides 40 Spartan3 I O pins JTAG signals two differential clocks synchronized to the on board 100Mhz master clock and 3 3V 3 5A and 18V 0 5A power supply lines Copyright 2008 The Learning Labs Inc UM 10 TLL5000 vi 1 documentation User Manual 1 2 17 SD CARD interface The TLL5000 system includes a header for SD and MMC cards which enable users to store their data on a removable media Copyright 2008 The Learning Labs Inc UM 11 TLL5000 vi 1 documentation User Manual 2 Using the System 2 1 Power and Clock Distribution Before starting TLL5000 Monitor Controller application the TLL5000 should be connected to the PC using ARM USB port TLL5000 Monitor Controller application initial screen is shown in Figure 2 1 Figure 2 1 TLL5000 Monitor Controller Initial Screen 7 LL5000 Monitor Controler Board ID per ed Eth Addr LL 5000 Development Board i Choose Device sr LL 5000 Development Board i I Eh Snead Se ssa sa ase e SEA Se sa Esai Status information Reset DK First TLL5000 Development Board device should be selected using circled drop down box After that board can be powered up using Power button After powering up the TLL5000 Monitor Controller screen should look like it is shown in Figure 2 2 Copyright 2008 The Learning Labs Inc UM 12 TLL5000 vi 1 documen
21. either the front or back porch of the video signal A separate teletext port enables the user to directly input teletext data during the vertical blanking interval Table 2 5 shows the connection list between the FPGA and the video encoder The provided FPGA IP enables reading out a region of SDRAM memory containing CCIR 601 data stream and sending it to the encoder circuitry The video encoder can be used stand alone or together with the video decoder circuit Table 2 5 Video encoder connection to FPGA FPGA Schematic Net Interface Signal BALL Name Name Copyright 2008 The Learning Labs Inc UM 22 TLL5000 v1 1 documentation User Manual AB2 VENC_IO0 Pi AB1 VENC_IO1 P2 Y7 VENC_IO2 TTX Y6 VENC_IO3 CSO HSO AA4 VENC_I04 PO AA3 VENC_IO5 VSO YS VENC_I06 FIELD VSYNC Y4 VENC_IO7 RESET AA2 VENC_IO8 P3 AA1 VENC_I09 P4 Y2 VENC_IO10 P5 Y1 VENC _IO11 P6 W7 VENC_I012 TTXREQ W6 VENC_I013 HSYNC W5 VENC_I014 BLANK V7 VENC_IO15 SCRESET RTC W4 VENC_I016 PAL NTSC W3 VENC_IO17 CLAMP W2 VENC_I018 P7 2 7 Using the Video Decoder The TLL5000 contains a video decoder circuitry ADV7180 enabling conversion from standard analog PAL NTSC video signal to CCIR 601 data The ADV7180 automatically detects and converts standard analog baseband television signals compatible with worldwide NTSC PAL and SECAM standards into 4 2 2 component video data compatible with the 8 bit ITU R BT 656 interface standard External HS VS and FIELD si
22. gnals provide timing references for LCD controllers and other video ASICs if required The accurate 10 bit analog to digital conversion provides professional quality video performance for consumer applications with true 8 bit data resolution Three analog video input channels accept standard composite S video or component video signals supporting a wide range of consumer video sources AGC and clamp restore circuitry allow an input video signal peak to peak range up to 1 0 V Alternatively these can be bypassed for manual settings The provided IP core enables setting ADV7180 registers using IC and receiving CCIR 601 data and storing it to SDRAM memory from where it can be read by the video encoder or a user application Connections to the FPGA are given in Table 2 6 Table 2 6 Video Decoder Schematic Connection FPGA schematic Net Interface Signal Name BALL Name j AD2 VDEC_IO0 RESET ADI VDEC_IO1 Pi AB4 VDEC_IO2 P2 AB3 VDEC_IO3 LCC Copyright 2008 The Learning Labs Inc UM 23 TLL5000 vi 1 documentation User Manual AC2 VDEC_104 PO AC1 VDEC_IO5 PWRDWN AA6 VDEC_IO06 P3 AB6 VDEC_IO7 P4 ADS VDEC_IO8 P5 AC6 VDEC_IO9 P6 AD6 VDEC_I010 P7 AC7 VDEC_IO11 SFL AC8 VDEC_I012 HS AD8 VDEC_1013 INTRQ AC9 VDEC_IO14 VS FIELD 2 8 Using the AC97 Audio Codec The TLL5000 has an AC9 rev 2 3 compliant IC AD1981BL It can be used to record and play audio but also for basic signal acquisition and generation at audio frequencies
23. he Platform Flash device XCF32PVO48C can contain up to 4 FPGA code revisions 1 2 7 System RAM The TLL5000 Development System has on board mounted Micron 1Meg x 32 x 4 Banks SDRAM module 1 2 8 System Flash The TLL5000 Development System has on board mounted 128Mbit Spansion S29GL128N Flash module 1 2 9 Ethernet interface The TLL5000 Development System provides an IEEE compliant Fast Ethernet transceiver that supports both LOOBASE TX and 10BASE T applications It supports full duplex operation at 10 Mb s and 100 Mb s with auto negotiation and parallel detection The PHY provides a Media Independent Interface MII for attachment to the 10 100 Media Access Controller MAC implemented in the FPGA Each board is equipped with a Silicon Serial Number that uniquely identifies it with a 48 bit serial Copyright 2008 The Learning Labs Inc UM 9 TLL5000 vi 1 documentation User Manual number This serial number is retrieved using the 1 Wire protocol This serial number can be used as the system MAC address 1 2 10 Serial interfaces The TLL5000 Development System provides three serial ports a single RS 232 port and two PS 2 ports The RS 232 port supports hardware handshake and it uses a standard DB 9 serial connector This connector is typically used for communications with a host computer using a standard 9 pin serial cable connected to a COM port The two PS 2 ports could be used to attach a keyboard and mouse to t
24. he TLL5000 Development System 1 2 11 User LEDs Switches and Push Buttons A total of eight LEDs are provided for user defined purposes Turning the LED on is done by setting a logic 0 to the corresponding FPGA pin Eight position separate slide switches and five push button switches are provided for user input The middle push button is used as FPGA reset button 1 2 12 VGA Output The TLL5000 includes a video DAC and 15 pin high density D sub connector to support XSGA output The video DAC can operate with a pixel clock of up to 180 MHz Only VESA compatible output of 640 x 480 at 60 Hz refresh is supported by software It can also be used as a 3 channel signal generator 1 2 13 Video decoder The TLL5000 includes an Analog Devices ADV7180 video decoder with CVBS composite Y C S video and YPrPb component video input support It supports NTSC PAL SECAM video standards with additional video standard autodetection feature 1 2 14 Video encoder The TLL5000 offers composite Y C S video and YPrPb component video output Support provided by Analog Devices ADV7173 video encoder 1 2 15 AC97 Audio CODEC An audio CODEC and stereo power amplifier are included on the TLL5000 to provide a high quality audio path and provide all of the analog functionality in a PC audio system It features a full duplex stereo ADC and DAC with an analog mixer combining the line level inputs microphone input and PCM data 1 2 16 Expansion Conn
25. ideo and YUV Video The on board SSAF Super Sub Alias Filter with extended luminance frequency response and sharp stopband attenuation enables studio quality video playback on modern TVs giving optimal horizontal line resolution An additional sharpness control feature allows extra luminance boost on the frequency response A PC 98 Compliant autodetect feature has been added to allow the user to determine whether or not the DACs are correctly terminated If not the ADV7173 flags that they are not connected through the Status bit and provides the option of automatically powering them down thereby reducing power consumption The ADV7173 also supports both PAL and NTSC square pixel operation The parts also incorporate WSS and CGMS A data control generation The output video frames are synchronized with the incoming data Timing Reference Codes Optionally the encoder accepts and can generate HSYNC VSYNC and FIELD timing signals These timing signals can be adjusted to change pulsewidth and position while the part is in the master mode The Encoder requires a single two times pixel rate 27 MHz clock for standard operation Alternatively the Encoder requires a 24 5454 MHz clock for NTSC or 29 5 MHz clock for PAL square pixel mode operation All internal timing is generated on chip HSO CSO and VSO TTL outputs synchronous to the analog output video are also available A programmable CLAMP output signal is also available to enable clamping in
26. nu as shown in Figure 21 The iMPACT software responds with a form that allows the user to specify which design revisions are to be programmed and the programming options for the various revisions De select Design Revision Rev 0 and Rev 1 and all of the options for these revisions to minimize the programming time Figure 2 9 Selecting configuration file for XCF32P Dou UNE SE tlie ge Lookin G ATY_DESGH mi pr EF EMY _DESGH_PROR mis Fie rara M _CESICN_PROM mes Open Fis type MES Fisu menj Cancel Canoa A Bypass Copyright 2008 The Learning Labs Inc UM 18 TLL5000 vi 1 documentation User Manual Figure 2 10 PROM programming options Advanced PROM Programming Options x Design Revision and Customer Code g led Design Revision and Erter Cusiomer Code Max 64 Hex Digts Design Read Were Eras werh 39 Customer Reagon Protect Protect Code Pen PPP Powe DER pe nn PR Ae we eR vm a Pe ee Pee Peep a Res FF dae aoia m T Detsut Revision Opensthig Hoda LO Configuration Slave clocked by extemal dock Perslel Mode C Waste select clack soircel Le ercode i ee CEPTE La a Enter Hew Dlighe Wearconde L file nie ul ER o Cock Frequency OMHe Load FRG Hk Cancel Help 22 Select Design Revision Rev 2 and set the Erase ER bit to erase any previous
27. on Version 1 01 defined by SD Card Association Communication is implemented with Xilinx SPI IP core opb_spi_v1_00_d Additional functions are provided which enable initializing the card reading it s size and block read and write The connection to the FPGA is given in Table 2 14 Table 2 14 SD card interface connection to FPGA FPGA BALL Schematic Net Name Interface Signal Name J21 MMC_IO0 DI CD CMD K20 MMC_IO1 SW_CI Copyright 2008 The Learning Labs Inc UM 27 TLL5000 v1 1 documentation User Manual H21 MMC_IO2 CD DAT3 J20 MMC_IO3 DAT2 L19 MMC_I04 Do DATO L20 MMC_IO5 CLK M19 MMC_I06 DATI N19 MMC_IO SW_WP 2 14 Using the Mezzanine Expansion Connectors The TLL 5000 is able to accept two Mezzanine expansion modules 80 pins module and these are intended to provide the expansion capability to allow for complementary processing RISC DSP and interface analog power wireless modules needed for prototyping advanced electronic systems For that purpose two pairs of high speed Samtec connectors for mezzanine board A and B are implemented on the board Each of the interface consist of 80 bits wide bus connected to FPGA I C bus 3 3V and 18V power two differential or selectable one single ended and one LVPECL clocks from clock generator subsystem and dedicated JTAG lines The connectors are symmetrical both in electrical and physical sense giving the opportunity to use both pair of connector
28. ric Xilinx SDRAM controller OPB_SDRAM IP is used to enable access to SDRAM in the design S gt lt gt gt lt lt lt lt 26 B25 SiS SISS S SiS lt z 222 lt E gt 2 4 Using the System Flash The TLL5000 board is equipped with a Spansion S29GL N MirrorBit Flash Family device The Flash IP enables access to the flash with the following commands read erase sector erase chip write word write buffer The connection between the Flash and the FPGA is given in Table 2 3 BALL Name o DQO Table 2 3 Flash to FPGA connection SCH Net Name Name BALL Name 5 1 LASH_IO2 LASH_IO2 LASH_IO2 LASH_IO2 LASH_IO2 LASH_IO2 LASH_IO3 LASH_IO3 LASH_IO3 LASH_IO3 LASH_IO3 TI TI NJ OY O71 BR OU FLASH_IO FLASH_109 F4 FLASH 1010 OE F3 FLASH 1011 DQO T T T O O OO F6 F5 E4 E3 D2 D1 G7 G6 E2 El F4 F3 H J7 K7 J5 J4 J3 J2 6 N K TI 11 11 A GJ Copyright 2008 The Learning Labs Inc UM 20 TLL5000 v1 1 documentation User Manual K3 FLASH_1035 9 FLASH_IO12 WP G5 FLASH_1017 A FLASH_1040 FLASH_1018 CS 1 6 7 A16 M7 2 5 Using the XSGA output The TLL5000 board is equipped with a triple 8 bit DAC ADV7125 U402 a high density 15 pin D Sub connector CON203B and IP placed in the FPGA The data inputs and control signals are converted into analog current outputs that
29. s equally The 18V and 3 3V power supplies are brought to connectors for powering up the mezzanine boards The 80 bit interface is routed as high speed 50ohm lines with equalized line length to achieve signal integrity for a wide range of possible mezzanine boards High speed connectors QTE 40 02 L D A K from Samtec are used for the mezzanine boards interconnecting Mating connectors on the mezzanine boards should be QSE 40 01 L D A K Please refer to manufacturer resources for more detailed information on the connectors FPGA to mezzanine connectors A and B connection list is shown in Table 2 15 and Table 2 16 respectively Table 2 15 Mezzanine A connections with the FPGA FPGA SCH Net FPGA SCH Net BALL Name Name BALL Name Name AF15 AE15 MZ_IO_A _IO_A4 MZ_IO_A _IO A4 MZ_IO_A _IO A4 _IO A4 IO A4 IO A4 IO A4 IO A4 IO A4 AC16 _IO A5 lt lt lt NININ O Z_IO_A Z_IO_A Z_IO_A AE20 MZ_IO_A M NIN 1 2 3 M 4 MZ_IO_A5 M 6 7 8 9 zZ NINN WO 00 NI Oy O71 A G0 IN IE ES NIN Copyright 2008 The Learning Labs Inc UM 28 AF21 MZ_IO All CON900 53 6 7 8 Z AB20 MZ_IO_A20 CON900 75 AA20 MZ_IO A21 CON900 77 MZ_IO_A22 CON900 26 MZ_IO_A23 CON900 28 MZ_IO_A25 MZ_IO_A26 Z_IO_A29 Z_IO_A30 Z_IO_A31 _IO_A32 _IO_A33 _IO_A34 5 6 7 8 9 a ea wWiwlO Rm r NO NO RQ e UW IN gt gt 0 CO N NJ OY O7
30. stem e Programmable Configuration PROM e On board 10 100 Ethernet PHY device e Silicon Serial Number for unique board identification e SD MMC card slot e RS 232 DB9 serial port e Two PS 2 serial ports e Eight LEDs connected to Spartan3 I O pins e LCD 16 x 2 character display with backlight e Eight switches connected to Spartan3 I O pins e Five push buttons connected to Spartan3 1 0 pins e Two high speed mezzanine board connectors joined to 80 Spartan3 I O pins e AC 97 audio CODEC with audio amplifier and speaker headphone output and line level output e Microphone and line level audio input e On board VGA output 640 x 480 at 60 Hz supported by software with added signal generator capability e On board video decoder with CVBS composite Y C S video and YPrPb component video input support e On board video encoder with with CVBS composite Y C S video YPrPb component and EuroSCART RGB video output support e On board power supplies e Power on reset circuitry Copyright 2008 The Learning Labs Inc UM 6 TLL5000 vi 1 documentation User Manual 1 2 General Description The TLL5000 Development System provides an advanced hardware software platform that consists of a high capacity Spartan3 Platform FPGA surrounded by a comprehensive collection of peripheral components that can be used to create a complex digital system 1 2 1 Block Diagram Figure 1 1 shows a block diagram of the TLL5000 Development System
31. tation User Manual Figure 2 2 TLL5000 Monitor Controller Power On Screen LL 5000 Monitor Controler Ethernet Test Board ID Connected Eth Add 00 00 Od ba e1 42 ual Host IP 192 168 1 79 Tt LL 5000 Development Board Wite Eth Addr to fonts BoadIP 192 168 1 0 Not Done 12 kd 1239Y 33 La 3 30VY 000000 e g Real eg onoo ie Read 25 2 57 18V 1814 o 0000 al 00000 Lev 1e0v ady ADS510 Registers Clock Inputs soo reg Ox00 Ce ae C Cki 0 M l Ck 100 0000 MHz ie Witte val 000 Read Clock Sets LVPECL es CMOS fe E Status information Clocks set OK Power Values Monitor shows current power supply levels with their valid ranges 2 FPGA R W provides FPGA OPB read write functionality It can be used for debug purposes 3 CPLD R W provides CPLD registers read write functionality It can be used for debug purposes 4 AD9510 Clock Divider input clock selection External clock Clk 1 or on board generated 100MHz clock Clk 2 can be selected as Clock Divider input clock 5 AD9510 Clock Divider manual register access It should be used if desired clock distribution can not be obtained using controls 6 and 7 6 Four LVPECL Clock Divider outputs settings Divide value and phase offset can be individually adjusted for each channel Channel setting is implemented by pressing the corresponding set button 7 Two selectable CMOS LVDS and two CMOS Clock Divi

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