Computer - Digalog Systems, Inc.
Contents
1. RN2 ct JP21 ma pi p U2 mL C2 79 JP26 JP1 JP6 pa LI JP7 D us 07 C14 JP4 JP9 cu J5 H 420 en vii p en 15 L C3 js cu ol 3516 us ng Jer MH JP13 JP18 7 U10 R9 JPM JP19 c4 R7 JP27 JP15 JP20 m JP28 L us JP29 R8 JP30 C16 JP31 p un U22 C5 cu g n 5 I 07 7 UT 7 Ul 023 JP33 js JP22 T T 2 l 7 4 024 5 _ C8 C9 7 UB c18 T 7 Ut5 U25 E NE Figure 15 0000 2268 I O Controller Assembly 2030 Computer Manual Revision 1 4 Page 47 Interface Card Mounted on a plate at the back of the computer is a circuit card that converts the signals from the I O Controller assembly to connectors usable by the outside world This card is called the I O Interface card and accepts the other end of the 50 pin connector coming from the I O Controller Assembly This card contains 4 DB 25 connectors for RS 232 422 a Centronix 36 pin connector for a printer parallel port and a DB 15 connector that is used by a keypad or Operator Interface Panel The pin out of the connectors are listed in the following tables The RS 232 ports located on the 4 DB 25 connectors are configured as DCE ports This means that there is a driver connected to pins 3 and 5 and a receiver connected to pins 2 and 4 Remember that the signal name for the2. 4f TERM serial 0000000000004 T4 serial port port 3 x 000000000000 JO P printer port en 0 KP keypad connector port TBus connector Figure 1 2030 Computer Back Panel 2030 Computer Manual Revision 1 4 Page 4 STARTUP Ordinarily when power is applied or the reset button is released the loader program will bring up the OS9 68000 operating system from the hard disk and the system will begin accepting commands from the console keyboard or will request a user to log in It may be instructive to see exactly what happens during this complicated process to help users diagnose and avoid problems and make the most of the many opportunities to fine tune the operating system to their personal requirements The loader is located in EPROM on the CPU board at FE0000 FFFFFF When the RESET line is asserted by the power on reset circuit reset push button or reset instruction the memory map is switched to overlay the EPROMs at 000000 01FFFF The microprocessor enters supervisor state loads its stack pointer from locations 0 3 and loads its program counter from locations 4 7 The loader is executed and immediately clears a latch to restore RAM access at 0000000 01FFFF The loader then begins to initialize RAM All of the 68010 exception vectors at 000C 03FF all vectors except reset and bus e
3. 43 TABLE 33 0000 1568 OTHER INTERRUPT POSSIBILITIES eene rennen 43 TABLE 34 0000 2268 JUMPER SETTINGS FOR OS 9 V2 4 enne nn nennen nente eren nennen 44 TABLE 35 0000 2268 OTHER INTERRUPT POSSIBILITIES 44 TABLE 36 0000 1568 JUMPER SETTINGS FOR 5 232 44 TABLE 37 0000 1568 JUMPER SETTINGS FOR 422 44 TABLE 38 0000 2268 JUMPER SETTINGS FOR 5 232 45 TABLE 39 0000 2268 JUMPER SETTINGS FOR RS 422 eene eene 45 TABLE 40 0000 1568 0000 2268 OUTPUT CONNECTOR PIN OUT 45 TABLE 41 11 12 T3 TA CONNECTOR PIN QUT eese ERE REY VENUE Ne E Y 48 TABLE 42 7 CONNECTOR PIN OUT ood tec vases ee a RUE ERE UU 48 TABLE 43 KP CONNECTOR PIN OUT E enne E AE AAE ee enses entren enn 49 TABLE 44 0000 2563 OUTPUT CONNECTOR PIN OUT eene nennen enne 50 TABLE 45 GPIB CONTROLLER ADDRESS MAP ee eene eene entere entres es eene ener nn 51 TABLE 46 0000 1570 JUMPER SETTINGS FOR OS 9 V2 4 51 TABLE 47 0000 1570 OTHER INTERRUPT JUM
4. nnn enne enne 23 TABLE 18 0000 2232 MEMORY SIZE SELECTION ente 23 TABLE 19 0000 2232 1 MEGABYTE CARD NUMBER SELECTIONS 2 24 TABLE 20 0000 2232 2 MEGABYTE CARD NUMBER SELECTION eee 24 TABLE 21 0000 2232 4 MEGABYTE CARD NUMBER SELECTION nn enne enne 24 TABLE 22 GESSIO 1B CHANNEL 1 T5 CONNECTOR PIN 26 TABLE 23 GESSIO 1B CHANNEL 2 T6 CONNECTOR 26 TABLE 24 GESSIO 1B JUMPER SELECTIONS OS 9 VERSION 2 4 nanas 30 TABLE 25 0000 3220 0000 3520 CHANNEL 2 T6 CONNECTOR PIN 32 TABLE 26 0000 3220 0000 3520 CHANNEL 1 T5 CONNECTOR PIN 32 TABLE 27 0000 3220 0000 3520 JUMPER SETTINGS FOR RS 232 OS9 VERSION 2 4 33 TABLE 28 0000 3220 0000 3520 JUMPER SETTINGS FOR RS 422 059 VERSION 2 4 33 TABLE 29 2000 3022 0000 3422 SCSI SASI HOST ADAPTER MEMORY 36 TABLE 30 2000 3022 GESHDI 2A JUMPER SETTINGS FOR OS 9 VERSION 2 4 36 TABLE 31 0000 3422 JUMPER SETTINGS FOR OS 9 VERSION 2 4 38 TABLE 32 0000 1568 JUMPER SETTINGS FOR OS 9 V2 4
5. Figure 9 0000 3520 Dual Serial Port Card 2030 Computer Manual Revision 1 4 Page 34 E z LJ LJ LJ LI JP2J JP19 e 124 JPi e 2242 12202 2 Pa 24 JP21 JP6 JP3 Cu NC 020 C5 RO 17 RI E E ne Ce E C21 C6 5 22 C jon C IX Is ES C23 C8 BE 22 G gt To 024 S 5 5 mon c 22m H Qe en mes C17 C16 C9 JP7 agi g JPE c8 JP14 es 10
6. O a vin Figure 7 0000 2232 Memory Card For pin assignments of the G 96 bus connector please see the section titled G 96 Mother board Assembly 2030 Computer Manual Revision 1 4 Page 25 Dual Serial Port Card The Dual Serial Port Card provides two serial communication channels on the G64 G96 bus As configured for use in the Digalog Systems computer the card offers asynchronous communication using the RS 232C protocol Its baud rate is software programmable RS 422 levels are also possible with this card The TTY interface on the GESSIO cards is not supported by Digalog Systems The communication ports on this card are known to the operating system through the device descriptors 15 and t6 The settings of each device descriptor as shipped from Digalog are listed in the back of this manual The device driver sc6850 and the file manager SCF are used to control the card Four different Dual Serial Port Cards are in use on the 2030 computers They are the GESSIO 1A and GESSIO 1B cards Digalog P N 2000 3020 and Digalog s Dual Serial Port Card P N 0000 3220 and 0000 3520 All cards except the GESSIO 1A are interchangeable without having to change the software The GESSIO 1A card cannot be used with the Digalog implementation of the OS 9 operating system version 2 4 and above 2000 3020 GESSIO 1B Dual Serial Port C
7. JP4 1 5 031 C28 C26 555 C20 2030 Computer Manual Revision 1 4 Page 50 Figure 16 0000 2563 Testhead Controller Assembly GPIB Controller Assembly Digalog System s GPIB Controller Assembly uses a TMS9914A chip set to implement the IEEE 488 instrument control bus Included on the card are interrupt vector registers and daisy chain IACK logic The hardware implementation supports the IEEE 488 controller talker and listener functions The card is connected to a standard IEEE 488 connector through the Digalog P N 0000 2059 cable Two part numbers have been used for GPIB Controller Assemblies 0000 1570 and 0000 1970 They are completely interchangeable The device driver gpib and file manager SCF is used to control the functions on the board System implementation parameters are stored in the device descriptor g A no response time out and device address parameters are also stored in the descriptor As Microware had not envisioned using the SCF device drivers and descriptors with an addressable bus the time out and address parameters are kept in the tabs and tabc entries of the device descriptor The time out parameter is stored in tabs and GPIB address is stored in tabc Application programming of the GPIB Controller Assembly is described in the Series2030 Analog Manual Access to the card is permitted at odd addresses only The base address is located in
8. S3 and incremental tape backup mt0 A SASI interface controller is used The standard hard disk is a four surface plated media design with a formatted capacity of 40 Mb 1 Mb 1048576 bytes However other drives of similar capacity may be substituted as availability changes The floppy disk format is double sided double bit density double track density 96 TPI 80 tracks for a formatted capacity of 655360 bytes The back up streaming tape uses the QIC 02 format with a high capacity cassette style cartridge The hard disk may be backed up and restored as a whole disk image for emergency use The back up tape may be used as a very slow read only device for recovery of individual files by treating the tape drive as a disk The file descriptor used for this is s3 For individual file or directory backup the user may execute the Fsave and Frestore commands The descriptor used for doing this is mt0 Follow the Fsave Frestore instructions found in the Microware manual sets Because of the way Fsave writes files to the tape incremental restoration of files 1s much faster than trying to restore them from a streamed bit image tape The floppy disk cannot be backed up to or used as a hard disk back up per se other than that individual files may be read or written in the usual manner In particular the OS9 BACKUP command is not used with this system The DSAVE command may be used in conjunction with the COPY command to copy all files on a
9. Table 17 0000 2232 Card Type Selection Memory Size JP2 JP3 Forbidden Condition megabyte Open Closed 2 megabyte 4 megabyte Table 18 0000 2232 Memory Size Selection 2030 Computer Manual Revision 1 4 Page 23 O Closd Closed Closed Closed 18 Closed Closed Closd Open 9 Open Closed Closed Open B Closed Open Closed Open Table 19 0000 2232 1 Megabyte Card Number Selections O Closed Closed Closed 2 _______ Closed Open Closed 144 Closd Closed Open 6 Open Table 20 0000 2232 2 Megabyte Card Number Selection Note JP4 is unused Leave the jumper open O Closed Table 21 0000 2232 4 Megabyte Card Number Selection Note JP4 and JP5 are not used Leave the jumpers open 2030 Computer Manual Revision 1 4 Page 24 19 9 2 72 c c c N amp M eo c c c s s s 5 Q o Q o gt JP 2 JP3 lt JP4 gt E T JP5 Ips 7 2
10. opf __ Yes 2 02 kp __ ___ EVLAN 11 GESCNX GESVIG 2 GESHDI 25 GESFDC 2B EMBus Controller Unused _____ FB8000 N A memory No autovector Table 2 G96 Interrupt Map Notes for G96 Interrupt Map 1 The polarity of ACK is active HIGH which follows the G64 convention 2 Synchronous devices are autovectored IRQ Number Mode Autovectored 2 Undefined 7 3 4 Vetoed 5 7 Autovectored 6 Veetored only used by MPUI4A board Table 3 Interrupt Modes Address Range Mode FD0000 FDO1FF FD0200 FD03FF FD0400 FDOSFF FD0600 FDO7FF Table 4 Peripheral Addressing Modes INSTALLATION This section contains information regarding the shipment inspection installation and self test of the Series 2030 CPU The Series 2030 CPU is shipped essentially ready for use when received However the following sections should be covered before attempting to operate the system RECEIVING INSPECTION A close visual inspection should be performed promptly after the system has been received Any evidence of rough handling should be reported to the shipper and to Digalog Systems Look for broken switches scratched or dented panel surfaces and for any other damage to the exterior of the unit Also check the Terminal and cables for possible mishandling If damages of any kind are found refer to the procedures outlined in the w
11. 19 If the size word is nonzero a seek is performed to the indicated sector and the file is loaded into RAM starting at 2400 The loader then transfers control to the module at 2400 which should be the OS9 kernel At this point the loader is finished The loader may not be able to find the boot file on logical unit zero This always occurs on the first few attempts after a cold start while the hard disk is not yet up to speed The loader would then try unit one floppy disk starting over from where the DIGALOG SYSTEMS message is displayed As long as a boot file cannot be located on either unit the loader will alternate between units trying to locate one The loader can be directed to get the boot file from the hard disk by removing the floppy disk before powering up the computer or resetting the CPU The loader can be forced to get the boot file from a floppy disk by turning off the power briefly thus causing the hard disk to lose enough speed whereby the floppy drive is accessed first In either case the desired unit must contain a valid boot file Boot files are installed with the utility program OS9GEN which makes the file contiguous and installs the size and location in sector zero as mentioned above The boot file OS9Boot is made up of modules some are mandatory and others optional KERNEL must be the first module The others may be in any order INIT is mandatory it is a data module containing system configuration parameters see the
12. S2 Jumper Positions The jumpers for S2 Toshiba M222XD2 are Table 54 Toshiba M222XD2 S2 Jumper Positions SO will have to be repositioned in the mounting plates in order to install S2 Install S2 immediately under and with the same orientation as SO 2030 Computer Manual Revision 1 4 Page 57 7 Install cable 0000 2054 to J4 of the OMTI5400 board and 12 of S2 8 Replace cable 0000 2051 with cable 0000 2045 The middle connector of this cable connects to S2 J1 9 Install cable 6000 2044 in the computer 10 Re install the hard drive assembly into the computer 11 Check disk operation by using the OS 9 utility Dcheck 12 Re install the computer rack back into the system 2030 Computer Manual Revision 1 4 Page 58
13. 0000 rev CC ASSEMBLY sec Figure 13 2000 3012 Disk Controller OMTI 5400 2030 Computer Manual Revision 1 4 Page 41 I O Controller Assembly The I O Controller Assembly contains four serial ports a printer port and a user keypad port Two different assemblies are used in the 2030 computer system The Digalog part numbers for the assemblies are 0000 1568 and 0000 2268 Software used to set options of the I O controller are the serial port descriptors t1 t2 t3 and t4 and the printer port descriptor p An additional descriptor kp 1s used to control an optional keypad Control of the board is through the device drivers sc68681 and The base address and selection of hardware interrupt level is done via jumpers located on the board The base address is located in the VPA space Interrupts are from 1 to 5 If the interrupt level selected is vectored then acknowledge priority between boards is handled by the G 96 bus chain in and chain out signals Interrupt priority on board is the p VIA the 1 2 DUART and t3 t4 DUART Serial Ports The serial ports are asynchronous format and are controlled by two MC68681 dual UART chips Jumpers for each serial port select RS 232 single ended mark 12 volts space 12 volts or RS 422 differential 5 volts voltage levels Data is preceded by a mark to space transition for one bit time and transmitted LSB first 8 bits no parity Software allows selection of 1 1 5 or 2 st
14. 4 EA 2030 Computer Manual Revision 1 4 Page 33 P3 P2 U24 20 17 1 JP22 Tup g JP4 JP1 2 9923 2 1220 e 5 JP2 JP24 4221 JP3 CH R7 C20 C5 R8 SE RI gt lt U29 M 2 25 U9 L3 CAL 21 C6 ES 5 m C22 U27 U21 18 15 U10 07 4 c C23 BE C15 528 mo 22 19 16 1 8 es go 28 Zu RE sen dm 225 HE na 555 C17 C16 cg gt gt ba JP7 en JP14 JP9 C18 JP15 _ uP10 U23 26 mE m JP12 gt Sj a JP18 JP13 2
15. 4 Page 37 Jumpers Function Jumper Setting Result Addmsslin AS 8 4 50 Addrssline A9 9 50 _JP10 21 Interrupt level selection IRQI selected Optioncode 0 2 Opioncode Option code JPI3 PIAOinterrptAtoIRQ1 JP14 PIAOinterruptAtoNMI 15 PIAOinterrptBtoIRQ 16 Closed PlA0inemupBtoNMI 17 PAlimemptAtoIRO JPl8 LinterruptAtoNMI JP19 _______ PIA LinterruptBtoIRQ1 20 Closed ________ PIA LinterruptBtoNMI JP21 JPIJP2 SCSI SASI bus parity Oddparity m cro 37 A 9 2 Table 31 0000 3422 Jumper Settings for OS 9 Version 2 4 2030 Computer Manual Revision 1 4 Page 38 Ox RNID 55 HS RN2 gt Sb a 04 02 So SE C1 SE eB 55 qd R2 RN4 cdi 05 E So ua 9 9 9 Sus 4 4 c sla 3944 4 ok Sc Sc S ED E Figure 12 0000 3422 SCSI S
16. IRQSautovectored 212 17601743 Closed IRQ4 vectored ____ 7 7027 12 Closed IRQ3vectored 17807 Open IRQ2autovectored 2122 9 0 40 Open 101 autovectored IACK sense selection J8 1 to J8 2 IACK when high 59 20393 0 2 to 103 O e a Sse A sux SEGRE Enable three state J11 1 to J11 2 Open IACK active fail signal selector nf 11 4 to J11 5 Open a SYCLK ir during gene Toe 2 2 11 7 to J11 8 Open No power PIT MEM field J3 does not exist wa Table 12 GESMPU 14A Jumper Settings for OS9 Version 2 4 2030 Computer Manual Revision 1 4 Page 18 E d m 8 LP A AL Pac Q ETT TT z us U33 vYEYX Wd WOE vd Bees ist C i518 THS CG NI 09S 1 410595 19 5958 FE NdWSaD Figure 5 2025 1020 GESMPU 14A Computer Card Memory Card Three different memory cards are used in the 2030 computer systems The first two use the same printed circuit board The 256 kilobyte board uses 32 8 kilobyte SRAM chips and has the Digalog P N 0000 2203 The 1 megabyte board uses 32 kilo byte SRAM chips and has the Digalog P N 0000 2213 The only way to tell the two cards apart is to identify the type of chip on the board The 1 megabyte configuration is the most popular 2030 Computer Manual Revision 1 4 Page 19 The last memory card used in the 2030 computer
17. NEE DI TE Pl a IATA P4 15 PGP 50 oue C Table 10 GESMPU14 A RS 232 Connector Table 11 Reset Abort Switch Connector Note J1 jumper must be open for external use of the abort switch Note that when setting the jumpers on most Gespac cards the jumper field is numbered like most integrated circuits i e in a U shaped pattern For further reference consult the GESMPU 14A data sheet Local Remote abort selector J1 1 to J1 2 Local abort switch J2 Internal External Tx and Rx clock J2 1 to J2 10 Closed Internal baud rate selector clock 102210123 Closed 7 Lo 09 pO Sto 2 6 Open ____ C C Open 1343101416 Closed Closed Closed 7 Closed C Aod ____ Mt Closed _ 5 Wom dosd EPROM access time selector bus J5 1 to J5 10 Open 450 ns access time system clock selector 8 MHz system AA 12 52980 pa 2030 Computer Manual Revision 1 4 Page 17 154057 Closed 155056 Je _ Real time clock power enable J6 1 to J6 2 Async Sync VPA field mode J7 1 to J7 18 Open VPA field 0 async Autovectored vectored interrupt selector 212 2 0 17 Open VPA field 1 async 212 3 0 46 Open field 2 async 212 137 41097 15 Closed VPA field 3sync 212 1J7 5107 14 Open _
18. OS9 68000 technical manual for a description of the INIT module RBF is required for any disk I O GESHDI is required to operate the SASI controller and S0 amp RB5400 are needed for the hard disk and floppy disk units SYSGO is required it is a simple endless loop which is actually the mainline program of the entire operating system The boot file is limited to 64K bytes which requires some of the necessary modules to be located in the boot loader EEPROM When the KERNEL starts 2030 Computer Manual Revision 1 4 Page 5 it will search memory for modules and add any it finds to the module directory The following modules are located in the boot loader EEPROM SHELL which is the command line interpreter CLOCK and TK68901 which implement the real time clock and MK68901 which is the console serial port driver The descriptor TERM which is for the console serial port is located in the boot file to allow its characteristics such as baud rate to be changed Any other modules that are desired may be loaded later When control is passed to the kernel it initializes the operating system tables and data structures and then transfers control to SYSGO In turn this transfers control to the command line interpreter SHELL This is more complicated than absolutely necessary but it makes OS9 adaptable to a wider variety of applications The shell is capable of reading command lines from the disk as well as from the terminal The file SO STARTUP is p
19. RQ4 205 Table 35 0000 2268 Other Interrupt Possibilities Table 36 0000 1568 Jumper settings for RS 232 Table 37 0000 1568 Jumper settings for RS 422 Note It 15 a Delco Electronics standard that t3 be set to RS 422 and all other ports to RS 232 2030 Computer Manual Revision 1 4 Page 44 Table 38 0000 2268 Jumper Settings for RS 232 t2 t3 t4 Setting Table 39 0000 2268 Jumper Settings for RS 422 Note It 15 Delco Electronics standard that t3 be set to RS 422 and all other ports to RS 232 For pin assignments of the G 96 bus connector please see the section titled G 96 Mother board Assembly Table 40 0000 1568 0000 2268 Output Connector Pin Out 2030 Computer Manual Revision 1 4 Page 45 0559138 c ups dig SE een AL TE 2 0049 Re 0049 0029 TE IIS TEE IIS e E y 74278 n _ ETE rere 2100 2611 Figure 14 0000 1568 1 Controller Assembly 2030 Computer Manual Revision 1 4 Page 46 J2
20. RS 232 port stays the same Whether a device is driving or receiving on a particular line is dependent on 1f that device is DTE or DCE Q ND 2 72 55 Q Z 2 5 Q 5 Q Q Q Q Z zzz Table 42 p Connector Pin Out 2030 Computer Manual Revision 1 4 Page 48 PA4 Table 43 kp Connector Pin Out Testhead Controller Assembly The Testhead controller card consists of data and address buffers address decoders and TBus optoisolator circuitry The TBus isolator is connected via shielded ribbon cable to the Digital motherboard in the Testhead The TBus provides address data and timing signals to the cards located in the Testhead The isolation provided prevents electrical noise from the computer system from interfering with analog measurements By using the Testhead Controller Assembly the Testhead is memory mapped into the MC68010 VMA space The Testhead occupies 256 bytes within this space Byte swapping is performed on the Testhead Controller Assembly such that the 8 bit TBus appears as contiguous bytes on the 16 bit G96 bus Only byte write and read commands may be performed within the TBus memory space Word write and read commands will generate bus errors The memory address that the Testhead Controller Assembly occupies is fixed at FBE900 through FBE9FF Jumpers were placed on the board allow the user to select which interrupt the TBus interrupt will be routed to Later engineering cha
21. port for printers a parallel IEEE 488 GPIB port for instruments and a port for the small 24 key pad Serial port TERM is physically located on the CPU board and serves the main or only user console Serial port T1 T2 T3 and T4 are located on the I O controller board and are for additional user terminals or any other purpose such as serial printers data networks bar code readers etc ports TERM and T1 T4 conform to EIA RS232 pinout and signal levels Baud rate character format and other operating characteristics are determined by the XMODE utility program The parallel port P implements a subset of the Centronix interface 8 data strobe and acknowledge and is compatible with most printers The XMODE utility may be used to set a time limit for acknowledge The IEEE 488 port G is described in a separate section 4 11 The keypad may be used two ways As a standard OS9 I O device KP it provides a subset of the ASCII character set including the digits 0 9 symbols amp etc letters a h and A H delete cancel and carriage return Alternatively the procedure KPscan N reads the instantaneous state of the keypad as a key number 0 23 24 for no key This permits the keypad to be polled at any time for the duration of a keystroke to be determined as well as its identity MASS STORAGE PERIPHERALS Four devices are used for file storage and backup the hard disk 50 floppy S1 streaming back up tape
22. the VPA space of the computer system and is determined by on board jumpers TMS9914A Registers 17 31 Interrupt vector register repeated 8 times Table 45 GPIB Controller Address Map JPI JP6 Base Address Selection VPAT 0100 _____ Closed 9060 O 21072 Closed 80040 Closed 80080 Open 80100 _____ S Closed 80200 416 Closed 80400 _JP7 JP11 Interrupt level selection 4 O u BEP Eo J Open ____ Lo pen Closed ____ Open ee sc ji JP12 JP14 Interrupt priority selection Closed 4 ES Ef Table 46 0000 1570 Jumper Settings for OS 9 V2 4 Note The 0000 1570 GPIB Controller Card shares an interrupt with the I O Controller Assembly in the OS 9 V2 4 configuration For this reason the GPIB Controller Card must be installed adjacent to and to the left of the I O Controller Card 2030 Computer Manual Revision 1 4 Page 51 Jumper IRQ1 IRQ2 IRQ 4 IRQ 5 Table 47 0000 1570 Other Interrupt Jumper Possibilities JPI JP6 Base Address Selection VPAT 0100 2179 Closed 00 040 Closed 0 24216 Open X 000 Closed 00 4 40 _JP7 JP11 Interrupt level selection 7 1 4 ____ MO Open __ Ip Open Open 21023 E Lo ma pen _JP12 JP14 Interrupt priority selection 3 Closed C
23. u ne u 36 DISK CONTROLLER OMTI 5400 39 CONTROLLER ASSEMBL Y 42 SBRIAE PORTS a et eec ies eet e e ech akaqa 42 PRINTER rou 42 MEMORY las re Ve sek eee eB cea 42 LOJINTERFACE CARD na eee vo eb vn vere SSS EF Rer TS 48 TESTHEAD CONTROLLER ASSEMBL Y 49 GPIB CONTROLLER ASSEMBL Y 51 MASS STORAGE PERIPHERAL S 56 HARD DRIVES PM cC EET 56 ELOPPY DRIVES irata tee e etti ise ted qaz 56 l2 NN HNOESCO DEN 57 PROCEDURE FOR INSTALLING 2ND HARD DISK ccccccceesceeeesssceceessececsscececseeeceesseceeseseceesaeeeceesaeesenseseesenses 57 TABLE 142030 MEMORY cts teret beh et tet ee ee e Shc ei le esee bte shes DR Pese del se te ede ee pore be due 1 TABTE 2 G96 INTERRUPT rest aan Ure Der b En ta 2 TABLE 3 INTERRUPT MODES nie
24. 2 AZ BZ we EZ Pe E 2 264 nates 8284 24 4 Er V pe 2 pe pa AS B3 3 ES F3 GS HMEZE magaga Es Q9 C DARE CO NES 1502 2030 1505 30 1500 2036 1530 3000 1500 1210 1500 2030 1500 2030 ae x wT XJ T A i M 54 m EA 4 54 4 HH62E4 EMEZG4 HHBIb4 Aus 264 Haze 1 O mE 26 S7 221 1860 3020 Figure 6 0000 2203 0000 2213 Memory For pin assignments of the G 96 bus connector please see the section titled G 96 Mother board Assembly 2030 Computer Manual Revision 1 4 Page 22 0000 2232 This G64 G96 form factor card allows the system to have 1 2 or 4 megabytes of no wait state static RAM It can also be configured for 1 2 or 4 megabytes of PROM The card accepts either 128 kilo byte SRAM or PROM chips for the 1 megabyte mode or 512 kilo byte SRAM or PROM chips for the 2 or 4 megabyte modes In the 2 megabyte mode the sockets for the SRAM PROM are half populated 512 kilo byte chips are placed in U1 U3 U5 and U7 In any of the selected configurations the address lines are routed through a PLD such that no gaps appear in the memory map When using the selection jumpers the user selects a card number To translate the card number into the base address multiply the card number by the memor
25. 2030 Computer Manual Revision 1 4 Copyright 1996 Digalog Systems Inc SYSTEM OVERVIEW 1 INSTALLATION 2 222282 RYE aq RO ENIM 2 RECEIVING INSPECTION aa e enne neue ed dens 2 POWER gana 3 ENVIRONMENTAL OPERATING CONDITIONS een 3 EXTERNAL CABLES AND CONNECTIONS eee teen 3 SEARTUPD e ETE DOS REIR I WI De EH 5 OPERATION 0 A aun dep mensem 6 CHARACTER VO DEVICES G aso naar anne 9 MASS STORAGE 8 00 lt esee ee a 9 G 96 MOTHER BOARD ASSEMBL Y 10 COMPUTER POWER SUPPLY SYSTENM 13 GESMPU14 A MC68010 MICROPROCESSOR MODUIE 15 MEMORY L rae ENS 19 00002203 000022 13 ii reete a Yaqa SB 20 MDC 23 DUAL SERIAL PORT CARD essen antenne ba Cu e ce een veo a Resa e ene 26 2000 3020 GESSIO 1B DUAL SERIAL PORT CARD nennen nete nnne eren entere nnns 26 0000 3220 0000 3520 DUAL SERIAL PORT CARDS nennen 32 SESTSASTHOST ADAPTER u a i eae
26. 5969 112 15968 Opn 864 67 4 4 65 66 Closed 209 Jona S OE PB Cosa O 4 pS 776 0 20 2 89 112 83588 0 0 7 Closed pod BS tO TRG Closed Z9 _ 5 5 112009 open 8 Open J9 4toJ9 7 Closed J10 Protocol selector channel 2 RS 232 DCE modem 10 020 00 Open 903107108 Closed Closed 050106 Closed is RS 422 terminator resistor J11 1 to J11 2 Open No resistor channel 1 J12 RS 422 terminator resistor J12 1 to J12 2 Open No resistor channel 1 2030 Computer Manual Revision 1 4 Page 27 Jumper Field Function Jumpers Setting Result J13 RS 422 terminator resistor J13 1 to J13 2 Open No resistor channel 1 J14 Protocol selector channel 1 J14 1 to J14 2 RS 232 DCE modem J15 RS 422 terminator resistor J15 1to J15 2 Closed Resistor channel 1 i J J channel 1 channel 1 channel 1 9 0 1 RS 422 terminator resistor J19 1 to J19 2 Open No resistor channel 1 J2 Protocol selector channel 2 J20 1 to J20 2 RS 232 DCE modem channel 2 J22 RS 422 terminator resistor No resistor channel 2 channel 2 J24 RS 422 terminator resistor No resistor channel 2 J25 RS 422 terminator resistor No resistor channel 2 J26 RS 422 terminator resistor No resistor channel 2 channel 2 J28 RS 422 termina
27. ASI Host Adapter Disk Controller OMTI 5400 The disk controller supports one QIC 02 streaming tape drive and up to three hard floppy drives in any combination The standard configuration is one 40 mega byte hard disk one 720K floppy drive and a cassette cartridge tape drive 2030 Computer Manual Revision 1 4 Page 39 Backup to the tape drive can be accomplished using one tape The OS 9 utilities Fsave and Frestore are recommended for this procedure Jumpers Function Jumper Setting Result WO SCSIControllerID_ ____ ____ ____ Scsim 0 o we fo oo 10020 po Open 3 Open 4 41905 5020 4211406 62020 E qu n y SWOT Closed W2 2 to W2 3 Closed W3 W4 Hard disk sector size 1312 bytes sector W3 W4 OpnoOpn 128 bytes sector W3 W4 O Closed Open 256 bytes sector ss Wawa Open Closed 512 bytes sector ____ W3 W4 ____ Closed Closed 1024 bytes sector W9 Notomboad o S S W12 W13 Notonboard __ Disabled Ready override Disabled 2030 Computer Manual Revision 1 4 Page 40 WIS woron ON J10 FDC9229 J7 Com Ew QICO2 PARITY Q ENC DEC VCO OMT 5070 CHIP SEQUENCER BUFFER 5050 CHIP OMTI 5060 CHIP 2207330 3 4 J1 Sea TERMINATOR Z8 MICROPROCESSOR wif HOST PARITY NOTE THE FARRICATION assy
28. Address line A6 SPIO Addessle A7 JPll Addressline A8 Addessle A9 3 Open pT RQ5selected 1 04 Open AAA Closed Open 2 2030 Computer Manual Revision 1 4 Page 32 Jumpers Function Jumper Setting Result Opn 224 pS Opn Pd Open 2 BA Ee E JP19 20 22 RS232 422 mode select RS 232 NN PS 9 jose _ 18020 jo A JP23 Open E E E 3 Table 27 0000 3220 0000 3520 Jumper Settings for RS 232 OS9 Version 2 4 Jumpers Function Jumper Setting Result _JP7 13 ____ Address Selectors 7F0 7FF in the VPA address range Addrsslie A3 JP7 Addrsslie A4 _______ 8__ Open 50 Addrsslie A5 JP9 Open 50 Addrsslie AG JPI0 Open 50 Addessle A7 PUL Open 1000 Address line A8 JPI2 Open 500 A9 JPI3 Open 540 JP14 18 Interrupt level selection IRQ 5 selected JP1 2 4 6 RS232 422 mode select RS 422 channel 1 1 Closed 0 1 12 Open Closed Open ______________ 6 Clsd JP19 20 22 RS232 422 mode select RS 422 24 channel 2 Lo PI Closed Lo 0 2 22 Ce 22 Opn f Closed Table 28 0000 3220 0000 3520 Jumper Settings for RS 422 OS9 Version 2
29. IRQ1 2 PIACHB Closed PIA O interrupt BtoNMI J2 PIAO NB Open PIAlinteruptAtoIRQ J2 PIAIIA Open PIATinteruptAtoNMI J2 PIAI NA Opn O PIAlinteruptBtoIRQ1 J2 PIAIIB Closed PlAlinemupBtoNMI J2 PIAI NB Opn 4 SCSUSASIbuspaiy Odd parity 0 4 ____ _ __ ____ __ 77 Oper ges _ Table 30 2000 3022 GESHDI 2A Jumper Settings for OS 9 Version 2 4 2030 Computer Manual Revision 1 4 Page 36 NE One un anc 1789 sine 7745 sn 1 E AS A4 AS A6 A AT A8 A9 0 Yid e vif L Wid Figure 11 2000 3022 GESHDI 2A SCSI SASI Host Adapter Jumpers Function Jumper Setting Result _JP3 JP9 Base Address Selectors 681 68F in the VPA address range d Address line A6 080 Address line A7 100 ES Addressline A5 JPS Closed 040 2030 Computer Manual Revision 1
30. PER POSSIBILITIES eene 52 TABLE 48 0000 1970 JUMPER SETTINGS FOR 05 9 2 4 eene enne en enne enne en eere enne 52 TABLE 49 0000 1970 OTHER INTERRUPT JUMPER POSSIBILITIES eene 52 TABLE 50 0000 1570 0000 1970 J1 CONNECTOR PIN OUT enne enne nennen enne 53 TABLE 51 2000 3017 HARD DRIVE ADDRESS SELECTION nn 56 TABLE 52 2000 3016 FLOPPY DISK DRIVE JUMPER SETTINGS enne 56 TABLE 53 NEC D3142H S2 JUMPER POSITIONS eee n entr nene enne nens 57 TABLE 54 TOSHIBA M222XD2 S2 JUMPER POSITIONS 57 System Overview Control of the 2030 Series systems is based on the Motorola MC68010 microprocessor running Microware Systems OS9 multitasking multiple user operating system This combination provides the ideal hardware and software foundation for the real time control and computing requirements of the 2030 systems The back plane used to communicate to the individual boards within the computer system 1s the Gespac G96 bus The standard computer system hardware configuration includes the MC68010 computer card up to 8 M bytes of SRAM memory a SASI SCSI interface a 40 M byte hard disk cartridge streamer tape drive floppy disk drive and I O controller card The I O controller card provides 4 serial ports a printer port and operator keypad port Op
31. SDD floppy disk Formatted storage capacity is about 644 kilobytes NOTE Do NOT use double sided high density DSHD disks with this drive While appearing to work this floppy disk will not retain data reliably This floppy disk drive requires that terminator resistor pack RAT be installed for proper operation Result Address 1 not selected Position DO Open Address 2 selected Fee Ul Closed 4 Uo Open FG Closed gt aan Jumper Name MOTOR ON input active Closed Table 52 2000 3016 Floppy Disk Drive Jumper Settings For the FD55GFR Jumper settings please consult the factory 2030 Computer Manual Revision 1 4 Page 56 MAINTENANCE Procedure for installing 2nd hard disk 1 Remove the 68000 computer rack from the system 2 Remove the right rear panel of the computer This is the panel that contains the power switch There is no need to disconnect the wires 3 The hard disk assembly should now be visible from the back of the computer Remove the hard disk assembly according to the directions on page 25 of chapter 6 of the 2030 analog tester manual Be sure to note the positions of all cables 4 The hard disk just taken out is known as S0 The one that is going to be installed will be known as S2 If SO is a NEC D5146H or D3142H check to see that S1 1 is in the off position 5 The jumpers for S2 NEC D3142H are Table 53 NEC D3142H
32. ard sssi ERE E ES CE AVR VEA O ETE NIC Table 22 GESSIO 1B Channel 1 15 Connector Pin Out Note Signals with a are not connected under normal operation pue E CE ETA o o __ P 13 _ O P4l4 TxDR RS 22 Table 23 GESSIO 1B Channel 2 t6 Connector Pin Out Note Signals with a are not connected under normal operation For pin assignments of the G 96 bus connector please see the section titled G 96 Mother board Assembly Note that when setting the jumpers on most Gespac cards the jumper field is numbered like most integrated circuits i e in a U shaped pattern For further reference consult the GESSIO 1B data sheet 2030 Computer Manual Revision 1 4 Page 26 Jumper Field Function Jumpers Setting Result TTY power supply 12 volts J1 1 to J1 2 Open 12 volts supplied from external supply Po TSE TTY power supply ground J2 1 to J2 2 Open Ground supplied from external supply o AA Cloned Se i TTY mode selector channel 2 J3 1 to J3 8 TTY mode for channel 2 is DCE po BR to 37 Closed po 433100 6 Closed Ba JA TTY mode selector channel 1 J4 1 to J4 8 Closed TTY mode for channel 1 is DCE Closed 2 M3teM 6 Closed cos ene 52959 Oe 2 58 Open 557 Closed 2 155 5 6 Closed J6 Protocol selector channel 1 76 1 to J6 10 Open RS 232 DCE modem 8
33. arranty at the beginning of this manual 2030 Computer Manual Revision 1 4 Page 2 The Emulator is shipped fully operational apart from the systems connections which must be made in accordance with Section 3 13 However a careful inspection should be performed to ensure functionality POWER REQUIREMENTS The Series 2030 CPU requires 115 VAC A standard power cord is included Care must be taken to ensure that the unit is grounded properly If grounding outlets are not available adapters with grounding connections must be used ENVIRONMENTAL OPERATING CONDITIONS The Series 2030 CPU is designed for use between 10 and 40 degrees Celsius A cooling fan is mounted on the front panel of the unit to provide cooling for the system s electronics Care must be taken to ensure that fan openings remain uncovered for proper air flow DAMAGE may occur if the filters are not periodically cleaned EXTERNAL CABLES AND CONNECTIONS Depending on the system configuration cable connections will need to be made between some or all of the following devices Computer Terminal Printer Keypad Testhead Emulator and GPIB Instruments 2030 Computer Manual Revision 1 4 Page 3 Power inlet E USE NLY WITH 258V FUSES O BISCGNNECT POWER BEF RE REPLACING FUS S SID T1 serial port T2 serial port T3 serial port
34. assed by SYSGO to the shell as its first set of commands This is where most system customization takes place The clock is set from the battery powered calendar additional I O modules are loaded terminal port parameters are adjusted time sharing consoles are activated the message of the day is displayed etc In short any command can be given to or any program can be run by STARTUP If and when these commands have all been executed the shell then takes input from the console Time sharing consoles e g T1 may be activated by the command SHELL lt T1 gt gt gt T1 amp which will not require a login password However if the user leaves the shell by typing control Z no additional login sessions are possible Usually these consoles are activated with the command TSMON T1 amp which uses CMDS LOGIN and SYS PASSWORD to request the user s ID If the user leaves the shell future login sessions are still possible References OS9 68000 user manual sections 1 2 3 3 5 OSIGEN TSMON commands technical manual sections 1 1 2 5 1 For creating text files such as Startup see BUILD and EDT commands or SCRED screen editor user s manual OPERATION Microware sOS9 68000 operating system 1s an advanced multitasking operating system designed for high performance in real time system applications It combines significant new operating system concepts with the overall architecture of Unix yet OS9 68000 is by far smaller and more e
35. device or in a subdirectory DSAVE produces a shell procedure file which may be viewed and edited before execution to copy a particular list of files to a target device for backup purposes For backing up the hard disk the command BSTREAM may be used This will display the tape ID block 1f the tape has been used previously and prompt for an R restore or B back up command Bstream is limited to backing up 40Mb or less hard disks as it does not support multiple volume backups An alternative way of backing up the system s hard disk is to use the Fsave command This program does a file by file backup of the hard disk structure and files and supports multiple volumes tapes if a hard drive larger than 40 MB needs to be backed up Fsave uses the descriptor mt0 Other tape operations may be accessed through the tape utility 2030 Computer Manual Revision 1 4 Page 9 provided by Microware They include erasing rewinding reading and writing tapes Please refer to the Microware manual set for more information on the tape utility When the equipment is to be moved stored or transported it is recommended to park the hard disk heads on a reserved landing zone of the disk surface The command BPARK is used for this purpose Before a new hard disk or floppy can be used it must be formatted which provides it with sector address marks and a blank directory structure In addition if a device is to be used as the source of the boot file see this manua
36. ecting even or odd byte addresses Thus Al on the MC68010 is connected to 0 the G 96 bus A2 to Al to A2 etc A23 of the G96 bus is driven low and is unused by the GESMPU14 A board For further information refer to the G 64 Bus Specifications Manual Revision 3 0 June 1986 Pin Number Power Supply 12V 5V STANDBY SV Table 5 G96 Mother board Power Suppy Connector Pin Out 2030 Computer Manual Revision 1 4 Page 10 co 03 1 1 1 B9 AS 9 AT CIO 80 0 BGRT cu 1 UDS LDS CI2 2 BGACK 12 HALT C13 BIA RESET 4 cis BIS DTACK C16 C17 C18 C19 C20 Co 1 1 B26 D7 _____ 26 ps CO 29 5STANDBY 9 PWF 1 C0 CBB ax aso 0 Table 6 G 96 Bus Connector Pin Out 2030 Computer Manual Revision 1 4 Page 11 O ur or O O 6r O O er In or sp vn er O O zr O O O O or O Figure 3 0000 2230 G96 Mother Board 2030 Computer Manual Revision 1 4 Page 12 Computer Power Supply System The 2030 computer chassis is powered from one power supply with multiple outputs This power supply provides 5 volts 12 volts and 2 separate 12 volt supplies 115V AC power 50 60 Hz is provided to the supply via a combination pow
37. er entry module fuse holder and line filter The entry fuse is a 3 amp slow blow fuse 2030 Computer Manual Revision 1 4 Page 13 4000 1120 14 L 2 Q amp o REAR VIEW Q O n Figure 4 0000 2067 AC Power Supply Harness Installation 2030 Computer Manual Revision 1 4 Page 14 5 volts G GND I2vodts GND Unused S 5 volt sense line 4 GND sense line 6 Table 7 DC Power Supply Harness Connections Note Below is pictured a hard disk connector on the DC harness GESMPU14 A MC68010 Microprocessor Module The GESMPU14 A is high performance computer board based on the MC68010 32 bit microprocessor It includes a battery powered calendar clock asynchronous serial port sockets for up to 128K bytes of PROM a small EEPROM with 256 4 bit words and a socket for an optional NS16081 arithmetic co processor The MK68901 multifunction peripheral provides the serial port four user programmable timers and interrupt vectoring for the other on board functions The provide boot strap software that loads the OS 9 operating system from the SASI disk controller They also contain a monitor for bus error and abort push button exceptions The MC68010 microprocessor requires a DTACK signal data transfer acknowledge
38. fficient than Unix OS9 68000 supports modular programming techniques that multiply programmer efficiency and dramatically improve software maintainability Its tree structured directory system and memory module format allow dynamic linking of standard library or custom modules together to form an overall application program Microware s BASIC combines all the standard BASIC statements with advanced features such as PASCAL type loop constructs and data structures It is procedure oriented supports modular programming and is totally integrated into the OS9 modular software environment Procedures may call each other or themselves even using automatic parameter passing External procedures written in Basic09 C or assembly language can be mixed freely and interchangeably Most of the system utilities that are available through the Shell console command interpreter are described in the Microware OS9 68000 User s Guide This manual also describes the Shell itself and the OS9 file system Many of the same language or equivalent utilities are accessible in assembly language through system service requests using a trap instruction These calls are described in the OS9 68000 Technical Manual This manual is also useful to advanced Basic09 programmers who need detailed knowledge of the I O system memory management and process scheduling Microware BASIC has its own manual The section describing external procedure calls the RUN statement is of i
39. gt o 20 U U S S D LI E E 2 ES JP4 JP5 O S JP6 JP7 JP8 JP9 SS au BARSE 29 Figure 18 0000 1970 GPIB Controller Assembly 2030 Computer Manual Revision 1 4 Page 55 Mass Storage Peripherals Hard Drives The hard drive used most in the 2030 Computer was either the NEC D5146H or the NEC D3142H The two drives used have similar specifications Earlier models used a Teac drive The NEC drives have a storage capacity of 40 megabytes The first hard drive installed into the 2030 Computer must be addressed as unit number 1 The second hard drive must be addressed as unit number 3 Only two hard drives can be supported in the 2030 Computer 1 On Address 1 selected 2 Off Address 2 not selected 3 Off Address 3 not selected SW2 572 14 Off Address 4 not selected Table 51 2000 3017 Hard Drive Address Selection The ST 412 bus used for the hard drives requires termination on the last drive on the cable Digalog uses a serial configuration for multiple drives This means for the last drive SW1 1 needs to be set to the off position and SW2 through SW 8 needs to be set to the on position For all other drives SW1 1 through SW1 8 need to be set to the off position Floppy Drive Most of the 2030 Computers use a Teac FD 55FR 511 U floppy disk drive Some use a FD55GFR model This floppy disk drive uses a 5 25 double sided double density D
40. is the 0000 2232 card While this card may be configured up to 6 ways only one has been used This configuration is the 1 megabyte configuration 0000 2203 0000 2213 This is a no wait state static RAM board using 32 8 bit memory chips surface mounted on one side of the card When equipped with 8 kilo byte chips the total capacity is 256 kilo bytes When equipped with 32 kilo byte chips the capacity is 1 megabyte per board In any system which contains both 256 kilobyte and 1 megabyte memory boards the 1 megabyte boards must be addressed first followed by the 256 kilobyte boards Jumper Field Function Jumpers Settings Result JP8 Board capacity AtoB Closed 256 kilo byte Open ee hs BR c d 0 Table 13 0000 2203 Jumper Settings Capacity Table 14 0000 2203 Jumper Settings Address Range First Eight Settings Closed hc due iet ati c d s ESTOS ES Table 15 0000 2213 Jumper Settings Capacity 2030 Computer Manual Revision 1 4 Page 20 Table 16 0000 2213 Jumper Settings Address Range First Eight Settings 2030 Computer Manual Revision 1 4 Page 21 1 Di H1 K1 HH IRA MIEL HeE254 C 1 QUEM Mm Lit fin tnc 4536 700 1500203 15050 7035 lt gt uw i pur 2 kaj
41. l section 3 14 the OS9GEN command must be used to properly initialize it References OS9 68000 user manual ATTR COPY DEL DELDIR DIR DSAVE FORMAT FREE MAKDIR OS9GEN and RENAME commands chapter 4 the OS9 file system G 96 Mother board Assembly The G 96 bus offers 8 and 16 bit data bus capability synchronous and asynchronous data transfers single Euro board mechanical standard and a high reliability DIN 41612 connector Twenty four address lines and a signal named allow a 32M word 64M bytes address space The GESMPU14 A computer card Digalog P N 2025 1020 can access up to 16M bytes The interrupt structure includes 6 interrupt lines 1 interrupt acknowledge and a daisy chain implementation that allows both vectored and non vectored interrupts to be used at the same time The G96 bus must be terminated at one end with 3 volt 132 ohm resistor networks These networks are included on the EMBus controller card Digalog P N 0000 2211 Ifthe system is an analog test system the termination is provided by a terminator card Digalog P N 0000 2007 Terminators are located in the far right hand slot Only the power lines and interrupt daisy chain lines are without terminators VPA valid peripheral address is the address strobe for the peripheral area VMA is used for all other address validation and IACK are mutually exclusive Address lines A0 A23 refer to word addresses with UDS and LDS sel
42. lose Lo 4 pen Table 48 0000 1970 Jumper Settings for OS 9 V2 4 Note The 0000 1970 GPIB Controller Card shares an interrupt with the I O Controller Assembly in the OS 9 V2 4 configuration For this reason the GPIB Controller Card must be installed adjacent to and to the left of the I O Controller Card Jumper IRQ4 IRQ2 IRQ3 IRQ4 IRQS JP2 Table 49 0000 1970 Other Interrupt Jumper Possibilities 2030 Computer Manual Revision 1 4 Page 52 Table 50 0000 1570 0000 1970 J1 Connector Pin Out The connector J1 of the GPIB Controller Assembly does not have a normal pin numbering sequence Pin 2 is to the right of pin 1 and pin 11 is below pin 1 For pin assignments of the G 96 bus connector please see the section titled G 96 Mother board Assembly 2030 Computer Manual Revision 1 4 Page 53 6192 0014 3 8 zen e ODE ODs EL 5 eic 215145 1900 1400 M a S 2100 2811 Figure 17 0000 1570 GPIB Controller Assembly 2030 Computer Manual Revision 1 4 Page 54 2 O Sc Sc C1 E u Pi e 2 O LI U LI U
43. m JP16 17 E o Bl JP18 JP13 Figure 10 0000 3220 Dual Serial Port Card 2030 Computer Manual Revision 1 4 Page 35 SCSI SASI Host Adapter The host adapter is a simple G96 card with two MC6821 PIAs to implement a SASI SCSI bus The bus is carried by a 50 wire ribbon to the disk controller The disk controller is mounted on the hard drive Access to the card is permitted at odd addresses only The base address is located in the VPA space of the computer system and is determined by on board jumpers Relative Address Device Register 9 DDRA DRA B DDRBDRB D JPAI ____ Table 29 2000 3022 0000 3422 SCSI SASI Host Adapter Memory Map For pin assignments of the G 96 bus connector please see the section titled G 96 Mother board Assembly Jumpers Function Jumper Setting Result _______ 681 68F in VPA address range ______ EZ i ______ i Addressline J3A6 080 AddrsslineA7 13 7 Closed 100 Addressline A8 3 A8 50 Addrssline A9 13 A9 9400 72 level selection ________ Open ________ J2 B_ Optoncde ________ D PlA0intmuptAtoIRQ1 J2 PIAOIA PIA 0 interrupt A to NMI J2 PIAO NA Open PIAOinterruptBto
44. nge orders hardwired the interrupt to the G96 bus No jumpers should be installed on the jumper field For pin assignments of the G 96 bus connector please see the section titled G 96 Mother board Assembly Connector Pin Signal Connector Pin Signal 1 51144 ___ y 9 1 TRESET 2 00 GND 2030 Computer Manual Revision 1 4 Page 49 Connector Pin Signal Connector Pin Signal 5 5T 5 Table 44 0000 2563 Output Connector Pin Out t RNA RN2 RNI ae GUS aS si 2 RNG RNIO je r qup pee E J ETJd F44 H4DIGALOG SYSTEMS INC Sess 2030 TESTHEAD CONTROLLER ASSY JPCB 0000 2562 ASSY 0000 2563 eee elo EXE sog Fi dvds Sus 8 PUT a Shs RNB RN RNG RNG y LI LI LI E E B C30 LI U 5 ca e C28 E amp 5 5 3 L z 023 als LI 3 C28 LI LI LI LI LI m amp s 5 a S 621 U LI E 5 5 JPI JPZ
45. nterest not only to users who write their own assembly language procedures but also to anyone desiring more insight into the nature of the Digalog extensions to Basic09 which interface with the test system 2030 Computer Manual Revision 1 4 Page 6 hardware Finally the Relocating Macro Assembler R68 L68 and screen editor UMacs are described in their own separate manuals a lower performance text editor Edt is described as a utility in the user s manual Although Microwave BASIC has its own interactive source text editor it is possible to write source programs using UMacs UMacs can also used to write and maintain the Startup file and any other user command files Sys Password file used by Login assembly language source files etc 2030 Computer Manual Revision 1 4 Page 7 0 D c a c mmm E Reset switch C C 6 C C Floppy disk drive S1 Tape drive mto s3 S amp Figure 2 2030 Computer Front View 2030 Computer Manual Revision 1 4 Page 8 CHARACTER I O DEVICES The standard character I O devices are of four types asynchronous bit serial ports for terminals and modems a parallel Centronix type
46. op bit times at mark level Software selection also allows for selection of standard baud rates at 75 110 134 5 150 300 600 1200 1800 2000 2400 4800 9600 and 19200 Selecting external baud rate will enable the internal timer but not program the frequency The frequency may be set by writing to the counter register of the MC68681 The value written is N 115200 rate The most significant byte of n is written to the chip address 12 and the least significant byte to address 14 Note that 1f both ports in one chip are set external then both will run at the same rate DTR handshake is not implemented Instead software provides for transmission to be stopped and started by receipt of the XOFF 13 and XON 11 characters Printer port A Centronix type parallel port with active low STB and ACK is provided by a 6522 VIA The other Centronix control signals are not implemented Software allows for a timeout error to occur after a programmable delay if ACK does not occur The VIA used for the printer port also provides an interface for a 24 key matrix encoded keypad Memory Map Access to the card is permitted at odd addresses only The base address is located in the VPA space of the computer system and is determined by on board jumpers Relative Address Device Device Descriptors 01 1F MC68681 1 2 21 3F MC68681 2 T3 T4 41 5 MC6522 P KP 61 7f MC6522 Repeated 64 times Vector register 2030 Com
47. puter Manual Revision 1 4 Page 42 Jumpers Function Jumper Setting Result _JP1 JP3 Base Address Selection Closed 900 4 00 _JP7 JP11 Interrupt level selection 1 Lo 7 Open Lo JP on m6 ded x Oe CPAJP6 Interrupt priority selection A ____ i e ded Om 4 OOO rec Closed 0 1 Table 32 0000 1568 Jumper Settings for OS 9 V2 4 Note The 0000 1568 I O Controller Card shares an interrupt with the GPIB Controller Card in the OS 9 V2 4 configuration For this reason the I O Controller Card must be installed adjacent to and to the right of the GPIB Controller Card Jumper IRQ1 IRQ2 IRQ3 1804 IRQS Table 33 0000 1568 Other Interrupt Possibilities JP23 Base Address Selection 12211 VPA 000 JP25 NE 0100 er 0200 2030 Computer Manual Revision 1 4 Page 43 172 50400 JP27 Interrupt level selection IRQ 4 JP31 8 Open 09 Open 7 Open _____ Bm Closed YO Ope Interrupt priority selection ____ 2 connected disconnected Table 34 0000 2268 Jumper Settings for OS 9 V2 4 Note The 0000 2268 I O Controller Card shares an interrupt with the GPIB Controller Card in the OS 9 V2 4 configuration For this reason the I O Controller Card must be installed adjacent to and to the right of the GPIB Controller Card Jumper 802
48. r N alada aver Force e te aces eases 2 TABLE 4 PERIPHERAL ADDRESSING MODES eene nenne tete nnns sen ente tense 2 TABLE 5 G96 MOTHER BOARD POWER SUPPY CONNECTOR PIN 10 TABLE 6 G 96 BUS CONNECTOR PIN OUIT nn 11 TABLE 7 DC POWER SUPPLY HARNESS CONNECTIONS ener ea 15 TABLE 8 GESMPU14 A MEMORY 1 01 00000000000000000000000000100000 16 TABLE 9 MK68901 TIMER INTERFACE 17 TABLE 10 GESMPU14 A RS 232 CONNECTOR 17 TABLE 11 RESET ABORT SWITCH CONNECTOR esee nnns enne 17 TABLE 12 GESMPU 14A JUMPER SETTINGS FOR OS9 VERSION 2 4 18 TABLE 13 0000 2203 JUMPER SETTINGS 20 TABLE 14 0000 2203 JUMPER SETTINGS ADDRESS RANGE FIRST EIGHT SETTINGS 20 TABLE 15 0000 2213 JUMPER SETTINGS 00000000000000000000000000000100000 20 TABLE 16 0000 2213 JUMPER SETTINGS ADDRESS RANGE FIRST EIGHT SETTINGS 21 TABLE 17 0000 2232 CARD TYPE
49. rror which are handled in the EPROMs are assigned values starting at 00000040A and incremented by 10 In turn between 040A and 0DEB a 10 byte routine is installed for each vector These short routines consist of the instructions PEA xxxx JMP yyyyyyyy The reason for having the original vectors essentially point to jump instructions is to allow implementing OS9 on hardware which does not permit the original vectors to be in RAM The jump instructions provide a second level of vectors which will always be in RAM and thus dynamically configurable by the operating system The loader does not need to initialize the jump addresses That is done later by the OS9 kernel using its own F IRQ service request The PEA arguments start at 000C and increment by 4 and thus are equal to the original vector offsets The 68010 automatically stacks the vector offset but OS9 was designed for the 68000 which did not The loader then determines the amount of RAM in the system and creates a linked list of RAM blocks OS9 was designed to work with noncontiguous memory blocks but our loader only recognizes the contiguous block starting at location 0 so the linked list is trivial This is when the message DIGALOG SYSTEMS INC is displayed The loader requests the SASI interface to read logical sector number zero of logical unit number zero the hard disk OS9 disks contain the boot file location in bytes 15 17 of this sector and the boot file size in bytes 18
50. tes 145 3 to J42 Open 14 ve 5 to J42 Open 12 2030 Computer Manual Revision 1 4 Page 29 Jumper Field Function Jumpers Setting Result J42 6 to J42 Open 11 J42 8 to J42 9 10 11 0 0 143 5 to J43 8 143 6 to 143 7 Interrupt operating mode J44 1 to J44 2 with DTACK signal Interrupt mode selector J45 1 to J45 IACK Active high 1 po 945 210145 9 1453058 po 45 41045 7 J45 5 to J45 6 Closed used when board is vectored irq Table 24 GESSIO 1B Jumper Selections OS 9 Version 2 4 1 J43 4 to J43 9 Pp EA EH 1 i E EA 2030 Computer Manual Revision 1 4 Page 30 HL 0ISS38 sin ZH va lac vd O Haras Figure 8 2000 3020 GESSIO 1B Dual Serial Port Card 3 4 Uh C Td 2030 Computer Manual Revision 1 4 Page 31 0000 3220 0000 3520 Dual Serial Port Cards P3 15 TxClock P3 16 P3 17 RxClock P3 18 Is ee P3 19 P3 20 Table 25 0000 3220 0000 3520 Channel 2 t6 Connector Pin Out Table 26 0000 3220 0000 3520 Channel 1 t5 Connector Pin Out For pin assignments of the G 96 bus connector please see the section titled G 96 Mother board Assembly Jumpers Function Jumper Setting Result JP7 13 Base Address Selectors 7 0 7FF in the VPA address range Addesslie A3 7 Open Addressline A4 ___ Addesslie A5
51. tional cards for the computer system include a IEEE 488 controller and local area network interface Digital test system emulator modules are interfaced to the computer system through the EMBus controller board The EMBus controller supports up to 6 emulator modules The TBus controller board provides the interface to the analog Testhead The TBus controller maps a section of the MC68010 memory for use by the boards of the Testhead This is accomplished by extending the data and address buses of the G96 bus through optically coupled buffers to the analog Testhead Start End Description FBEA00 FCFFFF Available for RAM FD8261 write 1 to remove ROM from low RAM area 8808281 ______ SMC8l36baudrategenerar Table 1 2030 Memory Map Board IRQ Vector Address Device I O Mode Vector Register Testhead Controller 7 31 FBE900 AMSint N A memory No autovector pore c read Lo IEEE sp write 70 FD8201 abort Async Yes 2 1 clock 77 FD8201 tick Async Yes Lj rac Dual Serial Port Card FDO7F1 Yes async mode 2030 Computer Manual Revision 1 4 Page 1 Board IRQ Vector Address Device I O Mode Vector Register 129 5 075 as ___ Syne ______ Yes async mode Controller 4 540 SFDOOO 1 8 12 80 2 X FD0021 3G Yes 12 81 X J FD003 4 X 82 FD0041 p Po 82 FD041
52. to complete each address cycle On this board an 8 microsecond timer will generate a bus error if the DTACK signal does not occur within this time The faulted cycle will be rerun up to 8 times automatically by on board logic before the MC68010 is allowed to fetch the bus error vector and initiate an exception Each retry is preceded by a 100 millisecond delay making the systems very robust in surviving power transients Once the bus error exception is initiated the system will enter the bus error monitor It is advised that the user write down the information displayed on the screen so that the information is available later while debugging the system A hardware reset is usually the only method that can be used to recover from this error condition 2030 Computer Manual Revision 1 4 Page 15 The system clock rate is 8 MHz A machine cycle requires at least 4 clock cycles 8 states With static RAM the CPU can maintain 16 bit memory transfers at 2 MHz INT1 through INTS5 are assigned hardware interrupt levels 1 5 which may be vectored or autovectored Level 6 is always vectored by the MK68901 which handles the serial port abort button and PWF power fail interrupts NMI nonmaskable interrupt is connected at level 7 and is always autovectored On board logic decodes a 2K byte block of addresses for peripherals Address locations in this area use the address qualifier VPA Within this 2K byte block 4 blocks of 512 bytes may be individuall
53. tor resistor No resistor channel 2 __ 129 3 10 1294 Open O 130 3 to 30 4 Open 8 3 to 1314 Open 1323101324 Open No three state RS 422 J33 RS 485 three state control J33 1 to J33 2 Open channel 1 83 2 to 133 3 Closed J34 TTY source polarity selector J34 1 to J34 2 Open Parallel channel 2 PA 40343 Closed O TTY source polarity selector J35 1 to J35 2 Open Parallel channel 1 11520353 Closed RS 485 three state control 36 1 to J36 2 Open No three state RS 422 channel 2 1362107363 Closed J Baud rate selector channel 1 J37 1to J37 Closed Baud rate by software selection 18 92 9 Opn 2030 Computer Manual Revision 1 4 Page 28 EN Field TE an L 3 to J37 Wu 4 to J37 Open 15 J37 5 to J37 Open 14 13 p 7 to J37 57 8 to J37 Open 11 J37 9 to J37 Open 10 Baud rate selector channel 2 138 1 to J38 Baud rate by software selection 18 nm 2 to J38 De 3 to J38 Open 16 J38 4 to J38 Open 15 pe 8 to J38 Open 11 J38 9 to J38 Open 10 Sync full speed selector J39 1 to J39 2 Open Normal baud rate output clock channel 1 J39 2 to J39 3 J40 Sync full speed selector J40 1 to J40 2 Open Normal baud rate output clock channel 2 J40 2 to J40 3 nae selection J42 1 to J42 Closed 7FF in the field 16 odd by
54. y capacity of the card When using the selection jumpers on the card it should be remembered that you are selecting the card number To translate the card number to the base address multiply the card number times the memory capacity of the card Examples Card number 0 4 megabyte capacity 000000 400000 000000 Card number 1 4 megabyte capacity 000001 400000 400000 Card number 3 1 megabyte capacity 000003 100000 300000 When placing memory cards of mixed capacity in the same system the following practice is recommended Place the largest capacity card e g 4 megabyte lowest in the memory map i e 000000 Place the next largest capacity card in the memory map following the last address of the first card Continue placing successively lower capacity cards in the system with addresses following the previous card An example follows Card Number Size Address Range 0 4 megabyte 000000 3FFFFF 2 2 megabyte 5400000 5FFFFF 6 megabyte 600000 7FFFFF Note that even though there are not six 1 megabyte cards in the system the 1 megabyte card had to be selected as card number six to get base address 600000 The physical location of the cards in the rack are irrelevant with the exception of the chain in and chain out jumper This jumper is used to connect or separate cards on the same interrupt vector Memory type ROM or JP1 Open Card selected for RAM RAM Chain in Chain out Chain in not connected to chain out
55. y jumpered for either asynchronous transfer using DTACK or synchronous transfer using the 1 MHz E clock When the computer board is reset the on board EPROM will overlay the lowest block of memory addresses including the vector table as well as appear at the EPROM addresses During system initialization the software will set an on board latch to remove the EPROM from the low addresses and permit access to RAM instead There are three LEDs on the front edge of the board The red indicates the supervisory mode from the MC68010 function code The yellow indicates a bus error retry The green indicates a microprocessor halt Only a hardware reset will restart a halted microprocessor The yellow LED will also light during a synchronous data transfer When the bus timer does time out and lights the LED the MC68010 ignores the BERR signal during the asynchronous transfer Start End Description SFD8261 ______ Write I to remove ROM from low RAM area 808281 ______ SMC8136 baud rate generator Table 8 GESMPU14 A Memory Map FD0000 FDOIFF Peripheral Block 0 512 bytes For pin assignments of the G 96 bus connector please see the section titled G 96 Mother board Assembly 2030 Computer Manual Revision 1 4 Page 16 Table 9 MK68901 Timer Interface Connection Note The above connector is normally not used as part of the 2030 tester configuration Connector Pin Signal Connector Pin Signal
Download Pdf Manuals
Related Search