CAN IP (precan_plb46), v1.0 - With PLB v4.6 interface Prevas AB
Contents
1. ISE 10 1 03i Product Specification CAN Controller precan_plb46 v1 0 User logic instantiating the PLB CAN controller I gt Master PLB Signals Addr precan_irq Optional CAN CORE Loop mode BIT Tos from ERROR CAN PHY DETEC off chip BAUD PRE SCALER Figure1 CAN Controller IP Block diagram Functional Description The figure above shows a high level block diagram and the major data flow of the CAN Controller The TX and RX signals should be connected to an external CAN transceiver chip A description of the sub modules follows IPIF The connection of the CAN controller to the PLB bus is provided by a PLBV46_SLAVE_SINGLE IPIF module from Xilinx This block provides a seamless interface slave port to the PLB bus for easy integration of user peripherals with Xilinx MicroBlaze and IBM PowerPC in Xilinx devices A preconfigured IPIF module is integrated together with the Prevas CAN IP The IPIF module is configured to support the functions available in the CAN Controller CAN core The CAN core is responsible for all transfer layer functions of the CAN protocol and consist primarily of a control unit bit stream processor error handler and bit synchronization unit Control unit The control unit is supervisor of the other modules in the CAN core and handles the overall node behavior depending on the node state i e if the node is in init mode error active error passive or bus2. Prevas Prevas AB PO Box 4 Legeringsgatan 18 SE 721 03 V ster s Sweden Phone 46 21 360 19 00 Fax 46 21 360 19 29 Email johan ohlsson prevas se URL www prevas se Features E Compliant with ISO 11898 1 CAN 2 0B protocol Supports bus speeds above 1 Mbit s Overload frames on CAN bus are recognized and handled but not transmitted by this core E TX and RX FIFOs with configurable depth of 2 to 63 messages each m High Prio TX Buffer Optional High Prio RX buffer RX message filtering Number of filters can be set from 0 2 by generic parameter One dedicated filter for High prio RX buffer Loop mode for diagnostic purpose Maskable interrupts Readable error counters Single clock fully synchronous design Seamless interface slave port to PLB v4 6 bus for easy integration with Xilinx MicroBlaze and IBM PowerPC in Xilinx devices The Prevas CAN Controller IP Core provides a flexible solution which may be implemented in all Xilinx Spartan 3 3A 3E and Virtex II Il Pro 4 5 device families See examples in the table below The slice count depends on the selected FIFO depths and number of message filters The figures shown are for a configuration with 1 RX filter RX prio buffer enabled RX FIFO depth of 16 messages and TX FIFO depth of 4 messages Table 1 Example implementation statistics CAN IP precan_plb46 v1 0 With PLB v4 6 interface Product Specification ORE Facts
3. a FIFO structure The depth of each buffer is individually configurable through generic parameters and may be from 2 to 63 messages each High Prio Buffers In addition to the FIFOs there are a High Prio TX buffer which can store one message A message stored in this buffer will be transmitted as soon as the CAN bus is idle bypassing any remaining messages in the TX FIFO There is also an optional High Prio RX buffer enabled with a generic parameter This buffer can store one message Any incoming message which matches the dedicated filter for this buffer is stored here RX filters IDs of incoming messages are compared with user defined ID acceptance masks If there is a match the message is stored in the RX buffer connected to the filter If no match is found the message is just acknowledged and then discarded The number of acceptance filters for the RX FIFO is defined with a generic parameter which may be set from 0 to 2 The high prio RX buffer if enabled has a dedicated filter If no acceptance filter is used all successfully received messages are stored in the RX buffer User interface The user interface of the CAN controller uses naming conventions of the user side of the IPIF module These signals provide a seamless interface to Byte enables not used all registers are the IPIF module Table 2 accessed at word boundaries W Register read qualifiers a Register write qualifiers describes the signal
4. i User s Manual Data sheet this document i VHDL Source RTL onstraint Files Verification CAN protocol compliance tested according to IS016845 using the XA3S1600E ECU development board from Si Gate Instantiation templates Reference designs amp application notes Additional Items Xilinx XPS peripheral description files pao mpd Simulation Tool Used Modelsim v6 1c Support provided by Prevas AB Applications The Prevas CAN Controller IP core targets many CAN communication applications like Automotive networks E Industrial control networks E Sensor monitoring and actuator control E Other embedded systems with CAN capabilities General Description The CAN Controller IP implements to the ISO 11898 1 CAN 2 0B protocol It takes care of all transfer layer protocol tasks like message framing message arbitration error signaling and fault confinement and automatic retransmission due to tx faults or loss of arbitration TX RX FIFOs of configurable depth and message filters provides message buffering and filtering and decreases the load on the local CPU Max bus speed for CAN networks according to the standard is 1 Mbit s This CAN controller can however support bus speeds above 1 Mbit s for special applications Family Example Device Fmax BRAM Design Tools MHz external sS o ss 2 2 XC3S1600E 4 ISE 10 1 03i 2 03i XCAVLX16 12 ISE 10 1 03 2 O3i xcsvixso s 150 5 2 2
5. off and if the node is receiver or transmitter of the current message Bit stream processor The bits stream processor BSP takes care of message data serialization and de serialization framing and format tasks During transmission these tasks are e Insert fixed form bits in the message frame e Insert stuff bits e Calculate CRC and append CRC bits to the outgoing message stream e Perform bus arbitration e Monitor the transmitted bits to detect bit errors e Automatic retransmission of the message in the case of a transmission error or if arbitration was lost During reception of a message similar tasks are performed in an opposite way There are also several other error checks e Remove and check value of fixed form bits to detect form errors e Remove stuff bits and check for stuffing errors e Calculate CRC of the incoming message and compare with received CRC e Acknowledge successfully received messages by transmitting a dominant bit in the ACK slot of the CAN frame Error handler Any errors detected by the BSP are signaled to the error handler which is responsible for fault confinement and transmission of error frames It updates its transmit and receive error counters in accordance with the ISO 11898 1 CAN 2 0B standard and based on the value of these counters determines the error state of the controller active passive or bus off Product Specification Bit synchronization The bit synchronization mo
6. dule has the following functions e Clock pre scaling e Synchronizing the CAN core to the traffic on the CAN bus e Place TX bits on the bus with the correct timing e Calculate the sampling point and provide a sample clock to the rest of the CAN core e n loop mode the core is disconnected from the CAN bus i e only recessive bits are transmitted and the bits transmitted by this node is instead routed back to the receive input Incoming data from the CAN bus is ignored e Bit error detection The synchronization process compensates for propagation delays and oscillator frequency differences between the transmitting and receiving nodes Configuration and status registers The configuration and status registers is the interface for an external micro controller Refer to the user manual for description of the registers All registers are 32 bit wide addressed at word boundaries and represented in big endian format Bit 0 is MSB bit 31 is LSB Description Bus2IP_Clk IN Bus2 P_Reset IN Bus2IP Data IN 0 C_SLV_DWIDTH 1 Bus2IP _BE 0 C_SLV_DWIDTH 8 1 Bus2IP_RdCE 0 C_NUM_REG 1 Bus2 IP_WrCE 0 C_NUM_REG 1 Active high reset Address bus Write data bus IN IN IP2Bus_ Data OUT Read data bus 0 C_SLV_DWIDTH 1 IP2Bus_RdAck IP2Bus_WrAck IP2Bus_Error System clock min 24 MHz CAN Controller precan_plb46 v1 0 TX RX FIFO Separate storage buffers for transmit and receive message are provided in
7. interface Active high read transfer acknowledge Active high write transfer acknowledge Not used tied to GND RX data from CAN transceiver precan_irq OUT enerated Table 2 User interface signals Interrupt line Goes high when an irq is Product Specification CAN Controller precan_plb46 v1 0 Design parameters Design Services A number of generic parameters can be used to tailor the design to specific application needs for optimum Prevas also offers core integration core performance The value of these parameters has customisation and other design services some impact on the resource utilization of the IP see table 1 pramor poat pn OOOO C_RX_FIFO_DEPTH o S The desired depth of the RX buffer in number of messages Settings 2 63 are valid C_ TX FIFO DEPTH i The desired depth of the TX buffer in number of messages Settings 2 63 are valid C_NR_OF FILTERS The desired number of receive filters Settings 0 2 are valid C_RX_PRIO_ BUFFER FALSE Enable disable the RX High Prio buffer C_SLV_DWIDTH Data bus width Do not change this setting C_NUM_REG 32 The number of register selects within the address space Do not change this setting Table 3 Core generic parameters Core Modifications More features may be added to the core at request Ordering Information and additional cost This product is available from Prevas AB under terms of the SignOnce IP License See www prevas se for pricing or contact Pre
8. vas for additional information about this product Customers may also modify the RTL source code at own responsibility Verification Methods Prevas AB The CAN Controller core s functionality has been PO Box 4 Legeringsgatan 18 extensively tested in hardware using the XA38S1600E SE 721 03 Vasteras ECU development board from Si Gate The Sweden functionality has also been verified in accordance with the 1S016845 2004 Road vehicles Controller area Phone 46 21 360 19 00 network CAN Conformance Test Plan This Fax 46 21 360 19 29 compliance test has been performed by C amp S Group Email johan ohlsson prevas se Germany URL www prevas se Prevas AB cores are purchased under a Licence Agreement copies of which are available on request Prevas AB retains the right to make changes to these Specifications at any time without notice All trademarks registered trademarks or service marks are the property of their respective owners Related Information Xilinx Programmable Logic For information on Xilinx programmable logic or development system software contact your local Xilinx sales office or Xilinx Inc 2100 Logic Drive San Jose CA 95124 Phone 1 408 559 7778 URL www xilinx com
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