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1. Select an IP and drag it to the Memo and Memoy Controle System Assembly View window or Farrez Contate double click on the selected IP to f m be included into the system MHS file LL yoyo 2 XILINX Embedded Design Progress GPIO Peripherals Added to System Spartan 3E Starter Kit Spartan 3E Z XILINX Making Bus Connections MicroBlaze communicates with external peripheral devices using busses select Bus Interfaces F J tab B B Ou Corn Expand Peripherals in system View Click under Bus Connection column and select a bus TP debug module CP proc_sys_resef_0 srafor 0 Pps goo 0 ps go 7 instance to which it T needs to connect AA pga I X XILINX Assigning Addresses MicroBlaze communicates with external devices through registers or memories at specific address ranges Q Select Addresses filter Click in the size column and select desired size Enter base address XPS will calculate the high address from base address B and size entries Base ddress High Address Size C_BASEADDR Adaa OXOOOO1 FF Instead of entering base address lock addresses of g instances for which you don t dais E nn want XPS to change address amp i x and then click Generate Addresses button E Z XILINX Hardware Design Progress GPIO instances are now connected to PLB bus with Base High2. Mp download bit download cmd IP Library or User Repository Drivers MDD EDK SW Libraries X Application Source CRIES Compiler GCC Linker GCC NR z VHD Model Simulation Generator XILINX iMPACT Hardware Design e After defining the system hardware and connectivity the next step is to create hardware netlists with the Platform Generator PlatGen s PlatGen inputs the following files Microprocessor Hardware Specification MHS file Microprocessor Peripheral Definitions MPD file e PlatGen constructs the embedded processor system in the form of hardware netlists HDL and implementation netlist files aw yo X XILINX Hardware Design Files Microprocessor Hardware Specification MHS File BEGIN opb uartlite PARAMETER INSTANCE PARAMETER D PARAM RS232 Uart Q D PARAMETER C ODD_ PARITY 0 PARAMETER G USE_ PARITY 0 PARAMETER G CLK FREO PARAMETER C BASEADDR PARAMETER C HIGHADDR BUS INTERFACE SOPB 100000000 0x40600000 Ox4060ffff opb MHS overrides MPD MHS and MPD Microprocessor Peripheral Definitions MPD File Bus Interfaces BUS_INTERFACE BUS SOPB BUS STD OPB BU Generics for VHDL or Parameters for Veri PARAMETER C_BASEADDR OXFFFFFFFF DT std PARAMETER C HIGHADDR Ox00000000 DT std PARAMETER C OPB DWIDTH 32 DT integer
3. Hardware Design Using EDK XILINX This material exempt per Department of Commerce license exception TSU 2007 Xilinx Inc All Rights Reserved Objectives After completing this module you will be able to Describe how to add hardware to an existing XPS project Discuss the function of Platform Generator PlatGen Utilize the integration between ISE and Xilinx Platform Studio XPS to enhance the design flow Utilize the Xflow in XPS Describe the steps involved in creating a submodule with XPS and integrating the submodule into a bigger system with ISE na yoyo X XILINX Outline ep Adding System Components e Generating the System netlists PlatGen e Generating the Bitstream Manually with ISE Project Navigator Integration s Top Level e Submodule Automatically from XPS Xflow Integration na yoyo 2 XILINX Embedded Design Initial System created with Base System Builder targeting Spartan 3E Starter Kit er Xilinx Platform Studio C XUP Markets tmbedded Workshopsicourses v92Embedded sp3ekit test HW design ED File Edit View Project Hardware Software Device Configuration Debug Simulation Window Help OBA 2h mh Gt Sarnen DBMN fg Xe SQ amp int Er Businterfaces Ports Addresses PD E L M Mm L B B B Name Bus Connection IP Type IP Version pe i a 9 B avcrobisze_0 microblaze 00 a ipti b 10 UE Projec t Information Area P se Project Applications IP C
4. GCC Linker GCC AN z VHD Model Simulation Generator XILINX iMPACT Outline e Adding System Components e Generate the System Netlists PlatGen Generate the Bitstream Manually in ISE Project Navigator Integration Automatically with XPS Xflow Integration aw 2 XILINX Manual ISE Flow User generates bitstream in ISE e The processor system xmp can be added and connected in an ISE project XPS can be invoked from ISE e Benefits include Add additional logic to the FPGA design Synthesize the design by utilizing ISE supported synthesis tools Control the FPGA implementation flow by using ISE Timing and constraints entry Implementation tool flow control e Point tool control FPGA Editor tool Constraints Editor tool ChipScope Pro tool E X XILINX TWO ways to use the XPS and ISE tools to process embedded systems Top Down s Invoke ISE and create a top level project e Then create a new embedded processor source to include in the top level design This automatically invokes XPS where you develop your embedded sub module Bottom Up s Invoke XPS and develop your embedded processor design as a sub module Later invoke ISE and add the embedded sub module as a source to include in your top level ISE project Instantiate Processor System in ISE Sources for Synthesis Implementation X s 3 proj
5. Addresses Assigned Spartan 3E Starter Kit Spartan 3E Z XILINX Parameterize IP Instances Set a GPIO to a 4 bit input to connect to the 4 DIP Switches on the Board proc_sys_feset cuu a clock generator 1 002 Q Double click the om instance or right click Raes Change Lo on the instance and ais aa select Configure IP to list the configurable Driver gpio v2 Il a K ser System Buses F Common parameters Cherel Gpodasttamewan a GPIO Supports Interrupts O Enter new values gaia lt Override defaults System Buses Common oh c Channel is Input Only TRUE Take similar steps for the EE 3 Channel 1 is Bi directional FALSE j other GPIO Channel 1 Data Out Default Value 9x00000000 Z XILINX Connecting Ports Direction Range External Ports D merobiaze 0 CP imb lt dind D mh ob gt dim enik D mb Gn SP inb_bram 35232 OCE Oo Select Ports filter Click on plus sign to see available ports ps goin 0 GPIO2 t out No Connection vio 0 C_GPIO_WIDTH 1 GPIO2 d out No Connection vo 0 C_GPIO_WIDTH 1 CI ick under the Net GPIO2 in No Connection xl 0 C_GPIO_WIBTH 1 GPIO2_10_T No Connection vio 0 C_GPIO_WIDTH 1 column and select TAN E AE s GPIO2 IO No Connection vil 0 C_GPIO_WIDTH 1 a p p ro p rl ate S Ig n al GPIO2 IO No Connection I0 0 C_GPIO_WIDTH 1 GPIO_t_o
6. Let I be the unsigned number formed by the starting address and S be the size of the memory If I S is the integer then the memory is built on the 2 boundary 1 KB 1024 memory at 0x4000 16384 is at the 2 boundary 16384 1024 16 whereas 1 KB 1024 at 0x4100 16640 is not 16640 1024 16 25 E rr Z XILINX Block Memory Map s A Block RAM Memory Map BMM file contains a syntactic description of how individual block RAMs constitute a contiguous logical data space e PlatGen has the following policy for writing a BMM file f PORTA is connected and PORTB is not connected the generated BMM will be from PORTA point of reference f PORTA is not connected and PORTB is connected the generated BMM will be from PORTB point of reference f PORTA is connected and PORTB is connected the generated BMM will be from PORTA point of reference na yoyo X XILINX Outline e Adding System Components e Generate the System Netlists PlatGen m Generate the Bitstream Manually in ISE Project Navigator Integration Automatically with XPS Xflow Integration LL yoo 2 XILINX Hardware Implementation Flow comptub Library Generation ss Hardware ompEDKLi ompXLi Platform Generation Testbench Stimulus 5 Embedded Software CNCD PCP PAR Development S tGen Download bit Download cmd EDK SW Libraries Application Source CRIES Compiler
7. PARAMETER C OPB AWIDTH 32 DT integer PARAMETER cr DATA_ BITS 8 DT integer Ri PARAM D 125 000 000 DT in PARAMETER cy BAUDRATE 9600s 9DT integer MPD contains all of the defaults XILINX PlatGen PlatGen Generated Directories HDL directory system vhd v file if top level system stub Ivhdlvi file if submodule LI hdl directory peripheral_wrapper vhad v files Implementation directory peripheral wrapper ngc files system ngc file system bmm file s Synthesis directory peripheral wrapper fprjlscr files system prj scr files E project_directory B implementation directory E synthesis directory ak oo e X XILINX PlatGen Memory Generation e Platform Generator generates the necessary banks of memory and the initialization files for the block RAM block bram block The block RAM block is coupled with a block RAM controller e Current block RAM controllers for MicroBlaze include the following PLB block RAM controller xps bram if cntir OPB block RAM controller opb bram if cntir LMB block RAM controller Imb bram if cntir aw oo X XILINX PlatGen Memory Sizes e Memory sizes Memory Size kBytes Memory Size kBytes Architecture 32 bit 64 bit F write S Spartan II 2 4 8 16 32 64 128 4 8 16 32 64 128 2 4 8 16 32 64 128 256 8 16 32 64 128 256 512 e Memory must be built on 2 boundaries
8. XPS integration na yoyo XILINX Answers e What are some of the advantages of using ISE and XPS integration Add additional logic to the FPGA design Synthesize the design by utilizing ISE supported synthesis tools Control the FPGA implementation flow by using ISE s What are some of the advantages of using Xflow and XPS integration One GUI to perform all design work Simple push button flow na yoyo X XILINX Knowledge Check What is the smallest memory size that PlatGen can generate for a Spartan IIE device Why is the address OxFFFF_B100 NOT a valid BASEADDR for a Local Memory Bus LMB block RAM controller What will the BAUDRATE for the peripheral be lfthe MPD file has the following parameter C BAUDRATE 9600 Ifthe MHS file has the following parameter C BAUDRATE 115200 E X XILINX Answers e What is the smallest memory size that PlatGen can generate for a Spartan IIE device 2 KB e Why is the address 0xFFFF_B100 NOT a valid BASEADDR for a Local Memory Bus LMB block RAM controller Itis not ona 2n boundary e What will the BAUDRATE for the peripheral be Ifthe MPD file has the following parameter C BAUDRATE 9600 lf the MHS file has the following parameter C BAUDRATE 115200 The BAUDRATE will be 115200 E X XILINX Knowledge Check Memory Space e How do you build a 48 KB OPB BRAM memory space for a MicroBlaze processo
9. atalog Description D gt imb lb 10 1 00 a Analog D aind Imb_v10 1 00 5 Bus and Bridge s mb o plb v46 1 00 a Clock Reset and Interrupt O B Pd enik Imb bram if cnth 210 2 E Communication High Speed O E inb enk mb bram if cnt 2 10 a E Communication Low Speed B nb bra bram block 1 00 4 Debug ka 35232 DCF xps_uartlite O00 DMA and Timer H debug module mdm 1 00 4 proc_syvs_resef_0 proc_sys reset 200 a Interprocessor Communication clock_generafor_0 clock generator 1 003 E Memory and Memory Controller PCI Peripheral Controller Processor E Utility E XILINX Embedded Design Add GPIO Peripherals to connect to on board DIP Switches and LEDs Spartan 3E Starter Kit Spartan 3E XILINX Adding IP to Design Project Information Project m 1 ama Te amp Bus Interfaces Po ru vzr vzr By j a Name To add hardware in a new empty TON eee project or to an existing project 2s rr D mb_pb select IP Catalog tab in XPS Bus and Bridge Clock Reset and Interrupt D dind_cnit Communication High Speed Dim eni Communication Low Speed gt im bam 1 Debug 352732 DCE 2 Expand group s of IP in the left 2 1 S General Purpose I0 proc_sys_sesef_0 window O OPB General Purpose I0 Dolche gegga 0 XPS General Purpose I0 Q P gt p gp 0 nterprocessor Lommunication Oo Na Paps gpio 7
10. cessor system One GUI for performing all design work e Limitations No direct control of synthesis and implementation options No point tool support The embedded system design must be the top level of the design E X XILINX Xflow Required XPS Directory Structure e Code TestApp directory lt application gt c La project_directory e data directory 9 Code TestApp directory optional lt system gt ucf e elc directory EE data directory ion B etc directory download cmd E pcores fast runtime opt l BSDL files 1 synthesis e pcores directory User IP Customized block RAM controllers E X XILINX Controlling Xflow e A file called fast runtime is in the etc directory e This is what it looks like Options for Translator Type ngdbuild h for a detailed list of ngdbuild command line options Program ngdbuild p lt partname gt Partname to use picked from xflow commandline nt timestamp NGO File generation Regenerate only when source netlist is newer than existing NGO file default bm lt design gt bmm block RAM memory map file lt userdesign gt User design pick from xflow command line lt design gt ngd Name of NGD file Filebase same as design filebase End Program ngdbuild E X XILINX Knowledge Check What are some of the advantages of using ISE and XPS integration s What are some of the advantages of using Xflow and
11. ile etc Bitgen Options File etc bitgen Project Options Device xc3s500efg320 4 Netlist TopLevel Implementation XPS Xflow HDL VHDL Oo obs Li RPA MAPA A Net fpga O LEDs 8Bit GPIO d_out_pin lt 6 gt LOC E12 Net fpga_O LEDs 8Bit GPIO d _out_pin lt gt LOC F12 IOSTANDARD LVCMOS33 IOSTANDARD LVCM0S33 Net fpga O LEDs 8Bit GPIO d out_pin lt 5 gt LOC E11 IOSTANDARD LVCMOS33 l l Pin location constraints for the DIP switches NET dip_GPIO in pin lt 0 gt LOC L13 IOSTANDARD LVTTL PULLUP Switchd NET dip SPIO in pin lt 1 gt LOC L14 IOSTANDARD LVTTL PULLUP Switch1 NET dip GPIO_in_pin lt 2z gt LOc H18 IOSTANDARD LVTTL PULLUP Switch2 et dip GPIO in pin lt 3 gt LOC N17 IOSTANDARD LVTTL PULLUP Switch3 E X XILINX Hardware Design Progress The GPIO instances are connected to the external DIP switches and LEDs on the board Spartan 3E Starter Kit Spartan 3E Z XILINX Outline e Adding System Components e Generating the System Netlists PlatGen e Generating the Bitstream Manually in ISE Project Navigator Integration s Top Level e Submodule Automatically from XPS Xflow Integration aw oo XILINX Hardware Creation Flow CompEDKLib CompXLib Hardware Library Generation ss S Embedded Software Development Platform Generation Testbench Stimulus System and Gystem bmm Wrapper HDL E di XST NGDBuild PAR Las
12. nav EF xc4vix1 2 101f668 DE system_stub STRUCTURE system_stub vhd oP system_i system system xmp L PG system ucf data system ucf E Sources pa Snapshots Processes L CJ Add Existing Source L CJ Create New Source L E View Design Summary H S Design Utilities H 3 User Constraints H UO Synthesize xST T TO Implement Design H DO Generate Programming File v EO Update Bitstream with Processor Data Legu Analyze Design Using Chipscope XILINX Outline e Adding System Components e Generating the System Netlists PlatGen e Generate the Bitstream Manually in ISE Project Navigator Integration p Automatically with XPS Xflow Integration E 2 XILINX Hardware Implementation Automated Approach s Xflow Automatically implements hardware and generates the bitstream Input files ngc netlists system bmm file system vhd ucf Output Files system bit system bd bmm Xflow calls the ISE Implementation tools using fast_runtime opt file s NGDBuild MAP PAR and TRACE are executed Xflow then calls the BitGen program using bitgen ut file s BitGen generates the bit file system bit s BitGen also generates the back annotated system bd bmm BMM file which contains the physical location of the block RAMs na yoyo X XILINX Automatic ISE Flow XPS generates bitstream using Xflow e Benefits Independent design of the pro
13. r in a Spartan 3E device 0x0000_0000 KB Ox Ox KB Ox aw yo X XILINX Answers Memory Space e How do you build a 48 KB OPB BRAM memory space for a MicroBlaze processor in a Spartan 3E device 0x0000_0000 0x0000 7FFF 0x0000 8000 0x0000 BFFF na yoyo X XILINX Where Can I Learn More e Tool documentation Embedded System Tools Guide Xilinx Platform Studio e Support Website EDK Website www xilinx com edk na yoyo X XILINX
14. ut No Connection v0 0 C_GPIO_wWIDTH 1 i i GPIO d out No Connection w0 0 C_GPIO_WIBTH 1 If the port is external in the GPIO IO T No Comection vo 0 C_GPIO_WIDTH 1 f GPIO 10 0 No Connection sio 0 C_GPIO_WIDTH 1 desig n then make it external GPIO_10_ No Connection wal 0 C_GPIO_WIDTH 1 GPIO 10 No Connection lo 0 C_GPIO_WIDTH 1 IP2INTC_Irpt ee Verify the external pin entry GPIO_in m Rp pO in the External Ports section Direction Range V Fsternal Parts xps goio 0 GPIO in pin ps gpio 0 GPIO in 03 ERE wT dem_clk_s v Inna A ASIII NOL TY nin nda N ACPI PE sin X XILINX Hardware Design Progress External Port Connections for both GPIO instances have been established Spartan 3E Starter Kit Spartan 3E Z XILINX Make Pin Assignments Oo Double click the system ucf under the Project tab 2 Enter the pin location constraints refer to the board user manual Module LEDs 8Bit constraints Net fpga O LEDs 8Bit GPIO d out pin lt O gt LOC F9 IOSTANDARD LVCMOS33 Net fpga O LEDs 8Bit GPIO d out pincl LOC E9 IOSTANDARD LVCMOS33 Net fpga O LEDs 8Bit GPIO d out pin lt 2 gt LOC D11 IOSTANDARD LVCMOS33 Net fpga O LEDs 8Bit GPIO d out pin lt 3 gt LOC C11 IOSTANDARD LVCMOS33 Net fpga O LEDs 8Bit GPIO d out pin lt 4 gt LOC Fii IOSTANDARD LVCMOS33 Platform Project Files UCF Fil da nL iMPAC do Implementation Options F
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