Developer III board ver3.0
Contents
1. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 19 DragonFLASH Dragonchip We bring silicon to life Rev2 0 The memory configuration in ICE environment is shown below DC66XXF Developer III Board ver3 0 8 1 2 DC6688FSB 5 5 5 5 55 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 55 5 SSS u 5 55 5 5 5 5 5 5 5 5 5 e 22 5 552 25252555 5555555555555555 2 2 5 2 2252 55 5555555555555555 2 5 2 52 5 5555555555555555 2522522525525 5555555555555555 25 5 5 5 5 5 5 5 5 5 5 5 5 5 2222222225 55 5 5 5 5 5 5 2 5 5 5 5 5 5 5 M 5 5 5 5 5 55 5 2 5 5 5 5 5 5 5 S SS e GE 55 5 5 5 5 5 5 5 5 5 5 5 5 5 5 e EGE SSE S S BS 55 5 5 5 5 5 5 5 5 5 5 5 5 eZEzzzzizzizzzziii 5555555555555555 5 55 5 5 5 5 5 5 5 5 5 52. 55 5 5 5 5 5 5 5 5 5 5 5 5 5 jaaa e 5 5 5 5 5 5 55 55 5 5 5 5 5 5 20 DragonFLASH Dragonchip We bring silicon to life Rev2 0 The memory configuration in ICE environment is shown below ICE zd Break Points Memory Map Events DC66XXF Developer III Board ver3 0 8 1 3 DC6688FL32A x 55 5 5 5 5 5 5 5 5 5 5 SES 55 5 5 5 5 5 5 5 5 5 5 S S S 5 5 5 55 5 5 5 5 5 5 5 5 5 5 eG Eua S 5 5 5 5 5 5 5 5 5 5 5 5 S 5 5 o SS SSS e 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 SS SSS a 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 gt RS e 5 55 5 5 5 5 5 5 5 5 5 5 5 5 SSE mile o BESS SS 55 5 5 5 5 5 5 5 5 5 5 5 5 aaa o 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 55 5 5 5 5 5 5 5 5 5 5 5
3. SS SST o 55 5 5 5 5 5 5 5 5 5 5 5 5 Eaa ee freee Eee 55 5 2 5 5 5 5 5 5 5 gt BET RS SS gt 5 5 5 5 5 5 5 5 5 5 5 5 2 5 5 5 BEGETS gt 55 5 5 5 5 5 5 5 5 5 5 5 5 5 55 5 5 5 5 5 5 5 5 5 5 5 5 5 in nad mB SS 5 5 5 5 5 5 5 5 5 5 5 5 55 e iia 5 5 5 5 5 5 5 5 2 5 5 2 2 5 5 5 5 5 5 5 5 5 5 2 5 5 2 5 5 55 5 5 5 55 5 5 5 5 5 5 5 5 5 in Do no 222222222 5555555555555555 5 55 5 5 5 5 5 5 5 5 5 5 5 d i jaa ICE zi Break Points Memory Map Events x 23 DragonFLASH life to Dragonchip We bring silicon Rev2 0 The memory configuration in ICE environment is shown below ICE zd Break Points Memory Map Events DC66
4. o 5 5 5 55 5 5 5 5 5 5 5 5 5 BESS GS ESS 5 5 55 52 5525 5555555555555555 55 55 5 552525552525555555555555555 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Ea SS 55 55 5 5 5 5 55 5 5 5 5 keke 21 DragonFLASH Dragonchip We bring silicon to life Rev2 0 ICE Status Break Points Memory Map Events The memory configuration in ICE environment is shown below DC66XXF Developer III Board ver3 0 8 1 4 DC6688FLX 2 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 VERS SGT GSTS HTS STE 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 w 5 555 5 5 5 5 5 5 5 5 5 5 eaa 5 5 55 5 5 5 5 5 5 5 5 5 5 5 5 o 5 55 5 5 5 5 5 5 5 5 5 5 5 5 5 a 5 555 5 5 5 5 5 5 5 5 5 5 5 5 in in in e 5 55 5 5 5 5 5 5 5 5 5 5 5 5 EEE
5. 5 5 5 5 5 5 5 5 5 5 5 5 5 2 5 a a 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 S SS 5 5 5 5 5 5 5 55 5 5 5 5 SSS m 5 5 5 55 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 imme e Gm 5 5 5 5 5 5 5 5 5 5 5 5 2 5 co 5 2 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 e 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 55 5 5 5 5 5 5 5 5 5 5 5 s E 3 55 5 5 5 5 5 5 5 5 5 5 2 5 5 5 5 5 5 5 5 5 5 5 5 5 2 5
6. DC6688FSA is also available in 28 pin The part number is DC6688FSAE The target pin out is 14x2 header 2 54mm pitch and the pin layout for target interface is illustrated below Only pins in blue color are used PC3 VCC PC2 PCI PCO PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO PCS IRI GND Target Clock NC NC PAO PAI PA2 PA3 PA4 PAS PA6 m i i BH i i i PA7 PC4 Top view of 28 pin header J1 Dragonchip We bring silicon to life DragonFLASH i DC66XXF Developer III Board ver3 0 6 2 DC6688FSB 6 2 1 24 pin Rev2 0 If device DC6688FSB is selected according to following settings then the pin assignment for component J1 will be shown below SW6 SW7 Device On Off DC6688FSB The target pin out is 14x2 header 2 54mm pitch and the pin layout for target interface is illustrated below Only pins in blue color are used PC3 VCC PC2 PCI PCO PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO PCS 1 GND Target Clock NC NC PAO PAI PA2 PA3 PA4 PAS PA6 PA i i 5 E i i PC4 Top view of 28 pin header J1 Dragonchip We bring silicon to life DragonFLASH Bs DC66XXF Developer III Board ver3 0 6 2 2 28 pin Rev2 0 If device DC6688FSB is selected according to following settings then the pin assignment for component J1 will
7. gt 5 555 5 5 5 5 5 5 5 5 5 5 5 2 co 5 55 5 5 5 5 5 5 5 5 5 5 5 25 5 55 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 25 EEEa BESS GSE 5 5 5 5 5 5 5 5 5 5 5 5 E a Gojoe 5 55 5 5 5 5 5 5 5 5 5 5 5 5 5 55 5 5 5 5 5 5 5 5 5 5 5 5 EEEa a 5 5 55 55 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 55 5 5 5 5 S o i CD C CD CD C CD CD C om oc C Co Co C2 a CD C C C2 CD C C CD 22 DragonFLASH Dragonchip We bring silicon to life MopulAA 5 Rev2 0 The memory configuration in ICE environment is shown below DC66XXF Developer III Board ver3 0 8 1 5 DC6688F05S 5 5 5 5 5 5 5 5 5 2 5 5 2 5 5 5 ETE 5 5 5 5 5 5 5 5 5 2 5 5 2 5 5 5 SSS S S w 5 5 5 5 5 5 5 5 2 2 5 5 2 5 5 5 euam 55 2 5 5 5 5 2 2 5 5 2 5 5 5
8. keke 24 DragonFLASH Dragonchip We bring silicon to life DC66XXF Developer III Board ver3 0 Rev2 0 9 Precaution on using emulator At this moment one type of emulator is available 1 DEEMAX 80532 4T ICE from DEEMAX company This type of emulator has it own limitation when using together with the developer III board DC6688EMT and will be described in detail in the following section 9 1 9 1 DEEMAX 80532 4T ICE 9 1 1 Limitation The number of machine cycle occupied for each instruction and the period of machine cycle in ICE is all the same as real silicon only with the following exception 1 INC DPTR RET RETI JMP A DPTR MOVC A A DPTR MOVC A A PC The exact number of machine cycle occupied for each instruction above refers to the document Development Tools Setup Guide for Dragonchip Development board 9 1 2 Additional limitation on Emulate DC6688FSA Power down mode is not implemented in ICE don t use it otherwise undetermined result occurs No ISP select pin on CONA in the ICE No XOUT pin on CON4 in the ICE No pull up resistors in the ICE s port A B and C No watchdog basic timer No backup mode No ISP programming No UART1 Only operated at 3 3V power No access to PCNT register No T2 output on PC2 by setting bit T2OE in T2MOD register 9 1 3 Additional limitation on Emulate DC6688FSB Power down mode is not implemented in ICE don t
9. 080 ocd 5 3 n DC66XXF Developer III board ETTI 52222 5 6 d OF See gt O OO O 999 OOOO Ol O O O O O Application board 00 000000 provided by customer 9999999 DragonFLASH DC66XXF Developer III Board ver3 0 Rev2 0 3 Powering up the developer Ill board Attach a fixed power supply to the power connector at J4 An unregulated 9V up to 12V 800mA power source can be used to supply the power of the developer board DC6688EMT The correct polarity of the power plug is shown below ve inside Polarity ve outside 4 DIP Switch Settings S1 Dip switch on the board applies to section 3 To change the settings the board should remove the power first 4 1 Clock Frequency selection The on board clock source of developer board is derived from 48MHz It can run up to a maximum frequency of 24 MHz It can be changed to various frequencies according to customer s preference by the SW3 5 4 and SW5 switch settings Their settings are as follows 5 3 5 4 SW5 Clock frequency Off Off On Invalid Off On On Invalid On Off On Invalid On On On 24 1 Off Off Off 12 default Off On Off 8 On Off Off 6 On On Off 4 2 Remarks 1 only available for DC6688FL32A DC6688FLB 2 DC
10. OUTRE RELIER o Cien 19 8 1 2 DG5688FSB ska ee ES AGAR AE e EES 20 8 1 3 DC5688FE32A kso ERE DAO EIER Ed eR 21 8 1 4 DC6688FEEX kao ote ERES dO Er ES mee d 22 8 1 5 DC6688F058S AE SRI GR n EOD E SESS 23 8 16 DG5688FLB kso Re S EDD PEE E RE UE DON SUPR RENE ee 24 9 PRECAUTION ON USING EMULATOR e eeeeee esses eene enata aetas stas 5999 5999 5999 5999 88 98 8 59 8 59 8 58 8 58 9 5869 5669 56 25 93 DEEMAX 8053224 TICE SSSA SASS SSS arte oe AS et 25 0 T T LEimitatllon AS Ee E sad cies ie adh iis Be vendo sda tol set 25 9 1 2 Additional limitation on Emulate 54 0 505555555 55 55 5 5 55 55 5 50 25 9 1 3 Additional limitation on Emulate DC6688FSB sse entente entente 25 9 1 4 Additional limitation on Emulate 6 324 26 9 1 5 Additional limitation on Emulate 6 5 555 555 5 5 5 26 9 1 6 Additional limitation on Emulate DC6688F058 sse reete entree tnnt 26 9 1 7 Additional limitation on Emulate DC6688FLB sse entrent 26 10 NOTES ON CUSTOMER TARGET BORHARB
11. be shown below SW6 SW7 Device On Off DC6688FSB DC6688FSB is also available in 28 pin The part number is DC6688FSBE The target pin out is 14x2 header 2 54mm pitch and the pin layout for target interface is illustrated below Only pins in blue color are used PC3 VCC PC2 PCI PCO PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO PC5 m i i BH i i i IRI GND Target Clock NC NC PAO PAI PA2 PA3 4 PAS PA6 PA7 PC4 Top view of 28 pin header J1 Dragonchip We bring silicon to life 12 DragonFLASH DC66XXF Developer III Board ver3 0 Rev2 0 6 3 DC6688FL32A If device DC6688FL32A is selected according to following settings then the pin assignment for component J1 will be shown below SW6 SW7 Device On On DC6688FL32A The target pin out is 14x2 header 2 54mm pitch and the pin layout for target interface is illustrated below Only pins in blue color are used PC3 IRI 1 VCC GND PC2 Target Clock PCI NC ro 7 PG BEEE r PBS EN rx m rx Be EN r 82 m rx 80 a a PA7 PCS B c Top view of 28 pin header J1 Remarks 1 Don t use this pin Use the on board IR sensor for IR signal reception Dragonchip 13 We bring silicon to life DragonFLASH DC66XXF Developer III Boa 6 4 DC6688FLX
12. 3 POWERING UP THE DEVELOPER III BOARD 2 ens sense 689998 5969 5699 58 5959 5659 6 4 DIP SWITGH SETTINGS notre eto bo no an sess eese 6 4 TCL LOCK EREQUENGY SELE TION zu sale EN GR REIN Ig HI 6 4 2 C OCK SOURCE SELECTION ea aN OS AID IRIS AROUND 6 4 3 DEVICE SELECTION ee SSE SSeS 7 44 DEFAU T SETTINGS e n 7 5 RESET BUTTON AND GREEN 0000100100 8 6 TARGET INTERFACE EE EN 9 6 4 DG6589F SA oe SURROUND RM MM E er e e e SN 9 URL DII aT 9 6 12 LE PUN 10 6 2 DG668SFSB ie vues het ee A ee Uem ue ee 11 6 2 1 24 Ppif aici cues eee te eere Es tete e ER eee donee 11 G22 DISSES ipee i d p dte e abest 12 6 3 DCO689FE32A veto mea bate et ete et etra ER 13 64 D66689E BX cGic ice es en bue cuneum v SO Lee 14 6 5 DG6689F05S A tumens ute co a e oes EHE 15 6 6 DG6689F nea Reads amen he 17 7 TOP VIEW OF THE COMPONENT DIAGRAM eeeeeee neenon s tuns setas ense stesse 689999 5999 58 89 59 5699 58 96 596 18 8 MEMORY CONFIGURATION IN IN CIRCUIT EMULATOR ICE 4 eere eere enero 19 8 1 DEEMAX 80532 4T iube entere en ORS UE 19 84 1 DC5688FSA issu AREAS ERROR
13. 6688F05S can only use this frequency 4 2 Clock source selection This board can support the clock source from target system by setting SW2 to Off position SW2 Clock Source Off Target board On On board default Dragonchip 6 We bring silicon to life DragonFLASH DC66XXF Developer III Board ver3 0 Rev2 0 4 3 Device selection It is required to determine which device to emulate by using this SW6 and SW7 The table below only applies to v1 2 see marking on U4 component as shown below SW6 SW7 Device On Off DC6688FSA DC6688FSB default Off Off Reserved On On DC6688FL32A DC6688FLB Off On DC6688F05S The table below only applies to v1 3 see marking on U4 component as shown below SW6 SW7 Device Off On DC6688F05S The table below only applies to DC6688EMT dvlp3 080710b see marking on U4 component as shown below SW6 SW7 Device On On DC6688FLX CLOCK MHz OFF f OFF ON INVALID OFF PON ON INVALID RON OFF ON INVALID ON ON JON 24 OFF f OFF f OFF 12 OFF PON OFF 8 ON J OFF OFF 6 ON TON OFF 4 DC6688FL32 DC6688FE 4 4 Default settings SW1 On SW2 On SW3 Off 5 4 Off SW5 Off SW6 On SW7 Off Sws Off Warning SW1 SW8 should not be changed Dragonchip 2 7 We bring silicon to life DragonFLASH DC66XXF Developer III
14. Board ver3 0 Rev2 0 5 Reset Button and Green LED When pressed the reset button the blue circle as shown below the Green LED the red circle as shown below turns off After released the button the Green LED will be lit up again to indicate the success of reset This button should be pressed whenever re starting the program e e lt e Dragonchip E 8 We bring silicon to life DragonFLASH DC66XXF Developer III Board ver3 0 6 Target interface 6 1 DC6688FSA 6 1 1 24 pin Rev2 0 If device DC6688FSA is selected according to following settings then the pin assignment for component J1 will be shown below SW6 SW7 Device On Off DC6688FSA default The target pin out is 14x2 header 2 54mm pitch and the pin layout for target interface is illustrated below Only pins in blue color are used PC3 VCC PC2 PCI PCO PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO PCS IRI GND Target Clock NC NC PAO PAI PA2 PA3 PA4 PAS PA6 PA7 i i 5 i i E i PC4 Top view of 28 pin header J1 Dragonchip We bring silicon to life DragonFLASH DC66XXF Developer III Board ver3 0 6 1 2 28 pin Rev2 0 If device DC6688FSA is selected according to following settings then the pin assignment for component J1 will be shown below SW6 SW7 Device On Off DC6688FSA default
15. D eeeeeeee renes tns tn setas staat 9999 8999 969 8969 8869 8899 86 99 56 59 8 55 6 55 69 28 Dragonchip 3 We bring silicon to life DragonFLASH DC66XXF Developer III Board ver3 0 Rev2 0 1 Introduction The Objective of this document is to provide the user a quick start to evaluate our products on their application development A block diagram for the environment setup for development is shown below The scope of this manual covers the Development board The development board is DC66XXF Developer board ver3 0 DC6688EMT in this case This board is applicable to the following devices 1 DC6688FSA 2 DC6688FSB 3 DC6688FL32A 4 DC6688FLX 5 DC6688F05S 6 DC6688FLB The whole setup involves two parts One is PC to ICE while the other is ICE to development board There is no pre requisite software required for the development board Here the third vendor in circuit emulator ICE from DEEMAX model 80532 4T is suggested ICE interface DCXXXX chip To parallel port in PC side Third party In Circuit Emulator i i Development board 1 Target Board Dragonchip 4 We bring silicon to life DragonFLASH DC66XXF Developer III Board ver3 0 Rev2 0 2 Hardware Setup Connect power Dragonchip We bring silicon to life To emulator e ANHAN siy es 58 D 8EEBH a LJ Jn n OO 22 tdl 53141 zdl
16. DC66XXF Developer III Board ver3 0 Rev2 0 a e g Dragonchip User Manual for DC66XXF Developer III board ver3 0 DC6688EMT Document Revision 2 0 Aug 2007 Dragonchip 1 We bring silicon to life DragonFLASH DC66XXF Developer III Board ver3 0 Rev2 0 Revision History The following table shows the revision history for this document Date Rev Description Edited By Reviewed By July 2005 1 0 Preliminary for DC66XXF Developer board ver3 0 Dec 2005 1 1 Revise section 7 8 add description when using DEEMAX ICE May 2006 1 2 Revise section 1 and 7 June 2006 1 3 Add section 2 hardware setup June 2006 1 4 1 Add 0 6688 059 2 Add section 10 Sept 2006 1 5 revise section 9 1 Jan 2007 1 6 July 2008 1 7 Remove appendix A July 2008 1 8 Remove all related to Miceteck EPLV52 ICE section Ken Yeung Danny Ho Added edited by and reviewed by in revision history Added DC6688FLX July 2008 1 9 Added DC6688FLB Danny Ho Ken Yeung Aug 2008 2 0 Added DC6688FSB Kennis To Ken Yeung Dragonchip 2 We bring silicon to life DragonFLASH DC66XXF Developer III Board ver3 0 Rev2 0 Contents DOCUMENT REVISION 2 0 AUG 2007 e eeeeeeee eee eene en etant tn strate tastes tae saa ena ena 9999969969 8968 698 8899 58 59 88 56 655 99 1 1 INTRODUCTION pma 4 2 HARDWARE SETUP otto tion eu E VR GENE EE 5
17. XXF Developer III Board ver3 0 8 1 6 DC6688FLB x BSE 5555555555555555 55 5 5 5 5 5 5 5 5 5 5 S S S 5 5 5 55 5 5 5 5 5 5 5 5 5 5 eG Eua S 5 5 5 5 5 5 5 5 5 5 5 5 S 5 5 o SS SSS e 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 SS SSS a 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 gt RS e 5 55 5 5 5 5 5 5 5 5 5 5 5 5 SSE mile o BESS SS 55 5 5 5 5 5 5 5 5 5 5 5 5 aaa o 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 55 5 5 5 5 5 5 5 5 5 5 5 o 5 5 5 55 5 5 5 5 5 5 5 5 5 BESS GS ESS 5 5 55 52 5525 5555555555555555 55 55 5 552525552525555555555555555 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Ea SS 55 55 5 5 5 5 55 5 5 5 5
18. d lew o 7 Topv DC66XXF Developer III Board ver3 0 o0 C Tx sna sua ss aou 3 EI MASTER OFF OFF JTAG INVALID INVALID 582 cock source ON BOARD OFF TARGET 0000 815 7 0 J5 UN OFF DC6688FS DC668BFSA S1 08 08 OFF FON 1006588055 TP2TP1 E C12 C23 i 5 3 U5 es CJ E 1 5 voor R26 27 6 8 8 2 1 I SHORT 5 ILC cs 72 oren fron OPEN z I 68 C LI 3 lt C n L e TARGET cud P r T renove 2 839 EE 886635 5 OO Ds ejs fie TP4 TP3C7 c20 HE PA 5 G ajg PC2 R19 R18 R16 C27 R24 R23 R 1 m 8 o C24 e 3E PCO 5 4 als o SHE 2 EMULATOR O 7 LL a E 8 QE n sa EF LJ d e RM 026 628 TARGET CLK o 8 9 NC ESS gt 52 o x e PB7 cul oss 2225 To Target Board os gt 0055 Oo Qu g T2 cot 6 5 8 o J4 CON2 ur 6 a8 Lr 8z RI5 S o O48 E as Rev2 0 8 Memory Configuration in In Circuit Emulator ICE ICE Status Break Points Memory Map Events 8 1 DEEMAX 80532 4T 8 1 1 DC6688FSA The memory configuration in ICE environment is shown below DC66XXF Developer III Board ver3 0 54 5 5 5 5 5 5 5 5 5 5 5 5 5 5 SSS 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 SSS
19. der J1 Dragonchip We bring silicon to life DragonFLASH DC66XXF Developer III Board ver3 0 Rev2 0 2 6688 055 20 pin package The target pin out is 14x2 header 2 54mm pitch and the pin layout for target interface is illustrated below Only pins in blue color are used PC3 VCC PC2 PCI PCO PB7 PB6 PB5 PB4 PB3 PB2 PB1 PBO PC5 IRI 1 GND Target Clock NC NC PAO PAI PA2 PA3 PA4 PAS PA6 PA7 HN 6 6 6 HN 65 65 HEN PC4 Top view of 28 pin header J1 Dragonchip We bring silicon to life 1 DragonFLASH DC66XXF Developer III Board ver3 0 Rev2 0 6 6 DC6688FLB If device DC6688FLB is selected according to following settings then the pin assignment for component J1 will be shown below SW6 SW7 Device On On DC6688FLB The target pin out is 14x2 header 2 54mm pitch and the pin layout for target interface is illustrated below Only pins in blue color are used PC3 IRI 1 VCC GND PC2 Target Clock PCI NC ro 7 PG BEEE r PBS EN rx m rx Be EN r 82 m rx 80 PA7 PCS Top view of 28 pin header J1 Remarks 1 Don t use this pin Use the on board IR sensor for IR signal reception Dragonchip 17 We bring silicon to life DragonFLASH Rev2 0 iagram f the component
20. mulate DC6688F05S Power down mode is not implemented in ICE don t use it otherwise undetermined result occurs No ISP select pin on CONA in the ICE No XOUT pin on CON4 in the ICE No pull up resistors in the ICE s port A B and C No watchdog basic timer No backup mode No ISP programming No UART1 Only operated at 3 3V power No access to T1_PCNTA register No T2 output on PC2 by setting bit T2OE in T2MOD register 9 1 7 Additional limitation on Emulate DC6688FLB Power down mode is not implemented in ICE don t use it otherwise undetermined result occurs No ISP select pin on CONA in the ICE No XOUT pin on CON4 in the ICE No pull up resistors in the ICE s port A B and C No watchdog basic timer Dragonchip 26 We bring silicon to life DragonFLASH DC66XXF Developer III Board ver3 0 Rev2 0 No backup mode No ISP programming No UART1 Only operated at 3 3V power No access to T1_PCNTA register No T2 output on PC2 by setting bit T2OE in T2MOD register Dragonchip E 27 We bring silicon to life DragonFLASH DC66XXF Developer III Board ver3 0 Rev2 0 10 Notes on Customer Target board Customer Target board means the one described in section 1 When building a target board the following points have to be checked before connecting to the Developer board DC6688EMT 1 Pull up resistors on port For example to use DC6688FSA for remote control application pull up resist
21. ors should be put on the target board to connect to port A Power line Make sure the line is not shorted to ground line Ground line Make sure the line is not shorted to power line and connected to ground line in development board Cable between Target board and Development board Choose cable as short as possible to avoid any noise Power down mode When running the program make sure the power down mode instruction is disabled otherwise the emulator will have no response Dragonchip E 28 We bring silicon to life DragonFLASH DC66XXF Developer III Board ver3 0 Rev2 0 Copyright Notice This specification is copyrighted by Dragonchip Ltd No part of this specification may be reproduced in any form or means without the expressed written consent Dragonchip Ltd Disclaimer Dragonchip Ltd assumes no responsibility for any errors contained herein Copyright by Dragonchip Ltd All Rights Reserved Dragonchip Ltd TEL 852 2776 0111 FAX 852 2776 0996 http www dragonchip com Dragonchip 29 We bring silicon to life DragonFLASH
22. rd ver3 0 Rev2 0 If device DC6688FLX is selected according to following settings then the pin assignment for component J1 will be shown below SW6 SW7 Device On On DC6688FLX The target pin out is 14x2 header 2 54mm pitch and the pin layout for target interface is illustrated below Only pins in blue color are used VCC Remarks PCZ PCI PCO PB7 PB6 PB5 PB4 PB3 PB2 PBI PBO ps HN 656 HN HN HN HN HN E Hi HN IRI 1 GND Target Clock NC NC PAO PAI PA2 PA3 PA4 PAS PA6 PA7 PC4 Top view of 28 pin header J1 1 Don t use this pin Use the on board IR sensor for IR signal reception Dragonchip We bring silicon to life DragonFLASH DC66XXF Developer III Board ver3 0 6 5 DC6688F05S Rev2 0 If device DC6688F05S is selected according to following settings then the pin assignment for component J1 will be shown below SW6 SW7 Device Off On DC6688F05S 1 DC6688F05S 24 pin package The target pin out is 14x2 header 2 54mm pitch and the pin layout for target interface is illustrated below Only pins in blue color are used PC3 VCC PC2 PC1 PCO 87 86 PBS PB4 PB3 PB2 PB1 PBO PC5 n i i a B i i IRI 1 GND Target Clock NC NC PAO PAI PA2 PA3 PA4 PAS PA6 PA7 PC4 Top view of 28 pin hea
23. use it otherwise undetermined result occurs No ISP select pin on CONA in the ICE No XOUT pin on CON4 in the ICE No pull up resistors in the ICE s port A B and C No watchdog basic timer No backup mode No ISP programming Only operated at 3 3V power No access to T1 No T2 output on PC2 by setting bit T2OE in T2MOD register Dragonchip 2 25 We bring silicon to life DragonFLASH DC66XXF Developer III Board ver3 0 Rev2 0 9 1 4 Additional limitation on Emulate DC6688FL32A Power down mode is not implemented in ICE don t use it otherwise undetermined result occurs No ISP select pin on CONA in the ICE No XOUT pin on CON4 in the ICE No pull up resistors in the ICE s port A B and C No watchdog basic timer No backup mode No ISP programming No UART1 Only operated at 3 3V power No access to T1_PCNTA register No T2 output on PC2 by setting bit T2OE in T2MOD register 9 1 5 Additional limitation on Emulate DC6688FLX Power down mode is not implemented in ICE don t use it otherwise undetermined result occurs No ISP select pin on CON4 in the ICE No XOUT pin on CON4 in the ICE No pull up resistors in the ICE s port A B and C No port D No watchdog basic timer No backup mode No ISP programming No UART1 Only operated at 3 3V power No access to PCNT register No T2 output on PC2 by setting bit T2OE in T2MOD register 9 1 6 Additional limitation on E
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