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CPU Instruction Set Details

1. A 18 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details BCzFL UE T Z BCzFL 31 26 25 21 20 16 15 0 COPz BC BCFL offset 0100xx 01000 00010 6 5 5 16 Format BCzFL offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended If the contents of coprocessor z s condition line as sampled during the previous instruction is false the target address is branched to with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified Because the condition line is sampled during the previous instruction there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line See the table Opcode Bit Encoding on next page or CPU Instruction Opcode Bit Encoding at the end of Appendix A MIPS R4000 Microprocessor User s Manual A 19 Appendix A B h OnC BCzFL e Faetky BOZFL continued Operation 32 T 1 condition not COC z T target lt offset offset 0 T 1 if condition then PC amp PC target else endif 64 T 1 condition not COC z T target lt offset 5 49 offset 0 T 1 if condition then PC c PC target NullifyCurrentInstruction
2. 31 26 25 21 20 16 15 0 SLTIU rs rt immediate 001011 6 5 5 16 Format SLTIU rt rs immediate Description The 16 bit immediate is sign extended and subtracted from the contents of general register rs Considering both quantities as unsigned integers if rs is less than the sign extended immediate the result is set to one otherwise the result is set to zero The result is placed into general register rt No integer overflow exception occurs under any circumstances The comparison is valid even if the subtraction used during the comparison overflows Operation 32 T if 0 GPR rs lt immediate s5 immediate s 9 then GPR rd 03 1 else GPR rd 09 endif 64 T if 0 GPR rs lt immediate 5 9 immediate 5 9 then GPR rd 082 4 else GPR rd 094 endif Exceptions None A 144 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details SLTU Set On Less Than Unsigned SLTU 26 25 21 20 16 15 11 10 SPECIAL 0 SLTU 000000 00000 101011 6 5 6 Format SLTU rd rs rt Description The contents of general register rt are subtracted from the contents of general register rs Considering both quantities as unsigned integers if the contents of general register rs are less than the contents of general register Tt the result is set to one otherwise the result is set to zero The result is placed into general regist
3. 26 25 21 20 16 15 11 10 SPECIAL 000000 6 Format SLL rd rt sa Description The contents of general register rt are shifted left by sa bits inserting zeros into the low order bits The result is placed in register rd In 64 bit mode the 32 bit result is sign extended when placed in the destination register It is sign extended for all shift amounts including zero SLL with a zero shift amount truncates a 64 bit value to 32 bits and then sign extends this 32 bit value SLL unlike nearly all other word operations does not require an operand to be a properly sign extended word value to produce a valid sign extended word result NOTE SLL with a shift amount of zero may be treated as a NOP by some assemblers at some optimization levels If using SLL with a zero shift to truncate 64 bit values check the assembler you are using Operation 32 T GPRird GPR rt s S4 o 092 64 T seO0 sa temp GPR rt a s o 0 GPR rd temp31 temp Exceptions None A 140 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details SLLV Shift Left Logical Variable SLLV 26 25 21 20 16 15 11 10 SPECIAL 0 SLLV 000000 00000 000100 6 5 6 Format SLLV rd rt rs Description The contents of general register rt are shifted left the number of bits specified by the low order five bits contained in general register rs inserting zeros into the low or
4. 0 1 2 3 4 5 6 7 Figure B 3 cont Bit Encoding for FPU Instructions Key Y Operation codes marked with a gamma cause a reserved instruction exception They are reserved for future versions of the architecture Operation codes marked with a delta cause unimplemented operation exceptions in all current implementations and are reserved for future versions of the architecture n Operation codes marked with an eta are valid only when MIPS III instructions are enabled Any attempt to execute these without MIPS III instructions enabled causes an unimplemented operation exception B 62 MIPS R4000 Microprocessor User s Manual
5. Opcode BC sub opcode Branch condition Coprocessor Unit Number A 24 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details B EQ Branch On Equal B EQ 31 26 25 21 20 16 15 0 rs rt offset BEQ 000100 6 5 5 16 Format BEQ rs rt offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended The contents of general register rs and the contents of general register rt are compared If the two registers are equal then the program branches to the target address with a delay of one instruction Operation 32 T target lt offset s 4 offset 0 condition GPR rs GPR rt T 1 if condition then PC PC target endif 64 T target lt offset 5 6 offset 0 condition GPR rs GPR rt T 1 if condition then PC c PC target endif Exceptions None MIPS R4000 Microprocessor User s Manual A 25 Appendix A B EQL Branch On Equal Likely B EQL 31 26 25 21 20 16 15 0 BEQL rs rt offset Format BEQL rs rt offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended The contents of general register rs and the contents of general register rt are com
6. 001001 6 16 Format ADDIU rt rs immediate Description The 16 bit immediate is sign extended and added to the contents of general register rs to form the result The result is placed into general register rt No integer overflow exception occurs under any circumstances In 64 bit mode the operand must be valid sign extended 32 bit values The only difference between this instruction and the ADDI instruction is that ADDIU never causes an overflow exception Operation 32 T GPR rt GPR rs immediate immediate o 64 T temp GPR rs immediate 5 immediate 5 o GPR rt lt temps temps o Exceptions None MIPS R4000 Microprocessor User s Manual A 13 Appendix A ADDU Add Unsigned ADDU A 14 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL rs rt rd 0 ADDU 000000 00000 100001 6 5 5 5 5 6 Format ADDU rd rs rt Description The contents of general register rs and the contents of general register rt are added to form the result The result is placed into general register rd No overflow exception occurs under any circumstances In 64 bit mode the operands must be valid sign extended 32 bit values The only difference between this instruction and the ADD instruction is that ADDU never causes an overflow exception Operation 32 T GPRi rd GPR rs GPR rt 64 T temp GPR rs GPR rt GPR rd temps
7. Reserved Reserved 20 single 32 bit binary fixed point longword Reserved 64 bit binary fixed point Table B 5 lists all floating point instructions MIPS R4000 Microprocessor User s Manual B 9 Appendix B Table B 5 Floating Point Instructions and Operations Code A Mnemonic Operation S D Add Subtract DD UB IV Divide SORT Square root A Absolute value ROUND L 9 TRUNC L BS MOV Move NEG Negate Convert to 64 bit long fixed point rounded to nearest even Convert to 64 bit long fixed point rounded toward zero 10 CEIL L 11 FLOOR L 12 ROUND W 0 3 6 Lc Convert to 64 bit long fixed point rounded to 0 Convert to 64 bit long fixed point rounded to co Convert to single fixed point rounded to nearest even 13 TRUNC W 14 CEIL W 15 FLOOR W Convert to single fixed point rounded toward zero Convert to single fixed point rounded to co Convert to single fixed point rounded to c 16 31 Reserved 32 CVT S Convert to single floating point 33 CVT D Convert to double floating point 34 35 36 Reserved Reserved Convert to 32 bit binary fixed point 37 38 47 48 63 C Convert to 64 bit long binary fixed point Floating point compare MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details In the following pages the notat
8. COPzSDw trt StoreMemory uncached DOUBLEWORD data pAddr vAddr DATA See the table Opcode Bit Encoding on next page or CPU Instruction Opcode Bit Encoding at the end of Appendix A MIPS R4000 Microprocessor User s Manual A 131 Appendix A Store Doubleword SDCz From Coprocessor SDCz continued Exceptions TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception Coprocessor unusable exception Opcode Bit Encoding SDCZ ais 30 29 28 27 26 0 spci 1 1 1 1 0 1 Bits31 30 29 28 27 26 0 spc2 1 1 1 1 1 0 Ne A J ba yY SD opcode Coprocessor Unit Number A 132 MIPS R4000 Microprocessor User s Manual SDL CPU Instruction Set Details Store Doubleword Left SDL 31 26 25 21 20 16 15 0 SDL base rt offset 101100 6 5 5 16 Format SDL rt offset base Description This instruction can be used with the SDR instruction to store the contents of a register into eight consecutive bytes of memory when the bytes cross a doubleword boundary SDL stores the left portion of the register into the appropriate part of the high order doubleword of memory SDR stores the right portion of the register into the appropriate part of the low order doubleword The SDL instruction adds its sign extended 16 bit offset to the contents of general register base to form a virtual address w
9. Coprocessor unusable exception MIPS R4000 Microprocessor User s Manual B 25 Appendix B Move Control Word To FPU CTC1 Coprocessor 1 CTC1 31 26 25 21 20 16 15 11 10 0 COP1 CT rt fs 0 010001 00110 00000000000 6 5 5 5 11 Format CTCI rt fs Description The contents of general register rt are loaded into FPU control register fs This operation is only defined when fs equals 0 or 31 Writing to Control Register 31 the floating point Control Status register causes an interrupt or exception if any cause bit and its corresponding enable bit are both set The register will be written before the exception occurs The contents of floating point control register fs are undefined for the instruction immediately following CTC1 Operation 32 T temp GPR rt T 1 FCR fs lt temp COC 1 FCR 31 23 64 T temp GPR ri a4 o T 1 FCR fs temp COC 1 FCR 31 o5 Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Unimplemented operation exception Invalid operation exception Division by zero exception Inexact exception Overflow exception Underflow exception B 26 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details CVT D fmt 55e CVT D fmt Floating Point Format 31 26 25 21 20 16 15 11 10 6 5 0 COP1 fmt 0 fs fd CVT D 010001 00000 100001 6 5 5 5 5 6 Format CV
10. temps o Exceptions None MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details AND And AND 26 25 21 20 16 15 11 10 SPECIAL 0 AND 000000 00000 100100 6 5 6 Format AND rd rs rt Description The contents of general register rs are combined with the contents of general register rt in a bit wise logical AND operation The result is placed into general register rd Operation 32 T GPR rd lt GPR rs and GPR rt 64 T GPhR rd GPR rs and GPR rt Exceptions None MIPS R4000 Microprocessor User s Manual A 15 Appendix A ANDI And Immediate ANDI 26 25 21 20 16 15 ANDI immediate 001100 6 16 Format ANDI rt rs immediate Description The 16 bit immediate is zero extended and combined with the contents of general register rs in a bit wise logical AND operation The result is placed into general register rt Operation 32 T GPR r 016 immediate and GPR rs s o 64 T GPRirt 075 immediate and GPR s s o Exceptions None A 16 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details BCzF Branch On Coprocessor z False BCzF 31 26 25 21 20 16 15 0 COPz BC BCF offset 0100xx 01000 00000 6 5 5 16 Format BCzF offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot
11. MIPS R4000 Microprocessor User s Manual A 43 Appendix A CACHE Code Cach aontinuedi CACH E Bits 20 18 this value is listed under the Code column of the instruction specify the operation as follows Caches Name Operation I SI Index Invalidate Set the cache state of the cache block to Invalid A 44 SD All All Index Writeback Invalidate Index Writeback Invalidate Index Load Tag Index Store Tag Examine the cache state and Writeback bit W bit of the primary data cache block at the index specified by the virtual address If the state is not Invalid and the W bit is set write the block back to the secondary cache if present or to memory if no secondary cache The address to write is taken from the primary cache tag When a secondary cache is present and the CE bit of the Status register is set the contents of the ECC register is XOR d into the computed check bits during the write to the secondary cache for the addressed doubleword Set the cache state of primary cache block to Invalid The Wbit is unchanged and irrelevant because the state is Invalid Examine the cache state of the secondary data cache block at the index specified by the physical address If the block is dirty the state is Dirty Exclusive or Dirty Shared write the data back to memory Like all secondary writebacks the operation writes any modified data for the addresses from the primary data
12. SWR Store Word Right SWR 0 31 26 25 21 20 16 15 SWR 101110 base rt offset 6 5 5 16 Format SWR rt offset base Description This instruction can be used with the SWL instruction to store the contents of a register into four consecutive bytes of memory when the bytes cross a boundary between two words SWR stores the right portion of the register into the appropriate part of the low order word SWL stores the left portion of the register into the appropriate part of the low order word of memory The SWR instruction adds its sign extended 16 bit offset to the contents of general register base to form a virtual address which may specify an arbitrary byte Italters only the word in memory which contains that byte From one to four bytes will be stored depending on the starting byte specified Conceptually it starts at the least significant rightmost byte of the register and copies it to the specified byte in memory then copies bytes from register to memory until it reaches the high order byte of the word in memory No address exceptions due to alignment are possible memory big endian register address 4 4 5 6 7 address 0 before A B C D 24 0 1 2 3 SWR 24 1 0 address 4 address 0 3 after A 158 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details Stor
13. 0 Exceptions Coprocessor unusable exception A 76 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details J Jump J 26 25 J 000010 6 Format J target Description The 26 bit target address is shifted left two bits and combined with the high order bits of the address of the delay slot The program unconditionally jumps to this calculated address with a delay of one instruction Operation 32 T temp lt target T 1 PC lt PCs 5g temp 0 64 T temp lt target T 1 PC PCgs 5g temp 0 Exceptions None MIPS R4000 Microprocessor User s Manual 4 77 Appendix A JAL Jump And Link JAL 31 26 25 0 JAL target 000011 6 26 Format JAL target Description The 26 bit target address is shifted left two bits and combined with the high order bits of the address of the delay slot The program unconditionally jumps to this calculated address with a delay of one instruction The address of the instruction after the delay slot is placed in the link register 731 Operation 32 T temp lt target GPR 31 PC 8 T 1 PC PC a 9 temp 0 64 T temp lt target GPR 31 PC 8 T 1 PC PC gs 5g temp 0 Exceptions None A 78 MIPS R4000 Microprocessor User s Manual JALR CPU Instruction Set Details Jump And Link Register JALR 26 25 21 20 16 15 11 10 SPECIAL 00000
14. 1 6 1 25 Format COPz cofun Description A coprocessor operation is performed The operation may specify and reference internal coprocessor registers and may change the state of the coprocessor condition line but does not modify state within the processor or the cache memory system Details of coprocessor operations are contained in Appendix B Operation 32 64 T CoprocessorOperation z cofun Exceptions Coprocessor unusable exception Coprocessor interrupt or Floating Point Exception R4000 CP1 only Opcode Bit Encoding COPZ sit 3130 29 28 27 26 25 0 copo 0 1 0 09 fo 0 1 Bit 3130 29 28 27 26 25 0 cop 0 1 0 0 0 1 1 Bit 3130 29 28 27 26 25 0 cop2 0 1 0 0 1 0 1 J hs di desee sub opcode see end of Appendix A Coprocessor Unit Number MIPS R4000 Microprocessor User s Manual 4 49 Appendix A CTCz Move Control to Coprocessor CTCz 26 25 21 20 16 15 11 10 COPz CT 0 0100xx 00110 00000000000 6 5 11 Format CTCz rt rd Description The contents of general register rt are loaded into control register rd of coprocessor unit z This instruction is not valid for CPO Operation 32 64 T data GPR rt T 1 CCR zrd data Exceptions Coprocessor unusable See CPU Instruction Opcode Bit Encoding at the end of Appendix A A 50 MIPS R4000 Microprocessor User s Manual CPU Instruction Set De
15. GPRIrtIes GPR rtles s Exceptions Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual A 69 Appendix A DSRA32 Arithmetic 32 DSRA32 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 0 rt rd sa DSRA32 000000 00000 411111 6 5 5 5 5 6 Format DSRA32 rd rt sa Description The contents of general register rt are shifted right by 32 sa bits sign extending the high order bits The result is placed in register rd This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T sella GPR rd GPR rt g3 GPRIrt es A 70 Exceptions Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details DSRL Doubleword DSRL Shift Right Logical 26 25 21 20 16 15 11 10 SPECIAL 0 DSRL 000000 00000 111010 6 5 6 Format DSRL rd rt sa Description The contents of general register rt are shifted right by sa bits inserting zeros into the high order bits The result is placed in register rd This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T seo0 sa GPR rd 0 GPR rt es s Exceptions
16. NullifyCurrentInstruction Exceptions Coprocessor unusable exception Opcode Bit Encoding BCzFL Bit 4 3130 29 28 27 26 25 24 2322 21 20 19 18 17 16 0 BCoFL 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 Bit 3130 29 28 27 26 25 24 2322 21 20 1918 17 16 0 Bcip 0 1 0 0 0 1 0 1 0 0 0 0 0 0 1 0 Bit 3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 gcor 0 11 o o 1 0 o 1 o o o o o o 1 o Nc PN NX Ae A nS Y Yn DA Opcode BC sub opcode Branch condition Coprocessor Unit Number A 20 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details BCzT Branch On Coprocessor z True BCzT 31 26 25 21 20 16 15 COPz BC offset 0100xx 01000 6 5 16 Format BCzT offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended If the coprocessor z s condition signal CpCond is true then the program branches to the target address with a delay of one instruction Because the condition line is sampled during the previous instruction there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line Operation 32 T 1 condition COC z T target lt offsetys offset 07
17. Operation 32 64 T if GPR rs 2 GPR rt then TrapException endif Exceptions Trap exception MIPS R4000 Microprocessor User s Manual A 165 Appendix A TG EI Trap If Greater Than Or Equal Immediate TG EI 31 26 25 21 20 16 15 0 REGIMM rs TGEI immediate 000001 01000 6 5 5 16 Format TGEI rs immediate Description The 16 bit immediate is sign extended and compared to the contents of general register rs Considering both quantities as signed integers if the contents of general register rs are greater than or equal to the sign extended immediate a trap exception occurs Operation if GPR rs gt immediate 5 immediate s 9 then TrapException endif if GPR rs 2 immediate immediate o then TrapException endif Exceptions Trap exception A 166 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details Trap If Greater Than Or Equal TG EI U ed ican TG EI U 31 26 25 21 20 16 15 0 REGIMM rs TGEIU immediate 000001 01001 6 5 5 16 Format TGEIU rs immediate Description The 16 bit immediate is sign extended and compared to the contents of general register rs Considering both quantities as unsigned integers if the contents of general register rs are greater than or equal to the sign extended immediate a trap exception occurs Operation 32 T if 0 GPR rs 0 immediate 5 immediate 5 o the
18. The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LDL or LDR instruction which also specifies register rt No address exceptions due to alignment are possible This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 vAddr lt offset 5 49 offsety5 o GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpgizg 3 pAddrs o xor ReverseEndian if BigEndianMem 0 then pAddr pAddrpsize 1 3 0 endif byte vAddro 9 xor BigEndianCPU mem LoadMemory uncached byte pAddr vAddr DATA GPR rt mem g pyre o GPR rt 55 8 byte 0 MIPS R4000 Microprocessor User s Manual 4 87 Appendix A L D L Load Cond Left L D L Given a doubleword in a register and a doubleword in memory the operation of LDL is as follows LDL Register A B C D E F G H Memory J K L M N O P BigEndianCPU 0 BigEndianCPU 1 vAddr o destination type offset destination type ofisel LEM BEM LEM BEM 0 PBCDEFGH 0 0 7 JKLMNOP 7 0 0 1 OPCDEFGH 1 0 6 JKLMNOPH 6 0 1 2 NOPDEFGH 2 0 5 KLMNOPGH 5 0 2 3 MNOPEFGP 3 0 4 LMNOPFGH 4 0 3 4 L MNOPFGH
19. 32 wora ll GPRIrtl23 8 byte 0 GPR rt temp vAddr lt offset 5 49 offsety5 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpsizg 4 5 pAddra o xor ReverseEndian if BigEndianMem 0 then pAddr pAddrpsize 1 2 0 endif byte vAddr _9 xor BigEndianCPU word vAddrs xor BigEndianCPU mem LoadMemory uncached 0 byte pAddr vAddr DATA temp MeM32 word 8 byte 7 32 word GPR rt o3 g byte 0 GPR rt temp31 temp MIPS R4000 Microprocessor User s Manual A 103 Appendix A Load Word Left LW L continued LW L Given a doubleword in a register and a doubleword in memory the operation of LWL is as follows LWL Register A B C D E F G H Memory J K L M N O P BigEndianCPU 0 BigEndianCPU 1 vAddr o destination type offset destination type 9ffset LEM BEM LEM BEM 0 SSSSPFGH 0 0 7 JSSSSIJKL 3 4 0 1 SSSSOPGH 1 0 6 SSSSJKLH 2 4 1 2 SSSSNOPH 2 0 5 SSSSKLGH 1 4 2 3 SSSSMNOP 3 0 4 SS SSLFGIH O0 4 3 4 SSSSLFGH 0 4 3 SS SSMNOP 3 0 4 5 SSSSKLGH 1 4 2 SSSSNOPH 2 0 5 6 SSSSJKLH 2 4 1 SSSSOPQGH 1 0 6 7 SSSSI JKL 3 4 0 SSSSPFGH 0 0 7 LEM Little endian memory BigEndianMem 0 BEM BigEndianMem 1 Type AccessType see Table 2 1 sent to memory Offset pAddr _ 9 sent to memory S sign extend of destination3 Exceptions TLB refill exception TLB invalid e
20. 6 offset 0 condition GPR rs g3 0 and GPR rs 09 T 1 if condition then PC PC target endif Exceptions None MIPS R4000 Microprocessor User s Manual A 31 Appendix A Branch On Greater BGTZL Than Zero Likely BGTZL 31 26 25 21 20 16 15 0 BGTZL rs 0 offset 010111 00000 6 5 5 16 Format BGTZL rs offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended The contents of general register rs are compared to zero If the contents of general register rs have the sign bit cleared and are not equal to zero then the program branches to the target address with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified Operation 32 T target lt offset s 4 offset 0 condition GPR rs a 0 and GPR rs 092 T 1 if condition then 64 T PC c PC target else NullifyCurrentInstruction endif target lt offset 5 9 offset 0 condition GPR rs gs 0 and GPR rs 09 T 1 if condition then PC lt PC target else NullifyCurrentInstruction endif Exceptions A 32 None MIPS R4000 Microprocessor User s Manual BLEZ Branch on Less Than CPU Instruction Set Details BLEZ Or
21. 64 T BreakpointException Exceptions Breakpoint exception MIPS R4000 Microprocessor User s Manual A 41 Appendix A CACHE Cache CACHE 21 20 16 15 offset 16 Format CACHE op offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address The virtual address is translated to a physical address using the TLB and the 5 bit sub opcode specifies a cache operation for that address If CPO is not usable User or Supervisor mode the CPO enable bit in the Status register is clear and a coprocessor unusable exception is taken The operation of this instruction on any operation cache combination not listed below or on a secondary cache when none is present is undefined The operation of this instruction on uncached addresses is also undefined The Index operation uses part of the virtual address to specify a cache block For a primary cache of ROE bytes with QEINEBITS bytes per tag VAddrcACHEBITS LINEBITS specifies the block For a secondary cache of 2 AFEBITS bytes with 2LINEBITS bytes per tag pPAddrcAcurBriTS LINEBITS specifies the block Index Load Tag also uses vAddry jrprrs 3 to select the doubleword for reading ECC or parity When the CE bit of the Status register is set Hit WriteBack Hit WriteBack Invalidate Index WriteBack Invalidate and Fill also use vAddr qNgprrs 5 to select the doublewo
22. DATA data GPR rt StoreMemory uncached DOUBLEWORD data pAddr vAddr DATA Exceptions A 130 TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception Reserved instruction exception R4000 in 32 bit user mode R4000 in 32 bit supervisor mode MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details SDCz Store Doubleword SDCz From Coprocessor 31 26 25 21 20 16 15 0 SDCz base rt offset 11141xx 6 5 5 16 Format SDCz rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address Coprocessor unit z sources a doubleword which the processor writes to the addressed memory location The data to be stored is defined by individual coprocessor specifications If any of the three least significant bits of the effective address are non Zero an address error exception takes place This instruction is not valid for use with CPO This instruction is undefined when the least significant bit of the rt field is non zero Operation 32 T vAddr c offset s offsetys 9 GPR base pAddr uncached lt AddressTranslation vAddr DATA data COPzSD rt StoreMemory uncached DOUBLEWORD data pAddr vAddr DATA 64 T vAddr c offset s offsets 9 GPR base pAddr uncached AddressTranslation vAddr DATA data
23. MIPS R4000 Microprocessor User s Manual A 81 Appendix A LBU Load Byte Unsigned LBU 31 26 25 21 20 16 15 0 LBU base rt offset 100100 6 5 5 16 Format LBU rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address The contents of the byte at the memory location specified by the effective address are zero extended and loaded into general register rt Operation 32 T vAddr lt offset s offsetys 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpgize 1 3 0Addr2 o xor ReverseEndian mem lt LoadMemory uncached BYTE pAddr vAddr DATA byte vAddrs o xor BigEndianC PU GPR rt 07 memz byte 8 byte 64 T vAddr lt offset 5 8 offset o GPR base pAddr uncached lt AddressTranslation vAddr DATA pAddr pAddrpgizg 1 3 pAddra o xor ReverseEndian mem lt LoadMemory uncached BYTE pAddr vAddr DATA byte vAddra xor BigEndianCPU GPR rt 099 memz a byte 8 byte Exceptions TLB refill exception TLB invalid exception Bus error exception Address error exception A 82 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details L D Load Doubleword L D 31 26 25 21 20 16 15 LD 110111 6 Format LD rt offset base Description The 16 bit offset is sign extended and a
24. Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual A 71 Appendix A DSRLV Logical Variables DSRLV 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL rs rt rd 0 DSRLV 000000 00000 010110 6 5 5 5 5 6 Format DSRLV rd rt rs Description The contents of general register rt are shifted right by the number of bits specified by the low order six bits of general register rs inserting zeros into the high order bits The result is placed in register rd This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T s cGPhRIS s 0 GPR rd 0 GPRI rtle3 s Exceptions Reserved instruction exception R4000 in 32 bit mode A 72 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details DSRL32 Pegicats 32 DSRL32 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 0 rt rd sa DSRL32 000000 00000 111110 6 5 5 5 5 6 Format DSRL32 rd rt sa Description The contents of general register rt are shifted right by 32 sa bits inserting zeros into the high order bits The result is placed in register rd This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation T s lt 1 sa GP
25. T 1 if condition then PC lt PC target endif 64 T 1 condition COC z T target lt offset lt offset 0 T 1 if condition then PC c PC target endif See the table Opcode Bit Encoding on next page or CPU Instruction Opcode Bit Encoding at the end of Appendix A MIPS R4000 Microprocessor User s Manual A 21 Appendix A Branch On Coprocessor z True B CzT continued B CzT Exceptions Coprocessor unusable exception Opcode Bit Encoding BCzT Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 Bcor 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 Bit 91 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 BC1T Bit 91 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 BceT 0 1 0 0 1 0 0 1 00 0 0 0 0 0 1 V A XN A A y Y NGC ne Opcode BC sub opcode Branch condition Coprocessor Unit Number A 22 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details BCzTL BCzTL 31 26 25 21 20 16 15 COPz BC BCTL offset 0100xx 01000 00011 6 5 5 16 Format BCzIL offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended If the contents of coprocessor z s condition line as sampled during the
26. an Invalid operation exception is raised If Invalid operation is not enabled then no exception is taken and 2 is returned MIPS R4000 Microprocessor User s Manual B 59 Appendix B TRUNC W fmt Floating Point TRUNC W fmt Truncate to Single Fixed Point Format continued Operation T StoreFPR fd W ConvertFmt ValueFPR fs fmt fmt W Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception B 60 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details FPU Instruction Opcode Bit Encoding Opcode 28 26 31 29 0 1 2 3 4 5 6 7 0 1 2 COP1 3 4 5 6 LWC1 LDC1 7 SWC1 SDC1 sub 23 21 25 24 0 1 2 3 4 5 6 7 0 MF DMFn CF 5 MT DMTn CT 5 1 BC 5 5 5 5 5 5 2 S D 5 W Ln 5 5 3 5 5 5 5 5 5 5 5 18 16 br 20 19 9 1 2 3 4 5 6 7 0 BCF BCT BCFL BCTL y Y y Y 1 y y y y y y y y 2 Y Y Y Y Y Y Y Y 3 Y Y Y y Y Y Y Y Figure B 3 Bit Encoding for FPU Instructions MIPS R4000 Microprocessor User s Manual B 61 Appendix B 2 0 function 5 3 0 1 2 3 4 5 7 ADD SUB MUL DIV SORT ABS NEG ROUND LT TRUNC LT CEIL LN FLOOR LT ROUND W TRUNC W FLOOR W 5 5 5 5 5 5 CVT Ly 5 C ULT C NGE
27. 1 3 pAddra 9 xor ReverseEndian If BigEndianMem 0 then pAddr lt pAddra 2 0 endif byte vAddr 9 xor BigEndianCPU if vVAddra xor BigEndianCPU 0 then data 0 o Y GPRItt s1__24 8 byte else data 0 4 8 byte GPRIrt ls1 24 8 byte 092 endif StoreMemory uncached byte data pAddr vAddr DATA A 156 MIPS R4000 Microprocessor User s Manual SWL Store Word Left Continued CPU Instruction Set Details SWL Given a doubleword in a register and a doubleword in memory the operation of SWL is as follows SWL Register A B C D E F G H Memory J K L M N O P BigEndianCPU 0 BigEndianCPU 1 offset offset vAddr 9 destination type LEM BEM destination type LEM BEM 0 I JKLMNOE 0 0 7 EF GHMNOP 3 4 0 1 I J KLMNEF 1 0 6 I EF GMNOP 2 4 1 2 I JKLMEFG 2 0 5 J EFMNOP 1 4 2 3 I J KLEFGH 3 0 4 J KEMNOP O0 4 3 4 I JKEMNOP 0 4 3 JKLEFGH 3 0 4 5 JEFMNOP 1 4 2 JKLMEFG 2 0 5 6 EF GMNOP 2 4 1 JKLMNEF 1 0 6 7 EFGHMNOP 3 4 0 J JKLMNOE O0 0 7 LEM Little endian memory BigEndianMem 0 BEM BigEndianMem 1 Type AccessType see Table 2 1 sent to memory Offset pAddr o sent to memory Exceptions TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception MIPS R4000 Microprocessor User s Manual A 157 Appendix A
28. 134 MIPS R4000 Microprocessor User s Manual SDL CPU Instruction Set Details SDL Store Doubleword Left continued Given a doubleword in a register and a doubleword in memory the operation of SDL is as follows SDL Register A B C D E F G H Memory J K L M N O P BigEndianCPU 0 BigEndianCPU 1 offset offset vAddr o destination type EM BEM destination type LEM BEM 0 I J KLMNOA 0 0 7 ABCDEFGH 7 0 0 1 I JKLMNAB 1 0 6 ABCDEF G 6 O0 14 2 I J KLMABC 2 0 5 J ABCDEF 5 0 2 3 I JKLABOCD 3 0 4 1 JKABCDE 4 0 3 4 JKABCDE 4 0 3 I JKLABCD 3 0 4 5 I JABCDEF 5 0 2 I1 JKLMABOC 2 0 5 6 I ABCDEFG 6 0 1 I JKLMNA BI 1 0 6 7 ABCDEFGH 7 0 0 I JKLMNOA 0 0 7 LEM Little endian memory BigEndianMem 0 BEM BigEndianMem 1 Type AccessType see Table 2 1 sent to memory Offset pAddr o sent to memory Exceptions TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual A 135 Appendix A SDR Store Doubleword Right SDR 31 26 25 21 20 16 15 0 SDR base rt offset 101101 6 5 5 16 Format SDR rt offset base Description This instruction can be used with the SDL instruction to store the contents of a register into eight consecutive bytes of mem
29. 2 s complement or floating point multiplication 2 s complement integer division 2 s complement modulo Floating point division 2 s complement less than comparison Bit wise logical AND Bit wise logical OR Bit wise logical XOR Bit wise logical NOR GPRM General Register x The content of GPR 0 is always zero Attempts to alter the content of GPR 0 have no effect CPR z X Coprocessor unit z general register x CCR z X Coprocessor unit z control register x COC Z Coprocessor unit z condition signal BigEndianMem Big endian mode as configured at reset 0 Little 1 Big Specifies the en dianness of the memory interface see LoadMemory and StoreMemory and the endianness of Kernel and Supervisor mode execution ReverseEndian Signal to reverse the endianness of load and store instructions This feature is available in User mode only and is effected by setting the RE bit of the Status register Thus ReverseEndian may be computed as SRos and User mode BigEndianCPU The endianness for load and store instructions 0 Little 1 Big In User mode this endianness may be reversed by setting SRos Thus BigEndianCPU may be computed as BigEndianMem XOR ReverseEndian LLbit Bit of state to specify synchronization instructions Set by LL cleared by ERET and nvalidate and read by SC T i Indicates the time steps betwee
30. 26 25 21 20 16 15 0 BNEL rs rt offset 010101 6 5 5 16 Format BNEL rs rt offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended The contents of general register rs and the contents of general register rt are compared If the two registers are not equal then the program branches to the target address with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified Operation 32 T target lt offset s offset 0 condition GPR rs GPR rt T 1 if condition then PC amp PC target NullifyCurrentInstruction endif 64 T target lt offset 5 6 offset 0 condition GPR rs GPR rt T 1 if condition then PC lt PC target else NullifyCurrentInstruction endif Exceptions None 4 40 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details BREAK Breakpoint BREAK 31 26 25 65 0 SPECIAL code BREAK 000000 001101 6 20 6 Format BREAK Description A breakpoint trap occurs immediately and unconditionally transferring control to the exception handler The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction Operation 32
31. BCF offset 010001 01000 00000 6 5 5 16 Format BCIF offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended If the result of the last floating point compare is false zero the program branches to the target address with a delay of one instruction There must be at least one instruction between C cond fmt and BCIF Operation 32 T 1 condition not COC 1 T target lt offset offset 0 T 1 if condition then PC PC target endif 64 T 1 condition not COC 1 T target lt offset 5 46 offset 0 T 1 ifcondition then PC PC target endif Exceptions Coprocessor unusable exception MIPS R4000 Microprocessor User s Manual B 15 Appendix B BC1FL besser BCIFL 31 26 25 2120 1615 0 COP1 BC BCFL offset 010001 01000 00010 6 5 5 16 Format BCIFL offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended If the result of the last floating point compare is false zero the program branches to the target address with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified There must be at least one instruction betwee
32. R4000 in 32 bit mode A 138 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details SH Store Halfword SH 31 26 25 21 20 16 15 0 base rt offset SH 101001 6 5 5 16 Format SH rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form an unsigned effective address The least significant halfword of register rt is stored at the effective address If the least significant bit of the effective address is non zero an address error exception occurs Operation 32 T vAddr lt offset 5 9 offset s 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpsizg 4 5 pAddre 9 xor ReverseEndian 0 byte lt vAddro 9 xor BigEndianCPU 0 data GPR rtjes ebyte o 09 Ye StoreMemory uncached HALFWORD data pAddr vAddr DATA 64 T vAddr lt offset 5 9 offset s 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpsizg 5 pAddre 9 xor ReverseEndian 0 byte vAddro o xor BigEndianCPU 0 data GPR rt as byte 09 Pte StoreMemory uncached HALFWORD data pAddr vAddr DATA Exceptions TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception MIPS R4000 Microprocessor User s Manual 4 139 Appendix A SLL Shift Left Logical SLL
33. and the 16 bit offset shifted left two bits and sign extended If coprocessor z s condition signal CpCond as sampled during the previous instruction is false then the program branches to the target address with a delay of one instruction Because the condition line is sampled during the previous instruction there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line Operation 32 T 1 condition not COC z T target lt offset s offset 0 T 1 if condition then PC c PC target endif 64 T 1 condition not COC z T target lt offset 5 offset 0 T 1 if condition then PC c PC target endif See the table Opcode Bit Encoding on next page or CPU Instruction Opcode Bit Encoding at the end of Appendix A MIPS R4000 Microprocessor User s Manual 4 17 Appendix A BCzF Branch On Coprocessor z False BCzF continued Exceptions Coprocessor unusable exception Opcode Bit Encoding BCzF Bit 91 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 Bcop 0 1 0 0 0 0 0 1 00 0 0 00 0 0 0 Bit 91 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 BC1F Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 Boor 0 1 0 0 1 0 0 1 0 0 0 0 0 O O O N Jc e pu y Opcod pese BC sub opcode Branch condition Coprocessor Unit Number
34. base Description This instruction can be used in combination with the LDR instruction to load a register with eight consecutive bytes from memory when the bytes cross a doubleword boundary LDL loads the left portion of the register with the appropriate part of the high order doubleword LDR loads the right portion of the register with the appropriate part of the low order doubleword The LDL instruction adds its sign extended 16 bit offset to the contents of general register base to form a virtual address which can specify an arbitrary byte It reads bytes only from the doubleword in memory which contains the specified starting byte From one to eight bytes will be loaded depending on the starting byte specified Conceptually it starts at the specified byte in memory and loads that byte into the high order left most byte of the register then it loads bytes from memory into the register until it reaches the low order byte of the doubleword in memory The least significant right most byte s of the register will not be changed memory big endian address 8 8 9 10 11 12 13 14 15 addesso0 0 1 2 3 4 5 6 7 before register A BCDE FGHI 24 LDL 24 3 0 after 3 4 5 6 7 F GIH 24 A 86 MIPS R4000 Microprocessor User s Manual LDL CPU Instruction Set Details Load Doubleword Left continued L D L
35. cache contains modified data matching blocks with W bit set that modified data is written to memory If the cache block is valid and contains the specified physical address a hit the operation cleans up the primary caches to avoid virtual aliases all blocks in both primary caches that match the secondary line are invalidated without writeback Note that the search for matching primary blocks uses the virtual index of the Plax field of the secondary cache tag the virtual index when the location was last used and not the virtual index of the virtual address used in the operation the virtual index where the location will now be used If the secondary tag and address do not match miss or the tag and address do match hit and the block is in a shared state an invalidate for the specified address is sent over the System interface In all cases the cache block tag must be set to the specified physical address the cache state must be set to Dirty Exclusive and the virtual index field set from the virtual address The CH bit in the Status register is set or cleared to indicate a hit or miss This operation is used to avoid loading data needlessly from secondary cache or memory when writing new contents into an entire cache block If the cache block does not contain the specified address and the block is dirty write it back to the secondary cache if present or otherwise to memory In all cases set the cache block tag to the specified physica
36. ebyre o 09 Y StoreMemory uncached BYTE data pAddr vAddr DATA vAddr offset 5 49 offset o GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrps ze 1 3 pAddre o xor ReverseEndian byte vAddr 9 xor BigEndianCPU data GPR rt es byte o 08 Pte StoreMemory uncached BYTE data pAddr vAddr DATA Exceptions TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception MIPS R4000 Microprocessor User s Manual 4 125 Appendix A SC Store Conditional SC 31 26 25 21 20 16 15 0 SC base rt offset 111000 6 5 5 16 Format SC rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address The contents of general register rt are conditionally stored at the memory location specified by the effective address If any other processor or device has modified the physical address since the time of the previous Load Linked instruction or if an ERET instruction occurs between the Load Linked instruction and this store instruction the store fails and is inhibited from taking place The success or failure of the store operation as defined above is indicated by the contents of general register rt after execution of the instruction A successful store sets the contents of general register rt to 1 an unsucces
37. exception Inexact exception Overflow exception MIPS R4000 Microprocessor User s Manual B 35 Appendix B FLOOR W fmt 997 FLOOR W fmt Fixed Point Format 31 26 25 21 20 16 15 11 10 6 5 0 COP1 010001 fmt 0 fs fd FLOOR W 00000 001111 6 5 5 5 5 6 Format FLOOR W fmt fd fs Description The contents of the floating point register specified by fs are interpreted in the specified source format fmt and arithmetically converted to the single fixed point format The result is placed in the floating point register specified by fd Regardless of the setting of the current rounding mode the conversion is rounded as if the current rounding mode is round to RM 3 This instruction is valid only for conversion from a single or double precision floating point formats The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of adjacent coprocessor general registers When the FR bit in the Status register equals one both even and odd register numbers are valid When the source operand is an Infinity or NaN or the correctly rounded integer result is outside of 22 to 231 1 an Invalid operation exception is raised If Invalid operation is not enabled then no exception is taken and 231_4 is returned MIPS R4000 Microprocessor User s Manual FPU Instruct
38. exception takes precedence This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T vAddr lt offset s offset s 9 GPR base pAddr uncached AddressTranslation vAddr DATA data lt GPR rt if LLbit then StoreMemory uncached DOUBLEWORD data pAddr vAddr DATA endif GPR tt 083 LLbit Exceptions TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual A 129 Appendix A SD Store Doubleword S D 26 25 21 20 16 15 SD offset 111111 6 16 Format SD rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address The contents of general register rt are stored at the memory location specified by the effective address If either of the three least significant bits of the effective address are non zero an address error exception occurs This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T vAddr lt offset 5 9 offsety5 o GPR base pAddr uncached AddressTranslation vAddr
39. floating point coprocessor are stored into processor register rt The contents of register rt are undefined for the instruction immediately following MFC1 The FR bit of the Status register specifies whether all 32 registers of the R4000 are addressable If FR equals zero MFC1 stores either the high or low half of the 16 even Floating Point registers If FR equals one MFC1 stores the low 32 bits of both even and odd Floating Point registers Operation 32 T data FGR fs ai o T 1 GPR rt data 64 T data FGR fs a o T 1 GPR rt datag data Exceptions Coprocessor unusable exception B 42 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details MOV fmt Floating Point Move MOV fmt 31 26 25 21 20 16 15 11 10 65 0 COP1 fmt 0 fs fd MOV 010001 00000 000110 6 5 5 5 5 6 Format MOV fmt fd fs Description The contents of the FPU register specified by fs are interpreted in the specified format and are copied into the FPU register specified by fd The move operation is non arithmetic no IEEE 754 exceptions occur as a result of the instruction This instruction is valid only for single or double precision floating point formats The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of adjacent coprocessor general re
40. in the link register r31 If the contents of general register rs have the sign bit set then the program branches to the target address with a delay of one instruction General register rs may not be general register 31 because such an instruction is not restartable An attempt to execute this instruction with register 31 specified as rs is not trapped however If the conditional branch is not taken the instruction in the branch delay slot is nullified Operation 32 T target c offsets offset 0 condition GPR rs a 1 GPR 31 PC 8 T 1 if condition then PC PC target else NullifyCurrentInstruction endif 64 T target lt offset 5 9 offset 07 condition GPR rs es 1 GPR 81 PC 8 T 1 if condition then PC PC target else NullifyCurrentInstruction endif Exceptions None MIPS R4000 Microprocessor User s Manual 4 37 Appendix A B LTZ L Branch On Less Than Zero Likely B LTZ L 26 25 21 20 16 15 REGIMM BLTZL offset 000001 00010 6 5 16 Format BLTZ rs offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended If the contents of general register rs have the sign bit set then the program branches to the target address with a delay of one instruction If the conditional branch is not taken the instruction in t
41. instruction adds its sign extended 16 bit offset to the contents of general register base to form a virtual address which may specify an arbitrary byte It alters only the word in memory which contains that byte From one to four bytes will be stored depending on the starting byte specified Conceptually it starts at the most significant byte of the register and copies it to the specified byte in memory then it copies bytes from register to memory until it reaches the low order byte of the word in memory No address exceptions due to alignment are possible memory big endian register 4 5 6 7 before A B C D 24 0 1 2 3 SWL 24 1 0 after MIPS R4000 Microprocessor User s Manual A 155 Appendix A SW L Store Word Left SW L Continued Operation 32 T vAddr c offset s offset 45 o GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrps ze 1 3 pAddra 9 xor ReverseEndian If BigEndianMem 0 then pAddr lt pAddrgy__ gt 0 endif byte vAddr 9 xor BigEndianCPU if vVAddra xor BigEndianCPU 0 then data lt 0 o Y GPRIrt s1__24 8 byte else data 0249 byte GPRIrt s1 24 8 byte 092 endif Storememory uncached byte data pAddr vAddr DATA 64 T vAddr lt offset s offset 45 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrps ze
42. integers if the contents of general register rs are less than the contents of general register rt a trap exception occurs The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction Operation 32 64T if 0 GPR rs lt 0 GPR rt then TrapException endif Exceptions Trap exception A 176 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details TN E Trap If Not Equal TN E 26 25 21 20 16 15 SPECIAL TNE 000000 110110 6 6 Format TNE rs rt Description The contents of general register rt are compared to general register rs If the contents of general register rs are not equal to the contents of general register rt a trap exception occurs The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction Operation 32 64T if GPR rs GPR rt then TrapException endif Exceptions Trap exception MIPS R4000 Microprocessor User s Manual A 177 Appendix A TN EI Trap If Not Equal Immediate TN EI 31 26 25 21 20 16 15 0 REGIMM rs TNEI immediate 000001 01110 6 5 5 16 Format TNEI rs immediate Description The 16 bit immediate is sign extended and compared to the contents of general
43. lt value return D L FGR fpr 1 lt valuees 32 FGR fpr lt values o return endcase else undefined result for odd 32 bit reg s undefined result endif B 12 MIPS R4000 Microprocessor User s Manual ABS fmt Floating Point Absolute Value FPU Instruction Set Details ABS fmt 31 26 25 21 20 16 15 11 10 6 5 o COP1 010001 fmt 0 00000 fs fd ABS 000101 5 6 Format ABS fmt fd fs Description The contents of the FPU register specified by fs are interpreted in the specified format and the arithmetic absolute value is taken The result is placed in the floating point register specified by fd The absolute value operation is arithmetic a NaN operand signals invalid Operation This instruction is valid only for single and double precision floating point formats The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of adjacent coprocessor general registers When the FR bit in the Status register equals one both even and odd register numbers are valid Operation T StoreFPR fd fmt AbsoluteValue ValueFPR fs fmt Excep tions Coprocessor unusable exception Coprocessor exception trap Coprocessor Exceptions Unimplemented operation exception Invalid operat
44. order bits The result is placed in register rd In 64 bit mode the operand must be a valid sign extended 32 bit value Operation 32 T s lt GPRIirs q4 o GPR rd GPRIrt 31 GPRIrt 31 5 64 T s lt GPRIrs q 0 temp GPR rt 31 GPR rt 31 s GPR rd temp3 temp Exceptions None MIPS R4000 Microprocessor User s Manual A 147 Appendix A SRL Shift Right Logical SRL 26 25 21 20 16 15 11 10 SPECIAL 0 000000 00000 6 5 Format SRL rd rt sa Description The contents of general register rt are shifted right by sa bits inserting zeros into the high order bits The result is placed in register rd In 64 bit mode the operand must be a valid sign extended 32 bit value Operation 32 T GPR rd 0 GPRIrt 31 sa 64 T seo0l sa temp lt 05 GPRIrt 34 s GPR rd temp31 temp Exceptions None A 148 MIPS R4000 Microprocessor User s Manual SRLV CPU Instruction Set Details Shift Right Logical Variable SRLV 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL rs rt rd 0 SRLV 000000 00000 000110 6 5 5 5 5 6 Format SRLV rd rt rs Description The contents of general register rt are shifted right by the number of bits specified by the low order five bits of general register rs inserting zeros into the high order bits The result is placed in register rd
45. previous instruction is true the target address is branched to with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified Because the condition line is sampled during the previous instruction there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line Operation 32 T 1 condition COC z T target lt offset s offset 0 T 1 if condition then PC amp PC target else NullifyCurrentInstruction endif 64 T 1 condition CoCr T target lt offset s 5 offset 07 T 1 if condition then PC lt PC target NullifyCurrentInstruction else endif See the table Opcode Bit Encoding on next page or CPU Instruction Opcode Bit Encoding at the end of Appendix A MIPS R4000 Microprocessor User s Manual A 23 Appendix A BCzTL Branch Tuck S Z BCzTL continued Exceptions Coprocessor unusable exception Opcode Bit Encoding BCzTL Bit 3130 29 28 27 26 25 24 2322 21 20 1918 17 16 0 BcoTL 9 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 Bit 3130 29 28 27 26 25 24 2322 21 20 1918 17 16 0 Bcim 0 1 0 0 0 1 0 1 0 0 0 0 0 O1 1 Bit 3130 29 28 27 26 25 24 2322 21 20 1918 17 16 0 Bcon 0 110 0 1 0 0 1 0 0 O 0 0 O0 1 1 x EXE a oe 7 v v vo
46. register rs and the contents of general register rt are added to form the result The result is placed into general register rd No overflow exception occurs under any circumstances The only difference between this instruction and the DADD instruction is that DADDU never causes an overflow exception This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T GPR rd GPR rs GPR rt Exceptions Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual DDIV CPU Instruction Set Details Doubleword Divide D DIV 31 26 25 21 20 16 15 6 5 0 SPECIAL rs rt 0 DDIV 000000 00 00000000 011110 6 5 5 10 6 Format DDIV rs rt Description The contents of general register rs are divided by the contents of general register rt treating both operands as 2 s complement values No overflow exception occurs under any circumstances and the result of this operation is undefined when the divisor is zero This instruction is typically followed by additional instructions to check for a zero divisor and for overflow When the operation completes the quotient word of the double result is loaded into special register LO and the remainder word of the double result is loaded into special register HI If either of the two preceding instructions is MFHI
47. rs Description The contents of general register rs are loaded into special register HI If a MTHI operation is executed following a MULT MULTU DIV or DIVU instruction but before any MFLO MFHI MTLO or MTHI instructions the contents of special register LO are undefined Operation 32 64 T 2 HI undefined T 1 HI lt undefined T HI GPR rs Exceptions None A 116 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details MTLO Move To LO MTLO 26 25 2120 0 000000000000000 15 Format MTLO rs Description The contents of general register rs are loaded into special register LO If a MILO operation is executed following a MULT MULTU DIV or DIVU instruction but before any MFLO MFHI MILO or MTHI instructions the contents of special register HI are undefined Operation 32 64 T 2 LO lt undefined T 1 LO lt undefined T LO GPRIrs Exceptions None MIPS R4000 Microprocessor User s Manual A 117 Appendix A MULT Multiply MULT 31 26 25 21 20 16 15 SPECIAL 0 MULT 000000 0000000000 011000 6 10 6 Format MULT rs rt Description The contents of general registers rs and rt are multiplied treating both operands as 32 bit 2 s complement values No integer overflow exception occurs under any circumstances In 64 bit mode the operands must be valid 32 bit sign extended values When the operation completes the low ord
48. z LEM BEM Type Offset Exceptions type O NM WO N Little endian memory BigEndianMem 0 offset LEM BEM NO oR OD oO OO oO fF fF FH BigEndianMem 1 AccessType see Table 2 1 sent to memory destination KLMNO KLMNO HL MNO GHMNO KLHNO KLGHO KLFGH KLEFG pAddr _ o sent to memory TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception I U U U U U U U type On OWN O offset LEM BEM O NN WB OD RA HR HOC OO MIPS R4000 Microprocessor User s Manual SYNC CPU Instruction Set Details Synchronize SYNC 31 26 25 6 5 0 SPECIAL 0 SYNC 000000 0000 0000 0000 0000 0000 001111 6 20 6 Format SYNC Description The SYNC instruction ensures that any loads and stores fetched prior to the present instruction are completed before any loads or stores after this instruction are allowed to start Use of the SYNC instruction to serialize certain memory references may be required in a multiprocessor environment for proper synchronization For example Processor A Processor B SW R1 DATA 1 LW R2 FLAG LI R2 1 BEQ R2 RO 1B SYNC NOP SW R2 FLAG SYNC LW R1 DATA The SYNC in processor A prevents DATA being written after FLAG which could cause processor B to read stale data The SYNC in processor B prevents DATA from being read before FLAG which could likew
49. zero For doubleword loads and stores the access type field is always DOUBLEWORD and the low order three bits of the address must always be zero Regardless of byte numbering order endianness the address specifies that byte which has the smallest byte address in the addressed field For a big endian machine this is the leftmost byte for a little endian machine this is the rightmost byte B 8 MIPS R4000 Microprocessor User s Manual B 4 Computational Instructions Computational instructions include all of the arithmetic floating point operations performed by the FPU FPU Instruction Set Details Figure B 2 shows the R Type instruction format used for computational operations R Type Register 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 COP1 is a 6 bit operation code fmt is a 5 bit format specifier fs is a 5 bit source1 register ft is a 5 bit source2 register fd is a 5 bit destination register function is a 6 bit function field Figure B 2 Computational Instruction Format The function field indicates the floating point operation to be performed Each floating point instruction can be applied to a number of operand formats The operand format for an instruction is specified by the 5 bit format field decoding for this field is shown in Table B 4 Table B 4 Format Field Decoding Code Mnemonic single Binary floating point 17 double Binary floating point
50. 0 6 Format JALR rs JALR rd rs Description The program unconditionally jumps to the address contained in general register rs with a delay of one instruction The address of the instruction after the delay slot is placed in general register rd The default value of rd if omitted in the assembly language instruction is 31 Register specifiers rs and rd may not be equal because such an instruction does not have the same effect when re executed However an attempt to execute this instruction is not trapped and the result of executing such an instruction is undefined Since instructions must be word aligned a Jump and Link Register instruction must specify a target register rs whose two low order bits are zero If these low order bits are not zero an address exception will occur when the jump target instruction is subsequently fetched Operation 32 64 T temp lt GPR rs GPR rd PC 8 T 1 PC temp Exceptions None MIPS R4000 Microprocessor User s Manual A 79 Appendix A JR Jump Register JR 21 20 SPECIAL 0 JR 000000 00000000000 0000 001000 6 15 6 Format JR rs Description The program unconditionally jumps to the address contained in general register rs with a delay of one instruction Since instructions must be word aligned a Jump Register instruction must specify a target register rs whose two low order bits are zero If these l
51. 0 5 5 5 5 6 Format Descr MUL fmt fd fs ft iption The contents of the floating point registers specified by fs and ft are interpreted in the specified format and arithmetically multiplied The result is rounded as if calculated to infinite precision and then rounded to the specified format according to the current rounding mode The result is placed in the floating point register specified by fd This instruction is valid only for single or double precision floating point formats The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of adjacent coprocessor general registers When the FR bit in the Status register equals one both even and odd register numbers are valid Operation T StoreFPR fd fmt ValueFPR fs fmt ValueFPR ft fmt Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Unimplemented operation exception Invalid operation exception Inexact exception Overflow exception Underflow exception MIPS R4000 Microprocessor User s Manual B 45 Appendix B NEG fmt Floating Point Negate NEG fmt 31 26 25 21 20 16 15 11 10 6 5 0 COP1 fmt 0 fs fd NEG 010001 00000 000111 6 5 5 5 5 6 Format NEG fmt fd fs Description The contents of the FPU register spec
52. 4 0 3 MNOPEFGH 3 0 4 5 KLMNOPGH 5 0 2 NOPDEFGH 2 0 5 6 JKLMNOPH 6 0 1 OPCDEFGH 1 0 6 7 I J KLMNOP 7 0 0 PBCDEFGH 0 0 7 LEM Little endian memory BigEndianMem 0 BEM BigEndianMem 1 Type AccessType see Table 2 1 sent to memory Offset pAddr o sent to memory Exceptions TLB refill exception TLB invalid exception Bus error exception Address error exception Reserved instruction exception R4000 in 32 bit mode A 88 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details LD R Load Doubleword Right LD R 26 25 21 20 16 15 0 LDR base offset 011 z 11 16 Format LDR rt offset base Description This instruction can be used in combination with the LDL instruction to load a register with eight consecutive bytes from memory when the bytes cross a doubleword boundary LDR loads the right portion of the register with the appropriate part of the low order doubleword LDL loads the left portion of the register with the appropriate part of the high order doubleword The LDR instruction adds its sign extended 16 bit offset to the contents of general register base to form a virtual address which can specify an arbitrary byte It reads bytes only from the doubleword in memory which contains the specified starting byte From one to eight bytes will be loaded depending on the starting byte specified Conceptually it starts at the specified byte in memory and loads that byte into the low order right most byte
53. Addr DATA pAddr pAddrpgjze 1 3 0Addr2 9 xor ReverseEndian 0 byte vAddr gt o xor BigEndianCPU 0 data GPR rt gs spy 09 5Ye StoreMemory uncached WORD data pAddr vAddr DATA Exceptions TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception A 152 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details SWOz Store Word From Coprocessor SWOz 31 26 25 21 20 16 15 0 SWCz base rt offset 1110x x 6 5 5 16 Format SWCz rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address Coprocessor unit z sources a word which the processor writes to the addressed memory location The data to be stored is defined by individual coprocessor specifications This instruction is not valid for use with CPO If either of the two least significant bits of the effective address is non zero an address error exception occurs Operation 32 T vAddr lt offset s offset 5 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr lt pAddrpsizg 35 pAddra 9 xor ReverseEndian 0 byte vAddrs o xor BigEndianCPU 0 data COPzSW byte rt StoreMemory uncached WORD data pAddr vAddr DATA 64 T vAddr offset s offset 9 GPR base pAddr uncached AddressTrans
54. CPLI Instruction Set Details This appendix provides a detailed description of the operation of each R4000 instruction in both 32 and 64 bit modes The instructions are listed in alphabetical order Exceptions that may occur due to the execution of each instruction are listed after the description of each instruction Descriptions of the immediate cause and manner of handling exceptions are omitted from the instruction descriptions in this appendix Figures at the end of this appendix list the bit encoding for the constant fields of each instruction and the bit encoding for each individual instruction is included with that instruction MIPS R4000 Microprocessor User s Manual A 1 Appendix A A 1 Instruction Classes CPU instructions are divided into the following classes Load and Store instructions move data between memory and general registers They are all I type instructions since the only addressing mode supported is base register 16 bit immediate offset Computational instructions perform arithmetic logical and shift operations on values in registers They occur in both R type both operands are registers and I type one operand is a 16 bit immediate formats Jump and Branch instructions change the control flow of a program Jumps are always made to absolute 26 bit word addresses J type format or register addresses R type for returns and dispatches Branches have 16 bit offsets relative to the program counter I t
55. Equal To Zero 31 26 25 21 20 16 15 0 BLEZ rs 0 offset 000110 00000 6 5 5 16 Format BLEZ rs offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended The contents of general register rs are compared to zero If the contents of general register rs have the sign bit set or are equal to zero then the program branches to the target address with a delay of one instruction Operation 32 T target lt offset s offset 0 condition GPR rs 3 1 or GPR rs 09 T 1 if condition then PC lt PC target endif 64 T target lt offset offset 07 condition GPR rs gs 1 or GPR rs 04 T 1 if condition then PC c PC target endif Exceptions None MIPS R4000 Microprocessor User s Manual A 33 Appendix A B honL Th BLEZL o waTozeouky BLEZL 26 25 21 20 16 15 BLEZL 010110 6 Format BLEZL rs offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended The contents of general register rs is compared to zero If the contents of general register rs have the sign bit set or are equal to zero then the program branches to the target address with a delay of one instruction If the conditional branch is not taken the instruction i
56. From Coprocessor M FCz 26 25 21 20 16 15 11 10 COPz MF 0 0100xx 00000 000 00000000 6 5 11 Format MFCz rt rd Description The contents of coprocessor register rd of coprocessor z are loaded into general register rt Operation 32 T data CPR z rd T 1 GPR rt lt data 64 T ifrdo 0 then data CPR z rd4 O 31 0 else data CPR z rd Oles 32 endif T 1 GPR rt data31 data Exceptions Coprocessor unusable exception See the table Opcode Bit Encoding on next page or CPU Instruction Opcode Bit Encoding at the end of Appendix A A 110 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details Move From Coprocessor M FCz continued M FCz Opcode Bit Encoding MFCz Bit 31 30 29 28 27 26 25 24 23 22 21 0 MFco 90 1 0 0 0 0 010 0 0 0 Bit 31 30 29 28 27 26 25 24 23 22 21 0 MFc1 90 1 0 0 0 1 010 00 0 Bit 31 30 29 28 27 26 25 24 23 22 21 0 MFc2 0 1 0 0 1 0 0 0 010 0 Ss A AN A Opcod d Coprocessor Suboperation Coprocessor Unit Number MIPS R4000 Microprocessor User s Manual A 111 Appendix A MFHI Move From HI MFHI 31 26 25 16 15 11 10 6 5 0 SPECIAL 0 rd 0 MFHI 000000 0000000000 00000 010000 6 10 5 5 6 Format MFHI rd Description The contents of special regi
57. IPS R4000 Microprocessor User s Manual LDR CPU Instruction Set Details Load Doubleword Right continued LDR Given a doubleword in a register and a doubleword in memory the operation of LDR is as follows LDR Register A B C D E F G H Memory J K L M N O P BigEndianCPU 1 type NOOR WD OC offset LEM BEM Oo NUN WB OOD oOoOOoOoOoOoOoO oO oO BigEndianCPU 0 vAddr 9 destination type otfset destination LEM BEM 0 I JKLMNOP 7 0 0 ABCDEFGI 1 AI JKLMNO 6 1 0 JABCDEFIJ 2 ABI JKLMN 5 2 0 JABCDEIJK 3 ABCIJKLM 4 3 0 ABCDIJKL 4 ABCDI JKL 3 4 O JABCIJKLM 5 ABCDEIJK e2 5 0 ABIJKLMN 6 ABCDEFI J 1 6 0 JAI JKLMNO 7 ABCDEFGI 0 7 0 IJKLMNOP LEM Little endian memory BigEndianMem 0 BEM BigEndianMem 1 Type AccessType see Table 2 1 sent to memory Offset pAddr o sent to memory Exceptions TLB refill exception TLB invalid exception Bus error exception Address error exception Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual A 91 Appendix A LH Load Halfword LH 21 20 16 15 offset 16 Format LH rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address The contents of the halfword at the memory location specified by the effective address are sign extended a
58. In 64 bit mode the operand must be a valid sign extended 32 bit value Operation 32 T 64 T s lt GPRIrs q_ o GPR rd 05 GPR rt s amp s GPRIrs q o temp lt 0 GPR ri g GPR rd temp temp Exceptions None MIPS R4000 Microprocessor User s Manual A 149 Appendix A S U B Subtract S U B 26 25 21 20 16 15 11 10 SPECIAL 0 000000 00000 6 5 Format SUB rd rs rt Description The contents of general register rt are subtracted from the contents of general register rs to form a result The result is placed into general register rd In 64 bit mode the operands must be valid sign extended 32 bit values The only difference between this instruction and the SUBU instruction is that SUBU never traps on overflow An integer overflow exception takes place if the carries out of bits 30 and 31 differ 2s complement overflow The destination register rd is not modified when an integer overflow exception occurs Operation 32 T GPR rd e GPR rs GPR rt 64 T temp GPR rs GPR rt GPR rd tempa1 temps o Exceptions Integer overflow exception A 150 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details SUBU Subtract Unsigned SUBU 26 25 21 20 16 15 11 10 SPECIAL 000000 6 Format SUBU rd rs rt Description The contents of general register rt are subtracted from the c
59. In this appendix all variable subfields in an instruction format such as rs rt immediate etc are shown in lowercase names For the sake of clarity we sometimes use an alias for a variable subfield in the formats of specific instructions For example we use rs base in the format for load and store instructions Such an alias is always lower case since it refers to a variable subfield Figures with the actual bit encoding for all the mnemonics are located at the end of this Appendix and the bit encoding also accompanies each instruction In the instruction descriptions that follow the Operation section describes the operation performed by each instruction using a high level language notation The R4000 can operate as either a 32 or 64 bit microprocessor and the operation for both modes is included with the instruction description Special symbols used in the notation are described in Table A 1 A 4 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details Table A 1 CPU Instruction Operation Notations Meaning Assignment Bit string concatenation Replication of bit value x into a y bit string Note xis always a single bit value Selection of bits y through z of bit string x Little endian bit notation is always used If y is less than z this expression is an empty zero length bit string 2 s complement or floating point addition 2 s complement or floating point subtraction
60. LoO TLB Indexs 9131 0 64 T PageMask TLB Indexs oless 192 EntryHi TLB Indexs o 191 128 and not TLB Indexs oless 192 EntryLo1 TLB Indexs 9 127 65 TLB Indexs ol44o EntryLoO TLB Indexs oles 1 TLB Indexs ol44o Exceptions Coprocessor unusable exception A 170 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details TLBWI Write Indexed TLB Entry TLBWI 31 26 25 24 65 0 COPO CO 0 TLBWI 010000 1 0000000000000000000 000010 6 1 19 6 Format TLBWI Description The G bit of the TLB is written with the logical AND of the G bits in the EntryLo0 and EntryLo1 registers The TLB entry pointed at by the contents of the TLB Index register is loaded with the contents of the EntryHi and EntryLo registers The operation is invalid and the results are unspecified if the contents of the TLB Index register are greater than the number of TLB entries in the processor Operation 32 64T TLB Indexs o lt PageMask EntryHi and not PageMask EntryLo1 EntryLoO Exceptions Coprocessor unusable exception MIPS R4000 Microprocessor User s Manual A 171 Appendix A TLBWR Write Random TtBb Entry TLBWR 31 26 25 24 6 5 0 COPO CO 0 TLBWR 010000 1 0000000000000000000 000110 6 1 19 6 Format TLBWR Description The G bit of the TLB is written with the logical AND of the G bits in the EntryLo0 and EntryLo1 registe
61. R rd lt 05 GPR rt s Exceptions Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual A 73 Appendix A DS U B Doubleword Subtract DSU B 26 25 21 20 16 15 11 10 SPECIAL 0 DSUB 000000 00000 101110 6 5 6 Format DSUB rd rs rt Description The contents of general register rt are subtracted from the contents of general register rs to form a result The result is placed into general register rd The only difference between this instruction and the DSUBU instruction is that DSUBU never traps on overflow An integer overflow exception takes place if the carries out of bits 62 and 63 differ 2s complement overflow The destination register rd is not modified when an integer overflow exception occurs This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T GPR rd GPRirs GPR I Exceptions A 74 Integer overflow exception Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details DSU B U Doubleword Subtract Unsigned DSU B U 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL rs rt rd 0 DSUBU 000000 00000 101111 6 5 5 5 5 6 Format DSUBU rd rs rt Description The contents of general register rt are subtracted fro
62. SO id BC1 TL 31 26 25 21 20 16 15 0 COP1 BC BCTL offset 010001 01000 00011 6 5 5 16 Format BCITL offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended If the result of the last floating point compare is true one the program branches to the target address with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified There must be at least one instruction between C cond fmt and BC1TL Operation 32 T 1 condition COC 1 T target lt offset s 4 offset 0 T 1 if condition then PC PC target else NullifyCurrentInstruction endif 64 T 1 condition COC 1 T target lt offset 5 49 offset 0 T 1 if condition then PC PC target else NullifyCurrentInstruction endif Exceptions Coprocessor unusable exception B 18 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details Floating Point C cond fmt Compare C cond fmt 31 26 25 21 20 16 15 11 10 COP1 0 010001 00000 6 Format C cond fmt fs ft Description The contents of the floating point registers specified by fs and ft are interpreted in the specified format fmt and arithmetically compared A result is determined based on the comparison and the co
63. T D fmt fd fs Description The contents of the floating point register specified by fs is interpreted in the specified source format fmt and arithmetically converted to the double binary floating point format The result is placed in the floating point register specified by fd This instruction is valid only for conversions from single floating point format 32 bit or 64 bit fixed point format If the single floating point or single fixed point format is specified the operation is exact The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of adjacent coprocessor general registers When the FR bit in the Status register equals one both even and odd register numbers are valid Operation T StoreFPR fd D ConvertFmt ValueFPR fs fmt fmt D Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception Underflow exception MIPS R4000 Microprocessor User s Manual B 27 Appendix B CVT L fmt cConveriotong CVT L fmt Fixed Point Format 31 26 25 21 20 16 15 11 10 6 5 0 COP1 fmt 0 fs fd CVT L 010001 00000 100101 6 5 5 5 5 6 Format CVT L fmt fd fs Description The contents of the floating point register specified by
64. WR 24 4 0 gt after A B C 4 MIPS R4000 Microprocessor User s Manual A 105 Appendix A LWR A 106 32 Load Word Right continued LWR The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LWR or LWL instruction which also specifies register rt No address exceptions due to alignment are possible Operation T vAddr offset s offsety5 o GPR base pAddr uncached lt AddressTranslation vAddr DATA pAddr pAddrpsizg 4 5 pAddrs o xor ReverseEndian if BigEndianMem 1 then pAddr pAddrps ze 31 3 0 endif byte vAddr 9 xor BigEndianCPU word lt vAddrs xor BigEndianCPU mem lt LoadMemory uncached 0 byte pAddr vAddr DATA temp lt GPRfrt 31 32 8 byte MEM31432 word 32 word 8 byte GPR rt temp vAddr lt offset s offset gt GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrps ze 1 3 pAddrs o xor ReverseEndian if BigEndianMem 1 then pAddr pAddrpgize ai 3 0 endif byte vAddr 9 xor BigEndianCPU word lt vAddro xor BigEndianCPU mem lt LoadMemory uncached 0 byte pAddr vAddr DATA temp GPHR rt a 32 8 byte MEM31432 word 32 word 8 byte GPR rt temp31 temp MIPS R4000 Microprocesso
65. adjacent coprocessor general registers When the FR bit in the Status register equals one both even and odd register numbers are valid When the source operand is an Infinity or NaN or the correctly rounded integer result is outside of 2 to 231 1 the Invalid operation exception is raised If the Invalid operation is not enabled then no exception is taken and 231 1 is returned MIPS R4000 Microprocessor User s Manual B 23 Appendix B Floating Point CEIL W fmt ceiling to single CEIL W fmt Fixed Point Format continued Operation il StoreFPR fd W ConvertFmt ValueFPR fs fmt fmt W Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception B 24 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details CFC1 Move Control Word From FPU CFC1 Coprocessor 1 26 25 21 20 16 15 11 10 COP1 CF 0 010001 00010 0000000 0000 6 5 11 Format CFC1 rt fs Description The contents of the FPU control register fs are loaded into general register rt This operation is only defined when fs equals 0 or 31 The contents of general register rt are undefined for the instruction immediately following CFC1 Operation 32 T temp FCRI fs T 1 GPR rt temp 64 le temp FCR fs T 1 GPR rt lt temp3 temp Exceptions
66. bit mode the loaded word is sign extended Operation 32 T GPR ri immediate 01 64 T GPR rt immediate immediate 016 Exceptions None A 98 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details LW Load Word LW 31 26 25 21 20 16 15 0 LW base rt offset 100011 6 5 5 16 Format LW rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address The contents of the word at the memory location specified by the effective address are loaded into general register rt In 64 bit mode the loaded word is sign extended If either of the two least significant bits of the effective address is non zero an address error exception occurs Operation 32 T vAddr lt offset s offset 5 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpsizg 5 pAddra o xor ReverseEndian 02 mem lt LoadMemory uncached WORD pAddr vAddr DATA byte vAddrs o xor BigEndianCPU 0 GPR It mems e byre g byte 64 T vAddr c offset s offset 5 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpsizg 5 pAddra o xor ReverseEndian 02 mem lt LoadMemory uncached WORD pAddr vAddr DATA byte vAddrs_ 9 xor BigEndianCPU 07 32 GPR rt memM3148 byte MEM3148 byte 8 byt
67. ble result is loaded into special register HI If either of the two preceding instructions is MFHI or MFLO the results of those instructions are undefined Correct operation requires separating reads of HI or LO from writes by two or more instructions MIPS R4000 Microprocessor User s Manual 4 59 Appendix A DIVU Divide Unsigned DIVU continued Operation 32 T 2 LO lt undefined HI lt undefined T 1 LO lt undefined HI lt undefined E LO lt 0 GPR rs div 0 GPR rt HI lt 0 GPR rs mod 0 GPR rt 64 T 2 LO lt undefined HI lt undefined T 1 LO lt undefined HI lt undefined T q lt 0 GPR rs a o div 0 GPR rt a o r lt 0 GPR rs 31 o mod 0 GPR rt a o LO 03 q4 o HI r31 rai o Exceptions None A 60 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details Doubl dM F DMFCO System Control Coprocessol DMFCO 21 20 16 15 0 0000000 0000 11 Format DMFCO rt rd Description The contents of coprocessor register rd of the CPO are loaded into general register rt This operation is defined for the R4000 operating in 64 bit mode and in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception All 64 bits of the general register destination are written from the coprocessor register source The operation of DMFCO on a 32 bit c
68. cache The address to write is taken from the secondary cache tag The Plax field of the secondary tag is used to determine the locations in the primaries to check for matching primary blocks In all cases set the state of the secondary cache block and all matching primary subblocks to Invalid No Invalidate is sent on the R4000 s system interface Read the tag for the cache block at the specified index and place it iinto the TagLo and TagHi CPO registers ignoring any ECC or parity errors Also load the data ECC or parity bits into the ECC register Write the tag for the cache block at the specified index from the TagLo and TagHi CPO registers The processor uses computed parity for the primary caches and the TagLo register in the case of the secondary cache MIPS R4000 Microprocessor User s Manual CACHE Code Caches Name CPU Instruction Set Details Cach continued CACH E Operation 4 SI SD Create Dirty Exclusive Create Dirty Exclusive Hit Invalidate Hit Invalidate Hit Writeback Invalidate This operation is used to avoid loading data needlessly from memory when writing new contents into an entire cache block If the cache block is valid but does not contain the specified address a valid miss the secondary block is vacated The data is written back to memory if dirty and all matching blocks in both primary caches are invalidated As usual during a secondary writeback if the primary data
69. ception Operation 64 T vAddr lt offset 5 9 offset 45 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpgize 1 3 Addr 9 xor ReverseEndian If BigEndianMem 0 then pAddr lt pAddrpgize 31 3 0 endif byte vAddr 9 xor BigEndianCPU data GPR rt gs g yie 09 byte StoreMemory uncached DOUBLEWORD byte data pAddr vAddr DATA MIPS R4000 Microprocessor User s Manual A 137 Appendix A SDR Store Doubleword Right continued SDR Given a doubleword in a register and a doubleword in memory the operation of SDR is as follows SDR Register A B C D E F G H Memory J K L oN OJP BigEndianCPU 0 BigEndianCPU 1 Add T offset AY offset vAdQr o destination type LEM BEM destination type EM BEM 0 ABCDEFGH 7 0 0 HJKLMNOP O0 7 0 1 BCDEFGHP 6 1 0 GHKLMNOP 1 6 0 2 CDEFGHOP 5 2 0 FGHLMNOP 2 5 0 3 DEFGHNOP 4 3 0 EF GHMNOP 3 4 0 4 EFGHMNOP 3 4 0 DEFGHNOP 4 3 0 5 FGHLMNOP 2 5 0 CDEFGHOP 5 2 0 6 GHKLMNOP 1 6 0 BCDEFGHP 6 1 0 7 HJ KLMNOP 0 7 0 ABCDEFGH 7 0 0 LEM Little endian memory BigEndianMem 0 BEM BigEndianMem 1 Type AccessType see Table 2 1 sent to memory Offset pAddr o sent to memory Exceptions TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception Reserved instruction exception
70. ched DOUBLEWORD data pAddr vAddr DATA Exceptions Coprocessor unusable TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception B 52 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details SQRT fmt Zo nos SQRT fmt 31 26 25 21 20 16 15 11 10 6 5 0 COP1 fmt 0 fs fd SQRT 010001 00000 000100 6 5 5 5 5 6 Format SORT fmt fd fs Description The contents of the floating point register specified by fs are interpreted in the specified format and the positive arithmetic square root is taken The result is rounded as if calculated to infinite precision and then rounded to the specified format according to the current rounding mode If the value of fs corresponds to 0 the result will be 0 The result is placed in the floating point register specified by fd This instruction is valid only for single or double precision floating point formats The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of adjacent coprocessor general registers When the FR bit in the Status register equals one both even and odd register numbers are valid Operation T StoreFPR fd fmt SquareRoot ValueFPR fs fmt Exceptions Coprocessor unusable exception Floating Point exception Coprocess
71. ction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual 4 67 Appendix A Doubl d DS RA Shift Right Arithmetic DS RA 26 25 21 20 16 15 11 10 SPECIAL 0 DSRA 000000 00000 111011 6 5 6 Format DSRA rd rt sa Description The contents of general register rt are shifted right by sa bits sign extending the high order bits The result is placed in register rd This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T s lt 0 sa GPR rd GPR rt g3 GPR rt 63 s Exceptions Reserved instruction exception R4000 in 32 bit mode A 68 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details Doubl d Shift Right DS RAV Arithmetic Variable DS RAV 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL rs rt rd 0 DSRAV 000000 00000 010111 6 5 5 5 5 6 Format DSRAV rd rt rs Description The contents of general register rt are shifted right by the number of bits specified by the low order six bits of general register rs sign extending the high order bits The result is placed in register rd This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T s lt GPRIrs s5 0 GPR rd
72. d sign extended If the contents of general register rs have the sign bit cleared then the program branches to the target address with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified Operation 32 T target lt offset s offset 0 condition GPR rs 3 0 T 1 if condition then PC PC target else NullifyCurrentInstruction endif 64 T target lt offset 5 49 offset 0 condition GPR rs gs 0 T 1 if condition then PC amp PC target else NullifyCurrentInstruction endif Exceptions None 4 30 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details BGTZ Branch On Greater Than Zero BGTZ 31 26 25 21 20 16 15 0 BGTZ rs 0 offset 000111 00000 6 5 5 16 Format BGTZ rs offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended The contents of general register rs are compared to zero If the contents of general register rs have the sign bit cleared and are not equal to zero then the program branches to the target address with a delay of one instruction Operation 32 T target lt offset lt 4 offset 0 condition GPR rs 3 0 and GPR rs 09 T 1 if condition then PC PC target endif 64 T target lt offset 5
73. d and Store Conditional can be used to atomically update memory locations as shown L1 LL T1 TO ADD T2 T1 1 SC T2 TO BEQ T2 0 L1 NOP This atomically increments the word addressed by T0 Changing the ADD to an OR changes this to an atomic bit set This instruction is available in User mode and it is not necessary for CPO to be enabled The operation of LL is undefined if the addressed location is uncached and for synchronization between multiple processors the operation of LL is undefined if the addressed location is noncoherent A cache miss that occurs between LL and SC may cause SC to fail so no load or store operation should occur between LL and SC otherwise the SC may never be successful Exceptions also cause SC to fail so persistent exceptions must be avoided If either of the two least significant bits of the effective address are non zero an address error exception takes place MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details Load Linked LL continued LL Operation 32 T vAddr lt offset s offsetys 9 GPR base pAddr uncached lt AddressTranslation vAddr DATA pAddr pAddrpgizg 4 5 pAddra 9 xor ReverseEndian 02 mem lt LoadMemory uncached WORD pAddr vAddr DATA byte vAddrs_ xor BigEndianCPU 0 GPR rt mem3148 byte 8 byte LLbit lt 1 64 T vAddr c offset s offset s 9 GPR base pAddr uncached Addre
74. dded to the contents of general register base to form a virtual address The contents of the 64 bit doubleword at the memory location specified by the effective address are loaded into general register rt If any of the three least significant bits of the effective address are non zero an address error exception occurs This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T vAddr lt offset 5 9 offset s 9 GPR base pAddr uncached AddressTranslation vAddr DATA mem lt LoadMemory uncached DOUBLEWORD pAddr vAddr DATA GPR rt mem Exceptions TLB refill exception TLB invalid exception Bus error exception Address error exception Reserved instruction exception R4000 in 32 bit user mode R4000 in 32 bit supervisor mode MIPS R4000 Microprocessor User s Manual A 83 Appendix A L DCz Load Doubleword To Coprocessor L DCz 31 26 25 21 20 16 15 0 LDCz base rt offset 1101xx 6 5 5 16 Format LDCz rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address The processor reads a doubleword from the addressed memory location and makes the data available to coprocessor unit z The manner in which each coprocessor uses the data is defined by the individual coprocessor sp
75. ddr DATA pAddr pAddrpsizg 5 pAddra o xor ReverseEndian 02 mem lt LoadMemory uncached WORD pAddr vAddr DATA byte vAddra o xor BigEndianCPU 0 COPzLW byte rt mem Exceptions TLB refill exception TLB invalid exception Bus error exception Address error exception Coprocessor unusable exception Opcode Bit Encoding LWCz sit 31 30 29 28 27 26 0 Lweci 1 1 0 0 0 1 Bit 31 30 29 28 27 26 0 Lwce2 1 1 0 0 1 0 Ne IN JA MC Y Opcode Coprocessor Unit Number MIPS R4000 Microprocessor User s Manual A 101 Appendix A LWL Load Word Left LWL 31 26 25 21 20 16 15 0 LWL base rt offset 100010 6 5 5 16 Format LWL rt offset base Description address 4 address 0 A 102 This instruction can be used in combination with the LWR instruction to load a register with four consecutive bytes from memory when the bytes cross a word boundary LWL loads the left portion of the register with the appropriate part of the high order word LWR loads the right portion of the register with the appropriate part of the low order word The LWL instruction adds its sign extended 16 bit offset to the contents of general register base to form a virtual address which can specify an arbitrary byte It reads bytes only from the word in memory which contains the specified starting byte From one to four bytes
76. der bits The result is placed in register rd In 64 bit mode the 32 bit result is sign extended when placed in the destination register It is sign extended for all shift amounts including zero SLLV with a zero shift amount truncates a 64 bit value to 32 bits and then sign extends this 32 bit value SLLV unlike nearly all other word operations does not require an operand to be a properly sign extended word value to produce a valid sign extended word result NOTE SLLV with a shift amount of zero may be treated as a NOP by some assemblers at some optimization levels If using SLLV with a zero shift to truncate 64 bit values check the assembler you are using Operation 32 T s lt GP rs 4 o GPR rd GPR rt 31 s o 03 64 T s lt O GPrirs 4 o temp GPR rt g1 s 0 0 GPR rd temp41 temp Exceptions None MIPS R4000 Microprocessor User s Manual A 141 Appendix A SLT Set On Less Than SLT 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL rs rt rd 0 SLT 000000 00000 101010 6 5 5 5 5 6 Format e SLT rd rs rt Description The contents of general register rt are subtracted from the contents of general register rs Considering both quantities as signed integers if the contents of general register rs are less than the contents of general register rt the result is set to one otherwise the result is set to zero The result is placed into gen
77. dress are loaded into general register rt The loaded word is zero extended If either of the two least significant bits of the effective address is non zero an address error exception occurs This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T vAddr c offset s offset 5 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAdarpsizg 5 pAddra o xor ReverseEndian 02 mem lt LoadMemory uncached WORD pAddr vAddr DATA byte vAddrs_ xor BigEndianCPU 02 GPR rt 0 memg148 byte 8 byte Exceptions TLB refill exception TLB invalid exception Bus error exception Address error exception Reserved instruction exception R4000 in 32 bit mode A 108 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details M F M FCO System Control Coprocessor M FCO 31 26 25 21 20 16 15 11 10 0 COPO MF rt rd 0 010000 00000 00000000000 6 5 5 5 11 Format MFCO rt rd Description The contents of coprocessor register rd of the CPO are loaded into general register rt Operation 32 T data lt CPRIO rd T 1 GPR rt data 64 T data CPR O rd T41 GPR rt datag datas 9 Exceptions Coprocessor unusable exception MIPS R4000 Microprocessor User s Manual A 109 Appendix A M FCz Move
78. e Exceptions TLB refill exception TLB invalid exception Bus error exception Address error exception MIPS R4000 Microprocessor User s Manual A 99 Appendix A LWCz Load Word To Coprocessor LWCz 21 20 16 15 offset 16 Format LWCz rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address The processor reads a word from the addressed memory location and makes the data available to coprocessor unit z The manner in which each coprocessor uses the data is defined by the individual coprocessor specifications If either of the two least significant bits of the effective address is non zero an address error exception occurs This instruction is not valid for use with CPO See the table Opcode Bit Encoding on next page or CPU Instruction Opcode Bit Encoding at the end of Appendix A A 100 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details LWCz Load MS ica ee LWCz Operation 32 T vAddr offset s offsetys 9 GPR base pAddr uncached lt AddressTranslation vAddr DATA pAddr pAddrpsizg i 3 pAddrs 9 xor ReverseEndian 02 mem lt LoadMemory uncached WORD pAddr vAddr DATA byte vAddra o xor BigEndianCPU 0 COPzLW byte rt mem 64 T vAddr offset s offset s 9 GPR base pAddr uncached e AddressTranslation vA
79. e Word Right SWR Continued SWR Operation 32 T vAddr lt offset s offset 45 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrps ze 1 3 pAddra 9 xor ReverseEndian If BigEndianMem 0 then pAddr lt pAddra 0 endif byte vAddr 9 xor BigEndianCPU if vVAddra xor BigEndianCPU 0 then data 0 GPR rt 31 s byte 0 08 e else data GPR rt 31 8 byte 0 08 Ye 0 endif Storememory uncached WORD byte data pAddr vAddr DATA 64 T vAddr lt offset 5 9 offset amp 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrps ze 1 3 pAddra 9 xor ReverseEndian If BigEndianMem 0 then pAddr lt pAddra 0 endif byte vAddr 9 xor BigEndianC PU if vVAddra xor BigEndianCPU 0 then data 0 GPR rt 31 s byte 0 08 e else data GPR r 31 8 byte 0 09 Pte 092 endif StoreMemory uncached WORD byte data pAddr vAddr DATA MIPS R4000 Microprocessor User s Manual 4 159 Appendix A SWR A 160 vAddr o NOOR WN O Store Word Right Continued SWR Given a doubleword in a register and a doubleword in memory the operation of SWR is as follows SWR Register Memory BigEndianCPU 0 BigEndianCPU 1 destination JKLEF GH JKLFGHP JKLGHOP JKLHNOP FGHMNOP GHLMNOP HKLMNOP JKLMNOP Io Tn m
80. e operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of adjacent coprocessor general registers When the FR bit in the Status register equals one both even and odd register numbers are valid When the source operand is an Infinity or NaN or the correctly rounded integer result is outside of 2 to 231 1 an Invalid operation exception is raised If Invalid operation is not enabled then no exception is taken and 291 _1 is returned Operation T StoreFPR fd W ConvertFmt ValueFPR fs fmt fmt W Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details DIV fmt Floating Point Divide DIV fmt 31 26 25 21 20 16 15 11 10 6 5 0 COP1 fmt ft fs fd DIV 010001 000011 6 5 5 5 5 6 Format DIV fmt fd fs ft Description The contents of the floating point registers specified by fs and ft are interpreted in the specified format and the value in the fs field is divided by the value in the ft field The result is rounded as if calculated to infinite precision and then rounded to the specified format according to the current rounding mode The result is placed in the float
81. e virtual address The function fails and an exception is taken if the required translation is not present in the TLB LoadMemory StoreMemory Uses the cache and main memory to find the contents of the word containing the specified physical address The low order two bits of the address and the Access Type field indicates which of each of the four bytes within the data word need to be returned If the cache is enabled for this access the entire word is returned and loaded into the cache Uses the cache write buffer and main memory to store the word or part of word specified as data in the word containing the specified physical address The low order two bits of the address and the Access Type field indicates which of each of the four bytes within the data word should be stored MIPS R4000 Microprocessor User s Manual B 7 Appendix B Figure B 1 shows the I Type instruction format used by load and store operations I Type Immediate 31 26 25 21 20 16 15 0 offset op is a 6 bit operation code base isthe 5 bit base register specifier is a 5 bit source for stores or destination for loads FPA register ft ds specifier offset is the 16 bit signed immediate offset Figure B 1 Load and Store Instruction Format All coprocessor loads and stores reference aligned data items Thus for word loads and stores the access type field is always WORD and the low order two bits of the address must always be
82. ecifications If any of the three least significant bits of the effective address are non Zero an address error exception takes place This instruction is not valid for use with CPO This instruction is undefined when the least significant bit of the rt field is non zero See the table Opcode Bit Encoding on next page or CPU Instruction Opcode Bit Encoding at the end of Appendix A A 84 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details LDCz Load Doubleword To Coprocessor LDCz continued Operation 32 T vAddr lt offset s offset s 9 GPR base pAddr uncached AddressTranslation vAddr DATA mem lt LoadMemory uncached DOUBLEWORD pAddr vAddr DATA COPzLD rt mem 64 T vAddr lt offset s offset s 9 GPR base pAddr uncached lt AddressTranslation vAddr DATA mem lt LoadMemory uncached DOUBLEWORD pAddr vAddr DATA COPZLD rt mem Exceptions TLB refill exception TLB invalid exception Bus error exception Address error exception Coprocessor unusable exception Opcode Bit Encoding LDCz 8 43 30 29 28 27 26 LDC 1 1 0 1 Bit 31 30 29 28 1 0 1 LDc2 1 ks Opc de Coprocessor Unit Number MIPS R4000 Microprocessor User s Manual A 85 Appendix A L D L Load Doubleword Left L D L 21 20 offset 16 Format LDL rt offset
83. ed into general register rd In 64 bit mode the operands must be valid sign extended 32 bit values An overflow exception occurs if the carries out of bits 30 and 31 differ 2 s complement overflow The destination register rd is not modified when an integer overflow exception occurs Operation 32 T GPR rd GPR rs GPR rt 64 T temp GPR rs GPR rt GPRIrd tempa1 temps o Exceptions Integer overflow exception MIPS R4000 Microprocessor User s Manual A 11 Appendix A ADDI Add Immediate ADDI 26 25 21 20 16 15 ADDI immediate 001000 6 16 Format ADDI rt rs immediate Description The 16 bit immediate is sign extended and added to the contents of general register rs to form the result The result is placed into general register rt In 64 bit mode the operand must be valid sign extended 32 bit values An overflow exception occurs if carries out of bits 30 and 31 differ 2 s complement overflow The destination register rt is not modified when an integer overflow exception occurs Operation 32 T GPR rt GPR rs immediate 5 9 immediate s5 o 64 T temp GPR rs immediate 5 9 immediate 5 o GPR rt tempa temp o Exceptions Integer overflow exception A 12 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details ADDIU Add Immediate Unsigned ADDIU 26 25 21 20 16 15 ADDIU immediate
84. er odd or even registers If any of the three least significant bits of the effective address are non Zero an address error exception takes place MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details Load Doubl d to FPU LDC1 PM Coprocessor 1 LDC1 continued Operation 32 T vAddr lt offset s offset s 9 GPR base 64 T vAddr lt offset s offsets 9 GPR base 32 64 pAddr uncached AddressTranslation vAddr DATA data LoadMemory uncached DOUBLEWORD pAddr vAddr DATA if SRog 1 then 64 bit wide FGRs FGR ft data elseif fty 0 then valid specifier 32 bit wide FGRs FGR ft 1 datag3 _ 30 FGR ft data3 1_ 0 else undefined result if odd undefined result endif Exceptions Coprocessor unusable TLB refill exception TLB invalid exception Bus error exception Address error exception MIPS R4000 Microprocessor User s Manual B 39 Appendix B Load Word to FPU LWC1 Coprocessor 1 LWC1 31 26 25 21 20 16 15 0 LWC1 base ft offset 110001 6 5 5 16 Format LWCI ft offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form an unsigned effective address The contents of the word at the memory location specified by the effective address is loaded into register ft of the floating point coprocessor The FR bit of the Status register specifies whet
85. er rd No integer overflow exception occurs under any circumstances The comparison is valid even if the subtraction used during the comparison overflows Operation 32 T if 0 GPR rs lt 0 GPR rt then GPR rd 03 1 else GPR rd lt 09 endif 64 T if 0 GPR rs lt 0 GPR rt then GPR rd 0 1 else GPR rd 094 endif Exceptions None MIPS R4000 Microprocessor User s Manual A 145 Appendix A SRA Shift Right Arithmetic 26 25 21 20 16 15 11 10 SPECIAL 0 000000 00000 6 5 Format SRA rd rt sa Description The contents of general register rt are shifted right by sa bits sign extending the high order bits The result is placed in register rd In 64 bit mode the operand must be a valid sign extended 32 bit value Operation 32 T GPR rd GPRIrt 31 2 GPRIrt 34 sa 64 T s lt O lsa temp lt GPR rt s GPRIrt 31 GPR rd temp31 temp Exceptions None A 146 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details SRAV Arithmetic Variable SRAV 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL rs rt rd 0 SRAV 000000 00000 000111 6 5 5 5 5 6 Format SRAV rd rt rs Description The contents of general register rt are shifted right by the number of bits specified by the low order five bits of general register rs sign extending the high
86. er word of the double result is loaded into special register LO and the high order word of the double result is loaded into special register HI If either of the two preceding instructions is MFHI or MFLO the results of these instructions are undefined Correct operation requires separating reads of HI or LO from writes by a minimum of two other instructions A 118 MIPS R4000 Microprocessor User s Manual MULT Operation Exceptions None 64 T 2 LO HI LO HI LO HI LO HI LO HI LO HI CPU Instruction Set Details Multiply continued lt undefined lt undefined lt undefined lt undefined lt GPR rs GPR rt lt 131 0 163 32 lt undefined lt undefined lt undefined lt undefined lt GPR rs 31_ 0 GPR rt 314 0 amp t31 t31 0 t3 tea 32 MIPS R4000 Microprocessor User s Manual MULT A 119 Appendix A MULTU Multiply Unsigned MULTU 26 25 21 20 16 15 6 5 0 SPECIAL MULTU 200902 00 onc 011001 10 6 Format MULTU rs rt Description The contents of general register rs and the contents of general register rt are multiplied treating both operands as unsigned values No overflow exception occurs under any circumstances In 64 bit mode the operands must be valid 32 bit sign extended values When the operation completes the low order word of the double result is loaded into special register LO and the high order w
87. eral register rd No integer overflow exception occurs under any circumstances The comparison is valid even if the subtraction used during the comparison overflows Operation 32 T ifGPR r GPR r then GPR rd 03 1 else GPR rd 09 endif 64 T ifGPR rs lt GPR rI then GPR rd 082 1 else GPR rd 064 endif Exceptions None A 142 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details SLTI Set On Less Than Immediate SLTI 31 26 25 21 20 16 15 0 SLTI rs rt immediate 001010 6 5 5 16 Format SLTI rt rs immediate Description The 16 bit immediate is sign extended and subtracted from the contents of general register rs Considering both quantities as signed integers if rs is less than the sign extended immediate the result is set to one otherwise the result is set to zero The result is placed into general register rt No integer overflow exception occurs under any circumstances The comparison is valid even if the subtraction used during the comparison overflows Operation 32 T ifGPR rs lt immediate 5 immediate 5 9 then GPR rd 0 1 else GPR rd 09 endif 64 T ifGPR rs lt immediate s immediate s o then GPR rd 083 1 else GPR rd 094 endif Exceptions None MIPS R4000 Microprocessor User s Manual A 143 Appendix A Set On Less Than SLTI U Immediate Unsigned SLTI U
88. et Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended Unconditionally the address of the instruction after the delay slot is placed in the link register r31 If the contents of general register rs have the sign bit set then the program branches to the target address with a delay of one instruction General register rs may not be general register 31 because such an instruction is not restartable An attempt to execute this instruction with register 31 specified as rs is not trapped however Operation 32 T target offset 5 offset 0 condition GPR rs 3 1 GPR 31 PC 8 T 1 if condition then PC c PC target endif 64 T target lt offset 5 46 offset 0 condition GPR rs es 1 GPR 31 PC 8 T 1 if condition then PC c PC target endif Exceptions None 4 36 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details BLTZALL than zero and Link Likely BLTZALL 31 26 25 21 20 16 15 0 REGIMM rs BLTZALL offset 000001 10010 6 5 5 16 Format BLTZALL rs offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended Unconditionally the address of the instruction after the delay slot is placed
89. et or cleared to indicate a hit or miss Fill Fill the primary instruction cache block from secondary cache or memory If the CE bit of the Status register is set the content of the ECC register is used instead of the computed parity bits for addressed doubleword when written to the instruction cache For the R4000PC the cache is filled from memory For the R4000SC and R4000MC the cache is filled from the secondary cache whether or not the secondary cache block is valid or contains the specified address SD Hit Writeback Hit Writeback If the cache block contains the specified address and the W bit is set write back the data The W bit is not cleared a subsequent miss to the block will write it back again This second writeback is redundant but not incorrect When a secondary cache is present and the CE bit of the Status register is set the content of the ECC register is XOR d into the computed check bits during the write to the secondary cache for the addressed doubleword Note The W bit is not cleared during this operation due to an artifact of the implementation the W bit is implemented as part of the data side of the cache array so that it can be written during a data write If the cache block contains the specified address and the cache state is Dirty Exclusive or Dirty Shared data is written back to memory The cache state is unchanged a subsequent miss to the block causes it to be written back again This sec
90. fined Correct operation requires separating reads of HI or LO from writes by two or more instructions This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T 2 LO lt undefined HI lt undefined T 1 LO lt undefined HI lt undefined T LO 0 GPR rs div 0 GPR rt HI lt 0 GPR rs mod 0 GPR rt Exceptions Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual DIV CPU Instruction Set Details Divide DIV 81 26 25 21 20 16 15 6 5 0 SPECIAL z rt 0 DIV 000000 00 00000000 011010 6 5 5 10 6 Format DIV rs rt Description The contents of general register rs are divided by the contents of general register rt treating both operands as 2 s complement values Nooverflow exception occurs under any circumstances and the result of this operation is undefined when the divisor is zero In 64 bit mode the operands must be valid sign extended 32 bit values This instruction is typically followed by additional instructions to check for a zero divisor and for overflow When the operation completes the quotient word of the double result is loaded into special register LO and the remainder word of the double result is loaded into special register HI If either of the two preceding instructions is MFHI
91. for certain formats Implementations may support some of these formats and operations through emulation but they only need to support combinations that are valid marked V in Table B 1 Combinations marked R in Table B 1 are not currently specified by this architecture and cause an unimplemented operation trap They will be available for future extensions to the architecture MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details Table B 1 Valid FPU Instruction Formats Oyeradon Source Format Single Double Word Longword ADD V V R R MUL V V R R SORT y v ABS V V R R NEG y v TRUNC L V V FLOOR L V V uxpW v Y __ CEIL W V V CVT D V V V c y y MIPS R4000 Microprocessor User s Manual B Co Appendix B The coprocessor branch on condition true false instructions can be used to logically negate any predicate Thus the 32 possible conditions require only 16 distinct comparisons as shown in Table B 2 below Table B 2 Logical Negation of Predicates by Condition True False Condition Relations Invalid ration Mnemonic Greater Bic noi ie True Unordered F F F F EQ UEQ F T T OLE T T F Zi NGLE F F T LT F T F F NGT B 4 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details Floating Point Loads Stores and Moves All movement of data between the floating point coprocessor and memory is accom
92. format operations are not provided MIPS R4000 Microprocessor User s Manual B 5 Appendix B B 2 Instruction Notation Conventions In this appendix all variable subfields in an instruction format such as fs ft immediate and so on are shown in lower case The instruction name such as ADD SUB and so on is shown in upper case For the sake of clarity we sometimes use an alias for a variable subfield in the formats of specific instructions For example we use rs base in the format for load and store instructions Such an alias is always lower case since it refers to a variable subfield In some instructions the instruction subfields op and function can have constant 6 bit values When reference is made to these instructions upper case mnemonics are used For instance in the floating point ADD instruction we use op COP1 and function ADD In other cases a single field has both fixed and variable subfields so the name contains both upper and lower case characters Bit encodings for mnemonics are shown in Figure B 3 at the end of this appendix and are also included with each individual instruction In the instruction description examples that follow the Operation section describes the operation performed by each instruction using a high level language notation Instruction Notation Examples The following examples illustrate the application of some of the instruction notation conventions Example 1 GPR t lt im
93. fs are interpreted in the specified source format fmt and arithmetically converted to the long fixed point format The result is placed in the floating point register specified by fd This instruction is valid only for conversions from single or double precision floating point formats The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero When the source operand is an Infinity NaN or the correctly rounded integer result is outside of 263 to 2691 the Invalid Operation exception is raised Ifthe Invalid operation is not enabled then no exception is taken and 263 1 is returned Operation T StoreFPR fd L ConvertFmt ValueFPR fs fmt fmt L Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception B 28 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details CVT S fmt convetiosige CVT S fmt Floating Point Format 26 25 21 20 16 15 11 10 COP1 0 CVT S 010001 00000 100000 6 6 Format CVT S fmt fd fs Description The contents of the floating point register specified by fs are interpreted in the specified source format fmt and arithmetically converted to the single binary floating point format The result is placed in the floating point register specified by fd R
94. gisters When the FR bit in the Status register equals one both even and odd register numbers are valid Operation StoreFPR fd fmt ValueFPR fs fmt Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Unimplemented operation exception MIPS R4000 Microprocessor User s Manual B 43 Appendix B M To FPU MTC 1 iCoproceseor 1 MTC1 31 26 25 21 20 16 15 11 10 0 COP1 MT rt fs 0 010001 00100 000 0000 0000 6 5 5 5 11 Format MTCI1 rt fs Description The contents of register rt are loaded into the FPU general register at location fs The contents of floating point register fs is undefined for the instruction immediately following MTC1 The FR bit of the Status register specifies whether all 32 registers of the R4000 are addressable If FR equals zero MTC1 loads either the high or low half of the 16 even Floating Point registers If FR equals one MTC1 loads the low 32 bits of both even and odd Floating Point registers Operation 32 64 T data GPRIrt 3 _ o T 1 ifSRag 1then 64 bit wide FGRs FGR fs undefined data else 32 bit wide FGRs FGR fs data endif Exceptions Coprocessor unusable exception B 44 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details MUL fmt Floating Point Multiply MUL fmt 31 26 25 21 20 16 15 11 10 6 5 0 COP1 010001 fmt ft fs fd MUL 00001
95. hardware interlocks requiring additional real cycles so scheduling load delay slots is still desirable although not required for functional code Two special instructions are provided in the RA000 implementation of the MIPS ISA Load Linked and Store Conditional These instructions are used in carefully coded sequences to provide one of several synchronization primitives including test and set bit level locks semaphores and sequencers event counts In the load and store descriptions the functions listed in Table A 2 are used to summarize the handling of virtual addresses and physical memory Table A 2 Load and Store Common Functions Function Meaning AddressTranslation LoadMemory Uses the TLB to find the physical address given the virtual address The function fails and an exception is taken if the required translation is not present in the TLB Uses the cache and main memory to find the contents of the word containing the specified physical address The low order two bits of the address and the Access Type field indicates which of each of the four bytes within the data word need to be returned If the cache is enabled for this access the entire word is returned and loaded into the cache StoreMemory Uses the cache write buffer and main memory to store the word or part of word specified as data in the word containing the specified physical address The low order two bits of the address and the Acces
96. he branch delay slot is nullified Operation 32 T target lt offset 5 offset 0 condition GPR rs 3 1 T 1 if condition then PC c PC target NullifyCurrentInstruction endif 64 T target lt offset 5 46 offset 07 condition GPR rs es 1 T 1 if condition then PC lt PC target else NullifyCurrentInstruction endif Exceptions None 4 38 MIPS R4000 Microprocessor User s Manual BNE CPU Instruction Set Details Branch On Not Equal BN E 31 26 25 21 20 16 15 0 BNE rs rt offset 000101 6 5 5 16 Format BNE rs rt offset Description Operat A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended The contents of general register rs and the contents of general register rt are compared If the two registers are not equal then the program branches to the target address with a delay of one instruction ion 32 T T 1 if condition then target offset c offset 0 condition GPR rs GPR rt PC lt PC target endif 64 T target offset 5 46 offset 0 condition GPR rs GPR rt T 1 if condition then PC lt PC target endif Exceptions None MIPS R4000 Microprocessor User s Manual A 39 Appendix A BN EL Branch On Not Equal Likely BNEL 31
97. he operation of LLD is undefined if the addressed location is noncoherent A cache miss that occurs between LLD and SCD may cause SCD to fail so no load or store operation should occur between LLD and SCD otherwise the SCD may never be successful Exceptions also cause SCD to fail so persistent exceptions must be avoided This instruction is available in User mode and it is not necessary for CPO to be enabled If any of the three least significant bits of the effective address are non Zero an address error exception takes place This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T vAddr lt offset 5 9 offset 5 9 GPR base pAddr uncached AddressTranslation vAddr DATA mem LoadMemory uncached DOUBLEWORD pAddr vAddr DATA GPR rt lt mem LLbit 1 Exceptions TLB refill exception TLB invalid exception Bus error exception Address error exception Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual 4 97 Appendix A L UI Load Upper Immediate LUI 31 26 25 21 20 16 15 0 rt immediate LUI 0 001111 00000 6 5 5 16 Format LUI rt immediate Description The 16 bit immediate is shifted left 16 bits and concatenated to 16 bits of zeros The result is placed into general register rt In 64
98. her all 64 bit Floating Point registers are addressable If FR equals zero LWC1 loads either the high or low half of the 16 even Floating Point registers If FR equals one LWC1 loads the low 32 bits of both even and odd Floating Point registers If either of the two least significant bits of the effective address is non zero an address error exception occurs B 40 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details Load Word to FPU LWC1 Goprocaseor 1 LWC1 continued Operation 32 T vAddr lt offset s offsety5 o GPR base 64 T vAddr lt offset s offsets 9 GPR base 32 64 pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpgijze 1 3 pAddra 9 xor ReverseEndian 02 mem lt LoadMemory uncached WORD pAddr vAddr DATA byte vAddr gt 9 xor BigEndianCPU 07 mem is aligned 64 bits from memory Pick out correct bytes if SRog 1 then 64 bit wide FGRs FGR ft undefined mems1 s byte 8 byte else 32 bit wide FGRs FGR ft mems31 8 pyte 8 byte endif Exceptions Coprocessor unusable TLB refill exception TLB invalid exception Bus error exception Address error exception MIPS R4000 Microprocessor User s Manual B 41 Appendix B M F FPU M FC1 CODIOCSSSO 1 M FC1 21 20 16 15 11 10 0 00000000000 11 Format MFCI1 rt fs Description The contents of register fs from the
99. hich may specify an arbitrary byte It alters only the word in memory which contains that byte From one to four bytes will be stored depending on the starting byte specified Conceptually it starts at the most significant byte of the register and copies it to the specified byte in memory then it copies bytes from register to memory until it reaches the low order byte of the word in memory No address exceptions due to alignment are possible memory big endian register address 8 8 9 10 11 12 13 14 15 address 0 0 1121314151617 before A B C D E F G H 24 SDL 24 1 0 address 8 8 9 10 11 12 13 14 15 after address0 0 B C DI EIF GI H MIPS R4000 Microprocessor User s Manual A 133 Appendix A SDL Store Doubleword Left continued SD L This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T vAddr lt offset s offset 45 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrps ze 1 3 pAddra 9 xor ReverseEndian If BigEndianMem 0 then pAddr lt pAddr 4 0 endif byte vAddrs o xor BigEndianCPU data 096 9 Y GPR rt es 5e eye Storememory uncached byte data pAddr vAddr DATA A
100. ified by fs are interpreted in the specified format and the arithmetic negation is taken polarity of the sign bitis changed The result is placed in the FPU register specified by fd The negate operation is arithmetic an NaN operand signals invalid operation This instruction is valid only for single or double precision floating point formats The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of adjacent coprocessor general registers When the FR bit in the Status register equals one both even and odd register numbers are valid Operation T StoreFPR fd fmt Negate ValueFPR fs fmt Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Unimplemented operation exception Invalid operation exception B 46 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details ROUND L fmt konserton ROUND L fmt Fixed Point Format 26 25 21 20 16 15 11 10 COP1 0 ROUND L 010001 00000 001000 6 5 6 Format ROUND L fmt fd fs Description The contents of the floating point register specified by fs are interpreted in the specified source format fmt and arithmetically converted to the long fixed point format The result is placed in the floating point register specified by fd Regardless of the setting of the current rou
101. ignificant bit of the effective address is non zero an address error exception occurs Operation 32 T vAddr lt offset s offsetys 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpsizg 1 3 pAddra 9 xor ReverseEndian 0 mem lt LoadMemory uncached HALFWORD pAddr vAddr DATA byte vAddr o xor BigEndianCPU 0 GPRIrt 0 memis e byte a byte 64 T vAddr lt offset s offset s 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpgize 1 3 pAddrs_9 xor ReverseEndian 0 mem lt LoadMemory uncached HALFWORD pAddr vAddr DATA byte vAddro_ o xor BigEndianCPU 0 GPR rt lt 0 9 mem15 s byte e byte Exceptions TLB refill exception TLB invalid exception Bus Error exception Address error exception MIPS R4000 Microprocessor User s Manual A 93 Appendix A LL Load Linked LL 26 25 21 20 16 15 LL offset 110000 6 16 Format LL rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address The contents of the word at the memory location specified by the effective address are loaded into general register rt In 64 bit mode the loaded word is sign extended The processor begins checking the accessed word for modification by other processor and devices Load Linke
102. igure A 2 R4000 Opcode Bit Encoding A 181 Appendix A CPO Function 3 3 0 1 2 3 0 1 2 3 Figure A 2 cont R4000 Opcode Bit Encoding Operation codes marked with an asterisk cause reserved instruction exceptions in all current implementations and are reserved for future versions of the architecture y Operation codes marked with a gamma cause a reserved instruction exception They are reserved for future versions of the architecture Operation codes marked with a delta are valid only for R4000 processors with CPO enabled and cause a reserved instruction exception on other processors Operation codes marked with a phi are invalid but do not cause reserved instruction exceptions in R4000 implementations Operation codes marked with a xi cause a reserved instruction exception on R4000 processors X Operation codes marked with a chi are valid only on R4000 Operation codes marked with epsilon are valid when the processor is operating either in the Kernel mode or in the 64 bit non Kernel User or Supervisor mode These instructions cause a reserved instruction exception if 64 bit operation is not enabled in User or Supervisor mode A 182 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details This appendix provides a detailed description of each floating point unit FPU instruction refer
103. ing point register specified by fd This instruction is valid for only single or double precision floating point formats The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of adjacent coprocessor general registers When the FR bit in the Status register equals one both even and odd register numbers are valid Operation T StoreFPR fd fmt ValueFPR fs fmt ValueFPR ft fmt Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Unimplemented operation exception Invalid operation exception Division by zero exception Inexact exception Overflow exception Underflow exception MIPS R4000 Microprocessor User s Manual B 31 Appendix B DMFC1 Doubleword Move From DMFC1 Floating Point Coprocessor 26 25 21 20 16 15 COP1 0 010001 000 00000000 6 11 Format DMEC I rt fs Description The contents of register fs from the floating point coprocessor is stored into processor register rt The contents of general register rt are undefined for the instruction immediately following DMFC1 The FR bit in the Status register specifies whether all 32 registers of the R4000 are addressable When FR equals zero this instruction is not defined when the least significant bit of fs is non zero When FR is set fs may specify either odd
104. integers if the contents of general register rs are less than the sign extended immediate a trap exception occurs Operation 32 T if GPR rs lt immediate 6 immediate s 9 then TrapException endif 64 T if GPR rs lt immediate 5 9 immediate s o then TrapException endif Exceptions Trap exception A 174 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details TLTI U Trap If Less Than Immediate Unsigned TLTI U 31 26 25 21 20 16 15 0 REGIMM rs TLTIU immediate 000001 01011 6 5 5 16 Format TLTIU rs immediate Description The 16 bit immediate is sign extended and compared to the contents of general register rs Considering both quantities as signed integers if the contents of general register rs are less than the sign extended immediate a trap exception occurs Operation 32 T if 0 GPR rs lt 0 immediate 5 immediate o then TrapException endif 64 T if 0 GPR rs lt 0 immediate 5 9 immediate s o then TrapException endif Exceptions Trap exception MIPS R4000 Microprocessor User s Manual A 175 Appendix A TLTU Trap If Less Than Unsigned TLTU 31 26 25 21 20 16 15 6 5 0 SPECIAL rs rt code TLTU 000000 110011 6 5 5 10 6 Format TLTU rs rt Description The contents of general register rf are compared to general register rs Considering both quantities as unsigned
105. ion FGR refers to the 32 General Purpose registers FGRO through FGR31 of the FPU and FPR refers to the floating point registers of the FPU e When the FR bit in the Status register SR 26 equals zero only the even floating point registers are valid and the 32 General Purpose registers of the FPU are 32 bits wide e When the FR bit in the Status register SR 26 equals one both odd and even floating point registers may be used and the 32 General Purpose registers of the FPU are 64 bits wide The following routines are used in the description of the floating point operations to retrieve the value of an FPR or to change the value of an FGR value lt ValueFPR fpr fmt if SRog 1 then 64 bit wide FGRs case fmt of S W value lt FGR fpr a o return D L value lt FGR fpr return endcase elseif fpro 0 then valid specifier 32 bit wide FGRs case fmt of S W value lt FGR fpr return D L value lt FGR fpr 1 FGR fpr return endcase else undefined result for odd 32 bit reg s value lt undefined endif MIPS R4000 Microprocessor User s Manual B 11 Appendix B StoreFPR fpr fmt value if SRog 1 then 64 bit wide FGRs case fmt of S W FGR fpr lt undefined value return D L FGR fpr lt value return endcase elseif foro O then valid specifier 32 bit wide FGRs case fmt of S W FGR fpr 1 lt undefined FGR fpr
106. ion Set Details FLOOR W fmt 5s FLOOR W fmt Fixed Point Format continued Operation T StoreFPR fd W ConvertFmt ValueFPR fs fmt fmt W Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception MIPS R4000 Microprocessor User s Manual B 37 Appendix B LDC1 Load Doubleword to FPU Coprocessor 1 LDC1 31 26 25 21 20 16 15 0 LDC 1101 1 0 1 base ft offset 6 5 5 16 Format LDC1 ft offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form an unsigned effective address In 32 bit mode the contents of the doubleword at the memory location specified by the effective address is loaded into registers ft and ft 1 of the floating point coprocessor This instruction is not valid and is undefined when the least significant bit of ft is non zero In 64 bit mode the contents of the doubleword at the memory location specified by the effective address are loaded into the 64 bit register ft of the floating point coprocessor The FR bit of the Status register SR specifies whether all 32 registers of the R4000 are addressable If FR equals zero this instruction is not defined when the least significant bit of ft is non zero If FR equals one ft may specify eith
107. ion exception MIPS R4000 Microprocessor User s Manual Appendix B ADD fmt X Floating Point Add ADD fmt 31 26 25 21 20 16 15 11 10 6 5 0 COP1 fmt ft fs fd ADD 010001 000000 6 5 5 5 5 6 Format ADD fmt fd fs ft Description The contents of the FPU registers specified by fs and ft are interpreted in the specified format and arithmetically added The result is rounded as if calculated to infinite precision and then rounded to the specified format fmt according to the current rounding mode The result is placed in the floating point register FPR specified by fd This instruction is valid only for single and double precision floating point formats The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of adjacent coprocessor general registers When the FR bit in the Status register equals one both even and odd register numbers are valid Operation T StoreFPR fd fmt ValueFPR fs fmt ValueFPR ft fmt Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Unimplemented operation exception Invalid operation exception Inexact exception Overflow exception Underflow exception B 14 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details BCiF WEN BC1F 31 26 25 2120 1615 0 COP1 BC
108. ise result in reading stale data For processors which only execute loads and stores in order with respect to shared memory this instruction is a NOP LL and SC instructions implicitly perform a SYNC This instruction is allowed in User mode Operation 32 64 T SyncOperation Exceptions None MIPS R4000 Microprocessor User s Manual A 161 Appendix A SYSCALL Systemcat SYSCALL 26 25 SPECIAL SYSCALL 000000 00 1 100 6 6 Format SYSCALL Description A system call exception occurs immediately and unconditionally transferring control to the exception handler The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction Operation 32 64 T SystemCallException Exceptions System Call exception A 162 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details TEQ Trap If Equal TEQ 26 25 SPECIAL TEQ 000000 110100 6 6 Format TEQ rs rt Description The contents of general register rt are compared to general register rs If the contents of general register rs are equal to the contents of general register rt a trap exception occurs The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction Ope
109. l address set the cache state to Dirty Exclusive If the cache block contains the specified address mark the cache block invalid If the cache block contains the specified address mark the cache block invalid and also invalidate all matching blocks if present in the primary caches the Plax field of the secondary tag is used to determine the locations in the primaries to search The CH bit in the Status register is Set or cleared to indicate a hit or miss If the cache block contains the specified address write the data back if it is dirty and mark the cache block invalid When a secondary cache is present and the CE bit of the Status register is set the contents of the ECC register is XOR d into the computed check bits during the write to the secondary cache for the addressed doubleword MIPS R4000 Microprocessor User s Manual A 45 Appendix A CACHE Cach continued CACH E Code Caches Name Operation SD Hit Writeback Invalidate If the cache block contains the specified address write back the data if dirty and mark the secondary cache block and all matching blocks in both primary caches invalid As usual with secondary writebacks modified data in the primary data cache matching block with the W bit set is used during the writeback The Pldx field of the secondary tag is used to determine the locations in the primaries to check for matching primary blocks The CH bit in the Status register is s
110. l InvalidOperationException endif else less ValueFPR fs fmt lt ValueFPR ft fmt equal ValueFPR fs fmt ValueFPR ft fmt unordered lt false endif condition conde and less or cond and equal or condo and unordered FCR 31 o3 lt condition COC 1 condition Exceptions Coprocessor unusable Floating Point exception Coprocessor Exceptions Unimplemented operation exception Invalid operation exception B 20 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details CEIL L fmt ceiingt tong CEIL L fmt Fixed Point Format 26 25 21 20 16 15 11 10 COP1 0 CEIL L 010001 00000 001010 6 5 6 Format CEIL L fmt fd fs Description The contents of the floating point register specified by fs are interpreted in the specified source format fmt and arithmetically converted to the long fixed point format The result is placed in the floating point register specified by fd Regardless of the setting of the current rounding mode the conversion is rounded as if the current rounding mode is round to o 2 This instruction is valid only for conversion from single or double precision floating point formats When the FR bit in the Status register equals one both even and odd register numbers are valid When the source operand is an Infinity NaN or the correctly rounded integer result is outside of 263 to 26 _ 1 the Invalid operation exception is
111. lation vAddr DATA pAddr lt pAddrpsizg 35 pAddra 9 xor ReverseEndian 0 byte vAddrs o xor BigEndianCPU 0 data COPzSW byte rt StoreMemory uncached WORD data pAddr vAddr DATA See the table Opcode Bit Encoding on next page or CPU Instruction Opcode Bit Encoding at the end of Appendix A MIPS R4000 Microprocessor User s Manual A 153 Appendix A SWCz A 154 Exceptions Store Word From Coprocessor Continued TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception Coprocessor unusable exception SWCz Opcode Bit Encoding SWCz Bit 31 30 29 28 27 2 0 SWC1 1 1 1 0 0 1 Bit 31 30 29 28 27 26 0 E 1 1 1 0 1 0 Nes A J v v SW opcode Coprocessor Unit Number MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details Store Word Left SWL 0 21 20 16 15 offset 16 Format SWL rt offset base Description address 4 address 0 address 4 address 0 This instruction can be used with the SWR instruction to store the contents of a register into four consecutive bytes of memory when the bytes cross a word boundary SWL stores the left portion of the register into the appropriate part of the high order word of memory SWR stores the right portion of the register into the appropriate part of the low order word The SWL
112. lay slot may not itself be occupied by a jump or branch instruction however this error is not detected and the results of such an operation are undefined If an exception or interrupt prevents the completion of a legal instruction during a delay slot the hardware sets the EPC register to point at the jump or branch instruction that precedes it When the code is restarted both the jump or branch instructions and the instruction in the delay slot are reexecuted Because jump and branch instructions may be restarted after exceptions or interrupts they must be restartable Therefore when a jump or branch instruction stores a return link value register 31 the register in which the link is stored may not be used as a source register Since instructions must be word aligned a Jump Register or Jump and Link Register instruction must use a register whose two low order bits are zero If these low order bits are not zero an address exception will occur when the jump target instruction is subsequently fetched MIPS R4000 Microprocessor User s Manual A 9 Appendix A A 6 Coprocessor Instructions Coprocessors are alternate execution units which have register files separate from the CPU The MIPS architecture provides four coprocessor units or classes and these coprocessors have two register spaces each space containing thirty two 32 bit registers The first space coprocessor general registers may be directly loaded from memory and st
113. load instructions store instructions and TLB operations immediately prior to and after this instruction are undefined Operation 32 64 T data GPR rt T 1 CPR O rd data Exceptions Coprocessor unusable exception A 114 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details MTCz Move To Coprocessor MTCz 0 0 000 0000 0000 11 Format MTCz rt rd Description The contents of general register rt are loaded into coprocessor register rd of coprocessor z Operation 32 T data lt GPR rt T 1 CPR z rd data 64 T data GPRIrt 31_ o T 1 if rdg 2 O CPR z rd4 0 CPRI z rd4 1 I O e3 32 data else CPR z rd4 0 data CPR z rd4 1 0 31 0 endif Exceptions Coprocessor unusable exception Opcode Bit Encoding MTCz 8153 30 29 28 27 26 25 24 23 2221 0 copo 09 1 0 0 0 0 B 5 5f oar 20 Bit 31 30 29 28 27 26 25 24 23 22 21 0 e EB E MEC E EN ERR Ie SOs se Bit 31 30 29 28 27 26 25 24 23 22 21 0 cope 0 1 0 0 1 0 Gell 0 ae 708 20 KE mS N E a Y 0 Opcode Coprocessor Unit Number Coprocessor Suboperation MIPS R4000 Microprocessor User s Manual A 115 Appendix A MTHI Move To HI MTHI 31 26 25 21 20 65 0 SPECIAL rs 0 MTHI 000000 000000000000000 010001 6 5 15 6 Format MTHI
114. lt 032 8 byte FGRift o8 byte endif StoreMemory uncached WORD data pAddr vAddr DATA Exceptions Coprocessor unusable TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception B 56 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details TRUNC L fmt 55 5 TRUNC L fmt Truncate to Long Fixed Point Format 26 25 21 20 16 15 11 10 COP1 0 TRUNC L 010001 00000 001001 6 5 6 Format TRUNC L fmt fd fs Description The contents of the floating point register specified by fs are interpreted in the specified source format fmt and arithmetically converted to the long fixed point format The result is placed in the floating point register specified by fd Regardless of the setting of the current rounding mode the conversion is rounded as if the current rounding mode is round toward zero 1 This instruction is valid only for conversion from single or double precision floating point formats When the source operand is an Infinity NaN or the correctly rounded integer result is outside of 263 to 263 1 the Invalid operation exception is raised If the Invalid operation is not enabled then no exception is taken and 2991 is returned MIPS R4000 Microprocessor User s Manual B 57 Appendix B TRUNC L fmt 2 m TRUNC L fmt Truncate to Long Fixed Point Format continued Operation StoreFPR fd L C
115. m the contents of general register rs to form a result The result is placed into general register rd The only difference between this instruction and the DSUB instruction is that DSUBU never traps on overflow No integer overflow exception occurs under any circumstances This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T GPR rd GPRirs GPRI rt Exceptions Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual A 75 Appendix A E R ET Exception Return E R ET COPO CO 0 ERET 010000 1 0000000 0000 0000 0000 011000 6 1 19 6 Format ERET Description ERET is the R4000 instruction for returning from an interrupt exception or error trap Unlike a branch or jump instruction ERET does not execute the next instruction ERET must not itself be placed in a branch delay slot If the processor is servicing an error trap SR 1 then load the PC from the ErrorEPC and clear the ERL bit of the Status register SR Otherwise SR 0 load the PC from the EPC and clear the EXL bit of the Status register SR An ERET executed between a LL and SC also causes the SC to fail Operation 32 64 T if SR 2 1 then PC ErrorEPC SR SRs 3 I 0 SR o else PC e EPC SR SB 0 SRo endif LLbit
116. mediate 018 Sixteen zero bits are concatenated with an immediate value typically 16 bits and the 32 bit string with the lower 16 bits set to zero is assigned to General Purpose Register rt Example 2 immediate 6 immediate 5 o Bit 15 the sign bit of an immediate value is extended for 16 bit positions and the result is concatenated with bits 15 through 0 of the immediate value to form a 32 bit sign extended value MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details B 3 Load and Store Instructions In the R4000 implementation the instruction immediately following a load may use the contents of the register being loaded In such cases the hardware interlocks requiring additional real cycles so scheduling load delay slots is still desirable although not required for functional code The behavior of the load store instructions is dependent on the width of the FGRs When the FR bit in the Status register equals zero the Floating Point General registers FGRs are 32 bits wide When the FR bit in the Status register equals one the Floating Point General registers FGRs are 64 bits wide In the load and store operation descriptions the functions listed in Table B 3 are used to summarize the handling of virtual addresses and physical memory Function Table B 3 Load and Store Common Functions Meaning AddressTranslation Uses the TLB to find the physical address given th
117. n R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual A 65 Appendix A DSLLV P avaswu DSLLV 26 25 21 20 16 15 11 10 SPECIAL 0 DSLLV 000000 00000 010100 6 5 6 Format DSLLV rd rt rs Description The contents of general register rt are shifted left by the number of bits specified by the low order six bits contained in general register rs inserting zeros into the low order bits The result is placed in register rd This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation qa s GPR rs s o GPR rd GPR rt 63 s 0 03 Exceptions Reserved instruction exception R4000 in 32 bit mode A 66 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details DSLL32 5 DSLLS32 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 0 rt rd sa DSLL32 000000 00000 111100 6 5 5 5 5 6 Format DSLL32 rd rt sa Description The contents of general register rt are shifted left by 32 sa bits inserting zeros into the low order bits The result is placed in register rd This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T S 1 sa GPR rd GPR rt 63 s 0 0 Exceptions Reserved instru
118. n TrapException endif 64 T if 0 GPR rs gt 0 immediate 4 4 immediate 5 o then TrapException endif Exceptions Trap exception MIPS R4000 Microprocessor User s Manual A 167 Appendix A TG E U Trap If Greater Than Or Equal Unsigned TG E U 26 25 21 20 16 15 SPECIAL 000000 6 Format TGEU rs rt Description The contents of general register rt are compared to the contents of general register rs Considering both quantities as unsigned integers if the contents of general register rs are greater than or equal to the contents of general register rt a trap exception occurs The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction Operation T if 0 GPR rs 2 0 GPR rt then TrapException endif Exceptions Trap exception A 168 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details TLBP ProberLB For Matching Entry TLBP 26 25 24 65 CO 0 TLBP 1 0000000000000000000 001000 1 19 6 Format TLBP Description The Index register is loaded with the address of the TLB entry whose contents match the contents of the EntryHi register If no TLB entry matches the high order bit of the Index register is set The architecture does not specify the operation of memory references associated wi
119. n C cond fmt and BCIFL Operation 32 T 1 condition not COC 1 T target lt offset 4 offset 0 T 1 if condition then PC PC target else NullifyCurrentInstruction endif 64 T 1 condition not COC 1 T target offset 9 offset 07 T 1 if condition then PC PC target else NullifyCurrentInstruction endif Exceptions Coprocessor unusable exception B 16 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details Branch On FPU True BC1 T Coprocessor 1 BC1 T 31 26 25 2120 1615 0 COP1 BC BCT offset 010001 01000 00001 6 5 5 16 Format BCIT offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended If the result of the last floating point compare is true one the program branches to the target address with a delay of one instruction There must be at least one instruction between C cond fmt and BCIT Operation 32 T 1 condition COC 1 T target lt offset offset 0 T 1 if condition then PC PC target endif 64 T 1 condition COC 1 T target lt offset 5 9 offset 0 T 1 ifcondition then PC PC target endif Exceptions Coprocessor unusable exception MIPS R4000 Microprocessor User s Manual B 17 Appendix B B h FPU True Likel BC1 TL a S
120. n operations Each of the statements within a time step are defined to be executed in sequential order as modified by con ditional and loop constructs Operations which are marked T i are executed at instruction cycle relative to the start of execution of the instruction Thus an instruction which starts at time j executes operations marked T at time i j The interpretation of the order of execution between two instructions or two operations which execute at the same time should be pessimistic the or der is not defined MIPS R4000 Microprocessor User s Manual A 5 Appendix A Instruction Notation Examples The following examples illustrate the application of some of the instruction notation conventions Example 1 GPR t lt immediate 0 6 Sixteen zero bits are concatenated with an immediate value typically 16 bits and the 32 bit string with the lower 16 bits set to zero is assigned to General Purpose Register rt Example 2 immediate 5 6 immediate 5 o Bit 15 the sign bit of an immediate value is extended for 16 bit positions and the result is concatenated with bits 15 through 0 of the immediate value to form a 32 bit sign extended value A 6 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details A 4 Load and Store Instructions In the R4000 implementation the instruction immediately following a load may use the loaded contents of the register In such cases the
121. n the branch delay slot is nullified Operation 32 T target lt offset s offset 0 condition GPR rs a 1 or GPR rs 09 T 1 if condition then PC lt PC target NullifyCurrentInstruction endif 64 T target lt offset 5 9 offset 07 condition GPR rs g3 1 or GPR rs 094 T 1 if condition then PC lt PC target else NullifyCurrentInstruction endif Exceptions None A 34 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details BLTZ Branch On Less Than Zero BLTZ 26 25 21 20 16 15 REGIMM BLTZ offset 000001 00000 6 5 16 Format BLTZ rs offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended If the contents of general register rs have the sign bit set then the program branches to the target address with a delay of one instruction Operation 32 T target c offset s offset 0 condition GPR rs a 1 T 1 if condition then PC PC target endif 64 T target lt offset 5 46 offset 0 condition GPR rs es 1 T 1 if condition then PC c PC target endif Exceptions None MIPS R4000 Microprocessor User s Manual A 35 Appendix A BLTZAL nzeoAndtm BLTZAL 26 25 21 20 16 15 REGIMM BLTZAL 000001 10000 6 5 Format BLTZAL rs offs
122. nd loaded into general register rt If the least significant bit of the effective address is non zero an address error exception occurs Operation 32 T vAddr lt offsets offsetys o GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpgize 1 3 PAddre 9 xor ReverseEndian 0 mem lt LoadMemory uncached HALFWORD pAddr vAddr DATA byte vAddr o xor BigEndianCPU 0 GPR rt Mem1548 byte MeM15 8 byte 8 byte 64 T vAddr lt offset s offset s 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrps ze 1 3 pAddra o xor ReverseEndian 0 mem lt LoadMemory uncached HALFWORD pAddr vAddr DATA byte lt vAddrs_ xor BigEndianCPU 0 48 GPR rt mem 5 8 pyte mem15 8 byte 8 byte Exceptions TLB refill exception TLB invalid exception Bus error exception Address error exception A 92 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details LHU Load Halfword Unsigned L HU 31 26 25 21 20 16 15 0 LHU base rt offset 100101 6 5 5 16 Format LHU rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address The contents of the halfword at the memory location specified by the effective address are zero extended and loaded into general register rt If the least s
123. nding mode the conversion is rounded as if the current rounding mode is round to nearest even 0 This instruction is valid only for conversion from single or double precision floating point formats When the source operand is an Infinity NaN or the correctly rounded integer result is outside of 263 to 295 1 the Invalid operation exception is raised If the Invalid operation is not enabled then no exception is taken and 299 1 is returned MIPS R4000 Microprocessor User s Manual B 47 Appendix B ROUND L fmt 455599 ROUND L fmt Round to Long Fixed Point Format continued Operation StoreFPR fd L ConvertFmt ValueFPR fs fmt fmt L Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception B 48 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details ROUND W fmt Floating Point ROUND W fmt Round to Single Fixed Point Format 31 26 25 21 20 16 15 11 10 6 5 0 COP1 fmt 0 fs fd ROUND W 010001 00000 001100 6 5 5 5 5 6 Format ROUND W fmt fd fs Description The contents of the floating point register specified by fs are interpreted in the specified source format fmt and arithmetically converted to the single fixed point format The result is placed in the floating point register specified by fd Regardless of the
124. nditions specified in the cond field If one of the values is a Not a Number NaN and the high order bit of the corid field is set an invalid operation exception is taken After a one instruction delay the condition is available for testing with branch on floating point coprocessor condition instructions There must be at least one instruction between the compare and the branch Comparisons are exact and can neither overflow nor underflow Four mutually exclusive relations are possible results less than equal greater than and unordered The last case arises when one or both of the operands are NaN every NaN compares unordered with everything including itself Comparisons ignore the sign of zero so 0 0 This instruction is valid only for single and double precision floating point formats The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of adjacent coprocessor general registers When the FR bit in the Status register equals one both even and odd register numbers are valid See FPU Instruction Opcode Bit Encoding at the end of Appendix B MIPS R4000 Microprocessor User s Manual B 19 Appendix B Floating Point C cond fmt Compare C cond fmt continued Operation T if NaN ValueFPR fs fmt or NaN ValueFPR ft fmt then less false equal false unordered lt true if cond then signa
125. ocessor User s Manual 4 27 Appendix A BGEZAL Branch On Greater Than Or Equal To Zero And Link BGEZAL 31 26 25 21 20 16 15 0 REGIMM rs BGEZAL offset 000001 10001 6 5 5 16 Format BGEZAL rs offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended Unconditionally the address of the instruction after the delay slot is placed in the link register r31 If the contents of general register rs have the sign bit cleared then the program branches to the target address with a delay of one instruction General register rs may not be general register 31 because such an instruction is not restartable An attempt to execute this instruction is not trapped however Operation 32 T 64 T T 1 T 1 target lt offset s 4 offset 0 condition GPR rs 3 0 GPR 31 PC 8 if condition then PC PC target endif target lt offset 5 9 offset 0 condition GPR rs es 0 GPR 31 PC 8 if condition then PC PC target endif Exceptions None MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details BGEZALL gignere BGEZALL And Link Likely 31 26 25 21 20 16 15 0 REGIMM rs BGEZALL offset 000001 10011 6 5 5 16 Format BGEZALL rs offset Description A branch
126. of the register then it loads bytes from memory into the register until it reaches the high order byte of the doubleword in memory The most significant left most byte s of the register will not be changed memory big endian address 8 8 9 10 11 12 13 14 15 address 0 0 1 2 3 4 5 6 7 LDR 24 4 0 register before A B C D E F G H 24 register after A BICIOI1 2 3 4 24 MIPS R4000 Microprocessor User s Manual A 89 Appendix A LDR Load Doubleword Right LD R continued The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LDR or LDL instruction which also specifies register rt No address exceptions due to alignment are possible This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T vAddr offset 5 4 9 offsety5 o GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrps ze 1 3 PAddro 9 xor ReverseEndian if BigEndianMem 1 then pAddr pAddra 4 0 endif byte vAddra xor BigEndianCPU mem LoadMemory uncached byte pAddr vAddr DATA GPR rt GPRIrt 3 64 8 byte memes apyte A 90 M
127. on Set Details Store Word from FPU SWC1 Coprocessor 1 SWC1 21 20 16 15 offset 16 Format SWCI ft offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form an unsigned effective address The contents of register ft from the floating point coprocessor are stored at the memory location specified by the effective address The FR bit of the Status register specifies whether all 64 bit floating point registers are addressable If FR equals zero SWC1 stores either the high or low half of the 16 even floating point registers If FR equals one SWC1 stores the low 32 bits of both even and odd floating point registers If either of the two least significant bits of the effective address are non zero an address error exception occurs MIPS R4000 Microprocessor User s Manual B 55 Appendix B SWC1 uen SWC1 continued Operation 32 T vAddr lt offset s offset s 9 GPR base 64 T vAddr lt offset5 9 offset s__09 GPR base 32 64 pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpsizg 4 pAddra o xor ReverseEndian 02 byte vAddra xor BigEndianCPU 0 the bytes of the word are put in the correct byte lanes in data for a 64 bit path to memory if SRog 1 then 64 bit wide FGRs data FGR ftles s byte o 09 5Y e else 32 bit wide FGRs data
128. ond writeback is redundant but not incorrect The CH bit in the Status register is set or cleared to indicate a hit or miss The writeback looks in the primary data cache for modified data but does not invalidate or clear the Writeback bit in the primary data cache Note The state of the secondary block is not changed to clean during this operation because the W bit of matching sub blocks cannot be cleared to put the primary block in a clean state A 46 Hit Writeback If the cache block contains the specified address data is written back unconditionally When a secondary cache is present and the CE bit of the Status register is set the contents of the ECC register is XOR d into the computed check bits during the write to the secondary cache for the addressed doubleword MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details CACHE continued CACHE Code Caches Name Operation This operation is used to change the virtual index of secondary cache contents avoiding unnecessary memory operations If the cache block contains the specified address invalidate matching blocks in the primary caches at the index formed by concatenating Plax in the secondary cache tag not the virtual address of the operation and vAddr 4 and then set the virtual index field of the secondary cache tag from the specified virtual address Modified data in the primary data cache is not preserved by the operation and sh
129. ontents of general register rs to form a result The result is placed into general register rd In 64 bit mode the operands must be valid sign extended 32 bit values The only difference between this instruction and the SUB instruction is that SUBU never traps on overflow No integer overflow exception occurs under any circumstances Operation 32 T GPR rd e GPR rs GPR rt 64 T temp lt GPR rs GPR rt GPR rd tempa1 temps o Exceptions None MIPS R4000 Microprocessor User s Manual A 151 Appendix A SW Store Word SW 31 26 25 21 20 16 15 0 SW base rt offset 101011 6 5 5 16 Format SW rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address The contents of general register rt are stored at the memory location specified by the effective address If either of the two least significant bits of the effective address are non Zero an address error exception occurs Operation 32 T vAddr lt offset s offset 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpgjze 1 3 0Addr2 9 xor ReverseEndian 0 byte vAddr gt o xor BigEndianCPU 0 data GPR rt gs spy 08 e StoreMemory uncached WORD data pAddr vAddr DATA 64 T vAddr offset 5 8 offsety5 9 GPR base pAddr uncached AddressTranslation v
130. onvertFmt ValueFPR fs fmt fmt L Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception B 58 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details TRUNC W fmt o nas I RUNC W fmt Truncate to Single Fixed Point Format 31 26 25 21 20 16 15 11 10 6 5 0 COP1 fmt 0 fs fd TRUNC W 010001 00000 001101 6 5 5 5 5 6 Format TRUNC W fmt fd fs Description The contents of the FPU register specified by fs are interpreted in the specified source format fmt and arithmetically converted to the single fixed point format The result is placed in the FPU register specified by fd Regardless of the setting of the current rounding mode the conversion is rounded as if the current rounding mode is round toward zero RM 1 This instruction is valid only for conversion from a single or double precision floating point formats The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of adjacent coprocessor general registers When the FR bit in the Status register equals one both even and odd register numbers are valid When the source operand is an Infinity or NaN or the correctly rounded integer result is outside of 2 to 231 1
131. oprocessor 0 register is undefined Operation 64 T data CPR O0 rd T 1 GPR rt data Exceptions Coprocessor unusable exception Reserved instruction exception R4000 in 32 bit user mode R4000 in 32 bit supervisor mode MIPS R4000 Microprocessor User s Manual A 61 Appendix A Doubl dM T DMTCO System Control Gopracessdi DMTCO 31 26 25 21 20 16 15 11 10 0 COPO DMT rt rd 0 010000 00101 000 0000 0000 6 5 5 5 11 Format DMTCO rt rd Description The contents of general register rt are loaded into coprocessor register rd of the CPO This operation is defined for the R4000 operating in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception All 64 bits of the coprocessor 0 register are written from the general register source The operation of DMTCO on a 32 bit coprocessor 0 register is undefined Because the state of the virtual address translation system may be altered by this instruction the operation of load instructions store instructions and TLB operations immediately prior to and after this instruction are undefined Operation 64 T data GPR rt T 1 CPR O rd data Exceptions Coprocessor unusable exception R4000 in 32 bit user mode R4000 in 32 bit supervisor mode A 62 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details DMULT D
132. or Exceptions Unimplemented operation exception Invalid operation exception Inexact exception MIPS R4000 Microprocessor User s Manual B 53 Appendix B SUB fmt Floating Point Subtract SUB fmt 26 25 21 20 16 15 11 10 Format SUB fmt fd fs ft Description The contents of the floating point registers specified by fs and ft are interpreted in the specified format and the value in the ft field is subtracted from the value in the fs field The result is rounded as if calculated to infinite precision and then rounded to the specified format according to the current rounding mode The result is placed in the floating point register specified by fd This instruction is valid only for single or double precision floating point formats The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of adjacent coprocessor general registers When the FR bit in the Status register equals one both even and odd register numbers are valid Operation T StoreFPR fd fmt ValueFPR fs fmt ValueFPR ft fmt Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Unimplemented operation exception Invalid operation exception Inexact exception Overflow exception Underflow exception B 54 MIPS R4000 Microprocessor User s Manual FPU Instructi
133. or MFLO the results of those instructions are undefined Correct operation requires separating reads of HI or LO from writes by two or more instructions MIPS R4000 Microprocessor User s Manual 4 57 Appendix A Divid DIV NL DIV Operation 32 T 2 LO lt undefined HI lt undefined T 1 LO lt undefined HI lt undefined T LO lt GPR rs div GPR rt HI lt GPR rs mod GPR rt 64 T 2 LO lt undefined HI lt undefined T 1 LO lt undefined HI lt undefined T q c GPR rs 31 o div GPRfrt 31 0 r lt GPR rs 34 9 mod GPRIrt 3 _ 9 LO 031 q31 HI r3 r3 9 Exceptions None A 58 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details Divide Unsigned DIVU 31 26 25 21 20 16 15 6 5 0 SPECIAL fe rt 0 DIVU 000000 000000 0000 011011 6 5 5 10 6 Format DIVU rs rt Description The contents of general register rs are divided by the contents of general register rt treating both operands as unsigned values No integer overflow exception occurs under any circumstances and the result of this operation is undefined when the divisor is zero In 64 bit mode the operands must be valid sign extended 32 bit values This instruction is typically followed by additional instructions to check for a zero divisor When the operation completes the quotient word of the double result is loaded into special register LO and the remainder word of the dou
134. or MFLO the results of those instructions are undefined Correct operation requires separating reads of HI or LO from writes by two or more instructions This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T 2 LO lt undefined HI lt undefined T 1 LO lt undefined HI lt undefined T LO lt GPR rs div GPR rt HI lt GPR rs mod GPR rt Exceptions Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual A 55 Appendix A DDIVU Doubleword Divide Unsigned DDIVU 31 26 25 21 20 16 15 6 5 0 SPECIAL rs rt 0 DDIVU 000000 000000 0000 011111 6 5 5 10 6 Format DDIVU rs rt Description The contents of general register rs are divided by the contents of general register rt treating both operands as unsigned values No integer overflow exception occurs under any circumstances and the result of this operation is undefined when the divisor is zero This instruction is typically followed by additional instructions to check for a zero divisor When the operation completes the quotient word of the double result is loaded into special register LO and the remainder word of the double result is loaded into special register HI If either of the two preceding instructions is MFHI or MFLO the results of those instructions are unde
135. or even registers Operation 64 T if SRog 1 then 64 bit wide FGRs data FGR fs elseif fsy 0 then valid specifier 32 bit wide FGRs data FGR fs 1 FGR fs else undefined for odd 32 bit reg s data undefined endif T 1 GPR rt data Exceptions Coprocessor unusable exception Coprocessor Exceptions Unimplemented operation exception B 32 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details Doubleword Move To DMTC1 Floating Point Coprocessor DMTC1 26 25 21 20 16 15 COP1 DMT 0 010001 00101 000 00000000 6 5 11 Format DMTCI rt fs Description The contents of general register rt are loaded into coprocessor register fs of the CP1 The contents of floating point register fs are undefined for the instruction immediately following DMTC1 The FR bit in the Status register specifies whether all 32 registers of the R4000 are addressable When FR equals zero this instruction is not defined when the least significant bit of fs is non zero When FR equals one fs may specify either odd or even registers Operation 64 T data GPR rt T 1 if SRog 1 then 64 bit wide FGRs FGR fs data elseif fsy 0 then valid specifier 32 bit wide valid FGRs FGR fs 1 datags 30 FGR fs data31 0 else undefined result for odd 32 bit reg s undefined_result endif Exceptions Coprocess
136. or unusable exception Coprocessor Exceptions Unimplemented operation exception MIPS R4000 Microprocessor User s Manual B 33 Appendix B FLOOR L fmt Fioortotong FLOOR L fmt Fixed Point Format 26 25 21 20 16 15 11 10 COP1 0 FLOOR L 010001 00000 001011 6 5 6 Format FLOOR L fmt fd fs Description The contents of the floating point register specified by fs are interpreted in the specified source format fmt and arithmetically converted to the long fixed point format The result is placed in the floating point register specified by fd Regardless of the setting of the current rounding mode the conversion is rounded as if the current rounding mode is round to v 3 This instruction is valid only for conversion from single or double precision floating point formats When the source operand is an Infinity NaN or the correctly rounded integer result is outside of 263 to 295 1 the Invalid Operation exception is raised If the Invalid operation is not enabled then no exception is taken and 2991 is returned B 34 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details FLOOR L fmt Floating Point FLOOR L fmt Floor to Long Fixed Point Format continued Operation StoreFPR fd L ConvertFmt ValueFPR fs fmt fmt L Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Invalid operation exception Unimplemented operation
137. ord of the double result is loaded into special register HI If either of the two preceding instructions is MFHI or MFLO the results of these instructions are undefined Correct operation requires separating reads of HI or LO from writes by a minimum of two instructions A 120 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details MULTU mv MULTU Operation lt undefined lt undefined lt undefined lt undefined lt 0 GPR rs 0 GPR rt lt 131 0 lt 163 32 lt undefined lt undefined lt undefined lt undefined lt 0 GPR rs 31 0 0 GPR rt 31 o tg1 ta4 0 tgg II tes 32 Exceptions None MIPS R4000 Microprocessor User s Manual A 121 Appendix A NOR Nor NOR 100111 26 25 21 20 16 15 11 10 SPECIAL 0 000000 00000 6 5 Format NOR rd rs rt Description 6 The contents of general register rs are combined with the contents of general register rt in a bit wise logical NOR operation The result is placed into general register rd Operation 32 64 T GPhR rd GPR rs nor GPR rt Exceptions None A 122 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details OR or OR 26 25 21 20 16 15 11 10 SPECIAL 0 OR 000000 00000 100101 6 5 6 Format OR rd rs rt Description The contents of general register rs are combined with
138. ored into memory and their contents may be transferred between the coprocessor and processor e The second space coprocessor control registers may only have their contents transferred directly between the coprocessor and the processor Coprocessor instructions may alter registers in either space A 7 System Control Coprocessor CPO Instructions There are some special limitations imposed on operations involving CPO that is incorporated within the CPU Although load and store instructions to transfer data to from coprocessors and to move control to from coprocessor instructions are generally permitted by the MIPS architecture CP0 is given a somewhat protected status since it has responsibility for exception handling and memory management Therefore the move to from coprocessor instructions are the only valid mechanism for writing to and reading from the CP0 registers Several CPO instructions are defined to directly read write and probe TLB entries and to modify the operating modes in preparation for returning to User mode or interrupt enabled states A 10 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details ADD Add ADD 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL is rt rd 0 ADD 000000 00000 100000 6 5 5 5 5 6 Format ADD rd rs rt Description The contents of general register rs and the contents of general register rt are added to form the result The result is plac
139. ory when the bytes cross a boundary between two doublewords SDR stores the right portion of the register into the appropriate part of the low order doubleword SDL stores the left portion of the register into the appropriate part of the low order doubleword of memory The SDR instruction adds its sign extended 16 bit offset to the contents of general register base to form a virtual address which may specify an arbitrary byte It alters only the word in memory which contains that byte From one to eight bytes will be stored depending on the starting byte specified Conceptually it starts at the least significant rightmost byte of the register and copies it to the specified byte in memory then it copies bytes from register to memory until it reaches the high order byte of the word in memory No address exceptions due to alignment are possible memory big endian address8 8 9 10 11 12 13 14 15 addressO gl1 2 3 4 5 6 7 register before A B C D E F G H 24 ORe SDR 24 4 S0 address 8 8 9 10 11 12 13 14 15 after addressS0 E F GIH 4 5 6 7 A 136 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details Store Doubleword Right SD R continued SD R This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction ex
140. oubleword Multiply DMULT 31 26 25 21 20 16 15 6 5 0 SPECIAL rs rt 0 DMULT 000000 0000000000 011100 6 5 5 10 6 Format DMULT rs rt Description The contents of general registers rs and rt are multiplied treating both operands as 2 s complement values No integer overflow exception occurs under any circumstances When the operation completes the low order word of the double result is loaded into special register LO and the high order word of the double result is loaded into special register HI If either of the two preceding instructions is MFHI or MFLO the results of these instructions are undefined Correct operation requires separating reads of HI or LO from writes by a minimum of two other instructions This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T 2 LO lt undefined HI lt undefined T 1 LO lt undefined HI lt undefined T t lt GPR rs GPR rt LO t63 0 HI lt t4127 64 Exceptions Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual A 63 Appendix A DMULTU DMULTU 31 26 25 21 20 16 15 6 5 0 SPECIAL rs rt 0 DMULTU 000000 0000000000 011101 6 5 5 10 6 Format DMULTU rs rt Description The contents of general register rs and the contents of gene
141. oubleword SCD 31 26 25 21 20 16 15 0 SCD base rt offset 111100 6 5 5 16 Format SCD rt offset base Description A 128 The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address The contents of general register rt are conditionally stored at the memory location specified by the effective address If any other processor or device has modified the physical address since the time of the previous Load Linked Doubleword instruction or if an ERET instruction occurs between the Load Linked Doubleword instruction and this store instruction the store fails and is inhibited from taking place The success or failure of the store operation as defined above is indicated by the contents of general register rt after execution of the instruction A successful store sets the contents of general register rt to 1 an unsuccessful store sets it to 0 The operation of Store Conditional Doubleword is undefined when the address is different from the address used in the last Load Linked Doubleword This instruction is available in User mode it is not necessary for CPO to be enabled If either of the three least significant bits of the effective address is non zero an address error exception takes place MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details Store Conditional Doubleword SCD continued SCD If this instruction should both fail and take an exception the
142. ould be explicitly written back before this operation The CH bit in the Status register is set or cleared to indicate a hit or miss 7 SI SD Hit Set Virtual Operation 32 64 T vAddr offset 5 8 offsety5 9 GPR base pAddr uncached AddressTranslation vAddr DATA CacheOp op vAddr pAddr Exceptions Coprocessor unusable exception MIPS R4000 Microprocessor User s Manual 4 47 Appendix A Move Control From CFCz Coprocessor CFCz 81 26 25 21 20 16 15 11 10 0 COPz GF rt rd 0 0100xx 00010 00000 6 5 5 5 11 Format CFCz rt rd Description The contents of coprocessor control register rd of coprocessor unit z are loaded into general register rt This instruction is not valid for CPO Operation 32 T data CCR z rd T 1 GPRirt data 64 T data CCR z rd 31 CCR z rd T 1 GPRirt data Exceptions Coprocessor unusable exception Opcode Bit Encoding CFCz Bit 31 30 29 28 27 26 25 24 23 22 21 0 cFc1 9 1 0 0 0 1 0 0 0 1 0 Bit 31 30 29 28 27 26 25 24 23 22 21 0 CFc2 9 1 010 1 0 0 00 1 0 Ne A DN EP vy Inu Opcode Coprocessor Suboperation Coprocessor Unit Number A 48 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details COPz Coprocessor Operation COPz 31 26 25 24 0 COPz CO cofun 0100xx
143. ounding occurs according to the currently specified rounding mode This instruction is valid only for conversions from double floating point format or from 32 bit or 64 bit fixed point format The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of adjacent coprocessor general registers When the FR bit in the Status register equals one both even and odd register numbers are valid Operation T StoreFPR fd S ConvertFmt ValueFPR fs fmt fmt S Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception Underflow exception MIPS R4000 Microprocessor User s Manual B 29 Appendix B CVT W fmt uenis CVT W fmt Fixed Point Format 31 26 25 21 20 16 15 11 10 6 5 0 COP1 010001 fmt 0 fs fd CVT W 00000 100100 6 5 5 5 5 6 Format CVT W fmt fd fs Description The contents of the floating point register specified by fs are interpreted in the specified source format fmt and arithmetically converted to the single fixed point format The result is placed in the floating point register specified by fd This instruction is valid only for conversion from a single or double precision floating point formats Th
144. ow order bits are not zero an address exception will occur when the jump target instruction is subsequently fetched Operation 32 64 T temp GPR rs T 1 PC temp Exceptions None A 80 MIPS R4000 Microprocessor User s Manual LB CPU Instruction Set Details Load Byte L B 31 26 25 21 20 16 15 0 LB base rt offset 100000 6 5 5 16 Format LB rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address The contents of the byte at the memory location specified by the effective address are sign extended and loaded into general register rt Operation 32 T 64 T vAddr lt offset s offsets 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpgize 1 3 pAddra o xor ReverseEndian mem lt LoadMemory uncached BYTE pAddr vAddr DATA byte vAddrs o xor BigEndianCPU GPR rt mem7 g pyte memz sbyte a byte vAddr lt offset s offsetys 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrps ze 1 3 PAddre o xor ReverseEndian mem lt LoadMemory uncached BYTE pAddr vAddr DATA byte vAddra 9 xor BigEndianCPU 56 GPR rt memz s pyig MEM7 g byte 8 byte Exceptions TLB refill exception TLB invalid exception Bus error exception Address error exception
145. pared If the two registers are equal the target address is branched to with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified Operation 32 T target lt offset s offset 0 condition GPR rs GPR rt T 1 if condition then PC c PC target NullifyCurrentInstruction else endif 64 T target lt offset 5 9 offset 0 condition GPR rs GPR rt T 1 if condition then PC amp PC target else NullifyCurrentInstruction endif Exceptions None A 26 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details Branch On Greater Than BG EZ Or Equal To Zero BG EZ 26 25 21 20 16 15 REGIMM offset 000001 6 16 Format BGEZ rs offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended If the contents of general register rs have the sign bit cleared then the program branches to the target address with a delay of one instruction Operation 32 T target lt offset z offset 07 condition GPR rs 3 0 T 1 if condition then PC PC target endif 64 T target lt offset z 46 offset 0 condition GPR rs as 0 T 1 if condition then PC amp PC target endif Exceptions None MIPS R4000 Micropr
146. plished by coprocessor load and store operations which reference the floating point coprocessor General Purpose registers These operations are unformatted no format conversions are performed and therefore no floating point exceptions can occur due to these operations Data may also be directly moved between the floating point coprocessor and the processor by move to coprocessor and move from coprocessor instructions Like the floating point load and store operations move to from operations perform no format conversions and never cause floating point exceptions An additional pair of coprocessor registers are available called Floating Point Control registers for which the only data movement operations supported are moves to and from processor General Purpose registers Floating Point Operations The floating point unit operation set includes e floating point add e floating point subtract e floating point multiply e floating point divide e floating point square root e convert between fixed point and floating point formats convert between floating point formats e floating point compare These operations satisfy the requirements of IEEE Standard 754 requirements for accuracy Specifically these operations obtain a result which is identical to an infinite precision result rounded to the specified format using the current rounding mode Instructions must specify the format of their operands Except for conversion functions mixed
147. r User s Manual LWR CPU Instruction Set Details Load Word Right continued LWR Given a word in a register and a word in memory the operation of LWR is as follows LWR Register A B C D E F G H Memory J K b SM LUN 119 RP BigEndianCPU 0 BigEndianCPU 1 vAddr o destination type offset destination type offset LEM BEM LEM BEM 0 SSSSMNOP 0 0 4 XXXXEFGI 0 7 0 1 XXXXEMNO 1 1 4 IXXXXEFI1 J 1 6 0 2 XXXXEFMN 2 2 4 IXXXXEIJK e2 5 0 3 XXXXEFGM 3 3 4 SSSSIJKL 3 4 0 4 SSSSI JKL 0 4 0 IXXXXEFGM 0 3 4 5 XXXXEI JK 1 5 0 XXXXEFMN 1 2 4 6 XXXXEFI J 2 6 0 XXXXEMNO 2 1 4 7 XXXXEFGI 3 7 O0 SSSSMNOP 3 0 4 LEM Little endian memory BigEndianMem 0 BEM BigEndianMem 1 Type AccessType see Table 2 1 sent to memory Offset pAddr o sent to memory S sign extend of destinations X either unchanged or sign extend of destinationg Exceptions TLB refill exception TLB invalid exception Bus error exception Address error exception MIPS R4000 Microprocessor User s Manual A 107 Appendix A LWU Load Word Unsigned LWU 31 26 25 21 20 16 15 0 LWU base rt offset 100111 6 5 5 16 Format LWU rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address The contents of the word at the memory location specified by the effective ad
148. raised If the Invalid operation is not enabled then no exception is taken and 29 1 is returned MIPS R4000 Microprocessor User s Manual B 21 Appendix B Floating Point CEIL L fmt Ceiling A Long CEIL L fmt Fixed Point Format continued Operation il StoreFPR fd L ConvertFmt ValueFPR fs fmt fmt L Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception B 22 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details CEIL W fmt ceing io single CEIL W fmt Fixed Point Format 26 25 21 20 16 15 11 10 COP1 0 CEIL W 010001 00000 001110 6 5 6 Format CEIL W fmt fd fs Description The contents of the floating point register specified by fs are interpreted in the specified source format fmt and arithmetically converted to the single fixed point format The result is placed in the floating point register specified by fd Regardless of the setting of the current rounding mode the conversion is rounded as if the current rounding mode is round to e 2 This instruction is valid only for conversion from a single or double precision floating point formats The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of
149. ral register rt are multiplied treating both operands as unsigned values No overflow exception occurs under any circumstances When the operation completes the low order word of the double result is loaded into special register LO and the high order word of the double result is loaded into special register HI If either of the two preceding instructions is MFHI or MFLO the results of these instructions are undefined Correct operation requires separating reads of HI or LO from writes by a minimum of two instructions This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation LO undefined HI undefined LO undefined HI undefined t 0 GPR rs 0 GPR rt LO 163 0 HI t127 64 Exceptions Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details DSLL __Doubleword Shift Left Logical DSLL 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL 0 rt rd sa DSLL 000000 00000 111000 6 5 5 5 5 6 Format DSLL rd rt sa Description The contents of general register rt are shifted left by sa bits inserting zeros into the low order bits The result is placed in register rd Operation 64 T s lt O l sa GPR rd lt GPR rt 63 s 0 03 Exceptions Reserved instruction exceptio
150. rating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T GPR rt GPR rs immediate s immediate s5 o Exceptions Integer overflow exception Reserved instruction exception R4000 in 32 bit mode A 52 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details DADDIU immediate Unsigned DADDIU 31 26 25 21 20 16 15 0 DADDIU rs rt immediate 011001 6 5 5 16 Format DADDIU rt rs immediate Description The 16 bit immediate is sign extended and added to the contents of general register rs to form the result The result is placed into general register rt No integer overflow exception occurs under any circumstances The only difference between this instruction and the DADDI instruction is that DADDIU never causes an overflow exception This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T GPR rt GPR rs immediate immediate s o Exceptions Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual A 53 Appendix A DADDU Poubteword Add Unsigned DADDU 26 25 21 20 16 15 11 10 SPECIAL 0 DADDU 000000 00000 101101 6 5 6 Format DADDU rd rs rt Description The contents of general
151. ration 32 64 T if GPR rs GPR rt then TrapException endif Exceptions Trap exception MIPS R4000 Microprocessor User s Manual A 163 Appendix A TEOI Trap If Equal Immediate TEQI 31 26 25 21 20 16 15 0 REGIMM rs TEQI immediate 000001 01100 6 5 5 16 Format TEQI rs immediate Description The 16 bit immediate is sign extended and compared to the contents of general register rs If the contents of general register rs are equal to the sign extended immediate a trap exception occurs Operation 32 T if GPR rs immediate 8 immediate y then TrapException endif 64 T if GPR rs immediate 9 immediate45 y then TrapException endif Exceptions Trap exception A 164 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details TG E Trap If Greater Than Or Equal TG E 31 26 25 21 20 16 15 6 5 0 SPECIAL rs rt code TGE 000000 110000 6 5 5 10 6 Format TGE rs rt Description The contents of general register rt are compared to the contents of general register rs Considering both quantities as signed integers if the contents of general register rs are greater than or equal to the contents of general register rt a trap exception occurs The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction
152. rd that has its ECC or parity modified This operation is performed unconditionally The Hit operation accesses the specified cache as normal data references and performs the specified operation if the cache block contains valid data with the specified physical address a hit If the cache block is invalid or contains a different address a miss no operation is performed 4 42 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details CAC H E iom di CAC H E Write back from a primary cache goes to the secondary cache if there is one otherwise to memory Write back from a secondary cache always goes to memory A secondary write back always writes the most recent data the data comes from the primary data cache if present and modified the W bit is set Otherwise the data comes from the specified secondary cache The address to be written is specified by the cache tag and not the translated physical address TLB Refill and TLB Invalid exceptions can occur on any operation For Index operations where the physical address is used to index the cache but need not match the cache tag unmapped addresses may be used to avoid TLB exceptions This operation never causes TLB Modified or Virtual Coherency exceptions Bits 17 16 of the instruction specify the cache as follows Code Name Cache 0 primary instruction 1 D primary data 2 SI secondary instruction 3 secondary data or combined instruction data
153. register rs If the contents of general register rs are not equal to the sign extended immediate a trap exception occurs Operation 32 T if GPR rs immediate 5 immediate o then TrapException endif 64 T if GPR rs immediate 4 immediate 5 o then TrapException endif Exceptions Trap exception A 178 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details XOR Exclusive Or XOR 31 26 25 21 20 16 15 11 10 6 5 0 SPECIAL rs rt rd 0 XOR 000000 00000 100110 6 5 5 5 5 6 Format XOR rd rs rt Description The contents of general register rs are combined with the contents of general register rt in a bit wise logical exclusive OR operation The result is placed into general register rd Operation 32 64 T GPR rd lt GPR rs xor GPR rt Exceptions None MIPS R4000 Microprocessor User s Manual 4 179 Appendix A XORI Exclusive OR Immediate XORI 26 25 21 20 16 15 XORI immediate 001110 6 16 Format XORI rt rs immediate Description The 16 bit immediate is zero extended and combined with the contents of general register rs in a bit wise logical exclusive OR operation The result is placed into general register rt Operation 32 T GPR rt GPR rs xor 016 immediate 64 T GPRirt GPR rs xor 048 immediate Exceptions None A 180 MIPS R4000 Microprocessor U
154. rs The TLB entry pointed at by the contents of the TLB Random register is loaded with the contents of the EntryHi and EntryLo registers Operation 32 64T TLB Randoms og lt PageMask EntryHi and not PageMask EntryLo1 EntryLoO Exceptions Coprocessor unusable exception A 172 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details TLT Trap If Less Than TLT 31 26 25 21 20 16 15 6 5 0 SPECIAL rs rt code TLT 000000 110010 6 5 5 10 6 Format TLT rs rt Description The contents of general register rt are compared to general register rs Considering both quantities as signed integers if the contents of general register rs are less than the contents of general register rt a trap exception Occurs The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction Operation 32 64 T if GPR rs lt GPR rt then TrapException endif Exceptions Trap exception MIPS R4000 Microprocessor User s Manual A 173 Appendix A TLTI Trap If Less Than Immediate TLTI 31 26 25 21 20 16 15 0 REGIMM rs TLTI immediate 000001 01010 6 5 5 16 Format TLTI rs immediate Description The 16 bit immediate is sign extended and compared to the contents of general register rs Considering both quantities as signed
155. s Type field indicates which of each of the four bytes within the data word should be stored MIPS R4000 Microprocessor User s Manual A 7 Appendix A As shown in Table A 3 the Access Type field indicates the size of the data item to be loaded or stored Regardless of access type or byte numbering order endianness the address specifies the byte which has the smallest byte address in the addressed field For a big endian machine this is the leftmost byte and contains the sign for a 2 s complement number for a little endian machine this is the rightmost byte Table A 3 Access Type Specifications for Loads Stores Access Type Mnemonic Value Meaning DOUBLEWORD 7 8 bytes 64 bits SEPTIBYTE 6 7 bytes 56 bits SEXTIBYTE 5 6 bytes 48 bits QUINTIBYTE 4 5 bytes 40 bits WORD 3 4 bytes 32 bits TRIPLEBYTE 2 3 bytes 24 bits HALFWORD 1 2 bytes 16 bits BYTE 0 1 byte 8 bits The bytes within the addressed doubleword which are used can be determined directly from the access type and the three low order bits of the address A 8 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details A 5 Jump and Branch Instructions All jump and branch instructions have an architectural delay of exactly one instruction That is the instruction immediately following a jump or branch that is occupying the delay slot is always executed while the target instruction is being fetched from storage A de
156. ser s Manual CPU Instruction Opcode Bit Encoding CPU Instruction Set Details The remainder of this Appendix presents the opcode bit encoding for the CPU instruction set ISA and extensions as implemented by the R4000 Figure A 2 lists the R4000 Opcode Bit Encoding MIPS R4000 Microprocessor User s Manual 28 26 Opcode 31 29 0 1 2 3 4 5 6 7 0 SPECIAL REGIMM J JAL BEQ BNE BLEZ BGTZ 1 ADDI ADDIU SLTI SLTIU ANDI ORI XORI LUI 2 COPO COP1 COP2 BEQL BNEL BLEZL BGTZL 3 DADDIe DADDIUe LDLe LDRe 4 LB LH LWL LW LBU LHU LWR LWUe 5 SB SH SWL SW SDLe SDRe SWR CACHE 5 6 LL LWC1 LWC2 LLDe LDC1 LDC2 LDe 7 SC SWC1 SWC2 SCDe SDC1 SDC2 SDe 2 0 SPECIAL function 5 3 0 1 3 4 5 6 7 0 SLL SRL SRA SLLV i SRLV SRAV 1 JR JALR SYSCALL BREAK j SYNC 2 MFHI MTHI MFLO MTLO DSLLVe DSRLVe DSRAVe 3 MULT MULTU DIV DIVU DMULTe DMULTUe DDIVe DDIVUe 4 ADD ADDU SUB SUBU AND OR XOR NOR 5 y SLT SLTU DADDe DADDUe DSUBe DSUBUe 6 TGE TGEU TLT TLTU TEQ TNE 7 DSLLe DSRLe DSRAe DSLL32e DSRL32e DSRA32e 18 16 REGIMM rt 20 19 0 1 2 3 6 7 0 BLTZ BGEZ BLTZL BGEZL E i E 1 TGEI TGEIU TLTI TLTIU TEQI id TNEI d 2 BLTZAL BGEZAL BLTZALL BGEZALL s 23 21 COPz rs 25 24 0 2 4 5 6 7 0 MF DMFe CF Y MT DMTe CT Y 1 BC Y Y Y Y Y Y Y 2 CO 3 F
157. setting of the current rounding mode the conversion is rounded as if the current rounding mode is round to the nearest even RM 0 This instruction is valid only for conversion from a single or double precision floating point formats The operation is not defined if bit 0 of any register specification is set and the FR bit in the Status register equals zero since the register numbers specify an even odd pair of adjacent coprocessor general registers When the FR bit in the Status register equals one both even and odd register numbers are valid When the source operand is an Infinity or NaN or the correctly rounded integer result is outside of 21 to 231 1 an Invalid operation exception is raised If Invalid operation is not enabled then no exception is taken and 231 _1 is returned MIPS R4000 Microprocessor User s Manual B 49 Appendix B ROUND W fmt Floating Point ROUND W fmt Round to Single Fixed Point Format continued Operation T StoreFPR fd W ConvertFmt ValueFPR fs fmt fmt W Exceptions Coprocessor unusable exception Floating Point exception Coprocessor Exceptions Invalid operation exception Unimplemented operation exception Inexact exception Overflow exception B 50 MIPS R4000 Microprocessor User s Manual FPU Instruction Set Details Store Doubleword from FPU SDC1 Coprocessor 1 SDC1 21 20 16 15 offset 16 Format SDC1 ft offset base Descrip
158. sful store sets it to 0 The operation of Store Conditional is undefined when the address is different from the address used in the last Load Linked This instruction is available in User mode it is not necessary for CPO to be enabled If either of the two least significant bits of the effective address is non zero an address error exception takes place If this instruction should both fail and take an exception the exception takes precedence A 126 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details SC Mr SC Operation 32 T vAddr lt offset s offsetys 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpsizg 4 5 pAddre o xor ReverseEndian 02 data lt GPR rt e3 g byte 0 09 Pte if LLbit then StoreMemory uncached WORD data pAddr vAddr DATA endif GPR rt 0 LLbit 64 T vAddr lt offset s offset s 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrpsizg 4 5 pAddra o xor ReverseEndian 02 data GPR rtle3 s byte o 09 gt if LLbit then StoreMemory uncached WORD data pAddr vAddr DATA endif GPR rt 099 LLbit Exceptions TLB refill exception TLB invalid exception TLB modification exception Bus error exception Address error exception MIPS R4000 Microprocessor User s Manual A 127 Appendix A SCD Store Conditional D
159. ssTranslation vAddr DATA pAddr pAddrpsizg 35 Addr o xor ReverseEndian 02 mem lt LoadMemory uncached WORD pAddr vAddr DATA byte vAddrs_ xor BigEndianCPU 0 GPR rt mem a 5yie mems a byte a byte LLbit 1 Exceptions TLB refill exception TLB invalid exception Bus error exception Address error exception MIPS R4000 Microprocessor User s Manual 4 95 Appendix A LLD Load Linked Doubleword LLD 31 26 25 21 20 16 15 0 LLD base rt offset 110100 6 5 5 16 Format LLD rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to form a virtual address The contents of the doubleword at the memory location specified by the effective address are loaded into general register rt The processor begins checking the accessed word for modification by other processor and devices Load Linked Doubleword and Store Conditional Doubleword can be used to atomically update memory locations LLD T14 T0 ADD T2 T1 1 SCD T2 TO BEQ T2 0 L1 NOP This atomically increments the word addressed by T0 Changing the ADD to an OR changes this to an atomic bit set A 96 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details L L D Load Cont d Tena rd L L D The operation of LLD is undefined if the addressed location is uncached and for synchronization between multiple processors t
160. ster HI are loaded into general register rd To ensure proper operation in the event of interruptions the two instructions which follow a MFHI instruction may not be any of the instructions which modify the HI register MULT MULTU DIV DIVU MTHI DMULT DMULTU DDIV DDIVU Operation 32 64 T GPR rd lt HI Exceptions A 112 None MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details MFLO Move From Lo MFLO 31 26 25 16 15 11 10 6 5 0 SPECIAL 0 rd 0 MFLO 000000 0000000000 00000 010010 6 10 5 5 6 Format MFLO rd Description The contents of special register LO are loaded into general register rd To ensure proper operation in the event of interruptions the two instructions which follow a MFLO instruction may not be any of the instructions which modify the LO register MULT MULTU DIV DIVU MTLO DMULT DMULTU DDIV DDIVU Operation 32 64 T GPR rd LO Exceptions None MIPS R4000 Microprocessor User s Manual A 113 Appendix A Move To MTCO System Control Coprocessor MTCO 31 26 25 21 20 16 15 11 10 0 COPO MT rt rd 0 010000 00100 000 0000 0000 6 5 5 5 11 Format MTCO rt rd Description The contents of general register rt are loaded into coprocessor register rd of CPO Because the state of the virtual address translation system may be altered by this instruction the operation of
161. tails DADD Doubleword Add DADD 31 26 25 21 20 16 15 11 10 SPECIAL 0 DADD 000000 00000 101100 6 5 6 Format DADD rd rs rt Description The contents of general register rs and the contents of general register rt are added to form the result The result is placed into general register rd An overflow exception occurs if the carries out of bits 62 and 63 differ 2 s complement overflow The destination register rd is not modified when an integer overflow exception occurs This operation is only defined for the R4000 operating in 64 bit mode Execution of this instruction in 32 bit mode causes a reserved instruction exception Operation 64 T GPR rd GPR rs GPR rt Exceptions Integer overflow exception Reserved instruction exception R4000 in 32 bit mode MIPS R4000 Microprocessor User s Manual A 51 Appendix A DADDI boubieword Add Immediate PADD 31 26 25 21 20 16 15 0 DADDI rs rt immediate 011000 6 5 5 16 Format DADDI rt rs immediate Description The 16 bit immediate is sign extended and added to the contents of general register rs to form the result The result is placed into general register rt An overflow exception occurs if carries out of bits 62 and 63 differ 2 s complement overflow The destination register rt is not modified when an integer overflow exception occurs This operation is only defined for the R4000 ope
162. target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended Unconditionally the address of the instruction after the delay slot is placed in the link register r31 If the contents of general register rs have the sign bit cleared then the program branches to the target address with a delay of one instruction General register rs may not be general register 31 because such an instruction is not restartable An attempt to execute this instruction is not trapped however If the conditional branch is not taken the instruction in the branch delay slot is nullified Operation 32 T target lt offset s offset 0 condition GPR rs 3 0 GPR 31 PC 8 T 1 if condition then PC PC target S NullifyCurrentInstruction endif 64 T target lt offset 5 46 offset 07 condition GPR rs as 0 GPR 31 PC 8 T 1 if condition then PC PC target ene NullifyCurrentInstruction endif Exceptions el None MIPS R4000 Microprocessor User s Manual A 29 Appendix A B h On Great B G EZ L Than Or Equal To Zero Likely B G EZ L 31 26 25 21 20 16 15 REGIMM BGEZL offset 000001 00011 6 5 16 Format BGEZL rs offset Description A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits an
163. th the instruction immediately after a TLBP instruction nor is the operation specified if more than one TLB entry matches Operation 32 T Indexe 1 079 undefined for i in 0 TLBEntries 1 if TLB i os 77 EntryHig1 12 and TLB i zg Or TLB i z g4 EntryHiz_ o then Index 0 l is 9 endif endfor 64 T Indexe 1 0 5 undefined for i in 0 TLBEntries 1 if TLB i 167 141 and not 0 TLB i 246 205 EntryHiss 3 and not 0 TLB i 216 295 and TLB i 140 or TLB i 135 128 EntryHiz 9 then Index 0 l is 9 endif endfor Exceptions Coprocessor unusable exception MIPS R4000 Microprocessor User s Manual A 169 Appendix A TLBR Read Indexed TLB Entry TLBR 31 26 25 24 65 0 COPO CO 0 TLBR 010000 1 0000000000000000000 000001 6 1 19 6 Format TLBR Description The G bit which controls ASID matching read from the TLB is written into both of the EntryLo0 and EntryLol registers The EntryHi and EntryLo registers are loaded with the contents of the TLB entry pointed at by the contents of the TLB Index register The operation is invalid and the results are unspecified if the contents of the TLB Index register are greater than the number of TLB entries in the processor Operation 32 T PageMask TLB Indexs 1127 96 EntryHi lt TLB Indexs o gs g4 and not TLB Indexs 6 127 96 EntryLo1 TLB Indexs olea 32 Entry
164. the contents of general register rt in a bit wise logical OR operation The result is placed into general register rd Operation 32 64 T GPR rd GPR rs or GPR rt Exceptions None MIPS R4000 Microprocessor User s Manual A 123 Appendix A ORI Or Immediate ORI 31 26 25 21 20 16 15 0 ORI rs rt immediate 001101 6 5 5 16 Format ORI rt rs immediate Description The 16 bit immediate is zero extended and combined with the contents of general register rs in a bit wise logical OR operation The result is placed into general register rt Operation 32 T GPRirt GPR rs a 16 immediate or GPR rs 15__ o 64 T GPR rt GPR rsles 16 immediate or GPR rs 15 0 Exceptions None A 124 MIPS R4000 Microprocessor User s Manual SB CPU Instruction Set Details Store Byte SB 31 26 25 21 20 16 15 0 SB base rt offset 101000 6 5 5 16 Format SB rt offset base Description The 16 bit offset is sign extended and added to the contents of general register base to forma virtual address The least significant byte of register rt is stored at the effective address Operation 32 T 64 T vAddr lt offset s offsetys 9 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrps ze 1 3 pAddre o xor ReverseEndian byte vAddr 9 xor BigEndianCPU data GPR rtjes
165. tion The 16 bit offset is sign extended and added to the contents of general register base to form an unsigned effective address In 32 bit mode the contents of registers ft and ff 1 from the floating point coprocessor are stored at the memory location specified by the effective address This instruction is not valid and is undefined when the least significant bit of ft is non zero In 64 bit mode the 64 bit register ft is stored to the contents of the doubleword at the memory location specified by the effective address The FR bit of the Status register SR specifies whether all 32 registers of the R4000 are addressable When FR equals zero this instruction is not defined if the least significant bit of ft is non zero If FR equals one ft may specify either odd or even registers If any of the three least significant bits of the effective address are non Zero an address error exception takes place MIPS R4000 Microprocessor User s Manual B 51 Appendix B Store Doubleword from FPU SDC1 Coprocessor 1 SDC1 continued Operation vAddr lt offset s offsetys 9 GPR base vAddr lt offset s offset 5 9 GPR base pAddr uncached lt AddressTranslation vAddr DATA if SRog 1 64 bit wide FGRs data FGR ft elseif fty 0 then valid specifier 32 bit wide FGRs data FGR ft 1 FGR ft else undefined for odd 32 bit reg s data undefined94 endif StoreMemory unca
166. to Appendix A for a detailed description of the CPU instructions The instructions are listed alphabetically and any exceptions that may occur due to the execution of each instruction are listed after the description of each instruction Descriptions of the immediate causes and the manner of handling exceptions are omitted from the instruction descriptions in this appendix refer to Chapter 7 for detailed descriptions of floating point exceptions and handling Figure B 3 at the end of this appendix lists the entire bit encoding for the constant fields of the floating point instruction set the bit encoding for each instruction is included with that individual instruction MIPS R4000 Microprocessor User s Manual B 1 Appendix B B 1 Instruction Formats There are three basic instruction format types e I Iype or Immediate instructions which include load and store operations e M Type or Move instructions e R Type or Register instructions which include the two and three register floating point operations The instruction description subsections that follow show how these three basic instruction formats are used by e Load and store instructions e Move instructions e Floating Point computational instructions e Floating Point branch instructions Floating point instructions are mapped onto the MIPS coprocessor instructions defining coprocessor unit number one CP1 as the floating point unit Each operation is valid only
167. will be loaded depending on the starting byte specified In 64 bit mode the loaded word is sign extended Conceptually it starts at the specified byte in memory and loads that byte into the high order left most byte of the register then it loads bytes from memory into the register until it reaches the low order byte of the word in memory The least significant right most byte s of the register will not be changed memory big endian register 4 5 6 7 before A B C D 24 0 1 2 3 LWL 24 1 0 after 1 2 3 D 24 MIPS R4000 Microprocessor User s Manual LWL 32 64 CPU Instruction Set Details Load Word Left LWL continued The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LWL or LWR instruction which also specifies register rt No address exceptions due to alignment are possible Operation T vAddr lt offset s offsety5 0 GPR base pAddr uncached lt AddressTranslation vAddr DATA pAddr pAddrpgizg 5 pAddrs o xor ReverseEndian if BigEndianMem 0 then pAddr pAddrpgize 1 2 0 endif byte vAddr 9 xor BigEndianCPU word lt vAddr xor BigEndianCPU mem LoadMemory uncached 0 byte pAddr vAddr DATA temp Mem32 word 8 byte 7
168. xception Bus error exception Address error exception A 104 MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details Load Word Right LWR 26 25 21 20 16 15 LWR offset 100110 6 16 Format LWR rt offset base Description This instruction can be used in combination with the LWL instruction to load a register with four consecutive bytes from memory when the bytes cross a word boundary LWR loads the right portion of the register with the appropriate part of the low order word LWL loads the left portion of the register with the appropriate part of the high order word The LWR instruction adds its sign extended 16 bit offset to the contents of general register base to form a virtual address which can specify an arbitrary byte It reads bytes only from the word in memory which contains the specified starting byte From one to four bytes will be loaded depending on the starting byte specified In 64 bit mode if bit 31 of the destination register is loaded then the loaded word is sign extended Conceptually it starts at the specified byte in memory and loads that byte into the low order right most byte of the register then it loads bytes from memory into the register until it reaches the high order byte of the word in memory The most significant left most byte s of the register will not be changed memory big endian register weed EHIH so CATS CT e L
169. ype Jump and Link instructions save their return address in register 31 Coprocessor instructions perform operations in the coprocessors Coprocessor loads and stores are I type Coprocessor computational instructions have coprocessor dependent formats see the FPU instructions in Appendix B Coprocessor zero CPO instructions manipulate the memory management and exception handling facilities of the processor Special instructions perform a variety of tasks including movement of data between special and general registers trap and breakpoint They are always R type MIPS R4000 Microprocessor User s Manual CPU Instruction Set Details A 2 Instruction Formats Every CPU instruction consists of a single word 32 bits aligned on a word boundary and the major instruction formats are shown in Figure A 1 I Type Immediate 31 26 25 2120 1615 0 op rs rt immediate J Type Jump 31 26 25 0 EN QNI R Type Register 31 26 25 2120 1615 1110 65 0 op rs rt rd shamt funct op 6 bit operation code rs 5 bit source register specifier rt 5 bit target source destination or branch condition inmediate 16 bit immediate branch displacement or address displacement target 26 bit jump target address rd 5 bit destination register specifier shamt 5 bit shift amount funct 6 bit function field Figure A 1 CPU Instruction Formats MIPS R4000 Microprocessor User s Manual A 3 Appendix A A 3 Instruction Notation Conventions

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