“Leopard” Nexus Emulation Adapter 257BGA – 144TQ
Contents
1. 1 SY 5 F M Solutions for Embedded Systems Development V1 4 Adapters Leopard Nexus Emulation Adapter 257BGA 14410 Ordering code IA257BGA144TG 564XL Target CPU package OFP144 Original microcontroller in the QFP144 package has only 4 bit Nexus port Leopard Nexus Emulation Adapter 15 based on the MPC5643L microcontroller in the BGA257 package emulation device which exposes 12 bit Nexus port The Emulation Adapter exhibits the same behaviour to the target as the original 144 pin microcontroller and additionally provides a 12 bit Nexus port max port bandwidth which allows advanced functionalities like trace profiler and code coverage 144 pin solder part which must be ordered separately under the IA144TO SOLDER ordering code is soldered to the target PCB instead of populating the original microcontroller in a 144 pin QFP package Then the Emulation Adapter which acts as the original microcontroller and additionally provides debug Nexus port is connected on top Contact iSYSTEM sales representative for more details on available Nexus tools 1ISYSTEM November 2013 1 8 lA144TQ SOLDER 4 VE Nos Ne Ne Ne Na Now 9 Unit mm A B C D E K L 22 1 125 23 0 23 0 2 15 25 05 25 05 IA144TQ SOLDER dimensions iSYSTEM November 2013 2 8 Jumper configuration J1 and J2 clock s2. cnp __ Joen joon joon joon Teen o TEXTAL 10pL 10 iSYSTEM November 2013 6 8 iSY STEM November 2013 7 8 Disclaimer 15 5 assumes no responsibility for any errors which may appear in this document reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information herein iSYSTEM All rights reserved iSY STEM November 2013 8 8
3. D LVZ 7 GND Ab S18 Cpu TRST VDD LVZ 419 Nt Bo MDOG VDD LVZ k GND atts 41 Fe VOD LV ND wz T A A RIS VDD LVZ kaa GND VOD LVZ K1 _GND VDD LVZ Ki1_GND so tZ GND BLI eft L8 GND 8 2 CND B 4 VDD_LV_COR F9 GND Bts B 4 s VDD LVZ GND 815 B 5 07 IPFO VDD LVZ bs 815 ate 55 TPF1 VDD LVZ VsS_LV_CORE_RiNc 25 ate 87 02 __ VDDT LVZ VSS__LV_ CORE 67 818 8 Ez MDO2 LV VSS LV CORE RING GND 8 12 ats E2 MDO1 VDD LVZ VSST LV CORE RING G2 GND EE B ts MCKO VDD LVZ VSS LV CORE RING 611 GND az B ka MSEO1 VDD LV VSST LV COREZ RING S11 GND B K1 MSEOG VDD LVZ VSS LV_ CORE RING 9 GND iz EVIO VDD LV VSS LV CORE RING GND B 15 B 22 VDD_LV_ 814 12 N4 8 13 VDD_LV_PLL VDD LV PLLO PLLI VSS_LV_ PLLO GND ch c D13 IPE14 cho c TPF15 H R VDD_HV_PMU CVDD HV PMU che FCCU_ 9 1 cl c Z FCCUZ 1 CVDD HV OSC OSC VSS_HV_OSC GND chs 51 TPG2 CVDD HV ADRG VDD ADRO vss_HVv_aprel 17 cu che cfs 217 CVDD ADR1 VDD HV ADR VSST HV ADRI GND rta c 417 IPG4 u10 5 17 TPGS CVDD HV ADV VDD HV ADV
4. EG 12 Notconnected a E 18 11 Notconnected Notconnected 39 28 N14 E 13 39 C12 El 14 15 93 14 hi E19 U 15 131 E 15 135 012 2 U13 3 Notconnected Notconnected 4 VDD LV PLLO PILI 36 5 6 VSS_HV_ADR 25 GND MPC5643L BGA257 7 VSST ADRI GND 9 VSS HV ADVG ADV1 22 GND 96 11 GND CVDD_HV_REC 1 e gq ne 2 GND 127 6ND a G 2 28 VDD LV c 3 GND 9 15 css 2 orig cts 1001 1 10u 1001 10u 10u Nb Che 40 k R15 94 GND VDD LV c 8 N ce3 4 ces 0 132 SND VSS_LV_ POLO 25 GND a Hi POUF 10u 1001 10u 100x 1 1 cnp OSB C7 iON oy 100n n GND MPC5643L_ 144 3 CVDD HV OSC P6 77 058 ea n GARE J3 MDO9 7 1 MD CVDD HV ADRO OH TAR_ RESET EPU BESET BJ EN 59 CPU RESET CPU TDO ovce cnp 08n MDO10 E ne CvDD_ HY ADRT 657 CPU TDI MDO5 CPU TRST MDO4 1 011 MDO3 MDO2 CVDD HV ADV MDO1 ee CVDD_HV_FLAy c56 MSEOO mr 1 MICTOR CVDD HV PMU s PM gular IDC26TH sae GND n GND as J1 CVDD_HV_REG 1667 1666 1653 1051 c49 4 4 gt PXTAL Ps J2 heen leon joon _ Noe TXTAL CVDD 10 1067310721071 1070 C69 C52 C50 48 Pera
5. Note that these values are valid for 40MHz crystal only If different crystal is used appropriate capacitors must be soldered replace original ones Note It has been confirmed that some quartz crystals don t generate sufficient clock amplitude for the MPC564xL microcontroller operation Freescale MPC564xL reference design uses the NX5032GA quartz and no problems have been noticed with the emulation adapter when using this particular type iSYSTEM November 2013 3 8 J3 target reset configuration Jumper J3 connects the reset line between the emulation device and the target By default J3 1s not populated U3 power selection The U3 header row is used for power supply selection Power supplies are organized in groups and the same voltage must be supplied for each group Refer to the microcontroller user manual for more details which power supply designation belongs to which power supply Signal Signal Pin Pin Signal Signal IEA PS direction direction jumper Re fo Tee 7 8 PU Tasei VOD ADV S 10 evon PU m E E Tee jaja Te U3 signal description TE T T T By default all jumpers are set even though only some jumpers affect the configuration When jumpers are set target power supply coming from the target gets connected to the microcontroller residing on the emulation adapter If a different pow
6. VSS ADV GND _ 1206 16 c 15 c c 7 514 1PG7 CVDD HV FLA VSS_HV_FLA GND call R17 TPG9 VSS HV 10 RING A GND 0 2 oe c te 15 TPG10 CVDD HV REG HV REG 0 VSST HV 102 RING A7 lt GND DE pfa e1 1 TPG1 1 REG 55 HV 107 RING 419 GND ie ss 3 Le F 8 1 A6 AV 82 pfs VDD_HV_ADRO VDD HV ADRO D 4 G 14 CVDD HV REG VSS HV IO RING GND m 56 7 0 ele SVDD HV REG VS AIO RING B9 GND ADR1 3 VDD ADR1 A5 105 C3 ofa VDD_HV_ADV _ADV1 VDD HV ADV ote Ht VSS HV Io RING SIS GND Dj ec a ee p 9 HL 21 61 MDO5 CVDD HV IO VDD HV IO RING H2 GND H3 1 MDO4 CVDD HV IO T 10T RING H2 GND 0 7 6 __ O D 11 Hall CVDD HV 10 E P9 GND 0 14 21 VDDT HVT IO oft prej H17 CVBD HV 10 VOD HZ 107 RING R3 END 126 VDO HV IO HS CVDD HV 10 VOD HVZ IOL RING R15 GND 52 VDD HY 10 Efo 5 CVDDZ HVT IO ZHVIL VSST 107 RINGIL GND 2 BE oe ia 616 Ho HV 10 T17 eta VDD_HV_OSC E 2 Ho CVDD_ HV IO HV IOL RING VSST 107 RING GND Osc 72 HV HV_10_ HV_10_ Ui E 5 VDD OHV PMU HVZ PMU 5 CVDDZ HVZ 10 PI VOD HY IO RING VSS HY 107 RING U GND ere et HUE 615 HV 105 VDD HY IOZ RING VSS HV 107 RING 17 Elo VOD HV REG 1 130 VOD REG 8 HESI Al2 Ho m Efo VDD_HV_REG_2 VDD R
7. er source is to be used e g in case of a standalone operation jumpers must be removed and power source must be applied to CVDD REG pin4 CVDD HV PMU CVDD HV FLA pin8 CVDD HV ADV pinl0 CVDD HV ADRI pinl2 CVDD HV pinl4 CVDD HV OSC pinl6 CVDD HV IO pinl8 and GND pins 21 26 signals 1SYSTEM November 2013 4 8 1SYSTEM power supply adapter can be ordered separately under the IEA PS ordering code It connects on top of the emulation adapter directly to the U3 header row and allows standalone usage of the emulation adapter 3 3V or 5V voltage can be selected for each group with appropriate jumpers JO J9 This is convenient when the target is not available or it s not adjusted for the emulation adapter connection yet JA 6 6 Ae 5 V Re 2 222 te de oe IEA PS optional emulation adapter power supply iSYSTEM November 2013 5 8 Schematic 144T 29 __ U1 CPU TEXTAL A2 GND 1 ar RI EXTAL VDD LV CORG H7 GND ats 31 de VDD LVZ HS Ne RESET NMI VDD LVZ Ho GND A 88 VDD LVZ 618 a 87 5 CPU_ RESET VDD LVZ H11_GND ne are o LVZ H14 123 L1S_cpy_TCK VDD LVZ 37 GND AJ ala CPU TMS VDD LVZ 48 9 ato VD
8. ource configuration Jumpers J1 and J2 select clock source for the emulation device Per default both jumpers set to position 1 2 which yields clock source being used from the emulation adapter For the first time after receiving the emulation adapter 1t 15 recommended that it s tested with this setting Once it s confirmed that it is operational target clock use J1 amp J2 position 2 3 can be tested Note that the emulation adapter may not operate when crystal circuit is used in the target Typical design guideline is that a crystal should be as close as possible to the microcontroller However it may happen that the target crystal may not oscillate with the emulation adapter since clock lines XTAL EXTAL between the target and the emulation device on the emulation adapter are prolonged There should be no problem with the oscillator being used in the target If an oscillator in the target is not an option and the target crystal doesn t oscillate in conjunction with the emulation adapter clock from the emulation adapter must be used J1 amp J2 position 1 2 In this case a crystal circuit must be assembled on the emulation adapter Q1 e51 7 PXTAL GND N SO 4 fF PEXTAL alls SO Crystal circuit Crystal circuit is located in the corner of the emulation adapter next to the Nexus Mictor connector Per default 10pF capacitors are populated for C3 and C4 and 40MHz crystal for O1
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