Verilog-2001 Presentation
Contents
1. 2000 2001 by Sutherland HDL Inc www sutherland hdl com 12 SUTHERLAND Constant Functions Example AD p module ram parameter RAM SIZE 1024 parameter ADDRESS 12 input ADDRESS 1 0 address_bus module ram parameter RAM SIZE 1024 input clogb2 RAM_SIZE 1 0 address_bus function integer clogb2 input 31 0 depth begin for clogb2 0 depth gt 0 clogb2 clogb2 1 depth depth gt gt 1 end endfunction original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com L 13 SUTHERLAND 4 Hp L Indexed Vector Part Selects Verilog 2001 adds the capability to use variables to select a group of bits from a vector The starting point of the part select can vary The width of the part select remains constant reg 63 0 word reg 3 0 byte num a value from 0 to 7 wire 7 0 byteN word byte num 8 8 original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 14 SUTHERLAND D Hp Multi dimensional Arrays Verilog 1995 allows 1 dimensional arrays of reg integer and time variables Typically used to model RAM and ROM memories Verilog 2001 adds Multidimensional arrays of any variable data type a Multidimensional arrays of any net data type L declare a 3 dimensional array of 8 bit wire nets wire 7 0 array2. 2001 adds new timing constraint checks a More accurately model very deep submicron input constraints a New timing constraint tasks added removal recrem timeskew fullskew Refer to the proposed IEEE 1364 2001 Verilog standard for details on these tasks L original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 40 SUTHERLAND St Hp Negative Timing Constraints Verilog 2001 adds the ability to specify negative values for setuphold setup and hold times Adds new optional arguments to the Verilog 1995 setuphold task recrem recovery and removal times A new timing check task in Verilog 2001 L original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 41 SUTHERLAND 32 Hp Enhanced SDF support The Verilog 2001 standard defines How timing objects in SDF map to objects in Verilog Based on the latest SDF standard IEEE 1497 1999 Verilog 2001 changes the syntax of the Sspecparam constant Can now be declared at the module level as well as within a specify block to support SDF labels Verilog 2001 adds a standard sdf_annotate system task Already a de facto standard in all simulators L original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 42 SUTHERLAND 33 Hp Extended VCD Files Veril
3. 45 SUTHERLAND When Will These Hp Enhancements Be Available The official word from several EDA vendors is They will not comment on future product plans They will not begin to implement Verilog 2001 until it is ratified The unofficial word from EDA vendors is Some have already started implementing Verilog 2001 One essentially says they do not see any need to implement the new features in Verilog 2001 L E ye original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 46 SUTHERLAND Summary Hp p Verilog 2001 is complete The proposed IEEE 1364 2000 Verilog standard is now in the final balloting phase Verilog 2001 contains Over 30 major enhancements a Many clarifications and errata corrections Verilog 2001 adds powerful capabilities Greater deep submicron accuracy More abstract system level modeling Scalable re usable modeling Final approval is expected in late 20 00 PPA P E FEREN S EH E A A P tan Aawel watt Manal OT TINISNING ratirying tne standard untill Marc PETIT original Dut the ALITY N 2001 updated To UUL ZUUL W ZUUU ZUUL DY oOuuGdiU MUL LIC WWW SUUTET diU CONI 47 SUTHERLAND For More Information AD E The book Verilog 2001 A Guide to the New Features of the Verilog HDL covers the enhancements in Verilog 2001 in more detail Author Stua
4. be hard coded Verilog 1995 77 Verilog 2001 will automatically extend a logic Z or X to the full width of the left hand side parameter WIDTH 64 Verilog 2001 reg WIDTH 1 0 data data bz ills with hzzz222222222z222z original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 23 SUTHERLAND 14 Hp Default Nets with Continuous Assigns L Verilog 2001 will default to a net data type on the left hand side of any continuous assignment The net will be scalar 1 bit if not connected to a port of the module In Verilog 1995 the left hand side must be explicitly declared if not connected to a port of the module Verilog 1995 Verilog 2001 assign eq a b defaults to 1 bit wire original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 24 SUTHERLAND 15 Hp Disable Default Net Declarations n In Verilog 1995 undeclared signals can default to a wire data type The default data type can be changed to another net data type using default_nettype lt data_type gt Verilog 2001 provides a means to disable default net declarations default_nettype none a Any undeclared signals will be a syntax error Prevents hard to debug wiring errors due to a mistyped name none is not a new reserved word original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Suthe
5. initializing variables at the time they are declared The initialization is executed in time step zero just like initial procedures Verilog 1995 Verilog 2001 reg clock 0 original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 29 SUTHERLAND 20 Hp _ Register Changed To Variable The Verilog 2001 standard changes the term register to variable register is not a reserved word it is just a term Since its inception in 1984 Verilog manuals have used the term register to describe a class of data types reg unsigned variable integer signed variable real double precision variable etc The term register often confuses new Verilog users register is a hardware term for storage elements Verilog registers do not imply a hardware register L original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 30 SUTHERLAND 2t Hp Enhanced Conditional Compilation Verilog 1995 supports limited conditional compilation ifdef else endif and undef compiler directives Verilog 2001 adds more extensive conditional compilation control a New directives ifndef and elsif original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 31 SUTHERLAND 22 Hp File and Line Compiler Directive
6. operand is real a real value is returned If both operands are integers an integer value is returned L module ram parameter WORD SIZE parameter ADDR SIZE reg WORD SIZE 1 0 core 0 2 ADDR SIZE 1 original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 18 SUTHERLAND 9 Re entrant Tasks Hp and Recursive Functions Verilog 2001 adds automatic tasks and functions Each call to the task function allocates unique storage In Verilog 1995 tasks and functions are static each call shares the same storage space Concurrent task calls will not interfere with each other Recursive calls to a function are stacked New reserved word added automatic function automatic 63 0 factorial input 31 0 n L if n 1 factorial 1 else factorial n factorial n 1 endfunction original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 19 SUTHERLAND 10 Hp Comma separated Sensitivity List E Verilog 2001 adds a second syntax style for listing signals in a sensitivity list Signals in the list can be separated with a comma The old or separated list will still work Verilog 1995 Verilog 2001 always sel case sel 2 b00 2 b01 2 b10 2 b11 endcase original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Su
7. 3 0 255 0 255 0 15 select one word out of a 3 dimensional array wire 7 0 out3 array3 addr1 addr2 addr3 original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 15 SUTHERLAND 6 Hp Array Bit and Part Selects Verilog 2001 adds Bit selects out of an array Part selects out of an array L select the high order byte of one word in a 2 dimensional array of 32 bit reg variables reg 31 0 array2 0 255 0 15 wire 7 0 out2 array2 100 7 31 24 original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 16 SUTHERLAND f Hp Signed Arithmetic Extensions Verilog 2001 adds reg and net data types can be declared as signed reg signed 63 0 data wire signed 11 0 address Function returns can be declared as signed function signed 128 0 alu Literal integer numbers can be declared as signed New arithmetic shift operators lt lt lt and gt gt gt maintain the sign of a value New signed and unsigned system functions can cast a value to signed or unsigned original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 17 L SUTHERLAND 8 Hp Power Operator Verilog 2001 add an exponential power operator a Represented by the token Similar to the C pow function If either
8. ERLAND Overview of HDL Enhancements ADL Cb 33 major enhancements were added to the Verilog HDL Brief description and examples New reserved words Errata and clarifications Dozens of corrections were made to 1364 1995 Do not affect Verilog users Very important to Verilog tool implementors Not listed in this paper refer to the 1364 2001 Verilog Language Reference Manual LRM original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com SUTHERLAND ip Hp Verilog Configurations Verilog 1995 leaves design management up to the software tools Every tool has different ways to manage large designs Verilog 2001 adds configuration blocks All software tools will have a consistent method a The version for each module instance can be specified Virtual libraries specified within Verilog source code Physical file locations specified in a map file a New reserved words added config endconftig design instance cell use liblist L original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com SUTHERLAND Hp Verilog Configuration Notes L Verilog design hierarchy is modeled the same as always Configurations can be used to specify which module source code should be used for each instance of a module With Verilog 1995 it is up to the simulator on how to specify which model ver
9. The IEEE Verilog 1364 2660 2001 Standard What s New and Why You Need It by Stuart Sutherland Sutherland HDL Inc Verilog Training and Consulting Experts Presented at the HDLCON 2000 Conference March 10 2000 San Jose California This presentation was updated August 2001 to clarify some points and make minor corrections in some examples my thanks to Cliff Cummings of Sunburst Design for suggesting the changes SUTHERLAND Verilog 2606 2001 Status ADL p The specification of the Verilog 2666 2001 standard is complete Voting draft completed March ist 2000 The final IEEE balloting process has started Expect Verilog 2000 to be ratified in Q3 2000 The official standard will be IEEE Std 1364 26006 2001 UPDATE The IEEE officially ratified the proposed standard in March 2001 The official name for the new Verilog standard is IEEE Std 1364 2001 The common nickname is Verilog 2001 The original version of this presentation was prepared in 2000 At that time it was anticipated that the IEEE would ratify the standard that year Therefore the original version of this presentation used the nickname Verilog 2000 orig upd SUTHERLAND Why a New Standard DL amp Add enhancements to Verilog Design methodologies are evolving System level design intellectual property models design re use very deep submicron etc Cliff Cumming s Top Five Enhance
10. Verilog 2001 adds a line file and line compiler directive Documents the original location of Verilog source code L Verilog tools often include file name and line number information in error and warning messages If a pre process utility program modifies the Verilog source code the original file and line information could be lost The preprocessor can add a line directive to the modified code to preserve the original source file location original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 32 SUTHERLAND 23 Hp Attributes 7 Verilog 2001 adds attribute properties A standard means to specify non Verilog tool specific information to Verilog models Adds new tokens and Eliminates need to hide commands in comments The standard does not define any specific attributes Software vendors can define proprietary attributes Other standards might define standard attributes Verilog 1995 case 1 b1 synopsys parallel case 1 hot FSM Verilog 2001 rtl synthesis parallel case case 1 b1 1 hot FSM original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 33 SUTHERLAND 24 Hp Standard Random Number Generator Verilog 2001 defines the C source code for the generator used by random All simulators can generate the same random number sequence when
11. given the same seed value Simulation results from different simulators can be compared New products do not need to re invent the wheel Uses the random number generator from Verilog XL original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 34 SUTHERLAND 25 Hp Enhanced Invocation Option Tests Verilog 1995 contains a true false test to see if simulation was invoked with a specific option test plusargs Verilog 2001 adds the ability to read arguments of invocation options a New system function value plusargs original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 35 SUTHERLAND 20 Hp Enhanced PLA Modeling Verilog 2001 extends the capability of the PLA system tasks async or array async and array etc L In Verilog 1995 arguments had to be scalar In Verilog 2001 arguments can be vectors original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 36 SUTHERLAND 2T Hp Accurate BNF with Subsections The Verilog 1995 BNF Backus Naur Form had errors and inconsistencies L Verilog 2001 contains a much stronger BNF definition of the Verilog language Consistent terminology More definitive terms Divided into sub sections to make it easier to find specific definitions a Checked for accuracy or
12. iginal 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 37 SUTHERLAND 28 Hp On detect Pulse Error Propagation Verilog 1995 has on event pulse error propagation A pulse is a glitch on the inputs of a module path that is less than the delay of the path An input pulse propagates to a path output as an X with the same delay as if a valid input change had propagated to the output Verilog 2001 adds on detect pulse error propagation As soon as an input pulse is detected a logic X is propagated to a path output without the path delay New reserved words added pulsestyle_onevent pulsestyle_ondetect original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 38 SUTHERLAND 29 Hp Negative Pulse Detection Verilog 2001 adds negative pulse detections Due to different rising transition and falling transition delays it is possible for the trailing edge of a glitch to propagate before the leading edge has propagated In Verilog 1995 a negative pulse is cancelled Negative pulse detection will propagate a logic X for the duration of the negative pulse New reserved words added showcancelled noshowcancelled L original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 39 SUTHERLAND 30 Hp New Timing Constraint Checks Verilog
13. ment Requests from HDLCON 1996 Clarify ambiguities in Verilog 1364 1995 The 1364 1995 reference manual came the Gateway Design Automation Verilog XL User s Manual Verilog 2001 more clearly defines Verilog syntax and semantics original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com SUTHERLAND Goals for Verilog 2001 AD p Enhance Verilog for Higher level abstract system level modeling Intellectual Property IP modeling Greater timing accuracy for very deep submicron Make Verilog even easier to use Correct errata and ambiguities Maintain backward compatibility existing models will work with the new standard Ensure that EDA vendors will implement all enhancements original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com SUTHERLAND The IEEE 1364 Hp Verilog Standards Committee A main working group Final approval of all changes to 1364 1995 About 20 active participants Three task forces a Behavioral Task Force Cliff Cummings chair RTL and behavioral modeling enhancements a ASIC Task Force Steve Wadsworth chair ASIC and FPGA library modeling enhancements a PLI Task Force Drew Lynch Stu Sutherland co chairs PLI enhancements L original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com SUTH
14. og 2001 adds new Value Change Dump VCD capabilities Dump port change values Dump strength level changes Dump the time at which simulation finishes New system tasks added dumpports dumpportsall sdumpportsoff dumpportson dumpportslimit and dumpportsflush L original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 43 SUTHERLAND PLI Enhancements AD amp L Several enhancements added to the VPI library Simulation control Stop finish save restart etc Support for new Verilog 2001 HDL constructs Array of instances attributes signed arithmetic recursive functions enhanced file I O etc Maintenance updates to TF and ACC libraries Corrected errata Clarified ambiguities original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 44 SUTHERLAND The VPI Library Is The Future ADL All enhancements to the Verilog language will only be supported in the VPI library of the PLI TA a The TF and ACC libraries PLI 1 0 ieee are only being maintained _ Y f Al WAREN Warning To Simulator Vendors Z PLI 1 0 is OVI s 1990 Verilog PLI standard It isn t 1990 anymore Your customers do not want prehistoric simulators original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com
15. rland HDL Inc www sutherland hdl com 25 SUTHERLAND 16 eh Explicit In line Parameter Passing E Verilog 2001 adds the ability to explicitly name parameters when passing parameter values Provides better self documenting code Parameter values can be passed in any order module ram parameter WIDTH parameter SIZE endmodule Verilog 1995 Verilog 2001 module my chip RAM SIZE 1023 ram2 endmodule original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 26 SUTHERLAND 17 Hp Combined Port Data Type Declarations Verilog 2001 permits combining port declarations and data type declarations into one statement Verilog 1995 Verilog 2001 module mux8 y a b en output reg 7 0 y input wire 7 0 a b input wire en original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 27 SUTHERLAND 18 H 3 ANSI style Port Lists Verilog 2001 adds ANSI C style input and output declarations a For modules tasks and functions Verilog 1995 Verilog 2001 module mux8 output reg 7 0 y input wire 7 0 a input wire 7 0 b input wire en original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 28 SUTHERLAND 19 Hp Reg Declaration With Initialization f Verilog 2001 permits
16. rt Sutherland Publisher Kluwer Academic Publishers www wkap com ISBN 07923 7568 8 a Price 72 00 US suggested retail price 152 pages original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 48 SUTHERLAND Hp About The Author amp L Stuart Sutherland President of Sutherland HDL Inc Portland Oregon Provides expert Verilog design consulting and training More than 15 years design experience and over 12 years working with Verilog Author of Verilog 2001 A Guide to the New Features of the Verilog HDL The Verilog HDL Quick Reference Guide The Verilog PLI Quick Reference Guide and The Verilog PLI Handbook Member of the IEEE 1364 Verilog standards committee since 1993 co chair of the PLI task force original 10 Mar 2000 updated 18 Oct 2001 49
17. sion should be used for each instance if the simulator can do it at all The configuration block is specified outside of all modules Can be in the same file as the Verilog source code Can be in a separate file Verilog model source code does not need to be modified in order to change the design configuration A separate file maps logical library names to physical file locations Verilog source code does not need to be modified when a design is moved to a different physical source location original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com SUTHERLAND Verilog Configuration Example MDL Verilog Design Configuration Block part of Verilog source code define a name for this configuration config cfg4 specify where to find top level modules design rtlLib test set the default search order for finding instantiated modules default liblist rtlLib gateLib explicitly specify which library to use for the following module instance instance test dut a2 liblist gateLib endconfig location of RTL models current directory library rtlLib v Library Map File Location of synthesized models library gateLib synth _ out v original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com SUTHERLAND 2 Hp Verilog Generate Verilog 2001 adds true generate capabilit
18. therland HDL Inc www sutherland hdl com 20 SUTHERLAND 11 Hp Combinational Logic Sensitivity Verilog 2001 adds a wildcard token to indicate a combinational logic sensitivity list The token indicates automatic sensitivity to any change on any signal that is read by the following statement or statement group L Verilog 1995 Verilog 2001 always case sel 2 b00 2 DOL 2 b10 2 bD1l1 endcase original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 21 SUTHERLAND 12 Hp Enhanced File I O Cb Verilog 1995 has limited built in file I O tasks Up to 31 files can be opened for writing Only ASCII characters can be written to files More complex file I O is done using the Verilog Programming Language Interface PLI Verilog 2001 adds The ability to open up to 2 files New file I O tasks ferror fgetc fgets fflush fread fscanf fseek ftel rewind ungetc New string tasks sformat swrite swriteb Sswriteh swriteo original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 22 L SUTHERLAND 13 Hp Automatic Width Extension Past 32 bits In Verilog 1995 Verilog assignments zero fill when the left hand side is wider than the right hand side Unsized integers default to 32 bits wide therefore the widths of integers must
19. y Use for loops to generate any number of instances of Modules primitives procedures continuous assignments tasks functions variables nets Use F e lse and case decisions to control what instances are generated Provides greater control than the VHDL generate New reserved words added generate endgenerate genvar localparam L original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 10 SUTHERLAND Verilog Generate Example AD p module multiplier a b product parameter a width 8 b width 8 localparam product width a width b width input a width 1 0 a output product width 1 0 product generate if a width lt 8 b width lt 8 CLA multiplier a width b width ul a b product else WALLACE multiplier a width b width ul a b product endgenerate endmodule original 10 Mar 2000 updated 18 Oct 2001 2000 2001 by Sutherland HDL Inc www sutherland hdl com 11 SUTHERLAND 3 Hp Constant Functions Verilog 2001 adds constant functions Same syntax as standard Verilog functions Limited to statements that can be evaluated at compile time Can be called anywhere a constant expression is required Vector width declarations Array declarations Replicate operations Provides for more scalable re usable models L original 10 Mar 2000 updated 18 Oct 2001
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