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Acromag AVME948x Series Manual

1. Mnemonic Mnemonic Mnemonic Mnemonic 1_1 00 D0 2 or 1 3 02 j 6 05 03 7 Do ___ __ 8 __ 007 ___ 05 __ 9 ___ GND 12 pst SYSRESET LWORD WRITE 04 15 16 17 18 19 2 21 P IACKIN 22 24 47 25 ao 26 AOS 27 A04 28 ao 29 ao iRQ27 149 30 aon 18017 A8 31 _32 __ USE WITH SOLID STATE RELAYS The AVME984X Digital Board may interface with industry standard Solid State relays and termination panels PB16A PB32 and their equivalents Configuring The AVME948x On Model AVME948x the following jumpers or shorting clips should be in place J1 J2 J3 J4 J5 J6 J7 and J8 Pullup resistor networks R57 R50 R56 R51 R35 R52 R54 and R53 are optional Table 2 5 lists the Module Number Bit Positioning for the I O port registers Table 2 5 Module Number Bit Positioning Number 765423 0 EE EN To euren 8 76543210 Ln eurei 8 76543 Cne euren 8 76543 0 BABOS e Guaranteed 888 88 SOURCE www artisantg com AVME948x USER S MANUAL Digital Board For bit positions corresponding to output modules a 1 state will turn the I O point on and the output latch will draw current 0 state will turn
2. 14 4500 790 9921 16 Connection Diagram x 15 4500 791 9921 32 Connection Diagram 16 4500 786 9920 16 Digital I O Adapter 17 4500 787 9920 32 Digital I O Adapter 18 4500 785 9920 16 Connection 19 4500 792 9920 32 Connection Diagram 20 4500 743 Relay Driver amp Input Configurations 21 4500 740 VME Interrupter Block Diagram 229 4500 741 9480 Block 23 4500 742 9480 Simplified Schematic 24 4500 737 Digital 25 IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall System design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility 1 0 GENERAL INFORMATION The AVME948x Digital Input Output Boards provide a means for interfacing various discrete devices to a VMEbus based computer Interfacing is accomplished via software control of 64 general purpose points which may be
3. NOISN3NIO 93H2NI LNOUA 19 99 sve 3018 932v14 sd00NVIS 1v34 72 82 orte 06 88 08 6 17 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SIDE VIEW 3 50 88 90 no OFT ON OTTOON DCE AOKANTHOK NNT DONBAD etree anaona B e Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com a a lt 2 lt 5 lt E LI o o INCHES NOTE DIMENSIONS ARE IN MILLIMETERS 1 50 38 10 FRONT VIEW HOIW WOXIM Sowo y 1804 9 1404 1 1804 v 1804 zz 1404 1404 4 8 1404 MM 91 0869 631835 WVYOVIG NOILO3NNOO 91 0266 1 _ IWLIDIG t0 009t 19 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com HOIW WOXIM Sowos y 0140 T13NNVHO WVHO5VIG NOIL23NNOO ualdVQV 26 0266 IWLIDIG 20 Guaranteed 888 88 SOURCE www artisantg com Artisan Technology Group Quality Instrumentation se c e21e
4. SNOISNAWIG 310N LNOYS 86 29 13 80 061 24 ld 90 009 14 Guaranteed 888 88 SOURCE www artisantg com Artisan Technology Group Quality Instrumentation HORM 3V9 V NI SANV1dNOVE OLNI H31dVQV SIHL LON E 6600 2jc6 833 34VS LON SI GUVD 1 91 1266 ALON 4404 1uOd ev 1404 1408 NOILO3S 4 9 51803 NOILO3S 8 7 51808 NOILO3S 51808 935 1 6 1403 tation Guaranteed 888 88 SOURCE www artisantg com n 18 1404 1304 Artisan Technology Group Quality Instru 41818 Hi3OVdS HOLVINSNI ANVIdNOVE 5766 1 1404 9 1804 STANVd 91 0869 531935 NOILO3NNOO 22 1266 WOXIM 0 140 TANNVHO 26 39VO JWA NI 53 Zd OLNI H3 ldVQV SIHL LON OG 34VS LON SI H31dVOV 58 66 310N 9141 5 BHOLVINSNI 16 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 5 0 1 91 0266 T9 T 1 S6owosyv NI
5. 73137130 SI 2d 0350 34V 0896 1300 bd 3 d NJHM 0313130 34V bd d 0350 SI 1096 1300 0 N3HM 1 5340 BN GD mut min 02 8 aan E CU 2310N 335 ooonooannoaaoaonooonon 335 960 009 25 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 4 rtisan tisan Technology Group is your source for quality new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment 7 EQUIPMENT DEMOS HUNDREDS OF Instra 2 REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com 7 information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED aed Contact 888 88 SOURCE sales artisantg com www artisantg com
6. 4 rtisan tisan Technology Group is your source for quality new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment 7 EQUIPMENT DEMOS HUNDREDS OF Instra 2 REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com 7 information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED aed Contact 888 88 SOURCE sales artisantg com www artisantg com Acromag 4M Series 948x Digital Boards USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 1994 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 189 G97C009 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com AVME948x USER S MANUAL Digital Board The information c
7. 1 M3dWnr 30151535 sr er tr saadwar SOURCE www artisantg com 888 88 Quality Instrumentatierl2 Guaranteed Artisan Technology Group 788 ARE ASSIGNED IN REVERSE OF ACTUAL CONNECTOR MARKINGS AND ORDERED 1 1 4500 AS SHOWN a 5 2 e L3 z c 2 z 0050050006000606060600060 NEENA BS SEA 3 G0 3 SAAC 50 0 ef GR CR SA 508 AR EAE SAS SAR SADE AB WIXOM MICH AAA RS 6060000 AE BE E AR 608060 501560 50506060 AS SIDE VIEW Tm 9921 16 DIGITAL 1 0 ADAPTER CARD INCHES MILLIMETERS 0 FRONT VIEW NOTE ALL DIMENSIONS ARE IN 228588295558853 2222 000000000000 00 NNO 1 49 3 5 2 4 6 8 18 13 16 18 20 22 24 26 28 32 34 36 49 48 50 17 13 sem Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com sans Fl HaldVaV 0 1 1V1IOIG 25 1266 HIIN 341 AR 600064 AA AAR BAR 50585460 605 ARE SRR AAA AAS AA A A A AAA 505505 5050 NI
8. 1 6 or 9920 32 are used to interface When in place sets thresholds for Jumper in between P3 amp P4 and the ribbon cables see Drawings 4500 786 input to 1V 42 2V TTL low and place 4500 787 Refer to Table 2 3 and the termination panel high respectively Remove J6 to connection diagrams 4500 785 and 4500 792 D establish reference off card Ports 2 amp N43 voltage CAUTION DO NOT PLUG P2 INTO ANY BACKPLANES IN E jumper When in place pulls the I O Jumper in A CARD CAGE J8 J7 J6 J5 lines to 5V through the optional place J2 J1 4 3 pullup networks Table 2 3A Connectors P2 P3 Ports N 4 amp N 5 reference voltage Functions P2Pin When in place sets thresholds for Jumper in input to 1V and 2 2V TTL low and place high respectively Remove J2 to establish reference off card Ports N 4 amp N 5 pullup voltage jumper When in place pulls the I O Jumper in lines to 5V through the optional place pullup networks Ports 6 amp N 7 reference voltage When in place sets thresholds for Jumper in input to 1V and 2 2 TTL low place high respectively Remove J4 to establish reference off card Bia Bo 44 J jumper When in place pulls the I O Jumper in lines to 5V through the optional pulup networks B9 Dr will disable the outputs of that group DTACK Timer Jumper This jumper Factory is preset at
9. before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before attempting calibration or repair be sure that all of the procedures in Section 2 Preparation For Use have been followed These procedures are necessary since the board has jumpers that must be properly configured Note It has been observed that on occassion a boot program for a disk operating system will hang waiting for the VMEbus SYSFAIL signal to be released by an intelligent disk controller board Acromag s non intelligent slave boards assert the SYSFAIL signal as described to the VMEbus Specification and therefore the disk operating system will remain hung The best solution to this problem is to correct the boot program so that it is no longer dependent upon the SYSFAIL signal When this solution is not practical it is possible to disconnect the SYSFAIL from the circuitry on the Acromag board by removing the jumper for J20 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com AVME948x USER S MANUAL Digital Board CALIBRATION PROCEDURE Due to the digital nature of the AVME948x no maintenance is required during normal operation of the board REPLACEABLE PARTS The Replaceable Parts List Table 5 1 is provided as an aid to the user in troubleshooting the board Replacement par
10. bus Address modifier codes Interrupt request levels Memory Board 5126 A16 016 008 EO slave 29H 2DH IRQ 1 IRQ 7 eight programmable vectors Short I O space user or supervisor amp occupying 1Kbyte consecutive locations base address jumper configurable within 64K short space Double Eurocard NEXP 233mm X 160mm Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 1865 0059 1401 X86 19385 sms NOI1U201 3dMWnfr 43534 dN 3139 1194545 143559 TIM 4908 GATIVLSNI 4301594 11945456 oer 11948545 SNA AMUn NYD NOILISOd LON 3771915 19294 81 51100 S OL 394333338 SLOSNNOD 0311915 1 30N383438 LAdNI sr br er 100 100 100 100 100 100 5 2 TIM 08908 919 1 ON Q3903TSNIYd NON ONY AYOSINYSdNS HLOG 3ZINDO233 TIM 98908 0311915 1 6 8 61044100 8 30 dNOND 19 1 53189510 6 Y ONILLND 1 1 1 1 3201 7104 0311915 1 4501293 1 1 gtr SI vi ETF etr ef 5 51100 S 01 535294 40151533 40 1104 SIO3NNOO 0311915
11. for that group Resistors R21 and R22 along with comparator U8 form a hysteresis switch with a lower threshold of 1V and an upper threshold of 2 2V Buffer U38 is used to put the comparator outputs for the port on the data bus during read operations Output Latches Drivers Refer to Drawing 4500 742 for the following discussion Output latch driver U52 contains 8 CMOS latches and 8 open collector darlington transistors Removable resistor network R57 provides pullup for the lines and is usually pulled up to 5V on the card through jumper J7 Each output has a protection diode Dp which is usually tied to the relay supply voltage when driving relay coils This diode clamps the high voltage spike reverse emf that can occur when a relay coil is turned off quickly 5 0 SERVICE AND REPAIR INFORMATION This section provides calibration procedures service diagrams and instructions on how to obtain service and repair assistance SERVICE AND REPAIR ASSISTANCE It is highly recommended that a non functioning board be returned to Acromag for repair Acromag uses tested and burned in parts and in some cases parts that have been selected for characteristics beyond that specified by the manufacturer Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is fully tested placed in a burn in room at elevated temperature and then retested
12. the module off For bit positions corresponding to input modules a 1 state indicates the presence of a low voltage for the on state of the module A 0 state indicates a high voltage is present Configuring The PB16A If the PB16A is to receive power from the 9480 install a jumper at pin 1 or pin 49 of the PB16A termination panel Install appropriate solid state relay modules Then connect the 50 pin ribbon cable between the PB16A and the AVME9480 while observing the pin 1 index mark USE WITH OTHER DEVICES The AVME9480 Digital I O Board can interface to a variety of discrete devices such as relays switches contact closures and indicators The optional termination panel Model 6980 16U can be used to connect field wiring to the digital I O card The following guidelines should be followed to insure proper interfacing Relays And Other Inductive Loads When driving relays coils or other inductive loads the PROTECT line should be tied to the voltage supply of the loads This puts a suppression diode across each load to limit the voltage spike reverse emf generated when an inductive load is switched off quickly However since PROTECT is common to all 16 outputs the supply voltage for all of the loads must be the same Otherwise each load must have its own external diode and the pullup resistors should be removed from the digital card See Drawing 4500 743 for relay driver configurations Contact Closures And Swit
13. 1 0 The eight interrupt points are level sensitive and prioritized Interrupt point 7 has the highest priority and interrupt point 0 has the lowest priority Each I O interrupting point may be programmed with its own interrupt vector Further each interrupt point may be Reset Condition interrupt points masked individually masked and the interrupt polarity selected Refer to the following paragraphs for further discussion of the interrupt registers Interrupt Level Register Read Write 84 Interrupt Pending Clear Register Read Write 80 The Interrupt Level Register maintains the interrupt level 1 7 that the board responds with when it issues an interrupt request to The Interrupt Pending Register reflects the status of the eight the VMEbus I O interrupt points from Port 0 A 1 in a bit position indicates an interrupt is pending for the corresponding point Each bit is the Reset Condition Register unaffected logical AND of its associated Interrupt Enable and Interrupt Input bits Hence input that is not enabled will never have its interrupt Interrupt Input Polarity Register Read Write 85 pending bit set to a 1 The Interrupt Input Polarity Register determines the level that An individual interrupt can be cleared by writing 1 to its bit will cause an interrupt for each of the eight interrupt points position if the input level has been negated If the input level has no
14. 17 8 i 9 11 13 15 COMMON SUPPLY PROTECT LINE TIED TO V1 PUTS A PROTECTION DIODE NOTE PULL UPS ACROSS EACH RELAY ON AVME 9480 SHOULD BE REMOVED PROTECT NC 9 11 13 15 SEPARATE SUPPLIES EACH RELAY NEEDS ITS OWN EXTERNAL DIODE RELAY DRIVER CONFIGURATIONS SHOWN FOR PORTS amp 0 5 5 5 PULL UP J7 INSTALLED R57 PULL UP NETWORK INSTALLED PULL UP 857 PULL UP 5 INSTALLED 4 SIZE FOR PROPER POWER DISSIPATION SIMPLE CONTACT CLOSURE SENSING CONTACTS SWITCHING A VOLTAGE INPUT CONFIGURATIONS SHOWN FOR PORTS amp 0 1 POINT 0 21 suum Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 02 009 X0v6 52018 u31dnuH34NI IWA nu HIIN 2018 YALdNYYALNI AWA 0896 3NAV 2 S9xx 2 y y O 199 INONIVI 08 i 161099 15193 IWA ONIGNAd 1 ______ TO pin ein pin ein Lan 920 v HO1VH3N3D ssaudaav gual 5 5 ULSI 08 5193 4 orn 6n sen O N 1404 8
15. 3E 3F 40 41 7E 7F R W Interrupt R W Status Control Pending Clear 82 R Int Inputs R W InterruptEnable 83 ___ 84 R W Int Level R W Interrupt Polarity 85 ___ 86 Undefined R W PointO Vector 87 881 Undefined R W Point Vecto 89 Undefined R W Point2Vector 88 Undefined R W Point3 Vector 8D ___ _ Undefined R W Point4 Vector 8F __ Undefined R W Point5 Vector __ 91 Undefined R W Point6 Vector 93 Undefined W Point7 Vector __ 95 97 Undefined FF Undefined 90 92 94 96 FE ___100 102 ___104 106 108 3FE Board Identification ID PROM Read Only 01 3F The Board Identification PROM occupies the 32 odd bytes beginning at location 01 These bytes contain ASCII character strings that identify various characteristics of the board See Table 3 2 Guaranteed 888 88 SOURCE www artisantg com AVME948x USER S MANUAL Digital Board Table 3 2 Digital Board Identification ID PROM BiT NAME DESCRIPTION Hex Offset ASCII Numeric Bit7 Reserved for future use equals O if read Field Description Board Bte Reserved for future use equals 0 if read causes a software reset Writing 0 or reading the bit has no effect A software reset turns all of the ports off which effectively programs the ports for inputs The effect of a Software reset on the va
16. IONS Several jumpers have been included for flexibility in interfacing to external devices Table 2 2 describes these jumpers and their functions IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature 3 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com AVME948x USER S MANUAL Digital Board Table 2 2 Jumper Descriptions CONNECTIONS Jumper Function Shipped Ports N O amp N 1 reference voltage On Model AVME 9481 the 64 I O points are accessible through When in place sets thresholds for Jumper in a 96 DIN 41612 connector labeled P2 adapter card Models input to 1V and 2 2V TTL low place 9921 16 or 9921 32 are used to interface between P2 and the ribbon high respectively Remove J8 to cables see Drawings 4500 788 amp 4500 789 These adapters establish reference off card mount to the back of a VME cage to provide the mating socket for Ports N 0 amp N 1 pullup voltage P2 Refer to Table 2 3 and the termination panel connection jumper When in place pulls the Jumper in diagrams 4500 790 and 4500 791 lines to 5V through the optional place On Model AVME 9480 two 50 pin ribbon cable connectors on pullup networks the front panel are used to access the 64 I O points and P4 Ports N 2 8 3 reference voltage adapter card Models 9920
17. SFAIL after power up or reset ADDRESS ASSIGNMENT Jumpers J17 and J19 are used to establish the base address for the 1Kbyte block of memory that the AVME948x will occupy in the short I O memory J17 selects the base address while J19 selects the address modifier codes An open jumper corresponds to a logic 0 state for the base address For the address modifier code an open jumper selects the Short Supervisory Access 2DH code and a jumper short will allow the card to recognize both the Short Supervisory and the Short Non Supervisory Access 29H codes Table 2 1 VMEbus Address Decode Jumper J17 Pins BASE ADDR 15 A14 A13 A12 A10 11 amp 12 10 amp 9 8 amp 7 6 amp 5 4 amp 3 2 amp 1 0000 OUT OUT OUT OUT OUT OUT 040 OUT OUT OUT OUT OUT IN OUT OUT OUT OUT IN OUT OUT OUT OUT OUT IN IN OUT ECOO N N N OUT IN IN N N N OUT OUT F400 N N N N OUT IN N N IN IN OUT N N IN IM N Consult your host CPU manual for detailed information about addressing the VMEbus short I O space A16 16 bit In many cases CPU s utilizing 24 bit addressing will start the 16 bit addressing at FF0000 Hex and 32 bit CPU s at FFFF0000 Hex N 1000 OUT OUT OUT IN OUT OUT N PORT JUMPERS AND OPT
18. XX 93151939 viva oen sin 910 0097 Guaranteed 888 88 SOURCE www artisantg com 22 Artisan Technology Group Quality Instrumentation Sowosy 91901 3 7034405 3WA INWA 93151939 0115 508 viva 3009430 O T WALIDIG 2 4304 9 N 1404 S N 1404 1404 12019 08 6 3NAV 58333 8 viva 3WA HOLVI 593181099 104100 N 4404 2 O N 4309 Guaranteed 888 88 SOURCE www artisantg com 23 Artisan Technology Group Quality Instrumentation atl 005 xoc snas 2ILYW3H2S 03414174 0956 INAY aun SEED WOXIM mtr 1504 8 JO 1 zaole 211VW3H2 LNIOd O T 03131748 YINYOWILY 119 8 257 71110 404400 401231102 NIdO 53 708 118 8 1 02 44 8 3N 7702 O 1dO SUO1VJVIWOJ H3H10 OL 439 gdv2 3440 39V1704 HSITEVLS7 OL JAOWJY 190 3784 HSITGVLSF 01 FAOWIE NOWWO2 TVLI9IG 122104d 9NIMIM 0133 L 24 Guaranteed 888 88 SOURCE www artisantg com Artisan Technology Group Quality Instrumentation Sowosy ACHIA 106 e sen
19. ad HIGH The Green LED will be ON with the Red LED OFF and SYSFAIL HIGH This indicates that the board is fully functional A t Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com AVME948x USER S MANUAL Digital Board VME Interrupter Reset Condition All interrupt inputs cleared unless the interrupt condition is still present The VME Interrupter is made up of a series of registers that control the eight I O interrupt points and the interrupt mode Refer to Interrupt Enable Register Read Write 83 the Interrupter Block Diagram Drawing 4500 740 and the memory map Table 3 1 for items referenced in the following discussion The Interrupt Enable Register provides a mask bit for each of the eight I O interrupt points A 0 in a bit position will prevent the The VME interrupter on the Digital I O card is a Release On corresponding interrupt point from causing an interrupt 1 Register Access RORA type interrupter and will return an eight bit will allow the input to cause an interrupt providing the global vector during the interrupt acknowledge cycle The RORA type interrupt enable bit is set interrupter will release the interrupt request line IRQx after the interrupt has been cleared The interrupter logic contains a Interrupt Enable Register for I O Port 0 Inputs programmable interrupt level accessible through the Interrupt Level MSB LSB Register 7 5 4 3 2
20. ained in U26 and U27 Both the Interrupt Pending and Interrupt Inputs Register are read through U13 and U14 DIGITAL I O PORT REGISTERS READ WRITE The I O Port Registers reflect and or control the state of the bidirectional I O points Points are grouped eight to a port use a point as an input first write a to it to cause the open collector output driver to go into an OFF high impedance state That lets the point be pulled to a high voltage level by an onboard pull up resistor The point may then be driven by an external device Reading the point will reflect the INVERTED level at the I O connector To use a point as an output write 1 or 0 to the point as desired If the point is read it will reflect the state of the output as well Note that because inverted logic is used a high level at the connector is read as 0 in the port register and a low level is read as a 1 This is consistent with the use of open collector outputs to drive relays and switches A logic 1 in the computer produces a low level at the output driver to pull in a relay or turn something on Input Comparators Buffers Analog voltage comparators are used as input devices to allow the inputs to withstand up to 30V see Drawing 4500 742 During normal operation REF is held at 5V which establishes a reference voltage of approximately 1 8 volts from voltage divider R23 amp R24 which appears at the inverting inputs of all the comparators
21. care of the Data Transfer Acknowledge DTACK timing and the Bus Error BERR logic The Digital I O Board will assert the BERR signal if the host CPU tries to access the card using long word read or write data transfer 057 and 043 control the DTACK timing The transfer ackowledge delay signal DDLAY is asserted when the card has been properly decoded and either of the data strobes DS1 0 0 are asserted This allows U43 to start shifting a logical 1 across its outputs The delay time is programmed by the factory through jumper J18 When DTACK is asserted it is inverted through U42 and the VME signal is asserted The VME Interrupter The VME interrupter block diagram is shown in Drawing 4500 740 Refer to the schematic and parts location Drawing 4500 737 for the items referenced in the following paragraphs The VME interrupter on the Digital I O card is a Release on Register Access RORA type interrupter and will return an eight bit vector during the interrupt acknowledge cycle The RORA type interrupter will release the interrupt request line IRQx after the interrupt has been cleared The interrupter logic contains a programmable interrupt level accessible through the Interrupt Level Register The eight interrupt points are level sensitive and work on a first come first serve basis unless the interrupts occur at the same time If two or more interrupts occur at the same time then I O interrupt poi
22. ches When sensing contact closures that already are connected to a voltage source the pullup resistor networks should be removed The input voltage should be within the range listed in the specifications For isolated or grounded contacts the pullups and the 5 volt supply can be used to establish an input voltage See Drawing 4500 743 for various input configurations 3 0 PROGRAMMING INFORMATION This section provides the specific information necessary to program the Digital I O Board MEMORY MAPS The memory for the Industrial Digital I O board a non intelligent I O architecture is shown in Table 3 1 The Digital I O board is addressable on 1Kbyte boundries in the short address space All Acromag VMEbus non intelligent slaves have a standard interface configuration which consists of a 32 byte on board ID PROM and a board status register The rest of the 1Kbyte address space contains registers or other memory specific to the function of the board All addresses are in hexadecimal The letters R and W indicate whether a register may be Read and or Written to The areas marked undefined in the memory map will read with all bits high 1 s These areas are reserved for future use For future compatibility application programs should not use these areas for any reason Artisan Technology Group Quality Instrumentation Table 3 1 AVME948x Digital I O Board Memory Base Base Hex D15 008 007 DOO Hex 00 01
23. e 1 Measured from the falling edge of DSx to the falling edge of during a normal data transfer cycle AM5 AM1 MAXIMUM INPUT FREQUENCY Minimum positive pulse width 1 4 uS Minimum negative pulse width 2 0 uS Maximum input frequency w minimum pulse widths 295 KHz Maximum input frequency with 50 duty 250 KHz DIGITAL INPUT OUTPUT NON ISOLATED Input Voltage Range Input Threshold to Input Threshold to Input Hysteresis Input Current pull up resistors Points per Output Output Voltage Range Output Current Sink Output Saturation Voltage Logic Compatibility Minimum interrupt point pulse width to guarantee recognition VME COMPLIANCE 0 0 to 30V DC 2 2V DC Nominal Adjustable 1 0V DC Nominal Adjustable 1 2 V DC Nominal 61uA at 30VDC 64 I O points Each point can be configured as an input or output Up to eight points can interrupt the VME bus Open collector with optional pull up resistor 0 to 30 V DC 100mA Max 1 1V 100mA 0 9V Typ TTL LSTTL CMOS amp Others gt 2uS Meets or exceeds all written VME Specifications per revision C 1 dated October 1985 and IEC 821 1987 Data transfer
24. fers Output latches drivers A block diagram is shown in Drawing 4500 741 Refer to the Schematic and Parts Location Drawing 4500 737 for the items referenced in the following information VMEbus INTERFACE The VMEbus Interface logic contains the logic necessary to interface the Digital I O points to the VMEbus This logic includes VME address decode logic the VME Control logic and the VME Interrupter logic The VME Address Logic The Digital I O Board interfaces with the VMEbus as non intelligent slave in the short I O address space The card will recognize two of the Address Modifer Codes the Short Supervisory Access 2DH and the Short Non Supervisory Access 29H codes Jumper J19 selects the Address Modifer Code that the card will recognize The starting address of the Digital I O Board is determined by jumpers on pins 1 12 of J17 This allows the Digital Board to reside in any one of the 64 1K blocks of the short I O address space Integrated circuit U55 compares the VME address lines A10 A15 and the Address Modifier line AM2 to Jumpers J17 and J19 If the two are equal then the EQ line is asserted 057 checks the remaining Address Modifier Lines and AS and then asserts the card enable line Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com AVME948x USER S MANUAL Digital I O Board The VME Control Logic The VME control logic takes
25. flect the state of the output as well 8 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com AVME948x USER S MANUAL Digital Board Note that because inverted logic is used a high level at the I O connector is read as a 0 in the Port Registers and a low level is read as a 1 This is consistent with the use of open collector outputs to drive relays and switches A logic 1 in the computer produces a low level at the output driver to pull in a relay and turn something ON Reset Conditions All of the I O points are set to 0 which causes the output drivers to go into an OFF high impedance state The result is that all I O points are configured as inputs INTERRUPT BEHAVOIR Several interrupt schemes are possible with the board s register architecture Some of the possibilities are Each point serviced by a separate software interrupt handler routine e A single software handler for the entire board e mix of some points causing interrupts some polled Two different interrupt release methods are described in the VME System Architecture They are Release On Register Access RORA and Release On Acknowledge ROAK The architecture of this board follows the RORA method This means that an interrupt request is removed from the bus when the associated interrupt point has been cleared This method is necessary to allow several interrupts to be serviced w
26. individually programmed as inputs or outputs Additionally eight of these 64 I O lines may be configured to generate VMEbus interrupts This manual covers two models of Digital I O Boards Table 1 1 below lists these model numbers and their major differences Table 1 1 Model Numbers INTERFACE FRONT PANEL REAR MODEL NO POINTS ACCESS ACCESS AVME 9480 64 I O P3 P4 9481 64l0 j P2 KEY FEATURES OF MODEL AVME948x I O BOARDS High Channel Count Provides up to 64 programmable I O points lines configured as eight 8 bit ports or four 16 bit ports Output Readback The state of output points can read e High Sink Capability Outputs may sink up to 100mA at voltages up to 30V Output Protection Built in protection diodes for driving inductive loads Wide Input Range Input range of 0 to 30V Wide Input Hysteresis Input hysteresis is included Adjustable Input Threshold Input threshold is adjustable Termination Panel Solid State Relay Interface Compatible with industry standard solid state relays and termination panels PB16 and PB32 TTL CMOS TTL and CMOS compatible Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com AVME948x USER S MANUAL Digital Board Optional Termination Panel Optional universal termination panel available for use with contact closures relays and incandescent lamps Byte
27. ith a single handler if so desired Interrupt Example The following example outlines the steps taken to initialize the board to cause interrupts 1 Clear the global interrupt enable bit in the Status Control Resister 2 Write the interrupt level into the Interrupt Level Register 3 Write vector s into the Vector Registers 4 Write proper patterns to establish the interrupt level into the Interrupt Input Polarity Register 5 Write all 1 s into the Interrupt Clear Register to reset interrupt inputs 6 Write 1 s into the Interrupt Enable Register to enable individual interrupts 7 Write a 1 into the global interrupt enable bit of the Status Control Register Interrupts may now occur from the board When the board asserts an interrupt the following action takes place 1 The host processor asserts IACK and a level of the interrupt it is seeking and if the level matches the board s the board puts vector out on the data bus lines 00 07 The original interrupt request from the board remains asserted 2 The host processor uses the vector to determine the software interrupt handler to execute and then executes it For a single handler per point scheme the handler writes to the proper bit in the Interrupt Clear register to remove the interrupt request This also clears its interrupt pending flag and interrupt input flag If other points have interrupts pending another interrupt request is asserted or j
28. nt 7 has the highest priority with I O interrupt point 0 having the lowest priority Each interrupting point may be programmed with its own interrupt vector Also each interrupt point may be individually masked and the polarity may be selected The Interrupt Vector Register is contained in U30 U15 is the Interrupt Enable Register The Enable Register is read through U9 and U10 U28 is the Interrupt Polarity Register When the interrupt inputs sense the proper level on one of the I O interrupt points of Port 0 the interrupter logic will assert the pre programmed interrupt request level IRQ7 IRQ1 and then monitor the Interrupt Acknowledge Input IACKIN line When the IACKIN is asserted the logic compares the VME address lines A1 A2 and to the pre programmed interrupt level If the lines are not equal it will pass the signal along by asserting IACKOUT If the lines are equal it will then drive the data bus with the vector associated with the I O interrupting point and assert the DTACK signal 053 controls the interrupt request level decoding 061 contains the Interrupt Level Register and controls all VME interrupt interface signals U25 senses an incoming interrupt request from the I O interrupt point s enables U53 selects the proper address for the interrupt vector RAM and will give priority to simultaneous interrupt requests The Interrupt Pending Register is U11 and U12 The Interrupt Inputs Register is cont
29. ontained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Table of Contents 1 0 GENERAL KEY FEATURES OF MODEL AVME948x I O BOARDS VMEbus INTERFACE 5 2 0 PREPARATION FOR UNPACKING AND INSPECTION CARD CAGE CONSIDERATIONS BOARD CONFIGURATION ss Default Jumper Configuration sess ADDRESS 8 0 PORT JUMPERS AND OPTIONS Input Threshold Adjustment CONNECTIONS 2 BACKPLANE USE WITH SOLID STATE Configuring The AVME948x Configuring The 16 USE WITH OTHER DEVICES E Relays And Other Inductive Con
30. or Word Interchange Byte or word data transfers Built in ID On board identification PROM included Port 0 Interrupt Handling Port 0 may be used for handshaking mode with both flag and interrupt capability e Status Indicators Pass Fail status indicators on front panel Front or Back I O Access I O points are accessible through the front panel or out of the back of the card cage VMEbus INTERFACE FEATURES Slave Module Slave Module 16 D16 D08 E0 Release On Register Access Interrupts 008 0 type Interrupter Single Multiple Input Vectors Single or Multiple Interrupt Vectors Short Addressable Responds to short address modifier codes 29H 2DH a capital H suffix indicates a hexadecimal number Low Memory Consumption Board occupies 1K bytes of memory space jumper selectable ID PROM Board Identification PROM installed 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain ret
31. rious registers is determined in the discussion of each of the registers NOTE If a reset is performed when interrupts are enabled then in order to completely reset the AVME948x it is necessary to perform two Software resets with a delay of at least 2 microseconds between them This is to prevent a spurious interrupt being caused by the latency of the actual field output being read back at a later time by the input circuit Bit3 Global Global Interrupt Enable R W writing a 1 to Interrupt this bit enables interrupts to occur from the NEED I 4 __ 0 D 4 4t Manufacturer ID Acromag HUC EUM Ear rou Bit4 Software Software Reset W Writing a 1 to this bit 9480 0 prevents interrupts Number of Kbytes R W Reset Condition Set to O all interrupts of Address Space disabled Used If equal 0 Bit2 Global Global Interrupt Pending R this bit will be a then Address Interrupt 1 when there is an interrupt pending from any Space is indicated Pending of the interrupt inputs This bit will be 0 at byte 29H R when there are no interrupts pending Reset condition Set to 0 no interrupts pending Bit 1 Green LED R W when written this bit will control the state of the green LED on the front panel A 1 will turn it on will turn it off Reading it will reflect its current state Reset Condi
32. same interrupt points prior to the point where they are masked by the In this case the handler will have to determine the interrupting point Interrupt Enable register This allows the level detecting circuitry by examining the Interrupt Pending Register for some inputs to be used in a polled or non interrupt mode while 1 others operate in an interrupt mode 1 in a bit position indicates Reset Condition Registers unaffected the input went through the transition defined by the Interrupt Input Polarity Register A write to the corresponding Interrupt Clear Digital Port Registers Read Write 100 107 Register bit will clear the interrupt input flag if the input level has been negated If the input level has not been negated then the The Port Registers reflect and or control the state of the interrupt input flag will remain set bidirectional I O points Points are grouped 8 to a port To use a point as an input first write a O to it to cause the output driver to go Interrupt Inputs Register for I O Port 0 Inputs into an OFF high impedance state That lets the point be pulled to MSB LSB a high voltage level by an onboard pull up resistor The point may then be driven by an external device Reading the point will reflect the INVERTED level the I O connector To use point as an output write the desired 1 or 0 to the point If the point is read it 7 6 5 4 3 2 1 0 will re
33. t 1 in a bit position means that an interrupt will occur when the I O been negated then the individual point must be masked or the interrupt point is high A 0 in a bit position means that an interrupt interrupt level must be changed in the Interrupt Input Polarity will occur when the I O interrupt point is low Register and then a 1 written to its bit position in the Interrupt Pending Clear Register This is the only way to clear interrupts Interrupt Input Polarity Register for I O Port 0 Inputs from the board This is known as the Release on Register Access MSB LSB RORA method as defined in the VME System Architecture 7 5 4 3 2 1 0 Point Point Point Point Point Point Point Point Interrupt Pending Clear Register for I O Port 0 Inputs 7 6 5 4 3 2 1 0 21410 7 5 4 3 2 1 0 Reset Condition All inputs will cause interrupts when I O Interrupt Point Point Point Point Point Point Point Point Point is low 7 6 5 4 3 2 1 0 Interrupt Vector Registers Read Write Odd Bytes from 86 95 Reset Condition All interrupts cleared The Interrupt Vector Registers maintain the interrupt vectors for Interrupt Inputs Register Read 82 each of the eight I O interrupt lines This allows each I O interrupt line to be serviced by its own software handler A single software The Interrupt Inputs Register provides the status of the eight handler can be used by simply making all of the vectors the
34. tact Closures and Switches 3 0 PROGRAMMING INFORMATION MEMORY 5 Board Identification PROM s Status Control Register sss VME Interr pter coordina Interrupt Pending Clear Register Interrupt Inputs Register Interrupt Enable Register Interrupt Level Interrupt Input Polarity Interrupt Vector Registers Port Registers INTERRUPT BEHAVIOR m Interrupt Example eene 016 iiec 4 0 THEORY OF OPERATION VMEbus INTERFACE The VME Address Logic 2 The VME Control The VME InterrUpt r sess DIGITAL I O PORT REGISTERS Input Comparators Buffers Output Latches Drivers 5 0 SERVICE AND REPAIR INFORMATION SERVICE AND REPAIR 55 5 PRELIMINARY SERVICE PROCEDURE CALIBRATION PROCEDURE REPLACEABLE PARTS 6 0 SPECIFICATIONS sx DRAWINGS Page 4500 981 Jumper 12 4500 788 9921 16 Digital I O Adapter Card 13 4500 789 9921 32 Digital I O Adapter
35. the factory and should not be reprogrammed by the user SYSFAIL Jumper This asserts SYSFAIL after power up or reset Place J9 J16 are used only in cases where it is absolutely necessary to have outputs disabled through the hardware See Programming Considerations Section 3 for instruction on software enabling disabling of outputs Input Threshold Adjustment Different input thresholds may be established by connecting REF to a voltage other than 5V When this is done the input hysteresis still remains at approximately 1 2 volts The new high and low thresholds are defined by the following equations GND 0 448 x REF 1 22 REF Ports 2 amp 3 84 8 0 448 x REF 0 025 Pullup Ports 2 amp 3 BS 6 2 75 lt REF lt 27 5 Volts Protect Ports 2 amp 3 4 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com AVME948x USER S MANUAL Digital Board Table 2 3B I O Connectors P2 amp P4 Functions P2Pin P4Pin REFPots6 amp 7 C4 8 687 6 BACKPLANE REQUIREMENTS The AVME9480 is electrically and mechanically compatible with the VMEbus Specification The backplane connection is made through the 96 pin DIN 41612 connector labeled P1 The signals used are listed in Table 2 4 Artisan Technology Group Quality Instrumentation gt Table 2 4 Backplane Connector 1
36. tion Set to 0 LED off BitO Red LED Red LED R W when written this bit will Undefined Reserved R W control the state of the red LED on the front panel A 1 will turn it off a O will turn it on Reading it will reflect its current state Reset Condition Will read a 0 LED lit and Status Control Register Read Write 81 SYSFAIL is set low The Status Control Register reflects and controls functions 1 globally on the card The status register bits 1 and 0 along with the Green and Red LED S provide the user with a means of keeping track of a card s MSB LSB functionality in the system Since there is no intelligence on the 1201 board the host computer controls these bits The following is one possible use of these bits in the status register and the LED s on the Rst Int Int LED LED Enable Pending On power up the bits in the status register will read low with the Green LED OFF the Red LED ON and SYSFAIL LOW This The bits of the Status Control Register have the following indicates that the board has failed or that it hasn t been tested yet function The Status Register Bit 1 reads LOW and Bit 0 reads HIGH The LED s will both be OFF and SYSFAIL HIGH This indicates an inactive board The Status Register Bit 1 reads HIGH and Bit 0 reads LOW The LED s will both be ON and SYSFAIL LOW This indicates that the board is undergoing a diagnostic checkout The Status Register Bits 1 and 0 re
37. ts and repair services are available from Acromag If repair is deemed necessary for this circuitry it is highly recommended that the board be returned to Acromag for repair and recalibration Information on ordering replacement parts is shown below Table 5 1 AVME 948x Replacement Parts ACROMAG REFERENCE PART NO DESCRIPTION 6 0 SPECIFICATIONS The following specifications apply at 25 C ambient temperature and nominal power supply values unless otherwise noted AMBIENT TEMPERATURE RANGES Operating Temperature 0 to 70 C Storage 25 to 85 C PHYSICAL DIMENSIONS Length etnies 233mm Width iini ee 160mm Board Thickness 1 6mm Maximum Component Height 13 9mm CONNECTORS B2 IEC Type 603 2 C096MX XXX or equivalent PO 50 Pin Header Connector Right Angle Amp 1 499919 0 or equivalent POWER REQUIREMENTS 5 Volts 4 875 to 5 25V DC at 1 6A Typical Board Logic only Does not include additional current for output loads VMEbus Loading Current Input LOW Input HIGH AM2 A15 A10 LWORD A9 A6 IACKIN 0 25 mA A1 051 050 WRITE 015 00 100 uA VMEbus Drive Current Output LOW Output HIGH BERR SYSFAIL MEME Typical VMEbus Access Time lt 59005 typical Not
38. urn instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment It is recommended that the board be visually inspected for evidence of mishandling prior to applying power v CAUTION SENSITIVE ELECTRONIC DEVICES The board utilizes static sensitive DO NOT SHIP OR STORE NEAR STRONG components and should only be handled at ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS a static safe workstation CARD CAGE CONSIDERATIONS Refer to the electrical specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the board within the voltage tolerances specified BOARD CONFIGURATION This Digital Board may be configured in a variety of ways for many different applications Each possible jumper setting will be discussed in the following sections The jumper locations are shown in Drawing 4500 981 at the back of this manual Default Jumper Configuration A board is shipped from the factory configured as follows VMEbus Short I O Address of 0000 Set respond to both address modifiers 2DH and 29H All of the ports have the reference and pullup resistors connected to 5 Volts Board will assert SY
39. ust remains and upon returning from the handler another interrupt cycle is started 3 If asoftware handler is used to handle several points it could service them at the same time that it services the original interrupt by examining the Interrupt Pending Register to determine what other interrupts need servicing Service of Interrupts The following examples outline the steps necessary to service an interrupt from the AVME948x Example A 1 Disable the interrupt point s by writing a zero to the individual bit s in the Interrupt Enable Register 2 Clear the interrupt point s by writing a one to the individual bit s in the Interrupt Pending Clear Register 3 Then reenable the interrupt point s by writing a one to the individual bit s in the Interrupt Enable Register Example B 1 Clear the Global Interrupt Enable bit in the Status Register 2 Clear the Interrupt point s by writing a one to the individual bit s in the Interrupt Pending Clear Register 3 Then reenable the Global Interrupt Enable bit in the Status Register The interrupt input stimulus must be removed before the interrupt can be cleared 4 0 THEORY OF OPERATION This section provides a functional description of the AVME948x Digital Board which consists of the following functional blocks VME address decode VME control logic Digital map decode logic Identification PROM Status register VME interrupter Input comparators buf

Acromag AVME948x Series Manual

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