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logiSPI SPI to AXI4 Controller Bridge Xylon d.o.o. Features

1. Tris Designed by XYLON logiSPI SPI to AXI4 Controller Bridge September 3 2014 Xylon d o o Fallerovo setaliste 22 10000 Zagreb Croatia Phone 3851 368 00 26 Fax 385 1 365 51 67 E mail support logicbricks com URL www logicbricks com Features e Supports Xilinx Zynq 7000 All Programmable SoC and all Xilinx FPGA families Data Sheet Version v3 01 Core Facts Provided with Core Documentation User s Manual Design File Formats Encrypted VHDL Constraints Files Contact Xylon Support for Application Notes information on Reference Designs Additional Items logiCRAFT CC evaluation board Simulation Tool Used Reference Designs amp e Bridge controller between the Serial Peripheral Interface SPI bus and the Advanced eXtensible Interface AX14 on chip bus e Works as a Slave controller on the SPI bus anda master controller on the ARM AMBA AXI4 bus e Enables full duplex communication MSB first between an external SPI Master controller and SoC FPGA peripherals on chip and off chip memories e Supports SPI telegrams of different lengths single transfers or burst transfers up to 2 kB back to back e Supports four signals interface SI SO SCLK and SCS_N e Provides transfer status signals SPI telegrams acknowledgment and Slave reset mechanisms e Supports SCLK frequency of up to fox 4 where fak is frequency of the system clock AXI4 clock e Supports all SPI clock polarity CP
2. that expand the capabilities of the embedded host processor by adding missing host features and by offloading high speed processing tasks The IP core works as a SPI Slave bus controller and a 32 bit master controller on the AMBA Advanced eXtensible Interface AXI4 on chip bus The SPI is a full duplex synchronous and a four wire serial interface between a single bus master and one or more bus slave devices The bus master initiates communication by asserting slave s select signal and issuing a data frame SPI telegram Data is exchanged between the master and the selected slave device shift registers which shift data bits synchronous on SPI clock signal generated by the master device The logiSPI IP core accepts the SPI telegram sent by the SPI master de serializes it decodes SPI Master s commands and writes reads data to from Xilinx Zyng 7000 SoC or FPGA peripherals and on chip memories interconnected with a high speed 32 bit AXI4 on chip bus By mean of SoC FPGA memory controllers the logiSPI can relay large bursts of data up to 2 kBytes between the SPI master device and SDRAM type memories connected to the Xilinx Zyng 7000 SoC or FPGA device The logiSPI SPI to AXI4 Controller Bridge IP core implements an acknowledgment mechanism that assures integrity of data exchanged through the SPI bus Properly decoded SPI telegrams are acknowledged by the command code bounced back to the SPI master and the faulty telegrams are discarded By asserti
3. 4 bus and the serial SPI bus SFRs SFRs Module contains Special Function Registers of the logiSPI IP core Those registers are accessible only via SPI interface Core Modifications The core is supplied in an encrypted VHDL format compatible with Xilinx Vivado IP Integrator and ISE Platform Studio logiSP has configuration parameters that are selectable prior to VHDL synthesis and the following table presents a selection from a list of available parameters Table 3 logiSPI VHDL Configuration Parameters C_SPI _MODE SPI communication mode selection CPOL CPHA C BURST WIDTH Maximum number of AXI4 data transfers per burst If you wish to adopt the logiSPI IP core to your specific needs and or supplement the features set you can allow us to tailor the logiSPI to your requirements Core I O Signals The core signals I O have not been fixed to any specific device pins to provide flexibility for interfacing with user logic Descriptions of all I O signals are provided in Table 3 Table 4 Core I O Signals Signal ae Signal a Description Direction Common signals clk Input System clock AXI4 clock System bus interface AXI4 Master Interface Bus Refer to ARM s AMBA AXI4 protocol specification sclk Input SPI serial clock scs_n Input SPI slave select SPI serial input MOSI SPI serial output MISO input signal SPI serial output MISO output signal SPI serial output MISO three state control si
4. OL and phase CPHA combinations e Prepared for Xilinx Vivado and ISE Design Suits ModelTech s Modelsim Support provided by Xylon Applications e Inter chip board level communications i e external MCU controlling FPGA co processor Table 1 Example Implementation Statistics for Xilinx FPGAs Family Fmax MHz Fmax MHz Slices MULT DCM Design Device M_AXI_ACLK clk FFs LUTs DSP48 E CMT oe Tools ISE 1779 152 4 435 729 Spartan 6 XC6SLX45T 3 N A Kintex 7 XC7K70T 2 278 Artix 7 er 264 ji XC7A200T 3 428 703 278 1779 152 4 431 706 Zynq 243 1555 156 4 XC7Z020 1 as 437 650 Notes 1 Assuming 32 bit AXI4 master interface 2 Assuming only SPI signals are routed off chip other signals are connected internally Copyright Xylon d o o 2001 2014 All Rights Reserved Page 1 of 6 logiSPI SPI to AXI4 Controller Bridge Data Sheet Version v3 01 SCS_N SCLK SI SO SPI Interface Read and Write Ala Module Controller Interface Module Write _done Read_done lt 4 Figure 1 logiSPI Architecture General Description The logiSPI SPI to AXI4 Controller Bridge IP core allows external host processors to communicate with peripherals or processors implemented in Xilinx Zyng 7000 All Programmable SoC and FPGAs through the Serial Peripheral Interface SPI serial bus In enables easy implementations of Xilinx FPGA SoC companion chips
5. additional information Email sales logicbricks com URL www logicbricks com This publication has been carefully checked for accuracy However Xylon does not assume any responsibility for the contents or use of any product described herein Xylon reserves the right to make any changes to product without further notice Our customers should ensure that they take appropriate action so that their use of our products does not infringe upon any patents Xylon products are not intended for use in the life support applications Use of the Xylon products in such appliances is prohibited without written Xylon approval Related Information Xilinx Programmable Logic For information on Xilinx programmable logic or development system software contact your local Xilinx sales office or Xilinx Inc 2100 Logic Drive San Jose CA 95124 Phone 1 408 559 7778 Fax 1 408 559 7114 URL www xilinx com Copyright Xylon d o o 2001 2014 All Rights Reserved Page 5 of 6 logiSPI SPI to AXI4 Controller Bridge Data Sheet Version v3 01 Revision History Version pate Note U O f200 18 04 2012 Initial Xylon release 03 09 2014 Update to AXI4 Support for Xilinx Vivado Design Suite Copyright Xylon d o o 2001 2014 All Rights Reserved Page 6 of 6
6. ecks incomming SPI telegram de codes the SPI command and issues proper write or read operation to the SFRs Module or the AXI4 Interface module 4 bits 12 bits variable 8 16 32 bits SPI_CMD SPI_LADDR SPI_DATA Figure 2 SPI telegram structure for single transfers e SPI_CMD SPI command single transfer SPI_ADDR SPI address 12 lowest bits of target AXl4 bus address the upper address bits defined by the SFR register e SPI_DATA SPI data bytes to write to read from target system address 4 bits 1 bit 11 bits 32 bits variable SPI_BURST_L 1 x 8 bits SPI_CMD R SPI_BURST_L SPI_ADDR SPI_DATA Figure 3 SPI telegram structure for burst transfers e SPI CMD WR_BURST RD_BURST command burst transfer e SPI_ADDR SPI address complete 32 bit system address e SPI_DATA SPI data bytes to write to read from target system address e R reserved e SPI_BURST_L burst length in number of bytes 0 2047 Copyright Xylon d o o 2001 2014 All Rights Reserved Page 3 of 6 logiSPI SPI to AXI4 Controller Bridge Data Sheet Version v3 01 AXI4 Interface Module The AXI4 Interface Module translates the decoded read and write commands from the Read and Write Controller into properly formatted AMBA AXI4 bus transfers and vice versa the AXI4 bus transfers into SPI formatted telegrams The module contains write and read address data FIFOs to compensate different data speeds on the parallel AXI
7. gnal read_done Output Requested read data available on output port write_done Output Data successfully written to target system address Copyright Xylon d o o 2001 2014 All Rights Reserved Page 4 of 6 logiSPI SPI to AXI4 Controller Bridge Data Sheet Version v3 01 Verification Methods The logiSPI is fully supported by the Xilinx Vivado and ISE Design Suits This tight integration tremendously shortens IP integration and verification A full logiSPI implementation does not require any particular skills beyond general Xilinx tools knowledge Recommended Design Experience The user should have experience in the following areas Xilinx design tools ModelSim Available Support Products Xylon logicBRICKS IP cores can be evaluated on logiCRAFT CC Xylon development platform which is designed especially for developers working in the fields of multimedia and infotainment This platform demonstrates modularity on all levels software board FPGA and IP cores The platform makes excellent development tool particularly appropriate for the development of embedded systems with strong graphics capabilities To learn more about the Xylon development platforms contact Xylon or visit the web Email support logicbricks com URL www logicbricks com Ordering Information This product is available directly from Xylon under the terms of the Xylon s IP License Please visit our web shop or contact Xylon for pricing and
8. ng and de asserting the slave select signal the SPI master can reset the logiSPI IP core s operation The following table shows SPI Master commands currently supported by the logiSPI IP core Copyright Xylon d o o 2001 2014 All Rights Reserved Page 2 of 6 logiSPI SPI to AXI4 Controller Bridge Data Sheet Version v3 01 Single transfer 8 bit read Single transfer 16 bit read Single transfer 32 bit read SFR access read Special Function Register internal logiSPI register Burst transfer read specified number of data bytes WR_8 Single transfer 8 bit write WR_16 Single transfer 16 bit write WR_32 Single transfer 32 bit write SFR access write to Special Function Register internal logiSPI register WR_BURST Burst transfer write specified number of data bytes Table 2 logiSPI supported SPI commands Functional Description The Figure 1 represents internal logiSPI architecture The logiSPI functional blocks are SPI Interface Module Read and Write Controller AXI4 Interface Module and SFRs Module SPI Interface Module The logiSPI front end part implements a state machine that receives SPI telegrams from a SPI master and controls shifting in and shifting out of serial data in a full duplex mode Serial data on the SPI bus is shifted MSB first The SO MISO Serial Output is a tristate output to enable use in the SPI bus with multiple slaves Read and Write Controller Read and Write Controller ch

logiSPI SPI to AXI4 Controller Bridge Xylon d.o.o. Features

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