PCI9622 User`s Manual
Contents
1. vim lui nfn ls A amp Li O CW i LSB 2 LSE mA CLE GATE OUT FI ich i 0 FF FF 0 0 d FF FE 4 3 Figure 7 2 Mode 1 BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 25 PCI9622 Data Acquisition V6 022 MODE 2 Rate Generator This Mode functions like a divide bv N counter It is typically used to generate a Real Time Clock interrupt OUT will initially be high When the initial count has decremented to 1 OUT goes low for on CLK pulse OUT then goes high again the Counter reloads the initial count and the process is repeated Mode 2 is periodic the same sequence is repeated indefinitely For an initial count of N the sequence repeats every N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low during an output pulse OUT is set high immediately A trigger reloads the Counter with the initial count on the next CLK pulse OUT goes low N CLK pulses after the trigger Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse OUT goes low N CLK Pulses after the initial count is written This allows the Counter to be synchronized by software also Writing a new count while counting does not affect the current counting sequence If a trigger is received after writing a new count but before the end of the current period the Counter will be loaded with the new2. AGND DGND Figure 4 5 clock input output and trigger signal connection 4 4 Multiple Instrument Synchronization Three methods can realize the synchronization for the PC19622 the first method is using the cascade master slave card the second one is using the common external trigger and the last one 1s using the common external clock When using master slave cascade card programs the master card generally uses the internal clock source model while the slave card uses the external clock source mode After the master card and the slave card are initialized according to the corresponding clock source mode At first start all the slave cards as the main card has not been activated and there is no output clock signal so the slave card enters the wait state until the main card was activated At this moment the multi card synchronization has been realized When you need to sample more than channels of a card you could consider using the multi card cascaded model to expand the number of channels PCI9622 Data Acquisition V6 022 Master Card CLKIN Slave Card 1 LKI j ra Slave Card 2 When using the common external trigger please make sure all parameters of different PCI9622 are the same At first CLKOUT I configure hardware parameters and use analog or digital signal triggering ATR or DTR then connect the signal that will be sampled by PCI9622 input triggering signal from
3. PCI9622 User s Manual g Beijing ART Technologv Development Co Ltd PCI9622 Data Acquisition V6 022 Contents CO Sa d d TA l 2 CNPT L VEIT La 3 Chapter 2 Components Layout Diagram and a Brief Description ss ssessssnnnnnnnnnnnnnnnnzznnnnnnzzznnzzzzzzntenznznzzzzzznannnzznnnzzana 5 2 1 The Main Components Layout Di tatt is iswi tatu taa ia kai i Era EEN n EAEEREN ETRE EEEREN ERE E EEEE REN EREE Era ESE 5 2 2 The Function Description for the Main Component cccccccccesesseseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 5 2 2 1 Signal Input and Output Connectors ccccccccccessceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeeseeeeeeseeeeeeeeeeeeeeeeees 5 2 2 2 ey Sal 100 TIE Sy VOM A E AA I E A ees anes ee ees ana aaa OA E 5 PAPA EEO MGC AG OM a A 6 Chopremo sa mal CONC OD Sis i a tersessucctectiatia dap c bons aod cna ese Te Bo asec Bond eatna Lat dott 7 3 1 The Definition of Signal Input and Output Connectors L ssseeennnnnennnnnnnnnnnnnnnnnnnznznnznnznznnnnzzanananannnzananznnnnnnnnnza 7 3 2 The Definition of Digital Signal Input Connectors 0 ss seeeeeennnnnznnnnnznnnenmnnznnznnznnznnznnnnnnnn na nara nanna nanna nanna 8 3 3 The Definition of Digital Signal Output Connectors L ss sseeeeeennnnnnnnnnnnnnnnnannnnnnnennnn anna nanna nanna nanna 9 Chapter 4 Connection Ways for Each Signal nn A aa AAEEAAAA AME A EEA ANA AEEE EMB MM MEEKMNE
4. A GATE transition should not occur one clock prior to terminal count MODE 4 Software triggered strobe OUT will be initially high When the initial count expires OUT will go low for one CLK pulse and then go high again The counting sequence is triggered by writing the initial count GATF I enables counting GATE 0 disables counting GATE has no effect on OUT After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after the initial count is written If a new count is written during counting if will be loaded on the next CLK pulse and counting will continue from the new count If a two byte count is written the following happens 1 Writing the first byte has no effect on counting 2 Writing the second byte allows the new count to be loaded on the next CLK pulse BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 28 PCI9622 Data Acquisition V6 022 This allows the sequence to be retriggered by software OUT strobe low N 1 CLK pulses after the new count of N is written CW 18 LSB 3 0 l g O FF FF FF 1 0 FF FE FD CW 18 LSB 3 ai Nr o GATE INA JNTTTI AT o o o o o o amp fw tw twin 3 3 MEIEREI CW 16 LSB 3 LSB GATE OUT 2 1 Figure 7 5 Mode 4 MODE 5 Hardware triggered strobe OUT will in
5. ART pin or DTR pin then click Start Sampling button at this time PCI9622 does not sample any signal but waits for external trigger signal When each module is waiting for external trigger signal use the common external trigger signal to startup modules at last we can realize synchronization data acquisition in this way See the following figure External Trigger Signal ATR DTR PCI9622 ATR DTR PCI9622 lili ATR DTR PCI9622 When using the common external clock trigger please make sure all parameters of different PCI9622 are the same At first configure hardware parameters and use external clock then connect the signal that will be sampled bv PC19622 input trigger signal from ART pin or DTR pin then click Start Sampling button at this time PCI9622 does not sample any signal but wait for external clock signal When each module is waiting for external clock signal use the common external clock signal to startup modules at last we realize synchronization data acquisition in this way See the following figure External clock signal CLKIN PCI9622 i PCI9622 PCI9622 12 PCI9622 Data Acquisition V6 022 Chapter 5 The Instruction of the AD Trigger Function 5 1 AD Internal Trigger Mode When AD is in the initialization if the AD hardware parameter ADPara TriggerMode PCI9622_ TRIGMODE SOFT we can achieve the internal trigger acquisition In this function when calling
6. a fixed frequency external clock Group Cycle external clock cycle External signal cycle cycle signal points Loops of group x Group Cycle External signal frequency 1 external signal cycle Formula Notes The internal sampling clock cycle 1 AD Para Frequency The total number of sampling channels AD Para Last Channel AD Para First Channel 1 Loops of group ADPara LoopsOfGroup AD Chips conversion time see AD Analog Input Function parameter Group Interval AD Para Group Interval Signal Cycle Points with the display of the waveform signal in test procedures we can use the mouse to measure the signal cycle points Under the internal clock mode for example sample two channel 0 1 and then 0 and 1 become a group Sampling frequency Frequency 100000Hz cycle is 10us Loops of group is 1 Group Interval 50us then the acquisition process is to collect a set of data first including a data of channel 0 and a data of channel 1 We need 10us to sample the two data 20us to convert the data from the two channels After the conversion time of an AD chip AD will automatically cut off to enter into the waiting state until the 50us group interval ends We start the next group begin to convert the data of channel 0 and 1 and then enter into the waiting state again and the conversion is going on in this way as the diagram following shows Start Enabled en Convert Pulse lal lal lal Z bic ai d a
7. count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current counting cycle In mode2 a COUNT of 1 I illegal CW 14 L5B i3 a a a GATE OUT slelitalelsla w ufu ln pM N NN 3 GWmla LSB 3 GATE CW 14 LSB 4 L5 5 GATE OUT LJ o oO oO oO FY Oo IR KO A odessa dele des Figure 7 3 Mode 2 Note A GATE transition should not occur one clock prior to terminal count BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 26 PCI9622 Data Acquisition V6 022 MODE 3 Square wave mode Mode 3 is typically used for Baud rate generation Mode 3 is similar to Mode 2 except for the duty cycle of OUT OUT will initially be high When half the initial count has expired OUT goes low for mainder of the count Mode 3 is periodic the sequence above is repeated indefinitely An initial count of N results in a square wave with a period of N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low while OUT is low OUT is set high immediately no CLK pulse is required A trigger reloads the Counter with the initial count on the next CLK pulse Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This allows the Counter to be synchronized by software also Writing a new count
8. for example when sampling data of two channel 0 1 then channel 0 and channel consist of a group Sampling frequency Frequency 100000Hz the cycle is 10us Loops of group is 2 then the acquisition process 1s to collect the first set of data including two data of channel 0 and two data of channel 1 the order of conversion 0 1 0 1 We need 10us to sample the four data and 40us to convert of the four data After the conversion time of an AD chip AD will automatically stop to enter into the waiting state until the next edge of the external clock triggers AD to do the next acquisition and the conversion is going on in this way as the diagram following shows Start Enabled External Clock er Convert Pulse The external clock before the start pulse is ignored Figure 6 3 Grouping sampling under the fixed frequency external clock mode PCI9622 Data Acquisition V6 022 Notes a internal clock sample cycle b AD chips conversion time d group cycle external clock cycle Under an unfixed frequency external clock mode for example the grouping sampling principle is the same as that of the fixed frequency external clock mode Under this mode users can control any channel and any number of data Users will connect the control signals with the clock input of the card CLKIN set the sampling channels and Loops of group When there are external clock signals it will sample the data which is set by use
9. guarantee card Users must keep quality guarantee card carefully if the products have some problems and need repairing please send products together with quality guarantee card to ART we will provide good after sale service and solve the problem as quickly as we can When using PCI9622 in order to prevent the IC chip from electrostatic harm please do not touch IC chip in the front panel of PCI9622 module 8 2 Warranty Policy Thank you for choosing ART To understand your rights and enjoy all the after sales services we offer please read the following carefully 1 Before using ART s products please read the user manual and follow the instructions exactly When sending in damaged products for repair please attach an RMA application form which can be downloaded from www art control com 2 All ART products come with a limited two year warranty gt The warranty period starts on the day the product is shipped from ART s factory gt For products containing storage devices hard drives flash cards etc please back up your data before sending them for repair ART is not responsible for any loss of data gt Please ensure the use of properly licensed software with our systems ART does not condone the use of pirated software and will not service systems using such software ART will not be held legally responsible for products shipped with unlicensed software installed by the user 3 Our repair service is not covered by ART s g
10. in the progress of the hardware configuration and software programming The following four place numbers are expressed by the binary system When DIP switch points to ON that means 1 and when it points to the other side that means 0 As they are shown in the following diagrams place ID3 is the high bit IDO is the low bit and the black part in the diagram represents the location of the switch Test software of the company often uses the logic ID management BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 5 PCI9622 Data Acquisition V6 022 equipments and at this moment the physical ID DIP switch is invalid If you want to use more than one kind of the equipments in one and the same system at the same time please use the physical ID as much as possible ID3 ID2 IDI IDO 4 3 2 1 ON The above chart shows 1111 so it means that the physical ID is 15 ID3 ID2 IDI IDO 4 3 2 1 ON The above chart shows 0111 so it means that the physical ID is 7 ID3 ID2 IDI IDO 4 3 2 l ON The above chart shows 0101 so it means that the physical ID is 5 o ooo Caua as oo A c 2 2 4 Status indicator EF FIFO non empty indicator on for non empty FF FIFO overflow indicator on for overflow HF FIFO half full indicator on for half full PCI9622 Data Acquisition V6 022 Chapter 3 Signal Connectors 3 1 The Definition of Signal Input and Output Conne
11. that the acquisition will occur if the exoteric signal changes 2 Triggering level function Level trigger is to capture the condition that trigger signal is higher or lower than the trigger level to trigger AD conversion When ADPara TriggerType PCI9622 TRIGTYPE PULSE it is level trigger type When ADPara TriggerDir PCI9622 TRIGDIR NEGATIVE AD is in the conversion process if the ATR is lower than the trigger level And AD conversion will automatically stop if the ATR is higher than the trigger level AD s work status changes with changes of ATR BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 14 PCI9622 Data Acquisition V6 022 AD Start Pulse AD Working Pulse Analog Trigger Signal pm JA AU A The waiting time _ Mm S l The falling edge before i The low level after the AD APPET TM OI OTT XX TO TOTO OTT OTC OC OI i the AD started is invalid i i i started is valid PAN tessssesesssesesssssesesessnsenss ness et Sesssrssssssssssassessesassrss sse Figure 5 4 Low Level Trigger When ADPara TriggerDir PC19622 TRIGDIR POSITIVE AD is in the conversion process if the ATR is higher than the trigger level And AD conversion will automatically stop if the ATR is lower than the trigger level AD s work status changes with changes of ATR When ADPara TriggerDir PCI9622 TRIGDIR POSIT NEGAT it means the trigger level is low The effect is the same as the internal software trigger 5
12. the StartDeviceProAD function it will generate AD start pulse AD immediately access to the conversion process and not wait for the conditions of any other external hardware It also can be interpreted as the software trigger As for the specific process please see the figure below the cycle of the AD work pulse is decided by the sampling frequency AD Start Pulse OO The first working pulse after the AD start pulse Figure 5 1 Internal Trigger Mode tesessssssssssesssesassesssn ss sense 5 2 AD External Trigger Mode When AD is in the initialization if the AD hardware parameter ADPara TriggerMode PC19622 TRIGMODE POST we can achieve the external trigger acquisition In this function when calling the StartDeviceProAD function AD will not immediately access to the conversion process but wait for the external trigger source signals accord with the condition then start converting the data It also can be interpreted as the hardware trigger Trigger source includes the DTR Digital Trigger Source and ATR Analog Trigger Source 5 2 1 ATR Trigger When the trigger signal is the analog signal using the ATR trigger source Trigger level needs to be set when using the ATR trigger source trigger level is OV 10V There are two trigger types edge trigger and level trigger PCI9622 Data Acquisition V6 022 Result Comparer Trigger Level Figure 5 2 Analog compare The trigger modes include the edge trigger and
13. 2 2 DTR Trigger When the trigger signal is the digital signal standard TTL level using the DTR trigger source 1 Edge trigger function Edge trigger is to capture the characteristics of the changes between the trigger source signal and the trigger level signal to trigger AD conversion When ADPara TriggerDir PCI9622_ TRIGDIR NEGATIVE choose the trigger mode as the falling edge trigger That is when the DTR trigger signal is on the falling edge AD will immediately access to the conversion process and its follow up changes have no effect on AD acquisition PCI9622 Data Acquisition V6 022 AD Start Pulse Digital Trigger Signal f PO FFNME Ca a The falling edge before The waiting time gt The first falling edge after the the AD started is q AD started is valid invalid tana eteneeeaeeeceerererecerererererecerecererees ot Secocoosocccooooccoccocoocosoosocsoocssocsooocoooosoosoooooosstt E E ee The first working Figure 5 5 Falling edge Trigger When ADPara TriggerDir PCI9622 TRIGDIR POSITIVE choose the trigger mode as rising edge trigger That is when the DTR trigger signal is on the rising edge AD will immediately access to the conversion process and its follow up changes have no effect on AD acquisition When ADPara TriggerDir PCI9622 TRIGDIR POSIT NEGAT choose the trigger mode as rising or falling edge trigger That is when the DTR trigger signal is on the rising or falling edg
14. M On board 2M oscillator output output cycle is 0 5ms 3 2 The Definition of Digital Signal Input Connectors P1 20 pin definition DIO l 2 D 3 4 DB DI4 5 6 5 DI6 7 LS 7 DIS 9 l DID DILO 1 I DIII DI 13 l4 Ss Dil D114 15 I DIIS DGND 17 DGND 19 If DGND 20 DGND Each pin function is defined in the table DIO DI15 Digital input choose the DGND as reference ground DGND Digital ground PCI9622 Data Acquisition V6 022 3 3 The Definition of Digital Signal Output Connectors P2 20 pin definition DON 7 D2 4 05 Do4 6 pos DOG He DCs l0 DOS DOLO l2 DOll DO12 l4 DOL3 DOl4 l DOIS DGND I DGND iN 20 DGND Each pin function is defined in the table DOO DO15 Output Digital output choose the DGND as reference ground DGND Digital ground PCI9622 Data Acquisition V6 022 Chapter 4 Connection Ways for Each Signal 4 1 AD Input Signal Connection Mode 4 1 1 AD Single ended Input Connection Mode Single ended mode can achieve a signal input by one channel and several signals use the common reference ground This mode is widely applied in occasions of the small interference and relatively many channels AIO analog signal H All A AI ae 3 e Ko device device O ach device WA Figure 4 1 single ended input connection 4 1 2 AD Differential Input Connection Mode Differential input mode uses positive and negat
15. NENEEEEEEEEEZZZZZZZZZEEEEEAZAtA 10 4 1 AD Input Signal Connection Mode ccccccccccccsccsseseeeeeeeeeeeeeeeeeeeeeeeeeeeeseseeeeeseeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeeeeeeeeeeeeeeeeeees 10 4 1 1 AD Single ended Input Connection Mode cccccsssssssesssseeeseessesssssssssssssssessssssssssseesseseeeseseseseeeseesseeees 10 AA AD Dirierential Input Connection Moderna 10 4 2 Digital Input Output Connection Mode ccccccccccccccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 11 4 3 Clock and Trigger Signal Connection 000nsnnennnnnnnenunnuerereseerrrerrrrrrererererererererrrerrrrerrrrrrrrrerrrerreeeereseereeeeereesseeens 11 4 4 Multiple Instrument Synchronization ennnnneennensnsnnesssssssssrssrrrerererrerrrerrrererrrerrrrerererrrrrereeereeerererrereeerreseseeeens 11 Chapter 5 The Instruction of the AD Trigger Function ss sseeeeennnnzznnnnnnznnnnnzniatnnnnttni nn nrrrnnnntnnnrnnratnnnntnnzzzzannnnnnnnnz nata 13 9 il AD Iotemal Triez Mod Re ee ee re ee ee 13 e SPARA Bl B qisa a 21 B B E a L eee ee E E eee eee eee ae 13 SA E B a EA 13 eL DIRT a ee eee eee ee 15 Chapter 6 Methods of using AD Internal and External Clock Function ss ss ssssssnnzzznnnnnnannnnnznnznnenznnnzzzzzznznnnzzzznznnna 18 6 1 Internal Clock Function of AD Q ccccc cece ecseessssesesscsscscccccccccccccccccccccccccccccesscscssecccasccaccecsseccccccccccccccccsscsssccs
16. a TriggerDir PCI9622 TRIGDIR POSIT NEGAT it means the trigger level is low or high The effect is the same as the internal software trigger PCI9622 Data Acquisition V6 022 Chapter 6 Methods of using AD Internal and External Clock Function 6 1 Internal Clock Function of AD Internal Clock Function refers to the use of on board clock oscillator and the clock signals which are produced by the user specified frequency to trigger the AD conversion regularly To use the clock function the hardware parameters ADPara ClockSource PCI9622 CLOCKSRC IN should be installed in the software The frequency of the clock in the software depends on the hardware parameters ADPara Frequency For example if Frequency 100000 that means AD work frequency is 100000Hz that is 100 KHz 10us point 6 2 External Clock Function of AD External Clock Function refers to the use of the outside clock signals to trigger the AD conversion regularly The clock signals are provide by the CLKIN pin of the CNI connector The outside clock can be provided by PCI9622 clock output CLKOUT of CN1 as well as other equipments for example clock frequency generators To use the external clock function the hardware parameters ADPara ClockSource PCI9622 CLOCKSRC OUT should be installed in the software The clock frequency depends on the frequency of the external clock and the clock frequency on board that is the frequency depends on the hardware parameters ADPara Freque
17. a computer which is compatible with PCI9622 to constitute the laboratory product quality testing center and systems for different areas of data acquisition waveform analysis and processing It may also constitute the monitoring system for industrial production process Unpacking Checklist Check the shipping carton for any damage If the shipping carton and contents are damaged notify the local dealer or sales for a replacement Retain the shipping carton and packing material for inspection by the dealer Check for the following items in the package If there are any missing items contact your local dealer or sales gt PCI9622 Data Acquisition Board gt ART Disk a user s manual pdf b drive c catalog gt Warranty Card FEATURES Analog Input gt Converter Type AD7663ASTZ default AD7665 gt Input Range 10V 45V default 2 5 0 10V 0 5V gt 16 bit resolution gt Sampling Rate up to 250KS s AD7665 it can up to 500KS s Note each channel actual sampling rate sampling rate the number of sampling channels Frequency division formula master frequency the number of frequency division the master frequency 20MHz 32 bit frequency division and the number of frequency division from 80 to 2 AD7665 the number of frequency division from 40 to 1290322 Analog Input Mode 32SE 16DI Data Read Mode non empty half full inquiry mode and inquire mode Memory Depth 16K word FIFO memory Memory Signs non empty
18. al cycle 1 external signal frequency Start enable Pulse conversion Figure 6 1continuous acquisition in internal clock Note a sample cycle 6 3 2 AD Grouping Sampling Function Grouping acquisition pseudo synchronous acquisition function refers to the sampling clock frequency conversion among the channels of the group in the AD sampling process and also a certain waiting time exists between every two groups this period of time is known as the Group Interval Loops of group refer to numbers of the cycle acquisition for each channel in the same group In the internal clock mode and the fixed frequency external clock mode the time between the groups is known as group cycle The conversion process of this acquisition mode as follows a short time stop after the channels conversion in the group that is Group Interval and then converting the next group followed by repeated operations in order so we call it grouping acquisition The purpose of the application of the grouping acquisition is that at a relatively slow frequency to ensure that all of the time difference between channels to become smaller in order to make the phase difference become smaller thus to ensure the synchronization of the channels so we also say it is the pseudo synchronous acquisition function In a group the higher the sampling frequency is the longer Group Interval is and the better the relative synchronization signal 1s The sampling frequency in a
19. count of N will result in a one shot pulse N CLK cycles in duration The one shout is retriggerable hence OUT will remain low for N CLK pulses after any trigger The one shot pulse can be repeated without rewriting the same count into the counter GATE has no effect on OUT If a new count is written to the Counter during a one shot pulse the current one shot is not affected unless the counter is retriggered In that case the Counter is loaded with the new count and the one shot pulse continues until the new count expires BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 24 PCI9622 Data Acquisition V6 022 NOTE The following conventions apply to all mode timing diagrams 1 Counters are programmed for binary not BCD counting and for reading writing least significant byte LSB only 2 The counter is always selected CS always low 3 CW stands for Control Word CW 10 means a control word of 10 HEX is written to the counter 4 LSB stands for Least Significant Byte of count 5 Numbers below diagrams are count values The lower number is the least significant byte The upper number is the most significant byte Since the counter is programmed to read writer LSB only the most significant byte cannot be read N stands for an undefined count Vertical lines show transitions between count values CWsil LSB 3 CLA GATE OUT o o o o FF o o sjn Safafa lela e CWelt LSB 3 OUT
20. ctors CNI 68 pin SCSI definition AU 68 TA 34 AIO AGND 67 ik jii 33 AD AB 66 x a 32 AI4 AGND 65 jix a 31 AI5 AI6 64 ik lli 30 AI AGND 63 iii a 29 AI8 AI9 62 gt a 28 AIO AGND 61 ix i 27 AIl 1 All2 60 iii jil 26 AI13 AGND 59 ii a 25 All4 AILS sill Llu AIL6 AGND 57 iu L 23 AI AGND s J Ll2 ALIS AGND 55 jiu kl 21 AII9 AGND 54 ik je 20 AI20 AGND 53 jiu jil 19 AI2I AGND 52 iii b 18 AI22 AGND 51 a 17 AI23 AGND so klis AI24 AGND 49 iii je 15 AI25 AGND slo Lola AI26 AGND 47 i lili 13 AI27 AGND 46 il ii 12 AI28 AGND 45 i a 11 AI29 AGND 44 Mi El 10 ALO AGND 43 L kl 9 ABI AGND 42 gt a 8 ATR AGND 41 ii a 7 AGND GND sol d Lle GND GND 39 ji kl 5 GATE0 DIR 38 gt a 4 CLKO GND 37 J Lls OUTO CLKIN 36 gt ie 2 CLK2M GND 35 a a l CLKOUT l PCI9622 Data Acquisition V6 022 Pin definition about AD AIO AI31 AD analog input reference ground is AGND AGND Analog ground This AGND pin should be connected to the system s AGND plane Digital ground Ground reference for Digital circuitry This GND pin should be connected to the system s GND plane CLKIN External clock input please use GND as reference ground CLKOUT Internal clock output when allow clock output it is internal clock output otherwise it is CNT counter output GND for reference ground ka i Digital trigger signal input choose GND as reference ground Counter clock input Input Counter gate o OUTO Output Counter output 11 CLK2
21. e AD will immediately access to the conversion process and its follow up changes have no effect on AD acquisition This function can be used in the case that the acquisition will occur if the exoteric signal changes 2 Triggering level function Level trigger is to capture the condition that trigger signal is higher or lower than the trigger level to trigger AD conversion When ADPara TriggerDir PCI9622 TRIGDIR NEGATIVE it means the trigger level is low When DTR trigger signal is in low level AD is in the conversion process once the trigger signal is in the high level AD conversion will automatically stop when the trigger signal is in the low level again AD will re access to the conversion process that is only converting the data when the trigger signal is in the low level AD Start pase o INI Digital Trigger Signal pereretezzoseseseseseseeeneti Saon The high level before gt Phe wart ume gt IN a Figure 5 6 High Level Trigger PCI9622 Data Acquisition V6 022 When ADPara TriggerDir PCI9622 TRIGDIR POSITIVE it means the trigger level is high When DTR trigger signal is in high level AD is in the conversion process once the trigger signal is in the low level AD conversion will automatically stop when the trigger signal is in the high level again AD will re access to the conversion process that is only converting the data when the trigger signal 1s in the high level When ADPar
22. group depends on ADPara Frequency Loops of group depends on ADPara LoopsOfGroup the Group Interval depend on ADPara Group Interval Based on the grouping function it can be divided into the internal clock mode and the external clock mode Under the internal clock mode the group cycle is decided by the internal clock sampling period the total number of sampling channels Loops of group and Group Interval together In each cycle of a group AD only collects a set of data Under the external clock mode external clock cycle internal clock sampling cycle x the total number of sampling channels x Loops of group AD chip conversion time AD data acquisition is controlled and triggered by external clock The external clock mode is divided into fixed frequency external clock mode and unfixed frequency external clock mode Under the fixed frequency external clock mode the group cycle is the sampling period of the external clock The formula for calculating the external signal frequency is as follows BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 19 PCI9622 Data Acquisition V6 022 Under the internal clock mode Group Cycle the internal clock sampling period x the total number of sample channels x Loops of group AD chips conversion time Group Interval External signal cycle cycle signal points Loops of group x Group Cycle External signal frequency 1 external signal cycle Under the external clock mode
23. half full AD Mode continuum sampling grouping sampling Group Interval software configurable minimum value is sampling period maximum value is 419430us Loops of Group software configurable minimum value is one time maximum value is 65535 times Clock Source external clock internal clock software configurable Trigger Mode software trigger hardware trigger external trigger VV VV VV VV V V Trigger Type level trigger edge trigger BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 3 PCI9622 Data Acquisition V6 022 Trigger Direction negative positive either positive or negative trigger Trigger Source ATR analog trigger and DTR digital trigger ATR Input Range 0 10V DTR Input Range standard TTL level Trigger Level 0 10V AD Conversion Time lt 10us Programmable Gain 1 2 4 8 AD8251 default or 1 2 5 10 AD8250 or 1 10 100 1000 AD8253 Analog Input Impedance 1OMQ Amplifier Set up Time 785ns 0 001 max Non linear error 1 LSB Maximum System Measurement Accuracy 0 01 Operating Temperature Range 0 C 55 C VV VV VV VV VV VV V Storage Temperature Range 20 C 70 C Digital Input gt Channel No 16 channel gt Electric Standard TTL compatible gt High Voltage 2V gt Low Voltage 0 8V DO digital output Channel No 16 channel Electrical Standard CMOS compatible High Voltage 4 45V Low Voltage 0 5V Power on Reset Yy VV V V CNT C
24. ib Figure 6 1 Grouping Sampling which grouping cycle No is 1 under the Internal Clock Mode Note a internal clock sample cycle b AD chips conversion time c Group Interval d group cycle BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 20 PCI9622 Data Acquisition V6 022 Change the loops of group into 2 then the acquisition process is to collect the first set of data including two data of channel 0 and two data of channel 1 the conversion order is 0 1 0 1 We need 10us to sample each of the four data After the conversion time of an AD chip AD will automatically stop to enter into the waiting state until the 50us Group Interval ends We start the next group begin to convert the data of channel 0 and 1 and then enter into the waiting state again and the conversion is going on in this way as the diagram following shows Start Enabled Z os ee Convert Pulse ibic ia d Figure 6 2 Grouping Sampling which grouping cycle No is 2 under the Internal Clock Mode Notes a internal clock sample cycle b AD chips conversion time c Group Interval d group cycle Under the external clock mode the requirement is the external clock cycle gt the internal clock sampling period x the total number of sampling channelsx Loops of group AD chip conversion time otherwise the external clock appearing in the group conversion time will be ignored Under the fixed frequency external clock mode
25. itially be high Counting is triggered by a rising edge of GATE When the initial count has expired OUT will go low for one CLK pulse and then go high again After writing the Control Word and initial count the counter will not be loaded until the CLK pulse after a trigger This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 pulse after a trigger A trigger results in the Counter being loaded with the initial count on the next CLK pulse The counting sequence is retriggerable OUT will not strobe low for N 1 CLK pulses after any trigger GATE has no effect on OUT BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 29 PCI9622 Data Acquisition V6 022 If a new count is written during counting the current counting sequence will not be affected If a trigger occurs after the new count is written but before the current count expires the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there CW 1A L5B 3 CLE GATE l OUT l inIn Ina EJ O CW ms 14 L5BH A CLE GATE OUT CWmlA LSB LSB 6 m LIL LPT CLA GATE OUT In wntw nf n eo o o s Fe rej o 6 2 olfrlrel s la Figure 7 6 Mode 5 PCI9622 Data Acquisition V6 022 Chapter 8 Notes Calibration and Warranty Policy 8 1 Notes In our products packing user can find a user manual a PCI9622 module and a quality
26. ive channels to input a signal This mode is mostly used when biggish interference happens and the channel numbers are few Single ended differential input mode can be set bv the software please refer to PCI9622 software manual According to the diagram below PCI9622 board can be connected as analog voltage double ended input mode which can effectively suppress common mode interference signal to improve the accuracy of acquisition Positive side of the 16 channel analog input signal is connected to AIO AI15 the negative side of the analog input signal is connected to AI16 AI31 equipments in industrial sites share the AGND with PCI9622 board Me a AIO analog signal AGND i Vass o evice AI16 i All an AGND i AEG 9 evice AI17 fi e e AI15 AI3B1 e aos es device AGND SG e Figure 4 2 differential input connection BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 10 PCI9622 Data Acquisition V6 022 4 2 Digital Input Output Connection Mode DIo switch signal DOO switch signal aan Dil A DOI DI2 DO2 c i JI i L L e i e e DI5 DO15 switch device switch device switch device DGND DGND Y e ie TA Figure 4 3 digital signal input connection Figure 4 4 digital signal output connection 4 3 Clock and Trigger Signal Connection CLKOUT CLKIN
27. level trigger 1 Edge trigger function Edge trigger is to capture the characteristics of the changes between the trigger source signal and the trigger level signal to trigger AD conversion When TriggerIvpe PCI9622 TRIGTYPE EDGE it is the edge trigger type When ADPara TriggerDir PCI9622_ TRIGDIR NEGATIVE choose the trigger mode as the falling edge trigger That is when the ATR trigger signal is on the falling edge AD will immediately access to the conversion process and its follow up changes have no effect on AD acquisition AD Start Pulse AD Working Pulse after triggered a b al LILULLULULULULIL i ATR The falling edge The first falling edge after the before the AD started i AD started is valid iz maalid Pw ccc n ccc rece ncccccceseesceesseesseesseesscessseseseseseseseee Figure 5 3 Falling edge Trigger When ADPara TriggerDir PCI9622 TRIGDIR POSITIVE choose the trigger mode as rising edge trigger That is when the ATR trigger signal is on the rising edge AD will immediately access to the conversion process and its follow up changes have no effect on AD acquisition When ADPara TriggerDir PC19622 TRIGDIR POSIT NEGAT choose the trigger mode as rising or falling edge trigger That is when the ATR trigger signal is on the rising or falling edge AD will immediately access to the conversion process and its follow up changes have no effect on AD acquisition This function can be used in the case
28. ncy only functions in the packet acquisition mode and its sampling frequency of the AD is fully controlled by the external clock frequency 6 3 Methods of Using AD Continuum and Grouping Sampling Function 6 3 1 AD Continuum Sampling Function The continuous acquisition function means the sampling periods for every two data points are completely equal in the sampling process of AD that is completely uniform speed acquisition without any pause so we call that continuous acquisition To use the continuous acquisition function the hardware parameters ADPara ADMode PCI9622 ADMODE SEQUENCE should be installed in the software For example in the internal clock mode hardware parameters ADPara Frequency 100000 100KHz should be installed and 10 microseconds after the AD converts the first data point the second data point conversion starts and then 10 microseconds later the third data point begins to convert and so on The formula for calculating the external signal frequency is as follows Under the internal clock mode External signal frequency AD sampling frequency cycle signal points the total number of channels External signal cycle 1 external signal frequency BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 18 PCI9622 Data Acquisition V6 022 Under the external clock mode External signal frequency AD sampling frequency cycle signal points the total number of channels External sign
29. omplete the installation Self check At this moment there should be installation information of the installed device in the Device Manager when the device does not work you can check this item Open Start gt Programs gt ART Demonstration Monitoring and Control System gt Corresponding Board gt Advanced Testing Presentation System the program is a standard testing procedure Based on the specification of Pin definition connect the signal acquisition data and test whether AD is normal or not Connect the input pins to the corresponding output pins and use the testing procedure to test whether the switch is normal or not Delete Wrong Installation When you select the wrong drive or viruses lead to driver error you can carry out the following operations In Resource Explorer open CD ROM drive run Others SUPPORT gt PCI bat procedures and delete the hardware information that relevant to our boards and then carry out the process of section I all over again we can complete the new installation BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 32
30. ounter Timer 32 bit counter timer 3 independent subtraction counters Count Mode 6 modes Electrical Standard TTL level Clock Source CLKn frequency range 1Hz 10MHz Gate GATEn rising edge high level low level Counter Output OUTn high level low level VV VV V WV Other Features Board Clock Oscillation 40MHz Dimension 132 5mm L 87 5mm w 15mm H 4 PCI9622 Data Acquisition V6 022 Chapter 2 Components Layout Diagram and a Brief Description 2 1 The Main Components Layout Diagram le L PCI962Z2 rnmm ji te MW i A RE V6 08 ee Sr m FE 4 ULL tata i ii fe YH Qal I ki pe miT i r i sg 04 Woo cn S fel jin Ahna PS Wet E N MA a ge a qi 4 ha MA pre ET MITT Rune To MITT ETTI F e Li l i Tar rem e eu VST TY 3 7 ee TE 3 gt Sr i idi ii j mi iew Eam E3 jllithih T i T ili ka Ww r t ita ee TRL L l jU Be H ried MITI ww L T a L Jr TEL pant 8 RIETAGAC 3 2 2 The Function Description for the Main Component 2 2 1 Signal Input and Output Connectors CNI analog signal input connector P1 digital signal input port P2 digital signal output port 2 2 2 Physical ID of DIP Switch DIDI Set physical ID number When the PC is installed more than one PCI9622 you can use the DIP switch to set a physical ID number for each board which makes it very convenient for users to distinguish and visit each board
31. rs Because the external clock frequency is not fixed the size of external clock cycle is inconsistent but to meet the external clock cycle gt the internal clock sampling period x the total number of sampling channels x Loops of group AD chip conversion time otherwise the external clock edge appearing in the group conversion time will be ignored Start Enabled External Clock a Convert Pulse Figure 6 4 Grouping sampling under the not fixed frequency external clock mode Note a internal clock sample cycle b AD chips conversion time BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 22 PCI9622 Data Acquisition V6 022 Chapter 7 Timer Counter Function MODE 0 Interrupt on terminal count Mode 0 is typically used for event counting After the Control Word is written OUT is initially low and will remain low until the Counter reaches zero OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Counter GATE I enables counting GATE 0 disables counting GATE has no effect on OUT After the Control Word and initial count are written to a Counter the initial count will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not go high until N 1 CLK pulses after the initial count is written If a new count is written to the Counter it will be loaded on the next CLK pulse and co
32. sseees 18 0 2 External C lock Funcion ot a EEE TEENE 18 6 3 Methods of Using AD Continuum and Grouping Sampling FUNCTION ssnennzennnenznnnnnnnnnmrennzznmrnnznzznna 18 6 3 1 AD Continuum Sampling FUNCTION ccccceceesesseeeeesseseseessseessseesseesssssessssssassasaasasaaaaeeeaeeeeeeaaaaaaaaaas 18 6 3 2 AD Grouping Sampling FUNCTION sl cceceeeeeeeeeeeeeeeeeesseeeeeessssseeseesaeseeeesseaesaasesseasaasaaaaaaaaaaaaaaaaaaaaaaaaaaas 19 Chapper L I mo Counter CTO Is aon tessa anetd apy ee REENA mains eae rE 23 Chapter 8 Notes Calibration and Warranty POLICY icccccccccsssccccccccccesnesesccecceeeeeaeesseeeceeeeeaaeseeeeeeeeeeaaaseeeeeeeeesaaaaseeeceeeeeaaaaeeeeess 31 SAINT Sa 31 6 2 Warrativ We ONG o E E A 31 Products Rapid Installation and Self check is sescsctecsden cies nnota a aoasssasbacseaceoetedonsendees 32 Kapid Jista GT e f a L 32 DG eC MSC i aa e sous seubss E A so seoe ieee ne iteesde EA E E E 32 Dete vone dis tall Oi a Gala 32 PCI9622 Data Acquisition V6 022 Chapter I Overview In the fields of Real time Signal Processing Digital Image Processing and others high speed and high precision data acquisition modules are demanded ART PCI9622 data acquisition module which brings in advantages of similar products that produced in China and other countries is convenient for use high cost and stable performance ART PC19622 is a data acquisition module based on PCI bus It can be directly inserted into IBM PC AT or
33. uarantee in the following situations Damage caused by not following instructions in the User s Manual Damage caused by carelessness on the user s part during product transportation Damage caused by unsuitable storage environments 1 e high temperatures high humidity or volatile chemicals VV V Y Damage from improper repair by unauthorized ART technicians gt Products with altered and or damaged serial numbers are not entitled to our service 4 Customers are responsible for shipping costs to transport damaged products to our company or sales office 5 To ensure the speed and quality of product repair please download an RMA application form from our company website PCI9622 Data Acquisition V6 022 Products Rapid Installation and Self check Rapid Installation Product driven procedure is the operating system adaptive installation mode After inserting the disc you can select the appropriate board type on the pop up interface click the button driver installation or select CD ROM drive in Resource Explorer locate the product catalog and enter into the APP folder and implement Setup exe file After the installation pop up CD ROM shut off your computer insert the PCI card If it is a USB product it can be directly inserted into the device When the system prompts that it finds a new hardware you do not specify a drive path the operating system can automatically look up it from the system directory and then you can c
34. unting will continue from the new count If a two byte count is written the following happens 1 Writing the first byte disables counting OUT is set low immediately no clock pulse required 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the counting sequence to be synchronized by software Again OUT does not go high until N 1 CLK pulses after the new count of N is written If an initial count is written while GATE 0 it will still be loaded on the next CLK pulse When GATE goes high OUT will go high N CLK pulse later no CLK pulse is needed to load the Counter as this has already been done BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 23 PCI9622 Data Acquisition V6 022 CW 10 LSB 4 a ee o o GATE OUT Peas L A L FF i o H Jn nn 3 2 FF FE CW 10 LSB 3 Cw 10 LS68 3 LSB 7 OUT i Q d 0 FF ONINININI5l3 xi il 8 IA IB Figure 7 1 Mode 0 MODE 1 Hardware retriggerable one shot OUT will be initially high OUT will go low on the CLK pulse following a trigger to begin the one shot pulse and will remain low until the Counter reaches zero OUT will then go high and remain high until the CLK pulse after the next trigger After writing the Control Word and initial count the Counter is armed A trigger results in loading the Counter and setting OUT low on the next CLK pulse thus starting the one shot pulse An initial
35. while counting does not affect the current counting sequence If a trigger is received after writing a new count but before the end of the current half cycle of the square wave the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new counter will be loaded at the end of the current half cycle Mode 3 1s implemented as follows Even counts OUT is initially high The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses When the count expires OUT changes value and the Counter is reloaded with the initial count The above process is repeated indefinitely Odd counts OUT is initially high The initial count minus one an even number is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses One CLK pulse after the count expires OUT goes low and the Counter 1s reloaded with the initial count minus one Succeeding CLK pulses decrement the count by two When the count expires OUT goes high again and the Counter is reloaded with the initial count minus one The above process is repeated indefinitely So for odd counts OUT will be high for N 1 2 counts and low for N 1 2 counts BUY ONLINE at art control com englishs or CALL 86 10 51289836 CN 27 PCI9622 Data Acquisition V6 022 CW 16 LSB 4 CW 16 LSB 25 Ly G 16 LSB 4 Inirleleizizisizlzlizisizisi i Figure 7 4 Mode 3 Note
Download Pdf Manuals
Related Search