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Rabbit ® 3000 Microprocessor User`s Manual

1. Rabbit Z180 Meaning Bit select 000 bit 0 001 bit 1 b b 010 bit 2 011 bit 3 100 bit 4 101 bit 5 110 bit 6 111 bit 7 Condition code select 00 NZ 01 Z 10 NC 11 C d d 7 bit signed displacement Expressed in two s complement dd ww Word register select destination 00 BC 01 DE 10 HL 11 SP dd Word register select alternate 00 BC 01 DE 10 HU e j 8 bit signed displacement added to PC Condition code select 000 NZ non zero 001 Z zero f f 010 NC non carry 011 C carry 100 LZ logical zero 101 LO logical one 110 P sign plus 111 M sign minus m m MSB of a 16 bit constant mn mn 16 bit constant n n 8 bit constant or LSB of a 16 bit constant Byte register select 000 B 001 C r g g g 010 D 011 E 100 H 101 L IIl A ss ww Word register select source 00 BC 01 DE 10 HL 11 SP Restart address select 010 0x0020 011 0x0030 100 0x0040 101 0x0050 111 0x0070 xx xx Word register select 00 BC 01 DE 10 IX 11 SP YY YY Word register select 00 BC 01 DE 10 IY 11 SP zz zz Word register select 00 BC 01 DE 10 HL 11 AF Logical zero if all four of the most significant bits of the result are 0 Logical one if any of the four most significant bits of the result are 1 Chapter 19 Rabbit Instructions 251 19 1
2. MEN Clock E 1 1 l l l egel ignore transitions Bi S adj none ne none al 4 ignore transitions subtract one none Bi M mone l l l l l l l l l l l l l l l l Bi M Clock SE L A KA 512157450572 t ignore transitions subtract one none add one ignore transitions I 1 1 l l l add on n l l l l d n l l l l l l l l l l l J Bi S Clock ATE Dp SIISE ee ee 190 Rabbit 3000 Microprocessor User s Manual With NRZ and NRZI encoding all transitions occur on bit cell boundaries and the data should be sampled in the middle of the bit cell If a
3. 316 B 2 Pins with Alternate Functions u a orte tere reet eere er E Rete 318 Appendix C System User Mode 319 Cl System User Mode Opcodes oti erri e et pt ecc eg ee e e pr ee tes 320 C 2 System User Mode RegISt rs l N Aaa RIS innen 321 CS ntetf ptS eoe mee suya elu Doi a be m t ipei re Cree einen 323 C 3 Peripheral Interrupt Prioritization 2 324 Using the System User Mode eintreten rete tetra re HER HEP SR 326 C41 Memory Protection Only uet pa BDS BE ER Ee RE eee E 326 C 4 2 Mixed System User Mode Operation eese eterne etre en enne 327 C 4 3 Complete Operating Systeme niseni eieiei tEn EEE ea RE EESAN COSE EE EEA T 328 Appendix D Rabbit 3000A Internal I O Registers 329 Index 337 Table of Contents Rabbit 3000 Microprocessor User s Manual 1 INTRODUCTION Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in small and medium scale controllers The first microprocessor was the Rabbit 2000 The second microprocessor now available is the Rabbit 3000 Rabbit microprocessor design ers have had years of experience using Z80 Z180 and HD64180 microprocessors in small controllers The Rabbit shares a similar architecture and a high degree of compatibility with these microprocessors but it is a vast improve
4. Register Name Mnemonic Address Global Control Status Register GCSR 0x0000 Watchdog Timer Control Register WDTCR 0x0008 Watchdog Timer Test Register WDTTR 0x0009 Global Clock Modulator 0 Register GCMOR 0x000A Global Clock Modulator 1 Register GCMIR 0x000B Secondary Watchdog Timer Register SWDTR 0x000C Global Power Save Control Register GPSCR 0x000D Global Output Control Register GOCR 0 000 Global Clock Double Register GCDR 0x000F Instruction Data Register MMIDR 0x0010 Stack Segment Register STACKSEG 0 0011 Data Segment Register DATASEG 0x0012 Segment Size Register SEGSIZE 0x0013 Memory Bank 0 Control Register MBOCR 0x0014 Memory Bank 1 Control Register MBICR 0 0015 Memory Bank 2 Control Register MB2CR 0x0016 Memory Bank 3 Control Register MB3CR 0x0017 MMU Expanded Code Register MECR 0x0018 Memory Timing Control Register MTCR 0x0019 Breakpoint Debug Control Register BDCR 0x001C User Enable registers 0 03 Memory Protection registers Ox04xx These registers are only available on the Rabbit 3000A 322 Rabbit 3000 Microprocessor User s Manual C 3 Interrupts When enabled for User mode access a peripheral interrupt if it is capable of generating an interrupt can only be requested at Interrupt Priority Level 2 or 1 Interrupts and RSTs and SYSCALL all enter the System mode automatically There will be times however that an interrupt should be handled in the
5. Register Name Mnemonic I O Address R W Reset Bank 2 Control Register IB2CR 0x0082 w 00000000 Bank 3 Control Register IB3CR 0x0083 w 00000000 Bank 4 Control Register IBACR 0x0084 00000000 Bank 5 Control Register 185 0 0085 00000000 Bank 6 Control Register IB6CR 0x0086 W 00000000 I O Bank 7 Control Register IB7CR 0x0087 W 00000000 PWM LSB 0 Register PWLOR 0x0088 W 00 PWM MSB 0 Register PWM0R 0x0089 w XXXXXXXX PWM LSB 1 Register PWLIR 0x008A w xxxxx00x PWM MSB 1 Register PWMIR 0x008B w XXXXXXXX PWM LSB 2 Register PWL2R 0x008C w 00 PWM MSB 2 Register PWM2R 0x008D PWM LSB 3 Register PWL3R 0x008E 00 PWM MSB 3 Register PWM3R 0x008F w XXXXXXXX Input Capture Ctrl Status Register ICCSR 0x0056 R W 00000000 Input Capture Control Register ICCR 0x0057 w 00 Input Capture Trigger 1 Register ICTIR 0x0058 00000000 Input Capture Source 1 Register ICSIR 0x0059 Input Capture LSB 1 Register ICLIR 0x005A R XXXXXXXX Input Capture MSB 1 Register ICMIR 0x005B R XXXXXXXX Input Capture Trigger 2 Register ICT2R 0x005C w 00000000 Input Capture Source 2 Register ICS2R 0x005D w XXXXXXXX Input Capture LSB 2 Register ICL2R 0x005E R XXXXXXXX Input Capture MSB 2 Register ICM2R 0x005F R XXXXXXXX Quad Decode Ctrl Status Register QDCSR 0x0090 R W XXXXXXXX Quad Decode Control Register QDCR 0 0091 w 00000000 Quad De
6. Timer A1 Decode perclk 2 HE perclk 16 8 Timer B System 10 bit counter Quadrature 10 bits gt Serial B Serial C Serial D compare Timer_B1 match reg A match preload A Timer_B2 match reg match preload i Figure 11 1 Block Diagram of Timers A and B Control Timer Svnchronized outputs Chapter 11 Timers 149 11 1 Timer A Timer A consists of ten separate countdown timers A1 A10 as shown in Figure 11 1 Timers A1 and A2 A 10 are 8 bit countdown registers as shown in Figure 11 2 The reload register can contain any number in the range from 0 to 255 The counter divides by n 1 For example if the reload register contains 127 then 128 pulses enter on the left before a pulse exits on the right If the reload register contains zero then each pulse on the left results in a pulse on the right that is there is division by one 8 bit reload register Clock in load g 8 bit down counter pulse on zero count out Input clock Count value 2 2 1 Output pulse Figure 11 2 Reload Register Operation The timer systems can be driven by the peripheral clock or p
7. HL 10110110 5 fr 0 OR IX d 11011101 10110110 d 9 fr s LO OR IY d 11111101 10110110 d 9 fr s LO OR HL DE 11101100 2 fr L0 OR IX DE 11011101 11101100 4 f L0 OR IY DE 11111101 11101100 4 f L0 OR n 11110110 n 4 fr L0 OR r 10110 r 2 fr L0 POP IP 11101101 01111110 7 POP IX 11011101 11100001 9 11111101 11100001 9 SSeS POP zz 11zz0001 7 r 5 11101101 01110110 9 PUSH IX 11011101 11100101 12 m PUSH IY 11111101 11100101 12 SS BS PUSH zz 11220101 10 Fu SS ten aE RES b HL 11001011 10 b 110 10 RES b IX d 11011101 11001011 d 10 b 110 13 RES b 11111101 11001011 d 10 b 110 13 RES b r 11001011 10 b r 4 r RET 11001001 8 RET 11 000 8 2 RETI 11101101 01001101 12 RL HL 11001011 00010110 10 f b L RL IX d 11011101 11001011 d 00010110 13 f b L RL IY d 11111101 11001011 d 00010110 13 f b L RL DE 11110011 2 fr TL RL r 11001011 00010 r 4 fr L RLA 00010111 2 fr mam Gs RLC HL 11001011 00000110 10 f b L RLC IX d 11011101 11001011 d 00000110 13 f b L RLC IY d 11111101 11001011 d 00000110 13 f b L RLC r 11001011 00000 r 4 fr L RLCA 00000111 2 fr a RR HL 11001011 00011110 10 f b L RR 11011101 11001011 d 00011110 13 f b L
8. Output Capacitance Time Delay 30 pF 60pF 90 pF Max clock to address delay 6 ns 8 ns 11 ns Max clock to memory chip select delay Tcs 6 ns 8 ns 11 ns Max clock to I O chip select delay Tjocsx 6 ns 8 ns 11 ns Max clock to I O write strobe delay Tjowg 6 ns 8 ns 11 ns Max clock to I O buffer enable delay TpuFEN 6 ns 8 ns 11 ns Max high Z to data valid rel to clock Tpgzy 10 ns 12 ns 15 ns Max data valid to high Z rel to clock Tpygz 10 ns 12 ns 15 ns The measurements were taken at the 50 points under the same conditions that the I O read delays were measured I O bus cycles have an automatic wait state and thus require 3 clocks plus any extra wait states specified See Table 16 2 for delays at other voltages 226 Rabbit 3000 Microprocessor User s Manual 16 3 Further Discussion of Bus and Clock Timing The clock doubler is normally used except in situations where low frequency systems are specifically being used The clock doubler works by oring the clock with a delayed ver sion of itself The nominal delay varies from 6 to 20 ns and is settable under program con trol Any asymmetry in the oscillator waveform before it is doubled will result in alternate clocks having slightly different periods Using the suggested oscillator circuit the asym metry is no worse than 52 48 This results in a given clock being shortened by the ratio 50 52 or 4 Memory access time is
9. 1 1 0 Serial Port async cks 0x00D0 0x00D7 HR 7 1 0 OxDO Serial Port F async HDLC 0x00D8 0x00DF IIR 7 1 1 OxDO Serial Port C async cks 0x00E0 0x00E7 HR 7 1 0 OxEO Serial Port D async cks 0x00F0 0x00F7 HR 7 1 0 OxFO RST 10 instruction n a UIR 7 1 0 0x20 RST 18 instruction n a UIR 7 1 0 0x30 RST 20 instruction n a UIR 7 1 0 0x40 RST 28 instruction n a UIR 7 1 0 0x50 282 Rabbit 3000 Microprocessor User s Manual Table B 4 Rabbit 3000 I O Address Ranges and Interrupt Service Vectors continued On Chip Peripheral l O Address Range ISR Starting Address SYSCALL instruction n a UIR 7 1 0 0x60 RST 38 instruction n a UIR 7 1 0 0x70 Secondary Watchdog 0x000C IR 7 11 0 0x10 Stack Limit Violation n a UIR 7 1 1 OxBO Write Protection Violation n a UIR 7 1 0 0x90 System Mode Violation n a UIR 7 1 1 0x80 Appendix B Rabbit 3000 Revisions 283 B 1 3 Revision Level ID Register Two read only registers are provided to allow software to identify the Rabbit microproces sor and recognize the features and capabilities of the chip Five bits in each of these regis ters are unique to each version of the chip One register identifies the CPU GCPU and the other register is reserved for revision identification GREV The CPU identification GC
10. lt BUFEN 7 lt TBUFEN TBUFEN gt lt setup D 7 0 l External I O Write one programmed wait state I T1 gt lt Tw gt lt T2 gt acl Lt ty 15 0 x lt Tadr amp Tcsx 5 A gt lt Tlocsx Tlocsx IOWR TiowR BUFEN 7 TBUFEN TBUFEN gt D 7 0 gt TDHZV TpvHz gt Figure 16 6 I O Read and Write Cycles No Extra Wait States NOTE IOCSx be programmed to be active low default or active high Chapter 16 AC Timing Specifications 225 The following I O read time delays were measured Table 16 5 I O Read Time Delays Output Capacitance Time Delay 30 pF 60pF 90 pF Max clock to address delay T a 6 ns 8 ns 11 ns Max clock to memory chip select delay Tcsx 6 ns 8 ns 11 ns Max clock to I O chip select delay Tjocsx 6 ns 8 ns 11 ns Max clock to I O read strobe delay Tjogp 6 ns 8 ns 11 ns Max clock to I O buffer enable delay TpuFEN 6 ns 8 ns 11 ns Min data setup time 1 ns Min data hold time Ons The measurements were taken at the 50 points under the following conditions e T 40 C to 85 C V 3 3 V e Internal clock to nonloaded CLK pin delay lt 1 ns 85 C 3 0 V The following I O write time delays were measured Table 16 6 I O Write Time Delays
11. 229 programming port 18 multiple interrupts 46 distribution 81 Dynamic C 1 19 on chip peripherals 282 284 low power design 212 BIOS 239 periodic 3 72 main clock 80 91 211 library functions 244 82 93 149 194 240 243 oscillator circuits 211 periodic interrupts 240 273 276 294 300 power consumption power consumption 243 priorities 44 45 97 PO 85 237 238 virtual drivers 240 priviliged instructions and spectrum spreader Watchdog 240 semaphores 46 eee 80 86 214 227 E semaphores 47 time date clock 3 91 serial 179 timer and clock use 246 EMI mitigation 213 System User mode 323 timing issues 227 228 PCB layout 214 updating registers 245 cold boot 52 spectrum spreader 214 comparison Rabbit 3000 vs extended memory L land D space e 2128 low power design 212 compiler 128 practical considerations 30 crystal frequencies 273 TON DoWer options spiriti 57 stack segment 29 LQFP package external bus ATA LAND pattern
12. Write Protect Segment x Low Register WPSALR Address 0x0481 WPSBLR Address 0x0485 Bit s Value Description 0 Disable write protect for address offset 0x7000 0x7FFF in WP Segment x 1 Enable write protect for address offset 0x7000 0x7FFF in WP Segment x 0 Disable write protect for address offset 0x6000 0x6FFF in WP Segment x 1 Enable write protect for address offset 0x6000 0x6FFF in WP Segment x 0 Disable write protect for address offset 0x5000 0x5FFF in WP Segment x i 1 Enable write protect for address offset 0x5000 0x5FFF in WP Segment x 0 Disable write protect for address offset 0 4000 in WP Segment x d 1 Enable write protect for address offset 0x4000 0x4FFF in WP Segment x 0 Disable write protect for address offset 0x3000 0x3FFF in WP Segment x 1 Enable write protect for address offset 0x3000 0x3FFF in WP Segment x 0 Disable write protect for address offset 0x2000 0x2FFF in WP Segment _ 1 Enable write protect for address offset 0x2000 0x2FFF in WP Segment x 0 Disable write protect for address offset 0x 1000 0x1FFF in WP Segment 1 Enable write protect for address offset 0 1000 0 1 in WP Segment x 0 Disable write protect for address offset 0x0000 0x0FFF in WP Segment l 1 Enable write protect for address offset 0x0000 0xOFFF in WP Segment x Appendix B Rabbit 3000 Revisions 289 Ta
13. 000 Timer B Control Register TBCR OxB1 w xxxx0000 Timer B MSB 1 Register TBMIR 0xB2 Timer B LSB 1 Register TBLIR OxB3 W XXXXXXXX Timer B MSB 2 Register TBM2R OxB4 Timer B LSB 2 Register TBL2R 0xB5 Timer B Count MSB Register TBCMR OxBE R XXXXXXXX Timer B Count LSB Register TBCLR OxBF R XXXXXXXX 156 Rabbit 3000 Microprocessor User s Manual The control status register for Timer B TBCSR is laid out as shown in Table 11 7 Table 11 7 Timer B Control and Status Register Timer B Control and Status Register TBCSR Address 0 00 0 Bit s Value Description 753 These bits are alwavs read as zero 0 Timer B2 comparator has not encountered a match condition 1 Timer B2 comparator has encountered a match condition This status bit and the Timer B2 interrupt but not interrupt enable are cleared by a read of this register 2 0 Timer B2 interrupt disabled write 1 Timer B2 interrupt enabled 0 Timer B1 comparator has not encountered a match condition 2 1 Timer B1 comparator has encountered a match condition This status bit and the Timer interrupt but not interrupt enable are cleared by a read of this register 1 0 Timer B1 interrupt disabled write 1 Timer B1 interrupt enabled 0 Disable the main clock for Timer B 1 Enable the main clock for Timer B The control register for Timer B
14. ADDR write data write strobe read data read strobe chip select strobe External I O Timing with 1 wait state Figure 10 1 External I O Bus Cycles Chapter 10 I O Bank Control Registers 145 Table 10 1 shows how the eight I O bank control registers are organized Table 10 1 I O Bank x Control Register 10 Bank x Control Register IBOCR Address 0x0080 IB1CR Address 0x0081 IB2CR Address 0x0082 IB3CR Address 0x0083 IB4CR Address 0x0084 IB5CR Address 0x0085 IB6CR Address 0x0086 IB7CR Address 0x0087 Bit s Value Description 7 6 00 Fifteen wait states for accesses in this bank 01 Seven walt states for accesses in this bank 10 Three wait states for accesses in this bank 11 One wait state for accesses in this bank 5 4 00 The Ix signal is an I O chip select 01 The Ix signal is an I O read strobe 10 The Ix signal is an I O write strobe 11 The Ix signal is an I O data read or write strobe 0 Writes are not allowed to this bank Transactions are normal in every other way 3 only the write strobe is inhibited 1 Writes are allowed to this bank 0 strobe Ix is active low 2 1 strobe Ix is active high 1 0 These bits are ignored Bit 2 is ignored in versions of the Rabbit 3000 before the Rabbit 3000A 146 Rabbit 3000 Micropr
15. Output Memory Write Enable 1 99 B11 Control BUFEN Output Buffer Enable 42 M4 IORD Output I O Read Enable 41 L4 IOWR Output Write Enable 40 K4 62 Rabbit 3000 Microprocessor User s Manual Table 5 1 Rabbit Pin Descriptions continued Pin Pin Pin Group Pin Name Direction Function Numbers Numbers LQFP TFBGA D7 A8 B8 ports PA 7 0 Input Output I O Port A 111 104 C8 D8 9 B9 C9 ports 5 BS continued PB 7 0 Input Output I O Port B 123 116 C5 05 B6 C6 L11 M11 66 71 74 MI2 L12 PC 7 0 41n 4 Out I O Port C 75 K12 K11 J10 H12 K7 L7 M7 PD 7 0 Input Output I O Port D 52 59 J8 K8 L8 MS JO 26 31 34 H4 J1 J4 PE 7 0 Input Output I O Port E 35 KLLI L2 B3 4 127 124 B4 A10 PF 7 0 Input Output I O Port F 103 100 B10 All 12 M1 2 13 PG 7 0 Input Output I O Port G 9n M3 K9 L9 M9 K10 Power VDDCORE 13 3 8 24 72 D2 E11 H2 processor core 88 J12 Power 1 17 33 AT C10 D6 Processor I O VDDIO 43 3 V 65 81 97 G10 Ring 115 M10 Power Battery AT 3 3 V or battery 51 77 Backup Ground Processor VSSCORE Ground 2929 19 D3 E10 89 Jil Core Ground 16 32 48 A2 C7 C11 Processor I O VSSIO Ground 64 80 96 F2 G11 K2 Ring 112 128 K6 L10 Chapter 5 Pin Assignments and Functions 63 5 4 B
16. 00 PWM LSB 3 Register PWL3R 0x008E W XXXXx00x Quad Decode Control Register QDCR 0x0091 W 00xx0000 00000000 Appendix B Rabbit 3000 Revisions 281 B 1 2 Peripheral and ISR Address Table B 4 Rabbit 3000 I O Address Ranges and Interrupt Service Vectors On Chip Peripheral I O Address Range ISR Starting Address System Management 0 0000 0 000 R 7 1 0 0 00 Memory Management 0x0010 0x001F and 0x0400 0x04FF No interrupts Slave Port 0 0020 0 002 UIR 7 1 0 0 80 Parallel Port A 0 0030 0 0037 interrupts Parallel Port F 0 0038 0 003 interrupts Parallel Port B 0 0040 0 0047 interrupts Parallel Port G 0x0048 0x004F No interrupts Parallel Port C 0 0050 0 0055 interrupts Input Capture 0x0056 0x005F HR 7 1 1 OxAO Parallel Port D 0x0060 0x006F No interrupts Parallel Port E 0x0070 0x007F No interrupts External I O Control 0 0080 0 0087 interrupts Pulse Width Modulator 0x0088 0x008F UIR 7 1 1 0x70 Quadrature Decoder 0x0090 0x0097 UIR 7 1 1 0x90 INTO EIR 0x00 External Int t 0x0098 0x009F xternal Interrupts x INTI EIR 0x10 Timer A 0 00 0 0 00 IIR 7 1 0 0xAO Timer B 0x00B0 0x00BF IIR 7 1 0 OxBO Serial Port A async cks 0 00 0 0 00 7 IIR 7 1 0 0 Serial Port E async HDLC 0 00 8 0 00
17. 218 Rabbit 3000 Microprocessor User s Manual Figure 16 2 and Figure 16 3 illustrate the memory read and write cycles The Rabbit 3000 operates at 2 clocks per bus cycle plus any wait states that might be specified Memory Read no wait states T _ 12 CLK A 19 0 lt Taqr Iess C N gt qf osx gt 1 Tess OEx y To lt gt D 7 0 A 19 0 CSx D 7 0 Figure 16 2 Memory Read and Write Cycles Chapter 16 AC Timing Specifications 219 The following memory read time delays were measured Table 16 3 Memory Read Time Delays Output Capacitance Time Delay 30pF 60pF 90pF Max clock to address delay 6 ns 8 ns 11 ns Max clock to memory chip select delay Tcsx 6 ns 8 ns 11 ns Max clock to memory read strobe delay 6 ns 8 ns 11 ns Min data setup time 1 ns Min data hold time Ons The measurements were taken at the 50 points under the following conditions e T 40 C to 85 C V 3 3 V e Internal clock to nonloaded CLK pin delay lt 1 ns 85 C 3 0 V The following memory write time delays were measured Table 16 4 Memory Write Time Delays Output Capacitance Time Delay 30 pF 60pF 90 pF Max clock to address delay 6 ns 8 ns 11 ns Max clock to memory chip select delay Tcsx 6 ns 8 ns
18. Clocked serial mode with external clock 10 Serial Port A clock is on Parallel Port PB1 Serial Port B clock is on Parallel Port PBO Clocked serial mode with internal clock 11 Serial Port A clock is on Parallel Port PB1 Serial Port B clock is on Parallel Port PBO 1 0 00 The Serial Port interrupt is disabled 01 The Serial Port uses Interrupt Priority 1 10 The Serial Port uses Interrupt Priority 2 Chapter 12 Rabbit Serial Ports 173 Table 12 15 Serial Port Control Register Ports C and D Serial Port x Control Register SCCR Address 0xE4 SDCR Address 0xF4 Bit s Value Description 00 No operation These bits are ignored in the async mode 01 In clocked serial mode start a byte receive operation 7 6 10 In clocked serial mode start a byte transmit operation T In clocked serial mode start a byte transmit operation and a byte receive operation simultaneously 0 Enable the receiver input 5 1 Disable the receiver input 4 x This bit is ignored 00 Async mode with 8 bits per character 01 Async mode with 7 bits per character In this mode the most significant bit of a byte is ignored for transmit and is always zero in receive data Clocked serial mode with external clock 3 2 10 Serial Port C clock is on Parallel Port PF1 Serial Port D clock is on Parallel Port PFO Clocked serial mode with internal clock 11 Serial Port C clo
19. Global Power Save Control Register GPSCR Address 0x000D Bit s Value Description 7 5 000 Self timed chip selects disabled 001 This bit combination is reserved and should not be used 010 This bit combination is reserved and should not be used 011 This bit combination is reserved and should not be used 100 296 ns self timed chip selects 192 ns best case 457 ns worst case 101 234 ns self timed chip selects 151 ns best case 360 ns worst case 110 171 ns self timed chip selects 111 ns best case 264 ns worst case 111 109 ns self timed chip selects 71 ns best case 168 ns worst case 0 Normal Chip Select timing for read cycles ki 1 Short Chip Select timing for read cvcles not available in full speed 0 Normal Chip Select timing for write cycles 1 Short Chip Select timing for write cycles not available in full speed 2 0 000 The 32 kHz clock divider is disabled 001 This bit combination is reserved and should not be used 010 This bit combination is reserved and should not be used 011 This bit combination is reserved and should not be used 100 32 kHz oscillator divided by two 16 384 kHz 101 32 kHz oscillator divided by four 8 192 kHz 110 32 kHz oscillator divided by eight 4 096 kHz 111 32 kHz oscillator divided by sixteen 2 048 kHz Appendix B Rabbit 3000 Revisions 299 B 1 12 1 Clock Select and Power Save Modes Table B 24 outlines the power save modes available in the Rabbit 3000A T
20. Chapter 16 AC Timing Specifications 223 The following factors have to be taken into account when calculating the output enable access time required The gross output enable access time is T minimum clock low time it is assumed that the early output enable option is enabled This is reduced by the spectrum spreader loss the time from clock to output for the output enable signal the data setup time and a correction for the asymmetry of the original oscillator clock Example Th Clock 29 49 MHz 34 ns operating voltage is 3 3 V the clock doubler has a nominal delay of 16 ns resulting in a minimum clock low time of 12 8 ns the spectrum spreader is on in normal mode resulting in a loss of 3 ns clock to output enable is 5 ns assuming 20 pF load the clock asymmetry is 52 48 resulting in a loss of 4 of the clock period or 1 4 ns e output enable access time is given by access time T min clock low clock to output enable spreader delay asymmetry delay data setup time 34 ns 12 8 ns 5 ns 3 ns 1 36 ns 1 ns 36 5 ns 224 Rabbit 3000 Microprocessor User s Manual 16 2 I O Access Time Figure 16 6 illustrates the I O read and write cycles External I O Read one programmed wait state T1 gt lt Tw gt lt T2 gt ad LI LI LI A 15 0 ICSx gt Tesx Tes IOCSx Y y gt Tlocsx Tocs lt NORD
21. O O O O O oc RS X Operation A HL CF IX d CF IY d CF n CF r CF HL IX d IY d n r HL IX d IY d pp p p p p pp p pr mm m m m m H HL IX4d rY d gt p p p p p Chapter 19 Rabbit Instructions 255 CP m CP r OR HL OR IX d OR IY d OR n OR r SBC IX d SBC IY d SBC A HL SBC A n SBC A r SUB HL SUB IX d SUB IY d SUB n SUB r XOR HL XOR IX4d XOR IY d XOR n XOR r N amp WU Ul NM g HO WU UN UO ON KF UD o f f fr fr fr fr fr fr fr fr fr fr fr fr fr fr fr fr fr fr fr s F FH HF HF S LO A frs LO amp amp amp n amp r LO LO A n A r LO HL LO IX d LO 1 KLO KLO V IX d CY V IY d CY V HL V A n CY cout if r CY gt A V A r CY cout if r CY gt A A A HL V IX d V V A A r LO A amp HL l A amp HL A amp IX d l A IY d A amp n A amp r SBC and CP instruction output inv
22. PFDCR_ ome 140 serial port control registers tion for numerous peripher PEDDR u ai 140 173 174 175 sen ri 278 PEDR 140 serial port data registers 168 expanded low power capabili cete 140 serial port extended asynchro Ty ac ste bas 278 PGCR 143 144 nous registers 176 external I O interface enhance PGDCR mens 143 serial port extended registers MONS 278 PGDDR ede 143 clocked serial mode 177 ID registers for version 278 PODR a nisin gies 143 serial port HDLC mode ex integrated Schmitt trigger 278 PGPR 143 tended registers 178 internal I O address space 278 PWLOR 314 serial port HDLC mode status interrupt after I O with short 314 registers 172 CSx enabled bug fix 278 PWL2R PWL3R 314 serial port long stop registers IrDA bug fix 278 PWLXZR 103 169 LDIR LDDR with wait states PWMXR 103 serial port status registers 170 bus fi sisien 278 PER ise 67 SESR 167 memory protection 278 110 113 316 SPAR nentes 167 multiply add and multiply 110 112 SEER 167 subtract sristi nii 278 QDCXHR 316 SEDR eee eis 167 parallel port alternate func QDEXR eee 110 113 SPER xs ee 167 TODS aie sees
23. ARXF yes PGO TCLKF TCLKF ARCLKF Introduced with Rabbit 3000A chip 66 Rabbit 3000 Microprocessor User s Manual The alternate output functions identified in Table 5 2 are configured by setting the appro priate bits in the Paralle Port x Function Register Table 5 3 Parallel Port x Alternate Functions Parallel Port x Function Register PCFR Address 0x0055 PDFR Address 0x0065 PEFR Address 0x0075 PFFR Address 0x003D PGFR Address 0x004D Bit s Value Description 0 The corresponding port bit functions normally The corresponding port bit carries its alternate signal as an output See Table 5 4 70 1 below Only the bits that have alternate functions listed in Table 5 4 actually have a control bit in these registers That is there are four in Port C four in Port D eight in Port E four in Port E and eight in Port G Table 5 4 Parallel Port x Alternate Functions Control Bits Alternate Output Function Bit Port B Port G Port D Port E Port F Port G 7 SLAVEATTN IA5 APWM3 17 PWM3 APWMI 6 IA4 TXA ATXA 16 PWM2 TXE 5 IA3 APWM2 I5 PWMI RCLKE 4 IA2 TXB ATXB 14 PWMO TCLKE 3 APWMO 2 IAO TXC D TXF 1 CLKA RCLKF 0 CLKB TXD 10 CLKD TCLKF Chapter 5 Pin Assignments and Functions 67 5 6 DC Characteristics Table 5 5 Rabbit 3000 Absolute Maximum Ratings Symbol Parame
24. EX SP HL old opcode 0 0 3 opcode 0x0ED 0x054 Chapter 20 Differences Rabbit vs Z80 Z180 Instructions 261 The following instructions use different register names LD A EIR LD EIR A was I register LD IIR A LD A IIR was R register The following Z80 Z180 instructions have been dropped and are not supported Alterna tive Rabbit instructions are provided Z80 Z180 Instructions Dropped Rabbit Instructions to Use CALL CC ADR JR JP CALL ADR xxx ncc xxx reverse condition TST R HL n PUSH DE PUSH AF AND r HL n POP DE get a in h LD A d POP DE 262 Rabbit 3000 Microprocessor User s Manual 21 INSTRUCTIONS IN ALPHABETICAL ORDER WITH BINARY ENCODING Spreadsheet Conventions ALTD A Column Symbol Key Flag Description ALTD selects alternate flags fr ALTD selects alternate flags and register ALTD selects alternate register ALTD operation is a special case IOI IOE 1 Column Symbol Key Description TOI and IOE affect source and destination and IOE affect destination IOI and IOE affect source Flag Register Key LN Description Sign flag affected Sign flag not affected Zero flag affected Zero flag not affected L V flag contains logical check result L V flag contains arithmetic overflow result od Hn L V flag
25. Register Name Mnemonic Address R W Reset Serial Port A Data Register SADR 0xC0 R W XXXXXXXX Serial Port A Address Register SAAR 0 1 Serial Port A Long Stop Register SALR 0xC2 w XXXXXXXX Serial Port A Status Register SASR 0xC3 R 0xx00000 Serial Port A Control Register SACR 0xC4 000000 Serial Port A Extended Register SAER 0xC5 W 00000000 Table 12 3 Serial Port B Registers Register Name Mnemonic Address R W Reset Serial Port B Data Register SBDR OxDO R W XXXXXXXX Serial Port B Address Register SBAR OxD1 w XXXXXXXX Serial Port B Long Stop Register SBLR 0xD2 Serial Port B Status Register SBSR 0xD3 R 0xx00000 Serial Port B Control Register SBCR 0 4 w xx000000 Serial Port B Extended Register SBER OxD5 W 00000000 Table 12 4 Serial Port C Registers Register Name Mnemonic Address R W Reset Serial Port C Data Register SCDR OxEO R W XXXXXXXX Serial Port C Address Register SCAR 0 1 Serial Port C Long Stop Register SCLR OxE2 Serial Port C Status Register SCSR OxE3 R 0xx00000 Serial Port C Control Register SCCR OxE4 w xx000000 Serial Port C Extended Register SCER 0 5 W 00000000 166 Rabbit 3000 Microprocessor User s Manual Table 12 5 Serial Port D Registers Register Name
26. Rx Read the data from the SADR or SAAR Serial Port A Tx Write data to the SADR SAAR SALR or write a dummy byte to the SASR Rx Read the data from the SBDR or SBAR Serial Port B Tx Write data to the SBDR SBAR SBLR or write a dummy byte to the SBSR Rx Read the data from the SCDR or SCAR Serial Port C Tx Write data to the SCDR SCAR SCLR or write a dummy byte to the SCSR Rx Read the data from the SDDR or SDAR Lowest Serial Port D Tx Write data to the SDDR SDAR SDLR or write a dummy byte to the SDSR Appendix C System User Mode 325 C 4 Using the System User Mode The System User mode is designed to work with new features in the Rabbit 3000A memory protection stack protection etc to provide a seamless framework for protection of critical code However there are many levels at which the System User mode can be used some examples are described here C 4 1 Memory Protection Only At the beginning of the user program all necessary peripherals are enabled all peripheral interrupts to be used are set up for the User mode critical memory regions are protected stack limits are set and the various system memory stack violation interrupts are enabled The processor then enters the User mode and remains in the User mode for all operations interrupts can be handled however the user desires Obviously the critical interrupts can be handled in the System mode but at that point the device
27. The Rabbit 3000 Designer s Handbook has a chapter on the Rabbit BIOS with more details 17 2 Virtual Driver The Virtual Driver is compiled with the user s application It includes support for the fol lowing services e Hitting the hardware watchdog timer e Decrementing software watchdog timers e Synchronizing the system timer variables with the real time clock and keeping them updated e Driving uC OS II multi tasking e Driving slice statement multi tasking 17 2 1 Periodic Interrupt The periodic interrupt that drives the Virtual Driver occurs every 16 clocks or every 488 us If the 32 768 KHz oscillator is absent it is possible to substitute a different periodic interrupt This alternative is not supported by Rabbit Semiconductor since the cost of con necting a crystal is very small The periodic interrupt keeps the interrupts turned off that is the processor priority is raised to 1 from zero for about 75 clocks so it contributes lit tle to interrupt latency The periodic interrupt is turned on by default before main is called It can be disabled if needed The Dynamic C Users s Manual chapter on the Virtual Driver provides more details on the periodic interrupt The Rabbit 3000 microprocessor requires the 32 kHz oscillator in order to boot via Dynamic C unless a custom loader and BIOS are used 17 2 2 Watchdog Timer Support A microprocessor system can crash for a variety of reasons A software bug or an electri
28. enne enne eene nennen nnn 91 7 8 Watchdog rice Ae eU eee hee tere u A e 93 TO System once eR ORPHEO gre REC Ure EE ted 95 7 10 Rabbit Interrupt Structure siete ete tete e 97 7 10 1 External Interrupts o u nete e e o rare P terrae 99 7 10 2 Interrupt Vectors INTO EIR OxOO INTI 0 08 100 1 11 Bootstrap Operation eee enge EIE I Se PRI E ep REOR 101 7 12 Pulse Wadth Modulatot i ise fee eee tod o l ied eed 103 1 18 Input Capture y Hag eI HERRERA eR ERREUR 105 7 314 Quadr ature Decoder orte eme etre e I er OH Ute tn ees 110 Chapter 8 Memory Interface and Mapping 115 8 1 Interface for Static Memory Chips terere etr i bee EE 115 8 2 Memory Mapping Overview a ener 117 8 3 Memory Mapping Unita nee e et dee e eene disiecta 117 Rabbit 3000 Microprocessor User s Manual 8 4 Memory Interface Unit otiose entree e ED stade ie 119 8 5 Memory Bank Control Registers 120 8 5 1 Optional A16 A19 Inversions by Segment CS1 Enable eee 121 8 6 Allocation of Extended Code and Data n 124 8 7 Instruction and Data Space SUppOTt mens eene eene nennen nennen emen sms 125 8 8 How the Compiler Compiles to Memory sess ener ene 128 Chapter 9 Parallel Ports 129 9 1 Parallel Port Az seien HERE PP GN
29. pins PG4 and PGS on Parallel Port G 00 The serial port interrupt is disabled 01 The serial port uses Interrupt Priority 1 1 0 10 The serial port uses Interrupt Priority 2 11 The serial port uses Interrupt Priority 3 Chapter 12 Rabbit Serial Ports 175 Table 12 17 Extended Register Asynchronous Mode AII Ports Serial Port x Extended Register SAER Address 0xC5 SBER Address 0xD5 SCER Address 0xE5 SDER Address 0xF5 SEER Address 0xCD SFER Address 0xDD Bit s Value Description Async mode only 7 5 XXX These bits are ignored in async mode 0 Normal async data encoding 4 1 Enable RZI coding 3 16ths bit cell IIDA compliant 0 Normal Break operation This option should be selected when address bits are expected 3 1 Fast Break termination At the end of Break a dummy character is written to the buffer and the receiver can start character assembly after one bit time 0 Async clock is 16X data rate 2 1 Async clock is 8X data rate 1 0 xx These bits are ignored in async mode 176 Rabbit 3000 Microprocessor User s Manual Table 12 18 Extended Register Clocked Serial Mode Ports A D only Serial Port x Extended Register SAER Address 0xC5 SBER Address 0xD5 SCER Address 0xE5 SDER Address 0xF5 Bit s Value Description Clocked serial mode only 0 Normal clocked serial
30. sasa 215 stack protection 291 system clock 12 system management 282 System User mode 285 319 addresses 322 interrupts 323 interrupt prioritization 324 Iegisters eee eee 321 326 complete operating system uay eH 328 memory protection 326 mixed operation 327 T time date clock 3 91 mers iere 149 Timer A 150 151 Timer 156 timing quadrature decoder 317 short chip select 301 302 303 304 305 306 Wes 5i cun ene 307 308 309 310 311 312 W watchdog timer 93 secondary watchdog timer 294 writes short chip select timing 299 X XPC register 26 340 Rabbit 3000 Microprocessor User s Manual
31. Control Instructions Jumps and Calls on page 259 Miscellaneous Instructions on page 259 Privileged Instructions on page 260 Instructions in Alphabetical Order With Binary Encoding on page 263 Chapter 19 Rabbit Instructions 249 Spreadsheet Conventions ALTD A Column Symbol Key Flag Description f ALTD selects alternate flags fr ALTD selects alternate flags and register r ALTD selects alternate register s ALTD operation is a special case IOI IOE 1 Column Symbol Key Flag Description b IOI and IOE affect source and destination d IOI and IOE affect destination s IOI and IOE affect source Flag Register Key S Z LVv c Description Sign flag affected Sign flag not affected Zero flag affected Zero flag not affected L LV flag contains logical check result flag contains arithmetic overflow result 0 LV flag is cleared LV flag is affected Carry flag is affected Carry flag is not affected 0 Carry flag is cleared 1 Carry flag is set The L V logical overflow flag serves a dual purpose L V is set to 1 for logical operations if any of the four most significant bits of the result are 1 and L V is reset to 0 if all four of the most significant bits of the result are 0 250 Rabbit 3000 Microprocessor User s Manual Symbols
32. HL I6 01 0 CY HL 7 IX d IX d 6 0 0 IX d 7 IY d I d 6 01 0 CY IY d 7 Chapter 19 Rabbit Instructions 257 SLA r 4 fr L x r 6 0 0 CY r 7 SRA HL 10 f b 1 HL HL 7 HL 17 11 CY HL 0 SRA IX4d 13 f b L IX d IX d 7 IX d 7 1 CY 0 SRA IY d 13 f b L IY d IY d 7 7 11 CY I d 0 SRA r 4 fr L x r 7 r 7 1 CY rlol SRL HL 10 f b L HL 0 HL 7 1 CY HL 0 SRL IX d 13 f b 1 IX d 0 zX d 7 1 CY IX d 0 SRL IY4d 13 f b L 0 rY d 7 11 IY d 0 SRL r 4 fr L xr 0 r 7 1 cy r 0 19 15 Instruction Prefixes Instruction A ISZVC Operation ALTD 2 alternate register destinatin for next Instruction IOE 2 I O external prefix IOI 2 I O internal prefix 19 16 Block Move Instructions Instruction A ISZVC Operation LDD 10 4 DE HL BC BC 1 DE DE 1 HL HL 1 LDDR 647i d if BC l 0 repeat LDI 10 d DE HL BC BC 1 DE 1 HL HL 1 LDIR 647i d if BC 0 repeat If any of the block move instructions are prefixed by an I O prefix the destination will be in the specified I O space Add 1 clock for each iteration for the prefix if the prefix is IOI internal I O If the prefix is IOE add 2 clocks plus the number
33. I TsU SWR SRD Slave Port Write Cycle y NT Teu SCS c Th SCS SA1 SAO Tsu SA Th SA SWR _ gt Tw SWR es SD 7 0 Tsu SD SRD Tsu SRD SWR Figure 13 2 Slave Port R W Sequencing Chapter 13 Rabbit Slave Port 201 The following table explains the parameters used in Figure 13 2 Symbol Parameter Tsu SCS SCS Setup Time 5 Th SCS SCS Hold Time 0 Tsu SA SA Setup Time 5 Th SA SA Hold Time 0 Tw SRD SRD Low Pulse Width 40 Ten SRD ISRD to SD Enable Time 0 Ta SRD ISRD to SD Access Time 30 Tdis SRD ISRD to SD Disable Time 15 Tsu SRW SRD SWR High to SRD Low Setup Time 40 Tw S WR SWR Low Pulse Width 40 Tsu SD SD Setup Time 10 Th SD SD Hold Time 5 Tsu SRD SWR SRD High to SWR Low Setup Time 40 The two SPDOR registers have special functionality not shared by the other data registers If the master writes to SPDOR an inbound interrupt flip flop is set If slave port interrupts are enabled the slave processor will take a slave port interrupt If the slave writes to the other SPDOR register the slave attention line SLAVEATTN 100 is asserted driven low by the slave processor This line can be used to create an interrupt in the master Either side that is interrupted can clear the signal
34. IY DE DE CY UMS 2 8 81 1 1 1 15 1 IX 1 IY 1 HL HL 1 repeat while 0 DE HL 1 HL HL 1 eee a repeat while BC 0 a el bs ee LSIDR 2 167 DB 1 DE DE 1 repeat while 0 1 9 1 New UMA UMS Opcodes The new UMA UMS opcodes perform the following operation CY DE HL IX IY DE CY where HL IX and IY increment after each byte repeated BC times This fundamental operation allows the addition or subtraction of two arbitrarily long unsigned integers after one is scaled by a single byte value This operation is common in many cryptographic operations Appendix B Rabbit 3000 Revisions 295 B 1 9 2 New Block Copy Opcodes The LDxR family of block move opcodes has been expanded In the Rabbit 3000 proces sor block copy operations could only be done between memory addresses or from mem ory to an I O address In addition the destination I O address would increment or decrement if using LDDR after each byte making the block copy opcodes effectively useless for repeated reads or writes to a peripheral for example a device on the external I P bus Six new block copy opcodes were added to the Rabbit 3000 revision These opcodes can copy from an I O address as well as to one and either the source or
35. LD IY mn 11111101 00101010 n m 13 s LD SPrn 11111101 11000100 n 11 LD IY HL 11111101 01111101 4 LD IY mn 11111101 00100001 n m 8 LD r HL 01 r 110 5 r s LD r IX d 11011101 O1 r 110 d 9 r s LD r IY d 11111101 O1 r 110 d 9 r s LD r g 01 r g 2 r LD r n 00 r 110 n 4 r LD SP HL 11111001 2 LD SP IX 11011101 11111001 4 LD SP IY 11111101 11111001 4 LD XPC A 11101101 01100111 4 LDD 11101101 10101000 10 d LDDR 11101101 10111000 6 71 d LDI 11101101 10100000 10 d LDIR 11101101 10110000 6 71 d LDP HL HL 11101101 01100100 12 LDP IX HL 11011101 01100100 12 LDP IY HL 11111101 01100100 12 LDP mn HL 11101101 01100101 n m 15 LDP mn IX 11011101 01100101 n m 15 LDP mn IY 11111101 01100101 n m 15 268 Rabbit 3000 Microprocessor User s Manual Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A 152 LDP HL HL 11101101 01101100 10 em ums LDP HL IX 11011101 01101100 10 edm Bere LDP HL IY 11111101 01101100 10 m lu LDP HL mn 11101101 01101101 n m 13 amm LDP mn 11011101 01101101 n m 13 xe LDP IY mn 11111101 01101101 n m 13 c ime LJP nbr mn 11000111 m nbr 10 LRET 11101101 01000101 13 im re MUL 11110111 12 sm a NEG 11101101 01000100 4 fr V NOP 00000000 2
36. LRET RET RET RETI RST v ann i H 10 13 8 2 12 10 Operation SP 1 PCH SP 2 PCL PC mn SP SP 2 B B 1 if B 0 PC PC j PC HL PC IX PC IY if f PC mn PC mn if cc PC PC e PC PC e if e 0 next seq inst is executed SP 1 XPC SP 2 PCH SP 3 PCL PC mn SP SP 3 XPC xpc PC mn PCL SP PCH SP 1 XPC SP 2 SP SP 3 PCL SP PCH SP 1 SP SP 2 if f PCL SP PCH SP 1 SP SP 2 IP SP PCL SP 1 PCH SP 2 SP SP 3 SP 1 PCH SP 2 PCL SP SP 2 R v v 10 18 20 28 38 only 19 18 Miscellaneous Instructions Instruction CCF IPSET IPSET IPSET IPSET IPRES LD A EIR LD A IIR LD A XPC LD EIR A LD IIR A LD XPC A NOP POP IP PUSH IP SCF NBEO clk KKK KP aga PND A fr fr Operation CF CF IP IP 5 0 00 IP 5 0 01 IP IP 5 0 10 IP IP 5 0 11 IP IP 1 0 IPI7 21 A EIR A IIR A MMU EIR IIR Operation SP SP 8 1 SP 1 IP SP SP 1 CF 1 Chapter 19 Rabbit Instructions 259 19 19 Privileged Instructions The privileged instructions are described in this section Privilege means that an interrupt cannot take place between the privileged instruction and the following instruction The three instr
37. RABBIT 3000 AT56C55 A1D2583 0209 Rabbit 3000 Microprocessor User s Manual 019 0108 070831 R Rabbit 3000 Microprocessor User s Manual Part Number 019 0108 070831 R Printed in U S A 2002 2007 Rabbit Semiconductor Inc All rights reserved No part of the contents of this manual may be reproduced or transmitted in any form or by any means without the express written permission of Rabbit Semiconductor Permission is granted to make one or more copies as long as the copyright page contained therein is included These copies of the manuals may not be let or sold for any reason without the express written permission of Rabbit Semiconductor Rabbit Semiconductor reserves the right to make changes and improvements to its products without providing notice Trademarks Rabbit and Dynamic C are registered trademarks of Rabbit Semiconductor Inc Rabbit 3000 is a trademark of Rabbit Semiconductor Inc The latest revision of this manual is available on the Rabbit Semiconductor Web site www rabbit com for free unregistered download Rabbit Semiconductor Inc www rabbit com Rabbit 3000 Microprocessor User s Manual TABLE OF CONTENTS Chapter 1 Introduction 1 1 1 Features and Specifications Rabbit 3000 00 2 1 2 Summary of Rabbit 3000 Advantages enne nennen nennen nennen nnne 6 1 3 Differences Rabbit 3000 vs Rabbit 2000 n eee en
38. RR IY d 11111101 11001011 d 00011110 13 f b L RR DE 11111011 2 fr Lx RR HL 11111100 2 fr L RR IX 11011101 11111100 4 f L RR IY 11111101 11111100 4 f L Chapter 21 Instructions in Alphabetical Order With Binary Encoding 269 Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A 152 RR 11001011 00011 r 4 fr L RRA 00011111 2 fr RRC HL 11001011 00001110 10 f b L RRC IX d 11011101 11001011 d 00001110 13 f b L RRC IY d 11111101 11001011 d 00001110 13 f b L RRC r 11001011 00001 r 4 fr L RRCA 00001111 2 fr RST v 11 111 v 2 3 4 5 7 only 8 SBC IX d 11011101 10011110 d 9 fr s V SBC IY d 11111101 10011110 d 9 fr s V SBC A HL 10011110 fr s v SBC A n 11011110 n 4 fr Vox SBC A r 10011 r 2 fr Vox SBC HL ss 11101101 01550010 4 fr V SCF 00110111 2 1 SET b HL 11001011 11 b 110 10 b SET b IX d 11011101 11001011 d 11 b 110 13 b SET b IY d 11111101 11001011 d 11 b 110 13 b SET b r 11001011 il b r 4 r SLA HL 11001011 00100110 10 f b L SLA IX d 11011101 11001011 d 00100110 13 f b L SLA IY d 11111101 11001011 d 00100110 13 f b L SLA r 11001011 00100 r 4 fr L SRA HL 11001011 00101110 10 f b L SRA IX d 11011101 11001011 d 00101110 13 f b L SRA IY d 11111101 11001011 d 00101110 13
39. Since its release the Rabbit 3000 microprocessor has gone through one revision The revi sion reflects bug fixes improvements and the introduction of new features All Rabbit 3000 revisions are pin compatible and transparently replace previous versions of the chip The Rabbit 3000 has been supplied in the following versions 1 Original Rabbit 3000 Available two packages and identified by for the LQFP package and IZIT for the TFBGA package The LQFP package began shipping in March 2002 and the TFBGA package began shipping in January 2003 There were several bugs a Port A decode bug This bug is documented in TN228 Rabbit 3000 Parallel Port F Bug The problem involves an incomplete address decode of the data output register for Parallel Port A If Parallel Port A is used as an output or is used as the bidirectional bus for the slave port then writing to any of the Paral lel Port F registers will cause a spurious write to the Parallel Port A register b LDIR LDDR with wait states This bug is documented in Section 19 16 The nature of the problem is such that first iteration of LDIR LDDR uses the cor rect number of wait states for both the read and the write However all subse quent iterations use the number of waits programmed for the memory located at the write address for both the read and the write cycles This becomes a problem when moving a block of data from a slow memory device requiring wait states to a fa
40. Use of the Programming Port as a Diagnostic Setup Port sese 272 A2 Alternate Programming Port una sana tinte tee tete tete ete i teorie 272 Suggested Rabbit Crystal Frequencies n 273 Appendix B Rabbit 3000 Revisions 275 B 1 Discussion of Fixes and Improvements 0 sese enne nennen nennen nennen 278 B 1 1 Rabbit Internal I O Registers 279 B 1 2 Penpberaland ISR Address Cu u ep RUE Gere A 282 B 1 3 Revision Level ID Register asa au su sub umumi aaa hiaan nennen 284 B 1 4 System User Mode mete pre ei HE pe Pt re etit iens 285 B 1 5 Memory Protection a u ett qe e de reete Ee snd e ri Eee bush RETE PNE eee 286 B 1 6 Stack Protection oer rne e I ee eere E een Ee PA ee ete rape e 291 B 1 7 RAM Segment Relocation Sies ie e a EEUU ERU eee RE 293 B 1 8 Secondary Watchdog Timer essent ener 294 B 1 9 New Opcodes uenire hte mrt ROTER Febr End rt sod D ve sed eer p eH Oe 295 B 1 10 Expanded I O Memory Addressing LL essere nennen 297 B 1 11 External I O Improvements Ta 298 B 1 12 Short Chip Select Timing for Writes 299 B 1 13 Pulse Width Modulator Improvements n 313 B 1 14 Quadrature Decoder
41. clock on timer B1 11 clock on timer B2 11 clock on timer B2 Chapter 9 Parallel Ports 135 The following registers are described in Table 9 8 and in Table 9 9 e PDDR Parallel Port D data register Read Write e PDDDR Parallel Port D data direction register 1 makes the corresponding pin output Write only e PDDCR Parallel Port D drive control register A 0 makes the corresponding pin a regular output A 1 makes the corresponding pin an open drain output Write only e PDFR Parallel Port D function control register This port may be used to make port positions 4 and 6 be serial port outputs Write only e PDBxR These eight registers may be used to set outputs on individual port positions e PDCR Parallel Port D control register This register is used to control the clocking of the upper and lower nibble of the final output register of the port On reset bits 0 1 4 and 5 are reset to zero 136 Rabbit 3000 Microprocessor User s Manual 9 5 Parallel Port E Parallel Port E shown in Figure 9 2 has eight I O pins that can be individually pro grammed as inputs or outputs PE7 is used as the slave port chip select when the slave port is enabled Each of the port E outputs can be configured as an I O strobe In addition four of the port E lines can be used as interrupt request inputs The output registers are cas caded and timer controlled making it possible to generate precise
42. l Driver optional open drain Timer A1 Timer B1 Timer B2 perclk 2 Timer A1 Timer B1 Timer B2 Figure 9 1 Parallel Port D Block Diagram 134 Rabbit 3000 Microprocessor User s Manual Table 9 8 Parallel Port D Register functions Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDIS PD7 PD6 PD5 PD4 PD3 PD2 PDI PDO adr 0x060 PDDCR W out out out out out out out out adr 0x066 open open open open open open open open drain drain drain drain drain drain drain drain PDFR W adr 0x065 x alt TXA x alt TXB x x x x PDDDR W dir dir dir dir dir dir dir dir adr 0x067 out out out out out out out out PDBOR W x x x x x x x PD0 adr 0x068 PDBIR W x x x x x x PDI x adr 0x069 PDB2R W x x x x x PD2 x x adr 0 06A PDB3R W X x x x PD3 x x x adr 0 06 PDB4R W x x x PD4 x x x x adr 0x06C PDBSR W x x PD5 x x x x x adr 0x06D PDB6R W x PD6 x x x x x x adr 0 06 PDB7R W PD7 x x x x x x x adr 0 06 Table 9 9 Parallel Port D Control Register adr 0x064 Bits 7 6 Bits 5 4 Bits 3 2 Bits 1 0 00 clock upper nibble on pclk 2 00 clock lower nibble on pclk 2 01 clock on timer A1 01 clock on timer Al 10 clock on timer B1 e 10
43. ters named SPDOR SPDIR and SPD2R can be written by the master and read by the slave Three different registers also named SPDOR SPDIR and SPD2R can be written by the slave and read by the master The same names are used for different registers since it is usually clear from the context which register is meant If it is necessary to distinguish between registers we will refer to the registers as SPDOR writable by the slave or SPDOR writable by the master A status register can be read by either the slave or the master The status register has full empty bits for each of the six registers A data register is considered full when it is written to by whichever side is capable of writing to it If the same register is then read by either side it is considered to be empty The flag for that register is thus set to a 1 when the reg ister is written to and the flag is set to a 0 when the register is read 200 Rabbit 3000 Microprocessor User s Manual The registers appear to be internal I O registers to the slave To the master at least for a Rabbit master the registers appear to be external I O registers The figure below shows the sequence of events when the master reads writes the slave port registers Slave Port Read Cycle SCS X3 y lt gt Tsu SCS lt gt Th SCS SA1 SAO gt 4 Tsu SA lt gt Th SA ISRD S gt Tw SRD SD 7 0 Ten SRD 1 1 Tdis SRD I Ta SRD SWR
44. 0 0 Serial Port A async cks UIR 7 1 0 0 Serial Port E async hdlc IIR 7 1 1 OxCO Serial Port B async cks IIR 7 11 0 OxDO Serial Port F async hdlc IIR 7 1 1 OxDO Serial Port C async cks IIR 7 11 0 OxEO Serial Port D async cks UIR 7 1 0 OxFO RST 10 instruction UIR 7 1 0 0x20 RST 18 instruction UIR 7 1 0 0x30 RST 20 instruction IIR 7 1 0 0x40 RST 28 instruction IIR 7 11 0 0x50 RST 38 instruction UIR 7 1 0 0x70 Rabbit 3000 Microprocessor User s Manual 6 1 Default Values for all the Peripheral Control Registers The default values for all of the peripheral control registers are shown in Table 6 2 The registers within the CPU affected by reset are the Stack Pointer SP the Program Counter PC the IIR register the EIR register and the IP register The IP register is set to all ones disabling all interrupts while all of the other listed CPU registers are reset to all zeros Table 6 2 Rabbit Internal I O Registers Register Name Mnemonic I O Address R W Reset Global Control Status Register GCSR 0x00 R W 11000000 Global Clock Modulator 0 Register GCMOR Ox0A w 00000000 Global Clock Modulator 1 Register GCMIR 0x0B 00000000 Global Power Save Control Register GPSCR 0x0D w 00
45. 01 DE 10 HL 11 SP Restart address select 2 010 0 0020 011 0x0030 100 0x0040 101 0x0050 111 0x0070 xx xx Word register select 00 BC 01 DE 10 IX 11 SP 264 Rabbit 3000 Microprocessor User s Manual Rabbit Z180 Meaning yy yy Word register select 00 BC 01 DE 10 Z IY 11 SP Word register select 00 BC 01 DE 10 HL 11 AF Logical zero if all four of the most significant bits of the result are O Logical one if any of the four most significant bits of the result are 1 Chapter 21 Instructions in Alphabetical Order With Binary Encoding 265 Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A ISZVC ADC A HL 10001110 5 fr s V ADC A IX d 11011101 10001110 d 9 fr sk ADC A IY d 11111101 10001110 d 9 fr sk ADC A n 11001110 n 4 fr V ADC A r 10001 r 2 fr k V ADC HL ss 11101101 01ss1010 4 fr V ADD A HL 10000110 5 fr XV ADD A IX d 11011101 10000110 d 9 fr sk ADD A IY d 11111101 10000110 d 9 fr sk ADD A n 11000110 n 4 fr ADD A r 10000 r 2 fr ADD HL ss 00551001 2 fr ADD IX xx 11011101 00 1001 4 ADD IY yy 11111101 00 1001 4 ADD SP d 00100111 d 4 ALTD 01110110 2 AND HL 10100110 5 fr LO AND IX d 11011101 10100110 d 9 fr s L0 AND IY d 11111101 10100110 d 9
46. 2 0 Normal timing for OEOB rising edge to rising edge one clock minimum 1 Extended timing for OEOB one half clock earlier than normal 1 0 Normal timing for WE1B rising edge to falling edge one and one half clocks minimum 1 Extended timing for WE1B falling edge to falling edge two clocks minimum 0 0 Normal timing for WEOB rising edge to falling edge one and one half clocks minimum Extended timing for WEOB falling edge to falling edge two clocks minimum Chapter 8 Memory Interface and Mapping 123 The Breakpoint Debug controller allows the RST 28 instruction to be used as a software breakpoint Normally the RST 28 Instruction causes a call to a particular location in mem ory but the operation of this instruction is modified when the breakpoint debug feature is enabled The RST 28 instruction is treated as a NOP in the breakpoint debug mode Table 8 7 Breakpoint Debug Control Register BDCR adr 0x01C Breakpoint Debug Control Register BDCR Address 0x01C Bit s Value Description 7 0 Normal RST 28 operation 1 RST 28 is NOP 6 0 These bits are reserved and should not be used 8 6 Allocation of Extended Code and Data The Dynamic C compiler compiles code to root code space or to extended code space Root code starts in low memory and compiles upward Allocation of extended code starts above the root code and data Allocation normally con tinues to t
47. Address 0x0085 IB6CR Address 0x0086 IB7CR Address 0x0087 Bit s Value Description 7 6 00 Fifteen wait states for accesses in this bank 01 Seven wait states for accesses in this bank 10 Three walt states for accesses in this bank 11 One wait state for accesses in this bank 5 4 00 The Ix signal is an I O chip select 01 The Ix signal is an I O read strobe 10 The Ix signal is an I O write strobe 11 The Ix signal is an I O data read or write strobe 0 Writes are not allowed to this bank Transactions are normal in every other way 3 only the write strobe is inhibited 1 Writes are allowed to this bank 0 Active Low Ix signal 2 1 Inverted active High Ix 0 Normal I O Transaction timing 1 1 Shorten read strobe by one clock cycle Transaction length remains the same 0 Use I O bus if enabled 0 1 Always use memory data bus 298 Rabbit 3000 Microprocessor User s Manual B 1 12 Short Chip Select Timing for Writes The Rabbit 3000 provided the ability to produce shorter chip select strobes for reads when in a reduced speed mode A new feature has been added to produce short chip select strobes for writes as well and can be controlled by the GPCSR register The new control bit for the short chip selects are listed in Table B 22 NOTE Bit 3 was always written with zero in the original Rabbit 3000 chip Table B 22 Global Power Save Control Register
48. IXL SP n 1 SP n IYL SP n 1 L SP n H SP n 1 IXL SP n IXH SP n 1 IYL SP n SP n 1 IX d L IX d 1 H L IX d IX d 1 L IY d 1 H IY d 1 IXH IYH 252 Rabbit 3000 Microprocessor User s Manual B C D E H L A 19 5 16 bit Load and Store 20 bit Address Instruction clk LDP HL HL 12 LDP IX HL 12 LDP IY HL 12 LDP HL HL 10 LDP HL IX 10 LDP HL IY 10 LDP mn HL 15 LDP mn IX 15 LDP mn IY 15 LDP HL mn 13 LDP IX mn 13 LDP IY mn 13 A I s V C Operation HL L HL 1 H Adr 19 16 A 3 0 IX L 1 H Adr 19 16 A 3 0 IY L IY 1 H Adr 19 16 A 3 0 L HL H HL 1 Adr 19 16 A 3 0 L IX H IX41 Adr 19 16 A 3 0 L IX H IY 1 Adr 19 16 A 3 0 mn L mn 1 H Adr 19 16 A 3 0 mn IXL mn 1 IXH Adr 19 16 A 3 0 mn IYL mn 1 IYH Adr 19 16 A 3 0 L mn mn41 Adr 19 16 A 3 0 mn IXH mn 1 Adr 19 16 A 3 0 IYL mn mn 1 Adr 19 16 A 3 0 Note that the LDP instructions wrap around on a 64K page boundary Since the LDP instruc tion operates on two byte values the second byte will wrap around and be written at the start of the page if you try to read or write across a page boundary Thus if you fetch or store
49. If no write cycles are in progress the reset takes effect immediately The reset sequence requires a minimum of 128 cycles of the fast oscillator to complete even if no write cycles were in progress at the start of the reset Reset forces both the processor clock and the peripheral clock in the divide by eight mode Note that if the processor is being clocked from the 32 kHz clock the 128 cycles of the fast oscillator will probably not be sufficient to allow any writes in progress to be completed before the reset sequence completes and the clocks switch to divide by eight mode During reset CS1 is high impedance and all of the other memory and I O control signals are held inactive High After the RESET signal becomes inactive High the processor begins fetching instructions and the memory control signals begin normal operation Note that the default values in the Memory Bank Control Registers select four wait states per access so the initial program fetch memory reads are 48 clock cycles long 8 x 2 4 Software can immediately adjust the processor timing to whatever the system requires CS1 is high impedance during reset and during power down when only VBAT is pow ered to allow an external RAM connected to CS1 to be powered by VBAT This is possi ble because the CS1 pin is powered by VBAT In this case an external pull up resistor to VBAT is required on CS1 to keep the RAM deselected during power down If the exter nal RAM conn
50. OF Os O lt m 0 f ul lb d I Figure 5 4 Ball Grid Array Pinout Looking Through the Top of Package 59 Chapter 5 Pin Assignments and Functions Table 5 2 Ball and Land Size Dimensions 5 2 2 Mechanical Dimensions and Land Pattern Nominal Ball Tolerance Nominal Land Land EE Ball Pitch ee Diameter Variation Diameter Variation mm mm mm mm mm 0 3 0 35 0 25 0 8 0 25 0 25 0 20 The design considerations in Table 5 3 are based on 5 mil design rules and assume a single conductor between solder lands Table 5 3 Design Considerations all dimensions in mm Key Feature Recommendation A Solder Land Diameter 0 254 0 010 B NSMD Defined Land Diameter 0 406 0 016 C Land to Mask Clearance min 0 050 0 002 D Conductor Width max 0 127 0 005 E Conductor Spacing typ 0 127 0 005 F Via Capture Pad max 0 406 0 016 G Via Drill Size max 0 254 0 010 ale Land and Trace 60 Rabbit 3000 Microprocessor User s Manual BOTTOM VIEW TOP VIEW O O O O OO O O O O Ofc O O O O O OJ O O O O OOOD OOOOPO O O 0000 O 000000 0 0000 Kk O O OOOO 0000 01 OO00000 000 Q9 Q ttm O a I x gt gt 0 80 10 00 0 05 L Ball Pitch 0 80 Ball Diameter 0
51. RR HL RR IX RR IY SBC HL ss A A ANN fr fr fr fr fr H Pee ee IY IY yy yy BC DE IY SP SP SP d 4 0 to 255 HL HL amp DE IX IX amp DE IY IY amp DE if HL 0 HL 1 set flags to match HL if IX 0 IX 1 if IY 0 IY 1 IX 1 IY 1 ss ss 1 ss BC DE HL SP IX IX 1 IY TY 1 ss ss 1 ss BC DE HL SP HL BC BC DE signed 32 bit result DE unchanged HL HL DE bitwise or IX IX DE IY IY DE DE CY left shift with CF HL CX CY HL ix cv CY IX Iv cx cv iv HL HL ss Cy cout if gt 1 19 10 8 bit Arithmetic and Logical Ops Instruction ADC A HL ADC A IX d ADC A IY d ADC A n ADC A r ADD A HL ADD A IX d ADD A ADD A n ADD A r AND HL AND IX4d AND IY d AND n AND r CP HL CP IX d CP IY d O Ul N g O WO N gB N PF O 0 A fr fr fr fr fr fr fr fr fr fr fr fr fr fr fr m m m H m mm t 0 FN 90 FP RPRPP RP lt q lt q lt lt lt lt lt lt lt lt Q
52. but that have 5 V tolerant inputs and are available from many suppli ers True level translating parts are available with separate 3 3 V and 5 V supply pins but these parts are not usually needed and have design traps involving power sequencing Many charge pump chips that perform DC to DC voltage conversion at low cost have been introduced in recent years These are convenient for systems with dual voltage requirements 2 2 2 Serial Ports There are six serial ports designated ports A B C D E and F All six serial ports can operate in an asynchronous mode up to a baud rate equal to the system clock divided by 8 The asynchronous ports use 7 bit or 8 bit data formats with or without parity A 9th bit address scheme where an additional bit is set or cleared to mark the first byte of a mes sage is also supported The serial port software driver can tell when the last byte of a message has finished trans mitting from the output shift register correcting an important defect of the Z180 This is Chapter 2 Rabbit 3000 Design Features 11 important for RS 485 communication because a half duplex line driver cannot have the direction of transmission reversed until the last data bit has been sent In many UARTs including those on the Z180 it is difficult to generate an interrupt after the last bit is sent A so called address bit can be transmitted as either high or low after the last data bit The address bit if used is followed by a h
53. does not disable the watchdog timer Only a sequence of two writes where the first write is 0x54 0x51 0x52 or 0x53 followed by a write of 0x54 actually disables the watchdog timer The watchdog timer will be re enabled by any other write to this register c Normal clocking 32 kHz oscillator for the watchdog timer This is the condition after reset The code to do this may also hit the watchdog with a 0 25 second period to speed up the reset Such watchdog code must be written so that it is highly unlikely that a crash will incorporate the code and continue to hit the watchdog in an endless loop The following suggestions will help 1 Place a jump to self before the entry point of the watchdog hitting routines This pre vents entry other than by a direct call or jump to the routine 2 Before calling the routine set a data byte to a special value and then check it in the rou tine to make sure the call came from the right caller If not go into an endless loop with interrupts disabled 3 Maintain data corruption flags and or checksums If these go wrong go into an endless loop with interrupts off 94 Rabbit 3000 Microprocessor User s Manual 7 9 System Reset The Rabbit 3000 contains a master reset Input pin 46 which initializes everything in the device except for the Real Time Clock RTC This reset is delayed until the completion of any write cycles in progress to prevent potential corruption of memory
54. oscillator and to provide an added range of clock frequency adjustability The clock dou bler is controlled via the Global Clock Double Register as shown in Table 7 7 Table 7 7 Global Clock Double Register Global Clock Double Register GCDR Address 0x0F Bit s Value Description 7 4 XXXX Reserved 0000 The clock doubler circuit is disabled 0001 6 ns nominal low time 0010 7 ns nominal low time 0011 8 ns nominal low time 0100 9 ns nominal low time 0101 10 ns nominal low time 0110 11 ns nominal low time 0111 12 ns nominal low time ii 1000 13 ns nominal low time 1001 14 ns nominal low time 1010 15 ns nominal low time 1011 16 ns nominal low time 1100 17 ns nominal low time 1101 18 ns nominal low time 1110 19 ns nominal low time 1111 20 ns nominal low time The clock doubler uses an on chip delay circuit that must be programmed by the user at startup if there is a need to double the clock Table 7 8 lists the recommended delays for the Global Clock Double Register for various oscillator frequencies Table 7 8 Recommended Delays Set In GCDR for Clock Doubler Recommended GCDR Value Frequency Range 15 lt 7 3728 MHz 13 7 3728 11 0592 MHz 9 11 0592 16 5888 MHz 6 16 5888 20 2752 MHz 3 20 2752 52 8384 MHz 0 gt 52 8384 MHz Chapter 7 Miscellaneous Functions 83 When the clock doubler is used and there is no subsequent divisi
55. to level before interrupt took place more interrupts could now take place but receiver data is in registers now handle the rest of the receiver interrupt routine LD HL bufbase 6 LD D O 6 ADD HL DE 2 location to store data LD HL A 6 put awav the data bvte POP DE ed POP HL iod POP AF 27 27 RET 8 from interrupt 117 clocks to here This routine gets the interrupts turned on in about 68 clocks or 3 5 us at a clock speed of 20 MHz Although two characters may be handled out of order this will be invisible to a higher level routine checking the status of the input buffer because all the interrupts will be completed before the higher level routine can perform a check on the buffer status A typical way to organize the buffers is to have an in pointer and an out pointer that incre ment through the addresses in the data buffer in a circular manner The interrupt routine manipulates the in pointer and the higher level routine manipulates the out pointer If the in pointer equals the out pointer the buffer is considered full If the out pointer plus 1 equals the in pointer the buffer is empty All increments are done in a circular fashion most easily accomplished by making the buffer a power of two in length then anding a mask after the increment The actual memory address is the pointer plus a buffer base address 12 9 1 Controlling an RS 485 Driver and Receiver RS 485 uses a half duplex method of communication
56. without disabling interrupts The following sequence is used A bit is a semaphore and the first task to set the bit owns the semaphore and has a right to manipulate the resources associated with the semaphore BIT B HL SET B HL JP z ihaveit here I don t have it The SET instruction has no effect on the flags Since no interrupt takes place after the BIT instruction if the flag is zero that means that the semaphore was not set when tested by the bit instruction and that the set instruction has set the semaphore If an interrupt was allowed between the BIT and set instructions another routine could set the semaphore and two routines could think that they both owned the semaphore 260 Rabbit 3000 Microprocessor User s Manual 20 DIFFERENCES RABBIT vs Z80 Z180 INSTRUCTIONS The Rabbit is highly code compatible with the Z80 and Z180 and it is easy to port non I O dependent code The main areas of incompatibility are instructions that are concerned with or particular hardware implementations The more important instructions that were dropped from the Z80 Z180 are automatically simulated by an instruction sequence in the Dynamic C assembler A few fairly useless instructions have been dropped and cannot be easily simulated Code using these instructions should be rewritten The following Z80 Z180 instructions have been dropped and there are no exact substi tutes DAA HALT DI EI IMO IM 1 IM 2 OUT IN OUTO INO SL
57. 12 7 2 Clocked Serial Timing with External Clock mem nn en eene 185 12 8 Synchronous Communications on Ports E and 187 12 9 Serial Port Software Suggestions 22222 a ente tree Ri tert tette ttes ede edd 192 12 9 1 Controlling an RS 485 Driver and Receiver 2 193 12 9 2 Transmitting Dummy Characters 193 12 9 3 Transmitting and Detecting a Break 194 12 9 4 Using Serial Port to Generate a Periodic Interrupt 194 12 9 5 Extra Stop Bits Sending Parity 9th Bit Communication Schemes sess 194 12 9 6 Parity Extra Stop Bits with 7 Data Bit Characters 195 12 9 7 Parity Extra Stop Bits with 8 Data Bit Characters sess 195 12 9 8 Supporting 9th Bit Communication Protocols essere 196 12 9 9 Rabbit Only Master Slave Protocol n ener nennen rennen 196 12 9 10 Data Fr mmg Modb s eroe tede prac 196 Chapter 13 Rabbit Slave Port 199 13 1 Hardware Design of Slave Port Interconnection essere enne 204 13 2 Slave Port Registers tereti te tne Eee 205 13 3 Applications and Communications Protocols for Slaves sese 208 13 3 T Slave Applications ete tede B e eins 208 13 3 2 Master Slave Messaging Protocol eren eene ne
58. 144 OISSA VSSIO IOE1 A11 A9 A8 A13 A14 VSSCORE VDDCORE A17 IWEO A18 A16 A15 A12 VDDIO VSSIO AT A6 A5 4 PC0 TXD PC1 RXD VSSCORE VDDCORE PC2 TXC PC3 RXC PC4 TXB PC5 RXB PC6 TXA PC7 RXA VDDIO 3 4 5 6 7 8 21 22 23 24 25 26 28 29 VDDIO CLK ICS2 STATUS IOE0 A10 ICS0 VDDCORE VSSCORE A1 A2 A3 VDDCORE VSSCORE Iscs 7 PE7 5 PES 4 PE4 INT1B INT0B OISSA 09 44191 LSd JXL 9d AXY 0dd vad axiv Sad axuv 9 VXLV Gd Z81715 OISSA LSO 13S134 03QOWS yaaouws LNOIGM N3ang quor UMOH 9d IAIL S9d 34198H 99d 1 29 03d Ol VOLNI bad LI OlaqA Figure 5 1 Package Outline and Pin Assignments Rabbit 3000 Microprocessor User s Manual 56 5 1 2 Mechanical Dimensions and Land Pattern Figure 5 2 shows the mechanical dimensions of the Rabbit 3000 LQFP package 16 00
59. 2 4 1 1 1 1 150 145011 01 5017 21 Yes Performs LD E E but if IDET 11211141 7 59 appears before it always does LD E E RDMODE 2 4 1 1 1 15 50 0 Yes 120114 0 320 Rabbit 3000 Microprocessor User s Manual C 2 System User Mode Registers Table C 3 lists the new I O registers added to support the System User mode The Enable Dual Mode Register EDMR is used to enable and disable the System User mode All other I O registers listed in the table are User mode enable registers for each peripheral On startup User mode access is not allowed to all the peripherals all writes to I O registers for that peripheral are ignored but can be enabled by writing to the appropri ate register Note that User mode writes to all other I O registers are always ignored Table C 3 System User Mode I O Registers Register Name Mnemonic A eee RW Reset Enable Dual Mode Register EDMR 0x0420 W 00000000 Real Time Clock User Enable Register RTUER 0x0300 W 00000000 Slave Port User Enable Register SPUER 0x0320 W 00000000 Parallel Port A User Enable Register PAUER 0x0330 W 00000000 Parallel Port B User Enable Register PBUER 0x0340 W 00000000 Parallel Port C User Enable Register PCUER 0x0350 W 00000000 Parallel Port D User Enable Register PDUER 0x0360 W 00000000 Parallel Port E User Enable Register PEUER 0x03
60. 2T Example The access time is given by clock 29 49 MHz 234ns operating voltage is 3 3 V bus loading is 60 pF address to output time 8 ns see Table 16 2 data setup time 1 ns the spectrum spreader is on in normal mode resulting in a loss of 3 ns access time 2T clock to address data setup spreader delay 68 ns 8 ns 1 ns 3 ns 56 ns 222 Rabbit 3000 Microprocessor User s Manual The required memory output enable access time is more complicated since it is affected by the clock doubler delays The clock doubler setup register creates a nominal delay time ranging from 6 to 20 ns resulting in a nominal clock low time ranging from 6 to 20 ns The clock low time depends on internal delays and is subject to variation arising from process variation operating voltage and temperature Minimum and maximum clock low times for various doubler settings are given in the formulas and in the graph below Max delay 3 3 V 6 1 121 n 6 nis the nominal delay 6 20 ns Min delay 3 3 V 3 7 0 75 n 6 Max delay 2 5 V 7 6 1 67 n 6 Min delay 2 5 V 4 7 1 03 n 6 Max delay 1 8 V 12 2 2 7 n 6 Min delay 1 8 V 6 6 1 44 n 6 60 0 50 0 40 0 3 3 m 2 5 V A1 8 V 30 0 Delay ns 20 0 10 0 0 0 0 5 10 15 20 25 Nominal Delay ns Figure 16 5 Clock Doubler Max Min Clock Low Times
61. 3 0 25 0 35 4 060 020 Figure 5 5 BGA Package Outline 61 Chapter 5 Pin Assignments and Functions 5 3 Rabbit Pin Descriptions Table 5 1 lists all the pins on the device along with their direction function and pin num ber on the package Table 5 1 Rabbit Pin Descriptions Pin Pin Pin Group Pin Name Direction Function Numbers Numbers LQFP TFBGA Hardware CLK Output Internal Clock 2 Bl CLK32K Input 32 kHz Oscillator In 49 L6 RESET Input Master Reset 46 M5 RESOUT Output Reset Output 50 M6 Main Oscillator In if an external clock is used this pin should be driven by XTALA1 Input the external clock see 113 B7 Technical Note TN235 for more information on external oscillator circuits XTALA2 Output Main Oscillator Out 114 A7 CPU Buses ADDR 19 0 Output Address Bus various TET 10 15 18 D4 1 4 DATA 7 0 Bidirectional Data Bus 19 FI F4 GO Status Control WDTOUT Output WDT Time Out 43 J5 STATUS Output Instruction Fetch First 4 Cl Byte SMODE 1 0 Input Bootstrap Mode Select 44 45 K5 L5 CSO Output Memory Chip Select 0 7 DI Memory CUP esi Output Memory Chip Select 1 147 16 Selects CS2 Output Memory Chip Select 2 3 B2 Memory JOEO Output Memory Output Enable 0 5 C2 Output Enables 1 Memory Output Enable 1 95 12 Memory WEO Output Memory Write Enable 0 86 F9 Write Enables
62. 3 V Preliminary Commercial Ratings Industrial Ratings Duty Cycle Conditions Minimum Maximum Minimum Maximum Requirements Period Frequency Period Frequency ns ns MHz ns MHz Neen 17 58 8 18 55 5 spreader epreader only 20 50 0 21 47 6 normal 21 47 6 22 45 4 strong Doubler only 1 gt clock low 8 ns delay 19 a 25 clock high 0 Doubler only internal 50 20 50 21 47 6 clock high gt 1 clock Spreader normal with 4 clock low doubler 21 22 clock high gt 2 8 ns delay Spreader noma 1 gt clock low doubler 8 ns 24 41 6 25 40 0 clock high gt 1 delay internal 50 clock ERER 21 5 46 5 22 5 45 0 strong Spreader strong with doubler 23 43 5 24 41 6 8 ns delay Chapter 16 AC Timing Specifications 229 Example The spreader and doubler are enabled with 8 ns nominal delay in the doubler The high and low clock are equal to within 1 ns This violates the duty cycle requirement by 3 ns since clock low clock high can be as small as 1 ns but the requirement is that it not be less than 2 ns Thus 3 ns must be added to the minimum period of 21 ns giving a mini mum period of 24 ns and a maximum frequency of 41 6 MHz commercial Since the built in high speed oscillator buffer generates a clock that is very close to having a 50 duty cycle to obtain the highest clock speeds using the clock doubl
63. 318 Rabbit 3000A internal I O 329 SPER sche sinha 167 Port A decode bug fix 278 RAMSR 293 167 PWM improvements 278 reading writing to I O registers shadow registers 245 quadrature decoder improve Ae 244 SPCR 130 205 206 DIenfS_ nasa 278 revision level ID 284 SPDXR sia 205 RAM segment relocation 278 RTCXR 92 SESR seen 205 207 RoHS innere 2T SAAR 166 stack pointer 22 secondary watchdog timer 278 SACR enar 166 status register 22 stack protection 278 166 STKCR eie 292 System User mode 278 SAER 166 292 variants of block move op SALR 166 292 COdeS sci 278 SASR 166 SWDIR irer mE 294 Index 339 s secondary watchdog timer 294 serial ports 11 161 9th bit protocols 196 address registers 168 baud rates 163 breaks 142 uem 194 clocked serial ports Ports A D 182 clocked serial timing 185 control registers Ports A B 173 control registers Ports C D 174 control registers Ports E F 175 controlling RS 485 driver and receiver aspasia 193 data and parity bits 163 data registers 168 dumm
64. CRC An interrupt is generated at the end of CRC 01 transmission Data written in response to this interrupt will cause only one Flag to be transmitted between frames and no interrupt will be generated by this Flag 2 1 10 Transmitter finished sending an Abort An interrupt is generated at the end of an Abort transmission T The transmitter finished sending a closing Flag Data written in response to this interrupt will cause at least two Flags to be transmitted between frames 0 The byte in the receiver buffer is 8 bits 0 1 The byte in the receiver buffer is less than 8 bits 172 Rabbit 3000 Microprocessor User s Manual Table 12 14 Serial Port Control Register Ports A and B Serial Port x Control Register SACR Address 0xC4 SBCR Address 0xD4 Bit s Value Description 7 6 00 No operation These bits are ignored in the Async mode 01 In clocked serial mode start a byte receive operation 10 In clocked serial mode start a byte transmit operation In clocked serial mode start a byte transmit operation and a byte receive 11 AUFS operation simultaneously 54 00 Parallel Port C is used for input 01 Parallel Port D is used for input Ix Disable the receiver input 3 2 00 Async mode with 8 bits per character Async mode with 7 bits per character In this mode the most significant bit of a 01 E byte is ignored for transmit and is always zero in receive data
65. EMI tests of the final product Execution speed with the Rabbit is usually a pleasant surprise compared to other pro cessors This is due to the well chosen and compact instruction set partnered with and excellent compiler and library We have many benchmarks comparing the Rabbit to 186 386 8051 Z180 and ez80 families of processors that prove the point The Rabbit memory bus is an exceptionally efficient and very clean design No external logic is required to support static memory chips Battery backed external memory is supported by built in functionality During reduced power slow clock operation the memory duty cycle can be correspondingly reduced using built in hardware resulting in low power consumption by the memories The Rabbit external bus uses 2 clocks for read cycles and 3 clocks for write cycles This has many advantages compared to a single clock design and on closer examination the advantages of the single clock system turn out to be mostly chimerical The advantages include easy design to avoid bus fights clean write cycles with solid data and address hold times flexibility to have memory output enable access times greater than gt of the bus cycle and the ability to use an asymmetric clock generated by a clock doubler The supposed advantage that single clock systems have of double speed bus operation is not possible with real world memories unless the memory is backed with fast cache RAM The Rabbit 3000 operates at 3 6
66. HL HL 1 if C was set otherwise HL convert not carry bit into boolean variable in HL SBC HL HL HL 0 if C 0 else HL ffff if C 1 INC HL HL 1 if C 0 else HL 0 if C note carry flag set but zero sign flags reversed In order to compare signed numbers using the SBC instruction the programmer can map the numbers into an equivalent set of unsigned numbers by inverting the sign bit of each number before performing the comparison This maps the most negative number 0x08000 to the smallest unsigned number 0x0000 and the most positive signed number 0x07FFF to the largest unsigned number OxOFFFF Once the numbers have been converted the com parision can be done as for unsigned numbers This procedure is faster than using a jump tree that requires testing the sign and overflow bits example test for HL gt DE where HL and DE are signed numbers invert sign bits on both ADD HL HL shift left CCF invert carry RR HL rotate right RL DE CCF RR DE invert DE sign SBC HL DE no carry if HL gt DE generate boolean variable true if HL gt DE SBC HL HL zero if no carry else 1 INC HL 1 if no carry else zero BOOL use this instruction to set flags if needed Chapter 3 Details on Rabbit Microprocessor Features 37 The sBc instruction can also be used to perform a sign extension extend sign of 1 to HL LD A 1 rla sign to carry SBC A a a is all 1 s if sign negative LD h a sign extended The mult
67. In sleepy mode the unit operates from the 32 768 kHz clock which may be divided down to as slow as 2 048 kHz The current consumption is given by HA 0 32 x V x f 0 23 x V xf 5xV where f is in kHz V is the operating voltage and V V x V 2 0 7 Leakage the standby current of the reset generator the current consumption of the oscilla tor and the real time clock and the current consumption of memories must be added to the sleepy mode current consumption Generally the self timed chip select mode is used to reduce memory current consumption Chapter 16 AC Timing Specifications 235 16 8 Memory Current Consumption Since there are many different memories available let s look at an example using one of the recommended flash and SRAM memories Flash memory SST part SST39LF512020 256K x 8 45 ns access time Standby current nil e Static Current chip select low 3 5 mA 3 3 V e Dynamic Current 7 mA at 14 7 MHz bus speed and 3 3 V The total current is 10 mA at a clock speed of 29 49 MHz or a bus speed of 5 MHz The static part of the current is computed using 3 5 x chip select duty cycle The dynamic part is computed using 0 5 x f in mA where f is the bus speed in MHz At 0 46 MHz 3 68 MHZ 8 and using a short chip select the duty cycle is about 10 giving a static current of about 0 35 mA The dynamic current is 0 25 mA for a total cur rent of 0 6 mA Added to the approximately 2 5 mA operatin
68. Load Immediate Data Instruction LD IX mn LD IY mn LD dd mn LD r n clk A 186 Z V Operation IX mn IY mn dd mn ren 19 2 Load amp Store to Immediate Address Instruction LD mn A LD A mn LD mn HL LD mn IX LD mn IY LD mn ss LD HL mn LD IX mn LD IY mn LD dd mn clk 10 9 13 15 15 15 11 13 13 13 A m m m m o o aH Operation mn A A mn mn L mn 1 H mn IXL mn 1 IXH mn IYL mn 1 IYH mn ssl mn 1 ssh L mn H mn 1 mn IXH mn 1 IYL mn IYH mn 1 441 mn ddh mn41 19 3 8 bit Indexed Load and Store Instruction LD A BC LD A DE LD BC A LD DE A LD HL n LD HL r LD r HL LD IX d n LD IX d r LD r IX d LD IY d n LD IY d r LD r K uaan 0 0 p p O p mn aH Operation A BC A DE BC HL n HL r r HL IX d n IX d r r IX d IY d Iy d r IY d n w m 19 4 16 bit Indexed Loads and Stores Instruction LD HL d HL LD HL HL d LD SP n HL LD SP n IX LD SP n IY LD HL SP n LD IX SP n LD IY SP n LD IX d HL LD HL IX d LD IY d HL LD HL IY d clk 13 11 11 13 13 9 11 11 11 9 13 11 A 186 Z V L Operation HL d L HL d 1 H L HL d H HL d 1 SP n L SP n 1 H SP n
69. Output Patterns 12 9 6 Parity Extra Stop Bits with 7 Data Bit Characters If only 7 data bits are being sent sending an additional parity or signal bit is easily solved by sending 8 bits and always setting bit 7 the eighth bit of the byte to 1 or 0 depend ing on what is desired No special precautions are needed if two stop bits are to be received If parity is received with 7 data bits receive the data as 8 bits and the parity will be in the high bit of the byte 12 9 7 Parity Extra Stop Bits with 8 Data Bit Characters In order to receive parity with 8 data bits a check is made on each character for a 9th bit low The 9th bit or parity bit is low if bit 6 of the serial port status register SxSR is set to a 1 after the character is received If the 9th bit is not a zero then the serial port treats it as an extra stop bit So if the 9th bit low flag is not set it should be assumed that the parity bit is a 1 Setting the 9th bit high or low can easily be done in the Rabbit 3000 The 9th bit can be set low by a write to the Serial Port A F Address Register SxAR and the 9th bit can be set high by a write to the Serial Port A F Long Stop Register SxLR Chapter 12 Rabbit Serial Ports 195 12 9 8 Supporting 9th Bit Communication Protocols This section describes how 9th bit communication protocols work 9th bit communication protocols are supported by processors such as the 8051 and the Z180 and by compan
70. PADR 0x30 R W XXXXXXXX Port B Data Register PBDR 0x40 R W 00 Port B Data Direction Register PBDDR 0x47 11000000 Port C Data Register PCDR 0x50 R W xOxIixixi Port C Function Register PCFR 0x55 x0x0x0x0 Port D Data Register PDDR 0x60 R W XXXXXXXX Port D Control Register PDCR 0x64 xx00xx00 Port D Function Register PDFR 0 65 Port D Drive Control Register PDDCR 0x66 w XXXXXXXX Port D Data Direction Register PDDDR 0x67 00000000 Port D 0 Register PDBOR 0x68 w XXXXXXXX Port D Bit 1 Register PDBIR 0x69 w XXXXXXXX Port D Bit 2 Register PDB2R 0 6 Port D 3 Register PDB3R 0x6B w XXXXXXXX Port D Bit 4 Register PDB4R 0x6C Port D Bit 5 Register PDB5R 0 6 w XXXXXXXX Port D Bit 6 Register PDB6R 0x6E w XXXXXXXX Port D Bit 7 Register PDB7R Ox6F Port E Data Register PEDR 0x70 R W XXXXXXXX Port E Control Register PECR 0x74 xx00xx00 Port E Function Register PEFR 0x75 W 00000000 Port E Data Direction Register PEDDR 0 77 00000000 Port E 0 Register PEBOR 0x78 W XXXXXXXX Port E Bit 1 Register PEBIR 0x79 Port E 2 Register PEB2R Ox7A Port E 3 Register PEB3R 0x7B Port E 4 Register PEB4R 0x7C w XXXXXXXX Port E Bit 5 Register PEB5R 0x7D w XXXXXXXX Port E Bit 6 Register PEB6R Ox7E W XXXXXXXX 74 Rabbit 3000 Microprocessor User s Manual Table 6
71. Quadrature Decoder 2 inputs Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement 7 6 01 This bit combination is reserved and should not be used 10 Quadrature Decoder 2 inputs from Port F bits 3 and 2 11 Quadrature Decoder 2 inputs from Port F bits 7 and 6 5 4 These bits are ignored 00 Disable Quadrature Decoder 1 inputs Writing a new value to these bits will not cause Quadrature Decoder 1 to increment or decrement 3 2 01 This bit combination is reserved and should not be used 10 Quadrature Decoder 1 inputs from Port F bits 1 and 0 11 Quadrature Decoder 1 inputs from Port F bits 5 and 4 00 Quadrature Decoder interrupts are disabled 01 Quadrature Decoder interrupt use Interrupt Priority 1 i 10 Quadrature Decoder interrupt use Interrupt Priority 2 11 Quadrature Decoder interrupt use Interrupt Priority 3 Table 7 27 Quadrature Decoder Count Register Quad Decode Count Register QDC1R Address 0x94 QDC2R Address 0x96 Bit s Value Description 7 0 read The current value of the Quadrature Decoder counter is reported Chapter 7 Miscellaneous Functions 113 114 Rabbit 3000 Microprocessor User s Manual 8 MEMORY INTERFACE AND MAPPING 8 1 Interface for Static Memory Chips Static memory chips generally have address lines data line a chip select line an output enable line and a write enable The Rabbit 3000 has these same lines that can connect directly to a number
72. RR DE 1 byte 2 clocks RL DE rotate DE left with carry 1 byte 2 clocks RR IX rotate IX right with carry 2 bytes 4 clocks RR IY rotate IY right with carry Logical Operations AND HL DE 1 byte 2 clocks AND IX DE 2 bytes 4 clocks AND IY DE OR HL DE 1 byte 2 clocks OR IX DE 2 bytes 4 clocks OR IY DE 36 Rabbit 3000 Microprocessor User s Manual The BOOL instruction is a special instruction designed to help test the HL register BOOL sets HL to the value 1 if HL is non zero otherwise if HL is zero its value is not changed The flags are set according to the result BOOL can also operate on IX and TY BOOL HL set HL to 1 if non zero set flags to match HL BOOL IX BOOL IY ALTD BOOL HL set HL an f according to HL ALTD BOOL IY modify IY and set f with flags of result The SBC instruction can be used in conjunction with the Boon instruction for performing comparisions The SBC instruction subtracts one register from another and also subtracts the carry bit The carry out is inverted compared to the carry that would be expected if the number subtracted was negated and added The following examples illustrate the use of the SBC and BOOL instructions Test if HL gt DE HL and DE unsigned numbers 0 65535 OR A Clear carry SBC HL DE if C 0 then HL gt DE else if C 1 then HL DE convert the carry bit into a boolean variable in HL SBC HL HL sets HL 0 if C 0 sets HL 0ffffh if C BOOL
73. Register TBCR 0 00 1 0000 Timer B MSB 1 Register TBMIR 0x00B2 w XXXXXXXX Timer B LSB 1 Register TBLIR 0x00B3 Timer B MSB 2 Register TBM2R 0x00B4 W XXXXXXXX Timer B LSB 2 Register TBL2R 0 00 5 B Count MSB Register TBCMR 0 00 R XXXXXXXX Timer B Count LSB Register TBCLR 0x00BF R XXXXXXXX Serial Port A Data Register SADR 0x00C0 R W XXXXXXXX Serial Port A Address Register SAAR 0x00C1 Serial Port A Long Stop Register SALR 0x00C2 Serial Port A Status Register SASR 0x00C3 R 0xx00000 Serial Port A Control Register SACR 0x00C4 W xx000000 Serial Port A Extended Register SAER 0x00C5 W 00000000 Serial Port B Data Register SBDR 0x00D0 R W XXXXXXXX 334 Rabbit 3000 Microprocessor User s Manual Table D 1 Rabbit 3000A Internal I O Registers continued Register Name Mnemonic I O Address R W Reset Serial Port B Address Register SBAR 0x00D1 W XXXXXXXX Serial Port B Long Stop Register SBLR 0x00D2 W XXXXXXXX Serial Port B Status Register SBSR 0x00D3 R 0xx00000 Serial Port B Control Register SBCR 0x00D4 W xx000000 Serial Port B Extended Register SBER 0x00D5 00000000 Serial Port C Data Register SCDR 0 00 R W XXXXXXXX Serial Port C Address Register SCAR 0 00 1 Serial Port C Long
74. SDUER 0x03F0 00000000 Enable Dual Mode Register EDMR 0x0420 w 00000000 Slave Port Data 0 Register SPD0R 0x0020 R W XXXXXXXX Slave Port Data 1 Register SPDIR 0x0021 R W XXXXXXXX Slave Port Data 2 Register SPD2R 0x0022 R W XXXXXXXX Slave Port Status Register SPSR 0x0023 R 00000000 Slave Port Control Register SPCR 0x0024 R W 0xx00000 Port A Data Register PADR 0x0030 R W XXXXXXXX Port B Data Register PBDR 0x0040 R W 00 Port B Data Direction Register PBDDR 0x0047 w 11000000 Port C Data Register PCDR 0x0050 R W xOxixixi Port C Function Register PCFR 0x0055 x0x0x0x0 Port D Data Register PDDR 0x0060 R W XXXXXXXX Port D Control Register PDCR 0x0064 w xx00xx00 Port D Function Register PDFR 0x0065 W XXXXXXXX Port D Drive Control Register PDDCR 0x0066 W XXXXXXXX Port D Data Direction Register PDDDR 0x0067 W 00000000 Port D Bit 0 Register PDBOR 0x0068 W XXXXXXXX Port D Bit 1 Register PDBIR 0x0069 W XXXXXXXX Appendix D Rabbit 3000A Internal I O Registers 331 Table D 1 Rabbit 3000A Internal I O Registers continued Register Name Mnemonic I O Address R W Reset Port D Bit 2 Register PDB2R 0x006A w XXXXXXXX Port D Bit 3 Register PDB3R 0x006B w XXXXXXXX Port D Bit 4 Register PDB4R 0x006C Port D Bit 5 Register PDB5R 0x006D Port D 6 Register PDB6R 0x006E w XXXXXXXX Port D Bit 7 Regi
75. Serial Transmit In CLKD Clock for clocked mode bidirectional Serial Port E TXE Serial Transmit Out RXE Serial Transmit In TCLKE Optional external transmit clock RCLKE Optional external receive clock Chapter 12 Rabbit Serial Ports 161 Table 12 1 Serial Port Signals continued Serial Port Signal Name Function Serial Port F TXF Serial Transmit Out RXF Serial Transmit In TCLKF Optional external transmit clock RCLKF Optional external receive clock Figure 12 1 shows a block diagram of the serial ports Timer A4 Serial Port A Serial Port B A5 Timer A6 Serial Port Input to timers percik or Timer A7 Serial Port D Serial Port Timer A3 Serial Port perclk 2 or prescaled Timer A1 Timer A2 Figure 12 1 Block Diagram of Rabbit Serial Ports 162 Rabbit 3000 Microprocessor User s Manual The individual serial ports are capable of operating at baud rates in excess of 500 000 bps in the asynchronous mode and 8 times faster than that in the synchronous mode Either 7 or 8 data bits may be transmitted and received in the asynchronous mode The so called Oth bit or address bit mode of operation is also supported The 9th bit can
76. TBCR is laid out as shown in Table 11 8 Table 11 8 Timer B Control Register Timer B Control Register TBCR Address 0x00B1 Bit s Value Description 7 4 These bits are reserved and should be written with zeroes 00 Timer B clocked by the main Timer B clock perclk 2 3 2 01 Timer B clocked by the output of Timer A1 Ix Timer B clocked by the main Timer B clock perclk 2 divided by 8 00 Timer B interrupts are disabled 01 Timer B interrupts use Interrupt Priority 1 10 Timer B interrupts use Interrupt Priority 2 11 Timer B interrupts use Interrupt Priority 3 Chapter 11 Timers 157 The MSB x registers for Timer B TBMIR TBM2R are laid out as shown in Table 11 9 Table 11 9 Timer B Count MSB x Registers Timer B Count MSB x Register TBM1R Address 0xB2 TBM2R Address 0xB4 Bit s Value Description The two MSBs of the comparae value for the Timer B comparator are stored 7 6 Write This compare value will be loaded into the actual comparator when the current compare detects a match 5 0 These bits are always read as zeroes The LSB x registers for Timer B TBLIR TBL2R laid out as shown in Table 11 10 Table 11 10 Timer B Count LSB x Registers Timer B Count LSB x Register TBL1R Address 0xB3 TBL2R Address 0xB5 Bit s Value Description The eight LSBs of the comparae value for the Timer B comparator ar
77. Table 7 25 Quadrature Decoder Control Status Register Quad Decode Control Status Register QDCSR Address 0x90 Bit s Value Description 7 0 Quadrature Decoder 2 did not increment from OxFF Quadrature Decoder 2 incremented from OxFF to 0x00 This bit is cleared by a read only read of his register 6 0 Quadrature Decoder 2 did not decrement from 0x00 Quadrature Decoder 2 decremented from 0x00 to 0xFF This bit is cleared by a read only 1 read of this register 5 This bit always reads as zero 4 0 No effect on the Quadrature Decoder 2 write only 1 Reset Quadrature Decoder 2 to 0x00 without causing an interrupt 3 0 Quadrature Decoder 1 did not increment from OxFF Quadrature Decoder 1 incremented from OxFF to 0x00 This bit is cleared by a read only 1 read of this register 2 0 Quadrature Decoder 1 did not decrement from 0x00 Quadrature Decoder 1 decremented from 0x00 to OxFF This bit is cleared by a read only 1 read of this register 1 This bit always reads as zero 0 0 No effect on the Quadrature Decoder 1 write only 1 Reset Quadrature Decoder 1 to 0x00 without causing an interrupt 112 Rabbit 3000 Microprocessor User s Manual Table 7 26 Quadrature Decoder Control Register Quad Decode Control Register QDCR Address 0x91 Bit s Value Description 00 Disable
78. The Rabbit 3000 has important features that aid in the control if EMI e The power supply for the processor core is on separate pins from the power supply for the I O buffers associated with the processor and various peripheral devices e A spectrum spreader in the clock circuit can be enabled to spread the spectrum of the clock by varying the clock frequency in a regular pattern e The built in clock doubler allows the external oscillator circuitry to operate at 1 2 the ultimate clock frequency e In most cases it is not necessary to route the system clock outside the package although a pin is provided for this purpose in the unusual circumstances where it might be neces sary The high speed clock on PC board traces is a major cause of EMI If all the EMI suppression features of the Rabbit 3000 are properly utilized and low EMI design techniques are used on the printed circuit board system EMI will likely be reduced to a very low level probably much lower than is necessary to pass government tests Chapter 15 EMI Control 213 15 1 Power Supply Connections and Board Layout Refer to Technical Note TN221 PC Board Layout Suggestions for the Rabbit 3000 Microprocessor for recommendations on laying out a PC board to minmize EMI emsis sions 15 2 Using the Clock Spectrum Spreader The spectrum spreader is very powerful for reducing EMI because it will reduce all sources of EMI above 100 MHz that are related to the clock by about 15 d
79. User mode The solution to this is for the System mode interrupt vector to reenter User mode before calling the User mode interrupt handler An example of both system and user interrupt handling is shown in Figure C 1 INTERRUPT UNDER SYSTEM CONTROL ISR system Application code user Application code user INTERRUPT UNDER USER CONTROL ISR system Application ISR user Application code user Application code user Figure C 1 Interrupt Handing in System User Mode Some sample code for both System mode interrupts and User mode interrupts is shown below system isr jumped to from interrupt vector table handle interrupt sures reenter previous mode ret user isr jumped to from interrupt vector table push su preserve current SU stack setusr enter user mode handle interrupt pop su restore previous SU stack sures reenter previous mode ret Appendix C System User Mode 323 C 3 1 Peripheral Interrupt Prioritization Most interrupts can be programmed to occur at any of three priority levels but several are restricted to Level 3 the highest priority only The interrupts restricted to Level 3 are sys tem mode violation stack limit violation write protection violation and the secondary watchdog In addition any interrupt assigned to User mode is prevented by hardware from requesting a Level 3 interrupt If a user assigned interrupt is programmed to occur at Level 3 the hardware will autom
80. V or less but it has 5 V tolerant inputs and has a sec ond complete bus for I O operations that is separate from the memory bus This second auxiliary bus can be enabled by the application as a designer option These features make it easy to design systems that mix 3 V and 5 V components and avoid the loading problems and the EMI problems that result if the memory bus is extended to connect with many I O devices The Rabbit may be remotely programmed including complete cold boot via a serial link Ethernet or even via a network or the Internet using built in capabilities and or the RabbitLink ethernet network accessory device These capabilities proven and inexpen sive to implement The Rabbit 3000 on chip peripheral complement is huge compared to competitive pro cessors 10 Rabbit 3000 Microprocessor User s Manual The Rabbit is an 8 bit processor with an 8 bit external data bus and an 8 bit internal data bus Because the Rabbit makes the most of its external 8 bit bus and because it has a com pact instruction set its performance is as good as many 16 bit processors We hesitate to compare the Rabbit to 32 bit processors but there are undoubtedly occa sions where the user can use a Rabbit instead of a 32 bit processor and save a vast amount of money Many Rabbit instructions are 1 byte long In contrast the minimum instruction length on most 32 bit RISC processors is 32 bits 2 2 Overview of On Chip Peripherals and Feature
81. address 0x70000 0x7FFFF H 1 Enable 64K write protect for physical address 0 70000 0 7 0 Disable 64K write protect for physical address 0x60000 0x6FFFF 1 Enable 64K write protect for physical address 0x60000 Ox6FFFF 0 Disable 64K write protect for physical address 0x50000 0x5FFFF i 1 Enable 64K write protect for physical address 0x50000 0x5FFFF 0 Disable 64Kwrite protect for physical address 40000 0 4 I 1 Enable 64K write protect for physical address 0 40000 0 4 0 Disable 64K write protect for physical address 0x30000 0x3FFFF 1 Enable 64Kwrite protect for physical address 0x30000 0x3FFFF 0 Disable 64K write protect for physical address 0x20000 0x2FFFF 1 Enable 64K write protect for physical address 0x20000 0x2FFFF 0 Disable 64K write protect for physical address 0x 10000 0 1FFFF 1 Enable 64K write protect for physical address 0 10000 0 1 0 Disable 64K write protect for physical address 0x00000 0x0FFFF j 1 Enable 64K write protect for physical address 0 00000 0 Appendix B Rabbit 3000 Revisions 287 Table B 8 Write Protect High Register Write Protect High Register WPHR Address 0x0461 Bit s Value Description 0 Disable 64K write protect for physical address OXF0000 0xFFFFF 1 Enable 64K write protect for physical address 0xF0000 0xFFFFF 0 Disable 64K
82. an exter nal oscillator can be modified by a clock spectrum spreader internal to the Rabbit 3000 chip When the spectrum spreader is engaged the clock is alternately speeded up and slowed down thus spreading the spectrum of the clock harmonics in the frequency domain This reduces EMI and improves the results of official radiated emissions tests typically by 15 20 dB at critical frequencies The spectrum spreader has 3 modes of oper ation off normal and strong Slightly faster memory access time is required when the spectrum spreader is used 2 3 ns for the normal setting when the clock doubler is enabled and 6 9 ns for the strong setting when the clock doubler is used The spreader slightly influences baud rates and other timings because it introduces clock jitter but the effect is usually small enough to be negligible 2 2 13 Separate Core and I O Power Pins The silicon die that constitutes the Rabbit 3000 processor is divided into the core logic and the I O ring The I O ring located on the 4 edges of the die holds the bonding pads and the large transistors used to create the I O buffers that drive signals to the external world The core section inside the I O ring contains the main processor and peripheral logic The clock and clock edges in the core are very fast with large transient currents that create a lot of noise that is communicated to the outside of the package via the power pins The I O buffers have slower switching times
83. and then go about its business while the other side takes care of the request according to its own time schedule The other side can be alerted by an interrupt that takes place when a store is made to register zero or it can alert itself by a periodic poll of the status register Chapter 4 Rabbit Capabilities 53 Of the three registers seen by each side for each direction of communication the first reg ister slave register zero has a special function because an interrupt can only be generated by a write to this register which then causes an interrupt to take place on the other side of the link if the interrupt is enabled One type of protocol is to store data first in registers 1 and 2 and then as the last step store to register 0 Then 24 bits of data will be available to the interrupt routine on the other side of the link Bulk data transfers across the link can take place by an interrupt for each byte transferred similar to a typical serial port or UART In this case a full duplex transfer can take place similar to what can be done with a UART The overhead for such an interrupt driven trans fer will be on the order of 100 clocks per byte transferred assuming a 20 instruction inter rupt routine To keep the interrupt routine to 20 instructions the interrupt routine needs to be very focused as opposed to general purpose Several methods are available to cater to a faster transfer with less computing overhead There are enough regist
84. and mostly operate at much lower frequencies than the core logic The Rabbit has separate power and ground pins for the core and I O ring This allows the designer to feed clean power to the I O ring filtered to be free of the noise generated by the core switching This minimizes high frequency noise that would other wise appear on output pins driven by buffers in the I O ring The result is lower EMI 2 3 Design Standards The same functionality can often be accomplished in more than one way with the Rabbit 3000 By publishing design standards or standard ways to accomplish common objec tives software and hardware support become easier Refer to the Rabbit 3000 Microprocessor Designer s Handbook for additional information 2 3 1 Programming Port Rabbit Semiconductor publishes a specification for a standard programming port see Appendix A The Rabbit Programming and provides a converter cable that may be used to connect a PC serial port to the standard programming interface The interface is implemented using a 10 pin connector with two rows of pins on 2 mm centers The port is connected to Rabbit Serial Port A to the startup mode pins on the Rabbit to the Rabbit 18 Rabbit 3000 Microprocessor User s Manual reset pin and to a programmable output pin that is used to signal the PC that attention is needed With proper precautions in design and software it is possible to use Serial Port A as both a programming port and
85. be set high or low by accessing the appropriate serial port register Although Parity and multiple stop bits are not directly supported by the hardware the 9th bit can be used to issue an extra stop bit 9th bit high or toggled to indicate parity Chapter 12 Rabbit Serial Ports 163 12 1 Serial Port Register Layout Figure 12 2 shows a functional block diagram of a serial port Each serial port has a data register a control register and a status register Writing to the data register starts transmis sion The least significant bit LSB is always transmitted first This is true for both asyn chronous and synchronous communication If the write is performed to an alternate data register address the extra address bit or 9th bit 8th bit if 7 data bits is sent When data bits have been received they are read from the data register LSB first The control regis ter is used to set the transmit and receive parameters The status register may be tested to check on the operation of the serial port long stop register Read Data Write Data Data In Reg Data Out Reg T _ alternate data out fifo ports E F only fifo ports E F only register 4 bytes deep 4 bytes deep address register Input Shift Reg Output Shift Reg Rx serial data in L Tx serial data out LSB First LSB First Bit 0 6 7 stop Tx Tr
86. bit operations such as ADD HL DE which adds 16 bit register DE to the 16 bit accumulator HL For many operations IX or IX can substitute for HL as accumulators The register marked F is the flags register or status register It holds a number of flags that provide information about the last operation performed The flag register cannot be accessed directly except by using the POP AF and PUSH AF instructions Normally the flags are tested by conditional jump instructions The flags are set to mark the results of arithmetic and logic operations according to rules that are specified for each instruction There are four unused read write bits in the flag register that are available to the user via the PUSH AF and AF instructions These bits should be used with caution since new generation Rabbit processors could use these bits for new purposes The registers IX and HL can also serve as index registers They point to memory addresses from which data bits are fetched or stored Although the Rabbit can address a megabyte or more of memory the index registers can only directly address 64K of mem ory except for certain extended addressing LDP instructions The addressing range is expanded by means of the memory mapping hardware see Memory Mapping on page 23 and by special instructions For most embedded applications 64K of data mem ory as opposed to code memory is sufficient The Rabbit can efficiently handle a mega byte o
87. by Segment CS1 Enable The inversion of A19 or A16 controlled by the read write MMIDR register is used to redirect mapping of the root segment and the data segment by inverting certain bits when these segments are accessed The optional enable of CS1 is valuable for systems that are pushing the access time of battery backed RAM By enabling CS1 the delay time of the switch that forces CS1 high when power is off can be bypassed This feature increases power consumption since the RAM is always enabled and its access is controlled normally by OEI Table 8 4 MMU Instruction Data Register MMIDR 0x010 MMU Instruction Data Register MMIDR Address 0x010 Bit s Value Description 7 6 00 These bits are ignored and alwavs return zeros when read 0 Enable A16 and A19 inversion independent of instruction data 5 Enable 16 and 19 inversion controlled by bits 0 3 for data accesses only This enables the instruction data split This is separate I and D space 0 Normal CS1 operation 4 Force CS1 always active This will not cause any conflicts as long as the 1 memory using CS1 does not also share an Output Enable or Write Enable with another memory 0 Normal operation 1 1 For a DATASEG access invert A19 before MBxCR bank select decision 0 Normal operation 1 For a DATASEG access invert 16 0 Normal operation 1 For root access invert 19 before MBxCR bank select dec
88. cal upset are common reasons When the system crashes the program will typically settle into an endless loop because parameters that govern looping behavior have been cor rupted Typically the stack becomes corrupted and returns are made to random addresses The usual corrective action taken in response to a crash is to reset the microprocessor and reboot the system The crash can be detected either because an anomaly is detected by pro 240 Rabbit 3000 Microprocessor User s Manual gram consistency checking or because a part of the program that should be executing peri odically is not executing and the watchdog times out The Virtual Driver s periodic interrupt hits the hardware watchdog timer with a 2 second time out If the periodic interrupt stops working then the watchdog will time out after 2 seconds The Virtual Driver provides a number of additional virtual watchdog timers for use in other parts of the code that must be entered periodically The user program must hit each virtual watchdog periodically The best practice is to let the periodic interrupt hit the hardware watchdog exclusively and use virtual watchdogs for other code that must be run periodically If hits to the hardware watchdog are scattered through a program then it may be possible for the code to enter an endless loop where the watchdog is hit and therefore rendered useless for detecting the endless loop condition If no virtual watchdogs are used an unde
89. clock on timer B1 11 clock on timer B2 11 clock on timer B2 The following registers are described in Table 9 14 and in Table 9 15 e PFDR Port F data register Reads value at pins Writes to port F preload register e PFCR Parallel Port F control register This register is used to control the clocking of the upper and lower nibble of the final output register of the port On reset bits 0 1 4 and 5 are reset to zero e PFFR Port F function register Set bit to 1 to enable alternate output function Bits 7 4 enable the PWM outputs and bits 1 0 enable synchronous serial ports C and D clock outputs for when the serial port is configured for internal clock generation e PFDCR Parallel Port F drive control register A 0 makes the corresponding pin a regular output A 1 makes the corresponding pin an open drain output Write only e PFDDR Port F data direction register Set to 1 to make corresponding pin an output This register is zeroed on reset On reset the data direction register is zeroed making all pins inputs In addition certain bits in the control register are zeroed bits 0 1 4 5 to ensure that data is clocked into the output registers when loaded All other registers associated with port F are not initialized on reset 9 6 1 Using Parallel Port A and Parallel Port F A bug has been discovered in the Rabbit 3000 that results in a conflict between Parallel Port F and Parallel Port A under certain cond
90. destination address can remain fixed instead of changing after each byte The new opcodes are described in Table B 19 Table B 19 Rabbit 3000 Revision Block Copy Opcode Effects r Destination Opcode hn ud 1 Nees Change Change LDDR destination LDIR destination LDDSR none destination LDISR none destination LSDR E source LSIR source LSDDR none source LSIDR none source 296 Rabbit 3000 Microprocessor User s Manual B 1 10 Expanded I O Memory Addressing In the Rabbit 3000 only the lower 8 bits of an I O address were decoded To provide room for new peripherals this was expanded to 16 bits To ensure backwards compatibility the processor always comes up in 8 bit I O address mode the 16 bit I O address mode needs to be enabled in the MMIDR register by setting bit 7 to 1 The updated MMIDR register is listed in Table B 20 NOTE Bits 7 was always written with a zero in the original Rabbit 3000 chip Table B 20 MMU Instruction Data Register MMU Instruction Data Register MMIDR Address 0x010 Bit s Value Description 0 8 bit internal I O addresses address range 0 0000 0 00 7 1 15 bit internal I O addresses address range 0x0000 0x 7FFF required to access internal I O addresses of 0x0100 and higher 6 0 This bit is ignored and will always return zero when read 0 Enable A16 and A19 inversion
91. divides the data space into two separate segments for constants and variables If the stack segment which is still combined I and D space and the extended code segment also combined I and D space occupy 12K at the top of the 64K space then the remaining 52K is doubled into a 52K code space in flash and a 52K data space which may be split into two parts one for con stants and one for variables The relative size of the two parts depends on the lower 4 bits of the SEGSIZE register which define the 4K page boundary between the root segment and the data segment Combined amp D Separate amp D 64k Extended Code 52k Stack D Space Allocate Var 4 n k RAM D Space Allocate Const consts flash vars Figure 8 5 Combined versus Separate amp D Space The use of physical memory that goes with this map is shown in Figure 8 6 Use of Phys ical Memory Separate I amp D Space Model on page 127 In this figure n is the number of 4k pages devoted to D space constants In the figure it is assumed that the lower 512k of memory is entirely composed of flash memory and the upper 512K is entirely RAM This does not have to be the case For example if a low cost 32K x 8 RAM is used and mapped to the 3rd quadrant using CS1 the RAM memory will begin at 512K and will be repeated 8 times in the 3rd quadrant from addresses 512K to 768K Since the memory repeats it
92. eight in async mode and divided by six teen in HDLC mode The HDLC receiver employs a Digital Phase Locked Loop DPLL to generate a synchro nized receive clock for the incoming data stream HDLC mode also allows for an external 1x same speed as the data rate clock for both the receiver and the transmitter HDLC receive and transmit clocks can be input or output as appropriate via the specified pins When using an external clock the maximum data rate is one sixth of the peripheral clock rate In asynchronous mode the port can send and receive seven or eight bits and has the option of appending and recognizing an additional address bit On transmit the address bit is automatically appended to the data when this data is written to the address register or long stop register Writing to the address register appends an zero address bit to the data while writing to the long stop register appends an one address bit to the data The address bit is followed by a normal stop bit Normal data is written to the data register to be transmitted On receive a status bit distinguishes normal data from address data This status bit is set to one if a zero address bit is received In non address bit applications this indicates a framing error This status bit can also indicate a received break if the accompanying data is all zeros this is the definition of break Asynchronous mode oper ates full duplex Either the receive data avail
93. f b L SRA r 11001011 00101 r 4 fr L SRL HL 11001011 00111110 10 f Db L SRL IX d 11011101 11001011 d 00111110 13 f b L SRL IY d 11111101 11001011 d 00111110 13 f b L SRL r 11001011 00111 r 4 fr L SUB HL 10010110 5 fr SUB IX d 11011101 10010110 d 9 fr sk SUB IY d 11111101 10010110 d 9 fr sk SUB n 11010110 n 4 fr k k V SUB r 10010 r 2 fr XOR 10101110 5 fr s LO IX d 11011101 10101110 d 9 fr s 0 IY d 11111101 10101110 d 9 fr s LO XOR n 11101110 n 4 fr L 0 XOR r 10101 r 2 fr L0 ZINTACK interrupt 10 270 Rabbit 3000 Microprocessor User s Manual APPENDIX A THE RABBIT PROGRAMMING PORT The programming port provides a standard physical and electrical interface between a Rabbit based system and the Dynamic C programming platform A special interface cable and converter the programming cable connects a PC serial port to the programming port The programming port is usually implemented with a standard 2 mm or 1 27 mm 10 pin connector With this setup the PC can communicate with the target reset it and reboot it The DTR line on the PC serial interface is used to drive the target reset line which should be drivable by an external CMOS driver The STATUS pin is used to by the Rabbit based target to respond to Dynamic C before the pilot BIOS and the cold loader binary fi
94. for address offset 0x8000 0x8FFF in WP Segment x 290 Rabbit 3000 Microprocessor User s Manual B 1 6 Stack Protection Stack overflow and underflow can now be detected Low and high stack limits can be set on 256 byte boundaries When a stack relative memory access occurs within 16 bytes of these limits or outside of them a new Priority 3 stack violation interrupt occurs The 16 byte buffer exists to allow stack protection even if the stack is placed against a memory segment boundary Figure B 2 shows one possible stack layout A 2048 byte stack is set up by setting STKHLR to OxEO STKLLR to OxD8 and SP to OxDFFO Any stack relative memory accesses above OxDFEF 1 stack underflow or below OxD810 i e overflow would trigger the stack violation interrupt TKHLR 0xE0 Stack access this 0 000 region triggers an interrupt OxDFFO OxDFEF Stack access in this region is allowed OxD810 OxD80F OxD800 Stack access in this region triggers an interrupt TKLLR OxD8 Figure B 2 Simple Stack Protection Lavout Appendix B Rabbit 3000 Revisions 291 The stack protection registers are listed in Table B 12 Table B 13 and Table B 14 Table B 12 Stack Limit Control Register Stack Limit Control Register STKCR Address 0x0444 Bit s Value Description 7 1 These bits are reserved and sh
95. in the total memory space Special instructions make it possible to jump call or return from one page to another These spe cial instructions are called long calls long jumps and long returns to distinguish them from the same operations that only operate on 16 bit variables The Rabbit also uses a paging scheme to expand the code space beyond the reach of a 16 bit address The Rabbit paging scheme uses the concept of a sliding page which is 8K long This is the XPC segment The 8 bit XPC register serves as a page register to specify the part of memory where the window points When a program is executed in the XPC segment normal 16 bit jumps calls and returns are used for most jumps within the win dow Normal 16 bit jumps calls and returns may also be used to access code in the other three segments in the 16 bit address space If a transfer of control to code outside the win dow is required then a long jump long call or long return is used These instructions mod ify both the program counter PC and the XPC register causing the XPC window to point to a different part of memory where the target of the long jump call or return is located The XPC segment is always 8K long The granularity with which the XPC segment can be positioned in memory is 4K Because the window can be slid by one half of its size it is possible to compile continuously without unused gaps in memory As the compiler generates code resident in the XPC window the window
96. interrupt must be serviced after each edge to set up the time for the next edge This restriction limits the minimum pulse width to about 5 us depending on the clock speed and interrupt priorities 160 Rabbit 3000 Microprocessor User s Manual p 12 RABBIT SERIAL PORTS The Rabbit 3000 has 6 on chip serial ports designated A B C D E and F All the ports can per form asynchronous serial communications at high baud rates Ports A D can operate as clocked ports Ports A and B can be switched to alternate pins Ports E and F support SDLC HDLC syn chronous communications in addition to standard asynchronous communications Port A has the special capability of being used to remote boot the microprocessor via asynchronous synchro nous or IrDA asynchronous serial Table 12 1 lists the synchronous serial port signals Table 12 1 Serial Port Signals Serial Port Signal Name Function Serial Port A TXA Serial Transmit Out RXA Serial Transmit In CLKA Clock for clocked mode bidirectional ATXA Alternate serial transmit out ARXA Alternate serial receive in Serial Port B TXB Serial Transmit Out RXB Serial Transmit In CLKB Clock for clocked mode bidirectional ATXB Alternate serial transmit out ARXB Alternate serial receive in Serial Port C TXC Serial Transmit Out RXC Serial Transmit In CLKC Clock for clocked mode bidirectional Serial Port D TXD Serial Transmit Out RXD
97. is slid down by 4K when the code goes beyond F000 This is accomplished by a long jump that reposi tions the window 4K lower This is illustrated by Figure 3 5 The compiler is not presented with a sharp boundary at the end of the page because the window does not run out of space when code passes F000 unless 4K more of code is added before the window is slid down All code compiled for the XPC window has a 24 bit address consisting of the 8 bit XPC and the 16 bit address Short jumps and calls can be used provided that the source and tar get instructions both have the same XPC address Generally this means that each instruc tion belongs to a window that is approximately 4K long and has a 16 bit address between E000 n and F000 m where n and m are on the order of a few dozen bytes but can be up to 4096 bytes in length Since the window is limited to no more than 8K the compiler is unable to compile a single expression that requires more than 8K or so of code space This is not a practical consideration since expressions longer than a few hundred bytes are in the nature of stunts rather than practical programs Program code can reside in the root segment or the XPC segment Program code may also be resident in the data segment Code can be executed in the stack segment but this is usu ally restricted to special situations Code in the root meaning any of the segments other 26 Rabbit 3000 Microprocessor User s Manual than the XPC segment c
98. l E SNIN NTN Biph se Mark ONY NJS NIN NSN N data 1 0 1 1 0 0 1 0 In HDLC mode the internal clock comes from the output of Timer 2 This timer output is divided by sixteen to form the transmit clock and is fed to the Digital Phase Locked Loop DPLL to form the receive clock The DPLL is basically just a divide by 16 counter that uses the timing of the transitions on the receive data stream to adjust its count The DPLL adjust the count so that the output of the DPLL will be properly placed in the bit cells to sample the receive data To work properly then transitions are required in the receive data stream NRZ data encoding does not guarantee transitions in all cases a long string of zeros for example but the other data encodings do NRZI guarantees transitions because of the inserted zeros and the Biphase encodings all have at least one transition per bit cell The DPLL counter normally counts by sixteen but if a transition occurs earlier or later than expected the count will be modified during the next count cycle If the transition occurs earlier than expected it means that the bit cell boundaries are early with respect to the DPLL tracked bit cell boundaries so the co
99. memory read or write to that quadrant takes place For example if a 512K x 8 flash mem ory is to be accessed in the first 512K of the 20 bit address space then CSO WEO OEO could be enabled in both quadrants Figure 3 4 shows a memory interface unit Axxin from processor Axx out from memory control unit A19in Macs A19 2 18 19 invertible Address lines shown A18in by quadrant are passed directly yq A19in 19 CS0 Memory CS1 Control CS2 Lines A18in Optional A19 inversion Memory Control WEO Read Write _ JOE1 Synchronization WE1 p Figure 3 4 Memory Interface Unit Chapter 3 Details on Rabbit Microprocessor Features 25 3 2 1 Extended Code Space A crucial element of the Rabbit memory mapping scheme is the ability to execute pro grams containing up to a megabyte of code in an efficient manner This ability is absent in a pure 16 bit address processor and it is poorly supported by the Z180 through its memory mapping unit On paged processors such as the 8086 this capability is provided by paging the code space so that the code is stored in many separate pages On the 8086 the page size is 64K so all the code within a given page is accessible using 16 bit addressing for jumps calls and returns When paging is used a separate register CS on the 8086 is used to determine where the active page currently resides
100. messages if this is a problem A 3 Suggested Rabbit Crystal Frequencies Table A 1 provides a list of suggested Rabbit operating frequencies The numbers in Table A 1 are based on the following assumptions spectrum spreader set to normal doubler in use 52 48 duty cycle and a combined 6 ns for clock to address and data setup times The crystal can be half the operating frequency if the clock doubler is used up to 27 MHz Beyond this operating clock speed it is necessary to use an X1 crystal or an external oscil lator because asymmetry in the waveform generated by the oscillator becomes a variation in the clock speed if the clock speed is doubled Appendix A The Rabbit Programming Port 273 Table A 1 Preliminary Crystal Frequencies Memory Access Times and Baud Rates Frequency Frequency Period Access Time Divisor for MHz MHz ns 1 8432 3 6864 271 522 4 3 6864 7 3728 136 257 8 7 3728 14 7456 68 124 16 9 216 18 432 54 97 20 11 0592 22 1184 45 79 24 12 9024 25 8048 39 67 28 14 7456 29 4912 34 57 32 18 432 36 864 27 44 40 22 1184 44 2368 23 35 48 25 8048 51 6096 19 29 56 Non Stock Crystals 20 2752 40 5504 25 39 44 21 1968 42 3936 24 37 46 23 04 46 08 22 33 50 23 9616 47 9232 21 32 52 24 8832 49 7664 20 30 54 26 7264 53 4528 19 27 58 274 Rabbit 3000 Microprocessor User s Manual APPENDIX B RABBIT 3000 REVISIONS
101. not affected because memory bus cycle is 2 clocks long and includes both a long and a short clock resulting in no net change due to asymmetry However if an odd number of wait states is used then the memory access time will be affected slightly When the clock spectrum spreader is enabled clock periods are shortened by a small amount depending on whether the normal or the strong spreader setting is used and depending on the operating voltage If the clock doubler is used the spectrum spreader affects every other cycle and reduces the clock high time If the doubler is not used then the spreader affects every clock cycle and the clock low time is reduced Of course the spectrum spreader also lengthens clock cycles but only the worst case shortening is rele vant for calculating worst case access times The numbers given for clock shortening with the doubler disabled are the combined shortening for 2 consecutive clock cycles worst case In computing memory requirements the important considerations are address access time output enable access time and minimum write pulse required Increasing the clock dou bler delay increases the output enable time but decreases memory write pulse width The early write pulse option can be used to ensure a long enough write pulse but then it must be ensured that the write pulse does not begin before the address lines have stabilized Chapter 16 AC Timing Specifications 227 O
102. of static memory chips The chip selects are not completely inter changeable because certain chip selects have special functions When the processor starts up not in cold boot mode execution starts at address zero in the memory attached to CSO A static RAM should be connected to CS1 because Dynamic C development tools assume a static RAM connected to CS1 In addition CS1 has special features that support battery backing of static RAM When the processor power is removed but battery power is supplied to the battery power pin VBAT GSI is held in a high impedance state This allows a pull up resistor to the bat tery backup power to hold CS1 high and thus hold the static memory chip in standby mode The RESOUT pin is also held high while the processor is powered down and bat tery power is supplied to VBAT This allows the RESOUT pin to be used to control power to the processor and the static RAM chip via a transistor It is also possible to force CS1 to be enabled at all times This is convenient if an external battery backup device is used that might slow down the transition of CS1 during the memory cycle Most users will not use this feature 3 3V FDV302P Main Power p channel 5ko f NN 1 100 kQ nanm ICS Rabbit 3000 Rabbit 3000 VBAT SRAM RESOUT VDD Figure 8 1 Battery Backup Circuit Chapter 8 Memory Interface and Mapping 115 DATA LINES 8 Rabbi
103. on 40 3 4 2 Exchanges Not Directly Implemented 40 3 4 3 Manipulation of Boolean Variables essere 40 3 4 4 Comparisons of Integers enne eene nete nm 41 Table of Contents 3 4 5 Atomic Moves from Memory to I O 5 43 3 5 Interrupt Str Cture teet A eR 44 3 541 Interrupt Priority oec RU Pet elt ete a A ashe Gree 44 3 5 2 Multiple External Interrupting Devices 22222 4 1 1 010000000 46 3 5 3 Privileged Instructions Critical Sections and Semaphores 46 3 5 4 Critical Sections mee eter er e e RU EURO HIP ORG tests 47 3 5 5 Semaphores Using Bit B HL sess es ettet te beet yaqan chri ree Peri 47 3 5 6 Computed Long Calls and Jumps LL eese eene nennen nennen nennen 48 Chapter 4 Rabbit Capabilities 49 42 Precisely Timed Output Pulses L usus ee tt e HEU E ey LEUR 49 4 1 1 Pulse Width Modulation to Reduce Relay Power eee 50 4 2 Open Drain Outputs Used for Key 5 51 4 3 Cold Boot oce eni nere a ier 52 4 4 The Slave Pott Cerere tbe ete rt EU ERSTER uy 53 4 4 1 Slave Rabbit As A 7 54 Chapter 5 Pin Assignments and Functions 55 35 1 LQFP eene ehe ta emet heec Tr u hasa ao 56 51 1 ieu DERE HO EET PpU Pee
104. operation 1 Timer synchronized clocked serial operation 0 Timer synchronized clocked serial uses Timer B1 1 Timer synchronized clocked serial uses Timer B2 00 Normal clocked serial clock polarity inactive High Internal or external clock 01 Normal clocked serial clock polarity inactive Low Internal clock only 10 Inverted clocked serial clock polarity inactive Low Internal external clock 11 Inverted clocked serial clock polarity inactive High Internal clock only 3 2 XX These bits are ignored in clocked serial mode 0 No effect on transmitter 1 Terminate current clocked serial transmission No effect on buffer 0 No effect on receiver l 1 Terminate current clocked serial reception Chapter 12 Rabbit Serial Ports 177 Table 12 19 Extended Register HDLC Mode Ports E and F only Serial Port x Extended Register SEER Address 0xCD SFER Address 0xDD Bit s Value Description HDLC mode only 000 NRZ data encoding for HDLC receiver and transmitter 010 NRZI data encoding for HDLC receiver and transmitter 7 5 100 Biphase Level Manchester data encoding for HDLC receiver and transmitter 110 Biphase Space data encoding for HDLC receiver and transmitter 111 Biphase Mark data encoding for HDLC receiver and transmitter 0 Normal HDLC data encoding 4 1 Enable RZI coding 1 4th bit cell IRDA compliant This mode only be used with in
105. preload registers that can be clocked into the output registers under timer control for pulse gen eration Port bits of Port E can be configured as I O strobes 4 bits of port E can be used as external interrupt inputs One bit of port E is shared with the slave port chip select Port E has output preload registers that can be clocked into the output registers under timer control for pulse generation Port F As outputs Port F can be configured as open drain outputs Alternatively Par allel Port F outputs can carry the four Pulse Width Modulator outputs As inputs Paral lel Port F inputs can carry the inputs to the two channels of the quadrature decoders Port F pins can also be configured to be used as clock pins for clocked Serial Ports C and D Port G As outputs Port G can be configured as open drain outputs Port G inputs and outputs are also used for access to other serial peripherals on the chip such as those used for asynchronous or SDLC HDLC communication Parallel Ports D G behave in the same manner when used as digital I O NOTE There may be a conflict in using Parallel Port A and Parallel Port F Either Paral lel Port A can be used as inputs in which case Parallel Port F has full function or if Parallel Port A cannot be used as inputs use any pins on Parallel Port F not used for PWM or serial clock outputs as inputs and take the precaution of setting up Parallel Port F before the conflicting functionality of P
106. root data accesses in always segment before data segment segment before root segment enabled quadrant selection quadrant selection To make this clear let s look at an example Suppose a 1 megabyte flash memory is con trolled by CSO WEO and OEO Suppose this memory is accessed as part of the first quadrant and MBOCR is set up to enable CSO WEO or on accesses to this bank Then if A18 and A19 are zero the first 256K of the flash memory will be visible in the first 256K of the physical memory If access is made to the second quadrant the memory will not be selected unless MB1CR is mapped to the flash memory However if A18 is inverted by setting bit 4 in MBOCR to a 1 then the second 256K of the flash will be mapped into the first quadrant A18 will have been inverted but he quadrant does not change because this inversion occurs after the quadrant has been selected The inversion of A19 or A16 controlled by the MMIDR register on D space accesses is used to separate I and D space to different memory locations The separation of I and D space can only occur for the first two memory zones in the64K space For each zone the root code segment and the data segment either or both of 19 and 16 can be inverted The reasoning behind these choices is that a normal memory map places flash memory in the lower 512K of the physical memory space RAM memory begins at 512K By invert ing A19 on D space accesses me
107. set and the register layout of the Z80 and Z180 Compared to the Z180 the instruction set has been augmented by a sub stantial number of new instructions Some obsolete or redundant Z180 instructions have been dropped to make available efficient 1 byte opcodes for important new instructions see Chapter 20 Differences Rabbit vs Z80 Z180 Instructions The advantage of this evolutionary approach is that users familiar with the Z80 or Z180 can immediately under stand Rabbit assembly language Existing Z80 or Z180 source code can be assembled or compiled for the Rabbit with minimal changes Changing technology has made some features of the Z80 Z180 family obsolete and these features have been dropped in the Rabbit For example the Rabbit has no special support for dynamic RAM but it has extensive support for static memory This is because the price of static memory has decreased to the point that it has become the preferred choice for medium scale embedded systems The Rabbit has no support for DMA direct memory access because most of the uses for which DMA is traditionally used do not apply to embedded systems or they can be accomplished better in other ways such as fast inter rupt routines external state machines or slave processors Our experience in writing C compilers has revealed the shortcomings of the Z80 instruc tion set for executing the C language The main problem is the lack of instructions for han dling 16 bit words and
108. spectrum spreader has two operating modes normal spreading and strong spreading The spreader can also be turned off 80 Rabbit 3000 Microprocessor User s Manual 32 768 kHz Clock The 32 768 kHz clock is primarily used to clock the on chip real time clock In addition it is also used to support remote cold boot via Serial Port A driving the 2400 baud commu nications used to initiate the cold boot Another function of the 32 768 kHz oscillator is to drive the low power sleepy mode with the main oscillator shut down to reduce power The 32 768 kHz clock can be left out of a system provided that its functions are not required Rabbit 3000 clock out 9 K lt XTALB1 113 Processor clock 5 2 5 114 XTALB2 Spectrum Clock Spreader Doubler 1 8 6 4 2 1 2 control the power consumed the unbuffered inverter VBAT Divider 1 1 2 4 8 16 R1 SN74AHC1GU04 49 U2A NC7SP14 Peripheral clock EE Watchdog Real Time Note Peripherals Timer Clock cannot be clocked 32 768 kHz slower than processor 1 C24 Reference design for 32 768 kHz oscillator Figure 7 1 Clock Distribution TN235 External 32 768 kHz Oscillator Circuits provides further information on oscilla tor circuits and selecting the values of components to use in the oscillator circuit Chapter 7 Miscellan
109. that has 8 and 16 bit registers 3 2 3 Using the Stack Segment for Data Storage Another approach to extending data memory is to use the stack segment to access data placing the stack in the data segment so as to free up the stack segment This approach works well for a software system that uses data groupings that are self contained and are accessed one at a time rather than randomly between all the groupings An example would be the software structures associated with a TCP IP communication protocol connection where the same code accesses the data structures associated with each connection in a pat tern determined by the traffic on each connection The advantage of this approach is that normal C data access techniques such as 16 bit pointers may be used The stack segment register has to be modified to bring the data structure into view in the stack segment before operations are performed on a particular data structure Since the stack has to be moved into the data area it is important that the number of stacks required be kept to a minimum when using the stack segment to view data Of course tasks that don t need to see the data structures can have their stack located in the stack segment Another possibility is to have a data structure and a stack located together in the stack segment and to use a different stack segment for different tasks each task having its own data area and stack bound to it These approaches are shown in Figure 3
110. the port s con tents For example GCSR has a number of write only bits These can be read by consult ing the shadow provided that the shadow register is always updated when writing to the register k GCSRShadow 18 3 1 Updating Shadow Registers If the address of a shadow register is passed as an argument to one of the functions that write to the internal or external I O registers then the shadow register will be updated as well as the specified I O register A NULL pointer may replace the pointer to a shadow register as an argument to WrPortI and WrPortE the shadow register associated with the port will not be updated A pointer to the shadow register is mandatory for BitWrPortI and BitWrPortE 18 3 2 Interrupt While Updating Registers When manipulating I O registers and shadow registers the programmer must keep in mind that an interrupt can take place in the middle of the sequence of operations and then the interrupt routine may manipulate the same registers If this possibility exists then a solution must be crafted for the particular situation Usually it is not necessary to disable the interrupts while manipulating registers and their associated shadow registers 18 3 2 1 Atomic Instruction As an example consider the Parallel Port D data direction register PDDDR This register is write only and it contains 8 bits corresponding to the 8 I O pins of Parallel Port D If a bit in this register is a 1 the cor
111. the slave port register SPDOR These commands cause data to be stored in memory or I O space When the master that is managing the cold boot has finished setting up memory and I O space the SMODEI SMODEO pins are changed to code 0 0 which causes execution to start at address zero Typically this will start execution of a secondary boot program At some point bit 7 will be set to a 1 so that the SMODEX pins can be used as normal input pins Bits 6 5 be used to read the input pins SMODE SMODEO Bits 3 2 A 10 written to bits 3 2 enables the slave port disabling Parallel Port A and vari ous other port lines Bits 3 2 are automatically set to a 10 if a cold boot is done via the slave port If bit 3 is 0 then bit 2 controls whether Parallel Port A is an input bit 2 0 or an output bit 2 1 A 11 written to bits 3 2 enables the Auxilliarv I O bus Bits 1 0 This 2 bit field sets the priority of the slave port interrupt The interrupt is disabled by 0 0 206 Rabbit 3000 Microprocessor User s Manual Table 13 3 describes the slave port status register The status register has 6 bits that are set if the particular register is full That means that the register has been written by the processor that can write to it but it has not been read by the processor that can read it The bits for SPDOR are used to control the slave interrupt and the handshaking lines as shown in Figure 13 3 Table 13 3 Slave Port
112. transition occurs after the expected bit cell boundary but before the midpoint the DPLL needs to lengthen the count to line up the bit cell boundaries This corresponds to the add one and add two regions shown If a transition occurs before the bit cell boundary but after the midpoint the DPLL needs to shorten the count to line up the bit cell boundaries This corresponds to the subtract one and subtract two regions shown DPLL makes no adjustment if the bit cell bound aries are lined up within one count of the divide by sixteen counter The regions that adjust the count by two allow the DPLL to synchronize faster to the data stream when starting up With Biphase Level encoding there is a guaranteed clock transition at the center of every bit cell and optional data transitions at the bit cell boundaries The DPLL only uses the clock transitions to track the bit cell boundaries by ignoring all transitions occur ring outside a window around the center of the bit cell This window is half a bit cell wide Additionally because the clock transitions are guaranteed the DPLL requires that they always be present If no transition is found in the window around the center of the bit cell for two successive bit cells the DPLL is not in lock and immediately enters the search mode Search mode assumes that the next transition seen is a clock transition and immedi ately synchronizes to this transition No clock output
113. unsigned int mktm struct tm timeptr unsigned long time The format of the structure used is the following struct tm char tm_sec seconds 0 59 char tm min 0 59 char tm hour 0 59 char tm mday 1 31 char tm mon 1 12 char tm year 00 150 1900 2050 char tm wday 0 6 O sunday The day of the week is not used to compute the long seconds but it is generated when computing from long seconds to the structure A utility program setclock c is avail able to set the date and time in the real time clock from the Dynamic C STDIO console Chapter 18 Other Rabbit Software 247 248 Rabbit 3000 Microprocessor User s Manual 19 RABBIT INSTRUCTIONS Summary Load Immediate Data on page 252 Load amp Store to Immediate Address on page 252 8 bit Indexed Load and Store on page 252 16 bit Indexed Loads and Stores on page 252 16 bit Load and Store 20 bit Address on page 253 Register to Register Moves on page 253 Exchange Instructions on page 254 Stack Manipulation Instructions on page 254 16 bit Arithmetic and Logical Ops on page 254 8 bit Arithmetic and Logical Ops on page 255 8 bit Bit Set Reset and Test on page 256 8 bit Increment and Decrement on page 256 8 bit Fast A Register Operations on page 257 8 bit Shifts and Rotates on page 257 Instruction Prefixes on page 258 Block Move Instructions on page 258
114. when the SMODE pins are set to zero The SMODE pins are sampled just prior to fetching the first instruction of the bootstrap program If the SMODE pins are zero instructions are fetched from normal memory starting at address 0x0000 The Slave Port Control register allows the bootstrap operation to be terminated remotely Writing a one to bit 7 of this register causes the bootstrap operation to terminate immediately So the sequence 0x80 0x24 and 0x80 will terminate bootstrap operation Bootstrap operation is not restricted to the time immediately after reset because the boot ROM is addressed by only the four least significant bits of the address So any time that the address ends in four zeros if the SMODE pins are non zero and bit 7 of the SPCR is Zero the bootstrap program will begin execution This allows in line downloading from the selected bootstrap port Upon completion of the bootstrap operation either by return ing the SMODE pins to zero or setting the bit in the SPCR execution will continue from where it was interrupted for the bootstrap operation The Slave Port is selected for bootstrap operation when SMODEI SMODEO 0 1 In this case the pins of Parallel Port A are used for a byte wide data bus and selected pins of Parallel Ports B and E are used for the Slave Port control signals Only Slave Port Data Register 0 is used for bootstrap operation and any writes to the other data registers will be ignored by the processor an
115. will become the output bits on the next match pulse It is neces sary to keep a shadow register for the parallel port unless the bit addressable feature of Ports D and E is used If you wish to read the time from the Timer B counter either during an interrupt caused by the match pulse or in some other interrupt routine asynchronous to the match pulse you will have to use a special procedure to read the counter because the upper 2 bits are in a different register than the lower 8 bits The following method is suggested 1 Read the lower 8 bits read TBCLR register 2 Read the upper 2 bits read TBCMR register 3 Read the lower 8 bits again read TBCLR register 4 If bit 7 changed from 1 to 0 between the first and second read of the lower 8 bits there has been a carry to the upper 2 bits In this case read the upper 2 bits again and decre ment those 2 bits to get the correct upper 2 bits Use the first read of the lower 8 bits This procedure assumes that the time between reads can be guaranteed to be less than 256 counts This can be guaranteed in most systems by disabling the priority 1 interrupts which will normally be disabled in any case in an interrupt routine It is inadvisable to disable the high priority interrupts levels 2 and 3 as that defeats their purpose If speed is critical the three reads of the registers can be performed without testing for the carry The three register values can be saved and the carry test
116. x 1 5 mm LQFP Size of package 10 x 10 x 1 2 mm 24 x 18 x 3 mm PQFP TFBGA k 0 4 mm 16 mils LQFP 0 65 26 mils acing between package pins 65 mm mils PNE FERE 0 8 mm TFBGA Separate power and ground for I O buffers EMI Yes No reduction Rabbit 2000B and Clock Spectrum Spreader EMI reduction Yes Rabbit 2000C versions Clock Modes 1 2x 2 3 4 16 8 1x 2x 4 8 Sleepy 32 kHz Power Down Modes Ultra Sleepy Sleepy 32 kHz 16 8 2 kHz Short CS CLK 4 6 8 Low Power Memory Control Chip Select Self Timed None 32 16 8 2 kHz Extended memory timing for high freq operation Yes No Number of 8 bit I O ports 7 5 Auxiliary I O Data Address bus Yes None Number of serial ports 6 4 Serial ports capable of SPI clocked serial 4 A B C D 2 A B Serial ports capable of SDLC HDLC 2 E F None Asynch serial ports with support for IrDA 6 None communications Chapter 1 Introduction 7 Feature Rabbit 3000 Rabbit 2000 Serial ports with support for SDLC HDLC IrDA 2 None communications Maximum asynchronous baud rate clock speed 8 clock speed 32 Input capture unit 2 None 8 Rabbit 3000 Microprocessor User s Manual 2 RABBIT 3000 DESIGN FEATURES The Rabbit 3000 is an evolutionary design The processor and instruction set are nearly identical to the immediate predecessor processor the Rabbit 2000 Both the Rabbit 3000 and the Rabbit 2000 follow in broad outline the instruction
117. x x x adr 0x07C PEBSR W x x PE5 x x x x x adr 0x07D PEB6R W x PE6 x x x x x x adr 0x07E PEB7R W PE7 x x x x x x x adr 0 07 Table 9 12 Parallel Port E Control Register adr 0x074 Bits 7 6 Bits 5 4 Bits 3 2 Bits 1 0 00 clock upper nibble on pclk 2 00 clock lower nibble on pclk 2 01 clock on timer A1 01 clock on timer A1 n 10 clock on timer B1 iia 10 clock on timer B1 11 clock on timer B2 11 clock on timer B2 Chapter 9 Parallel Ports 139 9 6 Parallel Port F Parallel Port F is a byte wide port with each bit programmable for data direction and drive These are simple inputs and outputs controlled and reported in the Port F Data Register As outputs the bits of the port are buffered with the data written to the Port F Data Regis ter transferred to the output pins on a selected timing edge The outputs of Timer A1 Timer B1 or Timer B2 can be used for this function with each nibble of the port having a separate select field to control this timing These inputs and outputs are also used for access to other peripherals on the chip As out puts the Parallel Port F outputs can carry the four Pulse Width Modulator outputs As inputs Parallel Port F inputs can carry the inputs to the quadrature decoders When Serial Port C or Serial Port D is used in the clocked serial mode two pins of Parallel Port F are used to carry the serial clock si
118. 0 Al SA1 SMODEO CLK XTALB1 portout HTH RESET SMODE 1 INTOA SLAVEATTN Hr SCS INT1A 16 Second Slave Rabbit Reset Pulldown SMODEO SMODE 1 SLAVEATTN SCS Figure 13 4 Typical Connection Slave Rabbit to Master Rabbit 13 1 Hardware Design of Slave Port Interconnection The designer has the option of cold booting the slave and downloading the program to RAM on each cold start Another option is to configure the slave with both RAM and flash memory In this case the slave will only have the program downloaded for maintenance or upgrades Usually the flash would not be written to on every startup because of the lim ited number of lifetime writes to flash memory The slaves reset in Figure 13 4 is under the program control of the master If the master is reset the slave will also be reset because the master s drive of the reset line will be lost on reset and the pulldown resistor will pull the slaves resets low This may be undesirable because it forces the slave to crash if the master crashes and has a watchdog timeout 204 Rabbit 3000 Microprocessor User s Manual 13 2 Slave Port Registers The slave port registers are listed in Table 13 1 These registers each of which is actually two separate registers one for read and one for write are accessible to the slave at the I O addresses shown in the table and they are accessible to the master at the external address shown which spe
119. 0 25 mm 14 00 0 10 mm 14 00 0 10 mm 16 00 0 25 mm 64 lt 0 18 0 05 mm 1 40 0 05 mm Y 0 40 0 10 0 05 The same dimensions apply along the x axis and the y axis 0 10 mm lt 0 60 _ 0 15 Figure 5 2 Mechanical Dimensions Rabbit LQFP Package Chapter 5 Pin Assignments and Functions 57 Figure 5 3 shows the PC board land pattern for the Rabbit 3000 chip in a 128 pin LQFP package This land pattern is based on the IPC SM 782 standard developed by the Surface Mount Land Patterns Committee and specified in Surface Mount Design and Land Pat tern Standard IPC Northbrook IL 1999 16 85 mm max 13 75 mm min 13 75 mm min 16 85 mm max 0 28 mm max gt 12 4 mm A 1 55 mm Y 12 4 mm 15 3 mm TOLERANCE AND SOLDER JOINT ANALYSIS Jr 0 29 0 55 mm 0 29 0 604 mm Jg 0 01 0 077 mm Lmin Z max 16 85 mm Gmin 13 75 mm 0 28 lt 2 Side Fillet Toe Fillet Heel Fillet J
120. 00x000 Global Output Control Register GOCR OxOE W 00000000 Global Clock Double Register GCDR OxOF W 00000000 MMU Instruction Data Register MMIDR 0 10 R W 00000000 MMU Common Base Register STACKSEG Ox11 R W 00000000 MMU Bank Base Register DATASEG 0x12 R W 00000000 MMU Common Bank Area Register SEGSIZE 0x13 R W 11111111 Memorv Bank 0 Control Register MBOCR 0 14 00001000 Memory Bank 1 Control Register MBICR Ox15 w XXXXXXXX Memory Bank 2 Control Register MB2CR 0x16 Memory Bank 3 Control Register MB3CR 0x17 w XXXXXXXX MMU Expanded Code Register MECR 0 18 R W xxxxx000 Memory Timing Control Register MTCR 0 19 0000 Breakpoint Debug Control Register BDCR Ox1C W OXXXXXXX Slave Port Data 0 Register SPDOR 0x20 R W XXXXXXXX Slave Port Data 1 Register SPDIR 0 21 R W XXXXXXXX Slave Port Data 2 Register SPD2R 0x22 R W XXXXXXXX Slave Port Status Register SPSR 0x23 R 00000000 Slave Port Control Register SPCR 0x24 R W 0xx00000 Global ROM Configuration Register GROM 0x2C 0xx00000 Global RAM Configuration Register GRAM 0x2D 0xx00000 Global CPU Configuration Register GCPU 0 2 Oxx00001 Chapter 6 2 Rabbit Internal I O Registers 73 Table 6 2 Rabbit Internal I O Registers continued Register Name Mnemonic I O Address R W Reset Global Revision Register GREV Ox2F R 0 00000 Port Data Register
121. 101 INC IY d 11111101 INC IX 11011101 INC IY 11111101 INC r 00 r 100 INC ss 00ss0011 ss 00 BC 01 DE IOE 11011011 IOI 11010011 IPSET 0 11101101 IPSET 1 11101101 IPSET 2 11101101 IPSET 3 11101101 IPRES 11101101 JP HL 11101001 JP IX 11011101 JP IY 11111101 JP mn 11 010 JP mn 11000011 JR 001cc000 JRe 00011000 Note If byte following op code is zero is executed LCALL xpc mn LD BC A LD DE A LD HL n LD HL r LD HL d HL LD IX d HL LD IX4d n LD IX4d r LD IY d HL LD IY d n LD IY d r LD mn A LD mn HL LD mn IX LD mn IY LD mn ss LD SP n HL LD SP n IX LD SP n IY 11001111 00000010 00010010 00110110 01110 r 11011101 11110100 11011101 11011101 11111101 11111101 11111101 00110010 00100010 11011101 11111101 11101101 11010100 11011101 11111101 Byte 2 11100011 11100011 00110100 00110100 00100011 00100011 10 HL 11 SP 01000110 01010110 01001110 01011110 01011101 11101001 11101001 es EZ 2 2 n n 11110100 d 00110110 01110 r 11110100 00110110 01110 r p ss 00100010 00100010 01550011 11010100 11010100 Byte 3 sELIdizc ad Z m m m ia a d 2258 4225 ee 2222d2c ad 22522423 Sum Et n n Byte 4 clk OY KR d g
122. 11 ns Max clock to memory write strobe delay Twex 6 ns 8 ns 11 ns Max high Z to data valid rel to clock Tpgzy 10 ns 12 ns 15 ns Max data valid to high Z rel to clock Tpygz 10 ns 12 ns 15 ns The measurements were taken at the 5096 points under the same conditions that the mem ory read delays were measured See Table 16 2 for delays at other voltages 220 Rabbit 3000 Microprocessor User s Manual Memory Read no wait states A 19 0 CSx _ j gt Tesx gt 1 OEx E Togx I lt ToEx D 7 0 A 19 0 CSx IWEX D 7 0 Figure 16 3 Memory Read and Write Cycles Early Output Enable and Write Enable Timing Chapter 16 AC Timing Specifications 221 Figure 16 4 illustrates the sources that create memory access time delays clock period shortening 4 amp due to spectrum spreader Clock clock to address output lt data out memory access time r data in setup time output enabl early a memory output enable time Figure 16 4 Sources of Memory Access Time Delays The gross memory access time is 2T where T is the clock period To calculate the actual memory access time subtract the clock to address output time the data in setup time and the clock period shortening due to the clock spectrum spreader from
123. 14 Rabbit 3000 Microprocessor User s Manual Table 15 1 Spread Spectrum Enable Disable Register Global Clock Modulator 0 Register GCM0R Address 0x0A Bit s Value Description 0 Enable normal spectrum spreading 1 1 Enable strong spectrum spreading 6 0 These bits are reserved Table 15 2 Spread Spectrum Mode Select Global Clock Modulator 1 Register GCM1R Address 0x0B Bit s Value Description 0 Disable the spectrum spreader 1 Enable the spectrum spreader 6 0 These bits are reserved When the spectrum spreader is engaged the frequency is modulated and individual clock cycles may be shortened or lengthened by an amount that depends on whether the clock doubler is engaged and whether the spectrum spreader is set to the normal or strong set ting The frequency modulation amplitude and the change in clock cycle length is greater at lower voltages or higher temperatures since it Is sensitive to process parameters The spectrum spreader also introduces a time offset in the system clock edge and an equal off set in edges generated relative to the system clock A feedback system limits the worst case time error of any signal edge derived from the system clock to plus or minus 20 ns for the normal setting and plus or minus 40 ns for the strong setting at 3 3 V The maximum time offset is inversely proportional to operating voltage The time error will not usually interfere
124. 191 12 9 Serial Port Software Suggestions The receiver and transmitter share the same interrupt vector but it is possible to make the receive and transmit interrupt service routines ISRs separate by dispatching the interrupt to either of two different routines This is desirable to make the ISR less complex and to reduce the interrupt off time No interrupts will be lost since distinct interrupt flip flops exist for receive and transmit The dispatcher can test the receiver data register full bit to dispatch If this bit is on the interrupt is dispatched for receive otherwise for transmit The receiver receives first consideration because it must be serviced attentively or data could be lost The dispatcher might look as follows interrupt PUSH AF 10 IOI LD A SCSR 7 get status register serial port C JP m receive 7 go service the receive interrupt i else service transmit interrupt The individual interrupts would assume that register AF has been saved and the status reg ister has been loaded into Register A The interrupt service routines can as a matter of good practice and obtaining optimum performance remove the cause of the interrupt and re enable the interrupts as soon as pos sible This keeps the interrupt latency down and allows the fastest transmission speed on all serial ports All the serial ports will normally generate priority level 1 interrupts In exceptional circum stances one or more serial ports can b
125. 2 Rabbit Internal I O Registers continued Register Name Mnemonic I O Address R W Reset Port E Bit 7 Register PEB7R Ox7F w XXXXXXXX Port F Data Register PFDR 0x38 R W XXXXXXXX Port F Control Register PFCR 0x3C w xx00xx00 Port F Function Register PFFR 0x3D w XXXXXXXX Port F Drive Control Register PFDCR 0x3E W XXXXXXXX Port F Data Direction Register PFDDR Ox3F W 00000000 Port G Data Register PGDR 0x48 R W XXXXXXXX Port G Control Register PGCR 0 4 xx00xx00 Port G Function Register PGFR 0x4D w XXXXXXXX Port G Drive Control Register PGDCR Ox4E Port G Data Direction Register PGDDR 0x4F w 00000000 Input Capture Ctrl Status Register ICCSR 0x56 R W 00000000 Input Capture Control Register ICCR 0x57 00 Input Capture Trigger 1 Register ICTIR 0x58 w 00000000 Input Capture Source 1 Register ICSIR 0x59 w XXXXXXXX Input Capture LSB 1 Register ICLIR 0 5 R XXXXXXXX Input Capture MSB 1 Register ICMIR 0 58 R XXXXXXXX Input Capture Trigger 2 Register ICT2R 0x5C W 00000000 Input Capture Source 2 Register ICS2R 0 5 Input Capture LSB 2 Register ICL2R 0 5 R XXXXXXXX Input Capture MSB 2 Register ICM2R 0 5 R XXXXXXXX Bank 0 Control Register IBOCR 0x80 W 000000xx I O Bank 1 Control Register IBICR 0x81 W 000000xx Bank 2 Control Register IB2CR 0x82 W 000000xx Bank 3 Control
126. 2 kHz clock frequency By conven tion 12 AM on January 1 1980 is taken as time zero Rabbit Semiconductor software ignores the highest order bit giving the counter a capacity of 136 years from January 1 1980 To read the counter value the value is first transferred to a 6 byte holding register Then the individual bytes may be read from the holding registers To perform the transfer any data bits are written to RTCOR the first holding register The counter may then be read as six 8 bit bytes at RTCOR through RTCSR The counter and the 32 kHz oscillator are powered from a separate power pin that can be provided with power while the remain der of the chip is powered down This design makes battery backup possible Since the processor operates on a different clock than the RTC there is the possibility of performing a transfer to the holding registers while a carry is taking place resulting in incorrect infor mation In order to prevent this the processor should do the clock read twice and make sure that the value is the same in both reads If the processor is itself operating at 32 kHz the read clock procedure must be modified since a number of clock counts would take place in the time needed by the slow clocked processor to read the clock An appropriate modification would be to ignore the lower bytes and only read the upper 5 bytes which are counted once every 256 clocks or every 1 128th of a second If the read cannot be performed in this ti
127. 21 3 1 Processot REpisters u 21 9 2 Memory Mapping 23 3 2 1 Extended Code e teni teh era eere s Hoe apte Est 26 3 2 2 Separate I and D Space Extending Data 2 27 3 2 3 Using the Stack Segment for Data Storage 29 3 2 4 Practical Memory Considerations a aaa a 30 3 3 Instruction Set Outline 32 3 3 1 Load Immediate Data to a Register 33 3 3 2 Load or Store Data from or to a Constant Address sse 33 3 3 3 Load or Store Data Using an Index Register sese 34 3 3 4 Register to Register Move enne eene nennen enter tannar nra 35 3 3 5 Register Exchanges ayu oeste erre eee beet p Erbe bete been 35 3 3 6 Push and Pop Instructions 36 3 3 7 16 bit Arithmetic and Logical Ops Lu 36 3 3 8 Input Ou tput Instr ctlOns iter eter rte better etre te Op EEKE ETE EEE E 39 3 4 How to Do It in Assembly Language Tips and Tricks eee 40 3 4 1 Zero HL in 4 Clocks erionenn eese amapas estet nes En earns ase
128. 3 276 294 300 opcodes 295 I O read time delays 226 pin descriptions 62 Rabbit Semiconductor write time delays 226 alternate functions 65 tete 1 instruction and data space pinout RAM segment relocation 293 support 125 BGA package 59 TEQISTETS 21 power consumption 236 LQFP package 56 accumulators 22 read and write cycles no wait ports alternate registers 22 states 219 221 Rabbit slave port 199 BDCR een 124 read time delays 220 slave port lines 200 clocked serial port status write time delays 220 slave port registers 205 registers 171 memory interface 25 119 power consumption 85 231 default values 73 battery backup 115 clock sm 237 238 GCDR tre 83 SRAM eiecti 115 Dynamic 243 215 321 typical connections 116 mechanisms 234 GCPU 80 284 321 memory mapping 117 Inemoty iecit tte 236 eke dished 82 memory mapping unit 23 24 sleepy mode 233 235 eet 90 memory protection 286 power man
129. 3 0 635 2 5 0 380 1 8 0 252 Design Recommendations e Add current limiting resistors to reduce current without inhibiting oscillator start up e Increase the 1 MQ resistor to improve gain e Minimize loop area to reduce EMI 238 Rabbit 3000 Microprocessor User s Manual 17 RABBIT BIOS AND VIRTUAL DRIVER When a program is compiled by Dynamic C for a Rabbit target the Virtual Driver is auto matically incorporated into the program Virtual Driver is the name given to some initial ization routines and a group of services performed by the periodic interrupt The Rabbit BIOS software that handles startup shutdown and various basic features of the Rabbit is compiled to the target along with the application program Rabbit Semiconductor provides the full source code for the BIOS and Virtual Driver so the user can modify them and examine details of the operation that are not apparent from the documentation More details on the BIOS and Virtual Driver software can be found in the Dynamic C User s Manual the Rabbit 3000 Designer s Handbook and the source code in the Dynamic C libraries 17 1 The BIOS The BIOS provided with Dynamic C will work with all Rabbit board products The BIOS is compiled separately from the user s application It occupies space at the bot tom of the root code segment When execution of the user s program starts at address zero on power up or reset it starts in the BIOS When Dynamic C co
130. 3000A provides greater flexibility for multiplexing I O functions to other pins The following alternate connections were introduced in the Rabbit 3000A for these peripherals and are indicated by an asterisk in Table 5 2 e Slave port CS ASCS Alternate slave port chip select input e Serial Ports E F ARXE Alternate Serial Port E receive ARCLKE Alternate Serial Port E receive clock HDLC ARXF Alternate Serial Port F receive ARCLKF Alternate Serial Port F receive clock HDLC e PWM outputs APWM3 Alternate PWM output bit 3 APWM2 Alternate PWM output bit 2 APWMI Alternate PWM output bit 1 Alternate PWM output bit 0 318 Rabbit 3000 Microprocessor User s Manual APPENDIX C SYSTEM USER MopE The Rabbit 3000A is the first Rabbit microprocessor to incorporate a system user mode The purpose of the System User mode is to provide two tiers of control in the CPU sys tem which provides full access to all processor resources and user a more restricted mode Table C 1 describes the essential differences between the System mode and the User mode The System mode is essentially the same as the normal operation of the Rabbit 3000 and earlier processors Table C 1 Differences Between System and User Modes System Mode User Mode All peripherals accessible No peripherals accessible by default All processor control registers available No processor control registers available All interrupt prioritie
131. 56 5 1 2 Mechanical Dimensions and Land Pattern 57 9 2 Ball Grid Package iii e sau Na SD sean eee enr he 59 2 25 5 I 59 5 2 2 Mechanical Dimensions and Land Pattern 042224 1000100100000000000 eene 60 X Rabbit Pin a LI Sp d tet aa e a p A 62 3 4 ates ii e n ek Ss One eS te 64 5 5 Description of Pins with Alternate Functions 65 5 6 DC Characteristics i UG a es 68 5 7 I O Buffer Sourcing and Sinking Limit san enne ene 69 Chapter 6 Rabbit Internal I O Registers 71 6 1 Default Values for all the Peripheral Control 73 Chapter 7 Miscellaneous Functions 79 7 1 Processor Identification eee bu ara Spa p pa B B REESE 79 7 2 Rabbit Oscillators and Clocks et inei ert t hte 80 7 37 Clock Doubler tonio rene REOR re IP e er ien 83 7 4 Clock Spectrum Spreader ic iie e eed e h uuu pede aus 86 7 5 Chip Select Options for Low Power LL nee 87 7 6 Output Pins CLK STATUS WDTOUT 90 7 7 Time Date Clock Real Time Clock
132. 58 read and write timing 64 mechanical dimensions 57 PINOUT 56 Index 337 M P R memory Parallel Port D Rabbit 3000 A16 A19 inversions CS1 open drain outputs 51 block diagram 5 enable 121 parallel ports 129 comparison with Rabbit 2000 access time 217 conflict between Port A and 2s 261 access time delays 222 Port Es 129 141 crystal frequencies 273 access times with clock Parallel Port A 130 design features 9 doubler 223 Parallel Port B 131 features scies ees 1 allocation of extended code Parallel Port C 132 list of advantages 6 and data space 124 Parallel Port D 133 on chip peripherals 11 breakpoint debug controller Parallel Port E 137 programing port 271 124 Parallel Port F 140 revision history 275 278 compiler operation 128 Parallel Port G 143 specifications 2 4 data and clock delays 218 periodic interrupts 3 72 Rabbit 3000A D space 126 82 93 149 194 240 243 internal I O registers 329 I O access time 225 27
133. 7 below Chapter 3 Details on Rabbit Microprocessor Features 29 Stack Segment used as data Stack Segment d window gt used for stack Data Segment used as data window Stacks in data Data segment Data RAM RAM Root Segment mapped to Root RAM has both Root Code root code and Code flash qata RAM Using Stack Segment Using Data Segment for for a Data Window a Data Window Code must be copied to RAM on startup Figure 3 7 Schemes for Data Memory Windows A third approach is to place the data and root code in RAM in the root segment freeing the data segment to be a window to extended memory This requires copying the root code to RAM at startup time Copying root code to RAM is not necessarily that burdensome since the amount of RAM required can be quite small say 12K for example The XPC segment at the top of the memory can also be used as a data segment by pro grams that are compiled into root memory This is handy for small programs that need to access a lot of data 3 2 4 Practical Memory Considerations The simplest Rabbit configurations have one flash memory chip interfaced using CSO and one RAM memory chip interfaced using CS1 Typical Rabbit based systems use 256K of flash and 128 K of RAM but smaller or larger memories may be used Although the Rabbit can support code size approaching a megabyte it is anticipated that the majori
134. 70 W 00000000 Parallel Port F User Enable Register PFUER 0x0338 W 00000000 Parallel Port G User Enable Register PGUER 0x0348 W 00000000 Input Capture User Enable Register ICUER 0x0358 W 00000000 Bank User Enable Register IBUER 0 0380 W 00000000 PWM User Enable Register PWUER 0x0388 W 00000000 Quad Decode User Enable Register QDUER 0x0390 W 00000000 External Interrupt User Enable Register IUER 0x0398 W 00000000 Timer A User Enable Register TAUER 0 03 0 W 00000000 Timer User Enable Register TBUER 0x03BO W 00000000 Serial Port A User Enable Register SAUER 0 03 0 W 00000000 Serial Port B User Enable Register SBUER 0 3 W 00000000 Serial Port C User Enable Register SCUER 0x3E0 W 00000000 Serial Port D User Enable Register SDUER 0x3F0 W 00000000 Serial Port E User Enable Register SEUER 0x03C8 W 00000000 Serial Port F User Enable Register SFUER 0x3D8 W 00000000 Appendix C System User Mode 321 The I O banks on Port E enabled for the User mode by IBUER have a slightly different operation in the User mode Disabling user access to a given I O bank not only causes writes to the corresponding IBxCR register to be ignored in the User mode but also inhib its the strobe associated with that I O bank Access to the internal I O registers listed in Table C 4 is always denied in the User mode Table C 4 I O Addresses Inaccessible in User Mode
135. AR Serial Port A Tx Write data to the SADR SAAR SALR or write a dummy byte to the SASR Rx Read the data from the SBDR or SBAR Serial Port B Tx Write data to the SBDR SBAR SBLR or write a dummy byte to the SBSR Rx Read the data from the SCDR or SCAR Serial Port C Tx Write data to the SCDR SCAR SCLR or write a dummy byte to the SCSR Rx Read the data from the SDDR or SDAR Lowest Serial Port D Tx Write date to the SDDR SDAR SDLR or write a dummy byte to the SDSR In the case of the external interrupts the only action that will clear the interrupt request is for the interrupt to take place which automatically clears the request A special action must be taken in the interrupt service routine for the other interrupts 98 Rabbit 3000 Microprocessor User s Manual 7 10 1 External Interrupts There are two external interrupts Each interrupt has two input pins that can be used to trigger the interrupt The inputs have a pulse catcher that can detect rising falling or both edges The pulse needs to be present for a least three peripheral clocks to be detected INT1A PE1 pulse catcher N l je gt INT1B PE5 pulse catcher 1 interrupt acknowledge INTOA PEO pulse a INTOB PEAJ pulse catcher 0 interrupt acknowledge Figure 7 6 External Interrupt Line Logic The ext
136. B This is a very large reduction since it is common to struggle to reduce EMI by 5 dB in order to pass government tests 15 dB _ Strong Spreading 10 2 Y Normal Spreading 5 50 100 150 200 250 300 350 Figure 15 1 Peak Spectral Amplitude Reduction from Spectrum Spreader The spectrum spreader modulates the clock so as to spread out the spectrum of the clock and its harmonics Since the government tests use a 120 kHz bandwidth to measure EMI spreading the energy of a given harmonic over a wider bandwidth will decrease the amount of EMI measured for a given harmonic The spectrum spreader not only reduces the EMI measured in government tests but it will also often reduce the interference cre ated for radio and television reception The spectrum spreader has three settings under software control see Table 15 1 and Table 15 2 off standard spreading and strong spreading Two registers control the clock spectrum spreader These registers must be loaded in a spe cific manner with proper time delays GCMOR is only read by the spectrum spreader at the moment when the spectrum spreader is enabled by storing 0x080 in GCMIR If GCMIR is cleared when disabling the spectrum spreader there is up to a 500 clock delay before the spectrum spreader is actually disabled The proper procedure is to clear GCMIR wait for 500 clocks set GCMOR and then enable the spreader by storing 0x080 in GCMIR 2
137. BIOS waits until this oscillator is oscillating regularly before continuing the startup procedure If the clock is battery backed there will be no startup delay since the oscillator is already oscillating The startup delay may be as much as 5 seconds Crys tals with low series resistance R lt 35 kQ will start faster Chapter 14 Rabbit 3000 Clocks 211 14 1 Low Power Design The power consumption is proportional to the clock frequency and to the square of the operating voltage Thus operating at 3 3 V instead of 5 V will reduce the power consump tion by a factor of 10 9 25 or 43 of the power required at 5 V The clock speed is reduced proportionally to the voltage at the lower operating voltage Thus the clock speed at 3 3 V will be about 2 3 of the clock speed at 5 V The operating current is reduced in proportion to the operating voltage The Rabbit 3000 does not have a standby mode that some microprocessors have Instead the Rabbit has the ability to switch its clock to the 32 768 kHz oscillator This is called the sleepy mode When this is done the power consumption is decreased dramatically The current consumption is often reduced to the region of 100 u A at this clock speed The Rabbit executes about 6 instructions per millisecond at this low clock speed Generally when the speed is reduced to this extent the Rabbit will be in a tight polling loop looking for an event that will wake it up The clock speed is increased to wake
138. C7 in drive PC5 in PC3 in drive PCl in drive PCDR COR PC6 x PCA x PC2 x PCO adr 0x050 PCFR w Drive 2 Drive Drive Drive adr 0x055 TXA TXB TXC TXD Parallel Port C shares its pins with serial ports A D The parallel port inputs can be config ured as serial port inputs while the dedicated outputs as serial port outputs When serving as serial inputs the data lines can still be read from the Parallel Port C data register The parallel port outputs can be selected to be serial port outputs by setting the corresponding bit positions in the Port C Function register PCFR When a parallel port output pin is selected to be a serial port output the value stored in the data register is ignored On reset the active even numbered function register bits are zeroed resulting in Port C to behave as an I O port Bit 6 of the Port C data register is zeroed while the remaining even numbered bits are set to 1 132 Rabbit 3000 Microprocessor User s Manual 9 4 Parallel Port D Parallel Port D shown in Figure 9 1 has eight pins that can be programmed individually to be inputs or outputs When programmed as outputs the pins can be individually selected to be open drain outputs or standard outputs Port D pins can be addressed by bit if desired The output registers are cascaded and timer controlled making it possible to generate precise timing pulses Port D bits 4 and 5 can be used as alternate
139. DA bug fix 278 Rabbit 3000 Microprocessor User s Manual B 1 1 Rabbit Internal I O Registers Table B 2 summarizes the reset state of the new I O registers added in the Rabbit 3000A revision Table B 3 summarizes the reset state of the existing I O registers with new features Table B 2 Reset State of New Rabbit 3000A I O Registers Register Name Mnemonic A ET R W Reset Secondary Watchdog Timer Register SWDTR 0 000 W 11111111 RAM Segment Register RAMSR 0x0448 W 00000000 Write Protect Control Register WPCR 0x0440 W 00000000 Stack Limit Control Register STKCR 0x0444 W 00000000 Stack Low Limit Register STKLLR 0x0445 W Stack High Limit Register STKHLR 0x0446 W Write Protect Low Register WPLR 0x0460 W 00000000 Write Protect High Register WPHR 0x0461 W 00000000 Write Protect Segment A Register WPSAR 0x0480 W 00000000 Write Protect Segment A Low Register WPSALR 0x0481 W 00000000 Write Protect Segment A High Register WPSAHR 0x0482 W 00000000 Write Protect Segment B Register WPSBR 0x0484 W 00000000 Write Protect Segment B Low Register WPSBLR 0x0485 W 00000000 Write Protect Segment B High Register WPSBHR 0x0486 W 00000000 Real Time Clock User Enable Register RTUER 0x0300 W 00000000 Slave Port User Enable Register SPUER 0x0320 W 00000000 Parallel Port A User Enable
140. FLR Address 0xDA Bit s Value Description Read Returns the contents of the receive buffer 7 0 Write Loads the transmit buffer with an address byte marked with a one address bit for transmission In HDLC mode the last byte of a frame is written to this register to enable subsequent closing Flag transmission Chapter 12 Rabbit Serial Ports 169 Table 12 11 Status Register Asynchronous Mode Only All Ports Serial Port x Status Register SASR Address 0xC3 SBSR Address 0xD3 SCSR Address 0xE3 SDSR Address 0xF3 SESR Address 0xCB SFSR Address 0xDB Bit s Value Description Async mode only 0 The receive data register is empty no input character is ready There is a byte in the receive buffer The transition from 0 to 1 sets the 7 receiver interrupt request flip flop The interrupt FF is cleared when the character 1 is read from the data buffer The interrupt FF will be immediately set again if there are more characters available in the FIFO or shift register to be transferred into the data buffer 0 The byte in the receive buffer is data received with a valid Stop bit Address bit or 9th 8th bit received This bit is set if the character in the receiver data register has a 9th 8th bit This bit is cleared and should be checked before 6 reading a data register since a new data value with a new address bit may be 1 loaded immediate
141. IX IY in eight clocks DEC HL 1 goes to zero zero goes to 1 BOOL HL 1 to 1 zero to zero 4 clocks total Logical xor operator xor HL DE when HL DE are 1 or 0 ADD HL DE RES 0x1 L 6 clocks total clear bit 1 result of if l L 2 40 Rabbit 3000 Microprocessor User s Manual 3 4 4 Comparisons of Integers Unsigned integers may be compared by testing the zero and carry flags after a subtract operation The zero flag is set if the numbers are equal With the sBc instruction the carry cleared is set if the number subtracted is less than or equal to the number it is subtracted from 8 bit unsigned integers span the range 0 255 16 bit unsigned integers span the range 0 65535 OR A SBC HL DE A gt B C A lt B 2 gt amp lt v 2 Clear carry HL A and DE B Z If the value ss is in HL and the value tt is in DE these operations can be performed as follows assuming that the object is to set HL to 1 or 0 depending on whether the compare is true or false compute HL DE unsigned integers EX DE HL OR A SBC HL DE SBC HL HL BOOL HL 7 7 7 7 7 uncomment for DE lt HL clear carry C set if HL lt DE HL HL C 1 if carry set set to l if carry else zero else result unsigned integers compute HL gt DE or DE gt HL check for IC EX DE HL OR A SBC HL DE SBC HL HL INC HL 7 7 r 7 7 7 uncomment for DE lt HL clear carry C if HL g
142. LEWIS DS pibe tre rie RE 253 19 7 Exchange Instructions 5 S Bao Iter te icc ce be E cases Plebe epe iei 254 19 8 Stack Manipulation Instructions eene enne ene a rete 254 19 9 16 bit Arithmetic and Logical ener 254 19 10 8 bit Arithmetic and Logical Ops ener enin nennen tenens 255 19 11 85bit Bit Set Resetand Test ineat aiat A es 256 19 12 8 bit In rement and Decrement eet teque re pre eere 256 19 13 8 bit Fast A Register Operations ens nn ners nn rennen nennen trennen teen ene 257 19 14 8S bit Shifis and Rotates 5 c neteecettei ee rt eem PEOR 257 19 15 Instruction Prefixes caes ede NA Ae Ae OA AN 258 Rabbit 3000 Microprocessor User s Manual 19 16 Block Move Instructions ccccccecesssesssscececceceecececescscesesesscsnecscsescsusescscscseseceseseeseeseseserseeenenaes 258 19 17 Control Instructions Jumps and Calls nn ners ern snanar nsa 259 19 18 Miscellaneous Instructions 2 00 ce eescesecessecenseceeeecsseeecceesecesaecescecsaeeeaceseeeesaeceeecsaeeeaaeceneeceeeeeeeee 259 19 19 Privileged Instructions egere eut RU Re dre ES 260 Chapter 20 Differences Rabbit vs Z80 Z180 Instructions 261 Chapter 21 Instructions in Alphabetical Order With Binary Encoding 263 Appendix A The Rabbit Programming Port 271
143. Mnemonic Address R W Reset Serial Port D Data Register SDDR OxFO R W XXXXXXXX Serial Port D Address Register SDAR 0 1 Serial Port D Long Stop Register SDLR OxF2 Serial Port D Status Register SDSR OxF3 R 0xx00000 Serial Port D Control Register SDCR OxF4 w xx000000 Serial Port D Extended Register SDER OxF5 00000000 Table 12 6 Serial Port E Registers Register Name Mnemonic Address R W Reset Serial Port E Data Register SEDR 0xC8 R W XXXXXXXX Serial Port E Address Register SEAR 0xC9 Serial Port E Long Stop Register SELR Serial Port E Status Register SESR OxCB R 0xx00000 Serial Port E Control Register SECR 0 000000 Serial Port E Extended Register SEER 0xCD 000 000 Table 12 7 Serial Port F Registers Register Name Mnemonic Address R W Reset Serial Port F Data Register SFDR OxD8 R W XXXXXXXX Serial Port F Address Register SFAR 0 9 Serial Port F Long Stop Register SFLR OxDA W XXXXXXXX Serial Port F Status Register SFSR OxDB R 0xx00000 Serial Port F Control Register SFCR OxDC W xx000000 Serial Port F Extended Register SFER OxDD W 000x000x Chapter 12 Rabbit Serial Ports 167 Table 12 8 Data Register All Ports Serial Port x Data Register SADR Address 0xC0 SBDR Address 0xD0 SCDR Address OxEO SDDR Address 0xF0 SEDR Addre
144. Note that RxA is sampled by the rising edge of 1 A __ Nf CLKA 7 Ext RxA m Figure 12 8 Synchronous Serial Data Receive Timing with External Clock Mode 00 When clocking the Rabbit externally the maximum serial clock frequency is limited by the amount of time required to synchronize the external clock with the Rabbit percik If we sum the maximum number of percik cycles required to perform clock synchroniza tion for each of the receive and transmit cases then the fastest external serial clock fre quency would be limited to perc1k 6 186 Rabbit 3000 Microprocessor User s Manual 12 8 Synchronous Communications on Ports E and F Serial Port E and F are a dual function serial ports that can be used in either asynchronous or HDLC mode Four bytes of buffering are available for both receiver and transmitter to reduce interrupt overhead An interrupt is generated whenever at least one byte is avail able in the receiver buffer and every time a byte is removed from the transmitter buffer Serial Port E is clocked by the output of Timer A2 and Serial Port F by A3 In asynchro nous mode this clock can be either sixteen the default or eight times the data rate In HDLC mode this clock is sixteen times the data rate Note that the fastest output from Timer A2 or A3 is the same frequency as the peripheral clock Thus the maximum data rate is the peripheral clock frequency divided by
145. One station enables its driver and sends a message After the message is complete the station disables the driver and listens to the line for a reply The driver must be enabled before the start bit is sent and not dis abled until the stop bit has been sent The transmitter idle interrupt is normally used to dis able the RS 485 driver and possibly enable the receiver 12 9 2 Transmitting Dummy Characters It may be desired to operate the serial transmitter without actually sending any data Dummy characters are transmitted to pass time or to measure time The output of the transmitter may be disconnected from the transmitter output pin by manip ulating the control registers for Parallel Port C or D which are used as output pins For example if Serial Port B is to be temporarily disconnected from its output pin which is bit 4 of Parallel Port C this can be done as follows 1 Store a 1 in bit 4 of the parallel port data output register to provide the quiescent state of the drive line Chapter 12 Rabbit Serial Ports 193 2 Clear bit 4 of the Parallel Port C function register so that the output no longer comes from the serial port Of course this should not be done until the transmitter is idle A similar procedure can be used if the serial port is set up to use alternate output pins on port D Only Serial Ports A and B can use alternate outputs on Parallel Port D If an RS 485 driver is being used dummy characters can be tr
146. P OUTI IND OUTD INIR OTIR INDR OTDR TESTIO MLT SP RRD RLD CPI CPIR CPD CPDR Most of these op codes deal with I O devices and thus do not represent transportable code The only opcodes that are not processor I O related are MLT SP DAA RRD RLD CPI CPIR CPD and CPDR MLT SP is not a practical op code The codes that are concerned with decimal arithmetic DAA RRD and RLD could be simulated but the simulation is very inefficient The bit in the status register used for half carry is available and can be set and cleared using the PUSH AF and POP AF instructions to gain access Usually code that uses these instructions should be rewritten The instructions CPI CPIR CPD and CPDR are repeating compare instructions These instructions are not very useful because the scan stops when equal compare is detected Unequal compare would be more useful They are difficult to simulate efficiently so it is suggested that code using these instructions be rewritten which in most cases should be quite easy The following op codes are dropped RST 0 RST 8 RST 0x30 The remaining RST instructions are kept but the interrupt vector is relocated to a variable location the base of which is established by the IIR register RST can be simulated by a call instruction but this is not done automatically by the assembler since most of these instruc tions are used for debugging by Dynamic C The following instruction has had its op code changed
147. PDDDR setting it to a wrong value 18 3 3 Write only Registers Without Shadow Registers Shadow register are not needed for many of the registers that can be written to In some cases writing to registers is used as a handy way of changing a peripheral s state and the data bits written are ignored For example a write to the status register in the Rabbit serial ports is used to clear the transmitter interrupt request but the data bits are ignored and the status register is actually a read only register except for the special functionality attached to the act of writing the register An illustration of a write only register for which a shadow is unnecessary is the transmitter data register in the Rabbit serial port The transmitter data register is a write only register but there is little reason to have a shadow register since any data bits stored are transmitted promptly on the serial port 18 4 Timer and Clock Usage The battery backable real time clock is a 48 bit counter that counts at 32768 counts per second The counting frequency comes from the 32 768 kHz oscillator which is separate from the main oscillator Two other important devices are also powered from the 32 768 kHz oscillator the periodic interrupt and the watchdog timer It is assumed that all mea surements of time will derive from the real time clock and not the main processor clock which operates at a much higher frequency e g 22 1184 MHz This allows the main pro cesso
148. PU of all revisions of the Rabbit 3000 microprocessor is the same Rabbit 3000 revi sions are differentiated by the value in the GREV register Table B 5 summarizes the processor identification information for the different Rabbit 3000 versions Table B 5 Rabbit 3000 Revision Identification Information Package GCPU GREV Processor Revision Identifier 4 0 4 0 Rabbit 3000 ILIT IZIT 00001 00000 Rabbit 3000A IL2T 172 00001 00001 284 Rabbit 3000 Microprocessor User s Manual B 1 4 System User Mode By default all of the hardware is accessible by the programmer However if a control bit in the Enable Dual Mode Register EDMR is set to one two operating modes System and User become available The System mode is just like the normal operating mode but the User mode restricts program access to the hardware and to the System mode Individ ual peripherals may be enabled for User mode access in the User Enable registers listed below When enabled for User mode access a peripheral interrupt if it is capable of gen erating an interrupt can only be requested at interrupt priority level 2 or 1 and it is assumed that the interrupt service routine will be executed by User mode code Note that the processor automatically enters the System mode when entering the ISR area in response to an interrupt and the User mode must be specifically entered before continuing with the interrupt service routine
149. PWM output seven out of eight iterations of PWM counter 10 Suppress PWM output three out of four iterations of PWM counter 11 Suppress PWM output one out of two iterations of PWM counter 3 1 These bits are ignored and should be written with zero 0 PWM output High for single block Spread PWM output throughout the cycle Appendix B Rabbit 3000 Revisions 315 B 1 14 Quadrature Decoder Improvements The Quadrature Decoder counters can now be expanded to 10 bits instead of 8 bits This is controlled by bit 5 in QDCR listed in Table B 28 The additional two bits can be read in the QDCxHR registers listed in Table B 29 Reading the lower 8 bits of the Quadrature Decoder latches the upper 2 bits which can then be read at any time afterwards The latch is cleared when the upper 2 bits are read and subsequent reads of these upper two bits will return the current counter value until they are latched again by another read of the lower 8 bits NOTE Bit 5 of QDCR was always written with a zero in the original Rabbit 3000 chip Table B 28 Quadrature Decoder Control Register Quadrature Decoder Control Register QDCR Address 0x0091 Bit s Value Description 7 6 00 Disable Quadrature Decoder 2 inputs Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement 01 This bit combination is reserved and should not be used 10 Quadrature Decod
150. Pulse Width Modulator interrupts are disabled 01 Pulse Width Modulator interrupts use Interrupt Priority 1 10 Pulse Width Modulator interrupts use Interrupt Priority 2 11 Pulse Width Modulator interrupts use Interrupt Priority 3 0 PWM output High for single block 1 Spread PWM output throughout the cycle Table B 26 PWM LSB 1 Register PWMLSB 1 Register PWL1R Address 0x008A Bit s Value Description 7 6 write The least significant two bits for the Pulse Width Modulator count are stored 5 4 00 Normal PWM operation 01 Suppress PWM output seven out of eight iterations of PWM counter 10 Suppress PWM output three out of four iterations of PWM counter 11 Suppress PWM output one out of two iterations of PWM counter 3 This bit is ignored and should be written with zero 2 1 00 Normal PWM interrupt operation 01 Suppress PWM interrupts seven out of eight iterations of PWM counter 10 Suppress PWM interrupts three out of four iterations of PWM counter 11 Suppress PWM interrupts one out of two iterations of PWM counter 0 PWM output High for single block i 1 Spread PWM output throughout the cycle 314 Rabbit 3000 Microprocessor User s Manual Table B 27 PWM LSB 2 and 3 Registers PWM LSB x Register PWL2R Address 0x008C PWL3R Address 0x008E Bit s Value Description 7 6 write The least significant two bits for the Pulse Width Modulator count are stored 5 4 00 Normal PWM operation 01 Suppress
151. QDCIHR 0x0095 Quad Decode Count 2 High Register QDC2HR 0x0097 280 Rabbit 3000 Microprocessor User s Manual Table B 3 Reset State of I O Registers Modified Rabbit 3000A I O Rabbit Rabbit Register Name Mnemonic Address R W 3000 3000A Reset Reset Global Power Save Control Register GPSCR OxOOOD W 0000x000 00000000 Global Revision Register GREV 0x002F R 0 00000 0 00001 MMU Expanded Code Register MECR 0x0018 R W xxxxx000 00000000 Memory Timing Control Register MTCR 0x0019 W xxxx0000 00000000 Breakpoint Debug Control Register BDCR 0 001 W Oxxxxxxx 00000000 Bank 0 Control Register IBOCR 0x0080 W 000000xx 00000000 Bank 1 Control Register IBICR 0x0081 W 000000xx 00000000 Bank 2 Control Register IB2CR 0x0082 W 000000xx 00000000 Bank 3 Control Register IB3CR 0x0083 W 000000xx 00000000 Bank 4 Control Register IB4CR 0x0084 W 000000xx 00000000 Bank 5 Control Register 5 0 0085 W 000000xx 00000000 Bank 6 Control Register IB6CR 0x0086 W 000000xx 00000000 Bank 7 Control Register IB7CR 0x0087 W 000000xx 00000000 PWM LSB 0 Register PWL0R 0x0088 W 00 PWM LSB 1 Register PWLIR 0 008 W xxxxx00x PWM LSB 2 Register PWL2R 0x008C W
152. Register IB3CR 0x83 000000 Bank 4 Control Register IBACR 0 84 000000 Bank 5 Control Register 5 0 85 w 000000xx Bank 6 Control Register IB6CR 0x86 w 000000xx Bank 7 Control Register IB7CR 0 87 000000 PWM LSB 0 Register PWL0R 0x88 W XXXXXXXX Chapter 6 2 Rabbit Internal I O Registers 75 Table 6 2 Rabbit Internal I O Registers continued Register Name Mnemonic I O Address R W Reset PWM MSB 0 Register PWMOR 0 89 1 5 1 Register PWLIR Ox8A w XXXXXXXX PWM MSB 1 Register PWMIR Ox8B PWM LSB 2 Register PWL2R Ox8C MSB 2 Register PWM2R 0 8 PWM LSB 3 Register PWL3R Ox8E MSB 3 Register PWM3R Ox8F Quad Decode Ctrl Status Register QDCSR 0x90 R W XXXXXXXX Quad Decode Control Register QDCR 0x91 w 00xx0000 Quad Decode Count 1 Register QDCIR 0x94 R XXXXXXXX Quad Decode Count 2 Register QDC2R 0x96 R XXXXXXXX Interrupt 0 Control Register IOCR 0x98 000000 Interrupt 1 Control Register 0 99 w xx000000 Real Time Clock Control Register RTCCR 0 01 00000000 Real Time Clock Byte 0 Register RTCOR 0x02 R W XXXXXXXX Real Time Clock Byte 1 Register RTCIR 0x03 R XXXXXXXX Real Time Clock Byte 2 Register RTC2R 0x04 R XX
153. Register Name Mnemonic 10 address R W Reset Port G Data Register PGDR 0x48 R W XXXXXXXX Port G Control Register PGCR 0 4 00 00 Port G Function Register PGFR 0x4D w XXXXXXXX Port G Drive Control Register PGDCR Ox4E Port G Data Direction Register PGDDR Ox4F w 00000000 Table 9 17 Parallel Port G Data Register Functions Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PODR RW PG7 PG6 PG5 PG4 PG3 PG2 PG1 PGO adr 0x048 POER OY X SOUT_E RCLK E TCLK_E x SOUT RCLK TCLK_F adr 0x04D PGDCR W out out out out out out out out adr 0 04 open open open open open open open open drain drain drain drain drain drain drain drain PGDDR W dir dir dir dir dir dir dir dir adr 0x04F out out out out out out out out Chapter 9 Parallel Ports 143 Table 9 18 Parallel Port G Control Register adr 0x04C Bits 7 6 Bits 5 4 Bits 3 2 Bits 1 0 00 clock upper nibble on pclk 2 00 clock lower nibble on pclk 2 01 clock on timer A1 01 clock on timer A1 sn 10 clock on timer B1 PS 10 clock on timer B1 11 clock on timer B2 11 clock on timer B2 The following registers are described in Table 9 17 and in Table 9 18 PGDR Port G data register Reads value at pins Writes to port G preload register PGCR Parallel Port G control register This register is used to control the clocking of the upper and lower nibble of the final output register of
154. Register PAUER 0x0330 W 00000000 Parallel Port B User Enable Register PBUER 0x0340 W 00000000 Parallel Port C User Enable Register PCUER 0x0350 W 00000000 Parallel Port D User Enable Register PDUER 0x0360 W 00000000 Parallel Port E User Enable Register PEUER 0x0370 W 00000000 Parallel Port F User Enable Register PFUER 0x0338 W 00000000 Parallel Port G User Enable Register PGUER 0x0348 W 00000000 Input Capture User Enable Register ICUER 0x0358 W 00000000 Bank User Enable Register IBUER 0x0380 W 00000000 PWM User Enable Register PWUER 0x0388 W 00000000 Quad Decode User Enable Register QDUER 0x0390 W 00000000 Appendix B Rabbit 3000 Revisions 279 Table B 2 Reset State of New Rabbit 3000A I O Registers continued Register Name Mnemonic A R W Reset External Interrupt User Enable Register IUER 0x0398 W 00000000 Timer A User Enable Register TAUER 0x03A0 W 00000000 Timer B User Enable Register TBUER 0x03B0 W 00000000 Serial Port A User Enable Register SAUER 0x03C0 W 00000000 Serial Port B User Enable Register SBUER 0x03DO W 00000000 Serial Port C User Enable Register SCUER 0 03 W 00000000 Serial Port D User Enable Register SDUER 0x03F0 W 00000000 Serial Port E User Enable Register SEUER 0 03 8 W 00000000 Serial Port F User Enable Register SFUER 0x03D8 W 00000000 Enable Dual Mode Register EDMR 0x0420 W 00000000 Quad Decode Count High Register
155. Rr g 130 92 Parallel Port Bs sa eut te KT erdt 131 9 3 Parallel Post C Reta i NG ae S i s n uhu T ette 132 9 4 Parallel Port Disk oett e e Hen icd ete plene e 133 9 5 Parallel Port E uso NORRIS aee a ig 137 9 6 Parallel Port E iii sisien 140 9 6 1 Using Parallel Port A and Parallel 141 9 7 ParallelPortG 2 4 seats pra a RE 143 Chapter 10 I O Bank Control Registers 145 Chapter 11 Timers 149 Ibid ETE D ae 150 11 1 1 Timer A Registers emere unuhina aasan a 151 11 1 2 Practical Use of saa etit p ee bm qe derer 155 IE2 Timer B 3 denne En tetuer tet ores 156 1122 T Using Timer B Dec ES EU D Hose EHE 159 Chapter 12 Rabbit Serial Ports 161 12 1 Serial Port Register Layout e eres eet ET Pe OE POETE E ret EEES 164 12 2 Serial Port Registers an EE ec a i I e ER dert 166 12 3 Serial Port Interrupt erento epe setta ta 179 12 4 Transmit Serial Data Timing naa es apaspa EE te HE hu EE Tee 180 12 5 Receive Serial Data Timing noe era i tette Utd epe tere np e e 181 12 6 Clocked Serial Ports estero t Mes certe iti rea ir sb trenes eie est 182 12 7 Clocked Serial Timing 22 25 22 iii peut p Uere ette eterne ed 185 12 7 1 Clocked Serial Timing With Internal Clock esee 185
156. Shifts and Rotates RL RLA RLC RLCA RRC RRCA Instruction clk A ISZVC RL HL 10 f b L RL IX d 13 f b L RL IY d 13 f be RL r 4 fr L RLC HL 10 f b L RLC IX4d 13 f L RLC IY d 13 f b L RLC r 4 fr L RR HL 10 f b Lk RR IX d 13 f b L RR IY d 13 f b L RR r 4 fr L RRC HL 10 f be RRC IX d 13 f b L RRC IY d 13 f L RRC r 4 fr L SLA HL 10 f b L SLA IX d 13 f SLA IY d 13 f b L Operation A A A 0 A cy A a cy A A 6 0 A 7 CY A 7 a cy cy a A 0 AI 7 1 A 0 Operation cv HL H1 CY cv IX d cv I d I d cy cy r r cy HL HL 6 0 HL 71 CY HL 7 IX d 1X d 6 0 rX d 71 IX d 7 rY d 6 0 rY d 71 riv d 7 r r 6 0 r 7 CY rI71 HL CY cv HL IX d cy CY IX d IY d CY r cx cy r HL HL 0 HL 7 11 CY HL 0 IX d IX d 0 IX d 7 11 CY 0 IY d 0 IY d 7 1 CY IY d 0 r 0 r 7 1 CY r 0 HL
157. Solder fillet min max toe heel and side respectively L Toe to toe distance across chip S Heel to heel distance across chip T Toe to heel distance on pin W Width of pin Figure 5 3 PC Board Land Pattern for Rabbit 3000 128 pin LQFP 58 Rabbit 3000 Microprocessor User s Manual 5 2 Ball Grid Array Package 5 2 1 Pinout Rabbit 3000 56 55 171 IZ2T 128 pin Thin Map Ball Grid Array TFBGA 10 x 10 Body 0 8 mm pitch x o hae N e e LLI O O O Oz Oz Ox O O 2 Os gt x o x u lt 8 Q2 O O QE Ox O O O8 x lt amp 2 2 gt gt lu ac On OF OF OF OF Of Os O27 OF 0905 08 a a a lt a lt i a a gt gt gt gt 2 OZ O8 Os OF O8 O2 Os O8 08 Oz Os Os Of Oz OF Oz O OF OF OF OF e Oe O lt x Oz Og O Oz a x x gt N md ome O OF Of O n A Q gt m m a a Dn Dn n n N Qe Qe Of Os n n Dn n O O O O gt n n n E 5 O8 O8 O8 8 08 O Og _ 2 lu m o a a E o o u gt gt a z a z Of O O8 Os Os Os OF O O O OF Ot Ot O OF Os OF O O O O8 O Of Os OF O O LLI a o 22 oc e a a gt OF Oe OF 5 n o p a A T T s O8 O Og O Os O Os O
158. Status Register SPSR adr 0x023 Chapter 13 Rabbit Slave Port Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 set by 1 setby 1 setby 1 setby 1 setby 1 setby 1 setby 1 set by master master master master slave write slave write slave write slave write to write to write to write to to SPDOR toSPD2R to SPDIR write to SPDOR SPD2R SPDIR SPDOR Cleared by Cleared Cleared SPDOR Cleared by Cleared Cleared Cleared master when when Cleared slave write when slave when slave when slave write to master master when to SPSR reads reads reads SPSR reads reads master SPD2R SPDIR SPDOR SPD2R SPDIR reads register register register register register SPDOR register 207 13 3 Applications and Communications Protocols for Slaves The communications protocol used with the slave port depends on the application A slave processor may be used for various reasons Some possible applications are listed below Keep in mind that the Rabbit can also be operated as a slave processor via a serial port and some of the protocols will work well via a serial communications connection If a serial connection is used the protocol becomes more complicated if errors in transmission need to be taken into account If the physical link can be controlled so that transmission errors do not occur a realistic possibility if the interconnection environment is controlled the serial protoco
159. Stop Register SCLR 0x00E2 Serial Port C Status Register SCSR 0x00E3 R 0xx00000 Serial Port C Control Register SCCR 0 00 4 000000 Serial Port C Extended Register SCER 0x00E5 w 00000000 Serial Port D Data Register SDDR 0x00F0 R W XXXXXXXX Serial Port D Address Register SDAR 0x00F1 Serial Port D Long Stop Register SDLR 0x00F2 w XXXXXXXX Serial Port D Status Register SDSR 0x00F3 R 0xx00000 Serial Port D Control Register SDCR 0x00F4 000000 Serial Port D Extended Register SDER 0x00F5 00000000 Serial Port E Data Register SEDR 0 00 8 R W XXXXXXXX Serial Port E Address Register SEAR 0x00C9 Serial Port E Long Stop Register SELR 0x00CA Serial Port E Status Register SESR 0x00CB R 0xx00000 Serial Port E Control Register SECR 0x00CC w xx000000 Serial Port E Extended Register SEER 0x00CD 00000000 Serial Port F Data Register SFDR 0x00D8 R W XXXXXXXX Serial Port F Address Register SFAR 0x00D9 Serial Port F Long Stop Register SFLR 0x00DA w XXXXXXXX Serial Port F Status Register SFSR 0x00DB R 0xx00000 Serial Port F Control Register SFCR 0x00DC w xx000000 Serial Port F Extended Register SFER 0x00DD 00000000 Appendix D Rabbit 3000A Internal I O Registers 335 336 Rabbit 3000 Microprocessor User s Manual INDEX Numerics D G 5 V tolerant inputs 11 design features 9 generating p
160. The Stop condition is either edge of the ending input 108 Rabbit 3000 Microprocessor User s Manual Table 7 22 Input Capture Source x Register Input Capture Source x Register ICS1R Address 0x59 ICS2R Address 0x5D Bit s Value Description 7 6 00 Parallel Port C used for Start condition input 01 Parallel Port D used for Start condition input 10 Parallel Port F used for Start condition input 11 Parallel Port G used for Start condition input 5 4 00 Use port bit 1 for Start condition input 01 Use port bit 3 for Start condition input 10 Use port bit 5 for Start condition input 11 Use port bit 7 for Start condition input 3 2 00 Parallel Port C used for Stop condition input 01 Parallel Port D used for Stop condition input 10 Parallel Port F used for Stop condition input 11 Parallel Port G used for Stop condition input 1 0 00 Use port bit 1 for Stop condition input 01 Use port bit 3 for Stop condition input 10 Use port bit 5 for Stop condition input 11 Use port bit 7 for Stop condition input Table 7 23 Input Capture LSB x Register Input Capture LSB x Register ICL1R Address 0x5A ICL2R Address 0x5E Bit s Value Description The least significant eight bits of the latched Input Capture count are returned 7 0 read Reading the Isb of the count latches the msb of the count to avoid reading stale data Reading the msb of the
161. The System User mode is discussed in great detail in Appendix C Appendix B Rabbit 3000 Revisions 285 B 1 5 Memory Protection The ability to inhibit writes to physical memory was added The sixteen 64 KB physical memory blocks can be individually protected and two of those blocks can additionally be subdivided and protected at a granularity of 4 KB When a write is attempted a new Priority 3 write protection interrupt request is generated The write protection can be enabled for the User mode only or for all modes see Appendix C for more information WPHR 0x85 WPSAR 0x04 WPLR 0x6C WPSAHR 0x07 OxFFFFF WPSALR 0xCC 4 0x48000 0x00000 0x40000 Figure B 1 Sample Memory Protection Layout The new memory protection registers are listed in Table B 6 through Table B 11 Table B 6 Write Protect Control Register Write Protect Control Register WPCR Address 0x0440 Bit s Value Description 7 1 These bits are reserved and should be written with zeros write protection in User mode only write protection in System and User modes 286 Rabbit 3000 Microprocessor User s Manual Table B 7 Write Protect Low Register Write Protect Low Register WPLR Address 0x0460 Bit s Value Description 0 Disable 64K write protect for physical
162. User mode was added This mode provides a framework for separating application code from system critical code which helps prevent application code from crashing the entire device System User mode is described in detail in Appendix C b The ability to write protect 64 KB physical memory blocks was added with the option of further protecting two of the 64 KB blocks in 4 KB segments Attempts to write to a protected block triggers a Priority 3 write protection interrupt c Stack protection was added Writing outside set stack boundaries triggers a Priority 3 stack violation interrupt d RAM segment relocation was added This feature allows a 1 2 or 4 KB segment of the logical memory space to be mapped as data or for program execution when separate I D space is enabled e Secondary watchdog timer added The secondary watchdog timer was added to function as a safety net for the periodic interrupt f Two new opcodes were added to support multiply and add and multiply and subtract operations on large unsigned integers These operations can be used to speed up public key calculations g Six new opcodes were added to support block copy operations from I O addresses to memory addresses and vice versa h The I O address space has been expanded to 16 bits to make room for new peripherals i Two new features were added to further expand the external I O interface capabilities of the processor First an option was added to ena
163. XXXXXX Real Time Clock Byte 3 Register RTC3R 0x05 R XXXXXXXX Real Time Clock Byte 4 Register RTC4R 0x06 R XXXXXXXX Real Time Clock Byte 5 Register RTCSR 0x07 R XXXXXXXX Timer A Control Status Register TACSR 0 R W 00000000 Timer A Prescale Register TAPR OxA1 w XXXXXXX Timer A Time Constant 1 Register TATIR 0 Timer A Control Register TACR OxA4 00000000 Timer A Time Constant 2 Register TAT2R 5 Timer A Time Constant 8 Register TAT8R 0xA6 Timer A Time Constant 3 Register TAT3R OxA7 Timer A Time Constant 9 Register TAT9R OxA8 w XXXXXXXX Timer A Time Constant 4 Register TAT4R 0 9 Timer A Time Constant 10 Register TATIOR OxAA w XXXXXXXX 76 Rabbit 3000 Microprocessor User s Manual Table 6 2 Rabbit Internal I O Registers continued Register Name Mnemonic I O Address R W Reset Timer A Time Constant 5 Register TATSR OxAB w XXXXXXXX Timer A Time Constant 6 Register TAT6R OxAD W XXXXXXXX Timer A Time Constant 7 Register TAT7R OxAF W XXXXXXXX Timer B Control Status Register TBCSR OxBO R W XXxxx000 Timer B Control Register TBCR OxB1 W xxxx0000 Timer B MSB 1 Register TBMIR 0xB2 Timer B LSB 1 Register TBLIR 0xB3 w XXXXXXXX Timer B MSB 2 Register TBM2R 0xB4 w XXXXXXXX Timer B LSB 2 Regi
164. able transmit buffer empty or transmit idle conditions can be programmed to generate an interrupt The HDLC mode allows full duplex synchronous communication Either an internal or external clock may be selected for both the receiver and the transmitter HDLC mode encapsulates data within opening and closing Flags and sixteen bits of CRC precedes the closing Flag All information between the opening and closing Flag is zero stuffed That is if five consecutive ones occur independent of byte boundaries a zero is automatically inserted by the transmitter and automatically deleted by the receiver This allows a Flag byte 0x07E to be unique within the serial bit stream The standard CRC CCITT polyno 12 mial x x 4 x 1 is implemented with the generator and checker preset to all ones Both receive and transmit operation are essentially automatic In the receiver each byte is marked with status to indicate end of frame short frame and CRC error The receiver automatically synchronizes on Flag bytes and presets the CRC checker appropriately If Chapter 12 Rabbit Serial Ports 187 the current receive frame is not needed because it is addressed to a different station for example a Flag Search command is available This command forces the receiver to ignore the incoming data stream until another Flag is received In the transmitter the CRC gener ator is preset and the opening Flag is transmitted automatically after the first
165. ad The processor keeps a one byte stack called the SU register that is analogous to the IP register that keeps track of the interrupt priority Every time SETUSR is executed to enter the User mode or an interrupt occurs or SYSCALL or RST is executed to enter the Sys tem mode the current mode is pushed onto the SU register When a SURES is executed the previous mode is popped off the SU register The effects of each opcode are The SETUSR opcode puts the processor into the User mode by pushing the correct value into the SU register PUSH SU and POP SU push and the single byte SU register on off the SP stack SURES pops the current processor mode off the SU register returning it to the previous mode IDET causes an interrupt if executed in the User mode and does nothing in the System mode RDMODE returns the current mode in the carry flag 0 for System mode 1 for User mode SYSCALL is essentially a new RST opcode and was added to allow User mode access to the System mode without using one of the existing RST opcodes It will put the processor into the System mode and execute code in the corresponding interrupt vector table entry Table C 2 New System User Mode Opcodes Instruction Bytes clk A 5 Z V C Operation d SETUSR 2 4 1 1 SUz SU 5 0 0x01 Yes PUSH SU 2 9 1 1 1 50 SPZSP 1 Yes POP SU 2 7 1 1 1 1 150 1 5 5 5 1 Yes SURES
166. agement 243 GPSCR ane 88 299 memory timing 123 power usage standby mode 212 GRAM configuration 79 memory mapping unit 117 programming cable 271 GREV ens 80 284 ModDUS nie 196 programming port 271 configuration 79 RESET line 272 GSCR Basen 300 0 alternate programming port bank control 145 295 NE eene 272 IBxCR 146 152 154 157 298 revision blockefiesisoso 296 pin assignments 271 ieu 105 108 System User mode 320 programming cable 271 ICCSR 105 107 open drain outputs 51 SMODE pins aaa 271 ICLEXR eg 105 109 audere we 211 STATUS 271 ICMxR 105 109 man GA hes 211 use as diagnostic port 272 ICSXR einn 105 109 seillators PWM modulator 103 313 ICTxR eene 105 108 32 768 kHz 80 81 211 PWM outputs 17 50 index registers quee 22 main clock 80 211 Q minal VO output pins interrupt priority register 22 alternate assignment 90 quadrature decoder 110 TID 1 quadrature encoder inputs 17 MBOER iii 321 MBXCR ms 120 MEGR n ERR 123 memory bank control 120 338 Rabbit 3000 Microprocessor User
167. al IrDA Watchdog Serial Ports Timer E F Asynch HDLC Serial SDLC ADDRESS BUS XTALA1 XTALA2 Timer B CLK32K 32 768 kHz Clock Input Real Time Clock Periodic Asynch Serial IrDA 1 52 ICS1 CSO IOE1 OEO IWE1 WEO TXB RXB CLKB ATXB ARXB TXC RXC CLKC TXD RXD CLKD 1 1 1 1 1 RXE 1 TCLKE RCLKE 1 gt RXF TCLKF RCLKF HDLC SDLC IrDA Pulse Width Modulation Interrupt ID 7 0 IA 5 0 I 7 0 External I O Chip Interface External Interrupts INTOA INT1A INTOB INT1B Slave Port Slave Interface Bootstrap Interface Figure 1 1 Rabbit 3000 Block Diagram Quadrature Decoder Input Capture 1 PWN 3 0 QD1A QD1B QD2A QD2B AQD1A AQD1B AQD2A AQD2B PC 7 5 3 1 PD 7 5 3 1 PF 7 5 3 1 7 5 3 1 SD 7 0 SA 1 0 ISCS ISRD ISWR ISLAVEATTN Chapter 1 Introduction 1 2 Summary of Rabbit 3000 Advantages The glueless architecture makes it is easy to design the hardware system There are a lot of serial ports and they can communicate very fast Precision pulse and edge generation is a standard feature EMI is at extremely low levels Interrupts can have multiple priorities Processor speed and power consumption are under program control The ultra low power mode can perform computations and execute logical tests since the processor continues to execute albeit at 32 kHz or even as slow as 2 kHz The Rabbit may b
168. an call other code in the root using short Jumps and calls Code in the XPC segment can also call code in the root using short jumps and calls However a long call must be used when code in the XPC segment is called Functions located in the root have an efficiency advantage because a long call and a long return require 32 clocks to execute but a short call and a short return require only 20 clocks to execute The differ ence is small but significant for short subroutines Compiler notices that code has Compiler inserts passed F000 long jump in code XPC Segment Stack Segment short calls returns Data Segment E000 XPC N 1 PC F000 K PC E000 K 4 Root Segment Illustration of Sliding XPC Window Figure 3 5 Use of XPC Segment 3 2 2 Separate l and D Space Extending Data Memory In the normal memory model the data space must share a 64K space with root code the stack and the XPC window Typically this leaves a potential data space of 40K or less The XPC requires 8K the stack requires 4K and most systems will require at least 12K of root code This amount of data space is sufficient for many embedded applications One approach to getting more data space is to place data in RAM or in flash memory that is not mapped into the 64K space and then access this data using function calls or in assembly language using the LDP instructions
169. ansmitted by disabling the driver after the stop bit has been sent This is an alternative to the above procedure 12 9 3 Transmitting and Detecting a Break A break is created when the output of the transmitter is driven low for an extended period If a break is received it will appear as a series of characters filled with zeros and with the 9th bit detected low This could only be confused with a legitimate message if a protocol using the 9th bit was in effect Break is not usually used as a message in such protocols A break can be transmitted by transmitting a byte of zeros at a very slow baud rate Another and probably better method is to disconnect the transmitter from the output pin and use the parallel port bit to set the line low while sending dummy characters to time out the break The use of break as a signaling device should be avoided because it is slow erratically sup ported by different types of hardware and usually creates more problems than it solves 12 9 4 Using A Serial Port to Generate a Periodic Interrupt A serial port may be used to generate a periodic interrupt by continuously transmitting characters Since the Tx output via Parallel Port C or D can be disabled the transmitted characters are transmitted to nowhere Because the character output path is double buff ered there will be no gaps in the character transmission and the interrupts will be exactly periodic The interrupts can happen every 9 10 or 11 baud tim
170. ansmitting 0x0D6 1 Start Bit Stop Bit A st d Transmitting 0x0D6 Tx with 9th bit zero A 7 Start Bit 9th bit Stop Bit Signals Shown at Microprocessor Tx Pin Figure 12 2 Functional Block Diagram of a Serial Port 164 Rabbit 3000 Microprocessor User s Manual The clock input to the serial port unit must be 8 or 16 selectable times the baud rate in the asynchronous mode and 2 times the baud rate for the clocked serial mode when the internal clock is used Timers A2 A7 supply the input clock for Serial Ports A F These timers can divide the frequency by any number from 1 to 256 see Chapter 11 The input frequency to the timers can be selected in different ways described in the documentation for the timers One choice is the peripheral clock with that choice and a well chosen crystal frequency for the main oscillator the most commonly used baud rates can be obtained down to approximately 2400 bps or lower by prescaling timer AO at the highest Rabbit clock fre quencies see Section A 3 in Appendix A Chapter 12 Rabbit Serial Ports 165 12 2 Serial Port Registers Each serial port has 6 registers shown in the tables below The status control and extended registers may have somewhat different formats for different serial ports Table 12 2 Serial Port A Registers
171. ants thus mapping the RAM chip to addresses 0x80000 to OXOFFFFF Chapter 8 Memory Interface and Mapping 119 8 5 Memory Bank Control Registers Table 8 3 describes the operation of the four memory bank control registers The registers are write only Each register controls one quadrant in the 1M address space Table 8 3 Memory Bank Control Register x MBxCR 0x014 x Memory Bank x Control Register MB0CR Address 0x014 MB1CR Address 0x015 MB2CR Address 0x016 MB3CR Address 0x017 Bit s Value Description 00 Four wait states for accesses in this bank 01 Two walt states for accesses in this bank a 10 One wait states for accesses in this bank 11 Zero wait states for accesses in this bank 0 Pass A 19 for accesses in this bank d 1 Invert A 19 for accesses in this bank 0 Pass A 18 for accesses in this bank t 1 Invert A 18 for accesses in this bank 00 OE0 and WEO are active for accesses in this bank 01 are active for accesses in this bank 3 2 10 JOEO only is active for accesses in this bank i e read only Transactions are normal in every other way OE1 only is active for accesses in this bank i e read only Transactions are normal in every other way 00 CSO is active for accesses in this bank 1 0 01 CS1 is active for accesses in this bank 1x CS2 is active for accesses in this bank Bits 7 6 The number
172. anual 9 2 Parallel Port B Parallel Port B has eight pins that can programmed individually to be inputs and outputs After reset Parallel Port B comes up as six inputs PB 5 0 and two outputs PB7 and PB6 The output value on pins PB6 and PB7 package pins 99 100 will be low Table 9 3 Parallel Port B Registers Register Name Mnemonic 10 address R W Reset Port B Data Register PBDR 0x40 R W 00 Port B Data Direction Register PBDDR 0x47 11000000 Table 9 4 Parallel Port B Register Bit Functions Bit7 BitG Bits Bit2 Bit 0 PBDR R W PB7 PB6 PB5 PB4 PB3 PB2 PBI PBO adr 0x040 T dips des ji diez dir ire jir dip adr 2 0x047 out out out out out out out out When the auxiliary I O bus is enabled Parallel Port B bits 2 7 provide 6 address lines the least significant 6 lines of the 16 lines that define the full I O space When the slave port is enabled parallel port lines PB2 PB7 are assigned to various slave port functions However it is still possible to read 5 using the Port B data register even when lines PB2 PB7 are used for the slave port It is also possible to read the signal driving PB6 and PB7 this signal is on the signaling lines from the slave port logic Regardless of whether the slave port is enabled PBO reflects the input of the pin unless Serial Port B has its internal clock enabled wh
173. arallel Port A is enabled Refer to Section 9 6 1 Using Parallel Port A and Parallel Port F for more information Chapter 9 Parallel Ports 129 9 1 Parallel Port A Parallel Port A has a single read write register Table 9 1 Parallel Port A Registers Register Name Mnemonic I O address R W Reset Port A Data Register PADR 0x30 R W XXXXXXXX Slave Port Control Register SPCR 0x24 R W 0xx00000 Table 9 2 Parallel Port A Data Register Bit Functions Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PADR R W PA7 PA6 PAS PA4 PA3 PA2 PAO adr 0x030 This register should not be used if the slave port or auxiliary I O bus is enabled The slave port control register is used to control whether Parallel Port A is configured as slave databus auxiliary I O data bus parallel Input or parallel output To make the port an input store 0x080 in the SPCR slave port control register To make the port an output store 0x084 in SPCR Parallel Port A is set up as an input port on reset When the port is read the value read reflects the voltages on the pins 1 for high and 0 for low This could be different than the value stored in the output register if the pin is forced to a different state by an external voltage NOTE Refer to Section 9 6 1 Using Parallel Port A and Parallel Port F for more information 130 Rabbit 3000 Microprocessor User s M
174. as a user defined serial port although this will not be nec essary in most cases Rabbit Semiconductor supports the use of the standard programming port and the standard programming cable as a diagnostic and setup port to diagnosis problems or set up systems in the field 2 3 2 Standard BIOS Rabbit Semiconductor provides a standard BIOS for the Rabbit The BIOS is a software program that manages startup and shutdown and provides basic services for software run ning on the Rabbit 2 4 Dynamic C Support for the Rabbit Dynamic C is Rabbit Semiconductor s interactive C language development system Dynamic C runs on a PC under Windows 32 bit operating systems Dynamic C provides a combined compiler editor and debugger The usual method for debugging a target system based on the Rabbit is to implement the 10 pin programming connector that connects to the PC serial port via a standard converter cable Dynamic C libraries contain highly per fected software to control the Rabbit These includes drivers utility and math routines and the debugging BIOS for Dynamic C In addition the internationally known real time operating system uC OS II has been ported to the Rabbit and is available with Dynamic C on a license free royalty free basis for use in Rabbit based products Chapter 2 Rabbit 3000 Design Features 19 20 Rabbit 3000 Microprocessor User s Manual 3 DETAILS ON RABBIT MICROPROCESSOR FEATURES 3 1 Processor Registe
175. at address Oxn OxFFFF you will get the bytes located at 0xn OxFFFF and 0 0000 instead of Oxn OxFFFFand Ox n 1 0x0000 as you might expect Therefore do not use LDP at any physical address ending in 19 6 Register to Register Moves Instruction IS V C Operation LD r g 2 r r g r g any of B C D H L A LD A EIR 4 fr A EIR LD A IIR 4 fr A IIR LD A XPC 4 r A MMU LD EIR A 4 EIR A LD IIR A 4 LD XPC A 4 XPC A LD HL IX 4 r HL IX LD HL IY 4 r HL LD IX HL 4 IX HL LD IY HL 4 IY HL LD SP HL 2 SP HL LD SP IX 4 SP IX LD SP IY 4 SP IY LD dd BC 4 dd BC dd 00 BC 01 DE 10 HL LD dd DE 4 dd DE dd 00 BC 01 DE 10 HL Chapter 19 Rabbit Instructions 253 19 7 Exchange Instructions Instruction clk A 152 2 5 15 r gt tax sa tee EX SP IX 15 o to ere EX SP IY 15 A gu EX AF AF 2 nin Z t EX DE HL 2 s EX DE HL 8 Se Soe EX DE HL 2 s gt DE HL s T EXX 2 ss T EX DE HL Operation H lt gt SP 1 L lt gt SP IXH lt gt SP 1 IXL lt gt SP IYH lt gt SP 1 IYL lt gt SP AF lt gt AF if ALTD then DE else DE lt gt HL DE lt gt HL if ALTD then DE lt gt HL e
176. at the middle of each data bit and are shifted into the receive shift register After 7 or 8 data bits have been received the next bit will be either a 9th 8th address bit or a stop bit will be sampled If the Rx line is low it is an address bit and the address bit received bit in the status register will be enabled If an address bit is detected the receiver will attempt to sample the stop bit If the line is high when sampled it is a stop bit and a new scan for a new start bit will begin after the sample point At the same time the data bits are transferred into the receive data register and an interrupt if enabled is requested On receive an interrupt is requested when the receiver data register has data This hap pens when data bits are transferred from the receive shift register to the data register This also sets bit 7 of the status register The interrupt request and bit 7 are cleared when the data register is read An interrupt is requested if bit 7 is high The interrupt is requested on the edge of the transmitter data register becoming empty or the transmitter shift register becoming empty The transmitter interrupt is cleared by writing to the status register or to the data register On receive the scan for the next start bit starts immediately after the stop bit is detected The stop bit is normally detected at a sample clock that nominally occurs in the center of the stop bit If there is a 9th 8th address bit the stop bit f
177. ata stream Since they are optional they will eventually not be present and the DPLL can attempt to lock onto the required transitions Since the DPLL can adjust by one count every bit cell the maximum difference between the sending data rate and DPLL output clock rate is 1 16 6 With Biphase data encoding the DPLL is designed to work in multiple access conditions where there may not be Flags on an idle line The DPLL will properly generate an output clock based on the first transition in the leading zero of an opening Flag Similarly only the completion of the closing Flag is necessary for the DPLL to provide the extra two clocks to the receiver to properly assemble the data In Biphase Level mode this means the transi tion that defines the last zero of the closing Flag In Biphase Mark and Biphase Space modes this means the transition that defines the end of the last zero of the closing Flag The figure below shows the adjustment ranges and output clock for the different modes of operation of the DPLL Each mode of operation will be described in turn Bit cell i x oe er 1 T i 1 1 l i J NRZI adj none add oni add two subtract two subtract one none I i i i Bi L adj
178. atically modify the request to occur at Level 2 Within a given interrupt priority level the interrupts are prioritized according to Table C 5 324 Rabbit 3000 Microprocessor User s Manual Table C 5 Interrupts Priority and Action to Clear Requests Priority Interrupt Source Action required to clear the interrupt Highest System Mode Violation Automatically cleared by the interrupt acknowledge Stack Limit Violation Automatically cleared by the interrupt acknowledge Write Protection Violation Automatically cleared by the interrupt acknowledge Secondary Watchdog Restart the Secondary Watchdog by writing to WDTCR External 1 Automatically cleared by the interrupt acknowledge External 0 Automatically cleared by the interrupt acknowledge Periodic 2 kHz Read the status from the GCSR Quadrature Decoder Read the status from the QDSR Timer B Read the status from the TBSR Timer A Read the status from the TASR Input Capture Read the status from the ICCSR PWM Write any PWM register Rd Read the data from the SPDOR SPD1R or SPD2R Slave Port Wr Write data to the SPDOR SPDIR SPD2R or write a dummy byte to the SPSR Rx Read the data from the SEDR or SEAR Serial Port E Tx Write data to the SEDR SEAR SELR or write a dummy byte to the SESR Rx Read the data from the SFDR or SFAR Serial Port F Tx Write data to the SFDR SFAR SFLR or write a dummy byte to the SFSR
179. ation sequences 96 Rabbit 3000 Microprocessor User s Manual 7 10 Rabbit Interrupt Structure An interrupt causes a call to be executed pushing the PC on the stack and starting to exe cute code at the interrupt vector address The interrupt vector addresses have a fixed lower byte value for all interrupts The upper byte is adjustable by setting the registers EIR and IIR for external and internal interrupts respectively There are only two external interrupts generated by transitions on certain pins in Parallel Port E The interrupt vectors are shown in Table 6 2 The interrupts differ from most Z80 or Z180 interrupts in that the 256 byte tables pointed to EIR and IIR contain the actual instructions beginning the interrupt routines rather than a 16 bit pointer to the routine The interrupt vectors are spaced 16 bytes apart so that the entire code will fit in the table for very small interrupt routines Interrupts have priority 1 2 or 3 The processor operates at priority 0 1 2 or 3 If an inter rupt is being requested and its priority is higher than the priority of the processor the interrupt will take place after then next instruction The interrupt automatically raises the processor s priority to its own priority The old processor priority is pushed into the 4 position stack of priorities contained in the IP register Multiple devices can be requesting interrupts at the same time In each case there is a latch set in th
180. bit 3000 Microprocessor User s Manual 7 12 Pulse Width Modulator PWM interrupt and suppression features were added starting with Rev A of the Rabbit 3000 microprocessor These are described in complete detail in Appendix B 1 13 The Pulse Width Modulator consists of a ten bit free running counter and four width reg isters Each PWM output is High for n 1 counts out of the 1024 clock count cycle where n is the value held in the width register The PWM output high time can optionally be spread throughout the cycle to reduce ripple on the externally filtered PWM output The PWM is clocked by the output of Timer A9 Register Name Mnemonic WO Address R W Reset PWM LSB 0 Register PWLOR 0x88 W XXXXXXXX PWM MSB 0 Register PWMOR 0x89 W XXXXXXXX PWM LSB 1 Register PWLIR Ox8A MSB 1 Register PWMIR 0x8B PWM LSB 2 Register PWL2R Ox8C MSB 2 Register PWM2R Ox8D w XXXXXXXX PWM LSB 3 Register PWL3R Ox8E w XXXXXXXX PWM MSB 3 Register PWM3R Ox8F w XXXXXXXX The spreading function is implemented by dividing each 1024 clock cycle into four quad rants of 256 clocks each Within each quadrant the Pulse Width Modulator uses the eight MSBs of each pulse width register to select the base width in each of the quadrants This is the equivalent to dividing the contents of the pulse width register by four and using this value in each q
181. bits for Serial Port B and bits 6 and 7 can be used as alternate bits for Serial Port A Alternate serial port bit assignments make it possible for the same serial port to connect to different communi cations lines that are not operating at the same time On reset the data direction register is zeroed making all pins inputs In addition certain bits in the control register are zeroed bits 0 1 4 5 to ensure that data is clocked into the output registers when loaded All other registers associated with port D are not initialized on reset Table 9 7 Parallel Port D Registers Register Name Mnemonic I O address R W Reset Port D Data Register PDDR 0x60 R W XXXXXXXX Port D Control Register PDCR 0x64 xx00xx00 Port D Function Register PDFR 0x65 w XXXXXXXX Port D Drive Control Register PDDCR 0x66 w XXXXXXXX Port D Data Direction Register PDDDR 0x67 w 00000000 Port D Bit 0 Register PDBOR 0x68 w XXXXXXXX Port D Bit 1 Register PDBIR 0x69 Port D 2 Register PDB2R 0 6 Port D 3 Register PDB3R 0x6B w XXXXXXXX Port D Bit 4 Register PDB4R 0x6C w XXXXXXXX Port D Bit 5 Register PDB5R 0x6D w XXXXXXXX Port D Bit 6 Register PDB6R 0x6E w XXXXXXXX Port D Bit 7 Register PDB7R Ox6F w XXXXXXXX Chapter 9 Parallel Ports 133 p gt 25 A ATXBI Inputs I O Data perclk 2
182. ble B 11 Write Protect Segment x High Register Write Protect Segment x High Register WPSAHR Address 0x0482 WPSBHR Address 0x0486 Bit s Value Description 0 Disable write protect for address offset OXF000 0xFFFF in WP Segment x 1 Enable write protect for address offset OxFOOO OxFFFF in WP Segment x 0 Disable write protect for address offset 0 000 in WP Segment x 1 Enable write protect for address offset 0 000 in WP Segment x 0 Disable write protect for address offset 0xDO00 OxDFFF in WP Segment x i 1 Enable write protect for address offset OxD000 OxDFFF in WP Segment x 0 Disable write protect for address offset 0 000 0 in WP Segment x i 1 Enable write protect for address offset 00 0 WP Segment x 0 Disable write protect for address offset 0xBOOO OxBFFF in WP Segment x 1 Enable write protect for address offset 0xB000 0xBFFF in WP Segment x 0 Disable write protect for address offset 000 0 in WP Segment x l 1 Enable write protect for address offset Ox A000 0xAFFF in WP Segment x 0 Disable write protect for address offset 0 9000 0 9 in WP Segment x 1 Enable write protect for address offset 0 9000 0 9 in WP Segment x 0 Disable 4Kwrite protect for address offset Ox8000 0x8FFF in WP Segment x 1 Enable write protect
183. ble or disable the auxiliary I O bus interface for a given I O bank If the auxiliary I O bus is dis abled for a given external I O bank the processor uses the memory bus for external I O transactions The second feature is the addition of an option for enabling hold time for external I O read operations The option shortens the read strobes by one clock cycle j The low power capability of the processor was further expanded with the addi tion of short chip select timing for all clock modes except for divide by one mode and for reads writes or both k The PWM outputs can now trigger a PWM interrupt each cycle or every other fourth eighth cycle In addition the PWM output can be suppressed every other cycle three out of every four cycles or seven out of every eight cycles These options were added to provide support for driving servos in addi tion to generating audio using the Rabbit 3000A 276 Rabbit 3000 Microprocessor User s Manual 1 The quadrature decoder hardware can be configured to use a 10 bit counter in place of the existing 8 bit counter option was added to alternatively multiplex PWM outputs slave chip select SCS and Serial Ports E and F transmit and receive clocks on other pins n The Schmitt trigger IC normally required for the low power 32 768 kHz oscil lator circuit is now integrated inside the Rabbit 3000A NOTE Based on this modification a new low power oscillator circuit is recom
184. byte is writ ten to the transmitter buffer and CRC and the closing flag are transmitted after the byte that is written to the buffer through the Address Register If no CRC is required writing the last byte of the frame to the Long Stop Register automatically appends a closing flag after the last byte If the transmitter underflows either an Abort or a Flag will be transmit ted under program control A command is available to send the Abort pattern seven con secutive ones if a transmit frame needs to be aborted prematurely The Abort command takes effect on the next byte boundary and causes the transmission of an OxFE a zero fol lowed by seven ones after which the transmitter will send the idle line condition The Abort command also purges the transmit FIFO The idle line condition may be either Flags or all ones Both the receiver and transmitter contain four bytes of buffering for the data Status bits are buffered along with the data in both receiver and transmitter The receiver automati cally generates an interrupt at the end of a received frame and the transmitter generates an interrupt at the end of CRC transmission at the end of the transmission of an Abort sequence and at the end of the transmission of a closing Flag The transmitter is not capable of sending an arbitrary number of bits but only a multiple of bytes However the receiver can receive frames of any bit length If the last byte in the frame is not eight bit
185. can arise if there are dual interrupts for each character transmitted One problem is that the message transmission rate will free run at a speed limited by the inter rupt latency and compute speed of each processor This could consume a high percentage of the compute resources of one or both processors starving other processes and espe cially interrupt routines for compute time If this is a problem then a timed interrupt can be used to drive the process on one side thus limiting the data transmission rate Another solution which may be better than limiting the transmission rate is to use inter rupts only for the first byte of the message on the slave side and then lower the interrupt priority and conduct the rest of the transaction as a polled transaction On the master side the entire transaction can be a polled transaction In this case the entire transaction takes place in the interrupt routine on the slave but other interrupts are not inhibited since the priority has been lowered A typical slave system consists of a Rabbit microprocessor and a RAM memory con nected to it The clock can be provided either by connecting a crystal or crystals to the slave or by providing an external clock which could be the master s clock The reset line of the slave would normally be driven by the master At system startup time the master resets the slave and cold boots it via the slave port The SMODE pins must be configured for this Once the sof
186. can be considered to start at any address and continue for 32K At least 4K of RAM is needed for the stack segment so if a 32K RAM is used a maximum of 28K would be available for storing data variables If more stack segments are needed the amount of data variable space would be corresponding reduced 126 Rabbit 3000 Microprocessor User s Manual 64k 4 n alloc xcode 912k 4 n 512k 52k 64k 52k xconsts 1024k e 512k alloc xdata vars Root Space alloc consts allocate vars Constant Variable D Space D Space 77 Flash memory available for 2 extended code constant data PAM memory Figure 8 6 Use of Physical Memory Separate I amp D Space Model In Figure 8 6 arrows indicate the direction in which variables and constants are allocated as the compile or assemble proceeds Each of these arrows starts at a constant location in physical memory This is important because the Dynamic C debugging monitor needs to keep a small number of constants and variable in data space and it needs to be able to access these regardless of the state of the user program The Dynamic C debugger vari ables are kept at the top of the data segment starting at 52k and working down in memory The user program variables are allocated by the compiler starting just below the Dynamic C debugger data The Dynamic C constants start at address zero User constants are allo cated stating at a low address just above the D
187. can be performed by a lower priority analysis routine Since the upper 2 bits are in the TBCMR register at address OxOBE and the lower 8 bits are in TBCLR at address OxOBF both registers can be read with a single 16 bit I O instruction The following sequence illustrates how the regis ters could be captured 7 enter from external interrupt on pulse input transition 19 clocks latency plus 10 clocks interrupt execution push af 7 push hl ioi ld a TBCLR 11 get lower 8 bits of counter ioi ld hl TBCMR 13 get l upper h lower Chapter 11 Timers 159 Timer B can be used for various purposes The 10 bit counter can be read to record the time at which an event takes place If the event creates an interrupt the timer can be read in the interrupt routine The known time of execution of the interrupt routine can be sub tracted The variable interrupt latency is then the uncertainty in the event time This can be as little 19 clocks if the interrupt is the highest priority interrupt If the system clock is 20 MHz the counter can count as fast as 10 MHz The uncertainty in a pulse width measure ment can be nearly as low as 38 clocks 2 x 19 or about 2 us for a 20 MHz system clock Timer B can be used to change a parallel port output register at a particular specified time in the future A pulse train with edges at arbitrary times can be generated with the restric tion that two adjacent edges cannot be too close to each other since an
188. cause of the required prefix byte Instructions such as 1 A d or LD d e are not allowed Several 16 bit register to register move instructions are available Except as noted these instructions all require 2 bytes and four clocks The instructions are listed below LD dd BC where dd is any of HL DE BC 2 bytes 4 clocks LD dd DE LD IX HL LD IY HL LD HL IY LD HL IX LD SP HL l bvte 2 clocks LD SP IX LD SP IY Other 16 bit register moves can be constructed bv using 2 bvte moves 3 3 5 Register Exchanges Exchange instructions are verv powerful because two or more moves are accomplished with one instruction The following register exchange instructions are implemented EX af af exchange af with af EXX exchange HL DE BC with HL DE BC EX DE HL exchange DE and HL The following instructions are unique to the Rabbit EX DE HL 1 byte 2 clocks EX DE HL 2 bytes 4 clocks EX DE HL 2 bytes 4 clocks The following special instructions Rabbit and Z180 Z80 exchange the 16 bit word on the top of the stack with the HL register These three instructions are each 2 bytes and 15 clocks EX SP HL EX SP IX EX SP IY Chapter 3 Details on Rabbit Microprocessor Features 35 3 3 6 Push and Pop Instructions There are instructions to push and pop the 16 bit registers AF HL DC BC IX and The registers DE and can be popped Popping the al
189. ccess to a peripheral and or interrupt from the System mode If allowed the System mode can create an interrupt vector as described in Section C 3 that will execute the user code interrupt handler When the application code wants to perform an action that is controlled by the System mode it can request the particular action by loading the appropriate value into HL and executing SYSCALL This requires generating a list of all the actions that the application code would want to do assigning values to each action and implementing a SYSCALL handler in the System mode that parses the value passed to it and calls the appropriate function Write protection should be enabled User mode only for all blocks containing system code and data as well as any critical memory regions If any critical interrupts occur stack limit violation system mode violation write protec tion violation the System mode handlers can perform any of a number of operations restart the application code signal another device halt operation and so on An overview of this level of operation is shown in Figure C 4 System Mode User Mode Return from interrupts Interrupt Application handlers code Flash file User defined system interrupts SYSCALL handler Interrupts SYSCALL RST Figure C 4 System User Mode Setup for Operating System 328 Rabbit 3000 Microprocessor User s Manual APPENDIX D RABBIT 3000A INTERNAL I O REGISTERS Table D 1 prov
190. ccurs if the addition would result in an address that does not fit in 20 bits Table 8 1 Segment Registers Segment Register Function XPC Locates extended code segment in physical memory Read and written by processor instructions 14 a xpc 1 lcall lret 1 STACKSEG 0x11 Locates stack segment in physical memory DATASEG 0x12 Locates data segment in physical memory Table 8 2 Segment Size Register Bits 7 4 Bits 3 0 SEGSIZE 0x13 Boundary address stack segment Boundary address data segment 118 Rabbit 3000 Microprocessor User s Manual 8 4 Memory Interface Unit The 20 bit memory addresses generated by the memory mapping unit feed into the mem ory interface unit The memory interface unit has a separate write only control register for each 256K quadrant of the 1M physical memory This control register specifies how mem ory access requests to that quadrant are to be dispatched to the memory chips connected to the Rabbit There are three separate chip select output lines CSO CS1 and CS2 that can be used to select one of three different memory chips A field in the control register determines which chip select is selected for memory accesses to the quadrant The same chip select line may be accessed in more than one quadrant For example if a 512K RAM is installed and is selected by CS1 it would be appropriate to use CS1 for accesses to the 3rd and 4th quadr
191. ced within 1 2 clock To transmit each byte in external clock mode the user must load the data register and then store the send code When the shift register is idle and the receiver provides a clock burst the data bits are transferred to the shift register and are shifted out Once the transfer is made to the shift register a new byte can be loaded into the transmit register and a new send code can be stored To receive a byte in external clock mode the user must set the receive code for the first byte and then store the receive code for the next byte after each byte is removed from the data register Since the receive code must be stored before the transmitter sends the next byte the receiver must service the interrupt within 1 2 baud clock to maintain full speed transmission This is usually not practical unless a flow control arrangement is made or the transmitter inserts gaps between the clock bursts In order to carry on high speed communication the best arrangement will usually be for the receiver to provide the clock When the receiver provides the clock the transmitter should always be able to keep up because it is double buffered and has a full character time to answer the transmitter data register empty interrupt The receiver will answer interrupts that are generated on the last clock rising edge If the interrupt can be serviced within 1 2 clock there will be no pause in the data rate If it takes the receiver longer to answer the
192. ch the processor can operate If an interrupt is requested and the priority of the interrupt is higher than that of the processor the interrupt will take place after the execu tion of the current instruction is complete except for privileged instructions Multiple interrupt priorities have been established to make it feasible for the embedded systems programmer to have extremely fast interrupts available Interrupt latency refers to the time required for an interrupt to take place after it has been requested Generally inter rupts of the same priority are disabled when an interrupt service routine is entered Some times interrupts must stay disabled until the interrupt service routine is completed other times the interrupts can be re enabled once the interrupt service routine has at least dis abled its own cause of interrupt In any case if several interrupt routines are operating at 44 Rabbit 3000 Microprocessor User s Manual the same priority this introduces interrupt latency while the next routine is waiting for the previous routine to allow more interrupts to take place If a number of devices have inter rupt service routines and all interrupts are of the same priority then pending interrupts can not take place until at least the interrupt service routine in progress is finished or at least until it changes the interrupt priority As a rule of thumb Rabbit Semiconductor usually suggests that 100 us be allowed for interrupt latenc
193. cial register and the lower byte is fixed by hardware for each interrupt as shown in Table 6 1 There are separate registers for internal interrupts IIR and external interrupts EIR to specify the high byte of the interrupt service routine address These registers are accessed by special instructions LD A IIR LD IIR A LD A EIR LD EIR A Interrupts are initiated by hardware devices or by certain 1 byte instructions called reset instructions RST 10 RST 18 RST 20 RST 28 RST 38 The RST instructions are similar to those on the Z80 and Z180 but certain ones have been removed from the instruction set 00 08 30 The RST interrupts are not inhibited regard less of the processor priority The user is advised to exercise caution when using these instructions as they are mostly reserved for the use of Dynamic C for debugging Unlike the Z80 or Z180 the IIR register contributes the upper byte of the service routine address for RST interrupts Since interrupt routines do not affect the XPC interrupt routines must be located in the root code space However they can jump to the extended code space after saving the XPC on the stack 3 5 1 Interrupt Priority The Z80 and Z180 have two levels of interrupt priority maskable and nonmaskable The nonmaskable interrupt cannot be disabled and has a fixed interrupt service routine address of 0x66 The Rabbit in contrast has three levels of interrupt priority and four priority lev els at whi
194. cifies the value of the slave address SAO SA1 input to the slave when the master reads or writes the registers The register that can be written by the slave can only be read by the master and vice versa If one side were to attempt to read a register at the same time that the other side attempted to write the register the result of the read could be scrambled However the protocols and handshaking bits used in communication are normally such that this never happens Table 13 1 Slave Port Registers Register Mnemonic Internal External Address Address Slave Port Data 0 Register SPDOR 0x20 0 Slave Port Data 1 Register SPDIR 0x21 1 Slave Port Data 2 Register SPD2R 0x22 2 Slave Port Status Register SPSR 0x23 3 Slave Port Control Register SPCR 0x24 N A If the user for some reason wants to depart from the suggested protocols and poll a register while waiting for the other side to write something to the register the user should be aware that all the bits might not change at the exact same time when the result changes and a transitional value could be read from the register where some bits have changed to the new value and others have not To avoid being confused by a transitional value the user can read the register twice and make sure both values are the same before accepting the value or the user can test only one bit for a change The transitional value can only exist for one read of the register and each bi
195. ck is on Parallel Port PF1 Serial Port D clock is on Parallel Port PFO 00 The serial port interrupt is disabled 01 The serial port uses Interrupt Priority 1 1 0 10 The serial port uses Interrupt Priority 2 11 The serial port uses Interrupt Priority 3 174 Rabbit 3000 Microprocessor User s Manual Table 12 16 Serial Port Control Register Ports E and F Serial Port x Control Register SECR Address 0xCC SFCR Address 0xDC Bit s Value Description 00 No operation These bits are ignored in the Async mode 01 In HDLC mode force receiver in Flag Search mode 7 6 10 No operation 11 In HDLC mode transmit an Abort pattern 0 Enable the receiver input 5 1 Disable the receiver input 4 x This bit is ignored 00 Async mode with 8 bits per character 01 Async mode with 7 bits per character In this mode the most significant bit of a byte is ignored for transmit and is always zero in receive data HDLC mode with external clock The external clocks are supplied as follows 3 2 10 e Transmit clock Serial Port F pins PGO and PGlon Parallel Port G Receive clock Serial Port E pins PG4 and PGS on Parallel Port G HDLC mode with internal clock The clock is 16x the data rate and the DPLL is used to recover the receive clock If necessary the clocks are supplied as follows e Transmit clock Serial Port F pins PGO and PGlon Parallel Port G Receive clock Serial Port E
196. code 0 7 To write internal I O registers there are two functions void WrPortI int PORT char PORTShadow int value void BitWrPortI int PORT char PORTShadow int value int bitcode The external registers are also accessible with Dynamic C functions int RdPortE int PORT returns PORT high byte zero int BitRdPortE int PORT int bitcode bit code 0 7 int WrPortE int PORT char PORTShadow int value int BitWrPortE int PORT char PORTShadow int value int bitcode In order to read a port the following code could be used k RdPortI PADR returns Port A Data Register 244 Rabbit 3000 Microprocessor User s Manual 18 3 Shadow Registers Many of the registers of the Rabbit s internal I O devices are write only This saves gates on the chip making possible greater capability at lower cost Write only registers are eas ier to use if a memory location called a shadow register is associated with each write only register To make shadow register names easy to remember the word shadow is appended to the register name For example the register GOCR Global Output Control register has the shadow GOCRShadow Some shadow registers are defined in the BIOS source code as shown below char GCSRShadow Global Control Status Register char GOCRShadow Global Output Control Register char GCDRShadow Global Clock Doubler Register If the port is a write only port the shadow register can be used to find out
197. code Count 1 Register QDCIR 0x0094 R XXXXXXXX Quad Decode Count High Register QDCIHR 0x0095 R XXXXXXXX Quad Decode Count 2 Register QDC2R 0x0096 R XXXXXXXX Quad Decode Count 2 High Register QDC2HR 0x0097 R XXXXXXXX Appendix D Rabbit 3000A Internal I O Registers 333 Table D 1 Rabbit 3000A Internal I O Registers continued Register Name Mnemonic I O Address R W Reset Interrupt 0 Control Register IOCR 0x0098 w xx000000 Interrupt 1 Control Register 0 0099 w xx000000 Timer A Control Status Register TACSR 0x00A0 R W 00000000 Timer A Prescale Register TAPR 0 00 1 XXXXXXX Timer A Time Constant 1 Register TATIR 0x00A3 w XXXXXXXX Timer A Control Register TACR 0x00A4 00000000 Timer A Time Constant 2 Register TAT2R 0 00 5 Timer A Time Constant 8 Register TAT8R 0x00A6 Timer A Time Constant 3 Register TAT3R 0x00A7 Timer A Time Constant 9 Register TAT9R 0x00A8 W XXXXXXXX Timer A Time Constant 4 Register TAT4R 0x00A9 Timer A Time Constant 10 Register 10 0x00AA W XXXXXXXX Timer A Time Constant 5 Register TATSR 0 00 Timer A Time Constant 6 Register TAT6R 0 00 Timer A Time Constant 7 Register TAT7R 0 00 Timer B Control Status Register TBCSR 0x00B0 R W xxxxx000 Timer B Control
198. code in WDTCR Note that although a watchdog timeout resets the processor it does not reset the timeout period stored in the WDTCR This was done inten tionally because an application may require the initialization of the processor resulting from the watchdog timeout to be based on a specific timeout period that is different from that of the reset initialization Table 7 12 Watchdog Timer Control Register WDTCR adr 0x08 Bit s Value Description 7 0 0 5 Restart hit the watchdog timer with a 2 second timeout period 0x57 Restart hit the watchdog timer with a l second timeout period 0 59 Restart hit the watchdog timer with a 500 ms timeout period 0x53 Restart hit the watchdog timer with a 250 ms timeout period 0 5 Restart the secondary watchdog timer starting with Rabbit 3000A chip other No effect on watchdog timer The watchdog timer may be disabled by storing a special code in the WDTTR register Normally this should not be done unless an external watchdog device is used The purpose of the watchdog is to unhang the processor from an endless loop caused by a software crash or a hardware upset It is important to use extreme care in writing software to hit the watchdog timer or to turn off the watchdog timer The programmer should not sprinkle instructions to hit the watch dog timer throughout his program because such instructions can become part of an endless loop if
199. corresponding output an I O strobe The nature of the I O strobe is controlled by the I O bank control registers IBxCR The data direction must be set to output for the I O strobe to work PEBxR These are individual registers to set individual output bits on or off PECR Parallel Port E control register This register is used to control the clocking of the upper and lower nibble of the final output register of the port On reset bits 0 1 4 and 5 are reset to zero On reset the data direction register and function register are zeroed making all pins inputs and disabling the alternate output functions In addition certain bits in the control register are zeroed bits 0 1 4 5 to ensure that data is clocked into the output registers when loaded All other registers associated with Port E are not initialized on reset 138 Rabbit 3000 Microprocessor User s Manual Table 9 11 Parallel Port E Register functions Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PEDR R W PE7 PE6 PES PE4 PE3 PE2 PEI PEO adr 0x070 PEFR W alt I7 alt I6 alt I5 alt I4 alt I3 alt I2 alt I1 alt IO adr 0x075 PEDDR W dir dir dir dir dir dir dir dir adr 0x077 out out out out out out out out PEBOR W x x x X X X X PEO adr 0x078 PEBIR W x x x x x x 1 x adr 0x079 PEB2R W x x x x x PE2 x x adr 0x07A PEB3R W X X X X PE3 X X X adr 0x07B PEB4R W x x x PE4 x
200. count opens the latches Table 7 24 Input Capture MSB x Register Input Capture MSB x Register ICM1R Address 0x5B ICM2R Address 0x5F Bit s Value Description 7 0 read The most significant eight bits of the latched Input capture count are returned Chapter 7 Miscellaneous Functions 109 7 14 Quadrature Decoder The two channel Quadrature Decoder accepts inputs via Parallel Port F from two external optical incremental encoder modules Each channel of the Quadrature Decoder accepts an in phase I and a quadrature phase Q signal and provides 8 bit counters to track shaft rotation and provide interrupts when the count goes from 0x00 to OxFF or from OxFF to 0x00 The Quadrature Decoder contains digital filters on the inputs to prevent false counts The Quadrature Decoder is clocked by the output of Timer A10 Register Name Mnemonic Address R W Reset Quad Decode Ctrl Status Register QDCSR 0x90 R W XXXXXXXX Quad Decode Control Register QDCR 0x91 00xx0000 Quad Decode Count 1 Register QDCIR 0x94 R XXXXXXXX Quad Decode Count 2 Register QDC2R 0x96 XXXXXXXX Each Quadrature Decoder channel accepts inputs from either the upper nibble or lower nibble of Parallel Port F The I signal is input on an odd numbered port bit while the Q signal is input on an even numbered port bit There is also a disable selection which is guaranteed not to generate a count increm
201. d 0 0 PWM output High for single block 1 Spread PWM output throughout the cycle See Table B 25 to Table B 27 for configuration information involving bits 5 1 reflecting the additional capabilities of Rev A and later Rabbit 3000 microprocessors Table 7 18 PWM MSB x Register PWM MSB x Register PWMOR Address 0x89 PWM1R Address 0x8B PWM2R Address 0x8D PWM3R Address 0x8F Bit s Value Description The most significant eight bits for the Pulse Width Modulator count are stored 7 0 write With a count of n the PWM output will be High for n 1 clocks out of the 1024 clocks of the PWM counter 104 Rabbit 3000 Microprocessor User s Manual 7 13 Input Capture The two channel Input Capture can be used to time input signals from various port pins Each Input Capture channel consists of a sixteen bit counter that is clocked by the output of Timer A8 and can be connected to one or two out of sixteen parallel port pins The Input Capture channel captures the state of its counter upon either of two programmed conditions and can then generate an interrupt The programmed conditions can also be used to start and stop the counter Register Name Mnemonic Address R W Reset Input Capture Ctrl Status Register ICCSR 0x56 R W 00000000 Input Capture Control Register ICCR 0x57 W 00 Input Capture Trigger 1 Register ICTIR 0x58 00000000 Inp
202. d KP oa N N 5 m m m m Fh Fh next sequential instruction If byte is 2 11111110 jr is to itself xpc n n m m m 19 7 7 7 6 13 11 11 10 13 11 10 10 13 15 15 15 11 13 13 n p op o o o o o Chapter 21 Instructions in Alphabetical Order With Binary Encoding 267 Instruction Byte 1 Byte 2 Byte 3 Byte 4 clk A I V LD A BC 00001010 6 r s LD A DE 00011010 6 r LD A mn 00111010 n m 9 r s LD A EIR 11101101 01010111 4 fr LD A IIR 11101101 01011111 4 fr LD A XPC 11101101 01110111 4 r LD dd mn 11101101 01441011 n m 13 r LD dd BC 11101101 01dd1001 4 LD dd DE 11101101 01dd0001 4 LD dd mn 00dd0001 n m 6 r LD bc mn 00000001 LD de mn 00010001 LD hl mn 00100001 LD sp mn 00110001 LD EIR A 11101101 01000111 4 LD HL HL d 11011101 11100100 d 11 r s LD HL IX d 11100100 d 9 r s LD HL IY d 11111101 11100100 d 11 r s LD HL mn 00101010 n m 11 r s LD HL SP n 11000100 9 r LD HL IX 11011101 01111100 4 r LD HL IY 11111101 01111100 4 r LD IIR A 11101101 01001111 4 LD IX mn 11011101 00101010 n m 13 s LD IX SPrn 11011101 11000100 n 11 LD IX HL 11011101 01111101 4 LD IX mn 11011101 00100001 n m 8
203. d can actually interfere with the bootstrap operation by mask ing the Write Empty signal Chapter 7 Miscellaneous Functions 101 Serial Port A is selected for bootstrap operation as a clocked serial port when SMODE 10 In this case bit 7 of Parallel Port C is used for the serial data and bit 1 of Parallel Port B is used for the serial clock Note that the serial clock must be externally supplied for boot strap operation This precludes the use of a serial EEPROM for bootstrap operation Serial Port A is selected for bootstrap operation as an asynchronous serial port when SMODE 11 In this case bit 7 of Parallel Port C is used for the serial data and the 32 kHz oscillator is used to provide the serial clock A dedicated divide circuit allows the use of the 32 kHz signal to provide the timing reference for the 2400 bps asynchronous transfer Only 2400 bps is supported for bootstrap operation and the serial data must be eight bits for proper operation In the case of asynchronous bootstrap Serial Port A accepts either regular NRZ data or IrDA encoded data RZI coding with 3 16ths bit cell automatically The hardware contians a monostable multivibrator triggered by the falling edge of serial data into the data path The one shot stretches any IrDA encoded pulses enough to look like NRZ data but not so much as to interfere with real NRZ data When the first phase of a bootstrap is performed using Serial Port A the TXA signal is not needed s
204. d should be driven from the output of Al and the reload register should be set to 255 This will cause counting to be as slow as possible and consume minimum power As for general purpose timers Timer A has seven separate subtimer units Al and A2 A7 that are also referred to as timers Most likely if a serial port is going to be used and a timer is needed to provide the baud clock that timer will be set up to be driven directly from the clock and the interrupt associated with that timer will be disabled Serial port interrupts are generated by the serial port logic The value in the reload register can be changed while the timer is running to change the period of the next timer cycle When the reload register is initialized the contents of the count down counter may be unknown for example during power up initialization If interrupts are enabled then the first interrupt may take place at an unknown time Similarly if the timer output is being used to drive the clock for a parallel port or serial port the first clock may come at a random time If a periodic clock is desired it is probably not important when the first clock takes place unless a phase relationship is desired relative to a different timers A phase relationship between two timers can be obtained in several ways One way is to set both reload registers to zero and to wait long enough for both timers to reload maxi mum 256 clocks Then both timers reload registers ca
205. data segment are combined into a single root code segment In the D space the segments are separately mapped to flash and RAM to provide storage for con stant data and variable data The hardware method to achieve separate 20 bit addresses for the D space is to invert either 16 or A19 for data accesses The inversion may be speci fied separately for the root segment and the data segment Normally A16 is inverted for data accesses in the root segment This causes data accesses to the root segment to be moved 64k higher to a section of flash starting at 20 bit address 64k that is reserved for constant data A19 is normally inverted for data accesses to the data segment causing the data accesses in the data segment to be moved to an address 512k higher in the 20 bit space an address normally mapped to RAM The stack segment and the XPC segment do 28 Rabbit 3000 Microprocessor User s Manual not have split I and D space and memory accesses to these segments do not distinguish between I and D space The advantage of having more root code space is that root code executes faster because short calls using a 16 bit address are used to call it This compares to long calls that have a 20 bit address for extended code Data located in the root can be more conveniently accessed due to the comparatively limited instructions available for accessing data in the full 20 bit space and the greater overhead involve in manipulating 20 bit addresses in a processor
206. ding data leaving the data register empty This causes an interrupt request The interrupt routine normally answers the interrupt before the shift register runs dry 9 to 11 baud clocks depending on the mode of operation The interrupt routine stores the next data item in the data register clearing the interrupt request and supplying the next data bits to be sent When all the characters have been sent the interrupt service routine answers the interrupt once the data register becomes empty Since it has no more data it clears the interrupt request by storing to the status register At this point the routine should check if the shift register is empty normally it won t be If it is because the interrupt was answered late the interrupt routine should do any final cleanup and store to the status register again in case the shift register became empty after the pending interrupt is cleared Normally though the interrupt service routine will return and there will be a final interrupt to give the routine a chance to disable the output buffers as in the case for RS 485 transmission 180 Rabbit 3000 Microprocessor User s Manual 12 5 Receive Serial Data Timing When the receiver is ready to receive data a falling edge indicates that a start bit must be detected The falling edge is detected as a different Rx input between two different clocks the clock being 8x or 16x the baud rate Once the start bit has been detected data bits are sampled
207. e See the Rabbit 3000 Designer s Handbook chapter Low Power Design and Sup port for more details Chapter 18 Other Rabbit Software 243 18 2 Reading and Writing I O Registers The Rabbit has two I O spaces internal I O registers and external I O registers 18 2 1 Using Assembly Language The fastest way to read and write I O registers in Dynamic C is to use a short segment of assembly language inserted in the C program Access is the same as for accessing data memory except that the instruction is preceded by a prefix IOI or IOE to indicate the internal or external I O space For example compute value and write to Port A Data Register value x y asm 14 a value value to write 101 14 PADR a write value to PADR endasm In the example above the IOT prefix changes a store to memory to a store to an internal I O port The prefix ioe is used for writes to external I O ports 18 2 2 Using Library Functions Dynamic C functions are available to read and write I O registers These functions are pro vided for convenience For speed assembly code is recommended For a complete description of the functions noted in this section refer to the Dynamic C User s Manual or from the Help menu in Dynamic C access the HTML Function Reference or Function Lookup options To read internal I O registers there are two functions int RdPortI int PORT returns PORT high byte zero int BitRdPortI int PORT int bitcode bit
208. e When the page is moved by 4K the previous end of code is still visible in the window provided that the midpoint of the page was crossed before moving the page alignment As the compiler compiles code in the extended code window it checks at opportune times to see if the code has passed the midpoint of the window or F000 When the code passes the compiler slides the window down by 4K so that the code at F000 x becomes resident at E000 x This results in the code being divided into segments that are typically 4K long but which can very short or as long as 8K Transfer of control can be accom plished within each segment by 16 bit addressing 20 bit addressing is required between segments 128 Rabbit 3000 Microprocessor User s Manual 9 PARALLEL PORTS The Rabbit has seven 8 bit parallel ports designated A B C D E F and G The pins used for the parallel ports are also shared with numerous other functions as shown in Table 5 2 The important properties of the ports are summarized below Port A Shared with the slave port data interface and auxiliary I O data bus Port B Shared with control lines for slave port auxiliary I O address bus and clock for clocked serial mode option for Serial Ports A and B Port C Shared with serial port data I O Port D 4 bits shared with alternate I O pins for Serial Ports A and B 4 bits not shared Port D can be configured as open drain outputs Port D also contains output
209. e I O control register and its corresponding space in the 64K address space Table 10 2 External I O Register Address Range and Pin Mapping Control Register Port E I O Address I O Address Pin A 15 13 Range IBOCR PEO 000 0x0000 0x 1 FFF IBICR 1 001 0x2000 0x3FFF IB2CR PE2 010 0 4000 0 5 IB3CR PE3 O11 0x6000 0x7FFF IB4CR PE4 100 0 8000 0 9 IB5CR PE5 101 0xA000 0xBFFF IB6CR PE6 110 0xC000 0xDFFF IB7CR PE7 111 0 000 Chapter 10 I O Bank Control Registers 147 148 Rabbit 3000 Microprocessor User s Manual 11 TIMERS There are two timers Timer A and Timer B Timer A is intended mainly for generating the clock for various peripherals baud clock for the serial ports a periodic clock for clocking Parallel Ports D and E or for generating periodic interrupts Timers A1 A7 are general purpose timers and Timers A8 A 10 are dedicated to specific peripherals Timer B can be used for the same functions but it cannot generate the baud clock Timer B is more flexible when it can be used because the program can read the time from a continu ously running counter and events can be programmed to occur at a specified future time Timer A System Serial E Serial F Serial A Input Capture PWM
210. e base of flash memory and contains the startup code as well as other code that may happen to be stored there The data segment usage varies depending on the overall strategy for setting up memory It may be an extension of 24 Rabbit 3000 Microprocessor User s Manual the root segment or it may contain data variables The stack segment is normally 4K long and it holds the system stack The XPC segment is normally used to execute code that is not stored in the root segment or the data segment Special instructions support executing code that is visible in the XPC segment The memory interface unit receives the 20 bit addresses generated by the memory map ping unit The memory interface unit conditionally modifies address lines 16 18 and A19 The other address lines of the 20 bit address are passed unconditionally The mem ory interface unit provides control signals for external memory chips These interface sig nals are chip selects 50 CS1 CS2 output enables OEO 1 and write enables WE1 These signals correspond to the normal control lines found on static mem ory chips chip select or CS output enable or OE and write enable or WE In order to generate these memory control signals the 20 bit address space is divided into four quad rants of 256K each A bank control register for each quadrant determines which of the chip selects and which pair of output enables and write enables if any is enabled when a
211. e configured to use a higher priority interrupt There is an exception to be aware of when a serial port has to operate at an extremely high speed At 115 200 bps the highest speed of a PC serial port the interrupts must be serviced in 10 baud times or 86 us in order not to lose the received characters If all six serial ports were operating at this receive speed it would be necessary to service the interrupt in less than 21 5 us to assure no lost characters In addition the time taken by other interrupts of equal or higher priority would have to be considered A receiver service routine might appear as follows below The byte at bufptr is used to address the buffer where data bits are stored It is necessary to save and increment this byte because characters could be han dled out of order if two receiver interrupts take place in quick succession receive PUSH HL 10 save HL PUSH DE 10 save DE LD HL struct 6 LD A HL 5 get in pointer LD E A 2 save in pointer in E INC HL 2 point to out pointer CMP A HL 5 see if in pointer out pointer buffer full JR Z roverrun 5 go fix up receiver over run INC A 2 incement the in pointer AND A mask 4 mask such as 11110000 if 16 buffer locs DEC HL 52 192 Rabbit 3000 Microprocessor User s Manual LD HL A 6 update the in pointer IOI LD A SCDR ll get data register port C clears interrupt request IPRES 4 restore the interrupt priority 68 clocks to here
212. e device that requests the interrupt If that latch is cleared before the interrupt is latched by the central interrupt logic then the interrupt request is lost and no interrupt takes place This is shown in Table 7 15 The priorities shown in this table apply only for interrupts of the same priority level and are only meaningful if two interrupts are requested at the same time Most of the devices can be programmed to interrupt at priority level 1 2 or 3 Chapter 7 Miscellaneous Functions 97 Table 7 15 Interrupts Priority and Action to Clear Requests Priority Interrupt Source Action Required to Clear the Interrupt Highest External 1 Automatically cleared by the interrupt acknowledge External 0 Automatically cleared by the interrupt acknowledge Periodic 2 kHz Read the status from the GCSR Quadrature Decoder Read the status from the QDCSR Timer B Read the status from the TBSR Timer A Read the status from the TASR Input Capture Read the status from the ICCSR Rd Read the data from the SPDOR SPD1R or SPD2R Slave Port Wr Write data to the SPDOR SPDIR SPD2R or write a dummy byte to the SPSR Rx Read the data from the SEDR or SEAR Serial Port E Tx Write data to the SEDR SEAR SELR or write a dummy byte to the SESR Rx Read the data from the SFDR or SFAR Serial Port F Tx Write data to the SFDR SFAR SFLR or write a dummy byte to the SFSR Rx Read the data from the SADR or SA
213. e responds with a similar message as an acknowledgement Nothing happens unless the master sends a message The slave is not allowed to initiate a message but the slave could signal the master by using a parallel port line other than SLAVEATN or by placing data in one of the registers the master can read without interfering with the mes sage protocol The master sends a message byte by storing it in SPDOR The slave notices that SPDOR is full and reads the byte When the master notices that SPDOR is empty because the slave read it the master stores the next byte in SPDOR Either side can tell if any register is empty or full by reading the status register When the slave acknowledges the message with a reply message the process is reversed To perform the protocol with interrupts a slave interrupt can be generated each time the slave receives a character The slave can acknowledge the master by reading SPDOR if the master is polling for the slave response 208 Rabbit 3000 Microprocessor User s Manual to each character If the master is to be interrupted to acknowledge each character the slave can create an interrupt in the master by storing a dummy character in SPDOR to cre ate a master interrupt assuming that the SLAVEATTN line is wired to interrupt the mas ter The acknowledgement message works in a similar manner except that the master writes a dummy character to interrupt the slave to say that it has the character Several problems
214. e stored 7 0 Write This compare value will be loaded into the actual comparator when the current compare detects a match Table 11 11 Timer B Count MSB Register Timer B Count MSB Register TBCMR Address 0xBE Bit s Value Description 7 6 Read The current value of the two MSBs of the Timer B counter are reported 5 0 These bits are always read as zeroes Table 11 12 Timer B Count LSB Register Timer B Count LSB Register TBCLR Address 0xBF Bit s Value Description 7 0 Read The current value of the eight LSBs of the Timer B counter are reported 158 Rabbit 3000 Microprocessor User s Manual 11 2 1 Using Timer B Normally the prescaler is set to divide perclk 2 by a number that provides a counting rate appropriate to the problem For example if the clock is 22 1184 MHz then perclk 2 is 11 0592 MHz A Timer B clock rate of 11 0592 MHz will cause a complete cycle of the 10 bit clock in 92 6 us Normally an interrupt will occur when either of the comparators in Timer B generates a pulse The interrupt routine must detect which comparator is responsible for the interrupt and dispatch the interrupt to a service routine The service routine sets up the next match value which will become the match value after the next interrupt If the clocked parallel ports are being used then a value will normally be loaded into some bits of the parallel port register These bits
215. e used to create an intelligent peripheral or a slave processor For example protocol stacks can be off loaded to a Rabbit slave The master can be any processor The Rabbit can be cold booted so unprogrammed flash memory can be soldered in place You can write serious software be it 1 000 or 50 000 lines of C code The tools are there and they are low in cost If you know the Z80 or Z180 you know most of the Rabbit A simple 10 pin programming interface replaces in circuit emulators and PROM pro grammers The battery backable time date clock is included The standard Rabbit chip is made to industrial temperature and voltage specifications The Rabbit 3000 is backed by extensive software development tools and libraries espe cially in the area of networking and embedded Internet Rabbit 3000 Microprocessor User s Manual 1 3 Differences Rabbit 3000 vs Rabbit 2000 For the benefit of readers who are familiar with the Rabbit 2000 microprocessor the Rab bit 3000 is contrasted with the Rabbit 2000 in the table below Feature Rabbit 3000 Rabbit 2000 Maximum clock speed 54 MHz 30 MHz PER aie main oscillator may be 30 MHz 32 MHz 32 768 kHz crystal oscillator External Internal Maximum operating voltage 3 6V 5 5 V Maximum I O input voltage 5 5 V 5 5 V Current consumption 2 mA MHz 3 3 V 4 mA MHz 5 V Number of package pins 128 100 16 x 16
216. ected to CS1 is not powered by VBAT so that any information held within it is lost during power down no pull up resistor on CS1 is appropriate as this would add leakage through the protection diode to drain VBAT The RESOUT signal which is High during reset and power down can be used to control an external power switch to dis connect VDD from supplying VBAT The default selection for the memory control signals consists of CSO and writes are disabled This selection can also be immediately programmed to match the hardware configuration A typical sequence would be to speed up the clock to full speed followed by selection of the appropriate number of wait states and the chip select signals output enable signals and write enable signals At this point software would usually check the system status to determine what type of reset just occurred and begin normal opera tion The default values for all of the peripheral control registers are shown with the following register listing The registers within the CPU affected by reset are the Stack Pointer SP the Program Counter PC the IIR register the EIR register and the IP register The IP register is set to all ones disabling all interrupts while all of the other listed CPU regis ters are reset to all zeros Table 7 14 describes the state of the I O pins after an external reset is recognized by the Rabbit CPU Note that the RESET signal must be held low for three clock
217. ed when I O operations are executed writes to the internal I O registers require only two clocks rather than the minimum of three clocks required for writes to memory or external I O devices Chapter 3 Details on Rabbit Microprocessor Features 39 3 4 How to Do It in Assembly Language Tips and Tricks 3 4 1 Zero HL in 4 Clocks BOOL HL 2 clocks clears carry HL is 1 or 0 RR HL 2 clocks 4 total get rid of possible 1 This sequence requires four clocks compared to six clocks for LD HL 0 3 4 2 Exchanges Not Directly Implemented HL lt gt HL eight clocks EX DE HL 2 clocks EX DE HL 4 clocks EX DE HL 2 clocks 8 total DE lt gt DE six clocks EX DE HL 2 clocks EX DE HL 2 clocks EX DE HL 2 clocks 6 total BC lt gt BC 12 clocks EX DE HL 2 clocks EX DE HL 4 EX DE HL 2 2 EX DE HL 3222 Move between IX and DE DE IX TY gt DE DE gt IX TY IX IX gt DE EX DE HL LD HL IX IY LD IX IY HL EX DE HL 8 clocks total DE IX IY EX DE HL LD IX IY HL EX DE HL 8 clocks total 3 4 3 Manipulation of Boolean Variables The following examples show logical operations involving HL when HL is a logical variable with a value of 1 or 0 Such operations are important for the C language where the least bit of a 16 bit integer is used to represent a logical result in HL Logical not operator invert bit 0 of HL in four clocks also works for
218. ed with Timer A1 11 1 1 Timer A I O Registers The I O registers for Timer A are listed in Table 11 1 Table 11 1 Timer A I O Registers Register Name Mnemonic I O address R W Reset Timer A Control Status Register TACSR 0 R W 00000000 Timer A Prescale Register TAPR OxA1 XXXXXXX 1 Timer A Time Constant Register TATIR 0 Timer A Control Register TACR OxA4 00000000 Timer A Time Constant 2 Register TAT2R OxA5 Timer A Time Constant 8 Register TAT8R OxA6 w XXXXXXXX Timer A Time Constant 3 Register TAT3R OxA7 w XXXXXXXX Timer A Time Constant 9 Register TATOR 8 Timer A Time Constant 4 Register TAT4R OxA9 Timer A Time Constant 10 Register TATIOR OxAA Timer A Time Constant 5 Register TATSR OxAB w XXXXXXXX Timer A Time Constant 6 Register TAT6R OxAD W XXXXXXXX Timer A Time Constant 7 Register TAT7R OxAF W XXXXXXXX Chapter 11 Timers 151 The following table summarizes Timer A s capabilities Table 11 2 Timer A Capabilities Timer Cascade Interrupt Dedicated Connection Al none yes Parallel Ports D G Timer B A2 from Al yes Serial Port E A3 from Al yes Serial Port F A4 from Al yes Serial Port A A5 from Al yes Serial Port B A6 from Al yes Serial Port C A7 from Al yes Serial Port D 8 no Input Capt
219. egister SDLR OxF2 R W XXXXXXXX Serial Port D Status Register SDSR OxF3 R 0xx00000 Serial Port D Control Register SDCR OxF4 000000 Serial Port D Extended Register SDER OxF5 w 00000000 Serial Port E Data Register SEDR 0xC8 R W XXXXXXXX Serial Port E Address Register SEAR 0xC9 R W XXXXXXXX Serial Port E Long Stop Register SELR OxCA R W XXXXXXXX Serial Port E Status Register SESR 0 R 0xx00000 Serial Port E Control Register SECR OxCC w xx000000 Serial Port E Extended Register SEER 0xCD 00000000 Serial Port F Data Register SFDR OxD8 R W XXXXXXXX Serial Port F Address Register SFAR 0xD9 R W XXXXXXXX Serial Port F Long Stop Register SFLR OxDA R W XXXXXXXX Serial Port F Status Register SFSR 0xDB R 0xx00000 Serial Port F Control Register SFCR 0xDC 000000 Serial Port F Extended Register SFER OxDD 00000000 Watchdog Timer Control Register WDTCR 0x08 W 00000000 Watchdog Timer Test Register WDTTR 0x09 W 00000000 78 Rabbit 3000 Microprocessor User s Manual 7 MISCELLANEOUS FUNCTIONS 7 1 Processor Identification Four read only registers are provided to allow software to identify the Rabbit micropro cessor and recognize the features and capabilities of the chip Five bits in each of these registers are unique to each version of the chip One register is reserved for the on chip flash memory configuration GROM one register is reserved for the on chip RAM mem ory configuration GRAM one register identifies t
220. egister SPUER 0x0320 w 00000000 Parallel Port A User Enable Register PAUER 0x0330 w 00000000 Parallel Port F User Enable Register PFUER 0x0338 00000000 Parallel Port B User Enable Register PBUER 0x0340 00000000 Parallel Port G User Enable Register PGUER 0x0348 00000000 Parallel Port C User Enable Register PCUER 0x0350 00000000 Input Capture User Enable Register ICUER 0x0358 w 00000000 Parallel Port D User Enable Register PDUER 0x0360 w 00000000 Parallel Port E User Enable Register PEUER 0x0370 00000000 330 Rabbit 3000 Microprocessor User s Manual Table D 1 Rabbit 3000A Internal I O Registers continued Register Name Mnemonic I O Address R W Reset Bank User Enable Register IBUER 0x0380 w 00000000 PWM User Enable Register PWUER 0x0388 w 00000000 Quad Decode User Enable Register QDUER 0x0390 W 00000000 External Interrupt User Enable Register IUER 0x0398 W 00000000 Timer A User Enable Register TAUER 0x03A0 W 00000000 Timer B User Enable Register TBUER 0x03BO W 00000000 Serial Port A User Enable Register SAUER 0x03CO W 00000000 Serial Port E User Enable Register SEUER 0x03C8 W 00000000 Serial Port B User Enable Register SBUER 0 03 w 00000000 Serial Port F User Enable Register SFUER 0x03D8 w 00000000 Serial Port C User Enable Register SCUER 0x03E0 w 00000000 Serial Port D User Enable Register
221. em when there is a conflict is to assign inputs and outputs in such a manner as to avoid the bug Either Parallel Port A can be used as inputs in which case Parallel Port F has full function or if Parallel Port A cannot be used as inputs use any pins on Parallel Port F not used for PWM or serial clock outputs as inputs and take the precaution of setting up Parallel Port F before the conflicting functionality of Parallel Port A is enabled 142 Rabbit 3000 Microprocessor User s Manual 9 7 Parallel Port G Parallel Port G is a byte wide port with each bit programmable for data direction and drive These are simple inputs and outputs controlled and reported in the Port G Data Reg ister As outputs the bits of the port are buffered with the data written to the Port G Data Register transferred to the output pins on a selected timing edge The outputs of Timer A1 Timer B1 or Timer B2 can be used for this function with each nibble of the port having a separate select field to control this timing These inputs and outputs are also used for access to other peripherals on the chip As out puts Port G can carry the data and clock outputs from Serial Ports E and F As inputs Port G can carry the data and clock inputs for these two serial ports The following registers are described in Table 9 17 and in Table 9 18 Table 9 16 Parallel Port G Registers
222. emory mapping scheme is fairly complex the user rarely needs to worry about it because the details are handled by the Dynamic C development system Except for a handful of special instructions see Section 19 5 16 bit Load and Store 20 bit Address the Rabbit instructions directly address a 64K data memory space This means that the address fields in the instructions are 16 bits long and that the registers that may be used as pointers to memory addresses index registers IX program counter and stack pointer SP are also 16 bits long Because Rabbit instructions use 16 bit addresses the instructions are shorter and can exe cute much faster than if for example 32 bit addresses were used The executable code is very compact The Rabbit memory mapping unit is similar to but more powerful than the Z180 mem ory mapping unit Figure 3 2 illustrates the relationship among the major components related to addressing memory Memory Memory M Processor Mapping Interface 2 Unit Unit Chips 20 bits plus control Figure 3 2 Addressing Memory Components The memory mapping unit receives 16 bit addresses as input and outputs 20 bit addresses The processor except for certain LDP instructions sees only a 16 bit address space That is it sees 65536 distinctly addressable bytes that its instructions can manipulate Three segment registers are used to map this 16 bit space into a 1 me
223. ent or decrement on either entering or exiting the disable state The operation of the counter as a function of the I and Q inputs is shown below Interrupt 110 Rabbit 3000 Microprocessor User s Manual The Quadrature Decoders are clocked by the output of Timer A10 giving a maximum clock rate of one half of the peripheral clock rate The time constant of Timer A10 must be fast enough to sample the inputs properly Both the I and Q inputs go through a digital fil ter that rejects pulses shorter than two clock period wide In addition the clock rate must be High enough that transitions on the I and Q inputs are sampled in different clock cycles The Input Capture may be used to measure the pulse width on the I inputs because they come from the odd numbered port bits The operation of the digital filter is shown below peRICLOCK I 1L TL LIT 1 LJ LJ LI LI TIMER 10 REJECTED ACCEPTED The Quadrature Decoder generates an interrupt when the counter increments from OxFF to 0x00 or when the counter decrements from 0x00 to The timing for the interrupt is shown below Note that the status bits in the QDCSR are set coincident with the interrupt and the interrupt and status bits are cleared by reading the QDCSR TIMER A10 Q INPUT PERI CLOCK COUNTER 0x00 OxFF INTERRUPT Chapter 7 Miscellaneous Functions 111
224. eous Functions 81 Table 7 5 Global Control Status Register Global Control Status Register GCSR Address 0x00 Bit s Value Description 00 No Reset or Watchdog Timer time out since the last read The Watchdog Timer timed out These bits are cleared by a read of this 7 6 ol register rd only 10 This bit combination is not possible 11 Reset occurred These bits are cleared by a read of this register 0 No effect on the Periodic interrupt This bit will always be read as zero i 1 Force a Periodic interrupt to be pending 4 2 XXX See table below for decode of this field 00 Periodic interrupts are disabled 01 Periodic interrupts use Interrupt Priority 1 s 10 Periodic interrupts use Interrupt Priority 2 11 Periodic interrupts use Interrupt Priority 3 Table 7 6 Clock Select Field of GCSR Clock Select CPU Clock Peripheral Main i ue Bits 4 2 GCSR Clock Oscillator GPSCR 000 osc 8 osc 8 on short CS option 001 osc 8 osc on short CS option 010 osc osc on none 011 osc 2 osc 2 on none 100 32 kHz or fraction 32 kHz or fraction on self timed option 101 32 kHz or fraction 32 kHz or fraction off self timed option 110 osc 4 osc 4 on short CS option 111 osc 6 osc 6 on short CS option 82 Rabbit 3000 Microprocessor User s Manual 7 3 Clock Doubler The clock doubler is provided to allow a lower frequency crystal to be used for the main
225. er 2 inputs from Port F bits 3 and 2 11 Quadrature Decoder 2 inputs from Port F bits 7 and 6 5 0 Eight bit quadrature decoder counters 1 Ten bit quadrature decoder counters 4 This bit is reserved and should be written as zero 32 00 Disable Quadrature Decoder 1 inputs Writing a new value to these bits will not cause Quadrature Decoder 1 to increment or decrement 01 This bit combination is reserved and should not be used 10 Quadrature Decoder 1 inputs from Port F bits 1 and 0 11 Quadrature Decoder 1 inputs from Port F bits 5 and 4 1 0 00 Quadrature Decoder interrupts are disabled 01 Quadrature Decoder interrupt use Interrupt Priority 1 10 Quadrature Decoder interrupt use Interrupt Priority 2 11 Quadrature Decoder interrupt use Interrupt Priority 3 Table B 29 Quadrature Decoder Count High Register Quadrature Decoder Count High Register QDC1HR Address 0x0095 QDC2HR Address 0x0097 Bit s Value Description 152 read These bits are reserved and will always read as zeros 1 0 read The current value of bits 9 8 of the Quadrature Decoder counter is reported 316 Rabbit 3000 Microprocessor User s Manual Iinput Q input Cnt 8 bit TA Cnt 10 bit 3FF Interrupt T Figure B 22 Quadrature Decode 8 bit and 10 bit Counter Timing Appendix B Rabbit 3000 Revisions 317 B 2 Pins with Alternate Functions The Rabbit
226. er pins are required to exit the core module since the slave port and the I O bus can share the same pins and the memory bus no longer needs to exit the module to provide I O capability Because the I O bus has less activity and is slower than the memory bus it can be run further physically without EMI and ground bounce problems 5 V signals can appear on the I O bus since the Rabbit 3000 inputs are 5 V tolerant 5 V signals could easily cause problems on the main bus if non 5 V tolerant 3 3 V memories are connected 2 2 8 Timers The Rabbit has several timer systems The periodic interrupt is driven by the 32 768 kHz oscillator divided by 16 giving an interrupt every 488 us if enabled This is intended to be used as a general purpose clock interrupt Timer A consists of ten 8 bit countdown and reload registers that can be cascaded up to two levels deep Each countdown register can be set to divide by any number between 1 and 256 The output of six of the timers is used to provide baud clocks for the serial ports Any of these registers can also cause interrupts and clock the timer synchronized parallel output ports Timer B consists of a 10 bit counter that can be read but not written There are two 10 bit match registers and comparators If the match register matches the counter a pulse is output Thus the timer can be programmed to output a pulse at a predetermined count in the future This pulse can be used to clock the timer synchronized parallel p
227. er you must use an external oscillator buffer that will allow for duty cycle adjustment by changing the resistance of the power and ground connections as shown below Adjust the values of these resistors to 1 vary the duty cycle Figure 16 8 External Oscillator Buffer 230 Rabbit 3000 Microprocessor User s Manual 16 5 Power and Current Consumption With the Rabbit 3000 it is possible to design systems that perform their task with very low power consumption Unlike competitive processors the Rabbit 3000 has short chip select features designed to minimize power consumption by external memories which can easily become the dominant power consumers at low clock frequencies if not well handled The preferred configuration for a Rabbit based system is to use an external crystal or reso nator that has a frequency 2 of the maximum internal clock frequency The oscillator fre quency can be doubled or divided by 2 4 6 or 8 giving a variety of operating speeds from the same crystal frequency In addition the 32 768 kHz oscillator the drives the bat tery backable clock can be used as the main processor clock and to save the substantial power consumed by the fast oscillator the fast oscillator can be turned off This scenario is called the sleepy mode with a clock speed in the range of 2 kHz to 32 kHz and with an operating system current consumption in the range of 10 to 120 uA depending on fre quency and voltage Up to a
228. eripheral clock divided by two This clock is always the same as the processor clock or it is faster than the processor clock by a factor of eight The output pulses are always one clock long Clocking of the counters takes place on the negative edge of this pulse When the counter reaches zero the reload register is loaded on the next input pulse instead of a count being performed The reload registers may be reloaded at any time since the peripheral clock is synchronous with the processor clock Timers A2 A3 A4 A5 A6 and A7 always provide the baud clock for Serial Ports E F A B C and D respectively Except for very low baud rates clock A1 does not need to be used to prescale the input clock for timers A2 A7 For example if the system clock is 11 0592 MHz and the timer A4 divides by 144 an asynchronous baud rate of 2400 bps can be achieved in one step assuming that the timer is clocked by peripheral clock divided by two The clock input to the serial port can be 8 or 16 times the baud rate for asynchronous mode and 8 times the baud rate for synchronous mode The maximum asynchronous baud rate with a 11 0592 MHz clock would be 11 059 200 1 8 1 382 400 150 Rabbit 3000 Microprocessor User s Manual For seven of the counters A1 A7 the terminal count condition is reported in a status regis ter and can be programmed to generate an interrupt There is one interrupt vector for Timer A and a common interrupt priority A common
229. ernal Interrupts Reg Name Reg Address Bits 7 6 Bits 5 4 Bits 3 2 Bits 1 0 IOCR 10011000 XX INTOB PEA INTOA PEO Enb INTO 10011001 XX INTIB PES INTIA Enb INTI edge triggered edge triggered interrupt 00 disabled 00 disabled 00 disable 10 rising 10 rising Ol pril Ol falling Ol falling 10 pri 2 Il both 11 both 11 pri 3 7 10 2 Interrupt Vectors INTO EIR Ox00 INT1 0 08 When it is desired to expand the number of interrupts for additional peripheral devices the user should use the interrupt routine to dispatch interrupts to other virtual interrupt rou tines Each additional interrupting device will have to signal the processor that it is requesting an interrupt A separate signal line is needed for each device so that the proces sor can determine which devices are requesting an interrupt The following code shows how the interrupt service routines can be written External interrupt Routine 0 programmed priority could be 3 int2 PUSH IP IPSET 1 Save interrupt priority set to priority really desired 1 insert body of interrupt routine here r OPP IP IPRES RET get back entry priority restore interrupted routine s priority return from interrupt 2 etc 100 Rabbit 3000 Microprocessor User s Manual 7 11 Bootstrap Operation The device provides the option of bootstrap from any of three sources from the Slave Port from Se
230. ernal interrupts take place on a transition of the input which is programmable for rising falling or both edges Each of the interrupt pins has its own catcher device that can be programmed separately to catch the edge transition and request the interrupt When the interrupt takes place both pulse catchers associated with that interrupt are auto matically reset If both edges are detected before the corresponding interrupt takes place because the triggering edges occur nearly simultaneously or because the interrupts are inhibited by the processor priority then there will be only one interrupt for the two edges detected The interrupt service routine can read the interrupt pins via Parallel Port E and determine which lines experienced a transition provided that the transitions are not too fast Interrupts can also be generated by setting up the matching port E bit as an output and toggling the bit External interrupts are cleared automatically during the processor Interrupt Acknowledge cycle The Interrupt Acknowledge cycle will always immediately follow an Instruction Fetch cycle This instruction byte is ignored and will be the first byte fetched upon returning from the interrupt Interrupt Acknowledge cycles are always followed by two memory writes to push the contents of the PC onto the stack Execution then begins at the appropriate interrupt vector location Chapter 7 Miscellaneous Functions 99 Table 7 16 Control Registers for Ext
231. ers 329 Table D 1 Rabbit 3000A Internal I O Registers continued Register Name Mnemonic I O Address R W Reset Memory Bank 0 Control Register MBOCR 0x0014 00001000 Memory Bank 1 Control Register MBICR 0x0015 w XXXXXXXX Memory Bank 2 Control Register MB2CR 0x0016 Memory Bank 3 Control Register MB3CR 0x0017 MMU Expanded Code Register MECR 0 0018 R W 00000000 Memory Timing Control Register MTCR 0x0019 w 00000000 Breakpoint Debug Control Register BDCR 0x001C 00000000 RAM Segment Register RAMSR 0x0448 w 00000000 Write Protect Control Register WPCR 0x0440 00000000 Stack Limit Control Register STKCR 0x0444 w 00000000 Stack Low Limit Register STKLLR 0x0445 Stack High Limit Register STKHLR 0x0446 w XXXXXXXX Write Protect Low Register WPLR 0x0460 w 00000000 Write Protect High Register WPHR 0x0461 00000000 Write Protect Segment A Register WPSAR 0x0480 w 00000000 Write Protect Segment A Low Register WPSALR 0x0481 00000000 Write Protect Segment A High Register WPSAHR 0x0482 00000000 Write Protect Segment B Register WPSBR 0x0484 w 00000000 Write Protect Segment B Low Register WPSBLR 0x0485 00000000 Write Protect Segment B High Register WPSBHR 0x0486 00000000 Real Time Clock User Enable Register RTUER 0x0300 00000000 Slave Port User Enable R
232. ers to transfer two bytes on each interrupt thus nearly halving the overhead If a rendezvous is arranged between the processors data can be transferred at approximately 25 clocks per byte Each side polls the status register waiting for the other side to read write a data register which is then written read again by the other side 4 4 1 Slave Rabbit As A Protocol UART A prime application for the Rabbit used as a slave is to create a 4 port UART that can also handle the details of a communication protocol The master sends and receives messages over the slave port Error correction retransmission etc can be handled by the slave 54 Rabbit 3000 Microprocessor User s Manual 5 PIN ASSIGNMENTS AND FUNCTIONS Chapter 5 Pin Assignments and Functions 55 5 1 LQFP Package 5 1 1 Pinout Rabbit 3000 AT56C55 ILIT IL2T 128 pin Low Profile Quad Flat Pack LQFP 14 x 14 Body 0 4 mm pitch LIN ALQO 044 9419 ldd ods ovd Las LAI zal gas vas sas svd 9as 9Vd 106 Vd OISSA LVIVIX ZVIVLX 85112 oad Lad YMS OVI Zad Qus LYI edd 0VS vad LVS Sad 99 N LLV3AV IS SVI 184 HLGOV vid VLQOV 93 94d VZQOV
233. erted carry C is set if A lt B if the oper ation or virtual operation is A B Carry is cleared if A gt B SUB outputs carry in opposite sense from SBC and CP 19 11 8 bit Bit Set Reset and Test Instruction BIT b HL BIT b IX d BIT b IX d BIT b r RES b HL RES b IX d RES b IY d RES b r SET b HL SET b IX d SET b IY d SET b r 19 12 8 bit Increment and Instruction DEC HL DEC IX4d DEC IY d DEC r INC HL INC IX4d INC IY d INC r clk 7 10 10 4 10 13 13 4 10 13 13 4 clk 8 12 12 2 8 12 12 2 Fh Fh Fh h Fh Fh Fh Fh Fh fr m m m H a CoO OH oo NH Operation HL amp bit IX d amp bit IY d amp bit amp bit HL IX d IY d rer amp bit HL HL bit IX d IX d I d IV4d bit N HL amp bit IX d amp IY d amp r Decrement C Operation HL HL 1 IX d IX d IY d IY d ous p 2 HL HL 1 IX d IX d 1 IY d IY d 1 r 1 1 1 EN lt lt lt lt lt lt r bit bit bit bit 256 Rabbit 3000 Microprocessor User s Manual 19 13 8 bit Fast A Register Operations Instruction ISZVC CPL 2 r NEG 4 fr k V RLA 2 fr RLCA 2 fr RRA 2 fr RRCA 2 fr 19 14 8 bit
234. es depending on whether 7 or 8 bits are transmitted and on whether the 9th 8th bit is sent 12 9 5 Extra Stop Bits Sending Parity 9th Bit Communication Schemes Some systems may require two stop bits In some cases it may be necessary to send a par ity bit Certain systems such as some 8051 based multidrop communications systems use a 9th data bit to mark the start of a message frame The Rabbit 3000 can receive parity or message formats that contain a 9th bit without problem Transmitting messages with parity or messages that always contain a 9th bit is also possible It is quite easy to do so for byte formats that use only 7 data bits in which case the 9th bit or parity bit is actually an 8th bit Sending a 9th low bit is supported by hardware Sending a 9th bit as a high value requires a write to the Serial Port A F Long Stop Register SxLR which is the same as two stop bits 194 Rabbit 3000 Microprocessor User s Manual Figure 12 9 illustrates the standard asynchronous serial output patterns Stop Bit Start Bit Data Bits 9th bit low Character with 9th bit low Stop Bit 0 7 Start Bit Character w o 9th bit low Stop Bit 0 7 Character 9th bit high Start Bit 5 9th bit high Generated by a Write to SxLR Signal shown at output pin on processor A 1 is high Figure 12 9 Asynchronous Serial
235. es which are critically important for establishing memory access time requirements the capacitive loading is usually in the range of 25 100 pF and the load is due to the input capacitance of the mem ory devices and PC trace capacitance Delays are expressed from the waveform midpoint in keeping with the convention used by memory manufacturers Chapter 16 AC Timing Specifications 217 Figure 16 1 illustrates the parameters used to describe memory access time L Capacitive r loading Figure 16 1 Parameters Used to Describe Memory Access Time Table 16 2 lists the delays in gross memory access time for several values of Vpp Table 16 2 Data and Clock Delays Vpp 10 Temp 40 C 85 C maximum Clock to Address Output Delay Specirum Spreader Delay ns Data Setup ns VDD Time Delay N E orma ron 30pF 60pF 90pF ns 5 no dbl dbl dbl dbl 3 3 6 8 11 1 3 4 5 4 5 9 2 7 7 10 13 1 5 3 5 5 5 5 5 11 2 5 8 11 15 1 5 4 6 6 12 1 8 18 24 33 3 8 12 11 22 When the spectrum spreader is enabled with the clock doubler every other clock cycle is shortened sometimes lengthened bv a maximum amount given in the table above The shortening takes place bv shortening the high part of the clock If the doubler is not enabled then everv clock is shortened during the low part of the clock period The maxi mum shortening for a pair of clocks combined is shown in the table
236. es in one of three modes or can be disabled The counter is never automatically reset but must be reset by a software command Although 1t does not generate an interrupt there is a status bit which is set when the counter over flows counts from OxFFFF to 0x0000 so that software can recognize this condition To prevent potential stale data problems whenever the LSB of the latched count is read from the ICLxR the corresponding MSB of the latched count is transferred to a holding register until read from the ICMxR In the first mode the counter starts counting at the Start condition and stops counting at the Stop condition This mode is useful for pulse width measurement if the Start condition and Stop condition are assigned to the same pin The Input Capture inputs were chosen to take maximum advantage of this mode to allow baud rate detection for the serial ports and rotational speed measurement for the Quadrature Decoder channels Using this mode with different inputs for the Start and Stop condition allows time delay measurements between two signals This is the mode to use for high speed pulse measurement because only one count latch is available and it may be overwritten if the processor is not able to read the latched value quickly enough When the counter starts from a known count only the stop count is necessary to determine the pulse width In the second mode the counter runs continuously and the Start and Stop conditions merely latch t
237. esign the same address and data lines are used for both mem ory and I O spaces Sharing address and data lines in this manner often forces compromises or makes design more complicated Generally the memory bus has more critical timing and less tolerant of additional capacitive loading imposed by sharing it with an I O bus With the Rabbit 3000 the designer has the option of enabling completely separate buses for I O and memory The auxiliary I O bus uses many of the same pins used by the slave port so its operation is mutually exclusive from operation of the slave port Parallel Port A is used to provide 8 bidirectional data lines Parallel Port B bits 2 7 provide 6 address lines the least significant 6 lines of the 16 lines that define the full I O space The auxil iary bus is only active on I O bus cycles The address lines remain in the same state assumed at the end of the previous I O cycle until another I O cycle takes place I O chip selects as well as read and write strobes are available at various other pins so that the 64 byte space defined by the 6 address lines may be easily expanded I O cycles also execute in parallel on the main memory bus when they take place on the auxiliary bus so addi tional address lines can be buffered and provided if needed By connecting I O devices to the auxiliary bus the fast memory bus is relieved of the capacitive load that would otherwise slow the memory For core modules based on the Rabbit 3000 few
238. f HL gt 5 opportunity to jump on carry SUBC HL HL HL HL C if C on result is 1 else zero BOOL HL 22 clocks total true if HL gt 5 else false Figure 3 8 Mapping Signed Integers to Unsigned Integers by Inverting Bit 15 3 4 5 Atomic Moves from Memory to I O Space To avoid disabling interrupts while copying a shadow register to its target register it is desirable to have an atomic move from memory to I O space This can be done using LDD or LDI instructions LD HL sh PDDDR point to shadow register LD DE PDDDR set DE to point to I O reg SET 5 HL set bit 5 of shadow register use ldd instruction for atomic transfer IOI 14 io DE lt HL HL DE When the LDD instruction is prefixed with an I O prefix the destination becomes the I O address specified by DE The decrementing of HL and DE is a side effect If the repeating instructions LDIR and LDDR are used interrupts can take place between successive itera tions Word stores to I O space can be used to set two I O registers at adjacent addresses with a single noninterruptable instruction Chapter 3 Details on Rabbit Microprocessor Features 43 3 5 Interrupt Structure When an interrupt occurs on the Rabbit the return address is pushed on the stack and con trol is transferred to the address of the interrupt service routine The address of the inter rupt service routine has two parts the upper byte of the address comes from a spe
239. f PC 15 10 is equal to RAMSR 7 2 10 Select data type MMU translation if PC 15 11 is equal to RAMSR 7 3 11 Select data type MMU translation if PC 15 12 is equal to RAMSR 7 4 Appendix B Rabbit 3000 Revisions 293 B 1 8 Secondary Watchdog Timer The secondary watchdog timer SWDT is an eight bit modulo n 1 counter clocked by the 32 768 kHz clock The timer is off by default and is enabled by writing a Ox5F to the WDTCR The secondary watchdog timer register SWDTR holds the time constant value Depending on the value loaded into the SWDTR the timer can request an interrupt anywhere from 30 5 us to 7 8 ms If a 0x5F is written to the WDTCR prior to end of the countdown period the timer will not request an interrupt If the counter counts down to zero a level 3 interrupt is generated The SWDT is intended as a safety net for the peri odic interrupt and would normally be restarted in the service routine for the periodic inter rupt Although the hardware was intended to primarily be used by an operating system when the System User mode is enabled it can be used as a configurable periodic interrupt as well Table B 16 Watchdog Timer Control Register Updated Watchdog Timer Control Register WDTCR Address 0x0008 Bit s Value Description 7 0 Ox5A Restart the watchdog timer with a 2 second time out period 0x57 Restart the watchdog timer with a l second time out period 0 59 Restart the watchd
240. f program space The register SP points to the stack that is used for subroutine and interrupt linkage as well as general purpose storage A feature of the Rabbit and the Z80 Z180 is the alternate register set Two special instructions swap the alternate registers with the regular registers The instruction EX AF AF exchanges the contents of AF with The instruction EXX exchanges HL DE and BC with and Communication between the regular and alternate register set in the original Z80 architecture was difficult because the exchange instructions provided the only means of communication between the regular and alternate register sets The Rabbit has new instructions that greatly improve communication between the regular and alter nate register set This effectively doubles the number of registers that are easily available for the programmer s use It is not intended that the alternate register set be used to pro vide a separate set of registers for an interrupt routine and Dynamic C does not support this usage because it uses both registers sets freely The IP register is the interrupt priority register It contains four 2 bit fields that hold a his tory of the processor s interrupt priority The Rabbit supports four levels of processor pri ority something that exists only in a very restricted form in the Z80 or Z180 22 Rabbit 3000 Microprocessor User s Manual 3 2 Memory Mapping Although the Rabbit m
241. following sequence LD xpc a JP HL In this case A has the new XPC and HL has the new PC This code should normally be executed in the root segment so as not to pull the memory out from under the JP HL instruction A call to a computed address can be performed by the following code A xpc IY address LD A newxpc LD IY newaddress LCALL DOCALL call utility routine in the root The DOCALL routine DOCALL LD xpc a SET xpc JP IY go to the routine 48 Rabbit 3000 Microprocessor User s Manual 4 RABBIT CAPABILITIES This chapter describes the various capabilities of the Rabbit that may not be obvious from the technical description 4 1 Precisely Timed Output Pulses The Rabbit can output precise pulses under software control The effect of interrupt latency is avoided because the interrupt always prepares a future pulse edge that is clocked into the output registers on the next clock This is shown in Figure 4 1 Timer Output Parallel Port Output Parallel Port Output Latency Interrupt routine sets up B edge aN Timer Output Setup Register Figure 4 1 Timed Output Pulses The timer output in Figure 4 1 is periodic As long as the interrupt routine can be com pleted during one timer period an arbitrary pattern of synchronous pulses can be output from the parallel port The interrupt latency depends on the priority of the interru
242. for accessing data at a computed address especially when the stack contains that data New instructions correct these problems Another problem with many 8 bit processors is their slow execution and a lack of number crunching ability Good floating point arithmetic is an important productivity feature in smaller systems It is easy to solve many programming problems if an adequate floating point capability is available The Rabbit s improved instruction set provides fast floating point and fast integer math capabilities The Rabbit supports four levels of interrupt priorities This is an important feature that allows the effective use of fast interrupt routines for real time tasks Chapter 2 Rabbit 3000 Design Features 9 2 1 The Rabbit 8 bit Processor vs Other Processors The Rabbit 3000 processor has been designed with the objective of creating practical sys tems to solve real world problems in an economical fashion A cursory comparison of the Rabbit 3000 compared to other processors with similar capabilities may miss certain Rab bit strong points The Rabbit is a processor that can be used to build a system in which EMI is nearly absent even at clock frequencies in excess of 40 MHz This is due to the split power supply the clock doubler the clock spectrum spreader and the PC board layout advice or processor core modules that we provide Low EMI is a huge timesaver for the designer pressed to meet schedules and pass government
243. fr s L0 AND HL DE 11011100 2 fr L0 AND IX DE 11011101 11011100 4 f L0 AND IY DE 11111101 11011100 4 f L0 AND n 11100110 n 4 fr L 0 AND r 10100 r 2 fr L0 BIT b HL 11001011 01 b 110 7 f s BIT b IX d 11011101 11001011 d 01 b 110 10 f BIT b I d 11111101 11001011 d 01 b 110 10 f BIT b r 11001011 01 4 f BOOL HL 11001100 2 fr 0 0 BOOL IX 11011101 11001100 4 f 00 BOOL IY 11111101 11001100 4 f 00 CALL mn 11001101 n m 12 CCF 00111111 2 CP HL 10111110 5 f CP IX d 11011101 10111110 d 9 f CP IY d 11111101 10111110 d 9 f CP n 11111110 n 4 f k k V CP r 10111 r 2 V CPL 00101111 2 r DEC HL 00110101 8 f b Vv DEC IX d 11011101 00110101 d 12 f b V DEC 11111101 00110101 d 12 f b V DEC IX 11011101 00101011 4 DEC IY 11111101 00101011 4 DEC r 00 r 101 2 fr vV DEC ss 00ss1011 2 r ss 00 BC 01 DE 10 HL 11 SP DJNZ j 00010000 1 2 5 r EX SP HL 11101101 01010100 15 r EX SP IX 11011101 11100011 15 EX SP IY 11111101 11100011 15 266 Rabbit 3000 Microprocessor User s Manual Instruction Byte 1 EX AF AF 00001000 EX DE HL 11101011 EX DE HL 11100011 EX DE HL 01110110 EX DE HL 01110110 EXX 11011001 INC HL 00110100 INC IX d 11011
244. g current gives a total current of 3 1 mA at 0 46 MHz In sleepy mode with a self timed chip select of 106 ns and a clock speed of 32 kHz the duty cycle will be 0 106 66 1 600 and the static current will be 3 5 600 6 u A If the clock is divided down by a factor of 2 then the static current is reduced to 3 HA The dynamic current will be 16 uA at 32 kHz 1000x0 5xf and 8 uA at 16 kHz 236 Rabbit 3000 Microprocessor User s Manual 16 9 Battery Backed Clock Current Consumption When using the suggested tiny logic oscillator the oscillator and clock consume current as shown in Figure 16 12 below Normally a resistor is placed in the battery circuit to limit the current to about 3 u A which results in a voltage setpoint of about 1 7 V When operat ing at 3 3 V in sleepy mode the current of the oscillator and the real time clock about 12 uA must be added Using the suggested tiny logic oscillator circuit the external 32 768 kHz oscillator con sumes the following current in uA where V is the operating voltage Iose HA 0 35 x V 0 31 x V Generally the oscillator will not start unless the voltage is about 1 4 V However the oscil lator will continue to run until the voltage drops to about 0 8 V If the oscillator stops the current draw is very much lower than when it is running Below about 1 4 V most of the current draw is used to charge and discharge the capacitive load The current consumed by the battery backed porti
245. gabyte space The 16 bit space is divided into four separate zones Each zone except the first or root zone has a segment register that is added to the 16 bit address within the zone to create a 20 bit address The segment register has eight bits and those eight bits are added to the upper four bits of the 16 bit address creating a 20 bit address Thus each separate zone in the 16 bit memory becomes a window to a segment of memory in the 20 bit address space The relative size of the four segments in the 16 bit space is controlled by the SEGSIZE register This is an 8 bit register that contains two 4 bit registers This controls the bound ary between the first and the second segment and the boundary between the second and the third segment The location of the two movable segment boundaries is determined by a 4 bit value that specifies the upper four bits of the address where the boundary is located These relationships are illustrated in Figure 3 3 Chapter 3 Details on Rabbit Microprocessor Features 23 XPC register STACKSEG register DATASEG register XPC Segment Stack Segment D Data Segment SEGSIZE Register Root Segment 16 bit address space 00000 20 bit address space Figure 3 3 Example of Memory Mapping Operation The names given to the segments in the figure are evocative of the common uses for each segment The root segment is mapped to th
246. gnals When the internal clock is selected in these serial ports the corresponding bit of Parallel Port F is set as an output The Parallel Port F registers and their functions are described in Table 9 14 and in Table 9 15 Table 9 13 Parallel Port F Registers Register Name Mnemonic I O address R W Reset Port F Data Register PFDR 0x38 R W XXXXXXXX Port F Control Register PFCR 0 3 xx00xx00 Port F Function Register PFFR 0x3D Port F Drive Control Register PFDCR 0x3E Port F Data Direction Register PFDDR 0x3F w 00000000 Table 9 14 Parallel Port F Register Functions Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REDE PF7 PF6 PF5 PF4 PF3 PF2 PFI PFO adr 0x038 PFFR W adr 0x03D pwm 3 pwm 2 1 pwm 0 x x sclk_c sclk_d PEDCR W out out out out out out out out dr 0x03E open open open open open open open open 2 drain drain drain drain drain drain drain drain PFDDR W dir dir dir dir dir dir dir dir adr OxO3F out out out out out out out out 140 Rabbit 3000 Microprocessor User s Manual Table 9 15 Parallel Port F Control Register adr 0x03C Bits 7 6 Bits 5 4 Bits 3 2 Bits 1 0 00 clock upper nibble on pclk 2 00 clock lower nibble on pclk 2 01 clock on timer A1 01 clock on timer Al e 10 clock on timer B1 10
247. gnals are square waves 90 degrees out of phase also called being in quadrature with each other By having quadrature signals the direction of rotation can be detected by noting which signal leads the other signal The Rabbit 3000 has two quadrature decoder units Each unit has two inputs the normal input and the 90 degree or quadrature input An 8 bit up down counter counts encoder steps in the forward and backward directions The count can be extended beyond eight bits by an interrupt that takes place each time the count overflows or underflows The external signals are synchronized with an internal clock provided by the output of Timer A10 2 2 11 Pulse Width Modulation Outputs The pulse width modulated output generates a train of pulses periodic on a 1024 pulse frame with a duty cycle that varies from 1 1024 to 1024 1024 There are 4 independent PWM units The units are driven by the output of Timer A9 which may be used to vary the Chapter 2 Rabbit 3000 Design Features 17 length of the pulses When the duty cycle is greater then 1 1024 the pulses are spread into groups distributed 256 counts apart in the 1024 frame The pulse width modulation outputs can be passed through a filter and used as a 10 bit D A converter The outputs can also be used to directly drive devices that have intrinsic filtering such as motors or solenoids 2 2 12 Spread Spectrum Clock The main system clock which is generated by the crystal oscillator or input from
248. gure B 14 Short Chip Select Timing CLK 4 Write Operation 308 Rabbit 3000 Microprocessor User s Manual oscillator divide by 2 mode Figure B 15 Short Chip Select Timing CLK 2 Write Operation Appendix B Rabbit 3000 Revisions 309 The timing diagrams below illustrate the actual timing for the 32KHz cases of write cycles In these cases the chip selects are active for one clock cycle before and one clock cycle after the trailing edge of the write signal Figure B 16 Short Chip Select Timing 2 kHz Write Operation Figure B 17 Short Chip Select Timing 4 kHz Write Operation 310 Rabbit 3000 Microprocessor User s Manual 8 kHz operation Figure B 18 Short Chip Select Timing 8 kHz Write Operation 16 kHz operation Figure B 19 Short Chip Select Timing 16 kHz Write Operation Appendix B Rabbit 3000 Revisions 311 32 kHz operation Figure B 20 Short Chip Select Timing 32 kHz Write Operation 312 Rabbit 3000 Microprocessor User s Manual B 1 13 Pulse Width Modulator Improvements Several new features have been added to the pulse width modulator First a new PWM interrupt can be set up to be requested on every PWM cycle every other cycle every fourth cycle or every eighth cycle The setup for this interrupt is done in the PWLOR and PWLIR registers listed in Table B 25 and Table B 26 Options are available to suppress the PWM
249. he CPU GCPU and the final register is reserved for revision identification GREV The Rabbit 3000 does not contain on chip SRAM or flash memories Table 7 1 Global ROM Configuration Register Global ROM Configuration Register GROM Address 0x2C Bit s Value Description 7 0 Program fetch as a function of the SMODE pins read only 1 Ignore the SMODE pins program fetch function 6 5 read These bits report the state of the SMODE pins 4 0 00000 ROM identifier for this version of the chip Table 7 2 Global RAM Configuration Register Global RAM Configuration Register GRAM Address 0x2D Bit s Value Description 7 0 Program fetch as a function of the SMODE pins read only 1 Ignore the SMODE pins program fetch function 6 5 read These bits report the state of the SMODE pins 4 0 00000 RAM identifier for this version of the chip Chapter 7 Miscellaneous Functions 79 Table 7 3 Global CPU Register Global CPU Register GCPU Address 0x2E Bit s Value Description 7 0 Program fetch as a function of the SMODE pins read only 1 Ignore the SMODE pins program fetch function 6 5 read These bits report the state of the SMODE pins 4 0 00001 CPU identifier for this version of the chip Table 7 4 Global Revision Register Global Revision Register GREV Address 0x2F Bit s Value Description 7 0 Prog
250. he GCSR is shown in Table B 23 for reference Table B 23 Global Control Status Register Global Control Status Register GCSR Address 0x00 Bit s Value Description 00 No reset or watchdog timer time out since the last read 01 The watchdog timer timed out These bits are cleared by a read of this 7 6 register rd only 10 This bit combination is not possible 11 Reset occurred These bits are cleared by a read of this register 0 No effect on the periodic interrupt This bit will always be read as zero 5 1 Force a periodic interrupt to be pending 4 2 XXX See table below for decode of this field 00 Periodic interrupts are disabled 01 Periodic interrupts use Interrupt Priority 1 1 0 10 Periodic interrupts use Interrupt Priority 2 11 Periodic interrupts use Interrupt Priority 3 Table B 24 Clock Select Field of GCSR Clock Select CPU Clock Peripheral Main Sa Bits 4 2 GCSR Clock Oscillator B GPSCR 000 osc 8 osc 8 on short CS option 001 osc 8 osc on short CS option 010 osc osc on none 011 osc 2 osc 2 on short CS option self timed option 100 32 kHz or fraction 32 kHz or fraction on short CS option self timed option 101 32kHzorfraction 32KHz or fraction off short CS option 110 osc 4 osc 4 on short CS option 111 osc 6 osc 6 on short CS option 300 Rabbit 3000 Microprocessor User s Manual B 1 12 2 S
251. he clock can be selected to be the output of Timer A1 BI B2 or the peripheral clock divided by 22 The timer signal can also cause an interrupt that can be used to set up the next bit to be output on the next timer pulse This feature can be used to generate precisely controlled pulses whose edges are positioned with high accuracy in time Applications include communications signaling pulse width modulation and driving stepper motors A separate pulse width modulation facility is also included in the Rabbit 3000 External Input O Filtered Input Peripheral Clock Figure 2 2 Digital Filtering Input Pins Input pins to the parallel ports are filtered by cascaded D flip flops as shown in Figure 2 2 This prevents pulses shorter then the peripheral clock from being recognized synchro nizes external pulses to the internal clock and avoids problems with meta stability tem porarily indeterminate logical conditions due to marginal set up time with respect to the clock Chapter 2 Rabbit 3000 Design Features 13 2 2 6 Slave Port The slave port is designed to allow the Rabbit to be a slave to another processor which could be another Rabbit The port is shared with Parallel Port A and is a bidirectional data port The master can read any of three registers selected via two select lines that form the register address and a read strobe that causes the register contents to be output by the p
252. he current count This mode is useful for time stamping the input conditions against the time reference of the counter If the time stamp feature is not needed this mode gives the Rabbit 3000 up to four more external interrupt inputs This mode works well for slower speed pulse measurement where the processor has enough time to read the count latched by the Start condition before the Stop condition occurs and latches a new count In the third mode the counter runs continuously until the Stop condition occurs This mode measures the time from the software defined counter start until the Stop condition occurs on an input Note that once the counter stops because of the Stop condition it will not resume counting until re enabled by software 106 Rabbit 3000 Microprocessor User s Manual Table 7 19 Input Capture Control Status Register Input Capture Control Status Register ICCSR Address 0x56 Bit s Value Description 7 2 These status bits but not the interrupt enable bits are cleared by the read of this read register as is the Input Capture Interrupt 7 0 The Input Capture 2 Start condition has not occurred read 1 The Input Capture 2 Start condition has occurred 7 0 The corresponding Input Capture 2 Start interrupt is disabled write 1 The corresponding Input Capture 2 Start interrupt is enabled 6 0 The Input Capture 2 Stop condition ha
253. he end of the flash memory Data variables are allocated to RAM working backwards in memory Allocation normally starts at 52K in the 64K D space and continues The 52K space must be shared with the root code and data and is allocated upward from zero Dynamic C also supports extended data constants These are mixed in with the extended code in flash 124 Rabbit 3000 Microprocessor User s Manual 8 7 Instruction and Data Space Support Instruction and Data space I and D space support is accomplished by optionally invert ing address lines A16 and or A19 when the processor accesses D space but not inverting those lines when the processor accesses I space The MMIDR register see Table 8 8 is used to control this inversion It is important to understand that the bit inversion of A16 and A19 associated with I and D space occurs before the upper 2 bits of the 20 bit address are used to determine the quadrant and thus the bank register that is going to control mem ory access This contrasts with the optional address bit inversion of A19 and A18 con trolled by the 4 memory bank control registers see Table 8 3 that takes place after the quadrant has been computed Table 8 8 Use of MMIDR Register to Control Inversion of Address Lines A16 and A19 Bits 7 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 000 1 force Invert A19 for 1 Invert A16 for I Invert A19 for l Invert A16 for CS1 data accesses in data data accesses in data accesses in
254. hen the short chip select option is enabled the chip select delays turning on until the end of the of the memory cycle when it turns on for the last 2 undivided clocks If the clock is divided by 6 the memory read cycle with no wait states would normally be 12 undivided clocks long With the short chip select the chip select is on for only 2 12 clocks for a memory duty cycle of 1 6 If wait states are added the duty cycle is reduced even more For example if there is one wait state and the clock is divided by 6 the memory bus cycle will be 18 undivided clocks long and the duty cycle will be 2 18 1 9 with the short chip select option enabled When the short chip select option is enabled the interrupt sequence will attempt to write the return address to the stack if an interrupt takes place immediately after an internal or an external I O instruction The chip select will be suppressed during the write cycle and the correct return address will not be stored on the stack This happens only when an inter rupt takes place immediately after an I O instruction when the short chip select option is enabled Therefore when using the short chip select option ensure that interrupts are dis abled during I O instructions or do not use short chip select Interrupts can be disabled for a single I O instruction as shown in the following example PUSH IP Save interrupt state IPSET 3 interrupts off IOE LD a hl typical I O instruction POP IP ree
255. his status bit is cleared by a read of this register 3 0 A3 interrupt disabled write 1 A3 interrupt enabled 2 0 A2 counter has not reached its terminal count read 1 A2 count done This status bit is cleared by a read of this register 2 0 A2 interrupt disabled write 1 A2 interrupt enabled 1 0 1 counter has not reached its terminal count read 1 1 count done This status bit is cleared by a read of this register 1 0 Al interrupt disabled write 1 A interrupt enabled 0 0 Disable Timer A main clock perclk 2 write only 1 Enable Timer A main clock perclk 2 Chapter 11 Timers 153 The control register TACR is laid out as shown in Table 11 4 Table 11 4 Timer A Control Register Timer A Control Register TACR Address 0 00 4 Bit s Value Description 0 Timer A7 clocked by the main Timer A clock i 1 Timer A7 clocked by the output of Timer 1 0 Timer A6 clocked by the main Timer A clock i 1 Timer A6 clocked by the output of Timer A1 0 Timer A5 clocked by the main Timer A clock 3 1 Timer A5 clocked by the output of Timer A1 0 Timer A4 clocked by the main Timer A clock i 1 Timer A4 clocked by the output of Timer 1 0 Timer A3 clocked by the main Timer A clock 1 Timer A3 clocked by the output of Timer A1 0 Timer A2 clocked by the main Timer A clock 1 Timer A2 clocked by the output of Timer 1 00 Timer A inte
256. hort Chip Select Timing When short chip selects are enabled for read cycles the chip select signals are active only for the last part of the bus cycle Wait states are inserted between T1 and T2 so this will have no effect on the duration of the chip select signals in this mode The timing diagrams below illustrate the actual timing for the different divided cases In these cases the chip selects are two clock cycles of the fast oscillator long T1 T2 oscillator clock para CSx OEx divide by 8 mode Figure B 3 Short Chip Select Timing CLK 8 Read Operation Appendix B Rabbit 3000 Revisions 301 T1 T2 oscillator clock v 21 00 DATA ea CSx OEx divide by 6 mode Figure B 4 Short Chip Select Timing CLK 6 Read Operation oscillator divide by 4 mode Figure B 5 Short Chip Select Timing CLK 4 Read Operation 302 Rabbit 3000 Microprocessor User s Manual oscillator divide by 2 mode Figure B 6 Short Chip Select Timing CLK 2 Read Operation Appendix B Rabbit 3000 Revisions 303 When operating from the 32 kHz oscillator the same options are available but the timing is somewhat different This is illustrated in the diagrams below for the four different cases In these case the chip selects are one clock cycle of the 32 kHz clock long 32 kHz clock ADDR DATA CSx OEx 2 kHz operati
257. ich causes this line to be driven by the serial port clock PB 1 reflects the input of the pin unless Serial Port A has its internal clock enabled e PBDR Parallel Port B data register Read Write e PBDDR Parallel Port B data direction register A 1 makes the corresponding pin an output This register is write only Chapter 9 Parallel Ports 131 9 3 Parallel Port C Parallel Port C shown in Table 9 6 has four inputs and four outputs The even numbered ports PCO PC2 PC4 and PC6 are outputs The odd numbered ports PC1 PC3 5 and PC7 are inputs When the data register is read bits 1 3 5 7 return the value of the volt age on the pin Bits 0 2 4 6 return the value of the signal driving the output buffers The signal driving the output buffers and the value of the output pin are normally the same Either the Port C data register is driving these pins or one of the serial port transmit lines is driving the pin The bits set in the PCFR Parallel Port C Function Register identify whether the data register or the serial port transmit lines were driving the pins Table 9 5 Parallel Port C Registers Register Name Mnemonic I O address R W Reset Port C Data Register PCDR 0x50 R W xOx1x1x1 Port C Function Register PCFR 0x55 w x0x0x0x0 Table 9 6 Parallel Port C Register Bit Functions Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PCDR r Echo Echo Echo Echo adr 0x050 P
258. ides a list of all the Rabbit 3000A internal I O registers Table D 1 Rabbit 3000A Internal I O Registers Register Name Mnemonic Address R W Reset Global Control Status Register GCSR 0x0000 R W 11000000 Real Time Clock Control Register RTCCR 0x0001 w 00000000 Real Time Clock Byte 0 Register RTCOR 0x0002 R W XXXXXXXX Real Time Clock Byte Register RTCIR 0x0003 R XXXXXXXX Real Time Clock Byte 2 Register RTC2R 0x0004 R XXXXXXXX Real Time Clock Byte 3 Register RTC3R 0x0005 R XXXXXXXX Real Time Clock Byte 4 Register RTC4R 0x0006 R XXXXXXXX Real Time Clock Byte 5 Register RTCSR 0x0007 R XXXXXXXX Watchdog Timer Control Register WDTCR 0x0008 W 00000000 Watchdog Timer Test Register WDTTR 0x0009 W 00000000 Global Clock Modulator 0 Register GCMOR 0x000A W 00000000 Global Clock Modulator 1 Register GCMIR 0x000B W 00000000 Secondary Watchdog Timer Register SWDTR 0 000 11111111 Global Power Save Control Register GPSCR 0x000D w 00000000 Global Output Control Register GOCR 0x000E 00000000 Global Clock Double Register GCDR 0x000F w 00000000 Global ROM Configuration Register GROM 0x002C R 0xx00000 Global RAM Configuration Register GRAM 0x002D R 0xx00000 Global CPU Configuration Register GCPU 0x002E R Oxx00001 Global Revision Register GREV 0 002 R Oxx00001 MMU Instruction Data Register MMIDR 0x0010 R W 00000000 Appendix D Rabbit 3000A Internal I O Regist
259. ies such as Cimentrics Technology The data bytes have an extra 9th bit appended where a parity bit would normally be placed Requests from the network master to one of its slaves consist of a frame of bytes the first byte has the 9th bit set to 1 as the signal is observed at the Tx pin of the processor and the following bytes have the 9th bit set to 0 The first byte is identified as the address byte which specifies the slave unit where the message is directed This enables a slave to find the start of a message which is the byte with the 9th bit set and to determine if the message is directed to it If the message is directed to a particular slave the slave will then read the characters in the rest of the mes sage otherwise the slave will continue to scan for a start of message character containing its address Normally the 9th bit is set to 1 only on the first byte of a request transmitted by the net work master The subsequent bytes and the slave replies have the 9th bit set to zero Since the majority of the traffic has a 9th bit set low it is only necessary to stretch the stop bit for the first bytes or address bytes This can be done without sacrificing performance by send ing a dummy character transmitter disconnected after the address byte Some microprocessor serial ports have a wake up mode of operation In this mode char acters without the 9th bit set to 1 are ignored and no interrupt is generated When the sta
260. igh stop bit This facility can be used to transmit 2 stop bits or a parity bit if desired The ability to directly transmit a high voltage level address bit was not included in the original revision of the Rabbit 2000 processor Serial Ports A B C and D can be operated in the clocked serial mode In this mode a clock line synchronously clocks the data in or out Either the Rabbit serial port or the remote device can supply the clock When the Rabbit provides the clock the baud rate can be up to one half of the system clock frequency When the clock is provided by another device the maximum data rate is the system clock divided by 6 because of the need to synchronize the externally supplied clock with the internal clock The clocked serial mode may be used to support SPI bus devices Serial Port A has special features It can be used to cold boot the system after reset Serial Port A is the normal port that is used for software development under Dynamic C All the serial ports have a special timing mode that supports infrared data communications standards 2 2 3 System Clock The main oscillator uses an external crystal with a frequency typically in the range from 1 8 MHz to 26 MHz The processor clock is derived from the oscillator output by either doubling the frequency using the frequency directly or dividing the frequency by 2 4 6 or 8 The processor clock can also be driven by the 32 768 kHz real time clock oscillator for very
261. imer value If no other interrupt is of the same or higher priority then the uncertainty in the position of the edge is reduced to the variable time of the interrupt latency or about one half the execution time of the longest instruc tion This uncertainty is approximately 10 clocks or 0 5 us for a 20 MHz clock This enables pulse width measurements for pulses of any length with a precision of about 1 us If multiple pulses need to be measured simultaneously then the precision will be reduced but this reduction can be minimized by careful programming 4 1 1 Pulse Width Modulation to Reduce Relay Power Typically relays need far less current to hold them closed than is needed to initially close them For example if the driver is switched to a 75 duty cycle using pulse width modu lation after the initial period when the relay armature is picked the holding current will be approximately 75 of the full duty cycle current and the power consumption will be about 56 as great 50 Rabbit 3000 Microprocessor User s Manual 4 2 Open Drain Outputs Used for Key Scan The Parallel Port D outputs can be individually programmed to be open drain This is use ful for scanning a switch matrix as shown in Figure 4 2 A row is driven low then the col umns are scanned for a low input line which indicates a key is closed This is repeated for each row The advantage of using open drain outputs is that if two keys in the same col umn are depressed the
262. ince the bootstrap is a one way communication After the reset ends and the boot strap mode begins TXA will be low reflecting its function as a parallel port output bit that is cleared by the reset This may be interpreted as a break signal by some serial communi cation devices TXA can be forced high by sending the triplet 0x80 0x50 0x40 which stores 0x40 in Parallel Port C An alternate approach is to send the triplet 0x80 0x55 0x40 which will enable the TXA output from bit 6 of Parallel Port C by writing to the Parallel Port C function register 0x55 NOTE Although the TXA signal is not needed during the first phase of the boot procedure sending the byte triplets two way communication is required once the cold loader has been loaded The transfer rate in any bootstrap operation must not be too fast for the processor to exe cute the instruction stream The Write Empty signal acts as an interlock when using the Slave Port for bootstrap operation because the next byte should not be written to the Slave Port until the Write Empty signal is active No such interlock exists for the clocked serial and asynchronous bootstrap operation In these cases remember that the processor clock starts out in divide by eight mode with four wait states and limit the transfer rate accord ingly In asynchronous mode at 2400 bps it takes about 4 ms to send each character so no problem is likely unless the system clock is extremely slow 102 Rab
263. independent of instruction data 5 1 Enable 16 19 inversion controlled by bits 0 3 for data accesses only This enables the instruction data split for the separate I and D space 0 Normal CS1 operation 4 Force CS1 always active This will not cause any conflicts as long as the 1 memory using CS1 does not also share an Output Enable or Write Enable with another memory 0 Normal operation 1 For a DATASEG access invert A19 before MBxCR bank select decision 0 Normal operation 1 For a DATASEG access invert A16 0 Normal operation 1 For root access invert A19 before MBxCR bank select decision 0 Normal operation 1 For root access invert A16 Appendix B Rabbit 3000 Revisions 297 B 1 11 External I O Improvements Three new features have been added to the external I O strobes the ability to invert the strobe signal the ability to shorten a read strobe by one clock and the ability to direct a strobe to either the alternate I O bus if enabled or the memory bus The new control bits for the external I O strobes are listed in Table B 21 NOTE Bits 1 0 were always written with zero in the original Rabbit 3000 chip Table B 21 I O Bank x Control Register 10 Bank x Control Register IBOCR Address 0x0080 IB1CR Address 0x0081 IB2CR Address 0x0082 IB3CR Address 0x0083 IB4CR Address 0x0084 IB5CR
264. ins with Parallel Port E If several lines are to share interrupts with the same port the individual interrupt requests would normally be or ed together so that any device can cause an interrupt If several devices are requesting an interrupt at the same time only one interrupt results because there will be only one transition of the interrupt request line To resolve the situation and make sure that the separate interrupt routines for the different devices are called a good method is to have a interrupt dispatcher in software that is aided by providing separate attention request lines for each device The attention request lines are basically the inter rupt request lines for the separate devices before they are or ed together The interrupt dis patcher calls the interrupt routines for all devices requesting interrupts in priority order so that all interrupts are serviced 3 5 3 Privileged Instructions Critical Sections and Semaphores Normally an interrupt happens at the end of the instruction currently executing However if the instruction executing is privileged the interrupt cannot take place at the end of the instruction and is deferred until a non privileged instruction is executed usually the next instruction Privileged instructions are provided as a handy way of making a certain oper ation atomic because there would be a software problem if an interrupt took place after the instruction Turning off the interrupts explicitly may be
265. iply instruction performs a signed multiply that generates a 32 bit signed result MUL signed multiply of BC and DE result in HL BC 1 byte 12 clocks If a 16 bit by 16 bit multiply with a 16 bit result is performed then only the low part of the 32 bit result BC is used This counter intuitively is the correct answer whether the terms are signed or unsigned integers The following method can be used to perform a 16 x 16 bit multiply of two unsigned integers and get an unsigned 32 bit result This uses the fact that if a negative number is multiplied the sign causes the other multiplier to be sub tracted from the product The method shown below adds double the number subtracted so that the effect is reversed and the sign bit is treated as a positive bit that causes an addition LD 1 LD HL BC save BC in HL LD DE n2 LD A b Save sign of BC MUL form product in HL BC OR A test sign of BC multiplier JR 1 if plus continue ADD HL DE adjust for negative sign in BC x1 RL DE test sign of DE JR 2 if not negative subtract other multiplier from HL EX DE HL ADD HL DE x2 final unsigned 32 bit result in HL BC This method can be modified to multiply a signed number by an unsigned number In that case only the unsigned number has to be tested to see if the sign is on and in that case the signed number is added to the upper part of the product The multiply instruction can also be used to perfor
266. is bit will cause an interrupt to be latched when it goes from busy to not busy status after the last character has been sent there are no more data in the transmitter data register 1 0 00 These bits are always zero in async mode 170 Rabbit 3000 Microprocessor User s Manual Table 12 12 Status Register Clocked Serial Ports A D only Serial Port x Status Register SASR Address 0xC3 SBSR Address 0xD3 SCSR Address 0xE3 SDSR Address 0xF3 Bit s Value Description Clocked serial mode only 0 The receive data register is empty 7 1 There is a byte in the receive buffer The serial port will request an interrupt while this bit is set The interrupt is cleared when the receive buffer is empty 6 0 This bit is always zero in clocked serial mode 0 The receive buffer was not overrun 5 1 The receive buffer was overrun This bit is cleared by reading the receive buffer 4 0 This bit is always zero in clocked serial mode 0 The transmit buffer is empty The transmit buffer is not empty The serial port will request an interrupt when 3 1 the transmitter takes a byte from the transmit buffer Transmit interrupts are cleared when the transmit buffer is written or any value which will be ignored is written to this register 0 The transmitter is idle 2 The transmitter is sending a byte An interrupt is generated when the transmitter 1 clears this bit which occurs onl
267. is cleared L V flag is affected Carry flag is affected Carry flag is not affected Carry flag is cleared Carry flag is set Chapter 21 Instructions in Alphabetical Order With Binary Encoding 263 The L V logical overflow flag serves a dual purpose L V is set to 1 for logical operations if any of the four most signif icant bits of the result are 1 and L V is reset to 0 if all four of the most significant bits of the result are 0 Symbols Rabbit Z180 Meaning Bit select 000 bit 0 001 bit 1 b b 010 bit 2 011 bit 3 100 bit 4 101 bit 5 110 bit 6 111 bit 7 Condition code select 00 NZ 01 Z 10 11 d d 7 bit signed displacement Expressed in two s complement dd ww Word register select destination 00 01 DE 10 HL 11 SP dd Word register select alternate 00 01 DE 10 HL e j 8 bit signed displacement added to PC Condition code select 000 NZ non zero 001 Z zero f f 010 NC non carry 011 C carry 100 LZ logical zero 101 LO logical one 110 P sign plus 111 2 M sign minus m m MSB of a 16 bit constant mn mn 16 bit constant n n 8 bit constant or LSB of a 16 bit constant Byte register select 000 B 001 2 C r g g 9 010 011 E 100 2 H 101 L IIl A ss ww Word register select source 00 BC
268. is provided to the receiver during the search operation Decoding Biphase Level data requires that the data be sampled at either the quarter or three quarter point in the bit cell The DPLL here uses the quarter point to sample the data Biphase Mark and Biphase space encoding are identical as far as the DPLL is concerned and are similar to Biphase Level The primary difference is the placement of the clock and data transitions With these encodings the clock transitions are at the bit cell boundary and the data transitions are at the center of the bit cell and the DPLL operation is adjusted accordingly Decoding Biphase Mark or Biphase Space encoding requires that the data be sampled by both edges of the recovered receive clock An optional IRDA Infrared Data Association compliant encode and decode function is available in both asynchronous mode and HDLC mode The encoder sends an active High pulse for a zero and no pulse for a one In the asynchronous 16x mode this pulse is 3 16ths of a bit cell wide while in the asynchronous 8x mode it is 1 8th of a bit cell wide In HDLC mode the pulse is 1 4th of a bit cell wide In all modes the decoder watches for active Low pulses which are stretched to one bit time wide to recreate the normal asyn chronous waveform for the receiver Enabling the IRDA compliant encode decode modi fies the transmitter in HDLC mode so that there are always two opening Flags transmitted Chapter 12 Rabbit Serial Ports
269. is typically reset and the error is logged An overview of this level of operation is shown in Figure C 2 System Mode User Mode Application Critical code interrupts Critical Interrupts Interrupts Figure C 2 System User Mode Setup for Memory Protection Only 326 Rabbit 3000 Microprocessor User s Manual C 4 2 Mixed System User Mode Operation This mode is similar to the previous mode but with some portions of the program written for the System mode for example peripheral interrupts where latency is critical By keeping the System mode code sections small potential system crashes are still mini mized An overview of this level of operation is shown in Figure C 3 System Mode User Mode Return from interrupts Application Critical code interrupts User defined interrupts Time critical interrupts Critical Interrupts Figure C 3 System User Mode Setup for Mixed Operation Appendix C System User Mode 327 C 4 3 Complete Operating System This section describes a full use of the System User mode separating all common functions into a System mode operating system while letting the application specific code run in the User mode By default the System mode handles all peripherals and inter rupts as well as high level interfaces such as a flash file system However the processor will be running the application code in the User mode most of the time The application code can request direct a
270. ision 0 Normal operation 1 For root access invert A16 See Table B 20 for information on bit 7 for Rabbit 3000A and later versions Chapter 8 Memory Interface and Mapping 121 122 Rabbit 3000 Microprocessor User s Manual Table 8 5 MMU Expanded Code Register MECR 0x018 MMU Expanded Code Register MECR Address 0x018 Bit s Value Description 7 3 These bits are ignored for write and return zeros when read Oxx Normal operation 100 For an XPC access use MBOCR independent of A19 A18 2 0 101 For an XPC access use MB1CR independent of A19 A18 110 For an XPC access use MB2CR independent of 19 18 111 For an XPC access use MB3CR independent of A19 A18 The Memory Timing Control Register MTCR enables the extended timing for the memory output enables and write enables See Figure 7 2 for details on how the timing of the mem ory read and write strobes is affected when using the early output enable and write enable options Figure 16 3 shows extended output enable and write enable timing diagrams Table 8 6 Memory Timing Control Register MTCR adr 0x019 Memory Timing Control Register MTCR Address 0x019 Bit s Value Description 7 4 XXXX These bits are reserved and should not be used 3 0 Normal timing for OE1B rising edge to rising edge one clock minimum 1 Extended timing for OE1B one half clock earlier than normal
271. itions This bug has been corrected in ver sions of the Rabbit chip designated 3000A and later See Appendix B for further details The bug is rooted in an incomplete address decode for the data output register for Parallel Port A This register responds to any of 16 addresses 30 to 3F hex When Parallel Port F was added the addresses 38 to 3F were used and the decode for Parallel Port A was not updated There are five registers in Parallel Port F at addresses in the range of 38 to 3F Writing to any of these registers will also cause a write to the Parallel Port A output register which is identical to the slave port number zero output register If Parallel Port A is used as in input register or if the auxiliary I O bus which uses the pins of Parallel Port A as a data bus is enabled then the spurious write has no effect on operation because the Parallel Port A out put register is not used However if Parallel Port A is used as an output or is used as the bidirectional bus of the slave port then writing to any of the Parallel Port F registers will cause a spurious write to the Parallel Port A register which will have a spurious effect on the operation of the Rabbit 3000 chip Chapter 9 Parallel Ports 141 The functionality of the Parallel Port F pins is not affected for pulse width modulation out puts and serial clock outputs except that the Parallel Port F function and direction regis ters should be set up before a conflicting functi
272. l is simpler and faster than if error correction needs to be taken into account 13 3 1 Slave Applications Motion Controller Many types of motion control require fast action may be com pute intensive or both Traditional servo system solutions may be overly expensive or not work very well because of system nonlinearities The basic communications model for a motion controller is for the master to send short messages positioning com mands to the slave The slave acknowledges execution of the commands and reports exception conditions e Communications Protocol Processor Communications protocols may be very com plex may require fast responses or may be compute intensive e Graphics Controller The Rabbit can be used to perform operations such as drawing geometric figures and generating characters e Digital Signal Processing Although the Rabbit is not a speciality digital signal pro cessor it has enough compute speed to handle some types of jobs that might otherwise require a speciality processor The slave processor can process data to perform pattern recognition or to extract a specific parameter from a data stream 13 3 2 Master Slave Messaging Protocol In this protocol the master sends messages to the slave and receives an acknowledgement message The protocol can be polled or interrupt driven Generally the master sends a message that has a message type code perhaps a byte count and the text of the message The slav
273. lave Port The slave port allows a Rabbit to act as a slave to another processor which can also be a Rabbit The slave has to have only a processor chip a RAM chip and clock and reset sig nals that can be supplied by the master The master can cold boot and download a program to the slave The master does not have to be a Rabbit processor but can be any type of pro cessor capable of reading and writing standard registers For a detailed description see Chapter 13 Rabbit Slave Port The slave processor s slave port is connected to the master processor s data bus Commu nication between the master and the slave takes place via three registers implemented in the Rabbit for each direction of communication for a total of six data registers In addi tion there is a slave port status register that can be read by either the master or the slave see Figure 13 1 Two slave address lines are used by the master to select the register to be read or written The registers that carry data from the master to the slave appear as write registers to the master and as read registers to the slave The registers that operate in the opposite direction appear as read registers to the master and as write registers to the slave These registers appear as read write registers on both sides but are not true read write reg isters since different data may be read from what is written The master provides the clock or strobe to store data in the three write register
274. ld boots the target and downloads the binary image of the BIOS the BIOS symbol table is retained to make its entry points and global data available to the user application Board specific drivers are compiled with the user s program after the BIOS is compiled 17 1 1 BIOS Services The BIOS includes support for the following services e System startup including setup of memory wait states and clock speed e Writing to flash Writes to the primary code memory require turning off interrupts for up to 20 ms or so To protect the System Identification Block see the Rabbit 3000 Designer s Handbook for more information on the System ID Block the flash driver will not write to that block A routine that can actually write this block is not included in the BIOS to make it hard to accidently corrupt this block e Run time exception handling and logging to handle fatal errors and watchdog time outs error logging not implemented in older versions e Debugging and PC target communication Chapter 17 Rabbit BIOS and Virtual Driver 239 17 1 2 BIOS Assumptions The BIOS makes certain assumptions concerning the physical configuration of the proces sor Processors are expected to have RAM connected to CS1 WEI and OE1 Flash is expected to be connected to 50 WEO and OEO See the Rabbit 3000 Designer s Handbook Memory Planning chapter if you want to design a board with RAM only The crystal frequency is expected to be n 1 8432 MHz
275. les are first transmitted to the target system Dynamic C will return the No Rabbit Processor Detected error message when there is a problem with detecting the Rabbit microprocessor The SMODE pins are pulled up by the 5 V 3 3 V supplied from the target system through the programming cable The SMODE pins should be pulled down to ground on the board with 5 kQ resistors when the interface is not in use The target board provides the 5 V or 3 3 V to the programming cable to power the RS 232 driver and receiver PROGRAMMING PORT PIN ASSIGNMENTS Rabbit LQFP pins are shown in parenthesis m TRACE E 3 0 elu 2 GND 450 kO Ee 3 CKLKA 117 ANAAV 4 5 VI 3 3 V EG EZ d 5 IRESET IV 9 e 6 TXA 67 a nC Programming Port 8 STATUS output 4 Pin Numbers 9 SMODEO 45 GND 10 SMODE1 44 AA Ax GND Figure A 1 Rabbit Programming Port Appendix A The Rabbit Programming Port 271 A 1 Use ot the Programming Port as a Diagnostic Setup Port The programming port which is already in place can serve as a convenient communica tions port for field setup diagnosis or other occasional communication need for example as a diagnostic port There are several ways that the port can be automatically integrated into the user s software scheme If the purpose of the port is simply to perform a setup function that is write setup informatio
276. low or sleepy mode The Rabbit 3000 auto matically disables periodic interrupts when the clock mode is switched to 32 kHz or one of the multiples of 32 kHz This means that the periodic interrupt hardware does not function when running at any of these 32 kHz clock speeds simply because there are not enough clock cycles available to service the interrupt Hence virtual watchdogs which depend on the periodic interrupt cannot be used in the sleepy mode The user must set up an endless loop to determine when to exit sleepy mode A routine updateTimers is provided to update the system timer variables by directly reading the real time clock and to hit the watchdog while in sleepy mode If the user s routine cannot get around the loop in the maximum watchdog timer time out time the user should put several calls to updateTimers in the loop The user should avoid indiscriminate direct access to the watchdog timer and real time clock The least significant bits of the real time clock cannot be read in ultra slow mode because they count fast compared to the instruction execution time To reduce bus activity and thus power consumption it is useful to multiply zero by zero This requires 12 clocks for one memory cycle and reduces power consumption Typ ically a number of mul instructions can be executed between each test of the condition being waited for Dynamic C libraries also provide functions to change clock speeds to enter and exit sleepy mod
277. low power operation in which case the main oscillator can be shut down under software control 2 2 4 32 768 kHz Oscillator Input The 32 768 kHz oscillator input is designed to accept a 32 768 kHz clock A suggested low power clock circuit using tiny logic parts is documented and low in cost The 32 768 kHz clock is used to drive a battery backable there is a separate power pin internal 48 bit counter that serves as a real time clock RTC The counter can be set and read by software and is intended for keeping the date and time There are enough bits to keep the date for more than 100 years The 32 768 kHz oscillator input is also used to drive the watchdog timer and to generate the baud clock for Serial Port A during the cold boot sequence 12 Rabbit 3000 Microprocessor User s Manual 2 2 5 Parallel I O There are 56 parallel input output lines divided among seven 8 bit ports designated A through G Most of the port lines have alternate functions such as serial data or chip select strobes Parallel Ports D E F and G have the capability of timer synchronized outputs The output registers are cascaded as shown in Figure 2 1 Load Data Output Port Load Clock jal Timer Clock Figure 2 1 Cascaded Output Registers for Parallel Ports D and E Stores to the port are loaded in the first level register That register in turn is transferred to the output register on a selected timer clock T
278. lse DE lt gt HL DE lt gt HL BC lt gt BC HL lt gt HL lt gt HL DE lt gt DE D EX DE HL D E C Nw EX DE HD EXX exchange HL HEL DE DE BC BC 19 8 Stack Manipulation Instructions Instruction clk A ISZV ADD SP d 4 f POP IP 7 POP IX 9 POP IY 9 POP zz 7 r PUSH IP 9 PUSH IX 12 PUSH IY 12 PUSH zz 10 19 9 16 bit Arithmetic and Logical Ops Instruction clk A ISZVC ADC HL ss 4 fr k V ADD HL ss 2 fr ADD IX xx 4 f Operation SP SP d d 0 to 255 IP SP SP SP 1 IXL SP IXH SP 1 SP SP 2 IYL SP SP 1 SP SP 2 zzl SP zzh SP 1 SP SP 2 zz BC DE HL AF SP 1 IP SP SP 1 SP 1 IXH SP 2 IXL SP SP 2 SP 1 IYH SP 2 IYL SP SP 2 SP 1 zzh SP 2 221 SP SP 2 zz BC DE HL AF Operation HL HL ss CF ss BC DE HL SP HL HL ss IX IX xx xx BC DE IX SP 254 Rabbit 3000 Microprocessor User s Manual ADD IY yy 4 ADD SP d AND HL DE AND IX DE AND IY DE BOOL HL N g PD BS BOOL IX BOOL IY DEC IX DEC IX DEC ss N A Gg a a INC IX INC IY INC ss 2 A A MUL 12 OR HL DE OR IX DE OR IY DE RL DE N A AN RR DE
279. ly set lower by the programmer The IP register serves as a 4 word stack of 2 bit words to save and restore interrupt priori ties It can be shifted right restoring the previous priority by a special instruction IPRES Since only the current processor priority and 3 previous priorities can be saved in the inter rupt register instructions are also provided to PUSH and POP IP using the regular stack A new priority can be pushed into the IP register with special instructions IPSET 0 IPSET 1 IPSET 2 IPSET 3 Table 3 1 Effect of Processor Priorities on Interrupts Processor ae Effect on Interrupts Priority 0 All interrupts priority 1 2 and 3 take place after execution of current non privileged instruction 1 Only interrupts of priority 2 and 3 take place 2 Only interrupts of priority 3 take place 3 All interrupt are suppressed except RST instruction Chapter 3 Details on Rabbit Microprocessor Features 45 3 5 2 Multiple External Interrupting Devices The Rabbit 3000 has two distinct external interrupt request lines If there are more than two external causes of interrupts then these lines must be shared between multiple devices The interrupt line is edge sensitive meaning that it requests an interrupt only when a rising or falling edge whichever is specified in the setup registers takes place The state of the interrupt line s can always be read by reading Parallel Port E since they share p
280. ly timed edges and pulses to be generated under com bined hardware and software control Pulse width modulation outputs are implemented in addition to the timer synchronization feature see below Four pulse width modulated PWM outputs are implemented by special hardware The repetition frequency and the duty cycle can be varied over a wide range The resolution of the duty cycle is 1 part in 1024 There are six serial ports All six serial ports can operate asynchronously in a variety of commonly used operating modes Four of the six ports designated A B C D support clocked serial communications suitable for interfacing with SPI devices and various similar devices such as A D converters and memories that use a clocked serial protocol Two of the ports E and F support HDLC SDLC synchronous communication These ports have a 4 byte FIFO and can operate at a high data rate Ports E and F also have a digital phase locked loop for clock recovery and support popular data encoding meth ods High data rates are supported by all six serial ports The asynchronous ports also support the 9th bit network scheme as well as infrared transmission using the IRDA pro tocol The IRDA protocol is also supported in SDLC format by the two ports that sup port SDLC A slave port allows the Rabbit to be used as an intelligent peripheral device slaved to a master processor The 8 bit slave port has six 8 bit registers 3 for each direction of communicatio
281. ly when the data register is read The byte in the receive buffer is an address or a byte with a framing error If an address bit is not expected If the data in the buffer is all zeros this may be a Break 0 The receive buffer was not overrun 5 This bit is set if the receiver is overrun This happens if the shift register and the data 1 register are full and a start bit is detected This bit is cleared when the receiver data register is read 4 0 This bit is always zero in async mode 0 The transmit buffer is empty Transmitter data buffer full This bit is set when the transmit data register is full that is a byte is written to the serial port data register It is cleared when a byte is 3 transferred to the transmitter shift register or FIFO or a write operation is 1 performed to the serial port status register This bit will request an interrupt on the transition from 1 to 0 if interrupts are enabled Transmit interrupts are cleared when the transmit buffer is written or any value which will be ignored is written to this register 0 The transmitter is idle Transmitter busy bit This bit is set if the transmitter shift register is busy sending data It is set on the falling edge of the start bit which is also the clock edge that 2 transfers data from the transmitter data register to the transmitter shift register 1 The transmitter busy bit is cleared at the end of the stop bit of the character sent Th
282. m left or right shifts A left shift of n positions can be accomplished by multiplying by the unsigned number 2 n This works for n 15 and it doesn t matter if the numbers are signed or unsigned In order to do a right shift by n 0 lt n lt 16 the number should be multiplied by the unsigned number 2 16 n and the upper part of the product taken If the number is signed then a signed by unsigned multiply must be performed If the number is unsigned or is to be treated as unsigned for a logical right shift then an unsigned by unsigned multiply must be per formed The problem can be simplified by excluding the case where the multiplier is 255T5 38 Rabbit 3000 Microprocessor User s Manual 3 3 8 Input Output Instructions The Rabbit uses an entirely different scheme for accessing input output devices Any memory access instruction may be prefixed by one of two prefixes one for internal I O space and one for external I O space When so prefixed the memory instruction is turned into an I O instruction that accesses that I O space at the I O address specified by the 16 bit memory address used For example IOI LD A 0x85 loads A register with contents of internal I O register at location 0x85 LD 0 4000 IOE LD HL IY 5 get word from external I O location 0x4005 By using the prefix approach all the 16 bit memory access instructions are available for reading and writing I O locations The memory mapping is bypass
283. me further low order bits can be ignored The RTC registers cannot be set by a write operation but they can be cleared and counted individually or by subset In this manner any register or the entire 48 bit counter can be set to any value with no more than 256 steps If the 32 kHz crystal is not installed and the input pin is grounded no counting will take place and the six registers can be used as a small battery backed memory Normally this would not be very productive since the cir cuitry needed to provide the power switchover could also be used to battery back a regular low power static RAM Chapter 7 Miscellaneous Functions 91 Table 7 10 Real Time Clock RTCxR Data Registers Real Time Clock x Holding Register RTC0R R W Address 0x02 RTC1R Address 0x03 RTC2R Address 0x04 RTC3R Address 0x05 RTC4R Address 0x06 RTC5R Address 0x07 Bit s Value Description 7 0 Read The current value of the 48 bit RTC holding register is returned Writing to the transfers the current count of the to six holding Write l registers while the RTC continues counting Table 7 11 Real Time Clock Control Register adr 0x01 Bit s Value Description 7 0 0x00 Writing a 0x00 to the RTCCR has no effect on the RTC counter However depending on what the previous command was writing a 0x00 may either 1 disable the byte increment functi
284. mended for use with Rabbit 3000A based systems Please refer to TN235 External 32 768 kHz Oscillator Circuits for more information on the circuit Rabbit 3000 chips identified by UL2T for the LQFP package and DZ2J for the TFBGA package are RoHS compliant The UL2T and DZ2J RoHS versions were introduced in mid 2007 and the IL2T and IZ2T non RoHS versions are no longer avaialble Appendix B Rabbit 3000 Revisions 277 B 1 Discussion of Fixes and Improvements Table B 1 lists the bug fixes improvements and additions for the various revisions of the Rabbit 3000 Table B 1 Summary of Rabbit 3000 Improvements and Fixes Rabbit Rabbit Description 3000 3000A ILIT IZ1T IL2T IZ2T ID Registers for version revision identification x x System User mode Memory protection scheme Stack protection RAM segment relocation Secondary watchdog timer Multiply add and multiply subtract Variants of block move opcodes 16 bit internal I O address space External I O interface enhancements Expanded low power capability PWM improvements Quadrature decoder improvements Integrated Schmitt trigger for 32 kHz oscillator input Alternate output port connection for numerous peripherals Port A decode bug fix LDIR LDDR with wait states bug fix Interrupt after I O with short CSx enabled bug fix W w w w X w XK Ir
285. ment The Rabbit 3000 has been designed in close cooperation with Z World Inc a long time manufacturer of low cost single board computers Z World and Rabbit Semiconductor products are supported by an innovative C language development system Dynamic C The Rabbit 3000 is easy to use Hardware and software interfaces are as uncluttered and are as foolproof as possible The Rabbit has outstanding computation speed for a micro processor with an 8 bit bus This is because the Z80 derived instruction set is very com pact and the timing of the memory interface allows higher clock speeds for a given memory speed Microprocessor hardware and software development is easy for Rabbit users In circuit emulators are not needed and will not be missed by the Rabbit developer Software devel opment is accomplished by connecting a simple interface cable from a PC serial port to the Rabbit based target system or by performing software development and debugging over a network or the Internet using interfaces and tools provided by Rabbit Semiconductor Chapter 1 Introduction 1 1 Features and Specifications Rabbit 3000 128 pin LQFP package Operating voltage 1 8 V to 3 6 V Clock speed to 54 MHz All specifications are given for both industrial and commercial temperature and voltage ranges Rabbit microprocessors are low cost Industrial specifications are for 3 3 V 10 and a temperature range from 40 C to 85 C Modified commercial specificati
286. mory mapped to the lower 512K and held in flash will be switched to RAM for D accesses By inverting A16 D accesses will be switched to an adjacent 64K page which would normally still be in the lower 512K memory or flash To see how this works consider that data are of two different types constants stored in flash memory and variables which must be stored in RAM Because there are two types of data it is desirable to divide the D space into two zones one for constants and one for variables as shown in Figure 8 5 In a combined I and D space model the root code segment holds both code and data constants in flash memory The data segment holds data variables in RAM In the separate I and D space model the root code segment and the data segment Chapter 8 Memory Interface and Mapping 125 are mapped into contiguous regions of memory to create a continuous root code segment starting at the bottom of physical memory in flash In the I space the division between the root segment and the data segment is irrelevant because the DATASEG register contains zero and the division between the segments defined by the lower 4 bits of the SEGSIZE register does not mark a division in physical memory for code space However if for D space accesses A16 is inverted for the root segment and A19 is inverted for the data seg ment then root segment data is mapped to the next 64k of flash and data segment data is mapped to a place in memory 512K higher in the RAM This
287. n Independent strobes and interrupts are used to control the slave port in both directions Only a Rabbit and a RAM chip are needed to construct a complete slave system if the clock and reset control are shared with the master processor There is an option to enable an auxiliary I O bus that is separate from the memory bus The auxiliary I O bus toggles only on I O instructions It reduces EMI and speeds the operation of the memory bus which only has to connect to memory chips when the auxiliary I O bus is used to connect I O devices This important feature makes memory design easy and allows a more relaxed approach to interfacing I O devices The built in battery backable time date clock uses an external 32 768 kHz crystal oscil lator The suggested model circuit for the external oscillator utilizes a single tiny logic active component The time date clock can be used to provide periodic interrupts every 488 us Typical battery current consumption is about 3 uA Numerous timers and counters can be used to generate interrupts baud rate clocks and timing for pulse generation Two input capture channels can be used to measure the width of pulses or to record the times at which a series of events take place Each capture channel has a 16 bit counter and can take input from one or two pins selected from any of 16 pins Two quadrature decoder units accept input from incremental optical shaft encoders These units can be used to track the moti
288. n be set to new values before or after both are clocked Chapter 11 Timers 155 11 2 Timer B Figure 11 1 shows a block diagram of Timer B The Timer B counter can be driven directly by perclk 2 by that clock divided by 8 or by the output of Timer 1 Timer B has a continuously running 10 bit counter The counter is compared against two match regis ters the BI match register and the B2 match register When the counter transitions to a value equal to a match register an internal pulse with a length of 1 peripheral clock is gen erated The match pulse can be used to cause interrupts and or clock the output registers of Parallel Ports D and E The match registers are loaded from the match preload registers that are written to by an instruction The data byte in the match preload register is advanced to the next match register when the match pulse is generated Every time a match condition occurs the processor sets an internal bit that marks the match value in TBLXR as invalid Reading TBCSR clears the interrupt condition TBLxR must be reloaded to re enable the interrupt TBMxR does not need to be reloaded every time If both match registers need to be changed the most significant byte needs to be changed first The I O registers for Timer B are listed in Table 11 6 Table 11 6 Timer B Registers Register Name Mnemonic 5 fii R W Reset Timer B Control Status Register TBCSR OxBO R W
289. n operating speed of 29 5 MHz a SST39LF512020 256K x 8 45 ns access time flash memory combined with any of several 55 ns low power SRAMs is assumed for cal culating the current consumption estimates below A crystal frequency of 3 6864 MHz is a good choice for a low power system consuming between 2 and 18 mA at 3 3 V as the clock frequency is throttled between 0 46 MHz and 7 37 MHz The required memory access time is about 250 ns however a faster memory may result in less power since a short chip select cycle can then be used A crystal frequency of 11 0592 MHz is a good choice for a medium power system con suming between 5 and 50 mA at 3 3 V as the clock frequency is throttled between 1 4 MHz and 22 MHz The required memory access time is 70 ns A crystal frequency of 14 7456 MHz is a good choice for a faster medium power system consuming between 6 and 65 mA at 3 3 V as the clock frequency is throttled between 1 8 and 29 5 MHz The required memory access time is 55 ns A maximum speed system that will require fast RAM for program and data can be con structed using a 25 8048 MHz crystal This system will consume between 12 and 112 mA at 3 3V as the clock speed is throttled between 3 and 51 6 MHz The required memory access time is about 20 ns Typical system current consumptions are shown in the graphs below These are for the processor and oscillator only and do not include current consumed by memory and other devices It is assumed tha
290. n sleepy mode power consumption consists of the processor core the external recom mended external tiny logic 32 kHz oscillator and the memory The oscillator consumes 17 uA at 3 3 V and this drops rapidly to about 2 at 1 8 V The processor core con sumes between 3 and 50 uA at 3 3 V as the frequency is throttled from 2 kHz to 32 kHz and about 40 as much at 1 8 V If the flash memory specified above is used for memory and a self timed 106 ns chip select is used then the memory will consume 22 uA at 32 MHz and 1 4 uA at 2 KHz In addition to these items a low power reset controller may consume about 8 and CMOS leakage may consume several u A increasing with higher temperatures The graph below shows current consumption including the tiny logic core but not including memory or the reset controller 80 70 60 e 1 8V 50 2 22 40 27v z 3 0V cw X 3 3V 20 i 0 E 2 048 4 096 8 192 16 384 32 768 Clock Frequency kHz Figure 16 11 Sleepy Mode Current Consumption Chapter 16 AC Timing Specifications 233 16 6 Current Consumption Mechanisms The following mechanisms contribute to the current consumption of the Rabbit 3000 while it is operating 1 A current proportional to voltage and clock frequency that results from the charging of internal and external capacitances At 3 3 V see 2 below approximately 57 of the current is due
291. n there are options to reduce the duty cycle of memories when running at low clock speeds by only enabling the chip select for a brief period long enough to complete a read This greatly reduces the power used by flash memory when operating at low clock speeds e The excellent floating point performance is due to a tightly coded library and powerful processing capability For example a 50 MHz clock takes 7 us for a floating add 7 us for a multiply and 20 us for a square root In comparison a 386EX processor running with an 8 bit bus at 25 MHz and using Borland C is about 20 times slower e There is a built in watchdog timer e The standard 10 pin programming port eliminates the need for in circuit emulators A very simple 10 pin connector can be used to download and debug software using Rabbit Semiconductor s Dynamic C and a simple connection to a PC serial port The incremental cost of the programming port is extremely small Figure 1 1 shows a block diagram of the Rabbit 4 Rabbit 3000 Microprocessor User s Manual RESOUT SMODE0 SMODE1 IWDTOUT Data Buffer External Interface D 7 0 Memory Management Control Clock Doubler Global Power Save amp Clock Distribution 1 1 Address Dom ewm Spectrum Spreader Fast 1 Oscillator Serial Port A Asynch Synch Serial Serial Asynch Bootstrap Asynch Serial IrDA IrDA Bootstrap Serial Ports B C D Asynch Synch Serial Serial Asynch Seri
292. n there will be a gap between bytes the length of which depends on the inter rupt latency For example if the baud rate is 400 000 bps then up to 50 000 bytes per sec ond could be transmitted or a byte every 20 us No data will be lost if the transmitter can Chapter 12 Rabbit Serial Ports 183 answer its interrupts within 20 us There will be no slow down if the receiver can answer its interrupt within 1 2 clock or 1 25 us If it can answer within 1 5 clocks or 2 75 us the data rate will slow to 44 444 bytes per second If it can answer in 2 5 clocks or 6 25 us the data rate slows to 40 000 bytes per second If it can answer in 3 5 clocks or 8 75 us the data rate will slow to 36 363 bytes per second and so forth If two way half duplex communication is desired the clock can be turned around so that the receiver always provides the clock This is slightly more complicated since the receiver cannot initiate a message If the receiver attempts to receive a character and the transmitter is not transmitting the last bit sent will be received for all eight bits 184 Rabbit 3000 Microprocessor User s Manual 12 7 Clocked Serial Timing 12 7 1 Clocked Serial Timing With Internal Clock For synchronous serial communication the serial clock can be generated either by the Rabbit or by an external device The timing diagram in Figure 12 6 below can be applied to both full duplex and half duplex clocked serial communication where the serial cl
293. n to flash memory then the controller can be reset through the programming port followed by a cold boot to start execution of a special pro gram dedicated to this functionality The standard programming cable connects the programming interface to a PC program ming port The RESET line can be asserted by manipulating DTR on the PC serial port and the STATUS line can be read by the PC as DSR on the serial port The PC can restart the target by pulsing reset and then after a short delay sending a special character string at 2400 bps To simply restart the BIOS the string 0x80 0x24 0x80 can be sent When the BIOS is started it can tell whether the PROG connector on the programming cable is con nected because the SMODEI 5 pins are sensed as high This will cause the BIOS to think that it should enter programming mode The Dynamic C programming mode then can have an escape message that will enable the diagnostic serial port function Another approach to enabling the diagnostic port is to poll the serial port periodically to see if communication needs to begin or to enable the port and wait for interrupts The SMODE pins can be used for signaling and can be detected by a poll However recall that the SMODE pins have a special function after reset and will inhibit normal reset behavior if not held low The pull up resistors on RXA and CLKA prevent spurious data reception that might take place if the pins floated If the clocked serial m
294. nable interrupts When the 32 768 kHz clock is used as the main processor clock sleepy mode the mem ory duty cycle can be reduced by enabling a self timed chip select mode When the 32 768 kHz clock is used the clock period is approximately 32 us and a normal memory read cycle without wait states will be approximately 64 us No more than a few hundred nanoseconds are needed to read the memory The main oscillator is normally shut down when operating at 32 kHz and no faster clock is available to time out a short chip select cycle To provide for a low memory duty cycle a chip select and memory read can take place under control of a delay timer that is on the chip The cycle starts at the start of the final 64 us clock of the memory cycle and can be set to enable chip select for a period in the range of 70 to 200 ns The data are clocked in early at the end of the delay driven cycle The chip select duty cycle is very small about 0 2 128 1 600 Chapter 7 Miscellaneous Functions 87 When operating in the 32 kHz mode it is also possible to further divide the clock to a fre quency as low as 2 kHz further reducing execution speed and current consumption Global Power Save Conirol Regisiter GPSCR Address 0x0D Bit s Value Description 000 Self timed chip selects are disabled 001 This bit combination is reserved and should not be used 01x This bit combination is reserved and sh
295. nal I O space The high bit of the address is set to specify the I O space and thus writes are limited to the first 32K of either space The cold boot is terminated by a store to an address in I O space which causes execution to begin at address zero Since any memory chip can be remapped to address zero by storing in the I O space RAM can be temporarily be mapped to zero to avoid having to deal with the more complicated write protocol of flash memory which is the usual default memory located at address zero The following are the advantages of the cold boot capability e Flash memory can be soldered to the microprocessor board and programmed via a serial port or a parallel port This avoids having to socket the part or program it with a BIOS or boot program before soldering e Complete reprogramming of the flash memory can be accomplished in the field This is particularly useful during software development when the development platform can perform a complete reload of software regardless of the state of the existing software in the processor The standard programming cable for Dynamic C allows the development platform to reset and cold boot the target a Rabbit based microprocessor board e If the Rabbit is used as a slave processor the master processor can cold boot it over via the slave port This means the slave can operate without any nonvolatile memory Only RAM is required 52 Rabbit 3000 Microprocessor User s Manual 4 4 The S
296. ne 7 Chapter 2 Rabbit 3000 Design Features 9 2 1 The Rabbit 8 bit Processor vs Other Processors nennen nennen 10 2 2 Overview of On Chip Peripherals and 11 2 21 5 V Tolerant Inputs uu a 11 222 Serial i ia eb 11 2 2 3 SISTEMI CLOCK 12 2 24 32 768 kHz Oscillator Input tito ettet e rH ij 12 2222 NaCAMom 13 ADO SLAVE 14 2 2 7 Auxillary VO BUS sermesi eo aE EER EE E EEEE E EE 15 2 28 E E E E E EE E E 15 22 9 Input Capture Channels todo tete ettet e esee ee tried SEEE ees 16 2 2 10 Quadrature Decoder eter postna b Save EJ So 17 2 2 11 Pulse Width Modulation Outputs sess entem nennen ens 17 22 12 Spread Spectrum Clock ii esterne rro eer Tecra 18 2 2 13 Separate Core and I O Power Pins 18 2 3 Design Standards ire retenti Het ERE FER EHE E PEN 18 2 3 Programming Port a ouch SEE 18 2 32 Standard BIOS Mmm 19 2 4 Dynamic C Support for the 19 Chapter 3 Details on Rabbit Microprocessor Features
297. ne half of the way through the stop bit Data bits are transferred on this same clock from the receive shift register to the receive data register The transmit interrupt request flip flop is set on the leading edge of the start bit for data register empty and at the trailing edge of the stop bit for shift register empty transmitter idle Unless the data register is empty on this trailing edge of the stop bit the transmitter does not become idle The transmitter becomes idle only if the data register is empty at the trailing edge of the stop bit The serial port interrupt vectors are shown in Table 6 1 Chapter 12 Rabbit Serial Ports 179 12 4 Transmit Serial Data Timing On transmit if the interrupts are enabled an interrupt is requested when the transmit regis ter becomes empty and in addition an interrupt occurs when the shift register and trans mit register both become empty that is when the transmitter becomes idle The shift register is empty when the last bit is shifted out When the transmit data register contains data and the shift register finishes sending data the data bits are clocked from the transmit register to the shift register and the shift register is never idle The interrupt request is cleared either by writing to the data register or by writing to the status register which does not affect the status register The data register normally is clocked into the shift register each time the shift register finishes sen
298. nnen 208 Table of Contents Chapter 14 Rabbit 3000 Clocks 211 1451 Low Power haqa el nee ep eg eee eee aede e 212 Chapter 15 EMI Control 213 15 1 Power Supply Connections and Board Layout 000 0 eee eese eene 214 15 2 Using the Clock Spectrum Spreader sse nenne nennen ens 214 Chapter 16 AC Timing Specifications 217 16 1 Memory Access T Ime siete L L 217 16 2 I O Access iE RO REED PAPER ERGO OO EDI eee 225 16 3 Further Discussion of Bus and Clock ene emen 227 16 4 Maximum Clock Speeds tete ee ptem eire o deines 229 16 5 Power and Current Consumption 231 16 6 Current Consumption Mechanisms esses ener nennen nennen ene 234 16 7 Sleepy Mode Current Consumption a enne 235 16 8 Memory Current Consumption sess ene enneneenren eren OE nennen treten retener ene 236 16 9 Batterv Backed Clock Current Consumption essent 237 16 10 Reduced Power External Main Oscillator nn ener nennen 238 Chapter 17 Rabbit BIOS and Virtual Driver 239 17 1 The BIOS oec niea nonet A IU d ERROR emis 239 17 11 BIOS Services ee ob ie eee AG
299. not attempt a design that uses the chip select or a memory address as a clock or state changing signal without taking this into con sideration 64 Rabbit 3000 Microprocessor User s Manual 5 5 Description of Pins with Alternate Functions Table 5 2 Pins With Alternate Functions Pin Name Output Function Input Function Input Capture Option PA 7 0 SLAVE D 7 0 ID 7 0 SLAVE D 7 0 ID 7 0 PB7 SLAVEATTN IA5 PB6 IA4 8 8 5 SD1 PB4 IA2 50 PB3 1 SRD PB2 SWR CLKA CLKA PBO CLKB CLKB PC7 n a RXA yes PC6 TXA n a 5 n a RXB yes PC4 TXB n a PC3 n a RXC yes PC2 TXC n a n a RXD yes PC0 TXD n a PD7 APWM3 ARXA yes PD6 ATXA PD5 APWM2 ARXB ves PD4 ATXB PD3 yes PD2 PDI yes PD0 PE7 17 5 5 slave chip select PE6 16 PES 15 INTIB PE4 14 INTOB PE3 13 PE2 12 INTIA PEO 10 INTOA Chapter 5 Pin Assignments and Functions 65 Table 5 2 Pins With Alternate Functions continued Pin Name Output Function Input Function Input Capture Option PF7 PWM3 AQD2A yes PF6 PWM2 AQD2B PF5 PWM1 AQDIA yes PF4 PWM0 AQDIB PF3 QD2A yes PF2 QD2B PFI CLKC QDIA CLKC yes PF0 CLKD QDIB CLKD PG7 APWMI RXE yes PG6 TXE PGS RCLKE RCLKE ARXE yes PG4 TCLKE TCLKE ARCLKE PG3 APWM0 RXF yes PG2 TXF PGI RCLKF
300. ocessor User s Manual The eight I O bank control registers determine the number of I O wait states applied to an external I O access within the zone controlled by each register even if the associated strobes are not enabled Note that the IORD and IOWR signals reflect these registers as well The control over the generation of wait states is independent of whether or not the associ ated strobe in Port E is enabled The upper 2 bits of each register determine the number of wait states The four choices are 1 3 7 or 15 wait states On reset the bits are cleared resulting in 15 wait states There is always at least one external I O wait state and thus the minimum external I O read cycle is three clocks long The inhibit write function applies to both the Port E write strobes and the IOWR signal These control bits have no effect on the internal I O space which does not have wait states associated with read or write access Internal I O read or write cycles are two clocks long The I O strobes greatly simplify the interfacing of external devices On reset the upper 5 bits of each register are cleared Parallel Port E will not output these signals unless the data direction register bits are set for the desired output positions In addition the Port E function register must be set to 1 for each position Each I O bank is selected by the three most significant bits of the 16 bit I O address Table 10 2 shows the relationship between th
301. ock is generated internally by the Rabbit Other SPI compatible clock modes supported by the Rabbit 3000 are shown in Figure 12 5 With an internal clock the maximum serial clock rate Is perc1k 2 CYCLE 1 2 3 4 5 6 7 8 CLKA TxA 5 Y BiT 1 BI 2 BI 4 BIT 5 X 6 MSB RxA LSB Y BIT 1 Y BIT2 Y BITS Y BITS Y BIT6 MSB wees E POPE Pd Figure 12 6 Full Duplex Clocked Serial Timing Diagram with Internal Clock Mode 00 12 7 2 Clocked Serial Timing with External Clock In a system where the Rabbit serial clock is generated by an external device the clock sig nal has to be synchronized with the internal peripheral clock perc1k before data can be transmitted or received by the Rabbit Depending on when the external serial clock is gen erated in relation to perc1k it may take anywhere from 2 to 3 clock cycles for the exter nal clock to be synchronized with the internal clock before any data can be transferred Figure 12 7 shows the timing relationship among 1 the external serial clock and data transmit peck 777 072 7 A SA 2 SN lc we CLKA ext TxA Figure 12 7 Synchronous Serial Data Transmit Timing with External Clock Mode 00 Chapter 12 Rabbit Serial Ports 185 Figure 12 8 shows the timing relationship among perc1k the external serial clock and data receive
302. ode is used the serial port can be driven by having two toggling lines that can be driven and one line that can be sensed This allows a conversation with a device that does not have an asynchronous serial port but that has two output signal lines and one input signal line The line TXA also called PC6 is zero after reset if cold boot mode is not enabled A pos sible way to detect the presence of a cable on the programming port is for the cable to con nect TXA to one of the SMODE pins and then test for the connection by raising PC6 and reading the SMODE pin after the cold boot mode has been disabled A 2 Alternate Programming Port The programming port uses Serial Port A If the user needs to use Serial Port A in an application an alternate method of programming is possible using the same 10 pin pro gramming port For his own application the user should use the alternate I O pins for port A that share pins with Parallel Port D The TXA and RXA pins on the 10 pin program ming port are then a parallel port output and parallel port input using pins 6 and 7 on Par allel Port C Using these two ports plus the STATUS pin as an output clock the user can create a synchronous clocked communication port using instructions to toggle the clock and data Another Rabbit based board can be used to translate the clocked serial signal to 272 Rabbit 3000 Microprocessor User s Manual an asynchronous signal suitable for the PC Since the target controls
303. odes is different depending on whether the mode is internal clock or external clock To transmit in internal clock mode the user must first load the data register which must be empty and then store the send code When the shift register finishes sending the cur rent character if any the data register will be loaded into the shift register and transmitted by an 8 clock burst One character can be in the process of transmitting while another character is waiting in the data register tagged with the send code The send code is effec tively double buffered To receive a character in internal clock mode the receive shift register should be idle The user then stores the receive code in the control register A burst of 8 clocks will be gener ated and the sender must detect the clocks and shift output data to the data line on the fall ing edge of each clock The receiver will sample the data on the rising edge of each clock for clock modes 00 and 01 or the falling edge for clock modes 10 and 11 The receive mode cannot double buffer characters when using the internal clock The shift register must be idle before another character receive can be initiated However the interrupt request and character ready takes place on the rising edge of the last clock pulse If the next receive code is stored before the natural location of the next falling edge another receive will be initiated without pausing the clock To do this the interrupt has to be ser vi
304. of I O wait states enabled The V flag is set when BC transitions from 1 to 0 If the V flag is not set another step is performed for the repeating versions of the instructions Interrupts can occur between dif ferent repeats but not within an iteration equivalent to LDD or LDI Return from the inter rupt is to the first byte of the instruction which is the I O prefix byte if there is one A new LDIR LDDR bug was discovered in September 2002 The problem has to do with wait states and the block move operations With this problem the first iteration of LDIR LDDR uses the correct number of wait states for both the read and the write How ever all subsequent iterations use the number of waits programmed for the memory located at the write address for both the read and the write cycles This becomes a problem when moving a block of data from a slow memory device requiring wait states to a fast memory device requiring no wait states With respect to external I O operations the LDIR or LDDR performs reads with zero wait states independent of the waits programmed for the I O for all but the first iteration The first iteration is correct This bug is automatically cor rected by Dynamic C and will be fixed in future generations of the chip 258 Rabbit 3000 Microprocessor User s Manual 19 17 Control Instructions Jumps and Calls Instruction CALL mn DJNZ 3 JP HL JP IX JP IY JP mn JP mn JR cc e JRe LCALL xpc mn LJP xpc mn
305. of wait states used in access to this quadrant Without wait states read requires 2 clocks and write requires 3 clocks The wait state adds to these numbers Wait states should only be used for memory data accesses RAM or data flash not for memory from which instructions are executed code memory Bits 5 4 These bits allow the upper address lines to be inverted This inversion occurs after the logic that selects the bank register so setting these lines has no effect on which bank register is used The inversion may be used to install a 1M memory chip in the space normally allocated to a 256K chip The larger memory can then be accessed as 4 pages of 256K each There is no effect outside the quadrant that the memory bank control register is controlling 120 Rabbit 3000 Microprocessor User s Manual Bit 3 Inhibits the write pulse to memory accessed in this quadrant Useful for protecting flash mem ory from an inadvertent write pulse which will not actually write to the flash because it is protected by lock codes but will temporarily disable the flash memory and crash the system if the memory is used for code Bit 2 Selects which set of the two lines OEx and WEx will be driven for memory accesses in this quadrant Bits 1 0 Determines which of the three chip select lines will be driven for memory accesses to this quadrant All bits of the control register are initialized to zero on reset 8 5 1 Optional A16 A19 Inversions
306. og timer with a 500 ms time out period 0x53 Restart the watchdog timer with a 250 ms time out period Ox5F Restart the secondary watchdog timer other No effect on watchdog timer or secondary watchdog timer Table B 17 Secondary Watchdog Timer Register Secondary Watchdog Timer Register SWDTR Address 0x000C Bit s Value Description The time constant for the secondary watchdog timer is stored This time constant will take effect the next time that the secondary watchdog counter counts down 7 0 to zero The timer counts modulo n 1 where n is the programmed time constant The secondary watchdog can be disabled by writing the sequence 0 5 0 52 0 44 to this register 294 Rabbit 3000 Microprocessor User s Manual B 1 9 New Opcodes Eight new opcodes were added to the Rabbit 3000A UMA and UMS allow multiply and add and multiply and subtract operations on large integers and were added to speed up common cryptographic math used in public key calculations The remaining six expand the block copy operations available especially to and from I O addresses internal and external These opcodes are listed in Table B 18 Table B 18 New Rabbit 3000 Opcodes Instruction Bytes Clks A I S Z V C Operation CY DE HL IX DE DE CY UMA 2 8 81 1 1 1 15 1 IX 1 IY 1 HL HL 1 repeat while 0 CY DE HL IX
307. ollows that bit The serial clock can be configured to be either 16x the data rate or 8x the data rate Serial Port Input Clock lt 8 clocks uw Stop Bit Sampling Start Bit Point Receiver Data Ready Bit Asynchronous Receive Transmitter Data Reg Full Asynchronous Transmit Figure 12 4 Serial Port Synchronization Chapter 12 Rabbit Serial Ports 181 12 6 Clocked Serial Ports Ports A D can operate in clocked mode The data line and clock line are driven as shown in Figure 12 4 The data and clock are provided as 8 bit bursts with the LSB shifted out and or received first By default the transmit shift register advances on the falling edge of the clock and the receiver samples the data on the rising edge of the clock The serial port can generate the clock or the clock can be provided externally The clock polarity is programmable in clocked serial mode according to Figure The clocked serial transfer may also be synchronized to the output of either of the match conditions in Timer B to give precisely timed transfers To enable the clocked serial mode a code must be in bits 3 2 of the control register enabling the clocked serial mode with either an internal clock or an external clock The transition between the external and the internal clock should be performed with care Normally a pullup resistor is needed on the clock line to prevent spurious clocks
308. om lower byte to higher byte Chapter 7 Miscellaneous Functions 107 Table 7 20 Input Capture Control Register Input Capture Control Register ICCR Address 0x57 Bit s Value Description 7 2 These bits are ignored 1 0 00 Input Capture interrupts are disabled 01 Input Capture interrupt use Interrupt Priority 1 10 Input Capture interrupt use Interrupt Priority 2 11 Input Capture interrupt use Interrupt Priority 3 Table 7 21 Input Capture Trigger x Register Input Capture Trigger x Register ICT1R Address 0x58 ICT2R Address 0x5C Bit s Value Description 7 6 00 Disable the counter 01 The counter runs from the Start condition until the Stop condition 10 The counter runs continuously 11 The counter runs continuously until the Stop condition 5 4 00 Disable the count latching function 01 Latch the count on the Stop condition only 10 Latch the count on the Start condition only 11 Latch the count on either the Start or Stop condition 3 2 00 Ignore the starting input 01 The Start condition is the rising edge of the starting input 10 The Start condition is the falling edge of the starting input 11 The Start condition is either edge of the starting input 1 0 00 Ignore the ending input 01 The Stop condition is the rising edge of the ending input 10 The Stop condition is the falling edge of the ending input 11
309. ome capture conditions that may be specified for 2 independent edge detectors The counter can also be cleared and started under software control and then have its value captured in response to an input If desired the capture counter can synchronized with Timer B outputs used to synchro nously load parallel port output registers This makes it possible to generate an output sig nal precisely synchronized with an input signal Usually it will be desired to synchronize one of the input capture counters with the Timer B counter The count offset can be mea sured by outputting a pulse at a precise time using Timer B to set the output time and cap turing the same pulse Once the phase relationship is known between the counters it is then possible to output pulses a precise time delay after an input pulse is captured provided that the time delay is great enough for the interrupt routine to processes the capture event and set up the output pulse synchronized by Timer B The minimum time delay needed is probably less than 10 microseconds if the software is done carefully the clock speed is rea sonably high 2 2 10 Quadrature Decoder Inputs A quadrature encoder is a common electromechanical device used to track the rotation of a shaft or in some cases to track the motion of a linear follower These devices are usually implemented by the use of a disk or a strip with alternate opaque and transparent bands that excite dual optical detectors The output si
310. on Figure B 7 Short Chip Select Timing 2 kHz Read Operation T1 T2 X w 21 00 4 kHz operation Figure B 8 Short Chip Select Timing 4 kHz Read Operation 304 Rabbit 3000 Microprocessor User s Manual 8 kHz operation Figure B 9 Short Chip Select Timing 8 kHz Read Operation 16 kHz operation Figure B 10 Short Chip Select Timing 16 kHz Read Operation Appendix B Rabbit 3000 Revisions 305 32 kHz operation Figure B 11 Short Chip Select Timing 32 kHz Read Operation 306 Rabbit 3000 Microprocessor User s Manual In the case of write cycles the chip select signals are active only around the trailing edge of the write signal Wait states are inserted between T1 and T2 and this will have no effect on the duration of the chip select signals in this mode The timing diagrams below illus trate the actual timing for the different divided cases In these cases the chip selects are active for two clock cycles before and two clock cycles after the trailing edge of the write signal divide by 8 nnde Figure B 12 Short Chip Select Timing CLK 8 Write Operation Appendix B Rabbit 3000 Revisions 307 TI TWA T2 oscillator LULU clock spor DATA CSx WEx divide by 6 mode Figure B 13 Short Chip Select Timing CLK 6 Write Operation oscillator divide by 4 mode Fi
311. on of a rotating shaft or similar device Chapter 1 Introduction e A built in clock doubler allows 1 frequency crystals to be used e The built in main clock oscillator uses an external crystal or a ceramic resonator Typical crystal or resonator frequencies are in the range of 1 8 MHz to 30 MHz Since precision timing is available from the separate 32 768 kHz oscillator a low cost ceramic resonator with 1 2 percent error is generally satisfactory The clock can be doubled or divided down to modify speed and power dynamically The I O clock which clocks the serial ports is divided separately so as not to affect baud rates and timers when the processor clock is divided or multiplied For ultra low power operation the processor clock can be driven from the separate 32 768 kHz oscillator and the main oscillator can be powered down This allows the processor to operate at approximately between 20 and 100 u A and still execute instructions at the rate of up to 10 000 instructions per second The 32 768 kHz clock can also be divided by 2 4 8 or 16 to reduce power This sleepy mode is a pow erful alternative to sleep modes of operation used by other processors e Processor current requirement is approximately 65 mA at 30 MHz and 3 3 V The cur rent is proportional to voltage and clock speed at 1 8 V and 3 84 MHz the current would be about 5 mA and at 1 MHz the current is reduced to about 1 mA e To allow extreme low power operatio
312. on of the Rabbit 3000 which is driven by the 32 768 kHz oscillator is given by Lap 0 91 2 104 144 The current is negligible for V lt 1 14 V a Total Battery Backed m Rabbit 3000 Real Time Clock e Tiny Logic 32 kHz Osc Current HA amp aUe Se uu subo gh uer 2 S MR Battery Backup Voltage V Figure 16 12 Current Consumption Real Time Clock and 32 kHz Oscillator Circuit Chapter 16 AC Timing Specifications 237 16 10 Reduced Power External Main Oscillator The circuit in Figure 16 13 can be used to generate the main clock using less power than with the built in oscillator buffer The power consumption is less because of the current limiting resistors that cannot be used with the built in buffer The 2 2 kQ series resistor must be reduced as the clock frequency increases as must be the current limiting resistors Optional current reducing resistors gt To Rabbit 3000 XTALA1 2 2 33 pF 3 3 V SN74HCT1G04DBVR L 3 68 MHz SQ VE 4 Figure 16 13 Reduced Power External Main Oscillator Table 16 8 lists results for the reduced power external oscillator with no current limiting resistors Table 16 8 Current Draw Using Reduced Power External Oscillator 0Q current limiting resistors Voltage Current incl built in buffer V mA 3
313. on of the clock the output clock will be asymmetric as shown in Figure 7 2 Oscillator Oscillator delayed and inverted Doubled clock Delay gt time Address CS Example Write Data out Cycle Write pulse Early write pulse 7 option Address CS X Example Read Cycle Output enb Early output enb option Data out from mem Figure 7 2 Effect of Clock Doubler The doubled clock low time is subject to wide 5096 variation since it depends on process parameters temperature and voltage The times given above are for a supply voltage of 3 3 V and a temperature of 25 C The doubled clock low time increases by 2096 when the voltage is reduced to 2 5 V and increases by about 4096 when the voltage is reduced fur ther to 2 0 V The values increase or decrease by 196 for each 5 C increase or decrease in temperature The doubled clock is created by xor ing the delayed and inverted clock with itself If the original clock does not have a 50 50 duty cycle then alternate clocks will have a slightly different length Since the duty cycle of the built in oscillator can be as asymmetric as 52 48 the clock generated by the clock doubler will exhibit up to a 4 84 Rabbit 3000 Microprocessor User s Manual variation in period on alternate clocks This does not affec
314. on on Parallel Port A is in use since writing to these registers also writes to the Parallel Port A output register 9 6 1 1 Summary Parallel Port A Parallel Port F e Parallel Inputs e Full Functionality e Parallel Outputs e Parallel Inputs PWM Serial Port Clocks e Slave Port e Parallel Inputs PWM Serial Port Clocks e Auxiliary I O Bus e Full Functionality e If you enable the auxiliary I O bus which uses Parallel Port A then the bug does not manifest itself and you can use the full functionality of Parallel Port F e If you use Parallel Port A as inputs then the bug does not manifest itself and the full functionality of Parallel Port F is available e If you use Parallel Port A as outputs then you cannot use Parallel Port F pins as outputs too except that you can use the PWM and clock outputs provided that you are aware that writing to the control registers of Parallel Port F will also write to the data output register of Parallel Port A A simple way to resolve this is to leave Parallel Port A as an input until you complete the setup of Parallel Port F and then switch Parallel Port A to be an output You can always use pins on Parallel Port F as inputs e If you enable the slave port then you cannot use Parallel Port F as parallel outputs but you can still use the other output functions of Parallel Port F following the precautions regarding setup described above The easiest approach to avoid any probl
315. on or 2 cancel the RTC reset command If the OxCO command is followed by a 0x00 command only the byte increment function will be disabled The RTC reset will still take place 0x40 Arm RTC for a reset with code 0x80 or reset and byte increment function with code 0x0C0 0x80 Resets all six bytes of the RTC counter to 0x00 if preceeded by arm command 0x40 0xCO Resets all six bytes of the RTC counter to 0x00 and enters byte increment mode precede this command with 0x40 arm command 7 6 01 This bit combination must be used with every byte increment write to increment clock s register corresponding to bit s set to 1 Example 01001101 increments registers 0 2 3 The byte increment mode must be enabled Storing 0x00 cancels the byte increment mode 5 0 No effect on the RTC counter Increment the corresponding byte of the RTC counter 92 Rabbit 3000 Microprocessor User s Manual 7 8 Watchdog Timer The watchdog timer is a 17 bit counter In normal operation it is driven by the 32 768 kHz clock When the watchdog timer reaches any of several values corresponding to a delay of from 0 25 to 2 seconds it times out When it times out it emits a l clock pulse from the watchdog output pin and it resets the processor via an internal circuit To prevent this tim eout the program must hit the watchdog timer before it times out The hit is accom plished by storing a
316. ons are for a voltage variation of 5 and a temperature range from 40 C to 70 C l megabvte code data space allows C programs with 50 000 lines of code The extended Z80 style instruction set is C friendly with short and fast opcodes for the most important C operations Four levels of interrupt priority make a fast interrupt response practical for critical applications The maximum time to the first instruction of an interrupt routine is about 0 5 us at a clock speed of 50 MHz Access to I O devices is accomplished by using memory access instructions with an I O prefix Access to I O devices is thus faster and easier compared to processors with a distinct and narrow I O instruction set As an option the auxiliary I O bus can be enabled to use separate pins for address and data allowing the I O bus to have a greater physical extent with less EMI and less conflict with the requirements of the fast mem ory bus Further described below Hardware design is simple Up to six static memory chips such as RAM and flash memory connect directly to the microprocessor with no glue logic A memory access time of 55 ns suffices to support up to a 30 MHz clock with no wait states with a 30 ns memory access time a clock speed of up to 50 MHz is possible with no wait states Most I O devices may be connected without glue logic The memory read cycle is two clocks long The write cycle is 3 clocks long A clean memory and I O cycle completely avoid the
317. ort These same registers can be written as I O registers by the Rabbit slave Three additional registers transmit data in the opposite direction They are written by the master by means of the two select lines and a write strobe Figure 2 3 shows the data paths in the slave port RABBIT 3000 Registers Master Processor Registers Slave Interface lt chi Registers Figure 2 3 Slave Port Data Paths The slave Rabbit can read the same registers as I O registers When incoming data bits are written into one of the registers status bits indicate which registers have been written and an optional interrupt can be programmed to take place when the write occurs When the slave writes to one of the registers carrying data bits outward an attention line is enabled so that the master can detect the data change and be interrupted if desired One line tells the master that the slave has read all the incoming data Another line tells the master that new outgoing data bits are available and have not yet been read by the master The slave port can be used to signal the master to perform tasks using a variety of communication protocols over the slave port 14 Rabbit 3000 Microprocessor User s Manual 2 2 7 Auxiliary 1 Bus The Rabbit 3000 instruction set supports memory access and I O access Memory access takes place in a 1 megabyte memory space I O access takes place in a 64K I O space In a traditional microprocessor d
318. ort output registers as well as cause an interrupt Timer B is convenient for creating an event at a precise time in the future under program control Figure 2 4 illustrates the Rabbit timers Chapter 2 Rabbit 3000 Design Features 15 Timer A System perclk i Ae Serial E Serial F perclk 2 Serial A Serial B Input Capture Serial C PWM Quadrature Decode Serial D Timer A1 perclk 2 c 10 bit counter erclk 8 compare B 55 10 bits gt Timer B1 match reg Timer B System 1 Synchronized match preload outputs match reg i match preload i Timer B2 Figure 2 4 Rabbit Timers A and B 2 2 9 Input Capture Channels The input capture channels are used to determine the time at which an event takes place An event is signaled by a rising or falling edge or optionally by either edge on one of 16 input pins that can be selected as input for either of the two channels A 16 bit counter is used to record the time at which the event takes place The counter is driven by the outp
319. ould be written with zeros 0 Disable stack limit checking 1 1 Enable stack limit checking Table B 13 Stack Low Limit Register Stack Low Limit Register STKLLR Address 0x0445 Bit s Value Description Lower limit for stack limit checking If a stack operation or stack relative 7 0 memory access is attempted at an address less than STKLLR 0x10 a stack limit violation interrupt is generated Table B 14 Stack High Limit Register Stack High Limit Register STKHLR Address 0x0446 Bit s Value Description Upper limit for stack limit checking If a stack operation or stack relative 7 0 memory access is attempted at an address greater than STKHLR OxOEF a stack limit violation interrupt is generated 292 Rabbit 3000 Microprocessor User s Manual B 1 7 RAM Segment Relocation Normally when instruction data separation is enabled instructions are stored in flash memory and data are stored in RAM memory This can present a problem for the Interrupt Service Routine area which often requires run time modification The RAM Segment Register RAMSR allows a 1 2 or 4 KB segment of the logical memory space to be mapped as data would be mapped even for program execution Table B 15 RAM Segment Register RAM Segment Register RAMSR Address 0x0448 Bit s Value Description 7 2 Compare value for RAM segment limit checking 1 0 00 Disable RAM segment limit checking 01 Select data type MMU translation i
320. ould not be used 43 5 100 296 ns self timed chip selects 192 ns best case 457 ns worst case 101 234 ns self timed chip selects 151 ns best case 360 ns worst case 110 171 ns self timed chip selects 111 ns best case 264 ns worst case 111 109 ns self timed chip selects 71 ns best case 168 ns worst case 0 Normal Chip Select operation 1 Short Chip Select timing when dividing main oscillator by 4 6 or 8 3 x This bit is reserved and should not be used 000 The 32 kHz clock divider is disabled 001 This bit combination is reserved and should not be used 01 This bit combination is reserved should not be used 2 0 100 32 kHz oscillator divided by two 16 384 kHz 101 32 kHz oscillator divided by four 8 192 kHz 110 32 kHz oscillator divided by eight 4 096 kHz 111 32 kHz oscillator divided by sixteen 2 048 kHz It is anticipated that these measures would reduce operating current consumption to as low as 20 uA plus some additional leakage that would be significant at high operating temperatures 88 Rabbit 3000 Microprocessor User s Manual MEMCSxB OxB Figure 7 4 Short Chip Select Memory Read lt T1 2 gt 32 kHz ADDR DATA X s ui MEMCSxB IN N 100 lt Figure 7 5 Self Timed Chip Select Memory Read Cycle Chapter 7 Miscellaneous Functions 89 7 6 Out
321. output for seven of eight three of four and one of two iterations of the PWM counter The one of eight option works nicely with R C servos which require a 1 ms to 2 ms pulse width and a 20 ms period This option gives the full resolution for the pulse width while still meeting the period requirements The one of four and one of two options can be used to create more virtual PWM channels using soft ware to multiplex the PWM outputs There is a separate option to only generate an inter rupt during the active iteration of the PWM count The timing is shown below wu _ K o Kt Ao Ao fos As As A7 1 8 output pi 1 4 output d 1 8 interrupt 1 4 interrupt 1 2 interrupt Figure 21 PWM Interrupt Output Timing Appendix B Rabbit 3000 Revisions 313 Table B 25 PWM LSB 0 Register PWM LSB 0 Register PWL0R Address 0x0088 Bit s Value Description 7 6 write The least significant two bits for the Pulse Width Modulator count are stored 5 4 00 Normal PWM operation 01 Suppress PWM output seven out of eight iterations of PWM counter 10 Suppress PWM output three out of four iterations of PWM counter 11 Suppress PWM output one out of two iterations of PWM counter 3 This bit is ignored and should be written with zero 2 1 00
322. possibility of bus fights Peripheral I O devices can usually be interfaced in a glueless fashion using the common IORD and IOWR strobes in addition to the user configurable IO strobes on Parallel Port E The Parallel Port E pins can be configured as I O read write read write or chip select when they are used as I O strobes EMI reduction features reduce EMI levels by as much as 25 dB compared to other sim ilar microprocessors Separate power pins for the on chip I O buffers prevent high fre quency noise generated in the processor core from propagating to the signal output pins A built in clock spectrum spreader reduces electromagnetic interference and facil itates passing EMI tests to prove compliance with government regulatory requirements As a consequence the designer of a Rabbit 3000 based system can be assured of pass ing FCC or CE EMI tests as long as minimal design precautions are followed The Rabbit may be cold booted via a serial port or the parallel access slave port This means that flash program memory may be soldered in unprogrammed and can be reprogrammed at any time without any assumption of an existing program or BIOS Rabbit 3000 Microprocessor User s Manual A Rabhbit that is slaved to a master processor can operate entirely with volatile RAM depending on the master for a cold program boot There are 56 parallel I O lines shared with serial ports Some I O lines are timer syn chronized which permits precise
323. pt and the amount of time that other interrupt routines of the same or higher priority inhibit interrupts The first instruc tion of the interrupt routine will start executing within 30 clocks of the interrupt request for the highest priority interrupt routine This includes 19 clocks for the longest instruction to complete execution and 10 clocks for the interrupt to execute Pushing registers requires 10 12 clocks per 16 bit register Popping registers requires 7 9 clocks Return from inter rupt requires 7 clocks If three registers are saved and restored and 20 instructions averag ing 5 clocks are executed an entire interrupt routine will require about 200 clocks or 10 us with a 20 MHz clock Given this timing the following capabilities become possible Chapter 4 Rabbit Capabilities 49 Pulse width modulated outputs The minimum pulse width is 10 us If the repetition rate is 10 ms then a new pulse with 1000 different widths can be generated at the rate of 100 times per second Asynchronous communications serial output Asynchronous output data can be gener ated with a new pulse every 10 us This corresponds to a baud rate of 100 000 bps Asynchronous communications serial input To capture asynchronous serial input the input must be polled faster than the baud rate a minimum of three times faster with five times being better If five times polling is used then asynchronous input at 20 000 bps could be received Generating pul
324. put Pins CLK STATUS WDTOUT BUFEN Certain output pins can have alternate assignments as specified in Table 7 9 Table 7 9 Global Output Control Register GOCR 0 0 Bit s Value Description 00 CLK pin is driven with peripheral clock 01 CLK pin is driven with peripheral clock divided by 2 sa 10 CLKpinislow 11 CLK pin is high 00 STATUS pin is active low during a first opcode byte fetch 01 STATUS pin is active low during an interrupt acknowledge 10 STATUS pin is low 11 STATUS pin is high 1 WDTOUTB pin is low 1 cycle minimum 2 cycles maximum of 32 kHz 0 WDTOUTB pin follows watchdog function 2 x This bit is ignored 00 BUFEN pin is active low during external I O cycles 01 BUFEN pin is active low during data memory accesses 10 BUFEN pin is low 11 BUFEN pin is high 90 Rabbit 3000 Microprocessor User s Manual 7 7 Time Date Clock Real Time Clock The time date clock RTC is a 48 bit ripple counter that is driven by the 32 768 kHz oscillator The RTC is a modified ripple counter composed of six separate 8 bit counters The carries are fed into all six 8 bit counters at the same time and then ripple for 8 bits The time for this ripple to take place is a few nanoseconds per bit and certainly should not should not exceed 200 ns for all 8 bits even when operating at low voltage The 48 bits are enough to count up 272 years at the 3
325. r any reason the master will sneak a peek at SPD0R by reading SPSR If the interrupt is caused by a receive character it will remove the character from SPD1R and read SPDOR to handshake with the slave If the master is interrupted for transmitter ready as determined by the sneak peek it will place the outgoing character in SPD1R and write a code to SPDOR indicating transmit and channel number This will cause the slave to be interrupted and the slave will take the character and handshake by reading SPDOR This handshake does not interrupt the master 210 Rabbit 3000 Microprocessor User s Manual 14 RABBIT 3000 CLocks The Rabbit 3000 normally uses two clocks the main clock and the 32 768 kHz clock The 32 768 kHz clock is needed for the battery backable clock the watchdog timer and the cold boot function The main oscillator provides the run time clock for the microproces sor Figure 14 1 shows the main oscillator circuit TN235 External 32 768 kHz Oscillator Circuits provides further information on the 32 768 kHz oscillator circuit and selecting the values of components to use in the oscillator circuit XTALB2 33 pr H XTALB1 Main Oscillator Circuit Figure 14 1 Rabbit 3000 Main Oscillator Circuit NOTE You may have to adjust resistors and capacitors for various frequencies and crystal load capacitances The 32 768 kHz oscillator is slow to start oscillating after power on For this reason a wait loop in the
326. r oscillator to use less expensive ceramic resonators rather than quartz crystals Ceramic resonators typically have an error of 5 parts in 1000 while crystals are much more accurate to a few seconds per day 246 Rabbit 3000 Microprocessor User s Manual Two library functions are provided to read and write the real time clock unsigned long int read rtc void read bits 15 46 rtc void write rtc unsigned long int time write bits 15 46 note bits 0 14 and bit 47 are zeroed However it is not intended that the real time clock be read and written frequently The procedure to read it is lengthy and has an uncertain execution time The procedure for writing the clock is even more complicated Instead Dynamic C software maintains a long variable SEC_TIMER in memory SEC_TIMER is synchronized with the real time clock when the Virtual Driver starts and updated every second by the periodic interrupt It may be read or written directly by the user s programs Since SEC_TIMER is driven by the same oscillator as the real time clock there is no relative gain or loss of time between the two A millisecond timer variable MS_ TIMER is also maintained by the Virtual Driver Two utility routines are provided that can be used to convert times between the traditional format 10 Jan 2000 17 34 12 and the seconds since l Jan 1980 format converts time structure to seconds unsigned long mktime struct tm timeptr seconds to structure
327. ram fetch as a function of the SMODE pins read only 1 Ignore the SMODE pins program fetch function 6 5 read These bits report the state of the SMODE pins 4 0 00000 Revision identifier for this version of the chip 7 2 Rabbit Oscillators and Clocks The Rabbit 3000 usually requires two separate clocks The main clock normally drives the processor core and most of the peripheral devices and the 32 768 kHz clock drives the battery backable time date clock and other circuitry Main Clock An oscillator buffer is built into the Rabbit 3000 that may be used to implement the main processor oscillator Figure 7 1 For lowest power an external oscillator may be substi tuted for the built in oscillator circuit An oscillator implemented using the built in buffer accepts crystals up to a frequency of 27 MHz first overtone crystals only This frequency may be then doubled by the clock doubler The component values shown in the figure for the oscillator circuits are subject to adjustment depending on the crystal used and the oper ating frequency The Rabbit 3000 has a spectrum spreader unit that modifies the clock by shortening and lengthening clock cycles The effect of this is to spread the spectral energy of the clock harmonics over a fairly wide range of frequencies This limits the peak energy of the har monics and reduces EMI that may interfere with other devices as well as reducing the readings in government mandated EMI tests The
328. re will not be a fight between a driver driving the line high and another driver driving it low Figure 4 2 Using Open Drain Outputs for Key Scan Chapter 4 Rabbit Capabilities 51 4 3 Cold Boot Most microprocessors start executing at a fixed address often address zero after a reset or power on condition The Rabbit has two mode pins SMODE0 SMODE1 see Figure 5 1 The logic state of these two pins determines the startup procedure after a reset If both pins are grounded then the Rabbit starts executing instructions at address zero On reset address zero is defined to be the start of the memory connected to the memory control lines CSO and OEO However three other startup modes are available These alternate methods all involve accepting a data stream via a communications port that is used to store a boot program in a RAM memory which in turn can be used to start any further second ary boot process such as downloading a program over the same communications port For a detailed description see Section 7 11 Bootstrap Operation Three communication channels may be used for the bootstrap either Serial Port A in asyn chronous mode at 2400 bps Serial Port A in synchronous mode with an external clock or the parallel slave port The cold boot protocol accepts groups of three bytes that define an address and a data byte Each triplet causes a write of the data byte to either memory or to inter
329. require two extra clocks because the op code has a 1 byte prefix 3 3 2 Load or Store Data from or to a Constant Address LD A mn loads 8 bits from address mn LD A mn not possible on Z180 LD mn A LD HL mn load 16 bits from the address specified by mn LD HL mn to alternate register not possible 2180 LD mn HL Similar 16 bit loads and stores exist for DE BC SP IX and IY It is possible to load data to the alternate registers but it is not possible to store the data in the alternate register directly to memory LD A mn allowed LD mn D not a legal instruction LD mn DE not a legal instruction Chapter 3 Details on Rabbit Microprocessor Features 33 3 3 3 Load or Store Data Using an Index Register An index register is a 16 bit register usually IX IX SP or HL that is used for the address of a byte or word to be fetched from or stored to memory Sometimes an 8 bit offset is added to the address either as a signed or unsigned number The 8 bit offset is a byte in the instruction word BC and DE can serve as index registers only for the special cases below LD LD LD LD LD LD A BC A BC BC A A DE A DE DE A Other 8 bit loads and stores are the following LD LD LD LD LD LD LD r HL HL HL r LD HL r r IX d r IX d IX d r IY d r r 7 r 7 7 is of 7 register
330. requires two clocks for each byte of the op code and for each data byte read Three clocks are needed for each data byte written One additional clock is required if a memory address needs to be computed or an index register is used for addressing Only a few instructions don t follow this pattern An example is mul a 16 x 16 bit signed two s complement multiply mul is a 1 byte op code but requires 12 clocks to execute Compared to the Z180 not only does the Rabbit require fewer clocks but in a typical situ ation it has a higher clock speed and its instructions are more powerful The most important instruction set improvements in the Rabbit over the Z180 are in the following areas e Fetching and storing data especially 16 bit words relative to the stack pointer or the index registers IX TY and HL e 16 bit arithmetic and logical operations including 16 bit and s or s shifts and 16 bit multiply e Communication between the regular and alternate registers and between the index reg isters and the regular registers is greatly facilitated by new instructions In the Z180 the alternate register set is difficult to use while in the Rabbit it is well integrated with the regular register set e Long calls long returns and long jumps facilitate the use of 1M of code space This removes the need in the Z180 to utilize inefficient memory banking schemes for larger programs that exceed 64K of code 32 Rabbit 3000 Microprocessor U
331. responding port pin is an output otherwise it is an input It is easy to imagine a situation where different parts of the application such as an inter rupt routine and a background routine need to be in charge of different bits in the PDDDR register The following code sets a bit in the shadow and then sets the I O register If an interrupt takes place between the set and the LDD and changes the shadow register and PDDDR the correct value will still be set in PDDDR Chapter 18 Other Rabbit Software 245 ld hl PDDDRShadow point to shadow register 14 de PDDDR set de to point to I O reg set 5 hi set bit 5 of shadow register use ldd instruction for atomic transfer ioi ldd io de lt hl side effect hl de In this case the 1dd instruction when used with an I O prefix provides a convenient data move from a memory location to an I O location Importantly the 144 instruction is an atomic operation so there is no danger that an interrupt routine could change the shadow register during the move to the PDDDR register 18 3 2 2 Non atomic Instructions If the following two instructions were used instead of the 1dd instruction ld a 1 ld PDDDR a output to PDDDR then an interrupt could take place after the first instruction change the shadow register and the PDDDR register and then after a return from the interrupt the second instruction would execute and store an obsolete copy of the shadow register in the
332. rial Port A in clocked serial mode or from Serial Port A in asynchronous mode This is controlled by the state of the SMODE pins after reset Bootstrap operation is disabled if SMODEI SMODEO 0 0 Bootstrap operation inhibits the normal fetch of code from memory and instead substi tutes the output of a small internal boot ROM for program fetches This bootstrap program reads groups of three bytes from the selected peripheral device The first byte is the most significant byte of a 16 bit address followed by the least significant byte of a 16 bit address followed by a byte of data The bootstrap program then writes the byte of data to the downloaded address and jumps back to the start of the bootstrap program The most significant bit of the address is used to determine the destination for the byte of data If this bit is zero the byte is written to the memory location addressed by the downloaded address If this bit is one the byte is written to the internal peripheral addressed by the downloaded address Note that all of the memory control signals continue to operate nor mally during bootstrap Execution of the bootstrap program automatically waits for data to become available from the selected peripheral and each byte transferred automatically resets the watchdog timer However the watchdog timer still operates and bytes must be transferred often enough to prevent the watchdog timer from timing out Bootstrap operation is terminated
333. rong spreading has a greater effect in reducing the peak spectral strength as shown in the figure below 15 dB i Strong Spreading 10 Normal Spreading 5 1 50 100 150 200 250 300 350 MHz Figure 7 3 Reduction in Peak Spectral Strength from Spectrum Spreader In the normal spectrum spreading mode the maximum shortening of the clock cycle is 3 nanoseconds at 3 3 V and 25 C In the strong spreading mode the maximum shortening of a clock cycle under the same conditions is 4 5 ns The reduction in peak spectral strength is roughly independent of the clock frequency Special precautions must be followed in setting the GCMOR and GCMIR registers see Section 15 2 Using the Clock Spectrum Spreader 86 Rabbit 3000 Microprocessor User s Manual 7 5 Chip Select Options for Low Power Some types of flash memory and RAM consume power whenever the chip select is enabled even if no signals are changing The chip select behavior of the Rabbit 3000 can be modified to reduce unnecessary power consumption when the Rabbit 3000 is running at a reduced clock speed The short chip select option can be enabled when the processor clock is divided by 4 6 or 8 so as to run at a lower speed The short chip select option is exercised with clock select bits 4 2 of the GCSR register as shown in Table 7 6 Whether the chip select is normal or short is then determined by whether bit 4 in the GPSCR register is 0 or 1 W
334. rrupts are disabled 01 Timer A interrupts use Interrupt Priority 1 m 10 Timer A interrupts use Interrupt Priority 2 11 Timer A interrupts use Interrupt Priority 3 The Timer A Prescale Register TAPR specifies the main clock for Timer A This will affect all of the timer A countdown timers By default Timer A is clocked by peripheral clock divided by two The prescale register TAPR is laid out as shown in Table 11 5 Table 11 5 Timer A Prescale Register Timer A Prescale Register TAPR Address 0x00A1 Bit s Value Description 7 1 These bits are ignored 0 The main clock for Timer A is the peripheral clock 1 The main clock for Timer A is the peripheral clock divided by two 154 Rabbit 3000 Microprocessor User s Manual The time constant register for each timer TATxR is simply an 8 bit data register holding a number between 0 and 255 This time constant will take effect the next time that the Timer A counter counts down to zero The timer counts modulo divide by n 1 where n is the programmed time constant The time constant registers are write only The time constant registers are listed in Table 11 1 11 1 2 Practical Use of Timer A Timer A is disabled bit 0 in control and status register on power up Timer A is normally set up while the clock is disabled but the timer setup can be changed while the timer is running when there is a need to do so Timers that are not use
335. rs The Rabbit s registers are nearly identical to those of the Z180 or the Z80 The figure below shows the register layout The XPC and IP registers are new The EIR register is the same as the Z80 I register and is used to point to a table of interrupt vectors for the exter nally generated interrupts The IIR register occupies the same logical position in the instruction set as the Z80 R register but its function is to point to an interrupt vector table for internally generated interrupts 8 16 bit registers XPC A H A 8 bit accumulator F flags register HL 16 bit accumulator IX TY index registers alt accum s Alternate Registers SP stack pointer PC program counter S Z x x x V x C XPC extension of program counter flag register layout IIR internal interrupt register S sign Z zero V overflow EIR external interrupt register Bits marked x are read write interrupt priority register D B Figure 3 1 Rabbit Registers Chapter 3 Details on Rabbit Microprocessor Features 21 The Rabbit and the Z80 Z180 processor has two accumulators the A register serves as an 8 bit accumulator for 8 bit operations such as ADD or AND The 16 bit register HL regis ter serves as an accumulator for 16
336. rt of a frame is detected an interrupt takes place on that byte If the byte contains the address of the slave then the wake up mode is turned off so that the remaining charac ters in the frame can be read This scheme reduces the overhead associated with messages directed to other slaves but it does not really help with the worst case load In most cases the worst case compute load is the governing factor for embedded systems In addition it is quite easy for the interrupt driver to dismiss characters not directed to the system For these reasons the wake up mode was not implemented for the Rabbit The 9th bit protocols suffer from a major problem that the IBM PC uarts can support the 9th bit only by using special drivers 12 9 9 Rabbit Only Master Slave Protocol If only Rabbit microprocessors are connected the 9th bit low can be set on the address byte and the remaining bytes can be transmitted in the normal 8 bit mode This is more efficient than other 9th bit protocols because only the first byte requires 11 baud times the remaining bytes are transmitted in 10 baud times 12 9 10 Data Framing Modbus Some protocols for example Modbus depend on a gap in the data frame to detect the beginning of the next frame The 9th bit protocol is another way to detect the start of a data frame The Modbus protocol requires that data frames begin with a minimum 3 5 character quiet time The receiver uses this 3 5 character gap to de
337. s H L same but alternate register destination r is any of the 7 registers above or an immediate data byte r is same r is not any but any IX or IY a legal instruction of 7 registers d is 128 to 127 offset alternate destination of 7 registers or an immediate data byte can have offset d The following are 16 bit indexed loads and stores None of these instructions exists on the Z180 780 The only source for a store is HL The only destination for a load is HL or HL LD LD LD LD LD LD LD LD LD LD LD HL SP d SPrd HL HL HL d HL HL d HL d HL IX d HL HL IX d HL IX d IY d HL HL IY d HL IY d r r r r r r d is an offset from 0 to 255 16 bits are fetched to HL or HL corresponding store d is an offset from 128 to 4127 uses original HL value for addressing 1 4 h HL d 1 store HL at address pointed to by IX plus 128 to 127 offset store HL at address pointed to by IY plus 128 to 127 offset 34 Rabbit 3000 Microprocessor User s Manual 3 3 4 Register to Register Move Any of the 8 bit registers A B D E H and L can be moved to any other 8 bit regis ter for example LD LD d b LD e 1 The alternate 8 bit registers can be a destination for example LD a c LD d b These instructions are unique to the Rabbit and require 2 bytes and four clocks be
338. s The on chip peripherals were chosen based on our experience as to what types of periph eral devices are most useful in small embedded systems The major on chip peripherals are the serial ports system clock time date oscillator parallel I O slave port motion encoders pulse width modulators pulse measurement and timers These and other fea tures are described below 2 2 1 5 V Tolerant Inputs The Rabbit 3000 operates on a voltage in the range of 1 8 V to 3 6 V but most Rabbit 3000 input pins are 5 V tolerant The exceptions are the power supply pins and the oscillator buffer pins When a 5 V signal is applied to 5 V tolerant pins they present a high impedance even if the Rabbit power is off The 5 V tolerant feature allows 5 V devices that have a suitable switching threshold to be directly connected to the Rabbit This includes HCT family parts operated at 5 V that have an input threshold between 0 8 and 2 V NOTE CMOS devices operated at 5 V that have a threshold at 2 5 V are not suitable for direct connection because the Rabbit outputs do not rise above VDD which cannot exceed 3 6 V and is often specified as 3 3 V Although a CMOS input with a 2 5 V threshold may switch at 3 3 V it will consume excessive current and switch slowly In order to translate between 5 V and 3 3 V HCT family parts powered from 5 V can be used and are often the best solution There is also the LVT family of parts that operate from 2 0 V to 3 3 V
339. s the receiver sets a status flag that is buffered along with this last byte Software can then use the table below to determine the number of valid data bits in this last byte Note that the receiver transfers all bits between the opening and closing Flags except for the inserted zeros to the receiver data buffer Last Byte Bit Pattern Valid Data Hits bbbbbbbO 7 bbbbbb01 6 bbbbb011 5 bbbb0111 4 50001111 3 05011111 2 50111111 1 Several types of data encoding are available in the HDLC mode In addition to the normal NRZ they are NRZI Biphase Level Manchester Biphase Space FM0 and Biphase Mark FM1 Examples of these encodings are shown in the Figure below Note that in NRZI Biphase Space and Biphase Mark the signal level does not convey information Rather it is the placement of the transitions that determine the data In Biphase Level it is the polarity of the transition that determines the data 188 Rabbit 3000 Microprocessor User s Manual Serial Clock l NRZ Data NRZI NRZI N N Biphase Level EA SEN NASN Z ey NS U Z i P VU uA NU UNO NOU AU AN7A
340. s Manual memory mapping segments 166 System User mode 321 sa 118 SBCR ehe 166 TACR 5 225 151 154 MMIDR 121 297 166 TACSR 151 152 MTER 123 321 SBER 166 167 TAPR ocn 151 154 PADR 2s 130 SBER seek 166 TATXR ui 151 parallel port alternate func SBSR ua enne 166 TBELR 505024 5 156 158 LODS iesus 67 SCAR sk au asas 166 TBCMR 156 PBDDR nn 131 SCCR ense 166 TBCR eene 156 157 PBDR ves 131 166 TBCSR 156 157 PEDR sesta 132 SEER nune 166 TBLXR iii 156 158 PGER ueste 132 166 156 158 PDBXR 133 SESR seasoned 166 WDTCR isise 93 294 PDCR 133 135 SDAR 167 WDTTIR 02202 94 PDDCR 133 SDCR A 167 286 PDDDR nce 133 167 WPHR ai S G saa Sia 287 PDDR sasa 133 135 SDLR eni 167 WPLR 22e 286 PDER 133 SDSR osse 167 288 PEBXxR oe 138 SEAR 167 525 289 138 139 SECR niei 167 WPxLR 288 138 167 XPC register 26 27 PEDR 138 139 SBEER 167 95 96 PEFR en 138 serial port address registers revision history 275 278 140 141 168 alternate output port
341. s are used as communication lines between the slave and the master The slave unit is a Rabbit configured as a slave The master can be another Rabbit or any other type of processor Rabbits configured as slaves can themselves have slaves The master and slave communicate with each other via the slave port The slave port is a physical device that includes data registers a data bus and various handshaking lines The slave port is a part of the slave Rabbit but logically it is an independent device that is used to communicate between the two processors Figure 13 1 shows a diagram of the slave port Figure 13 1 Rabbit Slave Port Chapter 13 Rabbit Slave Port 199 The slave port lines are shown in Figure 13 1 The function of these lines is described below e SDO SD7 These are bidirectional data lines and are generally connected to the data bus of the master processor Multiple slaves can be connected to the data bus The slave drives the data lines only when SCS and SRD are both pulled low e SAI SAO These are address lines used to select one of the four data registers of the slave interface Normally these lines are connected to the low order address lines of the master The master always drives these lines which are always inputs to the slave e SCS Input Slave chip select The slave ignores read or write requests unless the chip select is low If a Rabbit is used as a master this line can be connected to one of the ma
342. s available Interrupt Priority 3 not allowed IDET opcode causes Priority 3 system mode IDET opcode has no effect PA violation interrupt No write protection when 0x00 is written to Write to protected segment causes Priority 3 WPCR write protection in User mode only write protection violation interrupt Difficult to enter system mode requires Easy to enter user mode SETUSR opcode interrupt SYSCALL or RST opcode The main intent of the System User mode is to protect critical code for example code that performs remote firmware updates data and the current processor state memory setup peripheral control etc from inadvertent changes by the user s standard code By remov ing access to the processor s I O registers and preventing memory writes to critical regions the user s code can run without the danger of locking up the processor to the point where it cannot be restarted remotely and or new code uploaded Appendix C System User Mode 319 C 1 System User Mode Opcodes Seven new opcodes have been added to support the System User mode and are listed in Table C 2 All but IDET are placed in previously empty opcode table assignments IDET shares the value of LD E E in the opcode table and will perform that operation when the System User mode is disabled or when it is enabled and in the System mode In addition if the ALTD prefix appears before the opcode LD E E is always executed inste
343. s for the proces sor to begin the reset sequence There is no facility to tri state output lines such as the address lines and the memory and I O control lines Chapter 7 Miscellaneous Functions 95 Table 7 14 Rabbit 3000 Reset Sequence and State of I O Pins RESET Low Pin Name Direction Recognized by CPU Post Resett RESET Input Low or High High CLK Output High Operational CLK32K Input Not Affected Not Affected RESOUT Output High Low XTALAI Input Not Affected Not Affected XTALA2 Output Not Affected Not Affected A 19 0 Output Last Value 0x00000 D 7 0 Bidirectional High Z High Z IWDTOUT Output High High STATUS Output High ode ei SMODE 1 0 Input Not Affected Not Affected CSO Output High Operational CS1 Output High Z High CS2 Output High High OEO Output High Operational 1 Output High High WE0 Output High High WEI Output High High BUFEN Output High High IORD Output High High IOWR Output High High PA 7 0 Input Output ZZZZZZZZ ZZZZZZZZ PB 7 0 Input Output 00777777 00777777 PC 7 0 4 In 4 Out 70717171 70212121 PD 7 0 Input Output ZZZZZZZZ ZZZZZZZZ PE 7 0 Input Output ZZZZZZZZ ZZZZZZZZ PF 7 0 Input Output ZZZZZZZZ ZZZZZZZZ PG 7 0 Input Output ZZZZZZZZ ZZZZZZZZ A low is recognized internally by the processor after a reset The default state of the I O ports after the completion of the reset and initializ
344. s from the address specified by the upper 4 bits of the SEGSIZE register to OXODFFF For exam ple if the upper 4 bits of SEGSIZE are 0x0D then the stack segment will occupy OxODO00 0xODFFF or If the upper 4 bits of SEGSIZE are greater than or equal to OxOE the stack segment vanishes If these bits are set to zero the two segments below the stack segment will vanish The lower 4 bits of SEGSIZE determine the lower boundary shown in the figure If this boundary is equal to the upper boundary or greater than OxOE the data segment will van ish If this segment is placed at zero the code segment will vanish Chapter 8 Memory Interface and Mapping 117 Extended code 44 XPC segment 8K Stack segment 4K typ Boundary SEGSIZE 0 3 7 ba segment XPC STACKSEG DATASEG Root segment 00 Boundary SEGSIZE 4 7 16 bit address 20 bit address Figure 8 4 Memory Segments The memory management unit accepts a 16 bit address from the processor and translates it into a 20 bit address The procedure to do this works as follows 1 It is determined which segment the 16 bit address belongs to by inspecting the upper 4 bits of the address Every address must belong to one of the possible 4 segments 2 Each segment has an 8 bit segment register The 8 bit segment register is added to the upper 4 bits of the 16 bit address to create a 20 bit address Wraparound o
345. s not occurred read 1 The Input Capture 2 Stop condition has occurred 6 0 The corresponding Input Capture 2 Stop interrupt is disabled write 1 The corresponding Input Capture 2 Stop interrupt is enabled 5 0 The Input Capture 1 Start condition has not occurred read 1 The Input Capture Start condition has occurred 5 0 The corresponding Input Capture 1 Start interrupt is disabled write 1 The corresponding Input Capture 1 Start interrupt is enabled 4 0 The Input Capture 1 Stop condition has not occurred read 1 The Input Capture Stop condition has occurred 4 0 The corresponding Input Capture 1 Stop interrupt is disabled write 1 The corresponding Input Capture 1 Stop interrupt is enabled 3 0 The Input Capture 2 counter has not rolled over to all zeros read 1 The Input Capture 2 counter has rolled over to all zeros 3 0 No effect on Input Capture 2 counter This bit always reads as zero write 1 Reset Input Capture 2 counter to all zeros and clears the rollover latch 2 0 The Input Capture 1 counter has not rolled over to all zeros read 1 The Input Capture 1 counter has rolled over to all zeros 2 0 No effect on Input Capture 1 counter This bit always reads as zero write 1 Reset Input Capture 1 counter to all zeros and clears the rollover latch 1 0 Ox Normal Input Capture operation 0 Normal Input Capture operation T Reserved for test The Input Capture counter increments at both bit 0 and bit 8 There is no carry fr
346. s under its control The master also can do a write to the status register which is used as a signaling device and does not actually write to the status register The three registers that the master can write appear as read reg isters to the slave Rabbit The master provides an enable strobe to read the three read data registers and the status register These registers are write registers to the Rabbit The first register or the three pairs of registers is special in that writing can interrupt the other processor in the master slave communications link An output line from the slave is asserted when the slave writes to slave register zero This line can be used to interrupt the master Internal circuits in the slave can be setup up to interrupt the slave when the master writes to slave register zero The status register that is available to both sides keeps score on all the registers and reports if a potential interrupt is requested by either side The status register keeps track of the full empty status of each register A register is considered full when one side of the link writes to it It becomes empty if the other side reads it In this way either side can test if the other side has modified a register or whether either side has even stored the same informa tion to a register The master slave communication link makes possible set and forget communication protocols Either side can issue a command or request by storing data in some register
347. scillator Oscillator delayed and inverted Doubled clock Delay gt time Address CS A Example Write Cycle Data out Write pulse early write pulse option Address CS Example Read AE Valid data out from mem Cycle output enb early output enb option 27 Figure 16 7 Clock Doubler Memory Timing 228 Rabbit 3000 Microprocessor User s Manual 16 4 Maximum Clock Speeds The Rabbit 3000 is rated for a minimum clock period of 17 ns commercial specifications and 18 ns industrial specifications The commercial rating calls for a 5 voltage varia tion from 3 3 V and a temperature range from 40 to 70 C The industrial ratings stretch the voltage variation to 10 and a temperature range from 40 to 85 C This corre sponds to maximum clock frequencies of 58 8 MHz commercial and 55 5 MHz indus trial If the clock doubler or spectrum spreader is used these maximum ratings must be reduced as shown in the following table When the doubler is used the duty cycle of the clock becomes a critical parameter The duty cycle should be measured at the separate clock output pin pin 2 The minimum period must be increased by any amount that the clock high time is greater or less than specified in the duty cycle requirement Table 16 7 Maximum Clock Speeds at 3
348. seen as noise distrib uted over the screen 216 Rabbit 3000 Microprocessor User s Manual 16 AC TIMING SPECIFICATIONS The Rabbit 3000 processor may be operated at voltages between 1 8 V and 3 6 V and at temperatures from 40 C to 85 C with use possible use over the extended range 55 C to 105 C For long life it is desirable not to exceed a die temperature of 125 C Most users will operate the Rabbit at 3 3 V 16 1 Memory Access Time Required memory address and output enable access time for some important typical cases are given in the table below It is assumed that the clock doubler is used that the clock spreader is enabled in the normal mode that the memory early output enable is on and that the address bus has 60 pF load Table 16 1 Memory Requirements at 3 3 V 40 C to 85 C Adr Bus 60 pF Clock Period Clock Doubler Memory Address Memory Output Frequency Nominal Delay Access Enable Access MHz ns ns ns ns 18 43 54 20 97 60 22 11 45 20 78 51 24 00 42 19 72 45 25 80 39 17 66 43 29 49 34 16 56 37 44 24 22 5 10 33 5 22 All important signals on the Rabbit 3000 are output synchronized with the internal clock The internal clock is closely synchronized with the external clock CLK that may be optionally output from pin 2 of the TQFP package The delay in signal output depends on the capacitive load on the output lines In the case of the address lin
349. ser s Manual e Input output instructions are now accomplished by normal memory access instructions prefixed by an op code byte to indicate access to an I O space There are two I O spaces internal peripherals and external I O devices Some Z80 and Z180 instructions have been deleted and are not supported by the Rabbit see Chapter 20 Differences Rabbit vs Z80 Z180 Instructions Most of the deleted instructions are obsolete or are little used instructions that can be emulated by several Rabbit instructions It was necessary to remove some instructions to free up l bvte op codes needed to implement new instructions efficiently The instructions were not re implemented as 2 byte op codes so as not to waste on chip resources on unimportant instructions Except for the instruction EX SP HL the original Z180 binary encoding of op codes is retained for all Z180 instructions that are retained 3 3 1 Load Immediate Data to a Register A constant that follows the op code in the instruction stream can generally be loaded to any register except PC IP and F Load to the PC is a jump instruction This includes the alternate registers on the Rabbit but not on the Z180 Some example instructions appear below LD A 3 LD HL 456 LD BC 3567 not possible 2180 LD H 0x4A not possible on Z180 LD IX 1234 LD C 54 Byte loads require four clocks word loads require six clocks Loads to IX IY or the alter nate registers generally
350. ses with precise timing relationships The relationship between two events can be controlled to within 10 us to 20 us Using a timer to generate a periodic clock allows events to be controlled to a precision of approximately 10 us However if Timer B is used to control the output registers a preci sion approximately 100 times better can be achieved This is because Timer B has a match register that can be programmed to generate a pulse at a specified future time The match register has two cascaded registers the match register and the next match register The match register is loaded with the contents of the next match register when a pulse is gener ated This allows events to be very close together one count of Timer B Timer B can be clocked by sysc1k 2 divided by a number in the range of 1 256 Timer B can count as fast as 10 MHz with a 20 MHz system clock allowing events to be separated by as little as 100 ns Timer B and the match registers have 10 bits Using Timer B output pulses can be positioned to an accuracy of 2 Timer can also be used to capture the time at which an external event takes place in conjunction with the external interrupt line The interrupt line can be programmed to interrupt on either rising falling or both edges To capture the time of the edge the interrupt routine can read the Timer B counter The execution time of the interrupt routine up to the point where the timer is read can be subtracted from the t
351. ss 0xC8 SFDR Address 0xD8 Bit s Value Description Read Returns the contents of the receive buffer 7 0 Write Loads the transmit buffer with a data byte for transmission Table 12 9 Address Register All Ports Serial Port x Address Register SAAR Address 0xC1 SBAR Address 0xD1 SCAR Address 0 1 SDAR Address 0 1 SEAR Address 0xC9 SFAR Address 0xD9 Bit s Value Description Returns the contents of the receive buffer In Clocked Serial mode reading the data from this register automatically causes the receiver to start a byte receive Read SP ERU operation the current contents of the receive buffer are read first eliminating the need for software to issue the Start Receive command 7 0 Loads the transmit buffer with an address byte marked with a zero address bit for transmission In HDLC mode the last byte of a frame must be written to this register to enable subsequent CRC and closing Flag transmission In Clocked Write Serial mode writing the data to this register causes the transmitter to start byte transmit operation eliminating the need for the software to issue the Start Transmit command 168 Rabbit 3000 Microprocessor User s Manual Table 12 10 Long Stop Register All Ports Serial Port x Long Stop Register SALR Address 0xC2 SBLR Address 0xD2 SCLR Address 0xE2 SDLR Address 0xF2 SELR Address 0xCA S
352. ss Ioz Output Current A nn 10 10 absolute worst case buffers DD DD 4 68 Rabbit 3000 User s Manual 5 7 Buffer Sourcing and Sinking Limit Unless otherwise specified the Rabbit I O buffers are capable of sourcing and sinking 6 8 mA of current per pin at full AC switching speeds The limits are related to the maxi mum sustained current permitted by the metallization on the die Chapter 5 Pin Assignments and Functions 69 70 Rabbit 3000 Microprocessor User s Manual 6 RABBIT INTERNAL I O REGISTERS Chapter 6 2 Rabbit Internal I O Registers 71 Table 6 1 Rabbit 3000 Peripherals and Interrupt Service Vectors On Chip Peripheral ISR Starting Address Periodic Interrupt GCSR IIR 7 1 0 0x00 Memory Management No interrupts Slave Port IIR 7 11 0 0x80 Parallel Port A No interrupts Parallel Port F No interrupts Parallel Port B No interrupts Parallel Port G No interrupts Parallel Port C No interrupts Input Capture IIR 7 1 1 OxAO Parallel Port D No interrupts Parallel Port E No interrupts External I O Control No interrupts Pulse Width Modulator No interrupts Rabbit 3000 UIR 7 1 1 0x70 Rabbit 3000A Quadrature Decoder UIR 7 1 1 0x90 External Interrupts INTO EIR 0x00 INTI EIR 0x10 Timer A IIR 7 11 0 OxAO Timer B IIR 7 1
353. st memory device requiring no wait states c Interrupt after I O with Short CSx enabled This bug is documented in Section 7 5 When the short chip select option is enabled the interrupt sequence will attempt to write the return address to the stack if an interrupt takes place immediately after an internal or an external I O instruction The chip select will be suppressed during the write cycle and the correct return address will not be stored on the stack This happens only when an interrupt takes place immediately after an I O instruction when the short chip select option is enabled d IrDA bug This bug is documented in TN236 Rabbit 3000 IrDA Bug When configured to operate in the IrDA mode the serial port may at times generate an extra pulse before the start bit is transmitted This pulse may appear either before a multi character transmission or before a single character transmission If the beginning of the start bit coincides with when the IrDA pulse generator output is high there will be a spurious 1 16th bit cell pulse on the transmit output Appendix B Rabbit 3000 Revisions 275 2 First revision Rabbit 3000A j Available in two packages and identified by IL2T for the LQFP package and 1721 for the TFBGA package This version began shipping in August 2003 All the bugs in the original Rabbit 3000 were fixed The Rabbit 3000A contains a number of new features and improvements a A new mode of operation known as System
354. status register TACSR has a bit for each timer that indicates if the output pulse for that timer has taken place since the last read of the status register When the status register is read these bits are cleared No bit will be lost Either it will be read by the status register read or it will be set after the status register read is complete If a bit is on and the corresponding interrupt is enabled an interrupt will occur when priorities allow However a separate interrupt is not guaranteed for each bit with an enabled interrupt If the bit is read in the status register it is cleared and no further interrupt corresponding to that bit will be requested It is possible that one bit will cause an interrupt and then one or more additional bits will be set before the status register is read After these bits are cleared they cannot cause an interrupt If any bits are on and the corresponding interrupt is enabled then the interrupt will take place as soon as priorities allow However if the bit is cleared before the interrupt is latched the bit will not cause an interrupt The proper rule to follow is for the interrupt routine to handle all bits that it sees set Although timers A8 A10 are part of Timer A they are dedicated to the input pulse cap ture PWM and quadrature decoder peripherals respectively The peripherals clocked by these timers can generate interrupts but the timers themselves cannot Furthermore these timers cannot be cascad
355. ster PDB7R 0x006F w XXXXXXXX Port E Data Register PEDR 0x0070 R W XXXXXXXX Port E Control Register PECR 0x0074 xx00xx00 Port E Function Register PEFR 0x0075 00000000 Port E Data Direction Register PEDDR 0x0077 w 00000000 Port E Bit 0 Register PEBOR 0x0078 Port E 1 Register PEBIR 0x0079 w XXXXXXXX Port E Bit 2 Register PEB2R 0x007A w XXXXXXXX Port E Bit 3 Register PEB3R 0x007B w XXXXXXXX Port E Bit 4 Register PEB4R 0x007C w XXXXXXXX Port E Bit 5 Register PEB5R 0x007D Port E 6 Register PEB6R 0 007 w XXXXXXXX Port E Bit 7 Register PEB7R 0x007F w XXXXXXXX Port F Data Register PFDR 0x0038 R W XXXXXXXX Port F Control Register PFCR 0x003C w xx00xx00 Port F Function Register PFFR 0x003D w XXXXXXXX Port F Drive Control Register PFDCR 0x003E Port F Data Direction Register PFDDR 0x003F 00000000 Port G Data Register PGDR 0x0048 R W XXXXXXXX Port G Control Register PGCR 0x004C w xx00xx00 Port G Function Register PGFR 0x004D Port G Drive Control Register PGDCR 0x004E Port G Data Direction Register PGDDR 0x004F w 00000000 Bank 0 Control Register IBOCR 0x0080 w 00000000 Bank 1 Control Register IBICR 0x0081 00000000 332 Rabbit 3000 Microprocessor User s Manual Table D 1 Rabbit 3000A Internal I O Registers continued
356. ster TBL2R 0xB5 Timer B Count MSB Register TBCMR OxBE R XXXXXXXX Timer B Count LSB Register TBCLR OxBF R XXXXXXXX Serial Port A Data Register SADR OxCO R W XXXXXXXX Serial Port A Address Register SAAR 0 1 R W XXXXXXXX Serial Port A Long Stop Register SALR 0xC2 R W XXXXXXXX Serial Port A Status Register SASR 0xC3 R 0xx00000 Serial Port A Control Register SACR 0xC4 000000 Serial Port A Extended Register SAER 0xC5 w 00000000 Serial Port B Data Register SBDR 0xD0 R W XXXXXXXX Serial Port B Address Register SBAR OxD1 R W XXXXXXXX Serial Port B Long Stop Register SBLR 0xD2 R W XXXXXXXX Serial Port B Status Register SBSR 0xD3 R 0xx00000 Serial Port B Control Register SBCR 0xD4 w xx000000 Serial Port B Extended Register SBER 0xD5 w 00000000 Serial Port C Data Register SCDR OxEO R W XXXXXXXX Serial Port C Address Register SCAR 0 1 R W XXXXXXXX Serial Port C Long Stop Register SCLR OxE2 R W XXXXXXXX Serial Port C Status Register SCSR OxE3 R 0xx00000 Serial Port C Control Register SCCR OxE4 000000 Serial Port C Extended Register SCER 0 5 00000000 Serial Port D Data Register SDDR OxFO R W XXXXXXXX Chapter 6 2 Rabbit Internal I O Registers 77 Table 6 2 Rabbit Internal I O Registers continued Register Name Mnemonic I O Address R W Reset Serial Port D Address Register SDAR OxF1 R W XXXXXXXX Serial Port D Long Stop R
357. ster s programmable chip select lines 10 17 e SRD Input If SCS is also low this line pulled low causes the contents of the register selected by the address lines to be driven on the data bus If a Rabbit is used as a master this line is normally connected to the global I O read strobe IORD e SWR Input If SCS is also low this line causes the data bits on the data bus to be clocked into the register selected by the address lines on the rising edge of SWR or SCS whichever rises first If a Rabbit is used as a master this line is normally con nected to the global I O write strobe IOWR e SLAVEATTN This line is set low asserted if the slave writes to the SPDOR register This line is set high if the master writes anything to the slave status register This line is usually connected to cause the master to be interrupted when it goes low The data lines of the slave port are shared with Parallel Port A that uses the same package pins The slave port can be enabled and Parallel Port A be disabled by storing an appro priate code in the slave port control register SCR After the processor is reset all the pins belonging to the slave interface are configured as parallel port inputs unless SMODEI SMODEDO are set to 0 1 in which case the slave port is enabled after reset and the slave starts the cold boot sequence using the slave port The slave port has three data registers for each direction of communication Three regis
358. t DE HL HL C zero if no carry 1 if C 14 16 clocks total if C after first SBC result 1 else 0 7 Oif C 1 if IC r compute HL DE OR j SBC HL DE BOOL HL DEC HL BOOL HL r clear carry zero is equal force to zero 1 invert logic 12 clocks total logical not l for inputs equal Chapter 3 Details on Rabbit Microprocessor Features 41 Some simplifications are possible if one of the unsigned numbers being compared is a constant Note that the carry has a reverse sense from SBC In the following examples the pseudo code in the form LD DE 65535 tt does not indicate a load of DE with the address pointed to by 65535 tt but simply indicates the difference between 65535 and the 16 bit unsigned integer tt test for HL gt tt tt is constant LD DE 65535 tt ADD HL DE carry set if HL gt tt SBC HL HL HL HL C result 1 if carry set else zero BOOL HL 14 total clocks true if HL gt tt HL stt tt is constant not zero LD DE 65536 tt ADD HL DE SBC HL HL BOOL HL 14 clocks HL gt tt and tt is zero LD HL 0x1 6 clocks HL lt tt tt is a constant not zero if tt 0 always false LD DE 65536 tt ADD HL DE not carry if HL tt SBC HL HL 1 if carry else 0 INC HL 14 clocks 0 if carry else 1 if no carry HL lt tt tt is constant not zero LD DE 65535 tt ADD HL DE C if HL tt CCF C if true SBC HL HL if C 1 else O INC HL 16 clocks 1 if tr
359. t 3000 P STATIC MEMORY ADDRESS LINES 20 FLASH 5 CS0 O o ics1 b 0 JOE 1 52 O WE OE1 WEO O O STATIC MEMORY RAM Figure 8 2 Typical Memory Chip Connection 116 Rabbit 3000 Microprocessor User s Manual 8 2 Memory Mapping Overview See Section 3 2 Memory Mapping for a discussion of Rabbit memory mapping Figure 8 3 shows an overview of the Rabbit memory mapping The task of the memory mapping unit is to accept 16 bit addresses and translate them to 20 bit addresses The memory interface unit accepts the 20 bit addresses and generates control signals applied directly to the memory chips Memory Memory Processor Mapping Interface Unit Unit Figure 8 3 Overview of Rabbit Memory Mapping 8 3 Memory Mapping Unit The 64K 16 bit address space accessed by processor instructions is divided into segments Each segment has a length that is a multiple of 4K Except for the extended code segment the segments have adjustable sizes and some segments can be reduced to zero size and thus vanish from the memory map The four segments are shown in the example in Figure 8 4 The segment size register SEGSIZE determines the boundaries marked in the diagram The extended code seg ment always occupies the addresses 0 0 000 0 The stack segment stretche
360. t approximately 30 pF is connected to each address line particu larly AO and A1 which account for three quarters of the charging current due to the address lines Chapter 16 AC Timing Specifications 231 I mA 120 x 100 80 x xtal 25 80 A A xtal 14 74 60 xtal 11 05 m e xtal 3 68 0 10 20 30 40 50 60 Clock Frequency MHz Figure 16 9 Rabbit 3000 System Current vs Frequency at 3 3 V 30 l 25 x xtal 25 80 A xtal 14 74 20 x 6 m xtal 11 05 0 2 4 6 8 10 12 14 16 Clock Frequency MHz Figure 16 10 Rabbit 3000 System Current vs Frequency at 3 3 V enlarged view over 0 16 MHz range 232 Rabbit 3000 Microprocessor User s Manual Lowering the operating voltage will greatly reduce current consumption and power Drop ping to 2 7 V from 3 3 V will result in 70 current consumption and 60 of the power Further dropping to 1 8 V will reduce current to 40 and power to 20 compared to 3 3 V Naturally this complicates the selection of memories especially at 1 8 V It is important to know that the lowest speed crystal will not always give the lowest power consumption because when the crystal is divided internally the short chip select option can be used to reduce the chip select duty cycle of the flash memory or fast RAM greatly reducing the static current consumption associated with some memories I
361. t the no wait states memory access time since two adjacent clocks are always used However the maximum allowed clock speed must be slightly reduced if the clock is supplied via the clock doubler The only signals clocked on the falling edge of the clock are the memory and I O write pulses and the early option memory output enable See Chapter 8 for more information on the early output enable and write enable options The spectrum spreader either stretches or shrinks the low plateau of the clock by a maxi mum of 3 ns for the normal spreading and 4 5 ns for the strong spreading If the clock dou bler is used this will cause an additional asymmetry between alternate clock cycles The power consumption is proportional to the clock frequency and for this reason power can be reduced by slowing the clock when less computing activity is taking place The clock doubler provides a convenient method of temporarily speeding up or slowing down the clock as part of a power management scheme Chapter 7 Miscellaneous Functions 85 7 4 Clock Spectrum Spreader When enabled the spectrum spreader stretches and compresses the clocks in a complex pattern that results in spreading the energy in the clock harmonics over a wide range of frequencies The spectrum spreader has a normal and a strong setting With either setting the peak spectral strength of the clock harmonics is reduced by approximately 15 dB for frequencies above 100 MHz For lower frequencies the st
362. t will have its old value change to the new value at some point without wavering back and forth The existence of a transitional value could be very rare and has the potential to create a bug that happens often enough to be serious but so infrequently as to be difficult to diagnose Thus the user is cautioned to avoid this situa tion Chapter 13 Rabbit Slave Port 205 Table 13 2 describes the slave port control register Table 13 2 Slave Port Control Register SPCR adr 0x024 Bit 7 Bits 6 5 Bit 4 Bit 3 2 Bits 1 0 Write Only Read Only Write Only Write Only 00 disable slave port port A is a byte wide input port 00 slave 01 disable slave port port A 0 obey SMODE Reads SMODE is a byte wide output port pins pins x 10 enable the slave port pp enable slave 1 ignore SMODE smode0 11 Enable the auxilliarv I O POF Interrupt pins bus Parallel Port A is used 01 priority 1 for the data bus and Parallel 10 priority 2 Port B 7 2 is used for the 11 priority 3 address bus The functionality of the bits is as follows Bit 7 If set to 0 the cold boot feature will be enabled Normally this bit is set to a 1 after the cold boot is complete The cold boot for the slave port is enabled automatically if SMODE1 SMODEO lines are set to 0 1 after the reset ends This features disables the normal operation of the processor and causes commands to be accepted via
363. te nee 239 17 1 2 BIOS Assumptions nien Bo peterem ree m er Pee ER Pee eerte hes at 240 17 2 Vart al Doveri sioe peti ener eic e pt e eee 240 17 2 1 Periodic Interrupt Rame EEUU eene 240 17 2 2 Watchdog Timer Support beenden ett uu 240 Chapter 18 Other Rabbit Software 243 18 1 Power Management Support eere edet tiet era erbe bee Heber ps 243 18 2 Reading and Writing I O Registers nee ners nennen nennen 244 18 2 1 Using Assembly Language trente tet rete diee eere es 244 18 2 2 Using Library Eunctiols iere eiit ee eese eroi deter 244 18 3 Shadow Registers eee n oerte ne eee ETUR en 245 18 3 1 Updating Shadow Registers noce e ret lee ese pee dotes 245 18 3 2 Interrupt While Updating Registers 245 18 3 3 Write only Registers Without Shadow Registers eese 246 18 4 Timer and Clock Usage ide erem e ie tee ep rein etie 246 Chapter 19 Rabbit Instructions 249 19 1 Load Immediate ssir irda es 252 19 2 Load amp Store to Immediate Address eese eene 252 19 3 8 bit Indexed Load and Store n eerte ener entente ene 252 19 4 16 bit Indexed Loads and Stores sese eee nenne nennen nennen 252 19 5 16 bit Load and Store 20 bit Address 0222242 1 10 000000000000 nn nennen nennen 253 19 6 Register to Register MOVES sasana maaan
364. tect the start of a frame In order for 196 Rabbit 3000 Microprocessor User s Manual the receiving interrupt service routine to detect this gap it is suggested that dummy char acters be transmitted to help detect the gap This can be done in the following manner The transmitter starts transmitting dummy characters when the first character interrupt is received Each time there is an interrupt either receiver data register full or transmitter data register empty a dummy character is transmitted if the transmitter data register is empty Although the transmitter and receiver operate at approximately the same baud rate there can be a difference of up to about 5 between their baud rates Thus the receiver full and transmitter empty interrupts will become out of phase with each other assuming that the remote station transmits without gaps between characters A counter is zeroed each time a character is received and the counter is incremented each time a character is transmitted If this counter holds n this indicates that a gap has been detected in the frame the length of the gap is n 1 to n characters The start of frame could be marked by n reaching 3 indicating that the existence of a gap at least two characters long Chapter 12 Rabbit Serial Ports 197 198 Rabbit 3000 Microprocessor User s Manual 13 RABBIT SLAVE PoRT When a Rabbit microprocessor is configured as a slave Parallel Port A and certain other data line
365. tected endless loop con dition could still occur since the periodic interrupt can still hit the hardware watchdog If any of the virtual watchdogs times out then hits are withheld from the hardware watch dog and it times out resulting in a hardware reset Virtual watchdogs may be allocated deallocated enabled and disabled The advantage of the virtual watchdogs is that if any of them fail an error is detected The Dynamic C Users s Manual chapter on the Virtual Driver provides more details on virtual watchdogs Chapter 17 Rabbit BIOS and Virtual Driver 241 242 Rabbit 3000 Microprocessor User s Manual 18 OTHER RABBIT SOFTWARE 18 1 Power Management Support The power consumption and speed of operation can be throttled up and down with rough synchronism This is done by changing the clock speed or the clock doubler The range of control is quite wide the speed can vary by a factor of 16 when the main clock is driving the processor In addition the main clock can be switched to the 32 768 kHz clock In this case the slowdown is very dramatic a factor of perhaps 500 In this ultra slow mode each clock takes about 30 us and a typical instruction takes 150 us to execute At this speed the periodic interrupt cannot operate because the interrupt routine would execute too slowly to keep up with an interrupt every 16 clocks Only about 3 instructions could be executed between ticks A different set of rules applies in the ultra s
366. ter Maximum Rating TA Operating Temperature 55 to 85 C Ts Storage Temperature 65 to 150 C Maximum Input Voltage e Oscillator Buffer Input Vpp 0 5 V e 5 V tolerant I O 5 5 V Vpp Maximum Operating Voltage 3 6 V Stresses beyond those listed in Table 5 5 may cause permanent damage The ratings are stress ratings only and functional operation of the Rabbit 3000 chip at these or any other conditions beyond those indicated in this section 1s not implied Exposure to the absolute maximum rating conditions for extended periods may affect the reliability of the Rabbit 3000 chip Table 5 6 outlines the DC characteristics for the Rabbit 3000 at 3 3 V over the recom mended operating temperature range from T 55 C to 85 C Vpp 3 0 V to 3 6 V Table 5 6 3 3 Volt DC Characteristics Symbol Parameter Test Conditions Min Typ Max Units Vpp Supply Voltage 3 0 3 3 3 6 V Vm High Level Input Voltage 2 0 V Low Level Input Voltage 0 8 V 6 8 mA 0 7 x V High Level Output Voltage V OH g P g Vpp Vpp Low Level Output Vol 04 ow Level Output Voltage m 89 Vpp Vpp min Vin High Level Input Current IN DD 10 uA absolute worst case all buffers Vpp Vpp max Low Level Input Current Vin Vss ln 10 HA absolute worst case all buffers Vpp Vpp max High Impedance State Vin Vpp or V
367. ternal clock and NRZ data encoding 0 Idle line condition is Flags 1 Idle line condition is all ones 0 Transmit Flag on underrun 1 Transmit Abort on underrun 1 0 xx These bits are ignored in HDLC mode 178 Rabbit 3000 Microprocessor User s Manual 12 3 Serial Port Interrupt A common interrupt vector is used for the receive and transmit interrupts There is a sepa rate interrupt request flip flop for the receiver and transmitter If either of these flip flops is set a serial port interrupt is requested The flip flops are set by a rising edge only The flip flops are cleared by a pulse generated by an I O read or write operation as shown in Figure 12 3 When an interrupt is requested it will take place immediately when priorities allow and an instruction execution is complete The interrupt is lost if the request flip flop is cleared before the interrupt takes place If the flip flop is not cleared in the interrupt another interrupt will take place when priorities are lowered Transmitter IRQ Transmitter Data D s 53 Request Interrupt Buffer Empty or Trans mitter not Busy Write Transmitter Data Register or Write Status Register Receiver IRQ Receiver Data Buffer Full Read Receiver Data Register Figure 12 3 Generation of Serial Port Interrupts The receive interrupt request flip flop is set after the stop bit is sampled on receive nomi nally o
368. ternate registers is exclusive to the Rabbit and is not allowed the 780 Z180 Examples POP HL PUSH BC PUSH IX PUSH af POP DE POP DE POP HL 3 3 7 16 bit Arithmetic and Logical Ops The HL register is the primary 16 bit accumulator IX and IX can serve as alternate accu mulators for many 16 bit operations The Z180 Z80 has a weak set of 16 bit operations and as a practical matter the programmer has to resort to combinations of 8 bit operations in order to perform many 16 bit operations The Rabbit has many new op codes for 16 bit operations removing some of this weakness The basic Z80 Z180 16 bit arithmetic instructions are ADD HL ww where ww is HL DE BC SP ADC HL ww ADD and ADD carry SBC HL ww sub and sub carry INC ww increment the register without affecting flags In the above op codes IX or IX can be substituted for HL The ADD and ADC instructions can be used to left shift HL with the carry An alternate destination prefix ALTD may be used on the above instructions This causes the result and its flags to be stored in the corre sponding alternate register If the ALTD flag is used when IX or IY is the destination regis ter then only the flags are stored in the alternate flag register The following new instructions have been added for the Rabbit Shifts RR HL rotate HL right with carry 1 byte 2 clocks note use ADC HL HL for left rotate or add HL HL if no carry in is needed
369. that can access memory using a 20 bit address This greatly expands the data space but the instructions are less efficient than instructions that access the 64k space using 16 bit addresses The Rabbit 3000 supports separate I and D or Instruction and Data spaces When separate I and D space is enabled it applies only to addresses in the root segment or data segment Separate I and D spaces mean that instruction execution makes a distinction between Chapter 3 Details on Rabbit Microprocessor Features 27 fetching an instruction from memory and fetching or storing data in memory When enabled separate I and D space make available the combined root and data segment typi cally 52k bytes for root code in the I space In the D space the root code segment part of the D space is typically used for constant data mapped to flash memory while the data seg ment part of the D space is used for variable data mapped to RAM Separate I and D space increases the amount of both root code and root data because they no longer have to share the same memory even though they share the same addresses 20 bit Memory Space RAM XPC window S stack D Space Data Variable Segment D Space oot ode Root Constant Segment D Space Y Figure 3 6 Separate l and D Space Normally separate I and D space is implemented as shown in Figure 3 6 In the I space the root segment and the
370. that is causing an interrupt request bv writ ing to the slave port status register The data bits are ignored but the flip flop that is the source of the interrupt request is cleared Figure 13 3 shows a logical schematic of this func tionalitv 202 Rabbit 3000 Microprocessor User s Manual Master writes SPD0R Slave inbound interrupt requested Visible in status register Slave writes status register SLAVEATTN PB7 Visible in status register Slave writes SPDOR Master writes status register Figure 13 3 Slave Port Handshaking and Interrupts Chapter 13 Rabbit Slave Port 203 Figure 13 4 shows a sample connection of two slave Rabbits to a master Rabbit The master drives the slave reset line for both slaves and provides the main processor clock from its own clock There is no requirement that the master and slave share a clock but doing so makes it unnecessary to connect a crystal to the slaves Each Rabbit in Figure 13 4 has to have RAM memory The master must also have flash memory However the slaves do not need nonvolatile memory since the master can cold boot them over the slave port and download their program In order for this to happen the SMODEO and SMODEI pins must be properly configured as shown in Figure 13 4 to begin a cold boot process at the end of the slave reset Master Rabbit First Slave Rabbit 07 500 807 IORD SRD IOWR WR SA
371. the clock for both send and receive the data transmission proceeds at a rate controlled by the target board under development This scheme does not allow for an interrupt and it is not desirable to use up an external interrupt for this purpose The serial port may be used if desired During program load because there is no conflict with the user s program at compile load time However the user s program will conflict during debugging The nature of the transmissions during debugging is such that the user program starts at a break point or otherwise wants to get the attention of the PC The other type of message is when the PC wants to read or write target memory while the target is running The target toggling the clock can simply send a clocked serial message to get the attention of the PC The intermediate communications board can accept these unsolicited messages using its clocked serial port To prevent overrunning the receiver the target can wait for a handshake signal on one of the SMODE lines or there can be suitable pre arranged delays If the PC wants attention from the target it can set a line to request attention SMODE The target will detect this line in the periodic interrupt routine and handle the complete message in the periodic interrupt routine This may slow down target execution but the interrupts will be enabled on the target while the message is read The intermediate board could split long messages into a series of shorter
372. the port On reset bits 0 1 4 and 5 are reset to zero PGFR Port G function register Set bit to 1 to enable alternate output function Bits 6 and 2 enable the asycnhronous or SDLC HDLC serial ports E and F outputs And bits 5 4 and 1 0 enable the SDLC HDLC transmit and receive clock outputs for serial ports E and F PGDCR Parallel Port G drive control register A 0 makes the corresponding pin a regular output 1 makes the corresponding pin an open drain output Write only PGDDR Port G data direction register Set to 1 to make corresponding pin an out put This register is zeroed on reset On reset the data direction register is zeroed making all pins inputs In addition certain bits in the control register are zeroed bits 0 1 4 5 to ensure that data is clocked into the output registers when loaded All other registers associated with port G are not initialized on reset 144 Rabbit 3000 Microprocessor User s Manual 10 I O BANK CONTROL REGISTERS The pins of Port E can be set individually to be I O strobes Each of the eight possible I O strobes has a control register that controls the nature of the strobe and the number of wait states that will be inserted in the I O bus cycle Writes can also be suppressed for any of the strobes The types of strobes are shown in Figure 10 1 Each of the eight I O strobes is active for addresses occupying 1 8th of the 64K external I O address space
373. the program crashes and thus disable the recovery ability given by having a watch dog The following is a suggested method for hitting the watchdog An array of up to 10 bytes is set up in RAM Each of these bytes is a virtual watchdog To hit a virtual watchdog a number is stored in a byte Every virtual watchdog is counted down by an interrupt routine driven by a periodic interrupt This can happen every 62 5 ms If none of the virtual watch dogs has counted down to zero the interrupt routine hits the hardware watchdog If any have counted down to zero the interrupt routine disables interrupts and then enters an endless loop waiting for the reset Hits of the virtual watchdogs are placed in the user s program at must exercise locations The Dynamic C User s Manual provides further information on the use of virtual watchdogs Chapter 7 Miscellaneous Functions 93 Table 7 13 Watchdog Timer Test Register WDTTR adr 0x09 Bit s Value Description 0 51 Clock the least significant byte of the watchdog timer from the peripheral clock Intended for chip test and code 0x54 below only 0x52 Clock the most significant byte of the watchdog timer from the peripheral clock Intended for chip test and code 0x54 below only 0x53 Clock both bytes of the watchdog timer in parallel from the peripheral clock Intended for chip test and code 0x54 below only 7 0 Disable the watchdog timer This value by itself
374. then it is possible to eliminate the stack segment entirely and place the single stack in the data seg ment This option is attractive for systems with only 32K of RAM that don t need multiple stacks Chapter 3 Details on Rabbit Microprocessor Features 31 3 3 Instruction Set Outline Load Immediate Data to a Register on page 33 Load or Store Data from or to a Constant Address on page 33 Load or Store Data Using an Index Register on page 34 Register to Register Move on page 35 Register Exchanges on page 35 Push and Pop Instructions on page 36 16 bit Arithmetic and Logical Ops on page 36 Input Output Instructions on page 39 these include a fix for a bug that manifests itself if an I O instruction prefix IOI or IOE is followed by one of 12 single byte op codes that use HL as an index register In the discussion that follows we give a few example instructions in each general category and contrast the Z80 Z180 with the Rabbit For a detailed description of every instruction see Chapter 19 Rabbit Instructions The Rabbit executes instructions in fewer clocks then the Z80 or Z180 The Z180 usually requires a minimum of four clocks for l bvte opcodes or three clocks for each byte for multi byte op codes In addition three clocks are required for each data byte read or writ ten Many instructions in the Z180 require a substantial number of additional clocks The Rabbit usually
375. timing pulses I O Data perclk 2 Timer A1 Timer B1 Timer B2 perclk 2 Timer A1 Timer B1 Timer B2 Figure 9 2 Parallel Port E Block Diagram Chapter 9 Parallel Ports 137 Table 9 10 Parallel Port E Registers Register Name Mnemonic I O address R W Reset Port E Data Register PEDR 0x70 R W XXXXXXXX Port E Control Register PECR 0x74 00 00 Port E Function Register PEFR 0x75 00000000 Port E Data Direction Register PEDDR 0x77 00000000 Port E 0 Register PEBOR 0x78 Port E 1 Register PEBIR 0x79 W XXXXXXXX Port E Bit 2 Register PEB2R Ox7A W XXXXXXXX Port E Bit 3 Register PEB3R Ox7B W XXXXXXXX Port E Bit 4 Register PEB4R Ox7C Port E Bit 5 Register PEBSR 0x7D W XXXXXXXX Port E Bit 6 Register PEB6R Ox7E W XXXXXXXX Port E Bit 7 Register PEB7R Ox7F The following registers are described in Table 9 11 and in Table 9 12 PEDR Port E data register Reads value at pins Writes to port E preload register PEDDR Port E data direction register Set to 1 to make corresponding pin an out put This register is zeroed on reset PEFR Port E function register Set bit to 1 to make
376. to charging and 43 is due to crossover current 2 A crossover current that is proportional to clock frequency and to the overdrive voltage Ve V x V 2 0 7 where V is the operating voltage of the Rabbit 3000 The cross over current results from a brief short circuit when both the P and N transistors of a CMOS buffer are turned on at the same time This component drops as the voltage drops and becomes negligible at 1 4 V 3 The current consumed by the built in main oscillator when turned on This current is also proportional to and is equal to 1 mA at 3 3 V 4 The current drawn by the logic that is driven at the oscillator crystal frequency This is considered distinct because it varies with the crystal frequency but is not reduced when the clock frequency is divided This current becomes zero when the main oscillator is turned off and is 2 5 mA at 3 3 V when the crystal frequency is 14 7 MHz This current is divided between capacitive and crossover components in the same manner as the cur rents in 1 and 2 above All of the above currents can be combined according to the following formula mA 0 32 x V x f 0 23 x Ve x f 0 30 x Vc 0 029 x V x fc 0 025 x Vc x fc where V the operating voltage of the Rabbit 3000 V V x V 2 0 7 f frequency of crystal oscillator in MHz and f clock frequency in MHz 234 Rabbit 3000 Microprocessor User s Manual 16 7 Sleepy Mode Current Consumption
377. too time consuming or not possi ble because the purpose of the privileged instruction is to manipulate the interrupt con trols For additional information on privileged instructions see Section 19 19 Privileged Instructions The privileged instructions to load the stack are listed below LD SP HL LD SP IY LD SP IX The following instructions to load SP are privileged because they are frequently followed by an instruction to change the stack segment register If an interrupt occurs between these two instructions and the following instruction the stack will be ill defined LD SP HL IOI LD sseg a 46 Rabbit 3000 Microprocessor User s Manual The privileged instructions to manipulate the IP register are listed below IPSET 0 shift IP left and set priority 00 in bits 1 0 IPSET 1 IPSET 2 IPSET 3 IPRES rotate IP right 2 bits restoring previous priority RETI pops IP from stack and then pops return address POP IP pop IP register from stack 3 5 4 Critical Sections Certain library routines may need to disable interrupts during a critical section of code Generally these routines are only legal to call if the processor priority is either 0 or 1 A priority higher than this implies custom hand coded assembly routines that do not call general purpose libraries The following code can be used to disable priority 1 interrupts IPSET 1 save previous priority and set priority to 1 Critical section IPRES res
378. tore previous priority This code is safe if it is known that the code in the critical section does not have an embed ded critical section If this code is nested there is the danger of overflowing the IP register A different version that can be nested is the following PUSH IP 1 save previous priority and set priority to 1 Critical section POP IP restore previous priority The following instructions are also privileged LD A xpc LD xpc a BIT B HL 3 5 5 Semaphores Using Bit B HL Thebit B HL instruction is privileged to allow the construction of a semaphore by the following code BIT B HL test a bit in the byte at HL SET B HL make sure bit set does not affect flag if zero flag set the semaphore belongs to us otherwise someone else has it A semaphore is used to gain control of a resource that can only belong to one task or pro gram at a time This is done by testing a bit to see if it is on in which case someone else is using the resource otherwise setting the bit to indicate ownership of the resource No interrupt can be allowed between the test of the bit and the setting of the bit as this might allow two different program to both think they own the resource Chapter 3 Details on Rabbit Microprocessor Features 47 3 5 6 Computed Long Calls and Jumps The instruction to set the XPC is privileged to so that a computed long call or Jump can be made This would be done by the
379. tware is loaded into the slave the slave can begin to perform its function As a simple example suppose that the slave is to be used as a four port UART It has the capability to send or receive characters on any of its four serial ports Leaving aside the ques tion of setting up parameters such as the baud rate we could define a protocol as follows e SPDOR readable by master is a status register with bits indicating which of the four receivers and four transmitters is ready that is has a character received or is ready to send a character e SPDOR writable by the master is a control register used to send commands to the slave e SPDIR is used to send or receive data characters or control bytes e The line SLAVEATTN is wired to the external interrupt request of the master so that the master is interrupted when the slave writes to SPDOR Typically the slave will write to SPDOR when there is a change of status on one of the serial ports The slave can interrupt the master at any time by storing to SPDOR It will do this every time an enabled transmitter is ready to accept a character or every time an enabled receiver receives a character When it stores to SPDOR it will store a code indicating the reason for the interrupt that is receive or transmit and channel number If the cause is receive the received character will also be placed in SPDIR writable by the slave When the master is Chapter 13 Rabbit Slave Port 209 interrupted fo
380. ty of applications will use less than 250K of code equivalent to approximately 10 000 20 000 C statements This reflects both the compact nature of Rabbit code and the typical size of embedded applications Directly accessible C variables are limited to approximately 44K of memory split between data stored in flash and RAM This will be more than adequate for many embed 30 Rabbit 3000 Microprocessor User s Manual ded applications Some applications may require large data arrays or tables that will require additional data memory For this purpose Dynamic C supports a type of extended data memory that allows the use of additional data memory even extending far beyond a megabyte Requirements for stack memory depend on the type of application and particularly whether preemptive multitasking is used If preemptive multitasking is used then each task requires its own stack Since the stack has its own segment in 16 bit address space it is easy to use available RAM memory to support a large number of stacks When a pre emptive change of context takes place the STACKSEG register can be changed to map the stack segment to the portion of RAM memory that contains the stack associated with the new task that is to be run Normally the stack segment is 4K which is typically large enough to provide space for several typically four stacks It is possible to enlarge the stack segment if stacks larger than 4K are needed If only one stack is needed
381. uadrant To get the exact High time the Pulse Width Modulator uses the two LSBs of the pulse width register to modify the High time in each quadrant according to the table below The n 4 term is the base count formed from the eight MSBs of the pulse width register Pulse Width LSBs 1st 2nd 3rd 4th 00 n 4 1 n 4 n 4 n 4 01 4 1 1 4 4 1 4 10 4 1 4 1 4 1 n 4 11 n A 1 n A 1 n 4 1 n 4 1 The diagram below shows PWM output for several different width values for both modes of operation Operation in the spread mode reduces the filtering requirements on the PWM output in most cases Chapter 7 Miscellaneous Functions 103 n 255 normal 256 counts n 255 spread les counts es counts les counts les counts n 256 spread les counts 64 counts le counts les counts n 257 spread les counts les counts 65 counts les counts n 258 spread 65 counts 65 counts 65 counts les counts n 259 spread 65 counts 65 counts 65 counts 65 counts n 259 normal 1 260 counts Table 7 17 PWM LSB x Register PWM LSB Register PWL0R Address 0x88 PWL1R Address 0x8A PWL2R Address 0x8C PWL3R Address 0x8E Bit s Value Description 7 6 write The least significant two bits for the Pulse Width Modulator count are stored 5 1 These bits are ignore
382. uctions below are privileged LD SP HL load the stack pointer LD SP IY LD SP IX The instructions to load the stack are privileged so that they can be followed by an instruc tion to load the stack segment SSEG register without the danger of an interrupt taking place with and incorrect association between the stack pointer and the stack segment reg ister For example LD SP HL IOI LD STACKSEG A The following instructions are privileged IPSET 0 shift IP left and set priority 00 in bits 1 0 IPSET 1 IPSET 2 IPSET 3 IPRES rotate IP right 2 bits restoring previous priority POP IP pop IP register from stack The instructions to modify the IP register are privileged so that they can be followed by a return instructions that is guaranteed to execute before another interrupt takes place This avoids the possibility of an ever growing stack RETI pops IP from stack and then pops return address The instruction reti can be used to set both the return address and the IP in a single instruction If preceded by a LD XPC a complete jump or call to a computed address can be done with no possible interrupt LD A XPC get and set the XPC LD XPC A The instruction LD XPC A is privileged so that it can be followed by other code setting interrupt priority or program counter without an intervening interrupt BIT B HL test a bit in memory The instruction bit B HL is privileged to make it possible to implement a semaphore
383. ue else 0 HL lt tt tt is zero true if HL BOOL HL result in HL HL tt and tt is a constant not zero LD DE 65536 tt ADD HL DE zero if equal BOOL HL INC HL RES 0x1 L 16 clocks HL tt and tt BOOL HL INC HL RES 0x1 L 8 clocks For signed integers the conventional method is to look at the zero flag the minus flag and the overflow flag Signed 8 bit integers span the range 128 to 4127 0x80 to 0x7F Signed 16 bit integers span the range 32768 to 32767 0 8000 to Ox7FFF The sign and zero flag tell which is the larger number after the subtraction unless the overflow is set in which case the sign flag needs to be inverted in the logic that is it is wrong 42 Rabbit 3000 Microprocessor User s Manual ss gt tt 16 amp IV IZ v S amp V ss lt tt S amp IV v IS amp V 8 12 ss tt ss gt tt ss lt tt Another method of doing signed compare is to first map the signed integers onto unsigned integers by inverting bit 15 This is shown in Figure 3 8 Once the mapping has been per formed by inverting bit 15 on both numbers the comparisions can be done as if the num bers were unsigned integers This avoids having to construct a jump tree to test the overflow and sign flags An example is shown below test HL gt 5 for signed integers LD DE 65535 5 0x08000 5 mapped to unsigned integers LD BC 0x08000 ADD HL BC invert high bit ADD HL DE 16 clocks to here Carry now set i
384. ulses 50 5 V tolerant inputs 11 A 9 assembly language clock spectrum spreader 18 input capture 105 instmetons 40 41 42 45 SPIE DOO 52 instructions 32 249 reading writing to I O regis Input capture channels 16 alphabetic order 263 TODS csse rre rerit 244 Instruction set s 2 arithmetic and logical ops 36 asynchronous VO 50 instructions 39 memory support 9 load to constant address 33 B E M o m load to register 33 outputs BGA package quadrature encoder inputs 17 0 dimensions separate and I O power register 35 OUUTE PINS DE 18 register to register move 35 bootstrap operation 101 102 serial ports ll aat 44 48 72 97 C slave port 14 53 Dynamic Le 240 system clock mes 12 external interrupts 99 clocks 2222222 80 211 time date clock 12 interrupt latency 49 32 768 kHz oscillator timed output pulses 49 interrupt service vector ad PN 12 80 81 211 OI ko dresses A 72 clock doubler 83 84 227 design standards interrupt vectors 100 clock speeds
385. unt is shortened either by one or two counts If the transition occurs later than expected it means that the bit cell boundaries are late with respect to the DPLL tracked bit cell boundaries so the count is lengthened either by one or two counts The decision to adjust by one or by two depends on how far off the DPLL tracked bit cell boundaries are This tracking allows for minor differences in the transmit and receive clock frequencies With NRZ and NRZI data encoding the DPLL counter runs continuously and adjusts after every receive data transition Since NRZ encoding does not guarantee a minimum density of transitions the difference between the sending data rate and the DPLL output Chapter 12 Rabbit Serial Ports 189 clock rate must be very small and depends on the longest possible run of zeros in the received frame NRZI encoding guarantees at least one transition every six bits with the inserted zeros Since the DPLL can adjust by two counts every bit cell the maximum dif ference between the sending data rate and the DPLL output clock rate is 1 48 2 With Biphase data encoding either Level Mark or Space the DPLL runs only as long as transitions are present in the receive data stream Two consecutive missed transitions causes the DPLL to halt operation and wait for the next available transition This mode of operation is necessary because it is possible for the DPLL to lock onto the optional transi tions in the receive d
386. up the Rabbit 212 Rabbit 3000 Microprocessor User s Manual 15 EMI CONTROL EMI or electromagnetic interference from unintentional radiation is of concern to the microprocessor system designer One concern is passing the tests sometimes required by the U S Federal Communications Commission FCC or by the European EMC Directive For example in the U S the FCC requires that computing devices intended for use in the home or in office environments but not industrial or medical environments not have unintentional electromagnetic radia tion above certain limits of field strength that depend on frequency and whether the device is intended for home or office use This is verified by measuring radiation from the device at a test site The device under test DUT is operated in a typical fashion with a typical mechanical and electrical configuration while the electromagnetic radiation is measured by a calibrated antenna located either 3 10 m from the device The output of the antenna is connected to a spectrum analyzer For the purposes of the test the spectral power is measured by using a filter with a bandwidth of 120 kHz The peak power is measured by using a quasi peak detector in the spectrum analyzer The quasi peak detector has a charge time constant of 1 ms and a discharge time constant of 550 ms In this manner the peak radiated signal strength is measured The tests required by the FCC and the EC are practically identical
387. ure A9 none no Pulse Width Modulator A10 none no Quadrature Decoder The control status register for Timer A TACSR is laid out as shown in Table 11 3 Table 11 3 Timer A Control and Status Register Timer A Control and Status Register TACSR Address 0x00A0 Bit s Value Description 7 0 AT counter has not reached its terminal count read 1 AT count done This status bit is cleared by a read of this register 7 0 A7 interrupt disabled write 1 A7 interrupt enabled 6 0 A6 counter has not reached its terminal count read 1 A6 count done This status bit is cleared by a read of this register 6 0 A6 interrupt disabled write 1 A6 interrupt enabled 5 0 A5 counter has not reached its terminal count read 1 5 count done This status bit is cleared by a read of this register 5 0 5 interrupt disabled write 1 5 interrupt enabled 4 0 A4 counter has not reached its terminal count read 1 A4 count done This status bit is cleared by a read of this register 152 Rabbit 3000 Microprocessor User s Manual Table 11 3 Timer A Control and Status Register continued Timer A Control and Status Register TACSR Address 0x00A0 Bit s Value Description 4 0 A4 interrupt disabled write 1 MA interrupt enabled 3 0 A3 counter has not reached its terminal count read 1 A3 count done T
388. us Timing The external bus has essentially the same timing for memory cycles or I O cycles A mem ory cycle begins with the chip select and the address lines One clock later the output enable is asserted for a read The output data and the write enable are asserted for a write Address 20 for memory 16 for I O IOCSn 5 IORD or wr X IX Data for read valid Data for write 3 s drive starts at end of T1 WEn or IOWR Notes Read may have no wait states Write cycles and I O read cycles have at least 1 wait state Clock may be asymmetric if clock doubler used I O chip select available on Port E as option Figure 5 6 Bus Timing Read and Write In some cases the timing shown in Figure 5 6 may be prefixed by a false memory access during the first clock which is followed by the access sequence shown in Figure 5 6 In this case the address and often the chip select will change values after one clock and assume the final values for the memory to be actually accessed Output enable and write enable are always delayed by one clock from the time the final stable address and chip select are enabled Normally the false memory access attempts to start another instruction access cycle which is aborted after one clock when the processor realizes that a read data or write data bus cycle is needed The user should
389. ut of Timer A8 and can be set to count at a rate ranging from full clock speed to 1 256 the clock speed Two events are recognized a start condition and a stop condition The start condition mav be used to start counting and the stop condition to stop counting However the counter may also run continuously or run until a stop condition is encountered The start and stop conditions mav also be used to latch the current time at the instant the condition occurs rather than actuallv start or stop the counter The same pin mav be used to detect the start 16 Rabbit 3000 Microprocessor User s Manual and stop condition for example a rising edge could be the start condition and a falling edge the stop condition However optionally the start and stop condition can be input from separate pins The input capture channels can be used to measure the width of fast pulses This is done by starting the counter on the first edge of the pulse and capturing the counter value on the second edge of the pulse In this case the maximum error in the measurement is approxi mately 2 periods of the clock used to count the counter If there is sufficient time between events for an interrupt to take place the unit can be set up to capture the counter value on either start or stop conditions or both and cause an interrupt each time the count is cap tured In this case the start and stop conditions lose the connection with starting or stop ping the counter and simply bec
390. ut Capture Source 1 Register ICSIR 0x59 Input Capture LSB 1 Register ICLIR 0 5 R XXXXXXXX Input Capture MSB 1 Register ICMIR 0x5B R XXXXXXXX Input Capture Trigger 2 Register ICT2R 0 5 00000000 Input Capture Source 2 Register ICS2R 0x5D Input Capture LSB 2 Register ICL2R 0 5 R XXXXXXXX Input Capture MSB 2 Register ICM2R Ox5F R XXXXXXXX Because the Input Capture channels synchronize their inputs to the peripheral clock fur ther divided by Timer 8 there is some delay between the input transition and when an interrupt is requested as shown below The status bits in the ICSxR are set coincident with the interrupt request and are reset when read from the ICSxR peRICLOCK Tg LJ LJ LJ LI LI TIMER 8 CPT INPUT INTERRUPT Each Input Capture channel has two inputs called the Start condition and the Stop condi tion Each of these two inputs can be programmed to come from one of four bits bits 1 3 5 or 7 in Parallel Port C D F or G The two inputs can come from the same or different pins and are edge sensitive Each input can be disabled rising edge sensitive falling edge sensitive or responsive to either edge polarity Either or both inputs can generate an Input Capture interrupt and either or both inputs can cause the current count to be latched Chapter 7 Miscellaneous Functions 105 Each Input Capture counter operat
391. while neither party is driving the clock CLK Mode 00 cik LIT LE LE LIE LIL CLK Mode 10 ss Pa EU fg Es l l C l l l l l en X m Figure 12 5 Clock Polarities Supported in Clocked Serial Mode In clocked serial mode the shift register and the data register work in the same fashion as for asynchronous communications However to initiate basic sending or receiving a command must be issued by writing to bits 7 6 of the control register for each byte sent or received One command is for sending a byte a different command is for receiving a byte and yet another command can initiate a transmit and receive at the same time for full duplex commu nication Alternatively a read or write to the Serial Ports A D Address registers SxAR elim inates the need to issue separate receive and transmit commands In clocked serial mode reading the data from the corresponding SxAR register automatically causes the receiver to start a byte receive operation eliminating the need for software to issue the Start Receive command Any data contained in the receive buffer will be read first before being replaced 182 Rabbit 3000 Microprocessor User s Manual with new incoming data Similarly writing the data to the SxAR register causes the trans mitter to start a byte transmit operation eliminating the need for the software to issue the Start Transmit command The effect of these c
392. with communications channels except perhaps at the extreme upper data rates More details on dealing with the clock variation introduced are available elsewhere see Chapter 16 AC Timing Specifications If the input oscillator frequency is 4 MHz or less the spectrum spreader modulation of fre quency will enter the audio range of 20 kHz or less and may generate an audible whistle in FM stations For this reason it may be desirable to disable the spreader for low speed oscil lators where it is probably unnecessary anyway However in practical cases the whistle may not be audible due to the very low level of the interference from a system with low oscillator frequency and the spectrum spreader engaged Each halving of clock frequency reduces the amplitude of the harmonics at a given frequency by 6 dB or more The effect of pure harmonic noise on an FM station is to either completely block out a sta tion near the harmonic frequency or to disturb reception of that station If the spectrum spreader is engaged then interference will be spread across the band but will generally be Chapter 15 EMI Control 215 so low as to be undetectable except perhaps for extremely weak stations The effect of a pure harmonic on TV reception is to create a herringbone pattern created by a harmonic falling within the station s band If the spreader is engaged the pattern will disappear unless the station is very weak in which case the interference will be
393. write protect for physical address 0 0000 1 Enable 64K write protect for physical address 0 0000 0 Disable 64K write protect for physical address 0xD0000 0xDFFFF 2 1 Enable 64K write protect for physical address 0xD0000 0xDFFFF 0 Disable 64K write protect for physical address 0xC0000 0xCFFFF 1 Enable 64K write protect for physical address 0xC0000 0xCFFFF 0 Disable 64K write protect for physical address 0 0000 1 Enable 64K write protect for physical address 0xBO000 OxBFFFF 0 Disable 64K write protect for physical address 0x A0000 0x AFFFF 1 Enable 64K write protect for physical address 0x A0000 0x AFFFF 0 Disable 64K write protect for physical address 0 90000 0 9 i 1 Enable 64K write protect for physical address 0x90000 0x9FFFF 0 Disable 64K write protect for physical address 0x80000 0x8FFFF j 1 Enable 64K write protect for physical address 0x80000 0x8FFFF Table B 9 Write Protect Segment x Register Write Protect Segment x Register WPSAR Address 0x0480 WPSBR Address 0x0484 Bit s Value Description 7 4 These bits are reserved and should be written with zeros 3 0 When these four bits match bits 19 16 of the physical address write protect that 64K range in 4K increments using WPSxLR and WPSxHR 288 Rabbit 3000 Microprocessor User s Manual Table B 10 Write Protect Segment x Low Register
394. y characters 193 extended asynchronous mode registers 176 extended registers clocked se rial mode Ports A D 177 extra stop bits parity 194 HDLC mode extended regis ters Ports 178 HDLC mode status registers Ports 172 interrupt service routines 192 Interrupts 179 long stop registers 169 master slave protocol 196 Modbus 196 periodic interrupts 194 Ports synchronous com munication 187 receive serial data timing 181 registers 164 status registers 170 status registers clock serial ports A D 171 transmit serial data timing 180 use to generate periodic inter 194 slave port 53 199 applications 208 hardware design 204 messaging protocol 208 protocols 208 R W cycles 201 Iegisters 205 typical connections 204 sleepy mode 233 235 specifications DC characteristics 68 I O buffer sinking and sourc ing limits 69 power consumption 231 spectrum spreader 80 86 EMI mitigation 214 181615
395. y if the transmitter is ready to start sending another byte but the transmit buffer is empty 1 0 00 These bits are always zero in clocked serial mode Chapter 12 Rabbit Serial Ports 171 Table 12 13 Status Register HDLC Mode Ports E and F only Serial Port x Status Register SESR Address 0xCB SFSR Address 0xD3 Bit s Value Description HDLC mode only 0 The receive data register is empty 7 1 There is a byte in the receive buffer The serial port will request an interrupt while this bit is set The interrupt is cleared when the receive buffer is empty 00 The byte in the receive buffer is data 01 The byte in the receive buffer was followed by an Abort 6 4 10 The byte in the receive buffer is the last in the frame with valid CRC 11 The byte in the receive buffer is the last in the frame with a CRC error 0 The receive buffer was not overrun 5 1 The receive buffer was overrun This bit is cleared by reading the receive buffer 0 The transmit buffer is empty The transmit buffer is not empty The serial port will request an interrupt when 3 1 the transmitter takes a byte from the transmit buffer unless the byte is marked as the last in the frame Transmit interrupts are cleared when the transmit buffer is written or any value which will be ignored is written to this register 00 Transmit interrupt due to buffer empty condition Transmitter finished sending
396. y on Z180 or Rabbit based controllers This can result if for example there are five active interrupt routines and each turns off the interrupts for at most 20 us The intention in the Rabbit is that most interrupting devices will use priority 1 level inter rupts Devices that need extremely fast response to interrupts will use priority level 2 or 3 interrupts Since code that runs at priority level 0 or 1 never disables level 2 and level 3 interrupts these interrupts will take place within about 20 clocks the length of the longest instruction or longest sensible sequence of privileged instructions followed by an unprivi leged instruction It is important that the user be careful not to overdisable interrupts in critical code sections The processor priority should not be raised above level 1 except in carefully considered situations The effect of the processor priority on interrupts is shown in Table 3 1 The priority of the interrupt is usually established by bits in an I O control register associated with the hard ware that creates the interrupt The 8 bit interrupt register IP holds the processor priority in the least significant 2 bits When an interrupt takes place the IP register is shifted left 2 positions and the lower 2 bits are set to equal the priority of the interrupt that just took place This means that an interrupt service request ISR can only be interrupted by an interrupt of higher priority unless the priority is explicit
397. ynamic C constants Chapter 8 Memory Interface and Mapping 127 8 8 How the Compiler Compiles to Memory The compiler actually generates code for root code and constants and extended code and extended constants It allocates space for data variables but does not generate data bits to be stored in memory In any but the smallest programs most of the code is compiled to extended memory This code executes in the 8K window from E000 to FFFF This 8K window uses paged access Instructions that use 16 bit addressing can jump within the page and also outside of the page to the remainder of the 64K space Special instructions particularly long call long jump and long return are used to access code outside of the 8K window When one of these transfer of control instructions is executed both the address and the view through the 8K window or page are changed This allows transfer to any instruction in the 1M memory space The 8 bit XPC register controls which of the 256 4K pages the 8K window aligns with The 16 bit PC controls the address of the instruction usually in the region E000 to FFFF The advantage of paged access is that most instructions continue to use 16 bit addressing Only when an out of range transfer of control is made does a 20 bit transfer of control need to be made The beauty of having a 4K minimum step in page alignment while the size of the page is 8K is that code can be compiled continuously without gaps caused by change of pag

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Rabbit ® 3000 Microprocessor User`s Manual