DG24 User`s Manual - Chicago Classic Computing
Contents
1. 2 3 2 3 Interrupt Disable Jumper Positions 2 4 3 1 DG24 Block disons nemli 3 1 8255 DESCRIPTION DATA SHEET REPRINT 4 8255A Block Diagram Showing Group A and NT Group B Control Functions 3 5 5 Basic Mode Definitions and Bus Interface EE 3 6 6 Mode Definition Format NP donk aie kee 3 6 7 Bit Set Reset Format 2 s osos c EIAS seme der 8 MODE 1 Input RAM 3 11 9 1 Strobed Input Re li mE CD 3 11 10 MODE 1 Output alaan eve a DI TEM 3 12 11 1 Strobed IIR Mp RA 3 12 12 Combinations of MODE 1 3 13 13 MODE Control Word E ne a 3 14 Pt MODE Zi dd UE a ALES 3 14 15 MODE 2 A A a AA 3 14 16 MODE 1 4 Combinations 3 15 17 MODE 1 Status Word Format MEER ee 3 16 18 MODE 2 Status Word Format oo een 3 16 19 Printer Interface c Mei m dee oc 3 17 20 Keyboard and Display 3 17 21 Keyboard and Terminal Address Interface Sle iret 3 17 22 Digital to Analog Analog to Digital 2 3 18 23 Basic CRT Controller Interface 3 18 24 Basic Floppy Disc Interface oo oo 2 2 IL 3 18 25 Machine Tool Controller Interface T IL LI I 3 18 1 DG24 P4 Con2. ea woe ec TRO tor MODE 0 Basic Input MODE 0 Basic Output 3 7 intel MODE 0 Port Definition a o Groupe PORT C PORT C Du os oo e o 0 oureur oursur o OUTPUT OUTPUT o o 1 ovreur 1 oursur input o 1 0 oursur oureur 2 eur OUTPUT o 3 1 1 04007 weur 1 ineur 1 0 o oureut_ s 04507 oureur 1 o o 1 eur oursur 9 outeur input 1 To 1 1 0001 11 eur INPUT 1 1 0 o eur 12 00107 ovreur 1 1 o input eur 00007 ineur 1 1 1 e peor eur va iweur 0 oureur 1 1 1 1 per MODE 0 Configurations CONTROL WORD 0 D D D D D O D CONTROL WORD 22 D D D 0 D D 0 D PA PA PA PA PC PC PC 0 05 PCy PC CONTROL WORD 43 D D 0 D EE ep CONTROL WORD 41 D De Ds D Dy D 0 0 PA PA PA PA PC PCy PCy PC 0 YE PC CONTROL WORD 4 D CECECECECA PA PC PC D 2 De PE PE PB PB CONTROL WORD 5 D D Ey 2 D PC PC 0 0 PE Py CONTROL WORD 6 0 0 D 0 D CONTROL WORD 28 D D D 0 P 0 D Dg
3. Figure 22 Digital to Analog Analog to Digital INTERRUPT REQUEST CRT CONTROLLER fi CHARACTER GEN A REFRESH BUFFER CURSOR CONTROL SHIFT CONTROL MODE 1 OUTPUT DATA READY ACK BLANKED BLACK WHITE ROW STB COLUMN STB CURSOR STB MODE 0 OUTPUT PB CURSOR ROW COLUMN ADDRESS HEY Figure 24 Basic Floppy Disc Interface tNT RRUPT REQUEST FLOPPY DISK CONTROLLER AND ORIVE OATA STR ACK DATA READY ACK OUT TRACK 0 SENSOR SYNC READY ge ENGAGE HEAD FORWARD REV PEAD ENABLE WAITE ENABLE DISC SELECT ENABLE CRC TEST GUEY LT MODE 0 OUTPUT Figure 23 Basic CRT Controller Interface INTERRUPT REQUEST BLEVEL PAPER TAPE READER MODE 1 18 ACK STOP GO 22554 MACHINE TOOL START STOP LIMIT SENSOR OUT OF FLUID MODE D NPUT CHANGE TOOL LEFT RIGHT UP DOWN MODE O HOR STEP STAOBE OUTPUT VERT STEP STROBE SLEW STEP FLUID ENABLE EMERGENCY STOP Figure 25 Machine Tool Controller tnterface Appendix A Specifications DG24 SPECIFICATIONS Interface IBM PC XT AT compatible No PC AT WAIT states required Jumper selectable base address mapped hex 200 300 240 340 280 380 200 200 Jumper selectable interrupts Both 8255 interrupts INTRA INTRB are provided PC IRQ channels Supported 2 7 Digital The DG24
4. CONTROL WORD 9 0 0 0 D 02 0 0 CONTROL WORO 10 5 D 0 D 0 D D CONTROL WORD 7 0 0 0 BD D 0 0 CONTROL WORD 11 0 D U D D D 3 9 CONTROL WORD 12 CONTROL WORD 14 D D D Dy 0 D D D CONTROL WORD 413 CONTROL WORD 18 D D Ds D D Dz D D D 0 Db D D PAPA PC 0 00 0706 PB PB Operating Modes f Mode 1 Basic Functional Definitions Two Groups Group A and Group B Each group contains one 8 bit data port and one 4 bit MODE 1 Strobed Input Output This functional con control data port figuration provides a means for transferring I O data to or from a specified port in conjunction with strobes or e The 8 bit data port can be either input or output handshaking signals In mode 1 port and Port Buse Both inputs and outputs are atched the lines on port C to generate or accept these The 4 bit port is used for control and status of the shaking signals 8 bit data port o intel input Control Signal Definition STB Strobe Input low on this input loads data into the input tatch IBF Input Buffer Full F F A high on this output indicates that the data has been loaded into the input latch in essence an acknowledgement is set by STB input being low and is reset by the rising edge of the RD input I
5. ADDRESS BUS CONTROL BUS DATA BUS t TI D Da Ay A 68786 PC PC PAPA PC PC oe PB PB CONTROL CONTROL PAPA OR 1 O OR O A Je Te P8 PB VO lt PA PA CONTROL d Figure 5 Basic Mode Definitions and Bus Interface 3 6 CONTROL WORO GROUP B PORT CILOWER INPUT 0 OUTPUT PORTB Ye INPUT 0 OUTPUT MODE SELECTION i 0 MODE 1 MODE 1 GROUP A PORT C UPPER 1 INPUT 0 OUTPUT PORT A 1 INPUT 0 OUTPUT MODE SELECTION 00 MODE 0 01 MODE 1 1X MODE 2 MODE SET FLAG 1 ACTIVE Figure 6 Mode Definition Format The mode definitions and possible mode combinations may seem confusing at first but after a cursory review of the complete device operation a simple logical ap proach wlil surface The design of the B255A has taken into account things such as efficient PC board layout control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic Such design represents the maximum use of the available pins Single Bit SeUReset Feature Any of the eight bits of Port C can be Set or Reset using single OUTput instruction This feature reduces software requirements in Control based applications When Port C is be ng used as status control for Port A or B CONTROL WORO these bits can be set or reset
6. p ws a ap 10 tor Dana Fi Ate neo 0 3 s nu Time Been READ napr war me A C CHARACTERISTICS Continued WRITE Parameter Address Stable Before WRITE Address Stable After WRITE WRITE Pulse Width Data Valid to WRITE T E Data Valid After WRITE WA DW two OTHER TIMINGS Parameter Min Max twB WR 1 to Output a 3 tin Peripheral Data Before RD tun Peripheral Data After RD BEI tak ACK Pulse Width tsT STB Pulse Width 3 Per Data Before T E of STB Per Data Atter of STB Oto Output ACK 1 to Output Float WR 1 to OBF 0111 OBF 1111 STB IBF 1111 1 to IBF 0 11 taiT Oto INTR 0111 ts r STB 1 to INTR 1 to INTR 1111 twit WR Oto INTR 011 31 PH AD ILE N ikp 2 tAOB trip 2 00 450 NOTES 1 Test Conditions C 150pF 2 Period of Reset pulse must be at least 504 during or after power on Subsequent Reset pulse be 500 ns min 3 INTRt may occur as early as WR A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT INPUT OUTPUT DEVICE UNDER 2 0 TEST gt TEST POINTS lt 0 8 100 pF 9 45 TESTING INPUTS ARE DRIVEN 2 4 FORALOGIC ANDO 45v FOR ALOGIC 0 TIMING MEASUREMENTS ARE MADE AT 20V FORA
7. 1 shows how the DG24 maps the PPI registers to four contiguous I O addresses beginning with the base address you selected in Chapter 2 Table 3 1 PPI Register DG24 I O Address Assignments PPI Register Base Address Port A Port B Port C Control Word The 8255 PPI is a versatile digital I O interface chip your application will determine how the I O ports should be configured and the different operating modes selected The accompaning data sheet reprinted by permission of Intel Corporation Copyright 1981 presents a very good discussion of controlling this chip 8255 DESCRIPTION The first section of the data sheet entitled 8255A Functional Description gives a general explanation of the I O ports This and the information contained in the section entitled 8255A Operational Description will allow you to determine how to most efficiently utilize the I O ports for your The first part of the Operational Description explains how the Control Word is used to select the operating modes of the PPI and is also used to individually set or reset the Port C bits This bit set reset feature is useful for controlling separate bits without effecting the other bits of Port C The bit set reset feature can be used with Port C bits only If your application requires the use of interrupts you will also want to read the information under the heading Interrupt Control Functions This section describes how the Interrupt Enabl
8. Set Reset Feature 3 6 Interrupt Control Functions 3 7 Operating Modes zu u S u C 3 7 MODE 0 Basic Input Output T T 3 7 MODE 0 Definition 3 8 MODE 0 Configurations 3 8 MODE 1 Strobed Input Output 2222 ama Input Control Signal Definition 2 3 11 Output Control Signal Definition 2 2 2 3512 Combinations of MODE 1 3 13 MODE 2 Strobed Bidirectional Bus I O 3 13 Bidirectional Bus I O Control Signal Definition 3 13 e a Output Operations rin 3 13 Input Operations 3 13 Mode Definition Summary 3 16 Special Mode Combination Considerations 3 16 Source Current Capability on Port B and vo Lr 3 16 Reading Port C Status Applications of the 8255A 5 6 as Appendix A Specifications DG24 Specifications acd arde RE te 8255 SDeclHicatlOnS u a lk RUE EROTIC Appendix B 1 0 Connector DG24 Connector Pin gt DG24 P4 Connector Mating Connector n TUER Appendix C References Appendix D Warranty i Illustrations Page 2 1 DG24 Component Locations 2 2 2 2 DG24 I O Port Address
9. YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE Real Time Devices Inc 1930 PARK FOREST AVENUE P O BOX 906 STATE COLLEGE PENNSYLVANIA 16804 814 234 8087 TELEX 4948141 SEDACOG
10. by using the Bit Set Reset op eration just as if they were data output ports Interrupt Control Functions When the 8255 is programmed to operate in mode 1 or dd mode 2 control signals are provided that can be used as 0 RESET interrupt request inputs to the CPU The interrupt re quest signais generated from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset function of port C BIT SELECT This function aliows the Programmer to disallow or allow a specific 1 0 device to interrupt the CPU without affecting any other device in the interrupt structure INTE flip flop definition BIT SET RESET FLAG 0 ACTIVE BIT SET INTE is SET Interrupt enable BIT RESET INTE is RESET nterrupt disable Note Ali Mask flip flops are automatically reset during Figure 7 Bit Set Reset Format mode selection and device Reset Operating Modes Mode 0 Basic Functional Definitions e Two 8 bit ports and two 4 bit ports _ Any port can be input or output MODE 0 Basic Input Output This functional configura Outputs are latched tion provides simpie input and output operations for e inputs are not latched each of the three ports No handshaking is required 16 different Input Output configurations are possible data Is simply written to or read from a specified port in this Mode w lan AO E ae 7 0706
11. utilizes an 8255 programmable peripheral interface PPI chip It provides 24 digital I O lines which are divided into three 8 bit ports A B and C Port A Port B and each half of Port C may be individually programmed as input or output In addition strobed I O operations may be performed using some of the Port C lines to control data transfers The three modes of operation are summarized below Mode 0 Basic I O provides simple input and output operations for each port Data is written to or read from a specified port Mode 1 Strobed I O uses handshaking signals to transfer data through Port A or Port B Interrupts may be utilized Mode 2 Strobed Bidirectional I O Port A is used as a bidirectional data bus Data transfers occur in conjunction with handshaking signals similar to Mode 1 operation Interrupts may be utilized Miscellaneous Outputs PC bus sourced Reset Driver 45 Vdc 12 Vdc Digital ground Software Features Sample BASICA programs are provided which demonstrate the control of each of the PPI operating modes Example CALL statements are also included to show how the 8255 may be used for high speed applications A complete directory of all software included with the DG24 is listed on the accompanying disk Electrical Current requirements V 20 Mechanical Connectors 40 pin right angle shrouded male header with ejector tabs Edge connector IBM PC XT AT compatible Envi
12. voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by REAL TIME DEVICES acts of God or other contingencies beyond the control of REAL TIME DEVICES OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN REAL TIME DEVICES EXCEPT AS EXPRESSLY SET FORTH ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A I PARTICULAR PURPOSE AND REAL TIME DEVICES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL REAL TIME DEVICES BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OF OR INABLILITY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITATIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EACLE SIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND
13. 40 258 6230 040 601 o 3M 3417 7040 Robinson Nugent IDS C40PK C SR TG MIL C 83503 M83503 7 09 Appendix References 1 2 3 4 5 6 7 8 Eggebrecht Lewis C Interfacing To The IBM Personal Computer Howard W Sams amp Co Inc Indianapolis IN 1983 ISBN 0 672 22027 Jourdain Robert Programmer s Problem Solver for the IBM PC XT amp AT Prentice Hall Press New York NY 1986 ISBN 0 89303 787 7 Morgan Christopher L and Waite Mitchell 3086 8088 16 Bit Microprocessor Primer BYTE McGraw Hill Peterborough NH 1982 ISBN 0 07 043199 4 Lafore Robert Assembly Language Primer for the IBM PC amp XT New American Library New York NY 1984 ISBN 0 452 25711 5 SM Peter and Socha John Peter Norton s Assembly Language Book for the IBM PC Prentice Hall Press New York NY 1986 ISBN 0 13 661901 0 Abel Peter Assembler for the IBM PC and PC XT Reston Publishing Company Inc Reston VA 1984 ISBN 0 8359 0153 Scanlon Leo IBM PC Assembly AMELE E Robert J Brady Co Bowie MD 1983 ISBN 0 89303 241 7 Angermeyer John Jaeger Kevin MS DOS Developer s Guide Howard W Sams amp Co Indianapolis IN 1986 ISBN 0 672 22409 7 9 Duncan Ray Advanced MSDOS Microsoft Press Redmond WA 1986 ISBN 0 914845 77 2 10 Rugg Tom and Feldman Phil Turbo Pascal Program bbs Que Corp
14. 8255 used on the DG24 is capable of 10 MHz transfer rates WAIT states are not required when using a PC AT machine A directory of the software included with your DG24 as well as a brief description of each program is listed in the file README DOC on the Program Disk INTERRUPT CONSIDERATIONS The interrupts generated in PPI Mode 1 and Mode 2 operation may be jumpered to any of the PC interrupt channels 2 7 The channel selection is made by jumpering pins on the DG24 P3 connector as explained in the Interrupt Channel Selection description in Chapter 2 The PPI interrupts must be enabled by writing a 1 to the INTE mask bit as described the data sheet reprint section entitled 8255A Operational Description Interrupt Control Functions The INTE mask bits are disabled during power up reset and whenever the PPI mode is changed Before you attempt to use interrupts be certain you are familiar with the procedure for intializing the interrupt vectors and the PC s interrupt controller and setting up the interrupt handling routines Reference 1 in Appendix C contains a very good description of the PC s system interrupts 8255 DESCRIPTION DATA SHEET REPRINT intel 8255A FUNCTIONAL DESCRIPTION Group A and Group B Controls The functional configuration of each port is program med by the systems software in essence the CPU out puts a control word to the 8255 The control word con tains information such as mode bi
15. C 1 2 Chapter 2 Installation The DG24 plugs into any expansion slot including a short slot of an IBM PC XT AT or compatible computer It may be advantageous therefore to choose an available short slot inside your computer The board s I O address and interrupt channel are jumper selectable Preventing possible contention with other devices simply involves changing three jumpers If the board address is unjumpered or incorrect the DG24 will not operate Before installing the board into your computer the jumper selections must be made All connections to external signals are made through one 40 pin I O connector which can be accessed through the rear of the computer after the board is installed JUMPER SETTINGS Base Address Selection Connector P2 To select the board s base I O address the jumper on the connecter labeled PZ must be positioned to correspond to the address desired The jumper should be placed horizontally across the pair of header pins beside the base address you select see Figure 2 1 The base addresses labeled beside connector P2 are hexadecimal values 2 1 Fig 2 1 DG24 Component Locations 2 2 N UM E When choosing a base address be careful not to use one that will cause contention with another peripheral The DG24 occupies 16 I O addresses beginning with the base address selected however only four addresses are actually used Chapter 3 Controlling th
16. DG24 User s Manual Real Time Devices DG24 User s Manual A User s Guide to the DG24 Digital I O Interface Real Time Devices Inc 1930 Park Forest Avenue P O Box 906 State College PA 16804 First Printing April 1987 Copyright 1987 All rights reserved Real Time Devices Inc Printed in U S A Contents Page uou Be ee dud t S k ele ite AE 111 Tables S PITE 111 Chapter 1 Introduction 1 1 Chapter 2 Installation Dj lt F e gt 0 4 2 1 2 1 Interrupt Channel Selection Connector P3 2 3 Board Installation JA 2 5 e e 8 e e e e Chapter 3 Controlling the 8255 PPI 3 1 8255 Description 3 2 3 3 Programming the DG24 ri 3 4 Interrupt Considerations u 3 4 8255 Description Data Sheet Reprint oaao a a ae rin 3 5 8255A Functional Description 3 5 Group and Group B Controls 3 5 FOIS AGB ander oou tee fos 3 5 8255A Operational Description 3 6 S uos oio sema eoi m a e e 3 6 Single Bit
17. LOGIC 1 AND 08V FOR A LOGIC 0 Vra IS SE VARIOUS VOLTAGES DURING TESTING TO GUARANTEE THE SPECIFICATION WAVEFORMS MODE 0 BASIC INPUT Tar SAND C ini MODE 0 BASIC OUTPUT WANEFORMS Continued MODE 1 STROBED INPUT INPUT FROM e __ m PERIPHERAL WAVEFORMS Continued MODE 2 BIDIRECTIONAL DATA FROM 8080 TO 8255 poen u rol lol _ BUS j DATA from DATA FROM PERIPHERAL 8255 T 8255 TO PERIPHERAL DATA FROM 22 8255 TO 8080 NOTE sequence where WR occurs before and STB occurs before RD is permissible _ INTR gt IBF MASK STB AD MASK WRITE TIMING 77 READ TIMING law tw a lt two DATA BUS HIGH IMPEDANC HIGH IMPEDANCE Appendix D VO Connector D 5 Digital Gnd 21 5 Volts 1 2 22 3 2 1 23 4 Digital Gnd 24 5 25 6 26 Digital Gnd 7 PA7 27 PA6 8 PAS 28 4 9 29 PA2 10 PA x 30 PAO 11 PC7 31 PC 12 PCS 32 PC4 13 PC3 33 2 14 PCI 34 PCO _ 15 PB7 35 pin 16 PBS 36 PB4 1 17 PB3 37 PB2 18 PB1 38 PBO 19 12 Volts 39 RESET DRV 20 12 Volts 40 Digital Gnd Fig B 1 DG24 P4 Connector Pin Assignment Table B 1 DG24 P4 Connector Mating Connector DG24 P4 Connector P4 Mating Connector KEL AM Inc 6201 0
18. NTR Interrupt Request A high on this output can be used to interrupt the CPU when an input device is requesting service INTR is set by the STB is a one IBF isa one and INTE is a one It is reset by the falling edge of RD This procedure allows an input device to request service from the CPU by simply strobing its data into the port INTE A Controlled by bit set reset of PC 4 INTE B Controlled by bit set reset of 18 all iBF INPUT FROM _ PERIPHERAL MODE 1 PORT Al CONTROL WORD D D 0 D D O D CONTROL WORD 0 D 0 O D D O ISSO Figure 8 MODE 1 Input Figure 9 MODE 1 Strobed Input intel Output Control Signal Definition OBF Output Butter Full F F The OBF output will go low to indicate that the CPU has written data out to the specified port The OBF F F will be set by the rising edge of the WR input and reset by ACK Input being low ACK Acknowledge Input A low on this input informs the 8255A that the data from port A or port B has been ac cepted n essence a response from the peripheral device indicating that it has received the data output by the CPU y x INTR Interrupt Request A high on this output be used to interrupt the CPU when an output device has ac cepted data transmitted by the CPU INTR is set when ACK is a one OBF is a one and INTE is a one It is rese
19. Note that INTRA and INTRB must each use a separate PC interrupt channel If interrupts are not used the jumpers must be positioned as shown in Figure 2 3 2 3 Disable Disable INTRB INTRA B A 17117 IRQ 55 ooo 4 ooo 5 0006 Ooo 7 Fig 2 3 Interrupt Disable Jumper Positions The DG24 interrupts are preset to the disabled position For future reference you may wish to record the interrupt channel assignments in Table 2 1 Table 2 1 DG24 User Selected Options I O Base Address hex decimal INTR IRQ Channel Selection INTRA IRQ INTRB IRO Chapter 3 Controlling the 8255 PPI describes considerations for using the DG24 interrupts BOARD INSTALLATION After selecting the base address and men APA DAL the DG24 may be installed inside the computer le TURN OFF THE POWER TO YOUR COMPUTER FIRST Refer to the owner s manual for your computer and remove the top cover 2 Select the expansion slot you ish to use and remove the corresponding blank bracket from the rear panel of the computer 3 Close both ejector latches on the DG24 1 0 connecter and orient the board inside the computer so that the connector protrudes through the rear of the computer and the card edge connector lines up with the selected expansion slot connector 2 4 4 After you are certain the board lines up correctly push down on the metal bracket tab and the top of the board until the board is seated firmly in the expansi
20. ORT IB T PORT RIT PORT C 45 VOLTS 8 VOLTS Figure 4 8225A Block Diagram Showing Group A and Group B Control Functions 3 5 intel 8255A OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be select ed by the system software Mode 0 Basic Input Output Mode 1 Strobed Input Output Mode 2 Bi Directional Bus When the reset input goes high all ports will be set to the input mode i e all 24 lines will be in the high im pedance State After the reset is removed the 8255A can remain in the input mode with no additional initialization required During the execution of the system program any of the other modes may be selected using a single output instruction This allows a single 8255 to service a variety of peripheral devices with a simple software maintenance routine The modes for Port A and Port B can be separately defined while Port C is divided into two portions as required by the Port and Port B definitions All of the output registers in cluding the status flip flops will be reset whenever the mode is changed Modes may be combined so that their functional definition can be tailored to almost any structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display compu tational results Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt driven basis
21. e INTE mask is used to enable the INTRA and INTRB interrupt signals generated when using Modes 1 and 2 The minder of the Operational Description discusses the operating modes in detail This information includes timing diagrams examples of how the operating modes may be combined and describes the Port C Status Word used in Modes 1 and 2 Port A and Port B source current capabilities are also defined Values referenced on the timing diagrams are defined in Appendix A Specifications The section entitled Applications of the 8255A gives some practical examples of how the PPI can be used for specific applications 3 2 MODE SELECTION Once you have decided how to define the operating modes of Ports A B and C determine the data that you will need to write to the Control Word refer to the 8255A Operational Description Figure 6 of the reprint For example to select Port Mode 1 Input Port B Mode 0 Output PC 0 1 2 Mode 0 Input PC 6 7 Mode 0 Output you would write the following data Data 7 6 5 4 3 2 1 0 _ Control wad Data Mode Set Port Port B 0 1 2 Flag Input Mode 0 Input Port A 6 7 Port B Mode 1 Output Output Note that PC 3 4 and 5 are used for the Port A handshaking and interrupt signals and are therefore not available for I O 8255A Operational Description Figure 8 however PC 0 1 2 6 and 7 can be used for digital I O The int
22. e 8255 PPI explains the function of these four addresses Figure 2 2 shows how the PC s I O port address bits are decoded by the DG24 Address Bit 10 9 8 7 6 RES E TTT PO x Done cae l d PPI Register Base Address Selected rr pore afol erorc contro xo x olol xao wo lolita xs ES pene Fig 2 2 DG24 I O Port Address Decode The DG24 base address has been preset to X 200 For future reference you may wish to record the base address you selected in Table 2 1 If the base address is changed from the preset value of X 200 the example software provided with the DG24 will need to be modified to reflect the new value The procedure to do this is explained in the comments which accompany each of the sample programs Interrupt Channel Selection Connector P3 The DG24 may be configured to generate interrupts during PPI Mode 1 or Mode 2 operation The two PPI interrupts INTRA and INTRB are available at the DG24 P3 connector and are labeled A and B across the top of the connector To select the PC interrupt channels used to service these interrupts position the jumpers on the connecter labled P3 to correspond to the desired interrupt channel numbers The jumpers should be placed horizontally across the pair of header pins corresponding to INTRA or INTRB and beside the interrupt channel number see Figure 2 1
23. equence where WR occurs before ACK and STB occurs before RD is permissible mm ME nm nn e 3 14 D YA FROM 8255A TO 8080 MODE 2 AND MODE 0 INPUT CONTROL WORD D D D D 0 D D D DB 1 INPUT 0 OUTPUT MODE 2 AND MODE 1 OUTPUT OBF CONTROL WORD m A 0 0 D D D4 0 0 O Ib DAT E eds ve 10 GBP WR INTR MODE 2 AND MODE 0 OUTPUT CONTROL WORD D D D 0 0 D D D L Ir oto je 1 INPUT 0 OUTPUT MODE 2 AND MODE 1 INPUT CONTROL wORD 0 0 0 D D O Do RD 0 WR Figure 16 MODE Combinations 3 15 Mode Definition Summary Special Mode Combination Considerations There are several combinations of modes when not ali of the bits in Port C are used for control or status The remaining bits can be used as follows If Programmed as Inputs All input lines can be accessed during a normal Port C read If Programmed as Outputs Bits C upper PC PC4 must be individually accessed using the bit set reset function Bits in C lower PC3 PCg can be accessed using the bit set reset function or accessed as a threesome by writing into Port C Source Current Capability on Port B and Port C Any set of eight output buffers selected randomly from Ports B and C can source 1mA at 1 5 volts This feature allows the 8255 to directly drive Darlington type dr
24. errupt signal generated on PC 3 may be jumpered to one of the the PC s interrupt channels The interrupt channel selection was described in Chapter 2 Finally you will need to write the data to the Control Word to select the operating modes of the ports Refer to Table 3 1 to determine the address of the Control Word To select the operating modes used in the above example the data X A1 would be written to I O location X 203 DG24 Base Address X 200 The following BASICA statement will write this data to the Control Word OUT amp H203 amp HA1 If your application will require changing the operating modes of the I O ports be aware that all output registers and status flags are reset whenever the mode is changed Also the Control Word can only be written into no Read operation of the Control Word Register is allowed 3 3 PROGRAMMING THE DG24 Due to the versatility of the 8255 PPI it would not be possible to provide utility software flexible enough for every application However the software included with your DG24 shows some example programs for controlling each operating mode These programs are written in BASICA and are extensively commented Also included are examples of CALL statements which are used from BASICA These CALL statements envoke assembly language subroutines which provide for a more efficient and faster execution of a routine CALL statements would be used for high speed data transfers Because the
25. ges the software interface between the device and the CPU The functional definition of the 8255A Is programmed by the service routine and becomes an extension of the system software By ex amining the l O devices Interface characteristics for both data transfer and timing and matching this intor mation to the examples and tables In the detailed opera tional description a control word can easily be devel oped to initialize the 8255A to exactly fit the applica tion Figures 19 through 25 present a few examples of typical applications of the 8255A INTEMRUPT REQUEST HIGH SPEED PRINTER DATAREADY ACK PAPER PEED FORWARQO REV RIBBON CARRIAQE SEN MODE 1 OUTPUT CONTROL LOGIC AND ORIVERS INTERRUPT RMtQUEST Figure 19 Printer interface 3 17 INTERRUPT REQUEST DECODED KEYBOARD MODE 1 INPUT CONTROL STROBE BURROUGHS SELF SCAN DISPLAY MODE 1 OUTPUT BACKSPACE CLEAR DATA READY ACK BLANKING CANCEL WORO INTERRUPT REQUEST Figure 20 Keyboard and Display Interface INTEARUPT REQUEST d FULLY MODE 8 DECODED UNPUY 7 pa KEYBOARD Pa SHIFT CONTROL STROBE ACKNOWLEDGE Figure 21 Keyboard and Terminal Address Interface MODE 0 OUTPUT CONVERTER ANALDG OUTPUT IDACI STB DATA OUTPUT EN BIT SET RESET SAMPLE EN AD CONVERTER ADC ANALOG INPUT MODE Q INPUT
26. ivers and high voltage displays that require such source current Reading Port C Status In Mode O Port C transfers data to or from the peripheral device When the 8255 is programmed to function in Modes 1 or 2 Port C generates or accepts hand shaking signals with the peripheral device Reading the contents of Port C T GROUPAONLY lt gt MODE 0 OR MODE 1 ONLY allows the programmer to test or verify the status of each peripheral device and change the program flow accordingly There is no special instruction to read the status informa tion from Port C A normal read operation of Port C is executed to perform this function INPUT CONFIGURATIDN D Ds 0 0 0 D D Do OUTPUT CONFIGURATION D a D D D VT gt v M QROUP A GROUP B Figure 17 MODE 1 Status Word Format D Di Dy D 0 0 0 ere mr pem EEK S wes saa s ee GROUP A GROUP B DEFINED BY MODE 0 OR MODE 1 SELECTION Figure 18 MODE 2 Status Word Format intel APPLICATIONS OF THE 8255A The 8255A is a very powerful tool for Interfacing peripheral equipment to the microcomputer system 11 represents the optimum use of avallable pins and is flex 1616 enough to interface almost any 1 O device without the need for additional external logic Each peripheral device in a microcomputer system usually has a service routine associated with it The routine mana
27. nd outputs are latched The 5 bit control port Port C is used for control A Bidirectional Bus Control Signal Definition INTR interrupt Request A high on this output can be used to interrupt the CPU for both input or output opera tions 3 13 and status for the 8 bit bi directional bus port Port Output Operations Output Buffer Ful The output will go low to indicate that the CPU has written data out to port A ACK Acknowledge A low on this input enables the tri state output buffer of port A to send out the data Otherwise the output buffer will be in the high im pedance state INTE 1 The INTE Flip Flop Associated with OBF Con trolted by bit set reset of PCg Input Operations STB Strobe Input STB Strobe input A low on this Input loads data into the input latch IBF Input Buffer Full F F A high on this output in dicates that data has been loaded into the input latch INTE 2 The INTE Flip Flop Associated with IBF Con troiled by bit seUreset of PC CONTROL WORD De D D D D D D 1 INPUT 0 OUTPUT PORT B Y INPUT 0 OUTPUT GROUP B MODE 0 MODE 0 1 MODE 1 Figure 13 MODE Control Word E PERIPHERAL BUS DATA FROM PERIPHERAL TO 8255A Figure 14 MODE 2 DATA FROM 62554 TO PERIPHERAL Figure 15 MODE 2 Bidirectional NOTE Any s
28. nector Pin Assignment 2 2 B 1 Tables Page 2 1 DG24 User Selected Options T 2 22 T LL 2 4 3 1 PPI Register DG24 I O Address Assignments LLL e 1 DG24 P4 Connector Mating Connector B 1 111 eet SS A Chapter 1 Introduction The DG24 is a highly versatile digital I O port for the IBM PC XT AT or compatible computer The board uses the popular 8255 Programmable Peripheral Interface PPI chip and provides for the control or monitoring of 24 digital I O signals The 8255 used is capable of 10 MHz transfer rates and therefore does not require WAIT states when using a PC AT The DG24 s base address is jumper selectable and interrupts are supported The PPI may be configured in combinations of three basic modes of operation Basic I O Strobed I O and Bi directional Strobed I O Applications of the DG24 include instrument interfacing event sensing process control and automated testing All 24 digital lines as well as 12 and 5 volts the PC s reset signal and digital ground are accessible through a 40 pin header connector at the end of the board This connector is compatible with Real Time Devices XB40 I O extender board and XC40 expansion cable The XB40 consists of two 20 pin screw terminals and a prototype area The screw terminals allow wires to easily connect to the DG24 and the prototype area allows development
29. of custom application circuits The XC40 is a cable assembly which terminates in a 40 pin wire wrap header connector This connector is suitable for installation in standard per board material The software included with the DG24 provides sample programs for controlling each of the PPI operating modes Example CALL statements are also included for applications requiring high speed data transfers 1 1 This manual has been organized into three chapters with a group of appendices containing reference material CHAPTER 1 briefly describes the DG24 operating featured capability and software CHAPTER 2 explains how to install the DG24 in your computer This incudes selecting the base address and interrupt E and connecting signals to the I O connector i CHAPTER 3 describes how to control the DG24 s PPI Detailed specifications of the PPI are provided which explain its various operating modes and communication with the Control Word and I O pcrts Some considerations are also given if you require the use of interrupts APPENDICES contain technical information related to your DG24 This includes the DG24 and 8255 PPI specifications I O connector pin out and connector types References and dii d information are also provided Every effort has been made to design a quality easy to use yet low cost digital I O interface board We are convinced that you wili find the DG24 to be a valuable intertacing tool for your P
30. on slot connector 5 Reinstall the screw that was remove with the blank bracket and replace the cover to your computer EXTERNAL CONNECTIONS Connector P4 All external connections to the DG24 are made to the I O connector labeled P4 see Figure 2 1 which is accessible through the rear panel of the computer after the board is installed The P4 mating connector type required is listed in Appendix B as well as the pin assignment of all signals associated with the DG24 To attach the mating connector first open the ejector tabs on the DG24 I O connector Then observing the keying of both connectors install the mating connector and push firmly until the tabs snap closed securing the connector in place This completes the installation your DG24 is now properly configured Next you must decide how to control the PPI for your specific application 2 5 2 6 Chapter 3 Controlling the 8255 PPI As shown in the block diagram Figure 3 1 the DG24 provides all the necessary interfacing signals to control the 8255 PPI 8 i T 7 8 8 eon a INTERRUPT E SELECTION ADDRESS BUS ADDRESS DECODE DATA BUS AQ A1 PORT DO D7 PORT Connector P4 RESET 12 Volts 5 Volts DIGITAL GROUND CONTROL BUS Fig 3 1 DG24 Block Diagram 3 1 These signals are used to communicate with the internal registers of the PPL Table 3
31. oration Indianapolis IN 1986 ew us 88022 vidis d p lt gt 2 Robinson Phillip R Use Turbo Brotes Osborne McGraw Hill Berkeley CA 1987 ISBN 0 07 881253 4 12 13 14 15 Kotta Elliot B Turbo Pascal A Problem Solving Approach Addison Wesley Publishing Inc MA 1986 ISBN 0 201 11743 6 Dooley George Szybist Daniel Interface Projects For the PC Real Time Devices Ies State College PA Dooley George Forth For Robot Control Robots ae Sep Vol 75 No 9 7 8 1985 Dooley George and Szybist Daniel Accessing the Analog World Chemical Engineering Aug 22 1983 Appendix D Warranty LIMITED WARRANTY Real Time Devices Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from REAL TIME DEVICES This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period REAL TIME DEVICES will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to REAL TIME DEVICES replaced pens and products become the property of REAL TIME DEVICES THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAMAGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input
32. ronmental Operating temperature O to 50 deg Centigrade Storage temperature 20 to 70 deg Centigrade Humidity O to 90 non condensing Size 3 875 X 4 500 Short slot Options XB40 Expansion Board XC40 Expansion Cable Warranty 1 year 8255 SPECIFICATIONS intel ABSOLUTE MAXIMUM RATINGS NOTICE Stresses above those listed under Absolute Maximum Ratings may cause permanent darnage to the device This is a stress rating only and functional opera Ambient Temperature Under Bias tion of the device at these or any other conditions above Storage Temperature 65 Cio 150 C those indicated in the operational sections of this speciti Voltage on Any Pin cation is not implied Exposure to absolute maximum With Respect to Ground 0 5V to 7V rating conditions for extended periods may affect device Power Dissipation 250 mW reliability D C CHARACTERISTICS Ta 0 C to 70 C Vec 5V 5 GND OV symbol Parameter Mee um Vos 081 High vote 22 v supiy Cure 0 ra 00000 NOTE 1 Available on any 8 pins from Port B and C CAPACITANCE Ta 25 C GND OV Lema Pammene Input Capacitance 1 0 Capacitance A C CHARACTERISTICS T 0 to 70 C Veg 5V 5 GND OV Bus Parameters 7
33. t by the falling edge of WR INTEA Controlled by bit set reset of PC INTE B Controlled by bit set reset of 2 c INTR OUTPUT MODE 1 PORT CONTROL WORD D 0 D 0 D D b D 1 INPUT 0 OUTPUT CONTROL WORD D 0 D D D D D 0 Figure 10 MODE 1 Output Combinations of MODE 1 Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed 1 applications AG CONTROL WORD D D D 0 0 D D D use o pe rper 1 INPUT 9 OUTPUT wa PORT A ISTROBED INPUT PORT STROBEO OUTPUT CONTROL WORD D D D D 0 D 0 O Lo wos 1 PC s INPUT 0 OUTPUT AD PORT ISTROBED OUTPUT PORT B ISTROBED INPUT Figure 12 Combinations of MODE 1 Operating Modes MODE 2 Strobed Bidirectional Bus 1 0 This functional configuration provides a means for communicating with a peripheral device or structure on a single B bit bus for both transmitting and receiving data bidirectional bus Handshaking signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1 Interrupt generation and anable disable functions also available MODE 2 Basic Functional Definitions e Used in Group only One 8 bit bi directional bus Port Port A and a 5 bit control Port Port C Both inputs a
34. t set bit reset etc that Initializes the functional configuration of the 8255A Each of the Control blocks Group A and Group B accepts commands from the Read Write Contro Logic receives control words from the internal data bus and issues the proper commands to its associated ports Control Group A Port A and Port C upper C7 C4 Control Group Port B and Port C lower 03 00 The Control Word Register can Only be written into No Read operation of the Control Word Register is allowed Ports A B and C The 8255A contains three 8 bit ports B and C All can be configured In a wide variety of functional charac teristics by the system software but each has 13 own special features or personality to further enhance the power and flexibility of the 8255A Port A One B bit data output latch buffer and one 8 bit data input latch Port B One B bit data input output latch buffer and one 8 bit data input buffer Port C One 8 bit data output latch buffer and one B bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal Inputs in conjunction with ports A and B PIN CONFIGURATION eraa s DC ria hava SUJ eso OT PIN NAMES DATA BUS B DIRECTIONALI RESET INPUT CHIP SELECT READ INPUT WRITE INPUT PORT ADDRESS P
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