Cycle Stealing Mode - Renesas Electronics
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1. Figure 1 1 Used Peripheral Function Block Diagram RO1AN1262EJ0100 Rev 1 00 Page 3 of 16 Dec 07 2012 7tENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC 2 Operation Confirmation Conditions The sample code described in this application note has been confirmed to run normally following conditions Table 2 1 Operating Conditions SH7216 Hem Contents MCU used SH7216 Operating frequency Main clock 200 MHz Bus clock 50 MHz Peripheral clock 50 MHz Operating voltage Vcc 3 3 V Integrated development environment Renesas Electronics High performance Embedded Workshop Ver 4 07 00 C compiler Renesas Electronics Renesas SuperH RISC engine Family C C Compiler Package Ver 9 03 Release 00 Compiler options cpu shZ2afpu fpu single include WORKSPDIR inc object CONFIGDIR FILELEAF obj debug gbr auto chgincpath errorpath global_volatile 0 opt_range all infinite_loop 0 del_vacant_loop 0 struct_alloc 1 nologo Operating mode User program mode Version of the sample code 1 00 Board used ROK572167C001BR Table 2 2 Operating Conditions SH7239 Item Contents MCU used SH7239A Operating frequency Operating voltage Integrated development environment Main clock 160 MHz Bus clock 40 MHz Peripheral clock 40 MHz Vcc 3 3 V Renesas Electronics High performanc2. Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics tENESAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1101 Nicholson Road Newmarket Ontario LY 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 651 700 Fax 44 1628 651 804 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Lid Unit 204 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West M
3. 0 auto increment HIE bit 0 Disable interrupts DM 1 0 bits B 01 Clear transfer complete flag SM 1 0 bits B 01 RS 3 0 bits B 0100 H 4 TB bit 0 TS 1 0 bits B 10 IE bit 0 TE bit 0 DE bit 0 DMAOR register lt H 0001 Set cycle stealing to normal mode CMS 1 0 bits B 00 Set fixed priority PR 1 0 bits B 00 Clear status flags AE bit 0 Enable DMA mask NMIF bit 0 DME bit 1 Figure 5 4 DMAC Initialization RO1AN1262EJ0100 Rev 1 00 Page 14 of 16 Dec 07 2012 7tENESAS H7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC 5 6 4 DMA Transfer Start Processing Figure 5 5 shows the flowchart for DMA transfer start processing Start DMACO transfers CHCR_0 register DE bit lt 1 Figure 5 5 DMA Transfer Start Processing 5 6 5 DMA Transfer End Processing Figure 5 6 shows the flowchart for DMA transfer end processing io_dma_poll_end DMA transfer complete Stop DMACO transfers CHCR_0 register DE bit 0 CHCR_0 register Clear transfer complete flag to 0 TE bit lt lt 0 Reads the register after clearing the flag return Figure 5 6 DMA Transfer End Processing RO1AN1262EJ0100 Rev 1 00 Page 15 of 16 Dec 07 2012 7tENESAS H7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC 6 Reference Documents e Hardware Manual SH7216 Group Users Man
4. 3 Reference Application Notes The following application notes are related to this document and should be referred to when using this application note e SH7216 Group Example of Initialization RJJO6B 1073 e SH7239 Group Example of Initialization RO1AN0297EJ e SH7231 Group Example of Initialization RO1AN0322EJ RO1AN1262EJ0100 Rev 1 00 Page 5 of 16 Dec 07 2012 ztENESAS H7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC 4 Peripheral Functions This section describes the direct memory access controller DMAC The basic description of this peripheral module is included in the SH7216 Group User s Manual Hardware SH7239 Group User s Manual Hardware and SH7231 Group User s Manual Hardware documents When there are DMA transfer requests the DMAC starts the transfer according to a predetermined channel priority and when the transfer complete conditions are met it terminates the transfer There are three transfer request modes auto request external request and internal peripheral module request The bus mode can be selected to be either burst mode or cycle stealing mode Table 4 1 provides an overview of the DMAC Figure 4 1 shows an example of a cycle stealing normal mode DMA transfer and figure 4 2 shows an example of a burst mode DMA transfer Table 4 1 DMAC Overview Item Description Number of channels e SH7216 and SH7239 8 channels CHO to CH7 Only the four channels
5. tENESAS APPLICATION NOTE SH7216 SH7239 SH7231 Groups ges RO1AN1262EJ0100 Data Transfer Within On Chip RAM Cycle Stealing Mode Rev 1 00 Using the DMAC Dec 07 2012 Abstract This application note describes a sample program for the SH7216 SH7239 and SH7231 Group MCUs that transfers data using the direct memory access controller DMAC The operation of this program has the following features e Use of DMAC channel 0 e Use of auto request mode for DMA transfers e Use of cycle stealing mode as the bus mode e The transfer source and destination are both in RAM Products SH7216 SH7239 and SH7231 Groups When using this application note with other Renesas MCUs careful evaluation is recommended after making modifications to comply with the alternate MCU RO1AN1262EJ0100 Rev 1 00 Page 1 of 16 Dec 07 2012 7tENESAS H7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC Contents UNE Tee EE 3 2 Operation Confirmation Conditions ccccccccsscceceesseeeeeesneeecesseeeeessaeeeeesaeeeeseaeeeessaeeeeesseeeesssieeeenss 4 3 Reference Application Notes cccceecccceeseccceeeeeeceeeeeeeceeeeaaeeeseaaaeesaeeaeaesseaaaeeeeeaeeeseeeaeeeseeaeaenees 5 Ax Peripheral int TEE 6 E E 8 Ge TE tele TEE 8 5 2 File Composition rices ected sate ca dncnes Red dedeadinndeeactahced aia aiaia a aac deeg AER 9 53 EC 9 54 Ee Le EE 9 5 5 FUNCHIOM Specifications c cccices
6. CHO to CH3 can accept external requests e SH7231 4 channels CHO to CH3 Only the two channels CHO and CH1 can accept external requests Address space 4 GB Logical address space Transfer data lengths Byte word 2 bytes long word 4 bytes and 16 bytes long word x 4 Maximum transfer count 16 777 216 24 bits transfers Address modes Single address mode and dual address mode Transfer requests External requests internal peripheral module requests auto requests Bus modes Cycle stealing mode normal mode and intermittent mode burst mode Priority Channel priority fixed mode round robin mode Interrupt requests CPU interrupt requests can be generated at data transfer 1 2 complete and at data transfer complete External request detection Low or high level detection and rising or falling edge detection for the DREQ input Transfer request accept signal The active levels for the DACK and TEND signals can be set and transfer complete signal Note The factors supported depend on the MCU RO1AN1262EJ0100 Rev 1 00 Page 6 of 16 Dec 07 2012 7tENESAS H7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC In cycle stealing normal mode the DMAC releases bus rights to another bus master each time the transfer of a single transfer unit byte word longword or 16 byte unit completes If there is a transfer request after that the DMAC reacquires bus rights from t
7. damages arising out of the use of Renesas Electronics products beyond such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you 8 Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with appl
8. e Embedded Workshop Ver 4 07 00 C compiler Operating mode Renesas Electronics Renesas SuperH RISC engine Family C C Compiler Package Ver 9 03 Release 02 Compiler options cpu sh2afpu fpu single include WORKSPDIR inc object CONFIGDIR FILELEAF obj debug gbr auto chgincpath errorpath global_volatile 0 opt_range all infinite_loop 0 del_vacant_loop 0 struct_alloc 1 nologo Single chip mode Version of the sample code 1 00 Board used RO1AN1262EJ0100 Rev 1 00 Dec 07 2012 ROK572390C000BR Page 4 of 16 7tENESAS H7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC Table 2 3 Operating Conditions SH7231 Hem Contents MCU used SH7231 Operating frequency Main clock 100 MHz Bus clock 50 MHz Peripheral clock 50 MHz Operating voltage Vcc 3 3 V Integrated development Renesas Electronics environment High performance Embedded Workshop Ver 4 08 00 C compiler Renesas Electronics Renesas SuperH RISC engine Family C C Compiler Package Ver 9 04 Release 00 Compiler options cpu sh2afpu fpu single include WORKSPDIR inc object CONFIGDIR FILELEAF obj debug gbr auto chgincpath errorpath global_volatile 0 opt_range all infinite_loop 0 del_vacant_loop 0 struct_alloc 1 nologo Operating mode Single chip mode Version of the sample code 1 00 Board used ROK572310CO0O00BR
9. ea Writes the pattern and updates the pointer and pattern ptr lt data Has all of the transfer source memory area been initialized Write done Yes Initializes the memory access pointer local variable ptr lt dst_addr to the transfer destination memory area Writes 0 and updates the pointer ptr lt 0 Has all of the transfer destination memory area been Write done initialized Yes Figure 5 3 Transfer Source Transfer Destination Memory Area Initialization R01AN1262EJ0100 Rev 1 00 Page 13 of 16 Dec 07 2012 7tENESAS H7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC 5 6 3 DMAC Initialization Figure 5 4 shows the flowchart for DMAC initialization a Arguments io_dma_init uint32_t src_addr Transfer source memory area start address uint32_t dst_addr Transfer destination memory area start address uint32_t dma_count Transfer count STBCR2 register Clear DMAC module standby state MSTP25 bit lt 0 ee Stop DMACO transfers n Set transfer source address SAR_0 register lt src_addr Set transfer destination address DAR_O register det adr Set transfer count DMATCR_0 register dma_count CHCR_O register DE bit lt 0 Set up cycle stealing mode auto request mode TC bit 1 Set transfer source and transfer destination to RLD bit 0 CHCR_0 register lt H 80005410 P HE bit
10. ec 07 2012 ztENESAS H7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC 5 6 Flowcharts 5 6 1 Main Processing Figure 5 2 shows the main processing main Initialize transfer source transfer destination memory areas memory_init Initialize DMAC The addresses of the transfer source transfer The addresses of the transfer source transfer destination memory areas and the size are passed as arguments destination memory areas and the transfer count io_dma_init are passed as arguments Start DMA transfer io_dma_start l Wait for DMA transfer complete io_dma_poll_end Figure 5 2 Main Processing RO1AN1262EJ0100 Rev 1 00 Page 12 of 16 Dec 07 2012 7tENESAS H7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC 5 6 2 Transfer Source Transfer Destination Memory Area Initialization Figure 5 3 shows the flowchart for transfer source transfer destination memory area initialization Arguments D uint32_t src_addr Transfer source memory area start address memory_init uint32_t dst_addr Transfer destination memory area start address uint32_t size Memory area size size in bytes Initializes the pattern local variable written to the transfer destination memory area Initializes the memory access pointer local variable to ptr lt src_addr the transfer source memory ar
11. encecesseceseneseueecuaeccaecerescesvaiecedeneesanceneaecenduetseceaesectenduedeacaecazess 10 eg WE Ge e ETC 12 56t Malin PROCESSING ET 12 5 6 2 Transfer Source Transfer Destination Memory Area Intialtzaton eeen 13 5 6 3 DMAC Initialization seiiet ideian 14 5 6 4 DMA Transfer Start Processing cccccccsceceeeeeceeeeeeaeceeeeeceeeeeeaeeeeeaeseneeeseeeseaeeeeaeeseeeeess 15 5 6 5 DMA Transfer End Processing A 15 6 Reference Dorumente cette eege eet SEENEN ed 16 RO1AN1262EJ0100 Rev 1 00 Page 2 of 16 Dec 07 2012 7tENESAS H7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC 1 Specifications This application note uses the direct memory access controller DMAC to transfer data within internal RAM The sample program sets the DMAC to cycle stealing mode and uses auto request as the DMA transfer start factor The sample program performs 128 transfers of 32 bits of data for a total of 512 bytes Table 1 1 lists the peripheral functions used and their uses and figure 1 1 shows the block diagram of the peripheral functions used Table 1 1 Peripheral Functions and Their Applications Peripheral Function Application Direct memory access controller DMAC DMA data transfers Internal RAM Transfer source and destination Internal RAM Transfer source memory area Initialization Transfer Verification of destination the operation memory area complete flag
12. he other master once again performs a single transfer unit transfer and when that transfer completes releases bus rights to another bus master This operation is repeated until the transfer complete conditions are met Cycle stealing normal mode can be used in all transfer periods regardless of the transfer request source transfer source or transfer destination DREQ Bus rights are temporarily returned to the CPU e a Bus cycle CPU CPU CPU DMAC X DMAC CPU DMAC X DMAC CPU Read write Read write Figure 4 1 Cycle Stealing Normal Mode DMA Transfer Example dual address DREQ low level detection In burst mode once the DMAC has acquired bus rights it continues the transfer operations without releasing those rights until the transfer complete conditions are met However in external request mode when level detection is used for DREQ if the DREQ signal transitions away from the active level after the DMAC transfer request that was already accepted completes bus rights will be passed to another bus master even if the transfer complete conditions are not met DREQ Bus cycle x CPU E CPU D CPU X omac X pmac X DMAC X DMAC X CPU X CPU X Read Write Read Write Figure 4 2 Bus Mode DMA Transfer Example dual address DREQ low level detection R01AN1262EJ0100 Rev 1 00 Page 7 of 16 Dec 07 2012 7tENESAS H7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC 5 S
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15. ing a reset only release the reset line after the operating clock signal has become stable When switching the clock signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable Differences between Products Before changing from one product to another i e to one with a different type number confirm that the change will not lead to problems The characteristics of MPU MCU in the same group but having different tyoe numbers may differ because of the differences in internal memory capacity and layout pattern When changing to products of different tyoe numbers implement a system evaluation test for each of the products Notice 1 Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third part
16. ins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed Clock Signals After apply
17. nstants Table 5 3 lists the constants used in the sample code Table 5 3 Constants Used in the Sample Code IRAM_SRC_ADDR H FFF8 1000 Transfer source start address internal RAM IRAM_DST_ADDR H FFF8 2000 Transfer destination start address internal RAM DMA_COUNT 128 DMA transfer count DMA_ SIZE 4 DMA transfer size 5 4 Functions Table 5 4 lists the functions Table 5 4 Functions Function Name Outline main Main processing memory_init Transfer source transfer destination memory area initialization io_dma_init DMAC initialization io_dma_start DMA transfer start processing io_dma_poll_end DMA transfer end processing RO1AN1262EJ0100 Rev 1 00 Page 9 of 16 Dec 07 2012 7tENESAS SH7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC 5 5 Function Specifications The following tables list the sample code function specifications main Outline Header Declaration Description Arguments Return Value memory_init Outline Header Declaration Description Arguments Return Value io_dma_init Outline Header Declaration Description Arguments Return Value io_dma_start Outline Header Declaration Description Arguments Return Value Main processing void main void This function first initializes the transfer source and transfer destination memory areas Then it initializes the DMAC starts a DMA transfer and waits for that transfe
18. nt test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear reactor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics 6 You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or
19. oftware 5 1 Operation Overview The sample program writes a pattern to the transfer source memory area in advance and after setting up the DMAC it starts an auto request transfer to the transfer destination memory area by enabling DMAC operation in software Table 5 1 lists the DMAC settings Figure 5 1 presents an overview of this operation Table 5 1 DMAC Settings Item Description Channel used CHO Transfer data length Long word 4 bytes Transfer count 128 transfers 128 transfers x 4 byte data length 512 bytes of data Address mode Dual address mode Transfer request Auto request Bus mode Cycle stealing mode normal mode Priority Channel priority fixed mode Interrupt Interrupts disabled Internal RAM Transfer source H FFF81000 address 512 bytes of data DMA transfer Transfer destination H FFF82000 address 512 bytes of data Legend SAR Source address register DAR Destination address register Figure 5 1 Operation Overview RO1AN1262EJ0100 Rev 1 00 Page 8 of 16 Dec 07 2012 7tENESAS H7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC 5 2 File Composition Table 5 2 lists the file used in the sample code Files not generated by the integrated development environment should not be listed in this table Table 5 2 File Used in the Sample Code main c Initialization and DMA transfer processing 5 3 Co
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21. r to complete Finally it enters an infinite loop None None Transfer source transfer destination memory area initialization void memory_init uint82_t src_addr uint82_t dst_addr uint32_t size This function writes pattern data to the transfer source memory area It clears the transfer destination memory area to all zeros uint32_t src_addr Transfer source memory area size uint32_t dst_adadr Transfer destination memory area address uint32_t size Transfer source transfer destination memory area sizes in bytes None DMAC initialization void io_dma_init uint32_t src_addr uint32_t dst_addr uint82_t dma_count After clearing the DMAC module standby state this function sets the DMAC registers uint32_t src_addr uint32_t dst_addr uint32_t dma_count None Transfer source memory area size Transfer destination memory area address DMA transfer count number of longwords to transfer DMA transfer start processing void io_dma_start void Starts a DMA transfer None None RO1AN1262EJ0100 Rev 1 00 Dec 07 2012 Page 10 of 16 7tENESAS H7216 SH7239 SH7231 Groups Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC io_dma_poll_end Outline DMA transfer end processing Header Declaration void io_dma_poll_end void Description After waiting for the completion of the DMA transfer terminates DMA transfer operation Arguments None Return Value None RO1AN1262EJ0100 Rev 1 00 Page 11 of 16 D
22. ual Hardware Rev 3 00 RO1UH0230EJ SH7239 Group Users Manual Hardware Rev 1 00 RO1UHO0086EJ SH7231 Group Users Manual Hardware Rev 2 00 RO1UH0073EJ The latest version can be downloaded from the Renesas Electronics website e Software Manual SH 2A SH2A FPU User s Manual Software Rev 4 00 RO1US0031EJ The latest version can be downloaded from the Renesas Electronics website Website and Support Renesas Electronics website http www renesas com Inquiries http www renesas com contact RO1AN1262EJ0100 Rev 1 00 Page 16 of 16 Dec 07 2012 ztENESAS SH7216 SH7239 SH7231 Groups Application Note REVISION HISTORY Data Transfer Within On Chip RAM Cycle Stealing Mode Using the DMAC Rev pats Description Summary 1 00 Dec 07 2012 First edition issued All trademarks and registered trademarks are the property of their respective owners A 1 General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this manual refer to the relevant sections of the manual If the descriptions under General Precautions in the Handling of MPU MCU Products and in the body of the manual differ from each other the description in the body of the manual takes precedence 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused P
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