User Manual - Hytec Electronics Ltd
Contents
1.2. HYTEC ELECTRONICS LTD 5 CRADOCK ROAD READING RG2 OJT U K Doc UM2256 Issue Date 12 9 94 Author PJM HYT FOUR AND EC VME VSMC 2256 CHANNEL STEPPER MOTOR CONTRO TECHNICA CIRCUIT LER L MANUAL UU ESCRIPTION CONTENTS lees Introduction 2 Stepper Control Channel Register Set Overvi om Setting Up Switches and Jumpers 4 VME Interface Full Register Set Description om Control and Status Register Format 6 Interrupts hes Detailed Operating Sequence 7 1 Soft Stop Limits and Fault 7 2 Power on reset Abort etc 8 Programming Information 9y Input Output Interface 9 1 Connections 9 2 Output Interface Step and Direction 9 3 Input Interface Fault 9 4 Input Interface Limits 9 5 Interface Signal Levels 9 6 Manual Controller Connector 9 7 Special modification remote manual changeover 10 Parts List Circuit Diagrams H H H a L Ay 1065
3. itted and the Global Interrupt Enable GIE command has been given This GIE command s an address only access o implement ROA Release ask bits A valid Interrupt Acknowledge cancels this GIE so it wi need eissuing after each interrupt service n any channel at base address plus 1E HEX and allows us n Acknowledge protocol without having to clear any source O O When the module receives an IACK cycle with code 100 on address bits A03 to A01 i e a level 4 acknowledge if acknowledge is passed on as are acknowledge cycles on other levels no channel has its interrupt output set then the ls are requesting service then the two bit code from the prioritiser is latched and that address used to select the channel which is then instructed to output its Request Register data on D00 D15 Having loaded th operated as follows The setting of the GO bit in the CSR causes i Hi gnal gh The High to start a program capacitor about 200 voltage f digital profile Ow inc The output of ab vo nanoseconds rom the register per second to be set to ow signal selec signal reasing f the le cur ltage ren slightly es rom 10 Step Register see Figure 4 t source charging a capacitor reaches OV and then di The time the ramp generator valu
4. Reset Abort A RESET Command initiated by writing a 1 to bit 0 in the CSR clears all GO flip flops and resets all LAM Mask bits It also clears the step counter to force an immediate Hard Abort for the channel After issuing this command you should wait at least 2 seconds to allow the ramp generators to settle Hard Stop This is not Soft Stop stops to Wad fl LO St The following seque UM2256 C Doc Issue Page Date Author 10 14 12 9 94 PJM designed in as a command but can be useful as a quicker alternative to Simply w state take a step and r Programming I rite a sma so try ava nformation 1l number Zero might work but the possibility exists that the logic might just be about the counter would overflow and start again without into the step counter so that in no time it noticing the lue of 5 nce shows how to go about running a stepper motor channel in the VSMC 2256 1 Write the number of steps required into the counter in the recommended sequenc 2 Assemble the Profile Register data and write this 3 Calculate the slow down count for the profile work out the slow down number to be written and write it 4 Read the Control and Status Register to check that Fault is not present and also that with your selected direction you do not
5. e A Mask register which selects certain bits in the CSR as possible interrupt sources A Request register showing unmasked status bits and the vector loaded g A 24 bit step counter register formed as 16 8 h A Profile Register for speed control ramp rate selection multiplier speed X1 X10 X100 direction and encoder control 1 A Slow Down Count register for detecting the ramp down point Bie Setting Up Switches and Jumpers Before installing the module there are some switches and jumpers to configure as follows 8 way DIL switch This sets the board s VME Base address and therefore the addresses of the registers in all four channels Switches 1 to 6 select 1 or O for each of 6 address lines switches 7 and 8 do nothing Switch 1 corresponds to address line A13 switch 6 to A08 Switch OPEN means that address line must be a 1 switch CLOSED means the address line must be 0 Address lines A15 and A14 must both be 1 to start at HEX C000 in line with Hytec s standard VXI scheme For example To select D700 as the start address A15 A14 A13 A12 A11 A10 A09 A08 i 1 0 1 0 1 1 alg Where C closed fixed fixed Cc O C O O O amp O means open Channel 1 s D780 and Cha Jumpers widths f ss 5 connec Jumper or CS C 2 S here are 5 hannels talled the unit s on Interrupts A are all the top Runni
6. h represents High converter consis tor senses when t nnel is the RUN signal and the High low speed The Run signal causes step pulses to be generated and t ts Start stop speed or ne rator speed ting of ng a pulse which is governed by t ferenc T as ar h lasts he rge time ich prevents a co or lected signal is outputs t memory nt channe This memory rate chosen N is the lower 8 bits of the r gives about 450 000 steps divide by 100 circuit and unting logic selects which signal is one of the two used to is periodically sampling the state onto the data bus and comparing them with a contains values loaded by the and when the top 16 bits of the pulse is sent to the High low down to start stop speed is hat given the high speed and the ramp rate the speed will have dropped to start stop speed by the time the ramp down is complete When the counter reaches all O s this wil ll knock down the GO signal Doc UM2256 Issue C Page 9 14 Date 12 9 94 Author PJM Tal Soft Stop Limits and Fault Soft Stop If the GO bit is reset by VME command the High low flip flop is cleared and Ramp Down starts A comparator associated with the ramp generator then looks for an output voltage just above low voltage which denotes bottom of ramp Until this point is reached the comparator generates a signal called RUN ON which al
7. have a limit condition 5 If you have zero in bits 8 9 and 10 set up the Mask with bits corresponding to Limits and Fault so that any one of them causing Stop will generate Interrupt 6 Set the GO bit by writing bit 11 to the CSR 7 Now if you wish you can set the Mask bit corresponding to the Absence of RUN selecting that as an interrupt source 8 Set the Interrupt Enable bit in the CSR and issue the Global Interrupt Enable command 9 Either wait for Interrupt or continuously poll the Status Register looking for absence of RUN or other Fault Limit status bits Clearly if you are not working on interrupts you do not need to do anything to the Mask register or interrupt enable functions Having set the channel in motion a movement can be curtailed in one of four ways three of which initiate a controlled or soft stop that is ramp down to low speed and stop These three sources are a Clockwise limit when going clockwise b Counter clockwise limit when going counter clockwise c Dataway Soft Stop by resetting GO bit in CSR If either HIGH occurs Limit LOW speed encountered DEAD STOP Th at moto The which causes an immediate Stop wi Limi is 1 is encountered flip flop This movement at is rese start s is normal th STOP then ft open he GO r is stopped fourth source ts and bit in the CSR is External bits in the Status Register rese RUN then
8. unconditionally disables the step counter useful in encoder applications for fi ine positioning The function of the Profile Register or towards Full Travel Limit is shown pictorially in Figure 2 i This 16 bit register Dits 8 23 Ju I Pleas Slow Down Count Register is continuously compared wi he comparison is sequential for that addressi not addressing the modul 20 microseconds nay cause this scanning system to must calculate the number of steps ta reg High speed of steps during This equates to th ister accordingly e g 1000 steps sec ramp down so sta High start stop in our example We subtract 1 because the comparator when equality occurs bottom 8 will all be TS averag will be 550 x 1 arrive at the number to be loaded speed dur 14 a rt stop 100 s s 590 is examining the top 16 count bits Control and Status Register Format ramp time x time 2 Doc Issue Page Date Author a miss an event ken during slow down and w ing ramp down multiplied by the ramp time Now divide that by 256 and subtract 1 to UM2256 C 6 14 12 9 94 PJM ith the top 16 bits of the step count 11 channels ing the module more often than every nd is interrupted by The host computer rite this 1 second Number
9. which and the The format of this register is as follows 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 1 MAN RUN GO FLT FULL HOME INTEN 0 Q RDY 1 1 0 BUSY BUSY and RDY are complementary and form the channel booking schem After power up RDY is 1 and BUSY is O When the CSR is first read these are seen as such i e the channel is available and the trailing edge of that read command sets the BUSY flag to ensure that all further reads show BUSY as 1 and RDY as 0 These two bits stay in that state until a reset is given which involves writing a 1 to bit 0 this means finished using channel Bits 1 2 3 5 6 14 and 15 are fixed by the VXI specification and are always read as shown Writing them has no effect Bit 7 is INTEN or Interrupt Enable specific to this channel If this bit is a l then the appearance of any CSR bit which has a corresponding mask bit set to 1 will cause this channel to assert its interrupt request This may give rise to VME IRQ4 as we see later Bit 8 is the state of the Home Limit switch provided the outer or Dead Stop Limit is open 1 open or hit limit read only Bit 9 is the same but for the Full Travel Limit read only Bit 10 reflects the state of the drive system s Fault output which is usually continuously energised to indicate OK read only Bit 11 is the GO bit Doc UM2256 Issue C Page 7 14 Date 12 9 94 Author PJM written as 1
10. 1066 1067 VME Interface and Basic Functions Channel 0 1 Channel 2 3 Doc UM2256 Issue C Page 1 14 Date 12 9 94 Author PJM Doc UM2256 Issue G Page 2 14 Date 12 9 94 Author PJM ds Introduction This single width 6U high VME module contains four independent Stepper Motor control channels which generate step and direction signals for and receive limit fault and opto encoder signals from an external drive system and motor assembly The unit offers 24 bit plus sign step magnitude with programmable speed ramp rate and slow down count independently programmable for each channel Read back of each step counter on the fly is allowed as well as soft stop Full Interrupt masking and handling is provided 2 Stepper Control Channel Register Set Overview Each of the four independent channels is equipped with its own complete set of VME registers in A16 short addressing space in line with Hytec s standard scheme which is modelled on the VXI Configuration Register set s Figure This register set comprises the following a An ID register indicating manufacturer and type b A vector register for programming interrupt acknowledge data c A Model Code register showing 2256 decimal the unit s type no d A Control and Status Register through which the channel is controlled and its status observed
11. d Vector register are at the same address You read the ID and on bits 0 11 is Hytec s unique VXI This simply shows the unit s Hytec catalogue number d T i t imple fixed i me I one channel show whether or se bi Control and Status Register nts ts Interrupt logic as an in his is a 16 bit register ts status observed rst be not which fi may CSR for short a channel boo a multi master devic the channel is in use derive from t king scheme he VXI spec 04 through which so that not A READY BUSY flagging In addition to this and then t Enable one bit to enable the output of t terrupt source register based stores a vector with which it will which is 2256 decimal the channel is controlled and only the module but also system is used to there are several he following his channel s i ii iv For more details on the CSR bit assignments and function e This Mask register di certain bits in the this register is toggle chosen bits is an 8 bit register not in it res OA ng UM2256 C Doc Issue Page Date Author 4 14 12 9 94 PJM Status bits for each limit and Drive System fault A GO bit for starting the channel A RUN bit for seeing if the channel is running see sect 5 in the top half of this location which select
12. e used by the DAC A voltage of 5V f Detailed Operating Sequence which rom t ischa capacito is presented which is an 8 bit device High spe towards ramp generator feeds a voltage to rges it r takes he ramp gene D P D Author Profile register and Slow down Count ed VCC whic frequency A compara generati to charge to a DAC rato less than 500 000 because of the discha The pulse output of the comparator goes also to dge whil nals depe lock ither While of number from host approp tep counte 20 micros the channel is each counter by enabling its the slow down coun riate tot count speed started Er ak The number should be calculated so t flip the sam flop for t the counter chip a read of the step output ivided sig the s 1 or the ndi ra eco run ne as ne count the o ng on nds lo ning releva speed and ramp the slow down count a clear l and a ramp Inside the cou riginal co ng the scanni is in progress nparator output the multiplier sel nd also a monostable which produces the output step pulse ng logic to a divide by nter chip is Furth ct 10 logic wh er pulse d The s UM2256 C oc ssue age ate 8 14 12 9 94 PJM the cha being set to a high level causes the output of a ramp gene of final value
13. goes of stop is E Fault all gi if Input Output Interface when travelli t for that top speed con ly two outer motor will stop im t a ramp dow false xternal Fault thout ramp down ve ng in the appropri channel tinues until the D limit switches wired in series ediately on encou n starts rise to module Interrupt thr Doc Iss Pag Dat Aut and a ramp and when UM2256 ue Cc e 11 14 e 12 9 94 hor PJM ate direction the down to slow speed almost ntering a LIMIT complete EAD STOP limit is If DEAD the the de energising of the Fault input ough the setting of the corresponding Mask bits are set All connections to the external drive system are via four 15 way Cannon socket connecto Step inputs are direct Connector Pi Pin No e000 OF WN FP External Step pulse output Direction output External VCC Dead Stop limit Home Li Full Boost output Incremental Incremental Incremental Incremental simi rs mounted on the front Lnout Function Ground S in Te i p t Travel limit Encode Encode Encode Encode ts common External Fault inp panel Direction and Boost outputs are opto isolated tep put CCW input CW r phase r phase r phase r phase B ve ve W p gt p ve ve mod
14. lows step pulses to continue up to bottom of ramp Limits see Figure 5 When a limit switch opens when travelling in the appropriate direction a slow down signal is generated and a ramp down starts Nothing happens then until the Dead Stop limit opens which knocks down GO If the Dead Stop limit is left open the channel WwW ja ill then stop immediately without ramping down Limit and Dead Stop will set he appropriate bit in the Control and Status Register Fault If the Fault input is d nergised the GO signal is immediately reset and the corresponding Status Register bit set NOTE Encountering a Limit or Fault at high speed obviously means not only that the position of the motor is now unknown due to the time taken to stop but also that the Ramp Generator will at that moment be in the wrong state for another move i e it has not returned to the start stop level Under these circumstances a wait of 2 seconds should be allowed so that the ramp has a chance to decay vine Power on Reset Abort etc Special consideration should be given to the following Power on reset ensures that all logic powers up in the non active state However when power is first applied to the module the integrating capacitors in the ramp generators will all be fully discharged 4 seconds should be allowed for them all to settle to the correct voltage
15. ng the format a cem a b The I write Readi identifier Writi respo c VME D1 h ID Vect D regis the vector Int 6 a D Model Code LEY Name and erface ll registers in this modul 08 EO through our nd function of or ng the ID gives HEX FF7F bits 12 15 means that this unit is A16 only tpr ng an 8 bit numbe nd during interrupt acknowledge cycles has no meaning tart address will then be D700 nnel 4 at D7CO jumpers on t to 4 respectively 20 microseco Interrupt ou he unit 1 Full Set D nd pulse Register compatible Overview list sect le may be accessed as required by but accesses to Channel 2 will start at D740 Total address space used 256 bytes UM2256 C Doc Issue Page Date Author 3 14 12 9 94 PJM Channel 3 at from D700 to D7FF jumpers 1 to 4 select step output pulse scrip in 2 ach register Offset from Channel Bas s Fig Address 00 where F7F on r to this location 02 DO D7 tion 16 bi the VM these will have no effect that is JP1 selects pulse width for channel jumper out tput signal to the VMEbus IRQ4 line 1 microsecond pulse jumper see section 6 t or 8 bit mode that is they Ebus Specification For some the following is a full description of 1 HI ter an
16. res distance would be quite satisfactory bearing in mind the opto isolated current loop mode of connection 9 6 The pinout of this 16 way IDC connector UM2256 C Doc Issue Page 14 14 Date 12 9 94 Author PJM Manual Controller Connector mounted just behind the front panel in the centre of the module is as follows Pin DNOPRPWNFP DUO WAAR WN FE Ss D s S D S S Di S S D S V 7 9 7 Module G No co ep irec OP tep irec OP tep rec OP ep irec top CC output MANUAL input Function round nnection han n P o a C u n oad C oad C u Cc oO C outpu nel nel nel ne Nes ne J w nel ne J DP POW ODN YD Fr 4 nel n connect to ground Special Modification Remote Manual Changeover Customer Request only This modi fication involves the connection of the Boost output of channel 1 to the MANUAL signal on pin 16 of the Manual connector Thus through this output of channel 1 the user can control whether the step and direction signals for any channel come from the module s electronics or from the manual controller connector As mentioned above switching over involves the disabling of each channel s step and direction outputs Ch 1 Boost 1 Manual Controller inputs active Ch 1 Boost 0 Channel electronics active
17. s CSR ib as poss iteable in a si Ww ry ma register with a l must therefore read then act accordi tion of the CS The func Interrup Fh lt Request ngly in it m Mask Register OC register is exactly place to this channel g This 24 bit register This register is the the Interrupt vector Step Counter Regis register ogical loaded v that which see sect LS cer bits at base OE You may read the counter at obvi is stopped for steps to be ta to count down halves care result does you read the there has not reconst not lower ruction wi to E You s riting bove ndif t LIL W909 is recommended and 8 bi ken or to zero needs to b give rise 16 bits fi been a major transition in 1l be good hich allows the channel to his is still taking place ts at b LOUS reasons whereupon taken to certain position irst to see if its cur AND of Status bits and Mask bits in ia location 00 in its is the actual any ti The coun the number of e interrupt sources It must be understood that it is TOGGLEABLE that is you can switch or lar way to that used in CAMAC If you write to this that means change this bit You state matches the desired state rent is discussed in more detail in sec
18. te selection multiplier speed x1 X10 X100 direction and encoder control and also permits drive system Boosting and step counter disabling 15 14 13 122 ALT 10 09 08 07 00 DIS DIR ENC B M2 M1 R2 RI SPEED The lower 8 bits of this register control the normal running speed or high speed of the channel The start stop speed is one tenth of this speed With a multiplier of X1 255 decimal gives a high speed of 5000 steps per second This 8 bit number controls a current which in turn generates a frequency In order to reduce noise influences it is recommended that a higher speed number be preferred with a lower multiplier e g 129 X10 is better than 13 X100 Furthermore since there is a degree of overlap between the ranges more granularity is available fine speed control when higher numbers are used The other bits of the register act as follows R2 R1 control the ramp time as follows R2 R1 Ramp Time 0 0 4 seconds 0 1 2 seconds 1 0 1 second iF 1 0 5 seconds M2 M1 control the speed multiplier as follows M2 M1 Multiplier 0 0 x1 0 1 X10 1 X100 B 1 Boost Controls boost output to drive system to increase drive current typically by 25 during acceleration ENC 1 Encoder Use quadrature encoder outputs for generating counting pulses and direction signal 0 means count step pulses DIR Direction 1 C DIS lockwise Disable Counter
19. tion 6 its top half and The data in this cycle takes bottom half output when an Interrupt Acknowledg ion 6 OE and 10 step counter and is formed as 16 se 10 for the channel to it when the channel required number of expected and proceeds register is in two me but you should only write ter is loaded with the shaft encoder output pulses he channel stops Since this to erro CSc he counter should only be don hould be certain that the ramp down is complete RUN ON tart the channel running and counting again nsure that reading it and reconstructing the s due to intervening counts It is recommended that then the top 8 then the lower 16 again Then if the lower 16 the result of the when the cha nnel is stopped as mentioned since there is logic after the GO bit is reset during Soft stop loading a non zero value into the step counter Observing the state of RUN in the CSR Having established that the channel has defini Doc Issue Page Date Author count in the following reco mended sequenc otherwise loading may not be achieved correctly UM2256 C 5 14 12 9 94 PJM itely stopped you should load the step top 8 bits first then the bottom 16 h Profile Register 12 This 16 bit register handles speed control ramp ra
20. to start a movement written to 0 to soft stop or ramp down to start stop speed and stop This bit is cleared when the step count reaches zero or a limit is hit or reset is given Bit 12 is RUN which reflects the state of GO except that it remains true during ramp down after a soft stop command Bit 13 is MAN or Manual which indicates that the manual controller has been plugged in This disables the channel s own step and direction signals so the host must not attempt to move the channel when this bit is set While the manual controller is in use the step counter follows any movements to allow the host to observe any positioning which may be done 6 Interrupts he Li ONH Ia he interrupt output of a channel is the logical OR of the AND product of the relevant CSR and Mask Register bits see Fig 3 mit and Fault bits work in the true sense i e when they are both 1 the AND will be true The RUN bit works in the opposite sense so that when it goes to e movement finished the AND will be true The interrupt outputs of all four channels are fed to a prioritiser which has one output which indicates one or more interrupt sources present and two more which output a code indicating the highest numerical source present The one present output will cause the VME IRQ4 line to be asserted provided JP5 is 5 H O Hoh If one or more chann
21. ule ground Module VCC to powe external VCC r encoder ut Direction as is the Fault common Drive system 5V to energise optos Fault input may be linked back to Limit Ly coupled through RC networks and Schmitt Trigger logic gates Encoder inputs are terminated RS422 pairs 9 2 Output Interface Step 5V 560R Fl OPTO COUPLI CTR gt 50 9 3 Input Interface Fault 5V 10K OV CTR gt 50 Doc UM2256 Issue C Page 12 14 Date 12 9 94 Author PJM Direction and Boost ST 1KO0 EP DIR BOOST EXT GND EXT VCC iS e EXT FAULT SIGNAL Doc UM2256 Issue C Page 13 14 Date 12 9 94 Author PJM 9 4 Input Interface Limits 5V 10K Sp Cy O LIMIT 100nF OV 13 O LIMITS COMMON GND Sea Interface Signal Levels Outputs ON STATE VSAT lt 0 5V at Iout 2mA OFF STATE VMAX 15V Io lt 100uA Inputs Limits Wetting current 0 5mA Total permitted external resistance 1K ohm Fault On State I on gt 3 0 mA Off State I off lt 100 uA The output interface for step pulse and direction signals is designed to be compatible with Hytec s Stepper Motor Drive System type SMDS4 and will also be compatible with most other types of translator cards in particular the PKS Digiplan range CD10 20 etc and will produce step pulses as required by them i e 20uS width Operation of this unit with translators at up to 40 met
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