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1. 5 648 735 to Derek Bowers and James Ashe for Comparator with a predetermined state in dropout 5 656 952 to K evin M cCall and David Reynolds for All MOS differential high speed output driver for providing positive ECL levels into a variable load impedance gt 5 659 262 to John M emishian for Offset trimming for a micromachined sensing devices 5 661 422 toT homas Tice David Crook Kevin Kattman and Charles Lane for High speed saturation prevention for saturable circuit elements 5 666 043 to Peter H enry and Evaldo M iranda for Voltage detector with trigger based on output load currency 5 666 299 to Robert Adams Tom K wan and Michael Coln for Asynchronous digital sample rate converter 5 668 551 to Patrick J Garavan and Eamon Byrne for Power up calibration of charge redistribution analog to digital converter 5 668 553 to James Ashe for R2R digital to analog converter with common shutdown mode 5 670 821 to Derek Bowers for Guard ring for mitigation of parasitic transistors in junction isolated integrated circuits 5 670 883 to Geoff O Donoghue and Scott M unroe for Integrated circuit interlevel conductor defect characterization test structure and system e e 5 671 252 to Janos K ovacs and Scott M unroe for Sampled data read channel utilizing charge coupled devices 5 672 952 to Thomas Szepesi for Controller for battery charger with reduced reverse leakage cur
2. T he initialization routines have been put into the init1847 dsp file T his file contains the interrupt vector table the main dummy loop and the interrupt service routines for the pushbutton and the serial port 0 receive T he pushbutton IRQE causes the LED on the EZ K it board to toggle with each button press Parameters controlling the sampling rate gains etc are contained in the file initl847 dsp Serial Port 0 is used to communicate with the AD 1847 T he transmit interrupts are used to configure the codec then they are disabled and the receive interrupts are used to implement the talk through audio T he definitions for the memory mapped control registers are contained in the file system h T he application can be built by asm21 c 2181 hello81 asm21 c 2181 init1847 d21 hello81 init1847 a 2181 e hello81 g x K3K3K3K KK KOR 3KOR KOR KOR KOR KOR ELLE EER EEREL EEL ERED E EERE EE A E K SED K KKK J module RAM ABS 0 E ZH ello include lt system h gt define taps 255 filter tap length var dm circ filt_data taps input data buffer var pm circ filt_coeffs taps coefficient buffer init filt_coeffs lt coefs dat gt initialize coefficients external rx_buf tx_buf external init_cmds stat_flag external next_cmd init_1847 init_system_regs init_sport0 ERESEAALE LATA KOR KOR KOR KOR KOR KOR LAE ARE R
3. Analog Dialogue A forum for the exchange of circuits systems and software for real world signal processing MIXED SIGNAL CHIPSET TARGETS HYBRID FIBER COAXIAL CABLE MODEMS page 3 Powerful Design Tools for Motion Control Applications page 6 Ask The Applications Engineer Switches amp Multiplexers page 20 Complete contents on page 3 ANALOG DEVICES Volume 31 Number 3 1997 Editor s Notes ADI WEB SITE http www analog com We first announced this Web F s ff Home Page almost exactly two years ago Volume 29 No 3 1995 At that time we bravely stated T his site is intended to help engineers throughout the design in process T here are articles and white papers discussing the underlying technologies search tools to help you find the ideal component for your application and we are developing a full set of material including data sheets on every current part and even SPICE models and evaluation board layouts for many of them D uring the past two years many of you have visited our Web site as it has developed Some hopefully many have been gratified others hopefully few have been disappointed You ve expressed your likes and dislikes quite volubly and we ve been listening Other than personal contact with our sales and applications engineers theWorldwideWeb through our site and our links with other sites has become one of the most important ways of providing you with information an
4. 16 pin TSSOP make these devices particularly Suitable for portable and power consumption critical applications T he serial interface is compatible with the serial interfaces of most uCs and DSPs A Package Address pin allows bus sharing Operation is specified from 40 to 105 C Prices 1000s are 2 90 and 3 30 Faxcode 2062 or Circle 14 B 16 Bit 5 V ADCs AD977 upgrades ADS7809 AD977A 200 ksps thruput TheAD977 and AD 977A are 16 bit serial output A D converters with a wide choice of analog input ranges 10 V 5 V 3 3V and 0to 10 5 and 4 V Requiring minimal support circuitry and low power they contain internal references provide low cost performance and run from a single 5 V supply T heir inputs are protected against voltages up to 25 V Consuming only 100 mW theAD 977A runs at 200 ksps 100 ksps for the AD 977 In the power down mode dissipation is only 50 uW The devices contain a successive approximation ADC an internal 2 5 V reference and a high speed serial interface and include on chip clock circuits Available in 20 lead plastic D IPs and SOICs and 28 lead SSOPs they operate from 40 to 85 C Price 1000s in PDIP is 20 for AD977 and 26 for AD977A Faxcode 1958 or Circle 18 B All brand or product names mentioned are trademarks or registered trademarks of their respective holders F or immediate data visit our WorldWideWeb site http wwwanalog com In N orth America call AD l
5. T hen interpolating filter stages are used to match the effective output data rate of the FIR filters to the output sampling frequency of the direct digital synthesizer D DS for frequency upconversion T heAD 9853 employs a state of the art D DS function to generate precise sine and cosine digital waveforms to mix with the pulse shaped data bitstream in a high speed mixer stage and create the 5 42 MHz modulated carrier The DDS is also responsible for making the device highly frequency agile its 32 bit tuning word capability enables the modulated carrier at the output to be tuned with a resolution of 0 029 Hz A high speed adder stage sums the upconverted digital and Q data to create a single data path which Is ready to be converted into the analog domain by a high speed 10 bit D A converter A SINC filter is utilized to pre compensate the data stream for the sinx x roll off of a high speed D A converter s quantized output function T he patented architecture of the AD9853 s CMOS D A converter stage with a55 dB SFDR at 40 MH zAout rivals the performance afforded by expensive and power hungry bipolar DACs A key system cost saving feature in theA D 9853 is its x6 reference clock multiplier circuitry which essentially allows the AD 9853 to generate the high speed clock for the DDS synthesizer internally Saving the user the expense and system design difficulty of F or technical data consult our Web site www analog com
6. T his converts the program file into a format that the other development tools can process Assembling also checks the code for syntax errors N ext one links the code to generate the DSP executable using the available memory that is declared in the architecture file T he Linker fits all of the code and data from the source code into the memory space the output is a DSP executable file which can be downloaded to the EZ K it Lite board GENERATING FILTER CODE Part 2 of this series Analog Dialogue 31 2 page 14 Figure 6 introduced a small assembly code listing for an FIR filter H ere that code is augmented to incorporate some EZ K it Lite specific features specifically codec initialization and data I O The core filter algorithm elements multiply accumulates data addressing using circular buffers for both data and coefficients and reliance on the efficiency of the zero overhead loop do not change T he incoming data will be sampled using the on board AD 1847 codec which has programmable sampling rate input gain output attenuation input selection and input mixing Its programmable nature makes the system flexible but it also adds a task of programming to initialize it for the DSP system ACCESSING DATA For this example a series of control words to the codec to be defined at the beginning of the program in the first section of the listing will initialize it for an 8 kH z sampling rate with moderate gain values on each
7. dB SIGNAL LEVEL dB 0 50 100 150 200 250 icLock ICLOCK SfcLOCK FREQUENCY 0 50 100 150 200 250 80 EASIER ANALOG FILTERING STEEP i ANALOG FILTER INTERPOLATED o9 DAC OUTPUT N DAC OUTPUT i WITH IMAGES k f feLock 2fcLock 3fcLock fckock 2fcLock 3fcLock 0 50 0 00 Figure 3 Time domain and frequency domain representation of continuous time and discrete sampled sine wave and an interpolated discrete sampled sine wave 40 SIGNAL LEVEL dB SIGNAL LEVEL dB 100 150 200 250 0 50 1 150 200 250 FREQUENCY T he task of the DAC reconstruction filter is to pass the highest desired output frequency F outmax and block the lowest image frequency located at F ao F outmax IMplying a smoothing filter transition band of F cock 2F outmax 10 T his suggests that as one tries to synthesize signals close to the Nyquist limit F outmax F clock 2 the filter transition gets impossibly steep To keep the filter problem tractable many designers use the rule of thumb that the DAC clock should be at least three times the maximum desired output frequency In addition to the filter difficulties higher frequency outputs may become noticeably attenuated by the sinx x envelope a signal at F dock 3 is attenuated by 1 65 dB a signal at Fak f2 Is attenuated by 3 92 dB Oversampling can ameliorate the D A filter problem just as it helpsin the ADC case M ore so in fact since one need not worry abou
8. 260 MHz Dual Buffer AD8079 0 01 AG 0 02 A 0 1 dB flat to 50 MHz T he AD 8079 is a dual fixed gain buffer for video and other wideband applications It is optionally available with pin strappable fixed gains of 2 1 and 1 A grade and 2 2 1 and 1 2 B grade the latter permits compensation of system gain losses T he 70 mA output can drive up to 8 video loads Bandwidth is 260 MHz 3 dB and response Is flat within 0 1 dB to gt 50 M Hz Typical applications are for differential driving of twisted pair wiring and for buffering inputs and outputs of switches such as the AD 8116 crosspoint D ifferential gain and phase errors are 0 01 and 0 02 respectively and crosstalk is 70 dB at 5 M Hz Quiescent dissipation is only 50 mW per amplifier The device operates on supplies from 3 V to 6 V and is available in an 8 pin plastic SOIC Prices start at 3 50 1000s Faxcode 2072 or Circle 5 B 14 Bit 125 MSPS D A AD9764 TxDAC 2 7 to 5 5 V Optimized for SFDR THD IMD T heAD 9764 brings 14 bit resolution to the T xDAC series of high performance low power pin compatible CMOS DACs It Is designed for reconstructing wideband high dynamic range signals in communications and test equipment Its excellent IM D and SFDR performance for single and multitone signals upgrades existing communication systems and permits new wideband transmit architectures Its applications include base stations and ADSL
9. 2T TEAV YOLAGTYLSIG YADA WS A NI GALNIdd L66T E ON TE uln joA anbojeiq bojeuy UO Hoyeue MMM dyY 3811S q A Spi POM S7PT LE6 L8Z suonesi ddy jeuqueD Z6EE LOV T8 JaqUeD aunzesa 79G 79Z 008 u 1 d H Y S N JINVLSISSV YAWOLSND 0L8 92E T8Z xeJ Ajuo Y S N V9S Z9Z 008 T OOLV 6ZE T8Z l L Y S N 90T6 Z90ZO VW POOMJON 9016 xog O d Ae M Abojouude uo SUSLYWNOGW3H JGIMGTYOM GG v 90S Z Xed 9 6 90S Z L buoy Puop Aeg Aemasnes 199 15 uos u1e W SUD enbs Sow AMO ISAM ICN ZOLZ SUaLUVNOGW3H VISV LSVSHLNOS COOT ZOVS X84 OLZ8 ZOVS L uede GOT 00L N 0 eU W uebley T 9T T Buipiing JAMO YNOS eqiysaye id M N SuaLuvndavaH NVdV LSS 06 94 680 xe3 TSS 06 94 680 l L AUCWHAD U YDUNW ELETS E T Yedisay Wy SuALYWNOGW3H IdOYNI Ane1u s id ux Aneyju s id u oJ v lilN p11 Abojouyde Ajjeul4 GEZ8 8 6 81T0 000 992 ZEGTO uuopBupi pozun CTO S6T Z0 ueMue L Ovl 8 8 U pP MS 00Z8 SLE auodebuls OOZEEZS 92 SPUBHSYION TOEE YSS Z e 103 OLZ8 ZOvs uede f OZT 00 S99 Z Ayex TOVPVLL 6 PES S9S0 Z9 TT T6 eIpul 9EE6 90S Z buoy buoy 0 806 6 T TILO 0 6Z6 89 IZZ0 0 06 94 680 A ueuu S 00 St V 9P TO 52ue13 008Sr8 r SHeWUDG L9OLZ 8TS TT Izeg 0 t0 SS 888 T eu3snV GGLL98 6S e llensnv S
10. C for high level program control functions and assembly code for the time critical math intensive portions of the system In any case the programmer must be aware of the processor s system constraints and peripheral specifics T he FIR filter system example in this article uses the native assembly language of the ADSP 2100 Family Software validation debugging T his phase tests the results of code generation using a software tool Known as a simulator to check the logical flow of the program and verify that an algorithm Is performing as intended T he simulator is a model of the DSP processor that a provides visibility into all memory locations and processor registers b allows the user to run the DSP code either Analog Dialogue 31 3 1997 continuously or one instruction at a time and c can simulate external devices feeding data to the processor Hardware implementation H ere the code is run on areal D SP typically in several phases a tryout on an evaluation platform such as EZ Kit Lite b in circuit emulation and c production ROM generation Tryout provides a quick go no go determination of the program s operation this technique is the implementation method used in this article In circuit emulation monitors software debug in the system where a tool such as an EZ ICE controls processor operation on the target platform After all debug Is complete aboot ROM of the final code can be generated it serves as
11. IN BAND A ARE ALIASED REFLECTIONS i i OF SIGNALS IN BAND B 0 fs2 fs 2fs OVERSAMPLING SIGNALS AND NOISE IN THIS RANGE DO NOT CREATE ALIASING ERRORS EASIER FILTER Pe Jw fs 0 fs 2 Figure 2 Oversampling makes filtering easier Of course if interferers at frequencies close to 200 kH z are very strong compared to the desired signal additional dynamic range will berequired in the converter to allow it to capture both signals without clipping see part IV A nalog Dialogue 31 2 for a discussion of dynamic range issues After conversion oversampled data may be passed directly to a digital demodulator or decimated to a data rate closer to N yquist Decimation involves reducing the digital Sampling rate through a digital filtering operation analogous to the analog anti aliasing filter A well designed digital decimation filter provides the additional advantage of reducing the quantization noise from theA D conversion For a conventional A D converter a conversion gain corresponding to a 3 dB reduction in quantization noise is realized for every octave factor of two decimation U sing the 1 6 M Hz sample rate for oversampling as above and decimating down to the N yquist rate of 400 kHz we can realize up to 6 dB in SNR gain two octaves N oise shaping converters such as sigma delta modulators are a special case of oversampling converters T he sampling rate of the modulator is its high speed clock rate and the antial
12. MEMORY RAM DATA ADDRESS GENERATORS ARITHMETIC UNITS MOTOR CONTROL PERIPHERALS PROG EVENT INTERRUPT arene CAPTURE CONTROLLER TIMERS FIVE INPUT CHANNELS Figure 2 The ADMC300 Single Chip DSP based Servo Motor Controller a full range of hardware and software development tools that allow rapid prototype development and real system evaluation In both the ADM C300 and the AD M C330 the program memory ROM block is preprogrammed with a monitor debugger function that enables access to the internal registers and memory of the processors In order to speed program development the ROM code also contains a library of useful mathematical and motor control utilities that may be called from the user code A separate evaluation board for code development is available for each type T hese evaluation boards contain easy interfaces to the many peripheral functions of the processors so that the board can be easily integrated into a final target development system Each evaluation board contains a UART interface that may be used to connect the DSP controller to aWindows based M otion Control D ebugger program T he debugger program allows the developer to download code to the D SP and monitor or modify the contents of program memory data memory DSP registers and the peripheral registers In addition a selection of debugging tools including breakpoints single step and continuous run operation may be selected from theW indows
13. ROM and the necessary motor control peripherals including a 3 phase center based PWM generator a seven channel 3 independent 4x1 multiplexed slope comparator ADC 8 bits of digital 1 0 etc It is used for ac motor control in domestic appliances industrial machinery electric vehicles and wherever else electric motors must be controlled On a single chip the DSP performs all the necessary calculations required for closed Open or servoloop motor control and the motor control peripherals initiate the appropriate PWM waveforms all with little external circuitry and software overhead T he ADM C330 in an 80 leadT QF P uses 5 V operates from 40 to 85 C Priceis 13 60 1000s An evaluation kit is 395 Faxcode 2126 or Circle 29 gt CCD CIS Processor 10 bit AD9805 is complete 1 chip CCD imaging front end T he AD 9805 like the pin compatible 12 bit AD 9807 Analog Dialogue 31 1 p 19 is a complete single chip analog front end AFE for converting outputs from CCD charge coupled device and CIS contact image sensor modules to digital data It requires no external active circuitry just a few capacitors Typical applications are in scanners and other CCD signal processing applications such as digital cameras It includes a 10 bit 6 M SPS A D converter an integrated triple correlated double Sampler programmable gain amplifiers pixel rate digital gain and offset adjustments an internal voltage reference
14. SATURATED VDD 1 5V POSITIVE OVERVOLTAGE 20V SATURATED SATU RATED Vpp 15V Vss 15V VrN NMOS THRESHOLD VOLTAGE 1 5V Figure 4 Positive Overvoltage on the Channel Analog Dialogue 31 3 1997 When a negative overvoltage is applied to a channel the PM OS transistor enters a saturated mode of operation as the drain voltage exceeds V ss Vrp As with a positive overvoltage the other M OS devices are non saturated NEGATIVE OVERVOLTAGE Vss VTp 20V 13V a NON SATURATED NEGATIVE NMOS PMOS OVERVOLTAGE 20V NON SATURATED SATURATED Vpp 15V Vss 15V V p PMOS THRESHOLD VOLTAGE 2V Figure 5 Negative Overvoltage on the Channel Q How does loading affect the clamping voltage A When the channel is loaded the channel output will clamp at a value of voltage between the thresholds For example with a load of 1 KQ Vpp 15 V and a positive overvoltage the output will clamp at Vpp Vry AV where AV is dueto the IR voltage drop across the channels of the non saturated M OS devices In the example shown below the voltage at the output of the clamped NMOS is 13 5 V The on resistance of the two remaining MOS devices is typically 100 Q Therefore the current is 13 5 V 1 kQ 100 Q 12 27 mA T his produces a voltage drop of 1 2 V across the N M OS and PM OS resulting in a clamp voltage of 12 3 V T he current during a fault condition is determined by the load on the outp
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17. addition to ADI s family of transmit DAC s is asubsystem on a chip based on the T xDAC core see adjacent story It consists of a matched pair of high performance 40 MSPS 10 bit DACs optimized for low distortion 58 dB SINAD 9 5 ENOB 65 dB SFDR for flexible handling of QAM amp Q data Included area pair of 2x digital interpolation filters with 62 5 dB stop band rejection and an on chip 1 2 V reference The AD9761 provides 10 mA of output Current and operates on a 2 7 to 5 5 V supply with only 200 mW dissipation at 3 V A Sleep mode reduces input current by a factor of about 9 The DACs share a common 20 MSPS interleaved data interface Operation is from 40 to 85 C and the device is housed in a 28 lead SSOP Its price 1000s is 11 95 Faxcode 2135 or Circle 9 gt Power References Low noise ADR290 291 292 XFET Better than bandgap The ADR290 ADR291 and ADR292 are precision 2 048 2 5 and 4 096 V low noise micropower precision references T hey employ anew reference technology X F E T eX tra implanted junction FET offering the benefits of low supply current and very low thermal hysteresis with substantially lower noise than bandgaps and lower power than buried Zeners T hey are specified for 2 7 3 0 and 5 0 V min supply voltage 15 15 and 18 uA max supply current 420 480 and 640 nV VHz noise density at 1 kH z T he best grades have initial accuracy to within 2 mV and 8 ppm C t
18. and a uP compatible control interface It uses a 5 V supply 500 mW and is compatible with 3 3 and 5 V digital I O Specified for 0 to 70 C it is packaged in a 64 pin PQFP Price 1000s is 9 50 Faxcode 2021 or Circle 27 gt Regulator Controller ADP3310 Is a low noise high precision LDO in 8 pin SOIC The ADP3310 is a precision voltage regulator controller that can be used with an external power PM OS device such as the N D P6020P to form atwo chip low dropout linear regulator with only 70 mV of dropout voltage at 1 A Its low headroom low quiescent current 800 uA and low shutdown current 1 uA help prolong battery life in battery powered systems Its accuracy spec is 1 5 over line load and temperature H andling up to 10 A of current it is stable with 10 uF output Capacitance Protection includes an internal gate to source clamp and current limiting with foldback Operating voltage is from 2 5 to 15 V It Is packaged in an 8 lead SOIC and has a 40 to 85 C ambient temperature range 4 fixed output options are available 1 8 3 3 3 amp 5 V Price 1000s is 0 94 Faxcode 2120 or Circle 30 B CCD Processor For electronic cameras 10 bit 18 MSPS full speed CDS The AD9801 is a complete CCD signal processor developed for electronic cameras It is well suited for both video conferencing and consumer level still camera applications Its signal processing chain comprises a high speed 18 M SPS c
19. gate drain capacitance associated with the PM OS device is about twice that of the N M OS device because for both devices to have the same on resistance the PM OS device has about twice the area of the NM OS Hence the associated stray capacitance is approximately twice that of the N M OS device for typical switches found in the marketplace C c SWITCH iL a VGN STRUCTURE EQUIVALENT ii CIRCUIT c ON OFF ON OFF JIL ay U SDP Cspn Casp Cesn figure 8 figure 9 Figure 8 CMOS Switch Structure showing parasitic capacitance Figure 9 Equivalent circuit showing the main parasitics which contribute to charge injection When the switch is turned on a positive voltage is applied to the gate of the NM OS and a negative voltage is applied to the gate of the PM OS Because the stray gate to drain capacitances are mismatched unequal amounts of positive and negative charge are injected onto the drain T he result is a removal of charge from the output of the switch manifested as a negative going voltage spike Because the analog switch is now turned on this negative charge is quickly discharged through the on resistance of the switch 100 Q This can be seen in the simulation plot at 5 us T hen when the switch is turned off a negative voltage is applied to the gate of the NMOS and a positive voltage is applied to the gate of the PM OS T he result is charge added to the output of the switch Because the analog switch is now of
20. information is recorded in a system description file for use by the ADSP 2100 Family development tools A system description file has a SY S extension T he following list shows a system description file EZKIT LT SYS system EZ LITE adsp2181 mmapo gives a name to this system specifies the processor J specifies that the system boots and that PM location 0 isin internal memory seg PM RAM ABS 0 code data int_pm 16384 seg D M RAM ABS 0 int_dm 16352 endsys ends the description Analog Dialogue 31 3 1997 T he listing declares 16 384 locations of PM as RAM starting at address 0 to let both code segments and data values be placed there Also declared are 16 352 available locations of data memory as RAM starting at address 0 Because these processors use a H arvard architecture with two distinct memory spaces PM address 0 is distinct from DM address 0 T he ADSP 2181 EZ K it Lite s codec is connected to the DSP using a Serial port which is not declared in the system description file To make the system description file available to other software tools the System Builder utility BLD 21 converts the SYS file into an architecture or ACH file The output of the System Builder is a file named EZKIT LT ACH After writing the code page 15 the next step is to generate an executable file i e turn the code into instructions that the D SP can execute First one assembles the DSP code
21. multiply accumulate operations equal to the length of the filter T he delay line for input data and the coefficient value list require reserved areas of memory in the DSP for storing data values and coefficients The DSP s enhanced Harvard architecture lets programmers store data in Program M emory as well as in Data M emory and thus perform two simultaneous memory accesses in every cycle from the DSP s internal SRAM With Data M emory holding the incoming samples and Program M emory storing the coefficient values both a data value and a coefficient value can be fetched in a single cycle for computation T his DSP architecture favors programs that use circular buffering discussed briefly in Part 2 and later in this installment T he implication is that address pointers need to be initialized only at 12 the beginning of the program and the circular buffering mechanism ensures that the pointer does not leave the bounds of its assigned memory buffer a capability used extensively in the FIR filter code for both input delay line and coefficients Once the elements of the program have been determined the next step is to develop the DSP source code to implement the algorithm DEVELOPING DSP SOFTWARE Software development flow for the ADSP 2100 Family consists of the following steps architecture description source code generation software validation debugging and hardware implementation Figure 2 shows a typical development cyc
22. of the input channels Since the AD 1847 is programmable users would typically reuse interface and initialization code segments changing only the specific register values for different applications T his example will add the specific filter segment to an existing code segment found in the EZ K it Lite software T his interface code declares two areas in memory to be used for data I O tx_buf for data to be transmitted out of the codec and rx_buf where incoming data is received Each of these memory areas or buffers contains three elements a control or status word left channel data and right channel data For each sample period the DSP will receive from the codec a status word left channel data and right channel data On every sample period the DSP must supply to the codec a transmit control word left channel data and right channel data In this application the control information sent to the codec will not be altered so the first word in the transmit data buffer will be left as is We will assume that the source is a monophonic microphone using the right channel no concern about left channel input data 13 Using the I O shell program found in the EZ K it Lite software we need only be involved with the section of code labeled input_samples T his section of code is accessed when new data is received from the codec ready to be processed If only the right channel data is required we need to read the data lo
23. s 24 hour AnalogF ax line 1 800 446 6212 and use Faxcode Analog Dialogue 31 3 1997 17 New Product Briefs For information use reply card or see back cover Digital Communication and Supervisory DECT IF Transceiver AD6402 integrated subsystem for multichannel base stations The AD 6402 is an IF subsystem used in high performance TDMA time domain multiple access digital radios employing FSK GFSK FM and QPSK modulation schemes Designed primarily for digital enhanced cordless communication DECT it can be used in any similar radio architecture with 1 M BPS bit rates H ighly integrated it includes a limiter stage with inter stage filter RSSI detection a PLL demodulator IF VCO IF buffers VCO regulator and power management The AD 6402 has multiple power down modes to maximize battery life U sing an on chip PLL demodulator it requires no manufacturing trims an integrated 2nd IF filter further reduces external component count It will operate with gt 2 7 V supply is housed in a 28 pin SSOP and operates from 25 to 85 C Price in 1000s Is 6 55 Faxcode 2256 or Circle 19 B DDS with On Chip D A AD9832 is complete for 25 MHz clock has 10 bit DAC T he AD 9832 is a low cost complete direct digital synthesizer D D S on achip with 25 M Hz clock speed and 10 bit resolution It Includes a phase accumulator sine lookup table and on chip D A converter to generate an output sine wave with a
24. 0 processor module the board may be used to develop sensorless control algorithms for brushless dc motors for applications such as compressors and washing machines In addition simple vector control strategies for an ac induction motor may be programmed for pump or fan applications If higher performance levels are required the AD M C 300 processor module may be mounted instead to implement open loop and closed loop vector control of induction motors for applications such as general purpose variable speed drives paper and textile machines and conveyors With the ADM C300 processor module the AD vanced PowlR train is suitable for developing high performance servo controllers using an induction motor a brushless dc motor or a permanent magnet synchronous motor T heAD vanced PowlR train board integrates the following features An integrated power module from International Rectifier T he AD vanced PowlRtrain board includes a power module that is capable of driving a 1 hp three phase motor The module integrates a three phase diode bridge that may be used to rectify a 50 60 H z three phase supply T he power module also includes a three phase GBT based inverter that may be connected directly to a three phase motor Interchangeable processor modules so that the appropriate D SP based motor controller may be used for your application A UART interface to theW indows based program development environment the M otion Control D ebu
25. 2 F will be translated down intact signals in the bands N 1 2 F lt signal lt N F will be translated flipped in frequency see Figure 1 T his flipping action is identical to the effect seen in high side injection mixing and needs to be considered carefully if aliasing is to be used as part of the signal processing T he anti alias filter in a conventional baseband system is a low pass filter In undersampling systems the anti allas filter must be a bandpass function Analog Dialogue 31 3 1997 Undersampling offers several more challenges for the A D converter designer the higher speed input signals not only require wider input bandwidth on the A D converter s sample and hold SHA circuit they also impose tighter requirements on the jitter performance of the A D converter and its sampling clock To illustrate compare a baseband system sampling a 100 kH z sine wave signal and an IF undersampling system sampling a 100 M Hz sine wave signal In the baseband system a jitter error of 100 ps produces a maximum signal error of 0 003 of full scale peak to peak probably of no concern In the IF undersampling case the same 100 ps error produces a maximum signal error of 3 of full scale CONTINUOUS TIME SAMPLED DATA A ANTI ALIAS FILTER 2 LOW PASS xy fs 2 ANTI ALIAS FILTER BAND PASS MIRRORED FREQUENCY fs 2 fs fs 2 ANTI ALIAS FILTER BAND PASS x l FREQU
26. 391440 SAWS 193910 WNOILWNYSLNI d 26 ZT TEV 688T YIG WNN LIWHdAd VW NOLSO dIVd ADVLSOd S n 4LVd X 1N8 pooquBeny Ben1sod WINY p zs nb y uon5 uoo2 SSouppy PueMIO JON Od GE86 LOLTO VW weybulwes4 L9E6 xog O d SJAA SOTVNV V S n NI GALNIdd L66T E ON TE uln joA anbojeiq bojeuy Woo boyeue MMM dyY 1IS q A PIM PLOM 0L8 9ZE T8 xe4 luo W S N r9S z9 Z 008 T OOL7 6ZE T8Z 1 W S N 90T6 Z90Z0 VW POOMION 9016 xog O d Ae M Abojouude uo SYILYYN AYIH JGIMATYOM GG v 90S Z Xed 9 6 90S Z L buoy BuoHr Aeg Aemasnesy 199 15 uos ul1e W SUD aenbs Sow AMO ISOM ICN ZOTZ SYALYVNOAVSH VISV LSVIHLNOS E90T ZOYS Xe4 OTZ8 ZOVS PL uede GOT 00L N 0 eU w ueBle gt T 9T T Buipiing MOL YNOS eqius ye IId M N SUSLYVNOGVSH NVdV LSS 06 9Z 680 X24 TSS 06 94 680 l L ueuu o UaysUNW ELET8 A E T Wedysan Wy rtrlIr rTr 008 J M 9TZZ ZS6 YTL 801d uu s 8910 299 008 J UO d G Z6 9r 008 S 1U01729 3 JHE M N 8E98 ZEE 008 MewjjeH uoljiuueH TEL8 88E 008 S91U01 29 3 imna OOTL 86Z LOY iddns diyo 9999 GZS 008 s unsnpul g OOLS Er 008 sSjzluodno 3 p l llV SYOLNSTYLSIC NVOIYSWV HLYON 8ZVT C6 T8Z Jol nqulsip 2207 SZYT LE6 T8Z v9SZ 9Zr 008 T ITTt T9r T8Z v9SZ 9Zr 008 T ITTt I9r T8Z JonqiAsip 2207 ZL9E T9v T8Z JOYNI
27. 4 can be performed in parallel with two data accesses one from D ata M emory one from Program M emory T his capability means that on every loop iteration aM AC operation is being performed At the same time the next data value and coefficient are being fetched and the counter is automatically decremented All without wasting time maintaining loops As the filter code is executed for each input data sample the output of the M AC loop will be written to the output data buffer tx_buf Although this program only deals with single channel input data the result will be written out to both channels by writing to memory buffer addresses tx_buf 1 and tx_buf 2 T he final source code listing is shown on page 15 T he filter algorithm itself is listed under Interrupt service routines T he rest of the code is used for codec and DSP initialization and interrupt service routine definition T hose topics will be explored in future installments of this series THE EZ KIT LITE T he Windows based monitor software provided with the EZ K it Lite makes it possible to load an executable file into the AD SP 2181 on the EZ K it Lite board T his is accomplished through the pull down Loading menu by selecting D ownload user program and Go Figure 5 T his will download the filter program to the ADSP 2181 and start program execution Figure 5 EZ Kit Lite download menu REVIEW AND PREVIEW T he goal of this article was to outline th
28. 6212 and use Faxcode 16 Analog Dialogue 31 3 1997 For information use reply card or see back cover New Product Briefs Analog to Digital Converters 8 Bit 32 MSPS ADC Low AD9280 2 7 to 5 5 V Has 300 MHz analog BW T he AD 9280 is a low cost 8 bit 32 M SPS A D converter with 2 7 to 5 5 V single supply operation and low power consumption 95 mW at3 V It has a wide bandwidth input sample hold 300 M Hz a programmable internal reference and a flexible input structure It also incorporates clamping useful in video dc restoring Sleep mode to conserve power an out of range indicator and 3 state output buffers The AD 9280 is used to digitize high speed analog data in video CCD signal chains scanners etc and com munications systems Performance includes differential non linearity of 0 2 LSB and 7 7 ENOB at 16 MHz The AD 9280 is housed in a 28 pin SSOP for temperatures from 40 to 85 C and is pin compatible to the 10 bit AD 9200 Price in 1000s Is 3 37 Faxcode 2163 or Circle 11 gt 8 10 Bit Serial ADCs AD7823 AD7810 operate on 2 7 5 5 V 8 pin DIP SO SO The AD7823 and AD7810 are pin compatible 8 and 10 bit low power single supply sampling A D converters with serial interfaces and maximum throughput rates of 135 and 350 ksps T hey are housed in 8 pin DIP SOIC and wSOIC packages N ormal dissipation alow 17 5 mW max in full operation drops to 5 uW max in power down
29. EA EA EAR Re K ee eh E K K K ck IK Interrupt vector table EELERLELELLEL ERE AEE ELE EERE LS SNS CARA A Ree han K KK KKK J jump start rti rti rti 00 reset rti rti rti rti 04 IRQ2 rti rti rti rti 08 IRQL1 rti rti rti rti Oc IRQLO ar dm stat flag 10 SPORT 0 tx ar pass ar if eq rti jump next_cmd jump input_samples 14 SPORT 1 rx rti rti rti jump irge rti rti rti Ps 18 IRQE rti rti rti rti 1c BDMA rti rti rti rti 20 SPORT 1 tx or IRQ 1 rti rti rti rti 24 SPORT 1 rx or IRQO rti rti rti rti 28 timer rti rti rti rti 2c power down PEER A A AA KOR RAAB EAE AEA AAA EARL AREA EAA AA AD SP 2181 intialization LEEEELEEEERELEEALEALERELEE SERED RELL EAL ELE KOR EE EEE EAR ER AE KKK J Analog Dialogue 31 3 1997 Start i0 rx_buf remember codec autobuffering uses i0 and i1 lO rx_buf il tx buf I1 tx_buf i3 init_cmds i3 can be used for something else after codec init 3 init_cmds m0 0 ml 1 initialize serial port 0 for communication with the AD 1847 codec call init_sport0 initialize the other system registers etc call init_system_regs initialize the AD 1847 codec call init_1847 ifc b 00000011111111 clear any pending interrupt nop there is a 1 cycle latency for ifc setup pointers for data and coeff
30. ENCY n 1 2 fg nxfs fg 2 ANTI ALIAS FILTER BAND PASS a Ni PETERE I a I nxfs n 1 2 fs fg 2 Figure 1 Aliasing and frequency translation through undersampling Oversampling is not quite the opposite of undersampling in fact it is possible to have a system that is simultaneously oversampling and undersampling Oversampling involves sampling the desired signal at a rate greater than that suggested by the N yquist criterion for example sampling a 200 kH z signal at 1 6 M Hz rather than the minimum 400 kH z required T he oversampling ratio is defined OSR sample rate 2 x input bandwidth Oversampling offers several attractive advantages Figure 2 T he higher sampling rate may significantly ease the transition band requirements of the anti alias filter In the example above sampling a 200 kH z bandwidth signal at 400 kH z requires a perfect brick wall anti alias filter since interferers at 201 kH z will alias in band to 199 kHz Since perfect filters are impossible most systems employ some degree of oversampling or rely on system specifications to provide frequency guard bands which rule out interferers at immediately adjacent frequencies On the other hand sampling at 1 6 MHz moves the first critical alias frequency out to 1 4 M Hz allowing up to 1 2 MHz of transition band for the anti alias filter Analog Dialogue 31 3 1997 NYQUIST SAMPLING OUTPUT OF INADEQUATE ANTI ALIAS FILTER an SIGNALS
31. Hz 2x 1 1 1 2 The application determines which intermodulation products present the greatest problems but the third order products are generally more troublesome because their frequencies tend to be very close to those of the original signals e Signal to noise plus distortion SIN AD T H D measures just the unwanted harmonic energy SIN AD measures all the non signal based energy in the specified portion of the spectrum including thermal noise quantization noise harmonic spurs and non harmonically related spurious signals CDM A code division multiple access systems for example are concerned with the total noise energy in a specified bandwidth SIN AD is a more accurate figure of merit for these applications SINAD is probably the most difficult measurement to make since many spectrum analyzers don t have low enough input noise T he most straightforward way to measure a DAC s SINAD is with an ADC of significantly superior performance T hese specifications or others derived from them represent the primary measures of a DAC s performance in signal synthesis FUNDAMENTAL OUTPUT FIRST IMAGE POWER dBm HARMONIC HARMONIC THIRD IMAGE HARMONIC 90 0 00 6 250 12 50 18 75 applications Besides these there are a number of conventional DAC specifications many associated with video DACs or other applications that are still prevalent on DAC data sheets T hese include integral nonlinearity INL differe
32. OS devices So if these parasitics can be matched there will be little if any charge injection effect T his Is precisely what is done in Analog D evices CM OS switches and multiplexers T he matching is accomplished by introducing a dummy capacitor between the gate and drain of the NMOS device Von CpUMMY MATCHING 10pF PARASITIC Cann CAPACITANCE Vsource 0V VouT CL 1nF Figure 13 Matching parasitics at Vsource 0 V ground 22 U nfortunately the matching is only accomplished under a specific set of conditions i e when the voltage on the Source of both devices is 0 V T he reason for this is that the parasitic capacitances C cpn and C gpp are not constant they vary with the Source voltage W hen the Source voltage of the NM OS and PM OS is varied their channel depths vary and with them Copn and Cepp AS a consequence of this matching at Vsource 0 V the charge injection effect will be noticeable for other values of Vsource O NOTE Charge injection is usually specified on the data sheet under these matched conditions i e Vsource 0 V Under these conditions the charge injection of most switches is usually quite good In the order of 2 to 3 pC max H owever the charge injection will increase for other values of Vsgurce to an extent depending on the individual switch M any data sheets will show a graph of charge injection as a function of Source voltage How dol minimize these effects in my appl
33. OV elssny YZ 16 OIZ LOv 6 dOL euewoy 0 Z8 6 Z O2913S l3S je6nyod CZCILIZO Z xaIeQ HNFS SLE ETZ T9 JNIATV d 3 d puejod ogzzzgr9 TZ leybueys O09 dhu3 lulod 2x3 lamMueys Z6V6VZE GGL u uzu usS 0877789 TZ eybueus yEsEZEg9 OT Buifieg P17 Ald Suu s S Julodj 2x3 996 6ZZ GGL UBUZUBYS T1rt0 6r z9 TZ euB6ueusS TT r8t Z Buoy BuoH 9GH8 v84 16S nouznd 6 1 9tr9 OT 6uifi g 3siq Buea OeYD 9678Z9Z9 OT Builieg SIIUOLJIO J MOV ulus JO 3 Iqnd ti s ldo d OL ET 86 99 YYINOYLYITI Lig Aenuon 1786S 989 6 P17 ZN A83 Jawa W puejeezZ MON VEZT 60 9 080 6666 OE Z OVO DINOYLDITI FTYIOdS ELEEELS EGO AG I U0N 99 F WIXIL SIGOYNA Z09Z0SZ 0V0 PueJ p N Ie2V spuepey oN OZOZ S9 8 Ua PeUeD Oop 6Z68vYZ 0 PIT Fld Ssuu s S 1Julod 2x3 eiskejeW 0026 099 Z PI C240 uO 1l 799 STL Z PIT OD soaluon3 3 yaeg Buo l 66S TOL Z P27 OD POM bojeuy e ioy TEVT99 ZO 21u09 ISe LyYSSS 8E ang PJlu5 C T6S 9 LLTSO899 Z pu lelp ds Go6SZrZ IT ang P Jlu3 e r01r09 9ES S V S SIIIPH TO6T8E Z HS 9WI LIMAY Ney GOOEZ SOSO 4e 0d sn 2eqv 0001068 T OAT JOUAV OvSS6SV T SIIUOLQII J MOLY pueja 9960 ZY8 S9 P27 Id s suu s S UJOILIdeD GQG0 EZ9 IT 16 PIT Wd Se es bojeuy elpul V66LOLE T LI Do ouu2 AWS 6 06 69Z T x 1 eq 3 l3S Meb
34. SIP e207 SI PO X S 3Lld S1J US e ep Bulpnjoul UOIJELUJOJU JO SOUD IV SZvT LE6 T8Z di u Ie31uu3 L epeueo pue v s n xe payewoyne Aq s ys eed l S 1ou uogedde syoog sjeaus e1eq SYSLYWNOGW3H 3d0103 GGOT 2Z8 SZ7 2324S uo BuIySe M v60S TEZ ZL6 Sexo 1S9M OZOS 9VZ Tr seJ 06 t9 STZ glueA s uu d QOOE T9r T18L sp snypesse w O6LL EV9 STZ pue Aue w LLLT 6TS 4v8 SIOUI Ovrr L6r 0 e1b1085 rtrr8 099 L0r epo YHON LEOZ 6SS 80t UNOS T6 6 Tr9 YTL eju10 I ep S391440 SAWS 193910 A9019V4 V S N So dwes A0QEB y JO UO AjJe3 D JON sped uonisinboe ejyep Jd s jnpow Buiuonipuo2o jeuBis Buiss ooid jeubis jeypq 9 so IeuDBis p xiuui pue Hojeuy SI jyo qns ino J Woo Bbojeue MMM dYY 1IS q A PIM PHOM CICO 9YY 008 T uoud VS0 929 80S T XeJ Z SS Jd 9G 797 008 T uoud HOddnNs in1e1 1 1 Xe4pojeuy d DO1VNV 008 T 79S Z9Z 008 T epeued pue y S N ull djay sduejsisse J uuolsnO S191430 SOWNV WOYd d13H 139 OL MOH
35. WO J U P MS IT OT 9 T6 O213S l3S ureds L0S9 S08 TT 32 SPNPOJId ejeq bojeuy e5ujv YNOS S6LL6ST T x 1 eq 3 l3S 01S86ST T DINOYLOITI VWTV elu Aols ELT ZLS L x eql3 l3S OE0 ZZL 8E8 04 S INODOTVIC epieAols 9968 Tr PIT Fld SW IS S 1lulodi 2x3 ssodebuis ZO9E8BZ S60 0D LIOSSNOUYV TSTEVEE S60Z XILNV OV elssny YZ 16 OTZ LOv 6 dOL eluewoy 0 Z8 6 Z O213S l3S jebnyod CZCILIZO Z xaIeQ FNFS SLE ETZ T9 JNIFTV d 3 d pue od 08ZZZ8r9 TZ leybueys 09 dhu3 lulod 2x3 lamMueys Z6V6VZE SSL u uzu usS 08ZZ 8r9 TZ euBueus y6E8EZEg9 OT Buifieg P17 Ald Suu s S lJulodj 2x3 996 6ZZ GGL u uzu usS 1r06 6r z9 TZ euB6ueuS TT r8t Z Buoy BuoH 9GH8 v84 L6S nouznd 6 1 9tr9 OT 6uifi g 3siq Buea OeYD 9678Z9Z9 OT Builieg SIIUOLIIO J MOV ulus JO 3 Iqnd ti s ldo qd OL ET 86 99 YYINOYLYITI Lig Aenuon 1786S 989 6 077 ZN A83 2 W Ww puejeez MON YEZT 60 9 080 6666 OE Z OVO DINOYLDITI FTY IOdS ELEEELS EGO AG S21UON29 F WIXIL SIGOYNA Z09Z0SZ 0V0 Pue p N Ie29V spuepeyyeN OZOZ S9 8 Ua PeUeD OIK W 6Z68rtZ 0 PIT Fld Suu s S 1Julod 2x3 eiskejewW 0026 099 Z PI C240 uO 1l 799 STL Z PIT OD so luon3 3 y eg Buo I 66S TOL Z P27 OD POM bojeuy e ijoy TEVT99 ZO eI UOINA FZ ISe LyYSSS 8EY ang PJlu5 C T6S 9 LLTSO899 Z puj leina
36. amp HFC cable modems Characteristics include update rate of 100 M SPS min 125 typical 2 7 to 5 5 V supply voltage on chip reference 20 mA current output 45 mW dissipation 3V and Sleep mode The CMOS device Is available in a 28 lead SOIC for temperatures from 40 to 85 C An evaluation board is available Prices are 19 18 in 1000s for the AD 9764 150 for the evaluation board Faxcode 2057 or Circle 8 gt Triple Irs Op Amp AD8023 has 250 MHz BW Drives heavy capacitive loads The AD 8023 has a trio of fast settling current feedback operational amplifiers with individual Disable on a single silicon chip T hey can drive loads including capacitive at up to 70 mA while drawing only 10 mA max quiescent current This makes the device useful in RGB video systems that require good flatness over a wide bandwidth while drawing minimal power Bandwidth is 250 MHz 10 MHz with 0 1 dB flatness with 1200 V us slew rate and 30 ns 0 1 Settling 300 pF 1 kQ load Video differential gain and phase errors are 0 06 and 0 02 T he D isable feature 1 3 mA power down high impedance output turnoff time is 30 ns T he AD 8023 operates 40 to 85 C with single 4 2 to 15V or dual 2 1 to 7 5 V supplies and the device is housed in a 14 lead plastic SOIC Price 1000s is 3 99 Faxcode 2192 or Circle 6 gt Dual 10 Bit TxDAC 40 MSPS AD9761 for I amp Q has dual 2x interpolation filters The AD 9761 the latest
37. an be operated with power supplies less than those specified in the data sheet A All of the ADG series switches and multiplexers operate with power supplies down to 5 V or 5 V The Specifications affected by power supply voltage are timing on resistance supply current and leakage current Lowering power supply voltage reduces power supply current and leakage current F or example the ADG411 s Isio f and Ip or are 20 nA and lb on IS 40 nA at 125 C with a 15 V power supply W hen the supply voltage is reduced to 5 V Ic orr aNd Ip orr drop to 2 5 nA while pion iS reduced to 5 nA at 125 C T he supply currents Ipp Iss and I1 are 5 uA maximum at 125 C with at15 V power supply W hen a 5 V power supply is used the supply currents are reduced to 1 uA maximum T he on resistance and timing increase as the power supply is reduced T he Figures below show how the timing and on resistance of the AD G 408 vary as a function of power supply voltage 300 are s 120 ADG408 Ta 25 C ON RESISTANCE VS SUPPLY VOLTAGE N Yoo 5V fives A a 209 ea cl ower o et UNS PING AA se ce SUPPLY VOLTAGE Royn 2 i pa Z _ Se gt P T i o 15 10 5 0 5 10 15 5 7 9 11 13 15 Vp Vs Volts VsuPPLY Volts Figure 2 Timing vs Power Supply Figure 1 On Resistance vs Power Supply Q Someofthe AD G series switches are fabricated on the D process W hat Is it A DI i
38. ased by increasing the area of the NMOS and PM OS devices thus increasing Caps and Copp So trading off Roy for reduced charge injection may also be an option in many applications How can evaluate the charge injection performance of an analog switch or multiplexer T he most efficient way to evaluate a switch s charge Injection performance is to use a setup similar to the one shown below By turning the switch on and off at a relatively high frequency gt 10 kH z and observing the switch output on an oscilloscope using a high impedance probe a trace similar to that shown in Figure 11 will be observed T he amount of charge injected into the load is given by AV oyr x C_ Where AV ou7 isthe output pulse amplitude 15V 5V Qin CL x AVouT Figure 14 Evaluating the charge injection performance of an analog Switch or Multiplexer gt Analog Dialogue 31 3 1997 MORE AUTHORS Continued from page 2 Aengus Murray page 3 of ADI sTransportation amp Industrial Products Division inWilmington MA leads the M otion Control Group s Systems Engineering team He has a BE Elec and a Ph D degree from University College Dublin with a specialism in ac motor control H e continued his work on brushless systems at K ollmorgen Ireland Ltd later became a Senior Lecturer and Director of the Power Electronics Research Laboratory at Dublin City University In his spare time he enjoys skiing and sailing Mary M
39. axcode 2042 2043 or Circle 31 32 O All brand or product names mentioned are trademarks or registered trademarks of their respective holders F or immediate data visit our WorldWideWeb site http wwwanalog com In N orth America call AD l s 24 hour AnalogF ax line 1 800 446 6212 and use Faxcode Analog Dialogue 31 3 1997 19 Ask The Applications Engineer 26 by Mary McCarthy amp Anthony Collins SWITCHES AND MULTIPLEXERS Q Analog Devices doesn t specify the bandwidth of its ADG series switches and multiplexers s there a reason A TheADG series switches and multiplexers have very high input bandwidths in the hundreds of megahertz H owever the bandwidth specification by itself is not very meaningful because at these high frequencies the off isolation and crosstalk will be significantly degraded For example at 1 MHz a switch typically has off isolation of 70 dB and crosstalk of 85 dB Both off isolation and crosstalk degrade by 20 dB per decade T his means that at 10 M Hz the off isolation is reduced to 50 dB and the crosstalk increases to 65 dB At 100 M Hz the off isolation will be down to 30 dB while the crosstalk will have increased to 45 dB So it is not sufficient to consider bandwidth alone the off isolation and crosstalk must be considered to determine if the application can tolerate the degradation of these specifications at the required high frequency Q Which switches and multiplexers c
40. ay to becoming the backbone of the Information Age H owever a roadblock to widespread adoption of the Internet is its painfully slow access time to PCs via the telephone modem T he slow response and consequent user frustration has slowed market growth and prevented the Internet from becoming an indispensable information tool for the average home consumer T he cable network industry has seen this as an opportunity to generate additional revenue by utilizing their vast cable plant resources and 1 G H z network bandwidth to provide higher speed interactive data services to homes institutions and businesses T he major cable industry multi system operators MSOs have announced their intentions to have cable modem service fully deployed by 1998 As originally designed the typical CAT V cable plant was intended for one way delivery of high quality television signals to the home T he prospect of offering cable modems and other interactive video services has required the system owners to upgrade their plants by providing bidirectional signal capability T his has entailed the installation of a bidirectional hybrid fiber coax trunk and 2 way line amplifiers It is estimated that approximately 20 of the existing CATV plants have already been upgraded to full bidirectional capability T his would mean that some 20 million US homes and businesses could take advantage of bidirectional cable service What are the winning advantages of Internet a
41. cCarthy page 20 Is an Applications Engineer in the General Purpose C onverter group in Limerick Ireland working on ADCs and devices for DDS V SE and communications She helps u tj customers resolve circuit and design problems generates data a Aa sheets develops evaluation w boards and aids in new product development M ary has a BE from University College Cork Ireland 1991 In her spare time she enjoys horseback riding and films Anthony Collins page 20 is an Applications Engineer with ADI s General Purpose Converter group Limerick Ireland He provides technical support worldwide for 12 14 bit ADCs power metering devices and analog switches amp multiplexers He helps define new products and generates new product documentation Hehasan Hons Dip EE from Dublin Institute of Technology and a BSc Eng from Trinity College Dublin H is current interests are road biking and passable guitar playing Jim Surber page 3 a Strategic M arketing Engineer in ADI s High Speed C onverter Group is located in Greensboro NC His photo and brief biography appeared in Analog Dialogue 30 3 Dave Robertson page 8 is a Design Engineer in the Analog Devices High Speed Converter group in Wilmington MA His photo and a brief biography appeared in A nalog Dialogue 30 3 Noam Levine page 12 isa Product M anager inADI s Computer Products Division in Norwood MA His photo and a brief biography appeared in Analog D
42. cated in data memory at location rx_buf 2 and place it in a data register to be fed into the filter program T he data arriving from the codec needs to be fed into the filter algorithm via the input delay line using the circular buffering capability of the AD SP 2181 T he length of the input delay line is determined by the number of coefficients used for the filter Because the data buffer is circular the oldest data value in the buffer will be wherever the pointer is pointing after the last filter access Figure 4 Likewise the coefficients always accessed in the same order every time through the filter are placed in a circular buffer in Program M emory MEMORY LOCATION READ WRITE READ WRITE READ 0 X 4 X 8 X 8 X 8 1 X 5 X 5 X 9 X 9 2 X 6 X 6 X 6 3 X 7 X 7 X 7 4 TAP EXAMPLES Y 7 h 0 x 7 h 1 x 6 h 2 x 5 h 3 x 4 Y 8 h 0 x 8 h 1 x 7 h 2 x 6 h 3 x 5 Y 9 h 0 x 9 h 1 x 8 h 2 x 7 h 3 x 6 Figure 4 Example of using circular buffers for filter data input Algorithm Code To operate on the received data the code section published in the last installment can be used with few modifications To implement this filter we need to use the multiply accumulate M AC computational unit and the data address generators The ADSP 2181 s MAC stores the result in a 40 bit register 32 bits for the product of 2 16 bit words and 8 bits to allow the sum to expand without overflowing T his allows intermediate fil
43. ccess via cable modems and the CAT V network over the prevailing telephone modem connection First the cable modem operates in a burst mode this means that while it remains physically connected to the cable plant it only uses network resources when it transmits a burst of data T his allows the cable modem to be effectively always signed on to the Internet and ready for instant two way data transfer To accomplish this with a telephone modem would require a dedicated phone line which leads to the next key advantage of cable modems the cable modem does not tie up a phone line while the user is surfing the net With telephone modem access unless there is a dedicated phone line normal telephone service is suspended during Internet sessions Analog Dialogue 31 3 1997 Another advantage of cable modems is the dramatically increased speed of data delivery C able modems are capable of up to 36 M b s downstream data rates and 10 Mb s upstream compared to the standard telephone modem service of 28 kb s up and downstream 56 kb s max T his many fold increase in data transmission speed means that the Internet access speed will be generally limited by URL file servers rather than the modem baud rate T his is especially important when the user is downloading large graphic video or image files A file that takes 8 minutes to download via a 28 8 kb s telephone modem takes 8 seconds via cable modem T his increased access speed will
44. d hearing your feedback truly another form of Analog Dialogue We are in the midst of an immense work in progress to improve the user friendliness helpfulness and intuitive nature of using the Web site throughout your design process not just for product selection but for support and procurement Our objectives are 1 continually earning your loyalty as a customer 2 attracting more of your colleagues in the industry and 3 achieving an interesting site with consistent rapid and complete content posting one that you will want to visit frequently A few specific things we are seeking to improve are 1 speeding your ability to search the site and to use our search engines for comparative product selection 2 increasing your ability to more easily become informed about what s new to the depth you need 3 making easily available the information you need for making replacements whether it be of competitive products you ve been considering or substitutions for obsolete AD products 4 speeding up the means of getting literature and samples to you 5 making it easier for you to acquire catalog information 6 increasing the ways to better interact with you in terms of improving feedback channels answering applications questions and making the features of our site that you regularly visit more readily accessible to you personally Rome wasn t built in a day but we think you will see visible signs of p
45. data can be read and in automatic power down between conversions mode the AD 7810 dissipates only 27 uW max at 1 ksps and 2 7 mW max at 100 ksps Both devices have microcontroller compatible serial interfaces for fast easy interfacing The AD 7823 and AD 7810 Operate over respective temperature ranges of 40 to 125 C and 40 to 105 C T hey can use an external precision reference or the power supply DIP package prices 1000s are respectively 1 95 amp 2 45 Faxcode 2085 2061 or Circle 15 16 B 8 amp 10 Bit ADCs 2 7 to 5 5 V AD7819 AD7813 have 200 400 ksps thruput The AD7819 and AD 7813 are pin compatible 8 and 10 bit low power single supply sampling A D converters T hey are housed in 16 pin DIP SOIC and TSSOP packages Normally dissipating a low 17 5 mW max in full operation they dissipate 5 uW max in power down and in the automatic power down between conversions mode the AD 7813 dissipates only 34 6 uW max at 1 ksps and 3 5 mW max at 100 ksps Both devices have an identical 8 bit parallel interface for easy interfacing to uPs and DSPs T he AD 7813 reads out 10 bits with a 2nd 2 bit byte The AD 7819 and AD 7813 Operate over respective temperature ranges of 40 to 125 C and 40 to 105 C T hey can use an external precision reference or the power supply Prices 1000s are 1 95 AD 7819 and 2 55 AD 7813 Faxcode 2064 2063 or Circle 12 13 D 24 Bit 2 A ADC AD7731 has buffered inputs
46. ds Go6SZrZ TT ang P Jlu3 e YOTYOS 9ES S V S SIll H TO6T8E Z HS DWI LIMAY Ney GOOEZ SOSO AJeJod sn2eqv 0001068 T ODAT JOUAV OvSS6SV T S3lIlUO l 2 3 MOLY puel 9960 Z8 S9 P27 Ald s suu s S UJOILIdeD GQG0 EZ9 TT 16 PIT Wd Se es bojeuy elpul V66LOLE T LI Do ouu2 AWS 6 06 69Z T x 1 eq 3 l3S Mebuny ZOLO ZOEZ Z PIT u5 SIJUOMCUIYD 8810 S9 Z PIT H X28110 9 Auxa ZTZZ 0S Z buoy BuoH suaaulbu7Z eiauay G89Z t8b Z 24ed BIS S21U401729 7 MOY buoy buoy CVOS6ES T DITIYOIW 828045 0 7 O EOT90 JINOYLIITI 714J0dS 0 10 O8 ZVLLO UOMIWAS ZTT EEL ESTZO HQUID slu uoduuo2 NI3t 0 80S TEV90 UAW 15S O IT 97 680 HOLONGNODIWIS ODSVS ueuu oS 00 68 61 69 10 q e32s l3S 00 0L EZ VE T0 Sluesoduuo2 jadeWig 00 0L 08 Tr TO nbiuo n2 3 19D 00 SZ S9 6r 10 DWF LINAV eouel 009 Z78S 6 AO oxxO puejul4 IT ZZ OT OL S Y luonp l3 pue neH goye gt pewiueq LOL 9 Lv Z x eq 3 l3S 99091z t S O S TOdS X31 WV B1Yyd9ZD 861 6ST T 08 x l eq 3 3S 60SSZE T S8E DINOYLIITI VWT1V eneo 6ELS Z96 Z6 x eq 3 l3S 64 6TS Z6 SOINOYLIITI LY euebing EEE 06Z TT SS 1 3 uuo2 3 S821125 u3 eudiv LIZZ OTL TT ep 1 S021U01729 7 slu uoduuoD2 ABIPUOD 689T 68SS TT Ieuoneuu 1u ebpig lize1g 09 9 GZL Z0 DINOYLIITA 31d3OdS 696v LyZ Z0 2 U04 99 F WIXIL SIQGOYN3 E8 6S OZL
47. e G aAs switch which would otherwise be required to minimize transitional glitches ENABLE AND GAIN CONTROL BUS PROGRAMMABLE CABLE DRIVER AMPLIFIER DATA IN AD9853 DIGITAL QPSK 16 QAM MODULATOR 20 48MHz CLOCK IN TO 750 CABLE CONTROL TA PLANT Figure 4 AD9853 and AD8320 in upstream Tx application T he AD 9853 AD 8320 chipset combination offers the highest dynamic performance available from an integrated chipset for the HFC upstream T x function As Figure 5a shows the chipset will typically deliver a signal to the cable plant s diplexer filter with gt 50 dB spur rejection for a42 M Hz 16 QAM modulated carrier Figures 5b amp c show a typical eye diagram and constellation for a 16 QAM modulated carrier the chipset delivers error voltage magnitude EVM performance of lt 2 1 Q phase imbalance is typically less than 1 due to the all digital modulator scheme Evaluation is facilitated by available board the AD 9853 45PCB which includes AD 9853 AD 8320 and a 45 M Hz LP filter 10 1 2 0 10 I N T1 O OUTPUT dBm LEVEL Volts 1 2 0 10 20 30 40 50 60 70 80 90 100 0 1 5 3 0 FREQUENCY MHz SYMBOLS b Eye diagram 80 a Output spectral plot 1 2 _ s IMAGINARY Q 1 2 1 5 REAL 1 5 REAL 1 c 16 QAM constellation Figure 5 AD9853 AD8320 chipset performance with 42 M Hz carrier 16 QAM modulated 320 ksym s T
48. e discrete time but analog signal processing though generally continuous time may also be in discrete time for example with switched capacitor circuits The Nyquist theorem expresses the fundamental limitation in trying to represent a continuous time signal with discrete samples Basically data with a sample rate of F samples per second can effectively represent a signal of bandwidth up to F 2 H z Sampling signals with greater bandwidth produces aliasing signal content at frequencies greater than F 2 is folded or aliased back into the F J2 band T his can create serious problems once the data has been sampled there is no way to determine which signal components are from the desired band and which are aliased M ost digital communications systems deal with band limited signals either because of fundamental channel bandwidths as in an ADSL twisted pair modem or regulatory constraints as with radio broadcasting and cellular telephony In many cases the 8 signal bandwidth Is very carefully defined as part of the standard for the application for example the GSM standard for cellular telephony defines a signal bandwidth of about 200 kHz IS 95 cellular teleohony uses a bandwidth of 1 25 MHz and aDMT ADSL twisted pair modem utilizes a bandwidth of 1 1MHz In each case the Nyquist criterion can be used to establish the minimum acceptable data rate to unambiguously represent these signals 400 kHz 2 5 M Hz and 2 2 M Hz res
49. e music synthesizer Phat circuitry for stereo output phase expansion a joystick interface with timer serial ports for DSP and 12S 2 TheM ODIO drivers use C PU resources to implement the flow of high speed fax data and voice with Echo Cancellation while simultaneously handling audio signals T he AD 1821 operates from a 5 V supply is housed in a 100 lead PQFP Price 10 000 per month is 18 15 modem only Faxcode 2252 or Circle 21 B LP Supervisory IC ADM1232 provides manual or Vcc out of tolerance Reset The ADM1232 is a microprocessor supervisory circuit with existing second sources It can monitor uP supply voltage tolerance selectable 5 10 it can detect an external interrupt and its watchdog timer determines with selectable time delay when the uP has locked up T he device can then respond to any of these stimuli with a direct or complementary RESET signal A universally required component of digital systems typical applications of the ADM 1232 are in microprocessor systems portable equipment computers controllers intelligent instruments automotive systems and for protection against uP failure The ADM 1232 operates at 5 V with 500 uA maximum quiescent current drain It is available for 40 to 85 C in 8 lead PDIP narrow SOIC and microSOIC as well as 16 lead wide SOIC Price 1000s is 0 90 Faxcode 2182 or Circle 24 gt All brand or product names mentioned are trademarks or regist
50. e steps from an algorithm description to a DSP executable program that could be run ona hardware development platform Issues introduced include software development flow architecture description source code generation data 1 0 and the EZ K it Lite hardware platform T here are many levels of detail associated with each of these topics that this brief article could not do justice to Further information Is available in the references below T he series will continue to build on this application with additional topics T he next article will examine data input output 1 0 issues in greater detail through the processor interrupt structure and discuss additional features of the simple filter algorithm REFERENCES ADSP 2100 Family Assemble Tools amp Simulator M anual Consult your local Analog D evices Sales Office ADSP 2100 Family User s M anual Analog Devices Free Circle 4 gt Analog Dialogue 31 3 1997 FIR Filter code listing for EZ Kit Lite ERASER ERE ELTA KOR KOR KOR KOR KOR KOR KOR EEE LEED EEL EERE ELLE A EL K EERE ER hello81 dsp template file for 2181 ez kit lite board T his sample program is organized into the following sections Assemble time constants system h Interrupt vector table ADSP 2181 intialization initl1847 dsp ADSP 1847 codec intialization initl1847 dsp Interrupt service routines T his program implements a simple talk through with the AD 1847 codec
51. eiver and transmitter physical layer the PH Y that modulates demodulates the data and IN THIS ISSUE Volume 31 Number 3 1997 24 Pages Editors Notes AUENONS ces eee See sre ae yes ee eee 2 mohe ast Isue 0 aren eE S Pas esas 2 Innovative mixed signal chipset targets hybrid fiber coaxial cablemodems 3 Poweful design tools for motion control applications 6 Selecting mixed signal components for digital communications systems V 8 DSP 101 Part 3 Implement algorithms on a hardware platform 12 N ew Product Briefs Amplifiers D A Converters References 16 Analog to Digital Converters r 17 Digital Communications and Supervisory 18 Signal Processing Regulation and Control 19 Ask T he Applications Engineer 26 Switches and multiplexes 20 More Authors Patents sa nn San PA ho se a pss 23 3 a media access controller the MAC that performs the master system control function When the standards are fully deployed the downstream data delivery will take place in the 42 850 MHz band with existing 6 M Hz CATV network channel spacing T he downstream digital modulation format will be 64 QAM quadrature amplitude modulation with a future migration to 256 QAM The HFC data delivery system will be asymmetric the data rate will be faster downstream than upstream T his is generally compatible with Internet
52. empco Minimum full load output current is 5 mA Each is available in three performance grades specified at 40 to 85 C and 25 to 85 C T hey are available in 8 lead SOICs and T O 92s and 3 pin T SSOPs Prices start at 1 95 in 1000s Faxcode 2110 or Circle 7 gt Dual 8 Bit Serial DAC Lo power 2 7 5 5 V Ad7303 in 8 pin PDIP SOIC wSOIC The AD 7303 is a dual 8 bit serial input voltage output D A converter with a supply voltage range of 2 7 to 5 5 V Its on chip precision output voltage buffers allow the DAC outputs to swing rail to rail T he shared input is a 3 wire serial interface that Operates at clock rates up to 30 M Hz it is compatible with QSPI SPI microwire and digital signal processor interface standards The control portion of the 16 bit input register addresses the relevant DAC provides device or chip power down selects internal or external reference and can provide for simultaneous updating Ideal for portable battery operated equipment the AD 7303 consumes only 7 5 mW max at 3 V and less than 3 uW with full power down It is available in 8 pin plastic DIP SOIC and uSOIC for 40 to 105 C Prices start at 2 35 in 1000s Faxcode 2044 or Circle 10 B All brand or product names mentioned are trademarks or registered trademarks of their respective holders F or immediate data visit our WorldWideWkb site http wwwanalog com In N orth America call AD l s 24 hour AnalogF ax line 1 800 446
53. ered trademarks of their respective holders F or immediate data visit our WorldWideWeb site http www analog com In N orth America call AD l s 24 hour AnalogF ax line 1 800 446 6212 and use Faxcode 18 Analog Dialogue 31 3 1997 For information use reply card or see back cover New Product Briefs Signal Processing Regulation amp Control Low Cost SHARCs ADSP 21061 for 5 V ADSP 21061L for 3 3 V The ADSP 21061 and ADSP 21061L are fast up to 50 MIPS 150M FLOPS low cost versions of the SHARC super Harvard architecture computer 32 bit floating point processor family C ode compatible to their kin they differ mainly in memory 1 M bit of on chip SRAM vs up to 4 M bits with 6 instead of 10 DMA channels and no link ports nevertheless up to 6 SHARCs can be used in cluster multiprocessing T hey are supported by SHARC EZ Kit Lite low cost evaluation board and development tools including a C compiler Applications include prosumer audio communications imaging industrial H oused in a240 lead metric PQ F P for 0 to 85 C peak performances of 100 120 150 M FLOPS are available at 33 40 50 MIPS Prices in 1000s for the AD SP 21061 and L start at 64 39 T he EZ K it Lite is 179 Circle 26 25 ADSP 21061 21061L B AC Motor Controller Single chip ADMC330 joins DSP amp MC peripherals The ADM C330 is a low cost single chip controller comprising a 20 MIPS ADSP 2171 core with on chip RAM and
54. f the discharge path for this injected positive charge is a high impedance 100 M Q T he result is that the load capacitance stores this charge until the switch is turned on again T he simulation plot clearly shows this with the voltage on C as a result of charge injection remaining constant at 170 mV until the switch is again turned on at 25 us At this point an equivalent amount of negative charge is injected onto the output reducing the voltage on C to 0 V At 35 us the switch is turned on again and the process continues in this cyclic fashion 1000 5us 15ys 25ps Figure 10 Timing used for simulation in Figure 11 21 SIMULATION SHOWING 100kHz CHARGE INJECTION EXPANDED SCALE 0 5 10 15 20 25 30 35 40 TIME ps Figure 11 Output of simulation to show the effect of charge injection switching at 100 kHz At lower switching frequencies and load resistance the switch output would contain both positive and negative glitches as the injected charge leaks away before the next switch transition 100 SWITCH OUTPUT AT LOW SWITCHING FREQUENCY AND LOW RL 200 0 05 10 15 20 25 30 35 4 0 TIME ms Figure 12 Switch output at low switching frequencies and low resistive loads Q A What can be done to improve the charge injection performance of an analog switch As noted above the charge injection effect is caused by a mismatch in the parasitic gate to drain capacitance of the NMOS and PM
55. fied levels to ensure that they do not create interference with other signals in the communications medium Several specifications can be used Analog Dialogue 31 3 1997 to measure the dynamic performance of D A converters in the frequency domain see Figure 4 Spurious free dynamic range SFDR the difference in signal strength dB between the desired signal could be single tone or multi tone and the highest spurious signal in the band being measured Figure 4 Often the strongest spurious response is one of the harmonics of the desired output signal In some applications the SFDR may be specified over a very narrow range that does not include any harmonics For narrowband transmitters where the DAC is processing a signal that looks similar to a single strong tone SFDR is often the primary spec of interest Total harmonic distortion THD while SFDR indicates the strength of the highest single spur in a measured band T H D adds the energy of all the harmonic spurs say the first 8 e Two tone intermodulation distortion IM D if the D A converter has nonlinearities it will produce a mixing action between synthesized signals For example if a nonlinear DAC tries to synthesize signals at 1 1 and 1 2 MHz second order intermodulation products will be generated at 100 kHz difference frequency and 2 3 MHz sum frequency T hird order intermodulation products will be generated at 1 3 MHz 2x 1 2 1 1 and 1 0 M
56. g is 100 pinT QFP Bundled per channel cost is 28 Circle 20 B RS 485 Transceivers Full duplex ADM488 489 are in 8 pin SOIC TSSOP 14 T heAD M 488 and AD M 489 are low power full duplex receive and transmit differential line transceivers suitable for communication on multipoint bus transmission lines Like other industry standard devices they meet EIA Standards RS 485 and RS 422 but with less quiescent current 37 uA lpp greater supply tolerance 10 and smaller packaging TSSOP ADM 489 than is typically available in comparable devices In addition their 2 kV EFT protection meets IEC 1000 4 4 and EMI immunity meets IE C 1000 4 3 T hey are short circuit protected and have controlled slew rate for low EM I T he ADM489 is available in 14 pin DIP and SOIC as well as 16 pinT SSOP the ADM488 is in 8 lead plastic DIP and narrow body SOIC Supply voltage is 5 V Operation is from 40 to 85 C Price 1000s Is 1 10 Faxcodes 2179 or Circle 23 B MODIO HSP Codec AD1821 single chip audio amp comm subsystem for PCs The single chip AD1821 MODIO modem over audio Soundcomm HSP audio and communications subsystem for personal computers includes the AD 1821 mixed signal controller IC and M ODIO host signal processing H SP software drivers It has full legacy compatibility with applications written for Soundblaster Pro and AdLib also servicing M icrosoft PC 97 applications Included are an OPL3 compatibl
57. gger All required gate drive circuitry T he board takes the PWM signals generated by the processor module and feeds them directly to an International Rectifier 1R 2132 gate drive circuit that provides the appropriate drive signals for the three low side and the three high side switches in the inverter Protection circuits T he AD vanced Powl R train provides automatic shutdown of the power stage in the event of an overvoltage overcurrent overtemperature or earth fault condition T he fault signal passed to the DSP based controller may also be used in a suitable interrupt service routine Sensor circuits The AD vanced PowlRtrain board includes all necessary voltage and current sensing to implement a wide variety of control structures gt PowlR train is a trademark of International Rectifier C orp Selecting Mixed Signal Components for Digital Communications systems Part V Aliases Images and spurs by Dave Robertson Part Analog Dialogue 30 3 provided an introduction to the concept of channel capacity and its dependence on bandwidth and SNR part II 30 4 briefly summarized different types of modulation schemes part III 31 1 discussed different approaches to sharing the communications channel including some of the problems associated with signal strength variability Part IV 31 2 examined some of the architectural trade offs used in digital communications receivers including the problems with frequency tran
58. gnals 5 633 636 to Hooman Reyhani for Half Gray digital encoding method and circuitry 5 634 076 to Douglas Garde and M ark Valley for DMA controller responsive to transition of a request signal between first state and second state and maintaining of second state for controlling data transfer 5 635 640 to John Geen for Micromachined device with rotationally vibrated mass 5 635 810 to Rakesh G oel for Control system for a permanent magnet synchronous motor 5 637 901 to David Beigel Edward Wolfe and William K rieger for Integrated circuit with diode connected transistor for reducing ESD damage 5 637 993 to D avid Whitney and M oshe G erstenhaber for Error compensated current mirror 5 638 010 to Robert Adams for Digitally controlled oscillator for a phase locked loop providing a residue signal for use in continuously variable interpolation and decimation filters e 5 639 542 to Roger Howe Richard Payne and Stephen Bart for Sub ground plane for micromachined device 5 640 039 to K evin Chau Roger H owe Richard Payne Yang Zhao T heresa Core and Steven Sherman for Conductive plane beneath suspended microstructure 5 644 312 to K enneth Deevy and Philip Quinlan for ROM encoder circuit for flash ADCs with transistor sizing to prevent sparkle errors 5 646 968 to Janos Kovacs Ronald Kroesen and Kevin McCall for Dynamic phase selector phase locked loop circuit
59. he output of D A converters have enjoyed far less visibility In the case of aD A converter it isnot unpredictable interferers that are a concern but the very predictable frequency images of the DAC output signal For a better understanding of the DAC image phenomenon Figure 3 a b illustrates an ideal 9 sine wave and DAC output in both the time and frequency domains It is important to realize that these frequency images are not the result of amplitude quantization they exist even with a perfect high resolution DAC T he cause of the images is the fact that the D A converter output exactly matches the desired signal only once during each clock cycle During the rest of the clock cycle the DAC output and ideal signal differ creating error energy T he corresponding frequency plot for this time domain error appears as a Set of Fourier series image frequencies c For an output signal at frequency F xu synthesized with a DAC updated at F dox images appear at NF aox Fout T he amplitude of these images rolls off with increasing frequency according to sin TU F out F clock TU F out F clock leaving nulls of very weak image energy around the integer multiples of the clock frequency M ost DAC outputs will feature some degree of clock feedthrough which may exhibit itself as spectral energy at multiples of the clock T his produces a frequency spectrum like the one shown in Figure 4 1 0 IDEAL OUTPUT SIGNAL LEVEL
60. he required memory T wo devices are described here the AD M C 330T designed for low to medium performance dynamic requirements and the ADM C 300T which extends the single chip capability to control of high performance servo drives ADMC330 Single Chip DSP Based Motor Controller see Figure 1 The ADM C330 integrates a 20 MIPS DSP core 2K word program memory RAM 2K word program memory ROM 1K word data memory RAM 2 serial ports and a variety of motor control peripherals onto a single chip T he DSP core Is similar to that used in the 16 bit fixed point AD SP 2171 T he motor control peripherals include 7 analog inputs with a comparator based AD C subsystem that permits 4 conversions per PWM period In addition a sophisticated 3 phase 12 bit PWM system enables all necessary inverter switching signals to be generated timed to within 100 ns with minimal processor overhead D ead time of these PWM signals may be adjusted in the processor so that no external logic is required T he PWM unit includes special modes for brushless dc motors or electronically commutated motors where only two of the three motor phases conduct at the same time In addition the ADM C330 Includes 8 digital I O lines a watchdog timer a general purpose 16 bit timer and two auxiliary PWM outputs ADMC300 Single Chip DSP Based Servo Motor Controller Figure 2 High performance servo drives for robotics and machine tools require high resolution AD Cs and a pos
61. ialogue 31 1 David Skolnick page 12 is aT echnicalW riter in AD I s Computer Products Division in Norwood MA His photo and a brief biography appeared in Analog Dialogue 31 1 gt NEW PATENTS not available from A nalog D evices 5 613 611 to Brian Johnson Robert M alone M William M iller and Jeffrey M oeller for Carrier for integrated circuit package 5 623 621 to Douglas G arde for Apparatus for generating target addresses within a circular buffer including a register for storing position and size of the circular buffer 5 625 359 to James Wilson Ronald Cellini and James Sobol for Variable sample rate ADC 5 627 401 to Kevin Yallup for Bipolar transistor operating method with base charge controlled by back gate bias 5 627 537 to Philip Quinlan and K enneth D eevy for Differential string DAC with improved integral nonlinearity performance gt 5 627 715 to A Paul Brokaw for Circuit construction for protective biasing 5 627 867 to David Thomson for Watchdog circuit employing minimum and maximum interval detectors 5 629 652 to Frederick Weiss for Band switchable low noise voltage controlled oscillator VCO for use with low Q resonator elements 5 631 598 to Evaldo Miranda Todd Brooks and A Paul Brokaw for Frequency compensation for a low drop out regulator 5 631 968 to Douglas Frey and Patrick Copley for Signal conditioning circuit for compressing audio si
62. iasing filter can be quite simple Sigma delta modulators use feedback circuitry to shape the frequency content of quantization noise pushing it to frequencies away from the signal band of interest where it can be filtered away T his is possible only in an oversampled system since by definition oversampled systems provide frequency space beyond the signal band of interest Where conventional converters allow for a 3 dB octave conversion gain through decimation sigma delta converters can provide 9 15 21 or more dB octave gain depending on the nature of the modulator design high order loops or cascade architectures provide more aggressive performance gains In a conventional converter quantization noise is often approximated as white spread evenly across the frequency spectrum For an N bit converter the full scale signal to quantization noise ratio SQN R will be 6 02 N 1 76 dB over the bandwidth from 0 to F J2 The white noise approximation works reasonably well for most cases but trouble can arise when the clock and single tone analog frequency are related through simple integer ratios for example when the analog Input is exactly 1 4 the clock rate In such cases the quantization noise tends to clump into spurs a considerable departure from white noise While much has been written in recent years about anti aliasing and undersampling operations for A D converters corresponding filter problems at t
63. ication T he effect of charge injection is a voltage glitch on the output of the switch due to the injection of a fixed amount of charge T he glitch amplitude is a function of the load capacitance on the switch output and also the turn on and turn off times of the switch T he larger the load capacitance the smaller will be the voltage glitch on the output i e Q C xV orV Q C and Q is fixed Naturally it may not always be possible to increase the load capacitance because it would reduce the bandwidth of the channel H owever for audio applications increasing the load capacitance is an effective means of reducing those unwanted pops and clicks Choosing a switch with a slow turn on and turn off time is also an effective means of reducing the glitch amplitude on the switch output T he same fixed amount of charge is injected over a longer time period and hence has a longer time period in which to leak away T he result is a wider glitch but much reduced in amplitude T his technique is used quite effectively in some of the audio switch products such as the SSM 2402 SSM 2412 where the turn on time is designed to be of the order of 10 ms Another point worth mentioning is that the charge injection performance is directly related to the on resistance of the switch In general the lower the Ron the poorer the charge injection performance T he reason for this is purely due to the associated geometry because Ron is decre
64. icients i2 Filt_data 2 filt_data i5 filt_coefs m5 1 I5 filt_coefs imask b 0000110000 enable rx0 interrupt TLLTL LT timer SPORT 1 rec or IRQO SPORT 1 trx or IRQ1 BDMA e TROE IRQLO IRQL1 IRQ2 CAAP DEE coe bese SA EEA EE EE EEEE wait for interrupt and loop forever Lla a a a a a a aa a a S J talkthru idle jump talkthru PEERI I AA A A EER EEE ELAR A O A A E K EERE LANA EEL EERE EAL Interrupt service routines PEE O KOR O A E E A KOR KOR A K A A A E K E A K A E K E E K K KK Kk input_samples ena sec_reg ax0 dm rx_buf 1 dm i2 m1 ax0 use shadow register bank read data from converter write new data into delay line pointer now pointing to oldest data cntr taps 1 mr 0 mx0 dm i2 m1 my0 pm i5 m5 clear accumulator get first data and coefficient value do filt_loop until ce set up zero overhead loop filt_loop mr mr mx0 my0 ss mx0 dm i2 m1 my0 pm i5 m5 MAC and two data fetches mr mr mx0 my0 rnd final multiply round to 16 bit result if mv saat mr check for overflow dm tx_buf 1 mr1 dm tx_buf 2 mr1 rti endmod output data to both channels 15 New Product Briefs For information use reply card or see back cover Amplifiers D A Converters References
65. in the domain of ADI s mixed signal and linear core competencies T he AD 9853 AD 8320 upstream T x chipset available now integrates the high speed digital and analog blocks that provide a complete ASIC solution for the HFC upstream transmitter requirement The AD 9853 is a modulator function that has been specifically defined to meet the requirements of both interoperable and proprietary implementations of the H F C upstream function T he AD 8320 is a companion cable driver amplifier with a digitally programmable gain function matched to the output of theAD 9853 modulator it directly drives the cable plant with the modulated carrier Together the AD 9853 and AD 8320 fully meet the HFC return path requirement The AD9853 CMOS digital modulator combines high speed conversion direct digital synthesis and digital signal processing technologies The modulator architecture is digital throughout which provides definite advantages in 1 Q channel phase and amplitude matching and long term modulator stability The AD 9853 is programmed and controlled via a serial control bus that is 12C compatible T he basic modulator block consists of an input channel encoder which formats the input data stream into the desired bit mapped constellation and modulation format T he data stream is demultiplexed into I Q channel data paths that are individually FIR filtered to provide the desired pulse response characteristic for controlled output burst ramping
66. ition sensor interface to meet the demanding performance requirements T he ADM C300 addresses these needs in a single chip DSP based solution for these applications The ADM C 300 s additional functionality for more demanding applications includes aD SP core enhanced for 25 M IPS performance In addition the program memory RAM has been doubled to 4K words T he need for multichannel high resolution ADCs is met by including five independent sigma delta A D Cs that provide 12 bits of resolution Analog signal expansion is made possible by the provision of three external multiplexer control lines In addition the ADM C 300 facilitates position sensing via an encoder interface that allows easy connection to an incremental encoder D evelopmentTools Since software is the key to the use of digital equipment powerful processing capability requires an equally powerful development system in order to use these sophisticated motor controllers in real applications Both processors come with See M otion Control Chip Sets in Analog Dialogue 30 2 1996 pp 3 5 tFor technical data consult our Web site wwwanalog com use F axback to request 2126 and 2253 see page 24 or use the reply card circle 2 MOTOR CONTROL PERIPHERALS SYSTEM WATCHDOG 8 DIGITAL VO TIMER TWO 8 BIT AUX PWMS Figure 1 The ADMC330 single chip DSP based motor controller Analog Dialogue 31 3 1997 25 MIPS FIXED POINT DSP CORE 1K DATA MEMORY RAM 4K PROGRAM
67. le GENERATE ARCHITECTURE Pee ARCHITECTURE DESCRIPTION ay he aia GENERATE ASSEMBLY ASSEMBLER SOURCE ASM21 DSP CODE GENERATION AND OR GENERATE c C Z a E vscoasia SARAN E pas SYSTEM VERIFICATION SIMULATOR SIM21xx WORKING CODE Figure 2 Software development flow SOFTWARE VERIFICATION TARGET E s ROM petri 5 Architecture description First the user creates a software description of the hardware system on which the algorithm runs T he system description file includes all available memory in the system and any memory mapped external peripherals Below is an example of this process using the AD SP 2181 EZ K it Lite Source code generation M oving from theory into practice this step where an algorithmic idea is turned into code that runs on the DSP is often the most time consuming step in the process T here are several ways to generate source code Some programmers prefer to code their algorithms in a high level language such as C others prefer to use the processor s native assembly language Implementations in C may be faster for the programmer to develop but compiled D SP code lacks efficiency by not taking full advantage of a processor s architecture Assembly code by taking full advantage of a processor s design yields highly efficient implementations But the programmer needs to become familiar with the processor s native assembly language M ost effective is combining
68. le implementations of cable modems T he AD 9853 also includes an output serial data control function for interfacing directly to theA D 8320 cable driver amplifier T his control function allows the AD 9853 to enable the AD 8320 automatically at the appropriate time in a burst transmission sequence and allows the cable modem s M AC function to control the output power of the modem via the AD 9853 s control bus T he AD 9853 modulator output is connected to the input of the AD 8320 programmable cable driver amplifier through an external low pass filter which is necessary to suppress the aliased images that are generated by the DAC s sampled output T he first aliased image occurs at F campling F out Which necessitates a fairly sharp cutoft low pass filter function An inexpensive 7 pole elliptical low pass passive 75 ohm LC filter can be implemented between theAD 9853 and AD 8320 to suppress the output aliases sufficiently for the HFC network application vccL VCC GND O O O DATA LATCH mI PD Wee DATA SHIFT REGISTER Q O DATEN CLK SDATA Figure 3 Block diagram of AD8320 digitally programmable cable driver amplifier T he AD 8320 Is a digitally programmable cable driver amplifier using a bipolar IC process that directly interfaces to the 75 Q cable plant It provides 36 dB of programmable gain range with a maximum power output level gt 18 dBm 6 2 V into a 75 Q load T he gain of the AD 8320 is controlled via a
69. m M A Analog Dialogue One Technology Way P O Box 9106 Norwood MA 02062 9106 Published by Analog Devices Inc and available at no charge to engineers and scientists who use or think about C or discrete analog conversion data handling and D SP circuits and systems C orrespondence is welcome and should be addressed to Editor Analog Dialogue at the above address Analog Devices Inc has representatives sales offices and distributors throughout the world Our web site is http www analog com For information regarding our products and their applications you are invited to use the enclosed reply card write to the above address or phone 781 937 1428 1 800 262 5643 U S A only or fax 781 821 4273 Analog Dialogue 31 3 1997 Innovative Mixed Signal Chipset Targets Hyorid Fiber Coaxial Cable Modems Jim Surber and Curt Ventola T he world is on the brink of anew era of widespread access to the information super highway and cable modems are poised to provide the high speed on ramp C able modems enable a CAT V system with bidirectional hybrid fiber coax HFC capability to serve as a two way high speed data port which can be utilized to provide telephony and Internet access service to the home T hough a relatively small percentage of the US population is presently connected to the Internet clearly its reputation as a valuable advertising and information resource is quickly spreading the Internet is well on its w
70. menu T he sample screen from the ADM C330 debugger shown in Figure 3 illustrates many of the features of the debugger Additional software tools such as the assembler linker and PROM programmer are also included For stand alone operation the evaluation boards may also use external memory for boot program loading FUNCTION ICONS DISASSEMBLED CODE PLOT MEMORY CAPABILITY DSP CORE REGISTERS L eee Se CONTENTS OF SSS SS DATA MEMORY s PERIPHERAL REGISTERS Figure 3 Sample Output Screen of Motion Control Debugger for ADMC330 ADvanced Powi Rtrain n order to develop real motor control solutions the computing power of the DSP must be combined with a suitable power electronic converter that produces the required voltages to drive the motor in response to the control commands and can furnish the necessary currents T he ADvanced PowlRtrain board represents a new departure in development systems for real world motor control systems T he board integrates Analog D evices s high performance D SP based motor controllers with an appropriate International Rectifier Analog Dialogue 31 3 1997 www irf com PowlR train integrated power module it provides all of the necessary circuitry to permit development of motor control algorithms for a variety of applications Using plug in interchangeable processor modules the user can choose the level of control appropriate for the application With the AD M C 33
71. mplications As F igure 3 shows the image amplitudes are actually points on a sinx x envelope in the frequency domain T he decreasing amplitude of sinx x with frequency suggests that the higher frequency images will be attenuated and the amount of attenuation may vary greatly depending on where the output frequency is located with respect to multiples of the clock frequency T he sinx x envelope is the result of the DAC s zero order hold effect the DAC output remains fixed at target output for most of clock cycle T his is advantageous for baseband DACs but for an undersampling application a return to zero DAC that outputs ideal impulses would not suffer from attenuation at the higher frequencies Since ideal impulses are physically impractical actual return to zero DACs will have some rollof of their frequency domain envelopes T his effect can be pre compensated with digital filtering but degradation of DAC dynamic performance at higher output frequencies generally limits the attractiveness of DAC undersampling approaches F requency domain images are but one of the many sources of spurious energy in a DAC output spectrum While the images discussed above exist even when the D A converter is itself oerfect most of the other sources of spurious energy are the result of D A converter non idealities In communications applications the transmitter signal processing must ensure that these spurious outputs fall below speci
72. n 8 bit SPI serial control word T heAD 8320 accomplishes programmable gain control with a bank of 8 binary weighted transconductance gm stages which are connected in parallel to their respective load resistors T he total attentuation of the core is determined by the combination of Gm Stages selected by the data latch T he eight gm stages with their 256 levels of attenuation provide a linear gain function with a dynamic range of 36 dB 64 V V full scale T he AD 8320 s harmonic distortion is typically 57 2 dB for a 42 M Hz output and 54 dB for 65 M Hz output at an output power level of 12 dBm into 75 Q This dynamic performance supports the requirements of cable telephony and data services over the HFC network T he AD 8320 s output stage has a dynamic output impedance of 75 Q This allows for direct single ended connection of the device output to the CAT V plant without back termination retaining the 6 dBm of load power that would be lost using the 75 Q back termination resistor required by the traditional low output Z driver amplifier In fact the AD 8320 maintains Analog Dialogue 31 3 1997 75 Q impedance at its output during device power down to minimize glitches during transitions T his helps minimize line reflections and insures proper filter operation for any forward mode device sharing the cable connection Another advantage of the dynamic 75 Q output impedance is that it saves cost significantly by eliminating an expensiv
73. n SFDR of 72 dBc On chip frequency and phase registers can be used to perform modulation such as FSK PSK and QPSK Frequency accuracy can be controlled to 1 part in 4x10 A serial interface is provided for loading settings and modulation signals Typical applications include DDS tuning and digital demodulation H oused in a 16 pinT SSOP it operates with a 3 or 5 V single supply consuming 45 mW A power down capability 3 amp 5 mW residual power with 3 amp 5 V supplies aids power conservation in battery powered operations Operation is from 40 to 85 C Price in 1000s is 5 00 Faxcode 2210 or Circle 22 gt 1 Chip RAS Modem Interfaces ISP serial T1 or E1 lines to digital network The ADSP 21mod870 is the world s first complete single chip digital modem for remote access servers RAS Itis optimized for implementing a complete V 34 56K modem Since its bundled cost includes software controller memory and data pump it needs no external memory or data controller At 2 58 cm 0 4 in2 and dissipating only 140 mW 3 3 V in the active mode it has the smallest size and lowest dissipation per channel plus the lowest cost among available alternatives Based on the ADSP 2100 family architecture each chip i e modem port can be reprogrammed on demand N ew protocols can be downloaded existing protocols updated Any protocols may be loaded automatically depending on the user s modem speed Packagin
74. ntial nonlinearity DNL glitch energy more accurately glitch impulse settling time differential gain and differential phase While there may be some correlation between these time domain specifications and the true dynamic measures the time domain specs aren t as good at predicting dynamic performance Even when looking at dynamic characteristics such as SFDR and SIN AD it is very important to keep in mind the specific nature of the signal to be synthesized Simple modulation approaches like QPSK tend to produce strong narrowband signals The DAC s SFDR performance recreating a single tone near full scale will probably be a good indicator of the part s suitability for the application On the other hand modern systems often feature signals with much different characteristics such as simultaneously synthesized multiple tones for wideband radios or discrete multi tone DMT modulation schemes and direct sequence spread spectrum modulations such as CD M A T hese more complicated signals which tend to spend much more time in the vicinity of the DAC s mid and lower scale transitions are sensitive to different aspects of D A converter performance than systems synthesizing strong single tone sine waves Since simulation models are not yet sophisticated enough to properly capture the subtleties of these differences the safest approach is to characterize the DAC under conditions that closely mimic the end application Such requireme
75. nts for characterization over alarge variety of conditions accounts for the growth in the size and richness of the datasheets for D A converters gt For Further Reading For detailed discussion of discrete time artifacts and the N yquist T heorem Oppenheim Alan V and Schaeffer Ronald W Discrete Time Signal Processing Englewood Cliffs NJ Prentice H all 1989 For more details on sigma delta signal processing and noise shaping N orsworthy Steven R Schreier Richard Temes G abor C Delta Sigma Data Converters Theory Design and Simulation NewYork IEEE Press 1997 For more details on DAC spectral phenomena H endriks Paul Specifying Communication DACs IEEE Spectrum magazine July 1997 pages 58 69 A CLOCK FEEDTHROUGH lass Wi Wasa EA THIRD HARMONIC IMAGE 25 00 31 25 37 50 43 75 50 00 FREQUENCY MHz ASEBAND 1ST NYQUIST ZONE 2ND NYQUIST ZONE 3RD NYQUIST ZONE 4TH NYQUIST ZONE Figure 4 Different error effects in the output spectrum of a DAC Analog Dialogue 31 3 1997 11 DSP 101 Part 3 Implement Algorithms on a Hardware Platform by Noam Levine and David Skolnick So far we have described the physical architecture of the DSP processor explained how D SP can provide some advantages over traditionally analog circuitry and examined digital filtering showing how the programmable nature of D SP lends itself to such algorithms N ow we look at the process of implementing a fini
76. o summarize the upstream transmitting chipset with its high level of functional integration and state of the art mixed signal technology today offers an effective silicon solution for the two way HFC network to help usher in the next wave of information resources for the home consumer D evelopments to look forward to include compact downstream tuners and demodulators and ultimately a single chip complete cable modem solution gt 5 Powerful Design Tools for Motion Control Applications Finbarr Moynihan Paul Kettle Aengus Murray and Tom Howe Introduction T he need for sophisticated solutions for motor control continues to increase in the consumer appliance industrial and automotive markets A wide variety of motor types are in use depending on the application the most common include the ac induction motor permanent magnet synchronous motor brushless dc motor and such newer designs as the switched reluctance motor Indeed many applications which were formerly dominated by constant speed mains fed induction motors now require the sophistication of variable speed control In some applications such as compressors fans and pumps this need for increased sophistication is driven by legislation and consumer demand for higher operating efficiencies Elsewhere high performance applications in process control robotics and machine tools demand variable speed and increased precision achievable only by the use of sophistica
77. oduce phase distortion at the edge of the passband jeopardizing signal recovery D esigners must also be aware of distortion requirements for anti alias filters in general the pass band distortion of the analog anti alias filters should be at least as good as the A D converter since any out of band harmonics introduced will be aliased Even if strong interferers are not present noise must be considered in anti alias filter design Out of band noise is aliased back into the baseband just like out of band interferers For example if the filter preceding the converter has a bandwidth of twice the N yquist band signal to noise SN R will be degraded by 3 dB assuming white noise while a bandwidth of 4x Nyquist would introduce a degradation of 6 dB Of course if SNR is more than adequate wide band noise may not be a dominant constraint Aliasing has a frequency translation aspect which can be exploited to advantage through the technique of undersampling To understand undersampling one must consider the definition of the N yquist constraint carefully N ote that sampling a signal of bandwidth F 2 requires a minimum sample rate gt F T his F 2 bandwidth can theoretically be located anywhere in the frequency spectrum e g NF to N 1 2 F not simply from dc to F 2 T he aliasing action like a mixer can be used to translate an RF or IF frequency down to the baseband Essentially signals in the bands NF lt signal lt N 1
78. orrelated double sampler CDS alow noise wideband variable gain amplifier 0 to 31 5 dB linear in dB anda 10 bit 18 M SPS A D converter 0 5 LSB DNL no missing codes guaranteed Also included are an on chip voltage reference and the required clamping circuitry for simple ac coupling Digital output control is 3 state T he AD 9801 operates from a single 3 V supply and typically consumes 185 mW 15 mW in power down mode It is packaged in space saving 48 pinT QFP and specified for an operating temperature range of 0 to 70 C Price is 8 50 1000s Faxcode 2118 or Circle 28 B LD Regulators 50 200 mA ADP3300 3303 use any type quality capacitor T heAD P3300 and AD P3303 areanyCAP low dropout linear regulators with wide input voltage range 3 2 to 12 V high accuracy 0 8 25 C and low dropout voltage The 50 mA AD P3300 with dropout voltage of 80 mV is housed in a tiny SOT 23 6 package and the 200 mA AD P3303 180 mV inhabits an efficient thermally enhanced SO 8 package Both devices offer a range of optional regulated output voltages 2 7 3 0 3 2 3 3 and 5 0 V Both devices are stable with a wide range of Capacitor values 20 47 uF types and ESRs anyCAP Both have low noise dropout detector current and thermal limiting and 1 uA shutdown current T he ADP3300 Operates from 40 to 85 C the AD P3303 from 20 to 85 C ambient T heir respective prices are 0 86 and 1 14 in 1000s F
79. pectively Filtering must be used carefully to eliminate signal content outside of this desired bandwidth T he analog filter preceding an ADC is usually referred to as an anti alias filter since its function is to attenuate signals beyond the N yquist bandwidth prior to the sampling action of the A D converter An equivalent filtering function follows a D A converter often referred to as asmoothing filter or reconstruction filter T his continuous time analog filter attenuates the unwanted frequency images that occur at the output of the D A converter At first glance the requirements of an anti alias filter are fairly straightforward the passband must of course accurately pass the desired input signals T he stopband must attenuate any interferer outside the passband sufficiently that its residue remnant after the filter will not hurt the system performance when aliased into the passband after sampling by the A D converter Actual design of anti alias filters can be very challenging If out of band interferers are both very strong and very near the pass frequency of the desired signal the requirements for filter stopband and narrowness of the transition band can be quite severe Severe filter requirements call for high order filters using topologies that feature aggressive filter roll off U nfortunately topologies of filters having such characteristics e g Chebychev typically place costly requirements on component match and tend to intr
80. rent 5 673 047 to Carl Moreland for Gain compensating differential reference circuit 5 675 276 to Rakesh G oel for Gate driver circuit and hysteresis circuit therefor 5 675 334 to Damien McCartney for Analog to digital conversion system 5 677 558 to Gerard M cGlinchey for Low dropout linear regulator 5 679 436 to Yang Zhao for Micromechanical structure with textured surface and method for making same 5 680 300 to T homas Szepesi and M artin Mallinson for Regulated charge pump dc dc converter All brand or product names mentioned are trademarks or registered trademarks of their respective holders For immediate data visit our WorldWideWkb site http wwwanalog com Analog Dialogue 31 3 1997 23 H4 L6 ZT TEGV OTOTSE6 STIO awey sopny GGG 69 ENZTO Squ uoduuo2 2luo 2 3 uuniu WAFS 0008S8 SZST0 4e Od sn 3 eqv 99ST1S SSSTO p 1luu S3Iuo n29 3 XIUBOUd 88808r ZIVTO SS 22V J UAY LZOOLZ YEZTO S3luol 2 3 UAW f mouy uiopbupi payun 06 LO T9r 9LZ 2 U0 999 F OH 15313 AOUNL 8981869 Z0 AOD 2140172917 AeM u ploD OLSE ZZL ZO PI7 09 sudi lu3 UOIYaIYD OIL60 9Z ZO P77 0D Abojouyse A puy ueMIeL OOTOL vZ0 Z9 Z9 t 8 IO Hquid euoneuJ lul UOANGLASIG DINOYLDITI 71490dS TITS LEV 9GO x eq 3 3S OGGZEN8 TZ0 08 Z9 pL8 T0 YOLOINGNODIWIS ODSVS puepeAims 00 SZ Stt 8 8V 2luo n2 3 3 puejayeH qoye f S8908 8 JV YALNINOd
81. rogress as the days go by in 1998 As always your feedback is not only welcome it s an essential part of the site s design O Dan Sheingold analog com IN THE LAST ISSUE Volume 31 Number 2 1997 24 Pages For a copy circle 33 Editor s N otes Authors Li lon battery charging requires accurate voltage sensing Pin compatible 14 bit monolithic A D Cs F irst to sample from 1 10 M SPS AD 924x 200 M Hz 16 x 16 video crosspoint switch IC AD 8116 S decting mixed signal components for digital communications systems IV Quad SHARC DSP in CQFP a 480 M FLOPS powerhouse AD 14060 Digital signal processing 101 an introductory course in DSP system design I N ew P roduct Briefs ADCsand DACs R DAC Audio Playback Amplifiers M ux Reference DC DC Power M anagement Supervisory Circuits Temp Sensor Codec Communications and ATE ICs AskT he Applications Engineer 25 O p amps driving capacitive loads Worth Reading M ore authors Potpourri 2 ISSN 0161 3626 Analog Devices Inc 1997 THE AUTHORS Curt Ventola page 3 is a Marketing M anager in ADI s Advanced Linear Products group responsible for wired communications line drivers variable gain amplifiers and video encoders H e holds a BS in M aterial Engineering from Rutgers U niv ersity and an M BA from Babson College In his spare time he enjoys racquetball ice hockey and coaching his sons various sports teams Finbarr Moynihan page 6 is a Sys
82. s short for dielectric isolation On the DI process an insulating layer trench is placed between the NMOS and PM OS transistors of each CM OS switch Parasitic junctions which occur between the transistors in standard switches are eliminated resulting in a completely latchup proof switch In 20 O junction isolation no trench used the N and P wells of the PMOSand NM OS transistors form a diode which is reverse biased in normal operation H owever during overvoltage or power off conditions when the analog input exceeds the power supplies the diode is forward biased forming a silicon controlled rectifier SC R like circuit with the two transistors causing the current to be amplified significantly leading eventually to latch up T his diode doesn t exist in dielectrically isolated switches making the part latchup proof DIELECTRIC ISOLATION Ve Ve T R E N C H a miia Lia Lia Lia Lia ln Lia Lia Lia Lia ika in iia iia le Lia Lia Lla Lla Lia Lia Atenan B BUI RIED OXIDE LAYER SEE eee a tae Figure 3 Dielectric Isolation How do the fault protected multiplexers and channa protectors work A channel of a fault protected multiplexer or channel protector consists of two NM OS and two PM OS transistors One of the PM OS transistors does not lie in the direct signal path but is used to connect the source of the second PM OS to its backgate T his has the effect of lowering the threshold voltage which increase
83. s the input signal range for normal operation T he source and backgate of the NM OS devices are connected for the same reason D uring normal operation the fault protected parts operate as a standard multiplexer W hen a fault condition occurs on the input to a channel this means that the input has exceeded some threshold voltage which is set by the supply rail voltages T he threshold voltages are related to the supply rails as follows for a positive overvoltage the threshold voltage is given by Vpp Vry where V isthe threshold voltage of the N M OS transistor typically 1 5 V For a negative overvoltage the threshold voltage is given by Vss Vtp where Vrp Is the threshold voltage of the PM OS device typically 2 V When the input voltage exceeds these threshold voltages with no load on the channel the output of the channel is clamped at the threshold voltage How do the parts operate when an overvoltage exists T henext two figures show the operating conditions of the signal path transistors during overvoltage conditions T his one demonstrates how the series N P and N transistors operate when a positive overvoltage is applied to the channel T he first N M OS transistor goes into saturation mode as the voltage on its drain exceeds Vpp Vry T he potential at the source of the NMOS device is equal to Vpp Vry The other MOS devices are in anon saturated mode of operation Vpp VTN 13 NMOS PMOS NMOS E ON
84. serial interface on chip PGA T heAD 7731 is a complete 24 bit low noise 55 nV rms typical high throughput A D converter for industrial measurement and process control applications It incorporates a 7 step binary programmable gain amplifier allowing input signal ranges from 20 mV to 1 28 V Throughput is programmable from 50 Hz up to 6400 Hz T he sigma delta architecture uses an analog modulator and a low pass programmable digital filter allowing adjustment of filter cutoff output rate and settling time Its 3 wire serial output is compatible with microcontrollers amp digital signal processors It operates from a single 5 V power supply and can accept external references ranging from 1V up to and including the 5 V positive rail It is available for 40 to 85 C packaged in 24 lead PDIP SO andT SSOP 1000 lot price is 9 86 Faxcode 2131 or Circle 17 B 4 amp 8 Channel ADCs 10 bit serial AD7811 AD7812 350 ksps thruput 2 5 5 5 Vs The AD7811 and AD 7812 are 10 bit sampling A D converters with serial digital Interfaces and multiplexed 4 and 8 channel analoginputs T hey operate from 2 7 to 5 5 V supplies and havea maximum throughput of 350 ksps T hey accept analog inputs over the range of 0 V to Vpp and users can employ the on chip references external precision references or the supply voltage T heir low power consumption 315 uW at 10 ksps ability to power down after conversions and small package size
85. slation and the factors contributing to dynamic range requirements T his final installment considers issues relating to the interface between continuous time and Sampled data and discusses sources of spurious signals particularly in the transmit path D igital communications systems must usually meet specifications and constraints in both the time domain e g settling time and the frequency domain e g signal to noise ratio AS an added complication designers of systems that operate across the boundary of continuous time and discrete time sampled signals must contend with aliasing and imaging problems Virtually all digital communications systems fall into this class and sampled data constraints can have a significant impact on system performance In most digital communications systems the continuous time to discrete time interface occurs in the digital to analog DAC and analog to digital AD C conversion process which is the interface between the digital and analog domains T he nature of this interface requires clear understanding since the level sensitive artifacts associated with conversion between digital and analog domains e g quantization are often confused with the time sensitive problems of conversion between discrete time and continuous time e g aliasing T he two phenomena are different and the subtle distinctions can be important in designing and debugging systems N ote all digital signals must inherently b
86. surfing applications since typical http navigation calls for much more data to be sent down to the computer than up to the network T he upstream transmit path required when using cable modems is the major new requirement that has been placed on the CAT V plant T he bandwidth that has been allocated for the return path function by the cable industries is 5 42 MHz in the USA and 5 65 M Hz in Europe T his particular bandwidth is expected to contain substantial amounts of impulse noise or ingress which will make reverse path communication difficult Initially a relatively simple modulation format quadrature phase shift keying QPSK Is being utilized by most cable modem vendors In the future as the cable plant environment is further upgraded and improved there will be a movement to a 16 QAM upstream modulation format to Increase the bits H z efficiency of the upstream data transmission Some of the technologically and market driven requirements for the upstream transmitter T x section of a cable modem are Output frequency agility with digital control Full digital control of modulation and output power parameters High spurious free dynamic range SFDR on the modulated output carrier Integrated digital signal processing with a high level of functionality Low cost Low power Analog D evices isin aunique position to supply an optimum silicon solution for the upstream T x requirement it falls squarely
87. t the strong interferer problem The D A requires an interpolation filter A digital interpolation filter increases the effective data rate of the D A by generating intermediate digital samples of the desired signal as shown in Figure 3 a T he frequency domain results are shown in d e in this case 2x interpolation has suppressed the DAC output s first two images increasing the available transition bandwidth for the reconstruction filter from F clock 2F outmax tO 2F dock ZF outmax his allows simplification of the filter and may allow more conservative pole placement to reduce the passband phase distortion problems that are the frequent side effects of analog filters Digital interpolation filters may be implemented with programmable DSP with ASICs even by integration with the D A converter e g AD 9761 AD 9774 Just as with analog filters critical performance considerations for the interpolation filters are passband flatness stop band rejection how much are the images suppressed and narrowness of the transition band how much of the theoretical N yquist bandwidth F dox 2 Is allowed in the passband DACs can be used in undersampling applications but with less efficacy than are A D Cs Instead of using a low pass reconstruction filter to reect unwanted images a bandpass reconstruction filter can be used to select one of the images instead of the fundamental This is analogous to the ADC undersampling but with a few co
88. te impulse response FIR filter algorithm briefly introduced in Part 2 Implemented in ADSP 2100 Family assembly code on a hardware platform the ADSP 2181 EZ Kit Lite The implementation is expanded to handle data I O issues USING DIGITAL FILTERS M any of the architectural features of the D SP such as the ability to perform zero overhead loops and to fetch two data values in a single processor cycle will be useful in implementing this filter Reviewing briefly an FIR filter is an all zeros filter that is calculated by convolving an input data point series with filter coefficients Its governing equation and direct form representation are shown in Figure 1 x n x n 1 x n N 2 x n N 1 XK h N 1 INPUT N 1 output y n gt h m x n m m 0 Figure 1 Direct form FIR filter structure gin In this structure each box represents a single increment of history of the input ic in z transform notation Each of the successively delayed samples is multiplied by the appropriate coefficient value h m and the results added together generate a single value representing the output corresponding to thenth input sample The number of delay elements or filter taps and their coefficient values determine the filter s performance T he filter structure suggests the physical elements needed to implement this algorithm by computation using a DSP For the computation itself each output sample requires a number of
89. ted control algorithms T he key to the real time implementation of sophisticated control algorithms for these motion control systems has been the advent of powerful digital signal processors DSPs Even in less demanding but cost sensitive applications such as domestic refrigerator compressor drives the power of the DSP can be harnessed to implement sensorless control algorithms that reduce the system cost and increase the overall robustness of the drive In high performance servo drives the powerful computational ability of the DSP permits more precise control through vector control ripple torque reduction predictive control structures and compensation for non ideal system behavior Besides the powerful D SP core all motor control systems require a significant array of additional circuits for correct operation including such functions as Analog to digital conversion for current or voltage feedback e Pulsewidth modulation PWM blocks for generation of the inverter switching commands e Position sensor interfaces for higher performance applications Serial ports for host communications e General purpose digital input output ports 20MIPS FIXED POINT DSP CORE DATA ADDRESS GENERATORS ARITHMETIC UNITS 2K PROGRAM MEMORY ROM 1K DATA MEMORY RAM Analog D evices now offers a range of single chip D SP based motor control solutions that integrate these peripheral functions with a high performance D SP coreand t
90. tems Engineer with the M otion Control group designing motor control algorithms and specifying new single chip solutions for motor control He holds BE M Eng Sc in EE and Ph D degrees from U niversity C ollege Cork Ireland H is doctoral thesis was on applying DSP to motor control He has authored papers and presented seminars on motion control theory and practice and lectured in motion control at U niversity C ollege Cork and the U niversity of Padova Italy Paul Kettle page 6 is a Senior Systems Engineer in the M otion Control group His responsibilities include product definition and design in opportunities in the Pacific rim countries and software tool development strategy for the motion control group He holds a Ph D in Stochastic Control and a B Eng in electronic engineering from D ublin City U niversity H e has published widely on motion control topics Paul s main passion in life is sailing and the sea in general Tom Howe page 6 is a Software Systems Engineer in the M otion Control group He develops kernels libraries and software tools for motor control DSPs Tom has a BSEE from the U niversity of New Hampshire and an MS in Computer Engineering from U M ass Lowell In his spare time Tom is renovating his house he also enjoys reading biking and travel M ore authors on page 23 Cover The cover illustration was designed and executed by Shelley Miles of Design Encounters Hingha
91. ter values to grow and shrink as necessary without corrupting data T he code segment being used is generic i e can be used for any length filters so the M AC s extra output bits allow arbitrary filters with unknown data to be run with little fear of losing data To implement the FIR filter the multiply accumulate operation is repeated for all taps of the filter on each data point To do this and be ready for the next data point the MAC instruction is written in the form of a loop The ADSP 21xx s zero overhead loop capability allows the M AC instruction to be repeated for a specified number of counts without programming intervention A counter is set to the number of taps minus one and the loop mechanism automatically decrements the counter for each loop Operation Setting the loop counter to taps 1 ensures that the data pointers end up in the correct location after execution is finished and allows the final M AC operation to include rounding AstheAD 1847 isa 16 bit codec the M AC with rounding provides a statistically unbiased result rounded to the nearest 16 bit value T his final result is written to the codec F or optimal code execution every instruction cycle should perform a meaningful mathematical calculation The ADSP 21xxs accomplish this with multi function instructions the processor can perform several functions in the same instruction cycle For the FIR filter code each multiply accumulate M AC operation 1
92. the final production implementation WORKING WITH THE ADSP 2181 EZ KIT LITE Our example of the development cycle walks through the process using the AD SP 2181 EZ K it Lite development package A D DS 21xx EZLIT E as the target hardware for the filter algorithm T he EZ K it Lite alow cost demonstration and development platform consists of a 33 M Hz AD SP 2181 processor an AD 1847 stereo audio codec and a socketed EPROM which contains monitor code for downloading new algorithms to the D SP through an RS 232 connection Figure 3 RS 232 9VDC I Dye ADSP 2181 EZ PORT AD1847 CODEC LINE MIC JUNPER o OFL1 Figure 3 Layout of EZ Kit Lite board To completethe architecture description phase one needsto know the memory and memory mapped peripherals that the DSP has available to it Programmers store this information in a system description file so that the development tools software can produce appropriate code for the target system T he EZ K it Lite needs no memory external to the DSP because available memory on chip consists of the 16 384 locations of the ADSP 2181 s Program Memory PM SRAM and 16 352 locations of Data M emory DM SRAM 32 DM locations used for system control registers are not available for working code M ore information on the ADSP 2181 the EZ Kit Lite s architecture and related topics can be found in texts mentioned at the end of this article Available system resources
93. unleash the true power of the nternet s imaging potential CABLE PLANT HEAD END EQUIPMENT HFC BI DIRECTIONAL MEDIA ACCESS TELEVISION TELEPHONY INTERNET ACCESS FIBER TRUNK CIU NEIGHBORHOOD 60 850MHz NODE MONITOR CONTROL POTS PLAIN OLD TELEPHONE SER CIU CONSUMER INTERFACE UNIT Figure 1 Block diagram of HFC CATV plant T he cable industry would prefer that cable modems for Internet surfing become off the shelf items purchased and maintained by the consumer very much like telephone modems To this end cable modems would need to be interoperable which means that a given cable modem will work in different cable systems with different vendors head end equipment To achieve interoperability of cable modems universal standards are required and indeed they are emerging T he M ultimedia Cable Network Systems M CNS group has issued their D ata over cable services interface Specifications for interactive communications via the HFC network The M CNS standards have been endorsed by many of the larger cable M SOs as their working standard T he lEEE 802 14 committee is also developing a set of standards for HFC cable networks and the DAVIC and DVB standards have been released and are being deployed in Europe For cable telephony however proprietary algorithms are employed for upstream downstream transmissions and interoperability is not a concern T he basic cable modem consists of an RF rec
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95. use F axback to request 2169 2203 see page 24 or use the reply card circle 1 ect wae ENABLE GAIN AND AD8320 SERIAL R S DATA BS RC DATA IN 9 FEC DELAY ENCODER Fea zuu FSK 10 INVERSE 10 5 Pr QPSK DAs DQPSK Q T TO LP 16 QAM P FILTER RANDOMIZER PREAMBLE SRRC pee D S gt INSERTION FILTER CONTROL OF CABLE DRIVER AMP DRIVE SINE ANPLIFIER NTROL FUNCTION X6 PLL CO OL FUNCTIONS REF FEC MASTER CLOCK IN ENABLE ENABLE RESET 20 48 MHz DISABLE FEC FORWARD ERROR CORRECTION SRRC SQUARE ROOT RAISED COSINE FSK FREQUENCY SHIFT KEYING QPSK QUADRATURE PHASE SHIFT KEYING DQPSK DIFFERENTIAL QUADRATURE PHASE SHIFT KEYING ooo S N BIDIRECTIONAL 3 WIRE SERIAL CONTROL BUS 32 BIT OUTPUT FREQUENCY TUNING WORD INPUT DATA RATE MODULATION FORMAT FEC RANDOMIZER PREAMBLE ENABLE CONFIGURATION FIR FILTER COEFFICENTS REF CLOCK PLL ENABLE 1 Q PHASE INVERT SLEEP MODE Figure 2 AD9853 digital modulator block diagram Analog Dialogue 31 3 1997 implementing an external 122 M Hz reference clock 160 M Hz clock for 65 M Hz carrier applications The SFDR specification is achieved with the low jitter clock multiplier circuitry enabled Additional programmable functions that support the requirements of HFC 2 way communication applications include forward error correction data scrambling and preamble word insertion T hese are functions specified for successful burst packet data transmission in interoperab
96. ut i e Vciamp R NONSATURATED OPERATION lout Figure 6 Determining the clamping point EFFECTIVE OVERVOLTAGE SPACE CHARGE R OPERATION SATURATED Va Vr 13 5V DETERMINING THE CLAMP VOLATGE Q Dothefault protected multiplexers and channel protectors function when the power supply is absent A Yes T hese devices remain functional when the supply rails are down or momentarily disconnected When Vpp and Vss equal 0 V all the transistors are off as shown and the current is limited to sub nanoampere levels OV POWER SUPPLIES ABSENT POSITIVE OR NMOS NMOS NEGATIVE OVERVOLTAGE j a O a T Vpp OV Vss 0V Vpp OV Figure 7 Power Supplies Absent Q What is charge injection A Charge injection in analog switches and multiplexers is a level change caused by stray capacitance associated with the N M OS and PM OS transistors that make up the analog switch T he F igure below models the structure of an analog switch and the Analog Dialogue 31 3 1997 stray capacitance associated with such an implementation T he structure basically consists of an NM OS and PM OS device in parallel This arrangement produces the familiar bathtub resistance profile for bipolar input signals T he equivalent circuit shows the main parasitic capacitances that contribute to the charge injection effect Cepu N M OS gate to drain and Cepp PM OS gate to drain T he
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