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CUDA C Programming Guide

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1. eeesesessseeeeseeeeeeee e eene enne hehehe eene 108 B 8 2 14 tex2DLayered 225r sede Ite as bonnes nube ravra ra Pra ess e o riva or Ve Elie ve 108 B 8 2 15 tex2DLayeredLod eeeeeseeeeeeeeeeee eee enhn hhhe nhe eher ern 108 B 8 2 16 tex2DLayeredGrad csesseeeesseeeeseeeeeee eene nenne eher 109 B 8 2 17 texCubemiap 5 cisco tret eter pe ee repere rrt re neo p e certes eere evuk edes 109 B 8 2 18 texCubemapLod cceeeeeeeeeeeeeeeee eene ehh ehe nnne rnnt 109 B 8 2 19 texCubemapLayered scecccscccsncseneesnsessccsncscasesneesesessceccesaaeeanenees 109 B 8 2 20 texCubemapLayeredLod ceesseeseeesseeseeeseen ene hene enne 109 B 8 2 21 tex2D eatlier iiiii iio ex eaae Ra T NOx RARSIRA T DEN EAT EO AUS 110 B 9 Surface FUICEIONS eresi oesse iiec e rwreu ers or revue t eR Ue Cbr VERUU E RU T Ke S 110 B 9 1 Surface Object AP lic ss eoi entero enr na dese ene E eara than elas a ERE Np AEE e RES 110 B 9 1 1 surf1Dread corio Perte tenn Een E Yee ea oet Enn E eR e Ere FI TRU S VES EREE ES EE RU HE 110 B 9 1 2 surf 1DWEIt6 oor roti eei ter Pere EpUeD rep i a valde vetue RU bile DU MB URINE 110 B 9 1 3 surf2Dread eii ite re nera OE eR Ea RRExE C IRERESLUI seem CE DU ERES Xo Ee REDE SE E 111 B 9 1 4 surf2DWrite eed eee en eeue eee Re E reae Yn sade ee EINE PO ER ENTRE Ute dead E TERRA 111 B 9 1 5 surf3Dread i isis ere ert ve ap RECEN OE
2. Host code int launchMyKernel int array int arrayCount int blockSize The launch configurator returned block size int minGridSize The minimum grid size needed to achieve the maximum occupancy for a full device launch ae peatoledto ep The actual grid size needed based on input size cudaOccupancyMaxPotentialBlockSize amp minGridSize amp blockSize void MyKernel 0 arrayCount Round up according to array size gridSize arrayCount blockSize 1 blockSize MyKernel lt lt lt gridSize blockSize gt gt gt array arrayCount cudaDeviceSynchronize If interested the occupancy can be calculated with cudaOccupancyMaxActiveBlocksPerMultiprocessor return 0 The CUDA Toolkit also provides a self documenting standalone occupancy calculator and launch configurator implementation in lt CUDA_Toolkit_Path gt include cuda occupancy h for any use cases that cannot depend on the CUDA software stack A spreadsheet version of the occupancy calculator is also provided The spreadsheet version is particularly useful as a learning tool that visualizes the impact of changes to the parameters that affect occupancy block size registers per thread and shared memory per thread 5 3 Maximize Memory Throughput The first step in maximizing overall memory throughput for the application is to minimize data transfers with low bandwidth That means minimizing data transfe
3. Invoke kernel int threadsPerBlock 256 int blocksPerGrid N threadsPerBlock 1 threadsPerBlock eeclesie measstcsBleok om OSEE C ENDE Copy result from device memory to host memory h contains the result in host memory cudaMemcpy h C d C size cudaMemcpyDeviceToHost Free device memory cudaFree d A cudaFree d B cudaFree d C Free host memory Linear memory can also be allocated through cudaMallocPitch and cudaMalloc3D These functions are recommended for allocations of 2D or 3D arrays as it makes sure that the allocation is appropriately padded to meet the alignment requirements described in Device Memory Accesses therefore ensuring best performance when accessing the row addresses or performing copies between 2D arrays and other regions of device memory using the cudaMemcpy2D and cudaMemcpy3D functions The returned pitch or stride must be used to access array elements The www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 22 Programming Interface following code sample allocates a width x height 2D array of floating point values and shows how to loop over the array elements in device code I hose CE int width 64 float devPtr gize 1E piten cudaMallocPitch amp devPtr amp pitch width sizeof float 512 devPtr pitch height 64 height MyKernel lt lt lt 100 width height Device code Rg lobe ond eMy Ke race logt
4. Allocation using runtime API cudaMalloc amp d data size devPtr CUdeviceptr d data In particular this means that applications written using the driver API can invoke libraries written using the runtime API such as cuFFT cuBLAS All functions from the device and version management sections of the reference manual can be used interchangeably www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 228 Appendix I CUDA ENVIRONMENT VARIABLES Environment variables related to the Multi Process Service are documented in the Multi Process Service section of the GPU Deployment and Management guide Table 15 CUDA Environment Variables ET Device CUDA VISIBLE DEVICES A comma GPU identifiers are given as integer Enumeration separated indices or as UUID strings GPU and Properties sequence of UUID strings should follow the same GPU identifiers format as given by nvidia smi such as GPU 8932f937 d72c 4106 c12f 20bd9faed9f6 However for convenience abbreviated forms are allowed simply specify enough digits from the beginning of the GPU UUID to uniquely identify that GPU in the target system For example CUDA VISIBLE DEVICES GPU 8932f937 may be a valid way to refer to the above GPU UUID assuming no other GPU in the system shares this prefix Only the devices whose index is present in the sequence are visible to CUDA applications and they are enumerated in the order of the sequence If one of
5. Syncthreads or Synchronization Functions Surface functions Surface Functions Funnel shift see reference manual Dynamic Parallelism Half precision floating point operations addition subtraction multiplication comparison warp shuffle functions conversion Table 13 Technical Specifications per Compute Capability Compute Capability at mee spectiatins 2x 30 32 38 37 2 52 55 Maximum number of resident grids per 4 32 device Concurrent Kernel Execution 3 Maximum dimensionality of grid of thread blocks Maximum x dimension of a grid of 31 Maximum y or z dimension of a grid of thread blocks 65535 Maximum dimensionality of thread 3 block Maximum x or y dimension of a block 1024 Maximum number of threads per block www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 205 Compute Capabilities Compute Capability mmm Pamaen ao ea es sr so sa ss Warp size Warp size Maximum number of resident blocks per multiprocessor Maximum number of resident warps per multiprocessor Maximum number of resident threads per multiprocessor Number of 32 bit registers per 128 K multiprocessor 1536 2048 Maximum number of 32 bit registers per thread block Hem oak Maximum number of 32 bit registers per thread Maximum amount of shared memory 112 Maximum amount of shared memory 48 KB per thread block Number of shared memory banks Amount of local memory
6. ccccce esse sce eee eect ence eee eee hee eene nnn 229 www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 xiii www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 xiv Chapter 1 INTRODUCTION 1 1 From Graphics Processing to General Purpose Parallel Computing Driven by the insatiable market demand for realtime high definition 3D graphics the programmable Graphic Processor Unit or GPU has evolved into a highly parallel multithreaded manycore processor with tremendous computational horsepower and very high memory bandwidth as illustrated by Figure 1 and Figure 2 www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 1 Theoretical GFLOP s 5750 5500 5250 5000 4750 4500 4250 4000 3750 3500 3250 3000 2750 2500 2250 2000 1750 1500 1250 1000 750 500 GeForce 6800 Ultra 250 GeForce FX 5800 Pentium 4 Apr 01 Sep 02 Introduction GeForce 780 Ti NVIDIA GPU Single Precision mtm NVIDIA GPU Double Precision Intel CPU Double Precision mtm ntel CPU Single Precision GeForce GTX TITAN GeForce GTX 680 GeForce GTX 580 Festa K40 GeForce GTX 480 Tesla K20X GeForce GTX 280 Tesla M2090 GeForce 8800 GTX Tesla C2050 Tesla C1060 Harpertown GeForce 7800 GTX Ivy Bridge oodcrest Bloomfield Westmere Jan 04 May 05 Oct 06 Feb 08 Jul 09 Nov 10 Apr 12 Aug 13 Dec 14 Figure 1 Floating Point Operations per Second for the CPU and GP
7. cewaee recria Wp IP Glass CO i void foo void Error enclosing function has private access in parent class auto tremol Cewies sexa XU Pg struci S21 q void foo void Error enclosing class S2 t has private access in its mM parene class awto temol _ Cevice q1 retura ie fp i i 2 A device lambda cannot be defined in a class that is local to a function www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 192 C C Language Support Example void foo void Stumee Sli oq void bar void M Error par iS member of al elass that is locall toma PUNCE ON automan eee d secum We fe 3 Ifthe enclosing function is an instantiation of a function template or a member function template and or the function is a member of a class template the template s must satisfy the following constraints gt The template must have at most one variadic parameter and it must be listed last in the template parameter list gt The template parameters must be named gt The template instantiation argument types cannot involve types that are either local to a function except for closure types for device lambdas or are private or protected class members www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 193 C C Language Support Example template lt typename T gt __ ileiseil vorc kerm aba C she p fj template lt typename T gt She
8. Calculate normalized texture coordinates unsigned int x blockIdx x blockDim x threadIdx x unsigned int y blockIdx y blockDim y threadIdx y float u x float width float v y float height Transform coordinates ip OADE Ww O SEA clope EM WU COSE tiere wv Sim laste s Wa Size los ier Scott NEUSS tec NEUSS OW Size Read from texture and write to global memory output y width x tex2D texRef tu tv Host code int main Allocate CUDA array in device memory cudaChannelFormatDesc channelDesc cudaCreateChannelDesc 32 0 0 O0 cudaChannelFormatKindFloat cudaArray cuArray cudaMallocArray amp cuArray amp channelDesc width height Copy to device memory some data located at address h data in host memory cudaMemcpyToArray cuArray 0 0 h data size cudaMemcpyHostToDevice Set texture reference parameters texRef addressMode 0 cudaAddressModeWrap texRef addressMode 1 cudaAddressModeWrap texRef filterMod cudaFilterModeLinear texRef normalized true Bind the array to the texture referenc cudaBindTextureToArray texRef cuArray channelDesc Allocate result of transformation in device memory float output cudaMalloc amp output width height sizeof float Invoke kernel cimo GdimBleck le ic dim3 dimGrid width dimBlock x 1 dimBlock x height dimBlock y 1 dimBlock y tran
9. H null pointer comparisons Eenplaker lt cillasiscmen eilasc yo acy pes device host bool operator const f unctron lt R Arglypes gt amp nuliliper it moexcepe Eenp lakes lt elassme eass Mc pes device host bool operator nullptr t const function lt R ArgTypes gt amp noexcept template lt class MR class ERBOQIbypes device host bool operator const function R ArgTypes gt amp nullptr t noexcept BempsatemolascM Chasis M cc pes device host I5eolMo perator milit ters MEC o mete DOO SETZEN D CSI METTO OC O Dp le specialized algorithms icemplliaie egestas JR GUESSo MUS IIS SE device host void swap function R ArgTypes gt amp function R ArgTypes gt amp const noexcept E 4 Experimental Feature Device Lambdas The nvcc flag expt extended lambda allows explicit execution space annotations in a lambda expression The execution space annotations should be present after the lambda introducer and before the optional lambda declarator www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 190 C C Language Support Example void foo void a device lambda auic Jew D CGevices wera 105 fe Lt a CS Sit device lambda auto lam2 host device meretucne2078 iP fy m hose lamos euic lens D _ host wem Sp Jp If the execution space annotations are not explicit
10. sscssssscsessssecesensacsunsedasessece nade eeinsiecebedeee essences 183 E2014 C 11 Features ee oorr lias a ee eorr era e eR pag dees e REF e ageae see rh aud 183 E 2 14 1 Lambda Expressions oee rente e ur eher eR ENCIS KAERRA r KARE e pner 184 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 ix E 2 14 2 std nitiallzer ls ioter teer Sad dance sietere vas ods sim Sardiess etn er ORTOS DEDERE os 185 E 2 14 3 Rvallie references recited eret t ences ERR Rae PNE TEEST Er eR TREE EET 185 E 2 14 4 Constexpr functions and function templates ccceeeeeeeee eee eeeeeeeeeees 185 E 2 14 5 Constexpr variables dir eet rtr quake toten nk ia ee nie RR RE A ien 186 E 2 14 6 Inline NAMESPACES coe s ecer ee oe nen rte ox ror SIRE ET REV E ESTEN SEPA Eat 186 WAP E NrENE GTC CUM oe tt 188 E 2 14 8 global functions and function templates leeeeeeeeeeeeees 188 E 2 14 9 device constant shared variables eeueeeeeess 189 E 3 Polymorphic Function WrappelS ceecee eee e eee eee eee eee een eee hee hehe ee enne 189 E 4 Experimental Feature Device Lambdas ceeeeseeeseeeeeee eene eene 190 E5416 cugledo C 191 E 4 2 Additional Notes eee eene eeu ex eon erae x ae ERE EN UE den kei ee yes even raa vs 196 E 5y Code Samples 554 Suede deese sene tie serre etiani siet es uota dines Deut e san etse He EEN D
11. works properly result 0 totalSum count 0 B 6 Synchronization Functions void syncthreads www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 99 C Language Extensions waits until all threads in the thread block have reached this point and all global and shared memory accesses made by these threads prior to syncthreads are visible to all threads in the block __syncthreads is used to coordinate communication between the threads of the same block When some threads within a block access the same addresses in shared or global memory there are potential read after write write after read or write after write hazards for some of these memory accesses These data hazards can be avoided by synchronizing threads in between these accesses __syncthreads is allowed in conditional code but only if the conditional evaluates identically across the entire thread block otherwise the code execution is likely to hang or produce unintended side effects Devices of compute capability 2 x and higher support three variations of syncthreads described below int syncthreads count int predicate is identicalto syncthreads with the additional feature that it evaluates predicate for all threads of the block and returns the number of threads for which predicate evaluates to non zero int syncthreads and int predicate is identical to__ syncthreads with the additional feature that it evaluate
12. www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 102 C Language Extensions fetches from the CUDA array specified by the one dimensional layered texture at layer layer using texture coordinate x and level of detail level B 8 1 13 tex1DLayeredGrad template class T T texlDLayeredGrad cudaTextureObject t texObj float x int layer clog eb 3tlhewue Chy 5 fetches from the CUDA array specified by the one dimensional layered texture at layer layer using texture coordinate x and a level of detail derived from the dx and dy gradients B 8 1 14 tex2DLayered template class T T tex2DLayered cudaTextureObject t texObj ieee xp closce yp tne dieses n fetches from the CUDA array specified by the two dimensional texture object texObj using texture coordinate x y and index layer as described in Layered Textures B 8 1 15 tex2DLayeredLod template class T T tex2DLayeredLod cudaTextureObject t texObj float x float y int layer float level fetches from the CUDA array specified by the two dimensional layered texture at layer layer using texture coordinate x y B 8 1 16 tex2DLayeredGrad template class T T tex2DLayeredGrad cudaTextureObject t texObj float x float y int layer rloa Che loar Ol p fetches from the CUDA array specified by the two dimensional layered texture at layer layer using texture coordinate x y and a level of detail derived from the dx and dy X and Y
13. Map vertex buffer for writing from CUDA float4 positions cudaGraphicsMapResources 1 amp positionsVB CUDA 0 size t num bytes cudaGraphicsResourceGetMappedPointer void amp positions amp num bytes positionsVB CUDA Execute kernel cimosasumbiltosis o ly SN dim3 dimGrid width dimBlock x height dimBlock y 1 createVertices lt lt lt dimGrid dimBlock positions time width height Unmap vertex buffer cudaGraphicsUnmapResources 1 amp positionsVB CUDA 0 Draw and present void releaseVB cudaGraphicsUnregisterResource positionsVB CUDA positionsVB gt Release _ global void createVertices float4 positions float time unsigned int width unsigned int height unsigned int x blockIdx x blockDim x threadIdx x unsigned int y blockIdx y blockDim y threadIdx y Calculate uv coordinates Pl Oate pr E xe 4 srlboxue vyske eine float v y float height wi ew 240 i Ore WS ws gum LOE Calculate simple sine wave pattern float freq 4 0f float w sinf u freq time GOSIE wr saec ap Cime OW Sip Write positions positions y width x make float4 u w v _int_as float Oxff00ff00 3 2 12 3 SLI Interoperability In a system with multiple GPUs all CUDA enabled GPUs are accessible via the CUDA driver and runtime as separate devices There are however special considerations as described belo
14. template lt class T void surfCubemapLayeredwrite T data cudaSurfaceObject t surfObj aues Sep dabei Wp amie layer Race boundaryMode cudaBoundaryModeTrap writes value data to the CUDA array specified by the cubemap layered object surfObj at coordinate x and y and index layerFace www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 113 C Language Extensions B 9 2 Surface Reference API B 9 2 1 surf1Dread template lt class Type gt Type surflDread surface void cudaSurfaceTypelD surfRef Ine X boundaryMode cudaBoundaryModeTrap template lt class Type gt void surflDread Type data surface lt void cudaSurfaceTypelD gt surfRef int x boundaryMode cudaBoundaryModeTrap reads the CUDA array bound to the one dimensional surface reference surfRef using coordinate x B 9 2 2 surf1Dwrite template lt class Type gt void surflDwrite Type data surface lt void cudaSurfaceTypelD gt surfRef IME Sep boundaryMode cudaBoundaryModeTrap writes value data to the CUDA array bound to the one dimensional surface reference surfRef at coordinate x B 9 2 3 surf2Dread template lt class Type gt Type surf2Dread surface lt void cudaSurfaceType2D gt surfRef Ewe SXp ALE Wp boundaryMode cudaBoundaryModeTrap template lt class Type gt void surf2Dread Type data surface lt void cudaSurfaceType2D gt surfRef Iwe xp Lae Wp boundaryMode cudaBoundaryModeTrap r
15. www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 23 Programming Interface The following code sample illustrates various ways of accessing global variables via the runtime API __constant__ float constData 256 float data 256 cudaMemcpyToSymbol constData data sizeof data cudaMemcpyFromSymbol data constData sizeof data cevices Elon Ende Dateay float value 3 14f cudaMemcpyToSymbol devData amp value sizeof float ceviee iileciey clewPoumiuecies PLOae ee pie exeleitedLloxe iepen OG w Sure nE oat cudaMemcpyToSymbol devPointer amp ptr sizeof ptr cudaGetSymbolAddress is used to retrieve the address pointing to the memory allocated for a variable declared in global memory space The size of the allocated memory is obtained through cudaGetSymbolSize 3 2 3 Shared Memory As detailed in Variable Type Qualifiers shared memory is allocated using the Shared qualifier Shared memory is expected to be much faster than global memory as mentioned in Thread Hierarchy and detailed in Shared Memory Any opportunity to replace global memory accesses by shared memory accesses should therefore be exploited as illustrated by the following matrix multiplication example The following code sample is a straightforward implementation of matrix multiplication that does not take advantage of shared memory Each thread reads one row of A and one www nvidia com CUDA C Programming G
16. www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 198 C C Language Support E 5 5 Functor Class Glass Ace i puer ENdeviccNNEE loq operan tilloat ar MEI at MEO igSielicig Gl ap do Hu cias SES ubin pubic _ Cewice Eos operaco lect a leei o conse ignes Gl o Device code template lt class O gt global void VectorOperation const float A const float B float C unsigned int N O op unsigned int iElement blockDim x blockIdx x threadIdx x if iElement N C iElement op A iElement B iElement Host code int main VectorOperation lt lt lt blocks threads gt gt gt vl v2 v3 N Add www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 199 Appendix F TEXTURE FETCHING This appendix gives the formula used to compute the value returned by the texture functions of Texture Functions depending on the various attributes of the texture reference see Texture and Surface Memory The texture bound to the texture reference is represented as an array T of gt Ntexels for a one dimensional texture gt NxM texels for a two dimensional texture gt NxM xL texels for a three dimensional texture It is fetched using non normalized texture coordinates x y and z or the normalized texture coordinates x N y M and z L as described in Texture Memory In this appendix the coordinates are assumed to be in the valid range
17. 0 Note unused variable for value arg all threads except lane 0 value shfl value 0 Get value from lane 0 if value arg printf Thread d failed n threadIdx x int main loeum I S2 SoS Ze cudaDeviceSynchronize return 0 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 124 C Language Extensions B 14 5 2 Inclusive plus scan across sub partitions of 8 threads include lt stdio h gt glosa vowel geewa i Bae int laneId threadIdx x amp Oxl1f Seed sample starting value inverse of lane ID int value 31 laneId Loop to accumulate scan within my partition Scan requires log2 n 3 steps for 8 threads It works by an accumulated sum up the warp f low d 2p By S cua SSRS for int i l i lt 4 i 2 Note shfl requires all threads being accessed to be active Therefore we do the shfl unconditionally so that we can read even from threads which won t do a sum and then conditionally assign the result int n shfl up value i 8 aie anete gt T value n printf Thread d final value d n threadIdx x value main Sean lt lt lt 52 0 cudaDeviceSynchronize return 0 B 14 5 3 Reduction across a warp include lt stdio h gt global void warpReduce IENE int laneId threadIdx x amp Oxlf Seed starting value as inverse lane ID int value 31 laneId Use XOR mo
18. 239 Unified Memory Programming J 2 2 3 Managing Data Visibility and Concurrent CPU GPU Access Until now it was assumed that any active kernel may use any managed memory and that it was invalid to use managed memory from the CPU while a kernel is active Here we present a system for finer grained control of managed memory The CUDA programming model provides streams as a mechanism for programs to indicate dependence and independence among kernel launches Kernels launched into the same stream are guaranteed to execute consecutively while kernels launched into different streams are permitted to execute concurrently Streams describe independence between work items and hence allow potentially greater efficiency through concurrency Unified Memory builds upon the stream independence model by allowing a CUDA program to explicitly associate managed allocations with a CUDA stream In this way the programmer indicates the use of data by kernels based on whether they are launched into a specified stream or not This enables opportunities for concurrency based on program specific data access patterns A new function exists to control this cudaError t cudaStreamAttachMemAsync cudaStream t stream VOLE MDEE size ic lengta 0 unsigned int flags 0 The cudaStreamAttachMemAsync function associates Length bytes of memory starting from ptr with the specified stream Currently Length must always be 0 to indicate that the entire region sh
19. and floorf each map to a single instruction as well Table 6 Single Precision Mathematical Standard Library Functions with Maximum ULP Error The maximum error is stated as the absolute value of the difference in ulps between a correctly rounded single precision result and the result returned by the CUDA library function www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 160 Mathematical Functions x y 0 for compute capability gt 2 when compiled with prec div true 2 full range otherwise 0 for compute capability gt 2 when compiled with prec div true 1 full range otherwise rsqrtf x 2 full range 1 sqrtf x Applies to 1 sqrt x only when it is converted to rsqrtf x by the compiler sqrtf x 0 for compute capability gt 2 when compiled with prec sqrt true 3 full range otherwise Ee RN www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 161 Mathematical Functions a T NN LONE T RN eme m www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 162 Mathematical Functions JOf x 9 for x lt 8 otherwise the maximum absolute error is 2 2 x 10 j1f x 9 for x 8 otherwise the maximum absolute error is 2 2 x m For n 128 the maximum absolute error is 2 2 x 10 yOf x 9 for x 8 otherwise the maximum absolute error is 2 2 x 10 y1f x 9 for x lt 8 otherwise the maximum absolute error is 2 2 x 10 ynf x ceil 2 2
20. device void putThis PrintBuffer p const Midevice virtuel vonc br awi bnitte BOE coU MEC TIS tn p gt put Shapeless _Geyvaes virial ehe eT 1 class Point s public Shape public device Point x 0 y 0 Cewice Game slime dixo dme ay a ae why d oJ ENdeviceNN veie Eu oor Eimer MEC Ost ENdewlceN voio rawi Eri Buteteq msi device Point private SLIME 3 amp 5 WP device Shape GetPointObj MemoryPool amp pool Shape shape new pool Point rand 20 10 rand 100 20 return shape www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 197 C C Language Support E 5 3 Class Template template lt class T gt class myValues T values MAX VALUES Dulles _Cewace myyelvwes t elear I oso J _ Cewice voie getvelve ime Tekk T value I ssa device void putToMemory T valueLocation he template lt class T gt void global useValues T memoryBuffer myValues lt T gt myLocation 0 cevice vorc lomibieies int main useValues lt int gt lt lt lt blocks threads gt gt gt buffer E 5 4 Function Template template typename T ENdevicegeeboo Neun cO ene ios o E template lt gt L device bool func int T x Specialization return true Explicit argument specification bool result func lt double gt 0 5 Implicit argument deduction ooie S JLP bool result func x
21. halz Sic ese vary im Sweclhyeueev aie wahehE sk wells AS P half shfl_up half var unsigned int delta int width warpSize half shfl down half var unsigned int delta int width warpSize half shfl xor half var int laneMask int width warpSize B 14 2 Description The shf1 intrinsics permit exchanging of a variable between threads within a warp without use of shared memory The exchange occurs simultaneously for all active threads within the warp moving 4 bytes of data per thread Exchange of 8 byte quantities must be broken into two separate invocations of sh 1 Threads within a warp are referred to as lanes and for devices of compute capability 3 x may have an index between 0 and warpSize 1 inclusive Four source lane addressing modes are supported __shf1 Direct copy from indexed lane Shfl up Copy from a lane with lower ID relative to caller www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 122 C Language Extensions Shfl down Copy from a lane with higher ID relative to caller Shfl xor Copy from a lane based on bitwise XOR of own lane ID Threads may only read data from another thread which is actively participating in the __shf1 command If the target thread is inactive the retrieved value is undefined All of the sh 1 intrinsics take an optional width parameter which alters the behavior of the intrinsic width must have a value which is a power of 2 results are un
22. it cannot be registered with CUDA The application needs to register the texture for interop before requesting an image or texture handle www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 57 Programming Interface The following code sample uses a kernel to dynamically modify a 2D width x height grid of vertices stored in a vertex buffer object GLuint positionsVBO struct cudaGraphicsResource positionsVBO CUDA int main Initialize OpenGL and GLUT for device 0 and make the OpenGL context current glutDisplayFunc display Explicitly set device 0 cudaSetDevice 0 Create buffer object and register it with CUDA glGenBuffers 1 amp positionsVBO glBindBuffer GL ARRAY BUFFER positionsVBO unsigned int size width height 4 sizeof float glBufferData GL ARRAY BUFFER size 0 GL DYNAMIC DRAW glBindBuffer GL ARRAY BUFFER 0 cudaGraphicsGLRegisterBuffer amp positionsVBO CUDA positionsVBO cudaGraphicsMapFlagsWriteDiscard Launch rendering loop glutMainLoop void display Map buffer object for writing from CUDA float4 positions cudaGraphicsMapResources 1 amp positionsVBO CUDA 0 size t num bytes cudaGraphicsResourceGetMappedPointer void amp positions amp num bytes positionsVBO CUDA Execute kernel iamiam e LG iG EI NT dim3 dimGrid width dimBlock x height dimBlock y 1 createVertices lt lt
23. umeicgpecl dat Coume 07 __ Shared bool isLastBlockDone global void sum const float array unsigned int N Ud volatile float result Each block sums a subset of the input array float partialSum calculatePartialSum array N SEE threadIdx x 0 Thread 0 of each block stores the partial sum to global memory The compiler will use a store operation that bypasses the L1 cache since the result variable is declared as volatile This ensures that the threads of the last block will read the correct partial sums computed by all other blocks result blockIdx x partialSum Thread 0 makes sure that the incrementation of the count variable is only performed after the partial sum has been written to global memory __threadfence Thread 0 signals that it is done unsigned int value atomicInc amp count gridDim x Thread 0 determines if its block is the last M plock to bedone isLastBlockDone value gridDim x 1 Synchronize to make sure that each thread reads the correct value of isLastBlockDone alae __syncthreads isLastBlockDone The last block sums the partial sums stored in result O0 gridDim x 1 float totalSum calculateTotalSum result if threadIdx x 0 Thread 0 of last block stores the total sum to global memory and resets the count varialble so that the next kernel call
24. 32 special function units for single precision floating point transcendental functions gt 4 warp schedulers When a multiprocessor is given warps to execute it first distributes them among the four schedulers Then at every instruction issue time each scheduler issues one instruction for one of its assigned warps that is ready to execute if any A multiprocessor has gt aread only constant cache that is shared by all functional units and speeds up reads from the constant memory space which resides in device memory gt aunified L1 texture cache of 24 KB used to cache reads from global memory gt 64 KB of shared memory for devices of compute capability 5 0 or 96 KB of shared memory for devices of compute capability 5 2 The unified L1 texture cache is also used by the texture unit that implements the various addressing modes and data filtering mentioned in Texture and Surface Memory www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 216 Compute Capabilities There is also an L2 cache shared by all multiprocessors that is used to cache accesses to local or global memory including temporary register spills Applications may query the L2 cache size by checking the I2CacheSize device property see Device Enumeration The cache behavior e g whether reads are cached in both the unified L1 texture cache and L2 or in L2 only can be partially configured on a per access basis using modifiers to the load instruct
25. CUDA C Programming Guide PG 02829 001 v7 5 17 Programming Interface an overview of nvcc workflow and command options A complete description can be found in the nvcc user manual 3 1 1 Compilation Workflow 3 1 1 1 Offline Compilation Source files compiled with nvcc can include a mix of host code i e code that executes on the host and device code i e code that executes on the device nvcc s basic workflow consists in separating device code from host code and then gt compiling the device code into an assembly form PTX code and or binary form cubin object gt and modifying the host code by replacing the lt lt lt gt gt gt syntax introduced in Kernels and described in more details in Execution Configuration by the necessary CUDA C runtime function calls to load and launch each compiled kernel from the PTX code and or cubin object The modified host code is output either as C code that is left to be compiled using another tool or as object code directly by letting nvcc invoke the host compiler during the last compilation stage Applications can then gt Either link to the compiled host code this is the most common case gt Orignore the modified host code if any and use the CUDA driver API see Driver API to load and execute the PTX code or cubin object 3 1 1 2 Just in Time Compilation Any PTX code loaded by an application at runtime is compiled further to binary code by the device driver
26. CUDA C Programming Guide PG 02829 001 v7 5 30 Programming Interface has therefore in general two addresses one in host memory that is returned by cudaHostAlloc ormalloc and one in device memory that can be retrieved using cudaHostGetDevicePointer and then used to access the block from within a kernel The only exception is for pointers allocated with cudaHostAlloc and when a unified address space is used for the host and the device as mentioned in Unified Virtual Address Space Accessing host memory directly from within a kernel has several advantages gt There is no need to allocate a block in device memory and copy data between this block and the block in host memory data transfers are implicitly performed as needed by the kernel gt There is no need to use streams see Concurrent Data Transfers to overlap data transfers with kernel execution the kernel originated data transfers automatically overlap with kernel execution Since mapped page locked memory is shared between host and device however the application must synchronize memory accesses using streams or events see Asynchronous Concurrent Execution to avoid any potential read after write write after read or write after write hazards To be able to retrieve the device pointer to any mapped page locked memory page locked memory mapping must be enabled by calling cudaSetDeviceFlags with the cudaDeviceMapHost flag before any other CUDA call is performed
27. Compute Capabilities Threads Banks Threads Banks Threads Banks o o o EINE NE NNNM oN Oak won NODON AOUN 1 2 3 4 5 6 7 8 9 Bay Ej E E T 8 uu um um au m MD hv Ej NN mo m oOo co LEE Left Linear addressing with a stride of one 32 bit word no bank conflict Middle Linear addressing with a stride of two 32 bit words two way bank conflict Right Linear addressing with a stride of three 32 bit words no bank conflict Figure 17 Strided Shared Memory Accesses Examples for devices of compute capability 3 x in 32 bit mode or compute capability 5 x www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 219 Compute Capabilities Threads Banks Threads Banks Threads Banks 0 0 0 1 1 1 2 2 2 3 3 3 4 4 4 5 5 5 6 6 6 7 7 7 8 8 8 9 9 9 10 10 10 11 11 11 NN 12 12 um 12 LZ a 13 13 13 A 14 14 14 15 15 um 15 16 16 dd 16 i 17 17 um 17 i 18 18 18 19 19 19 HN 20 20 20 HE L 21 21 za 21 A 22 22 22 23 23 23 y 24 24 a 24 25 25 25 26 26 26 27 27 27 28 28 28 29 29 29 30 30 30 31 31 31 Left Conflict free access via random permutation Middle Conflict free access since threads 3 4 6 7 and 9 access the same word within bank 5 Right Conflict free broadcast access threads access the same word within a bank Figure 18 Irregular Shared Memory Accesses Examples for devices of com
28. Initialize Direct3D D3D Direct3DCreate9E x D3D SDK VERSION Get a CUDA enabled adapter unsigned int adapter 0 for adapter lt g pD3D GetAdapterCount adapter D3DADAPTER IDENTIFIER9 adapterId g pD3D GetAdapterIdentifier adapter 0 amp adapterId if cudaD3D9GetDevice amp dev adapterId DeviceName cudaSuccess break Create device D3D CreateDeviceEx adapter D3DDEVTYPE HAL hWnd D3DCREATE HARDWARE VERTEXPROCESSING amp params NULL amp device Use the same devic cudaSetDevice dev Create vertex buffer and register it with CUDA unsigned int size width height sizeof CUSTOMVERTEX device gt CreateVertexBuffer size 0 D3DFVF_CUSTOMVERTEX D3DPOOL DEFAULT amp positionsVB 0 cudaGraphicsD3D9RegisterResource amp positionsVB CUDA positionsVB cudaGraphicsRegisterFlagsNone cudaGraphicsResourceSetMapFlags positionsVB CUDA cudaGraphicsMapFlagsWriteDiscard Launch rendering loop Wakes E Render www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 60 Programming Interface void Render Map vertex buffer for writing from CUDA float4 positions cudaGraphicsMapResources 1 amp positionsVB CUDA 0 size t num bytes cudaGraphicsResourceGetMappedPointer void amp positions amp num bytes positionsVB CUDA Execute kernel cimosa
29. NaNs is the quiet NaN of bit pattern Ox7fffffff gt Double precision floating point absolute value and negation are not compliant with IEEE 754 with respect to NaNs these are passed through unchanged Code must be compiled with ftz false prec div true and prec sqrt true to ensure IEEE compliance this is the default setting see the nvcc user manual for description of these compilation flags Regardless of the setting of the compiler flag tz gt Atomic single precision floating point adds on global memory always operate in flush to zero mode i e behave equivalent to FADD F32 FTZ RN gt Atomic single precision floating point adds on shared memory always operate with denormal support i e behave equivalent to FADD F32 RN In accordance to the IEEE 754R standard if one of the input parameters to fminf fmin fmaxf or fmax is NaN but not the other the result is the non NaN parameter The conversion of a floating point value to an integer value in the case where the floating point value falls outside the range of the integer format is left undefined by IEEE 754 For compute devices the behavior is to clamp to the end of the supported range This is unlike the x86 architecture behavior The behavior of integer division by zero and integer overflow is left undefined by IEEE 754 For compute devices there is no mechanism for detecting that such integer operation exceptions have occurred Integer division
30. Quadro GPUs offer higher performance OpenGL interoperability than GeForce and Tesla GPUs in a multi GPU configuration where OpenGL rendering is performed on the Quadro GPU and CUDA computations are performed on other GPUs in the system 3 2 12 2 Direct3D Interoperability Direct3D interoperability is supported for Direct3D 9Ex Direct3D 10 and Direct3D 11 A CUDA context may interoperate only with Direct3D devices that fulfill the following criteria Direct3D 9Ex devices must be created with DeviceType set to D3DDEVTYPE HAL and BehaviorFlags with the D3DCREATE HARDWARE VERTEXPROCESSING flag Direct3D 10 and Direct3D 11 devices must be created with DriverType setto D3D DRIVER TYPE HARDWARE The Direct3D resources that may be mapped into the address space of CUDA are Direct3D buffers textures and surfaces These resources are registered using cudaGraphicsD3D9RegisterResource cudaGraphicsD3D10RegisterResource and cudaGraphicsD3DllRegisterResource The following code sample uses a kernel to dynamically modify a 2D width x height grid of vertices stored in a vertex buffer object www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 59 Programming Interface 3 2 12 2 1 Direct3D 9 Version Direct3D9 D3D Direct3DDevice9 device struct CUSTOMVERTEX ECORI Wa o YA DWORD color HH Direct3DVertexBuffer9 positionsVB truct cudaGraphicsResource positionsVB CUDA Hw o int main int deyv
31. Texture Memory explained how out of range coordinates are remapped to the valid range based on the addressing mode F 1 Nearest Point Sampling In this filtering mode the value returned by the texture fetch is gt ex x Tli for a one dimensional texture gt fex x y Tl ij for a two dimensional texture gt tex x y z T 1 j k for a three dimensional texture where i floor x j floor y and k floor z Figure 13 illustrates nearest point sampling for a one dimensional texture with N 4 For integer textures the value returned by the texture fetch can be optionally remapped to 0 0 1 0 see Texture Memory www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 200 Texture Fetching X 0 1 2 3 4 Non Normalize 0 0 25 0 5 0 75 1 Normalize Figure 13 Nearest Point Sampling Filtering Mode Nearest point sampling of a one dimensional texture of four texels F 2 Linear Filtering In this filtering mode which is only available for floating point textures the value returned by the texture fetch is gt dex x 1 a T i aT i 1 for a one dimensional texture gt tex x y 1 a 1 B Tlij a 1 B Ti 1 j 1 a BT i j 1 aBT i 1 j 1 for a two dimensional texture gt tex x y z 1 a 1 B 1 y Tli j k a 1 B 1 y Tli 1 k 1 a B 1 y Ti j Lk ap 1 y Ti 1 j 1kj 1 a 1 B y Tii j k 1 4 a 1 B y Ti 1 j k 1 1 a ByT i j 1 k 1 aBy Ti j 1k 1 for a three dimensional texture where
32. The absolute difference value is computed for each byte of the unsigned integers A and B in SIMD fashion The optional accumulate operation add is specified to sum these differences Refer to the document Using Inline PTX Assembly in CUDA for details on using the assembly statement in your code Refer to the PTX ISA documentation Parallel Thread Execution ISA Version 3 0 for example for details on the PTX instructions for the version of PTX that you are using www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 139 Appendix C CUDA DYNAMIC PARALLELISM C 1 Introduction C 1 1 Overview Dynamic Parallelism is an extension to the CUDA programming model enabling a CUDA kernel to create and synchronize with new work directly on the GPU The creation of parallelism dynamically at whichever point in a program that it is needed offers exciting new capabilities The ability to create work directly from the GPU can reduce the need to transfer execution control and data between host and device as launch configuration decisions can now be made at runtime by threads executing on the device Additionally data dependent parallel work can be generated inline within a kernel at run time taking advantage of the GPU s hardware schedulers and load balancers dynamically and adapting in response to data driven decisions or workloads Algorithms and programming patterns that had previously required modifications to eliminate recurs
33. This is called just in time compilation Just in time compilation increases application load time but allows the application to benefit from any new compiler improvements coming with each new device driver It is also the only way for applications to run on devices that did not exist at the time the application was compiled as detailed in Application Compatibility When the device driver just in time compiles some PTX code for some application it automatically caches a copy of the generated binary code in order to avoid repeating the compilation in subsequent invocations of the application The cache referred to as compute cache is automatically invalidated when the device driver is upgraded so that applications can benefit from the improvements in the new just in time compiler built into the device driver Environment variables are available to control just in time compilation as described in CUDA Environment Variables 3 1 2 Binary Compatibility Binary code is architecture specific A cubin object is generated using the compiler option code that specifies the targeted architecture For example compiling with code sm 35 produces binary code for devices of compute capability 3 5 Binary www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 18 Programming Interface compatibility is guaranteed from one minor revision to the next one but not from one minor revision to the previous one or across major revisions In other word
34. Type is the same as DataType except when readMode is cudaReadModeNormalizedFloat see Texture Reference API in which case Type is the corresponding floating point type B 8 2 17 texCubemap template lt class DataType enum cudaTextureReadMode readMode gt Type texCubemap texture lt DataType cudaTextur Pleats dedhevsue Wie wedb reue va 9 l YypeCubemap readMode gt texRef fetches from the CUDA array bound to the cubemap texture reference texRef using texture coordinates x y and z as described in Cubemap Textures Type is equal to DataType except when readMode is equal to cudaReadModeNormalizedFloat see Texture Reference API in which case Type is equal to the matching floating point type B 8 2 18 texCubemapLod template lt class DataType enum cudaTextureReadMode readMode gt Type texCubemapLod texture lt DataType cudaTextureType3D readMode gt texRef zlocie 32 loet yp cloete Yap cloece levely fetches from the CUDA array bound to the two dimensional texture reference texRef using texture coordinate x y z The level of detail is given by level Type is the same as DataType except when readMode is cudaReadModeNormalizedFloat see Texture Reference API in which case Type is the corresponding floating point type B 8 2 19 texCubemapLayered template lt class DataType enum cudaTextureReadMode readMode gt Type texCubemapLayered texture lt DataType cudaTextureTypeCubemapLayered readM
35. deccm ot dee rone ME Srce Sil w q static void helper int fp return 6 device H The closure type of a lambda expression cannot be used in the type or non type argument of a__global___ function template instantiation unless the lambda is defined within a device or global function including operator www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 184 C C Language Support Example template lt typename T gt alobal vore Zoo m i p7 template lt typename T gt struct Si T bg void bar void auto templ CU d be COOL le Uere mo dE n error lambda closure type used in template type argument foo lt lt lt 1 1 gt gt gt Si t decltype templ error lambda closure type used in template type argument E 2 14 2 std initializer_list By default the CUDA compiler will implicitly consider the member functions of std initializer listtohave_host__ device execution space qualifiers and therefore they can be invoked directly from device code The nvcc flag no host device initializer list will disable this behavior member functions of std initializer list will then be considered as host functions and will not be directly invokable from device code Example include initializer list Cewice ime toot eM TES DS MENT cevice vone oan Gite foo IPIE a initializer list containing only constant expressio
36. from Unified Memory on the other hand decouples memory and execution spaces so that all data accesses are fast The term Unified Memory describes as a system that provides memory management services to a wide range of programs from those targeting the Runtime API down to www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 232 Unified Memory Programming those using the Virtual ISA PTX Part of this system defines the managed memory space that opts in to Unified Memory services Managed memory is interoperable and interchangeable with device specific allocations such as those created using the cudaMalloc routine All CUDA operations that are valid on device memory are also valid on managed memory the primary difference is that the host portion of a program is able to reference and access the memory as well J 1 1 Simplifying GPU Programming Unification of memory spaces means that there is no longer any need for explicit memory transfers between host and device Any allocation created in the managed memory space is automatically migrated to where it is needed A program allocates managed memory in one of two ways via the new cudaMallocManaged routine which is semantically similar to cudaMalloc or by defining a global managed variable which is semantically similar toa device variable Precise definitions of these are found later in this document The following code examples illustrate how the use of managed m
37. gencode arch compute 35 code V compute 35 sm 35V embeds binary code compatible with compute capability 2 0 and 3 0 first and second gencode options and PTX and binary code compatible with compute capability 3 5 third gencode option Host code is generated to automatically select at runtime the most appropriate code to load and execute which in the above example will be 2 0 binary code for devices with compute capability 2 0 and 2 1 3 0 binary code for devices with compute capability 3 0 3 5 binary code for devices with compute capability 3 5 and higher 3 x v v v yvy binary code obtained by compiling 3 5 PTX code for devices with compute capabilities 3 5 and higher x cu can have an optimized code path that uses warp shuffle operations for example which are only supported in devices of compute capability 3 0 and higher The CUDA ARCH macro can be used to differentiate various code paths based on compute capability It is only defined for device code When compiling with arch compute_35 for example CUDA ARCH isequalto 350 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 19 Programming Interface Applications using the driver API must compile code to separate files and explicitly load and execute the most appropriate file at runtime The nvcc user manual lists various shorthand for the arch code and gencode compiler options For example arch sm_35 is a shorthand for arch compute_35
38. standard IPC mechanisms e g interprocess shared memory or files and use cudaIpcOpenMemHandle to retrieve a device pointer from the IPC handle that is a valid pointer within this other process Event handles can be shared using similar entry points An example of using the IPC API is where a single master process generates a batch of input data making the data available to multiple slave processes without requiring regeneration or copying 3 2 9 Error Checking All runtime functions return an error code but for an asynchronous function see Asynchronous Concurrent Execution this error code cannot possibly report any of the asynchronous errors that could occur on the device since the function returns before the device has completed the task the error code only reports errors that occur on the host prior to executing the task typically related to parameter validation if an asynchronous error occurs it will be reported by some subsequent unrelated runtime function call The only way to check for asynchronous errors just after some asynchronous function call is therefore to synchronize just after the call by calling cudaDeviceSynchronize or by using any other synchronization mechanisms described in Asynchronous Concurrent Execution and checking the error code returned by cudaDeviceSynchronize The runtime maintains an error variable for each host thread that is initialized to cudaSuccess and is overwritten by the error code e
39. 2 1 5 Ordering and Concurrency The ordering of kernel launches from the device runtime follows CUDA Stream ordering semantics Within a thread block all kernel launches into the same stream are executed in order With multiple threads in the same thread block launching into the same stream the ordering within the stream is dependent on the thread scheduling within the block which may be controlled with synchronization primitives such as __syncthreads Note that because streams are shared by all threads within a thread block the implicit NULL stream is also shared If multiple threads in a thread block launch into the implicit stream then these launches will be executed in order If concurrency is desired explicit named streams should be used Dynamic Parallelism enables concurrency to be expressed more easily within a program however the device runtime introduces no new concurrency guarantees within the CUDA execution model There is no guarantee of concurrent execution between any number of different thread blocks on a device The lack of concurrency guarantee extends to parent thread blocks and their child grids When a parent thread block launches a child grid the child is not guaranteed to begin execution until the parent thread block reaches an explicit synchronization point e g cudaDeviceSynchronize While concurrency will often easily be achieved it may vary as a function of deviceconfiguration application workload a
40. 50 Programming Interface Table 1 Cubemap Fetch ee ee oxs0 o ox oz v Ix gt y and x gt z ee ee lyl gt Ix and ly gt Iz y 0 z gt x and z gt lyl A layered texture can only be a CUDA array by calling cudaMalloc3DArray with the cudaArrayCubemap flag Cubemap textures are fetched using the device function described in texCubemap and texCubemap Cubemap textures are only supported on devices of compute capability 2 0 and higher 3 2 11 1 6 Cubemap Layered Textures A cubemap layered texture is a layered texture whose layers are cubemaps of same dimension A cubemap layered texture is addressed using an integer index and three floating point texture coordinates the index denotes a cubemap within the sequence and the coordinates address a texel within that cubemap A layered texture can only be a CUDA array by calling cudaMalloc3DArray with the cudaArrayLayered and cudaArrayCubemap flags Cubemap layered textures are fetched using the device function described in texCubemapLayered and texCubemapLayered Texture filtering see Texture Fetching is done only within a layer not across layers Cubemap layered textures are only supported on devices of compute capability 2 0 and higher 3 2 11 1 7 Texture Gather Texture gather is a special texture fetch that is available for two dimensional textures only It is performed by the tex2Dgather function which has the
41. 5n for x n otherwise the maximum absolute error is 2 2 x 10 www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 163 Mathematical Functions EC RN Double Precision Floating Point Functions The recommended way to round a double precision floating point operand to an integer with the result being a double precision floating point number is rint not round The reason is that round maps to an 8 instruction sequence on the device whereas rint maps to a single instruction trunc ceil and floor each map to a single instruction as well Table 7 Double Precision Mathematical Standard Library Functions with Maximum ULP Error The maximum error is stated as the absolute value of the difference in ulps between a correctly rounded double precision result and the result returned by the CUDA library function www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 164 Mathematical Functions em www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 165 Mathematical Functions LONE NN em CNN feet lgamma x 4 outside interval 11 0001 2 2637 larger inside 30 x 7 for x 8 otherwise the maximum absolute error is 5 x 102 31 x 7 for x 8 otherwise the maximum absolute error is 5 x 102 www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 166 Mathematical Functions Function Maximum ulp error oo 12 10 y0 x 7 for x lt 8
42. Kernel0 lt lt lt gt gt gt Serial code Parallel kernel Kerneli lt lt lt gt gt gt Serial code executes on the host while parallel code executes on the device Figure 8 Heterogeneous Programming www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 15 Programming Model 2 5 Compute Capability The compute capability of a device is represented by a version number also sometimes called its SM version This version number identifies the features supported by the GPU hardware and is used by applications at runtime to determine which hardware features and or instructions are available on the present GPU The compute capability comprises a major revision number X and a minor revision number Y and is denoted by X Y Devices with the same major revision number are of the same core architecture The major revision number is 5 for devices based on the Maxwell architecture 3 for devices based on the Kepler architecture 2 for devices based on the Fermi architecture and 1 for devices based on the Tesla architecture The minor revision number corresponds to an incremental improvement to the core architecture possibly including new features CUDA Enabled GPUs lists of all CUDA enabled devices along with their compute capability Compute Capabilities gives the technical specifications of each compute capability The compute capability version of a particular GPU should not be confused with the CUDA version e
43. Moe Ww aime Juge boundaryMode cudaBoundaryModeTrap reads the CUDA array bound to the cubemap layered surface reference surfRef using coordinate x and y and index layerFace B 9 2 14 surfCubemapLayeredwrite template lt class Type gt void surfCubemapLayeredwrite Type data surface lt void cudaSurfaceTypeCubemapLayered gt surfRef GONE ox dude Svp aime deverias boundaryMode cudaBoundaryModeTrap writes value data to the CUDA array bound to the cubemap layered reference surfRef at coordinate x and y and index layerFace B 10 Read Only Data Cache Load Function The read only data cache load function is only supported by devices of compute capability 3 5 and higher ldgi const t address returns the data of type T located at address address where T is char short int long long unsigned char unsigned short unsigned int unsigned long long int2 int4 uint2 uint4 float float2 float4 double or double2 The operation is cached in the read only data cache see Global Memory B 11 Time Function Glock 1 Glock p long long int clock64 when executed in device code returns the value of a per multiprocessor counter that is incremented every clock cycle Sampling this counter at the beginning and at the end of a kernel taking the difference of the two samples and recording the result per thread provides a measure for each thread of the number of clock cycles taken by the device to
44. NEE 142 C 2 1 5 Ordering and ConcuUrrency sierra soot ha cide oO ER ERE EK EE SER Ea ARE ERR 143 C 2 1 6 Device Managernent ese eee han hh I nx EXC ERE E ERE FECE ERES 143 C 2 2 Memory Model es ches teuer n IRR nn tess eoa n EE re tiles SERE e eS E EEEPC e RES rM EUER 143 C 2 2 1 Coherence and Consistency ccccccccscssesscscccecceecceseesssscssesaeesaessesees 144 C 3 Programming Interface eere erinnerte nah naa nn E OPERE a EBERT EFEEE EUR N D Knie 146 C 3 1 CUDA C C Reference 2 eco e retener x hk xx ER EX AREE A E CH RESEKM E KR CEDE S 146 C 3 1 1 Device Side Kernel Launch ceeeeeeeeeeeeee eene ehh enhn enn 146 SN EDGE 147 Gm M ME2U ccm 148 C 3 1 4 Synchronization ore ee eru pete three e rante nhe ei n tco i we aia baie aee 148 C 3 1 5 Device Management eere rer e repr eph e nesses x ERA e EVA RYE ae Era cu Rees 148 C 3 1 6 Memory Declarations ee oe oe eee tnn nhe eot el nr torre ev ne REESE EF EE Es 149 C 3 1 7 API Errors and Launch Failures eceeessseeeeseseeeee ee ne enhn 150 C 3 1 8 API Refererce eec eei pne enl Rec eed RO DDe ned v red ea EENR nd res xs 151 C 3 2 Device side Launch from PTX eecseseeeeeeeeeee eene enne nhe nnne 152 C 3 2 1 Kernel Launch APIS Giai oce dete eruere ro eere y aeo uhr eee v EE vere kkr vette vues 152 C 3 2 2 Parameter Buffer Layout sccscccccscncssneesecccccscceenneeasevecesaessaeeeaeees 154 C 3 3 Toolk
45. OpenGL or Direct3D A resource must be registered to CUDA before it can be mapped using the functions mentioned in OpenGL Interoperability and Direct3D Interoperability These functions return a pointer to a CUDA graphics resource of type struct cudaGraphicsResource Registering a resource is potentially high overhead and therefore typically called only once per resource A CUDA graphics resource is unregistered using cudaGraphicsUnregisterResource Each CUDA context which intends to use the resource is required to register it separately Once a resource is registered to CUDA it can be mapped and unmapped as many times as necessary using cudaGraphicsMapResources and cudaGraphicsUnmapResources cudaGraphicsResourceSetMapFlags can be called to specify usage hints write only read only that the CUDA driver can use to optimize resource management www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 56 Programming Interface A mapped resource can be read from or written to by kernels using the device memory address returned by cudaGraphicsResourceGetMappedPointer for buffers and cudaGraphicsSubResourceGetMappedArray for CUDA arrays Accessing a resource through OpenGL Direct3D or another CUDA context while it is mapped produces undefined results OpenGL Interoperability and Direct3D Interoperability give specifics for each graphics API and some code samples SLI Interoperability gives specifics for when the system
46. T tex2Dgather cudaTextureObject t texObj hocwE xx aloa wy ios Cons 0 p fetches from the CUDA array specified by the 2D texture object texObj using texture coordinates x and y and the comp parameter as described in Texture Gather www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 104 C Language Extensions B 8 2 Texture Reference API B 8 2 1 tex1Dfetch template lt class DataType gt Type texlDfetch texture lt DataType cudaTextureTypelD cudaReadModeElementType texRef quale xg float texliDfetch texture unsigned char cudaTextureTypelD cudaReadModeNormalizedFloat texRef IE 9 E float texliDfetch texture lt signed char cudaTextureTypelD cudaReadModeNormalizedFloat texRef aioe Sei P float texlDfetch texture unsigned short cudaTextureTypelD cudaReadModeNormalizedFloat texRef siehe xw B float texliDfetch texture lt signed short cudaTextureTypelD cudaReadModeNormalizedFloat texRef gue x pg fetches from the region of linear memory bound to the one dimensional texture reference texRef using integer texture coordinate x tex1Dfetch only works with non normalized coordinates so only the border and clamp addressing modes are supported It does not perform any texture filtering For integer types it may optionally promote the integer to single precision floating point Besides the functions shown above 2 and 4 tuples are supported for example
47. Table 1 5Cubemap Fetch cnosti eerte Rede Ee EE Ee eH SERRE EE E RR OR PORE OE A Eee tiene 51 Table 2 Throughput of Native Arithmetic Instructions ssssssesssssssesesssssssesesssseseeeeeeo 83 Table 3 Alignment Requirements in Device Code cece eee cece eee e scence eeeeeeeeeeaeeseeeeeees 95 Table 4 New Device only Launch Implementation Functions eese 151 Table 5 Supported API FUNCtIONS c sccscceessedeecnsscensseseesseneessutescseenasenesssessacenneasasies 151 Table 6 Single Precision Mathematical Standard Library Functions with Maximum ULP Error 160 Table 7 Double Precision Mathematical Standard Library Functions with Maximum ULP Error 164 Table 8 Functions Affected by use fast math ccc cece cece cence ee ee eee eee 168 Table 9 Single Precision Floating Point Intrinsic Functions sce eee eee e eect eee eeeeeeeeeeeee 169 Table 10 Double Precision Floating Point Intrinsic Functions cc cece cee eceeeeeeeeeeeeeeees 170 Table 11 C 11 Language Features ccccccsnseesccencesceeeneescecseenaesanenssesecesaeeeaeesaeens 171 Table 12 Feature Support per Compute Capability cece cece eee eee cee eee e eee eeeeeeeeeeees 204 Table 13 Technical Specifications per Compute Capability cece cece eee ee ee eeeeeeee ee 205 Table 14 Objects Available in the CUDA Driver API ccecce eee eeee cece ne ene 221 Table 15 CUDA Environment Variables
48. The resulting requests are then serviced at the throughput of the constant cache in case of a cache hit or at the throughput of device memory otherwise Texture and Surface Memory The texture and surface memory spaces reside in device memory and are cached in texture cache so a texture fetch or surface read costs one memory read from device memory only on a cache miss otherwise it just costs one read from texture cache The texture cache is optimized for 2D spatial locality so threads of the same warp that read texture or surface addresses that are close together in 2D will achieve best performance Also it is designed for streaming fetches with a constant latency a cache hit reduces DRAM bandwidth demand but not fetch latency www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 82 Performance Guidelines Reading device memory through texture or surface fetching present some benefits that can make it an advantageous alternative to reading device memory from global or constant memory gt If the memory reads do not follow the access patterns that global or constant memory reads must follow to get good performance higher bandwidth can be achieved providing that there is locality in the texture fetches or surface reads gt Addressing calculations are performed outside the kernel by dedicated units gt Packed data may be broadcast to separate variables in a single operation gt 8 bit and 16 bit integer input data may be op
49. allocate and deallocate device memory transfer data between host memory and device memory manage systems with multiple devices etc A complete description of the runtime can be found in the CUDA reference manual The runtime is built on top of a lower level C API the CUDA driver API which is also accessible by the application The driver API provides an additional level of control by exposing lower level concepts such as CUDA contexts the analogue of host processes for the device and CUDA modules the analogue of dynamically loaded libraries for the device Most applications do not use the driver API as they do not need this additional level of control and when using the runtime context and module management are implicit resulting in more concise code The driver API is introduced in Driver API and fully described in the reference manual 3 1 Compilation with NVCC Kernels can be written using the CUDA instruction set architecture called PTX which is described in the PTX reference manual It is however usually more effective to use a high level programming language such as C In both cases kernels must be compiled into binary code by nvcc to execute on the device nvcc is a compiler driver that simplifies the process of compiling C or PTX code It provides simple and familiar command line options and executes them by invoking the collection of tools that implement the different compilation stages This section gives www nvidia com
50. amp ret 1000 sizeof int AplusB 1 1000 gt gt gt ret 10 100 cudaDeviceSynchronize inewe Gaeue L O9 aum S abs printf Viele ATB elus ah serene at p cudaFree ret return 0 Finally language integration allows direct reference of aGPU declared __ managed __ variable and simplifies a program further when global variables are used device managed int ret 1000 _ oleval onc Aplus ime ep ime o 1 ret threadIdx x a b threadIdx x int main AplusB lt lt lt 1 1000 gt gt gt 10 100 cudaDeviceSynchronize rozlane n07 lt LO aik omae Veola r SeN atn Ler Ee return 0 Note the absence of explicit cudaMemcpy commands and the fact that the return array ret is visible on both CPU and GPU It is worth a comment on the synchronization between host and device Notice how in the non managed example the synchronous cudaMemepy routine is used both to synchronize the kernel that is to wait for it to finish running and to transfer the data to the host The Unified Memory examples do not call cudaMemcpy and so require an explicit cudaDeviceSynchronize before the host program can safely use the output from the GPU An alternative here would be to set the environment variable CUDA_LAUNCH_BLOCKING 1 ensuring that all kernel launches complete synchronously This simplifies the code by eliminating all explicit synchronization but obviously has broader impact o
51. and a device each with their own separate memory Device Memory gives an overview of the runtime functions used to manage device memory Shared Memory illustrates the use of shared memory introduced in Thread Hierarchy to maximize performance Page Locked Host Memory introduces page locked host memory that is required to overlap kernel execution with data transfers between host and device memory Asynchronous Concurrent Execution describes the concepts and API used to enable asynchronous concurrent execution at various levels in the system www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 20 Programming Interface Multi Device System shows how the programming model extends to a system with multiple devices attached to the same host Error Checking describes how to properly check the errors generated by the runtime Call Stack mentions the runtime functions used to manage the CUDA C call stack Texture and Surface Memory presents the texture and surface memory spaces that provide another way to access device memory they also expose a subset of the GPU texturing hardware Graphics Interoperability introduces the various functions the runtime provides to interoperate with the two main graphics APIs OpenGL and Direct3D 3 2 1 Initialization There is no explicit initialization function for the runtime it initializes the first time a runtime function is called more specifically any function other than functions from th
52. are cached Using the dlem compilation flag they can be configured at compile time to be cached in both L1 and L2 Xptxas dlcm ca this is the default setting or in L2 only Xptxas dlcm cg A cache line is 128 bytes and maps to a 128 byte aligned segment in device memory Memory accesses that are cached in both L1 and L2 are serviced with 128 byte memory transactions whereas memory accesses that are cached in L2 only are serviced with 32 byte memory transactions Caching in L2 only can therefore reduce over fetch for example in the case of scattered memory accesses If the size of the words accessed by each thread is more than 4 bytes a memory request by a warp is first split into separate 128 byte memory requests that are issued independently gt Two memory requests one for each half warp if the size is 8 bytes gt Four memory requests one for each quarter warp if the size is 16 bytes Each memory request is then broken down into cache line requests that are issued independently A cache line request is serviced at the throughput of L1 or L2 cache in case of a cache hit or at the throughput of device memory otherwise Note that threads can access any words in any order including the same words If a non atomic instruction executed by a warp writes to the same location in global memory for more than one of the threads of the warp only one thread performs a write and which thread does it is undefined Figure 16 s
53. atime giclee as wl unsigned long long int address unsvgned lome Vong imne Ole evacddrossmacmulslly assumed elo 4 assumed old old atomicCAS address as ull assumed double as longlong val longlong as double assumed Note uses integer comparison to avoid hang in case of NaN since NaN NaN while assumed old return _longlong_as_double old B 12 1 Arithmetic Functions B 12 1 1 atomicAdd int atomicAdd int address int val unsigned int atomicAdd unsigned int address unsigned int val unsigned long long int atomicAdd unsigned long long int address unsigned long long int val float atomicAdd float address float val reads the 32 bit or 64 bit word old located at the address address in global or shared memory computes old val and stores the result back to memory at the same address These three operations are performed in one atomic transaction The function returns old www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 118 C Language Extensions The floating point version of atomicAdd is only supported by devices of compute capability 2 x and higher B 12 1 2 atomicSub int atomicSub int address int val unsigned int atomicSub unsigned int address unsigned int val reads the 32 bit word o1d located at the address address in global or shared memory computes old val and stores the result back to memory at the same address These
54. before thread 2 s read of X and Y Memory fence functions can be used to enforce some ordering void threadfence block ensures that gt All writes to shared and global memory made by the calling thread before the call to threadfence block are observed by all threads in the block of the calling thread as occurring before all writes to shared memory and global memory made by the calling thread after the callto threadfence block gt All reads from shared memory and global memory made by the calling thread before the call to threadfence block are performed before all reads from shared memory and global memory made by the calling thread after the call to threadfence block void threadfence acts as threadfence block for all threads in the block of the calling thread and also ensures that no writes to global memory made by the calling thread after the call to threadfence are observed by any thread in the device as occurring before any write to global memory made by the calling thread before the callto threadfence www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 97 C Language Extensions Note that for this ordering guarantee to be true the observing threads must truly observe global memory and not cached versions of it this is ensured by using the volatile keyword as detailed in Volatile Qualifier void _threadfence system acts as threadfence block for all threads in t
55. being used for the copy operation otherwise it will be accessed from the host Similar rules apply to the destination when cudaMemcpy ToHost is specified and the destination is managed memory Note that a segmentation fault can occur during the copy operation if data is being accessed from the host and its associated stream is active on the GPU If cudaMemcpyDeviceTo is specified and the source data is managed then it will be accessed from the device The source must either have global visibility or it must be associated with the copy stream otherwise an error is returned Similar rules apply to the destination when cudaMemcpy ToDevice is specified and the destination is managed memory If cudaMemcpyDefault is specified then managed data will be accessed from the device if it has global visibility or if it s associated with the copy stream otherwise it will be accessed from the host When using cudaMemset with managed memory the data is always accessed from the device The data must either have global visibility or it must be associated with the stream being used for the cudaMemset operation otherwise an error is returned When data is accessed from the device either by cudaMemcpy or cudaMemset the stream of operation is considered to be active on the GPU During this time any CPU access of data that is associated with that stream or data that has global visibility will result in a segmentation fault The program must
56. blocks that will be used to execute the function on the device as well as the associated stream see CUDA C Runtime for a description of streams The execution configuration is specified by inserting an expression of the form lt lt lt Dg Db Ns S gt gt gt between the function name and the parenthesized argument list where gt Dg is of type dim3 see dim3 and specifies the dimension and size of the grid such that Dg x Dg y Dg z equals the number of blocks being launched gt Db is of type dim3 see dim3 and specifies the dimension and size of each block such that Db x Db y Db z equals the number of threads per block gt Ns is of type size_t and specifies the number of bytes in shared memory that is dynamically allocated per block for this call in addition to the statically allocated memory this dynamically allocated memory is used by any of the variables declared as an external array as mentioned in shared Ns is an optional argument which defaults to 0 gt Sis of type cudaStream t and specifies the associated stream S is an optional argument which defaults to 0 As an example a function declared as global void Func float parameter must be called like this Func lt lt lt Dg Db Ns parameter The arguments to the execution configuration are evaluated before the actual function arguments The function call will fail if Dg or Db are greater than the maximum sizes allowed for the dev
57. but only after the parent synchronizes on the child s completion Concurrent accesses by parent and child may result in inconsistent data C 3 Programming Interface C 3 1 CUDA C C Reference This section describes changes and additions to the CUDA C C language extensions for supporting Dynamic Parallelism The language interface and API available to CUDA kernels using CUDA C C for Dynamic Parallelism referred to as the Device Runtime is substantially like that of the CUDA Runtime API available on the host Where possible the syntax and semantics of the CUDA Runtime API have been retained in order to facilitate ease of code reuse for routines that may run in either the host or device environments As with all code in CUDA C C the APIs and code outlined here is per thread code This enables each thread to make unique dynamic decisions regarding what kernel or operation to execute next There are no synchronization requirements between threads within a block to execute any of the provided device runtime APIs which enables the device runtime API functions to be called in arbitrarily divergent kernel code without deadlock C 3 1 1 Device Side Kernel Launch Kernels may be launched from the device using the standard CUDA lt lt lt gt gt gt syntax kernel name lt lt lt Dg Db Ns S gt gt gt kernel arguments gt Dgisoftype dim3 and specifies the dimensions and size of the grid gt Db is of type dim3 and specif
58. code compute_35 sm_35 which is the same as gencode arch compute 35 code compute_35 sm_35 3 1 5 C C Compatibility The front end of the compiler processes CUDA source files according to C syntax rules Full C is supported for the host code However only a subset of C is fully supported for the device code as described in C C Language Support 3 1 6 64 Bit Compatibility The 64 bit version of nvcc compiles device code in 64 bit mode i e pointers are 64 bit Device code compiled in 64 bit mode is only supported with host code compiled in 64 bit mode Similarly the 32 bit version of nvec compiles device code in 32 bit mode and device code compiled in 32 bit mode is only supported with host code compiled in 32 bit mode The 32 bit version of nvcc can compile device code in 64 bit mode also using the m64 compiler option The 64 bit version of nvcc can compile device code in 32 bit mode also using the m32 compiler option 3 2 CUDA C Runtime The runtime is implemented in the cudart library which is linked to the application either statically via cudart lib orlibcudart a or dynamically via cudart d11 or libcudart so Applications that require cudart d11 and or cudart so for dynamic linking typically include them as part of the application installation package All its entry points are prefixed with cuda As mentioned in Heterogeneous Programming the CUDA programming model assumes a system composed of a host
59. com CUDA C Programming Guide PG 02829 001 v7 5 213 Compute Capabilities G 4 2 Global Memory Global memory accesses for devices of compute capability 3 x are cached in L2 and for devices of compute capability 3 5 or 3 7 may also be cached in the read only data cache described in the previous section they are normally not cached in L1 Some devices of compute capability 3 5 and devices of compute capability 3 7 allow opt in to caching of global memory accesses in L1 via the Xptxas dlcm ca option to nvcc Caching in L2 behaves in the same way as for devices of compute capability 2 x see Global Memory Data that is read only for the entire lifetime of the kernel can also be cached in the read only data cache described in the previous section by reading it using the 1dg function see Read Only Data Cache Load Function When the compiler detects that the read only condition is satisfied for some data it will use 1dg to read it The compiler might not always be able to detect that the read only condition is satisfied for some data Marking pointers used for loading such data with both the const and restrict qualifiers increases the likelihood that the compiler will detect the read only condition Figure 16 shows some examples of global memory accesses and corresponding memory transactions www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 214 Compute Capabilities Aligned accesses sequential non
60. entire launch tree has completed Any ECC errors which arise during execution of a nested program will either generate an exception or continue execution depending upon error and configuration www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 159 Appendix D MATHEMATICAL FUNCTIONS The reference manual lists along with their description all the functions of the C C standard library mathematical functions that are supported in device code as well as all intrinsic functions that are only supported in device code This appendix provides accuracy information for some of these functions when applicable D 1 Standard Functions The functions from this section can be used in both host and device code This section specifies the error bounds of each function when executed on the device and also when executed on the host in the case where the host does not supply the function The error bounds are generated from extensive but not exhaustive tests so they are not guaranteed bounds Single Precision Floating Point Functions Addition and multiplication are IEEE compliant so have a maximum error of 0 5 ulp The recommended way to round a single precision floating point operand to an integer with the result being a single precision floating point number is rintf not roundf The reason is that round maps to an 8 instruction sequence on the device whereas rintf maps to a single instruction truncf ceilf
61. etc for each warp processed by a multiprocessor is maintained on chip during the entire lifetime of the warp Therefore switching from one execution context to another has no cost and at every instruction issue time a warp scheduler selects a warp that has threads ready to execute its next instruction the active threads of the warp and issues the instruction to those threads In particular each multiprocessor has a set of 32 bit registers that are partitioned among the warps and a parallel data cache or shared memory that is partitioned among the thread blocks The number of blocks and warps that can reside and be processed together on the multiprocessor for a given kernel depends on the amount of registers and shared memory used by the kernel and the amount of registers and shared memory available on the multiprocessor There are also a maximum number of resident blocks and a maximum number of resident warps per multiprocessor These limits as well the amount of registers and shared memory available on the multiprocessor are a function of the compute capability of the device and are given in Appendix Compute Capabilities If there are not enough registers or shared memory available per multiprocessor to process at least one block the kernel will fail to launch The total number of warps in a block is as follows 3L T ceil 1 W size gt Tis the number of threads per block gt W iz is the warp size which is equal to 32 gt ceil x
62. explicit syncthreads barriers so it is impossible to tell whether execution order has been modified by printf or by other scheduling behaviour in the hardware B 17 3 Associated Host Side API The following API functions get and set the size of the buffer used to transfer the printf arguments and internal metadata to the host default is 1 megabyte gt cudaDeviceGetLimit size t size cudaLimitPrintfFifoSize gt cudaDeviceSetLimit cudaLimitPrintfFifoSize size t size www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 129 C Language Extensions B 17 4 Examples The following code sample include lt stdio h gt _ global void helloCUDA float f printf Hello thread d f f n threadIdx x f int main Neweko CUDA lt lt aile eS o2 sdb p cudaDeviceSynchronize return 0 will output Hello thread 2 f 1 2345 Hello thread 1 f 1 2345 Hello thread 4 f 1 2345 Hello thread 0 f 1 2345 Hello thread 3 f 1 2345 Notice how each thread encounters the printf command so there are as many lines of output as there were threads launched in the grid As expected global values i e float f are common between all threads and local values i e threadIdx x are distinct per thread The following code sample include lt stdio h gt global X void helloCUDA float f if threadIdx x 0 printf Hello thread d f f n threadIdx x f int main hel loCUDA lt lt
63. first field of T F uses B in its definition such that B is laid out at offset 0 in the definition of F v wv As long as affected class types are used exclusively in host or device code the program should work correctly do not pass objects of such class types between between host and device code e g as arguments to global functions or through cudaMemcpy calls E 2 11 Templates A type or template cannot be used in the type non type or template template argument ofa global function template instantiation if either gt The type or template is defined withina host or host device gt The type or template is a class member with private or protected access and its parent class is not defined withina device or global function Example template typename T global void myKernel void class myClass private Sirus shame C d o E PUDIR gesmwele otel Marnen VIO Si e error inner t is used in template argument but it is private myKernel lt inner t gt lt lt lt 1 1 gt gt gt he One way to debug suspected layout mismatch of a type C is to use printf to output the values of sizeof C and offsetof C field inhost and device code www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 182 C C Language Support E 2 12 Trigraphs and Digraphs Trigraphs are not supported on any platform Digraphs are not supported on Windows E 2 13 Const qualified variabl
64. for the targeted architecture Inspection of the cubin object using cuobjdump will tell if this is the case Also the compiler reports total local memory usage per kernel 1mem when compiling with the ptxas options v option Note that some mathematical functions have implementation paths that might access local memory The local memory space resides in device memory so local memory accesses have same high latency and low bandwidth as global memory accesses and are subject to the same requirements for memory coalescing as described in Device Memory Accesses Local memory is however organized such that consecutive 32 bit words are accessed by consecutive thread IDs Accesses are therefore fully coalesced as long as all threads in a warp access the same relative address e g same index in an array variable same member in a structure variable On devices of compute capability 2 x and 3 x local memory accesses are always cached in L1 and L2 in the same way as global memory accesses see Compute Capability 2 x and Compute Capability 3 x www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 81 Performance Guidelines On devices of compute capability 5 x local memory accesses are always cached in L2 in the same way as global memory accesses see Compute Capability 5 x Shared Memory Because it is on chip shared memory has much higher bandwidth and much lower latency than local or global memory To achieve high bandwidth sh
65. g CUDA 5 5 CUDA 6 CUDA 6 5 which is the version of the CUDA software platform The CUDA platform is used by application developers to create applications that run on many generations of GPU architectures including future GPU architectures yet to be invented While new versions of the CUDA platform often add native support for a new GPU architecture by supporting the compute capability version of that architecture new versions of the CUDA platform typically also include software features that are independent of hardware generation The Tesla architecture is no longer supported starting with CUDA 7 0 www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 16 Chapter 3 PROGRAMMING INTERFACE CUDA C provides a simple path for users familiar with the C programming language to easily write programs for execution by the device It consists of a minimal set of extensions to the C language and a runtime library The core language extensions have been introduced in Programming Model They allow programmers to define a kernel as a C function and use some new syntax to specify the grid and block dimension each time the function is called A complete description of all extensions can be found in C Language Extensions Any source file that contains some of these extensions must be compiled with nvcc as outlined in Compilation with NVCC The runtime is introduced in Compilation Workflow It provides C functions that execute on the host to
66. he se eee nnne 100 B6 Texture Functlons ii oir terere ptr e ve Dervae pF Pee Yevre po Fer ebbae ENO eS 100 B 8 1 Texture Object APIs essen e ea onima eie nett RE ndis eX REC E ee EX RARE RE DET RO CK R ea dud eU 101 B 8 1 1 texTDfetch ies eret ter tere Drev re e e E ER P Ur FU i a PB U VERE ENT 101 LE RECS IU 101 B 8 1 3 tex1DLod ice er cette eee R ER gre RR UE C ERR SER CeboR c eeRE neg R EE ErCOEE 101 B 8 1 4 tex1DGrad si eet Lott reis avt aa FOrva e E tes eenseeetecwees Feld POMPE TE 101 B 8 1 5 tex2D u creo rex A T ex Rx Eee tu de ExueQ DIC lex axes ex eet A beds Er EU DUM X MEE 101 RI E BEC VAST Eod o eem 101 UE ARIS VAECCH UmT 102 B 8 1 8 tex3D aan aAA AAEE Ex DO EN MexTM OR NR den ERO A M OE Ere UR ENTE ovens 102 UM i e Bac ip Fors o e 102 B 8 1 10 tex3DGrad oreet eerte teet Ere een gren UR ex re EE ree re ev Ete e aae Evae 102 B 8 1 11 texfDLayered 5 edicere eh hee cessed eR eedeeloveecedenes opdeteaes 102 B 8 1 12 tex1DLEayeredLod s cc ori v eere ve etie Etpe en sete veri e ora a vera PUn Y wies 102 B 8 1 13 textDLayeredGrad ceeeeeeesseeeeee eee eee eh enhn nhe hh nnne 103 B 8 1 14 tex2DLayered edis eeet oe e eR eb pr pP KENEEN ENEN E PUR ERE e ed 103 B 8 1 15 texZDLayeredLod eicere Etre ep be n ke Ie Y sien v rPEN CU EY Pv PEE iE Re bEkRe E 103 B 8 1 16 tex2DLayeredGrad cs
67. host to device issued to stream 1 overlaps with the kernel launch issued to stream 0 On devices that do support concurrent data transfers the two streams of the code sample of Creation and Destruction do overlap The memory copy from host to device issued to stream 1 overlaps with the memory copy from device to host issued to stream 0 and even with the kernel launch issued to stream 0 assuming the device supports overlap of data transfer and kernel execution However for devices of compute capability 3 0 or lower the kernel executions cannot possibly overlap because www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 35 Programming Interface the second kernel launch is issued to stream 1 after the memory copy from device to host is issued to stream 0 so it is blocked until the first kernel launch issued to stream 0 is complete as per Implicit Synchronization If the code is rewritten as above the kernel executions overlap assuming the device supports concurrent kernel execution since the second kernel launch is issued to stream 1 before the memory copy from device to host is issued to stream 0 In that case however the memory copy from device to host issued to stream 0 only overlaps with the last thread blocks of the kernel launch issued to stream 1 as per Implicit Synchronization which can represent only a small portion of the total execution time of the kernel 3 2 5 5 6 Callbacks The runtime provides a wa
68. iL O0 cudaDeviceSynchronize y 20 Success GPU is idle so access is OK return 0 As this example shows a CPU thread may not access any managed data in between performing a kernel launch and a subsequent synchronization call regardless of whether the GPU kernel actually touches that same data or any managed data at all The mere potential for concurrent CPU and GPU access is sufficient for a process level exception to be raised Note that if memory is dynamically allocated with cudaMallocManaged or cuMemAllocManaged while the GPU is active the behavior of the memory is unspecified until additional work is launched or the GPU is synchronized Attempting to access the memory on the CPU during this time may or may not cause a segmentation fault This does not apply to memory allocated using the flag cudaMemAttachHost or CU MEM ATTACH HOST J 2 2 2 Explicit Synchronization and Logical GPU Activity Note that explicit synchronization is required even if kernel runs quickly and finishes before the CPU touches y in the above example Unified Memory uses logical activity to determine whether the GPU is idle This aligns with the CUDA programming model which specifies that a kernel can run at any time following a launch and is not guaranteed to have finished until the host issues a synchronization call Any function call that logically guarantees the GPU completes its work is valid This includes cudaDeviceSynchronize cudaS
69. is in SLI mode 3 2 12 1 OpenGL Interoperability The OpenGL resources that may be mapped into the address space of CUDA are OpenGL buffer texture and renderbuffer objects A buffer object is registered using cudaGraphicsGLRegisterBuffer In CUDA it appears as a device pointer and can therefore be read and written by kernels or via cudaMemcpy calls A texture or renderbuffer object is registered using cudaGraphicsGLRegisterImage In CUDA it appears as a CUDA array Kernels can read from the array by binding it to a texture or surface reference They can also write to it via the surface write functions if the resource has been registered with the cudaGraphicsRegisterFlagsSurfaceLoadStore flag The array can also be read and written via cudaMemcpy2D calls cudaGraphicsGLRegisterImage supports all texture formats with 1 2 or 4 components and an internal type of float e g GL RGBA FLOAT32 normalized integer e g GL RGBA8 GL INTENSITY16 and unnormalized integer e g GL RGBA8UI please note that since unnormalized integer formats require OpenGL 3 0 they can only be written by shaders not the fixed function pipeline The OpenGL context whose resources are being shared has to be current to the host thread making any OpenGL interoperability API calls Please note When an OpenGL texture is made bindless say for example by requesting an image or texture handle using the glGetTextureHandle glGetImageHandle APIs
70. is not current to the thread Each host thread has a stack of current contexts cuCtxCreate pushes the new context onto the top of the stack cuCtxPopCurrent may be called to detach the context from the host thread The context is then floating and may be pushed as the current context for any host thread cuCtxPopCurrent also restores the previous current context if any A usage count is also maintained for each context cuCtxCreate creates a context with a usage count of 1 cuCtxAttach increments the usage count and cuCtxDetach decrements it A context is destroyed when the usage count goes to 0 when calling cuCtxDetach or cuCtxDestroy Usage count facilitates interoperability between third party authored code operating in the same context For example if three libraries are loaded to use the same context each library would call cuCtxAttach to increment the usage count and cuCtxDetach to decrement the usage count when the library is done using the context For most libraries it is expected that the application will have created a context before loading or initializing the library that way the application can create the context using its own heuristics and the library simply operates on the context handed to it Libraries that wish to create their own contexts unbeknownst to their API clients who may or may not have created contexts of their own would use cuCtxPushCurrent and cuCtxPopCurrent as illust
71. it might end up waiting on itself if it makes such a call leading to a deadlock 3 2 5 5 7 Stream Priorities The relative priorities of streams can be specified at creation using cudaStreamCreateWithPriority The range of allowable priorities ordered as highest priority lowest priority can be obtained using the cudaDeviceGetStreamPriorityRange function At runtime as blocks in low priority schemes finish waiting blocks in higher priority streams are scheduled in their place www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 36 Programming Interface The following code sample obtains the allowable range of priorities for the current device and creates streams with the highest and lowest available priorities get the range of stream priorities for this device int priority high priority low cudaDeviceGetStreamPriorityRange amp priority low amp priority high create streams with highest and lowest available priorities cuda c team S th EST EO WI cudaStreamCreateWithPriority amp st high cudaStreamNonBlocking priority high cudaStreamCreateWithPriority amp st low cudaStreamNonBlocking priority low 3 2 5 6 Events The runtime also provides a way to closely monitor the device s progress as well as perform accurate timing by letting the application asynchronously record events at any point in the program and query when these events are completed An event has completed when all tasks or op
72. kernel should use to ensure that minBlocksPerMultiprocessor blocks or a single block if minBlocksPerMultiprocessor is not specified of maxThreadsPerBlock threads can reside on the multiprocessor see Hardware Multithreading for the relationship between the number of registers used by a kernel and the number of registers allocated per block The compiler then optimizes register usage in the following way gt If the initial register usage is higher than L the compiler reduces it further until it becomes less or equal to L usually at the expense of more local memory usage and or higher number of instructions gt If the initial register usage is lower than L gt IfmaxThreadsPerBlock is specified and minBlocksPerMultiprocessor is not the compiler uses maxThreadsPerBlock to determine the register usage thresholds for the transitions between n and n 1 resident blocks i e when using one less register makes room for an additional resident block as in the example of Multiprocessor Level and then applies similar heuristics as when no launch bounds are specified gt IfbothminBlocksPerMultiprocessor and maxThreadsPerBlock are specified the compiler may increase register usage as high as L to reduce the number of instructions and better hide single thread instruction latency A kernel will fail to launch if it is executed with more threads per block than its launch bound maxThreadsPerBlock www nvidia com CUDA C Programming Guide PG 0282
73. locality As mentioned in Compute Capability 2 x and Compute Capability 3 x for devices of compute capability 2 x and 3 x the same on chip memory is used for both L1 and shared memory and how much of it is dedicated to L1 versus shared memory is configurable for each kernel call The throughput of memory accesses by a kernel can vary by an order of magnitude depending on access pattern for each type of memory The next step in maximizing memory throughput is therefore to organize memory accesses as optimally as possible based on the optimal memory access patterns described in Device Memory Accesses This optimization is especially important for global memory accesses as global memory bandwidth is low so non optimal global memory accesses have a higher impact on performance 5 3 1 Data Transfer between Host and Device Applications should strive to minimize data transfer between the host and the device One way to accomplish this is to move more code from the host to the device even if that means running kernels with low parallelism computations Intermediate data structures may be created in device memory operated on by the device and destroyed without ever being mapped by the host or copied to host memory Also because of the overhead associated with each transfer batching many small transfers into a single large transfer always performs better than making each transfer separately On systems with a front side bus higher performance
74. may perform synchronization on the grids launched by that thread by other threads in the thread block or on streams created within the same thread block Execution of a thread block is not considered complete until all launches by all threads in the block have completed If all threads in a block exit before all child launches have completed a synchronization operation will automatically be triggered C 2 1 4 Streams and Events CUDA Streams and Events allow control over dependencies between grid launches grids launched into the same stream execute in order and events may be used to create dependencies between streams Streams and events created on the device serve this exact same purpose www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 142 CUDA Dynamic Parallelism Streams and events created within a grid exist within thread block scope but have undefined behavior when used outside of the thread block where they were created As described above all work launched by a thread block is implicitly synchronized when the block exits work launched into streams is included in this with all dependencies resolved appropriately The behavior of operations on a stream that has been modified outside of thread block scope is undefined Streams and events created on the host have undefined behavior when used within any kernel just as streams and events created by a parent grid have undefined behavior if used within a child grid C
75. must be marked either with host or host device annotation or it should have no explicit execution space annotation in which case it is equivalent to having an implicit host annotation The enclosing function www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 191 C C Language Support must be named and its address can be taken If the enclosing function is a class member then the following conditions must be satisfied gt All classes enclosing the member function must have a name gt The member function must not have private or protected access within its parent class gt All enclosing classes must not have private or protected access within their respective parent classes Example Error defined outside function curo Jem ncc I etr OE device void other void UB roOrcNenelosndgestunctiteng scit host or host device function ewro lem Ceywice racon OF Ie void foo void ROR seo llemil cewice meeumm O OK ame Jew Jj cewices Y estes Op Lg auto outer Error enclosing function operator is a class member of an unnamed class anee lems ceviee iem OF fe auto outer Error enclosing function operator is a class member of an unnamed class aie llemS cewice neuen We ig Io snexewwene Sub ws oq SL cE wesbeb d Error cannot take address of enclosing function eee demad
76. n toR a S eRE LOREXSEC OE Nu DRRESUURENNIDERKKUD E AE ET 119 B 12 1 3 atomicExcl iie ee reeo bee rer bra e teet niet Ey one eme nile e poe ec ee RU EIQUE ER DR KO TER ER 119 B 12 1 4 atomlcMin si ooi oer n e I Lo E e E Ye pret Pes so Eve sOPPTS Coupes TERES Y 119 D 12 1 5 atomicMaX seasick vodka sm ex See ced SE Ren ena Co E NO URE PUO o cies E ORNARE 119 NS rom were 120 B 12 1 7 atomlcDec ois eco o yan rt dase rette UPC RI y es aU ERE EE us PRPKSQE EET CPUS eters 120 B 12 1 8 atomicCAS iocos eret rok tes Exe ka 2 RR DRE CEA E EP EREES OE METERS ES SRRR FARA A E RE 120 B 12 2 BitWise Functions isses sorte bte rra rore e EP E ORE E geese re ERE ERR P ETE LEE E 120 B 12 2 1 atomicAnd eiie erre typ ohh e ane ve a GES ous Pure eal TR kr e e E a rares eye Er 120 B 12 2 2 atomlcOF eecercesvae e ees eo Ree eode dee ra aeree n ruo re eere T edF EN EE E EE HR ELE RR 121 B 12 2 3 atomlCcXOF ii oeseret rete o resureput terrae Fes b Debes uus a euer Eme v id Ra s ge Ub EUREREE 121 B 13 Warp Vote FUNCTIONS ss x lt icsesiandacsisinmicsnnsinade EERE DECRE REM OE ERE S EO ia 121 B 14 Warp Shuffle FUNCTIONS oes eret eo tenere e deans xR ERR neues owned wedGiedun EFE houses ce dro 122 MEPUMESI IURE 122 B 14 2 DescriptlOni cii eese eek eoa cook ope se en ener x PER PEE x re ESEE BAERE ERRANETAN 122 B 14 3 Return Value oerte ree rere y votre V ves ov esee hb gs eb ivRi D VC re TY EY er Der eeYd 123 ME rA RET 12
77. ne tonne nhe nx ra rra E erER ses kb e RN Ea YR 33 3 2 5 5 Streams capes eo oorpore nr IRR seEREF e URFFSLERFe IRAK M ERFREVERESSERE SURE ETREF VUA 33 3 2 5 6 EVEnlts iios cese ke e eu ee Eae eR ERES VR EE QNRSRRRRRSRRRRUEARRESKRTM SERI SUE detector ERO TE PS 37 3 2 0 7 Synchronous Calls eret pne oett nere teret etr au te Ree ope bra ra Dui 37 3 2 6 Multi Device System ceseeesseeeeeeeeeeeeeee eene he heh te OEE sns sesso HE esee esee hann 38 3 2 6 1 Device Enumeration iiie icis hene nhe eara e Ran a aae aane 38 3 2 6 2 Device Selection eese eret sunsets sides en alere RE e ERR a SERE TREE E FEREER EVI a peE 38 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 iii 3 2 6 3 Stream and Event Behaviol cccccccceceecesceccecccccccececeeeeucccececeseseucues 38 3 2 6 4 Peer to Peer Memory ACCESS ieee eere eere penne ern ah rn esa e Pues epa EKS s pae a 39 3 2 6 5 Peer to Peer Memory COPY sc sesccsssscsensscsnmaccensdecansceenneedemsaeseneedeamsesensns 39 3 2 7 Unified Virtual Address Space esses eene eee ee eene 40 3 2 8 Interprocess Communication ceesseeeesseeesseseeeee e eee enhn ehe e ehe enne 41 M MESidasysanpBeem c 41 32 10 Call Stack eee eti eh nex teen eat lese E ERR ER EUER ESSERE ENT MESE ad 42 3 2 11 Texture and Surface Memory eessesseeeeeeeesee eene enne enne hne rese tees nnne 42 3 2 11 1 Texture Memory eei ettet nte cusdushees eee Rak s
78. occur and the thread s last error will be set to cudaErrorLaunchPendingCountExceeded The default pending launch count is 2048 launches www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 158 CUDA Dynamic Parallelism C 4 3 1 5 Memory Allocation and Lifetime cudaMalloc and cudaFree have distinct semantics between the host and device environments When invoked from the host cudaMalloc allocates a new region from unused device memory When invoked from the device runtime these functions map to device side malloc and free This implies that within the device environment the total allocatable memory is limited to the device malloc heap size which may be smaller than the available unused device memory Also it is an error to invoke cudaFree from the host program on a pointer which was allocated by cudaMalloc on the device or vice versa e cudaMalloc on Host cudaMalloc on Device cudaFree on Device Not Supported Supported C 4 3 1 6 SM Id and Warp Id Note that in PTX smid and warpid are defined as volatile values The device runtime may reschedule thread blocks onto different SMs in order to more efficiently manage resources As such it is unsafe to rely upon smid or warpid remaining unchanged across the lifetime of a thread or thread block C 4 3 1 7 ECC Errors No notification of ECC errors is available to code within a CUDA kernel ECC errors are reported at the host side once the
79. of the API relative to the version available from the host Table 5 Supported API Functions cudaDeviceSynchronize Synchronizes on work launched from thread s own block only cudaGetLastError Last error is per thread state not per block state www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 151 CUDA Dynamic Parallelism Paneme ai Funcions Beas r LL e T e T from host eese OS C e I e CdS Notes about all memcpy memset functions Only async memcpy set functions are supported Only device to device memcpy is permitted cudaMemsetAsync May not pass in local or shared memory pointers May not call cudaFree on the device on a pointer created on the host and vice versa seisoscipencpiactiveslockenenwitiprosspees eeanoccopanoyinmotenciaimosie mamoecsesesesmetenise Meer mes CS C 3 2 Device side Launch from PTX This section is for the programming language and compiler implementers who target Parallel Thread Execution PTX and plan to support Dynamic Parallelism in their language It provides the low level details related to supporting kernel launches at the PTX level C 3 2 1 Kernel Launch APIs Device side kernel launches can be implemented using the following two APIs accessible from PTX cudaLaunchDevice and cudaGetParameterBuffer cudaLaunchDevice launches the specified kernel with the parameter buffer that is obtained by calling cudaGetParameterBuffer and filled with the p
80. other CUDA call is performed by the host thread www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 37 Programming Interface 3 2 6 Multi Device System 3 2 6 1 Device Enumeration A host system can have multiple devices The following code sample shows how to enumerate these devices query their properties and determine the number of CUDA enabled devices int deviceCount cudaGetDeviceCount amp deviceCount int device Etoj devilces S0 Eclewiceesedevileetcoumuibssclewelee me cudaDeviceProp deviceProp cudaGetDeviceProperties amp deviceProp device printf Device d has compute capability d d n device deviceProp major deviceProp minor 3 2 6 2 Device Selection A host thread can set the device it operates on at any time by calling cudaSetDevice Device memory allocations and kernel launches are made on the currently set device streams and events are created in association with the currently set device If no call to cudaSetDevice is made the current device is device 0 The following code sample illustrates how setting the current device affects memory allocation and kernel execution gize t Size 1024 giver QsdhoreuE p cudaSetDevice 0 ES device Ovals current sloges 190p cudaMalloc amp p0 size Allocate memory on device 0 MyKernel 1000 128 gt gt gt p0 Launch kernel on device 0 cudaSetDevice 1 mM Siue velessalrers MaS IeXbUEXE STONE io
81. per thread 512 KB Constant memory size 64 KB Cache working set per multiprocessor 10 KB for constant memory Cache working set per multiprocessor 12 KB Between 12 KB and 48 KB for texture memory Maximum width for a 1D texture 65536 reference bound to a CUDA array Maximum width for a 1D texture 327 reference bound to linear memory Maximum width and number of layers 16384 x 2048 for a 1D layered texture reference Maximum width and height for a 2D texture reference bound to a CUDA 65536 x 65535 array Maximum width and height for a 2D texture reference bound to linear 65000 x 65000 memory Maximum width and height for a 2D texture reference bound to a CUDA 16384 x 16384 array supporting texture gather Maximum width height and number of layers for a 2D layered texture 16384 x 16384 x 2048 reference www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 206 Compute Capabilities Compute Capability echnical Specifications 2x 38 32 35 27 9 52 sa Maximum width height and depth for a 3D texture reference bound to a 4096 x 4096 x 4096 CUDA array Maximum width and height for a 16384 cubemap texture reference Maximum width and height and number of layers for a cubemap 16384 x 2046 layered texture reference Maximum number of textures that can Maximum width for a 1D surface 65536 reference bound to a CUDA array Maximum width and number of layers 65536 x 2048 for a 1D layered surface referenc
82. pointers need to be aligned to the type they point to so the following code for example does not work since array is not aligned to 4 bytes exter mS Mics Cir Oat aera NIE sevice void eune device or global function short array Ge dlxoveupssy eeneseces0 L1L2 q I short array0 lose gucci Alignment requirements for the built in vector types are listed in Table 3 B 2 4 managed The managed qualifier optionally used together with device declaresa variable that gt Can be referenced from both device and host code e g its address can be taken or it can be read or written directly from a device or host function gt Has the lifetime of an application See managed Qualifier for more details B 2 5 restrict nvcc supports restricted pointers via the restrict keyword Restricted pointers were introduced in C99 to alleviate the aliasing problem that exists in C type languages and which inhibits all kind of optimization from code re ordering to common sub expression elimination Here is an example subject to the aliasing issue where use of restricted pointer can help the compiler to reduce the number of instructions void foo const float a conse EOM tloat c ClO ES TOR ME TROIS ep e eoe iolOle el2 e en sop allie CIE alO allile elal Cat OR b0 l 0l In C type languages the pointers a b and c may be aliased so any write through c could modify e
83. pool and a virtualized pool with lower performance The device runtime system software will try to track launch data in the fixed size pool first The virtualized pool will be used to track new launches when the fixed size pool is full The size of the fixed size launch pool is configurable by calling cudaDeviceSetLimit from the host and specifying cudaLimitDevRuntimePendingLaunchCount C 4 3 1 4 Configuration Options Resource allocation for the device runtime system software is controlled via the cudaDeviceSetLimit API from the host program Limits must be set before any kernel is launched and may not be changed while the GPU is actively running programs The following named limits may be set cudaLimitDevRuntimeSyncDepth Sets the maximum depth at which cudaDeviceSynchronize may be called Launches may be performed deeper than this but explicit synchronization deeper than this limit will return the cudaErrorLaunchMaxDepthExceeded The default maximum sync depth is 2 cudaLimitDevRuntimePendingLaunchCount Controls the amount of memory set aside for buffering kernel launches which have not yet begun to execute due either to unresolved dependencies or lack of execution resources When the buffer is full the device runtime system software will attempt to track new pending launches in a lower performance virtualized buffer If the virtualized buffer is also full i e when all available heap space is consumed launches will not
84. recommended Applications can also parameterize execution configurations based on register file size and shared memory size which depends on the compute capability of the device as well as on the number of multiprocessors and memory bandwidth of the device all of which can be queried using the runtime see reference manual The number of threads per block should be chosen as a multiple of the warp size to avoid wasting computing resources with under populated warps as much as possible 5 2 3 1 Occupancy Calculator Several API functions exist to assist programmers in choosing thread block size based on register and shared memory requirements gt The occupancy calculator API cudaOccupancyMaxActiveBlocksPerMultiprocessor can provide an occupancy prediction based on the block size and shared memory usage of a kernel This function reports occupancy in terms of the number of concurrent thread blocks per multiprocessor gt Note that this value can be converted to other metrics Multiplying by the number of warps per block yields the number of concurrent warps per multiprocessor further dividing concurrent warps by max warps per multiprocessor gives the occupancy as a percentage gt The occupancy based launch configurator APIs cudaOccupancyMaxPotentialBlockSize and cudaOccupancyMaxPotentialBlockSizeVariableSMen heuristically calculate an execution configuration that achieves the maximum multiprocessor level occupancy www nvidi
85. rennen 90 Betis AOVICC TE 90 B 1 2 Global ose ee hw scene es bases ER ONE EN de Fenein S DRPRe UE PerES 90 CENE Mo RP EE EEEE E EEE E OR A EARE EET 90 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 iv B 2 Variable Type Qualifiers 1er erret rere coe eee voa deeds AREAS 91 Bole device 4 uei evece vitis wes a n eivet bie vi ssa D AbUU a RI 91 B 2 2 constant iocis eee eere erexit o gae exe aan eee orna e Sis ERE rie RES Ex vausenanied oe RAE 92 B 2 3 Shared 1 rr Ete tare E SERRE ca esee EIN NE ERE T RU Ce Rer CUT 92 B 2 4 managed 4 cente ern e aee E o E acere oe ree TE e ea pee VE o EE e eT RERO 93 LS PEE pe dA 93 B 3 Built in Vector Types doeuic voies visse vereee nte vu Ere VANE EAEE vau Du devi vases 94 B 3 1 char short int long longlong float double eese 94 NCBI ke 95 BAe Built in Variables vie oreet eee rtu ey e rv ou DUE PY SER ess ble Ye gear bien Yet UYvse 96 E MEI 96 S yl DIGCKIOX dece TTC 96 Bi 423 DIOCKD IM e t 96 B 4 4 tlireadldX 3 suono vus oo s URS A SANAE AAIE sue dAs UMORE Dr IUS 96 E MP Cy Hm 96 B 5 Memory Fence Functions eeeeeeesseeeeseeseese eee hehehe e ese enne enne 96 B 6 Synchronization FUNCtIONS cece cece ee ence eee ee esee enhn hn he eh esse nennen 99 B 7 Mathematical FUNCtiONS cccccee eee c ence eee nee esee pE hes
86. runtime API are included automatically during program compilation There is no need to include cuda_device_runtime_api h explicitly www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 154 CUDA Dynamic Parallelism C 3 3 2 Compiling and Linking CUDA programs are automatically linked with the host runtime library when compiled with nvcc but the device runtime is shipped as a static library which must explicitly be linked with a program which wishes to use it The device runtime is offered as a static library cudadevrt 1ib on Windows libcudadevrt a under Linux and MacOS against which a GPU application that uses the device runtime must be linked Linking of device libraries can be accomplished through nvcc and or nvlink Two simple examples are shown below A device runtime program may be compiled and linked in a single step if all required source files can be specified from the command line PEnvecatchzsmaoomBdesthucemuelillemwosidgcU 0 nello lercecev t It is also possible to compile CUDA cu source files first to object files and then link these together in a two stage process nvcc arch sm_35 dc hello world cu o hello world o DECC Mame smog oec ets eet vorid 0 SII Maire elerelieerste Please see the Using Separate Compilation section of The CUDA Driver Compiler NVCC guide for more details C 4 Programming Guidelines C 4 1 Basics The device runtime is a functional subset of the host runtime API leve
87. same parameters as tex2D plus an additional comp parameter equal to 0 1 2 or 3 see tex2Dgather and tex2Dgather It returns four 32 bit numbers that correspond to the value of the component comp of each of the four texels that would have been used for bilinear filtering during a regular texture fetch For example if these texels are of values 253 20 31 255 250 25 29 254 249 16 37 253 251 22 30 250 and comp is 2 tex2Dgather returns 31 29 37 30 Texture gather is only supported for CUDA arrays created with the cudaArrayTextureGather flag and of width and height less than the maximum specified in Table 13 for texture gather which is smaller than for regular texture fetch www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 51 Programming Interface Texture gather is only supported on devices of compute capability 2 0 and higher 3 2 11 2 Surface Memory For devices of compute capability 2 0 and higher a CUDA array described in Cubemap Surfaces created with the cudaArraySurfaceLoadStore flag can be read and written via a surface object or surface reference using the functions described in Surface Functions Table 13 lists the maximum surface width height and depth depending on the compute capability of the device 3 2 11 2 1 Surface Object API A surface object is created using cudaCreateSurfaceObject from a resource description of type struct cudaResourceDesc www nvidia co
88. synchronize appropriately to ensure the operation has completed before accessing any associated data from the CPU J 2 3 Language Integration Users of the CUDA Runtime API who compile their host code using nvcc have access to additional language integration features such as shared symbol names and inline kernel launch via the lt lt lt gt gt gt operator Unified Memory adds one additional element to www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 243 Unified Memory Programming CUDA s language integration variables annotated with the managed keyword can be referenced directly from both host and device code The following example seen earlier in Simplifying GPU Programming illustrates a simple use of managed global declarations Managed variable declaration is an extra annotation with device _ devices _ meneg CES globel voici karoe i Reference x directly it s a normal variable on the GPU printf GPU sees x d n x int main Set x from Host code Note it s just a normal variable on the CPU x 1234 Launch a kernel which uses x from the GPU Kemngil lt lt lt i db EE cudaDeviceSynchronize return 0 The new capability introduced with managed variables is that the symbol is available in both device code and in host code without the need to dereference a pointer and the data is shared by all This makes it particularly easy to exchange data
89. system nothing about who can see y The system therefore conservatively assumes that kernel might access it and prevents the CPU from doing so J 2 2 5 Stream Attach With Multithreaded Host Programs The primary use for cudaStreamAttachMemAsync is to enable independent task parallelism using CPU threads Typically in such a program a CPU thread creates its own stream for all work that it generates because using CUDA s NULL stream would cause dependencies between threads www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 241 Unified Memory Programming The default global visibility of managed data to any GPU stream can make it difficult to avoid interactions between CPU threads in a multi threaded program Function cudaStreamAttachMemAsync is therefore used to associate a thread s managed allocations with that thread s own stream and the association is typically not changed for the life of the thread Such a program would simply add a single call to cudaStreamAttachMemAsync to use unified memory for its data accesses This function performs some task in its own private stream huexbel iii else eue alin ime SOWIE E d Create a stream for us to use cudaStream t stream cudaStreamCreate amp amp stream Allocate some managed data and associate with our stream Note the use of the host attach flag to cudaMallocManaged we then associate the allocation with our stream so that ou
90. the indices is invalid only the devices whose index precedes the invalid index are visible to CUDA applications For example setting CUDA VISIBLE DEVICES to 2 1 causes device 0 to be invisible and device 2 to be enumerated before device 1 Setting CUDA VISIBLE DEVICES to 0 2 1 1 causes devices 0 and 2 to be visible and device 1 to be invisible CUDA MANAGED O or 1 default Forces the driver to place all managed FORCE DEVICE ALLOC is 0 allocations in device memory CUDA DEVICE ORDER FASTEST FIRST FASTEST FIRST causes CUDA to guess PCI BUS ID which device is fastest using a simple www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 229 CUDA Environment Variables Compilation CUDA_CACHE_DISABLE CUDA_CACHE_PATH CUDA_CACHE_MAXSIZE CUDA_FORCE_PTX_JIT Execution CUDA_LAUNCH_ BLOCKING CUDA_DEVICE_MAX_ CONNECTIONS CUDA_AUTO_BOOST www nvidia com CUDA C Programming Guide default is FASTEST_FIRST O or 1 default is 0 filepath heuristic and make that device 0 leaving the order of the rest of the devices unspecified PCI BUS ID orders devices by PCI bus ID in ascending order Disables caching when set to 1 or enables caching when set to 0 for just in time compilation When disabled no binary code is added to or retrieved from the cache Specifies the folder where the just in time compiler caches binary codes the default values are gt on Windows SAPPDATASNNVIDIA Com
91. three operations are performed in one atomic transaction The function returns old B 12 1 3 atomicExch int atomicExch int address int val unsigned int atomicExch unsigned int address unsigned int val unsigned long long int atomicExch unsigned long long int address unsigned long long int val float atomicExch float address float val reads the 32 bit or 64 bit word old located at the address address in global or shared memory and stores val back to memory at the same address These two operations are performed in one atomic transaction The function returns old B 12 1 4 atomicMin int atomicMin int address int val unsigned int atomicMin unsigned int address unsigned int val unsigned long long int atomicMin unsigned long long int address unsigned long long int val reads the 32 bit or 64 bit word old located at the address address in global or shared memory computes the minimum of old and val and stores the result back to memory at the same address These three operations are performed in one atomic transaction The function returns old The 64 bit version of atomicMin is only supported by devices of compute capability 3 5 and higher B 12 1 5 atomicMax int atomicMax int address int val unsigned int atomicMax unsigned Int address unsigned int val unsigned long long int atomicMax unsigned long long int address unsigned long long int val reads the 32 bit or 64 bit
92. to 0 if not J 2 5 Advanced Topics J 2 5 1 Managed Memory with Multi GPU Programs Managed allocations are automatically visible to all GPUs in a system via the peer to peer capabilities of the GPUs If peer mappings are not available for example between GPUs of different architectures then the system will fall back to using zero copy memory in order to guarantee data visibility This fallback happens automatically regardless of whether both GPUs are actually used by a program If only one GPU is actually going to be used it is necessary to set the CUDA VISIBLE DEVICES environment variable before launching the program This constrains which GPUs are visible and allows managed memory to be allocated in GPU memory On a system with more than two GPUS so long as peer mapping is supported between all visible GPUs managed allocations will not fall back to zero copy memory Alternatively users can also set CUDA MANAGED FORCE DEVICE ALLOC to a non zero value to force the driver to always use device memory for physical storage When this environment variable is set to a non zero value all devices used in that process that support managed memory have to be peer to peer compatible with each other The error cudaErrorInvalidDevice will be returned if a device that supports managed memory is used and it is not peer to peer compatible with any of the other managed memory supporting devices that were previously used in that process even if
93. using the device runtime All kernels may read or write device variables whether the kernel was initially launched by the host or device runtime Equivalently all kernels will have the same view of constant sas declared at the module scope C 3 1 6 2 Textures amp Surfaces CUDA supports dynamically created texture and surface objects where a texture reference may be created on the host passed to a kernel used by that kernel and then destroyed from the host The device runtime does not allow creation or destruction of texture or surface objects from within device code but texture and surface objects created from the host may be used and passed around freely on the device Regardless of where they are created dynamically created texture objects are always valid and may be passed to child kernels from a parent The device runtime does not support legacy module scope i e Fermi style textures and surfaces within a kernel launched from the device Module scope legacy textures may be created from the host and used in device code as for any kernel but may only be used by a top level kernel i e the one which is launched from the host C 3 1 6 3 Shared Memory Variable Declarations In CUDA C C shared memory can be declared either as a statically sized file scope or function scoped variable or as an extern variable with the size determined at runtime by the kernel s caller via a launch configuration argument Both types of declar
94. via a CUDA debugger cuda gdb Nsight or an unspecified launch error otherwise 3 2 11 Texture and Surface Memory CUDA supports a subset of the texturing hardware that the GPU uses for graphics to access texture and surface memory Reading data from texture or surface memory instead of global memory can have several performance benefits as described in Device Memory Accesses There are two different APIs to access texture and surface memory gt The texture reference API that is supported on all devices gt The texture object API that is only supported on devices of compute capability 3 x The texture reference API has limitations that the texture object API does not have They are mentioned in Texture Reference API 3 2 11 1 Texture Memory Texture memory is read from kernels using the device functions described in Texture Functions The process of reading a texture calling one of these functions is called a texture fetch Each texture fetch specifies a parameter called a texture object for the texture object API or a texture reference for the texture reference API The texture object or the texture reference specifies gt The texture which is the piece of texture memory that is fetched Texture objects are created at runtime and the texture is specified when creating the texture object as described in Texture Object API Texture references are created at compile time and the texture is specified at runtime by bounding the te
95. will be inherited from the parent That is to say if when the parent is launched execution is configured globally for 16k of shared memory and 48k of L1 cache then the child s execution state will be configured identically Likewise device limits such as stack size will remain as configured For host launched kernels per kernel configurations set from the host will take precedence over the global setting These configurations will be used when the kernel is launched from the device as well It is not possible to reconfigure a kernel s environment from the device C 3 1 1 3 Launch from host device Functions Although the device runtime enables kernel launches from either the host or device kernel launches from host device functions are unsupported The compiler will fail to compileifa host device function is used to launch a kernel C 3 1 2 Streams Both named and unnamed NULL streams are available from the device runtime Named streams may be used by any thread within a thread block but stream handles may not be passed to other blocks or child parent kernels In other words a stream should be treated as private to the block in which it is created Stream handles are not guaranteed to be unique between blocks so using a stream handle within a block that did not allocate it will result in undefined behavior Similar to host side launch work launched into separate streams may run concurrently but actual concurrency is not guarantee
96. within the same 64 bit word even though the addresses of the two sub words fall in the same bank In that case for read accesses the 64 bit word is broadcast to the requesting threads and for write accesses each sub word is written by only one of the threads which thread performs the write is undefined In this mode the same access pattern generates fewer bank conflicts than on devices of compute capability 2 x for 64 bit accesses and as many or fewer for 32 bit accesses 32 Bit Mode Successive 32 bit words map to successive banks A shared memory request for a warp does not generate a bank conflict between two threads that access any sub word within the same 32 bit word or within two 32 bit words whose indices i and j are in the same 64 word aligned segment i e a segment whose first index is a multiple of 64 and such that j i 32 even though the addresses of the two sub words fall in the same bank In that case for read accesses the 32 bit words are broadcast to the requesting threads and for write accesses each sub word is written by only one of the threads which thread performs the write is undefined In this mode the same access pattern generates as many or fewer bank conflicts than on devices of compute capability 2 x G 5 Compute Capability 5 x G 5 1 Architecture A multiprocessor consists of gt 128 CUDA cores for arithmetic operations see Arithmetic Instructions for throughputs of arithmetic operations gt
97. www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 212 Compute Capabilities There is an L1 cache for each multiprocessor and an L2 cache shared by all multiprocessors The L1 cache is used to cache accesses to local memory including temporary register spills The L2 cache is used to cache accesses to local and global memory The cache behavior e g whether reads are cached in both L1 and L2 or in L2 only can be partially configured on a per access basis using modifiers to the load or store instruction Some devices of compute capability 3 5 and devices of compute capability 3 7 allow opt in to caching of global memory in both L1 and L2 via compiler options The same on chip memory is used for both L1 and shared memory It can be configured as 48 KB of shared memory and 16 KB of L1 cache or as 16 KB of shared memory and 48 KB of L1 cache or as 32 KB of shared memory and 32 KB of L1 cache using cudaFuncSetCacheConfig cuFuncSetCacheConfig MET NSE ode global void MyKernel 1 Host code Runtime API cudaFuncCachePreferShared shared memory is 48 KB cudaFuncCachePreferEqual shared memory is 32 KB cudaFuncCachePreferLl shared memory is 16 KB cudaFuncCachePreferNone no preference cudaFuncSetCacheConfig MyKernel cudaFuncCachePreferShared The default cache configuration is prefer none meaning no preference If a kernel is configured to have no preference then it will default to the
98. y is equal to x rounded up to the nearest multiple of y The total number of registers and total amount of shared memory allocated for a block are documented in the CUDA Occupancy Calculator provided in the CUDA Toolkit www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 71 Chapter 5 PERFORMANCE GUIDELINES 5 1 Overall Performance Optimization Strategies Performance optimization revolves around three basic strategies gt Maximize parallel execution to achieve maximum utilization Optimize memory usage to achieve maximum memory throughput gt Optimize instruction usage to achieve maximum instruction throughput Which strategies will yield the best performance gain for a particular portion of an application depends on the performance limiters for that portion optimizing instruction usage of a kernel that is mostly limited by memory accesses will not yield any significant performance gain for example Optimization efforts should therefore be constantly directed by measuring and monitoring the performance limiters for example using the CUDA profiler Also comparing the floating point operation throughput or memory throughput whichever makes more sense of a particular kernel to the corresponding peak theoretical throughput of the device indicates how much room for improvement there is for the kernel 5 2 Maximize Utilization To maximize utilization the application should be structured in a way that it exposes a
99. 11 flag turns on all C 11 features and also invokes the host preprocessor compiler and linker with the corresponding C 11 dialect option 10 At present the std c 11 flag is supported only for the following host compilers gcc version gt 4 7 clang www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 183 C C Language Support E 2 14 1 Lambda Expressions The execution space qualifiers for all member functions of the closure class associated with a lambda expression are derived by the compiler as follows As described in the C 11 standard the compiler creates a closure type in the smallest block scope class scope or namespace scope that contains the lambda expression The innermost function scope enclosing the closure type is computed and the corresponding function s execution space qualifiers are assigned to the closure class member functions If there is no enclosing function scope the execution space qualifier is host Examples of lambda expressions and computed execution space qualifiers are shown below in comments cuco ghelgsubWeue Dp 4 ssexewese Op fe woe o vordi Fiord auto 11 return 1p WA T NN bost device ou Met 24 rene NE auto 12 cocca p J7 device _ nose _ Ceyiga void ES oe MET auco 13 Tecur Se je Hf host device cevics voie ee so 0 Li retener p fee ETC ET global void f5 void auco IS Dy d sein Se hy fi Gew os
100. 171 E 2 Restrictlons s ses erras epe obe aet ete ba bie oi etx rates tuas eie ep pacis DUREE EAER 174 E 2 1 Host Compiler Extensions cree re oet re nnne a enr I rege tx x ah eiii 174 E 2 2 Preprocessor Symbols 4 spoenen eE a E a exa a vna Eye Eee Ea ha E Pane n 174 E 2 2 dese CU DASARCH cessccnsetecanssnsnind coscieuwatatcicuinn cx D Uv aex Se edad Mri e do ee ENEE OSS 174 E 2 3 Qualifiets o oorr kae oss aeso eos re diu chute csv vU Um RUP Paesi niin Cr Vekle vex 176 E 2 3 1 Device Memory Qualifiers eccesessseeeeseeeeeeee e eene enne 176 E 2 3 2 managed Qualifier cceecseseeseeeeeeeeeee eee eene enhn ehe 177 E 2 3 3 Volatile O alifier eter resti wed Decree ease a epe o ve ado eee 178 n cEhnicfthw e e ERSE 179 PEG gio xcs vassccanscarnmsadeuecedsescaseueas EEEE EA SAEN sais sehgaselnanicn egies 179 E 2 5 1 Assignment Operator o eee cessive ee eet e nace roa gia veins Qe ea eipesuigeistve alge ev atyieee aes 179 E 2 5 2 Address Operator c essc isie tree oam ee Rs On Rim RR Pn OE KNEE E ESSE SERATA AREE RUE 179 E 2 6 Run Time Type Information RTTI cesses I II nemen nnne 179 E 2 7 Exception Handling 15 cocco reete Rer eer e rhe pa Ree RR ee thes e ERR ee Ere 179 E 2 8 Standard Libra isrener eese ke see eee eet eo npe 4e CERTE ES ree UR WR bEE Oe ES CEP dene diee 179 y MEI secon 180 E 2 9 1 External Li
101. 1_v7 5 221 Driver API separately into PTX or binary objects Kernels are launched using API entry points as described in Kernel Execution Any application that wants to run on future device architectures must load PTX not binary code This is because binary code is architecture specific and therefore incompatible with future architectures whereas PTX code is compiled to binary code at load time by the device driver www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 222 Driver API Here is the host code of the sample from Kernels written using the driver API int main abahe IN aR alze Size IN Simeois Celloeic p Allocate input vectors h A and h B in host memory illom In JA i loeic mellow sae illom n Gi logic mellow sae Initialize input vectors Initialize ewuha Oe Get number of devices supporting CUDA int deviceCount 0 cuDeviceGetCount amp deviceCount if deviceCount 0 printf There is no device supporting CUDA n exit 0 Get handle for device 0 CUdevice cuDevice cuDeviceGet amp cuDevice 0 Ur erogate Ob o CUcontext cuContext cuCtxCreate amp cuContext 0 cuDevice Create module from binary file CUmodule cuModule uModuleLoad amp cuModule VecAdd ptx Q Allocate vectors in device memory Udeviceptr d A uMemAlloc amp d A size Udeviceptr d B uMemAlloc amp d B size udev cept
102. 24 are legacy intrinsic functions that have no longer any reason to be used www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 86 Performance Guidelines Type Conversion Sometimes the compiler must insert conversion instructions introducing additional execution cycles This is the case for gt Functions operating on variables of type char or short whose operands generally need to be converted to int gt Double precision floating point constants i e those constants defined without any type suffix used as input to single precision floating point computations as mandated by C C standards This last case can be avoided by using single precision floating point constants defined with an f suffix such as 3 141592653589793 1 0 0 5 5 4 2 Control Flow Instructions Any flow control instruction if switch do for while can significantly impact the effective instruction throughput by causing threads of the same warp to diverge i e to follow different execution paths If this happens the different executions paths have to be serialized increasing the total number of instructions executed for this warp When all the different execution paths have completed the threads converge back to the same execution path To obtain best performance in cases where the control flow depends on the thread ID the controlling condition should be written so as to minimize the number of divergent warps This is possible bec
103. 4 B 14 5 EXambpl S 2 ecce t oen eoe a voe eeu veda wis eue oeba ev messuw sense mo cceudest aet oet Puede meses 124 B 14 5 1 Broadcast of a single value across a warp eeeeeeeeeree nenne 124 B 14 5 2 Inclusive plus scan across sub partitions of 8 threads uusuus 125 B 14 5 3 Reduction across a warp eeseseeseeeeeee ee eene ehe enhn enhn eren 125 B 15 Profiler Counter Function vvee ou etr rero voee o ene Vere Ei p Y Pe e TY vyeex Pise Y TRE Ye 126 B 16 ASSert1On iioi serere nox ey uR S HE ERRERENFADS DRENERE ERR FRE EE E RRRA EAS 126 B 17 Formatted OUtDUt iiio onis Ent eo oro OO aeo E oc meE eds e unte d edax aet DER RERBA EFE 127 B 17 1 Format Specifiers ii eee reso ere Eten e aa Eee Pere a paa a iER e CER E e ERES DERE 128 B 17 2 limitations ooiee eer eet xe REESE EE ERES TRES EEEREERUN SERE PENNE OON ERE MN EE a cians 128 B 17 3 Associated Host Side API ceeeeeseeeeeseeeee eene hh ehh enhn enne 129 B 17 4 Examples e eee tree eR re ERR haved eR e DEP edi e e es ERES betes PER ene 130 B 18 Dynamic Global Memory Allocation and Operations c eese 131 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 vii B 18 1 Heap Memory Allocation cccccccce cece eee eeeeeee eee hee ehe enne nennen 131 B 18 2 Interoperability with Host Memory APlI eeeseseeseeeee nee nnne 132 B 18 3 EXAMPlOS ccevtisccew hse rre s
104. 4 Compute Capability 326 iieee eret eren ehe ehe nn Fan XR Soave EET E E FERT 212 GAT Arcitecture OP 212 G42 2 Global IRR RC PP O m 214 G 4 3 Shared Memory reet sees cee ves thes epe n XE banshee ex EXPO E Ea thie e Ee ke Xx vR e SEE come 215 G5 Compute Capability 5 X 5 esce nora the epe a Pep Rea voce evt eu eor suras tis etae rk e Pear perds 216 G 5 1 AP CHILE CLUE ss oce eeto rernm gere ose elvan eben nae a ee RERO ERN ERR ES 216 G 5 2 Global Memory rero tet eer dente exu E Raga ERRREESDESESRERY OU EEE EIEEE 217 6G 5 3 Shared MEMON Seer ea netri ten Ere e xw ee eeu dote noa sae oet eu e EAE deseen aM Ne EET 217 Appendix H Driver APl eee e eere eoe ne n nnne aen nn repere one eaae eR ee pn eaa R pea unE 221 UMEN STM 224 AN r m 225 H 3 Kernel Execution opere enn Rr rer hn ove nep ERR seus viet cues es Rave tee EDES ENN EESE 226 H 4 Interoperability between Runtime and Driver APIs cceeeeceeececeeneeeenneeeeneeees 228 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 x Appendix CUDA Environment Variables ccsccccccccceccccecscccecccccescceesssceesssceeees 229 Appendix J Unified Memory ProgrammMing cccsccceccccccscccccscccesscccescccecsscesssseenes 232 J 1 Unified Memory Introduction sssessessossossossossosssssosesossoss
105. 8 otherwise LIN CNN eserves eT LN NN a B 3 2 dim3 This type is an integer vector type based on uint3 that is used to specify dimensions When defining a variable of type dim3 any component left unspecified is initialized to 1 www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 95 C Language Extensions B 4 Built in Variables Built in variables specify the grid and block dimensions and the block and thread indices They are only valid within functions that are executed on the device B 4 1 gridDim This variable is of type dim3 see dim3 and contains the dimensions of the grid B 4 2 blockldx This variable is of type uint3 see char short int long longlong float double and contains the block index within the grid B 4 3 blockDim This variable is of type dim3 see dim3 and contains the dimensions of the block B 4 4 threadldx This variable is of type uint3 see char short int long longlong float double and contains the thread index within the block B 4 5 warpSize This variable is of type int and contains the warp size in threads see SIMT Architecture for the definition of a warp B 5 Memory Fence Functions The CUDA programming model assumes a device with a weakly ordered memory model that is gt The order in which a CUDA thread writes data to shared memory global memory page locked host memory or the memory of a peer device is not necessarily the order in whi
106. 9 001 v7 5 136 C Language Extensions Optimal launch bounds for a given kernel will usually differ across major architecture revisions The sample code below shows how this is typically handled in device code using the _ CUDA_ARCH__ macro introduced in Application Compatibility define THREADS PER BLOCK 256 if _ CUDA ARCH 200 define MY KERNEL MAX THREADS 2 THREADS PER BLOCK define MY KERNEL MIN BLOCKS 3 else define MY KERNEL MAX THREADS THREADS PER BLOCK define MY KERNEL MIN BLOCKS 2 endif Device code glose vowel launch bounds MY KERNEL MAX THREADS MY KERNEL MIN BLOCKS MyKernel In the common case where MyKernel is invoked with the maximum number of threads per block specified as the first parameter of launch bounds itis tempting to use MY KERNEL MAX THREADS as the number of threads per block in the execution configuration Host code MyKernel blocksPerGrid MY KERNEL MAX THREADS gt gt gt This will not work however since CUDA ARCH isundefined in host code as mentioned in Application Compatibility so MyKernel will launch with 256 threads per block even when CUDA ARCH is greater or equal to 200 Instead the number of threads per block should be determined gt Hither at compile time using a macro that does not depend on CUDA ARCH for
107. CUDA array specified by the one dimensional surface object surfObj at coordinate x B 9 1 3 surf2Dread template lt class T gt T surf2Dread cudaSurfaceObject t surfObj SLING xxn Gun Wp boundaryMode cudaBoundaryModeTrap template class T void surf2Dread T data cudaSurfaceObject t surfObj SLIME xxn DNE Ww boundaryMode cudaBoundaryModeTrap reads the CUDA array specified by the two dimensional surface object sur 0bj using coordinates x and y B 9 1 4 surf2Dwrite template class T void surf2Dwrite T data cudaSurfaceObject t surfObj sinus xp mE Wy boundaryMode cudaBoundaryModeTrap writes value data to the CUDA array specified by the two dimensional surface object surfObj at coordinate x and y B 9 1 5 surf3Dread template class T T surf3Dread cudaSurfaceObject t surfObj IME Hp tuc wo diae PAn boundaryMode cudaBoundaryModeTrap template class T void surf3Dread T data cudaSurfaceObject t surfObj GME Hep SUUS Wp line Ap boundaryMode cudaBoundaryModeTrap reads the CUDA array specified by the three dimensional surface object surfobj using coordinates x y and z B 9 1 6 surf3Dwrite template lt class T gt void surf3Dwrite T data cudaSurfaceObject t surfObj ines nE Ws int z boundaryMode cudaBoundaryModeTrap writes value data to the CUDA array specified by the three dimensional object surfObj at coordinate x y and z www nvidia com CUDA C Programm
108. DA arrays CUDA arrays are opaque memory layouts optimized for texture fetching They are described in Texture and Surface Memory Linear memory exists on the device in a 40 bit address space so separately allocated entities can reference one another via pointers for example in a binary tree Linear memory is typically allocated using cudaMalloc and freed using cudaFree and data transfer between host memory and device memory are typically done using www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 21 Programming Interface cudaMemcpy In the vector addition code sample of Kernels the vectors need to be copied from host memory to device memory Device code glosal woulel Weel loa Ap lose 13 ileeics Cy aime N Shae ab ex lolloelaDaiil ox 5 lollo liciteb lt as lt ar iwlaiceyeclitchk lt lt p wiz a lt WN Cl Alla ar Balle Host code int main sboue Jf eos oH size size IN cebzxexeus Cloet Allocate input vectors h A and h B in host memory nloc jm A Clocc ue loe size loar In B ario mel loc sabe 2 Initialize input vectors Allocate vectors in device memory float d A cudaMalloc amp d A size raul Ro oras I cudaMalloc amp d_B size zlocie qi CP cudaMalloc amp d C size Copy vectors from host memory to device memory cudaMemcpy d A h A size cudaMemcpyHostToDevice cudaMemcpy d B h B size cudaMemcpyHostToDevice
109. EA VEVRSE E S e ees ee vane Eva E Va oe 111 B 9 1 6 surf3DWrIte eos secex onte che EREN AARRE RA EE E en DR RT Kerr DU da prd dk ne 111 B 9 1 7 surf 1DEayeredread csscvssscevievevvertevedienvetsetv steer ho nv ER PE e bb EU buen 112 B 9 1 8 surf DLayeredwrite eeeeeeseeeeeeeeeeeee een enne nnne ener 112 B 9 1 9 s rf2DLayeredread oec eret ehe hte e ehe e reete ee enne rey e eere eS 112 B 9 1 10 surf2DLayeredwrite eeeeeseeeeeeeeeee enne nennen nnne eter nnne 112 B 9 1 11 surfCubemapread circo staves ret Lux e nae e RR Nae X eo ERE TR LEY 113 B 9 1 12 surfCubemapwWrite 22 cocer eden nee eden re eto aeo see usse re eeu eret beste 113 B 9 1 13 surfCubemapLayeredread ccccee sees scene eect eee e eee eeeeeeeeeeeee sees eeeeeeeee 113 B 9 1 14 surfCubemapLayeredwrite sesssssossosssossossossossossosssesosssossossosssss 113 B 9 2 Surface Reference API iei oce reta ere cea erue DER RN REER TURN ee esee Reed 114 B 9 2 1 surf 1Dread i soe o rep to rea asker ee cdey ee TE ee Evae PEE e re quae eg 114 D 9 2 2 SUBE TDWLEILO SEEE tox Ex CURE A RIPE USE DRE Ced TD EE E RUE 114 B 9 2 3 s rf2Dread c oresoss e Crete ppt aae Ove pe e oeabe esto eese soie e Dr ERA pir soa va qud 114 EP PDT EUIS VADE EM 114 B 9 2 5 surf3Dread iecit eerte ERR n eret a Nr E Te T ORA E CAT HEENRS NA RATEREEAS TEC euer POE AS 115 www nvidia com CUDA C Programming Gu
110. Ee cuMemAlloc amp d_C size i Qr Ore Gras Copy vectors from host memory to device memory cuMemcpyHtoD d A h A size cuMemcpyHtoD d B h B size Get function handle from module CUfunction vecAdd cuModuleGetFunction amp vecAdd cuModule VecAdd Invoke kernel int threadsPerBlock 256 int blocksPerGrid N threadsPerBlock 1 threadsPerBlock vorc args el A Go jS el C EN Ie cuLaunchKernel vecAdd blocksPerGrid 1 1 threadsPerBlock 1 0p O arge 0 58 Full code can be found in the vectorAddDrv CUDA sample www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 223 Driver API H 1 Context A CUDA context is analogous to a CPU process All resources and actions performed within the driver API are encapsulated inside a CUDA context and the system automatically cleans up these resources when the context is destroyed Besides objects such as modules and texture or surface references each context has its own distinct address space As a result CUdeviceptr values from different contexts reference different memory locations A host thread may have only one device context current at a time When a context is created with cuCtxCreate it is made current to the calling host thread CUDA functions that operate in a context most functions that do not involve device enumeration or context management will return CUDA ERROR INVALID CONTEXT ifa valid context
111. Event is supported but cudaEventSynchronize cudaEventElapsedTime and cudaEventQuery are not As cudaEventElapsedTime is not supported cudaEvents must be created via cudaEventCreateWithFlags passing the cudaEventDisableTiming flag As for all device runtime objects event objects may be shared between all threads withinthe thread block which created them but are local to that block and may not be passed to other kernels or between blocks within the same kernel Event handles are not guaranteed to be unique between blocks so using an event handle within a block that did not create it will result in undefined behavior C 3 1 4 Synchronization The cudaDeviceSynchronize function will synchronize on all work launched by any thread in the thread block up to the point where cudaDeviceSynchronize was called Note that cudaDeviceSynchronize may be called from within divergent code see Block Wide Synchronization It is up to the program to perform sufficient additional inter thread synchronization for example viaacallto__ syncthreads if the calling thread is intended to synchronize with child grids invoked from other threads C 3 1 4 1 Block Wide Synchronization The cudaDeviceSynchronize function does not imply intra block synchronization In particular without explicit synchronization viaa syncthreads directive the calling thread can make no assumptions about what work has been launched by any thread ot
112. Factory uuidof IDXGIFactory void amp factory IDXGIAdapter adapter 0 for unsigned int i 0 adapter i if FAILED factory gt EnumAdapters i amp adapter break if cudaD3D11GetDevice amp dev adapter cudaSuccess break adapter gt Release factory Release Create swap chain and device sFnPtr D3D11CreateDeviceAndSwapChain adapter D3D11 DRIVER TYPE HARDWARE 0 D3D11 CREATE DEVICE DEBUG featureLevels 3 D3D11 SDK VERSION amp swapChainDesc amp swapChain amp device amp featureLevel amp deviceContext adapter gt Release Use the same devic cudaSetDevice dev Create vertex buffer and register it with CUDA unsigned int size width height sizeof CUSTOMVERTEX D3D11 BUFFER DESC bufferDesc butterbDbesc Usage D3D11 USAGE DEFAULT bufferDesc ByteWidth size bufferDesc BindFlags D3D11 BIND VERTEX BUFFER bufferDesc CPUAccessFlags 0 bufferDesc MiscFlags 0 device gt CreateBuffer amp bufferDesc 0 amp positionsVB cudaGraphicsD3D11RegisterResource amp positionsVB CUDA positionsVB cudaGraphicsRegisterFlagsNone cudaGraphicsResourceSetMapFlags positionsVB CUDA cudaGraphicsMapFlagsWriteDiscard Launch rendering loop whale naa T Render www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 64 Programming Interface void Render
113. Height blockDepth gridWidth gridHeight gridDepth Q O O GER The alignment requirement of a structure is equal to the maximum of the alignment requirements of its fields The alignment requirement of a structure that contains built in vector types CUdeviceptr or non aligned double and long long might therefore differ between device code and host code Such a structure might also be padded differently The following structure for example is not padded at all in host code but it www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 227 Driver API is padded in device code with 12 bytes after field since the alignment requirement for field 4 is 16 typedef struct Foart cr float4 4 jr HE TED H 4 Interoperability between Runtime and Driver APIs An application can mix runtime API code with driver API code If a context is created and made current via the driver API subsequent runtime calls will pick up this context instead of creating a new one If the runtime is initialized implicitly as mentioned in CUDA C Runtime cuCtxGetCurrent can be used to retrieve the context created during initialization This context can be used by subsequent driver API calls Device memory can be allocated and freed using either API CUdeviceptr can be cast to regular pointers and vice versa CUdeviceptr devPtr float d data Allocation using driver API cuMemAlloc amp devPtr size El cara Elica sprevit
114. IEEE floating point standard Sections Compute Capability 2 x Compute Capability 3 x and Compute Capability 5 x give more details on the architecture of devices of compute capability 2 x 3 x and 5 x respectively G 1 Features and Technical Specifications Table 12 Feature Support per Compute Capability Feature Support Compute Capability Unlisted features are supported for all compute capabilities Atomic functions operating on 32 bit integer values in global memory Atomic Functions atomicExch operating on 32 bit floating point values in global memory atomicExch Atomic functions operating on 32 bit integer values in shared memory Atomic Functions atomicExch operating on 32 bit floating point values in shared memory atomicExch Atomic functions operating on 64 bit integer values in global memory Atomic Functions Warp vote functions Warp Vote Functions www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 204 Compute Capabilities Feature Support Compute Capability Unlisted features are supported for all compute capabilities Double precision floating point numbers Atomic functions operating on 64 bit integer values in shared memory Atomic Functions Atomic addition operating on 32 bit floating point values in global and shared memory atomicAdd ballot Warp Vote Functions threadfence system Memory Fence Functions Syncthreads count Syncthreads and
115. K SIZE m Get sub matrix Asub of A Matrix Asub GetSubMatrix A blockRow m Get sub matrix Bsub of B Matrix Bsub GetSubMatrix B m blockCol Shared memory used to store Asub and Bsub respectively Shared float As BLOCK SIZE BLOCK SIZE Shared float Bs BLOCK SIZE BLOCK SIZE Load Asub and Bsub from device memory to shared memory Each thread loads on lement of each sub matrix As row col GetElement Asub row col Bs row col GetElement Bsub row col Synchronize to make sure the sub matrices are loaded before starting the computation __syncthreads www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 28 Programming Interface Multiply Asub and Bsub together bore ame O Op eG s EMO Size ar Cvalue As row e Bs e col Synchronize to make sure that the preceding computation is done before loading two new sub matrices of A and B in the next iteration Syncthreads Write Csub to device memory Bach thread writes one element SetElement Csub row col Cvalue blockCol blockRow Figure 10 Matrix Multiplication with Shared Memory 3 2 4 Page Locked Host Memory The runtime provides functions to allow the use of page locked also known as pinned host memory as opposed to regular pageable host memory allocated by malloc gt cudaHostAlloc and cudaFreeHost allocate and free page locked host
116. NVIDIA CUDA C PROGRAMMING GUIDE CHANGES FROM VERSION 7 0 gt Updated C C Language Support to gt Added new section C 11 Language Features gt Clarified that values of const qualified variables with builtin floating point types cannot be used directly in device code when the Microsoft compiler is used as the host compiler gt Documented the extended lambda feature gt Documented that typeid std type_info and dynamic cast are only supported in host code gt Documented the restrictions on trigraphs and digraphs gt Clarified the conditions under which layout mismatch can occur on Windows gt Updated Table 12 to mention support of half precision floating point operations on devices of compute capabilities 5 3 Updated Table 2 with throughput for half precision floating point instructions Added compute capability 5 3 to Table 13 Added the maximum number of resident grids per device to Table 13 Clarified the definition of threadfence in Memory Fence Functions Mentioned in Atomic Functions that atomic functions do not act as memory fences v vV v v yv www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 ii TABLE OF CONTENTS Chapter 1 IMtrOduCtHi OM siscsecseccdesenccssccdescdewaccinceacanmascaisies saccwacceaesaacaeddecmicacwesicnseeaas lt awta 1 1 1 From Graphics Processing to General Purpose Parallel Computing ccs sees eee eee ees 1 1 2 CUDA A General Purpose Parallel Computi
117. Of a elass leewedksCIL eg SiS vp 4 With Visual Studio 2013 host compiler the function enclosing a__ device lambda definition must have external linkage The restriction is present because this host compiler does not support using the address of non extern linkage functions as template arguments which is needed by the CUDA compiler transformations to support device lambdas 5 A device lambda has the following restrictions on captured variables Variables can only be captured by value The number of captured variables must be less than 31 Variables of array type cannot be captured A function parameter that is an element of a variadic argument pack cannot be captured gt The type of the captured variable cannot involve types that are either local to a function except for closure types for device lambdas or are private or protected class members 6 When parsing a function the CUDA compiler assigns a counter value to each device lambda within that function This counter value is used in the substituted named type passed to the host compiler Hence whether or not a device lambda is defined within a function should not depend on a particular value of _ CUDA ARCH oron CUDA ARCH being undefined v v v y www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 195 C C Language Support Example template lt typename T gt Global veic kernel QP im d caa I host device void foo void E
118. Otherwise cudaHostGetDevicePointer will return an error cudaHostGetDevicePointer also returns an error if the device does not support mapped page locked host memory Applications may query this capability by checking the canMapHostMemory device property see Device Enumeration which is equal to 1 for devices that support mapped page locked host memory Note that atomic functions see Atomic Functions operating on mapped page locked memory are not atomic from the point of view of the host or other devices 3 2 5 Asynchronous Concurrent Execution CUDA exposes the following operations as independent tasks that can operate concurrently with one another gt Computation on the host v Computation on the device Memory transfers from the host to the device Memory transfers from the device to the host Memory transfers within the memory of a given device v v v y Memory transfers among devices The level of concurrency achieved between these operations will depend on the feature set and compute capability of the device as described below www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 31 Programming Interface 3 2 5 1 Concurrent Execution between Host and Device Concurrent host execution is facilitated through asynchronous library functions that return control to the host thread before the device completes the requested task Using asynchronous calls many device operations can be queued up togeth
119. PG 02829 001 v7 5 12 Programming Model memory also offers different addressing modes as well as data filtering for some specific data formats see Texture and Surface Memory The global constant and texture memory spaces are persistent across kernel launches by the same application Thread Per thread local gt memory Per block shared memory Global memory Figure 7 Memory Hierarchy www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 13 Programming Model 2 4 Heterogeneous Programming As illustrated by Figure 8 the CUDA programming model assumes that the CUDA threads execute on a physically separate device that operates as a coprocessor to the host running the C program This is the case for example when the kernels execute on a GPU and the rest of the C program executes on a CPU The CUDA programming model also assumes that both the host and the device maintain their own separate memory spaces in DRAM referred to as host memory and device memory respectively Therefore a program manages the global constant and texture memory spaces visible to kernels through calls to the CUDA runtime described in Programming Interface This includes device memory allocation and deallocation as well as data transfer between host and device memory www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 14 Programming Model C Program Sequential Execution Serial code Parallel kernel
120. PG 02829 001_v7 5 7 Introduction gt Appendix Mathematical Functions lists the mathematical functions supported in CUDA gt Appendix C C Language Support lists the C features supported in device code gt Appendix Texture Fetching gives more details on texture fetching gt Appendix Compute Capabilities gives the technical specifications of various devices as well as more architectural details gt Appendix Driver API introduces the low level driver API gt Appendix CUDA Environment Variables lists all the CUDA environment variables www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 8 Chapter 2 PROGRAMMING MODEL This chapter introduces the main concepts behind the CUDA programming model by outlining how they are exposed in C An extensive description of CUDA C is given in Programming Interface Full code for the vector addition example used in this chapter and the next can be found in the vectorAdd CUDA sample 2 1 Kernels CUDA C extends C by allowing the programmer to define C functions called kernels that when called are executed N times in parallel by N different CUDA threads as opposed to only once like regular C functions A kernel is defined using the global declaration specifier and the number of CUDA threads that execute that kernel for a given kernel call is specified using a new lt lt lt gt gt gt execution configuration syntax see C Language Extensions Each thread t
121. U www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 2 Introduction Theoretical GB s 360 GeForce 780 Ti 330 si Oe PU Tesla K 270 e ieeGeForce GPU Tesla K20X 240 210 GeForce GTX 480 180 GeForce GTX 680 Tesla M2090 150 GeForce GTX 280 Tesla C2050 120 GeForce 8800 GTX 20 Tesla C1060 GeForce 7800 GTX Ivy Bridge 60 Sandy Bridge Bloomfield GeForce 6800 GT 30 Prescott Woodcrest GeForce FX 5 Westmere F T T T fe ood T T T T 1 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 Figure 2 Memory Bandwidth for the CPU and GPU The reason behind the discrepancy in floating point capability between the CPU and the GPU is that the GPU is specialized for compute intensive highly parallel computation exactly what graphics rendering is about and therefore designed such that more transistors are devoted to data processing rather than data caching and flow control as schematically illustrated by Figure 3 CPU GPU Figure 3 The GPU Devotes More Transistors to Data Processing www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 3 Introduction More specifically the GPU is especially well suited to address problems that can be expressed as data parallel computations the same program is executed on many data elements in parallel with high arithmetic intensity the ratio of arithmetic operations to memory ope
122. UDA 6 0 that defines a new managed memory space in which all processors see a single coherent memory image with a common address space A processor refers to any independent execution unit with a dedicated MMU This includes both CPUs and GPUs of any type and architecture The underlying system manages data access and locality within a CUDA program without need for explicit memory copy calls This benefits GPU programming in two primary ways gt GPU programming is simplified by unifying memory spaces coherently across all GPUs and CPUs in the system and by providing tighter and more straightforward language integration for CUDA programmers gt Data access speed is maximized by transparently migrating data towards the processor using it In simple terms Unified Memory eliminates the need for explicit data movement via the cudaMemcpy routines without the performance penalty incurred by placing all data into zero copy memory Data movement of course still takes place so a program s run time typically does not decrease Unified Memory instead enables the writing of simpler and more maintainable code Unified Memory offers a single pointer to data model that is conceptually similar to CUDA s zero copy memory One key difference between the two is that with zero copy allocations the physical location of memory is pinned in CPU system memory such that a program may have fast or slow access to it depending on where it is being accessed
123. UE TOG 5 template lt template lt typename gt class T typename Pl typename P2 void paciiicons t PIE o oS CONSE I lt r2 Error enclosing function has multiple parameter packs auto lemil cewies 1 ses 102 Jg template lt template lt typename gt class T typename Pl typename T2 gt void locus Comsic WP ss 5S WZ P isi a Eor ene losing rUnctLon ENE parameter pack is not last in the template parameter list gee leunl P eewsee recura 1085 fe template typename T T gt void bar3 void Error for enclosing function the second templat parameter is not named au gomom ij Gewiles eua 2085 ep int main BOOZE nea lnc Eid dll foo char int 2 loxeusdl dedo 3522 lee 2 GEIL EQ E bar3 lt int 10 gt www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 194 C C Language Support Example template lt typename T gt Global vorc lee an ia E aa eg fj template typename T gt void bar4 void ene lemt M owes emos 107 T7 kern 1 1 lam1 swerve CUL d Sseemce Sl ou dq J7 Erien ame meaim woue e Ie int main Struc Gui d 4o 9 Error enclosing function for device lambda in bar4 is instantiated with a type local to main bar4 S81 t Error enclosing function for device lambda in bar4 is instantiated with a type that is a private member Jl
124. a com CUDA C Programming Guide PG 02829 001_v7 5 75 Performance Guidelines The following code sample calculates the occupancy of MyKernel It then reports the occupancy level with the ratio between concurrent warps versus maximum warps per multiprocessor Device code glosel vonie Mystras ime cl Taw el ne Unt sd creadha a block idz block mes ell suebx alie oltek e Host code Imee Mma o atonE fenpRUSdLolRSP Occupancy in terms of active blocks int blockSize 32 These variables are used to convert occupancy to warps int device cudaDeviceProp prop int activeWarps int maxWarps cudaGetDevice amp device cudaGetDeviceProperties amp prop device cudaOccupancyMaxActiveBlocksPerMultiprocessor amp numBlocks MyKernel blockSize 0 activeWarps numBlocks blockSize prop warpSize maxWarps prop maxThreadsPerMultiProcessor prop warpSize std cout lt lt Occupancy lt lt double activeWarps maxWarps 100 lt lt lt lt std endl return 0 www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 76 Performance Guidelines The following code sample configures an occupancy based kernel launch of MyKernel according to the user input Device code globally verde My Kernel Gin barca nme amm aie UTI dne esau seh each ta plbecekidk x lodb eXel Die 5 att ich ArrayCommic 1 array idx array idx
125. amming Guide PG 02829 001_v7 5 84 Performance Guidelines Compute Capability SIMD video instructions N A N A Multiple Multiple vabsdiff4 instructions instructions All other SIMD video Multiple Eu instructions instructions Eu Type conversions from 8 bit and 16 bit integer to 32 bit types Type conversions from and to 64 bit types conversions Other instructions and functions are implemented on top of the native instructions The implementation may be different for devices of different compute capabilities and the number of native instructions after compilation may fluctuate with every compiler version For complicated functions there can be multiple code paths depending on input cuobjdump can be used to inspect a particular implementation in a cubin object The implementation of some functions are readily available on the CUDA header files math functions h device functions h In general code compiled with tz true denormalized numbers are flushed to zero tends to have higher performance than code compiled with tz false Similarly code compiled with prec div false less precise division tends to have higher performance code than code compiled with prec div true and code compiled with prec sqrt false less precise square root tends to have higher performance than code compiled with prec sqrt true The nvcc user manual describes these compilation flags in more details Single Precision Floating Point Di
126. and y and the comp parameter as described in Texture Gather Type is a 4 component vector type It is based on the base type of DataType except when readMode is equal to cudaReadModeNormalizedFloat see Texture Reference API in which case it is always float4 B 9 Surface Functions Surface functions are only supported by devices of compute capability 2 0 and higher Surface objects are described in described in Surface Object API Surface references are described in Surface Reference API In the sections below boundaryMode specifies the boundary mode that is how out of range surface coordinates are handled it is equal to either cudaBoundaryModeClamp in which case out of range coordinates are clamped to the valid range or cudaBoundaryModeZero in which case out of range reads return zero and out of range writes are ignored or cudaBoundaryModeTrap in which case out of range accesses cause the kernel execution to fail B 9 1 Surface Object API B 9 1 1 surfiDread template class T T surfliDread cudaSurfaceObject t surfObj int x boundaryMode cudaBoundaryModeTrap reads the CUDA array specified by the one dimensional surface object surfObj using coordinate x B 9 1 2 surf Dwrite template class T void surflDwrite T data cudaSurfaceObject t surfObj alim ee boundaryMode cudaBoundaryModeTrap www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 110 C Language Extensions writes value data to the
127. ar spill cudaMalloc amp pl size Allocate memory on device 1 MyKernel 1000 128 gt gt gt pl Launch kernel on device 1 3 2 6 3 Stream and Event Behavior A kernel launch will fail if it is issued to a stream that is not associated to the current device as illustrated in the following code sample cudaSetDevice 0 EEUU E cudaStream t s0 cudaStreamCreate amp s0 Create stream s0 on device 0 yKernel 100 64 0 sO gt gt gt Launch kernel on device 0 in s0 cudaSetDevice 1 jf Seb device l as Current cudaStream t sl cudaStreamCreate amp s1 Create stream sil on device 1 yKernel 100 64 0 sl gt gt gt Launch kernel on device 1 in sl This kernel launch will fail yKernel 100 64 0 sO gt gt gt Launch kernel on device 1 in s0 A memory copy will succeed even if it is issued to a stream that is not associated to the current device cudaEventRecord will fail if the input event and input stream are associated to different devices www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 38 Programming Interface cudaEventElapsedTime will fail if the two input events are associated to different devices cudaEventSynchronize and cudaEventQuery will succeed even if the input event is associated to a device that is different from the current device cudaStreamWaitEvent will succeed even if the input stream and input e
128. arameters www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 152 CUDA Dynamic Parallelism to the launched kernel The parameter buffer can be NULL i e no need to invoke cudaGetParameterBuffer if the launched kernel does not take any parameters C 3 2 1 1 cudaLaunchDevice At the PTX level cudaLaunchDevice needs to be declared in one of the two forms shown below before it is used PTX level Declaration of cudaLaunchDevice when address size is 64 extern func param b32 func retval0 cudaLaunchDevice param b64 func param b64 parameterBuffer param align 4 b8 gridDimension 12 param align 4 b8 blockDimension 12 param b32 sharedMemSize param b64 stream PTX level Declaration of cudaLaunchDevice when address size is 32 extern func param b32 func retval0 cudaLaunchDevice Mamans sc Mam param b32 parameterBuffer param align 4 b8 gridDimension 12 param align 4 b8 blockDimension 12 param b32 sharedMemSize param b32 stream The CUDA level declaration below is mapped to one of the aforementioned PTX level declarations and is found in the system header file cuda device runtime api h The function is defined in the cudadevrt system library which must be linked with a program in order to use device side kernel launch functionality CUDA level declaration of cudaLaunchDevice amem WEN cevics cudaError t cudaLaunchDevice voi
129. ared memory is divided into equally sized memory modules called banks which can be accessed simultaneously Any memory read or write request made of n addresses that fall in n distinct memory banks can therefore be serviced simultaneously yielding an overall bandwidth that is n times as high as the bandwidth of a single module However if two addresses of a memory request fall in the same memory bank there is a bank conflict and the access has to be serialized The hardware splits a memory request with bank conflicts into as many separate conflict free requests as necessary decreasing throughput by a factor equal to the number of separate memory requests If the number of separate memory requests is n the initial memory request is said to cause n way bank conflicts To get maximum performance it is therefore important to understand how memory addresses map to memory banks in order to schedule the memory requests so as to minimize bank conflicts This is described in Compute Capability 2 x Compute Capability 3 x and Compute Capability 5 x for devices of compute capability 2 x 3 x and 5 x respectively Constant Memory The constant memory space resides in device memory and is cached in the constant cache mentioned in Compute Capability 2 x A request is then split into as many separate requests as there are different memory addresses in the initial request decreasing throughput by a factor equal to the number of separate requests
130. as launched Since thread 0 of the parent is performing the launch the child will be consistent with the memory seen by thread 0 of the parent Due to the first syncthreads call the child will see data 0 0 data 1 1 data 255 255 without the _ syncthreads call only data 0 would be guaranteed to be seen by the child When the child grid returns thread 0 is guaranteed to see modifications made by the threads in its child grid Those modifications become available to the other threads of the parent grid only after the second __syncthreads call Matcha ero emile Sur eh nds NE data threadlIdx x data threadIdx x 1 Eo licbhal vorc parene lauwnch ianrt ceta 1 data threadIdx x threadIdx x __syncthreads if threadIdx x 0 child launch 1 256 gt gt gt data cudaDeviceSynchronize syncthreads void host launch int data parent launch 1 256 data C 2 2 1 2 Zero Copy Memory Zero copy system memory has identical coherence and consistency guarantees to global memory and follows the semantics detailed above A kernel may not allocate or free zero copy memory but may use pointers to zero copy passed in from the host program C 2 2 1 3 Constant Memory Constants are immutable and may not be modified from the device even between parent and child launches That is to say the value of all constant variables must www nvidia com CUDA C Programming G
131. ata to the CUDA array specified by the one dimensional layered surface object surfObj at coordinate x and y and index layer www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 112 C Language Extensions B 9 1 11 surfCubemapread template lt class T gt T surfCubemapread cudaSurfaceObject t surfObj GLO ox agb Wi ule ace boundaryMode cudaBoundaryModeTrap template class T void surfCubemapread T data cudaSurfaceObject t surfObj dime Sep abes Wp use ffe ey boundaryMode cudaBoundaryModeTrap reads the CUDA array specified by the cubemap surface object surfobj using coordinate x and y and face index face B 9 1 12 surfCubemapwrite template class T void surfCubemapwrite T data cudaSurfaceObject t surfObj SLIME oxy BOE Wp aime aSr boundaryMode cudaBoundaryModeTrap writes value data to the CUDA array specified by the cubemap object sur Obj at coordinate x and y and face index face B 9 1 13 surfCubemapLayeredread template lt class T gt T surfCubemapLayeredread cudaSurfaceObject t surfObj me abge Wp abge Ilenxerelscicis boundaryMode cudaBoundaryModeTrap template lt class T gt void surfCubemapLayeredread T data cudaSurfaceObject t surfObj int x int y int layerFace boundaryMode cudaBoundaryModeTrap reads the CUDA array specified by the cubemap layered surface object surfObj using coordinate x and y and index layerFace B 9 1 14 surfCubemapLayeredwrite
132. ations are valid under the device runtime Dynamically created texture and surface objects are an addition to the CUDA memory model introduced with CUDA 5 0 Please see the CUDA Programming Guide for details www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 149 CUDA Dynamic Parallelism glasal ver PSrmTCe nE mp Ime CELE i eerm gnare dime nenfis if n lt 1 return smem threadIdx x data threadIdx x __syncthreads permute data smem n __syncthreads Write back to GMEM since we can t pass SMEM to children data threadIdx x smem threadIdx x __syncthreads if threadIdx x 0 permute lt lt lt 1 256 n 2 sizeof int gt gt gt n 2 data permutex 1 256 n 2 sizeot int gt gt gt n 2 Gatatn 2 void host launch int data permutes lt lt MEME oue eR ume 2560 data C 3 1 6 4 Symbol Addresses Device side symbols i e those marked __device__ may be referenced from within a kernel simply via the amp operator as all global scope device variables are in the kernel s visible address space This also applies to__ constant__ symbols although in this case the pointer will reference read only data Given that device side symbols can be referenced directly those CUDA runtime APIs which reference symbols e g cudaMemcpyToSymbol or cudaGetSymbolAddress are redundant and hence not supported by the device runtime Note this imp
133. ause the distribution of the warps across the block is deterministic as mentioned in SIMT Architecture A trivial example is when the controlling condition only depends on threadIdx warpSize where warpSize is the warp size In this case no warp diverges since the controlling condition is perfectly aligned with the warps Sometimes the compiler may unroll loops or it may optimize out if or switch statements by using branch predication instead as detailed below In these cases no warp can ever diverge The programmer can also control loop unrolling using the pragma unroll directive see pragma unroll When using branch predication none of the instructions whose execution depends on the controlling condition gets skipped Instead each of them is associated with a per thread condition code or predicate that is set to true or false based on the controlling condition and although each of these instructions gets scheduled for execution only the instructions with a true predicate are actually executed Instructions with a false predicate do not write results and also do not evaluate addresses or read operands The compiler replaces a branch instruction with predicated instructions only if the number of instructions controlled by the branch condition is less or equal to a certain threshold If the compiler determines that the condition is likely to produce many divergent warps this threshold is 7 otherwise it is 4 www nvidia com CUDA C Pro
134. b matrix of B of dimension block size A width that has the same column indices as C In order to fit into the device s resources these two rectangular matrices are divided into as many square matrices of dimension block size as necessary and C is computed as the sum of the products of these square matrices Each of these products is performed by first loading the two corresponding square matrices from global memory to shared memory with one thread loading one element of each matrix and then by having each thread compute one element of the product Each thread accumulates the result of each of these products into a register and once done writes the result to global memory www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 26 Programming Interface By blocking the computation this way we take advantage of fast shared memory and save a lot of global memory bandwidth since A is only read B width block_size times from global memory and B is read A height block_size times The Matrix type from the previous code sample is augmented with a stride field so that sub matrices can be efficiently represented with the same type __device__ functions are used to get and set elements and build any sub matrix from a matrix Matrices are stored in row major order M row col M elements row M stride col typedef struct Aie WERGE NA int height aene GIES float elements EMI Eri Get a matrix element er
135. between host and device programs without the need for explicit allocations or copying Semantically the behavior of managed variables is identical to that of storage allocated via cudaMallocManaged Data is hosted in physical GPU storage and is visible to all GPUs in the system as well as the CPU Stream visibility defaults to cudaMemAttachGlobal but may be constrained using cudaStreamAttachMemAsync A valid CUDA context is necessary for the correct operation of managed variables Accessing managed variables can trigger CUDA context creation if a context for the current device hasn t already been created In the example above accessing x before the kernel launch triggers context creation on device 0 In the absence of that access the kernel launch would have triggered context creation C objects declared as managed are subject to certain specific constraints particularly where static initializers are concerned Please refer to C C Language Support in the CUDA C Programming Guide for a list of these constraints J 2 3 1 Host Program Errors with managed ___ Variables Theuseof managed variables depends upon the underlying Unified Memory system functioning correctly Incorrect functioning can occur if for example the CUDA installation failed or if the CUDA context creation was unsuccessful When CUDA specific operations fail typically an error is returned that indicates the source of the failure Using managed variables intro
136. bilities To maximize global memory throughput it is therefore important to maximize coalescing by gt Following the most optimal access patterns based on Compute Capability 2 x and Compute Capability 3 x gt Using data types that meet the size and alignment requirement detailed in Device Memory Accesses www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 79 Performance Guidelines gt Padding data in some cases for example when accessing a two dimensional array as described in Device Memory Accesses Size and Alignment Requirement Global memory instructions support reading or writing words of size equal to 1 2 4 8 or 16 bytes Any access via a variable or a pointer to data residing in global memory compiles to a single global memory instruction if and only if the size of the data type is 1 2 4 8 or 16 bytes and the data is naturally aligned i e its address is a multiple of that size If this size and alignment requirement is not fulfilled the access compiles to multiple instructions with interleaved access patterns that prevent these instructions from fully coalescing It is therefore recommended to use types that meet this requirement for data that resides in global memory The alignment requirement is automatically fulfilled for the built in types of char short int long longlong float double like 1oat2 or float4 For structures the size and alignment requirements can be enforced by the
137. by changing the resolution or bit depth of the display using NVIDIA control panel or the Display control panel on Windows the amount of memory needed for the primary surface changes For example if the user changes the display resolution from 1280x1024x32 bit to 1600x1200x32 bit the system must dedicate 7 68 MB to the primary surface rather than 5 24 MB Full screen graphics applications running with anti aliasing enabled may require much more display memory for the primary surface On Windows other events that may initiate display mode switches include launching a full screen DirectX application hitting Alt Tab to task switch away from a full screen DirectX application or hitting Ctrl Alt Del to lock the computer If a mode switch increases the amount of memory needed for the primary surface the system may have to cannibalize memory allocations dedicated to CUDA applications Therefore a mode switch results in any call to the CUDA runtime to fail and return an invalid context error 3 6 Tesla Compute Cluster Mode for Windows Using NVIDIA s System Management Interface nvidia smi the Windows device driver can be put in TCC Tesla Compute Cluster mode for devices of the Tesla and Quadro Series of compute capability 2 0 and higher This mode has the following primary benefits gt It makes it possible to use these GPUs in cluster nodes with non NVIDIA integrated graphics gt It makes these GPUs available via Remote Desktop bo
138. by level Type is the same as DataType except when readMode is cudaReadModeNormalizedFloat see Texture Reference API in which case Type is the corresponding floating point type B 8 2 10 tex3DGrad template lt class DataType enum cudaTextureReadMode readMode gt Type tex3DGrad texture DataType cudaTextureType3D readMode gt texRef fioa ox ellen ye kloat van Floarida sslhexeued oh 9 fetches from the CUDA array bound to the two dimensional texture reference texRef using texture coordinate x y z The level of detail is derived from the dx and dy X and Y gradients Type is the same as DataType except when readMode is cudaReadModeNormalizedFloat see Texture Reference API in which case Type is the corresponding floating point type B 8 2 11 tex1DLayered template lt class DataType enum cudaTextureReadMode readMode gt Type texlDLayered texture lt DataType cudaTextureTypelDLayered readMode gt texRef float x int layer fetches from the CUDA array bound to the one dimensional layered texture reference texRef using texture coordinate x and index layer as described in Layered Textures Type is equal to DataType except when readMode is equal to www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 107 C Language Extensions cudaReadModeNormalizedFloat see Texture Reference API in which case Type is equal to the matching floating point type B 8 2 12 tex1DLayeredLod template lt c
139. by zero yields an unspecified machine specific value http developer nvidia com content precision performance floating point and ieee 754 compliance nvidia gpus includes more information on the floating point accuracy and compliance of NVIDIA GPUs G 3 Compute Capability 2 x G 3 1 Architecture For devices of compute capability 2 x a multiprocessor consists of gt For devices of compute capability 2 0 gt 32 CUDA cores for arithmetic operations see Arithmetic Instructions for throughputs of arithmetic operations gt 4 special function units for single precision floating point transcendental functions www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 208 Compute Capabilities gt For devices of compute capability 2 1 gt 48 CUDA cores for arithmetic operations see Arithmetic Instructions for throughputs of arithmetic operations gt 8 special function units for single precision floating point transcendental functions gt 2warp schedulers At every instruction issue time each scheduler issues gt One instruction for devices of compute capability 2 0 gt Two independent instructions for devices of compute capability 2 1 for some warp that is ready to execute if any The first scheduler is in charge of the warps with an odd ID and the second scheduler is in charge of the warps with an even ID Note that when a scheduler issues a double precision floating point instruction the other schedul
140. c enum cudaTextureAddressMode addressMode 3 enum cudaTextureFilterMod filterMode enum cudaTextureReadMod readMode age SRGB int normalizedCoords unsigned int maxAnisotropy enum cudaTextureFilterMod mipmapFilterMode float mipmapLevelBias float minMipmapLevelClamp float maxMipmapLevelClamp gt addressMode specifies the addressing mode filterMode specifies the filter mode readMode specifies the read mode normalizedCoords specifies whether texture coordinates are normalized or not See reference manual for sRGB maxAnisotropy mipmapFilterMode mipmapLevelBias minMipmapLevelClamp and maxMipmapLevelClamp v v v v www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 44 Programming Interface The following code sample applies some simple transformation kernel to a texture Simple transformation kernel _ global void transformKernel float output cudaTextureObject t texObj int width int height float theta Calculate normalized texture coordinates nsigned int x ook doe lt Tod cime tef era eiici c x unsigned int y blockIdx y blockDim y threadIdx y float u Eloet WW x y loeien y float height Transform coordinates u 0 5f Vi eem st itllovewE EM U s Coss asta w Sim laste x ast izlkoyeue ier we OE tierce ar Dl 9 Sime Cheren r OW Siee Read from texture and write to global memory output y w
141. call to printf will be executed by every thread using that thread s data as specified Multiple versions of the output string will then appear at the host stream once for each thread which encountered the printf It is up to the programmer to limit the output to a single thread if only a single output string is desired see Examples for an illustrative example www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 127 C Language Extensions Unlike the C standard printf which returns the number of characters printed CUDA s printf returns the number of arguments parsed If no arguments follow the format string 0 is returned If the format string is NULL 1 is returned If an internal error occurs 2 is returned B 17 1 Format Specifiers As for standard printf format specifiers take the form flags width precision size type The following fields are supported see widely available documentation for a complete description of all behaviors gt Flags 0 7 gt Width 0 9 gt Precision 0 9 k Size h TOI gt Type 7ocdiouxXpeEfgGaAs Note that CUDA s print will accept any combination of flag width precision size and type whether or not overall they form a valid format specifier In other words thd will be accepted and printf will expect a double precision variable in the corresponding location in the argument list B 17 2 Limitations Final formatting of the print
142. ccording to need Memory reserved for the device heap is in addition to memory allocated through host side CUDA API calls such as cudaMalloc B 18 2 Interoperability with Host Memory API Memory allocated via malloc cannot be freed using the runtime i e by calling any of the free memory functions from Device Memory Similarly memory allocated via the runtime i e by calling any of the memory allocation functions from Device Memory cannot be freed via free B 18 3 Examples B 18 3 1 Per Thread Allocation The following code sample include lt stdlib h gt include lt stdio h gt glasel void me llectest i size size 1237 char ptr char malloc size memset ptr 0 size printf Thread d got pointer p n threadIdx x ptr free ptr int main Set a heap size of 128 megabytes Note that this must be done before any kernel is launched cudaDeviceSetLimit cudaLimitMallocHeapSize 128 1024 1024 mallocTest lt lt lt 1 S gt 2 gt 7 cudaDeviceSynchronize return 0 will output Thread 0 got pointer 00057020 Thread 1 got pointer 0005708c Thread 2 got pointer 000570f8 Thread 3 got pointer 00057164 Thread 4 got pointer 000571d0 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 132 C Language Extensions Notice how each thread encounters the malloc and memset commands and so receives and initializes its own allocation Exact poi
143. ce EE siza piten ine wwalcheim aioe Invsalojoe fore iin 36 Op ce lt ImeougimEp aie ll ere mony loew Webern Clewikiee 4 i iTe p irene uae Of c lt wohne aue 4 float element row c The following code sample allocates a width x height x depth 3D array of floating point values and shows how to loop over the array elements in device code Host code int width 64 height 64 cudal cuda cuda Extent PitchedPtr devPitchedPtr alloc3D amp devPitchedPtr depth 64 xtent make cudaExtent width sizeof float height depth extent MyKernel 100 512 gt gt gt devPitchedPtr width height depth Ii Deriecs cowe global void MyKernel cudaPitchedPtr devPitchedPtr int width int height int depth char devPtr devPitchedPtr ptr susc pitea cle vibe bis oL CENA alze iE silicspirten piten laeua itor ime 2 Of x lt Geoana aara tt char slice devPtr z slicePitch iowe Gide S em OF sy lnSivejnee aay d Eloa scowl E eat ssbite o LESEN C EI itewe uae ok e Og xx lt walclcing aspx di float element row x The reference manual lists all the various functions used to copy memory between linear memory allocated with cudaMalloc linear memory allocated with cudaMallocPitch or cudaMalloc3D CUDA arrays and memory allocated for variables declared in global or constant memory space
144. ce ence eee eeeee ene en hee hee ehe ese ene 11 Figure 7 Memory Hierarchy 2o oeei cs sid nenna EREA AEEA nawdeae node RA DNI deanna PNEU eT DP 13 Figure 8 Heterogeneous Programming ceeeeseeessseseeseeeesee sene eene eene 15 Figure 9 Matrix Multiplication without Shared Memory c csse ene 26 Figure 10 Matrix Multiplication with Shared Memory cesses emen 29 Figure 11 The Driver API Is Backward but Not Forward Compatible esseeeeese 67 Figure 12 Parent Child Launch Nesting cece cece cee ee eee eee e ence eee ee hene 142 Figure 13 Nearest Point Sampling Filtering Mode sce e eee ee cece eee eese eee eeeeenseeeeeeeees 201 Figure 14 Linear Filtering Mode cccccsccecscceeseceeeeeeeeseeeeeeeeeeeesseeseeeeeeeeeeeseeeees 202 Figure 15 One Dimensional Table Lookup Using Linear Filtering eeeseeeeeeeesese 203 Figure 16 Examples of Global Memory ACCESSES ceecceee eee ence ence e eene enn 215 Figure 17 Strided Shared Memory ACCESSES ccc sce e eee eee eee eee eeeseeeeeeneeeneeeeeeeeeeeeeeees 219 Figure 18 Irregular Shared Memory ACCESSES cceece cece eee e eee eee eeceeeeeeeee eee eeeeeeeeeeeeees 220 Figure 19 Library Context Management cece cece eee e seen eee e eee eee eee ehe ehe eene nene 225 www nvidia com LIST OF FIGURES CUDA C Programming Guide PG 02829 001_v7 5 xii LIST OF TABLES
145. ch the data is observed being written by another CUDA or host thread gt The order in which a CUDA thread reads data from shared memory global memory page locked host memory or the memory of a peer device is not necessarily the order in which the read instructions appear in the program for instructions that are independent of each other www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 96 C Language Extensions For example if thread 1 executes writeXY and thread 2 executes readXY as defined in the following code sample cevice volercile aime MEN Y 27 ENdeviceN vorc mitre X Y 10g ZIP Bev comm venc raach h int A algae JB X Y it is possible that B ends up equal to 2 and A equal to 10 for thread 2 gt either because at the time thread 2 reads X and Y thread 1 s write to X has happened from thread 2 s perspective but thread 1 s write to Y has not gt or because thread 2 reads Y before X and thread 1 s writes to X and Y happen after thread 2 s read of Y and before thread 2 s read of X In a strongly ordered memory model the only possibilities would be gt Aequalto 1 and B equal to 2 thread 1 s writes to X and Y happen after thread 2 s read of X and Y gt Aequalto 10 and B equal to 2 thread 1 s write to X happens before thread 2 s read of X and thread 1 s write to Y happens after thread 2 s read of v gt Aequalto 10 and B equal to 20 thread 1 s writes to X and Y happen
146. com CUDA C Programming Guide PG 02829 001_v7 5 27 Programming Interface cudaMalloc amp d B elements size cudaMemcpy d B elements B elements size cudaMemcpyHostToDevice Allocate C in device memory Mates cr Gl C waiehEm Gl C strice Co wicin el C nerghe msaoimep size C width C height sizeof float cudaMalloc amp d C elements size Invoke kernel dim3 dimBlock BLOCK SIZE BLOCK SIZE dim3 dimGrid B width dimBlock x A height dimBlock y MatMulKernel dimGrid dimBlock d A d B d C Read C from device memory cudaMemcpy C elements d C elements size cudaMemcpyDeviceToHost Free device memory cudaFree d A elements cudaFree d B elements cudaFree d C elements Matrix multiplication kernel called by MatMul __global_ void MatMulKernel Matrix A Matrix B Matrix C Block row and column int blockRow blockIdx y ine DIGER J9leelsebssxp Each thread block computes one sub matrix Csub of C Matrix Csub GetSubMatrix C blockRow blockCol Each thread computes one element of Csub by accumulating results into Cvalue float Cvalue 0 Thread row and column within Csub int row threadIdx y int col threadIdx x Loop over all the sub matrices of A and B that are required to compute Csub Multiply each pair of sub matrices together and accumulate the results for int m 0 m A width BLOC
147. compiler using the alignment specifiers align 8 or X align 16 suchas uU MEER CNN CEP NET float x iclloeie NV or struct align 16 clore Zep Eloa tiyn itibkeysue vam H Any address of a variable residing in global memory or returned by one of the memory allocation routines from the driver or runtime API is always aligned to at least 256 bytes Reading non naturally aligned 8 byte or 16 byte words produces incorrect results off by a few words so special care must be taken to maintain alignment of the starting address of any value or array of values of these types A typical case where this might be easily overlooked is when using some custom global memory allocation scheme whereby the allocations of multiple arrays with multiple calls to cudaMalloc or cuMemAlloc is replaced by the allocation of a single large block of memory partitioned into multiple arrays in which case the starting address of each array is offset from the block s starting address Two Dimensional Arrays A common global memory access pattern is when each thread of index tx ty uses the following address to access one element of a 2D array of width width located at address www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 80 Performance Guidelines BaseAddress of type type where type meets the requirement described in Maximize Utilization BaseAddress width ty tx For these accesses to be fully coalesced both th
148. completely execute the thread but not of the number of clock cycles the device actually spent executing thread instructions The former number is greater than the latter since threads are time sliced www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 117 C Language Extensions B 12 Atomic Functions An atomic function performs a read modify write atomic operation on one 32 bit or 64 bit word residing in global or shared memory For example atomicAdd reads a word at some address in global or shared memory adds a number to it and writes the result back to the same address The operation is atomic in the sense that it is guaranteed to be performed without interference from other threads In other words no other thread can access this address until the operation is complete Atomic functions do not act as memory fences and do not imply synchronization or ordering constraints for memory operations see Memory Fence Functions for more details on memory fences Atomic functions can only be used in device functions and atomic functions operating on mapped page locked memory Mapped Memory are not atomic from the point of view of the host or other devices Note that any atomic operation can be implemented based on atomicCAS Compare And Swap For example atomicAdd for double precision floating point numbers can be implemented as follows device double atomicAdd double address double val winsialepovercl Ioinre Meine
149. conflicts even if no two threads in a quarter warp access different addresses belonging to the same bank Therefore to determine the ways of bank conflicts one must add 1 to the maximum number of threads in a quarter warp that access different addresses belonging to the same bank G 3 4 Constant Memory In addition to the constant memory space supported by devices of all compute capabilities where constant variables reside devices of compute capability 2 x support the LDU LoaD Uniform instruction that the compiler uses to load any variable that is gt pointing to global memory gt read only in the kernel programmer can enforce this using the const keyword gt not dependent on thread ID G 4 Compute Capability 3 x G 4 1 Architecture A multiprocessor consists of gt 192 CUDA cores for arithmetic operations see Arithmetic Instructions for throughputs of arithmetic operations gt 32 special function units for single precision floating point transcendental functions gt 4 warp schedulers When a multiprocessor is given warps to execute it first distributes them among the four schedulers Then at every instruction issue time each scheduler issues two independent instructions for one of its assigned warps that is ready to execute if any A multiprocessor has a read only constant cache that is shared by all functional units and speeds up reads from the constant memory space which resides in device memory
150. cpy Memset Behavior With Managed Memory eeeeeesss 243 J 2 3 Language Integration iier oreson rere eerte e ar rr e Pera rer rre PER 243 J 2 3 1 Host Program Errors with managed Variables eeeeuues 244 J 2 4 Querying Unified Memory Support sssseesseessessee e e eene eene nennen 245 J 2 4 1 Device PropertieS ccccsssccsccccsessecceceesscsceeeecssssescesesesseeesesessessnereees 245 3 2 4 2 Pointer AttFIDUtGs 2 eeoee erre nra Re Eee nore ae EX eee Fer PESEE ERT e BRE ERR EE TER 245 J 2 5 Advanced TOPICS 22 ies eoe oer wishes ORE S REERE E ewe ERES DE E FERIAS NES PabR A CREME REESE 245 J 2 5 1 Managed Memory with Multi GPU Programs cessere nne 245 J 2 5 2 Using fork with Managed Memory c csse e eene 246 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 xi Figure 1 Floating Point Operations per Second for the CPU and GPU s sce eeeeeeeeeee noone 2 Figure 2 Memory Bandwidth for the CPU and GPU cee eee cece eee e eee eee nenne enne 3 Figure 3 The GPU Devotes More Transistors to Data Processing ssssssssssessesseeseeseesereese 3 Figure 4 GPU Computing Applications cesses nennen hee hee e eene 5 Figure 5 Automatic Scalability ccccssscvscsccsecssnendassoecensmsaatensicnsoseeesesacendsenesdeessacinneasies 7 Figure 6 Grid of Thread Blocks cce eee e cece cece ee en
151. cudaDeviceReset has been called on those devices These environment variables are described in Appendix CUDA Environment Variables www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 245 Unified Memory Programming J 2 5 2 Using fork with Managed Memory The Unified Memory system does not allow sharing of managed memory pointers between processes It will not correctly manage memory handles that have been duplicated via a fork operation Results will be undefined if either the child or parent accesses managed data following a fork It is safe however to fork a child process that then immediately exits via an exec call because the child drops the memory handles and the parent becomes the sole owner once again It is not safe for the parent to exit and leave the child to access the handles www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 246 Notice ALL NVIDIA DESIGN SPECIFICATIONS REFERENCE BOARDS FILES DRAWINGS DIAGNOSTICS LISTS AND OTHER DOCUMENTS TOGETHER AND SEPARATELY MATERIALS ARE BEING PROVIDED AS IS NVIDIA MAKES NO WARRANTIES EXPRESSED IMPLIED STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS AND EXPRESSLY DISCLAIMS ALL IMPLIED WARRANTIES OF NONINFRINGEMENT MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Information furnished is believed to be accurate and reliable However NVIDIA Corporation assumes no responsibility for the consequences of use of such informat
152. d amp positions amp num bytes positionsVB CUDA Execute kernel cimosasumbiltosis o ly SN dim3 dimGrid width dimBlock x height dimBlock y 1 createVertices lt lt lt dimGrid dimBlock positions time width height Unmap vertex buffer cudaGraphicsUnmapResources 1 amp positionsVB CUDA 0 Draw and present void releaseVB cudaGraphicsUnregisterResource positionsVB CUDA positionsVB gt Release gileisenl EE Ouen eatevesiieesisiteai i joxeriaesems EE loat iis unsigned int width unsigned int height unsigned int x blockIdx x blockDim x threadIdx x unsigned int y leylexelisItebow lt bilockDummiya ar we hiaeadleseny Calculate uv coordinates float u x float width float v y float height US wi 2549 i Ore WS ws 201 LOE Calculate simple sine wave pattern float freq 4 0f float w sinf u freq time GOSIE wr Eee ap Cime OW Sip Write positions positions y width x make float4 u w v _int_as float Oxff00ff00 www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 63 Programming Interface 3 2 12 2 3 Direct3D 11 Version ID3D11Device device struct CUSTOMVERTEX he ECORI Wa o YA DWORD color ID3D11Buffer positionsVB struct cudaGraphicsResource positionsVB CUDA int main int dev Get a CUDA enabled adapter IDXGIFactory factory CreateDXGI
153. d Programs that depend upon concurrency between child kernels are not supported by the CUDA programming model and will have undefined behavior The host side NULL stream s cross stream barrier semantic is not supported on the device see below for details In order to retain semantic compatibility with the host runtime all device streams must be created using the cudaStreamCreateWithFlags API passing the cudaStreamNonBlocking flag The cudaStreamCreate call is a host runtime only API and will fail to compile for the device As cudaStreamSynchronize and cudaStreamQuery are unsupported by the device runtime cudaDeviceSynchronize should be used instead when the application needs to know that stream launched child kernels have completed C 3 1 2 1 The Implicit NULL Stream Within a host program the unnamed NULL stream has additional barrier synchronization semantics with other streams see Default Stream for details The device runtime offers a single implicit unnamed stream shared between all threads in www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 147 CUDA Dynamic Parallelism a block but as all named streams must be created with the cudaStreamNonBlocking flag work launched into the NULL stream will not insert an implicit dependency on pending work in any other streams C 3 1 3 Events Only the inter stream synchronization capabilities of CUDA events are supported This means that cudaStreamWait
154. d func void parameterBuffer dim3 gridDimension dim3 blockDimension unsigned int sharedMemSize cudaStream t stream The first parameter is a pointer to the kernel to be is launched and the second parameter is the parameter buffer that holds the actual parameters to the launched kernel The layout of the parameter buffer is explained in Parameter Buffer Layout below Other parameters specify the launch configuration i e as grid dimension block dimension shared memory size and the stream associated with the launch please refer to Execution Configuration for the detailed description of launch configuration www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 153 CUDA Dynamic Parallelism C 3 2 1 2 cudaGetParameterBuffer cudaGetParameterBuffer needs to be declared at the PTX level before it s used The PTX level declaration must be in one of the two forms given below depending on address size PTX level Declaration of cudaGetParameterBuffer when address size is 64 When address size is 64 extern func param b64 func retval0 cudaGetParameterBuffer param b64 alignment param b64 size PTX level Declaration of cudaGetParameterBuffer when address size is 32 extern func param b32 func retval0 cudaGetParameterBuffer param b32 alignment param b32 size The following CUDA level declaration of cudaGetParameterBuffer is mapped to the afore
155. d if there is no other application currently running on the PG 02829 001 v7 5 230 CUDA Environment Variables same GPU that successfully requested a different behavior otherwise it is ignored cuda gdb on CUDA_DEVICE_WAITS_ O or 1 default When set to 1 a CUDA application will Mac and Linux ON EXCEPTION is 0 halt when a device exception occurs platforms allowing a debugger to be attached for further debugging Driver Based CUDA DEVICE Integer default Specifies the index of the device to Profiler these is 0 profile variables have no impact COMPUTE PROFILE O or 1 default Disables profiling when set to 0 o on the Visual is 0 enables profiling when set to 1 Profiler or the COMPUTE_PROFILE_ Path Specifies the configuration file to set command line CONFIG profiling options and select performance profiler nvprof counters COMPUTE_PROFILE_LOG Path Specifies the file used to save the profiling output In case of multiple contexts use d in the COMPUTE_PROFILE_LOG to generate separate output files for each context with d substituted by the context number COMPUTE PROFILE CSV 0 or 1 default When set to 1 the output will be in is 0 comma separated format www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 231 Appendix J UNIFIED MEMORY PROGRAMMING J 1 Unified Memory Introduction Unified Memory is a component of the CUDA programming model first introduced in C
156. d the coordinate addresses a texel within that layer A two dimensional layered texture is addressed using an integer index and two floating point texture coordinates the index denotes a layer within the sequence and the coordinates address a texel within that layer A layered texture can only be a CUDA array by calling cudaMalloc3DArray with the cudaArrayLayered flag and a height of zero for one dimensional layered texture Layered textures are fetched using the device functions described in tex1DLayered tex1DLayered tex2DLayered and tex2DLayered Texture filtering see Texture Fetching is done only within a layer not across layers Layered textures are only supported on devices of compute capability 2 0 and higher 3 2 11 1 5 Cubemap Textures A cubemap texture is a special type of two dimensional layered texture that has six layers representing the faces of a cube gt The width of a layer is equal to its height gt The cubemap is addressed using three texture coordinates x y and z that are interpreted as a direction vector emanating from the center of the cube and pointing to one face of the cube and a texel within the layer corresponding to that face More specifically the face is selected by the coordinate with largest magnitude m and the corresponding layer is addressed using coordinates s m 1 2 and t m 1 2 where s and t are defined in Table 1 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5
157. d through CUDA as long as the current device uses unified addressing gt Allocations via cudaHostAlloc are automatically portable see Portable Memory across all the devices for which the unified address space is used and pointers returned by cudaHostAlloc can be used directly from within kernels running on these devices i e there is no need to obtain a device pointer via cudaHostGetDevicePointer as described in Mapped Memory www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 40 Programming Interface Applications may query if the unified address space is used for a particular device by checking that the unifiedAddressing device property see Device Enumeration is equal to 1 3 2 8 Interprocess Communication Any device memory pointer or event handle created by a host thread can be directly referenced by any other thread within the same process It is not valid outside this process however and therefore cannot be directly referenced by threads belonging to a different process To share device memory pointers and events across processes an application must use the Inter Process Communication API which is described in detail in the reference manual The IPC API is only supported for 64 bit processes on Linux and for devices of compute capability 2 0 and higher Using this API an application can get the IPC handle for a given device memory pointer using cudaIpcGetMemHandle pass it to another process using
158. d via malloc remains allocated for the lifetime of the CUDA context or until it is explicitly released by a call to free It can be used by any other CUDA threads even from subsequent kernel launches Any CUDA thread may free memory allocated by another thread but care should be taken to ensure that the same pointer is not freed more than once B 18 1 Heap Memory Allocation The device memory heap has a fixed size that must be specified before any program using malloc or free is loaded into the context A default heap of eight megabytes is allocated if any program uses malloc without explicitly specifying the heap size The following API functions get and set the heap size gt cudaDeviceGetLimit size_t size cudaLimitMallocHeapSize gt cudaDeviceSetLimit cudaLimitMallocHeapSize size t size The heap size granted will be at least size bytes cuCtxGetLimit and cudaDeviceGetLimit return the currently requested heap size www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 131 C Language Extensions The actual memory allocation for the heap occurs when a module is loaded into the context either explicitly via the CUDA driver API see Module or implicitly via the CUDA runtime API see CUDA C Runtime If the memory allocation fails the module load will generate a CUDA ERROR SHARED OBJECT INIT FAILED error Heap size cannot be changed once a module load has occurred and it does not resize dynamically a
159. daTextureReadMode readMode gt Type tex2DGrad texture DataType cudaTextureType2D readMode gt texRef moeg se closs yp itloeuE2 Che dtlhoeu2 ew www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 106 C Language Extensions fetches from the CUDA array bound to the two dimensional texture reference texRef using texture coordinate x y The level of detail is derived from the dx and dy X and Y gradients Type is the same as DataType except when readMode is cudaReadModeNormalizedFloat see Texture Reference API in which case Type is the corresponding floating point type B 8 2 8 tex3D template lt class DataType enum cudaTextureReadMode readMode gt Type tex3D texture DataType cudaTextureType3D readMode texRef float glen wie cedbhexsue vaa fetches from the CUDA array bound to the three dimensional texture reference texRef using texture coordinates x y and z Type is equal to DataType except when readMode is equal to cudaReadModeNormalizedFloat see Texture Reference API in which case Type is equal to the matching floating point type B 8 2 9 tex3DLod template lt class DataType enum cudaTextureReadMode readMode gt Type tex3DLod texture lt DataType cudaTextureType3D readMode gt texRef lose 2 ielhoeie Wy iedoeie wp ellos Jewel fetches from the CUDA array bound to the two dimensional texture reference texRef using texture coordinate x y z The level of detail is given
160. de to perform butterfly reduction ios ime ab 16s t sil 1 2 value t __shfl_xor value i 32 value now contains the sum across all threads printf Thread d final value d n threadIdx x value main warpReduce lt lt lt 1 32 gt gt gt cudaDeviceSynchronize return 0 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 125 C Language Extensions B 15 Profiler Counter Function Each multiprocessor has a set of sixteen hardware counters that an application can increment with a single instruction by calling the prof trigger function Iorc proz erigger laine COUme increments by one per warp the per multiprocessor hardware counter of index counter Counters 8 to 15 are reserved and should not be used by applications The value of counters 0 1 7 can be obtained via nvprof by nvprof events prof trigger Ox where x is 0 1 7 The value of those counters for the first multiprocessor can also be obtained via the old CUDA command line profiler by listing prof trigger 00 prof trigger 01 prof trigger 07 etc inthe profiler conf file see the profiler manual for more details All counters are reset before each kernel launch note that when collecting counters kernel launches are synchronous as mentioned in Concurrent Execution between Host and Device B 16 Assertion Assertion is only supported by devices of compute capability 2 x and higher It is not suppo
161. deTrap template lt class Type gt void surflDLayeredread Type data surface lt void cudaSurfaceTypelDLayered gt surfRef int x ine layer boundaryMode cudaBoundaryModeTrap reads the CUDA array bound to the one dimensional layered surface reference surfRef using coordinate x and index layer B 9 2 8 surfiDLayeredwrite template lt class Type gt void surflDLayeredwrite Type data surface lt void cudaSurfaceTypelDLayered gt surfRef int x int layer boundaryMode cudaBoundaryModeTrap writes value data to the CUDA array bound to the two dimensional layered surface reference surfRef at coordinate x and index layer www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 115 C Language Extensions B 9 2 9 surf2DLayeredread template lt class Type gt Type surf2DLayeredread surface lt void cudaSurfaceType2DLayered gt surfRef GONE 85 Guia wr avec levec boundaryMode cudaBoundaryModeTrap template lt class Type gt void surf2DLayeredread Type data surface lt void cudaSurfaceType2DLayered gt surfRef age 3X Ione yy Lae deyer boundaryMode cudaBoundaryModeTrap reads the CUDA array bound to the two dimensional layered surface reference surfRef using coordinate x and y and index layer B 9 2 10 surf2DLayeredwrite template lt class Type gt void surf2DLayeredwrite Type data surface lt void cudaSurfaceType2DLayered gt surfRef GME 85 aime wo aime lewis bo
162. defined if width is not a power of 2 or is a number greater than warpSize Sh 1 returns the value of var held by the thread whose ID is given by srcLane If width is less than warpSize then each subsection of the warp behaves as a separate entity with a starting logical lane ID of 0 If srcLane is outside the range 0 width 1 the value returned corresponds to the value of var held by the srcLane modulo width i e within the same subsection Shfl up calculates a source lane ID by subtracting delta from the caller s lane ID The value of var held by the resulting lane ID is returned in effect var is shifted up the warp by delta lanes If width is less than warpSize then each subsection of the warp behaves as a separate entity with a starting logical lane ID of 0 The source lane index will not wrap around the value of width so effectively the lower delta lanes will be unchanged Shfl down calculates a source lane ID by adding delta to the caller s lane ID The value of var held by the resulting lane ID is returned this has the effect of shifting var down the warp by delta lanes If width is less than warpSize then each subsection of the warp behaves as a separate entity with a starting logical lane ID of 0 As for Shfl up the ID number of the source lane will not wrap around the value of width and so the upper delta lanes will remain unchanged Shfl xor calculates a source line ID by performing a bitwise XOR of the ca
163. del allows the GPU architecture to span a wide market range by simply scaling the number of multiprocessors and memory partitions from the high performance enthusiast GeForce GPUs and professional Quadro and Tesla computing products to a variety of inexpensive mainstream GeForce GPUs see CUDA Enabled GPUs for a list of all CUDA enabled GPUs www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 6 Introduction A GPU is built around an array of Streaming Multiprocessors SMs see Hardware Implementation for more details A multithreaded program is partitioned into blocks of threads that execute independently from each other so that a GPU with more multiprocessors will automatically execute the program in less time than a GPU with fewer multiprocessors Figure 5 Automatic Scalability 1 4 Document Structure This document is organized into the following chapters Chapter Introduction is a general introduction to CUDA Chapter Programming Model outlines the CUDA programming model Chapter Programming Interface describes the programming interface Chapter Hardware Implementation describes the hardware implementation Chapter Performance Guidelines gives some guidance on how to achieve maximum performance Appendix CUDA Enabled GPUs lists all CUDA enabled devices gt Appendix C Language Extensions is a detailed description of all extensions to the C language v v v v y v www nvidia com CUDA C Programming Guide
164. des Shme ane pg funcPtr MyKernel cudaFuncSetCacheConfig funcPtr cudaFuncCachePreferShared The default cache configuration is prefer none meaning no preference If a kernel is configured to have no preference then it will default www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 209 Compute Capabilities to the preference of the current thread context which is set using cudaDeviceSetCacheConfig cuCtxSetCacheConfig see the reference manual for details If the current thread context also has no preference which is again the default setting then whichever cache configuration was most recently used for any kernel will be the one that is used unless a different cache configuration is required to launch the kernel e g due to shared memory requirements The initial configuration is 48 KB of shared memory and 16 KB of L1 cache Applications may query the L2 cache size by checking the 12CacheSize device property see Device Enumeration The maximum L2 cache size is 768 KB Multiprocessors are grouped into Graphics Processor Clusters GPCs A GPC includes four multiprocessors Each multiprocessor has a read only texture cache to speed up reads from the texture memory space which resides in device memory It accesses the texture cache via a texture unit that implements the various addressing modes and data filtering mentioned in Texture and Surface Memory G 3 2 Global Memory Global memory accesses
165. dsroyisd ida a elim Ute orsa cudaSurfaceObject t inputSurfObj 0 cudaCreateSurfaceObject amp inputSurfObj amp resDesc BeOS Des Cr he Smicusitdlyieraa avv a eru b Ut OUR Ste QT cudaSurfaceObject t outputSurfObj 0 cudaCreateSurfaceObject amp outputSurfObj amp resDesc Invoke kernel Gams climb locks Glo I OD dim3 dimGrid width dimBlock x 1 dimBlock x height dimBlock y 1 dimBlock y copyKernel dimGrid dimBlock inputSurfObj outputSurfObj width height Destroy surface objects cudaDestroySurfaceObject inputSurfObj cudaDestroySurfaceObject outputSurfObj Free device memory cudaFreeArray culInputArray cudaFreeArray cuOutputArray return 0 www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 53 Programming Interface 3 2 11 2 2 Surface Reference API A surface reference is declared at file scope as a variable of type surface surface lt void Type gt surfRef where Type specifies the type of the surface reference and is equal to cudaSurfaceTypelD cudaSurfaceType2D cudaSurfaceType3D cudaSurfaceTypeCubemap cudaSurfaceTypelDLayered cudaSurfaceType2DLayered or cudaSurfaceTypeCubemapLayered Type is an optional argument which defaults to cudaSurfaceType1D A surface reference can only be declared as a static global variable and cannot be passed as an argument to a function Before a kernel can use a surface reference to access a CUDA array the
166. duces a new failure mode whereby a non CUDA operation for example CPU access to what should be a valid host memory address can fail if the Unified Memory system is not operating correctly Such invalid memory accesses cannot easily be attributed to the underlying CUDA www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 244 Unified Memory Programming subsystem although a debugger such as cuda gdb will indicate that a managed memory address is the source of the failure J 2 4 Querying Unified Memory Support J 2 4 1 Device Properties Unified Memory is supported only on devices with compute capability 3 0 or higher A program may query whether a GPU device supports managed memory by using cudaGetDeviceProperties and checking the new managedMemSupported property The capability can also be determined using the individual attribute query function cudaDeviceGetAttribute with the attribute cudaDevAttrManagedMemSupported Either property will be set to 1 if managed memory allocations are permitted on the GPU and under the current operating system Note that Unified Memory is not supported for 32 bit applications unless on Android even if a GPU is of sufficient capability J 2 4 2 Pointer Attributes To determine if a given pointer refers to managed memory a program can call cudaPointerGetAttributes and check the value of the isManaged attribute This attribute is set to 1 if the pointer refers to managed memory and
167. e Maximum width and height for a 2D surface reference bound to a CUDA 65536 x 32768 array Maximum width height and number of layers for a 2D layered surface 65536 x 32768 x 2048 reference Maximum width height and depth for a 3D surface reference bound to a 65536 x 32768 x 2048 CUDA array Maximum width and height for a cubemap surface reference bound to a 32768 CUDA array Maximum width and height and number of layers for a cubemap 32768 x 2046 layered surface reference Maximum number of surfaces that can 16 be bound to a kernel Maximum number of instructions per kernel 512 million G 2 Floating Point Standard All compute devices follow the IEEE 754 2008 standard for binary floating point arithmetic with the following deviations gt There is no dynamically configurable rounding mode however most of the operations support multiple IEEE rounding modes exposed via device intrinsics www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 207 Compute Capabilities gt There is no mechanism for detecting that a floating point exception has occurred and all operations behave as if the IEEE 754 exceptions are always masked and deliver the masked response as defined by IEEE 754 if there is an exceptional event for the same reason while SNaN encodings are supported they are not signaling and are handled as quiet gt The result of a single precision floating point operation involving one or more input
168. e device and version management sections of the reference manual One needs to keep this in mind when timing runtime function calls and when interpreting the error code from the first call into the runtime During initialization the runtime creates a CUDA context for each device in the system see Context for more details on CUDA contexts This context is the primary context for this device and it is shared among all the host threads of the application As part of this context creation the device code is just in time compiled if necessary see Just in Time Compilation and loaded into device memory This all happens under the hood and the runtime does not expose the primary context to the application When a host thread calls cudaDeviceReset this destroys the primary context of the device the host thread currently operates on i e the current device as defined in Device Selection The next runtime function call made by any host thread that has this device as current will create a new primary context for this device 3 2 2 Device Memory As mentioned in Heterogeneous Programming the CUDA programming model assumes a system composed of a host and a device each with their own separate memory Kernels operate out of device memory so the runtime provides functions to allocate deallocate and copy device memory as well as transfer data between host memory and device memory Device memory can be allocated either as linear memory or as CU
169. e specified as in the example above Each block within the grid can be identified by a one dimensional two dimensional or three dimensional index accessible within the kernel through the built in blockIdx variable The dimension of the thread block is accessible within the kernel through the built in blockDim variable www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 11 Programming Model Extending the previous MatAdd example to handle multiple blocks the code becomes as follows Kernel definition global void MatAdd float A N N float B N N float C N N ime al plockar t5 lolloel lt iDauil o lt ur threada nA ie G Dlocwichas y block Dams yay ESEC a we GL lt N ue J lt N CHi Alil Bilig int main Kernel invocation dim3 threadsPerBlock 16 16 dim3 numBlocks N threadsPerBlock x N threadsPerBlock y MatAdd numBlocks threadsPerBlock gt gt gt A B C A thread block size of 16x16 256 threads although arbitrary in this case is a common choice The grid is created with enough blocks to have one thread per matrix element as before For simplicity this example assumes that the number of threads per grid in each dimension is evenly divisible by the number of threads per block in that dimension although that need not be the case Thread blocks are required to execute independently It must be possible to execute them in any order in parallel o
170. e 1 so index 2 6 3 for example accesses the fourth face of the third cubemap 3 2 11 3 CUDA Arrays CUDA arrays are opaque memory layouts optimized for texture fetching They are one dimensional two dimensional or three dimensional and composed of elements each of which has 1 2 or 4 components that may be signed or unsigned 8 16 or 32 bit integers 16 bit floats or 32 bit floats CUDA arrays are only accessible by kernels through texture fetching as described in Texture Memory or surface reading and writing as described in Surface Memory 3 2 11 4 Read Write Coherency The texture and surface memory is cached see Device Memory Accesses and within the same kernel call the cache is not kept coherent with respect to global memory writes and surface memory writes so any texture fetch or surface read to an address that has been written to via a global write or a surface write in the same kernel call returns undefined data In other words a thread can safely read some texture or surface memory location only if this memory location has been updated by a previous kernel call or memory copy but not if it has been previously updated by the same thread or another thread from the same kernel call 3 2 12 Graphics Interoperability Some resources from OpenGL and Direct3D may be mapped into the address space of CUDA either to enable CUDA to read data written by OpenGL or Direct3D or to enable CUDA to write data for consumption by
171. e 1 as current cudaDeviceEnablePeerAccess 0 0 Enable peer to peer access with device 0 Launch kernel on device 1 This kernel launch can access memory on device 0 at address p0 MyKernel 1000 128 gt gt gt p0 3 2 6 5 Peer to Peer Memory Copy Memory copies can be performed between the memories of two different devices When a unified address space is used for both devices see Unified Virtual Address Space this is done using the regular memory copy functions mentioned in Device Memory www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 39 Programming Interface Otherwise this is done using cudaMemcpyPeer cudaMemcpyPeerAsync cudaMemcpy3DPeer or cudaMemcpy3DPeerAsync as illustrated in the following code sample cudaSetDevice 0 SSE devalce 0 as eurrent Ploae 490p Sige i gae 1024 gio leu cudaMalloc amp p0 size Allocate memory on device 0 cudaSetDevice 1 m Sert device as eCUrrent Eigar qoa cudaMalloc amp pl size Allocate memory on device 1 cudaSetDevice 0 See device OaS currence MyKernel lt lt lt 1000 128 gt gt gt p0 Launch kernel on device 0 cudaSetDevice 1 ji Sec device I as ueni cudaMemcpyPeer pl 1 pO 0 size Copy pO to pl MyKernel 1000 128 gt gt gt p1 Launch kernel on device 1 A copy in the implicit NULL stream between the memories of two different devices gt does
172. e and the full range of the integer type is mapped to 0 0 1 0 for unsigned integer type and 1 0 1 0 for signed integer type for example an unsigned 8 bit texture element with the value Oxff reads as 1 If it is cudaReadModeElementType no conversion is performed gt Whether texture coordinates are normalized or not By default textures are referenced by the functions of Texture Functions using floating point coordinates in the range 0 N 1 where N is the size of the texture in the dimension corresponding to the coordinate For example a texture that is 64x32 in size will be referenced with coordinates in the range 0 63 and 0 31 for the x and y dimensions respectively Normalized texture coordinates cause the coordinates to be specified in the range 0 0 1 0 1 N instead of 0 N 1 so the same 64x32 texture would be addressed by normalized coordinates in the range 0 1 1 N in both the x and y dimensions Normalized texture coordinates are a natural fit to some applications requirements if it is preferable for the texture coordinates to be independent of the texture size gt The addressing mode It is valid to call the device functions of Section B 8 with coordinates that are out of range The addressing mode defines what happens in that case The default addressing mode is to clamp the coordinates to the valid range 0 N for non normalized coordinates and 0 0 1 0 for normalized coordinates If the border mode is speci
173. e compiler generated constructor function Derived Derived will be treated asa device function since it is invoked only from the device function foo The compiler generated constructor function Other Other will be treated as a host device function since it is invoked both from a device function foo anda host function bar E 2 9 3 Function Parameters global function parameters are passed to the device via constant memory and are limited to 4 KB device and global functions cannot have a variable number of arguments www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 180 C C Language Support E 2 9 4 Static Variables within Function Within the body ofa device or global function only shared variables may be declared with static storage class E 2 9 5 Function Pointers The address ofa global function taken in host code cannot be used in device code e g to launch the kernel Similarly the address of a global function taken in device code cannot be used in host code It is not allowed to take the address of a device function in host code E 2 9 6 Function Recursion global functions do not support recursion E 2 10 Classes E 2 10 1 Data Members Static data members are not supported The layout of bit fields in device code may currently not match the layout in host code on Windows E 2 10 2 Function Members Static member functions cannot be global functions E 2 10 3 Virt
174. e created in the managed memory space and so will not be accessible to CPU code www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 236 Unified Memory Programming J 2 1 2 Global Scope Managed Variables Using _ managed __ File scope and global scope CUDA __device___ variables may also opt in to Unified Memory management by adding anew __managed___ annotation to the declaration These may then be referenced directly from either host or device code as follows Bide cen anag CENE EE IE Cayce __iileimeryecl me y EEolcbo EE veuclikemneu Sb 220 an x int main x 0 3 wy 5p kernel 1 1 gt gt gt cudaDeviceSynchronize printf result d n x 1 serten Op All semantics of the original __device__ memory space along with some additional unified memory specific constraints are inherited by the managed variable See Compilation with NVCC in the CUDA C Programming Guide for details Note that variables marked __constant__ may not also be marked as managed this annotation is reserved for device variables only Constant memory must be set either statically at compile time or by using cudaMemcpyToSymbol as usual in CUDA J 2 2 Coherency and Concurrency J 2 2 1 GPU Exclusive Access To Managed Memory To ensure coherency the Unified Memory programming model puts constraints on data accesses while both the CPU and GPU are executing concurrently In effect the GPU has excl
175. e for correctly populating all necessary data structures in the correct format according to specification Backwards compatibility is guaranteed in these data structures As with host side launch the device side operator lt lt lt gt gt gt maps to underlying kernel launch APIs This is so that users targeting PTX will be able to enact a launch and so that the compiler front end can translate lt lt lt gt gt gt into these calls Table 4 New Device only Launch Implementation Functions Description of Difference From Host Runtime Behaviour behaviour is identical if Runtime API Launch Functions no description cudaGetParameterBuffer Generated automatically from lt lt lt gt gt gt Note different API to host equivalent cudaLaunchDevice Generated automatically from lt lt lt gt gt gt Note different API to host equivalent The APIs for these launch functions are different to those of the CUDA Runtime API and are defined as follows xtern devic cudaError t cudaGetParameterBuffer void params xtern devic cudaError t cudaLaunchDevice void kernel zx void params dim3 gridDim dim3 blockDim unsigned int sharedMemSize 0 cudaStream t stream 0 C 3 1 8 API Reference The portions of the CUDA Runtime API supported in the device runtime are detailed here Host and device runtime APIs have identical syntax semantics are the same except where indicated The table below provides an overview
176. e these types are always aligned on a two word boundary CUdeviceptr is an integer but represents a pointer so its alignment requirement is alignof void The following code sample uses a macro ALIGN UP to adjust the offset of each parameter to meet its alignment requirement and another macro ADD TO PARAM BUFFER to add each parameter to the parameter buffer passed to the CU LAUNCH PARAM BUFFER POINTER option define ALIGN UP offset alignment offset offset alignment 1 amp alignment 1 char paramBuffer 1024 size t paramBufferSize 0 define ADD TO PARAM BUFFER value alignment deo 4 paramBufferSize ALIGN UP paramBufferSize alignment memcpy paramBuffer paramBufferSize amp value sizeof value paramBufferSize sizeof value hile 0 EU OO Suum vorm D TO PARAM BUFFER i alignof i oat4 4 D TO PARAM BUFFER f4 16 float4 s alignment is 16 Bue ug D TO PARAM BUFFER c X alignof c GEE dE D TO PARAM BUFFER f X alignof f deviceptr devPtr D TO PARAM BUFFER devPtr X alignof devPtr Ga t2 TE D TO PARAM BUFFER f2 8 float2 s alignment is 8 Se Sa SS ae Sis eis iia le e den de void extra CU LAUNCH PARAM BUFFER POINTER paramBuffer CU LAUNCH PARAM BUFFER SIZE amp paramBufferSize CU LAUNCH PARAM END un cuLaunchKernel cuFunction blockWidth block
177. e width of the thread block and the width of the array must be a multiple of the warp size In particular this means that an array whose width is not a multiple of this size will be accessed much more efficiently if it is actually allocated with a width rounded up to the closest multiple of this size and its rows padded accordingly The cudaMallocPitch and cuMemAllocPitch functions and associated memory copy functions described in the reference manual enable programmers to write non hardware dependent code to allocate arrays that conform to these constraints Local Memory Local memory accesses only occur for some automatic variables as mentioned in Variable Type Qualifiers Automatic variables that the compiler is likely to place in local memory are gt Arrays for which it cannot determine that they are indexed with constant quantities gt Large structures or arrays that would consume too much register space gt Any variable if the kernel uses more registers than available this is also known as register spilling Inspection of the PTX assembly code obtained by compiling with the ptx or keep option will tell if a variable has been placed in local memory during the first compilation phases as it will be declared using the local mnemonic and accessed using the 1d 1ocal and st 1local mnemonics Even if it has not subsequent compilation phases might still decide otherwise though if they find it consumes too much register space
178. eads the CUDA array bound to the two dimensional surface reference surfRef using coordinates x and y B 9 2 4 surf2Dwrite template class Type void surf3Dwrite Type data surface lt void cudaSurfaceType3D gt surfRef IMG Sep Mie Wp ae A5 boundaryMode cudaBoundaryModeTrap writes value data to the CUDA array bound to the two dimensional surface reference surfRef at coordinate x and y www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 114 C Language Extensions B 9 2 5 surf3Dread template lt class Type Type surf3Dread surface lt void cudaSurfaceType3D gt surfRef GONE 25 Ine wen aum vp boundaryMode cudaBoundaryModeTrap template class Type void surf3Dread Type data surface lt void cudaSurfaceType3D gt surfRef WMG xp ugue Svo ASME A boundaryMode cudaBoundaryModeTrap reads the CUDA array bound to the three dimensional surface reference surfRef using coordinates x y and z B 9 2 6 surf3Dwrite template lt class Type void surf3Dwrite Type data surface lt void cudaSurfaceType3D gt surfRef aaie 3 SLE Wp Aime wa boundaryMode cudaBoundaryModeTrap writes value data to the CUDA array bound to the three dimensional surface reference surfRef at coordinate x y and z B 9 2 7 surfiDLayeredread template lt class Type gt Type surflDLayeredread surface void cudaSurfaceTypelDLayered surfRef age 3X aloe layer boundaryMode cudaBoundaryMo
179. ecca eoo bs oa Tc float loer Che itleeu2 eh fetches from the CUDA array specified by the two dimensional texture object texObj using texture coordinate x y The level of detail is derived from the dx and dy gradients B 8 1 8 tex3D template class T tees reuceaime apumeobsec ceo 9 bp aes LOd CEMETERIES fetches from the CUDA array specified by the three dimensional texture object texObj using texture coordinate x y z B 8 1 9 tex3DLod template class T D 1EESKSUDIL CrCl cudererture0o ect MM eo ENEMIES oc ME MENU MR ST M fetches from the CUDA array or the region of linear memory specified by the three dimensional texture object texOb using texture coordinate x y z at level of detail level B 8 1 10 tex3DGrad template class T Ttesoperacicudaiexiuuieobsectae Ceo loet xy loei yy leet Zp Eloac4 Cbe BloacA CW fetches from the CUDA array specified by the three dimensional texture object texObj using texture coordinate x y z ata level of detail derived from the X and Y gradients dx and dy B 8 1 11 tex1DLayered template class T etes esseciteuctamessuumebe ci ee proc Mm MEI ESTE NT fetches from the CUDA array specified by the one dimensional texture object texObj using texture coordinate x and index layer as described in Layered Textures B 8 1 12 tex1DLayeredLod template class T T texlDLayeredLod cudaTextureObject t texObj float x int layer float level
180. ed constexpr and that does not have execution space annotations e g device constant shared V is considered to be a host code variable If V is of scalar type 13 other than long double the value of V can be directly used in device code In addition the value of V can be used inside a constexpr device or host device function if the call to the function is a constant expression 1a Device source code cannot contain a reference to V or take the address of V Example constexpr int xxx 10 constexpr int yyy xxx 4 simuce Sul gratie CONSTE ame Cee dp F7 exomsesp ra amie MORE ariel 1 2 Sie Conste Cevics lmr gerame cios recura Dost erelickila p Cees iat FOO ime Lebe 1 int vl xxx yyy S1 t qqq OK const int amp v2 xxx a error reference to host constexpr variable const int v3 amp xxx error address of host constexpr variable const int amp v4 ST t qqq error reference to host constexpr variable Const aime ew Sil cs SII error address of host constexpr variable Wi t gerla H MOK eene 2 e a Conan expression vl get idx Becas usa Get ics EI Sam OE a GIO Stealth expression Wil r host elie 2 pg error host arr does not have i Se alla type return vil E 2 14 6 Inline namespaces For an input CUDA translation unit the CUDA compiler may invoke the host compiler for compiling the host code within the transla
181. ed int i 0 adapter i if FAILED factory gt EnumAdapters i amp adapter break if cudaD3D10GetDevice amp dev adapter cudaSuccess break adapter gt Release factory Release Create swap chain and device D3D10CreateDeviceAndSwapChain adapter D3D10 DRIVER TYPE HARDWARE D3D10 CREATE DEVICE DEBUG D3D10 SDK VERSION amp swapChainDesc amp swapChain amp device adapter Release Use the same devic cudaSetDevice dev Create vertex buffer and register it with CUDA unsigned int size width height sizeof CUSTOMVERTEX D3D10 BUFFER DESC bufferDesc butterDese Usage D3D10 USAGE DEFAULT bufferDesc ByteWidth size bufferDesc BindFlags D3D10 BIND VERTEX BUFFER bufferDesc CPUAccessFlags 0 bufferDesc MiscFlags 0 device gt CreateBuffer amp bufferDesc 0 amp positionsVB cudaGraphicsD3D10RegisterResource amp positionsVB CUDA positionsVB 0 cudaGraphicsRegisterFlagsNone cudaGraphicsResourceSetMapFlags positionsVB CUDA cudaGraphicsMapFlagsWriteDiscard Launch rendering loop vusatike ess di Render www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 62 Programming Interface void Render Map vertex buffer for writing from CUDA float4 positions cudaGraphicsMapResources 1 amp positionsVB CUDA 0 size t num bytes cudaGraphicsResourceGetMappedPointer voi
182. ed long long int val reads the 32 bit or 64 bit word old located at the address address in global or shared memory computes old compare val old and stores the result back to memory at the same address These three operations are performed in one atomic transaction The function returns old Compare And Swap B 12 2 Bitwise Functions B 12 2 1 atomicAnd int atomicAnd int address int val unsigned int atomicAnd unsigned int address unsigned int val unsigned long long int atomicAnd unsigned long long int address unsigned long long int val reads the 32 bit or 64 bit word old located at the address address in global or shared memory computes old amp val and stores the result back to memory at the same address These three operations are performed in one atomic transaction The function returns old www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 120 C Language Extensions The 64 bit version of atomicAnd is only supported by devices of compute capability 3 5 and higher B 12 2 2 atomicOr Huge acon cornine Eyeleheesic sue welll A unsigned int atomicOr unsigned int address unsigned int val unsigned long long int atomicOr unsigned long long int address unsigned long long int val reads the 32 bit or 64 bit word old located at the address address in global or shared memory computes old val and stores the result back to memory at the same address These three operation
183. ee dede meds 197 E 5 1 Data Aggregation Class orent ht eere S nitent a sais ea a pe Rae vk ae ea vane en i 197 E 5 2 Derived Class iiccacciawecssesa 197 E93 Class Template i deeds eo eee tt n tut otto moe b st eki rd etue tack eh nastebontecsoedsatatea sees 198 E 5 4 Function Template cocos eee ear et nr e ides RE n err e EE e TER e PER e EE eee 198 E 5 5 F nctor Classics tiet n Ehren ke ORERE ANERER ENER EEREN 199 Appendix F Texture Fetching 5 2 2d dozens e espe RA Pda Cp a cba ed Essa e sepa de gEaae Tied 200 F 1 Nearest Point Sampling cesceeeeeeeeeeeeeeeeeeee eene he enne etn ethernet eene nnns 200 26 Linear Filtering x2 m 201 FS EISE co Do 202 Appendix G Compute Capabilities ceeecceeeeeeeeee eese eese nennen nennen enne 204 G 1 Features and Technical Specifications ccc ece cece cece eee e eects ee eeeeeee eee eeeeeeeees 204 G 2 Floating Point Standard i c eret nett eienen erce oiee a nese sant 207 G 3 Compute Capability Z Xisccicsavesesncsacascssivaensesads AENEAN OEREN EKAA ETRA E ENEA E 208 cm PE eui nm 208 G 3 2 Global Memory s ressort nre iph n e ER Ee ERE RREEERS SERES PUARES thine seus ees ear RR EE REN Ves 210 G 3 3 Shared Memory iet rioekin aenn EEEE EDINE x OR ER SERE R ERVRUR KCN HE ENFIN UM SER 211 G 3 4 Constant Memory ise essen isiti RR a ex E REREREERERRRSRRNRE ERR ERR EE ERIR E RRK PES ERR US 212 G
184. eeeeeeeeenes 72 5 2 Maximize Utilization soie eee ra lr etae OR eer ERR CR ESI SENA ER EE ES ERN TE EE OL EUER 72 5 21 Application Level eot sends e eroe eue eae heads e pt pe eee eoe E devo aU e eere 72 5 2 2 Device Level ceases eoe eee ash beakeneses shen abinnsas tie m ERES RERAL IN Fe Ert a RERO TRE 73 5 2 3 Multiprocessor Level curetur px n odes neues AEE dre dure UR NM EE und IE sS 73 5 2 3 1 Occupancy Calc lator ener eren o teen rex enin e ax alex Ile eai nr es a a 75 5 3 Maximize Memory Throughput cssesseeeeeeeeeee eee ehh hehe ehh eher 77 5 3 1 Data Transfer between Host and Device ceessessseesseeeseee eee 78 5 3 2 Device Memory ACC6SSeS cei eee eere eere nite rao see iieis ts rne es Vrae e tae arae a E ra 79 5 4 Maximize Instruction ThroughpUut ccececc cence ce eee eee eee enhn enne 83 54 1 Arithmetic Instructions eere eoe se te ree ha eos oapt Yo eot eue x Ea Ee En FeREREE FEET E PEE RUE 83 5 4 2 Control Flow Instructions csv eseeeene otro rro Ete rn n rh wee nani nal E n aai e re i Vai eases 87 5 4 3 Synchronization Instruction ceseesseesseesseesseeeee eee hee he hene enne 88 Appendix A CUDA Enabled GPUSs 1 ceres casera essai sara ocaeca sees ceecseecase ees 89 Appendix B C Language Extensions ccsccssccsscessccscccsccescscssccscescccsssesssssscesecesees 90 B 1 Function Type Qualifiers eeesseeeeeseeeeeeeee eene hne
185. een EloatiGeumikemenia Comsiey Mate METER EO return A elements row A stride col Set a matrix element _ cevice vori gertilenent Werriz A inme Ow ime COl float value A elements row A stride col value Get the BLOCK SIZExBLOCK SIZE sub matrix Asub of A that is located col sub matrices to the right and row sub matrices down from the upper left corner of A device Matrix GetSubMatrix Matrix A int row int col Matrix Asub Asub width BLOCK SIZE Asub height BLOCK SIZE Asub stride A ral A stride Asub elements amp A elements A stride BLOCK SIZ BLOCK SIZI row io e al MEC eal EET return Asub Thread block size define BLOCK SIZE 16 Forward declaration of the matrix multiplication kernel global void MatMulKernel const Matrix const Matrix Matrix Matrix multiplication Host code Matrix dimensions are assumed to be multiples of BLOCK SIZ void MatMul const Matrix A const Matrix B Matrix C E Load A and B to device memory Matrix d A d A width d A stride A width d A height A height gize Size A wieta Aaingungime Sizer Elet cudaMalloc amp d A elements size cudaMemcpy d A elements A elements size cudaMemcpyHostToDevice Matrix d B d B width d B stride B width d B height B height size Bi vidth AB heirghe CULexexexs Toat www nvidia
186. emory cudaMemcpyToArray cuInputArray 0 0 h data size cudaMemcpyHostToDevice Bind the arrays to the surface references cudaBindSurfaceToArray inputSurfRef cuInputArray cudaBindSurfaceToArray outputSurfRef cuOutputArray Invoke kernel dim3 dimBlock 16 16 dim3 dimGrid width dimBlock x 1 dimBlock x height dimBlock y 1 dimBlock y copyKernel lt lt lt dimGrid dimBlock width height Free device memory cudaFreeArray culInputArray cudaFreeArray cuOutputArray return 0 3 2 11 2 3 Cubemap Surfaces Cubemap surfaces are accessed usingsurfCubemapread and surfCubemapwrite surfCubemapread and surfCubemapwrite as a two dimensional layered surface i e using an integer index denoting a face and two floating point texture coordinates addressing a texel within the layer corresponding to this face Faces are ordered as indicated in Table 1 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 55 Programming Interface 3 2 11 2 4 Cubemap Layered Surfaces Cubemap layered surfaces are accessed using surfCubemapLayeredread and surfCubemapLayeredwrite surfCubemapLayeredread and surfCubemapLayeredwrite as a two dimensional layered surface i e using an integer index denoting a face of one of the cubemaps and two floating point texture coordinates addressing a texel within the layer corresponding to this face Faces are ordered as indicated in Tabl
187. emory can change the way in which host code is written First a simple program written without the benefit of unified memory olose voLi Apilvusd ime UC UMEN EE EE NE E ret threadlIdx x a b threadIdx x int main abge ASEA cudaMalloc amp ret 1000 sizeof int MODES KK ab 1000 See teic 10 3590 E Hne aose rer ine Sy nedblbexe LOO cibeaetoxE ame 9 cudaMemcpy host ret ret 1000 sizeof int cudaMemcpyDefault iesus e Gic dL 0 g als printf d A B d n i host ret i free host ret cudaFree ret return 0 This first example combines two numbers together on the GPU with a per thread ID and returns the values in an array Without managed memory both host and device side storage for the return values is required host_ret and ret in the example as is an explicit copy between the two using cudaMemcpy Compare this with the Unified Memory version of the program which allows direct access of GPU data from the host Notice the new cudaMallocManaged routine which returns a pointer valid from both host and device code This allows ret to be www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 233 Unified Memory Programming used without a separate host_ret copy greatly simplifying and reducing the size of the program glosal veiri Aol lime mee aisle ay amie ME ret threadlIdx x a b threadIdx x int main Sige SASEA cudaMallocManaged
188. emplate lt template lt typename gt class Wrapper typename Pack gt global void fool Wrapper lt Pack gt error pack parameter is not last in parameter list template typename Pack template lt typename gt class Wrapper gt global void foo2 Wrapper lt Pack gt error multiple parameter packs template lt typename Packl int Pack2 template lt typename gt class Wrapperl template lt int gt class Wrapper2 gt __global__ void foo3 Wrapperl Packl Wrapper2 lt Pack2 gt www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 188 C C Language Support E 2 14 9 device constant shared variables device constant and shared variables cannot be marked with the keyword constexpr and cannot have rvalue reference type E 3 Polymorphic Function Wrappers A polymorphic function wrapper class template nvstd function is provided in the nvfunctional header Instances of this class template can be used to store copy and invoke any callable target e g lambda expressions The operator for instances of nvstd functionisa device function and can therefore be invoked only from device code Example include lt nvfunctional gt ccu cc void too oglosel voici fe 1 Assign address of device Tm esteso nvstd function void fnl foo n ianvoke auco lambda NT Cne S returni OMIE Assign lambda closure objec
189. er cannot issue any instruction A warp scheduler can issue an instruction to only half of the CUDA cores To execute an instruction for all threads of a warp a warp scheduler must therefore issue the instruction over two clock cycles for an integer or floating point arithmetic instruction A multiprocessor also has a read only constant cache that is shared by all functional units and speeds up reads from the constant memory space which resides in device memory There is an L1 cache for each multiprocessor and an L2 cache shared by all multiprocessors both of which are used to cache accesses to local or global memory including temporary register spills The cache behavior e g whether reads are cached in both L1 and L2 or in L2 only can be partially configured on a per access basis using modifiers to the load or store instruction The same on chip memory is used for both L1 and shared memory It can be configured as 48 KB of shared memory and 16 KB of L1 cache or as 16 KB of shared memory and 48 KB of L1 cache using cudaFuncSetCacheConfig cuFuncSetCacheConfig Device code Guieisedl vorc Miyiermeul Gime Io duoi loue cum m Host code Runtime API cudaFuncCachePreferShared shared memory is 48 KB cudaFuncCachePreferLl shared memory is 16 KB cudaFuncCachePreferNone no preference cudaFuncSetCacheConfig MyKernel cudaFuncCachePreferShared Or via a function pointer Nube sz biMel Ee si
190. er to be executed by the CUDA driver when appropriate device resources are available This relieves the host thread of much of the responsibility to manage the device leaving it free for other tasks The following device operations are asynchronous with respect to the host Kernel launches Memory copies within a single device s memory Memory copies from host to device of a memory block of 64 KB or less Memory copies performed by functions that are suffixed with Async gt Memory set function calls v v v y Programmers can globally disable asynchronicity of kernel launches for all CUDA applications running on a system by setting the CUDA_LAUNCH_BLOCKING environment variable to 1 This feature is provided for debugging purposes only and should not be used as a way to make production software run reliably Kernel launches are synchronous if hardware counters are collected via a profiler Nsight Visual Profiler unless concurrent kernel profiling is enabled Async memory copies will also be synchronous if they involve host memory that is not page locked 3 2 5 2 Concurrent Kernel Execution Some devices of compute capability 2 x and higher can execute multiple kernels concurrently Applications may query this capability by checking the concurrentKernels device property see Device Enumeration which is equal to 1 for devices that support it The maximum number of kernel launches that a device can execute concurrently depends on it
191. erands i e arithmetic instructions most of the time to the number of instructions with off chip memory operands is low this ratio is commonly called the arithmetic intensity of the program For example assume this ratio is 30 also assume the latencies are 600 cycles on devices of compute capability 2 x and 300 cycles on devices of compute capability 3 x Then about 20 warps are required for devices of compute capability 2 x and about 40 for devices of compute capability 3 x with the same assumptions as in the previous paragraph Another reason a warp is not ready to execute its next instruction is that it is waiting at some memory fence Memory Fence Functions or synchronization point Memory Fence Functions A synchronization point can force the multiprocessor to idle as more and more warps wait for other warps in the same block to complete execution of instructions prior to the synchronization point Having multiple resident blocks per multiprocessor can help reduce idling in this case as warps from different blocks do not need to wait for each other at synchronization points The number of blocks and warps residing on each multiprocessor for a given kernel call depends on the execution configuration of the call Execution Configuration the memory resources of the multiprocessor and the resource requirements of the kernel as described in Hardware Multithreading Register and shared memory usage are reported by the compiler when comp
192. es Let V denote a namespace scope variable or a class static member variable that has const qualified type and does not have execution space annotations e g __ device_ __constant__ __shared_ V is considered to be a host code variable The value of V may be directly used in device code if gt Vhas been initialized with a constant expression before the point of use and gt it has one of the following types gt builtin floating point type except when the Microsoft compiler is used as the host compiler gt builtin integral type Device source code cannot contain a reference to V or take the address of V Example conse Ine xo 10 semuce Sil statie Const ame yyy 207 8 extern const int zzz const float www 5 0 ENdeviceNNE voco o ONE int locall xxx OK time Jiexoeudl2 sil ies 801 OK int vall xxx TROR int val2 S1 t yyy OK ime vals AB JL errors m27 woe algbeupstlbatrzieyol walii CONS ta nit expression at the point of use const int amp val3 xxx error reference to host variable const int val4 amp xxx error address of host variable const float val5 www OK except when the Microsoft compiler is used as the host compiler conse Ine zz2 gt 20 E 2 14 C 11 Features C 11 features that are enabled by default by the host compiler are also supported by nvcc subject to the restrictions described in this document In addition invoking nvcc with std c
193. es abis GWEEHUESHO ee ula eA HEROS SisGUC Gao wh 4 dime Ereld Sil twoich m siecle d Pg he Seiler SZ ic sS ie veel dX soos cds j Sil t tempi error use of managed variable xxx in dynamic initialization S2 t temp2 exror use of managed variable x xxx in the destructor of object with static storage duration cewouge mencged const ime yyy dp erroz Creme guednraee type cevice mencgeel lie ZZA ezp error reference type ipemusllenue lt imte exelehe Ser Uee Sic iP S3 t amp xxx temp error address of managed variable xxx not a constant expression Bolo ai vocem SS i assert ptr amp xxx OK noe M Hi Que int main void int ptr amp xxx MIROR kern lt lt lt 1 1 gt gt gt ptr cudaDeviceSynchronize xxxtt OK decltype xxx qqq error managed variable xxx used as unparenthized argument to decltype decltype xxx zzz yyy LE MOK E 2 3 3 Volatile Qualifier The compiler is free to optimize reads and writes to global or shared memory for example by caching global reads into registers or L1 cache as long as it respects the memory ordering semantics of memory fence functions Memory Fence Functions and memory visibility semantics of synchronization functions Synchronization Functions These optimizations can be disabled using the volatile keyword If a variable located in global or shared memory i
194. es of various compute capabilities Table 2 Throughput of Native Arithmetic Instructions Number of Operations per Clock Cycle per Multiprocessor www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 83 Performance Guidelines Compute Capability 16 bit floating point add multiply multiply add 32 bit floating point add multiply multiply add 64 bit floating point add multiply multiply add 32 bit floating point reciprocal reciprocal square root base 2 logarithm __log2 base 2 exponential exp2f sine __sinf cosine cosf 32 bit integer add extended precision add subtract extended precision subtract 32 bit integer multiply multiply add extended precision multiply add 24 bit integer multiply Multiple Multiple Multiple Multiple Multiple Multiple 7 u mu124 instructions instructions instructions instructions instructions instructions compare minimum maximum 32 bit integer bit reverse bit field extract insert 32 bit bitwise AND OR Bw mEIb 91x count of leading zeros most significant non 16 16 32 32 Multiple Multiple sign bit instructions instructions E a warp shuffle warp shuffle sum of absolute difference SIMD video instructions Multiple Multiple vabsdiff2 instructions instructions 4 for GeForce GPUs 8 for GeForce GPUs 32 for GeForce GPUs Multiple Multiple instructions instructions www nvidia com CUDA C Progr
195. es vein er wes T Yo VIO V Me v Ne DT Dad 132 B 18 3 1 Per Thread Allocation eeseeeeeeeeeeeeeeee ee enne 132 B 18 3 2 Per Thread Block Allocation ceeeeeeeeeeee eene nnne enhn 133 B 18 3 3 Allocation Persisting Between Kernel Launches eee esee 134 B 19 Execution Confis ration ierit hes nro n ree RP X ex Fel ERE CS EA E a E eR enr es 135 B 20 Launch Bounds oue vescovo seo reto ve eser OR ve b pe v EEA du Vve tuv NERA Ye eeu Uu vei vae 135 B 21 Zpragma UNO loss esie euer or eret eren e EE aer RY E n Ea ties ee ke E xE VERE Cina oth 138 B 22 SIMD Video Instr ctiOris oon eta n deme er re AIEA nexu ce ga Rees Nd xr xN M Hus x RE 138 Appendix C CUDA Dynamic Parallelism ceeeeeee eese eee nennen 140 Lon PM INC FOUUCTIONS TEE ER 140 Cal Te OVEVIEW Rr P 140 C 1 2 GOSSA Nienna aiee a aeaa eaaa 140 C 2 Execution Environment and Memory Model esesssssssssssssssssssssssssssssssessessseseen 141 C 2 1 Execution EnvirOnMent ccccccssccccssesccsccccssesscceeescssescsssssssseesosossesseereees 141 C 2 1 1 Parent and Child Grids leeeeeeeeeeeeeeeeee eene enne 141 C 2 1 2 Scope of CUDA Primitives cccccccsceeenscsececcceenessaeeeseecseeceeeaaensaenees 142 C 2 1 3 Synchronization rore ere tene lerne ba Sartre te nea nt ne ERR eid a Reifen 142 C 2 1 4 Streams and Events ecc eoe cree cone aes o ee qe ege e ees eres eoe reus
196. essseeesseeeeseseee eee enhn nnne enne enne 103 B 8 1 17 texCubemap eode ener te Rede ee eei venire cue e dee con OON Eee eU UR ante de 103 B 8 1 18 texCubemapLod ceeeeeeeeeeeeeeeee eee VEEE NARESE ehh nnns eere 103 B 8 1 19 texCubemapLayered scecscccccscccenceenecssecsncscaeesaeesesesssencescaeeanesess 104 B 8 1 20 texCubemapLayeredLod ecceece ee eeee eee ence ence eee eene eene hene 104 B 8 1 21 tex2Deather cerit ette tere re e Ree te eO IRP ete e re eU Re e rei tee 104 B 8 2 Texture Reference API eeesseeeeeeeeeeeeeee ehe enne hh ehh ense hene hee 105 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 v B 8 2 1 texTlDfetch iers rereana bean dade eI be dhsesedadans PUR RR ERAS Qe ge e REPRE 105 LEAD C IPIE 105 B 3 2 3 texiDLOd OT 106 B 8 2 4 tex1DGrad EE E IE E E AEN A E E EE TE 106 eA PA e EEE E A A 106 B 8 2 6 tex2DLOd isiascccseccciescdates eee tre TEE EEEE EEANN E ahs 106 B 8 2 7 SDE E OE EA DR eR EN TO E MAD E EEE EE 106 UNS EC GIU EEE AEE EEEE NEEE EEE EEEE 107 B 8 2 9 tex3DLod iii eoseee see teu ee EAEE SEERNES NE ENEN EEEE 107 B 8 2 10 tex3DGrad si essi ku EAEN a Ue AER E rer bp rera AEEA E QU DA EX RDONDU MES 107 B 8 2 11 tex1DEayered s sore voee rta LieR repe tU EE UN D UP YariPYI e ER rape er bia ve 107 B 8 2 12 tex1DLayeredLod eeessseeeeeeeeeeee eene nene he nnne ern 108 B 8 2 13 textDLayeredGrad
197. evice _ declares a variable that gt Resides in constant memory space gt Has the lifetime of an application gt Is accessible from all the threads within the grid and from the host through the runtime library cudaGetSymbolAddress cudaGetSymbolSize cudaMemcpyToSymbol cudaMemcpyFromSymbol B 2 3 shared The shared qualifier optionally used together with device declaresa variable that gt Resides in the shared memory space of a thread block gt Has the lifetime of the block gt Is only accessible from all the threads within the block When declaring a variable in shared memory as an external array such as CxECr DERS naned reload Mares the size of the array is determined at launch time see Execution Configuration All variables declared in this fashion start at the same address in memory so that the layout of the variables in the array must be explicitly managed through offsets For example if one wants the equivalent of short array0 128 float arrayl 64 Suge array2 256 in dynamically allocated shared memory one could declare and initialize the arrays the following way Eaten ehbherecl as even Arran cervices voad fane iy O Gewis Os Gilas Cuneirion shore arrayO short array float arrayl float amp array0 128 alise array2 int amp array1 64 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 92 C Language Extensions Note that
198. example Host code MyKernel blocksPerGrid THREADS PER BLOCK gt gt gt gt Or at runtime based on the compute capability Host code cudaGetDeviceProperties amp deviceProp device int threadsPerBlock deviceProp major gt 2 2 THREADS PER BLOCK THREADS PER BLOCK MyKernel lt lt lt blocksPerGrid threadsPerBlock gt gt gt Register usage is reported by the ptxas options v compiler option The number of resident blocks can be derived from the occupancy reported by the CUDA profiler see Device Memory Accessesfor a definition of occupancy Register usage can also be controlled for all global functions in a file using the maxrregcount compiler option The value of maxrregcount is ignored for functions with launch bounds www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 137 C Language Extensions B 21 pragma unroll By default the compiler unrolls small loops with a known trip count The pragma unroll directive however can be used to control unrolling of any given loop It must be placed immediately before the loop and only applies to that loop It is optionally followed by a number that specifies how many times the loop must be unrolled For example in this code sample pragma unroll 5 itowe e ak Up 3L lt lt Jap araa the loop will be unrolled 5 times The compiler will also insert code to ensure correctness in the example ab
199. f output takes place on the host system This means that the format string must be understood by the host system s compiler and C library Every effort has been made to ensure that the format specifiers supported by CUDA s printf function form a universal subset from the most common host compilers but exact behavior will be host OS dependent As described in Format Specifiers printf will accept all combinations of valid flags and types This is because it cannot determine what will and will not be valid on the host system where the final output is formatted The effect of this is that output may be undefined if the program emits a format string which contains invalid combinations The printf command can accept at most 32 arguments in addition to the format string Additional arguments beyond this will be ignored and the format specifier output as is Owing to the differing size of the long type on 64 bit Windows platforms four bytes on 64 bit Windows platforms eight bytes on other 64 bit platforms a kernel which is compiled on a non Windows 64 bit machine but then run on a win64 machine will see corrupted output for all format strings which include 1d It is recommended that the compilation platform matches the execution platform to ensure safety www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 128 C Language Extensions The output buffer for printf is set to a fixed size before kernel launch see Associated Hos
200. f them any predicate Evaluate predicate for all active threads of the warp and return non zero if and only if predicate evaluates to non zero for any of them www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 121 C Language Extensions ballot predicate Evaluate predicate for all active threads of the warp and return an integer whose Nth bit is set if and only if predicate evaluates to non zero for the Nth thread of the warp and the Nth thread is active Notes For each of these warp vote operations the result excludes threads that are inactive e g due to warp divergence Inactive threads are represented by 0 bits in the value returned by ballot and are not considered in the reductions performed by a11 and any B 14 Warp Shuffle Functions Shfl shfl up shfl down shfl xor exchange a variable between threads within a warp Supported by devices of compute capability 3 x B 14 1 Synopsis Ae Sse ime Wee dione srele aoe walcheli welicasalvAxS 9 int shfl_up int var unsigned int delta int width warpSize int shfl down int var unsigned int delta int width warpSize gre shfl xor int var int laneMask int width warpSize SENE shfl float var int srcLane int width warpSize float shfl up float var unsigned int delta int width warpSize float shfl down float var unsigned int delta int width warpSize float shfl xor float var int laneMask int width warpSize
201. f this feature if it has been implemented for device code Table 11 C 11 Language Features Available C 11 in nvcc Proposal device code Language Feature Rvalue references for this N2439 Initialization of class objects by rvalues N1610 9 e g the lt lt lt gt gt gt syntax for launching kernels www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 171 C C Language Support Available C 11 in nvcc Proposal device code N2764 Forward declarations for enums 7 0 DR1206 Language Feature www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 172 C C Language Support Available C 11 in nvcc Proposal device code N2253 Extending sizeof 7 0 DR850 Explicit virtual overrides Minimal support for garbage collection and reachability based leak N A see i N2670 Hn detection Restrictions Allowing move constructors to throw noexcept N3050 Defining move special member functions N3053 Language Feature Concurrency fearon Roniewpeatos Me BwmcmpremiBduge Wm B 7 Mm A a Parr epenera oraes son anero e memes 0 MS T Morane wensgntendes MEL mwWeeazwae 0 a memi eret Wanurey Was www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 173 C C Language Support Available C 11 in nvcc Language Feature Proposal device code Extended integral types E 2 Restrictions E 2 1 Host Compiler Extension
202. fied instead texture fetches with out of range texture coordinates return zero For normalized coordinates the warp mode and the mirror mode are also available When using the wrap mode each coordinate x is converted to frac x x floor x where floor x is the largest integer not greater than x When using the mirror mode each coordinate x is converted to frac x if floor x is even and 1 frac x if floor x is odd The addressing mode is specified as an array of size three whose first second and third elements specify the addressing mode for the first second and third texture coordinates respectively the addressing mode are cudaAddressModeBorder cudaAddressModeClamp cudaAddressModeWrap and cudaAddressModeMirror cudaAddressModeWrap and cudaAddressModeMirror are only supported for normalized texture coordinates gt The filtering mode which specifies how the value returned when fetching the texture is computed based on the input texture coordinates Linear texture filtering may be done only for textures that are configured to return floating point data It performs www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 43 Programming Interface low precision interpolation between neighboring texels When enabled the texels surrounding a texture fetch location are read and the return value of the texture fetch is interpolated based on where the texture coordinates fell between the texels Simple linear interpolation is performed f
203. float4 texiDfetch texture uchar4 cudaTextureTypelD cudaReadModeNormalizedFloat texRef TNE X fetches from the region of linear memory bound to texture reference texRef using texture coordinate x B 8 2 2 tex1D template lt class DataType enum cudaTextureReadMode readMode gt Type texlD texture DataType cudaTextureTypelD readMode gt texRef TOENE x9 p fetches from the CUDA array bound to the one dimensional texture reference texRef using texture coordinate x Type is equal to DataType except when readMode is equal to cudaReadModeNormalizedFloat see lexture Reference API in which case Type is equal to the matching floating point type www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 105 C Language Extensions B 8 2 3 tex1DLod template lt class DataType enum cudaTextureReadMode readMode gt Type texlDLod texture DataType cudaTextureTypelD readMode gt texRef float x float level fetches from the CUDA array bound to the one dimensional texture reference texRef using texture coordinate x The level of detail is given by level Type is the same as DataType except when readMode is cudaReadModeNormalizedFloat see Texture Reference API in which case Type is the corresponding floating point type B 8 2 4 tex1DGrad template lt class DataType enum cudaTextureReadMode readMode gt Type texlDGrad texture DataType cudaTextureTypelD readMode gt texRef float x gloei Che
204. for data transfers between host and device is achieved by using page locked host memory as described in Page Locked Host Memory In addition when using mapped page locked memory Mapped Memory there is no need to allocate any device memory and explicitly copy data between device and host memory Data transfers are implicitly performed each time the kernel accesses the mapped memory For maximum performance these memory accesses must be coalesced as with accesses to global memory see Device Memory Accesses Assuming that they www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 78 Performance Guidelines are and that the mapped memory is read or written only once using mapped page locked memory instead of explicit copies between device and host memory can be a win for performance On integrated systems where device memory and host memory are physically the same any copy between host and device memory is superfluous and mapped page locked memory should be used instead Applications may query a device is integrated by checking that the integrated device property see Device Enumeration is equal to 1 5 3 2 Device Memory Accesses An instruction that accesses addressable memory i e global local shared constant or texture memory might need to be re issued multiple times depending on the distribution of the memory addresses across the threads within the warp How the distribution affects the instruction throughput this wa
205. function qualifier can be used as a hint for the compiler not to inline the function if possible The function body must still be in the same file where it is called The forceinline function qualifier can be used to force the compiler to inline the function B 2 Variable Type Qualifiers Variable type qualifiers specify the memory location on the device of a variable An automatic variable declared in device code without any ofthe device Shared and constant qualifiers described in this section generally resides in a register However in some cases the compiler might choose to place it in local memory which can have adverse performance consequences as detailed in Device Memory Accesses B 2 1 device The device qualifier declares a variable that resides on the device www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 91 C Language Extensions At most one of the other type qualifiers defined in the next two sections may be used together with device to further specify which memory space the variable belongs to If none of them is present the variable gt Resides in global memory space gt Has the lifetime of an application gt Is accessible from all the threads within the grid and from the host through the runtime library cudaGetSymbolAddress cudaGetSymbolSize cudaMemcpyToSymbol cudaMemcpyFromSymbol B 2 2 constant The constant qualifier optionally used together with d
206. ges rna i Porra Ra ny le ER endees PP RI MEER 19 3 1 4 Application Compatibility sisses cece cece ee ee eect eect enne me memes nnne 19 3 1 5 C Compatibilty enter oes e eot eorr Re Pee E ERR ER ERU EE TER PEE DP NONE REA E ERE RE 20 3 1 6 64 Bit Compatibility necesse roter rr e rtr tyre e a seas ERE VR FEE TERR R Mea i ras 20 3 2 CUDA C Runtime 5er erronea eR AR eire tesexex s les dux aen eee rine x wean AARAA KERERE E 20 32 eria s 21 3 2 2 Device M mo srecen ia eene tea EEEE E shoe aee ee lever grae y E EPRE T ease as 21 3 2 3 Shared Memory enano on hh hr n RR ER ERES E E ORRERA n OSA RA RECEN ERE 24 3 2 4 Page Locked Host Memory ceesseeeeeeeeeee eene ehh enhn eher 29 3 2 4 1 Portable Memory ceecece e cete eh nere n Rn en ee en ae eaae en eee Ere UE Pre es 30 3 2 4 2 Write Combining MEMOLSY cece eee eee cece eee eee ehe ehe sense eene 30 3 2 4 3 Mapped Metinory v vite rese teen eges ees sv v uU bbsDsv esser OEE sexe vU Fuel EEEE 30 3 2 5 Asynchronous Concurrent EX CUtion ccecce eee eee ee ee ee ee eee ene ehe enhn 31 3 2 5 1 Concurrent Execution between Host and Device ceeceeeeeeee sees eeeeeeees 32 3 2 5 2 Concurrent Kernel EX Cution ccccccccesnescccccceencesnassasessseseceeacesasenaees 32 3 2 5 3 Overlap of Data Transfer and Kernel ExeCution sceeeeeeeee eee eeeeeeeeees 32 3 2 5 4 Concurrent Data Tralisfers eoe eere
207. gi testAssert lt lt lt 1 1 gt gt gt cudaDeviceSynchronize reiten Op will output Cest CUa lOs vorc TeSTASSeErE O blocks 000l tnrecck 000l Assertion should be one failed Assertions are for debugging purposes They can affect performance and it is therefore recommended to disable them in production code They can be disabled at compile time by defining the NDEBUG preprocessor macro before including assert h Note that expression should not be an expression with side effects something like i gt 0 for example otherwise disabling the assertion will affect the functionality of the code B 17 Formatted Output Formatted output is only supported by devices of compute capability 2 x and higher HUGE JOTEULMEE GCSE Clee CufouedElo US9p asl prints formatted output from a kernel to a host side output stream The in kernel printf function behaves in a similar way to the standard C library printf function and the user is referred to the host system s manual pages for a complete description of printf behavior In essence the string passed in as format is output to a stream on the host with substitutions made from the argument list wherever a format specifier is encountered Supported format specifiers are listed below The printf command is executed as any other device side function per thread and in the context of the calling thread From a multi threaded kernel this means that a straightforward
208. gradients B 8 1 17 texCubemap template class T mtsexievibemapieucdase sumeo bec Ee mem Oa tax e eare TEE fetches the CUDA array specified by the three dimensional texture object texObj using texture coordinate x y z as described in Cubemap Textures B 8 1 18 texCubemapLod template class T T texCubemapLod cudaTextureObject t texObj float x float y float z float level www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 103 C Language Extensions fetches from the CUDA array specified by the three dimensional texture object texObj using texture coordinate x y z as described in Cubemap Textures The level of detail used is given by level B 8 1 19 texCubemapLayered template lt class T gt T texCubemapLayered cudaTextureObject t texObj itllexWwe xx i3tlhueiewE wp dtlhexewe we duse Je D fetches from the CUDA array specified by the cubemap layered texture object texObj using texture coordinates x y z and index layer as described in Cubemap Layered Textures B 8 1 20 texCubemapLayeredLod template class T T texCubemapLayeredLod cudaTextureObject t texObj float x float y float z int layer float level fetches from the CUDA array specified by the cubemap layered texture object texObj using texture coordinate x y z and index layer as described in Cubemap Layered Textures at level of detail level level B 8 1 21 tex2Dgather template class T
209. gramming Guide PG 02829 001 v7 5 87 Performance Guidelines 5 4 3 Synchronization Instruction Throughput for __syncthreads is 16 operations per clock cycle for devices of compute capability 2 x and 128 operations per clock cycle for devices of compute capability 3 x Note that __ syncthreads can impact performance by forcing the multiprocessor to idle as detailed in Device Memory Accesses www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 88 Appendix A CUDA ENABLED GPUS http developer nvidia com cuda gpus lists all CUDA enabled devices with their compute capability The compute capability number of multiprocessors clock frequency total amount of device memory and other properties can be queried using the runtime see reference manual www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 89 Appendix B C LANGUAGE EXTENSIONS B 1 Function Type Qualifiers Function type qualifiers specify whether a function executes on the host or on the device and whether it is callable from the host or from the device B 1 1 device The device qualifier declares a function that is gt Executed on the device gt Callable from the device only B 1 2 global _ The global qualifier declares a function as being a kernel Such a function is gt Executed on the device gt Callable from the host gt Callable from the device for devices of compute capability 3 x see CUDA Dynamic Para
210. gt i floor xp a frac xp xp x 0 5 gt j floor yp B frac yp yg y 0 5 gt k floor zp y frac zp zp z 0 5 a B and y are stored in 9 bit fixed point format with 8 bits of fractional value so 1 0 is exactly represented Figure 14 illustrates linear filtering of a one dimensional texture with N 4 www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 201 Texture Fetching X 0 1 2 3 4 Non Normalize 0 0 25 0 5 0 75 1 Normalize Figure 14 Linear Filtering Mode Linear filtering of a one dimensional texture of four texels in clamp addressing mode F 3 Table Lookup A table lookup TL x where x spans the interval 0 R can be implemented as TL x tex N 1 R x 0 5 in order to ensure that TL 0 T 0 and TL R T N 1 Figure 15 illustrates the use of texture filtering to implement a table lookup with R 4 or R 1 from a one dimensional texture with N 4 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 202 Texture Fetching 0 4 3 8 3 4 0 1 3 2 3 1 Figure 15 One Dimensional Table Lookup Using Linear Filtering www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 203 Appendix G COMPUTE CAPABILITIES The general specifications and features of a compute device depend on its compute capability see Compute Capability Table 12 gives the features and technical specifications associated to each compute capability Floating Point Standard reviews the compliance with the
211. gt texRef cudaChannelFormatDesc channelDesc cudaCreateChannelDesc lt float gt size t offset cudaBindTexture2D amp offset texRef devPtr channelDesc width height pitch The following code samples bind a 2D texture reference to a CUDA array cuArray gt Using the low level API texture float cudaTextureType2D cudaReadModeElementType gt texRef textureReference texRefPtr cudaGetTextureReference amp texRefPtr amp texRef cudaChannelFormatDesc channelDesc cudaGetChannelDesc amp channelDesc cuArray cudaBindTextureToArray texRef cuArray amp channelDesc gt Using the high level API texture lt float cudaTextureType2D cudaReadModeElementType gt texRef cudaBindTextureToArray texRef cuArray The format specified when binding a texture to a texture reference must match the parameters specified when declaring the texture reference otherwise the results of texture fetches are undefined There is a limit to the number of textures that can be bound to a kernel as specified in Table 13 www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 48 Programming Interface The following code sample applies some simple transformation kernel to a texture 2D float texture texture lt float cudaTextureType2D cudaReadModeElementType gt texRef Simple transformation kernel _ global void transformKernel float output int width int height float theta
212. hat executes the kernel is given a unique thread ID that is accessible within the kernel through the built in threadIdx variable As an illustration the following sample code adds two vectors A and B of size N and stores the result into vector C Kernel definition ENgiteba EE voie Veckdd elcak s Etio9 c By locis C int i threadIdx x Cs e aug s BS int main Kernel invocation with N threads Vechdd lt lt lt iF Ne gt gt i A E Here each of the N threads that execute VecAdd performs one pair wise addition www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 9 Programming Model 2 2 Thread Hierarchy For convenience threadIdx is a 3 component vector so that threads can be identified using a one dimensional two dimensional or three dimensional thread index forming a one dimensional two dimensional or three dimensional block of threads called a thread block This provides a natural way to invoke computation across the elements in a domain such as a vector matrix or volume The index of a thread and its thread ID relate to each other in a straightforward way For a one dimensional block they are the same for a two dimensional block of size Dy D the thread ID of a thread of index x y is x y D for a three dimensional block of size Dy Dy D the thread ID of a thread of index x y z is x y Dy z Dy Dy As an example the following code adds two matrices A and B
213. hat this may also apply to cudaMemcpyAsync which might itself generate a kernel launch See Configuration Options for details By default sufficient storage is reserved for two levels of synchronization This maximum synchronization depth and hence reserved storage may be controlled by calling cudaDeviceSetLimit and specifying cudaLimitDevRuntimeSyncDepth The number of levels to be supported must be configured before the top level kernel is launched from the host in order to guarantee successful execution of a nested program Calling cudaDeviceSynchronize ata depth greater than the specified maximum synchronization depth will return an error www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 157 CUDA Dynamic Parallelism An optimization is permitted where the system detects that it need not reserve space for the parent s state in cases where the parent kernel never calls cudaDeviceSynchronize In this case because explicit parent child synchronization never occurs the memory footprint required for a program will be much less than the conservative maximum Such a program could specify a shallower maximum synchronization depth to avoid over allocation of backing store C 4 3 1 3 Pending Kernel Launches When a kernel is launched all associated configuration and parameter data is tracked until the kernel completes This data is stored within a system managed launch pool The launch pool is divided into a fixed size
214. he default stream is a special stream called the NULL stream and each device has a single NULL stream used for all host threads The NULL stream is special as it causes implicit synchronization as described in Implicit Synchronization For code that is compiled without specifying a default stream compilation flag default stream legacy is assumed as the default 3 2 5 5 3 Explicit Synchronization There are various ways to explicitly synchronize streams with each other cudaDeviceSynchronize waits until all preceding commands in all streams of all host threads have completed cudaStreamSynchronize takes a stream as a parameter and waits until all preceding commands in the given stream have completed It can be used to synchronize the host with a specific stream allowing other streams to continue executing on the device cudaStreamWaitEvent takes a stream and an event as parameters see Events for a description of events and makes all the commands added to the given stream after the call to cudaStreamWaitEvent delay their execution until the given event has completed The stream can be 0 in which case all the commands added to any stream after the call to cudaStreamWaitEvent wait on the event cudaStreamQuery provides applications with a way to know if all preceding commands in a stream have completed To avoid unnecessary slowdowns all these synchronization functions are usually best used for timing purposes or to is
215. he block of the calling thread and also ensures that gt All writes to global memory page locked host memory and the memory of a peer device made by the calling thread before the call to__ threadfence system are observed by all threads in the device host threads and all threads in peer devices as occurring before all writes to global memory page locked host memory and the memory of a peer device made by the calling thread after the call to threadfence system gt All reads from shared memory global memory page locked host memory and the memory of a peer device made by the calling thread before the call to threadfence system are performed before all reads from shared memory global memory page locked host memory and the memory of a peer device made by the calling thread after the callto threadfence system threadfence system is only supported by devices of compute capability 2 x and higher In the previous code sample inserting a fence function call between X 10 and Y 20 and between int A X and int B Y would ensure that for thread 1 A will always be equal to 10 if B is equal to 20 If thread 1 and 2 belong to the same block it is enough to use threadfence block If thread 1 and 2 do not belong to the same block _ threadfence must be used if they are CUDA threads from the same device and threadfence system must be used if they are CUDA threads from two different devices A common use ca
216. hed by another thread happens to be running This might impact the thread s ability to access the newly allocated data from the CPU for example within a base class constructor before it is able to explicitly attach it to a private stream To enable safe www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 242 Unified Memory Programming independence between threads therefore allocations should be made specifying this flag An alternative would be to place a process wide barrier across all threads after the allocation has been attached to the stream This would ensure that all threads complete their data stream associations before any kernels are launched avoiding the hazard A second barrier would be needed before the stream is destroyed because stream destruction causes allocations to revert to their default visibility The cudaMemAttachHost flag exists both to simplify this process and because it is not always possible to insert global barriers where required J 2 2 7 Memcpy Memset Behavior With Managed Memory Since managed memory can be accessed from either the host or the device cudaMemcpy relies on the type of transfer specified using cudaMemcpyKind to determine whether the data should be accessed as a host pointer or a device pointer If cudaMemcpyHostTo is specified and the source data is managed then it will be accessed from the device if it has global visibility or if it s associated with the stream
217. her than itself For example if multiple threads within a block are each launching work and synchronization is desired for all this work at once perhaps because of event based dependencies it is up to the program to guarantee that this work is submitted by all threads before calling cudaDeviceSynchronize Because the implementation is permitted to synchronize on launches from any thread in the block it is quite possible that simultaneous calls to cudaDeviceSynchronize by multiple threads will drain all work in the first call and then have no effect for the later calls C 3 1 5 Device Management Only the device on which a kernel is running will be controllable from that kernel This means that device APIs such as cudaSetDevice are not supported by the device runtime The active device as seen from the GPU returned from cudaGetDevice will have the same device number as seen from the host system The cudaGetDeviceProperty call may request information about another device www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 148 CUDA Dynamic Parallelism as this API allows specification of a device ID as a parameter of the call Note that the catch all cudaGetDeviceProperties API is not offered by the device runtime properties must be queried individually C 3 1 6 Memory Declarations C 3 1 6 1 Device and Constant Memory Memory declared at file scope with device or constant qualifiers behave identically when
218. hes ee vex VERS EIE EEEEP NE EIE 42 3 2 11 2 Surface Memory eese xh Ee teen RERSRARR KR RENS EARS EREEREER RESAS 52 3 2 11 3 CUDA Arrays occorre erronee to ret ner y ener tara soaks PRSE SENERA 56 3 2 11 4 Read Write CONerency cccccsccsscscsccecneeeneessceeseecseecceessesseecceeeaeeseees 56 3 2 12 Graphics Interoperability cece cece eee ee eee ee eee eee eeeee eee ne eh eee 56 3 2 12 1 4 OpenGL Interoperability 5 eoe r n cerrar sees rar rra nte anon ss e aa RR aaa 57 3 2 12 2 Direct3D Interoperability cceeesseeeeeseeeeeeee eene eene 59 3 2 12 3 SEI Interoperability i 5 ue eet eben Ue e tree nn ern aet ee ora ss bdade noon e qa arae iu 65 3 3 Versioning and Compatibility 0 ccc ccc ce cece eee e cece eee e eee eeeeeee nee nehmen 66 EE EGER 67 LEES 68 3 6 Tesla Compute Cluster Mode for Windows c ccce eene 68 Chapter 4 Hardware Implementation ee ore eo ener rr ennt aree ea se enr aene le sese s eneie Onus 69 4 1 SIMT Architecture reste beta etta e hp FERT RE PEREA PRRR V ERTEN S PEERR ERU iE TUI o ta A ae Ee Vien 69 4 2 Hardware Multithreading ceceeesseeeeeeeee eee eene ne enhn ehe hh enhn nnns 71 Chapter 5 Performance Guidelines ecce esee ecce eese eene eene eene nhe hne eher 72 5 1 Overall Performance Optimization Strategies cc ecce ese e eee eee eee eee eeeee
219. hows some examples of global memory accesses and corresponding memory transactions www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 210 Compute Capabilities G 3 3 Shared Memory Shared memory has 32 banks that are organized such that successive 32 bit words map to successive banks Each bank has a bandwidth of 32 bits per two clock cycles A shared memory request for a warp does not generate a bank conflict between two threads that access any address within the same 32 bit word even though the two addresses fall in the same bank In that case for read accesses the word is broadcast to the requesting threads multiple words can be broadcast in a single transaction and for write accesses each address is written by only one of the threads which thread performs the write is undefined This means in particular that there are no bank conflicts if an array of char is accessed as follows for example exper mE hugredENEehar Shame olay char data shared BaseIndex tid Figure 18 shows some examples of memory read accesses that involve the broadcast mechanism for devices of compute capability 3 x The same examples apply for devices of compute capability 2 x 32 Bit Strided Access A common access pattern is for each thread to access a 32 bit word from an array indexed by the thread ID tid and with some stride s extern hurecdegEreg celare I float data shared BaseIndex s tid In this case threads
220. iables marked with the managed qualifier managed variables have the following restrictions gt The address of a managed variable is not a constant expression gt A managed variable shall not have a const qualified type gt A managed variable shall not have a reference type gt The address or value of a managed variable shall not be used when the CUDA runtime may not be in a valid state including the following cases gt Instatic dynamic initialization or destruction of an object with static or thread local storage duration gt In code that executes after exit has been called e g a function marked with gccs attribute destructor gt Incodethat executes when CUDA runtime may not be initialized e g a function marked with gcc s attribute constructor Amanaged variable cannot be used as an unparenthesized id expression argument to a decltype expression gt Managed variables have the same coherence and consistency behavior as specified for dynamically allocated managed memory gt When a CUDA program containing managed variables is run on an execution platform with multiple GPUs the variables are allocated only once and not per GPU www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 177 C C Language Support Here are examples of legal and illegal uses of managed variables device managed int xxx 10 ZR NE Oleic NONE error use of managed variable Hie Me
221. ic data members of its class that are of class type or array thereof the default constructors can be considered empty A destructor for a class is considered empty at a point in the translation unit if it is either a trivial destructor or it satisfies all of the following conditions gt The destructor function has been defined gt The destructor function body is an empty compound statement gt Its class has no virtual functions and no virtual base classes gt The destructors of all base classes of its class can be considered empty gt For all the nonstatic data members of its class that are of class type or array thereof the destructor can be considered empty When compiling in the whole program compilation mode see the nvcc user manual for a description of this mode device shared and constant variables www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 176 C C Language Support cannot be defined as external using the extern keyword The only exception is for dynamically allocated __shared__ variables as described in shared When compiling in the separate compilation mode see the nvcc user manual for a description of this mode _ device shared and constant variables can be defined as external using the extern keyword nvlink will generate an error when it cannot find a definition for an external variable unless it is a dynamically allocated Shared variable E 2 3 2 managed Qualifier Var
222. ice as specified in Compute Capabilities or if Ns is greater than the maximum amount of shared memory available on the device minus the amount of shared memory required for static allocation B 20 Launch Bounds As discussed in detail in Multiprocessor Level the fewer registers a kernel uses the more threads and thread blocks are likely to reside on a multiprocessor which can improve performance Therefore the compiler uses heuristics to minimize register usage while keeping register spilling see Device Memory Accesses and instruction count to a minimum www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 135 C Language Extensions An application can optionally aid these heuristics by providing additional information to the compiler in the form of launch bounds that are specified using the launch bounds qualifier in the definition ofa global function C alase venel launch bounds maxThreadsPerBlock minBlocksPerMultiprocessor MyKernel gt maxThreadsPerBlock specifies the maximum number of threads per block with which the application will ever launch MyKernel it compiles to the maxntid PTX directive gt minBlocksPerMultiprocessor is optional and specifies the desired minimum number of resident blocks per multiprocessor it compiles to the minnctapersm PTX directive If launch bounds are specified the compiler first derives from them the upper limit L on the number of registers the
223. ide PG 02829 001 v7 5 vi B 9 2 6 surf3Dwrite iece eese staves ecu te e OR ERR PER ree Sees dates Re erRE Ee dave EE 115 B 9 2 7 surf1DLayeredread eoe eerte etre erre tenen hen ere ERRA e reg eus 115 B 9 2 8 surf TDLayeredwrite 1 eese eerte eror pa rera ripe a cogs eased IEEE UPS Cere ss 115 B 9 2 9 surf2DLayeredread ecceeeeseeeeeeeeeee eene nnne hene enhn rne 116 B 9 2 10 surf2DLayeredwrite 5 o eter eee eee a gea Ie y ere n nera geo y eee y T rey saei 116 B 9 2 11 surfCubemapread cceeeeeeeeeeeeeeee eee enhn nnne hse ente 116 B 9 2 12 surf CubemapwWrite i sies eio eene rea an ex a eea a e eR ER eO A CR EROR NE VRE ROS APES 116 B 9 2 13 surfCubemapLayeredread ssssssssessosssesesssesssssossossessessessssossoseoseo 117 B 9 2 14 surfCubemapLayeredwrite cccecceecce eee eeee ence eeee eee ene hehehe eee 117 B 10 Read Only Data Cache Load FUNnCtion ccc ecee eee ece eect cece eee eee eeeeeeeeeeeee teens 117 B 11 Time FUNCHON ices scicesceveesscwiedtdecarsesavadennvonwits eaae ege ga Yee aboaenesecions sede dveesmedeleee 117 B 12 Atomic Functions oie eon sie terree vr san cues dsb baw eau eure weeded veut sehida RE EE 118 B 12 1 Arithmetic FUNCtIONS cce cece cece ee ee eee ne eee ehh thee thea 118 B 12 1 1 atomicAdd iecore intet nr nre ehem i eer dice ons wien ipee Vile QU aed a lens 118 B 12 1 2 atoimicSub oor eor
224. idth dimBlock x A height dimBlock y MatMulKernel lt lt lt dimGrid dimBlock d A d B d C Read C from device memory cudaMemcpy C elements Cd elements size cudaMemcpyDeviceToHost Free device memory cudaFree d A elements cudaFree d B elements cudaFree d C elements Matrix multiplication kernel called by MatMul __ global _ void MatMulKernel Matrix A Matrix B Matrix C Each thread computes one element of C by accumulating results into Cvalue float Cvalue 0 int row blockIdx y blockDim y threadIdx y me Cc Ol pioeck idis a Olock Daum se eh readies x tor ime Op lt A miekes srs Cvalue A elements row A width e B elements e B width col C elements row C width col Cvalue www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 25 Programming Interface B width 1 A height 1 Figure 9 Matrix Multiplication without Shared Memory The following code sample is an implementation of matrix multiplication that does take advantage of shared memory In this implementation each thread block is responsible for computing one square sub matrix C of C and each thread within the block is responsible for computing one element of C As illustrated in Figure 10 C is equal to the product of two rectangular matrices the sub matrix of A of dimension A width block size that has the same row indices as C and the su
225. idth x tex2D lt float gt texObj tu tv www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 45 Programming Interface Host code int main Allocate CUDA array in device memory cudaChannelFormatDesc channelDesc cudaCreateChannelDesc 32 0 O0 O cudaChannelFormatKindFloat cudaArray cuArray cudaMallocArray amp cuArray amp channelDesc width height Copy to device memory some data located at address h data in host memory cudaMemcpyToArray cuArray 0 0 h data size cudaMemcpyHostToDevice Specify texture struct cudaResourceDesc resDesc memset amp resDesc 0 sizeof resDesc resDesc resType cudaResourceTypeArray resDesc res array array cuArray Specify texture object parameters struct cudaTextureDesc texDesc memset amp texDesc 0 sizeof texDesc texDesc addressMode 0 cudaAddressModeWrap texDesc addressMode 1 cudaAddressModeWrap texDesc filterMode cudaFilterModeLinear texDesc readMod cudaReadModeElementType texDesc normalizedCoords 1 Create texture object cudaTextureObject t texObj 0 cudaCreateTextureObject amp texObj amp resDesc amp texDesc NULL Allocate result of transformation in device memory izdbreysuers foxulEjoXotie p cudaMalloc amp output width height sizeof float Invoke kernel cimsucinmibjiliec o EON dim3 dimGrid width dimBlock x 1 dimB
226. ies the dimensions and size of each thread block gt Ns is of type size_t and specifies the number of bytes of shared memory that is dynamically allocated per thread block for this call and addition to statically allocated memory Ns is an optional argument that defaults to 0 gt Sis of type cudaStream_t and specifies the stream associated with this call The stream must have been allocated in the same thread block where the call is being made S is an optional argument that defaults to 0 C 3 1 1 1 Launches are Asynchronous Identical to host side launches all device side kernel launches are asynchronous with respect to the launching thread That is to say the lt lt lt gt gt gt launch command will return immediately and the launching thread will continue to execute until it hits an explicit launch synchronization point such as cudaDeviceSynchronize The grid launch is posted to the device and will execute independently of the parent thread The child grid www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 146 CUDA Dynamic Parallelism may begin execution at any time after launch but is not guaranteed to begin execution until the launching thread reaches an explicit launch synchronization point C 3 1 1 2 Launch Environment Configuration All global device configuration settings e g shared memory and L1 cache size as returned from cudaDeviceGetCacheConfig and device limits returned from cudaDeviceGetLimit
227. iling with the ptxas options v option www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 74 Performance Guidelines The total amount of shared memory required for a block is equal to the sum of the amount of statically allocated shared memory and the amount of dynamically allocated shared memory The number of registers used by a kernel can have a significant impact on the number of resident warps For example for devices of compute capability 2 x if a kernel uses 32 registers and each block has 512 threads and requires very little shared memory then two blocks i e 32 warps can reside on the multiprocessor since they require 2x512x32 registers which exactly matches the number of registers available on the multiprocessor But as soon as the kernel uses one more register only one block i e 16 warps can be resident since two blocks would require 2x512x17 registers which are more registers than are available on the multiprocessor Therefore the compiler attempts to minimize register usage while keeping register spilling see Device Memory Accesses and the number of instructions to a minimum Register usage can be controlled using the maxrregcount compiler option or launch bounds as described in Launch Bounds Each double variable and each long long variable uses two registers The effect of execution configuration on performance for a given kernel call generally depends on the kernel code Experimentation is therefore
228. ility and OpenGL Interoperability for details on how the CUDA runtime interoperate with Direct3D and OpenGL respectively 3 3 Versioning and Compatibility There are two version numbers that developers should care about when developing a CUDA application The compute capability that describes the general specifications and features of the compute device see Compute Capability and the version of the CUDA driver API that describes the features supported by the driver API and runtime The version of the driver API is defined in the driver header file as CUDA VERSION It allows developers to check whether their application requires a newer device driver than the one currently installed This is important because the driver API is backward compatible meaning that applications plug ins and libraries including the C runtime compiled against a particular version of the driver API will continue to work on subsequent device driver releases as illustrated in Figure 11 The driver API is not forward compatible which means that applications plug ins and libraries including the C runtime compiled against a particular version of the driver API will not work on previous versions of the device driver It is important to note that there are limitations on the mixing and matching of versions that is supported gt Since only one version of the CUDA Driver can be installed at a time on a system the installed driver must be of the same or higher versio
229. in 29 20 the maximum ulp error is 2 The maximum ulp error is 2 floor abs 1 16 x __exp10f x The maximum ulp error is 2 floor abs 2 95 x __logf x For x in 0 5 2 the maximum absolute error is Fi otherwise the maximum ulp error is 3 log2f x For x in 0 5 2 the maximum absolute error is y otherwise the maximum ulp error is 2 log10f x For x in 0 5 2 the maximum absolute error is ye otherwise the maximum ulp error is 3 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 169 Mathematical Functions Function Error bounds __sinf x For x in 11 1 the maximum absolute error is gm and larger otherwise For x in 11 1 the maximum absolute error is gen and larger otherwise Sincosf x sptr cptr Same as sinf x and cosf x tanf x Derived from its implementation as sinf x 1 cosf x __powf x y Derived from its implementation as exp2 y __log2f x Double Precision Floating Point Functions dadd rn and dmul rn map to addition and multiplication operations that the compiler never merges into FMADs By contrast additions and multiplications generated from the and operators will frequently be combined into FMADs Table 10 Double Precision Floating Point Intrinsic Functions Supported by the CUDA Runtime Library with Respective Error Bounds ddiv rn rz ru rd x y x y IEEE compliant Requires compute capability 2 d
230. in fms Linker Output n sWn walltime info log cuModuleLoadData cuModule cubin cuLinkDestroy linkState Full code can be found in the ptxjit CUDA sample H 3 Kernel Execution cuLaunchKernel launches a kernel with a given execution configuration Parameters are passed either as an array of pointers next to last parameter of cuLaunchKernel where the nth pointer corresponds to the nth parameter and points to a region of memory from which the parameter is copied or as one of the extra options last parameter of cuLaunchKernel When parameters are passed as an extra option the CU LAUNCH PARAM BUFFER POINTER option they are passed as a pointer to a single buffer where parameters are assumed to be properly offset with respect to each other by matching the alignment requirement for each parameter type in device code www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 226 Driver API Alignment requirements in device code for the built in vector types are listed in Table 3 For all other basic types the alignment requirement in device code matches the alignment requirement in host code and can therefore be obtained using __alignof The only exception is when the host compiler aligns double and long long and long on a 64 bit system on a one word boundary instead of a two word boundary for example using gec s compilation flag mno align double since in device cod
231. ing Guide PG 02829 001_v7 5 111 C Language Extensions B 9 1 7 surfiDLayeredread template lt class T gt T surflDLayeredread cudaSurfaceObject t surfObj Gime ox augue LENS boundaryMode cudaBoundaryModeTrap template class T void surflDLayeredread T data cudaSurfaceObject t surfObj mie xp ime layer boundaryMode cudaBoundaryModeTrap reads the CUDA array specified by the one dimensional layered surface object surf Obj using coordinate x and index layer B 9 1 8 surfiDLayeredwrite template lt class Type gt void surflDLayeredwrite T data cudaSurfaceObject t surfObj SLIME oe aioe layer boundaryMode cudaBoundaryModeTrap writes value data to the CUDA array specified by the two dimensional layered surface object sur 0bj at coordinate x and index layer B 9 1 9 surf2DLayeredread template lt class T gt T surf2DLayeredread cudaSurfaceObject t surfObj siue Se shane yp sue layer boundaryMode cudaBoundaryModeTrap template class T void surf2DLayeredread T data cudaSurfaceObject t surfObj SLOG oxa aune WW alone JENA boundaryMode cudaBoundaryModeTrap reads the CUDA array specified by the two dimensional layered surface object sur 0bj using coordinate x and y and index layer B 9 1 10 surf2DLayeredwrite template lt class T gt void surf2DLayeredwrite T data cudaSurfaceObject t surfObj SUMS zp Ane yy iae layer boundaryMode cudaBoundaryModeTrap writes value d
232. ion Multiprocessors are grouped into Graphics Processor Clusters GPCs A GPC includes four multiprocessors G 5 2 Global Memory Global memory accesses are always cached in L2 and caching in L2 behaves in the same way as for devices of compute capability 2 x see Global Memory Data that is read only for the entire lifetime of the kernel can also be cached in the unified L1 texture cache described in the previous section by reading it using the __1dg function see Read Only Data Cache Load Function When the compiler detects that the read only condition is satisfied for some data it will use 1dg to read it The compiler might not always be able to detect that the read only condition is satisfied for some data Marking pointers used for loading such data with both the constand restrict qualifiers increases the likelihood that the compiler will detect the read only condition Data that is not read only for the entire lifetime of the kernel cannot be cached in the unified L1 texture cache for devices of compute capability 5 0 For devices of compute capability 5 2 it is by default not cached in the unified L1 texture cache but caching may be enabled using the following mechanisms gt Perform the read using inline assembly with the appropriate modifier as described in the PTX reference manual gt Compile with the Xptxas dlcm ca compilation flag in which case all reads are cached except reads that are performed using i
233. ion irregular loop structure or other constructs that do not fit a flat single level of parallelism may more transparently be expressed This document describes the extended capabilities of CUDA which enable Dynamic Parallelism including the modifications and additions to the CUDA programming model necessary to take advantage of these as well as guidelines and best practices for exploiting this added capacity Dynamic Parallelism is only supported by devices of compute capability 3 5 and higher C 1 2 Glossary Definitions for terms used in this guide Grid A Grid is a collection of Threads Threads in a Grid execute a Kernel Function and are divided into Thread Blocks www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 140 CUDA Dynamic Parallelism Thread Block A Thread Block is a group of threads which execute on the same multiprocessor SMX Threads within a Thread Block have access to shared memory and can be explicitly synchronized Kernel Function A Kernel Function is an implicitly parallel subroutine that executes under the CUDA execution and memory model for every Thread in a Grid Host The Host refers to the execution environment that initially invoked CUDA Typically the thread running on a system s CPU processor Parent A Parent Thread Thread Block or Grid is one that has launched new grid s the Child Grid s The Parent is not considered completed until all of its launched Child Grids have also comple
234. ion of a function or variable with external linkage shall not depend on whether CUDA ARCH is defined or on a particular value of CUDA ARCH a Example if defined CUDA ARCH void foo void exwexetoye The demini ion OE Foo is only present when CUDA ARCH _ is undefined fendif 4 In separate compilation CUDA ARCH must not be used in headers such that different objects could contain different behavior Or it must be guaranteed that all objects will compile for the same compute arch If a weak function or template function is defined in a header and its behavior depends on CUDA ARCH then the instances of that function in the objects could contlict if the objects are compiled for different compute arch For example if an a h contains template typename T cvice Ngee pier vec ie CUa ARCH 200 return NULL no address else imeweeol W aieie 2Z56 7 ms eem arry endif Then if a cu and b cu both include a h and instantiate getptr for the same type and b cu expects a non NULL address and compile with 7 This does not apply to entities that may be defined in more than one translation unit such as compiler generated template instantiations www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 175 C C Language Support MVCC ceuetelsxelsnnsuhnEe 20 Cle eibi Invece compute ecl MIS eu nve ereis Oma Om Me At link time only one version of the getptr i
235. ion or for any infringement of patents or other rights of third parties that may result from its use No license is granted by implication of otherwise under any patent rights of NVIDIA Corporation Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all other information previously supplied NVIDIA Corporation products are not authorized as critical components in life support devices or systems without express written approval of NVIDIA Corporation Trademarks NVIDIA and the NVIDIA logo are trademarks or registered trademarks of NVIDIA Corporation in the U S and other countries Other company and product names may be trademarks of the respective companies with which they are associated Copyright 2007 2015 NVIDIA Corporation All rights reserved e www nvidia com nVIDIA
236. ir parallelism to manycore GPUs with widely varying numbers of cores The CUDA parallel programming model is designed to overcome this challenge while maintaining a low learning curve for programmers familiar with standard programming languages such as C At its core are three key abstractions a hierarchy of thread groups shared memories and barrier synchronization that are simply exposed to the programmer as a minimal set of language extensions www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 5 Introduction These abstractions provide fine grained data parallelism and thread parallelism nested within coarse grained data parallelism and task parallelism They guide the programmer to partition the problem into coarse sub problems that can be solved independently in parallel by blocks of threads and each sub problem into finer pieces that can be solved cooperatively in parallel by all threads within the block This decomposition preserves language expressivity by allowing threads to cooperate when solving each sub problem and at the same time enables automatic scalability Indeed each block of threads can be scheduled on any of the available multiprocessors within a GPU in any order concurrently or sequentially so that a compiled CUDA program can execute on any number of multiprocessors as illustrated by Figure 5 and only the runtime system needs to know the physical multiprocessor count This scalable programming mo
237. it Support for Dynamic Parallelism ceeeeeeeeeeen e 154 C 3 3 1 Including Device Runtime API in CUDA Code eee 154 C 3 3 2 COMPILING and Linking iiise cse eer rette ee Rhin RR REX SERERE PE eS ara ERE E AER 155 C 4 Programming Guidelines ceres eee eene ot nonna h ne rra rn ERR E RR TRE eR CERE Ra aae ra 155 GU PEIUS 155 C 4 2 PerforimatiCe iicet terere eee recess ece e eder eet Rr ere e Te El TUN ee ev eur erede TEM 156 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 viii C 4 2 4 SYMCHFONIZALION vs 40s iier p o o Er eren oen to XR Manet gren eo eR aa ERR ere e e RARE thas 156 C 4 2 2 Dynamic parallelism enabled Kernel Overhead eeeeeeeeeseee 156 C 4 3 Implementation Restrictions and Limitations cce cece eee e eee cece eee eeeeeeeeee 157 C4 3 1 Runitlme iecore rore rete ex ERES ee aula ein SENS EVE ass EUER NO E canes EEIN ARESE Eh 157 Appendix D Mathematical Functions eeeeeeeeee eese eene eene ehh ether 160 D 1 Standard F nctions i eoe ceret ter E RO knee ER e E ne E n e E e EE RU ER ee E Oe EE ee 160 D 2 Intrinsic FUNCOMS sees north ee they xx nee Rex Erica DR Ir ER TORRA EEEE EREA FACE EI ER sees 168 Appendix E C C Language Support c ccce eese eeeee esses snsa EREEREER 171 E 1 C 11 Language Features eoecc eec eerie een n CR NR n C seid seins AENEA OVER ESTA EE ERAS ES
238. itlbexeue wor allie eI SB eL t27 c 4 t2 ee eB w iS eS e uw eS ekal se bs The effects here are a reduced number of memory accesses and reduced number of computations This is balanced by an increase in register pressure due to cached loads and common sub expressions Since register pressure is a critical issue in many CUDA codes use of restricted pointers can have negative performance impact on CUDA code due to reduced occupancy B 3 Built in Vector Types B 3 1 char short int long longlong float double These are vector types derived from the basic integer and floating point types They are structures and the 1st 2nd 3rd and 4th components are accessible through the fields x y z and w respectively They all come with a constructor function of the form make type name gt for example Hee maks inmt2 ime x ae NE which creates a vector of type int2 with value x y In host code the alignment requirement of a vector type is equal to the alignment requirement of its base type This is not always the case in device code as detailed in Table 3 www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 94 C Language Extensions Table 3 Alignment Requirements in Device Code a LIN NN long1 ulong1 4 if sizeof long is equal to sizeof int 8 otherwise long2 ulong2 8 if sizeof long is equal to sizeof int 16 otherwise long3 ulong3 4 if sizeof long is equal to sizeof int
239. ixed with ru operate using the round up to positive infinity rounding mode Functions suffixed with rd operate using the round down to negative infinity rounding mode Single Precision Floating Point Functions fadd rn rz ru rd and fmul rn rz ru rd map to addition and multiplication operations that the compiler never merges into FMADs By contrast www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 168 Mathematical Functions additions and multiplications generated from the and operators will frequently be combined into FMADs The accuracy of floating point division varies depending on whether the code is compiled with prec div false or prec div true When the code is compiled with prec div false both the regular division operator and dividef x y have the same accuracy but for 216 lt y lt gem __fdividef x y delivers a result of zero whereas the operator delivers the correct result to within the accuracy stated in Table 9 Also for 2126 lt y lt gum if x is infinity fdividef x y delivers a NaN as a result of multiplying infinity by zero while the operator returns infinity On the other hand the operator is IEEE compliant when the code is compiled with prec div true or without any prec div option at all since its default value is true Table 9 Single Precision Floating Point Intrinsic Functions Supported by the CUDA Runtime Library with Respective Error Bounds For y
240. k performance Vector architectures on the other hand require the software to coalesce loads into vectors and manage divergence manually Notes The threads of a warp that are on that warp s current execution path are called the active threads whereas threads not on the current path are inactive disabled Threads can be inactive because they have exited earlier than other threads of their warp or because they are on a different branch path than the branch path currently executed by the warp or because they are the last threads of a block whose number of threads is not a multiple of the warp size If a non atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp the number of serialized writes that occur to that location varies depending on the compute capability of the device see Compute Capability 2 x Compute Capability 3 x and Compute Capability 5 x and which thread performs the final write is undefined If an atomic instruction executed by a warp reads modifies and writes to the same location in global memory for more than one of the threads of the warp each read modify write to that location occurs and they are all serialized but the order in which they occur is undefined www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 70 Hardware Implementation 4 2 Hardware Multithreading The execution context program counters registers
241. l device management kernel launching device memcpy stream management and event management are exposed from the device runtime Programming for the device runtime should be familiar to someone who already has experience with CUDA Device runtime syntax and semantics are largely the same as that of the host API with any exceptions detailed earlier in this document www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 155 CUDA Dynamic Parallelism The following example shows a simple Hello World program incorporating dynamic parallelism include lt stdio h gt global void childKernel josealimtese Mello Wie __global__ void parentKernel VES c bc soe csse elits if cudaSuccess cudaGetLastError return wait for child to complete if cudaSuccess cudaDeviceSynchronize return peime e Nor Nna SME Wein MMe eree Cac esee EL launch parent parentKernel lt lt lt 1 1 gt gt gt if cudaSuccess cudaGetLastError return 1 wait for parent to complete if cudaSuccess cudaDeviceSynchronize return 2 return 0 This program may be built in a single step from the command line as follows S nve e eaen S nde esc hello morle leu one ES udddcvst C 4 2 Performance C 4 2 1 Synchronization Synchronization by one thread may impact the performance of other threads in the same Thread Block even when those other thread
242. lass DataType enum cudaTextureReadMode readMode gt Type texlDLayeredLod texture DataType cudaTextureTypelD readMode gt texRef itlhexewe exp ine layer itdhexne level fetches from the CUDA array bound to the one dimensional texture reference texRef using texture coordinate x and index layer as described in Layered Textures The level of detail is given by level Type is the same as DataType except when readMode is cudaReadModeNormalizedFloat see Texture Reference API in which case Type is the corresponding floating point type B 8 2 13 tex1DLayeredGrad template lt class DataType enum cudaTextureReadMode readMode gt Type texlDLayeredGrad texture DataType cudaTextureTypelD readMode gt texRef loewe x cus deyer locie che loew Chis fetches from the CUDA array bound to the one dimensional texture reference texRef using texture coordinate x and index layer as described in Layered Textures The level of detail is derived from the dx and dy X and Y gradients Type is the same as DataType except when readMode is cudaReadModeNormalizedFloat see Texture Reference API in which case Type is the corresponding floating point type B 8 2 14 tex2DLayered template lt class DataType enum cudaTextureReadMode readMode gt Type tex2DLayered texture lt DataType cudaTextureType2DLayered readMode gt texRef siose 9x5 ikoe Ww aude Lense fetches from the CUDA array bound to the two dimensional laye
243. ld grids created by its threads have completed Even if the invoking threads do not explicitly synchronize on the child grids www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 141 CUDA Dynamic Parallelism launched the runtime guarantees an implicit synchronization between the parent and child CPU Thread Grid A au nch Grid A Threads Grid A Paren Grid B Launch Grid B Threads 9 Figure 12 Parent Child Launch Nesting C 2 1 2 Scope of CUDA Primitives On both host and device the CUDA runtime offers an API for launching kernels for waiting for launched work to complete and for tracking dependencies between launches via streams and events On the host system the state of launches and the CUDA primitives referencing streams and events are shared by all threads within a process however processes execute independently and may not share CUDA objects A similar hierarchy exists on the device launched kernels and CUDA objects are visible to all threads in a thread block but are independent between thread blocks This means for example that a stream may be created by one thread and used by any other thread in the same thread block but may not be shared with threads in any other thread block C 2 1 3 Synchronization CUDA runtime operations from any thread including kernel launches are visible across a thread block This means that an invoking thread in the parent grid
244. lements of a or b This means that to guarantee functional correctness the compiler cannot load a 0 and b 0 into registers multiply them and store the result to both e 0 and c 1 because the results would differ from the abstract execution model if say a 0 is really the same location as c 0 So the compiler cannot take advantage of the common sub expression Likewise the compiler cannot just reorder the computation of c 4 into the proximity of the computation of c 0 and c 1 because the preceding write to c 3 could change the inputs to the computation of c 4 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 93 C Language Extensions By making a b and c restricted pointers the programmer asserts to the compiler that the pointers are in fact not aliased which in this case means writes through c would never overwrite elements of a or b This changes the function prototype as follows endNSROOIons EI Jr ESEE Ier el Const logic T TOBLTiCE lo ilhoguE _ restric C7 Note that all pointer arguments need to be made restricted for the compiler optimizer to derive any benefit With the _ restrict__ keywords added the compiler can now reorder and do common sub expression elimination at will while retaining functionality identical with the abstract execution model VOLE ROol COns kloat ireset ice const Alcat SSC Id loar seeguxseu float tO a 0 iikome wil PIOI clope tA t0 r27
245. lies that constant data cannot be altered from within a running kernel even ahead of a child kernel launch as references to constant space are read only C 3 1 7 API Errors and Launch Failures As usual for the CUDA runtime any function may return an error code The last error code returned is recorded and may be retrieved via the cudaGetLastError call Errors are recorded per thread so that each thread can identify the most recent error that it has generated The error code is of type cudaError t Similar to a host side launch device side launches may fail for many reasons invalid arguments etc The user must call cudaGetLastError to determine if a launch generated an error however lack of an error after launch does not imply the child kernel completed successfully For device side exceptions e g access to an invalid address an error in a child grid will be returned to the host instead of being returned by the parent s call to cudaDeviceSynchronize www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 150 CUDA Dynamic Parallelism C 3 1 7 1 Launch Setup APIs Kernel launch is a system level mechanism exposed through the device runtime library and as such is available directly from PTX via the underlying cudaGetParameterBuffer and cudaLaunchDevice APIs It is permitted for a CUDA application to call these APIs itself with the same requirements as for PTX In both cases the user is then responsibl
246. llelism for more details global functions must have void return type Any call toa global function must specify its execution configuration as described in Execution Configuration Acalltoa global function is asynchronous meaning it returns before the device has completed its execution B 1 3 host The host qualifier declares a function that is www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 90 C Language Extensions gt Executed on the host gt Callable from the host only It is equivalent to declare a function with only the __host__ qualifier or to declare it without any of the host device or global qualifier in either case the function is compiled for the host only The global and host qualifiers cannot be used together The device and host qualifiers can be used together however in which case the function is compiled for both the host and the device The CUDA ARCH macro introduced in Application Compatibility can be used to differentiate code paths between host and device ECCE Cewice mel if CUDA ARCH gt 500 Device code path for compute capability 5 x elif CUDA ARCH gt 300 Device code path for compute capability 3 x elif _ CUDA ARCH 200 Device code path for compute capability 2 x elif defined CUDA ARCH Host code path endif B 1 4 noinline and forceinline The compiler inlines any device function when deemed appropriate The noinline
247. ller s lane ID with laneMask the value of var held by the resulting lane ID is returned If width is less than warpSize then each group of width consecutive threads are able to access elements from earlier groups of threads however if they attempt to access elements from later groups of threads their own value of var will be returned This mode implements a butterfly addressing pattern such as is used in tree reduction and broadcast B 14 3 Return Value All shf1 intrinsics return the 4 byte word referenced by var from the source lane ID as an unsigned integer If the source lane ID is out of range or the source thread has exited the calling thread s own var is returned www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 123 C Language Extensions B 14 4 Notes All shf1 intrinsics share the same semantics with respect to code motion as the vote intrinsics any and all Threads may only read data from another thread which is actively participating in the __shf1 command If the target thread is inactive the retrieved value is undefined width must be a power of 2 i e 2 4 8 16 or 32 Results are unspecified for other values Types other than int or float must first be cast in order to use the sh 1 intrinsics B 14 5 Examples B 14 5 1 Broadcast of a single value across a warp include lt stdio h gt moehoen ebcasie Gunite sac a int laneId threadIdx x amp Oxlf int value if laneId
248. lock x neieiet ciam llio c EE MEI MEI EK IRA transformKernel dimGrid dimBlock output texObj width height angle Destroy texture object cudaDestroyTextureObject texObj Free device memory cudaFreeArray cuArray cudaFree output return 0 3 2 11 1 2 Texture Reference API Some of the attributes of a texture reference are immutable and must be known at compile time they are specified when declaring the texture reference A texture reference is declared at file scope as a variable of type texture texture lt DataType Type ReadMode gt texRef where www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 46 Programming Interface gt DataType specifies the type of the texel gt Type specifies the type of the texture reference and is equal to cudaTextureTypelD cudaTextureType2D or cudaTextureType3D fora one dimensional two dimensional or three dimensional texture respectively Or cudaTextureTypelDLayered or cudaTextureType2DLayered for a one dimensional or two dimensional layered texture respectively Type is an optional argument which defaults to cudaTextureTypelD gt ReadMode specifies the read mode it is an optional argument which defaults to cudaReadModeElementType A texture reference can only be declared as a static global variable and cannot be passed as an argument to a function The other attributes of a texture reference are mutable and can be changed at ru
249. ls on multi device systems but by default the benefits of using page locked memory described above are only available in conjunction with the device that was current when the block was allocated and with all devices sharing the same unified address space if any as described in Unified Virtual Address Space To make these advantages available to all devices the block needs to be allocated by passing the flag cudaHostAllocPortable to cudaHostAlloc or page locked by passing the flag cudaHostRegisterPortable to cudaHostRegister 3 2 4 2 Write Combining Memory By default page locked host memory is allocated as cacheable It can optionally be allocated as write combining instead by passing flag cudaHostAllocWriteCombined to cudaHostAlloc Write combining memory frees up the host s L1 and L2 cache resources making more cache available to the rest of the application In addition write combining memory is not snooped during transfers across the PCI Express bus which can improve transfer performance by up to 40 Reading from write combining memory from the host is prohibitively slow so write combining memory should in general be used for memory that the host only writes to 3 2 4 3 Mapped Memory A block of page locked host memory can also be mapped into the address space of the device by passing flag cudaHostAllocMapped to cudaHostAlloc or by passing flag cudaHostRegisterMapped to cudaHostRegister Such a block www nvidia com
250. lt 1 5 295 cudaDeviceSynchronize return 0 will output Hello thread 0 f 1 2345 Self evidently the if statement limits which threads will call printf so that only a single line of output is seen www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 130 C Language Extensions B 18 Dynamic Global Memory Allocation and Operations Dynamic global memory allocation and operations are only supported by devices of compute capability 2 x and higher void malloc SaaS SEC void free void ptr allocate and free memory dynamically from a fixed size heap in global memory vord mencpy word ces scons vod Sc Sn aae copy size bytes from the memory location pointed by src to the memory location pointed by dest VOICA menget vec per oe value S1276 S1723 set size bytes of memory block pointed by ptr to value interpreted as an unsigned char The CUDA in kernel malloc function allocates at least size bytes from the device heap and returns a pointer to the allocated memory or NULL if insufficient memory exists to fulfill the request The returned pointer is guaranteed to be aligned to a 16 byte boundary The CUDA in kernel free function deallocates the memory pointed to by ptr which must have been returned by a previous call to malloc If ptr is NULL the call to free is ignored Repeated calls to free with the same ptr has undefined behavior The memory allocated by a given CUDA threa
251. lt dimGrid dimBlock positions time width height Unmap buffer object cudaGraphicsUnmapResources 1 amp positionsVBO CUDA 0 Render from buffer object glClear GL COLOR BUFFER BIT GL DEPTH BUFFER BIT glBindBuffer GL ARRAY BUFFER positionsVBO glVertexPointer 4 GL FLOAT 0 0 glEnableClientState GL VERTEX ARRAY glDrawArrays GL POINTS 0 width height glDisableClientState GL VERTEX ARRAY Swap buffers glutSwapBuffers glutPostRedisplay www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 58 Programming Interface void deleteVBO cudaGraphicsUnregisterResource positionsVBO CUDA glDeleteBuffers 1 amp positionsVBO _ global void createVertices float4 positions float time unsigned int width unsigned int height unsigned int x unsigned int y ploboekidz x blkocle Dam x ur ehreadldx x blockIdx y blockDim y threadIdx y Calculate uv coordinates llc tU Elo ad Werth float v y float height wur ex wp Y 2530 ire xpo ex cw ww Zu d WES calculate simple sine wave pattern float freq 4 0f float w sinf u freq time oWeuE w saec ap deum 5t Write positions positions y width x make float4 u w v 1 0f On Windows and for Quadro GPUs cudaWGLGetDevice can be used to retrieve the CUDA device associated to the handle returned by wg1EnumGpusNV
252. ly specified they are computed based on the scopes enclosing the closure class associated with the lambda as described in the section on C 11 support The execution space annotations are applied to all methods of the closure class associated with the lambda In the rest of this section a device lambda indicates a lambda explicitly annotated with the device annotation A device lambda defined within a host function may be used to instantiatea global function template subject to the restrictions described in this document Example __ Geyaes line regullt template lt typename T gt _ Global Vou deme entr result ain 4 e void foo void rne 3 SOR herngil lt lt lt l IsSS cewies amc am Y return in x x captured by value E 4 1 Restrictions Fora device lambda defined within a host function the CUDA compiler will replace it with a placeholder type defined in namespace scope before invoking the host compiler The CUDA compiler will synthesize expressions involving the address of the enclosing function This is required for the correct execution of any global function template whose template argument involvesa device lambda This transformation requires certain restrictions on device lambdas described below 1 A device lambda must be defined directly within the block scope of a function definition enclosing function or within a nested block scope The enclosing function
253. m CUDA C Programming Guide PG 02829 001_v7 5 52 Programming Interface The following code sample applies some simple transformation kernel to a texture Simple copy kernel global void copyKernel cudaSurfaceObject t inputSurfObj cudaSurfaceObject t outputSurfObj int width int height Calculate surface coordinates unsigned inti lt ook on MET cil mee h Ehreadidx x unsigned int y blockIdx y blockDim y threadIdx y if x lt width amp amp y height uchar4 data Read from input surface surf2Dread amp data inputSurfObj x 4 y Write to output surface SME LDS Cece GUEISXUESUUEiROIS p zs 9 dz x x Host code int main Allocate CUDA arrays in device memory cudaChannelFormatDesc channelDesc cudaCreateChannelDesc 8 8 8 8 cudaChannelFormatKindUnsigned cudaArray culnputArray cudaMallocArray amp culnputArray amp channelDesc width height cudaArraySurfaceLoadStore cudaArray cuOutputArray cudaMallocArray amp cuOutputArray amp channelDesc width height cudaArraySurfaceLoadStore Copy to device memory some data located at address h data in host memory cudaMemcpyToArray cuInputArray 0 0 h data size cudaMemcpyHostToDevice Specify surface struct cudaResourceDesc resDesc memset amp resDesc 0 sizeof resDesc resDesc resType cudaResourceTypeArray Create the surface objects mesDescmuneseda
254. memory www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 29 Programming Interface gt cudaHostRegister page locks a range of memory allocated by malloc see reference manual for limitations Using page locked host memory has several benefits gt Copies between page locked host memory and device memory can be performed concurrently with kernel execution for some devices as mentioned in Asynchronous Concurrent Execution gt On some devices page locked host memory can be mapped into the address space of the device eliminating the need to copy it to or from device memory as detailed in Mapped Memory gt Onsystems with a front side bus bandwidth between host memory and device memory is higher if host memory is allocated as page locked and even higher if in addition it is allocated as write combining as described in Write Combining Memory Page locked host memory is a scarce resource however so allocations in page locked memory will start failing long before allocations in pageable memory In addition by reducing the amount of physical memory available to the operating system for paging consuming too much page locked memory reduces overall system performance The simple zero copy CUDA sample comes with a detailed document on the page locked memory APIs 3 2 4 1 Portable Memory A block of page locked memory can be used in conjunction with any device in the system see Multi Device System for more detai
255. mentioned PTX level declaration CUDA level Declaration of cudaGetParameterBuffer exc NEW Cleves void cudaGetParameterBuffer size t alignment size t size The first parameter specifies the alignment requirement of the parameter buffer and the second parameter the size requirement in bytes In the current implementation the parameter buffer returned by cudaGetParameterBuf fer is always guaranteed to be 64 byte aligned and the alignment requirement parameter is ignored However it is recommended to pass the correct alignment requirement value which is the largest alignment of any parameter to be placed in the parameter buffer to cudaGetParameterBuffer to ensure portability in the future C 3 2 2 Parameter Buffer Layout Parameter reordering in the parameter buffer is prohibited and each individual parameter placed in the parameter buffer is required to be aligned That is each parameter must be placed at the n byte in the parameter buffer where n is the smallest multiple of the parameter size that is greater than the offset of the last byte taken by the preceding parameter The maximum size of the parameter buffer is 4KB For a more detailed description of PTX code generated by the CUDA compiler please refer to the PTX 3 5 specification C 3 3 Toolkit Support for Dynamic Parallelism C 3 3 1 Including Device Runtime API in CUDA Code Similar to the host side runtime API prototypes for the CUDA device
256. n are performed within a single thread block as much as possible 5 2 2 Device Level At a lower level the application should maximize parallel execution between the multiprocessors of a device Multiple kernels can execute concurrently on a device so maximum utilization can also be achieved by using streams to enable enough kernels to execute concurrently as described in Asynchronous Concurrent Execution 5 2 3 Multiprocessor Level At an even lower level the application should maximize parallel execution between the various functional units within a multiprocessor As described in Hardware Multithreading a GPU multiprocessor relies on thread level parallelism to maximize utilization of its functional units Utilization is therefore directly linked to the number of resident warps At every instruction issue time a warp scheduler selects a warp that is ready to execute its next instruction if any and issues the instruction to the active threads of the warp The number of clock cycles it takes for a warp to be ready to execute its next instruction is called the latency and full utilization is achieved when all warp schedulers always have some instruction to issue for some warp at every clock cycle during that latency period or in other words when latency is completely hidden The number of instructions required to hide a latency of L clock cycles depends on the respective throughputs of these instructions see Arithmetic Instructi
257. n execution behavior as a whole J 1 2 Data Migration and Coherency Unified Memory attempts to optimize memory performance by migrating data towards the device where it is being accessed that is moving data to host memory if the CPU is accessing it and to device memory if the GPU will access it Data migration is fundamental to Unified Memory but is transparent to a program The system will try www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 234 Unified Memory Programming to place data in the location where it can most efficiently be accessed without violating coherency The physical location of data is invisible to a program and may be changed at any time but accesses to the data s virtual address will remain valid and coherent from any processor regardless of locality Note that maintaining coherence is the primary requirement ahead of performance within the constraints of the host operating system the system is permitted to either fail accesses or move data in order to maintain global coherence between processors J 1 3 Multi GPU Support Multi GPU systems are able to use managed memory but data does not migrate between GPUs Managed memory allocation behaves identically to unmanaged memory allocated using cudaMalloc the current active device is the home for the physical allocation and all other GPUs receive peer mappings to the memory This means that other GPUs in the system will access the memory at
258. n mind Looking at the earlier synchronization example cewce menage imie zp y 27 globel osi karnel 4 x 10 int main cudaStream t streaml cudaStreamCreate amp streaml cudaStreamAttachMemAsync streaml amp y 0 cudaMemAttachHost cudaDeviceSynchronize EVO E Eor Host diss I meni ONG CCS kernel 1 1 0 streaml gt gt gt Note Launches into streaml y 20 Success a kernel is running but y has been associated with no stream return O Here we explicitly associate y with host accessibility thus enabling access at all times from the CPU As before note the absence of cudaDeviceSynchronize before the access Accesses to y by the GPU running kernel will now produce undefined results Now here s an example of where things can go wrong This may seem like it should be okay but it s not BR cen anacgec mE z y 2 glo sal v id cnc NET x 10 int main cudaStream t streaml cudaStreamCreate amp streaml wa cudaStreamAttachMemAsync streaml amp x Associate x with streaml cudaDeviceSynchronize M Wait for N etse meni Co occut kernel lt lt lt 1 i 0 streami gt gt gt Note Launches into streaml y 20 ERROR y is still associated globally with all streams by default return 0 Note how the access to y will cause an error because even though x has been associated with a stream we have told the
259. n than the maximum Driver API version against which any application plug ins or libraries that must run on that system were built gt All plug ins and libraries used by an application must use the same version of the CUDA Runtime unless they statically link to the Runtime in which case multiple versions of the runtime can coexist in the same process space Note that if nvcc is used to link the application the static version of the CUDA Runtime library will be used by default and all CUDA Toolkit libraries are statically linked against the CUDA Runtime gt All plug ins and libraries used by an application must use the same version of any libraries that use the runtime such as cuFFT cuBLAS unless statically linking to those libraries www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 66 Programming Interface Apps Apps Apps Libs amp Libs amp Libs amp Plug ins Plug ins Plug ins Compatible Incompatible Figure 11 The Driver API Is Backward but Not Forward Compatible 3 4 Compute Modes On Tesla solutions running Windows Server 2008 and later or Linux one can set any device in a system in one of the three following modes using NVIDIA s System Management Interface nvidia smi which is a tool distributed as part of the driver gt Default compute mode Multiple host threads can use the device by calling cudaSetDevice on this device when using the runtime API or by making current a conte
260. n variables defined in Built in Variables E 2 6 Run Time Type Information RTTI The following RTTI related features are supported in host code but not in device code gt typeidoperator gt std type info gt dynamic castoperator E 2 7 Exception Handling Exception handling is only supported in host code but not in device code E 2 8 Standard Library Standard libraries are only supported in host code but not in device code unless specified otherwise www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 179 C C Language Support E 2 9 Functions E 2 9 1 External Linkage A call within some device code of a function declared with the extern qualifier is only allowed if the function is defined within the same compilation unit as the device code i e a single file or several files linked together with relocatable device code and nvlink E 2 9 2 Compiler generated functions The execution space qualifiers host device _ fora compiler generated function are the union of the execution space qualifiers of all the functions that invoke it note thata global caller will be treated asa device caller for this analysis For example class Base Tone pP Publier host device Base void x 10 H class Derived public Base jones VA H class Other public Base INE wap he evi ce voices ool ose Derived D1 Other D2 host void bar void Other D3 Here th
261. nd Hardware Multithreading describe the architecture features of the streaming multiprocessor that are common to all devices Compute Capability 2 x Compute Capability 3 x and Compute Capability 5 x provide the specifics for devices of compute capabilities 2 x 3 x and 5 x respectively The NVIDIA GPU architecture uses a little endian representation 4 1 SIMT Architecture The multiprocessor creates manages schedules and executes threads in groups of 32 parallel threads called warps Individual threads composing a warp start together at the same program address but they have their own instruction address counter and register state and are therefore free to branch and execute independently The term warp originates from weaving the first parallel thread technology A half warp is either the first or second half of a warp A quarter warp is either the first second third or fourth quarter of a warp When a multiprocessor is given one or more thread blocks to execute it partitions them into warps and each warp gets scheduled by a warp scheduler for execution The www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 69 Hardware Implementation way a block is partitioned into warps is always the same each warp contains threads of consecutive increasing thread IDs with the first warp containing thread 0 Thread Hierarchy describes how thread IDs relate to thread indices in the block A warp executes one common instruction a
262. nd a surface reference surfRef is accessed using tex2d texRef x y Via texRef but surf2Dread surfRef 4 x y via surfRef the byte offset of the y coordinate is internally calculated from the underlying line pitch of the CUDA array www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 54 Programming Interface The following code sample applies some simple transformation kernel to a texture 2D surfaces surface lt void 2 gt inputSurfRef surface lt void 2 outputSurfRef Simple copy kernel global void copyKernel int width int height Calculate surface coordinates unsigned int x blockIdx x blockDim threadidx x unsigned int y blockIdx y blockDim y threadIdx y if x lt width amp amp y lt height uchar4 data Read from input surface surf2Dread amp data inputSurfRef x 4 y Write to output surface Suerte wisis Lol citet COD S OT S UIS HESES C ox lt 1 sy Pp x Host code int main Allocate CUDA arrays in device memory cudaChannelFormatDesc channelDesc cudaCreateChannelDesc 8 8 8 8 cudaChannelFormatKindUnsigned cudaArray culnputArray cudaMallocArray amp culnputArray amp channelDesc width height cudaArraySurfaceLoadStore cudaArray cuOutputArray cudaMallocArray amp cuOutputArray amp channelDesc width height cudaArraySurfaceLoadStore Copy to device memory some data located at address h data in host m
263. nd runtime scheduling It is therefore unsafe to depend upon any concurrency between different thread blocks C 2 1 6 Device Management There is no multi GPU support from the device runtime the device runtime is only capable of operating on the device upon which it is currently executing It is permitted however to query properties for any CUDA capable device in the system C 2 2 Memory Model Parent and child grids share the same global and constant memory storage but have distinct local and shared memory www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 143 CUDA Dynamic Parallelism C 2 2 1 Coherence and Consistency C 2 2 1 1 Global Memory Parent and child grids have coherent access to global memory with weak consistency guarantees between child and parent There are two points in the execution of a child grid when its view of memory is fully consistent with the parent thread when the child grid is invoked by the parent and when the child grid completes as signaled by a synchronization API invocation in the parent thread All global memory operations in the parent thread prior to the child grid s invocation are visible to the child grid All memory operations of the child grid are visible to the parent after the parent has synchronized on the child grid s completion In the following example the child grid executing child_launch is only guaranteed to see the modifications to data made before the child grid w
264. ng Platform and Programming Model 4 1 3 A Scalable Programming MOdel cece eee e eee e cece eee eee ences eee eeee ene ehe eme hene 5 1 4 Document Str ct le uses eek pnt eee ee Rr RS sea Re EE A vex Pec Ru E ENS O vlan Kex eux S 7 Chapter 2 Programming Model oe oet ii erre pe veo dort o ER Orig WAR EON De EE E raRNUD ARV eSEEED SV EES 9 VCI m 9 2 2 Thread Hierarchy eese oett xx eux xx A bere RE TR E I R4 a e ex e SERV dense aves FOREN d ds 10 2 3 Memory Hierarchy ecce dee oor oo eei EIN e oor seed re esrb e tea He E Pe ERKIN RNDR 12 2 4 Heterogeneous ProgramimMing cccccsscnscccccssssesceccssssnssecsessensasseesssseseeseseseaens 14 2 5 COMPULE Capability wwe 5er ior o rte tease a NENEN EEEE EEEN RATE ETE ers 16 Chapter 3 Programming Interface cceeeeeeeeeeeeee essen enne hehe hehehe 17 3 1 Compilation With NVCC i cisteeesee e torn nrar eniran gees sieves sees cian r pra erui 17 3 1 1 Compilation Workflow oer oot oret o tren een eR RR EAEAN EE EAEAN ARENRM EK E UE 18 3 1 1 1 Offline CompllatiOn voci e eret ege ente xoa eo eh ri rr eaR Reo e wu Rae eee xri n Enea a 18 3 1 1 2 Just in Time Compilation essssssssssssesssosssssesscsssosssosooseoosossessssossossoso 18 3 1 2 Binary Compatibility oer trek oe prr ER ds dived PRR ERIS ERO ONENE CERES EEER SERERE ERES 18 3 1 3 PIX Compatibility eceer eoe ttt rtme tr ca
265. nkages eoo toan E nee AEREA dele ro an EFQU Ara RENS 180 E 2 9 2 Compiler generated fUNCtIONS cece cece cence ence eee ence eene 180 E 2 9 3 Function Paramieters eese e ete enne tarte shaves EE E EEE EE er er gears 180 E 2 9 4 Static Variables within FUNCtION ccc cececee eee ceeeeee eee eee nennen 181 E 2 9 5 Function Polnters 1 rsteeee vere rk rrt e o yua Peas bh Yn nerui vermes wr vea e eee YE 181 E 2 9 6 Function Recursion iore err neo an eva apes e eeu e ERE Ee eere kx aee rue Eur aes 181 E 2 10 CLldSS6S vin ccce ec eese tese woes eostee s men te utes e ases ost es Dosev e ite br conan eeedr men aie Se 181 E 2 10 1 Data Members orte atr vere tn ue v ebur e UN EY stecvatecevsbieehivccdhbecee 181 E 2 10 2 Function Members vies 1 cocer cerent et tre tre yr e ere UE Rex Ree ee Re E Te ey gue 181 E 2 10 3 Virtual Func HONS o 5 voies oet voee vede vds a ne eren ese pos ee oie ae Ce Y eee eydaE 181 E 2 10 4 Virtual Base Classes roce eee ett Up bie vts e vv vi Y sop ore Eye wx eiie 181 E 2 10 5 Anonymous Unions iier eerte rna enar hona honra eras E oar ER a e aa Eee aar 182 E 2 10 6 Windows Specii Cererea reenen Neon enn e eren orem oe Nur reae o aee nns union deep 182 E 2 11 Templates 4 oce terere ox Rer Roc eed Ros RR Dy PRe D pte gu Ro eee dees ees 182 E 2 12 Trigraphs and Digraphs ccseesseeeseseeeeee eene heh ehh ehh enn 183 E 2 13 Const qualified Variables
266. nline assembly with a modifier that disables caching gt Compile with the Xptxas fscm ca compilation flag in which case all reads are cached including reads that are performed using inline assembly regardless of the modifier used When caching is enabled using some the three mechanisms listed above devices of compute capability 5 2 will cache global memory reads in the unified L1 texture cache for all kernel launches except for the kernel launches for which thread blocks consume too much of the multiprocessor s resources These exceptions are reported by the profiler G 5 3 Shared Memory Shared memory has 32 banks that are organized such that successive 32 bit words map to successive banks Each bank has a bandwidth of 32 bits per clock cycle A shared memory request for a warp does not generate a bank conflict between two threads that access any address within the same 32 bit word even though the two www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 217 Compute Capabilities addresses fall in the same bank In that case for read accesses the word is broadcast to the requesting threads and for write accesses each address is written by only one of the threads which thread performs the write is undefined Figure 17 shows some examples of strided access Figure 18 shows some examples of memory read accesses that involve the broadcast mechanism www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 218
267. not start until all commands previously issued to either device have completed and gt runs to completion before any commands see Asynchronous Concurrent Execution issued after the copy to either device can start Consistent with the normal behavior of streams an asynchronous copy between the memories of two devices may overlap with copies or kernels in another stream Note that if peer to peer access is enabled between two devices via cudaDeviceEnablePeerAccess as described in Peer to Peer Memory Access peer to peer memory copy between these two devices no longer needs to be staged through the host and is therefore faster 3 2 7 Unified Virtual Address Space When the application is run as a 64 bit process a single address space is used for the host and all the devices of compute capability 2 0 and higher All host memory allocations made via CUDA API calls and all device memory allocations on supported devices are within this virtual address range As a consequence gt The location of any memory on the host allocated through CUDA or on any of the devices which use the unified address space can be determined from the value of the pointer using cudaPointerGetAttributes gt When copying to or from the memory of any device which uses the unified address space the cudaMemcpyKind parameter of cudaMemcpy can be set to cudaMemcpyDefault to determine locations from the pointers This also works for host pointers not allocate
268. ns int ub 4 FOO C Lauro 9o Oi B b initializer list with at least one non constant element This form may have better performance than a E 2 14 3 Rvalue references By default the CUDA compiler will implicitly consider std move and std forward function templates to have host __device___ execution space qualifiers and therefore they can be invoked directly from device code The nvcc flag no host device move forward will disable this behavior std move and std forward will then be considered as host functions and will not be directly invokable from device code E 2 14 4 Constexpr functions and function templates By default a constexpr function cannot be called from a function with incompatible execution space 12 The experimental nvcc flag relaxed constexpr removes 12 The restrictions are the same as with a non constexpr callee function www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 185 C C Language Support this restriction When this flag is specified host code can invoke a__ device __ constexpr function and device code can invokea host constexpr function Note that a function template instantiation may not be a constexpr function even if the corresponding template is marked with the keyword constexpr C 11 Standard Section dcl constexpr p6 E 2 14 5 Constexpr variables Let V denote a namespace scope variable or a class static member variable that has been mark
269. nter values will vary these are illustrative B 18 3 2 Per Thread Block Allocation include lt stdlib h gt _ global void mallocTest __ sheared ane detay The first thread in the block does the allocation and initialization and then shares the pointer with all other threads through shared memory so that access can easily be coalesced 64 bytes per thread are allocated if threadIdx x 0 Size it aee bloadn lt 194p data int malloc size memset data 0 size __syncthreads if CEER iene EE bp if data NULL TECOU Threads index into the memory ensuring coalescence ime Tore e elem oe me E S Of a K Gale aA Der ae block Dima ibhecadldx D 4 sehmeadiiese sx Ensure all threads complete before freeing __syncthreads Only one thread may free the memory if threadIdx x 0 free data int main cudaDeviceSetLimit cudaLimitMallocHeapSize 128 1024 1024 mallocTest 10 128 gt gt gt cudaDeviceSynchronize return 0 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 133 C Language Extensions B 18 3 3 Allocation Persisting Between Kernel Launches include lt stdlib h gt include lt stdio h gt define NUM BLOCKS 20 device int dataptr NUM BLOCKS Per block pointer __global_ void allocmem Only the first thread in the block does the allocation since we want only one all
270. ntime through the host runtime As explained in the reference manual the runtime API has a low level C style interface and a high level C style interface The texture type is defined in the high level API as a structure publicly derived from the textureReference type defined in the low level API as such struct textureReference int normalized enum cudaTextureFilterMod filterMode enum cudaTextureAddressMod addressMode 3 struct cudaChannelFormatDesc channelDesc time SRGB unsigned int maxAnisotropy enum cudaTextureFilterMod mipmapFilterMode float mipmapLevelBias iE ALONE minMipmapLevelClamp float maxMipmapLevelClamp gt normalized specifies whether texture coordinates are normalized or not gt filterMode specifies the filtering mode gt addressMode specifies the addressing mode gt channelDesc describes the format of the texel it must match the DataType argument of the texture reference declaration channelDesc is of the following type struct cudaChannelFormatDesc INE 2 5 Wp Yap W7 enum cudaChannelFormatKind f where x y z and w are equal to the number of bits of each component of the returned value and f is gt cudaChannelFormatKindSigned if these components are of signed integer type gt cudaChannelFormatKindUnsigned if they are of unsigned integer type cudaChannelFormatKindFloat if they are of floating point type gt See reference manual for sRGB maxAnisotropy mi
271. ocation per block if threadIdx x 0 leues D oJloxelelebsoss Clune imal loc Doc kpm ww dp __syncthreads Check for failure if dataptr blockIdx x NULL return Zero the data with all threads in parallel dataptr blockIdx x threadIdx x 0 Simpl xample store thread ID into each element global void usemem ineo jolie leues Deuce lich p if ptr NULL ptr threadIdx x threadIdx x Print the content of the buffer before freeing it global void freemem ie joie acapte ioloeitck lt xl n ar per l NULL printe Block d Thread d final value d n blockIdx x threadIdx x ptr threadIdx x Only free from one thread if threadIdx x 0 free ptr int main cudaDeviceSetLimit cudaLimitMallocHeapSize 128 1024 1024 Allocate memory allocmem NUM BLOCKS 10 gt gt gt Use memory usemem lt lt lt NUM BLOCKS 10 gt gt gt usemem lt lt lt NUM BLOCKS 10 gt gt gt usemem lt lt lt NUM BLOCKS 10 gt gt gt Free memory freemem NUM BLOCKS 10 gt gt gt cudaDeviceSynchronize return 0 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 134 C Language Extensions B 19 Execution Configuration Any calltoa__global___ function must specify the execution configuration for that call The execution configuration defines the dimension of the grid and
272. ode gt texRef loa 3 loaer y loat zp aime Meese p fetches from the CUDA array bound to the cubemap layered texture reference texRef using texture coordinates x y and z and index layer as described in Cubemap Layered Textures Type is equal to DataType except when readMode is equal to cudaReadModeNormalizedFloat see Texture Reference API in which case Type is equal to the matching floating point type B 8 2 20 texCubemapLayeredLod template lt class DataType enum cudaTextureReadMode readMode gt Type texCubemapLayeredLod texture lt DataType cudaTextureType3D readMode gt texRef itlhexeuE x float yn loat van Imne layses loat leveli www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 109 C Language Extensions fetches from the CUDA array bound to the two dimensional texture reference texRef using texture coordinate x y z and index layer as described in Layered Textures The level of detail is given by level Type is the same as DataType except when readMode is cudaReadModeNormalizedFloat see Texture Reference API in which case Type is the corresponding floating point type B 8 2 21 tex2Dgather template lt class DataType enum cudaTextureReadMode readMode gt Type tex2Dgather texture lt DataType cudaTextureType2D readMode gt texRef itlhowwE xp delhexwe WW Tie Como O7 fetches from the CUDA array bound to the 2D texture reference texRef using texture coordinates x
273. of size NxN and stores the result into matrix C Kernel definition _ global void MatAdd float A N N float B N N float CIN IN inte i tenacoicliliclsaesa int j threadIdx y Cty ta At fa se Bbi ale int main Kernel invocation with one block of N N 1 threads int numBlocks 1 dim3 threadsPerBlock N N MatAdd lt lt lt numBlocks threadsPerBlock gt gt gt A B C There is a limit to the number of threads per block since all threads of a block are expected to reside on the same processor core and must share the limited memory resources of that core On current GPUs a thread block may contain up to 1024 threads However a kernel can be executed by multiple equally shaped thread blocks so that the total number of threads is equal to the number of threads per block times the number of blocks Blocks are organized into a one dimensional two dimensional or three dimensional grid of thread blocks as illustrated by Figure 6 The number of thread blocks in a grid is usually dictated by the size of the data being processed or the number of processors in the system which it can greatly exceed www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 10 Programming Model Figure 6 Grid of Thread Blocks The number of threads per block and the number of blocks per grid specified in the lt lt lt gt gt gt syntax can be of type int or dim3 Two dimensional blocks or grids can b
274. ogramming language As illustrated by Figure 4 other languages application programming interfaces or directives based approaches are supported such as FORTRAN DirectCompute OpenACC www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 4 Introduction GPU Computing Applications MA LAD Mathematice Programming Languages Java Fortran Python DirectCompute Wrappers Directives e g OpenACC CER gn CUDA Enabled NVIDIA GPUs nu Kepler Architecture G TeslaK20 eForce 600 Series uadro Kepler Series compute capabilities 3 x Quadro Kep TeslaK10 Fermi Architecture GeForce 500 Series compute capabilities 2 x GeForce 400 Series Quadro Fermi Series Vul Sarles GeForce 200 Series QuadroFX Series GeForce 9 Series Quadro Plex Series Tesla 10 Series GeForce 8 Series QuadroNVS Series Tesla Architecture compute capabilities 1 x Bs cichel Mem Graphics Computing Figure 4 GPU Computing Applications CUDA is designed to support various languages and application programming interfaces 1 3 A Scalable Programming Model The advent of multicore CPUs and manycore GPUs means that mainstream processor chips are now parallel systems Furthermore their parallelism continues to scale with Moore s law The challenge is to develop application software that transparently scales its parallelism to leverage the increasing number of processor cores much as 3D graphics applications transparently scale the
275. olate a launch or memory copy that is failing 3 2 5 5 4 Implicit Synchronization Two commands from different streams cannot run concurrently if any one of the following operations is issued in between them by the host thread a page locked host memory allocation a device memory allocation a device memory set vY v v y a memory copy between two addresses to the same device memory www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 34 Programming Interface gt any CUDA command to the NULL stream gt aswitch between the L1 shared memory configurations described in Compute Capability 2 x and Compute Capability 3 x For devices that support concurrent kernel execution and are of compute capability 3 0 or lower any operation that requires a dependency check to see if a streamed kernel launch is complete gt Can start executing only when all thread blocks of all prior kernel launches from any stream in the CUDA context have started executing gt Blocks all later kernel launches from any stream in the CUDA context until the kernel launch being checked is complete Operations that require a dependency check include any other commands within the same stream as the launch being checked and any call to cudaStreamQuery on that stream Therefore applications should follow these guidelines to improve their potential for concurrent kernel execution gt All independent operations should be issued before dependent
276. ons See Configuration Options below for details The majority of reserved memory is allocated as backing store for parent kernel state for use when synchronizing on a child launch Conservatively this memory must support storing of state for the maximum number of live threads possible on the device This means that each parent generation at which cudaDeviceSynchronize is callable may require up to 150MB of device memory depending on the device configuration which will be unavailable for program use even if it is not all consumed C 4 3 1 2 Nesting and Synchronization Depth Using the device runtime one kernel may launch another kernel and that kernel may launch another and so on Each subordinate launch is considered a new nesting level and the total number of levels is the nesting depth of the program The synchronization depth is defined as the deepest level at which the program will explicitly synchronize on a child launch Typically this is one less than the nesting depth of the program but if the program does not need to call cudaDeviceSynchronize at all levels then the synchronization depth might be substantially different to the nesting depth The overall maximum nesting depth is limited to 24 but practically speaking the real limit will be the amount of memory required by the system for each new level see Memory Footprint above Any launch which would result in a kernel at a deeper level than the maximum will fail Note t
277. ons for the throughputs of various arithmetic instructions assuming maximum throughput for all instructions it is gt L for devices of compute capability 2 0 since a multiprocessor issues one instruction per warp over two clock cycles for two warps at a time as mentioned in Compute Capability 2 x gt 2L for devices of compute capability 2 1 since a multiprocessor issues a pair of instructions per warp over two clock cycles for two warps at a time as mentioned in Compute Capability 2 x gt 8L for devices of compute capability 3 x since a multiprocessor issues a pair of instructions per warp over one clock cycle for four warps at a time as mentioned in Compute Capability 3 x www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 73 Performance Guidelines For devices of compute capability 2 0 the two instructions issued every other cycle are for two different warps For devices of compute capability 2 1 the four instructions issued every other cycle are two pairs for two different warps each pair being for the same warp For devices of compute capability 3 x the eight instructions issued every cycle are four pairs for four different warps each pair being for the same warp The most common reason a warp is not ready to execute its next instruction is that the instruction s input operands are not available yet If all input operands are registers latency is caused by register dependencies i e some of the input ope
278. operations gt Synchronization of any kind should be delayed as long as possible 3 2 5 5 5 Overlapping Behavior The amount of execution overlap between two streams depends on the order in which the commands are issued to each stream and whether or not the device supports overlap of data transfer and kernel execution see Overlap of Data Transfer and Kernel Execution concurrent kernel execution see Concurrent Kernel Execution and or concurrent data transfers see Concurrent Data Transfers For example on devices that do not support concurrent data transfers the two streams of the code sample of Creation and Destruction do not overlap at all because the memory copy from host to device is issued to stream 1 after the memory copy from device to host is issued to stream 0 so it can only start once the memory copy from device to host issued to stream 0 has completed If the code is rewritten the following way and assuming the device supports overlap of data transfer and kernel execution gue use Gh e p ab XE spud cudaMemcpyAsync inputDevPtr i size hostPtr i size Size cudaMemcpyHostToDevice stream i io sine Op a lt Be sexui MyKernel lt lt lt 100 512 0 stream i gt gt gt outputDevPtr i size inputDevPtr i size size oi Ene G Of Gb Ze wearuL cudaMemcpyAsync hostPtr i size outputDevPtr i size Size cudaMemcpyDeviceToHost stream i then the memory copy from
279. or one dimensional textures bilinear interpolation for two dimensional textures and trilinear interpolation for three dimensional textures Texture Fetching gives more details on texture fetching The filtering mode is equal to cudaFilterModePoint or cudaFilterModeLinear If it is cudaFilterModePoint the returned value is the texel whose texture coordinates are the closest to the input texture coordinates If it is cudaFilterModeLinear the returned value is the linear interpolation of the two for a one dimensional texture four for a two dimensional texture or eight for a three dimensional texture texels whose texture coordinates are the closest to the input texture coordinates cudaFilterModeLinear is only valid for returned values of floating point type Texture Object API introduces the texture object API Texture Reference API introduces the texture reference API 16 Bit Floating Point Textures explains how to deal with 16 bit floating point textures Textures can also be layered as described in Layered Textures Cubemap Textures and Cubemap Layered Textures describe a special type of texture the cubemap texture Texture Gather describes a special texture fetch texture gather 3 2 11 1 1 Texture Object API A texture object is created using cudaCreateTextureObject from a resource description of type struct cudaResourceDesc which specifies the texture and from a texture description defined as such struct cudaTextureDes
280. osssossoesssssosssssessse 232 J 1 1 Simplifying GPU ProgrammMing ccecce sees cece eee ence ence esse eee eene 233 J 1 2 Data Migration and Coherency sssssssssssssssssssssessssssssssssesseesessesseesossee 234 J 1 3 M lti GPU Support iere otn rrr nane aS E tan roe eae ERE YR OEEEERKREC Sees Ya cae REN ES 235 J 1 4 System Requirements esee e rhe then rh RR ERR ERRARE senses S TAa a RAS ERAS 235 J Z Programming Model render torret rr Ea owe obalele tio gae toa EEEE are Divini e wa 235 J 2 1 Managed Memory Opt In ssseeseeeeeeeeee eene nene hehe eene tin sse E seen 235 J 2 1 1 Explicit Allocation Using cudaMallocManaged cesses 236 J 2 1 2 Global Scope Managed Variables Using managed esesees 237 J 2 2 Coherency and Concurrency seeeeceeeeeeeeee esee hene hehehe senes seen 237 J 2 2 1 GPU Exclusive Access To Managed Memory ssssssssssssssesseseesesseesesseesese 237 J 2 2 2 Explicit Synchronization and Logical GPU Activity eeeeeeeeeeeeee 238 J 2 2 3 Managing Data Visibility and Concurrent CPU GPU Access 240 J 2 2 4 Stream Association Examples sssesssssossossosssssssssessessssssssssssssssssssese 241 J 2 2 5 Stream Attach With Multithreaded Host Programs cesses 241 J 2 2 6 Advanced Topic Modular Programs and Data Access Constraints 242 J 2 2 7 Mem
281. otherwise the maximum absolute error is 5 x 102 y1 x 7 for x lt 8 otherwise the maximum absolute error is 5 x 102 yn x For x gt 1 5n the maximum absolute error is 5 x 10 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 167 Mathematical Functions D 2 Intrinsic Functions The functions from this section can only be used in device code Among these functions are the less accurate but faster versions of some of the functions of Standard Functions They have the same name prefixed with __ such as sinf x They are faster as they map to fewer native instructions The compiler has an option use_fast_math that forces each function in Table 8 to compile to its intrinsic counterpart In addition to reducing the accuracy of the affected functions it may also cause some differences in special case handling A more robust approach is to selectively replace mathematical function calls by calls to intrinsic functions only where it is merited by the performance gains and where changed properties such as reduced accuracy and different special case handling can be tolerated Table 8 Functions Affected by use_fast_math logf x logf x log2f x log2f x loglO0f x log10f x exp10f x exp10f x powf x y pow x y Functions suffixed with rn operate using the round to nearest even rounding mode Functions suffixed with rz operate using the round towards zero rounding mode Functions suff
282. ould be attached Because of this association the Unified Memory system allows CPU access to this memory region so long as all operations in stream have completed regardless of whether other streams are active In effect this constrains exclusive ownership of the managed memory region by an active GPU to per stream activity instead of whole GPU activity Most importantly if an allocation is not associated with a specific stream it is visible to all running kernels regardless of their stream This is the default visibility for a cudaMallocManaged allocation ora managed variable hence the simple case rule that the CPU may not touch the data while any kernel is running By associating an allocation with a specific stream the program makes a guarantee that only kernels launched into that stream will touch that data No error checking is performed by the Unified Memory system it is the programmer s responsibility to ensure that guarantee is honored In addition to allowing greater concurrency the use of cudaStreamAttachMemAsync can and typically does enable data transfer optimizations within the Unified Memory system that may affect latencies and other overhead www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 240 Unified Memory Programming J 2 2 4 Stream Association Examples Associating data with a stream allows fine grained control over CPU GPU concurrency but what data is visible to which streams must be kept i
283. ove to ensure that there will only be n iterations if n is less than 5 for example It is up to the programmer to make sure that the specified unroll number gives the best performance pragma unroll 1 will prevent the compiler from ever unrolling a loop If no number is specified after pragma unroll the loop is completely unrolled if its trip count is constant otherwise it is not unrolled at all B 22 SIMD Video Instructions PTX ISA version 3 0 includes SIMD Single Instruction Multiple Data video instructions which operate on pairs of 16 bit values and quads of 8 bit values These are available on devices of compute capability 3 0 The SIMD video instructions are gt vadd2 vadd4 gt vsub2 vsub4 gt vavrg2 vavrg4 gt vabsdiff2 vabsdiff4 gt vmin2 vmin4 gt vmax2 vmax4 gt vset2 vset4 PTX instructions such as the SIMD video instructions can be included in CUDA programs by way of the assembler asm statement The basic syntax of an asm statement is dsmiEenpillatesstmu gi Const aen i Olt DU me ceOms es SES CISEPTES UE ie DRY An example of using the vabsdiff4 PTX instruction is asm U vapodT i rA ie iG ebbe e srsxoleb M XUL Sail ee Vusig io MM ceeveiulic n Ma ue Mie B o a 6595 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 138 C Language Extensions This uses the vabsdiff4 instruction to compute an integer quad byte SIMD sum of absolute differences
284. pmapFilterMode mipmapLevelBias minMipmapLevelClamp and maxMipmapLevelClamp normalized addressMode and filterMode may be directly modified in host code www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 47 Programming Interface Before a kernel can use a texture reference to read from texture memory the texture reference must be bound to a texture using cudaBindTexture or cudaBindTexture2D for linear memory or cudaBindTextureToArray for CUDA arrays cudaUnbindTexture is used to unbind a texture reference Once a texture reference has been unbound it can be safely rebound to another array even if kernels that use the previously bound texture have not completed It is recommended to allocate two dimensional textures in linear memory using cudaMallocPitch and use the pitch returned by cudaMallocPitch as input parameter to cudaBindTexture2D The following code samples bind a 2D texture reference to linear memory pointed to by devPtr gt Using the low level API texture lt float cudaTextureType2D cudaReadModeElementType gt texRef textureReference texRefPtr cudaGetTextureReference amp texRefPtr amp texRef cudaChannelFormatDesc channelDesc cudaCreateChannelDesc lt float gt siza NORIS cudaBindTexture2D amp offset texRefPtr devPtr amp channelDesc width height pitch gt Using the high level API texture lt float cudaTextureType2D cudaReadModeElementType
285. preference of the current thread context which is set using cudaDeviceSetCacheConfig cuCtxSetCacheConfig see the reference manual for details If the current thread context also has no preference which is again the default setting then whichever cache configuration was most recently used for any kernel will be the one that is used unless a different cache configuration is required to launch the kernel e g due to shared memory requirements The initial configuration is 48 KB of shared memory and 16 KB of L1 cache Devices of compute capability 3 7 add an additional 64 KB of shared memory to each of the above configurations yielding 112 KB 96 KB and 80 KB shared memory per multiprocessor respectively However the maximum shared memory per thread block remains 48 KB Applications may query the L2 cache size by checking the 12CacheSize device property see Device Enumeration The maximum L2 cache size is 1 5 MB Multiprocessors are grouped into Graphics Processor Clusters GPCs A GPC includes three multiprocessors Each multiprocessor has a read only data cache of 48 KB to speed up reads from device memory It accesses this cache either directly for devices of compute capability 3 5 or 3 7 or via a texture unit that implements the various addressing modes and data filtering mentioned in Texture and Surface Memory When accessed via the texture unit the read only data cache is also referred to as texture cache www nvidia
286. pute capability 3 x or 5 x www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 220 Appendix H DRIVER API This appendix assumes knowledge of the concepts described in CUDA C Runtime The driver API is implemented in the cuda dynamic library cuda d11 or cuda so which is copied on the system during the installation of the device driver All its entry points are prefixed with cu It is a handle based imperative API Most objects are referenced by opaque handles that may be specified to functions to manipulate the objects The objects available in the driver API are summarized in Table 14 Table 14 Objects Available in the CUDA Driver API obese mde erm O OO O CUDA array CUarray Opaque container for one dimensional or two dimensional data on the device readable via texture or surface references Texture reference CUtexref Object that describes how to interpret texture memory data CUsurfref Object that describes how to read or write CUDA arrays The driver API must be initialized with cuInit before any function from the driver API is called A CUDA context must then be created that is attached to a specific device and made current to the calling host thread as detailed in Context Within a CUDA context kernels are explicitly loaded as PTX or binary objects by the host code as described in Module Kernels written in C must therefore be compiled www nvidia com CUDA C Programming Guide PG 02829 00
287. puteCache on MacOS HOME Library Application Support NVIDIA ComputeCache on Linux nv ComputeCache integer default Specifies the size in bytes of the cache is 33554432 32 MB and maximum is 4294967296 4 GB O or 1 default is 0 O or 1 default is 0 1 to 32 default 0 or 1 used by the just in time compiler Binary codes whose size exceeds the cache size are not cached Older binary codes are evicted from the cache to make room for newer binary codes if needed When set to 1 forces the device driver to ignore any binary code embedded in an application see Application Compatibility and to just in time compile embedded PTX code instead If a kernel does not have embedded PTX code it will fail to load This environment variable can be used to validate that PTX code is embedded in an application and that its just in time compilation works as expected to guarantee application forward compatibility with future architectures see Just in Time Compilation Disables when set to 1 or enables when set to 0 asynchronous kernel launches Sets the number of compute and copy engine concurrent connections work queues from the host to each device of compute capability 3 5 and above Overrides the autoboost behavior set by the auto boost default option of nvidia smi If an application requests via this environment variable a behavior that is different from nvidia smi s its request is honore
288. quired to achieve correct results over the entire argument range At present the argument reduction code for the trigonometric functions selects the fast path for arguments whose magnitude is less than 105615 0f for the single precision functions and less than 2147483648 0 for the double precision functions As the slow path requires more registers than the fast path an attempt has been made to reduce register pressure in the slow path by storing some intermediate variables in local memory which may affect performance because of local memory high latency and bandwidth see Device Memory Accesses At present 28 bytes of local memory are used by single precision functions and 44 bytes are used by double precision functions However the exact amount is subject to change Due to the lengthy computations and use of local memory in the slow path the throughput of these trigonometric functions is lower by one order of magnitude when the slow path reduction is required as opposed to the fast path reduction Integer Arithmetic Integer division and modulo operation are costly as they compiler to up to 20 instructions They can be replaced with bitwise operations in some cases If n is a power of 2 i n is equivalent to i gt gt log2 n and ivn is equivalent to i amp n 1 the compiler will perform these conversions if n is literal __brev and popc map to a single instruction and brevlland __popc11 toa few instructions u mu1
289. r i size Size cudaMemcpyDeviceToHost stream i Each stream copies its portion of input array hostPtr to array inputDevPtr in device memory processes inputDevPtr on the device by calling MyKernel and copies the result outputDevPtr back to the same portion of hostPtr Overlapping Behavior describes how the streams overlap in this example depending on the capability of the device Note that hostPtr must point to page locked host memory for any overlap to occur Streams are released by calling cudaStreamDestroy cese e a je aL E EE E cudaStreamDestroy stream i www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 33 Programming Interface cudaStreamDestroy waits for all preceding commands in the given stream to complete before destroying the stream and returning control to the host thread 3 2 5 5 2 Default Stream Kernel launches and host lt gt device memory copies that do not specify any stream parameter or equivalently that set the stream parameter to zero are issued to the default stream They are therefore executed in order For code that is compiled using the default stream per thread compilation flag or that defines the CUDA API PER THREAD DEFAULT STREAM macro before including CUDA headers cuda h and cuda runtime h the default stream is a regular stream and each host thread has its own default stream For code that is compiled using the default stream legacy compilation flag t
290. r GPU kernel launches can access it alg glieieap cudaMallocManaged void amp data length cudaMemAttachHost cudaStreamAttachMemAsync stream data cudaStreamSynchronize stream Iterate on the data in some way using both Host amp Device Ore mie 0 S SNI SISSE ET transform lt lt lt 100 256 0 stream gt gt gt in data length cudaStreamSynchronize stream host process data length CPU uses managed data convert 100 256 0 stream gt gt gt out data length cudaStreamSynchronize stream cudaStreamDestroy stream cudaFree data In this example the allocation stream association is established just once and then data is used repeatedly by both the host and device The result is much simpler code than occurs with explicitly copying data between host and device although the result is the same J 2 2 6 Advanced Topic Modular Programs and Data Access Constraints In the previous example cudaMallocManaged specifies the cudaMemAttachHost flag which creates an allocation that is initially invisible to device side execution The default allocation would be visible to all GPU kernels on all streams This ensures that there is no accidental interaction with another thread s execution in the interval between the data allocation and when the data is acquired for a specific stream Without this flag a new allocation would be considered in use on the GPU if a kernel launc
291. r in series This independence requirement allows thread blocks to be scheduled in any order across any number of cores as illustrated by Figure 5 enabling programmers to write code that scales with the number of cores Threads within a block can cooperate by sharing data through some shared memory and by synchronizing their execution to coordinate memory accesses More precisely one can specify synchronization points in the kernel by calling the syncthreads intrinsic function syncthreads acts as a barrier at which all threads in the block must wait before any is allowed to proceed Shared Memory gives an example of using shared memory For efficient cooperation the shared memory is expected to be a low latency memory near each processor core much like an L1 cache and syncthreads is expected to be lightweight 2 3 Memory Hierarchy CUDA threads may access data from multiple memory spaces during their execution as illustrated by Figure 7 Each thread has private local memory Each thread block has shared memory visible to all threads of the block and with the same lifetime as the block All threads have access to the same global memory There are also two additional read only memory spaces accessible by all threads the constant and texture memory spaces The global constant and texture memory spaces are optimized for different memory usages see Device Memory Accesses Texture www nvidia com CUDA C Programming Guide
292. rands are written by some previous instruction s whose execution has not completed yet In the case of a back to back register dependency i e some input operand is written by the previous instruction the latency is equal to the execution time of the previous instruction and the warp schedulers must schedule instructions for different warps during that time Execution time varies depending on the instruction but it is typically about 22 clock cycles for devices of compute capability 2 x and about 11 clock cycles for devices of compute capability 3 x which translates to 22 warps for devices of compute capability 2 x and 44 warps for devices of compute capability 3 x and higher still assuming that warps execute instructions with maximum throughput otherwise fewer warps are needed For devices of compute capability 2 1 and higher this is also assuming enough instruction level parallelism so that schedulers are always able to issue pairs of instructions for each warp If some input operand resides in off chip memory the latency is much higher 400 to 800 clock cycles for devices of compute capability 2 x and about 200 to 400 clock cycles for devices of compute capability 3 x The number of warps required to keep the warp schedulers busy during such high latency periods depends on the kernel code and its degree of instruction level parallelism In general more warps are required if the ratio of the number of instructions with no off chip memory op
293. rated in Figure 19 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 224 Driver API Figure 19 Library Context Management H 2 Module Modules are dynamically loadable packages of device code and data akin to DLLs in Windows that are output by nvcc see Compilation with NVCC The names for all symbols including functions global variables and texture or surface references are maintained at module scope so that modules written by independent third parties may interoperate in the same CUDA context This code sample loads a module and retrieves a handle to some kernel CUmodule cuModule cuModuleLoad amp cuModule myModule ptx CUfunction myKernel cuModuleGetFunction amp myKernel cuModule MyKernel This code sample compiles and loads a new module from PTX code and parses compilation errors define BUFFER SIZE 8192 CUmodule cuModule CUjit option options 3 void values 3 char PTXCode some PTX code char error log BUFFER SIZE int err e options 0 CU JIT ERROR LOG BUFFER values 0 void error log options 1 CU JIT ERROR LOG BUFFER SIZE BYTES values 1 void BUFFER SIZE x options 2 CU JIT TARGET FROM CUCONTEXT values 2 0 err cuModuleLoadDataEx amp cuModule PTXCode 3 options values if err CUDA SUCCESS printf Link error n s n error log www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 225 Driver API This code
294. rations Because the same program is executed for each data element there is a lower requirement for sophisticated flow control and because it is executed on many data elements and has high arithmetic intensity the memory access latency can be hidden with calculations instead of big data caches Data parallel processing maps data elements to parallel processing threads Many applications that process large data sets can use a data parallel programming model to speed up the computations In 3D rendering large sets of pixels and vertices are mapped to parallel threads Similarly image and media processing applications such as post processing of rendered images video encoding and decoding image scaling stereo vision and pattern recognition can map image blocks and pixels to parallel processing threads In fact many algorithms outside the field of image rendering and processing are accelerated by data parallel processing from general signal processing or physics simulation to computational finance or computational biology 1 2 CUDA A General Purpose Parallel Computing Platform and Programming Model In November 2006 NVIDIA introduced CUDA a general purpose parallel computing platform and programming model that leverages the parallel compute engine in NVIDIA GPUs to solve many complex computational problems in a more efficient way than on a CPU CUDA comes with a software environment that allows developers to use C as a high level pr
295. rcp rn rz ru rd x IEEE compliant Requires compute capability 2 dsqrt rn rz ru rd x IEEE compliant Requires compute capability 2 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 170 Appendix E C C LANGUAGE SUPPORT As described in Compilation with NVCC CUDA source files compiled with nvcc can include a mix of host code and device code The CUDA frontend compiler aims to emulate the host compiler behavior with respect to C input code The input source code is processed according to the C ISO IEC 14882 2003 or C ISO IEC 14882 2011 specifications and the CUDA frontend compiler aims to emulate any host compiler divergences from the ISO specification In addition the supported language is extended with CUDA specific constructs described in this document and is subject to the restrictions described below C 11 Language Features provides a support matrix for the C 11 features Restrictions lists the language restrictions Polymorphic Function Wrappers and Experimental Feature Device Lambdas describe additional features Code Samples gives code samples E 1 C 11 Language Features The following table lists new language features that have been accepted into the C 11 standard The Proposal column provides a link to the ISO C committee proposal that describes the feature while the Available in nvcc device code column indicates the first version of nvcc that contains an implementation o
296. red texture reference texRef using texture coordinates x and y and index layer as described in Texture Memory Type is equal to DataType except when readMode is equal to cudaReadModeNormalizedFloat see Texture Reference API in which case Type is equal to the matching floating point type B 8 2 15 tex2DLayeredLod template lt class DataType enum cudaTextureReadMode readMode gt Type tex2DLayeredLod texture DataType cudaTextureType2D readMode gt texRef float x float y int layer float level fetches from the CUDA array bound to the two dimensional texture reference texRef using texture coordinate x y and index layer as described in Layered Textures The level of detail is given by level Type is the same as DataType except when readMode is cudaReadModeNormalizedFloat see Texture Reference API in which case Type is the corresponding floating point type www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 108 C Language Extensions B 8 2 16 tex2DLayeredGrad template lt class DataType enum cudaTextureReadMode readMode gt Type tex2DLayeredGrad texture DataType cudaTextureType2D readMode gt texRef iElDorwE cx delere X aime dieses tlg whe dtlgeug2 ichy 2 fetches from the CUDA array bound to the two dimensional texture reference texRef using texture coordinate x y and index layer as described in Layered Textures The level of detail is derived from the dx and dy X and Y gradients
297. reduced bandwidth over the PCIe bus If peer mappings are not supported between the GPUs in the system then the managed memory pages are placed in CPU system memory zero copy memory and all GPUs will experience PCle bandwidth restrictions See Managed Memory with Multi GPU Programs for details J 1 4 System Requirements Unified Memory has three basic requirements gt a GPU with SM architecture 3 0 or higher Kepler class or newer gt a64 bit host application and operating system except on Android gt Linux or Windows J 2 Programming Model J 2 1 Managed Memory Opt In CUDA requires a program to opt in to automatic data management by either annotating a device X variable with the new _ managed keyword see the Language Integration section or by using a new cudaMallocManaged call to allocate data Managed memory must always be allocated on the heap either with an allocator or by declaring global storage It is not possible either to associate previously allocated memory with Unified Memory or to have the Unified Memory system manage a CPU or a GPU stack pointer www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 235 Unified Memory Programming J 2 1 1 Explicit Allocation Using cudaMallocManaged Unified memory is most commonly created using an allocation function that is semantically and syntactically similar to the standard CUDA allocator cudaMalloc The function description is as follow
298. rror the number and relative declaration order of device lambdas depends on CUDA ARCH if defined CUDA ARCH auto laml _ device _ recur n O fs fendif sue llem2 l cewiee zem 4p pg kernel lt lt lt 1 1 gt gt gt lam2 7 As described above the CUDA compiler replaces a device __ lambda defined in a host function with a placeholder type defined in namespace scope This placeholder type does not define a operator function equivalent to the original lambda declaration An attempt to determine the return type or parameter types of the operator function may therefore work incorrectly in host code as the code processed by the host compiler will be semantically different than the input code processed by the CUDA compiler However it is ok to introspect the return type or parameter types of the operator function within device code Example include type traits void foo void eure Tamil Ccewies recura 10g Ip Error attempt to extract the return type Mi ota _ Gevice lemoch ia bost Code std s resulg or lt Cecleyps demi Ves guys ses Ip The CUDA compiler will generate compiler diagnostics for a subset of cases described in 1 5 no diagnostic will be generated for cases 6 7 but the host compiler may fail to compile the generated code E 4 2 Additional Notes A device lambda defined inside a non static class member function is allowed to capture the this pointer The
299. rs between the host and the device as detailed in Data Transfer between Host and Device since these have much lower bandwidth than data transfers between global memory and the device That also means minimizing data transfers between global memory and the device by maximizing use of on chip memory shared memory and caches i e L1 cache available www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 77 Performance Guidelines on devices of compute capability 2 x and 3 x L2 cache available on devices of compute capability 2 x and higher texture cache and constant cache available on all devices Shared memory is equivalent to a user managed cache The application explicitly allocates and accesses it As illustrated in CUDA C Runtime a typical programming pattern is to stage data coming from device memory into shared memory in other words to have each thread of a block gt Load data from device memory to shared memory gt Synchronize with all the other threads of the block so that each thread can safely read shared memory locations that were populated by different threads gt Process the data in shared memory gt Synchronize again if necessary to make sure that shared memory has been updated with the results gt Write the results back to device memory For some applications e g for which global memory access patterns are data dependent a traditional hardware managed cache is more appropriate to exploit data
300. rted on MacOS regardless of the device and loading a module that references the assert function on Mac OS will fail void assert int expression stops the kernel execution if expression is equal to zero If the program is run within a debugger this triggers a breakpoint and the debugger can be used to inspect the current state of the device Otherwise each thread for which expression is equal to zero prints a message to stderr after synchronization with the host via cudaDeviceSynchronize cudaStreamSynchronize or cudaEventSynchronize The format of this message is as follows lt filename gt lt line number gt lt function gt plock olloelitcl loli ONCEk TOs thread threadIdx x threadIdx y threadIdx z Assertion expression failed Any subsequent host side synchronization calls made for the same device will return cudaErrorAssert No more commands can be sent to this device until cudaDeviceReset is called to reinitialize the device If expression is different from zero the kernel execution is unaffected www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 126 C Language Extensions For example the following program from source file test cu include lt assert h gt _ global void testAssert void dime le Quae ip Pie shouldmocmoncs 07 Mesa have momento cic assert 1s one This will halt kernel execution assert should be one Bt dudum ANE Euegie Chari Mar
301. s cudaError t cudaMallocManaged void devPtr sive Size unsigned int flags 0 The cudaMallocManaged function allocates size bytes of managed memory on the GPU and returns a pointer in devPtr The pointer is valid on all GPUs and the CPU in the system although program accesses to this pointer must obey the concurrency rules of the Unified Memory programming model see Coherency and Concurrency Below is a simple example showing the use of cudaMallocManaged glasal vorei joie Clie sieie petne fe Stis int main Allocate 100 bytes of memory accessible to both Host and Device code chark ep cudaMallocManaged amp s 100 Note direct Host code use of s strncpy s Hello Unified Memory n 99 Here we pass s to a kernel without explicitly copying peimemes lt lt dy i 29 cudaDeviceSynchronize Free as for normal CUDA allocations cudaFree s return 0 A program s behavior is functionally unchanged when cudaMalloc is replaced with cudaMallocManaged however the program should go on to eliminate explicit memory copies and take advantage of automatic migration Additionally dual pointers one to host and one to device memory can be eliminated In CUDA 6 0 device code is not able to call cudaMallocManaged All managed memory must be allocated from the host or at global scope see the next section Allocations on the device heap using malloc in a kernel will not b
302. s The use of host compiler specific language extensions in device code is unsupported E 2 2 Preprocessor Symbols E 2 2 1 _ CUDA_ARCH__ 1 The type signature of the following entities shall not depend on whether CUDA ARCH __ is defined or not or on a particular value of CUDA_ARCH_ gt global functions and function templates gt device and constant variables gt textures and surfaces Example if defined CUDA ARCH typedef int mytype else typedef double mytype endif device mytype xxx error xxx s type depends on _ CUDA ARCH _ global _ void foo mytype in error foo s type depends on CUDA ARCH mytype ptr ptr in 2 Ifa__global__ function template is instantiated and launched from the host then the function template must be instantiated with the same template arguments irrespective of whether CUDA ARCH is defined and regardless of the value of CUDA ARCH www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 174 C C Language Support Example Cowles ime secnulice template lt typename T gt gleise vo dicere result in __ aoet Cevice VOIE On Croic if defined CUDA ARCH kern lt lt lt 1 1 gt gt gt 1 Jl aaora ice renmite gt emis aint eo y when _ CUDA ARCH is undefined endif int main void foo cudaDeviceSynchronize return 0 3 In separate compilation mode the presence or absence of a definit
303. s a cubin object generated for compute capability X y will only execute on devices of compute capability X z where z2y 3 1 3 PTX Compatibility Some PTX instructions are only supported on devices of higher compute capabilities For example warp shuffle instructions are only supported on devices of compute capability 3 0 and above The arch compiler option specifies the compute capability that is assumed when compiling C to PTX code So code that contains warp shuffle for example must be compiled with arch sm 30 or higher PTX code produced for some specific compute capability can always be compiled to binary code of greater or equal compute capability 3 1 4 Application Compatibility To execute code on devices of specific compute capability an application must load binary or PTX code that is compatible with this compute capability as described in Binary Compatibility and PTX Compatibility In particular to be able to execute code on future architectures with higher compute capability for which no binary code can be generated yet an application must load PTX code that will be just in time compiled for these devices see Just in Time Compilation Which PTX and binary code gets embedded in a CUDA C application is controlled by the arch and code compiler options or the gencode compiler option as detailed in the nvec user manual For example MEG o CN gencode arch compute 20 code sm 20 gencode kareh compute 30 code sm 30
304. s are performed in one atomic transaction The function returns old The 64 bit version of atomicOr is only supported by devices of compute capability 3 5 and higher B 12 2 3 atomicXor int atomicXor int address int val unsigned int atomicXor unsigned int address unsigned int val unsigned long long int atomicXor unsigned long long int address unsigned long long int val reads the 32 bit or 64 bit word old located at the address address in global or shared memory computes old val and stores the result back to memory at the same address These three operations are performed in one atomic transaction The function returns old The 64 bit version of atomicXor is only supported by devices of compute capability 3 5 and higher B 13 Warp Vote Functions sue qeuLib abene jeueteyohicenes 9 int any inte predicaire unsigned int _ballot int predicate The warp vote functions allow the threads of a given warp to perform a reduction and broadcast operation These functions take as input an integer predicate from each thread in the warp and compare those values with zero The results of the comparisons are combined reduced across the active threads of the warp in one of the following ways broadcasting a single return value to each participating thread all predicate Evaluate predicate for all active threads of the warp and return non zero if and only if predicate evaluates to non zero for all o
305. s by the host compiler and compilation will fail E 2 14 6 1 Inline unnamed namespaces The following entities cannot be declared in namespace scope within an inline unnamed namespace gt device shared and constant variables gt global function and function templates gt variables with surface or texture type www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 187 C C Language Support Example inline namespace namespace N2 template lt typename T gt global void foo void Hie ieee __global__ void bar void U error template lt gt global void foo lt int gt void error device int xlb error Miconstant E0297 error Shared int x3b error texture lt int gt q2 M eror surface lt int gt s2 fii BONE he E 2 14 7 thread_local The thread_local storage specifier is not allowed in device code E 2 14 8 global functions and function templates A global function or function template cannot be declared as constexpr and cannot have trailing return type The following types are not allowed for a parameter ofa global function or function template gt rvalue reference type gt std initializer list gt restrict qualified reference type A variadic global function template has the following restrictions gt Onlyasingle pack parameter is allowed gt The pack parameter must be listed last in the template parameter list Example Hie ORS t
306. s compute capability and is listed in Table 13 A kernel from one CUDA context cannot execute concurrently with a kernel from another CUDA context Kernels that use many textures or a large amount of local memory are less likely to execute concurrently with other kernels 3 2 5 3 Overlap of Data Transfer and Kernel Execution Some devices can perform an asynchronous memory copy to or from the GPU concurrently with kernel execution Applications may query this capability by checking the asyncEngineCount device property see Device Enumeration which is greater than zero for devices that support it If host memory is involved in the copy it must be page locked It is also possible to perform an intra device copy simultaneously with kernel execution on devices that support the concurrentKernels device property and or with copies to or from the device for devices that support the asyncEngineCount property Intra www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 32 Programming Interface device copies are initiated using the standard memory copy functions with destination and source addresses residing on the same device 3 2 5 4 Concurrent Data Transfers Some devices of compute capability 2 x and higher can overlap copies to and from the device Applications may query this capability by checking the asyncEngineCount device property see Device Enumeration which is equal to 2 for devices that support it In order to be o
307. s declared as volatile the compiler assumes that its value can be changed or used at any time by another thread and therefore any reference to this variable compiles to an actual memory read or write instruction www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 178 C C Language Support E 2 4 Pointers Dereferencing a pointer either to global or shared memory in code that is executed on the host or to host memory in code that is executed on the device results in an undefined behavior most often in a segmentation fault and application termination The address obtained by taking the address of a device shared or constant variable can only be used in device code The address ofa device Or constant variable obtained through cudaGetSymbolAddress as described in Device Memory can only be used in host code As a consequence of the use of C syntax rules void pointers e g returned by malloc cannot be assigned to non void pointers without a typecast E 2 5 Operators E 2 5 1 Assignment Operator constant variables can only be assigned from the host code through runtime functions Device Memory they cannot be assigned from the device code Shared variables cannot have an initialization as part of their declaration It is not allowed to assign values to any of the built in variables defined in Built in Variables E 2 5 2 Address Operator It is not allowed to take the address of any of the built i
308. s do not call cudaDeviceSynchronize themselves This impact will depend upon the underlying implementation C 4 2 2 Dynamic parallelism enabled Kernel Overhead System software which is active when controlling dynamic launches may impose an overhead on any kernel which is running at the time whether or not it invokes kernel launches of its own This overhead arises from the device runtime s execution tracking and management software and may result in decreased performance for e g library www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 156 CUDA Dynamic Parallelism calls when made from the device compared to from the host side This overhead is in general incurred for applications that link against the device runtime library C 4 3 Implementation Restrictions and Limitations Dynamic Parallelism guarantees all semantics described in this document however certain hardware and software resources are implementation dependent and limit the scale performance and other properties of a program which uses the device runtime C 4 3 1 Runtime C 4 3 1 1 Memory Footprint The device runtime system software reserves memory for various management purposes in particular one reservation which is used for saving parent grid state during synchronization and a second reservation for tracking pending grid launches Configuration controls are available to reduce the size of these reservations in exchange for certain launch limitati
309. s much parallelism as possible and efficiently maps this parallelism to the various components of the system to keep them busy most of the time 5 2 1 Application Level At a high level the application should maximize parallel execution between the host the devices and the bus connecting the host to the devices by using asynchronous functions calls and streams as described in Asynchronous Concurrent Execution It should assign to each processor the type of work it does best serial workloads to the host parallel workloads to the devices www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 72 Performance Guidelines For the parallel workloads at points in the algorithm where parallelism is broken because some threads need to synchronize in order to share data with each other there are two cases Either these threads belong to the same block in which case they should use syncthreads and share data through shared memory within the same kernel invocation or they belong to different blocks in which case they must share data through global memory using two separate kernel invocations one for writing to and one for reading from global memory The second case is much less optimal since it adds the overhead of extra kernel invocations and global memory traffic Its occurrence should therefore be minimized by mapping the algorithm to the CUDA programming model in such a way that the computations that require inter thread communicatio
310. s predicate for all threads of the block and returns non zero if and only if predicate evaluates to non zero for all of them wae Sehen edis e is identical to__ syncthreads with the additional feature that it evaluates predicate for all threads of the block and returns non zero if and only if predicate evaluates to non zero for any of them B 7 Mathematical Functions The reference manual lists all C C standard library mathematical functions that are supported in device code and all intrinsic functions that are only supported in device code Mathematical Functions provides accuracy information for some of these functions when relevant B 8 Texture Functions Texture objects are described in Texture Object API Texture references are described in Texture Reference API Texture fetching is described in Texture Fetching www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 100 C Language Extensions B 8 1 Texture Object API B 8 1 1 tex1Dfetch template lt class T gt T tex breveh cudalextureObyiece Ceo init x fetches from the region of linear memory specified by the one dimensional texture object texObj using integer texture coordinate x tex1Dfetch only works with non normalized coordinates so only the border and clamp addressing modes are supported It does not perform any texture filtering For integer types it may optionally promote the integer to single precision floating point B 8 1 2
311. s used so the behavior would depend on which version is picked To avoid this either a cu and b cu must be compiled for the same compute arch or CUDA ARCH _ should not be used in the shared header function The compiler does not guarantee that a diagnostic will be generated for the unsupported uses of _ CUDA ARCH described above E 2 3 Qualifiers E 2 3 1 Device Memory Qualifiers The device shared and constant qualifiers are not allowed on gt class struct and union data members gt formal parameters gt local variables within a function that executes on the host Shared and constant variables have implied static storage device and constant variable definitions are only allowed in namespace scope including global namespace scope device constant and shared variables defined in namespace scope that are of class type cannot have a non empty constructor or a non empty destructor A constructor for a class type is considered empty at a point in the translation unit if it is either a trivial constructor or it satisfies all of the following conditions gt The constructor function has been defined gt The constructor function has no parameters the initializer list is empty and the function body is an empty compound statement gt Its class has no virtual functions and no virtual base classes gt The default constructors of all base classes of its class can be considered empty gt For all the nonstat
312. sample compiles links and loads a new module from multiple PTX codes and parses link and compilation errors define BUFFER SIZE 8192 CUmodule cuModule CUjit option options 6 void values 6 float walltime charter oni log BUREE RI SS EI inf oglkec S UE EE SSEZEJNT char PTXCode0 some PTX code char PTXCodel some other PTX code CUlinkState linkState int err vordo CUON size t cubinSize options 0 CU_JIT WALL TIME values 0 void amp walltime options 1 CU JIT INFO LOG BUFFER values 1 varc jimo log options 2 CU JIT INFO LOG BUFFER SIZE BYTES values 2 void iBUFFER SIZE options 3 CU JIT ERROR LOG BUFFER ellos S Groucl icone dores options 4 CU JIT ERROR LOG BUFFER SIZE BYTES values 4 void BUFFER SIZE options 5 CU JIT LOG VERBOSE values 5 void 1 cuLinkCreate 6 options values amp linkState esr culankAddData iinkState CULT INPUM PLX Gron cis IPIeosdco0 Me Siteitent Ee oce 0 EC E PRECOR if enm ECUDANSUSCESS printf Link error n s n error log err cuLinkAddData linkState CU JIT INPUT PTX wold Wee o ded MESusriltem l e oce M E ORO PEE PME DES HMM ison CU DAU SU S GE SS printf Link error n s n error_log cuLinkComplete linkState amp cubin amp cubinSize printf Link completed
313. se is when threads consume some data produced by other threads as illustrated by the following code sample of a kernel that computes the sum of an array of N numbers in one call Each block first sums a subset of the array and stores the result in global memory When all blocks are done the last block done reads each of these partial sums from global memory and sums them to obtain the final result In order to determine which block is finished last each block atomically increments a counter to signal that it is done with computing and storing its partial sum see Atomic Functions about atomic functions The last block is the one that receives the counter value equal to gridDim x 1 If no fence is placed between storing the partial sum and incrementing the counter the counter might increment before the partial sum is stored and therefore might reach gridDim x 1 and let the last block start reading partial sums before they have been actually updated in memory Memory fence functions only affect the ordering of memory operations by a thread they do not ensure that these memory operations are visible to other threads like syncthreads does for threads within a block see Synchronization Functions In www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 98 C Language Extensions the code sample below the visibility of memory operations on the result variable is ensured by declaring it as volatile see Volatile Qualifier device
314. sequential Addresses 96 128 160 192 224 256 288 Threads 0 s 81 Compute capability 2 x 3 x 5 x Memory transactions Uncached Cached 1x 32Bat 128 1x 128Bat 128 1x 32Bat 160 1x 32Bat 192 1x 32B at 224 Mis aligned accesses sequential non sequential Addresses 96 128 160 192 224 256 288 Threads 0 m 31 Compute capability 2 x 3 x 5 x Memory transactions Uncached Cached 1x 32Bat 128 1x 128Bat 128 1x 32Bat 160 1x 128B at 256 1x 32B at 192 1x 32B at 224 1x 32B at 256 Figure 16 Examples of Global Memory Accesses Examples of Global Memory Accesses by a Warp 4 Byte Word per Thread and Associated Memory Transactions for Compute Capabilities 2 x and Beyond G 4 3 Shared Memory Shared memory has 32 banks with two addressing modes that are described below The addressing mode can be queried using cudaDeviceGetSharedMemConfig and set using cudaDeviceSetSharedMemConfig see reference manual for more details Each bank has a bandwidth of 64 bits per clock cycle Figure 17 shows some examples of strided access Figure 18 shows some examples of memory read accesses that involve the broadcast mechanism 64 Bit Mode Successive 64 bit words map to successive banks www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 215 Compute Capabilities A shared memory request for a warp does not generate a bank conflict between two threads that access any sub word
315. sformKernel dimGrid dimBlock output width height angle Free device memory cudaFreeArray cuArray cudaFree output return 0 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 49 Programming Interface 3 2 11 1 3 16 Bit Floating Point Textures The 16 bit floating point or half format supported by CUDA arrays is the same as the IEEE 754 2008 binary2 format CUDA C does not support a matching data type but provides intrinsic functions to convert to and from the 32 bit floating point format via the unsigned short type float2half rn float and half2float unsigned short These functions are only supported in device code Equivalent functions for the host code can be found in the OpenEXR library for example 16 bit floating point components are promoted to 32 bit float during texture fetching before any filtering is performed A channel description for the 16 bit floating point format can be created by calling one of the cudaCreateChannelDescHalf functions 3 2 11 1 4 Layered Textures A one dimensional or two dimensional layered texture also known as texture array in Direct3D and array texture in OpenGL is a texture made up of a sequence of layers all of which are regular textures of same dimensionality size and data type A one dimensional layered texture is addressed using an integer index and a floating point texture coordinate the index denotes a layer within the sequence an
316. siec QS fetches from the CUDA array bound to the one dimensional texture reference texRef using texture coordinate x The level of detail is derived from the dx and dy X and Y gradients Type is the same as DataType except when readMode is cudaReadModeNormalizedFloat see Texture Reference API in which case Type is the corresponding floating point type B 8 2 5 tex2D template lt class DataType enum cudaTextureReadMode readMode gt Type tex2D texture DataType cudaTextureType2D readMode gt texRef Hoari rioari y fetches from the CUDA array or the region of linear memory bound to the two dimensional texture reference texRef using texture coordinates x and y Type is equal to DataType except when readMode is equal to cudaReadModeNormalizedFloat see Texture Reference API in which case Type is equal to the matching floating point type B 8 2 6 tex2DLod template lt class DataType enum cudaTextureReadMode readMode gt Type tex2DLod texture lt DataType cudaTextureType2D readMode gt texRef gloew be Cloe yp illosie levels fetches from the CUDA array bound to the two dimensional texture reference texRef using texture coordinate x y The level of detail is given by level Type is the same as DataType except when readMode is cudaReadModeNormalizedFloat see Texture Reference API in which case Type is the corresponding floating point type B 8 2 7 tex2DGrad template lt class DataType enum cu
317. ss is forbidden gt There are no constraints on concurrent inter GPU access of managed memory other than those that apply to multi GPU access of non managed memory gt There are no constraints on concurrent GPU kernels accessing managed data Note how the last point allows for races between GPU kernels as is currently the case for non managed GPU memory As mentioned previously managed memory functions identically to non managed memory from the perspective of the GPU The following code example illustrates these points int main cudaStream t streaml stream2 cudaStreamCreate amp streaml cudaStreamCreate amp stream2 int non managed managed also managed cudaMallocHost amp non managed 4 Non managed CPU accessible memory cudaMallocManaged amp managed 4 cudaMallocManaged amp also managed 4 Point 1 CPU can access non managed data kernel lt lt lt 1 1 0 streaml managed non managed 1 Point 2 CPU cannot access any managed data while GPU is busy Note we have not yet synchronized so kernel is still active also managed 2 Will issue segmentation fault Point 3 Concurrent GPU kernels can access the same data kernel lt lt lt 1 1 0 stream2 managed Point 4 Multi GPU concurrent access is also permitted cudaSetDevice 1 kernel 1 1 managed return 0 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5
318. sumbiltosis o ly SN dim3 dimGrid width dimBlock x height dimBlock y 1 createVertices lt lt lt dimGrid dimBlock positions time width height Unmap vertex buffer cudaGraphicsUnmapResources 1 amp positionsVB CUDA 0 Draw and present void releaseVB cudaGraphicsUnregisterResource positionsVB CUDA positionsVB gt Release gileisenl EE Ouen eatevesiieesisiteai i joxeriaesems EE loat iis unsigned int width unsigned int height unsigned int x blockIdx x blockDim x threadIdx x unsigned int y leylexelisItebow lt bilockDummiya ar we hiaeadleseny Calculate uv coordinates float u x float width float v y float height US wi 2549 i Ore WS ws 201 LOE Calculate simple sine wave pattern float freq 4 0f float w sinf u freq time GOSIE wr Eee ap Cime OW Sip Write positions positions y width x make float4 u w v _int_as float Oxff00ff00 www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 61 Programming Interface 3 2 12 2 2 Direct3D 10 Version ID3D10Device device struct CUSTOMVERTEX TEMIL OYMIE sx Wa AP DWORD color We ID3D10Buffer positionsVB struct cudaGraphicsResource positionsVB CUDA int main int dev Get a CUDA enabled adapter IDXGIFactory factory CreateDXGIFactory uuidof IDXGIFactory void amp factory IDXGIAdapter adapter 0 for unsign
319. surface reference must be bound to the CUDA array using cudaBindSurfaceToArray The following code samples bind a surface reference to a CUDA array cuArray gt Using the low level API surface lt void cudaSurfaceType2D gt surfRef surfaceReference surfRefPtr cudaGetSurfaceReference amp surfRefPtr surfRef cudaChannelFormatDesc channelDesc cudaGetChannelDesc amp channelDesc cuArray cudaBindSurfaceToArray surfRef cuArray amp channelDesc gt Using the high level API surface lt void cudaSurfaceType2D gt surfRef cudaBindSurfaceToArray surfRef cuArray A CUDA array must be read and written using surface functions of matching dimensionality and type and via a surface reference of matching dimensionality otherwise the results of reading and writing the CUDA array are undefined Unlike texture memory surface memory uses byte addressing This means that the x coordinate used to access a texture element via texture functions needs to be multiplied by the byte size of the element to access the same element via a surface function For example the element at texture coordinate x of a one dimensional floating point CUDA array bound to a texture reference texRef and a surface reference surfRef is read using texld texRef x via texRef but surf1Dread surfRef 4 x via surfRef Similarly the element at texture coordinate x and y of a two dimensional floating point CUDA array bound to a texture reference texRef a
320. t MASE miEpuse who aei lone uisum stim Ilewiloycle y icta LO n 7 ational Uu Eehosie vorc Jowell Gohirsiecls Sieibiniciealonak lt yrenliel O gt stig 4 in error invoking device function from host code host device void bar nvstd function lt void gt in in error invoking device function from host code ifdef CUDA ARCH sum g fe ue ww fendif CUDA ARCH www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 189 nvstd function is defined in the nvfunctional header as follows namespace nvstd C C Language Support template class RetType class ArgTypes gt class function RetType ArgTypes gt joni 3 6 s Jd teroxateie sete de rone dew cc OS EET CODO e ep device hos function nullptr t noexcept Li eser i Sot Ecco cc CS NEED cione onsite eto SET device host X function function amp amp template lt class F _Ceyiee mesic ZUMEELGN E destructor ENdeviccNEENNEOS EUNGEL ON 7 assignment operators device host function amp operator const function amp device host function amp operator function amp amp device host X function amp operator nullptr t _ Ceviea _ host EuncbonsN operator MEE swap _Cewies NOSE void swap function amp noexcept M uneen Ca ac ENdev cc _ NOSE explicit operator bool JL SSN EhOnaeIMNVO Calton Ben iva CCR CVO emoperdio clypeo E Ollie
321. t Side API It is circular and if more output is produced during kernel execution than can fit in the buffer older output is overwritten It is flushed only when one of these actions is performed gt Kernel launch via lt lt lt gt gt gt or cuLaunchKernel at the start of the launch and if the CUDA_LAUNCH_BLOCKING environment variable is set to 1 at the end of the launch as well gt Synchronization via cudaDeviceSynchronize cuCtxSynchronize cudaStreamSynchronize cuStreamSynchronize cudaEventSynchronize or cuEventSynchronize gt Memory copies via any blocking version of cudaMemcpy or cuMemcpy gt Module loading unloading via cuModuleLoad or cuModuleUnload gt Context destruction via cudaDeviceReset or cuCtxDestroy Prior to executing a stream callback added by cudaStreamAddCallback or cuStreamAddCallback Note that the buffer is not flushed automatically when the program exits The user must call cudaDeviceReset or cuCtxDestroy explicitly as shown in the examples below Internally printf uses a shared data structure and so it is possible that calling printf might change the order of execution of threads In particular a thread which calls printf might take a longer execution path than one which does not call printf and that path length is dependent upon the parameters of the printf Note however that CUDA makes no guarantees of thread execution order except at
322. t a time so full efficiency is realized when all 32 threads of a warp agree on their execution path If threads of a warp diverge via a data dependent conditional branch the warp serially executes each branch path taken disabling threads that are not on that path and when all paths complete the threads converge back to the same execution path Branch divergence occurs only within a warp different warps execute independently regardless of whether they are executing common or disjoint code paths The SIMT architecture is akin to SIMD Single Instruction Multiple Data vector organizations in that a single instruction controls multiple processing elements A key difference is that SIMD vector organizations expose the SIMD width to the software whereas SIMT instructions specify the execution and branching behavior of a single thread In contrast with SIMD vector machines SIMT enables programmers to write thread level parallel code for independent scalar threads as well as data parallel code for coordinated threads For the purposes of correctness the programmer can essentially ignore the SIMT behavior however substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge In practice this is analogous to the role of cache lines in traditional code Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for pea
323. ted Child A Child thread block or grid is one that has been launched by a Parent grid A Child grid must complete before the Parent Thread Thread Block or Grid are considered complete Thread Block Scope Objects with Thread Block Scope have the lifetime of a single Thread Block They only have defined behavior when operated on by Threads in the Thread Block that created the object and are destroyed when the Thread Block that created them is complete Device Runtime The Device Runtime refers to the runtime system and APIs available to enable Kernel Functions to use Dynamic Parallelism C 2 Execution Environment and Memory Model C 2 1 Execution Environment The CUDA execution model is based on primitives of threads thread blocks and grids with kernel functions defining the program executed by individual threads within a thread block and grid When a kernel function is invoked the grid s properties are described by an execution configuration which has a special syntax in CUDA Support for dynamic parallelism in CUDA extends the ability to configure launch and synchronize upon new grids to threads that are running on the device C 2 1 1 Parent and Child Grids A device thread that configures and launches a new grid belongs to the parent grid and the grid created by the invocation is a child grid The invocation and completion of child grids is properly nested meaning that the parent grid is not considered complete until all chi
324. tex1D template lt class T gt texl Di cudalextureObyject t texObj float x fetches from the CUDA array specified by the one dimensional texture object texObj using texture coordinate x B 8 1 3 tex1DLod template lt class T gt Rees Rod cudamexceume Obs Cr aee ET MESSIS eSI NS fetches from the CUDA array specified by the one dimensional texture object texObj using texture coordinate x at the level of detail level B 8 1 4 tex1DGrad template class T il texi DGraldi cudaTextureObyiectr eexOby Eloat x eToat dx float dy fetches from the CUDA array specified by the one dimensional texture object texObj using texture coordinate x The level of detail is derived from the X gradient dx and Y gradient dy B 8 1 5 tex2D template lt class T gt E cex2Dl euckmezttre0o ect e texo loar zp loar y fetches from the CUDA array or the region of linear memory specified by the two dimensional texture object texObj using texture coordinate x y B 8 1 6 tex2DLod template class T gess2iDieciieucdamesstumeboyec meo MEtiod Moo MEttod t Mte areae eT ED www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 101 C Language Extensions fetches from the CUDA array or the region of linear memory specified by the two dimensional texture object texObj using texture coordinate x y at level of detail level B 8 1 7 tex2DGrad template class T Tteese2iDemardiieudashessumeobsi
325. th directly and via cluster management systems that rely on Remote Desktop gt It makes these GPUs available to applications running as a Windows service i e in Session 0 However the TCC mode removes support for any graphics functionality www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 68 Chapter 4 HARDWARE IMPLEMENTATION The NVIDIA GPU architecture is built around a scalable array of multithreaded Streaming Multiprocessors SMs When a CUDA program on the host CPU invokes a kernel grid the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity The threads of a thread block execute concurrently on one multiprocessor and multiple thread blocks can execute concurrently on one multiprocessor As thread blocks terminate new blocks are launched on the vacated multiprocessors A multiprocessor is designed to execute hundreds of threads concurrently To manage such a large amount of threads it employs a unique architecture called SIMT Single Instruction Multiple Thread that is described in SIMT Architecture The instructions are pipelined to leverage instruction level parallelism within a single thread as well as thread level parallelism extensively through simultaneous hardware multithreading as detailed in Hardware Multithreading Unlike CPU cores they are issued in order however and there is no branch prediction and no speculative execution SIMT Architecture a
326. this pointer may be implicitly captured by value if any class member variables are captured in the lambda expression If the this pointer is captured and is dereferenced during GPU execution the memory pointed to by the this pointer must be accessible on the GPU otherwise the program may encounter an illegal memory access during GPU execution For example the object can be created in CUDA Unified Memory that is accessible on both the CPU and the GPU e g using placement new on a buffer allocated with cudaMallocManaged www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 196 C C Language Support E 5 Code Samples E 5 1 Data Aggregation Class class PixelRGBA pulo er EndcviceNESEeEGBATE MEME On Mcr 0 b 0 a 0 T merice kekek CEA Un sioned Chiat uns i onedio unsigned char b unsigned char a 255 r r g b b a a private Diasec Clic m Cp Id 7 oF friend PixelRGBA operator const PixelRGBA const PixelRGBA amp device PixelRGBA operator const PixelRGBA amp pl const PixelRGBA amp p2 isses JEaoxeddNelEm dise ro Ee pil ob t 2 9 p pis 2m device void func void PixelRGBA pl p2 Ube race Initialization of pl and p2 here PixelRGBA p3 pl p2 E 5 2 Derived Class device voilh operator new size t bytes MemoryPool amp p device void operator delete void MemoryPool amp p class Shape pulo er device Shape void
327. tid and tid n access the same bank whenever s n is a multiple of the number of banks i e 32 or equivalently whenever n is a multiple of 32 d where dis the greatest common divisor of 32 and s As a consequence there will be no bank conflict only if the warp size i e 32 is less than or equal to 32 d i e only if d is equal to 1 i e s is odd Figure 17 shows some examples of strided access for devices of compute capability 3 x The same examples apply for devices of compute capability 2 x However the access pattern for the example in the middle generates 2 way bank conflicts for devices of compute capability 2 x Larger Than 32 Bit Access 64 bit and 128 bit accesses are specifically handled to minimize bank conflicts as described below www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 211 Compute Capabilities Other accesses larger than 32 bit are split into 32 bit 64 bit or 128 bit accesses The following code for example struct type igbeweue xp Wp wR expen Shared MES ucyp cshut eiii struct type data shared BaseIndex tid results in three separate 32 bit reads without bank conflicts since each member is accessed with a stride of three 32 bit words 64 Bit Accesses For 64 bit accesses a bank conflict only occurs if two threads in either of the half warps access different addresses belonging to the same bank 128 Bit Accesses The majority of 128 bit accesses will cause 2 way bank
328. tion unit In the code passed to the host compiler the CUDA compiler will inject additional compiler generated code if the input CUDA translation unit contained a definition of any of the following entities gt global function or function template instantiation 13 C Standard Section basic types 14 C Standard Section expr const www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 186 C C Language Support gt device constant __ gt variables with surface or texture type The compiler generated code contains a reference to the defined entity If the entity is defined within an inline namespace and another entity of the same name and type signature is defined in an enclosing namespace this reference may be considered ambiguous by the host compiler and host compilation will fail This limitation can be avoided by using unique names for such entities defined within an inline namespace Example cewce ior Cem inline namespace N1 lece imme wees lt CUDA compiler inserts a reference to Gvar at this point in the translation unit This reference will be considered ambiguous by the host compiler and compilation will fail Example inline namespace N1 namespace N2 _ Cevige ime Cvm namespace N2 lecce iae wees lt CUDA compiler inserts reference to N2 Gvar at this point in the translation unit This reference will be considered ambiguou
329. tionally all commands in a given stream preceding the event have completed Events in stream zero are completed after all preceding tasks and commands in all streams are completed 3 2 5 6 1 Creation and Destruction The following code sample creates two events cudaEvent t start stop cudaEventCreate amp start cudaEventCreate amp stop They are destroyed this way cudaEventDestroy start cudaEventDestroy stop 3 2 5 6 2 Elapsed Time The events created in Creation and Destruction can be used to time the code sample of Creation and Destruction the following way cudaEventRecord start 0 for Stine ab Op 3L Qe peat di cudaMemcpyAsync inputDev i size inputHost i size Size cudaMemcpyHostToDevice stream i yKernel 100 512 0 stream i gt gt gt outputDev i size inputDev i size size cudaMemcpyAsync outputHost i size outputDev i size Size cudaMemcpyDeviceToHost stream i cudaEventRecord stop 0 cudaEventSynchronize stop float elapsedTime cudaEventElapsedTime amp elapsedTime start stop 3 2 5 7 Synchronous Calls When a synchronous function is called control is not returned to the host thread before the device has completed the requested task Whether the host thread will then yield block or spin can be specified by calling cudaSetDeviceFlags with some specific flags see reference manual for details before any
330. tionally converted to 32 bit floating point values in the range 0 0 1 0 or 1 0 1 0 see Texture Memory 5 4 Maximize Instruction Throughput To maximize instruction throughput the application should gt Minimize the use of arithmetic instructions with low throughput this includes trading precision for speed when it does not affect the end result such as using intrinsic instead of regular functions intrinsic functions are listed in Intrinsic Functions single precision instead of double precision or flushing denormalized numbers to zero gt Minimize divergent warps caused by control flow instructions as detailed in Control Flow Instructions gt Reduce the number of instructions for example by optimizing out synchronization points whenever possible as described in Synchronization Instruction or by using restricted pointers as described in restrict In this section throughputs are given in number of operations per clock cycle per multiprocessor For a warp size of 32 one instruction corresponds to 32 operations so if N is the number of operations per clock cycle the instruction throughput is N 32 instructions per clock cycle All throughputs are for one multiprocessor They must be multiplied by the number of multiprocessors in the device to get throughput for the whole device 5 4 1 Arithmetic Instructions Table 2 gives the throughputs of the arithmetic instructions that are natively supported in hardware for devic
331. treamSynchronize and cudaStreamQuery provided it returns cudaSuccess and not cudaErrorNotReady www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 238 Unified Memory Programming where the specified stream is the only stream still executing on the GPU cudaEventSynchronize and cudaEventQuery in cases where the specified event is not followed by any device work as well as uses of cudaMemcpy and cudaMemset that are documented as being fully synchronous with respect to the host Dependencies created between streams will be followed to infer completion of other streams by synchronizing on a stream or event Dependencies can be created via cudaStreamWaitEvent or implicitly when using the default NULL stream It is legal for the CPU to access managed data from within a stream callback provided no other stream that could potentially be accessing managed data is active on the GPU In addition a callback that is not followed by any device work can be used for synchronization for example by signaling a condition variable from inside the callback otherwise CPU access is valid only for the duration of the callback s There are several important points of note gt Itis always permitted for the CPU to access non managed zero copy data while the GPU is active gt The GPU is considered active when it is running any kernel even if that kernel does not make use of managed data If a kernel might use data then acce
332. ual Functions When a function in a derived class overrides a virtual function in a base class the execution space qualifiers i e host device ontheoverridden and overriding functions must match It is not allowed to pass as an argument toa global function an object of a class with virtual functions The virtual function table is placed in global or constant memory by the compiler E 2 10 4 Virtual Base Classes It is not allowed to pass as an argument toa global function an object of a class derived from virtual base classes supported with architectures gt sm_35 www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 181 C C Language Support E 2 10 5 Anonymous Unions Member variables of a namespace scope anonymous union cannot be referenced in a global or device function E 2 10 6 Windows Specific The CUDA compiler follows the IA64 ABI for class layout while the Microsoft host compiler does not This may cause the CUDA compiler to compute the class layout and size differently than the Microsoft host compiler for a class type T that satisfies any of the following conditions or for any class type that has T as a field type or as a base class type direct or indirect gt T has virtual functions v T has a virtual base class T has multiple inheritance with more than one direct or indirect empty base class All direct and indirect base classes B of T are empty and the type of the
333. uide PG 02829 001 v7 5 144 CUDA Dynamic Parallelism be set from the host prior to launch Constant memory is inherited automatically by all child kernels from their respective parents Taking the address of a constant memory object from within a kernel thread has the same semantics as for all CUDA programs and passing that pointer from parent to child or from a child to parent is naturally supported C 2 2 1 4 Shared and Local Memory Shared and Local memory is private to a thread block or thread respectively and is not visible or coherent between parent and child Behavior is undefined when an object in one of these locations is referenced outside of the scope within which it belongs and may cause an error The NVIDIA compiler will attempt to warn if it can detect that a pointer to local or shared memory is being passed as an argument to a kernel launch At runtime the programmer may use the __isGlobal intrinsic to determine whether a pointer references global memory and so may safely be passed to a child launch Note that calls to cudaMemcpy Async or cudaMemset Async may invoke new child kernels on the device in order to preserve stream semantics As such passing shared or local memory pointers to these APIs is illegal and will return an error C 2 2 1 5 Local Memory Local memory is private storage for an executing thread and is not visible outside of that thread It is illegal to pass a pointer to local memory as a la
334. uide PG 02829 001 v7 5 24 Programming Interface column of B and computes the corresponding element of C as illustrated in Figure 9 A is therefore read B width times from global memory and B is read A height times Matrices are stored in row major order ILLUS WIPE SONNEN Meelementse I oW New E GOD typedef struct Ape WA Cle b int height float elements Matrix Thread block size define BLOCK SIZE 16 Forward declaration of the matrix multiplication kernel global void MatMulKernel const Matrix const Matrix Matrix Matrix multiplication Host code Matrix dimensions are assumed to be multiples of BLOCK SIZ void MatMul const Matrix A const Matrix B Matrix C Ei Load A and B to device memory Matrix d A d A width A width d A height A height Bize Sige A widita A helgat yet ie lheeie p cudaMalloc amp d A elements size cudaMemcpy d A elements A elements size cudaMemcpyHostToDevice Matrix d B e Bowlen B o wiotny C B hes B3 peigne size B width B height sizeof float cudaMalloc amp d B elements size cudaMemcpy d B elements B elements size cudaMemcpyHostToDevice Allocate C in device memory Matrix ce GL C wichita Cowaicleiig eb Colncicine C lneaielaue g size C width C height sizeof float cudaMalloc amp d C elements size Invoke kernel dim3 dimBlock BLOCK SIZE BLOCK SIZE dim3 dimGrid B w
335. unch argument when launching a child kernel The result of dereferencing such a local memory pointer from a child will be undefined For example the following is illegal with undefined behavior if x_array is accessed by child launch dwe sx gewesen LOs Creates x array in parent s local memory Caile lewinci lt lt lt l i gt gt gt Ese S It is sometimes difficult for a programmer to be aware of when a variable is placed into local memory by the compiler As a general rule all storage passed to a child kernel should be allocated explicitly from the global memory heap either with cudaMalloc new or by declaring device storage at global scope For example Correct value is global storage cevice aime values cevieces voici NET Welle 55 mci enasuie s Invalid value is local storage ceyace voici yl T int value 5 childs db db Eb p C 2 2 1 6 Texture Memory Writes to the global memory region over which a texture is mapped are incoherent with respect to texture accesses Coherence for texture memory is enforced at the invocation www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 145 CUDA Dynamic Parallelism of a child grid and when a child grid completes This means that writes to memory prior to a child kernel launch are reflected in texture memory accesses of the child Similarly writes to memory by a child will be reflected in the texture memory accesses by a parent
336. undaryMode cudaBoundaryModeTrap writes value data to the CUDA array bound to the one dimensional layered surface reference surfRef at coordinate x and y and index layer B 9 2 11 surfCubemapread template lt class Type gt Type surfCubemapread surface lt void cudaSurfaceTypeCubemap gt surfRef IGG be d u e Wp AONE IES boundaryMode cudaBoundaryModeTrap template lt class Type gt void surfCubemapread Type data surface lt void cudaSurfaceTypeCubemap gt surfRef Tatik ane Wen alent Eco boundaryMode cudaBoundaryModeTrap reads the CUDA array bound to the cubemap surface reference surfRef using coordinate x and y and face index face B 9 2 12 surfCubemapwrite template lt class Type gt void surfCubemapwrite Type data surface lt void cudaSurfaceTypeCubemap gt surfRef WME 3x5 TNE Svo due JE boundaryMode cudaBoundaryModeTrap writes value data to the CUDA array bound to the cubemap reference surfRef at coordinate x and y and face index ace www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 116 C Language Extensions B 9 2 13 surfCubemapLayeredread template lt class Type gt Type surfCubemapLayeredread surface lt void cudaSurfaceTypeCubemapLayered gt surfRef int x int y int layerFace boundaryMode cudaBoundaryModeTrap template lt class Type gt void surfCubemapLayeredread Type data surface lt void cudaSurfaceTypeCubemapLayered gt surfRef iMG Se
337. usive access to all managed data while any kernel operation is executing regardless of whether the specific kernel is actively using the data When managed data is used with cudaMemcpy or cudaMemset the system may choose to access the source or destination from the host or the device which will put constraints on concurrent CPU access to that data while the cudaMemcpy or cudaMemset is executing See Memcpy Memset Behavior With Managed Memory for further details In general it is not permitted for the CPU to access any managed allocations or variables while the GPU is active Concurrent CPU GPU accesses even to different managed www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 237 Unified Memory Programming memory allocations will cause a segmentation fault because the page is considered inaccessible to the CPU BD CENE CUELLO global varc kermel i x e OA int main kernel lt lt lt 1 1 gt gt gt y 2102 ERROR CPU access concurrent with GPU cudaDeviceSynchronize return OF In example above the GPU program kernel is still active when the CPU touches y Note how it occurs before cudaDeviceSynchronize This access is invalid even though the CPU is accessing different data than the GPU The program must explicitly synchronize with the GPU before accessing y cev ee maneges Lat z y 2 ENolcboo wee kerne MO x or int main kernelk lt lt i
338. vent are associated to different devices cudaStreamWaitEvent can therefore be used to synchronize multiple devices with each other Each device has its own default stream see Default Stream so commands issued to the default stream of a device may execute out of order or concurrently with respect to commands issued to the default stream of any other device 3 2 6 4 Peer to Peer Memory Access When the application is run as a 64 bit process devices of compute capability 2 0 and higher from the Tesla series may address each other s memory i e a kernel executing on one device can dereference a pointer to the memory of the other device This peer to peer memory access feature is supported between two devices if cudaDeviceCanAccessPeer returns true for these two devices Peer to peer memory access must be enabled between two devices by calling cudaDeviceEnablePeerAccess as illustrated in the following code sample Each device can support a system wide maximum of eight peer connections A unified address space is used for both devices see Unified Virtual Address Space so the same pointer can be used to address memory from both devices as shown in the code sample below cudaSetDevice 0 7ESsuUwdevaces0NdsSNEcU55emt iEllyeuE joy lze t Size 1024 sizeor db n cudaMalloc amp p0 size Allocate memory on device 0 MyKernel lt lt lt 1000 128 p0 Launch kernel on device 0 cudaSetDevice 1 Set devic
339. verlapped any host memory involved in the transfers must be page locked 3 2 5 5 Streams Applications manage the concurrent operations described above through streams A stream is a sequence of commands possibly issued by different host threads that execute in order Different streams on the other hand may execute their commands out of order with respect to one another or concurrently this behavior is not guaranteed and should therefore not be relied upon for correctness e g inter kernel communication is undefined 3 2 5 5 1 Creation and Destruction A stream is defined by creating a stream object and specifying it as the stream parameter to a sequence of kernel launches and host lt gt device memory copies The following code sample creates two streams and allocates an array hostPtr of float in page locked memory cudaStream t stream 2 forane ab p 3L x Qe eral cudaStreamCreate amp stream i ioa MEOS Eb cudaMallocHost amp hostPtr 2 size Each of these streams is defined by the following code sample as a sequence of one memory copy from host to device one kernel launch and one memory copy from device to host ious ints a Op a lt ED M CNET cudaMemcpyAsync inputDevPtr i size hostPtr i size Size cudaMemcpyHostToDevice stream i MyKernel 100 512 0 stream i gt gt gt outputDevPtr i size inputDevPtr i size size cudaMemcpyAsync hostPtr i size outputDevPt
340. very time an error occurs be it a parameter validation error or an asynchronous error cudaPeekAtLastError returns this variable cudaGetLastError returns this variable and resets it to cudaSuccess Kernel launches do not return any error code so cudaPeekAtLastError or cudaGetLastError must be called just after the kernel launch to retrieve any pre launch errors To ensure that any error returned by cudaPeekAtLastError or cudaGetLastError does not originate from calls prior to the kernel launch www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 41 Programming Interface one has to make sure that the runtime error variable is set to cudaSuccess just before the kernel launch for example by calling cudaGetLastError just before the kernel launch Kernel launches are asynchronous so to check for asynchronous errors the application must synchronize in between the kernel launch and the call to cudaPeekAtLastError or cudaGetLastError Note that cudaErrorNotReady that may be returned by cudaStreamQuery and cudaEventQuery is not considered an error and is therefore not reported by cudaPeekAtLastError or cudaGetLastError 3 2 10 Call Stack On devices of compute capability 2 x and higher the size of the call stack can be queried using cudaDeviceGetLimit and set using cudaDeviceSetLimit When the call stack overflows the kernel call fails with a stack overflow error if the application is run
341. vision fdividef x y see Intrinsic Functions provides faster single precision floating point division than the division operator Single Precision Floating Point Reciprocal Square Root To preserve IEEE 754 semantics the compiler can optimize 1 0 sqrtf into rsqrtf only when both reciprocal and square root are approximate i e with prec div false and prec sqrt false It is therefore recommended to invoke rsqrt directly where desired 4 for GeForce GPUs 8 for GeForce GPUs www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 85 Performance Guidelines Single Precision Floating Point Square Root Single precision floating point square root is implemented as a reciprocal square root followed by a reciprocal instead of a reciprocal square root followed by a multiplication so that it gives correct results for 0 and infinity Sine and Cosine sinf x cosf x tanf x sincosf x and corresponding double precision instructions are much more expensive and even more so if the argument x is large in magnitude More precisely the argument reduction code see Mathematical Functions for implementation comprises two code paths referred to as the fast path and the slow path respectively The fast path is used for arguments sufficiently small in magnitude and essentially consists of a few multiply add operations The slow path is used for arguments large in magnitude and consists of lengthy computations re
342. w when the system is in SLI mode First an allocation in one CUDA device on one GPU will consume memory on other GPUs that are part of the SLI configuration of the Direct3D or OpenGL device Because of this allocations may fail earlier than otherwise expected Second applications should create multiple CUDA contexts one for each GPU in the SLI configuration While this is not a strict requirement it avoids unnecessary data transfers between devices The application can use the cudaD3D 9 10 11 GetDevices for www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 65 Programming Interface Direct3D and cudaGLGetDevices for OpenGL set of calls to identify the CUDA device handle s for the device s that are performing the rendering in the current and next frame Given this information the application will typically choose the appropriate device and map Direct3D or OpenGL resources to the CUDA device returned by cudaD3D 9 10 11 GetDevices or cudaGLGetDevices when the deviceList parameter is set to cudaD3D 9 10 11 DeviceListCurrentFrame or cudaGLDeviceListCurrentFrame Please note that resource returned from cudaGraphicsD9D 9 10 11 RegisterResource and cudaGraphicsGLRegister Buffer Image must be only used on device the registration happened Therefore on SLI configurations when data for different frames is computed on different CUDA devices it is necessary to register the resources for each separatly See Direct3D Interoperab
343. word old located at the address address in global or shared memory computes the maximum of old and val and stores the result back to memory at the same address These three operations are performed in one atomic transaction The function returns old www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 119 C Language Extensions The 64 bit version of atomicMax is only supported by devices of compute capability 3 5 and higher B 12 1 6 atomiclnc unsigned int atomicInc unsigned int address unsigned int val reads the 32 bit word old located at the address address in global or shared memory computes old gt val 0 old 1 and stores the result back to memory at the same address These three operations are performed in one atomic transaction The function returns old B 12 1 7 atomicDec unsigned int atomicDec unsigned int address unsigned int val reads the 32 bit word old located at the address address in global or shared memory computes old 0 old gt val val old 1 andstores the result back to memory at the same address These three operations are performed in one atomic transaction The function returns old B 12 1 8 atomicCAS ine cieOn hoe Ve Min ac Giascs PER ne Conec at vedy unsigned int atomicCAS unsigned int address unsigned int compare unsigned int val unsigned long long int atomicCAS unsigned long long int address unsigned long long int compare unsign
344. xt associated to the device when using the driver API at the same time gt Exclusive process compute mode Only one CUDA context may be created on the device across all processes in the system and that context may be current to as many threads as desired within the process that created that context gt Exclusive process and thread compute mode Only one CUDA context may be created on the device across all processes in the system and that context may only be current to one thread at a time gt Prohibited compute mode No CUDA context can be created on the device This means in particular that a host thread using the runtime API without explicitly calling cudaSetDevice might be associated with a device other than device 0 if device 0 turns out to be in the exclusive process mode and used by another process or in the exclusive process and thread mode and used by another thread or in prohibited www nvidia com CUDA C Programming Guide PG 02829 001_v7 5 67 Programming Interface mode cudaSetValidDevices can be used to set a device from a prioritized list of devices Applications may query the compute mode of a device by checking the computeMode device property see Device Enumeration 3 5 Mode Switches GPUs that have a display output dedicate some DRAM memory to the so called primary surface which is used to refresh the display device whose output is viewed by the user When users initiate a mode switch of the display
345. xture reference to the texture through runtime functions as described in Texture Reference API several distinct texture references might be bound to the same texture or to textures that overlap in memory A texture can be any region of linear memory or a CUDA array described in CUDA Arrays www nvidia com CUDA C Programming Guide PG 02829 001 v7 5 42 Programming Interface gt ts dimensionality that specifies whether the texture is addressed as a one dimensional array using one texture coordinate a two dimensional array using two texture coordinates or a three dimensional array using three texture coordinates Elements of the array are called texels short for texture elements The texture width height and depth refer to the size of the array in each dimension Table 13 lists the maximum texture width height and depth depending on the compute capability of the device gt The type of a texel which is restricted to the basic integer and single precision floating point types and any of the 1 2 and 4 component vector types defined in char short int long longlong float double that are derived from the basic integer and single precision floating point types gt The read mode which is equal to cudaReadModeNormalizedFloat or cudaReadModeElementType If it is cudaReadModeNormalizedFloat and the type of the texel is a 16 bit or 8 bit integer type the value returned by the texture fetch is actually returned as floating point typ
346. y is specific to each type of memory and described in the following sections For example for global memory as a general rule the more scattered the addresses are the more reduced the throughput is Global Memory Global memory resides in device memory and device memory is accessed via 32 64 or 128 byte memory transactions These memory transactions must be naturally aligned Only the 32 64 or 128 byte segments of device memory that are aligned to their size i e whose first address is a multiple of their size can be read or written by memory transactions When a warp executes an instruction that accesses global memory it coalesces the memory accesses of the threads within the warp into one or more of these memory transactions depending on the size of the word accessed by each thread and the distribution of the memory addresses across the threads In general the more transactions are necessary the more unused words are transferred in addition to the words accessed by the threads reducing the instruction throughput accordingly For example if a 32 byte memory transaction is generated for each thread s 4 byte access throughput is divided by 8 How many transactions are necessary and how much throughput is ultimately affected varies with the compute capability of the device Compute Capability 2 x Compute Capability 3 x and Compute Capability 5 x give more details on how global memory accesses are handled for various compute capa
347. y to insert a callback at any point into a stream via cudaStreamAddCallback A callback is a function that is executed on the host once all commands issued to the stream before the callback have completed Callbacks in stream 0 are executed once all preceding tasks and commands issued in all streams before the callback have completed The following code sample adds the callback function MyCallback to each of two streams after issuing a host to device memory copy a kernel launch and a device to host memory copy into each stream The callback will begin execution on the host after each of the device to host memory copies completes void CUDART CB MyCallback cudaStream t stream cudaError t status void data printf Inside callback d n size t data iore Guize tc x Of c 2p ux 4 cudaMemcpyAsync devPtrIn i hostPtr i size cudaMemcpyHostToDevice stream i MyKernel lt lt lt 100 512 0 stream i gt gt gt devPtrOut i devPtrIn i size cudaMemcpyAsync hostPtr i devPtrOut i size cudaMemcpyDeviceToHost stream i cudaStreamAddCallback stream i MyCallback void i 0 The commands that are issued in a stream or all commands issued to any stream if the callback is issued to stream 0 after a callback do not start executing before the callback has completed The last parameter of cudaStreamAddCallback is reserved for future use A callback must not make CUDA API calls directly or indirectly as

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