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20A017-00 E4 User Manual - MMC Media MicroComputer

1. J4 MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 Functional Description 2 14 2 3 Rear I O using VMEbus PO Ethernet As an option the A17 provides backplane Ethernet through VMEbus connector PO In this case the two additional Gigabit channels LAN3 and LANA are accessible at the rear The two link ports are connected in compliance with ANSI VITA 31 1 2003 LANG is connected to LPa of the backplane and LANA is connected to LPb The following table gives the pin assignment for PO Table 14 Pin assignment of VMEbus rear I O connector PO 95 pin type B modified Ethernet F E D C B A 1 GND j 2 GND GND 3 GND GND 4 GND GND 5 GND GND 6 GND s 7 GND GND 19 GND Table 15 Signal mnemonics of VMEbus rear I O connector PO Ethernet Signal Direction Function Power GND Digital ground MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 MENMON 3 MENMON 3 1 General MENMON is the CPU board firmware that is invoked when the system is powered on The basic tasks of MENMON are Initialize the CPU and its peripherals Load the FPGA code Set VMEbus bridge inbound outbound windows PCI auto configuration Perform self test Provide debug diagnostic features on MENMON command line Interaction with the user via touch panel TFT display Boot operating system
2. Table 24 MENMON System parameters for console selection and configuration Parameter ER User alias Description Default Access cbr baud Baud rate of all UART consoles 9600 Read write decimal default 9600 baud 8n1 con0 con3 CLUN of console 0 3 cond 08 COM1 Read write CLUN 0x00 disable cont 09 COM2 CLUN 0xF F autoselect next avail con2 00 none able console conO is implicitly the debug console gong SQ Hone ecl CLUN of attached network interface OxFF Read write hex CLUN 0x00 none CLUN 0xFF first available Ether net gcon CLUN of graphics device to display 0xFF AUTO Read write boot logo CLUN 0x00 disable CLUN 0xF F Autoselect first avail able graphics console hdp HTTP server TCP port decimal 1 Read write 0 don t start telnet server 1 use default port 23 else TCP port for telnet server tdp Telnet server TCP port decimal 1 Read write 0 don t start HTTP server 1 use default port 80 else TCP port for HTTP server MEN Mikro Elektronik GmbH 53 20A017 00 E4 2010 11 22 MENMON 3 6 2 Abort Pin Since the A17 has no real abort button it is simulated by connecting pin 8 ABORT to pin 7 GND on the test connector If the abort pin is detected asserted the secondary MENMON is not invoked the fallback FPGA image is loaded MENMON uses default parameters such as baud rate console port deactivates the watchdog and enters t
3. Update firmware or operating system The following description only includes board specific features For a general x description and in depth details on MENMON please refer to the MENMON 2nd Edition User Manual MEN Mikro Elektronik GmbH 42 20A017 00 E4 2010 11 22 3 1 1 State Diagram MENMON Figure 5 MENMON State diagram Degraded Mode Full Mode z Degraded Mode S do CPU early init Check if secondary MENMON valid Earlylnit Secondary MENMON not valid or abort pin set Y d DegradedStartup StartupPrologue Determine clocks I2C controller init SYSPARAM init Init early MMBIOS dev Check for D pressed Parse SO DIMM SPD Init DRAM Check for d pressed Quick DRAM test E E L Secondary MENMON valid BEEN Secondary MENMON D d pressed DRAM not working DRAM ok v Relocating MainState Full Mode y A FullStartup N Init heap in DRAM StartupPrologue i MainState MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 Figure 6 MENMON State diagram main state MENMON 7 Main State Init 4 N Init on chip MMBIOS devs PCI autoconfig RTC init FPGA load Init further MMBIOS devs Check for user abort No user intervention do start network servers Y Screen oriented Main menu
4. a a nye na s au kan a 33 3 6 4 MENMON BIOS Logical Units seles KK KS 56 3 05 System Parametets avo awate PI Dur pP Er XA PI 57 3 7 MENMON Commands s ossi e rr mm RR ERR E 63 4 Organization of the Board eeeeeeeeee een 65 4 1 Address Mappinl 55 oer m wa duwa n i b dr W Q Sete 65 4 2 Interrupt Handling eite Rake Rae nb ares 67 43 SMBDEVICES oS pero dr perro EE l ha ar r RU 68 44 PC Devices on BUSO ii 18a teas aeo arie d eb ams 68 5 Malnt nal C e skle e n ER EPKEREE TRE RR ay d ela ale se ER ER 69 S Jonhium Battery 3222 rox 4 5 4 54 aE h p Certo e ei 69 6 Appendix ear reb er ERREUR E y ees y y een 70 6 1 Literature and Web Resources 1 1 0 0 0 0 ce eese 70 Ola POWTEC guly ca Qa b awa bke ye Eq EOS Pp y 70 6 1 2 Ethernet br esas acd ra a W n asin RE 70 O13 XMCIPMC cuia pep 0203 xn 244 seuss dae ee rds 70 OLA IPOLBXDIGSS 52 12 29 934 99d Ea b cap aoe 2 DO a DECIR 71 GLS WVINMIBDUS geste exis n KO a0 ERXIRSUM Ub BA ee eds 71 6 2 Finding out the Board s Article Number Revision and Serial Number71 MEN Mikro Elektronik GmbH 12 20A017 00 E4 2010 11 22 Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 MEN Mikro Elektronik GmbH 20A017 00 E4
5. Electrostatic Discharge ESD Computer boards and components contain electrostatic sensitive devices Electrostatic discharge ESD can damage components To protect the board and other components against damage from static electricity you should follow some precautions whenever you work on your computer Power down and unplug your computer system when working on the inside Hold components by the edges and try not to touch the IC chips leads or cir cuitry Use a grounded wrist strap before handling computer components Place components on a grounded antistatic pad or on the bag that came with the component whenever the components are separated from the system Store the board only in its original ESD protected packaging Retain the original packaging in case you need to return the board to MEN for repair MEN Mikro Elektronik GmbH 8 20A017 00 E4 2010 11 22 About this Document About this Document AN This user manual describes the hardware functions of the board connection of peripheral devices and integration into a system It also provides additional information for special applications and configurations of the board The manual does not include detailed information on individual components data sheets etc A list of literature is given in the appendix History Issue Comments Date E1 First edition 2008 02 25 E2 MTBF added PO pinout corrected MENMON chapter 2008 07 28
6. SETUP E I Screen Menu E A Selftest s pressed Perform self tests User abort or degraded mode User abort or Self test error and stignfault false Check for user abort Touch pressed outside setup A TouchCalib No user intervention l Auto Update Check UN do check for update media do touch calibration Execute Auto update dialog when suitable medium found Leave dialog after 5 seconds GFE Booting Pev E mmstartup empty Jump to bootstrapper P No user intervention Execute mmstartup string L S Yy y MenmonCli d entry start network servers do process command line User abort or Boot failure MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 MENMON 3 2 Interacting with MENMON To interact with MENMON you can use the following consoles UART COMI RS232 e UART COM RS232 UARTs COM10 1x FPGA if implemented Touch panel TFT interface if present Telnet via network connection HTTP monpage via network connection The default setting of the COM ports is 9600 baud 8 data bits no parity and one stop bit 3 2 1 Entering the Setup Menu Command Line During normal boot you can abort the booting process in different ways during the self test depending on your console With a touch panel press the Setup bu
7. 2 12 Reset Button A reset button is integrated in the A17 s front panel handle A reset is triggered by releasing the handle Figure 4 Position of reset button Reset button 2 13 Status and User LEDs The A17 has four status LEDs at the front panel Three of the status LEDs are user LEDs driven by general purpose output pins of the MPC854X Programming these signals as outputs and driving them to logic 0 means the LED is turned on You can control the GPIO lines through dedicated functions provided by MEN s board support packages BSPs The implementation and usage depend on the operating system The Power Good LED shows the power status i e it is always on when the board is powered Table 10 Front panel LEDs LED No n Color Function MPC854X GPO Pin User LEDs 1 red User LED GPOUT29 1 23 Power BENE 2 yellow User LED GPOUT28 8 green User LED GPOUT27 COM1 COMZ 4 red Power Good LED MEN Mikro Elektronik GmbH HH 35 20A017 00 E4 2010 11 22 Functional Description 2 14 VMEbus Interface 2 14 1 General The A17 s VMEbus interface conforms to the VME64 specification It uses the TSI148 controller as a PCI to VMEbus bridge The TSI148 is currently the highest bandwidth VME bridge available providing PCI X to VME 2eSST performance levels while maintaining backwards compatibility with older standards TSI148 s decoupled architecture and proper buffer sizing allows a v
8. Charles Spurgeon s Ethernet Web Site Extensive information about Ethernet IEEE 802 3 local area network LAN technology www ethermanage com ethernet InterOperability Laboratory University of New Hampshire This page covers general Ethernet technology www iol unh edu services testing ethernet training 6 1 3 XMC PMC XMC PCI Express Protocol Layer Standard VITA 42 3 2006 June 2006 VMEbus International Trade Association www vita com XMC Switched Mezzanine Card Auxiliary Standard VITA 42 0 200x September 2005 Draft 0 29 VMEbus International Trade Association www vita com PMC specification Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC 1386 1 1995 IEEE www ieee org MEN Mikro Elektronik GmbH 70 20A017 00 E4 2010 11 22 Appendix 6 1 4 PCI Express PCI Express Base Specification Revision 1 0 April 29 2002 PCI Special Interest Group www pcisig com 6 1 5 VMEbus e VMEbus General The VMEbus Specification 1989 The VMEbus Handbook Wade D Peterson 1989 VMEbus International Trade Association www vita com TSI148 PCI X to VME Bridge Product information downloads and resources www tundra com genId TSI148 amp cid 18698888 6 2 Finding out the Board s Article Number Revision and Serial Number MEN user documentation may describe several different models and or hardware revisions of the A17 You can find information on the article number the board r
9. eoo se se 9e W l 4223w intri 22 2 71 DRAM System Memory 4 4 suk san 2 a eee eee 22 22 WBOGLEISSIL ys aa pp hich ENDE E S MO tA 22 2 7 3 Solid State Flash Disk os i 4 ks saa ka a say kanal a ala a 22 2145 IDRAM elan nek ene b eder Sed a81 EHO A 22 2 71 5 Additional SDRAM a zi lan ia ak anam eee 23 2 10 EEPROM i s sa H day RR Cea hk 2W b n y WEQ REUS 23 2 6 Bthernet Intera6eSs ooo voe PROP Peg eoi ede eiie us ids 24 2 8 1 Connection at Fronts 2 oed br hares dad n pr eed 24 2 92 Connection at Rea s near em dika lk a RERO 25 20 9 General Bm pp zm 23 2 8 4 TUBASeST S cest dont 00 2410 death a anaes eee nine ba oats 25 2 59 DO DBASe T ya gas n e l erae 9INTE Dr Bound 26 2 8 6 TO00Base T viue e RE ia Wa dake Cea RS REEERE 26 29 UART Interfaces 3 5312 ley ab he PEE i An a N Aro nan oleae 27 2 10 XMC SIOL aaro sid hoe Pa Ke danina 0L bad ER S9 GO T PUR 28 2 DO CODDCHOIE 3y ii 43 ho d ER pa ING RS E 4 Na 28 2 10 2 Installing an XMC Mezzanine Module 30 PANNI prc EP 31 2 11 1 Installing a PMC Mezzanine Module 32 2 11 2 FPGA I O through PMCI J4 0 0 0 0 0 2 KK KK 33 212 Rest BUON i ipee eley m o ka n l ak asco d al raria a ros dens 35 2 13 Status and User LEDS cco sca RR Rer a amp ke al Me J 35 2 14 VIMBbus AME ACE suis een IR IRE os W e UAE eU e 36
10. 2 14 4 General 12 dou vae pda ce pitas D nyay k an n e n 36 2 142 MCONMECUOMN dias earnen inan W 4 iA hana eR Idee hates wees 37 MEN Mikro Elektronik GmbH Il 20A017 00 E4 2010 11 22 Contents 3 MENMON iae RO oseen s l Qir al m tar ER EROR ent EREEE 42 Dat General msan LR ERREUR See Esta enis 42 21 State Didara gs aseo ove eg dada paged d pcne 43 3 2 Interacting with MENMON i s 2 aa 22 42 2A0 dy prs 45 3 2 1 Entering the Setup Menu Command Line 45 3 3 Configuring MENMON for Automatic Boot 45 3 4 Updating Boot Flash SSD Flash SDRAM and EEPROM 46 3 4 Update via the Serial Console using SERDL 46 3 4 Update from Network using NDL 46 3 43 Updating MENMON Code 5454 oou ace oido e 47 3 5 Diagnostic Tests sa 33 cd na aa gare erede ee ade E Es 48 9 9 Eene o iv wl n up E Spe LEES REA 48 3 5 0 SDRAM and PRAM ccs a d n RR s 49 on dE co CC 50 mod BBPRONL 25 cas 5 63 2002 Goo RICO RS Ea 40A O A50 ae n 50 2390 SSD Mash Disks 22i dre ah d ntm aene 51 2 56 COMI GON sitit 50ba eI 3 piesa to ar 51 SON REC Pr 52 3 6 MENMON Configuration and Organization 53 S01 Consoles asc cita doo ex aeo nue n dodi due vea d d LR nde 53 20 2 JNDOBDDIII nacen 2o al a ooo dd mbepiedotte bees dea ie tap b bans 54 3 6 3 MENMON Memory Mape
11. MEN Mikro Elektronik GmbH 19 20A017 00 E4 2010 11 22 Functional Description 2 5 Processor Core The board is equipped with the MPC8548 or MPC8543 processor which includes a 32 bit PowerPC e500 core the integrated host to PCI bridge Ethernet controllers and UARTs 2 5 1 General The MPC8548 3 family of processors integrates an e500v2 processor core built on Power Architecture technology with system logic required for networking telecommunications and wireless infrastructure applications The MPC8548 3 is a member of the PowerQUICC III family of devices that combine system level support for industry standard interfaces with processors that implement the embedded category of the Power Architecture technology The MPC8548 3 offers a double precision floating point auxiliary processing unit APU up to 512 KB of level 2 cache up to four integrated 10 100 1Gbits s enhanced three speed Ethernet controllers with TCP IP acceleration and classification capabilities a DDR DDR2 SDRAM memory controller a programmable interrupt controller two PC controllers a four channel DMA controller a general purpose I O port and dual universal asynchronous receiver transmitters DUART The MPC8548 3 is available with MPC8548 3E or without an integrated security engine with XOR acceleration Table 1 Processor core options on A17 Processor Type Core Frequency L2 Cache Encryption Unit Ethernet Ports MPC8548 1 GHz 1 2
12. noecc Do not use ECC even if board supports 0 No Read write it bool nspeed0 1 2 3 Speed setting for Ethernet interface AUTO Yes Read write 0 3 Possible values AUTO 10HD 10FD 100HD 100FD 1000 stdis Disable POST bool 0 No Read write stdis_XXX Disable POST test with name XXX 0 No Read write bool stdis ether Internal ETHERO 1 2 3 loopback stdis fpga FPGA test stdis fram FRAM test stdis ssd SSD Flash test stignfault Ignore POST failure continue boot 1 No Read write bool MEN Mikro Elektronik GmbH C DD DD 5 9 20A017 00 E4 2010 11 22 MENMON Parameter alias Description Standard Default Paramete r String User Access stwait Time in 1 10 seconds to stay at least in SELFTEST state decimal 0 Continue as soon as POST has fin ished 30 No Read write tdp Telnet server TCP port decimal No Read write tries Number of network tries 20 No Read write tlo Minimum timeout between network retries decimal in seconds No Read write u00 u15 User parameters hex 16 bits 0x0000 No Read write updcdis Disable auto update check bool 0 No Read write useflpar Store kerpar and mmstartup parame ters in boot Flash rather than in EEPROM bool 0 No Read write vme_in_a24 VME A24 inbound VME gt gt gt A17 map ping see Chapter 3 6 5 5 VMEbus Slave Address Mappings Param
13. 2010 11 22 Map of the board front panel and top view 4 16 Installing an XMC mezzanine Module o gt gt a sae sere h ua 30 Installing a PMC mezzanine module 0005 32 Position of reset buttons s less a pr Ah REI sees rant es 35 MENMON State diagram Degraded Mode Full Mode 43 MENMON State diagram main state eese 44 MENMON Position of abort pins on test connector bottom side 54 Position of lithium battery on A17 seeds 69 Labels giving the board s article number revision and serial number 71 Tables Tablel JProcessoreore options OD ALT ioa diode d badixi nn Rss 20 Table 2 Pin assignment of 8 pin RJ45 Ethernet front connectors EANTEAN2 l s y uye an 2 w k 6 evi vade e aA S is 24 Table 3 Signal mnemonics of Ethernet front interfaces 25 Table 4 Pin assignment of 8 pin RJ45 UART front connectors COMT GOM S ss 4s5555 4 4 3 q isiearaden Sars J s RA mara ime mages 27 Table 5 Signal mnemonics of UART front interfaces 27 Table 6 Pin assignment of 114 pin XMC connector 005 28 Table 7 Signal mnemonics of 114 pin XMC connector 29 Table 8 Assignment of 162034 GPIO controllers 000 33 Table 9 Pin assignment of PMCI board to board connector J4 FPGA I O SIPNAIS sal Ee a S db Ny sn A05000 0
14. 215 542 9577 E mail sales menmicro com www menmicro com MEN Mikro Elektronik GmbH 10 20A017 00 E4 2010 11 22 Contents Contents 1 Getting Started s s rrr b RE t E eee sale owes nk 16 Lal Map Or the Boatd s suas p tdeo o qan ode Sur phe 16 12 Configuring the Hardware 2 amp a sk rr RR Re 17 1 3 Integrating the Board into a System suk k saw al k a e a 17 1 4 Installing Operating System Software 00 0 0 00 008 18 2 Functional Description sk ss as s ne elalo e rore 19 2 1 Power SUDD Y dka cae sk seh ba e EET l ke dU n y ere d k 19 2 2 Board Supervision z k a ewe he a RR eas W n er da 19 2 3 3C IOGK Supply i ret dabe Siret nhat Sd ttp aa giis 19 2 4 Real Tim Clock i cc sa k ala Che bad may Sena ae dala y ab s 19 2 5 AROCESSOR COLe c 1255 o3 CHR REND a MCR Dd d n 2 dettes 20 2 5 1 o E bb lb nadine decals Aeon 20 2 5 24 Thermal Considerations sse o RR met 20 2 5 BUS SUUCUUTE s cse oi EPIRI CERES EACH dariy n 0000 iub 900545004 res 2 2 61 Host to PCI Bfrld s s qa la k dil Wa al We dal 21 2 6 2 Local POL D i ded bre pay maet dy oda rene Edi 21 2 6 3 PCI to VMEbuUSs Bridges s isi 0092904424052 4a4 4 21 2 08 PCDEXDpIeSS 5 62 031k 246 bebe ER dd ee s RETE 21 2 Memory and Mass Storage
15. A solid state disk SSD is a data storage device that uses solid state memory to store persistent data An SSD behaves like a conventional hard disk drive On A17 it has a PATA interface connected to the FPGA With no moving parts a solid state disk is more robust effectively eliminating the risk of mechanical failure and usually enjoys reduced seek time and latency by removing mechanical delays associated with a conventional hard disk drive Note If you would like to implement a hard disk on the A17 you can install a suit able PMC or XMC mezzanine module See also Chapter 2 10 XMC Slot on page 28 and Chapter 2 11 PMC Slots on page 31 2 7 4 FRAM The board has 128 KB non volatile FRAM memory connected to the local bus of the CPU The FRAM does not need a back up voltage for data retention MEN Mikro Elektronik GmbH 22 20A017 00 E4 2010 11 22 Functional Description 2 7 5 Additional SDRAM Up to hardware revision 03 xx of the A17 the board supports 32 MB additional DDR2 SDRAM It is controlled by the FPGA and can be used for graphics for instance From hardware revision 03 xx the A17 no longer supports FPGA controlled additional SDRAM 2 7 6 EEPROM The board has an 8 kbit serial EEPROM for factory data MENMON parameters and for the VxWorks bootline MEN Mikro Elektronik GmbH 23 20A017 00 E4 2010 11 22 P Functional Description 2 8 Ethernet Interfaces The A17 has up to four Ethernet interfaces cont
16. GAO 000000 9909009090 11 PETOpO PETOnO PETOp1 PETOn1 45V 000000 O00000 12 GND GND GA1 GND GND 999909069 e 2 13 PETOp2 PETOn2 PETOp3 PETOn3 5V 000000 AA 14 GND GND GA2 GND GND MSDA 15 PETOp4 PETOn4 PETOp5 PETOn5 5V 16 GND GND MVMRO GND GND MSCL 17 PETOp6 PETOn6 PETOp7 PETOn7 18 GND GND GND GND 19 REFCLK 0 REFCLK O WAKE ROOTO MEN Mikro Elektronik GmbH 28 20A017 00 E4 2010 11 22 MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 Functional Description Table 7 Signal mnemonics of 114 pin XMC connector Signal Direction Function Power 12V 12V out 12V supply voltage 3 3V out 3 3V supply voltage 5V VPWR out 5V supply voltage GND Ground PCle PEROp n 0 7 out PCI Express lane differential receive PETOp n O 7 in PCI Express lane differential transmit REFCLK 0 out Differential reference clock ROOTO out Root Complex enabling WAKE out Reactivation of power rails and reference clocks Other GA O 2 out laC channel select MRSTI out XMC reset in MRSTO in XMC reset out MSCL out IPMI I C serial clock MSDA in out IPMI PC serial data MVMRO out XMC write prohibit Functional Description 2 10 2 Installing an XMC Mezzanine Module Perform the following steps to install an XMC module V Power down your system and remove the A17 from the system MI Remove the filler panel fro
17. Logical Units DLUNs 56 Table 29 MENMON A17 system parameters Autodetected parameters 57 Table 30 MENMON A17 system parameters Production data 58 Table 31 MENMON A17 system parameters MENMON persistent parametets s i 322y a m re oe deed IRE Red ase Rte 59 Table 32 MENMON A17 system parameters VxWorks bootline parameters 61 Table 33 MENMON Reset causes through system parameter rststat 62 Table 34 MENMON Command reference 0 0 00 eee KK 63 Table 35 Memory map processor View W K KK RR KK KK KK KK 65 Table 36 Address mapping for PCI master a 2 wal n awa wa l a a Wa 65 MEN Mikro Elektronik GmbH 14 20A017 00 E4 2010 11 22 Table 37 Address mapping for PCI slave css sek d W n R n n 66 Table 38 Address mapping for VMEbus master kK KK KK KK KK 66 Table 39 Address mapping for VMEbus slave sk ake k ka kek 66 Table 40 Dedicated interrupt line assignment RR KK 67 Table 41 Interrupt numbering assigned by MENMON PCI 67 Table 42 Interrupt numbering assigned by MENMON PCle 67 Table43 SMB GdeVIG 56 lt xanay l dak PER Wan ay E n W 40 kec i baie 68 Table44 PCI devices On bus 0 225 sa m yan toros Rb SERE Qaziy a 68 MEN Mikro Elektronik GmbH 15 20A017 00 E4 2010 11 22 Getting
18. is fixed to 3 3 V The data width is 64 bits The FPGA is connected to the local PCI bus 2 6 3 PCI to VMEbus Bridge The board has a standard TSII48 PCI to VME bridge for connection to the VMEbus On the local PCI bus this bridge is a master 2 6 4 PCI Express On A17 eight PCI Express lanes connect the XMC mezzanine module to the PowerPC CPU They can be used as one x1 one x2 or one x4 link This means that the XMC card implementation determines the usage of these eight lanes One x8 link is also possible on request but this reduces the A17 s extended operation temperature range 2 6 4 1 PCI Express Basics PCI Express PCIe succeeds PCI and AGP and offers higher data transfer rates As opposed to the PCI bus PCIe is no parallel bus but a serial point to point connection Data is transferred using so called lanes with each lane consisting of a line pair for transmission and a second pair for reception Individual components are connected using switches At the electrical level each lane consists of two unidirectional LVDS Low Voltage Differential Signaling pairs Transmit and receive are separate differential pairs for a total of 4 data wires per lane PCIe supports full duplex operation and uses a clock rate of 1 25 GHz This results in a data rate of max 250 MB s per lane in each direction The standard PCI bus with 32 bits 33 MHz only allows a maximum of 133 MB s If you use only one lane you speak of a PCIe x1 link
19. manufacture of the part Unless agreed otherwise the products of MEN Mikro Elektronik are not suited for use in nuclear reactors and for application in medical appliances used for therapeutical purposes Application of MEN products in such plants is only possible after the user has precisely specified the operation environment and after MEN Mikro Elektronik has consequently adapted and released the product ESM ESMini MDIS MDIS4 MDISS MENMON M Module M Modules SA Adapter SA Adapters UBox USM and the MBIOS logo are trademarks of MEN Mikro Elektronik GmbH PC MIP is a registered trademark of MEN Micro Inc and SBS Technologies Inc MEN Mikro Elektronik ESMexpress MIPIOS and the MEN logo are registered trademarks of MEN Mikro Elektronik GmbH Altera Arria Avalon Cyclone Nios and Quartus are registered trademarks of Altera Corp Freescale and PowerQUICC are trademarks of Freescale Semiconductor Inc PowerPC is a registered trademark of IBM Corp OS 9 OS 9000 and SoftStax are registered trademarks of RadiSys Microware Communications Software Division Inc FasTrak and Hawk are trademarks of RadiSys Microware Communications Software Division Inc RadiSys is a registered trademark of RadiSys Corporation QNX is a registered trademark of QNX Ltd Tornado and VxWorks are registered trademarks of Wind River Systems Inc All other products or services ment
20. on port 23 HITP daemon started on port 80 MenMon gt MI Now you can use the MENMON BIOS firmware see detailed description in Chapter 3 MENMON on page 42 M Observe the installation instructions for the respective software 1 4 Installing Operating System Software The board supports Linux and VxWorks QNX and OS 9 are available on request operating system installation documentation on how to install the software A By standard no operating system is installed on the board Please refer to the You can find any software available on MEN s website MEN Mikro Elektronik GmbH 16 20A017 00 E4 2010 11 22 Functional Description 2 Functional Description The following describes the individual functions of the board and their configuration on the board There is no detailed description of the individual controller chips and the CPU They can be obtained from the data sheets or data books of the semiconductor manufacturer concerned Chapter 6 1 Literature and Web Resources on page 70 2 1 Power Supply The board is supplied with 5 V 3 3 V and 12 V via the VMEbus However 12 V may be required only by some mezzanine modules The onboard power supply generates the 1 1 V core voltage for the CPU 1 8 V for memory and for the VMEbus bridge 2 5 V for Ethernet and the 1 2 V core voltage for the FPGA 2 2 Board Supervision The board features a temperature sensor and voltage monitor The voltage monitor supervis
21. with a PCI Express x1 x2 or x4 link The second PMC only slot is connected to the onboard FPGA and can thus act as the physical layer for additional functions implemented in the FPGA The PMC XMC slots allow flexible extension to the A17 adding functions such as graphics mass storage further Ethernet or a simple FPGA backed physical layer Even more I O functions such as graphics touch CAN binary I O etc can be realized as IP cores in FPGA for the needs of the individual application The A17 comes with MENMON support This firmware BIOS can be used for bootstrapping operating systems from disk Flash or network for hardware testing or for debugging applications without running any operating system MEN Mikro Elektronik GmbH 2 20A017 00 E4 2010 11 22 Technical Data CPU Technical Data PowerPC PowerQUICC III MPC8548 MPC8548E MPC8543 or MPC8543E 800 MHz up to 1 5 GHz Please see Configuration Options for available standard versions e500 PowerPC core with MMU and double precision embedded scalar and vector floating point APU Integrated Northbridge and Southbridge Memory 2x32 KB L1 data and instruction cache 512 KB 256 KB L2 cache integrated in MPC8548 MPC8543 Up to 2 GB SDRAM system memory Soldered DDR2 with or without ECC Up to 300 MHz memory bus frequency depending on CPU e Up to 4 GB soldered Flash disk SSD solid state disk Higher capacity possible when com
22. 20A017 00 E4 2010 11 22 A17 6U VME 2eSST MPC8548 SBC Configuration example shown without heat sink User Manual man mikro elektronik gmbh n rnberg A17 6U VME 2eSST MPC8548 SBC A17 6U VME 2eSST MPC8548 SBC The A17 is an advanced PowerPC based single board computer for embedded applications and can act as a master or a slave in a legacy VMEbus environment Using the TSI148 bridge controller it provides 2eSST performance levels while maintaining backwards compatibility with older standards such as VME64 and VME32 The 2eSST protocol is based on synchronous data transfer and thus doubles the theoretical VME transaction bandwidth to transfer rates of up to 320 MB s The A17 is controlled by an MPC8548 or optionally an MPC8543 PowerPC processor alternatively with encryption unit with clock frequencies between 800 MHz and 1 5 GHz The SBC is equipped with ECC controlled DDR2 RAM for data storage with a Flash disk for program storage as well as with non volatile FRAM The board provides front panel access for two Gigabit Ethernet and two COM interfaces via four RJ45 connectors Another two Gigabit Ethernet channels are available at the optional PO rear connector to support Ethernet on the backplane complying with ANSI VITA 31 1 2003 The two PMC slots on the A17 support PMC modules working with 32 bit 33 MHz up to 64 bit 66 MHz One of the mezzanine slots supports rear I O and can also be used for XMC modules
23. 250500205255514 S ceu ERES 34 Table 10 Frontspauel BEDS adeo tan ol ot ood RUE is 35 Table 11 Pin assignment of VME64 bus connector Pl 38 Table 12 Pin assignment of VMEbus rear I O connector P2 PMC signals 39 Table 13 Signal mnemonics of VMEbus rear I O connector P2 PMC signals 40 Table 14 Pin assignment of VMEbus rear I O connector PO 95 pin type B Modified Bthertet ivre e alay A E CERE TERI CPI E a han 41 Table 15 Signal mnemonics of VMEbus rear I O connector PO Ethernet 41 Table 16 MENMON Program update files and locations 46 Table 17 MENMON Diagnostic tests Ethernet 0 005 48 Table 18 MENMON Diagnostic tests SDRAM and FRAM 49 Table 19 MENMON Diagnostic tests FPGA XY KK RR RR KK KK KK 50 Table 20 MENMON Diagnostic tests EEPROM kk kk KK KK KK KK 50 Table 21 MENMON Diagnostic tests SSD Flash disk 51 Table 22 MENMON Diagnostic tests COM1 COM2 51 Table 23 MENMON Diagnostic tests RTC i a anan salan ee eee ee eee 52 Table 24 MENMON System parameters for console selection and COMMBUTAUON ouis sym ddp UR EE Rais ed qu PRAE 53 Table 25 MENMON Address map full featured mode 55 Table 26 MENMON Boot Flash memory map kk KK KK 55 Table 27 MENMON Controller Logical Units CLUNS 56 Table 28 MENMON Device
24. 95 non condensing Relative humidity storage max 9596 non condensing Altitude 300 m to 3 000 m Shock 15 g 11 ms Bump 10 g 16 ms Vibration sinusoidal 1 g 10 150 Hz Conformal coating on request MTBF 220 017 h 40 C according to IEC TR 62380 RDF 2000 Safety PCB manufactured with a flammability rating of 94V 0 by UL recognized manu facturers EMC Conforming to EN 55022 radio disturbance IEC1000 4 2 ESD and IEC1000 4 4 burst with regard to CE conformity BIOS MENMONTM Software Support Linux VxWorks QNX on request support of the FPU is currently not provided by QNX OS 9 on request For more information on supported operating system versions and drivers see online data sheet d MEN Mikro Elektronik GmbH 5 20A017 00 E4 2010 11 22 Block Diagram RTC Watchdog PowerPC MPC8548 or MPC8543 MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 Ethernet EEE 1000Base T Ethernet 1000Base T jinasasoanaaenoaaaaaaooanasanan ANN i Ethernet i 1000Base T Ethernet 1000Base T sma com d FPGA Option User I O PMC 1 Shared slot PCI to VMEbus Bridge PMCO or e P2 Block Diagram lt gt Front connector R Rear I O connector pansa d E Options VME P1 Configuration Options Configuration Options CPU Several PowerQUICC III types with different clock frequenci
25. Always COM2 RTS CTS Groups NONAUTO ENDLESS Note Test will be skipped when COM or COM2 resp is currently used as a console This test requires an external test adapter connecting TXD and RXD To test TXD RXD a test string is sent through the UART RTS and CTS To test TXD RxD a test string is sent through the UART To test handshake lines the lines are toggled and it is checked whether input lines follow MEN Mikro Elektronik GmbH 51 20A017 00 E4 2010 11 22 MENMON 3 5 7 RTC Table 23 MENMON Diagnostic tests RTC Test Name Description Availability RTC Quick presence test of RTC Always Groups POST AUTO RTC_X Extended test of RTC Always Groups NONAUTO ENDLESS 3 5 7 1 RTC Test This is a quick presence test of the real time clock RTC and is executed on POST Checks Presence of RTC I2C access Does not check If RTC is running RTC backup voltage 3 5 7 2 Extended RTC Test Checks e Presence e g PC access RTC is running Does not check RTC backup voltage MEN Mikro Elektronik GmbH 52 20A017 00 E4 2010 11 22 MENMON 3 6 MENMON Configuration and Organization 3 6 1 Consoles You can select the active consoles by means of system parameters con0 con3 and configure the console through parameters ecl gcon hdp and tdp MENMON commands CONS xxx also give access to the console settings see Chapter 3 7 MENMON Commands page 63
26. B device path VME List VME windows MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 Organization of the Board Organization of the Board To install software on the board or to develop low level software it is essential to be familiar with the board s address and interrupt organization 4 1 Address Mappings Table 35 Memory map processor view CPU Address Range Size Description Ox 0000 0000 End of RAM 512 1024 DDR2 SDRAM 2048 MB 0x 8000 0000 CFFF FFFF 1280 MB PCI Memory Space Ox DOOO 0000 EFFF FFFF 512MB PCle Memory Space Ox F000 0000 F00F 0000 64MB CCSR Ox F200 0000 F200 3FFF Config PLD 0x F300 0000 F301 FFFF FRAM optional Ox FBOO 0000 FBFF FFFF 16 MB PCI I O ISA Space Ox FCOO 0000 FCFF FFFF 16 MB PCIe I O ISA Space Ox FF00 0000 FFFF FFFF 16 MB Boot Flash Table 36 Address mapping for PCI master CPU Address Range Mapped to PCI Space Description Ox 8000 0000 83FF FFFF 0x 8000 0000 83FF FFFF MEM Prefetchable BARs of onboard FPGA Ox 8400 0000 8FFF FFFF 0x 8400 0000 8FFF FFFF MEM Prefetchable BARs of all other PCI devices Ox 9000 0000 CFFF FFFF 0x 9000 0000 CFFF FFFF MEM Non prefetchable BARs and VME bridge Ox D000 0000 DFFF FFFF 0x D000 0000 DFFF FFFF MEM Prefetchable BARs PCle Ox E000 0000 EFFF FFFF 0x E000 0000 EFFF FFFF MEM Non prefetchable BA
27. Diagnostic tests Ethernet Test Name Description Availability ETHERO Ethernet 0 1 2 3 internal loopback test Always ETHER1 Groups POST AUTO except ETHER2 3 ETHER2 with an MPC8543 E processor ETHER3 ETHERO_X Ethernet 0 1 2 3 external loopback test Always ETHER1_X Groups NONAUTO ENDLESS except ETHER2 3 ETHER2 X with an MPC8543 E E processor ETHERS X 3 5 1 1 Ethernet Internal Loopback Test The test configures the network interface for loopback mode on PHY verifies that the interface s ROM has a good checksum verifies that the MAC address is valid not OXFFFFFF sends 10 frames with 0x400 bytes payload each verifies that frames are correctly received on the same interface If the network interface to test is the currently activated interface for the MENMON network stack the interface is detached from the network stack during test and reactivated after test Checks Connection between CPU and LAN controller Connection between LAN controller and PHY Does not check Connection between PHY and physical connector nterrupt line e All LAN speeds MEN Mikro Elektronik GmbH 48 20A017 00 E4 2010 11 22 MENMON 3 5 1 2 Ethernet External Loopback Test This test is the same as the Ethernet Internal Loopback Test but requires an external loopback connector Before sending frames the link state is monitored If it is not ok within 2 seconds the test fails
28. GHz 1 33 GHz or 512 KB No 4 1 5GHz MPC8548E 1 GHz 1 2 GHz 1 33 GHz or 512 KB Yes 4 1 5 GHz MPC8543 800 MHz or 1 GHz 256 KB No 2 MPC8543E 800 MHz or 1 GHz 256 KB Yes 2 MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 2 5 2 Thermal Considerations The CPU generates around 8 W of power dissipation when operated at 1 33 GHz To meet thermal requirements a suitable heat sink must be attached to the CPU and sufficient airflow must be provided MEN provides a suitable heat sink to meet thermal requirements Please note that if you use any other heat sink than that supplied by MEN or no heat sink at all warranty on functionality and reliability of the A17 may cease If you have any questions or problems regarding thermal behavior please contact MEN Functional Description 2 6 Bus Structure 2 6 1 Host to PCI Bridge The integrated host to PCI bridge is used as host bridge and memory controller for the PowerPC processor All transactions of the PowerPC to the PCI bus are controlled by the host bridge The FRAM and boot Flash are connected to the local memory bus of the integrated host to PCI bridge The PCI interface is PCI bus Rev 2 2 compliant and supports all bus commands and transactions Master and target operations are possible Only big endian operation is supported 2 6 2 Local PCI Bus The local PCI bus is controlled by the integrated host to PCI bridge It runs at 66 33 MHz The I O voltage
29. IRQ Input PCI Interrupt Line MEMO IRQS INTA 0x8 IRQS INTB 0x9 IRQ10 INTC OxA IRQ11 INTD 0xB Table 42 Interrupt numbering assigned by MENMON PCIe Assigned Number MPC854X IRQ Input PCI Interrupt Line MENMON IRQO INTA 0xF0 IRQ1 INTB 0xF1 IRQ2 INTC OxF2 IRQ3 INTD OxF3 Note Since each operating system may have a different numbering scheme it is possible that this mapping does not match each OS In this case the OS has to scan through the PCI device hierarchy reads the PCI interrupt line field and rewrites it according to the OS native mapping MEN Mikro Elektronik GmbH 67 20A017 00 E4 2010 11 22 Organization of the Board 4 3 SMB Devices Table 43 SMB devices Address Function 0x5E LM81 temperature and voltage monitor 0x 0 Reserved 0x DO Real time clock 0xA8 Configuration EEPROM 4 4 PCI Devices on Bus 0 Table 44 PCI devices on bus 0 Device Number Vendor ID Device ID Function 0x00 0x1057 0x0012 PCI host bridge in MPC854X 0x0A PMC 1 Ox1C 0x1A88 0x4D45 FPGA 0x1D 0x10E3 0x0148 VMEbus bridge 0x1E PMC 0 MEN Mikro Elektronik n PY DTP T 68 20A017 00 E4 2010 11 22 Maintenance 5 Maintenance A 5 1 Lithium Battery This board contains a snaphat lithium battery There is a danger of explosion if the battery is incorrectly replaced Replace only with the same or equivalent type e Manufacturer ST
30. Note A loopback connector makes a connection between the following pins of the 8 pin Ethernet connector 1 3 2 6 4 7 5 8 Checks Connection between CPU and LAN controller Connection between LAN controller and PHY Connection between PHY and physical connector Does not check Interrupt line All LAN speeds 3 5 2 SDRAM and FRAM Table 18 MENMON Diagnostic tests SDRAM and FRAM Test Name Description Availability SDRAM Quick SDRAM connection test Always Groups POST AUTO SDRAM_X Full SDRAM test Always Groups NONAUTO ENDLESS FRAM Quick FRAM test A17 is known to have FRAM Groups POST AUTO FRAM_X Full FRAM test Groups NONAUTO ENDLESS 3 5 2 1 Quick RAM Test This quick test checks most of the connections to the RAM chips but does not test all RAM cells It executes very quickly within milliseconds This test is non destructive saves restores original RAM content Checks All address lines All data lines Byte enable signals ndirectly checks clock and other control signals Does not check SDRAM cells Burst mode MEN Mikro Elektronik GmbH 49 20A017 00 E4 2010 11 22 MENMON 3 5 2 2 Extended RAM Test This full featured memory test allows to test all RAM cells Depending on the size of the SDRAM this test can take up to one minute It tests 8 16 or 32 bit access each with random pattern and single and burst access On each pass this tes
31. PMCO_J4 6 4 PMCO_J4 7 A24 PMCO J4 8 GND 5 s PMCO J4 9 A25 PMCO J4 10 6 PMCO J4 11 A26 PMCO J4 12 GND 7 PMCO J4 13 A27 PMCO J4 14 8 s PMCO J4 15 A28 PMCO J4 16 GND 9 PMCO J4 17 A29 PMCO J4 18 s 10 PMCO J4 19 A30 PMCO_J4 20 GND 11 PMCO J4 21 A31 PMCO_J4 22 12 a PMCO_J4 23 GND PMCO_J4 24 GND 13 PMCO J4 25 5V PMC0_J4 26 14 PMCO J4 27 D16 PMCO J4 28 GND 15 PMCO_J4 29 D17 PMCO_J4 30 16 PMCO J4 31 D18 PMCO J4 32 GND 17 PMCO_J4 33 D19 PMCO_J4 34 s 18 PMCO_J4 35 D20 PMCO_J4 36 GND 19 PMCO J4 37 D21 PMCO J4 38 20 PMCO J4 39 D22 PMCO J4 40 GND 21 PMCO_J4 41 D23 PMCO_J4 42 22 PMCO J4 43 GND PMCO J4 44 GND 23 PMCO_J4 45 D24 PMCO_J4 46 s 24 a PMCO_J4 47 D25 PMCO_J4 48 GND 25 PMCO J4 49 D26 PMCO J4 50 26 PMCO J4 51 D27 PMCO J4 52 GND 27 PMCO_J4 53 D28 PMCO_J4 54 28 PMCO J4 55 D29 PMCO J4 56 GND 29 PMCO_J4 57 D30 PMCO_J4 58 s 30 PMCO_J4 59 D31 PMCO_J4 60 GND 31 GND PMCO_J4 61 GND PMCO_J4 62 32 PMCO_J4 63 5V PMCO_J4 64 GND MEN Mikro Elektronik GmbH 39 20A017 00 E4 2010 11 22 Functional Description Table 13 Signal mnemonics of VMEbus rear I O connector P2 PMC signals Signal Direction Function Power 5V 5V power supply GND Digital ground VME64 A 31 24 in out VME64 address lines D 31 16 in out VME64 data lines RETRY out VME64 retry for postponed data transfer PMC 0 PMCO J4 xx in out Signal xx from PMC 0 rear I O connector
32. PROM on the A17 If required you can configure MENMON to store some strings in boot Flash rather than in EEPROM 3 6 5 2 Start up with Faulty EEPROM If a faulty EEPROM is detected i e the checksum of the EEPROM section is wrong the system parameters will use defaults The behavior is the same if the EEPROM is blank The default baud rate is 9600 3 6 5 3 A17 System Parameters Note Parameters marked by Yes in section Parameter String are part of the MENMON parameter string Table 29 MENMON A17 system parameters Autodetected parameters Parameter Se ic Paramete User alias Description Standard Default r String Access ccbclkhz CCB clock frequency decimal Hz Yes Read only clun MENMON controller unit number that Yes Read only MENMON used as the boot device hexadecimal cons Selected console Set to name of first Yes Read only selected console e g COM1 cpu CPU type as ASCII string e g Yes Read only MPC8548E cpuclkhz CPU core clock frequency decimal Hz Yes Read only dlun MENMON device unit number that Yes Read only MENMON used as the boot device hexadecimal flashO Flash size decimal kilobytes Yes Read only fpga Info which FPGA image was loaded Yes Read only 0 FPGAO 1 FPGA1 2 FPGA2 3 FPGAS 1 no FPGA loaded framo FRAM size decimal kilobytes Yes Read only immr Physical address of CCSR register Yes Read only block memo RAM size decimal kilobytes Yes Rea
33. Rs PCle Ox FBOO 0000 FBFE FFFF 0x 0000 0000 00FE FFFF MEM PCI ISA memory Ox FBFF 0000 FBFF OFFF 0x 0000 0FFF I O PCI I O space of onboard FPGA Ox FBFF 1000 FBFF FFFF 0x 1000 FFFF I O PCI I O space of all other PCI devices Ox FCOO 0000 FCFE OFFF 0x 0000 0000 00FE FFFF ISA PCle ISA memory Ox FCFF 0000 FCFF FFFF 0x 0000 FFFF I O PCIe I O memory MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 Table 37 Address mapping for PCI slave Organization of the Board PCI Address Range Mapped to CPU Space Description 0x 0000 0000 End of RAM 0x 0000 0000 End of RAM Default whole SDRAM mapped to PCI Table 38 Address mapping for VMEbus master CPU PCI Address Range Mapped to VME Space Size Ox A5FE 0000 A5FE FFFF Ox 0000 FFFF A16 D16 64 KB Ox A5FF 0000 A5FF FFFF Ox 0000 FFFF A16 D32 64 KB Ox A600 0000 A6FF FFFF 0x 00 0000 FF FFFF A24 D16 16 MB 0x A700 0000 A7FF FFFF 0x 00 0000 FF FFFF A24 D32 16 MB 0x A800 0000 AFFF FFFF Ox 0000 0000 07FF FFFF A32 D32 128 MB 0x B000 0000 CFFF FFFF 0x 0000 0000 0000 0000 512 MB Ox 0000 0000 1FFF FFFF A64 D64 The A64 D64 VME window is set up for 2eSST with a 320 MB s transfer rate and prefetching enabled All other VME windows are set up for non privileged SCT with prefetching disabled Table 39 Address mapping for VMEbus slave VME Address R
34. Started 1 Getting Started This chapter gives an overview of the board and some hints for first installation in a system 1 1 Map of the Board Figure 1 Map of the board front panel and top view Heat Sink MPC8548 43 VMEbus P1 TSI148 VMEbus Bridge oi Qi 4 o ra oO B i 2i j PMCO XMC VMEbus P2 J4 rear I O MEN Mikro Elektronik GmbH 16 20A017 00 E4 2010 11 22 d Getting Started 1 2 Configuring the Hardware You should check your hardware requirements before installing the board in a system since most modifications are difficult or even impossible to do when the board is mounted in a rack The following check list gives an overview on what you might want to configure M XMC module NS Refer to Chapter 2 10 2 Installing an XMC Mezzanine Module on page 30 for a detailed installation description M PMC modules SS Refer to Chapter 2 11 1 Installing a PMC Mezzanine Module on page 32 for a detailed installation description 1 3 Integrating the Board into a System You can use the following check list when installing the board in a system for the first time and with minimum configuration V Power down the system Mi Remove all boards from the VMEbus system Mi Insert the A17 into slot 1 of the system making sure that the VMEbus connec tors are properly aligned Vl Connect a terminal to the RS232 interface COMI RJ45 connector MEN offers an adap
35. THERO Ethernet 0 LAN 1 0x03 ETHER1 0x04 ETHER2 Ethernet 1 LAN 2 Ethernet 2 LAN 3 0x05 ETHERS Ethernet 3 LAN 4 0x06 USB USB controller if present via PMC 0x08 COM1 MPC854X DUART channel 0 COM1 0x09 COM2 MPC854X DUART channel 1 COM2 0x0A TOUCH Touch console if 16Z031_SPI found in onboard FPGA and can communicate with touch controller 0x0B COM10 UART 0 of onboard FPGA UART optional 0x0C COM11 UART 1 of onboard FPGA UART optional 0x0D COM12 UART 2 of onboard FPGA UART optional OxOE COM13 UART 3 of onboard FPGA UART optional 0x20 All other devices dynamically detected on PCI or FPGA devices 0x40 Telnet console 0x41 HTTP monitor console Table 28 MENMON Device Logical Units DLUNs CLUN DLUN MENMON BIOS Name Description 0x00 0x00 NAND Int CF Reserved for internal NAND Flash 0x01 0x00 SSD Internal SSD Flash disk IDE1 mas ter 0x06 0x00 USB USB controller if present via PMC MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 MENMON 3 6 5 System Parameters System parameters are parameters stored in EEPROM Some parameters are automatically detected by MENMON such as CPU type and frequency The parameters can be modified through the EE xxx command via the command line 3 6 5 1 Physical Storage of Parameters Most parameters are stored in the 1024 byte serial EE
36. Type M4T32 BR12SH6 e Capacity 120 mAh Data retention time is mainly a function of temperature and power duty cycle At a temperature of 60 C the battery life can be expected to be greater than 20 years without system power For details please refer to application note AN1012 which is available at www st com To replace the battery simply unplug it from its socket and install a new battery The socket is protected against reverse connection so that the battery will fit into the socket only if properly aligned Caution To avoid draining battery do not place snap hat pins in a conductive foam Dispose of used batteries according to the manufacturer s instructions Figure 8 Position of lithium battery on A17 MEN Mikro Elektronik GmbH 69 20A017 00 E4 2010 11 22 Appendix 6 Appendix 6 1 Literature and Web Resources e A17 data sheet with up to date information and documentation www men de products 01A017 html 6 1 1 PowerPC MPC8548 MPC8548E PowerQUICC III Integrated Processor Family Reference Manual MPC8548ERM 2007 Freescale Semiconductor Inc www freescale com 6 1 2 Ethernet ANSI IEEE 802 3 1996 Information Technology Telecommunications and Information Exchange between Systems Local and Metropolitan Area Net works Specific Requirements Part 3 Carrier Sense Multiple Access with Col lision Detection CSMA CD Access Method and Physical Layer Specifications 1996 IEEE www ieee org
37. You can couple several lanes to increase the data rate e g x2 with 2 lanes up to a x32 link using 32 lanes MEN Mikro Elektronik GmbH 21 20A017 00 E4 2010 11 22 Functional Description In addition PCIe supports hot plug for instance to exchange defect expansion boards during operation In terms of software most operating systems can handle PCI Express boards just as well as the old PCI 2 7 Memory and Mass Storage 2 7 1 DRAM System Memory The board provides up to 2 GB onboard soldered DDR2 double data rate SDRAM on nine memory components incl ECC The memory bus is 72 bits wide and operates at up to 300 MHz physical depending on the processor type Depending on the board version the SDRAM may have ECC error correcting code ECC memory provides greater data accuracy and system uptime by protecting against soft errors in computer memory 2 7 2 Boot Flash The board has 16 MB of onboard Flash It is controlled by the CPU Flash memory contains the boot software for the MENMON operating system bootstrapper and application software The MENMON sectors are software protected against illegal write transactions through a password in the serial download function of MENMON cf Chapter 3 4 1 Update via the Serial Console using SERDL on page 46 2 7 3 Solid State Flash Disk The board includes a 2 GB soldered NAND Flash disk controlled by the FPGA It is accessed via an UltraDMA IDE controller located in the FPGA
38. and description of reset behavior corrected E3 System parameter vme_irq added note on J4 on PMC 2008 11 27 1 added minor corrections E4 Changes for removed FPGA controlled DRAM as of 2010 11 22 hardware rev 03 xx minor errors corrected Conventions This sign marks important notes or warnings concerning proper functionality of the product described in this document You should read them in any case italics Folder file and function names are printed in italics bold Bold type is used for emphasis monospace A monospaced font type is used for hexadecimal numbers listings C function descriptions or wherever appropriate Hexadecimal numbers are preceded by Ox hyperlink Hyperlinks are printed in blue color The globe will show you where hyperlinks lead directly to the Internet so you can look for the latest information online IRQ Signal names followed by or preceded by a slash indicate that this signal is IRQ either active low or that it becomes active at a falling edge in out Signal directions in signal mnemonics tables generally refer to the corresponding board or component in meaning to the board or component out meaning coming from it Vertical lines on the outer margin signal technical changes to the previous edition of the document MEN Mikro Elektronik GmbH 9 20A017 00 E4 2010 11 22 About this Document Legal Information MEN Mikro Elektronik reserves the right to make changes without further noti
39. ange Mapped to CPU PCI Space Size Ox yy yyyy Zz Zzzz A24 Ox yyyy yyyy Zzzz ZZZZ Depends on 0x yyyy yyyy zz zzzz A82 Ox yyyy yYyyy ZZZZ zzzz settings default 0 MB Ox yyyy yyyy yyyy yyyy Ox yyyy Yyyy ZZZZ zzzz 0x zzzz ZZZZ ZZZZ ZZZZ A64 The address mapping for VMEbus slave access is completely configurable through MENMON Therefore the above table only shows the basic layout of the addresses Please see Chapter 3 6 5 5 VMEbus Slave Address Mappings Parameter vme_in_aXX on page 62 for a description of related MENMON parameters MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 Organization of the Board 4 2 Interrupt Handling Interrupt handling between the FPGA and the CPU is done via the 12 external interrupt lines of the CPU IRQ 0 11 While the IRQ lines 8 to 11 are used as the four PCI interrupt lines see Table 41 Interrupt numbering assigned by MENMON PCI on page 67 the FPGA unit interrupts are routed to dedicated interrupt lines The mapping is as follows Table 40 Dedicated interrupt line assignment MPC854X External Interrupt Line FPGA Function IRQ O Ethernet PHY 1 IRQ 1 SSD Flash disk IRQ 2 Reserved for NAND Flash IRQ 3 Board control IRQ 4 GPIOs 16Z034 GPIO instance 1 IRQ 5 GPIOs 16Z034_GPIO instance 2 IRQ 6 GPIOs 16Z034_GPIO instance 3 4 IRQ 7 XMC WAKE Table 41 Interrupt numbering assigned by MENMON PCI MPC854X
40. ations Table 16 MENMON Program update files and locations File Name A Password Extension Typical File Name for SERDL Location SMM 14A017 00 01 02 5MM MENMON Secondary MENMON FPO A017 00ICO05B1 FPO FPGAO FPGAO code 33 MHz PCI clock FP1 A017 00ICO05B1 FP1 FPGA1 FPGA1 code backup FP2 A017 00ICO05A 1 FP2 FPGA2 FPGA2 code 66 MHz PCI clock FP3 A017 00IC005A1 FP3 FPGA3 FPGAS code backup Bxx DSKIMG B00 DISK Starting at sector xx in second disk SSD Flash disk Cxx DSKIMG C00 DISK Starting at sector xx in first disk reserved for NAND Flash Dxx MYFILE DOO Starting at 0x200000 4 xx in SDRAM Exx MYFILE E00 Starting at byte xx in EEPROM Fxxx MYFILE F000 Starting at sector xxx in boot Flash Flash has 128 sectors with 0x20000 bytes each 3 4 2 Update from Network using NDL You can use the network download command NDL to download the update files from a TFTP server in network The file name extensions locations and passwords are the same as for the SERDL command MEN Mikro Elektronik GmbH 46 20A017 00 E4 2010 11 22 MENMON 3 4 3 Updating MENMON Code Updates of MENMON are available for download from MEN s website MENMON s integrated Flash update functions allow you to do updates yourself However you need to take care and follow the instructions given here Otherwise you may make your board inoperable In any case read the followi
41. ce to any products herein MEN makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does MEN assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts MEN does not convey any license under its patent rights nor the rights of others Unless agreed otherwise MEN products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the MEN product could create a situation where personal injury or death may occur Should Buyer purchase or use MEN products for any such unintended or unauthorized application Buyer shall indemnify and hold MEN and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that MEN was negligent regarding the design or
42. d lower software layers Ethernet is one of the most widely implemented LAN standards Ethernet networks provide high speed data exchange in areas that require economical connection to a local communication medium carrying bursty traffic at high peak data rates A classic Ethernet system consists of a backbone cable and connecting hardware e g transceivers which links the controllers of the individual stations via transceiver transmitter receiver cables to this backbone cable and thus permits communication between the stations 2 8 4 10Base T 10Base T is one of several adaptations of the Ethernet IEEE 802 3 standard for Local Area Networks LANs The 10Base T standard also called Twisted Pair Ethernet uses a twisted pair cable with maximum lengths of 100 meters The cable is thinner and more flexible than the coaxial cable used for the 10Base 2 or 10Base 5 standards Since it is also cheaper it is the preferable solution for cost sensitive applications Cables in the 10Base T system connect with RJ45 connectors A star topology is common with 12 or more computers connected directly to a hub or concentrator The 10Base T system operates at 10 Mbits s and uses baseband transmission methods MEN Mikro Elektronik GmbH 25 20A017 00 E4 2010 11 22 Functional Description 2 8 5 100Base T The 100Base T networking standard supports data transfer rates up to 100 Mbits s 100Base T is actually based on the older Ethernet standa
43. d only mem1 Size of SRAM decimal kilobytes Yes Read only MEN Mikro Elektronik GmbH 57 20A017 00 E4 2010 11 22 MENMON Parameter ae Paramete User alias Description Standard Default r String Access memclkhz Memory clock frequency decimal Hz Yes Read only mm Info whether primary or secondary Yes Read only MENMON has been used for booting either smm or pmm mmst Status of diagnostic tests as a string Yes Read only nmac0 1 2 32 MAC address of Ethernet interface x Yes Read only 0 n Format e g 00c03a650001 Set automatically according to serial number of the board pciclkhz PCI bus clock frequency system input Yes Read only clock decimal Hz rststat Reset status code as a string see Yes Read only Chapter 3 6 5 4 Reset Cause Param eter rststat on page 62 usbdp USB boot device path in format Yes Read only bus 1st port no last port no e g 00202201 for USB bus 0 port no 1 2 port no 2 1 If implemented 2 nmac2 3 only present if MPC8548 is used Table 30 MENMON A17 system parameters Production data Parameter wr Paramete User alias Description Standard Default r String Access brd Board name Yes Read only brdmod Board model mm Yes Read only brdrev Board revision xx yy zz Yes Read only prodat Board production date MM DD Y Y YY Yes Read only repdat Board last repair
44. date MM DD Y Y YY Yes Read only sernbr Board serial number Yes Read only MEN Mikro Elektronik GmbH 00000000000 58 20A017 00 E4 2010 11 22 Table 31 MENMON A17 system parameters MENMON persistent parameters MENMON Parameter Paramete User alias Description Standard Default r String Access bsadr bs Bootstrapper address Used when BO 0 No Read write command was called without argu ments hexadecimal 32 bits cbr baud Baudrate of all UART consoles dec 9600 Yes Read write con0 con3 CLUN of console 0 3 hex see Chap OxFF auto No Read write ter 3 6 1 Consoles on page 53 eccsth ECC single bit error threshold 32 No Read write ecl CLUN of attached network interface OxFF No Read write hex gcon CLUN of graphics screen hex see OxFF auto No Read write Chapter 3 6 1 Consoles on page 53 hdp HTTP server TCP port decimal 1 No Read write kerpar Linux Kernel Parameters 399 chars Empty string No Read write max Part of VxWorks bootline if usefl par 0 400 chars max if useflpar 1 Idlogodis Disable load of boot logo bool 0 No Read write Ixdcache Enable Data Cache before giving con 1 No Read write trol to Linux kernel 0 disable DCache 1 enable DCache mmstartup Start up string Empty string No Read write Startup 256 chars max if useflpar 0 512 chars max if useflpar 1 nobanner Disable ASCII banner on start up 0 No Read write
45. e 5 Signal mnemonics of UART front interfaces Signal Direction Function CTS in Clear to send GND Ground RTS out Request to send RXD in Receive data TXD out Transmit data MEN Mikro Elektronik GmbH HHHH 27 20A017 00 E4 2010 11 22 Functional Description 2 10 XMC Slot The A17 board provides one XMC slot for extension such as high speed graphics SATA Ethernet etc XMC modules have the same form factor as PMC modules however they do not use a PCI bus but a high speed PCI Express connection and therefore have a different carrier board connector The A17 supports one x1 one x2 or one x4 PCI Express link on one J15 connector as defined by the XMC Standard See also Chapter 2 6 4 PCI Express on page 21 The connector layout is fully compatible to the standard for XMC 3 connectors See also Chapter 6 1 Literature and Web Resources on page 70 2 10 4 Connection Connector types 114 pin XMC receptacle connector Mating connector 114 pin XMC plug connector e g SAMTEC ASP105885 01 Table 6 Pin assignment of 114 pin XMC connector A B C D E F 1 PEROpO PEROnO 3 3V PEROp1 PEROn1 5V 2 GND GND GND GND MRSTI 3 PEROp2 PEROn2 3 3V PEROp3 PEROn3 5V 4 GND GND GND GND MRSTO ABCDEF 5 PEROp4 PEROn4 3 3V PEROp5 PEROn5 5V 999999 3 999999 6 GND GND GND GND 12V 99 9 9 9 9 7 PEROp6 PEROn6 3 3V PEROp7 PEROn7 5V 000000 8 GND GND GND GND 12V oooooo 9 5V ESSE 10 GND GND GND GND
46. eap Ox 01FF 0000 1FF FFFF 64 KB Not touched for OS post mor tem buffer i e VxWorks WindView or MDIS debugs requires ECC to be turned off Ox 0200 0000 End of RAM Free or download area 3 6 3 2 Boot Flash Memory Map Table 26 MENMON Boot Flash memory map Flash Offset CPU Address Size Description 0x 00 0000 0x FFOO 0000 10 MB Available to user Ox A0 0000 0x FFAO 0000 1 MB Fallback FPGA code FPGA3 66 MHz Ox BO 0000 Ox FFBO 0000 1 MB Initial FPGA code FPGA2 66 MHz Ox CO 0000 Ox FFCO 0000 1 MB Fallback FPGA code FPGA1 33 MHz Ox DO 0000 Ox FFDO 0000 896 KB Initial FPGA code FPGAO 33 MHz Ox DE 0000 Ox FFDE 0000 128 KB System parameter section in boot Flash if useflpar system parameter is set to 1 Ox E0 0000 Ox FFEO 0000 1 MB Secondary MENMON Ox FO 0000 Ox FFFO 0000 1 MB Primary MENMON MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 MENMON 3 6 4 MENMON BIOS Logical Units The following table shows fixed assigned CLUNs All other CLUNs are used dynamically Table 27 MENMON Controller Logical Units CLUNs MENMON ae CLUN BIOS Name Description 0x00 IDEO Reserved for NAND Flash IDE primary IDE 0x01 IDE1 Flash disk SSD 0x02 E
47. ector layout is fully compatible to the IEEE1386 specification For connector pinouts please refer to the specification see Chapter 6 1 Literature and Web Resources on page 70 PMC slot 0 supports rear I O connection PMC slot 1 does not support rear I O See also Figure 1 Map of the board front panel and top view on page 16 As an option PMC slot 1 can be used to process additional I O from the A17 s onboard FPGA Please see Chapter 2 11 2 FPGA I O through PMC1 J4 on page 33 for details Please note that you must not install a PMC module with a J4 rear I O connector in PMC slot 1 since this connector is linked to the onboard FPGA Signals with a voltage level of more than 3 3 V on J4 will lead to damage of the FPGA Connector types 64 pin 1 mm pitch board to board receptacle according to IEEE 1386 Mating connector 64 pin 1 mm pitch board to board plug according to IEEE 1386 MEN Mikro Elektronik GmbH 31 20A017 00 E4 2010 11 22 Functional Description 2 11 1 Installing a PMC Mezzanine Module Perform the following steps to install a PMC module MI Make sure that the voltage keying of your PMC module matches the A17 MI Power down your system and remove the A17 from the system MI Remove the filler panel from the board s front PMC slot if installed M The PMC module is plugged on the A17 with the component sides of the PCBs facing each other V Put the PMC module s front connector through the A17 s front s
48. ery large number of simultaneous transactions to take place TSI148 is also a full featured master slave and system controller which allows it to be used in any VME application Main features e Supports VME32 VME64 2eVME and 2eSST VITA 1 5 Slot 1 function with auto detection Master D08 D16 D32 D64 A16 A24 A32 A64 BLT MBLT RMW Slave D08 D16 D32 D64 A16 A24 A32 A64 BLT MBLT DMA Mailbox functionality Bus timer Location Monitor Interrupter D08 O I 7 1 ROAK Interrupt handler D08 O IH 7 1 Single level 3 fair requester Single level 3 arbiter Low power consumption Since the TSI148 controller is a very complex component we have not included any details on register access etc here Please refer to the bridge s manufacturer data sheet which is available from the manufacturer s website T www tundra com genld TSI148 amp cid 18698888 For more literature on the VMEbus see Chapter 6 1 Literature and Web Resources on page 70 MEN Mikro Elektronik GmbH 36 20A017 00 E4 2010 11 22 Functional Description 2 14 2 Connection Connector types 160 pin 5 row plug performance level according to DIN41612 part 5 Mating connector 160 pin 5 row receptacle performance level according to DIN41612 part 5 2 14 2 1 Bus Connection VMEbus P1 The pin assignment of P1 conforms to the VME64 specification ANSI VITA 1 1994 R2002 and VME64 Extensions Standard ANSI VITA 1 1 1997 R2003 MEN Mikro E
49. es MPC8548 or MPC8548E 1 GHz 1 2 GHz 1 33 GHz or 1 5 GHz e MPC8543 or MPC8543E 800 MHz or 1 GHz Memory System RAM 512 MB 1 GB or 2 GB With or without ECC Flash Disk 0 GB up to 4 GB and more if components are available FRAM OKBor 128 KB I O Ethernet Two additional Gigabit Ethernet channels on VMEbus PO rear connector for ANSI VITA 31 1 2003 support only with MPC8548 Only two channels at front instead of four with MPC8543 PCI Express links one x8 link Reduces operation temperature range because of higher DDR SDRAM clock FPGA The onboard FPGA offers the possibility to add customized I O functionality FPGA Altera Cyclone II EP2C35 33 216 logic elements 483 840 total RAM bits Connection Total available pin count 31 pins Functions available via PMC slot 1 connector Pn4 Youcan find more information on our web page User I O in FPGA VMEbus Single 5V supply for operation in VME32 systems Please note that some of these options may only be available for large volumes Please ask our sales staff for more information lt For available standard configurations see online data sheet MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 Product Safety Product Safety AN AN Lithium Battery This board contains a lithium battery There is a danger of explosion if the battery is incorrectly replaced See Chapter 5 Maintenance on page 69
50. es 5V 3 3V 2 5V 1 8V 1 2V and 1 1V and holds the CPU in reset condition until all supply voltages are within their nominal values In addition the board contains a PLD watchdog that must be triggered After power up the CPU loads the FPGA After configuration the FPGA serves the PLD watchdog without further action by the CPU The watchdog timeout is automatically set to 1 12 s after the first trigger pulse by the FPGA An additional watchdog is implemented in the FPGA itself It can be enabled through MENMON and can then be triggered by a software application This function is normally supported by the board support package see BSP documentation 2 3 Clock Supply The CPU is supplied with one copy of the onboard PCI clocks This is internally multiplied to generate the core clock and the memory clock By default the board runs at 66 MHz PCI 266 MHz SDRAM memory and 1 33 GHz core 2 4 Real Time Clock A battery buffered real time clock is integrated on the A17 CPU board It is accessed via PC bus at address 0xDO The voltage of the snap hat standby battery is monitored by the RTC A warning flag is set if the battery voltage falls below 2 5V The CPU can read this flag from bit D4 at word address OxOF of the RTC After setting this flag the RTC continues operation for at least 1 month Interrupt generation of the RTC is not supported For details on maintenance of the snap hat battery see Chapter 5 Maintenance on page 69
51. eter vme_in_aXX on page 62 000000 20000000 0 No Read write vme_in_a32 VME A32 inbound VME gt gt gt A17 map ping see Chapter 3 6 5 5 VMEbus Slave Address Mappings Parameter vme_in_aXX on page 62 00000000 20000000 0 No Read write vme_in_a64 VME A64 inbound VME gt gt gt A17 map ping see Chapter 3 6 5 5 VMEbus Slave Address Mappings Parameter vme_in_aXX on page 62 00000000000000 00 20000000 0 No Read write vme irq VMEbus IRQ levels enable mask Ox01 bit 1 2 enable level 1 0x02 bit 2 2 enable level 2 0x40 bit 7 2 enable level 7 e g ee vme irq OCto enable IRQ level 3 amp 4 0x00 No Read write vmode Vesa Video Mode for graphics console hex 0x0101 No Read write wat Time after which watchdog timer shall reset the system after MENMON has passed control to operating system decimal in 1 10 s If 0 MENMON disables the watchdog timer before starting the operating sys tem 0 disabled No Read write MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 Table 32 MENMON A17 system parameters VxWorks bootline parameters MENMON Parameter T Paramete User alias Description Standard Default r String Access bf bootfile Boot file name 127 chars max Empty string No Read write bootdev VxWorks boot device name Empty string No Read
52. evision and the serial number on two labels attached to the board Article number Gives the board s family and model This is also MEN s order ing number To be complete it must have 9 characters Revision number Gives the hardware revision of the board Serial number Unique identification assigned during production If you need support you should communicate these numbers to MEN Figure 9 Labels giving the board s article number revision and serial number Complete article number 01A017 00 AE i W 00 00 00 641517 Revision number Serial number MEN Mikro Elektronik GmbH 71 20A017 00 E4 2010 11 22
53. he command line interface This is useful if a secondary MENMON has been programmed that does not work or if you have misconfigured a system parameter Note The test connector is not assembled in standard versions of A17 However it is possible to connect the two pins You should do so only if you are abso lutely sure about what you are doing In any case power off the system before you connect the abort pins The test connector pins are accessible at the bottom side of the PCB Figure 7 MENMON Position of abort pins on test connector bottom side Ed Test connector pins VMEbus P1 MEN Mikro Elektronik GmbH 54 20A017 00 E4 2010 11 22 3 6 3 3 6 3 1 MENMON Memory Map MENMON MENMON Memory Address Mapping Table 25 MENMON Address map full featured mode Address Space Size Description 0x 0000 0000 00 00 1400 5 KB Exception vectors Ox 0000 3000 00 00 3FFF 4 KB MENMON parameter string 0x 0000 4200 00 00 42FF 256 bytes VxWorks bootline Ox 0000 4300 00 FF FFFF Nearly Free 16 MB Ox 1D0 0000 1DF FFFF 2MB Heap2 Ox 1E0 0000 1EF FFFF 1 MB Text Reloc Ox 1FO 0000 1F1 FFFF 128 KB Stack Ox CeO ojo c 1F2 0000 Ce ojo c 1F4 FFFF 128 KB Stack for user programs and operating system boot 0x 01F5 0000 o 1FE FFFF 640 KB H
54. ioned in this publication are identified by the trademarks service marks or product names as designated by the companies who market those products The trademarks and registered trademarks are held by the companies producing them Inquiries concerning such trademarks should be made directly to those companies All other brand or product names are trademarks or registered trademarks of their respective holders Information in this document has been carefully checked and is believed to be accurate as of the date of publication however no responsibility is assumed for inaccuracies MEN Mikro Elektronik accepts no liability for consequential or incidental damages arising from the use of its products and reserves the right to make changes on the products herein without notice to improve reliability function or design MEN Mikro Elektronik does not assume any liability arising out of the application or use of the products described in this document Copyright 2010 MEN Mikro Elektronik GmbH All rights reserved D Please recycle Germany France USA MEN Mikro Elektronik GmbH MEN Mikro Elektronik SA MEN Micro Inc Neuwieder Stra e 5 7 18 rue Ren Cassin 24 North Main Street 90411 Nuremberg ZA de la Ch telaine Ambler PA 19002 Phone 49 911 99 33 5 0 74240 Gaillard Phone 215 542 9575 Fax 49 911 99 33 5 901 E mail info men de www men de Phone 33 0 450 955 312 Fax 33 0 450 955 211 E mail info men france fr www men france fr Fax
55. l gt Ethernet MII register command MO lt from gt lt to gt lt cnt gt Move copy memory MS lt from gt lt to gt lt val gt Search pattern in memory MT lt opts gt lt start gt lt end gt lt runs gt Memory test NBOOT lt opts gt Boot from Network NDL lt opts gt Update Flash from network NETSTAT Show current state of networking parameters PCI PCI probe PCIC lt dev gt lt addr gt lt bus gt lt func gt PCI config register change PCID lt dev gt lt bus gt lt func gt PCI config register dump PCIR List PCI resources PCI VPD lt devNo gt lt busNo gt lt capld gt PCI Vital Product Data dump PCI VPD lt devNo gt lt busNo gt lt capld gt PCI Vital Product Data dump PFLASH lt D gt lt O gt lt S gt lt A gt Program Flash PGM XXX lt args gt Media copy tool PING lt host gt lt opts gt Network connectivity test RELOC Relocate MM to RAM RST Cause an instant system reset RTC xxx lt arg gt Real time clock commands S lt addr gt Single step user program SERDL lt passwd gt Update Flash using YModem protocol SETUP Open interactive Setup menu USB lt bus gt Init USB controller and devices on a USB bus USBT Shows the USB device tree for the current bus USBDP lt bus p1 p5 gt d lt x gt Display modify US
56. lektronik GmbH 37 20A017 00 E4 2010 11 22 Table 11 Pin assignment of VME64 bus connector P1 Functional Description D C B A Z 1 D8 BBSY DO 2 GND D9 BCLR D1 GND 3 D10 ACFAIL D2 4 D11 BGOIN D3 GND 5 D12 BGOOUT D4 6 D13 BG1IN D5 GND 7 D14 BG10UT D6 8 D15 BG2IN D7 GND 9 GAP GND BG2OUT GND 10 GAO SYSFAIL BG3IN SYSCLK GND 11 GA1 BERR BG30UT GND 12 3 3V SYSRESET BRO DS1 GND 13 GA2 LWORD BR1 DSO 14 3 3V AM5 BR2 WRITE GND 15 GA3 A23 BR3 GND 16 3 3V A22 AMO DTACK GND 17 GA4 A21 AM1 GND 18 3 3V A20 AM2 AS GND 19 A19 AM3 GND 20 3 3V A18 GND IACK GND 21 A17 IACKIN 22 3 3V A16 IACKOUT GND 23 A15 GND AM4 24 3 3V A14 IRQ7 A7 GND 25 A13 IRQ6 A6 26 3 3V A12 IRQ5 A5 GND 27 A11 IRQ4 A4 28 3 3V A10 IRQ3 A3 GND 29 AQ IRQ2 A2 30 3 3V A8 IRQ1 A1 GND 31 GND 12V 12V 32 5V 5V 5V GND MEN Mikro Elektronik GmbH 38 20A017 00 E4 2010 11 22 Functional Description 2 14 2 2 Rear I O using VMEbus P2 PMC 0 The standard version of A17 provides VME64 signals and rear I O for PMC 0 The PMC I O signals are directly connected to connector P2 The following table gives the pin assignment for P2 Table 12 Pin assignment of VMEbus rear I O connector P2 PMC signals D C B A Z 1 PMCO_J4 1 5V PMCO J4 2 2 PMCO J4 3 GND PMCO J4 4 GND 3 a PMCO J4 5 RETRY
57. lly for each addressing type through MENMON system parameters vme in 24 vme in 32 and vme in 64 The values are assigned in the following format Pay attention to the alignment VME address PCI address size The values are given in hexadecimal format If the size is 0 the addressing mode is disabled Example ee vme in a24 0 20000000 100000 This would result in the following mapping for A24 VME Address Range Mapped to CPU PCI Space Size 0x 00 0000 10 0000 0x 2000 0000 2010 0000 1 MB MEN Mikro Elekfronik GmbH ED DD 62 20A017 00 E4 2010 11 22 OO totes apg MED PEE te ata e a MENMON 3 7 MENMON Commands The following table gives all MENMON commands that can be entered on the A17 MENMON prompt You can fork up this list also using the H command Table 34 MENMON Command reference Command Description lt reg gt lt val gt Display modify registers in debugger model ACT lt addr gt lt size gt Execute a HWACT script ARP Dump network stack ARP table AS lt addr gt lt cnt gt Assemble memory B DC no lt addr gt Set display clear breakpoints BIOS DBG masks net cons Set MENMON BIOS or network debug level lt clun gt set debug console BO lt addr gt lt opts gt Call OS bootstrapper BOOTP lt opts gt Obtain IP config via BOOTP C BWLLNAX lt add
58. lot at a 45 angle Vl Carefully put it down making sure that the connectors are properly aligned Press the PMC module firmly onto the A17 N MI Make sure that the EMC gasket around the PMC front panel is properly in its place M Screw the PMC module tightly to the A17 using the four mounting standoffs and four matching oval head cross recessed screws of type M2 5x6 Figure 3 Installing a PMC mezzanine module PMC module Mounting standoff y 64 pin 3 3V l connectors voltage key A CPU board A 2 M2 5x6 oval 2 M2 5x6 oval head cross head cross recessed screws recessed screws MEN Mikro Elektronik GmbH 32 20A017 00 E4 2010 11 22 Functional Description 2 11 2 FPGA I O through PMC1 J4 The FPGA on board the A17 leaves room for flexible I O extensions to the board 31 signal lines are connected from the FPGA to the PMC 1 slot s J4 connector The lines are free for customized functions such as LVDS IDE graphics GPIOs UARTS or fieldbus interfaces A plug on board in PMC format but without the need for actual PMC functionality can then be used as a physical layer to implement front panel I O connectors or an onboard hard disk MEN offers a great variety of ready to implement IP core functions for the A17 FPGA You can find an overview and descriptions of available standard FPGA IP Q amp cores on MEN S website Please note that with regard to the FPGA resources such as a
59. m the board s front XMC slot if installed M The XMC module is plugged on the A17 with the component sides of the PCBs facing each other Mi Put the XMC module s front connector through the A17 s front slot at a 45 angle Mi Carefully put it down making sure that the connectors are properly aligned M Press the XMC module firmly onto the A17 M Make sure that the EMC gasket around the XMC front panel is properly in its place M Screw the XMC module tightly to the A17 using the two mounting standoffs and four matching oval head cross recessed screws of type M2 5x6 Figure 2 Installing an XMC mezzanine module XMC module Mounting standoff 114 pin connector CPU board A A 2 M2 5x6 oval 2 M2 5x6 oval head cross head cross recessed screws recessed screws MEN Mikro Elektronik GmbH 30 20A017 00 E4 2010 11 22 Functional Description 2 11 PMC Slots The A17 board provides two PMC slots for extension such as graphics hard disk Ethernet etc The market offers lots of different PMC mezzanines The signaling voltage is set to 3 3 V i e the A17 has a 3 3 V voltage key see Figure 3 Installing a PMC mezzanine module on page 32 and can only carry PMC mezzanines that support this keying configuration Mezzanine cards may be designed to accept either or both signaling voltages 3 3 V 5 V The PMC slots support 32 bit and 64 bit PCI bus operation at 33 MHz or 66 MHz The conn
60. ng instructions carefully Please be aware that you do MENMON updates at your own risk After an incorrect update your CPU board may not be able to boot WARNING After a MENMON update the hardware revision displayed by MENMON will most probably be different from the actual hardware revision of your CPU board because MENMON follows MEN s hardware revision updates Do the following to update MENMON M Unzip the downloaded file e g 44017 00 01 02 zip into a temporary direc tory M Connect a terminal emulation program with the COM 1 port of your A17 and set the terminal emulation program to 9600 baud 8 data bits 1 stop bit no par ity no handshaking if you haven t changed the target baud rate on your own Vl Power on your A17 and press ESC immediately ISl In your terminal emulation program you should see the MenMon gt prompt M Enter SERDL MENMON to update the secondary MENMON You should now see a C character appear every 3 seconds Mi In your terminal emulation program start a YModem download of file 14A017 00 01 02 smm for example with Windows Hyperterm select Trans fer gt Send File with protocol YModem Mi When the download is completed reset the A17 MEN Mikro Elektronik GmbH 47 20A017 00 E4 2010 11 22 MENMON 3 5 Diagnostic Tests Note MENMON may include further tests for COM or other interfaces depending on the A17 functionality 3 5 1 Ethernet Table 17 MENMON
61. odule PIM support through J4 complying with VITA 35 PMC 0 Miscellaneous Real time clock with battery backup Temperature sensor power supervision and watchdog Reset button in ejector handle One power good LED three user configurable LEDs at front Local PCI Bus 64 bit 66 MHz 3 3 V V I O Compliant with PCI Specification 2 2 VMEbus TSI148 controller Compliant with VME64 Specification e Supports VME32 VME64 2eVME and 2eSST VITA 1 5 Slot 1 function with auto detection Master D08 D16 D32 D64 A16 A24 A32 A64 BLT MBLT RMW Slave D08 D16 D32 D64 A16 A24 A32 A64 BLT MBLT DMA Mailbox functionality Bus timer Location Monitor Interrupter D08 O I 7 1 ROAK Interrupt handler D08 O IH 7 1 Single level 3 fair requester Single level 3 arbiter MEN Mikro Elektronik GmbH 4 20A017 00 E4 2010 11 22 Technical Data Electrical Specifications Supply voltage power consumption 5 V 3 5 approx 2 2 A 3 3 V 3 5 approx 1 1 A 12 V 596 4 596 only provided for PMCs that need 12 V 12 V 3 5 only provided for PMCs that need 12 V Mechanical Specifications Dimensions standard double Eurocard 233 3 mm x 160 mm Weight 490 g incl heat sink without XMC PMC modules Environmental Specifications Temperature range operation 40 4 85 C screened Airflow min 10 m h e Temperature range storage 40 85 C Relative humidity operation max
62. ponents are available FPGA controlled Up to hardware revision 02 xx 32 MB additional DDR2 SDRAM FPGA con trolled e g for video data 16 MB boot Flash 128 KB non volatile FRAM Serial EEPROM 8 kbits for factory settings Mass Storage Up to 4 GB soldered ATA Flash disk SSD solid state disk Higher capacity possible if components are available FPGA controlled I O Ethernet Up to four 10 100 1000Base T Ethernet channels Two RJ45 connectors at front panel Two front LEDs per channel to signal LAN Link and Activity Two channels accessible via rear I O on connector PO complying with ANSI VITA 31 1 2003 option Two RS232 UARTs COM1 2 Two RJ45 connectors at front panel Data rates up to 115 2 kbits s 16 byte transmit receive buffer Handshake lines CTS RTS GPIO 31 GPIO lines FPGA controlled Connection via PMC1 board to board connector J4 MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 Technical Data Front Connections Two Ethernet RJ45 COM1 COM2 RJ45 XMC PMC 0 and PMC 1 Rear I O Two 10 100 1000Base T Ethernet on PO option Mezzanine rear I O PMC 0 on P2 Mezzanine Slots Two slots total one slot usable for PMC or XMC One XMC slot Compliant with XMC standard VITA 42 3 2006 PCI Express links one x1 or one x2 or one x4 Two PMC slots Compliant with PMC standard IEEE 1386 1 Up to 64 bit 64 MHz 3 3 V V I O PMCI O m
63. r gt val Change memory CHAM LOAD lt addr gt Load FPGA CHAM lt clun gt Dump FPGA Chameleon table CONS Show active consoles CONS ACT lt clun1 gt lt clun2 gt Test console configuration CONS BAUD lt baud gt Change baud rate instantly without storing CONS GX lt clun gt Test graphics console D lt addr gt lt cnt gt Dump memory DBOOT clun lt dlun gt lt opts gt Boot from disk DCACHE ON OFF Enable disable L1 data cache DI lt addr gt lt cnt gt Disassemble memory DIAG lt which gt VTF Run diagnostic tests DSKRD lt args gt Read blocks from RAW disk DSKWR args Write blocks to RAW disk EER xxx lt arg gt Raw serial EEPROM commands EE xxx lt arg gt Persistent system parameter commands ERASE D lt O gt lt S gt Erase Flash sectors Fl lt from gt lt to gt lt val gt Fill memory byte GO lt addr gt Jump to user program H Print help list commands HELP lt D gt List board information ICACHE ON OFF Enable disable L1 instruction cache IOI Scan for BIOS devices MEN Mikro ElektronikGmbH C i D D DD 63 20A017 00 E4 2010 11 22 MENMON Command Description LM81 Show current voltage and temperature val ues LOGO Display MENMON start up text screen LS lt clun gt lt dlun gt lt opts gt List files partitions on device MC lt addr1 gt lt addr2 gt lt cnt gt Compare memory MII lt clun gt lt reg gt lt va
64. rd Because it is 10 times faster than Ethernet it is often referred to as Fast Ethernet Officially the 100Base T standard is IEEE 802 3u There are several different cabling schemes that can be used with 100Base T e g 100Base TX with two pairs of high quality twisted pair wires 2 8 6 1000Base T 1000Base T is a specification for Gigabit Ethernet over copper wire IEEE 802 3ab The standard defines 1 Gbit s data transfer over distances of up to 100 meters using four pairs of CAT 5 balanced copper cabling and a 5 level coding scheme Because many companies already use CAT 5 cabling 1000Base T can be easily implemented Other 1000Base T benefits include compatibility with existing network protocols i e IP IPX AppleTalk existing applications Network Operating Systems network management platforms and applications MEN Mikro Elektronik GmbH 26 20A017 00 E4 2010 11 22 Functional Description 2 9 UART Interfaces COMI and COM2 are standard RS232 interfaces They are available via two RJ45 connectors at the front panel COM1 is controlled by the MPC854X UART 0 COM2 is controlled by the MPC854X UART 1 Connector types Modular 8 8 pin mounting jack according to FCC68 Mating connector Modular 8 8 pin plug according to FCC68 Table 4 Pin assignment of 8 pin RJ45 UART front connectors COM1 COM2 1 z 2 3 4 GND 5 RXD 6 TXD 7 CTS 8 RTS Tabl
65. rolled by the CPU AII channels support up to 1000 Mbits s and full duplex operation LANI and LAN are accessible at the front panel while LAN3 and LANA are routed to the optional VME PO connector for rear I O Please note that LAN3 and LANA are not available on board versions with the MPC8543 processor The unique MAC address is set at the factory and should not be changed Any attempt to change this address may create node or bus contention and thereby render the board inoperable The MAC addresses on the A17 are LANI 0x 00 CO 3A 65 xx xx LAN2 0x 00 CO 3A 66 xx xx LAN3 0x 00 CO 3A 67 xx xx LAN4 0x 00 CO 3A 68 xx xx where 00 CO 3A is the MEN vendor code 65 to 68 are the channel related codes and xx xx is the hexadecimal serial number of the product which depends on your board e g 00 2A for serial number 000042 See Chapter 6 2 Finding out the Board s Article Number Revision and Serial Number on page 71 2 8 1 Connection at Front Two standard RJ45 connectors are available at the front panel for connection of LANI and LAN2 Two status LEDs each are integrated into the connectors The pin assignments correspond to the Ethernet specification IEEE802 3 Connector types Modular 8 8 pin mounting jack according to FCC68 Mating connector Modular 8 8 pin plug according to FCC68 Table 2 Pin assignment of 8 pin RJ45 Ethernet front connectors LANT LAN2 1000Ba
66. se T 10 100Base T 1 BI DA TX Yellow OA 2 BI_DA TX Lights up whenever there is B receive activity 3 BI_DB RX 4 BI_DC 5 BI_DC Green L 6 BI_DB RX Lights up as soon as a E 1000 Gbit link is established 7 BLDD 8 BI_DD MEN Mikro Elektronik GmbH 24 20A017 00 E4 2010 11 22 Functional Description Table 3 Signal mnemonics of Ethernet front interfaces Signal Direction Function BI_D A D in out Differential pairs of data lines for 1000Base T RX in Differential pair of receive data lines for 10 100Base T TX out Differential pair of transmit data lines for 10 100Base T 2 8 2 Connection at Rear VMEbus connector PO can be implemented as an option for Gigabit Ethernet backplane I O according to ANSI VITA 31 1 2003 In this case channels LAN3 and LAN4 are connected in compliance with ANSI VITA 31 1 2003 LAN3 is connected to LPa of the backplane and LAN4 is connected to LPb For the pin assignment please see Table 14 Pin assignment of VMEbus rear I O connector PO 95 pin type B modified Ethernet on page 41 Please note that the PO rear I O option is not available on board versions with the MPC8543 E processor 2 8 3 General Ethernet is a local area network LAN protocol that uses a bus or star topology and supports data transfer rates of 100 Mbits s and more The Ethernet specification served as the basis for the IEEE 802 3 standard which specifies the physical an
67. t first fills the entire memory starting with the lowest address with the selected pattern using the selected access mode and then verifies the entire block This test is destructive Checks All address lines All data lines All control signals All SDRAM cells 3 5 3 FPGA Table 19 MENMON Diagnostic tests FPGA Test Name Description Availability FPGA FPGA presence test Always Groups POST AUTO 3 5 4 EEPROM Table 20 MENMON Diagnostic tests EEPROM Test Name Description Availability EEPROM laC access Magic nibble check Always Groups POST AUTO ENDLESS This test reads the first EEPROM cell over SMB and checks if bits 3 0 of this cell contain the magic nibble 0xE MEN Mikro Elektronik GmbH 50 20A017 00 E4 2010 11 22 MENMON 3 5 5 SSD Flash Disk Table 21 MENMON Diagnostic tests SSD Flash disk Test Name Description Availability IDE1 SSD Check if solid state Flash disk Always SSD is present Groups POST The test first performs an ATA register test then reads sector 0 from the Flash disk without verifying the content of the sector Checks Most ATA control lines Basic ATA transfer Does not check ATA signals IRQ DAK DRQ Partition table or file system on disk 3 5 6 COM1 COM2 Table 22 MENMON Diagnostic tests COM1 COM2 Test Name Description Availability COM1 External loopback test RxD TxD
68. ter cable with a standard 9 pin D Sub plug connector Please see MEN s website for ordering information MI Set your terminal to the following protocol 9600 baud data transmission rate 8 data bits 1 stop bit No parity MI Power up the system MEN Mikro Elektronik GmbH 17 20A017 00 E4 2010 11 22 Getting Started Mi The terminal displays a message similar to the following Secondary MENMON for MEN EM9 Family 1 1 A017 c 2007 2008 MEN Mikro Elektronik GmbH Nuremberg MENMON 2nd Edition Created Jan 9 2008 4s ile Sil CPU Board A017 00 Serial Number 8 CPU MPC8548E CPU MEM Clk 1320 264 MHz HW Revision 00 01 00 SABES Ca O 528 66 MHz DDR2 SDRAM 1 GB ECC on 4 0 4 11 FRAM 128 kB FLASH 16 MB Reset Cause by software Produced l PGs CA BI Y Ss MEI Last repair l Carrier Board a ee a ew DD es ee ee r r r r rrr rr eee Setting speed of NETIF 0 to AUT Seri ng speed or NETIF JL to AUT Seri ing speed er NETIF 2 to AUT Setting speed of NETIF 3 to AUT Sis SS press ESC for MENMON s for setup Test SDRAM amp IE Test FPGA ORK Test ETHERO 8 QIK Test ETHERI 8 QIK Test ETHER2 JAOK Test ETHERS amp 9e Test EEPROM amp IK Test RTC OK Test IDEO NAND OK NOW AUTOEXECUTING BO No default start address configured Stop Setup network interface CLUN 0x02 00 c0 3a 62 00 08 AUTO Searching for server BOOTP in background Telnet daemon started
69. tton to enter the Setup Menu With a text console press the s key to enter the Setup Menu With a text console press ESC to enter the command line By default the self test is not left until 3 seconds have elapsed measured from the beginning of the self test even if the actual test has finished earlier to give the user a chance to abort booting and enter the Setup Menu You can modify the self test wait time through MENMON system parameter stwait see page 60 3 3 Configuring MENMON for Automatic Boot You can configure how MENMON boots the operating system either through the Setup Menu or through the command line In the Basic Setup Menu you can select the boot sequence for the bootable devices on the A17 The selected sequence is stored in system parameter mmstartup as a string of MENMON commands For example if the user selects Int CF NAND Ether None the mmstartup string will be set to DBOOT 0 NBOOT TFTP You can view and modify this string directly using the Expert Setup Menu option Startup string or through the command line command EE MMSTARTUP See also MENMON 2nd Edition User Manual for further details MEN Mikro Elektronik GmbH 45 20A017 00 E4 2010 11 22 3 4 3 4 1 MENMON Updating Boot Flash SSD Flash SDRAM and EEPROM Update via the Serial Console using SERDL You can use command SERDL to update program data using the serial console The following table shows the A17 loc
70. vailable logic elements or pins it is not possible to grant all possible combinations of FPGA IP cores Please ask our sales staff for configuration possibilities By standard GPIO lines are routed to the J4 connector Four GPIO controllers MEN 16Z034 GPIO are included in the FPGA to provide 31 GPIO lines Voltage levels are LVTTL You can control the GPIO lines through software using MDIS driver software c available on MEN s website The following table gives the assignment of the GPIO controllers implemented in the A17 s FPGA to their function on the board Normally you can identify the controllers by their instance numbers in your operating system Table 8 Assignment of 162034 GPIO controllers Instance Function GPIO lines O to 7 bits O 7 GPIO lines 8 to15 bits 0 7 GPIO lines 16 to 23 bits O 7 GPIO lines 24 to 30 bits 0 6 Sl ST By default all GPIOs are configured as inputs so that there are no conflicts with PMC P4 signals if you use a PMC with a P4 connector unless you reconfigure the GPIO direction by software MEN Mikro Elektronik GmbH 33 20A017 00 E4 2010 11 22 MEN Mikro Elektronik GmbH 20A017 00 E4 2010 11 22 Functional Description Table 9 Pin assignment of PMC1 board to board connector J4 FPGA I O signals 63 LE 45 47 49 51 53 55 57 59 61 63 46 48 50 52 54 56 58 60 62 64 Functional Description
71. write e netip IP address subnet mask e g Empty string No Read write 192 1 1 28 ffffff00 g netgw IP address of default gateway Empty string No Read write h nethost Host IP address used when booting Empty string No Read write over NBOOT TFTP netaddr Access the IP address part of netip No Read write parameter netsm Access the subnet mask part of netip No Read write parameter procnum VxWorks processor number decimal O No Read write S VxWorks start up script Empty string No Read write tn netname Host name of this machine Empty string No Read write unitnum VxWorks boot device unit number deci 0 No Read write mal MEN Mikro ElektronikGmbH re eee eae 6I 20A017 00 E4 2010 11 22 MENMON 3 6 5 4 Reset Cause Parameter rststat The following rststat values are possible When MENMON starts up it determines the reset cause and sets system parameter rststat accordingly Table 33 MENMON Reset causes through system parameter rststat rststat Value Description hrst Board was reset due to activation of HRESET line pwon Power On wdog Board was reset by watchdog time out reset controller rbut Board was reset by an external reset pin e g reset button swrst Board was reset by software by means of the board s reset con troller vme VMEbus reset 3 6 5 5 VMEbus Slave Address Mappings Parameter vme in aXX You can set the address ranges for VMEbus slave accesses individua

20A017-00 E4 User Manual - MMC Media MicroComputer

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