AN2248 Application Note
Contents
1. when using both CS MOTOROLA Using the MGT5100 SDRAM Controller 11 AN2248 D Appendix C SDRAM DDR Configuration Examples The following table reports just some possible architectures supported by the MGT5100 Memory Controller It must be considered as an example only DDR Devices Device Row x Data Min Min total Physical Address Multiplexing on the internal XLB Control Xib_Sel Note Architec Col widthper number available Bus Regis 6 7 ture umn x single of devic memory ter bits Banks chip in es need per CS 3 l4 5 6 7 18 19 20 21 28 6 7 bits ed per CS Mbytes MT46V2M32 64 Mbit 11x8x4 32 1 8 xX X X CS Row 10 0 Bank 1 0 Col 7 0 00 00 Row 11 is not driven MT46V16M8 128 Mbit 12x10x4 8 4 64 X CS Col Col8 Row 11 0 Bank 1 0 Col 7 0 00 10 Not recommended to IBMN612804GT3B 3 use with both CS MT46V8M16 12x9x4 16 2 32 X X CS Col8 Row 11 0 Bank 1 0 Col 7 0 00 01 64 Mbytes can be mounted using both CS MT46V32M8 256 Mbit 13x10x4 8 4 128 X CS Col Row Row 11 0 Bank 1 0 Col 7 0 01 ar Not recommended to HYB25D256800AT 8 12 use with both CS MT46V16M16 13x9x4 16 2 64 X CS Col Row Row 11 0 Bank 1 0 Col 7 0 01 10 128 Mbytes possible 8 12 when both CS are used MT46V64M8 512 Mbit 13x11x4 8 4 256 xX X X xX X X X xX xX Not Su2. Up to 4 banks are used leaving a total of 24 internal address lines for row and column including the internal address line connected to the chip select e On the pins the MGT5100 presents 13 address lines on which rows and columns are multiplexed in time Up to 13 rows and 12 columns can be controlled but not at the same time The sum of rows and columns must always be less than or equal to 24 Aminimum number of eight columns used by the memory must be assured for proper operations For this reason the memory controller does not support those 4M x 32 bit devices which uses columns 0 through 6 only See the note below e The memory controller also will NOT work with devices which have more than 8 columns but less than 12 rows Always refer to the MGT5100 User Manual for a detailed table of the supported architectures Note There are 32 bit wide devices on the market such as the MT46V4M32 by Micron whose internal architecture uses a minimum of 8 columns and therefore can be used along with the MGT5100 s memory controller There are two physical chip select pins on the MGT5100 One is always used as chip select function and has no other possible function while the second has at boot the default function of GPIO GPIO_WKUP_6 The total addressable memory is split into equal parts on the 2 chip selects even when one is not used by programming of the Address Select Register located at MBAR MEMCTL 0x100 This impli
3. be set to 01 Here the value 0x40090000 is used enable DLL reduced drive strength QFC function disable normal operating mode This examples differs from the SDR example in that the DDR specific fields must be filled These are e ddr_mode bit must be set to 1 e ddr_32bit bit must be set to 1 in case a 32 bit device is used 32 bit devices use A8 instead of A10 to control refresh operation e the bits in the ddr_dqs_en field must set to 1 corresponding to the byte lanes the device uses Here the value 0x714FOFO0O is used minimum refresh cycle time is 15 625 us Here the value 0x73622730 is used The major difference to the SDR example is that some fields are expressed in XLB bus clocks and some use double the frequency of the XLB bus Please refer to MGT5100 s user manual for details Here the value 0x45770004 is used As in the Config1 registers some of the fields use the XLB bus clock some use double the frequency of the XLB bus The Config3 register is used in the same way in this example as in the SDR example i e using the value 0x0002 MOTOROLA Using the MGT5100 SDRAM Controller 7 AN2248 D Appendix A Software Listing SDRAM Controller Initialization equ MBAR 0x80000000 Module Base Address equ IPBI_SDRAM_START 0x0034 Offset to SDRAM start BAR equ IPBI_SDRAM_END 0x0038 Offset to SDRAM end BAR equ IPBI_CS ENABLE 0x0054 Offset to
4. controlled device and subsequently can be latched by the core MGT5100 supports a CL equal to 2 or 3 for SDR while for DDR the value can be 2 2 5 or 3 As already mentioned MGT5100 s memory controller supports invisible control of the memory device by taking responsibility of all the hand shaking once the appropriate setup for the memory has been completed Using the MGT5100 SDRAM Controller MOTOROLA Supported Architecture Chip Selects AN2248 D What is SDRAM The MGT5100 provides a simpler usage model for DRAMs compared to other processors of the PowerPC family ex PPC823 PPC8260 etc The price for this ease of use is the restriction that NOT all SDRAM DDR devices available on the market can be used but the memory controller covers most of them The limitations of the controller are shown in detail below e MGT5100 supports only a 32 bit wide external memory system architecture which can be achieved using a single 32 bit device or two 16 bit devices or even four 8 bit devices Single 16 bit devices can not be used on MGT5100 Internally the XLB data bus is 64 bits wide so that the data fetched from the external device is aligned on a long word 64 bit boundary e The MGT5100 s internal address bus allocates up to 26 bits to control the external dynamic memories to each of two external chip selects e With 26 address bits and 32 data bits the maximum memory size allowed is 256 MBytes 128 MBytes per chip select
5. is not driven HYB 39S64800ET 7 5 12x9x4 8 4 32 xX xX CS Col8 Row 11 0 Bank 1 0 Col 7 0 00 01 HYB 39S64160ET 7 5 12x8x4 16 2 16 xX X X CS Row 11 0 Bank 1 0 Col 7 0 00 00 K4S643232E Tl 11x8x4 32 1 8 X X xX CS Row 10 0 Bank 1 0 Col 7 0 00 00 Row 11 is not driven MT48LC16M8A2 128 Mbit 12x10x4 8 4 64 X CS Col Col8 Row 11 0 Bank 1 0 Col 7 0 00 10 Not recommended to HYB 398128800CT 7 5 9 use withibown GS MT48LC8M16A2 12x9x4 16 2 32 xX xX CS Col8 Row 11 0 Bank 1 0 Col 7 0 00 01 64 Mbytes can be HYB39 128160CT 7 5 mounted using both CS MT48LC4M32B2 12x8x4 32 1 16 xX X xX CS Row 11 0 Bank 1 0 Col 7 0 00 00 32 Mbytes can be obtained using both CS MT48LC32M8A2 256 Mbit 13x10x4 8 4 128 xX CS Col Row Row 11 0 Bank 1 0 Col 7 0 01 Ad Not recommended to HYB 39S256800CT 7 5 8 12 use with both CS MT48LC16M16A2 13x9x4 16 2 64 X CS Col Row Row 11 0 Bank 1 0 Col 7 0 01 10 128 Mbytes possible HYB 39S256160CT 7 5 8 12 when both CS are used MT48LC64M8A2 512 Mbit 13x11x4 8 4 256 X X X X X xX X X xX Not Supported There HYB 398512800AT 7 5 cari tbe 2o6Mbytes ona single CS MT48LC32M16A2 13x10x4 16 2 128 CS Col Col Row Row 11 0 Bank 1 0 Col 7 0 01 At Max available memory 9 8 12 256 Mbytes is reached HYB 398512160AT 7 5
6. must be one less e Read delay tab is set to default i e 4 XLB clocks 6 Using the MGT5100 SDRAM Controller MOTOROLA Config3 Register Example 2 DDR Mode Register Extended Mode Register Control Register Config1 Register Config2 Register Config3 Register AN2248 D Examples The Config3 Register also known as Adr_Sel Register is used to partition the available memory between the two SDRAM controller chip selects For this example the value written to this register is Ox0002 This is equivalent to 64 MBytes per chip select Therefore in this example the entire memory is covered by a single chip select This example demonstrates how to set up the MGT5100 memory controller to access four Micron MT46V16M68 devices which results in 64 MBytes of memory First the environment of the DDR SDRAM chips must be defined In this case the XLB speed is 66MHz and only one chip select is going to be used Now the configuration values for the SDRAM controller can be calculated This example will only show the differences to the SDR example above The Mode Register is used here in the same way it has been used in the SDR example Refer to the memory data sheet for the detailed meaning of the mode_code field s value Here the value Ox008D0000 is used Physically the Extended Mode Register is at the same address as the Mode Register To write to the Extended Mode Register the two most significant bits of the mode_code field must
7. select is going to be used Now the configuration values for the SDRAM controller can be calculated The mode_code field s value is defined in the data sheet of the SDRAM and must be taken from there For this example the burst length is eight burst type is sequential CAS latency is two operating mode is standard and write burst mode is set to the programmed burst length Additionally the Mode Register s write_strobe bit is set to one to generate a write strobe pulse to write the valid data into the SDRAM Therefore the value written to the Mode Register is 0x008D0000 MOTOROLA Using the MGT5100 SDRAM Controller 5 AN2248 D Control Register Config1 Register The value written to this register is 0x51470000 This is equivalent to e SDRAM clock is enabled e Memory device is of SDR type e Refresh counter is enabled e Fast XLB bus clock is not enabled e Row column multiplexing according to Table 1 is 01 column 10 9 8 and row 12 are multiplexed respectively to internal addresses 4 to 7 e SDRAM controller drives the data bus always except during read to save power e Refresh counter is set to 0x07 The refresh counter is calculated as follows the basic information is the minimum refresh time which can be found in the SDRAM data sheet For our example it is 7 81 us The formula to calculate the refresh counter value is refresh_count tea retek time perioe 1 64 Therefore refresh_count is e
8. Application Note AN2248 D Rev 1 02 2002 Using the MGT5100 SDRAM Controller eta rr MOTOROLA digital dna intelligence everywhere by Mark Jonas and Davide Santo Driver Information Systems Munich Germany Introduction What is SDRAM Synchronous Dynamic RAM SDRAM and Double Data Rate Synchronous Dynamic RAM DDR SDRAM or simply DDR are among today s preferred memories where high speed and low power are needed One specific advantage of the MGT5100 is the support of fast Synchronous Dynamic RAM by a dedicated memory controller and a physical interface separate from the peripheral bus also known as the local plus Bus This dedicated memory controller has its own set of registers to control its operation which should simplify the design of memory subsystem hardware and software The MGT5100 SDRAM Controller provides all the handshaking signalling for both SDRAM or DDR architectures allowing a glueless and straightforward connection of the memory to the processor A total of 5 registers are available to program the memory controller which is very flexible and can easily be adapted to many different types of SDRAM or DDR with minimum effort This application note will explore the characteristics and the programming environment of the MGT5100 memory controller and provide some simple examples for reference SDRAM and the recently introduced DDR SDRAM are dynamic RAMs Random Access Memory operating synchronous
9. CS ENABLE r8 r9 r9 0x0040 r9 IPBI_ CS ENABLE r8 set SDRAM in R8 setup SDRAM start stop address and enable chip select start address stop address enable SDRAM CS Using the MGT5100 SDRAM Controller MOTOROLA AN2248 D Examples Step 2 write CONFIG1 addis r4 xr0 DRAM CONFIG1 h ori r4 r4 DRAM CONFIG1 l stw r4 MEMCTL_ CONFIGI1 r8 write CONFIG1 Step 3 write CONFIG2 addis r4 xr0 DRAM CONFIG2 h ori r4 r4 DRAM CONFIG2 l stw r4 MEMCTL_ CONFIG2 r8 write CONFIG2 Step 4 write CONFIG3 addis r4 xr0 DRAM ADRSEL h ori r4 xr4 DRAM ADRSEL 1 stw r4 MEMCTL_ CONFIG3 r8 write CONFIG3 Step 5 write CONTROL addis r4 xr0 DRAM CONTROL h ori r4 xr4 DRAM CONTROL 1 mr r5 r4 oris r5 r5 0x8000 stw r5 MEMCTL_ CONTROL r8 write CONTROL Step 6 issue precharge all mr r6 r5 ori r6 r5 0x0002 stw r6 MEMCTL_ CONTROL r8 write CONTROL Step 7 write EXTENDED MODE for DDR only if RAMTYPE DDR addis r6 r0 DRAM EMODE h ori r6 xr6 DRAM EMODE 1 stw r6 MEMCTL_ MODE r8 write MODE endif Step 8 write MODE addis r6 xr0 DRAM MODE h ori r6 xr6 DRAM MODE 1 oris r6 xr6 0x0400 stw r6 MEMCTL MODE r8 write MODE Step 9 issue precharge all followed by a refresh mr r6 r5 ori r6 r5 0x0002 stw r6 MEMCTL_ CONTROL r8 write CONTROL ori r6 r5 0x0004 MOTOROLA Using the MGT5100 SDRAM Controller 9 AN2248 D stw r6 M EMCTL CONTROL r8 St
10. CS enable register equ MEMCTL_ MODE 0x0100 Offset to SDRAM Mode register equ MEMCTL_ CONTROL 0x0104 Offset to SDRAM Control register equ MEMCTL CONFIG1 0x0108 Offset to SDRAM Configl register equ MEMCTL CONFIG2 0x010C Offset to SDRAM Config2 register equ MEMCTL_ CONFIG3 0x0110 Offset to SDRAM Config2 register equ DRAM_START 0x00000000 SDRAM Start address equ DRAM_STOP 0x04000000 SDRAM stop address equ RAMTYPE DDR activate this switch for DDR else SDR if RAMTYPE DDR Settings for four Micron MT46V32M8 DDR devices XLB 66 MHz equ DRAM_EMODE 0x40090000 equ DRAM_MODE 0x008D0000 equ DRAM_CONTROL 0x714F0F00 equ DRAM_CONFIG1 0x73622730 equ DRAM_CONFIG2 0x45770004 equ DRAM_CONFIG3 0x02000000 64 MB total else Settings for two Micron MT48LC16M16A2 SDR devices XLB 66 MHz equ DRAM_MODE 0x008D0000 equ DRAM CONTROL 0x51470000 equ DRAM_CONFIG1 0xC2222600 equ DRAM_CONFIG2 0x88B70004 equ DRAM CONFIG3 0x02000000 64 MB total endif HHHHHHHHHH here the initialization code starts H HHHH HHH addis ori Step 1 addis ori stw addis ori stw lwz oris stw r8 r0 MBAR h r8 r8 MBAR 1 r9 r0 DRAM S r9 r9 DRAM S r9 IPBI_SDRAM_ r9 r0 DRAM _S1 MBAR held ART gt gt 15 h set SDRAM ART gt gt 15 1 START r8 TOP gt gt 15 h r9 r9 DRAM S1 TOP gt gt 15 l1 r9 IPBI_SDRAM_END r8 r9 IPBI_
11. egisters SDRAM Controller Registers Mode Register Control Register Config1 Register Config2 Register Config3 Register Examples Example 1 SDRAM Mode Register To set up the memory controller for operation with SDR or DDR SDRAM only 5 registers are needed The Mode Register is a general register address to facilitate access to the Mode Register and the Extended Mode Register for DDR only respectively of the SDRAM memory device It does not have an effect on the memory controller of the MGT5100 directly This register is used to set up the main characteristics of the memory controller It can select whether MGT5100 drives SDR or DDR memory the row column multiplexing scheme and many other things The MSB of this register enables write access to the Mode Register Single Read and Single Write timings are covered by this register Burst Read and Burst Write timings are covered by this register This register is also known as Addr_Sel Register It is used to set the maximum amount of memory accessed by each of the two available SDRAM chip selects That is it defines an address boundary where the total memory is split between the two chip selects This example demonstrates how to set up the MGT5100 memory controller to access two Micron MT48LC16M16A2 devices which results in 64 MBytes of memory First the environment of the SDR SDRAM chips must be defined In this case the XLB speed is 66MHz and only one chip
12. ep 10 issue refresh stw r6 M Step 11 write MOD EMCTL CONTROL r8 oy addis r6 xr0 DRAM MODE h ori r6 xr6 DRAM MODE 1 stw r6 MEMCTL_ MODE r8 Step 12 write CONTROL stw r4 MI EMCTL CONTROL r8 write write write write CONTROL CONTROL MODE CONTROL 10 Using the MGT5100 SDRAM Controller MOTOROLA Appendix B SDRAM SDR Configuration Examples AN2248 D Examples The following table reports just some possible architectures supported by the MGT5100 Memory Controller It must be considered as an example only SDR Devices Device Row x Data Min num Min total Physical Address Multiplexing on the internal XLB Bus Control XLB_S Note Archi Col width per ber of de available Register el 6 7 tecture umnx_ single vices memory 3 4 5 6 7 18 19 20 21 28 bits 6 7 Banks chip in needed per CS bits per CS Mbytes MT48LC1M16A1 16 Mbit 11x8x2 16 2 4 xX x X X X X xX X X Not Supported because it uses only 2 banks MT48LC8M8A2 64 Mbit 12x9x4 8 4 32 X X CS Col8 Row 11 0 Bank 1 0 Col 7 0 00 01 It is recommended NOT to use more than 4 devices allocated on the Memory controller bus MT48LC4M16A2 12x8x4 16 2 16 xX X X CS Row 11 0 Bank 1 0 Col 7 0 00 00 MT48LC2M32B2 11x8x4 32 1 8 X X X CS Row 10 0 Bank 1 0 Col 7 0 00 00 Row 11
13. es that up to 128 MBytes can be controlled by each single chip select The signals controlling each chip selects are derived directly from the internal bus address lines A3 A4 A5 or A6 depending whether 128 MBytes 64 MBytes 32 MBytes or just 16 MBytes are used per chip select See Appendix B at the end of this application note for a table reporting some possible devices which are supported by the controller The table shows how the physical columns and rows are re mapped on the internal XLB bus It also shows which internal signal is used case by case to control the 2 external chip select pins MOTOROLA Using the MGT5100 SDRAM Controller 3 AN2248 D As an example let s discuss a 512Mbit DDR memory by MICRON which comes in two different flavours a MT46V64M8 which is a 64Maddress x 8 bits 4 banks b MT46V32M16 which is a 32MAddress x 16 bits 4 banks Case a needs to be controlled by using AO A12 for rows and AO AQ plus A11 for the columns A10 is used in connection with the precharge operation therefore it is not really part of the address With the sum of rows and columns being equal to 24 the control of the device should be possible Indeed this is not the case In fact the memory controller internally multiplexes some higher row and column lines onto the internal address lines A3 to A6 The selection of which row column will be placed on which internal line is done via software at initialization time by writ
14. ics of SDRAM DDR memory can be summarized as follows 1 Internal matrix organization address of a memory location is decoded using row and column lines which are time multiplexed as they share the same pins on the controller 2 Refresh being a dynamic memory a refresh mechanism is needed to keep memory content valid The MGT5100 allows self refresh to be active even in the so called deep sleep mode when no clocks are running inside the core 3 Banks the memory is divided into banks to allow more efficient transactions A bank must be precharged before any one of its location can be read or written 4 Memory access is time multiplexed commands such as read active write etc are sequenced to allow access to a location For example a typical access to a new bank s location would be achieved by the Precharge Active Read Write sequence It is important that the memory controller controls all the specific timings and delays during the sequence 5 Single and multiple reads called Burst or writes operations are allowed 6 Initialization of a SDRAM device consists of a pre defined procedure which includes writing to dedicated registers located internally in the controlled device the MODE and EXTENDED MODE registers 7 CAS Latency CL this is the most important parameter of a SDRAM and represents the delay between a Read command issued by the controller and the instant when the data is driven onto the bus by the
15. ing the Control register s addr_sel bits bits 6 7 according to the following table Please note that bit 7 shall be always 0 Table 1Row and Columns Multiplexing Table Maximum number of device on the bus addr_sel bits PPC internal address lines mapped to COL or ROW address A3 A4 A5 A6 00 COL 11 COL 10 coL 9 COL 8 01 COL 10 COL 9 COL 8 ROW 12 10 X X X X 11 X X X X The obvious choice would be setting the add_sel bits to b 01 It is clear that Column Address Line 11 is not supported by this multiplexing and therefore the MGT5100 will NOT be able to use this architecture Instead Case b needs only columns AO AQ see data sheet for more details In this circumstance by choosing the option b 01 because A10 is not used by the device the internal address line A3 can be re routed externally on one chip select Careful analysis of the memory data sheet is highly recommended as the same device 512 MBits DDR might have different architectures NOT all of which will be supported The MGT5100 dynamic bus interface specifies an absolute maximum load of 25pF on the memory bus with a typical value of 17pF Considering these values and the high frequency of operation it is generally recommended for high performance to limit the number of memory devices supported by a single chip select to one or two Using the MGT5100 SDRAM Controller MOTOROLA AN2248 D SDRAM Controller R
16. ity of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was
17. ly to the processor which controls them Transactions of data are faster and more efficient than with more conventional memory devices such as FPRAM Fast Page Mode Dynamic RAM or EDORAM Extended Data Output Dynamic RAM or BEDORAM Burstable EDORAM As a matter of fact SDRAM memory includes all the specific advantages of these other devices such as bursting fetching the next block of memory when the previous one is sent over the bus etc Motorola Inc 2002 AN2248 D Synchronous Dynamic RAM characteristics DDR SDRAM also called SDRAM II uses both clock edges to transfer data during a transaction allowing a double data rate at the same clock speed if compared with SDRAM Also DDR memory will use only 2 5V supply voltage versus the typical 3 3V used by the SDRAM type thereby reducing power consumption For both kind of memories the synchronous operation tends to increase the number of instructions the processor can perform in a given time The main difficulty in using SDRAM and DDR is due to the unusual architecture different banks divided into rows and columns of the SDRAMs Their control can appear to the inexperienced person as cumbersome because many parameters have to be taken into consideration Part of the design goal behind the MGT5100 s Memory Controller was to achieve an easy to use program all under SW control and an easy to use interface for the user of the processor In general the characterist
18. negligent regarding the design or manufacture of the part MOTOROLA Motorola and the Stylized M Logo are registered in the U S Patent and Trademark Office All other product or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 2002 AN2248 D
19. pported There can t be 256Mbytes on a single CS MT46V32M16 13x10x4 16 2 128 CS Col Col Row Row 11 0 Bank 1 0 Col 7 0 01 ar Max available memory 9 8 12 256 Mbytes is reached when using both CS 12 Using the MGT5100 SDRAM Controller MOTOROLA MOTOROLA Using the MGT5100 SDRAM Controller 13 14 Using the MGT5100 SDRAM Controller MOTOROLA MOTOROLA Using the MGT5100 SDRAM Controller 15 HOW TO REACH US USA EUROPE LOCATIONS NOT LISTED Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 303 675 2140 or 1 800 441 2447 JAPAN Motorola Japan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 TECHNICAL INFORMATION CENTER 1 800 521 6274 HOME PAGE http www motorola com semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitabil
20. qual to 0x07 The Config1 Register is used to store the delay values between the single read and single write commands The SDRAM controller uses these values to generate the proper delays when accessing the device The delays are expressed in XLB bus clock cycles Some of these values are fixed by the design of the SDRAM controller and some must be calculated using the memory device s data sheet Please refer to the MGT5100 User Manual for the detailed description of each field For this example the value written to this register is OxC2222600 This is equivalent to e Single read to read write delay is 12 XLB clocks this is a conservative setting e Single write to read or pre charge delay is 2 XLB clocks e Read CAS latency is 2 XLB clocks e Active command to read write delay is 2 XLB clocks e Precharge command to active command delay is 2 XLB clocks e Refresh to active command delay is 6 XLB clocks e Write latency delay is O XLB clocks SDR does not have a latency on the write command Config2 Register The Config2 Register is used to store the delay values for burst access The same applies as mentioned previously for the Config1 Register For this example the value written to this register is Ox88B70004 This is equivalent to e Burst read to read pre charge delay is 8 XLB clocks e Burst write to read write delay is 8 XLB clocks e Burst read to write delay is 11 XLB clocks e Burst length is 8 XLB clocks the value written
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