LPC1766-STK development starterkit board
Contents
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3. 8 04 5 R15 8 352 5 4 0 _ Of 13 12 15 13 11 R152 2983 _ 41 Page 17 16 14 12 10 USB HOST Signal Name USB 2 0 full speed Host controller with dedicated DMA controller and on chip PHY The host controller enables full and low speed data exchange with USB devices attached to the bus It consists of a register interface a serial interface engine and a DMA controller The register interface complies with the OHCI specification USB DEVICE Signal Name 5V_USB_DEV USB_DEV_D The device controller enables 12 Mbit s data exchange with a USB Host controller It consists of a register interface serial interface engine endpoint buffer memory and a DMA controller The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer The status of a completed USB transfer or error condition is indicated via status registers An interrupt is also generated if enabled When enabled the DMA controller tr
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6. 00070 measures in Inches Page 21 AVAILABLE DEMO SOFTWARE Accelerometer Demo Basic use of I O timer interrupt controllers LDC module and the on board accelerometer EW ARM 5 40 Audio Device Class USB audio device class with one output and one input EW ARM 5 40 Getting Started Basic use of I O timer and interrupt controllers EW ARM 5 40 LCD Demo Basic use of the I O timer interrupt controllers and LDC module for graphic and text drawing EW ARM 5 40 Mass Storage Class USB mass storage class with MMC SD card drive EW ARM 5 40 Simple periherals Simple ADC demo Basic use of ADC Simple DAC demo Basic use of DAC Simple DMA demo Basic use of DMA Simple EMAC demo Basic use of EMAC Simple EXTINT demo Basic use of EXTINT Simple GPIO demo Basic use of GPIO Simple RTC demo Basic use of RTC Simple SSP demo Basic use of SSP Simple Timer demo Basic use of Timer Simple UART demo Basic use of UART Simple WDT demo Basic use of WDT EW ARM 5 40 uIP WEB Server WEB server application running on the top of the uIP 1 0 TCP IP stack EW ARM 5 40 USB Host Demo USB host masstorage class framework EW ARM 5 40 USB Mouse USB HID class Mouse EW ARM 5 40 Virtual COM Port USB communication device class EW ARM 5 40 Page 22 ORDER CODE LPC 1766STK assembled and tested board How to order You can order to us directly or by any of our distributors Check our web www olimex co
7. LPC1766 STK development board Users Manual Petes Sn All boards produced by Olimex are ROHS compliant Revision Initial October 2009 Copyright c 2009 OLIMEX Ltd All rights reserved Page 1 INTRODUCTION LPC1766 STK is development board with LPC1766 Cortex microcon troller from NXP This powerful microcontroller supports various serial interfaces such as USB Device Host OTG UART CAN and other On the board are avalable audio input and output digital accelerometer JTAG Ethernet TFT LCD and mini SD MMC card connector All this allows you to build a diversity of powerful appli cations to be used in a wide range of applications BOARD FEATURES MCU LPC1766 Cortex M3 100 Mhz 256KB Flash 64KB RAM Ether net MAC USB Host Device OTG x4 UARTS CAN SPI SSP 125 ADC DAC TC LCD NOKIA 6610 128x128 x12bit color TFT with Epson LCD controller 3 axis digital accelerometer with 11 bit accuracy temperature sensor Ethernet 100Mbit CAN interface and connector USB host connector USB device connector USB OTG connector two user LEDs three user buttons joystick potentiometer micro SD MMC card connector JTAG and TRACE connectors power supply RESET circuit UEXT connector Audio IN Audio OUT RTC battery FR 4 1 5 mm red soldermask component print Dimensions 134 6x101 6mm 5 3 x 4 0 Page 2 ELECTROSTATIC WARNING The LPC1766 STK board is shipped in protective anti static packaging
8. PO P2 GPIO INTERRUPT CONTROL RTCX1 mane l 1 2 OSCILLATOR BACKUP REGISTERS _ MOTOR CONTROL PWM 058 QUADRATURE ENCODER Grey shaded blocks represent peripherals with connection to the GPDMA Page 6 CLKOUT SCKO SSELO MISOO MOSIO RXD2 3 TXD2 3 3 x I2SRX 3 125 TX_MCLK RX_MCLK SCL2 SDA2 4 x 2 2 x MAT3 2 x CAP2 2 x CAP3 EINT 3 0 MCOA B MC1A B MC2A B MCFB1 2 MCABORT INDEX 0000 000 0 0007 000 0 0008 000 0 0002 000 7 0 0000 00 0 0007 00 0 0008 00 7 0 0000 00 0 0000 0007 0008 0000 0 0000 00 7 0 0007 00 7 0 0008 00 7 0 0000 00 0 0000 0007 0008 0000 0000 500 0 0000 900 7 0 0000 800 0 0000 0005 0 0007 0005 0 0008 0005 0 0000 0009 0 0000 1009 0 0000 0205 0 OYSWIL i dnyoeq O14 06 Pssst ____ _ 18 ___ _ 17 NYO 91 ENO ___ __ 1 sjesoudued 0 9 gsn pasn JOU p 5 1 0000 0000 0 any ysel diyd Uo gJ 962 0000 7
9. The board must not be subject to high electrostatic potentials General practice for working with static sensitive devices should be applied when working with this board BOARD USE REQUIREMENTS Cables The cable you will need depends on the programmer debugger you use If you use ARM JTAG EW you will need USB A B cable If you use a software programmer such as FlashMagic you will need RS232 cable Hardware Programmer Debugger ARM JTAG EW or other compatible programming debugging tool if you work with EW ARM You can use also ARM USB OCD ARM USB TINY ARM USB TINY H with CrossWorks or OpenOCD PROCESSOR FEATURES LPC1766 STK board use ARM 32 bit Cortex M3 microcontroller LPC1766FBD100 from NXP Semiconductors with these features ARM Cortex M3 processor running at frequencies of up to 100 MHz A Memory Protection Unit MPU supporting eight regions is included ARM Cortex M3 built in Nested Vectored Interrupt Controller NVIC 256 kB on chip flash programming memory Enhanced flash memory accelerator enables high speed 100 MHz operation with zero wait states In System Programming ISP and In Application Programming via on chip bootloader software On chip SRAM includes 32 of SRAM on CPU with local code data bus for high performance CPU access Two 16 kB SRAM blocks with separate access paths for higher throughput These SRAM blocks may be used for Ethernet
10. a a I 1 fal Al Hir 4 ty i USB DEV wi aE _ 14 1 4 A gt J aa mM a 1 766 8 2088 1 lt a 1 f lt 1 i Py 6232 0 E Headphones LCD a 1 S i POWER SUPPLY CIRCUIT LPC1766 STK is typically power supplied with 9 VDC The programmed board power consumption is about 200 mA with all peripherials enabled Page 9 RESET CIRCUIT LPC1766 STK reset circuit includes jumper RST_E pin 15 of JTAG connector pin 10 of TRACE connector and RESET button CLOCK CIRCUIT Quartz crystal 12 MHz is connected to LPC1766 pin 22 XTAL1 and pin 23 XTAL2 Quartz crystal 32 768 kHz is connected to LPC1766 pin 16 1 and pin 18 2 JUMPER DESCRIPTION CAN Disable If this jumper is closed is disabled Default state is open
11. amount of time if it enters an erroneous state System tick timer including an external clock input option Page 4 Repetitive interrupt timer provides programmable repeating timed interrupts Each peripheral has its own clock divider for further power savings Standard JTAG test debug interface for compatibility with existing tools Serial Wire Debug and Serial Wire Trace Port options Emulation trace module enables non intrusive high speed real time tracing of instruction execution Integrated PMU Power Management Unit automatically adjusts internal regulators to minimize power consumption during Sleep Deep sleep Power down and Deep power down modes Four reduced power modes Sleep Deep sleep Power down and Deep power down Single 3 3 V power supply 2 4 V to 3 6 Four external interrupt inputs configurable as edge level sensitive All pins on PORTO and PORT2 can be used as edge sensitive interrupt sources Non maskable Interrupt NMI input Clock output function that can reflect the main oscillator clock IRC clock RTC clock CPU clock and the USB clock The Wakeup Interrupt Controller WIC allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep Power down and Deep power down modes Processor wake up from Power down mode via interrupts from various peripherals Brownout detect with separate threshold for inter
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13. CAN_T This jumper assures correct work of the CAN At each end of the bus it should be US closed This means that if you have only two devices with CAN the jumpers of both devices should be closed If you have more than two devices only the two end devices should be closed Default state is closed 3 3V VREG _E This jumper when closed supplies 3 3 voltage for on chip voltage regulator only 42 and 84 pins of the MCU Default state is closed 3 3V_E This jumper when closed enable main 3 3 regulator VR1 3 3V LM1117 Default state is closed 3 3VA_E This jumper when closed supplies 3 3 voltage to the and pins of MCU Default state is closed 3 This jumper when closed supplies 3 3 voltage to the VDD 4 pins of the MCU Default state is closed Page 10 This jumper when closed supplies analog 5V voltage supply to audio amplifiers Default state is closed AGND_E Default state is closed This jumper when closed connects analog GND to the GND of the MCU EXT_TEMP TH1 This jumper when is in position EXT_TEMP takes signal from external temperature when is in position TH1 takes signal from the thermistor TH1 of board Default state is in position TH1 DBG_E The position of this jumper doesn t matter De
14. 000 0 _ 0000 0001 0 21345 0008 0001 0 1 0000 3331 0 1004 8 0002 0 ek 91 5 8791 0000 002 9950 0007 0002 0 0007 8004 0 0000 600 0 0000 004 0 0000 0000 _ 0000 000 0000 800 7 0 0000 0107 0 0000 0000 x 0000 0004 0 0000 0104 0 444540 9 19d 962 0000 0000 0 0010 0000 0 99 241 _____ 08 _ 15 1 je ____ 168 _ 16 10 JO4 U09 sjejoudued 0000 8007 0 0008 8007 0 0002 800 0 0000 600 7 0 000 0008 600 7 0 0000 600 0 0000 00 0 0007 0008 0009 0000 00 0 0007 9007 0 0008 800 7 0 0000 0 0000 200 0 0002 00 0000 7
15. 39001 eo 10uF 6 3V RSTN RTCK TCK TRSTN TMS TDI TDO 00 32 1 7 FOME PIET 02 NISYIL9LY 001 19 84 wid 2 NISY 101 odl WoL T 9 7 979198 100 HSI 00 MMM 2 6002 2 1 lt 4 2 45 992 3960 zing 03 e zing 04 XLSZIZLNI 9 6 dN JAYM LINIJ 25 45 3 481 5 1 ESN Joanno 1H9IY 1H9IY 59 1341 1331 59 Wig 1 391 32 1 2 1032 LINDYIO 19534 20 35 5 3591 ERDEN 3 SL SNIV 020 lt SNAJA io gt SNIA 1219 YAO 8518 850 DAN 89 1 89 1037 1037 015 4 015 OW 005171 005171 HASN 9 HASN 01355 GER o 01358 59 0105 0905 8518 8818 851 zee 031 d 8SN olan 1 3 2 2043 wid 4 3 58 4
16. D_CONNECT LED with name USBC green connected to LPC1766 pin 64 P2 9 USB_CONNECT RXD2 through and R29 User button with name BUT1 connected to LPC1766 9 0 23 0 0 125 _ User button with name BUT2 connected to LPC1766 50 P2 13 EINT3 1I2STX_SDA User button with name WAKE UP connected to LPC1766 pin 51 P2 12 EINT2 12STX_WS User button with name RESET connected to LPC1766 pin 17 RESET Joystick button with name J1 this is 4 directions plus center button in the schematic the joystick four directions switches are connected through 33k resistors to LPC1766 pins 65 P2 8 TD2 TXD2 RIGHT 66 P2 7 RD2 RTS1 LEFT 74 P2 1 PWM1 2 RXD1 DOWN 75 P2 0 PWM1 1 TXD1 UP the center button is connected to pin 80 PO 5 I2SRX_WS TD2 CAP2 1 Trimpot with name AN_TRIM connected to LPC1766 pin 20 P1 31 SCK1 ADO 5 TFT LCD 128x128 12 bit color with backlight Page 12 EXTERNAL CONNECTORS DESCRIPTION 5232 0 Signal Name NC __ _ 5232 1 Signal GND 13 PWR JACK UXT TAG Signal Name Signal Name is spo oie 2 4 6 8 10 JTAG connector allows software debugger to talk JTAG Joint Test Action Group port directly to the core Instructions may be inserted and executed by the c
17. USB and DMA memory as well as for general purpose CPU instruction and data storage Eight channel General Purpose DMA controller GPDMA on the AHB multilayer matrix that be used with the SSP 125 UART the Analog to Digital and Digital to Analog converter peripherals timer match signals and for memory to memory transfers Multilayer AHB matrix interconnect provides a separate bus for each AHB master AHB masters include the CPU General Purpose DMA controller Ethernet MAC and the USB nterface This interconnect provides communication with no arbitration delays Page 3 Split APB bus allows high throughput with few stalls between CPU and DMA Serial interfaces Ethernet MAC with RMII interface and dedicated DMA controller USB 2 0 full speed device controller with dedicated DMA controller and on chip PHY for device Host and OTG functions Four UARTs with fractional baud rate generation internal FIFO DMA support and RS 485 support One UART has modem control I O and one UART has IrDA support CAN 2 0B controller with two channels SPI controller with synchronous serial full duplex communication and programmable data length Two SSP controllers with FIFO and multi protocol capabilities The SSP interfaces can be used with the GPDMA controller Two 12 interfaces supporting fast mode with a data rate of 400 kbits s with multiple address recognition and m
18. ansfers data between the endpoint buffer and the on chip SRAM Page 18 USB Signal USB is a supplement to USB 2 0 specification that augments capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals The OTG Controller integrates the host controller device controller and a master only 2 bus interface to implement dual role device functionality The dedicated 12 interface controls an external OTG transceiver BAT Page 19 Signal 142 Signal Pull up SSEL1 MOSI1 VDD power supply GND Page 20 MECHANICAL DIMENSIONS 4 000 3 870 7 979282 75 rat hans 9 S 20 a 5555555 95555595 86559 65559 E an 2 Ege 0 HH 2 g 55 at 00 0 6 aD H gt 9 gt gt m J Hiogo 8444 nan na g aD 58 250 200000 10 0000 palp a JE T TAT kag 0 130 0 000
19. fault state is closed RST_E This jumper when closed enables programing via 5232 state is open ISP_E aS This jumper when closed enables programing via 5232 Default state is open 2 This jumper when is in position enables interrupt request from the accelerometer and when is in position LED2 enables LED2 Default state is LED2 USB_D This jumper when1 2 are shorted enables USB DEVICE when 3 4 are shorted enables USB HOST and when 5 6 are shorted enables USB OTG Default state is 1 2 Page 11 USB_D This jumper when1 2 are shorted enables USB DEVICE when 3 4 shorted enables USB HOST and when 5 6 are shorted enables USB OTG Default state is 1 2 PWR_SEL When 1 2 are shorted the board is supplied from PWR_JACK when 3 4 are shorted the board is supplied from JTAG and when 5 6 are shorted the board is supplied from USB_DEV Default state is 1 2 INPUT OUTPUT red connected to LPC1766 pin 39 1 25 1 LED2 red connected to LPC1766 81 PO 4 I2SRX_CLK RD2 CAP2 0 via jumper 2 when this jumper is in position LED2 SD MMC LED red connected to SD MMC pin 4 VDD Power on LED red with name PWR this LED shows that 3 3V is applied to the board USB_UP_LED with name USB_LINK yellow connected to LPC1766 pin 32 P1 18 USB_UP_LED PWM1 1 CAP1 0 USB
20. m dev for more info Revision history Revision Initial October 2009 Page 23 Disclaimer 2009 Olimex Ltd All rights reserved Olimex logo and combinations thereof are registered trademarks of Olimex Ltd Other terms and product names may be trademarks of others The information in this document is provided in connection with Olimex products No license express or implied or otherwise to any intellectual property right is granted by this document or in connection with the sale of Olimex products Neither the whole nor any part of the information contained in or the product described in this document may be adapted or reproduced in any material from except with the prior written permission of the copyright holder The product described in this document is subject to continuous development and improvements All particulars of the product and its use contained in this document are given by OLIMEX in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product OLIMEX Ltd shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use of the product Page 24
21. onitor mode One 2 interface supporting full I2C bus specification and fast mode plus with a data rate of 1 Mbit s with multiple address recognition and monitor mode 125 Inter IC Sound interface for digital audio input or output with fractional rate control The 125 interface can be used with the The 125 interface supports 3 wire 4 wire data transmit and receive as well as master clock input output Other peripherals 70 General Purpose I O GPIO pins with configurable pull up down resistors and a new configurable open drain operating mode 12 bit Analog to Digital Converter ADC with input multiplexing among eight pins conversion rates up to 1 MHz and multiple result registers The 12 bit ADC can be used with the GPDMA controller 10 bit Digital to Analog Converter DAC with dedicated conversion timer and DMA support Four general purpose timers counters with a total of eight capture inputs and ten compare outputs Each timer block has an external count input and DMA support One motor control PWM with support for three phase motor control Quadrature encoder interface that can monitor one external quadrature encoder One standard PWM timer block with external count input RTC with a separate power domain and dedicated RTC oscillator The RTC block includes 64 bytes of battery powered backup registers Watchdog Timer WDT resets the microcontroller within a reasonable
22. ore thus allowing LPC1766 memory to be programmed with code and executed step by step by the host software For more details refer to IEEE Standard 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture and LPC1766 datasheets and users manual Page 14 2 4 6 8 10 12 14 16 18 20 1 3 5 7 9 11 AS 15 17 49 LAN 1234567 8 45 SIDE OONW Page 15 Signal Chip Side Name Chip Side Pin Signal Name Chip Side Name Chip Side TPOUT Not Connected TPOUT 6 Not Connected NC CAN Pin Signal Description 1 GND Ground 2 CANL CAN LOW 3 CANH CAN HIGH TRACE Pin Signal Description Pin Signal Description 1 VCC 3 3V 2 TMS 3 GND 4 5 GND 6 7 8 TDI 9 GND 10 RSTN 11 GND 12 13 GND 14 Depends 150 157 15 GND 16 TRACE 1 Depends 153 161 17 GND 18 02 19 GND 20 16 95598088987 EAEE 3 gt _ 5 6505 4 sp ACC_IRQ LED2_ 2560 5 1 2 5 _ 5 6 59 LITHIUM BATTERY LPC1766 STK 2003
23. rupt and forced reset Power On Reset POR Crystal oscillator with an operating range of 1 MHz to 25 MHz 4 MHz internal RC oscillator trimmed to 1 accuracy that can optionally be used as a system clock PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal May be run from the main oscillator the internal RC oscillator or the RTC oscillator USB PLL for added flexibility Code Read Protection CRP with different security levels Page 5 debug JTAG XTAL1 port interface RMII pins USB pins XTAL2 TEST DEBUG USB PHY INTERFACE GENERATION POWER CONTROL SYSTEM FUNCTIONS USB HOST DEVICE OTG CONTROLLER ETHERNET DMA CONTROLLER CONTROLLER EMULATION TRACE MODULE WITH DMA ARM 6 D code system master master bus bus bus WITH DMA clocks and controls MULTILAYER AHB MATRIX PO to HIGH SPEED P4 lies AHB TO AHB TO APB APB BRIDGE 0 BRIDGE 1 SCK1 APB slave group 0 APB slave group 1 SSEL1 55 0 5 5 1 MOSI1 RXDO TXDO 2 3 8 x UART1 25 RD1 2 TD1 2 C SCLO 1 12 0 1 SCK SSEL oe C 202 MOSI MISO TIMER 0 1 RITIMER 2 gt EXTERNAL INTERRUPTS EXTERNAL INTERRUPTS 1 1 0 PWM1 R 0017 0 12 bit ADC SYSTEM CONTROL PIN CONNECT gt
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