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R5F100AEASP#V0 - Renesas Electronics

1. 0 51 detail of lead end R5F100LJGFA JEITA Package Code RENESAS Code P LQFP64 12x12 0 65 PLQPO0064JA A HD D 33 48 32 49 C 17 64 Each lead centerline is located within 0 13 mm of its true position at maximum material condition UNIT mm ITEM DIMENSIONS D 12 00 0 20 12 00 0 20 HD 14 00 0 20 14 00 0 20 1 60 1 0 10 0 05 2 1 40 0 05 0 25 b 0 32 0 08 0 07 0 055 0 145 70 099 0 50 0 60 0 15 1 00 0 20 5 3 0 65 0 13 0 10 1 125 1 125 2012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev 3 10 Nov 15 2013 RENESAS Page 187 of 194 RL78 G13 4 PACKAGE DRAWINGS R5F100LCAFB R5F100LDAFB R5F100LEAFB R5F100LFAFB R5F100LGAFB R5F100LHAFB R5F100LJAFB R5F100LKAFB R5F100LLAFB R5F101LCAFB R5F101LDAFB R5F101LEAFB R5F101LFAFB R5F101LGAFB R5F101LHAFB R5F101LJAFB R5F101LKA
2. SERIAL ARRAY CONTROL UNITO 4ch RAM DETECTOR RxDO P11 TxDO P12 x RESET CONTROL RxD1 P01 TxD1 P00 SCK00 P10 Voo Vss TOOLRxD P11 lt ON CHIP DEBUG TOOLO P40 ay TOOLTxD P12 SO00 P12 SYSTEM SCK11 P30 CONTROL RESET 5111 50 SERIAL SDAAO P61 HIGH SPEED X1 P121 011 17 INTERFACE IICAO SCLAO P60 ON CHIP SCLOO P10 OSCILLATOR X2 EXCLK P122 SDAOO P11 eh BUZZER OUTPUT VOLTAGE PCLBUZO P31 CONTROL DIRECT MEMORY ACCESS CONTROL MULTIPLIER amp CRC 137 DIVIDER c MULITIPLY INTERRUPT INTP1 P50 ACCUMULATOR NTROL INTP3 P30 ADJUSTMENT 2 INTP4 P31 INTP5 P16 R01DS0131EJ0310 Rev 3 10 aQ NECES AS Page 36 of 194 Nov 15 2013 RL78 G13 1 OUTLINE 1 5 4 30 pin products TI00 P00 TO00 P01 TI01 TO01 P16 TI02 TO02 P17 TI02 TO02 P15 TI03 TO03 P31 T103 TOO3 P 14 TI04 TOO4 P13 T105 TOOS P 12 TIO6 TOO6 P1 1 107 007 10 RxD2 P14 LOW SPEED ON CHIP OSCILLATOR RxDO0 P11 RxDO P16 TxDO0 P12 TxDO P17 RxD1 P01 TxD1 P00 SCKO00 P10 100 11 000 12 SCK11 P30 SH 1 P50 SO11 P51 SCLOO P10 SDAOO P11 SCL11 P30 SDA11 P50 RxD2 P14 TxD2 P13 SCK20 P15 SI20 P14 SO20 P13 SCL20 P15 SDA20 P14 TIMER ARRAY UNIT 8ch WINDOW WATCHDOG lt TIMER 12 BIT INTERVAL pu REAL TIME CLOCK SERIAL ARRAY UNITO 4ch SERIAL ARRAY UNIT1 2ch CODE FLASH MEMORY DATA FLASH MEMORY
3. Voo Vss SERIAL INTERFACE IICAO BUZZER OUTPUT CLOCK OUTPUT CONTROL MULTIPLIER amp DIVIDER MULITIPLY ACCUMULATOR DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT TOOLRxD P11 TOOLTxD P12 SDAAO P61 SDAAO P13 SCLAO P60 SCLAO P14 PCLBUZO P31 PCLBUZ1 P15 CRC roro K gt P01 lt roi cm P10 to P17 lt ro k P20 to P23 lt rors P30 P31 S NINE lt Porte KZ Peo Pet PORT 12 10 2 121 P122 PORT 13 P137 eme ANIO P20 to ANI3 P23 ANI16 P01 ANI17 POO ANI18 P147 ANI19 P120 AVnere P20 AVnerw P21 POWER ON RESET coni yp VOLTAGE CONTROL DETECTOR RESET CONTROL A D CONVERTER ON CHIP DEBUG TOOLO P40 SYSTEM CONTROL RESET HIGH SPEED X1 P121 ON CHIP X2 EXCLK P122 VOLTAGE REGULATOR REG RxD2 P14 INTPO P137 INTP1 P50 2 JINTP2 P51 gt INTPS P30 KJ iNTPA PSI 5 16 INTERRUPT CONTROL Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral redirection register PIOR PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 Nov 15 2013 RENESAS Refer to Figure 4 8 Format of Peripheral I O Redirection Register Page 37 of 194 RL78 G13 1 OUTLINE 1 5 5 32 pin products T100 P00 TO00 P01 TI01 TO01 P16 Tlo2 TOO2 P17 TIO2 T
4. CiH u z Z DX lt mo Tm o o m 2012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev 3 10 QE NE S AS Page 179 of 194 Nov 15 2013 RL78 G13 4 PACKAGE DRAWINGS 4 5 32 pin Products R5F100BAANA R5F100BCANA R5F100BDANA R5F100BEANA R5F100BFANA R5F100BGANA R5F101BAANA R5F101BCANA R5F101BDANA R5F101BEANA R5F101BFANA R5F101BGANA R5F100BADNA R5F100BCDNA R5F100BDDNA R5F100BEDNA R5F100BFDNA R5F100BGDNA R5F101BADNA R5F101BCDNA R5F101BDDNA R5F101BEDNA R5F101BFDNA R5F101BGDNA R5F100BAGNA R5F100BCGNA R5F100BDGNA R5F100BEGNA R5F100BFGNA R5F100BGGNA JEITA Package Code RENESAS Code Previous Code MASS g P HWQFN32 5x5 0 50 PWQN0032KB A P32K8 50 3B4 3 0 06 DETAIL OF A PART UNIT mm ITEM DIMENSIONS D 5 00 0 05 E 5 00 0 05 A 0 75 0 05 EXPOSED DIE PAD TU UE b 0 25 907 e 0 50 Lp 0 40 0 10 x 0 05 y 0 05 ITEM Da E2 MIN NOM MAX MIN NOM MAX EXPOSED DIE PAD 3 45 3 50 3 55 3 453 50 3 55 VARIATIONS 2012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 180 of 194 Nov 15 2013 RL78 G13 4 PACKAGE DRAWINGS 4 6 36 pin Products R5F100CAALA R5F100CCALA R5F100CDALA R5
5. TOOLRxD TOOLTxD mode TOOLO A tsu 1 i T lt gt lt gt lt 3 gt lt 4 gt f 1 723 us to 1 processing 00H reception gt tsuinit a seus 1 The low level is input to the TOOLO pin 2 The external reset is released POR and LVD reset must be released before the external reset is released 3 The TOOLO pin is set to the high level 4 Setting of the flash memory programming mode by UART reception and complete the baud rate setting Remark tsuinit Communication for the initial setting must be completed within 100 ms after the external reset is released during this period ts Time to release the external reset after the TOOLO pin is set to the low level tHo Time to hold the pin at the low level after the external reset is released excluding the processing time of the firmware to control the flash memory R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 175 of 194 Nov 15 2013 RL78 G13 4 PACKAGE DRAWINGS 4 PACKAGE DRAWINGS 4 1 20 pin Products R5F1006AASP R5F1006CASP R5F1006DASP R5F1006EASP R5F1016AASP R5F1016CASP R5F1016DASP R5F1016EASP R5F1006ADSP R5F1006CDSP R5F1006DDSP R5F1006EDSP R5F1016ADSP R5F1016CDSP R5F1016DDSP R5F1016EDSP R5F1006AGSP R5F1006CGSP R5F1006DGSP R5F1006EGSP JEITA Package Code RENESAS Code Previous Code MASS TYP g P LSSOP20 03
6. 10 000 Notes 1 1 erase 1 write after the erase is regarded as 1 rewrite The retaining years are until next rewrite after the rewrite 2 When using flash memory programmer and Renesas Electronics self programming library 3 These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation 3 9 Dedicated Flash Memory Programmer Communication UART Ta 40 to 105 C 2 4 V lt EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V R01DS0131EJ0310 Rev 3 10 QE NC S AS Nov 15 2013 Page 174 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 3 10 Timing Specs for Switching Flash Memory Programming Modes Ta 40 to 105 C 2 4 V lt EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions Time to complete the tsuiNiIT POR and LVD reset must be released before communication for the initial the external reset is released setting after the external reset is released Time to release the external reset POR and LVD reset must be released before after the TOOLO pin is set to the the external reset is released low level Time to hold the TOOLO pin at the POR and LVD reset must be released before low level after the external reset is the external reset is released released excluding the processing time of the firmware to control the flash memory
7. Address space 1 MB Main system High speed system X1 crystal ceramic oscillation external main system clock input EXCLK clock clock 1 to 20 MHz 2 7 to 5 5 V 1 to 8 MHz Voo 1 8 to 2 7 V 1 to 4 MHz Von 1 6 to 1 8 V High speed on chip HS High speed main mode 1 to 32 MHz 2 7 to 5 5 V oscillator HS High speed main mode 1 to 16 MHz 2 4 to 5 5 V LS Low speed main mode 1 to 8 MHz 1 8 to 5 5 V LV Low voltage main mode 1 to 4 MHz Voo 1 6 to 5 5 V Subsystem clock Low speed on chip oscillator 15 kHz TYP General purpose registers 8 bit register x 8 x 4 banks Minimum instruction execution time 0 03125 us High speed on chip oscillator 32 MHz operation 0 05 us High speed system clock fmx 20 MHz operation Instruction set Data transfer 8 16 bits Adder and subtractor logical operation 8 16 bits Multiplication 8 bits x 8 bits Rotate barrel shift and bit manipulation Set reset test and Boolean operation etc I O port Total 16 20 21 26 28 32 CMOS I O 13 15 15 21 22 26 N ch O D N ch O D N ch O D N ch O D N ch O D N ch O D Voo withstand Voo VoD VoD Voo voltage 5 withstand withstand withstand withstand withstand voltage 6 voltage 6 voltage 9 voltage 9 voltage 10 CMOS input 3 3 3 3 3 CMOS output _ _ 1 _ _ N ch O D I
8. RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Tcv vs LS low speed main mode 10 3 10 g When the high speed on chip oscillator clock is selected During self programming v When high speed system clock is selected 0 125 F F 1 1 0 01 0 10 20 30 40 5 0 5 5 6 0 1 8 Supply voltage Vo V Tcv vs Vpp LV low voltage main mode 10 a 1 0 R When the high speed on chip oscillator clock is selected E During self programming When high speed system clock is selected gt 0 25 0 1 0 01 E 5 0 5 5 6 0 0 1 0 20 3 0 4 0 1 61 8 Supply voltage Vo V R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 79 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C AC Timing Test Points V H VoH V H VoH T hes est points V u VoL External System Clock Timing 1 fex 1 fexs EXCLK EXCLKS TI TO Timing tri m TIOO to TIO7 TI10 to TI17 1 fro TOO0 to TOO7 TO10 to TO17 Interrupt Request Input Timing INTL tiNTH INTPO to INTP11 Key Interrupt Input Timing mi tkR KRO to KR7 RSL RESET R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 80 of 194 Nov 15 2013 RESET Input Timing RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 2 5 Peripheral Functions Characteristics AC T
9. fsus 32 768 kHz 5 105 Square wave input Resonator connection 40 25 50 70 85 105 Notes and Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS SIS SISS Page 138 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Notes 1 Total current flowing into EVopo and EVpo1 including the input leakage current flowing when the level of the input pin is fixed Vop EVppo and EVpp1 or Vss EVsso and 1 The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instruction execution by flash memory When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When RTCLPC 1 and setting ultra low current consumption AMPHS1 1 The current flowing into the RTC is included However not including the current flowing into the 12 bit interval timer and watchdog timer 6 Not including the current flowing into the RTC 12 bit interval timer an
10. 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V fuck 12 Notes 1 2 Theoretical value of the maximum transfer rate fork 32 MHz fuck folk Notes 1 Transfer rate in the SNOOZE mode is 4800 bps only 2 The following conditions are required for low voltage interface when Evppo lt Vpp 2 4 V EVppo 2 7 V MAX 1 3 Mbps 2 6 Caution Select the TTL input buffer for the RxDq and the N ch open drain output tolerance When 20 to 52 pin products EVpo tolerance When 64 to 100 pin products mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vi see the DC characteristics with TTL input buffer selected Remarks 1 2 3 Communication line voltage q UART number q 0 to 3 g PIM and POM number g 0 1 8 14 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 UART2 cannot communicate at different potential when bit 1 PIOR1 of peripheral I O redirection register PIOR is 1 R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 151 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 5 Communication at different potential 1 8 V 2 5 V 3 V UART mode 2 2 Ta 40 to 105 C 2 4 V lt EVppo EVpni lt
11. Communication line SCKp SOp load capacitance Ve V Communication line voltage 2 p CSI number p 00 m Unit number m 0 n Channel number n 0 g PIM and POM number g 1 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 4 This value is valid only when CSIOO s peripheral redirect function is not used R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 96 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 1 3 Ta 40 to 85 C 1 8 V lt EVppo EVpni lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX SCKp cycle 1 gt 4 4 0 V EVppo lt 5 5 V time 2 7 V Vo 4 0 V Co 30 pF Re 1 4 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V Co 30 pF Ro 2 7 kQ 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 Vs 30 pF 5 5 SCKp high level 4 0 V EVppo 5 5 V tkcvi 2 1 2 1 2 width 2 7 V lt Vo lt 4 0 V 75 75 75 Cb 30 pF Rb 1 4 KQ 2 7 V EVppo lt 4 0 V tkcvi 2 tkcvi 2
12. R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 190 of 194 Nov 15 2013 RL78 G13 4 PACKAGE DRAWINGS R5F100MFAFB R5F100MGAFB R5F100MHAFB R5F100MJAFB R5F100MKAFB R5F100MLAFB R5F101MFAFB R5F101MGAFB R5F101MHAFB R5F101MJAFB R5F101MKAFB R5F101MLAFB R5F100MFDFB R5F100MGDFB R5F100MHDFB R5F100MJDFB R5F100MKDFB R5F100MLDFB R5F101MFDFB R5F101MGDFB R5F101MHDFB R5F101MJDFB R5F101MKDFB R5F101MLDFB R5F100MFGFB R5F100MGGFB R5F100MHGFB R5F100MJGFB JEITA Package Code RENESAS Code Previous Code MASS TYP g P LFQFP80 12x12 0 50 PLQPOO080KE A P80GK 50 8EU 2 0 53 detail of lead end A3 1 Y 1 t L 0 gt L HE r Lp le L1 UNIT mm ITEM DIMENSIONS D 12 00 0 20 12 00 0 20 HD 14 00 0 20 HE 14 00 0 20 1 60 Y A1 0 10 0 05 A2 1 40 0 05 0 25 b 0 22 0 05 0 055 c 0 145 0 055 L I A 0 50 Lp 0 60 0 15 A24 L1 1 00 0 20 tt EE Jd 4 I i i x 0 08 y 0 08 eO y S A1 ZD 125 ZE 1 25 NOTE Each lead centerline is located within 0 08 mm of its true position at maximum material condition 92012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev
13. 1 2 2 3 V lt Vo lt 2 7 V 170 170 170 C 30 pF Pb 2 7 1 8 V lt EVppo lt 3 3 V tkcvi 2 tkcvi 2 tkcvi 2 1 6 V lt Ve lt 2 0 V Ne 458 458 458 C 30 pF Ro 5 5 SCKp low level 4 0 V EVppo 5 5 V tkcvi 2 tkcvi 2 1 2 width 2 7 V lt Vo lt 4 0 V 12 50 50 Cb 30 pF Rb 1 4 kQ 2 7 V EVppo lt 4 0 V tkcvi 2 tkcvi 2 tkcvi 2 2 3 V lt Vo lt 2 7 V 18 50 50 Co 30 pF Rb 2 7 1 8 V lt EVoppo lt 3 3 V tkcvi 2 tkcvi 2 1 2 1 6 V lt Vo lt 2 0 V 50 50 50 C 30 pF Rb 5 5 Note Use it with EVppo gt Vb Caution Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks are listed two pages after the next page R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 97 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 2 3 Ta 40 to 85 C 1 8 V lt EVppo 1 lt
14. 3 5 Peripheral Functions Characteristics AC Timing Test Points Test points Vi VoL a Vi VoL 3 5 1 Serial array unit 1 During communication at same potential UART mode Ta 40 to 105 C 2 4 V lt EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main Mode MIN MAX Note 1 Note 2 Mid 1 2 O Transfer rate Theoretical value of the 2 6 maximum transfer rate fork 32 MHz fuck folk Notes 1 Transfer rate in the SNOOZE mode is 4800 bps only 2 The following conditions are required for low voltage interface when Evppo lt Vpp 2 4 V EVppo lt 2 7 V MAX 1 3 Mbps Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg UART mode connection diagram during communication at same potential TxDq RL78 microcontroller User device RxDq UART mode bit width during communication at same potential reference 1 Transfer rate High Low bit width Baud rate error tolerance TxDq RxDq Remarks 1 UART number q 0 to 3 g PIM and POM number g 0 1 8 14 2 Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn
15. Falling interrupt voltage 3 6 5 Power supply voltage rising slope characteristics Ta 40 to 105 C Vss 0 V Pese e L vine Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until Voo reaches the operating voltage range shown in 3 4 AC Characteristics R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 173 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 3 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Ta 40 to 105 C Vss 0 V Note The value depends on the POR detection voltage When the voltage drops the data is retained before a POR reset is effected but data is not retained when a POR reset is effected 1 STOP mode I Data retention mode gt 4 STOP instruction execution Operation mode Standby release signal interrupt request 3 8 Flash Memory Programming Characteristics Ta 40 to 105 C 2 4 V lt lt 5 5 V Vss 0 V Parameter Conditions CPU peripheral hardware clock 2 4 V lt Vpp lt 5 5 V frequency Number of code flash rewrites Retained for 20 years TA 85 Notes 1 2 3 Number of data flash rewrites Retained for 1 years TA 25 1 000 000 Notes 1 2 3 Retained for 5 years TA 85 100 000 Retained for 20 years TA 85
16. 2012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev 3 10 QE NE S AS Page 188 of 194 Nov 15 2013 RL78 G13 4 PACKAGE DRAWINGS R5F100LCABG R5F100LDABG R5F100LEABG R5F100LFABG R5F100LGABG R5F100LHABG R5F100LJABG R5F101LCABG X R5F101LDABG R5F101LEABG R5F101LFABG R5F101LGABG R5F101LHABG R5F101LJABG R5F100LCDBG R5F100LDDBG R5F100LEDBG R5F100LFDBG R5F100LGDBG R5F100LHDBG R5F100LJDBG R5F101LCDBG R5F101LDDBG R5F101LEDBG R5F101LFDBG R5F101LGDBG R5F101LHDBG R5F101LJDBG JEITA Package Code RENESAS Code Previous Code MASS g P VFBGA64 4x4 0 40 PVBGOO64LA A P64F1 40 AA2 2 0 03 D w mu OO OOO 8 7 QOOOIO 6 OOOO O 5 OOOOO 4 OOOOO 3 OOOOO 2 OOOOO 1 Y HGFEDCBA INDEX MARK IO w SB INDEX MARK A Lo ITEM DIMENSIONS D 4 00 0 10 yi S 2 4 00 0 10 w 0 15 A 0 89 0 10 S A1 0 20 0 05 7 1 i A2 0 69 ry L ry e 0 40 y JS BB e A1 b 0 25 0 05 x 0 05 96 ox S A B y 0 08 yl 0 20 7 0 60 ZE 0 60 2012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev 3 10 24 NE S AS Page 189 of 194 Nov 15 2013 RL
17. When duty lt 70 3 Total of P05 P10 to P17 P30 P31 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 P101 P110 to P117 P146 P147 When duty lt 70 3 Total of all pins 150 0 When duty lt 70 3 Per pin for P20 to P27 P150 to P156 0 4 Note 2 5 0 Total of all pins 1 6 V lt lt 5 5 V When duty lt 70 3 Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVsso EVss1 and Vss pin However do not exceed the total current value Specification under conditions where the duty factor lt 70 The output current value that has changed to the duty factor gt 70 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n e Total output current of pins lot x 0 7 n x 0 01 Example Where 80 and lo 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA However the current that is allowed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 59 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta
18. 10 Communication at different potential 1 8 V 2 5 V 3 V simplified mode 1 2 Ta 40 to 85 C 1 8 V lt EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V SCLr clock frequency 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Conditions 4 0 V EVppo lt 5 5 V 2 7 V lt Vo 4 0 V 50 pF Rb 2 7 HS high speed main Mode MIN MAX LS low speed main Mode MIN MAX LV low voltage main Mode MIN MAX 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V Co 50 pF Rb 2 7 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V 100 pF Rb 2 8 KQ 2 7 V lt lt 4 0 V 2 3 V lt Vo 2 7 V Cb 100 pF Rb 2 7 kQ 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V 2 Co 100 pF Rb 5 5 Hold time when SCLr L 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V 50 pF Rb 2 7 KQ 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V 50 pF Rb 2 7 KQ 4 0 V EVppo lt 5 5 V 2 7 V lt Vo 4 0 V 100 pF Rb 2 8 KQ 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V 100 pF Rb 2 7 KQ 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 Vote Co 100 pF Rb 5 5 Hold time when SCLr H R01DS0131EJ0310 Rev 3 10 Nov 15 2013 4 0 V lt EVpoo lt 5 5 V 2 7
19. 2 2 14 tkcy2 2 16 2 4 V lt lt 5 5 V tkcy2 2 36 Slp setup time to SCKpT e 2 7 V lt EVppo 5 5 V 1 fuck 40 2 4 V lt EVppo 5 5 V 1 fuck 60 2 4 V lt EVppo 5 5 V 1 fuck 62 Slp hold time from SCKpT 2 Delay time from C 30 pF 4 2 7 V lt EVopo 5 5 2 fuick 66 SCKpJ to SOp output V NS 24 V lt EVo lt 5 5 V 2 fuck 1 13 Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The 51 setup time becomes to SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The 51 hold time becomes from SCKpl when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpT when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 4 C is the load capacitance of the SOp output lines 5 Transfer rate in the SNOOZE mode MAX 1 Mbps Caution Select the normal input buffer for the Slp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g PIMg and port output mode register g POMg Remarks 1 p CSI number p 00 01 10 11 20 21 30 31 m Unit number m 0 1 n Channel number n 0 to 3 g PIM number g 0 1 4 5 8 14 2 fuck Serial array unit operation clock frequency Operati
20. 25 116 SCK01 P43 ANI26 P115 lt ronn Kaypuocopu SI01 P44 AVreFe P20 SO01 P45 AVneru P21 FORTI kK P120 P125 to P127 SCK10 P04 SCK10 P80 P121 to P124 SDAOO P11 SCLO1 P43 SDAO1 P44 SCL10 PO4 SCL10 P80 SDA10 P03 SDA10 P81 SCL11 P95 SDA11 P96 RxD2 P14 RxD2 P76 SERIAL ARRAY UNIT1 4ch UART2 TxD2 P13 TxD2 P77 RxD3 P143 TxD3 P144 SCK20 P15 SI20 P14 SO20 P13 SCK21 P70 SI21 P71 1 021 72 SCK30 P142 SI30 P143 030 144 SCK31 P54 131 5 031 52 SCL20 P15 SDA20 P14 SCL21 P70 SDA21 P71 SCL30 P142 SDA30 P143 1 SCL31 P54 SDA31 P53 UART3 5120 CSI21 CSI31 IIC20 IIC21 IIC30 IIC31 RAM Voo Vss TOOLRxD P11 EVppo EVsso TOOLTxD P12 EVss1 SDAAO P61 SDAAO P13 SERIAL INTERFACE IICAO SCLAO Pe0 SCLAO P14 SERIAL SDAA1 P63 INTERFACE IICA1 SCLA1 P62 BUZZER OUTPUT PCLBUZO P140 Cay POLBUZOIPS PCLBUZ1 P141 CLOCK OUTPUT PCLBUZ1 P55 CONTROL MULTIPLIER amp DIVIDER MULITIPLY ACCUMULATOR DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT WINDOW WATCHDOG TIMER LOW SPEED 12 BIT INTERVAL e ON CHIP TIMER OSCILLATOR REALTIME RTC1HZ P30 CLOCK KEY RETURN 8 POWER ON RESET VOLTAGE DETECTOR RESET CONTROL ON CHIP DEBUG SYSTEM CONTROL HIGH SPE
21. L 2 7 V EVppo lt 5 5 V 50 pF Rb 2 7 1200 2 4 V lt EVpoo lt 5 5 V C 100 pF Ro 3 4600 Hold time when SCLr H 2 7 V EVppo 5 5 V 50 pF Rb 2 7 KQ 1200 2 4 V lt EVpoo lt 5 5 V Cb 100 pF Ro 3 4600 Data setup time reception 2 7 V lt EVobo lt 5 5 V Co 50 pF Ro 2 7 1 220 Note2 2 4 V lt EVpoo lt 5 5 V C 100 pF Ro 3 1 580 Note2 Data hold time transmission tHD DAT 2 7 V lt EVobo lt 5 5 V Cb 50 pF Ro 2 7 0 2 4 V EVpoo lt 5 5 V Co 100 pF Ro KQ Notes 1 The value must also be equal to or less than fuck 4 2 Set the fuck value to keep the hold time of SCLr L and SCLr Caution Select the normal input buffer and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SDAr the normal output mode for the SCLr pin by using port input mode register g PIMg and port output mode register h POMh Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NE SAS Page 149 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Simplified mode mode connection diagram during communication at same potential Vpp SDAr SDA RL78 microcon
22. Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fiH High speed on chip oscillator clock frequency 3 fsus Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation temperature condition of the value is TA 25 R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 68 of 194 Nov 15 2013 RL78 G13 2 Flash ROM 96 to 256 KB of 30 to 100 pin products 40 to 85 C 1 6 V lt EVppo 1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 2 2 Parameter Supply current Note 1 Note 2 mode HS high 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Conditions 32 MHz wae Von 3 0 V 0 62 186 mA 24 MHz Voo 5 0 V 0 50 1 45 mA Voo 3 0 V 0 50 145 mA fiu 16 MHz Note 4 Voo 5 0 V 0 44 1 11 mA Voo 3 0 V 044 1 11 mA LS low fin 8 MHz Voo 3 0 V I MED Voo 2 0 V LV low fin 4 MHz Voo 3 0 V 440 680 uA E Von 2 0 V 440 680 A Note 7 HS high fmx 20 MHz Square wave input 0 31 1 08 mA speed main Von 5 0 V Resonator 048 128 mA mode connection fux 20 2 3 Square wave input 0 31 1 08 mA Vpp 3 0 V Resonator 0 48 1 28 mA connection fux 10 MHz 3 Square wave input Voo 5 0 V Reso
23. and Vit see the DC characteristics with TTL input buffer selected Remarks 1 Re O Communication line SDAr SCLr pull up resistance Ce F Communication line SDAr SCLr load capacitance Ve V Communication line voltage 2 r IIC number r 00 01 10 20 30 31 g PIM POM number g 0 1 4 5 8 14 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 01 02 10 12 13 R01DS0131EJ0310 Rev 3 10 RENESAS Page 165 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 3 5 2 Serial interface IICA Ta 40 to 105 C 2 4 V lt EVppo EVpni lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main Mode Standard Fast Mode Mode MAX MAX SCLAO clock frequency Fast mode fcuk gt 3 5 MHz Standard mode gt 1 MHz Setup time of restart condition tsu sTA Hold time tHD STA Hold time when SCLAO L tLow Hold time when SCLAO H tHIGH Data setup time reception tsu DAT ote 2 Data hold time transmission tHD DAT Setup time of stop condition tsu sro Bus free time BUF Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MAX of is dur
24. lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main Mode Transfer rate Transmission 4 0 V EVppo lt 5 5 Note 1 Notes 1 MIN MAX V o Theoretical value of the 2 6 2 2 7V lt Ve lt 4 0V maximum transfer rate Co 50 pF Ro 1 4kQ Vo 27 V 2 7 V EVopo lt 4 0 V Theoretical value of the 2 3 V lt lt 2 7 V maximum transfer rate Co 50 pF Rb 2 7 Vo 2 3 V 2 4 V lt EV lt 3 3 V 1 6 V lt Vo lt 2 0 V Theoretical value of the maximum transfer rate Co 50 pF Rb 5 5 Vo 1 6 V The smaller maximum transfer rate derived by using 12 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 4 0 V x EVppo x 5 5 V and 2 7 V Vo lt 4 0 V Maximum transfer rate bps Cb x Rb x In 1 1 2 2 Transferratex 2 Co x Ro x In 1 Vo 1 Transfer rate Baud rate error theoretical value x 100 x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer The smaller maximum transfer rate derived by using 12 or the followi
25. 1 5 P20 to P27 P150 to P156 0 7Vpp P60 to P63 0 7EVppo P121 to P124 P137 EXCLK EXCLKS RESET 0 8Vpp Input voltage low P00 to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Normal input buffer 0 0 2EVppo P01 P03 P04 P10 P11 P13 to P17 P43 P44 P53 to P55 P80 P81 P142 P143 TTL input buffer 4 0 V lt EVppo lt 5 5 V TTL input buffer 3 3 V lt EVppo lt 4 0 V TTL input buffer 2 4 V lt EVppo lt 3 3 V P20 to P27 P150 to P156 P60 to P63 P121 to P124 P137 EXCLK EXCLKS RESET Caution The maximum value of Viu of pins POO P02 to P04 P10 to P15 P17 P43 to P45 P50 P52 to P55 P71 P74 P80 to P82 P96 and P142 to P144 is EVppo even in the N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins R01DS0131EJ0310 Rev 3 10 Nov 15 2013 ztENESAS Page 129 of 194 RL78 G13 Ta 40 to 105 C 2 4 V x EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V 4 5 Output voltage high 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Conditions POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120
26. 97 y lt Vpp lt 5 5 V ANI16 to ANI26 1 8 V lt VoD lt 5 5 V 1 6 V lt VoD lt 5 5 V Conversion time 10 bit resolution 3 6 V lt Vpp lt 5 5 V Target pin Internal 2 7 V lt Vpp lt 5 5 V reference voltage and temperature sensor output voltage HS high speed main mode 5 5 5 5 5 5 2 4 V lt lt 5 5 V Zero scale error gt 10 bit resolution DD lt 5 5 V DD lt 5 5 V Full scale 2 10 bit resolution DD lt 5 5 V DD lt 5 5 V Note 10 bit resolution DD lt 5 5 V DD lt 5 5 V Integral linearity error Differential linearity error 10 bit resolution DD lt 5 5 V 1 DD lt 5 5 V Analog input voltage ANI0 to ANI14 ANI16 to ANI26 Internal reference voltage Vear ote 4 2 4 V Vpp lt 5 5 V HS high speed main mode Temperature sensor output voltage Vrups s Note 4 2 4 V Vpp lt 5 5 V HS high speed main mode Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 When the conversion time is set to 57 ws min and 95 ws max 4 Refer to 2 6 2 Temperature sensor internal reference voltage characteristics R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 116 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 4 When reference voltage Intern
27. INTP2 P51 INTP3 P30 INTERRUPT INTP4 P31 NTROL CONTRO INTP5 P16 INTP6 P140 INTP8 P74 INTP9 P75 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware redirection register PIOR R01DS0131EJ0310 Rev 3 10 Nov 15 2013 RENESAS Page 42 of 194 RL78 G13 OUTLINE 1 5 10 52 pin products TIMER ARRAY PORT 0 P P um ZELUM roo TI00 P00 TO00 P01 dump PORT 1 KB P10toP17 TIO1 TOO1 P16 lt rw qu P20 to P27 TI02 TO02 P17 TI02 TO02 P15 lt PORT 3 K 2 gt P30 P31 TI03 TO03 P31 TI03 TO03 P14 em aree TI04 TO04 P13 lt PORT 5 2 gt P50 P51 TI05 TO05 P12 TI06 TOO6 P1 1 KO rows Km P60 to P63 TIO7 TOO7 P41 TI07 TOO7 P10 07 10 lt KB P70 to P77 RxD2 P76 P120 WINDOW PORT 12 WATCHDOG P121 to P124 TIMER PORT 13 P190 P4137 censa 12 BIT INTERVAL TIMER OSCILLATOR PORT 14 Ber Bus REAL TIME RTC1HZ P30 CLOCK ANIO P20 to 7 27 ANI16 P03 17 2 SERIAL ARRAY A D CONVERTER ANI18 P147 ANI19 P120 UNITO 4ch DATA FLASH MEMORY AVrerr P20 RxDO P11 RxDO P16 AVreru P21 TxDO P12 TxDO P17 RxD1 P03 KRO P70 to TxD1 PO2 KR7 P77 SCKO0 P10 SI00 P11 000 12 POR LVD SCK01 P75
28. Ltd 11F Samik Lavied or Bldg 720 2 Yeoksam Dong Kangnam Ku Seoul 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 2013 Renesas Electronics Corporation All rights reserved Colophon 2 2
29. Square wave input Resonator connection fsus 32 768 kHz Note 4 Ta 50 C Normal operation Square wave input Resonator connection 32 768 kHz Note 4 70 C Normal operation Square wave input Resonator connection 32 768 kHz Note 4 85 Notes and Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NE ESAS Normal operation Square wave input Resonator connection BS Page 63 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 Notes 1 Remarks Total current flowing into Vpp and EVppo including the input leakage current flowing when the level of the input pin is fixed to EVppo or Vss EVsso The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit port and on chip pull up pull down resistors and the current flowing during data flash rewrite When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When AMPHS 1 1 Ultra low power consumption oscillation However not including the current flowing into the RTC 12 bit interval timer and watchdog timer Rel
30. input Ta 40 to 85 C 1 8 V lt EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V 2 2 Parameter Conditions HS high LS low speed LV low voltage speed main main Mode main Mode Mode MIN MAX MIN MAX MIN MAX SCKp high low level 1 4 0 V EVppo lt 5 5 V 2 2 2 2 2 2 ns width tkL2 2 7 V lt Vo lt 4 0 V 12 50 50 2 7 V EVppo lt 4 0 V 2 2 2 ns 2 3 V lt Vo lt 2 7 V 18 50 50 1 8 V EVppo lt 3 3 V 2 2 2 2 ns 1 6 V lt Ve lt 2 0 V ete 50 50 50 Slp setup time tsike 4 0 V EVppo 5 5 V 1 fuck 1 fuck 1 fuck ns to SCKpT 27V lt V lt 40V 20 30 30 2 7 V EVppo lt 4 0 V 1 fuck 1 fuck 1 fuck ns 2 3V lt Vo lt 2 7V 20 30 30 1 8 V EVppo lt 3 3 V 1 fuck 1 fuck 1 fuck ns 1 6V lt Vo lt 2 0 VN 30 30 30 Slp hold time tksi2 1 1 fuck 1 fuck ns from SCKp7 ee 31 31 31 Delay time from tkso2 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo 4 0 2 2 2 ns SCKpl to SOp output V 120 573 573 mes Co 30 pF Re 1 4 KQ 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vo 2 7 2 2 fuck 2 fuck ns V 214 573 573 30 pF Rb 2 7 KQ 1 8 V EVppo lt 3 3 V 2 fuck 2 2 ns 1 6 V lt Vo lt 2 0 V e 573 573 573 Co 30 pF Rb 5 5 KQ Notes 1 Transfer rate i
31. lt K ra 27 lt rows P31 lt Kz Pao P41 lt rows 51 rows P60 to P63 Kj k P70 to P73 PORT 12 be 4 P121 to P124 PORT 13 P137 C5 PORT 14 K 2 P146 P147 ANIO P20 to ANI7 P27 ANI18 P147 ANI19 P120 AVnere P20 AVnerv P21 KRO P70 to KR3 P73 POWERONRESEU VOLTAGE CONTROL DETECTOR SYSTEM CONTROL RESET X1 P121 X2 EXCLK P122 XT1 P123 OSCILLATOR XT2 EXCLKS P124 VOLTAGE REGULATOR REGC RxD2 P14 INTPO P137 INTP1 P50 2 INTP2 P51 INTP3 P30 INTP4 P31 la INTPS P16 INTERRUPT CONTROL Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral redirection register PIOR PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 Nov 15 2013 RENESAS Refer to Figure 4 8 Format of Peripheral I O Redirection Register Page 41 of 194 RL78 G13 OUTLINE 1 5 9 48 pin products TIMER ARRAY UNIT 8ch TI00 P00 TO00 P01 TI01 TO01 P16 102 002 17 02 002 15 TI03 TOO3 P31 103 7003 14 104 7004 13 105 7005 12 TI06 TO06 P11 TI07 TO07 P41 TIO7 TOO7 P10 RxD2 P14 WINDOW WATCHDOG IMER LOW SPEED ON CHIP OSCILLATOR INTERVAL RTC1HZ P30 SERIAL ARRAY UNITO 4ch RxDO0 P1 1 RxDO P16 TxDO0 P12 TxD0 P17 RxD1 P01
32. lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX Slp setup time 4 0 V EVppo lt 5 5 V to SCKpT ete 1 2 7 V Ve lt 40 V Co 30 pF Re 1 4 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V Co 30 pF Rb 2 7 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 Vete Cp 30 pF Re 5 5 Slp hold time 4 0 V EVppo 5 5 V from SCKpT 2 7 Vo 4 0 V Co 30 pF Re 1 4 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V Co 30 pF Ro 2 7 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V 2 Co 30 pF Ro 5 5 Delay time from SCKpl 4 0 V lt EVppo lt 5 5 V to 2 7 V Vo 4 0 V Note 1 SOp output Co 30 pF Rb 1 4 KQ 2 7 V EVppo lt 4 0 V 2 3 V Vox 2 7 V C 30 pF Ro 2 7 1 8 V EVppo 3 3 V 1 6 V lt Vo lt 2 0 V 2 Co 30 pF Re 5 5 Notes 1 When DAPmn 0 and CKPmn or DAPmn 1 and CKPmn 1 2 Use it with EVppo gt Vb Caution Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode reg
33. s Manual Hardware Refer to Figure 4 8 Format of Peripheral I O Redirection Register R01DS0131EJ0310 Rev 3 10 Nov 15 2013 RENESAS Page 40 of 194 RL78 G13 1 5 8 44 pin products TI00 P00 TO00 P01 TI01 TO01 P16 TI02 TO02 P17 TI02 TO02 P15 TI03 TO03 P31 TI03 TO03 P14 TI04 TO04 P13 TI05 TO05 P12 TI06 TO06 P11 TI07 TO07 P41 TI07 TO07 P10 RxD2 P14 LOW SPEED ON CHIP OSCILLATOR REAL TIME RTC1HZ P30 I CLOCK 11 16 TxDO0 P12 TxD0 P17 RxD1 P01 TxD1 P00 SCKO0 P10 100 11 000 12 SCK11 P30 SI11 P50 SO11 P51 SCLO00 P10 SDAOO P11 SCL11 P30 SDA11 P50 RxD2 P14 TxD2 P13 SCK20 P15 SI20 P14 SO20 P13 SCK21 P70 SI21 P71 021 72 SCL20 P15 SDA20 P14 SCL21 P70 SDA21 P71 TIMER ARRAY UNIT 8ch WINDOW WATCHDOG TIMER BIT INTERVAL MER SERIAL ARRAY UNITO 4ch SERIAL ARRAY UNIT 2ch lt CODE FLASH MEMORY RL78 E CPU CORE lt J DATA FLASH MEMORY OUTLINE gt gt RAM Vop Vss TOOLRxD P11 TOOLTxD P12 SDAAO P61 SDAAO P13 SERIAL INTERFACE SCLAO PGO SCLAO P14 BUZZER OUTPUT PCLBUZO P31 CLOCK OUTPUT FOEBUZUPIS CONTROL MULTIPLIER amp DIVIDER ERE MULITIPLY ACCUMULATOR DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT gt roro K gt P00 P01 lt son Kx P10to P17
34. sensor output voltage ANI2 to ANI14 internal reference voltage and temperature 40 to 85 C 1 6 V lt AVnerP lt lt 5 5 V Vss 0 V Reference voltage AVnere Reference voltage AVrerm 0 V Parameter Resolution Conditions Overall error 1 10 bit resolution AVnere Notes 1 8 V lt AVrere lt 5 5 V 1 6 V lt AVnere lt 5 5 Pete 4 Conversion time 10 bit resolution ANI14 3 6 V lt Vpp lt 5 5 V Target pin ANI2 to 2 7 V lt Vpp lt 5 5 V 1 8 V lt Vpp lt 5 5 V 1 6 V lt Vpp lt 5 5 V 10 bit resolution 3 6 V lt Vpp lt 5 5 V Target pin Internal reference voltage and temperature sensor output voltage HS high speed main mode 2 7 V lt Vpp lt 5 5 V 2 4 V lt Vpp lt 5 5 V 515 5 5 5 5 5 Zero scale errorhetes gt 10 bit resolution AVnere Notes 1 8 V lt 5 5 V 1 6 V AVnere lt 5 5 V Pete 4 Full scale error es 10 bit resolution AVnere Notes 1 8 V lt AVrere lt 5 5 V 1 6 V lt AVREFP lt 5 5 V ote 4 Integral linearity error 10 bit resolution AVnere Notes 1 8 V lt AVrere 5 5 V 1 6 V lt AVnere lt 5 5 V Pete 4 Differential linearity error Note 1 10 bit resolution AVnere Notes 1 8 V lt AVrere lt 5 5 V 1 6 V lt AVnere lt 5 5 V
35. transmission 50 pF Ro 27 1 8 V lt EVppo lt 5 5 V 0 355 0 355 0 355 ns Co 100 pF Rb 1 8 V EVppo 2 7 V 0 405 0 405 0 405 ns Co 100 pF Rb 5 1 7 V EVppo 1 8 V 0 405 0 405 0 405 ns Co 100 pF Rb 5 KQ 1 6 V EVppo lt 1 8 V C 100 pF Ro 5 Notes 1 The value must also be equal to or less than 4 2 Set the fuck value to keep the hold time of SCLr L and SCLr Caution Select the normal input buffer and the N ch open drain output Vpp tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g PIMg and port output mode register h POMh Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 89 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Simplified mode mode connection diagram during communication at same potential Vpp Rb SDAr SDA RL78 microcontroller User device SCLr SCL Simplified mode serial transfer timing during communication at same potential 1 fsc SCLr SDAr tHD DAT tsu DAT Remarks 1 Rb Q Communication line SDAr pull up resistance Communication line SDAr SCLr load capacitance 2 r IIC number r 00 01 10
36. 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V Co 20 pF Re 2 7 tkcvi 2 120 tkcvi 2 120 tkcvi 2 120 SCKp low level width 4 0 V EVppo 5 5 V 2 7 V Vo 4 0 V Cb 20 pF Rb 1 4 kQ tkcvi 2 7 tkcvi 2 50 tkcvi 2 50 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V C 20 pF Rb 2 7 tkcvi 2 10 tkcvi 2 50 tkcvi 2 50 Slp setup time to SCKpT ete 1 4 0 V EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V Cb 20 pF Rb 1 4 kQ 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V Cb 20 pF Rb 2 7 51 hold time from SCKpT 1 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo 4 0 V Co 20 pF Rb 1 4 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V Cb 20 pF Rb 2 7 Delay time from SCKpJ to SOp output Note 1 Notes Caution and Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 4 0 V EVppo lt 5 5 V 2 7 V lt Vo 4 0 V 20 pF 1 4 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V Cb 20 pF Rb 2 7 21 NESAS Page 95 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 7 Communication at different potential 2 5 V 3 V CSI mode master mode SCKp internal clock output corresponding CSIOO
37. 40 to 85 C Ta 40 to 85 C 1 6 V x EVppo 1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 3 5 Conditions Input voltage to P07 P10 to P17 P30 to P37 Normal input buffer 0 8EVppo EVppo V high P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Vine P01 P03 P04 P10 P11 TTL input buffer 2 2 EVppo V P13 to P17 P43 P44 P53 to P55 4 0 V lt EVppo lt 5 5 V P80 P81 P142 P143 TTL input buffer 2 0 EVppo V 3 3 V lt EVppo lt 4 0 V TTL input buffer 1 5 EVppo V 1 6 V lt EVppo lt 3 3 V Vins P20 to P27 P150 to P156 0 7Vop Voo V Vin4 P60 to P63 0 7EVppo 6 0 V Vins P121 to P124 P137 EXCLK EXCLKS RESET 0 8Vpp Voo V Input voltage POO to P07 P10 to P17 P30 to P37 Normal input buffer 0 0 2EVppo V low P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Vite P01 P04 P10 P11 TTL input buffer 0 0 8 V P13 to P17 P43 P44 P53 to P55 4 0 V lt EVppo lt 5 5 V P80 P81 P142 P143 TTL input buffer 0 0 5 V 3 3 V EVppo lt 4 0 V TTL input buffer 0 0 32 V 1 6 V lt EVppo lt 3 3 V P20 to P27 P150 to P156 0 0 3Vop Vita P60 to P63 0 0 3EVppo Vis P121 to P124 P137 EXCLK EXCLKS RESET 0 0 2Vop Caution The maximum value of
38. 5 5 V 1 6 V lt EVppo lt 5 5 V Setup time of restart tsu sta 2 7 V lt EVppo lt 5 5 V condition 1 8 V lt EVbppo lt 5 5 V 1 7 V lt EVppo 5 5 V 1 6 V lt EVppo lt 5 5 V Hold time e tHosta 2 7V lt EVopo lt 5 5 V 1 8 V lt EVppo lt 5 5 V 1 7 V lt EVbppo lt 5 5 V 1 6 V lt EVppo lt 5 5 V Hold time when SCLAO 2 7 V lt EVomo lt 5 5 V 1 8 V lt lt 5 5 V 1 7 V lt EVbppo 5 5 V 1 6 V lt EVppo lt 5 5 V Hold time when SCLAO 2 7 V lt EVomo lt 5 5 V H 1 8 V EVoo lt 5 5 V 1 7 V lt EVbppo lt 5 5 V 1 6 V lt EVppo lt 5 5 V Data setup time tsu par 2 7 V lt EVppo lt 5 5 V reception 1 8 V EVoo lt 5 5 V 1 7 V lt EVbppo lt 5 5 V 1 6 V lt EVppo lt 5 5 V Data hold time tHo DaT 2 7 V lt EVppo lt 5 5 V transmission 2 18V lt EVow 55 V 1 7 V lt EVbppo lt 5 5 V 1 6 V lt lt 5 5 V Setup time of stop 2 7 V lt EVppo lt 5 5 V condition 1 8 V lt EVopo lt 5 5 V 1 7 V lt EVomo lt 5 5 V 1 6 V lt EVppo lt 5 5 V Bus free time 2 7 V lt EVo00 lt 5 5 V 1 8 V lt EVppo lt 5 5 V 1 7 V lt EVppo lt 5 5 V 1 6 V lt EVppo lt 5 5 V 5 5 5 5 5 5 15 5 5 5 5 5 5 1 851515 2 o 2 o 2 o 2 o 5 5 5 5 5 15 15 5 5 5 5 5 Notes Caution and Remark are listed on th
39. 8 channels PWM outputs 3 8 channels PWM outputs 7 ote 2 Note 3 outputs 7 N 8 channels PWM outputs 7 2 3 RTC output 1 channel e 1 Hz subsystem clock fsus 32 768 kHz Notes 1 In the case of the 4 KB this is about 3 KB when the self programming function and data flash function are used For details see CHAPTER 3 in the RL78 G13 User s Manual Hardware In the case of the 20 KB this is about 19 KB when the self programming function and data flash function are used For details see CHAPTER 3 in the RL78 G13 User s Manual Hardware In the case of the 32 KB this is about 31 KB when the self programming function and data flash function are used For details see CHAPTER 3 the RL78 G13 User s Manual Hardware 2 The number of PWM outputs varies depending on the setting of channels in use the number of masters and slaves 6 9 3 Operation as multiple PWM output function in the RL78 G13 User s Manual Hardware 3 When setting to PIOR 1 R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 50 of 194 Nov 15 2013 RL78 G13 Clock output buzzer output 1 OUTLINE 2 2 X30014SH X3L0LJSH X30014SH 0 XOLOLASY 0 16 XP LOLASY X10014SH x90014SY 2 2 2 2 X1L0LJSH 2 44 kHz 4 88 kHz 9 76 kHz 1 25 MHz 2 5 MHz 5 MHz 10 MHz Main system clock 20 MHz operation 256 Hz 512 Hz 1 024 kHz 2 048 kHz 4 096 kHz 8 192 kHz 16 384
40. AVrerP ANIO ADREFP1 0 ADREFPO 1 reference voltage AVREFWANI1 ADREFM 1 target pin sensor output voltage ANI2 to ANI14 internal reference voltage and temperature Ta 40 to 105 2 4 V lt AVnerP lt lt 5 5 V Vss 0 V Reference voltage AVrerr Reference voltage AVrerm 0 V Parameter Resolution Conditions Overall error 1 Conversion time 10 bit resolution Note 3 AVrere Vpp 10 bit resolution Target pin ANI2 to ANI14 2 4 V lt lt 5 5 10 bit resolution voltage and temperature sensor output voltage HS high speed main mode Target pin Internal reference 5 5 5 5 5 5 Zero scale errors 10 bit resolution AVrerp 3 2 4 V lt AVrerp lt 5 5 V Full scale error gt 10 bit resolution AVnere Notes 2 4 V lt AVrere lt 5 5 V Integral linearity error Note 1 10 bit resolution Note 3 AVnerP Vpp 2 4 V lt AVner lt 5 5 V Differential linearity error Note 1 10 bit resolution Note 3 AVnere Vpp 2 4 V lt lt 5 5 V Analog input voltage ANI2 to ANI14 Internal reference voltage output 2 4 V lt lt 5 5 V HS high speed main mode Note 4 Veer Notes are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 Temperature sensor output
41. C 2 4 V lt EVppo lt lt 5 5 V Vss EVsso 0 V 1 2 Parameter Supply current 1 Note Operating mode HS high speed main mode Note 5 Conditions 32 MHz Note Vo 5 0 V Vpp 3 0 V Voo 5 0 V Voo 3 0 V 24 MHz Notes Vpp 5 0 V Voo 3 0 V 16 MHz ee Vpp 5 0 V 3 0 V HS high speed main mode Note 5 fux 20 MHz 2 Voo 5 0 V Square wave input Resonator connection fux 20 MHz 2 Voo 3 0 V Normal operation Square wave input Resonator connection fux 10 MHz 2 Voo 5 0 V Normal operation Square wave input Resonator connection fux 10 MHz 2 Voo 3 0 V Normal operation Square wave input Resonator connection Subsystem clock operation 32 768 kHz Note 4 Ta 40 operation Square wave input Resonator connection 32 768 kHz Note 4 Ta 25 Normal operation Square wave input Resonator connection 32 768 kHz Note 4 Ta 50 C Normal operation Square wave input Resonator connection 32 768 kHz Note 4 70 Normal operation Square wave input Resonator connection 32 768 kHz Note 4 TA 85 Normal operation Square wave input Resonator
42. Caution The values in the above table are applied even when bit 2 PIOR2 in the peripheral I O redirection register PIOR is 1 At this time the pin characteristics must satisfy the values in the redirect destination Remark The maximum value of Cb communication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Fast mode plus Cb 120 pF Rb 1 1 kQ IICA serial transfer timing SCLAn TtHD STA SDAAn Stop Start Restart Stop condition condition condition condition Remark n 0 1 R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 112 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 2 6 Analog Characteristics 2 6 1 A D converter characteristics Classification of A D converter characteristics Input channel ANIO to ANI14 Reference voltage AVREFP Reference voltage AVREFM Refer to 2 6 1 1 Reference Voltage Refer to 2 6 1 3 ANI16 to ANI26 Refer to 2 6 1 2 Internal reference voltage Temperature sensor output voltage Refer to 2 6 1 1 Reference voltage VDD Reference voltage Vss Reference voltage VBGR Reference voltage AVREFM Refer to 2 6 1 4 1 When reference voltage AVnErP ANIO ADREFP1 0 ADREFPO 1 reference voltage AVREFWANI1 ADREFM 1 target pin
43. INTP1 P50 INTP2 P51 INTP3 P30 INTP4 P31 INTP5 P16 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral redirection register PIOR PIOR in the RL78 G13 User s Manual Hardware Refer to Figure 4 8 Format of Peripheral I O Redirection Register R01DS0131EJ0310 Rev 3 10 Nov 15 2013 RENESAS Page 38 of 194 RL78 G13 1 OUTLINE 1 5 6 36 pin products TIMER ARRAY C PORT O K 2 gt P00 P01 UNIT 8ch Porro TI00 P00 I01 TOO1 P16 lt PORT 2 lt 8 P20 to P25 102 002 17 TIO2 TOO2 P15 C PORT 3 lt 2 0 P31 TIO3 TOO3 P31 TI03 TO03 P14 lt PORT 4 P40 TI04 TO04 P13 PORT 5 P50 P51 TIO6 TOO6 P1 1 lt porte X KS to P62 TI07 TOO7 P10 iei lt PoRT7 lt 8 P70 to P72 WINDOW PORT 12 d wande 2 P121 P122 MER PORT 13 P137 INTERVAL OSCILLATOR MER C PORT 14 gt P147 RL78 CODE FLASH MEMORY CPU ANIO P20 to lt are DATA FLASH MEMORY ANI5 P25 SERIAL ARRAY UNITO 4ch A D CONVERTER ANI18 P147 ANI19 P120 AVnere P20 11 16 TxD0 P12 TxD0 P17 21 RxD1 P01 TxD1 P00 PONER ON BESET POR LVD SCK00 P10 DETECTOR CONTROL SI00 P11 000 12 SCK11 P30 RESET CONTROL SO11 P51 SCLOO P10 Va Mss MOOD PIS ON CHIP DEBUG TOOLO P
44. P137 PORT14 P147 CODE FLASH MEMORY ANI0 P20 to WINDOW ANI2 P22 WATCHDOG ANI16 P01 ANI17 P00 TIMER MEMORY AD CONVERTER ANIT8 P147 AVnerpe P20 POM SPEED 12 BIT INTERVAL Borne el ON enp TIMER lt OSCILLATOR POWER ON RESET PORNO VOLTAGE CONTROL DETECTOR RAM SERIAL ARRAY RESET CONTROL UNITO 4ch RxDO P11 lt ON CHIP DEBUG TOOLO P40 TxDO P12 Voo Vss TOOLRxD P11 STEN TOOLTxD P12 RxD1 P01 CONTROL RESET TxD1 P HIGH SPEED X1 P121 ON CHIP SCK00 P10 MULTIPLIER amp n OSCILLATOR X2 EXCLK P122 SIO0 P11 DIVIDER SO00 P12 MULITIPLY ACCUMULATOR VOLTAGE m SCK11 P30 REGULATOR SH1 P17 DIRECT MEMORY SO11 P16 ACCESS CONTROL NTP0 P137 SCL00 P10 INTERRUPT SDA00 P11 S BCD CONTROL INTP3 P30 ADJUSTMENT SCL11 P30 INTP5 P16 SDA11 P17 R01DS0131EJ0310 Rev 3 10 aQ NECES AS Page 34 of 194 Nov 15 2013 RL78 G13 1 OUTLINE 1 5 2 24 pin products TI00 P00 TO00 P01 TI01 TO01 P16 TI02 TO02 P17 TI03 TO03 P31 LOW SPEED ON CHIP OSCILLATOR REAL TIME CLOCK TIMER ARRAY UNIT 8ch WINDOW WATCHDOG TIMER IT INTERVAL TIMER K CODE FLASH MEMORY DATA FLASH MEMORY lt sw P01 Poni P12 P16 P17 lt P20 to P22 lt rows P30 P31 lt PORT13 I P137 L Pon P147 ANIO P20 to ANI2 P22 ANI16 P01 ANI17 POO ANI18 P147 AVnere P20
45. R01DS0131EJ0310 Rev 3 10 QE NE S AS Page 12 of 194 Nov 15 2013 RL78 G13 Pin count Note Package 80 pin plastic LQFP 14 x 14 mm 0 65 mm pitch 1 OUTLINE Table 1 1 List of Ordering Part Numbers Data flash Mounted Fields of Application Note 10 12 Ordering Part Number R5F100MFAFAz VO R5F100MGAFA VO R5F100MHAFA VO R5F100MJAFA VO R5F100MKAFAzVO R5F100MLAFA VO R5F100MFAFA X0 R5F100MGAFA X0 R5F100MHAFA XO R5F100MJAFA X0 R5F100MKAFA X0 R5F100MLAFAZXO R5F100MFDFA VO0 R5F100MGDFA VO R5F100MHDFA VO R5F100MJDFAZVO R5F100MKDFAzVO R5F100MLDFA VO R5F100MFDFA X0 R5F100MGDFA X0 R5F100MHDFAZXO R5F100MJDFA X0 R5F100MKDFA X0 R5F100MLDFA X0 R5F100MFGFA VO R5F100MGGFA VO R5F100MHGFA VO R5F100MJGFA VO R5F100MFGFA X0 R5F100MGGFA XO R5F100MHGFA XO R5F100MJGFA X0 Not mounted R5F101MFAFA VO R5F101MGAFA VO R5F101MHAFA VO R5F101MJAFA VO R5F101MKAFA VO R5F101MLAFA VO R5F101MFAFA X0 R5F101MGAFA X0 R5F101MHAFAZXO R5F101MJAFA X0 R5F101MKAFA X0 R5F101MLAFA X0 R5F101MFDFA VO0 R5F101MGDFA VO R5F101MHDFA VO R5F101MJDFAZVO R5F101MKDFAzVO R5F101MLDFA VO R5F101MFDFA X0 R5F101MGDFA X0 R5F101MHDFAZXO R5F101MJDFA X0 R5F101MKDFA X0 R5F101MLDFA X0 80 pin plastic LFQFP 12 x 12 mm 0 5 mm pitch Mounted R5F100MFAFB VO0 R5F100MGAFB VO R5F100MHAFB VO R5F100MJAFB V0 RSF100MKAFB V0 R5F100MLAFB V0 R5F100MFAFB X0 R5F100MGAFB X0 R5F100MHAFB XO R5F100MJAFB X0 R5F100MKA
46. SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 4 UART2 cannot communicate at different potential when bit 1 PIOR1 of peripheral I O redirection register PIOR is 1 R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 154 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 6 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 1 3 Ta 40 to 105 C 2 4 V lt EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V Parameter SCKp cycle time Conditions tkcvi gt 4 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo 4 0 V Cb 30 pF Rb 1 4 kQ MIN HS high speed main Mode MAX V Co 30 pF Rb 2 7 2 7 V lt EVppo lt 4 0 V 23V lt Vo 2 7 V Co 30 pF Pb 5 5 2 4 V lt EVppo lt 3 8 V 1 6 V lt Vo lt 2 0 SCKp high level width 4 0 V lt lt 5 5 V 2 7 V lt Vo 4 0 V Cb 30 pF Rb 1 4 1 2 150 2 7 V lt EVoto lt 4 0 V 2 3 V lt Vo lt 2 7 V Cb 30 pF Re 2 7 tkcvi 2 340 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo 2 0 V 30 pF Rb 5 5 1 2 916 SCKp low level width 4 0 V lt EVppoo lt 5 5 V 2 7 V lt Vo lt 4 0 V Cb 30 pF Ro 1 4 tkcvi 2 24 2 7 V lt EVpoo lt 4 0 V 2 3 V lt Vo lt
47. Vpp lt 5 5 V 2 7 V lt Vpp lt 5 5 V 2 4 V lt Vpp lt 5 5 V Zero scale 1 2 10 bit resolution EVppo lt AVrerp Notes 3 4 2 4 V AVnerP lt 5 5 V Full scale error es 10 bit resolution lt AVrerp Ses 4 2 4 V AVnerP lt 5 5 V Integral linearity error e 1 10 bit resolution EVppo AVrerp Notes 3 4 2 4 V AVnerP lt 5 5 V Differential linearity error Note 1 10 bit resolution EVppo lt AVnerp ots 3 4 2 4 V AVnerP lt 5 5 V Analog input voltage ANI16 to ANI26 Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 When AVrere lt the MAX values are as follows Overall error Add 1 0 LSB to the MAX value when AVrerp Voo Zero scale error Full scale error Add 0 05 FSR to the MAX value when AVnere Vov AVREFP and EVppo Integral linearity error Differential linearity error Add 0 5 LSB to the MAX value when AVnere Voo 4 When AVrere lt EVopopo Von the MAX values are as follows Overall error Add 4 0 LSB to the MAX value when AVaere Vpp Zero scale error Full scale error Add 0 20 FSR to the MAX value when AVrere Integral linearity error Differential linearity error Add 2 0 LSB to the MAX value when AVnere Voo R01DS0131EJ0310 Re
48. connection 32 768 kHz Note 4 Ta 105 Notes and Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Normal operation Square wave input Resonator connection k S 5 5 3 5 R E 5 E BS 5 Page 132 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Notes 1 Remarks Total current flowing into and EVppo including the input leakage current flowing when the level of the input pin is fixed to Vpp EVppo or Vss EVsso The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit port and on chip pull up pull down resistors and the current flowing during data flash rewrite When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When AMPHS 1 1 Ultra low power consumption oscillation However not including the current flowing into the RTC 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V lt Voo lt 5 5 V 1 MHz to 32 MHz 2 4 V lt lt 5 5 V 1 MHz to 16 MHz 1 fmx High speed system clock frequency X1 clock oscilla
49. high 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Conditions POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 P20 to P27 P137 P150 to P156 RESET P121 to P124 X1 X2 XT1 XT2 EXCLK EXCLKS In input port or external clock input In resonator connection Input leakage current low POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Vi EVsso P20 to P27 P137 P150 to P156 RESET P121 to P124 X1 X2 XT1 XT2 EXCLK EXCLKS In input port or external clock input In resonator connection On chip pll up resistance POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Vi EVsso In input port Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins R01DS0131EJ0310 Rev 3 10 Nov 15 2013 ztENESAS Page 131 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 3 3 2 Supply current characteristics 1 Flash ROM 16 to 64 KB of 20 to 64 pin products Ta 40 to 105
50. lt amp lt lt 5 lt a HRASERZA D SEES ONZE 2 A ese IT OSOGAa amp gOoB58mm Or eooo SFELLSEFFA Tras aagQe 58388995540 EEE lt OSOxxOSS ZZ22 K eoo o r QO t TIE amp QN CO sb O O F lt 10 aA o Tom 0 0 0 0 D aaoaaaaaoaaatnaoaadnhaa O Or OOO Or Ov Or Or QUO 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P27 ANI7 O P30 INTP3 RTC1HZ SCK11 SCL11 P26 ANI6 O P05 T105 T005 25 5 P06 TI06 TOO6 P24 ANIA O O P70 KRO SCK21 SCL21 P23 ANI3 O O P71 KR1 SI21 SDA 21 22 2 O O P72 KR2 SO 1 P21 ANI1 AVREFM O P73 KR3 SO01 P20 ANIO AVrere O P74 KR4 INTP8 SI01 SDA01 P130 O O P75 KRS5 INTP9 SCK01 SCLO1 P04 SCK10 SCL10 O P76 KR6 INTP10 RXD2 POS ANI16 SH O RXD1 SDA10 O P77 KR7 INTP11 TXD2 PO2 ANI17 SO10 TxD1 O P31 T103 TO03 INTP4 PCLBUZO P01 TOO0 O P63 POO TIOO O O P62 P141 PCLBUZ1 INTP7 O O P61 SDAAO P140 PCLBUZO INTP6 O P60 SCLAO 12 13 14 15 16 o 0 gag 888 5 gt gt gt 5 lt 6 Z X Q m u IK lt lt ul amp Ses Qi x lt BORA zz g P a a n Cautions 1 Make EVsso pin the same potential as Vss pin 2 Make Vpn pin the potential that is higher than
51. lt EVopo lt 4 0 V 10 0 mA P125 to P127 P130 P140 to P145 When duty lt 70 Note 1 8 V EVppo lt 2 7 V 5 0 1 6 V lt EVopo lt 1 8 V 2 5 mA Total of P05 P06 P10 to P17 P30 P31 4 0 V lt EVppo lt 5 5 V 80 0 mA P50 to P57 P64 to P67 P70 to P77 80 2 7 lt EVopo lt 40V 19 0 mA to P87 P90 to P97 P100 P101 P110 to P117 P146 P147 1 8 V lt EVppo lt 2 7 V 10 0 mA When duty lt 70 1 6 V lt EVppo lt 1 8 V 5 0 mA Total of all pins 1 6 V lt EVpro lt 5 5 V 135 0 mA When duty lt 70 3 Note Per pin for P20 to P27 P150 to P156 1 6 V lt Vpp lt 5 5 V 0 19 mA 2 Total of all pins 1 6V lt Vo lt 5 5V 1 5 mA When duty lt 70 3 Notes 1 Value of current at which the device operation is guaranteed even if the current flows from the EVppo EVoo1 pins to an output pin 2 However do not exceed the total current value 3 Specification under conditions where the duty factor lt 7096 The output current value that has changed to the duty factor gt 70 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n e Total output current of pins lou x 0 7 n x 0 01 Example Where n 80 and 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA However the current that is allowed to flow into one pin do
52. lt Ve lt 4 0 V Co 30 pF Re 1 4 KQ MAX 2 7 V lt EVppo lt 4 0 V 23V lt Vo lt 2 7 V 30 pF Rb 2 7 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V Cp 30 pF Re 5 5 Slp hold time from SCKpJ 4 0 V lt EVppo 5 5 V 2 7 V lt Vo 4 0 V pF Ro 1 4 2 7 V lt EVppo 4 0 V 2 3 V lt Vo 2 7 V Cb 30 pF Rb 2 7 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo 2 0 V 30 pF Ro 5 5 Delay time from SCKp to SOp output Note When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 4 0 V lt EVppo 5 5 V 2 7 V lt Vo 4 0 V 30 pF 1 4 KQ 2 7 V lt EVpoo lt 4 0 V 2 3 V lt Vo lt 2 7 V Co 30 pF Ro 2 7 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo 2 0 V 30 pF Ro 5 5 Caution Select the TTL input buffer for the Sip pin and the N ch open drain output tolerance When 20 to 52 pin products EVpp tolerance When 64 to 100 products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NE SAS Page 157 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C CSI mode
53. 0 66 JA clock Ta 40 C Resonator 0 50 0 85 JA operation connection fsus 32 768 kHz Square wave input 0 38 0 66 uA 25 C Resonator 0 57 0 85 LA connection fsus 32 768 kHz Square wave input 0 47 3 49 uA Ta 50 C Resonator 0 66 3 68 LA connection fsus 32 768 kHz Square wave input 0 80 6 10 uA 70 C Resonator 0 99 6 29 LA connection 32 768 kHz 5 Square wave input 1 52 10 46 uA Ta 85 C Resonator 1 71 10 65 LA connection mode Ta 40 C Ta 25 C 0 26 0 54 50 C 0 35 3 37 70 0 68 5 98 85 Notes and Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS S S 5 5 58 Page 73 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Notes 1 Total current flowing into EVopo and EVoo1 including the input leakage current flowing when the level of the input pin is fixed Vop EVppo and EVpp1 or Vss EVsso and EVssi The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors the current flowing during data flash rewrite During HALT instruction execution by flash memory When high speed on chip oscillator a
54. 00 0 05 gt TA A 0 75 0 05 EXPOSED DIE PAD 0 05 b 0 25 0 0 07 e 0 50 Lp 0 40 0 10 0 05 0 05 ITEM De ER MIN NOM MAX MIN EXPOSED DIE PAD A 2 452 50 2 55 2 45 2 50 2 55 VARIATIONS 2012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 177 of 194 Nov 15 2013 RL78 G13 4 3 25 pin Products R5F1008AALA R5F1008CALA R5F1008DALA R5F1008EALA R5F1018AALA R5F1018CALA R5F1018DALA R5F1018EALA R5F1008ADLA R5F1008CDLA R5F1008DDLA R5F1008EDLA R5F1018ADLA R5F1018CDLA R5F1018DDLA R5F1018EDLA JEITA Package Code RENESAS Code Previous Code 4 PACKAGE DRAWINGS MASS TYP g P WFLGA25 3x3 0 50 PWLGOO25KA A P25FC 50 2N2 2 0 01 21 95 S ZD L gt wS A ZE le yo 1 7 B E A _ I INDEX MARK wsSs B INDEX MARK y1 8S A Y S UNIT mm S y ITEM DIMENSIONS D 3 00 0 10 3 00 0 10 DETAIL OF C PART DETAIL OF D PART w 0 20 R0 17 0 05 0 43 0 05 e 0 50 Z R0 1240 05 0 33 0 05 A 0 69
55. 00 01 10 20 30 31 m Unit number n Channel number mn 00 01 02 10 12 13 0 PIM and POM number g 0 1 4 5 8 14 3 Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 01 02 10 12 13 4 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 104 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcve 2 ike Output data CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcy2 lee t 2 Output data Remarks 1 p CSI number p 00 01 10 20 30 31 m Unit number n Channel number mn 00 01 02 10 12 13 0 PIM and POM number g 0 1 4 5 8 14 2 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 105 of 194 Nov 15 2013 RL78 G13
56. 00 to 03 10 to 13 R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 145 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 2 During communication at same potential CSI mode master mode SCKp internal clock output Ta 40 to 105 C 2 4 V lt EVppo EVpni lt lt 5 5 V Vss EVsso EVssi 0 V HS high speed main Mode Parameter SCKp cycle time Conditions tkcvi gt 4 fcuk 2 7 V lt EVppo lt 5 5 V MIN 250 MAX 2 4 V lt EVboo lt 5 5 V 500 SCKp high low level width 4 0 V lt lt 5 5 V tkcvi 2 24 2 7 V lt EVppo 5 5 V tkcvi 2 36 2 4 V lt EVppo lt 5 5 V tkcy1 2 76 Slp setup time to SCKpT N 4 0 V lt lt 5 5 V 66 2 7 V lt EVppo 5 5 V 66 2 4 V lt lt 5 5 V Slp hold time from SCKpT Delay time from SCKpl to SOp output C 30 pF Note 4 Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The 51 setup time becomes to SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip hold time becomes from SCKpl when DAPmn 0 and CKPmn 1 or DAPmn 1 CKPmn 0 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpT when DAPmn 0 an
57. 1 1 5 Transfer rate x2 Co x PORN Transfer rate Baud rate error theoretical value x 100 96 x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides 7 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer Caution Select the TTL input buffer for the RxDq pin and the N ch open drain output tolerance When 20 to 52 products EVpo tolerance When 64 to 128 pin products mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg For and Vi see the DC characteristics with TTL input buffer selected UART mode connection diagram during communication at different potential Vb E User device RL78 microcontroller RxDq R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 93 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C UART mode bit width during communication at different potential reference 1 Transfer rate Low bit width High bit width Baud rate error tolerance icm ie 8 TxDq 1 Transfer rate High Low bit width Baud rate error tolerance RxDq Remarks 1 X Re O
58. 2 7 to 5 5 V oscillator HS High speed main mode 1 to 16 MHz 2 4 to 5 5 V LS Low speed main mode 1 to 8 MHz Voo 1 8 to 5 5 V LV Low voltage main mode 1 to 4 MHz 1 6 to 5 5 V Subsystem clock XT1 crystal oscillation external subsystem clock input EXCLKS 32 768 kHz Low speed on chip oscillator 15 kHz TYP General purpose registers 8 bit register x 8 x 4 banks Minimum instruction execution time 0 03125 ws High speed on chip oscillator fiu 32 MHz operation 0 05 us High speed system clock fmx 20 MHz operation 30 5 us Subsystem clock fsue 32 768 kHz operation Instruction set e Data transfer 8 16 bits e Adder and subtractor logical operation 8 16 bits e Multiplication 8 bits x 8 bits e Rotate barrel shift and bit manipulation Set reset test and Boolean operation etc port Total 36 40 44 48 58 CMOS 28 31 34 38 48 N ch O D I O N ch O D I O N ch O D I O N ch O D I O N ch O D I O Voo withstand Voo withstand Voo withstand Voo withstand Voo withstand voltage 10 voltage 10 voltage 11 voltage 13 voltage 15 CMOS input 5 5 5 5 CMOS output _ 1 1 N ch O D 3 4 4 4 withstand voltage 6 V 16 bit timer 8 channels Watchdog timer 1 channel Real time clock RTC 1 channel 12 bit interval timer IT 1 channel Timer output 4channels PWM 5 channels PWM outputs 4
59. 3 10 QE NEC S AS Page 191 of 194 Nov 15 2013 RL78 G13 4 PACKAGE DRAWINGS 4 13 100 pin Products R5F100PFAFB R5F100PGAFB R5F100PHAFB R5F100PJAFB R5F100PKAFB R5F100PLAFB R5F101PFAFB R5F101PGAFB R5F101PHAFB R5F101PJAFB R5F101PKAFB R5F101PLAFB R5F100PFDFB R5F100PGDFB R5F100PHDFB R5F100PJDFB R5F100PKDFB R5F100PLDFB R5F101PFDFB R5F101PGDFB R5F101PHDFB R5F101PJDFB R5F101PKDFB R5F101PLDFB R5F100PFGFB R5F100PGGFB R5F100PHGFB R5F100PJGFB JEITA Package Code RENESAS Code Previous Code MASS g P LFQFP100 14x14 0 50 PLQP0100KE A P100GC 50 GBR 1 0 69 gt detail of lead end L1 Lp UNIT mm ITEM DIMENSIONS D 14 00 0 20 14 00 0 20 HD 16 00 0 20 16 00 0 20 1 60 1 0 10 0 05 A2 1 40 0 05 A3 0 25 b 0 22 0 05 0 055 0 1452 0 045 L 0 50 Lp 0 60 0 15 L1 1 00 0 20 o got 3 0 50 0 08 0 08 1 00 1 00 2012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev 3 10 Nov 15 2013 192 of 194 RL78 G13 4 PACKAGE DRAWINGS R5F100PFAFA R5F100PGAFA R5F100
60. 50 2 7 V lt EVppo lt 5 5 V tkcvi 2 tkcvi 2 tkcvi 2 ns 18 50 50 2 4 V EVppo 5 5 V tkcvi 2 tkcvi 2 tkcvi 2 ns 38 50 50 1 8 V lt 5 5 V tkcvi 2 1 2 1 2 ns 50 50 50 1 7 V lt EVppo 5 5 V tkcvi 2 tkcvi 2 tkcvi 2 ns 100 100 100 1 6 V lt EVppo lt 5 5 V tkcvi 2 tkcvi 2 ns 100 100 51 setup time tsiki 4 0 V lt EVppo lt 5 5 V 44 110 110 ns 2 7 V lt EVooo lt 5 5 V 44 110 110 ns 2 4 V lt EVppo lt 5 5 V 75 110 110 ns 1 8 V lt EVppo 5 5 V 110 110 110 ns 1 7 V lt EVppo 5 5 V 220 220 220 ns 1 6 V lt EVppo lt 5 5 V 220 220 ns Slp hold time tksi 1 7 V lt EVopo 5 5 V 19 19 19 ns Note 2 from SCKpT 1 6 V lt lt 5 5 V 19 19 ns Delay time from tkso1 1 7 V lt EVppoo lt 5 5 V 25 25 25 ns SCKpl to SOp 30 Note 3 output 1 6 V lt EVo00 lt 5 5 V 25 25 ns C 30 pF ete Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The 51 setup time becomes to SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp hold time becomes from SCKpl when DAPmn 0 CKPmn 1 or DAPmn 1 and CKPmn 0 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpT when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 4 C is the
61. 7 V lt EVppo lt 5 5 V 6 fuck 6 fuck 6 fuck and and and 1500 1500 1500 1 6 V lt EVppo 5 5 V 6 fuck 6 fuck and and 1500 1500 SCKp high low 4 0 V lt EVppo lt 5 5 V 2 2 2 2 2 2 level width 7 7 7 2 7 V lt EVppo lt 5 5 V tkcy2 2 2 2 2 8 8 8 1 8 V lt EVppo 5 5 V tkcy2 2 tkcy2 2 tkcy2 2 18 18 18 1 7 V lt EVppo lt 5 5 V 2 2 tkcy2 2 2 2 66 66 66 1 6 V lt lt 5 5 V 2 2 66 66 Notes Caution and Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 85 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 4 During communication at same potential CSI mode slave mode SCKp external clock input 2 2 Ta 40 to 85 C 1 6 V lt EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed 15 low speed main LV low voltage main main Mode Mode Mode MIN MAX MIN MAX MIN MAX Slp setup time tsixe 2 7 V lt EVomo lt 5 5 V 1 fuck 2 1 30 1 fuck 3 ns to SCKpT ot 0 0 1 1 8 V lt EVppo lt 5 5 V 1 3 1 fuck 30 1 3 ns 0 0 1 7 V lt EVppo lt 5 5 V 1 4 1 fuck 40 1 fuck 4 ns 0 0 1 6 V lt EVppo lt 5 5 V 1 fuck 40 1 fuck
62. AVneru P21 AID CONVERTER POWER ON RESET POR LVD VOLTAGE SERIAL ARRAY CONTROL UNITO 4ch RAM RxDO P11 BQYE RESET CONTROL RxD1 P01 TxD1 P00 Voo Vss TOOLRxD P11 ON CHIP DEBUG TOOLO P40 SCKOO P10 TOOLTxD P12 SIO0 P11 000 12 SYSTEM SCK11 P30 CONTROL RESET SH 1 P50 SERIAL SDAAO P61 HIGH SPEED X1 P121 SO11 P17 INTERFACE IICA0 SCLA0 P60 ONLCHIP X2 EXCLK P122 SCLOO P10 DAOO P11 SPAN BUZZER OUTPUT SDA11 P50 CLOCK OUTPUT REGULATOR CONTROL DIRECT MEMORY ACCESS CONTROL MULTIPLIER amp CRC DIVIDER MULITIPLY INTERRUPT INTP1 P50 BCD ACCUMULATOR NTROL on INTP3 P30 INTP5 P16 R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 35 of 194 Nov 15 2013 RL78 G13 1 5 3 25 pin products TIMER ARRAY UNIT 8ch TIO0 POO TO00 P01 TIO1 TOO1 P16 102 002 17 103 03 1 WINDOW WATCHDOG TIMER EOW SPEED 12 BIT INTERVAL ON SIE TIMER lt OSCILLATOR REAL TIME L CODE FLASH MEMORY DATA FLASH MEMORY 5 1 OUTLINE lt Poro Poni P12 P16 P17 lt rore P20 to P22 lt rors P30 P31 up PORT 6 2 p60 P61 lt PORT 12 2 P121 P122 P P137 PORT14 P147 ANIO P20 to ANI2 P22 ANI16 P01 ANI17 POO ANI18 P147 AVnere P20 AVneru P21 AID CONVERTER POWER ON RESET VOLTAGE PORILVD
63. Communication line TxDq pull up resistance Communication line TxDq load capacitance Ve V Communication line voltage q UART number q 0 to 3 g PIM and POM number g 0 1 8 14 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 4 UART2 cannot communicate at different potential when bit 1 PIOR1 of peripheral I O redirection register PIOR is 1 R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 94 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 7 Communication at different potential 2 5 V 3 V CSI mode master mode SCKp internal clock output corresponding CSIOO only 1 2 Ta 40 to 85 C 2 7 V lt EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V Parameter SCKp cycle time tkcvi tkcy1 gt 2 foik Conditions 4 0 V lt EVppo 5 5 V 2 7 V lt Vo lt 4 0 V 20 pF Ro 1 4 HS high speed main Mode MIN MAX LS low speed main Mode MIN MAX LV low voltage main Mode MIN MAX 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V Cb 20 pF Ro 2 7 SCKp high level width 4 0 V EVppo 5 5 V 2 7 V Ve lt 4 0 V Cb 20 pF Rb 1 4 kQ tkcvi 2 50 tkcvi 2 50 1 2 50
64. EVppo pin 3 Connect the REGC to Vss via a capacitor 0 47 1 Remarks 1 For pin identification see 1 4 Pin Identification 2 When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced it is recommended to supply separate powers to the and EVppo pins and connect the Vss and EVsso pins to separate ground lines 3 Functions in parentheses in the above figure can be assigned via settings in the peripheral redirection register PIOR Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 27 of 194 Nov 15 2013 RL78 G13 1 OUTLINE e 64 pin plastic VFBGA 4 x 4 mm 0 4 mm pitch 5 05 5 Top View N woh ODN EN Bottom View OOOOOOOO OOOOOOOO OOOOOOOO OOOOOOOO OOOOOOOO OOOOOOOO OOOOOOOO POO OD H GF E DB B A P13 TxD2 SO20 SDAA0 TI04 TO04 P146 P30 INTP3 RTC1HZ SCK11 SCL11 SCLAO TIO3 TOO3 P25 ANI5 P70 KRO SCK21 SCL21 P74 KR4 INTP8 SI01 SDAO1 P15 SCK20 SCL20 TI02 TO02 P24 ANI4 P75 KRS INTP9 SCK01 SCLO1 P52 INTP10 P16 T101 TOO1 INTP5 S100 RxDO P22 ANI2 77 7 11 TxD2 P53 INTP11 POS3 ANI 6 SI10 RxD1 SDA10 P130 P61 SDAAO P41 TIO7 TOO7 PO2 ANI17 SO10 TxD1 P60 SCLAO RESET POO
65. Eo rEgrteo xag xpzxej E x S 60 Sem lt 55 e o lt 0 o x 2 cdozxacosg zOoondzctgs O N ooroasgt x optiopowzo gt 5 Oonasgogoza ZO o0 a Qa e N lt lt QQxXOND o x Cx Op SOOG2IE G fn SFEVLSE FMA D o9 SEEEE oCtoaaamttaamoo O0 ZZZZZ xgondoxoasrcEcoxyo r FE lt lt 2 OL2005 zz 5 sf O O Q c sf 10 O Q 10 OON O O O C c 102 IO 10 10 LO LO LO IO gt CO nnnaaaoanannaaonannnnanaunnunnai lan 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P156 ANI14 O 50 P86 INTP8 P155 ANI13 O 49 O P85 INTP7 P154 ANI12 O 48 P84 INTP6 P153 ANI11 O 47 O P83 P152 ANI10 O 46 P82 SO10 TXD1 P151 ANI9 O 45 O P81 SHO RXD1 SDA10 P150 ANI8 O 44 P80 SCK10 SCL10 P27 ANI7 O 43 EVssi P26 ANI6 O 42 O P05 P25 ANI5 O 41 O P06 P24 ANI4 O 40 O P70 KRO SCK21 SCL21 P23 ANI3 O 39 O P71 KR1 SI21 SDA21 P22 ANI2 O 38 O P72 KR2 SO 1 P21 ANI1 AVrcem O 37 O P73 KR3 2 O 36 P74 KR4 INTP8 P130 O 35 O P75 KR5 INTP9 P102 TI06 TO06 34 P76 KR6 INTP10 RXD2 P04 SCK10 SCL10 O 33 P77 KR7 INTP1 1 TXD2 PO3 ANI16 SI10 RxD1 SDA10 32 P67 TI13 TO13 PO2 ANI17 SO10 TxD1 O 81 O 66 112 12 P01 TO00 O 30
66. MHz Basic operation Vop 2 5 0V 3 0 V Normal operation Voo 5 0 V Vpp 3 0 V 24 MHz Notes Normal operation Vpp 5 0 V Voo 3 0 V 16 MHz 93 Normal operation 5 0 V Vpp 3 0 V LS low speed main moi d Note 5 8 MHz 63 Normal operation 3 0 V Voo 2 0 V LV low voltage main mode Note 5 4 MHz 63 Normal operation 3 0 V Voo 2 0 V HS high speed main mode t fux 20 MHz 2 Voo 5 0 V Normal operation Square wave input Resonator connection fux 20 MHz 2 Voo 3 0 V Normal operation Square wave input Resonator connection fux 10 MHz 2 Voo 5 0 V Normal operation Square wave input Resonator connection fux 10 MHz 2 Voo 3 0 V Normal operation Square wave input Resonator connection LS low speed main mo d le Note 5 fux 8 MHze e Vpp 3 0 V Normal operation Square wave input Resonator connection fux 8 2 Voo 2 0 V Normal operation Square wave input Resonator connection Subsystem clock operation fsus 32 768 kHz Note 4 40 C Normal operation Square wave input Resonator connection 32 768 kHz Note 4 25 Normal operation
67. Note 4 Analog input voltage ANI2 to ANI14 AVREFP Internal reference voltage 2 4 V Vpp lt 5 5 V HS high speed main mode Note 5 VecR Temperature sensor output voltage 2 4 V Vpp lt 5 5 V HS high speed main mode Notes are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NE SAS Note 5 Vimps2s Page 113 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 When AVaere lt Voo the MAX values are as follows Overall error Add 1 0 LSB to the MAX value when AVaere Voo Zero scale error Full scale error Add 0 05 FSR to the MAX value when AVnere Voo Integral linearity error Differential linearity error Add 0 5 LSB to the MAX value when AVnere Vo 4 Values when the conversion time is set to 57 ws min and 95 ws max 5 Refer to 2 6 2 Temperature sensor internal reference voltage characteristics R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 114 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 When reference voltage AVneErFP ANIO ADREFP1 0 ADREFPO 1 reference voltage AVREFWANI1 ADREFM 1 target pin ANI16 to ANI26 40 to 85 C 1 6 V lt EVppo 1 lt lt 5 5 V 1 6
68. Nov 15 2013 zeENESAS Page 28 of 194 RL78 G13 1 OUTLINE 1 3 12 80 pin products e 80 pin plastic LQFP 14 x 14 0 65 mm pitch e 80 pin plastic LFQFP 12 x 12 mm 0 5 mm pitch LG 8 amp OF 3 28 lt S E ExXO2 sect Ro 564 _ 2 lt zEo rEgtego x gt S 5 Sm lt hi lt 52869 a SpE oSzo2sz 2 G I OF 25 Doo oo AFAGKFEDHSVVOVE 8 FESLSRATEEMHLSLNT ZZZ Z22 S8A0XS59O TE aee lt lt lt EEQLOXRXOSLSFOLOSS BSR OK Soor tork lt D O st sb 0 QO s NP c sb 10 CO P 10 st QN gt CUM CR Rd er AM ced 10 10 10 O D anaavaAaArAaAaAaAaAaHaHAgaRaAgooHaaAaAgaAaao 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 4241 P152 ANHO O P30 INTPS RTC1HZ SCK11 SCL11 P151 ANI9 5 05 5 150 8 O P06 T106 TO06 P27 ANI7 O P70 KRO SCK21 SCL21 P26 ANI6 O P71 KR1 SI21 SDA 1 25 5 O O P72 KR2 SO21 P24 ANI4 P73 KR3 P23 ANI3 P74 KR4 INTP8 P22 ANI2 O O P75 KRS INTP9 P21 ANI1 AVrerm O I O P76 KR6 INTP10 RXD2 P20 ANIO AVnere I O P77 KR7 INTP11 TXD2 P130 O P67 TH3 TO13 P04 SCK10 SCL10 O P66 TI12 TO12 P03 ANI16 SI10 RxD1 SDA10 P65 TI 1 TO11 P02 ANH 7 SO10 TxD1 O P64 THO TO10 P01 TO00 O O P31 TIOS TOOS INTP4 PCLBUZ
69. O a 4 P147 ANI18 P51 INTP2 S011 P23 ANI3 O O P50 INTP 1 5111 5 11 P22 ANI2 O O P30 INTP3 SCK11 SCL11 P21 ANI1 AVrerm O P70 20 1 O O P 31 TI03 TOO03 INTP 4 P CLBUZO PO1 ANI16 TOOO RxD1 O P62 P00 ANI17 TIO0 TXD1 P61 SDAA0 P120 ANI19 78 P60 SCLAO INDEX MARK OOOOOO Ol ovnuonunsS gt O u x Ec ng n N N ci a Caution Connect the REGC pin to Vss via a capacitor 0 47 to 1 Remarks 1 For pin identification see 1 4 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware 3 Itis recommended to connect an exposed die pad to Vss R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 20 of 194 Nov 15 2013 RL78 G13 1 3 6 36 pin products e 36 pin plastic WFLGA 4 x 4 mm 0 5 mm pitch P60 SCLAO Top View N wo OC O INDEX MARK P121 X1 Bottom View 1 OUTLINE P122 X2 EXCLK P137 INTPO P40 TOOLO P61 SDAAO RESET P120 ANI19 72 8021 P71 SI21 SDA21 P14 RxD2 SI20 SDA20 SCLAO T103 TOO3 P31 T103 TO03 INTP4 PCLBUZO POO TIOO TxD1 P01 TOO0 RxD1 P50 INTP1 S t SDAt1 P70 SCK21 SCL21 P15 PCLBUZ1 SCK20 SCL20 T102 TOO2 P22 ANI2 P20 ANIO AVner
70. O 2 2 2 3 withstand voltage 6 V 16 bit timer 8 channels Watchdog timer 1 channel Real time clock RTC 1 channe 12 bit interval timer IT 1 channel Note 2 Timer output 3 channels 4 channels 4 channels PWM outputs 3 3 PW p PWM outputs 3 P 8 channels PWM outputs 7 tote 3 Note 4 2 lote RTC output Notes 1 In the case of the 4 KB this is about 3 KB when the self programming function and data flash function are used For details see CHAPTER 3 in the RL78 G13 User s Manual Hardware 2 Only the constant period interrupt function when the low speed on chip oscillator clock fi is selected 3 The number of PWM outputs varies depending on the setting of channels in use the number of masters and slaves 6 9 3 Operation as multiple PWM output function in the RL78 G13 User s Manual Hardware 4 When setting to PIOR 1 R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 48 of 194 Nov 15 2013 RL78 G13 Clock output buzzer output 1 OUTLINE 2 2 X90014GSH X9L0LJSH X 0014SH X L0LJSH X80014SH X8L013SH XV0014SH 101469 Xg00L4SHd 10139 X90014SH XOLOLASHY B 1 1 2 2 44 kHz 4 88 kHz 9 76 kHz 1 25 MHz 2 5 MHz 5 MHz 10 MHz Main system clock fva 20 MHz operation 8 10 bit resolution A D converter 6 channels 6 channels 6 channels 8 channels 8 channels 8 channels Serial i
71. O P65 TH 1 TO11 POO TIO0 O 29 O P64 TI10 TO10 P145 TI07 TOO7 28 O P31 TIOS TOOS INTPAPCLBUZO P144 SO30 TxD3 O Q 27 O P63 SDAA1 P143 SI30 RxD3 SDA30 O 26 O P62 SCLA1 91011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Ordooqwiuo t 9 l u0 ox c oa sssoo o 2 lt lt AEEZEOO0Z2OZOUZxEoXD2222321 Ozz zctodorc Ouosozxamg 0 SougBoo0O9s r rxaci OLOQ amp grtod o lt e NN Ox oc a 2S35rak eSr N EX omm 2 Did a x N I Vad 2 g e a ils s amp att e aa a Cautions 1 Make EVsso EVss1 pins the same potential as Vss pin 2 Make Voo pin the potential that is higher than EVppo EVon1 pins EVppo EVpp 3 Connect the REGC pin to Vss via a capacitor 0 47 to 1 Remarks 1 For pin identification see 1 4 Pin Identification 2 When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced it is recommended to supply separate powers to the EVppo and EVpp1 pins and connect the Vss EVsso and EVsst pins to separate ground lines 3 Functions in parentheses in the above figure can be assigned via settings in the peripheral redirection register PIOR Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 R
72. P67 P70 to P77 P80 to P87 P90 to P97 P100 P101 P110 to P117 P146 P147 Per pin Total of all pins P20 to P27 P150 to P156 Output current low Per pin to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Total of all pins 170 mA to P04 P07 P32 to P37 P40 to P47 P102 to P106 P120 P125 to P127 P130 P140 to P145 P05 P06 P10 to P17 P30 P31 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 P101 P110 to P117 P146 P147 Per pin Total of all pins P20 to P27 P150 to P156 1 5 Operating ambient temperature In normal operation mode In flash memory programming mode 40 to 85 Storage temperature 65 to 150 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins R01DS0131EJ0310 Rev 3 10 Nov 15 2013 ztENESAS Page 56 of 194 RL78 G13
73. P67 P70 to P77 P80 to P87 P90 to P97 P100 P101 P110 to P117 P146 P147 Per pin P20 to P27 P150 to P156 Total of all pins Output current low Per pin to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Total of all pins POO to P04 P07 P32 to P37 170 mA P40 to P47 P102 to P106 P120 P125 to P127 P130 P140 to P145 P05 P06 P10 to P17 P30 P31 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 P101 P110 to P117 P146 P147 Per pin P20 to P27 P150 to P156 1 Total of all pins 5 HR Operating ambient In normal operation mode 40 to 105 temperature In flash memory programming mode Storage temperature 65 to 150 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 125 of 194 Nov 15 2013 RL78 G13 3 2 Oscillator Cha
74. QE NEC S AS Page 181 of 194 Nov 15 2013 RL78 G13 4 PACKAGE DRAWINGS 4 7 40 pin Products R5F100EAANA R5F100ECANA R5F100EDANA R5F100EEANA R5F100EFANA R5F100EGANA R5F100EHANA R5F101EAANA R5F101ECANA R5F101EDANA R5F101EEANA R5F101EFANA R5F101EGANA R5F101EHANA R5F100EADNA R5F100ECDNA R5F100EDDNA R5F100EEDNA R5F100EFDNA R5F100EGDNA R5F100EHDNA R5F101EADNA R5F101ECDNA R5F101EDDNA R5F101EEDNA R5F101EFDNA R5F101EGDNA R5F101EHDNA R5F100EAGNA R5F100ECGNA R5F100EDGNA R5F100EEGNA R5F100EFGNA R5F100EGGNA R5F100EHGNA JEITA Package Code RENESAS Code MASS g P HWQFN40 6x6 0 50 PWQNOO40KC A P40K8 50 4B4 3 009 DETAIL OF A PART E E EN UNIT mm ITEM DIMENSIONS D 6 00 0 05 6 00 0 05 EXPOSED DIE PAD A 0 75 0 05 0 05 9 0 25 0 07 0 50 Lp 0 40 0 10 x 0 05 y 0 05 ITEM D2 E2 MIN INOMIMAX MIN INOM MAX EXPOSED DIE PAD 4 45 4 50 4 55 4 45 4 50 4 55 VARIATIONS 2012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 182 of 194 Nov 15 2013 RL78 G13 4 PACKAGE DRAWINGS 4 8 44 pin Products R5F100FAAFP R5F100FCAFP R5F100FDAFP JR5F100FEAFP R5F100FFAFP R
75. R5F101PHAFA VO R5F101PJAFA VO R5F101PKAFAzVO R5F101PLAFA VO R5F101PFAFA X0 R5F101PGAFA X0 R5F101PHAFA XO R5F101PJAFA X0 R5F101PKAFA X0 R5F101PLAFA X0 R5F101PFDFA VO R5F101PGDFA VO R5F101PHDFA VO R5F101PJDFA VO R5F101PKDFAzVO R5F101PLDFA VO R5F101PFDFA X0 R5F101PGDFA X0 R5F101PHDFA XO R5F101PJDFA X0 R5F101PKDFA X0 R5F101PLDFA X0 Note For the fields of application refer to Figure 1 1 Part Number Memory Size and Package of RL78 G13 Caution The ordering part numbers represent the numbers at the time of publication For the latest ordering part numbers refer to the target product page of the Renesas Electronics website R01DS0131EJ0310 Rev 3 10 Nov 15 2013 ztENESAS Page 14 of 194 RL78 G13 Pin count 128 pins 128 pin plastic LFQFP 14 x 20 mm 0 5 mm pitch Package Table 1 1 List of Ordering Part Numbers Data flash Mounted Fields of Application Note Ordering Part Number R5F100SHAFB V0 R5F100SJAFB VO R5F100SKAFB VO0 R5F100SLAFB VO R5F100SHAFB XO R5F100SJAFB XO R5F100SKAFB X0 R5F100SLAFB X0 R5F100SHDFB VO R5F100SJDFB VO R5F100SKDFB V0 R5F100SLDFB VO R5F100SHDFB XO R5F100SJDFB XO R5F100SKDFB X0 R5F100SLDFB 2XO 1 OUTLINE 12 12 Not mounted R5F101SHAFB VO R5F101SJAFB VO R5F101SKAFB V0 R5F101SLAFBZVO R5F101SHAFB XO R5F101SJAFB XO R5F101SKAFB X0 R5F101SLAFB X0 R5F101SHDFB VO0 R5F101SJDFB VO R5F101SKDFB V0 R5F101SLDFB 2VO R5F10
76. RAM CONTROL DETECTOR SI01 P74 SO01 P73 SCK11 P30 RESET CONTROL SI 1 P50 SO11 P51 SCLOO P10 Voo Vss TOOLRxD P11 ON CHIP DEBUG TOOLO P40 SDA00 P11 TOOLTxD P12 SCL01 P75 SVETEM RESET SDAO1 P74 CONTROL X1 P 121 SCL11 P30 X2 EXCLK P122 SDA11 P50 HIGH SPEED ON CHIP XT1 P123 SDAAO P61 SDAAO P13 OSCILLATOR SERIAL XT2 EXCLKS P124 INTERFAGETIGA0 SCLAO P60 SCLAO P14 VOLTAGE UNIT1 2ch REGULATOR BUZZER OUTPUT RxD2 P14 RxD2 P76 PCLBUZO P140 PCLBUZO P31 RxD2 P14 RxD2 P76 TxD2 P13 TxD2 P77 CLOCK OUTPUT PCLBUZ1 P15 1 1 7 CONTROL 5 INTP t P5O 20 15 CET INTP2 P51 SI20 P14 MULTIPLIERS CRC NTP3 P30 SO20 P13 DIVIDER INTERRUPT CZ INTP4 P31 RS CONTROL INTP5 P16 SCK21 P70 ACCUMULATOR INTP6 P140 SO21 P72 DIRECT MEMORY SCL20 P15 ACCESS CONTROL NTP8 P74 to SDA20 P14 SCL21 P70 BCD SDA21 P71 ADJUSTMENT Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral redirection register PIOR Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 43 of 194 Nov 15 2013 RL78 G13 1 5 11 64 pin p TI00 P00 TO00 P01 01 1 16 TIO2 TOO2 P17 TIO2 TOO2 P15 103 003 31 TI03 TO03 P14 TI04 TO04 P42 T104 TO04 P13 TI05 TO05
77. SI11 SDA11 9101112 INDEX MARK OOOOOOOO00000 OON MN Ged mud ud mud ud rmn lt O GFSCSONNNA 5202 A lt O O lt O 6 Rg UOMO UU Sa had oad O i r x da q agevyvyagg X A S S n X x FUN SS U m ano zat 2 Sb KR x Cz SU one RE a x ETT EI n E z H 5 amp 2 Caution Connect the REGC to Vss via a capacitor 0 47 to 1 LF Remarks 1 For pin identification see 1 4 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware 3 It is recommended to connect an exposed die pad to Vss R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 25 of 194 Nov 15 2013 RL78 G13 1 OUTLINE 1 3 10 52 pin products e 52 pin plastic LQFP 10 x 10 mm 0 65 mm pitch P27 ANI7 P26 ANI6 P25 ANI5 P24 ANI4 P23 ANI3 P22 ANI2 P21 ANI1 AVrerm P20 ANIO AVnerP P130 P03 ANI16 RxD1 P0O2 ANI17 TxD1 P01 TOOO POO TIOO O P11 SIO0 RXDO TOOLRxD SDAOO TIOG TOO6 P12 SO00 TxDO TOOLTxD TIO5 TOO05 P13 TxD2 SO20 SDAAO TIO4 TO04 O P14 RxD2 SI20 SDA20 SCLAO TIO3 TOO3 O P15 PCLBUZ1 SCK20 SCL20 T102 TO02 O P16 TIO1 TOO1 INTP5 RXDO O P17 TIO2 TOO2 TXDO O P51 INTP2 SO11 O P30 INTP3
78. Square wave input Resonator connection fux 10 MHz Vpp 3 0 V Normal operation Square wave input Resonator connection LS low speed main m od e Note 5 fux 8 MHz 2 Vpp 3 0 V Normal operation Square wave input Resonator connection fux 8 MHze e 2 Vpp 2 0 V Normal operation Square wave input Resonator connection Subsystem clock operation fsue 32 768 kHz Note 4 Ta 40 C Normal operation Square wave input Resonator connection 32 768 kHz Note 4 Ta 25 C Normal operation Square wave input Resonator connection 32 768 kHz Note 4 Ta 50 C Normal operation Square wave input Resonator connection 32 768 kHz Note 4 Ta 70 C Normal operation Square wave input Resonator connection 32 768 kHz Note 4 85 Notes and Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Normal operation Square wave input Resonator connection amp SPS B Page 71 of 194 RL78 G13 Notes 1 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Total current flowing into EVppo and EVoo1 including the input leakage current flowing when the level of the input pin is fixed to EVppo and EVpp1 Vss EVss
79. TO02 SO1 1 P50 INTP1 SH 1 SDA11 P30 INTP3 SCK11 SCL11 P31 T103 TO03 INTP4 PCLBUZO P21 ANI1 AVrerm Ol 19 P20 ANIO AVnere O P01 ANI16 TOOO RxD1 O 7 TIOO TxD1 O RESET O P60 SCLAO INDEX MARK OOOOOO e 5 x 9 Z x o x aq N A Caution Connect the REGC pin to Vss via a capacitor 0 47 to 1 LF Remarks 1 For pin identification see 1 4 Pin Identification 2 Itis recommended to connect an exposed die pad to Vss R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 17 of 194 Nov 15 2013 RL78 G13 1 OUTLINE 1 3 3 25 pin products e 25 pin plastic WFLGA 3 x 3 mm 0 50 mm pitch Top View Bottom View N C A INDEX MARK INDEX MARK P40 TOOLO RESET P01 ANI16 P22 ANI2 P147 ANI18 TOO00 RxD1 5 5 P122 X2 P137 INTPO POO ANI17 P21 ANI1 P10 SCKO0 4 EXCLK TIOO TxD1 AVREFM SCLOO 4 P121 X1 P20 ANIO 12 5000 11 5100 3 AVREFP 3 TOOLTxD TOOLRxD SDAO0 P30 INTP3 P17 TIO2 P50 INTP1 2 SCK11 SCL11 TO02 SO11 SI11 SDA11 2 P60 SCLAO P61 SDAAO P31 T103 P16 TIO1 P130 1 TOOS INTP4 TOO1 INTP5 1 PCLBUZO Caution Connect the REGC pin to Vss via a capacitor 0 47 to 1 Remark For pin identification see 1 4 Pin Identification R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 18 of 194 Nov 15 2013 RL78 G13 1 OUTLINE 1 3 4 30 pin products e 30 pin plastic LSSOP 7 62 mm 300 0 65 mm pitch O 2
80. TxD1 P00 SCKO00 P10 100 11 000 12 SCK01 P75 101 74 SO01 P73 SCK11 P30 SI11 P50 SO11 P51 SCLOO P10 SDAOO P11 SCLO01 P75 SDAO1 P74 SCL11 P30 SDA11 P50 SERIAL ARRAY UNIT 2ch RxD2 P14 TxD2 P13 SCK20 P15 SI20 P14 SO20 P13 SCK21 P70 SI21 P71 021 72 SCL20 P15 SDA20 P14 SCL21 P70 SDA21 P71 RL78 D CODE FLASH MEMORY CPU D DATA FLASH MEMORY RAM Vss TOOLRxD P11 TOOLTxD P12 SDAAO P61 SDAAO P13 SERIAL INTERFACE ICAO SCLA0 P60 SCLA0 P14 BUZZER OUTPUT PCLBUZO P140 PCLBUZO P31 CLOCK OUTPUT PCLBUZ1 P15 CONTROL MULTIPLIER amp CRC DIVIDER MULITIPLY ACCUMULATOR DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT E s K gt P00 P01 lt roi Kx P10 to P17 lt 27 lt rows K gt ss P31 C Cube 41 lt rows P51 Kj rows P60 to P63 Kj port Kc P70 to P75 4 JP121 to P124 P130 PORT 13 P137 140 PORT 14 P146 P147 H ANIO P20 to ANI7 P27 ANI18 P147 ANI19 P120 20 AVnerv P21 KEY RETURN s JKR0 P70 to KR5 P75 POWER ON RESET VOLTAGE DETECTOR POR LVD CONTROL RESET CONTROL lt ON CHIP DEBUG TOOLO P40 SYSTEM RESET CONTROL X1 P121 X2 EXCLK P122 ON CHIP XT1 P123 OSCILLATOR XT2 EXCLKS P124 VOLTAGE REGULATOR PEGG RxD2 P14 INTPO P137 INTP1 P50
81. U0 R5F101GKANAZUO R5F101GLANA U0 R5F101GAANA WO R5F101GCANA WO R5F101GDANA WO R5F101GEANA WO R5F101GFANA WO R5F101GGANA WO R5F101GHANAZWO R5F101GJANA WO R5F101GKANA WO R5F101GLANA WO0 R5F101GADNA U0 R5F101GCDNAZUO R5F101GDDNA UO R5F101GEDNA U0 R5F101GFDNA U0 R5F101GGDNAZUO R5F101GHDNA U0 R5F101GJDNA U0 R5F101GKDNA UO R5F101GLDNA U0 R5F101GADNA WO R5F101GCDNA WO R5F101GDDNA ZWO R5F101GEDNA WO R5F101GFDNA WO R5F101GGDNA WO R5F101GHDNA ZWO R5F101GJDNA WO R5F101GKDNAZWO R5F101GLDNAZWO Note For the fields of application refer to Figure 1 1 Part Number Memory Size and Package of RL78 G13 Caution The ordering part numbers represent the numbers at the time of publication For the latest ordering part numbers refer to the target product page of the Renesas Electronics website R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NE SAS Page 9 of 194 RL78 G13 1 OUTLINE Table 1 1 List of Ordering Part Numbers 7 2 Package Data flash Fields of Ordering Part Number Application Note 52 pin plastic LQFP Mounted R5F100JCAFA VO R5F100JDAFA V0 R5F100JEAFA VO 10 x 10 mm 0 65 R5F100JFAFA VO R5F100JGAFA VO R5F100JHAFA VO mm pitch R5F100JJAFA VO R5F100JKAFA VO R5F100JLAFA VO R5F100JCAFA X0 R5F100JDAFA X0 R5F100JEAFA XO R5F100JFAFA X0 R5F100JGAFA X0 R5F100JHAFA XO R5F100JJAFA X0 R5F100JKAFA X0 R5F100JLAFA X0O R5F100JCDFAzVO R5F100JDDFA V0 R5F100JEDFA VO R5F100JFDFA V0 R5F100JGDF
82. V lt Vo 4 0 V Cb 50 pF Rb 2 7 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V 50 pF Rb 2 7 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V Cb 100 pF Rb 2 8 KQ 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V 100 pF Rb 2 7 KQ 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 2 C 100 pF Rb 5 5 21 NESAS Page 106 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 10 Communication at different potential 1 8 V 2 5 V 3 V simplified mode 2 2 Ta 40 to 85 C 1 8 V lt EVppo EVpni lt lt 5 5 V Vss EVsso EVssi 0 V Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX Data setup time tsu DAT 4 0 V EVppo 5 5 V 1 fuck 1 fuck 1 fuck kHz reception 2 7V lt Vo lt 4 0V 135 Note 190 190 50 pF Rb 2 7 3 2 7 V EVppo lt 4 0 V 1 fuck 1 fuck 1 kHz 2 3 V lt Vo lt 2 7 V 135 Note 190 4 190 Note 3 Note 3 50 pF Rb 2 7 3 4 0 V EVppo lt 5 5 V 1 1 1 kHz 2 7 V lt Vo 4 0 V 190 ete 190 4 190 Note 3 Note 3 Cb 100 pF Re 2 8 3 2 7 V EVppo 4 0 V 1 fuck 1 fuck 1 fuck kHz 2 3 V lt Vo lt 2 7 V 190 Nete 190 4 190 Note 3 Not
83. When duty lt 70 ete3 2 4 V lt EVopo lt 5 5 V 23 9 ee 4 0 V lt EVppo lt 5 5 V 2 7 V lt EVppo lt 4 0 V 2 4 V lt EVppo lt 2 7 V 4 0 V lt EVppo lt 5 5 V 2 7 V lt EVbppo lt 4 0 V 2 4 V lt EVppo lt 2 7 V Total of all pins 2 4 V lt EVppo lt 5 5 V When duty lt 70 3 Per pin for P20 to P27 P150 to P156 2 4 V lt Voo lt 5 5 V Total of all pins 2 4 V lt Voo lt 5 5 V When duty lt 70 3 Value of current at which the device operation is guaranteed even if the current flows from the EVppo Vpp pins to an output pin Do not exceed the total current value Specification under conditions where the duty factor lt 70 The output current value that has changed to the duty factor gt 70 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n e Total output current of pins x 0 7 n x 0 01 Example Where 80 and 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA However the current that is allowed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin POO P02 to P04 P10 to P15 P17 P43 to P45 P50 P52 to P55 P71 P74 P80 to P82 P96 and P142 to P144 do not output high level in N ch open drain mode Unless specified otherwise t
84. ambient temperature Ta 40 to 85 C A Consumer applications D Industrial applications R5F101Sx Ta 40 to 105 Industrial applications Note The illegal instruction is generated when instruction code FFH is executed Reset by the illegal instruction execution not issued by emulation with the in circuit emulator or on chip debug emulator R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 53 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 ELECTRICAL SPECIFICATIONS A D TA 40 to 85 C This chapter describes the electrical specifications for the products A Consumer applications Ta 40 to 85 C and D Industrial applications TA 40 to 85 Cautions 1 The RL78 microcontrollers have an on chip debug function which is provided for development and evaluation Do not use the on chip debug function in products designated for mass production because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used and product reliability therefore cannot be guaranteed Renesas Electronics is not liable for problems occurring when the on chip debug function is used 2 With products not provided with an EVon 1 EVsso or EVss pin replace and EVon with or replace EVsso and EVss with Vss 3 The pins mounted depend on the product Refer to 2 1 Port Function to 2 2 1 With functions for each prod
85. communication at same potential CSI mode Modification of description in 3 During communication at same potential CSI mode Modification of table note 1 and caution in 4 During communication at same potential simplified mode Modification of table note 1 and caution in 5 Communication at different potential 1 8 V 2 5 V 3 V UART mode 1 2 Modification of table notes 2 to 6 caution and remarks 1 to 4 in 5 Communication at different potential 1 8 V 2 5 V 3 V UART mode 2 2 Modification of table in 6 Communication at different potential 1 8 V 2 5 V 3 V CSI mode 1 3 Modification of table and caution in 6 Communication at different potential 1 8 V 2 5 V 3 V CSI mode 2 3 Modification of table caution and remarks 3 and 4 in 6 Communication at different potential 1 8 V 2 5 V 3 V CSI mode 3 3 Modification of table and caution in 7 Communication at different potential 1 8 V 2 5 V 3 V CSI mode Date Aug 02 2013 Nov 15 2013 Description Page 163 164 165 166 166 167 167 168 169 170 171 172 173 173 174 175 Summary Modification of table in 8 Communication at different potential 1 8 V 2 5 V 3 V simplified C mode 1 2 Modification of table note 1 and caution in 8 Communication at different potential 1 8 V 2 5 V 3 V simplified mode 2 2 Modification of table in 3 5 2 Serial interface IICA Mo
86. connection diagram during communication at different potential lt Master gt SCKp RL78 microcontroller 51 User device Remarks 1 Re O Communication line SCKp SOp pull up resistance Communication line SCKp SOp load capacitance Ve V Communication line voltage 2 p CSI number p 00 01 10 20 30 31 m Unit number n Channel number mn 00 01 02 10 12 13 0 PIM and POM number g 0 1 4 5 8 14 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 4 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 158 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 Output data CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcy1 Output data Remarks 1 p CSI number p 00 01 10 20 30 31 m Unit number m 00 01 02 10 12 13 n Channel number
87. g POMg Remarks 1 p CSI number p 00 01 10 11 20 21 30 31 m Unit number m 0 1 n Channel number n 0 to 3 g PIM number g 0 1 4 5 8 14 2 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 86 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C CSI mode connection diagram during communication at same potential SCKp SCK RL78 SO User device S microcontroller SOp SI CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcy1 2 tKu1 2 1 1 2 tkso1 2 P CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcy1 2 tkso1 2 X R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 87 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Remarks 1 p CSI number p 00 01 10 11 20 21 30 31 2 m Unit number n Channel number mn 00 to 03 10 to 13 5 During communication at same potential simplified Pc mode 1 2 Ta 40 to 85 C 1 6 V lt EVppo 1 lt lt 5
88. kHz 32 768 kHz Subsystem clock fsus 32 768 kHz operation 8 10 bit resolution A D converter 12 channels 12 channels 9 channels 10 channels 10 channels Serial interface 40 pin 44 pin products e CSI 1 channel simplified 1 channel UART 1 channel e CSI 1 channel simplified 1 channel UART 1 channel e CSI 2 channels simplified C 2 channels UART UART supporting LIN bus 1 channel 48 pin 52 pin products e CSI 2 channels simplified IPC 2 channels UART 1 channel e CSI 1 channel simplified I C 1 channel UART 1 channel e CSI 2 channels simplified IPC 2 channesl UART UART supporting LIN bus 1 channel 64 pin products e CSI 2 channels simplified IC 2 channels UART 1 channel e CSI 2 channels simplified IC 2 channels UART 1 channel e CSI 2 channels simplified IFC 2 channels UART UART supporting LIN bus 1 channel bus 1 channel 1 channel 1 channel 1 channel 1 channel Multiplier and divider multiply accumulator e 16 bits x 16 bits 32 bits Unsigned or signed 32 bits 32 bits 32 bits Unsigned e 16 bits x 16 bits 32 bits 32 bits Unsigned or signed DMA controller 2 channels Vectored interrupt sources Internal 27 External 7 Key interrupt 4 Reset by RESET pin Internal reset by watchdog timer Internal reset by power on reset Internal reset by voltage detector I
89. lt 2 7 V 50 pF Rb 2 7 KQ 4 0 V lt EVppo lt 5 5 V 2 7 V lt lt 4 0 V Cb 100 pF Rb 2 8 2 7 V lt EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V 100 pF Rb 2 7 KQ 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo 2 0 V 100 pF Ro 5 5 Hold time when SCLr L 4 0 V EVpoo lt 5 5 V 2 7 V Ve x 4 0 V Co 50 pF Re 2 7 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V 50 pF Rb 2 7 KQ 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V 100 pF Rb 2 8 KQ 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V 100 pF Rb 2 7 KQ 2 4 V EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V 100 pF Rb 5 5 KQ Hold time when SCLr H 4 0 V EVppo 5 5 V 2 7 V lt Vo lt 4 0 V 50 pF Rb 2 7 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V Co 50 pF Rb 2 7 4 0 V lt EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V Cb 100 pF Rb 2 8 KQ 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V 100 pF Rb 2 7 kQ 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V 100 pF Rb 5 5 Notes and Caution are listed on the next page and Remarks are listed on the page after the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 zeENESAS Page 163 of 194 RL78 G13 3 ELECTRICAL SPECIFICATI
90. lt 5 5 V 16 MHz 2 4 V lt Voo lt 5 5 V LS low speed main mode 8 MHz 1 8 V x Vop lt 5 5 V LV low voltage main mode 4 MHz 1 6 V x Voo x 5 5 V Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 81 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C UART mode connection diagram during communication at same potential TxDq RL78 microcontroller User device RxDq UART mode bit width during communication at same potential reference 1 Transfer rate High Low bit width Baud rate error tolerance TxDq RxDq Remarks 1 UART number q 0 to 3 g PIM and POM number g 0 1 8 14 2 Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 82 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 During communication at same potential CSI mode master mode SCKp internal clock output corresponding CSIOO only Ta 40 to 85 C 2 7 V lt EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V HS high speed main Mo
91. lt Vo lt 2 0 V 2 Co 30 pF Re 5 5 Notes 1 When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 Use it with EVppo gt Vb Caution Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SOp and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 99 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 CSI mode connection diagram during communication at different potential Master SCKp RL78 Sip User device microcontroller SOp Remarks 1 Re O Communication line SCKp SOp pull up resistance Communication line SCKp SOp load capacitance Ve V Communication line voltage 2 p CSI number p 00 01 10 20 30 31 m Unit number n Channel number mn 00 01 02 10 12 13 g PIM and POM number g 0 1 4 5 8 14 3 Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 4 CSIO1 of 48 52 64 pin products and CSI11 a
92. main main Mode main Mode Mode MIN MAX MAX MAX SCKp cycle time 40V EVoo lt 5 5 V 24 MHz lt fuck 14 ns 27V Vox40V fuck 20 MHz lt fuck 24 MHz 12 ns fuck 8 MHz lt fuck lt 20 MHz 10 ns fuck 4 MHz lt fuck lt 8 MHz 8 fuck 16 ns fuck lt 4 MHz 6 fuck 10 10 ns fuck 2 7 V lt EVpr lt 4 0 V 24 MHz lt 20 ns 23V lt W lt s27V fuck 20 MHz lt fuck 24 MHz 16 ns fuck 16 MHz lt fuck 20 MHz 14 ns fuck 8 MHz lt fuck lt 16 MHz 12 ns fuck 4 MHz lt fuck lt 8 MHz 8 fuck 16 ns fuck 4 MHz 6 fuck 10 10 ns fuck 1 8 V lt lt 3 3 V 24 MHz lt fuck 48 ns 1 6 V lt Vo lt 2 0 V Note fuck i 20 MHz lt fuck lt 24 MHz 36 ns fuck 16 MHz lt fuck lt 20 MHz 32 ns fuck 8 MHz lt fuck 16 MHz 26 ns fuck 4 MHz fuck lt 8 MHz 16 16 ns fuck fuck 4 MHz 10 10 10 ns fuck fuck Notes and Caution are listed on the next page and Remarks are listed on the page after the next page R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 102 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 9 Communication at different potential 1 8 V 2 5 V 3 V CSI mode slave mode SCKp external clock
93. maximum value of Cb communication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Fast mode Cb 320 pF Rb 1 1 KQ R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 111 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D 40 to 85 3 fast mode plus Ta 40 to 85 C 1 6 V lt EVppo lt Von lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode SCLAO clock frequency fsc Fast mode plus 27 V lt lt 5 5 V fcuk gt 10 MHz Setup time of restart tsu sta 2 7 V lt EVppo lt 5 5 V condition Note tHo sTa 2 7 lt lt 5 5 V Hold time Hold time when SCLAO 2 7 V lt EVomo 5 5 V E Hold time when SCLAO 2 7 V lt EVppo 5 5 V Data setup time tsupar 2 7 V lt EVppo lt 5 5 V reception Data hold time tlHp paT 2 7 V lt EVppo lt 5 5 V transmission e Setup time of stop tsusro 2 7 V lt EVppo lt 5 5 V condition Bus free time tBuF 2 7 V lt EVppo lt 5 5 V Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MAX of is during normal transfer and a wait state is inserted in the ACK acknowledge timing
94. n 0 2 g PIM and POM number g 0 1 4 5 8 14 2 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential R01DS0131EJ0310 Rev 3 10 RENESAS Nov 15 2013 Page 159 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 7 Communication at different potential 1 8 V 2 5 V 3 V CSI mode slave mode SCKp external clock input Ta 40 to 105 2 4 V lt EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V HS high speed main Mode Parameter Note 1 SCKp cycle time 40VxEVo x 5 5 V 2 7 V lt Vo lt 4 0 V Conditions 24 MHZ lt fuck MIN 28 20 MHz lt fuck 24 MHz 24 fuck 8 MHz lt fuck lt 20 MHz 20 fuck 4 MHz fuck lt 8 MHz 16 fuck fuck 4 MHz 12 fuck 2 7 V lt lt 4 0 V 23V lt Vb lt s2 7V 24 MHz lt fuck 40 fuck 20 MHz lt fuck 24 MHz 32 fuck 16 MHz lt fuck lt 20 MHz 28 8 MHz fuck lt 16 MHz 24 fuck 4 MHz lt fuck lt 8 MHz 16 fuck fuck 4 MHz 12 fuck 2 4 V lt EVpro lt 3 3 24 MHz lt fuck 96 fuck V 20 MHz lt fuck lt 24 MHz 72 16 5 52 0 46 MHz lt fuck lt 20 MHz 64 fuck 8 MHz lt fuck lt 16 MHz 52 fuck 4 MHz lt fuck lt 8 MHz 32 fuck fu
95. not input signals or an pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device Notice 1 Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 2 Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein 3 Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics product
96. of pins P00 P02 to P04 P10 to P15 P17 P43 to P45 P50 P52 to P55 P71 P74 P80 to P82 P96 and P142 to P144 is EVppo even in the N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the R01DS0131EJ0310 Rev 3 10 Nov 15 2013 port pins ztENESAS Page 60 of 194 RL78 G13 Ta 40 to 85 C 1 6 V lt EVppo 1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 4 5 Output voltage high 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Conditions P00 to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 4 0 V EVppo lt 5 5 V lou 210 0 mA EVppo 1 5 4 0 V EVppo lt 5 5 V 3 0 mA EVppo 0 7 2 7 V lt EVopo 5 5 V lou 2 0 mA EVppo 0 6 1 8 V lt EVppo 5 5 V lou 1 5 mA EVppo 0 5 1 6 V EVppo lt 5 5 V lou 1 0 mA EVppo 0 5 P20 to P27 P150 to P156 1 6 V lt lt 5 5 V lone 100 LA Voo 0 5 Output voltage low Caution P00 P02 to P04 P10 to P15 P17 P43 to P45 P50 P52 to P55 P71 P74 P80 to P82 P96 and POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P
97. only 2 2 Ta 40 to 85 C 2 7 V lt EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX Slp setup time 4 0 V EVppo 5 5 V to SCKpL Note 2 7 V lt Ve lt 4 0 V Cb 20 pF Rb 1 4 KQ 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V Co 20 pF Rb 2 7 Slp hold time 4 0 V EVppo lt 5 5 V from SCKp ete 2 7 Vo 4 0 V Cb 20 pF Rb 1 4 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V Cb 20 pF Rb 2 7 Delay time from SCKpT 4 0 V lt EVppo lt 5 5 V to 2 7 V lt Vo lt 4 0 V SOp output Co 20 pF Ro 1 4 KQ 2 7 V EVpoo lt 4 0 V 2 3 V lt Vo lt 2 7 V Cb 20 pF Rb 2 7 Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 2 When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Caution Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks 1 Ro O Communication line SCKp SOp pull up resistance
98. pin to Vss via a capacitor 0 47 to 1 uF This value regulates the absolute maximum rating of the REGC pin Do not use this pin with voltage applied to it 2 Must be 6 5 V or lower 3 Do not exceed AVrer 0 3 V in case of A D conversion target Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remarks 1 Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 2 AVe side reference voltage of the A D converter 3 Vss Reference voltage R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 55 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Absolute Maximum Ratings TA 25 2 2 Parameter Output current high Per pin Conditions to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Ratings Total of all pins 170 mA to P04 P07 P32 to P37 P40 to P47 P102 to P106 P120 P125 to P127 P130 P140 to P145 P05 P06 P10 to P17 P30 P31 P50 to P57 P64 to
99. stages 1 63 V to 3 98 V 14 stages e Rising edge e Falling edge On chip debug function Provided Power supply voltage Voo 1 6 to 5 5 V Operating ambient temperature Ta 40 to 85 C A Consumer applications D Industrial applications Ta 40 to 105 C G Industrial applications Note The illegal instruction is generated when instruction code FFH is executed Reset by the illegal instruction execution not issued by emulation with the in circuit emulator or on chip debug emulator R01DS0131EJ0310 Rev 3 10 Nov 15 2013 ztENESAS Page 49 of 194 RL78 G13 1 OUTLINE 40 pin 44 pin 48 pin 52 pin 64 pin products Caution This outline describes the functions at the time when Peripheral I O redirection register PIOR is set to 00H 1 2 X300148H X3l0LJ4Su X30014SH N 10146 X600148H N 10146 001499 XPLOLASH 100146 N xiLoLdsd Code tlash memory KB 16 to 192 16 to 51 16 to 51 32 to 512 32 to 51 Data flash memory KB 4108 4to 8 _ 4108 4108 4108 RAM KB 2 to 16 1 2 to 32 2 to 328 2 to 328 2 to 328 Address space 1 MB Main system High speed system X1 crystal ceramic oscillation external main system clock input EXCLK clock clock 1 to 20 MHz 2 7 to 5 5 V 1 to 8 MHz Voo 1 8 to 2 7 V 1 to 4 MHz Vpp 1 6 to 1 8 V High speed on chip HS High speed main mode 1 to 32 MHz Voo
100. time clock correction clock 1 Hz output Receive data Serial clock input output Serial clock output peripheral SDAO1 SDA10 SDA11 to Key return SDA20 SDA21 SDA30 POO to P07 Port 0 SDA31 Serial data input output P10 to P17 Port 1 5100 101 SI10 5111 P20 to P27 Port 2 120 121 5130 5131 Serial data input P30 to P37 Port 3 000 5001 010 P40 to P47 Port 4 011 020 021 P50 to P57 Port 5 030 SO31 Serial data output P60 to P67 Port 6 TIOO to TIO7 P70 to P77 Port 7 TI10 to Timer input P80 to P87 Port 8 00 to TOO7 P90 to P97 Port 9 TO10 to TO17 Timer output P100 to P106 Port 10 TOOLO Data input output for tool P110 to P117 Port 11 TOOLRxD TOOLTxD Data input output for external device P120 to P127 Port 12 TxDO to TxD3 Transmit data P130 P137 Port 13 Voo Power supply P140 to P147 Port 14 Vss Ground P150 to P156 Port 15 X1 X2 Crystal oscillator main system clock PCLBUZO PCLBUZ1 Programmable clock XT1 XT2 Crystal oscillator subsystem clock output buzzer output R01DS0131EJ0310 Rev 3 10 21 NESAS Page 33 of 194 RL78 G13 1 OUTLINE 1 5 Block Diagram 1 5 1 20 pin products TIMER ARRAY UNIT 8ch TI00 P00 TO00 P01 C PORT 1 5 5P10to P12 P16 P17 eee lt Port2 3 gt P20 to P22 TIO2 TO02 P17 PORT12 2 P121 P122 C PORT 13
101. voltage 2 4 V lt Vpp lt 5 5 V HS high speed main mode ztENESAS Note 4 Vimps2s Page 167 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 When lt Voo the MAX values are as follows Overall error Add 1 0 LSB to the MAX value when AVaere Vpp Zero scale error Full scale error Add 0 05 FSR to the MAX value when AVnere Voo Integral linearity error Differential linearity error Add 0 5 LSB to the MAX value when AVnere Voo 4 Refer to 3 6 2 Temperature sensor internal reference voltage characteristics R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 168 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 2 When reference voltage AVnErP ANIO ADREFP1 0 ADREFPO 1 reference voltage AVrerm ANI1 ADREFM 1 target pin ANI16 to ANI26 Ta 40 to 105 C 2 4 V lt EVppo 1 lt lt 5 5 V 2 4 V lt lt lt 5 5 V Vss EVsso EVssi 0 V Reference voltage AVrerp Reference voltage AVrerm 0 V Parameter Resolution Conditions Overall error 10 bit resolution EVppo lt AVnerp ots 3 4 2 4 V AVnerP lt 5 5 V Conversion time 10 bit resolution Target pin ANI16 to ANI26 3 6 V lt
102. 0 07 0 50 0 05 b 0 24 0 05 0 08 2 uty y1 0 20 ZD 0 50 b ZE 0 50 LAND PAD 0 34 0 05 APERTURE OF 0 365 0 05 H RO 165 0 05 SOLDER RESIST 0 33 0 05 0 215 0 05 0 43 0 05 2012 Renesas Electronics Corporation All rights reserved RO1DS0131EJ0310 Rev 3 10 ztENESAS Page 178 of 194 Nov 15 2013 RL78 G13 4 PACKAGE DRAWINGS 4 4 30 pin Products R5F100AAASP R5F100ACASP R5F100ADASP R5F100AEASP R5F100AFASP R5F100AGASP R5F101AAASP R5F101ACASP R5F101ADASP R5F101AEASP R5F101AFASP R5F101AGASP R5F100AADSP R5F100ACDSP R5F100ADDSP R5F100AEDSP R5F100AFDSP R5F100AGDSP R5F101AADSP R5F101ACDSP R5F101ADDSP R5F101AEDSP R5F101AFDSP R5F101AGDSP R5F100AAGSP R5F100ACGSP R5F100ADGSP R5F100AEGSP R5F100AFGSP R5F100AGGSP JEITA Package Code RENESAS Code Previous Code MASS 9 P LSSOP30 0300 0 65 PLSP0030JB B S30MC 65 5A4 3 0 18 detail of lead end F G Y 1 T Y i i E E U ITEM MILLIMETERS LK A 9 85 0 15 0 45 0 65 T P 0 08 0 24 0 07 0 10 05 1 3 0 1 1 2 8 1 0 2 6 1 0 2 1 0 0 2 0 17 0 03 0 5 0 13 0 10 5 3 0 25 0 6 0 15 Each lead centerline is located within 0 13 mm of its true position T P at maximum material condition
103. 0 to 85 6 Communication at different potential 1 8 V 2 5 V 3 V UART mode 2 2 Ta 40 to 85 C 1 8 V lt EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high LS low LV low speed main j speed main voltage Mode Mode main Mode MIN MAX MIN MAX MIN MAX Transfer rate Transmission 4 0 V EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V Theoretical value of the maximum transfer rate Co 50 pF Ro Vo 2 7 V 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V Theoretical value of the maximum transfer rate Co 50 pF Ro 2 7 Vo 2 3 V 1 8 V EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V value of the maximum transfer rate Cb 50 pF Rb 5 5 Vo 1 6 V Notes 1 The smaller maximum transfer rate derived by using 6 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 4 0 V lt EVppo lt 5 5 V and 2 7 V Vo lt 4 0 V 1 gt bps Cb x Rb x In 1 Vb x3 Maximum transfer rate 1 2 2 Transfer rate x2 Co x Pe x In e V J 1 Transfer rate Baud rate error theoretical value x 100 x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides 2 Th
104. 00 0 65 PLSP0020JC A S20MC 65 5A4 3 0 12 detail of lead end F Y Y Y 1 A pi A E U MILLIMETERS 6 65 0 15 0 475 MAX 0 65 T P 0 08 0 24 0 07 0 1 0 05 1 3 0 1 1 2 8 1 0 2 6 1 0 2 1 0 0 2 0 17 0 03 0 5 0 13 0 10 o5 3 3 0 25 0 6 0 15 B NOTE Each lead centerline is located within 0 13 mm of its true position T P at maximum material condition 215 O 2012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev 3 10 24 NEC SAS Page 176 of 194 Nov 15 2013 RL78 G13 4 PACKAGE DRAWINGS 4 2 24 pin Products R5F1007AANA R5F1007CANA R5F1007DANA R5F1007EANA R5F1017AANA R5F1017CANA R5F1017DANA R5F1017EANA R5F1007ADNA R5F1007CDNA R5F1007DDNA R5F1007EDNA R5F1017ADNA R5F1017CDNA R5F1017DDNA R5F1017EDNA R5F1007AGNA R5F1007CGNA R5F1007DGNA R5F1007EGNA JEITA Package Code RENESAS Code Previous Code MASS TYP g P HWQFN24 4x4 0 50 PWQNOO24KE A P24K8 50 CAB 1 0 04 DETAIL OF A PART O IS UNIT mm ITEM DIMENSIONS B2 D 4 00 0 05 E 4
105. 01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 107 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Simplified mode connection diagram during communication at different potential SDAr RL78 microcontroller User device SCLr SCL Simplified mode serial transfer timing during communication at different potential 1 fsc tLow THIGH SCLr SDAr tHD DAT tsu DAT Remarks 1 Re O Communication line SDAr SCLr pull up resistance Ce F Communication line SDAr SCLr load capacitance Ve V Communication line voltage 2 r IIC number r 00 01 10 20 30 31 g PIM POM number g 0 1 4 5 8 14 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 01 02 10 12 13 R01DS0131EJ0310 Rev 3 10 QE NE S AS Page 108 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 5 2 Serial interface IICA 1 standard mode Ta 40 to 85 C 1 6 V lt EVppo 1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MAX MAX MAX SCLAO clock frequency Standard 2 7 V lt EVomo lt 5 5 V 1 8 V lt 5 5 V lt lt fork 2 1 MHz pees 1 7 V lt EVppo lt
106. 07CANA U0 R5F1007DANA UO R5F1007EANA U0 R5F1007AANA WO R5F1007CANA WO R5F1007DANA WO R5F1007EANA WO R5F1007ADNA U0 R5F1007CDNA U0 R5F1007DDNA UO0 R5F1007EDNA U0 R5F1007ADNA WO R5F1007CDNA WO R5F1007DDNA WO R5F1007EDNAZWO R5F1007AGNA U0 R5F1007CGNA U0 R5F1007DGNA UO R5F1007EGNA U0 R5F1007AGNA 2WO R5F1007CGNA WO R5F1007DGNA WO R5F1007EGNA WO Not mounted R5F1017AANA U0 R5F1017CANA U0 R5F1017DANAUO R5F1017EANA U0 R5F1017AANA WO R5F1017CANA WO R5F1017DANA WO R5F1017EANA WO R5F1017ADNA U0 R5F1017CDNA U0 R5F1017DDNA U0 R5F1017EDNA U0 R5F1017ADNA WO R5F1017CDNA WO R5F1017DDNA WO R5F1017EDNAZWO Note For the fields of application refer to Figure 1 1 Part Number Memory Size and Package of RL78 G13 Caution The ordering part numbers represent the numbers at the time of publication For the latest ordering part numbers refer to the target product page of the Renesas Electronics website R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 4 of 194 RL78 G13 1 OUTLINE Table 1 1 List of Ordering Part Numbers 2 12 Package Fields of Ordering Part Number Application Note WFLGA 3 x 3 mm R5F1008EALA amp UO R5F1008AALA WO R5F1008CALA WO R5F1008DALA WO R5F1008EALA WO Not A R5F1018AALA U0 R5F1018CALA U0 R5F1018DALA ZUO at R5F1018EALA UO R5F1018AALA WO R5F1018CALA WO R5F1018DALA WO R5F1018EALA WO 30 pins 30 pin plastic LSSOP Mounted A R5F100AAASP
107. 1 P22 ANI2 O P23 ANI3 O P147 ANI18 O P10 SCK00 SCLOO TIO7 TOO7 P11 SI00 RXDO TOOLRxD SDAOO TIO6 TOO6 P12 SO00 TxDO TOOLTxD TIO5 TOO5 O P13 TxD2 SO20 SDAAO TIO4 TOO4 P14 RxD2 SI20 SDA20 SCLAO TIO3 TOO3 REGC O _ 10 O P15 PCLBUZ1 SCK20 SCL20 TIO2 TOO2 Vss 11 O P16 TIO1 TOO1 INTP5 RXDO Voo O 112 O P17 TIO2 TOO2 TXDO O P51 INTP2 SO11 O P50 INTP1 SI11 SDA11 O P30 INTP3 SCK11 SCL11 20 O P01 ANI16 TOO0 RxD1 O P00 ANI 7 TIOO TxXD1 O O G N Caution Connect the REGC pin to Vss via a capacitor 0 47 to 1 LF Remarks 1 For pin identification see 1 4 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR Refer to Figure 4 8 Format of Peripheral Redirection Register PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 19 of 194 Nov 15 2013 RL78 G13 1 OUTLINE 1 3 5 32 pin products e 32 pin plastic HWQFN 5 x 5 mm 0 5 mm pitch P11 SIOO RXDO TOOLRXxD S DAOO T106 TO06 I O P12 SOO0 TxDO TOOLTXxD TIO5 TOO5 P15 P CLBUZ1 SCK20 SCL20 T102 TOO2 P13 TxD2 SO20 SDAAO T104 TO04 P16 TIO1 TOOl INTP 5 RXDO P14 RxD2 S120 SDA20 SCLAO T103 TOO3 P17 TIO2 TOO2 TXDO exposed die pad 3 o N o E 5 zl O S o Y
108. 1 Data flash is not provide gt G r c commou o o d Note 2 Memory type F Flash memory Renesas MCU Renesas semiconductor product Notes 1 Products only for A Consumer applications TA 40 to 85 C 2 Products only for A Consumer applications Ta 40 85 C and D Industrial applications TA 40 to 85 C R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 3 of 194 Nov 15 2013 RL78 G13 Package 20 pin plastic LSSOP 7 62 mm 300 0 65 mm pitch 1 OUTLINE Table 1 1 List of Ordering Part Numbers Mounted Fields of Application Note 1 12 Ordering Part Number R5F1006AASP VO0 R5F1006CASP VO R5F1006DASP VO R5F1006EASP VO RSF1006AASP X0 R5F1006CASP X0 R5F1006DASP XO R5F1006EASP X0 R5F1006ADSP VO R5F1006CDSP V0 R5F1006DDSP VO R5F1006EDSPzVO R5F1006ADSP XO RSF1006CDSP X0 R5F1006DDSP X0 R5F1006EDSP X0 R5F1006AGSP V0 R5F1006CGSP VO0 R5F1006DGSP VO R5F1006EGSP VO R5F1006AGSP X0 R5F1006CGSP X0 R5F1006DGSP XO R5F1006EGSP X0 Not mounted R5F1016AASP VO0 R5F1016CASP VO R5F1016DASP VO R5F1016EASP VO R5F1016AASP X0 R5F1016CASP XO R5F1016DASP XO R5F1016EASP XO R5F1016ADSP VO0 R5F1016CDSP V0 R5F1016DDSP VO R5F1016EDSP2VO R5F1016ADSP X0 R5F1016CDSP X0 R5F1016DDSP X0 R5F1016EDSP X0 24 pin plastic HWQFN 4 x 4mm 0 5 mm pitch Mounted R5F1007AANA U0 R5F10
109. 1 8 V EVppo lt 2 7 V Co 100 pF Rb 5 1550 1550 1550 ns 1 7 V EVppo lt 1 8 V Co 100 pF Rb 5 1850 1850 1850 ns 1 6 V EVppo lt 1 8 V Co 100 pF Rb 5 1850 1850 ns Notes and Caution are listed on the next page and Remarks are listed on the page after the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 ztENESAS Page 88 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 5 During communication at same potential simplified Pc mode 2 2 Ta 40 to 85 C 1 6 V lt EVppo EVpni lt lt 5 5 V Vss EVsso EVssi 0 V HS high speed main Mode Parameter Conditions MIN MAX LS low speed main Mode MIN MAX LV low voltage main Mode MIN MAX Data setup time reception tsu pat 2 7 V lt EVppo 5 5 V 1 fuck 1 fuck 1 fuck ns 14 14 50 pF Ro 2 7 kQ tae pae 1 8 V lt EVppo lt 5 5 V 1 fuck 1 fuck 1 fuck ns 14 14 14 Co 100 pF Ro 3 pues e pes 1 8 V lt EVppo lt 2 7 V 1 fuck 1 fuck 1 fuck ns 2 2 2 C 100 pF Ro 5 p peg pe 1 7 V EVpro lt 1 8 V 1 fuck 1 fuck 1 fuck ns 2 2 2 C 100 pF Ro 5 pred PAA p 1 6 V EVppo 1 8 V 1 fuck 1 fuck ns Co 100 pF Ro 5 kQ 290 290 Data hold time tHD DAT 2 7 V lt EVppo lt 5 5 V 0 305 0 305 0 305 ns
110. 101 Nicholson Road Newmarket Ontario L3Y 9C3 Canada Tel 1 905 898 5441 Fax 1 905 898 3220 Renesas Electronics Europe Limited Dukes Meadow Millboard Road Bourne End Buckinghamshire SL8 5FH U K Tel 44 1628 651 700 Fax 44 1628 651 804 Renesas Electronics Europe GmbH Arcadiastrasse 10 40472 D sseldorf Germany Tel 49 211 65030 Fax 49 211 6503 1327 Renesas Electronics China Co Ltd 7th Floor Quantum Plaza No 27 ZhiChunLu Haidian District Beijing 100083 P R China Tel 86 10 8235 1155 Fax 86 10 8235 7679 Renesas Electronics Shanghai Co Ltd Unit 204 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2886 9318 Fax 852 2886 9022 9044 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 80 Bendemeer Road Unit 06 02 Hyflux Innovation Centre Singapore 339949 Tel 65 6213 0200 Fax 65 6213 0300 Renesas Electronics Malaysia Sdn Bhd Unit 906 Block B Menara Amcorp Amcorp Trade Centre No 18 Jln Persiaran Barat 46050 Petaling Jaya Selangor Darul Ehsan Malaysia Tel 60 3 7955 9390 Fax 60 3 7955 9510 Renesas Electronics Korea Co
111. 106 107 108 109 110 111 112 113 114 115 116 117 P130 O 118 P102 TI06 TO06 P07 P04 SCK10 SCL10 O PO3 ANI16 SI10 RxD1 SDA10 PO2 ANI17 SO10 TxD1 P01 TOOO P00 TI00 O P145 T107 TOO7 P144 SO30 TxD3 P143 SI30 RxXD3 SDA30 Cautions 1 119 120 121 122 123 124 125 126 127 128 1234567 8 9 1011121314 15 1617 18 1920 21222324 25 26 27 28 29 30 3132 33 34 35 36 37 38 OOOOO0O00000000000000000000000000000000 8 8 8 2 EEE 3 AdEEZZZZ008500005L00Z JOROLLLOAXxCcOSQ gt gt Ste 9zz lt lt lt lt Neoregee ey TA SER QQ LID TEA EFEEEGE SSE at rx Bg ese aq Did a FoF e Soo 2 2 394 ES a Vea 2 29 A RIS lal x a Make EVsso EVss pins the same potential as Vss pin OOOOOOOOOOOOOO0OOOOOCOOOOOOCO 2 Make Vpn the potential that is higher than EVppo EVpp pins EVppo EVpp1 3 Connect the REGC pin to Vss via a capacitor 0 47 to 1 Remarks 1 For pin identification see 1 4 Pin Identification 1 OUTLINE P86 INTP8 P85 INTP7 P84 INTP6 P83 P82 SO10 TXD1 P81 SHO RXD1 SDA10 P80 SCK10 SCL10 EVop EVss1 P05 P70 KRO SCK21 SCL21 P71 KR1 SI21 SDA21 P72 KR2 SO21 P73 KR3 P74 KR4 INTP8 P75
112. 11 20 21 30 31 g PIM number g 0 1 4 5 8 14 h POM number g 0 1 4 5 7 to 9 14 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number n 0 to 3 mn 00 to 03 10 to 13 R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 90 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 6 Communication at different potential 1 8 V 2 5 V 3 V UART mode 1 2 Ta 40 to 85 C 1 8 V lt EVppo EVpni lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high LS low speed LV low speed main main Mode voltage main Mode Mode MIN MIN MAX MIN MAX Transfer 4 0 V EVppo 5 5 V fuck 6 fuck 6 6 Note 1 Note 1 Note 1 rate 2 7 V lt Vo lt 4 0 V Theoretical value 5 3 1 3 0 6 of the maximum transfer rate Note 4 2 7 V lt EVoppo lt 4 0 V fuck 6 fuck 6 6 Note 1 Note 1 Note 1 2 3 V 2 7 Theoretical value 5 3 1 3 0 6 of the maximum transfer rate Note 4 fuck fork 1 8 V EVppo lt 3 3 V fuck 6 6 fuck 6 Notes 1 to Notes 1 2 Notes 1 2 1 6 V lt Vo lt 2 0 V 3 Theoretical value 5 3 of the maximum transfer rate Note 4 fuck fork Notes 1 Transfer rate in the SNOOZE mode is 4800 bps onl
113. 127 P130 P140 to P147 4 0 V EVppo lt 5 5 V lou 20 mA 4 0 V EVppo lt 5 5 V lou 8 5 mA 2 7 V lt EVopo 5 5 V 3 0 mA 2 7 V lt EVopo 5 5 V lou 1 5 mA 1 8 V EVppo lt 5 5 V 0 6 mA 1 6 V EVppo lt 5 5 V 0 3 mA P20 to P27 P150 to P156 1 6 V lt lt 5 5 V lore 400 u A P60 to P63 4 0 V EVppo lt 5 5 V lots 15 0 mA 4 0 V EVppo lt 5 5 V lots 5 0 mA 2 7 V lt EVopo 5 5 V lois 3 0 mA 1 8 V EVppo lt 5 5 V lots 2 0 mA 1 6 V EVppo lt 5 5 V lois 1 0 mA P142 to P144 do not output high level in N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NE SAS Page 61 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 40 to 85 C 1 6 V x EVppo 1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 5 5 Conditions Input leakage current high to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Vi LA P20 to P27 P137 P150 to P156 RESET Vi LA ILins P121 to P1
114. 17 of 194 RL78 G13 2 6 2 Temperature sensor internal reference voltage characteristics 40 to 85 C 2 4 V lt Voo lt 5 5 V Vss 0 V HS high speed main mode Parameter Temperature sensor output voltage Symbol VTMPS25 2 ELECTRICAL SPECIFICATIONS A D 40 to 85 Conditions Setting ADS register 80H TA 25 MIN TYP MAX Unit Internal reference voltage VBGR Setting ADS register 81H Temperature coefficient Fvtmps Temperature sensor that depends on the temperature Operation stabilization wait time 2 6 3 POR circuit characteristics Ta 40 to 85 C Vss 0 V Parameter Detection voltage Conditions Power supply rise time Power supply fall time Minimum pulse width Note Minimum time required for a POR reset when Voo exceeds below This is also the minimum time required for a POR reset from when Vo exceeds below 0 7 V to when Von exceeds Veon while STOP mode is entered or the main system clock is stopped through setting bit 0 HIOSTOP and bit 7 MSTOP in the clock operation status control register CSC Supply voltage VPDR or 0 7 V R01DS0131EJ0310 Rev 3 10 Nov 15 2013 TPw 21 NESAS Page 118 of 194 RL78 G13 2 6 4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode 2 ELECTRICAL SPECIFICAT
115. 1SHDFB X0 R5F101SJDFB XO R5F101SKDFB X0 R5F101SLDFB X0 Note For the fields of application refer to Figure 1 1 Part Number Memory Size and Package of RL78 G13 Caution The ordering part numbers represent the numbers at the time of publication For the latest ordering part numbers refer to the target product page of the Renesas Electronics website R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NE SAS Page 15 of 194 RL78 G13 1 OUTLINE 1 3 Pin Configuration Top View 1 3 1 20 pin products e 20 pin plastic LSSOP 7 62 mm 300 0 65 mm pitch O P01 ANI16 TOOO RxD1 O 1 O P20 ANIO AVnerP POO ANI17 TI00 TxD1 O 2 P21 ANI1 AVrerm P40 TOOLO 3 O P22 ANI2 RESET O 4 O P147 ANI18 P137 INTPO O 5 O P10 SCK00 SCLOO P122 X2 EXCLK O 6 O P11 SIO0 RXDO TOOLRxD SDAO0 121 1 7 P12 SO00 TxDO TOOLTxD 8 P16 TIO1 TOO1 INTP5 SC1 1 Vss O O P17 TIO2 TOO2 SM 1 SDA11 Voo O 10 O P30 INTP3 SCK11 SCL11 Caution Connect the REGC pin to Vss via a capacitor 0 47 to 1 LF Remark For pin identification see 1 4 Pin Identification R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 16 of 194 Nov 15 2013 RL78 G13 1 OUTLINE 1 3 2 24 pin products e 24 pin plastic HWQFN 4 x 4 mm 0 5 mm pitch P10 SCK00 SCLOO P11 SI00 RxXDO TOOLRxD SDAO0 P12 SO00 TxDO TOOLTxD P16 TIO1 TOO1 INTP5 P22 ANI2 O P147 ANI18 exposed die pad 181716151413 P17 T102
116. 2 OP50 INTP1 SI11 SDA11 78 9 101112 OOOO OOOOOOO S252855S853555 299020205299 o ILLL S DEEZ o E 3o90o9oq9ooo aNPoan FL EOE ESN 215 Yet aes RES 2 5 RE x a Bum z gt 2 5 E A Caution Connect the REGC pin to Vss via a capacitor 0 47 to 1 LF Remarks 1 For pin identification see 1 4 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 24 of 194 Nov 15 2013 RL78 G13 1 OUTLINE e 48 pin plastic HWQFN 7 x 7 0 5 mm pitch 0 a z z e touc faq 8 d lt 58 Sdemsaoor EC 2229775 rd O O rm N rN rN rN N amp amp n D D D R n UH P120 ANI19 P147 ANI18 P 41 T107 T007 exposed die pad 1 P146 P40 TOOLO P10 SCK00 SCL00 TI07 TO07 RESET P11 SI00 RxD0 TOOLRxD SDA00 TI06 TO06 P124 XT2 EXCLKS P12 SO00 TxD0 TOOLTxD TI05 TO05 P123 XT1 P13 TxD2 SO20 SDAA0 TI04 TO04 P137 INTPO P14 RxD2 SI20 5 DA20 S CLAO TI03 TO 03 P122 X2 EXCLK P15 PCLBUZ1 S CK20 S CL20 T102 TO 02 P121 X1 P16 TIO1 TOO1 INTP 5 RX DO REGC O P17 TI02 TO02 TXD0 Vss O P51 INTP2 S011 Vo P50 INTP 1
117. 2 2 Oscillator Characteristics 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 2 1 X1 XT1 oscillator characteristics TA 40 to 85 C 1 6 V lt Voo lt 5 5 V Vss 0 V Parameter Resonator Conditions X1 clock oscillation Ceramic resonator 2 7 V lt Voo lt 5 5 V 1 0 20 0 MHz frequency crystal resonator 24V lt lt 2 7 V 1 0 16 0 MHz 1 8 V lt Voo lt 2 4 V 1 0 8 0 MHz 1 6 V lt Voo lt 1 8 V 1 0 4 0 MHz XT1 clock oscillation Crystal resonator 32 32 768 35 kHz frequency fx t Note Indicates only permissible oscillator frequency ranges Refer to AC Characteristics for instruction execution time Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics Caution Since the CPU is started by the high speed on chip oscillator clock after a reset release check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register OSTC by the user Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register OSTS after sufficiently evaluating the oscillation stabilization time with the resonator to be used Remark When using the X1 oscillator and XT1 oscillator refer to 5 4 System Clock Oscillator in the RL78 G13 User s Manual Hardware 2 2 2 On chip oscillator characteristics Ta 40 t
118. 2 7 V C 30 pF Re 2 7 t cv 2 36 2 4 V lt EVppo lt 3 3 V 1 6 V Vo 2 0 V Cb 30 pF Ro 5 5 1 2 100 Caution Select the TTL input buffer for the Sip pin and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SOp and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks are listed two pages after the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 155 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 6 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 2 3 Ta 40 to 105 C 2 4 V lt EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V HS high speed main Mode MIN Parameter Slp setup time to SCKpT Conditions 4 0 V lt EVppo lt 5 5 V 2 7 V lt Ve lt 4 0 V Co 30 pF Re 1 4 KQ MAX 2 7 V lt EVppo lt 4 0 V 23V lt Vo lt 2 7 V 30 pF Rb 2 7 2 4 V lt lt 3 3 V 1 6 V lt Ve lt 2 0 V Cp 30 pF Re 5 5 Slp hold time from SCKpT et 4 0 V lt EVppo 5 5 V 2 7 V lt Vo 4 0 V pF Ro 1 4 2 7 V lt EV
119. 2 X2 EXCLK O P121 X1 O OO ro EO NE xt n Caution Connect the REGC pin to Vss via a capacitor 0 47 to 1 Remarks 1 For pin identification see 1 4 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 23 of 194 Nov 15 2013 RL78 G13 1 OUTLINE 1 3 9 48 pin products e 48 pin plastic LFQFP 7 x 7 mm 0 5 mm pitch c DL Sag Ei lt lt O68 SEAS aco 2222222 2 S E E lt lt lt lt lt lt lt lt S cst LG O F lt T OO OQ N ON CM QN G D i D D D D D D OL HH 6 35 23 2 P120 ANI19O 24 OP147 ANI8 P41 TIO7 TOO7 O P40 TOOLOO 22 OP10 SCK00 SCLOO TIO7 TOO7 RESETO 21 OP11 SI00 RXDO TOOLRxD SDAOO TIO6 TOO6 P124 XT2 EXCLKS O 4 20 OP12 SO00 TxDO TOOLTxD TIO5 TO05 P123 XT1 O 19 OP13 TxD2 SO20 SDAAO TIO4 TOO4 P137 INTPO O 43 18 0OP14 RxD2 SI20 SDA20 SCLAO TIO3 TOO3 P122 X2 EXCLK O 17 OP15 PCLBUZ1 SCK20 SCL20 TIO2 TOO2 P121 X10 45 16 OP16 TIO1 TOO1 INTP5 RXDO REGCO 15 OP17 TIO2 TOO2 TXDO Vss O 14 OP51 INTP2 SO 1 1 VoD O 13
120. 2 channels 12 channels 16 channels Watchdog timer 1 channel 1 channel 1 channel Real time clock RTC 1 channel 1 channel 1 channel 12 bit interval timer IT 1 channel 1 channel 1 channel Timer output 12 channels PWM outputs 10 12 channels PWM outputs 10 Note 2 16 channels PWM outputs 14 Note 2 RTC output 1 channel e 1 Hz subsystem clock fsus 32 768 kHz Notes 1 In the case of the 20 KB this is about 19 KB when the self programming function and data flash function are used For details see CHAPTER 3 in the RL78 G13 User s Manual Hardware In the case of the 32 KB this is about 31 KB when the self programming function and data flash function are used For details see CHAPTER 3 in the RL78 G13 User s Manual Hardware 2 The number of PWM outputs varies depending on the setting of channels in use the number of masters and slaves 6 9 3 Operation as multiple PWM output function in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NE SAS Page 52 of 194 RL78 G13 Clock output buzzer output 1 OUTLINE 2 2 80 pin 100 pin 128 pin R5F100Mx R5F101Mx R5F100Sx 2 2 R5F100Px R5F101Px 2 44 kHz 4 88 kHz 9 76 kHz 1 25 MHz 2 5 MHz 5 MHz 10 MHz Main system clock fva 20 MHz operation e 256 Hz 512 Hz 1 024 kHz 2 048 kHz 4 096 kHz 8 192 kHz 16 384 kHz
121. 24 NC SAS RL78 G13 RENESAS MCU Datasheet R01DS0131EJ0310 Rev 3 10 Nov 15 2013 True Low Power Platform as low as 66 uA MHz and 0 57 pA for RTC LVD 1 6 V to 5 5 V operation 16 to 512 Kbyte Flash 41 DMIPS at 32 MHz for General Purpose Applications 1 OUTLINE 1 1 Features Ultra Low Power Technology 1 6 V to 5 5 V operation from a single supply e Stop RAM retained 0 23 uA LVD enabled 0 31 LA e Halt RTC LVD 0 57 e Snooze 0 70 mA UART 1 20 mA ADC e Operating 66 uA MHz 16 bit RL78 CPU Core e Delivers 41 DMIPS at maximum operating frequency of 32 MHz e Instruction Execution 86 of instructions can be executed in 1 to 2 clock cycles e CISC Architecture Harvard with 3 stage pipeline e Multiply Signed amp Unsigned 16 x 16 to 32 bit result in 1 clock cycle e MAC 16 x 16 to 32 bit result in 2 clock cycles e 16 bit barrel shifter for shift amp rotate in 1 clock cycle e 1 wire on chip debug function Main Flash Memory e Density 16 KB to 512 KB e Block size 1 KB e On chip single voltage flash memory with protection from block erase writing e Self programming with secure boot swap function and flash shield window function Data Flash Memory e Data Flash with background operation e Data flash size 4 KB to 8 KB size options e Erase Cycles 1 Million typ e Erase programming voltage 1 8 V to 5 5 V RAM e 2 KB to 32 KB size options e Supports operands or inst
122. 24 X1 X2 XT1 XT2 EXCLK EXCLKS In input port or external clock input LA In resonator connection LA Input leakage luii current low POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Vi EVsso LA 2 P20 to P27 P137 P150 to P156 RESET Vi Vss LA 121 to P124 X1 X2 XT1 XT2 EXCLK EXCLKS Vss In input port or external clock input LA In resonator connection LA On chip pll up Ru resistance POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Vi EVsso In input port 10 20 100 Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 62 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 3 2 Supply current characteristics 1 Flash ROM 16 to 64 KB of 20 to 64 pin products 40 to 85 C 1 6 V lt EVppo lt lt 5 5 V Vss EVsso 0 V 1 2 Parameter Supply current ete 1 Operating mode HS high speed main mode Note 5 Conditions 32
123. 30 LA speed main mode ete Voo 2 0 V 260 530 uA LV low 4 MHz Voo 3 0 V 420 640 uA voltage main mode Voo 2 0 V 420 640 JA Note 7 HS high fux 20 MHz 3 Square wave input 0 28 1 00 mA speed main mode 7 Von 5 0 V Resonator connection 0 45 1 17 mA fmx 20 2 3 Square wave input 0 28 1 00 mA Voo 9 0 V Resonator connection 0 45 1 17 mA fux 10 MHz ete Square wave input 0 19 0 60 mA Voo 5 0 V Resonator connection 0 26 0 67 mA fux 10 MHz e Square wave input 0 49 0 60 mA Voo 3 0 V Resonator connection 0 26 0 67 mA LS low fux 8 MHz 3 Square wave input 95 330 uA Speed main Voo 3 0 V Resonator connection 145 380 uA UMS fux 8 MHz 3 Square wave input 95 330 LA Voo 2 0 V Resonator connection 145 380 LA Subsystem fsus 32 768 kHz 5 Square wave input 0 25 0 57 clock 40 Resonator connection 0 44 0 76 uA Operator fsus 32 768 2 5 Square wave input 0 30 0 57 uA Ta 25 C Resonator connection 0 49 0 76 LA sus 32 768 kHz Square wave input 0 37 1 17 uA Ta 50 C Resonator connection 0 56 1 36 LA fsus 32 768 kHz Square wave input 0 53 1 97 LA 70 C Resonator connection 0 72 2 16 LA fsue 32 768 kHz Square wave input 0 82 3 37 LA Ta 85 C Resonator connection 1 01 3 56 LA Ipps 5 STOP Ta 40 C 0 18 0 50 yA mode _ 425 C 0 23 0 50 JA Ta 50 0 30 1 10 LA 70
124. 32 768 kHz Subsystem clock fsus 32 768 kHz operation 8 10 bit resolution A D converter 17 channels 20 channels 26 channels Serial interface 80 pin 100 pin 128 pin products e CSI 2 channels simplified IFC 2 channels UART 1 channel CSI 2 channels simplified I C 2 channels UART 1 channel e CSI 2 channels simplified IC 2 channels UART UART supporting LIN bus 1 channel e CSI 2 channels simplified 2 channels UART 1 channel bus 2 channels 2 channels 2 channels Multiplier and divider multiply accumulator 16 bits x 16 bits 32 bits Unsigned or signed 32 bits 32 bits 32 bits Unsigned e 16 bits x 16 bits 32 bits 32 bits Unsigned or signed DMA controller 4 channels Vectored Internal 37 37 interrupt sources External 13 13 Key interrupt 8 8 Reset Reset by RESET pin Internal reset by watchdog timer Internal reset by power on reset Internal reset by voltage detector Internal reset by illegal instruction execution Internal reset by RAM parity error Internal reset by illegal memory access Note Power on reset circuit Power on reset 1 51 V TYP Power down reset 1 50 V TYP Voltage detector 1 67 V to 4 06 V 14 stages 1 63 V to 3 98 V 14 stages e Rising edge e Falling edge On chip debug function Provided Power supply voltage Voo 1 6 to 5 5 V Operating
125. 4 to 100 pin products 40 to 85 C 1 6 V lt EVppo 1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 2 2 Parameter Supply current Note 1 Note 2 mode HS high speed main mode Note 7 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Conditions 32 MHz Voo 5 0 V Voo 3 0 V 0 02 189 mA fin 24 MHz Voo 5 0 V 0 50 1 48 mA Voo 3 0 V 0 50 148 mA fiu 16 MHz e 4 Voo 5 0 V 0 44 1 12 mA 3 0 V 0 44 112 mA LS low 8 MHz Voo 3 0 V 290 620 uA war Voo 2 0 V LV low 4 MHz Vop 3 0 V 460 700 uA Voo 2 0 V 460 700 Note 7 HS high fx 20 MHz Square wave input 0 31 1 14 mA speed main Yop 5 0 V Resonator 048 134 mA mode connection fux 20 3 Square wave input 0 31 1 14 mA Voo 3 0 V Resonator 0 48 1 34 mA connection fux 10 MHz 3 Square wave input Voo 5 0 V Resonator 0 28 0 76 mA connection fux 10 MHz Note 3 Square wave input 0 21 0 68 mA Voo 3 0 V Resonator 0 28 0 76 mA connection LS low fux 8 2 3 Square wave input 110 390 uA speed main Von 3 0 V Resonator 160 450 JA mode connection fux 8 MHz 3 Square wave input 110 390 uA Voo 2 0 V Resonator 160 450 LA connection Subsystem 32 768 kHz 5 Square wave input 0 31
126. 4 ns 0 Slp hold time tksi2 1 8 V lt EVppo lt 5 5 V 1 fuck 3 1 31 1 fuck 3 ns from 1 1 Note 2 1 7 V lt EVppo lt 5 5 V 1 1 1 ns 250 250 250 1 6 V lt EVbppo 5 5 V 1 fmck 1 fmck ns 250 250 Delay time tkso2 C 30 2 7 V lt lt 5 5 V 2 fmck 2 fmck 2 fmck ns from SCKpl to pF 4 44 110 110 Note SOp output 24 V lt lt 5 5 V 2 fmok 2 fmok 2 fuck ns 75 110 110 1 8 V lt EVppo 5 5 V 2 fuck 2 2 fuck ns 110 110 110 1 7 V lt EVppo lt 5 5 V 2 fuck 2 fuck 2 fuck ns 220 220 220 1 6 V lt lt 5 5 V 2 2 fuck ns 220 220 Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The 51 setup time becomes to SCKpl when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The 51 hold time becomes from SCKpl when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpT when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 4 C is the load capacitance of the SOp output lines 5 Transfer rate in the SNOOZE mode MAX 1 Mbps Caution Select the normal input buffer for the Slp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g PIMg and port output mode register
127. 40 SDAOO P11 SCL11 P30 SYSTEM SDA11 P50 CONTROL SERIAL SDAA0 P61 SDAA0 P13 RESET INTERFACE IICA0 HIGH SPEED X1 P121 SCLA0 P60 SCLA0 P14 SERIAL ARRAY OSCILLATOR T PRETIO BUZZER OUTPUT x PCLBUZO P31 VOLTAGE TxD2 P13 PCLBUZ1 P15 REGULATOR REGC CONTROL SCK20 P15 RxD2 P14 SI20 P14 MULTIPLIERS did INTPO P137 SO20 P13 DIVIDER INTP1 P50 SCK21 P70 c UMOR INTERRUPT INTP2 P51 SI21 P71 CONTROL INTP3 P30 INTP4 P31 S021 P72 y DIRECT MEMORY SCL20 P15 ACCESS CONTROL 5 16 SDA20 P14 SCL21 P70 BCD SDA21 P71 ADJUSTMENT Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral redirection register PIOR Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 39 of 194 Nov 15 2013 RL78 G13 1 OUTLINE 1 5 7 40 pin products TIMER ARRAY UNIT 8ch TI00 P00 TO00 P01 TI01 TO01 P16 TI02 TO02 P17 TIO2 TOO2 P15 TI03 TOO3 P31 103 7003 14 04 004 13 TIO5 TOO5 P12 TI06 TO06 P11 107 007 10 RxD2 P14 WINDOW WATCHDOG TIMER LOW SPEED ONUS I ERAL OSCILLATOR REAL TIME RTC1HZ P30 CLOCK SERIAL ARRAY UNITO 4ch RxD0 P11 RxD0 P16 TxD0 P12 TxD0 P17 RxD1 P01 TxD1 P00 SCK00 P10 100 11 000 12 SCK11 P30 SI11 P50 SO11 P51 SCLOO P10 SDAOO P11 SCL11
128. 40 to 105 C Operating mode Operating voltage range HS high speed main mode 2 7 V lt lt 5 5 V 1 MHz to 32 MHz 2 4 V lt Voo lt 5 5 V1 MHz to 16 MHz LS low speed main mode 1 8 V lt Voo lt 5 5 V1 MHz to 8 MHz LV low voltage main mode 1 6 V x Voo x 5 5 V 1 MHz to 4 MHz HS high speed main mode only 2 7 V lt Von lt 5 5 V 1 MHz to 32 MHz 2 4 V lt lt 5 5 V 1 MHz to 16 MHz High speed on chip oscillator clock accuracy 1 8 V lt Vio lt 5 5 V 1 0 Ta 20 to 85 C 1 5 Ta 40 to 20 C 1 6 V lt Voo lt 1 8 V 5 0 Ta 20 to 85 C 5 5 Ta 40 to 20 C 2 4 V lt Voo lt 5 5 V 2 0 Ta 85 to 105 C 1 0 Ta 20 to 85 C 1 5 Ta 40 to 20 C Serial array unit UART CSI 2 supporting 16 Mbps 4 Simplified communication UART CSI 4 Simplified communication Normal mode Fast mode Fast mode plus Normal mode Fast mode Voltage detector Remark is listed on the next page Rise detection voltage 1 67 V to 4 06 V 14 levels Fall detection voltage 1 63 V to 3 98 V 14 levels Rise detection voltage 2 61 V to 4 06 V 8 levels Fall detection voltage 2 55 V to 3 98 V 8 levels R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NE SAS Page 123 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Remark The electrical characteristics of the product
129. 5 5 5 5 R E 5 E BS 5 Page 136 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Notes 1 Total current flowing into EVopo and EVpo1 including the input leakage current flowing when the level of the input pin is fixed Vop EVppo and EVpp1 or Vss EVsso and 1 The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite 2 When high speed on chip oscillator and subsystem clock are stopped 3 When high speed system clock and subsystem clock are stopped 4 When high speed on chip oscillator and high speed system clock are stopped When 1 1 Ultra low power consumption oscillation However not including the current flowing into the 12 bit interval timer and watchdog timer 5 Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V lt Voo lt 5 5 V 1 MHz to 32 MHz 2 4 V lt lt 5 5 V 1 MHz to 16 MHz Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fiH High speed on chip oscillator clock frequency 3 fsus Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation temperature cond
130. 5 V Vss 0 V Parameter Interrupt and reset mode Symbol Conditions 2 VPoco 0 0 0 falling reset voltage MIN Unit lt VLVDA1 LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 1 Rising release reset voltage Falling interrupt voltage 151 LVISO 0 0 Rising release reset voltage Falling interrupt voltage VivpBo VPpoce 1 VPoco 0 0 1 falling reset voltage VuvDB1 LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage V uvpB2 LVIS1 LVISO 0 1 Rising release reset voltage Falling interrupt voltage VLVDB3 LVIS1 LVISO 0 0 Rising release reset voltage Falling interrupt voltage Vuvoco 2 Vroco 0 1 0 falling reset voltage Vuvpci LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage Vuvpc2 Vivocs LVIS1 LVISO 0 1 LVIS1 LVISO 0 0 Rising release reset voltage Falling interrupt voltage Rising release reset voltage Falling interrupt voltage Vivppo Vpoc2 VPoci Vroco 0 1 1 falling reset voltage Vivop1 LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage LVIS1 LVISO 0 1 Rising rele
131. 5 V Vss EVsso EVssi 0 V HS high speed main Mode Parameter Conditions LS low speed main Mode LV low voltage main Mode SCLr clock frequency fscL 2 7 V EVppo lt 5 5 V Co 50 pF Rb 2 7 MIN MAX 1000 Note 1 MIN MAX 400 Note 1 MIN MAX 400 Note 1 kHz 1 8 V EVppo 5 5 V Co 100 pF Rb KQ 400 Note 1 400 Note 1 400 Note 1 kHz 1 8 V EVppo lt 2 7 V Co 100 pF Rb 5 300 Note 1 300 Note 1 300 Note 1 kHz 1 7 V EVppo lt 1 8 V Co 100 pF Rb 5 250 Note 1 250 Note 1 250 Note 1 kHz 1 6 V EVppo lt 1 8 V Co 100 pF Rb 5 250 Note 1 250 Note 1 kHz Hold time when SCLr L tlow 2 7 V lt EVppo lt 5 5 V Cb 50 pF Ro 2 7 475 1150 1150 ns 1 8 V EVppo 5 5 V Cb 100 pF Rb 3 KQ 1150 1150 1150 ns 1 8 V EVppo lt 2 7 V Cb 100 pF Rb 5 KQ 1550 1550 1550 ns 1 7 V EVppo lt 1 8 V Cb 100 pF Rb 5 1850 1850 1850 ns 1 6 V EVppo 1 8 V Cb 100 pF Rb 5 1850 1850 ns Hold time when SCLr H THIGH 2 7 V lt EVppo 5 5 V Cb 50 pF Rb 2 7 KQ 475 1150 1150 ns 1 8 V EVppo 5 5 V Co 100 pF Rb 1150 1150 1150 ns
132. 55 V 0 03125 instruction execution time system main mode 24V V 27 V 0 0625 Clock fuain operation Subsystem clock fsus 24V lt Vo lt 55V 28 5 operation In the self HS high speed 2 7 V lt Von lt 5 5 V 0 03125 programming main mode 24V Vo 27 V 0 0625 mode External system clock frequency fex 2 7 V lt Vio lt 5 5 V 1 0 2 4 V lt Voo lt 2 7 V 1 0 fexs 32 External system clock input high text tex 2 7 V lt Voo lt 5 5 V 24 level width low level width 2 V lt Vpp lt 2 7 V 30 tExHs 13 7 TIOO to TIO7 TI10 to 7 input tris 1 10 high level width low level width tri TOO0 to TOO7 TO10 to TO17 fro HS high speed 4 0 V EVppo 5 5 V output frequency main mode 2 7 V lt EVbppo lt 4 0 V 2 4 V lt lt 2 7 V PCLBUZ0 PCLBUZ1 output HS high speed 4 0 V EVpopo lt 5 5 V frequency main mode 2 7 V lt EVoro lt 4 0 V 2 4 V lt EVppo lt 2 7 V Interrupt input high level width INTP0 2 4 V lt Voo lt 5 5 V low level width INTP1toINTP11 2 4 V lt EVopoo lt 5 5 V Key interrupt input low level width KR0 to KR7 2 4 V lt EVppo 5 5 V RESET low level width Note The following conditions are required for low voltage interface when Evppo lt Vpp 2 4V lt EVppo lt 2 7 V MIN 125 ns Remark fwck Timer array unit operation clock
133. 5F100FGAFP R5F100FHAFP R5F100FJAFP R5F100FKAFP R5F100FLAFP R5F101FAAFP JR5F101FCAFP R5F101FDAFP RS5F101FEAFP R5F101FFAFP R5F101FGAFP R5F101FHAFP R5F101FJAFP R5F101FKAFP R5F101FLAFP R5F100FADFP R5F100FCDFP R5F100FDDFP JR5F100FEDFP R5F100FFDFP R5F100FGDFP R5F100FHDFP R5F100FJDFP R5F100FKDFP R5F100FLDFP R5F101FADFP R5F101FCDFP R5F101FDDFP R5F101FEDFP R5F101FFDFP R5F101FGDFP R5F101FHDFP R5F101FJDFP R5F101FKDFP R5F101FLDFP R5F100FAGFP R5F100FCGFP R5F100FDGFP R5F100FEGFP R5F100FFGFP R5F100FGGFP R5F100FHGFP R5F100FJGFP JEITA Package Code RENESAS Code Previous Code MASS 9 P LQFP44 10x10 0 80 PLQP0044GC A P44GB 80 UES 2 0 36 l lt HD gt D detail of lead end 33 23 i A3 34 221 533 s 1 Y EE A A ii L E HE Lp 1 gt O UNIT mm 2144 12 ITEM DIMENSIONS 1 m 11 D 10 00 0 20 1 TT E 10 00 0 20 Loe Y HD 12 00 0 20 12 00 0 20 1 60 1 0 10 0 05 2 1 40 0 05 0 25 0 08 b 0 3710 07 0 055 0 145 0 045 0 50 Lp 0 60 0 15 L1 1 00 0 20 5 0 33o e 0 80
134. 5F101GK R5F101JK R5F101LK R5F101MK R5F101PK R5F101SK R5F100FJ R5F100GJ R5F100JJ R5F100LJ RSF100MJ R5F100PJ R5F100SJ R5F101FJ R5F101GJ R5F101JJ R5F101LJ R5F101MJ R5F101PJ R5F101SJ R5F100EH R5F100FH R5F100GH R5F100JH R5F100LH R5F100MH R5F100PH R5F100SH R5F101EH R5F101FH R5F101GH R5F101JH R5F101LH R5F101MH R5F101PH R5F101SH R5F100EG R5F100FG R5F100GG R5F100JG R5F100LG R5F100MG R5F100PG R5F101EG R5F101FG R5F101GG R5F101JG R5F101LG R5F101MG R5F101PG R5F100EF R5F100FF RBF100GF R5F100JF R5F100LF R5F100MF R5F100PF R5F101EF R5F101FF R5F101GF R5F101JF R5F101LF R5F101MF R5F101PF R5F100EE R5F100FE R5F100GE R5F100JE R5F100LE R5F101EE R5F101FE R5F101GE R5F101JE R5F101LE R5F100ED R5F100FD R5F100GD R5F100JD R5F100LD R5F101ED R5F101FD R5F101GD R5F101JD R5F101LD R5F100EC R5F100FC R5F100GC R5F100JC R5F100LC R5F101EC R5F101FC R5F101GC R5F101JC R5F101LC R5F100EA R5F100FA R5F100GA R5F101EA R5F101FA R5F101GA Notes 1 This is about 3 KB when the self programming function and data flash function are used For details see CHAPTER 3 in the RL78 G13 User s Manual Hardware 2 This is about 19 KB when the self programming function and data flash function are used For details see CHAPTER 3 i
135. 5F101SHDFB R5F101SJDFB R5F101SKDFB R5F101SLDFB JEITA Package Code RENESAS Code Previous Code MASS TYP g P LFQFP128 14x20 0 50 PLQP0128KD A P128GF 50 GBP 1 0 92 HD D detail of lead end pA A3 i A Lp Lp UNIT mm ITEM DIMENSIONS D 20 00 0 20 14 00 0 20 HD 22 00 0 20 16 00 0 20 1 60 A1 0 10 0 05 A2 1 40 0 05 0 25 b 0 22 0 05 0 145 0 055 L 0 50 0 60 0 15 L1 1 00 0 20 0 du 0 50 0 08 0 08 ZD 075 ZE 075 2012 Renesas Electronics Corporation All rights reserved RO1DS0131EJ0310 Rev 3 10 aS NES AS Nov 15 2013 Page 194 of 194 Revision History 1 00 2 00 Date Feb 29 2012 Oct 12 2012 Aug 02 2013 RL78 G13 Data Sheet Description Page Summary First Edition issued 7 Figure 1 1 Part Number Memory Size and Package of RL78 G13 Pin count corrected 25 1 4 Pin Identification Description of pins INTPO to INTP11 corrected 40 42 44 1 6 Outline of Functions Descriptions of Subsystem clock Low speed on chip oscillator and General purpose register corrected 41 43 45 1 6 Outline of Functions Lists of Descriptions changed 59 63 67 Descrip
136. 78 G13 4 PACKAGE DRAWINGS 4 12 80 pin Products R5F100MFAFA R5F100MGAFA R5F100MHAFA R5F100MJAFA R5F100MKAFA R5F100MLAFA R5F101MFAFA R5F101MGAFA R5F101MHAFA R5F101MJAFA R5F101MKAFA R5F101MLAFA R5F100MFDFA R5F100MGDFA R5F100MHDFA R5F100MJDFA R5F100MKDFA R5F100MLDFA R5F101MFDFA R5F101MGDFA R5F101MHDFA R5F101MJDFA R5F101MKDFA R5F101MLDFA R5F100MFGFA R5F100MGGFA R5F100MHGFA R5F100MJGFA JEITA Package Code RENESAS Code Previous Code MASS TYP g P LQFP80 14x14 0 65 PLQPO0080JB E P80GC 65 UBT 2 0 69 m HD detail of lead end L1 gt 1 1 d i 0 L a Lp E HE Referance Dimension in Millimeters Symbol Min Nom Max D 13 80 14 00 14 20 E 13 80 14 00 14 20 HD 17 00 17 20 17 40 HE 17 00 17 20 17 40 Y A 1 70 A1 0 05 0 125 0 20 A2 1 35 1 40 1 45 0 25 bp x S AB bp 026 032 038 0 10 0 145 0 20 A L 080 L 0 736 0 886 1 036 A24 E L1 1 40 1 60 1 80 S 0 0 3 8 i e 0 65 x 0 13 0 10 zD 0 825 ZE 0 825 2012 Renesas ElectronicsCorporation All rights reserved
137. 8 V 2 5 V 3 V CSI mode 1 2 Modification of table and caution in 9 Communication at different potential 1 8 V 2 5 V 3 V CSI mode 2 2 Modification of table in 10 Communication at different potential 1 8 V 2 5 V 3 V simplified mode 1 2 Modification of table note 1 and caution in 10 Communication at different potential 1 8 V 2 5 V 3 V simplified mode 2 2 Addition of 1 standard mode Addition of 2 fast mode Addition of 3 fast mode plus Modification of IICA serial transfer timing Addition of table in 2 6 1 A D converter characteristics Modification of description in 2 6 1 1 Modification of notes 3 to 5 in 2 6 1 1 Modification of description and notes 2 4 and 5 in 2 6 1 2 Modification of description and notes 3 and 4 in 2 6 1 3 Modification of description and notes 3 and 4 in 2 6 1 4 2 Rev 3 00 Date Aug 02 2013 Description Page 118 118 119 120 120 122 123 124 126 126 127 128 133 135 137 139 140 142 143 143 143 145 145 146 147 149 151 152 to 154 155 156 157 158 160 161 Summary Modification of table in 2 6 2 Temperature sensor internal reference voltage characteristics Modification of table and note in 2 6 3 POR circuit characteristics Modification of table in 2 6 4 LVD circuit characteristics Modification of table of LVD Detection Voltage of Interrupt amp Reset Mode R
138. A R5F100GFGNA R5F100GGGNA R5F100GHGNA R5F100GJGNA JEITA Package Code RENESAS Code Previous Code MASS TYP g P HWQFNA8 7x7 0 50 PWQNOO48KB A P48K8 50 5B4 4 0 13 DETAIL OF A PART UNIT mm e S ITEM DIMENSIONS D 7 00 0 05 D2 7 00 0 05 A 0 75 0 05 gt A EXPOSED DIE PAD 02505 e 0 50 Lp 0 40 0 10 x 0 05 y 0 05 ITEM De ER MIN NOMMAX MIN NOM MAX EXPOSED DIE PAD 5 45 5 5015 55 5 45 5 50 5 55 VARIATIONS 2012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 185 of 194 Nov 15 2013 RL78 G13 4 PACKAGE DRAWINGS 4 10 52 pin Products R5F100JCAFA R5F100JDAFA R5F100JEAFA R5F100JFAFA R5F100JGAFA R5F100JHAFA R5F100JJAFA R5F100JKAFA R5F100JLAFA R5F101JCAFA R5F101JDAFA R5F101JEAFA R5F101JFAFA R5F101JGAFA R5F101JHAFA R5F101JJAFA R5F101JKAFA R5F101JLAFA R5F100JCDFA R5F100JDDFA R5F100JEDFA R5F100JFDFA R5F100JGDFA R5F100JHDFA R5F100JJDFA R5F100JKDFA R5F100JLDFA R5F101JCDFA R5F101JDDFA R5F101JEDFA R5F101JFDFA R5F101JGDFA R5F101JHDFA R5F101JJDFA R5F101JKDFA R5F101JLDFA R5F100JCGFA R5F100JDGFA R5F100JEGFA R5F100JFGFA R5F100JGGFA R5F100JHGFA R5F100JJGFA JEITA Package Code RENESAS Code Previous Code MA
139. A U0 R5F101CGALA U0 R5F101CAALA WO R5F101CCALAZWO R5F101CDALA WO R5F101CEALA WO R5F101CFALAZWO R5F101CGALAZWO 40 pin plastic HWQFN Mounted R5F100EAANA U0 R5F100ECANA U0 R5F100EDANA UO 6 x 6 mm 0 5 mm R5F100EEANA U0 R5F100EFANA U0 R5F100EGANA UO pitch R5F100EHANA U0 R5F100EAANA WO R5F100ECANA WO R5F100EDANA WO R5F100EEANA WO R5F100EFANA WO R5F100EGANA WO R5F100EHANA WO R5F100EADNAZUO R5F100ECDNA U0 R5F100EDDNA UO R5F100EEDNAZUO R5F100EFDNA U0 R5F100EGDNA UO R5F100EHDNA U0 R5F100EADNA WO R5F100ECDNAZWO R5F100EDDNA WO R5F100EEDNA WO R5F100EFDNA WO R5F100EGDNA WO R5F100EHDNA WO R5F100EAGNA U0 R5F100ECGNA U0 R5F100EDGNA UO R5F100EEGNA U0 R5F100EFGNA UO R5F100EGGNA UO R5F100EHGNA U0 R5F100EAGNA WO R5SF100ECGNA WO R5F100EDGNAZWO R5F100EEGNAZWO R5F100EFGNA WO R5F100EGGNA ZWO R5F100EHGNAZWO Not R5F101EAANA U0 R5F101ECANA U0 R5F101EDANA UO mounted R5F101EEANA U0 R5F101EFANA U0 R5F101EGANA U0 R5F101 EHANA U0 R5F101EAANA WO R5F101ECANAZWO R5F101EDANAZWO R5F101EEANA WO R5F101EFANAZWO R5F101EGANAZWO R5F101EHANAZWO R5F101EADNAZUO R5F101ECDNA U0 R5F101EDDNA UO R5F101EEDNAZUO R5F101EFDNAZUO R5F101EGDNA UO R5F101EHDNA U0 R5F101EADNAZWO R5F101ECDNAZWO R5F101EDDNA WO R5F101EEDNAZWO R5F101EFDNAZWO R5F101EGDNA WO R5F101EHDNAZWO Note For the fields of application refer to Figure 1 1 Part Number Memory Size and Package of RL78 G13 Caution The ordering par
140. A VO R5F100JHDFA VO R5F100JJDFAs VO R5F100JKDFA VO R5F100JLDFA VO R5F100JCDFA X0 R5F100JDDFA X0 R5F100JEDFA XO R5F100JFDFA X0 R5F100JGDFA X0 R5F100JHDFA XO R5F100JJDFA X0 R5F100JKDFA X0 R5F100JLDFA X0 R5F100JCGFA sVO0 R5F100JDGFAs VO R5F100JEGFA VO R5F100JFGFA V0 R5F100JGGFA VO R5F100JHGFA VO RSF100JJGFA VO R5F100JCGFA X0 R5F100JDGFA X0 RSF100JEGFA XO R5F100JFGFA X0 R5F100JGGFA X0 RSF100JHGFA XO R5F100JJGFA X0 Not R5F101JCAFA V0 R5F101JDAFA V0 R5F101JEAFA VO mounted R5F101JFAFA V0 R5F101JGAFA V0 R5F101JHAFA VO R5F101JJAFA V0 R5F101JKAFA V0 R5F101JLAFA V0 R5F101JCAFA X0 R5F101JDAFA X0 R5F101JEAFA X0 R5F101JFAFA X0 R5F101JGAFA X0 R5F101JHAFA X0 R5F101JJAFA X0 R5F101JKAFA X0 R5F101JLAFA X0 R5F101JCDFA V0 R5F101JDDFA V0 R5F101JEDFA VO R5F101JFDFA V0 R5F101JGDFA V0 R5F101JHDFA VO R5F101JJDFA V0 R5F101JKDFA V0 RSF101JLDFA VO R5F101JCDFA X0 R5F101JDDFAZXO0 R5F101JEDFA XO R5F101JFDFA X0 R5F101JGDFA 2XO R5F101JHDFA XO R5F101JJDFA X0 R5F101JKDFA X0 R5F101JLDFA X0 Note For the fields of application refer to Figure 1 1 Part Number Memory Size and Package of RL78 G13 Caution The ordering part numbers represent the numbers at the time of publication For the latest ordering part numbers refer to the target product page of the Renesas Electronics website R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 10 of 194 Nov 15 2013 RL78 G13 1 OUTLINE Table 1 1 List of Orde
141. B to the MAX value when reference voltage AVREFM Differential linearity error Add 0 2 LSB to the MAX value when reference voltage AVREFM R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NE SAS Page 171 of 194 RL78 G13 3 6 2 Temperature sensor internal reference voltage characteristics 40 to 105 C 2 4 V lt lt 5 5 V Vss 0 V HS high speed main mode Parameter Temperature sensor output voltage VTMPS25 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Conditions Setting ADS register 80H TA 25 C Internal reference voltage Setting ADS register 81H Temperature coefficient FvrwPs Temperature sensor that depends on the temperature Operation stabilization wait time 3 6 3 POR circuit characteristics Ta 40 to 105 Vss 0 V Parameter Detection voltage Conditions Power supply rise time Power supply fall time Minimum pulse width Note Minimum time required for a POR reset when Vo exceeds below Vror This is also the minimum time required for a POR reset from when Voo exceeds below 0 7 V to when Vo exceeds Vror while STOP mode is entered or the main system clock is stopped through setting bit 0 HIOSTOP and bit 7 MSTOP in the clock operation status control register CSC Supply voltage VPDR or 0 7 V R01DS0131E
142. BDGNA UO R5F100BEGNA U0 R5F100BFGNA U0 R5F100BGGNA U0 R5F100BAGNAZWO R5F100BCGNAZWO R5F100BDGNA WO R5F100BEGNAZWO R5F100BFGNAZWO R5F100BGGNAZWO Not A R5F101BAANA U0 R5F101BCANA U0 R5F101BDANA UO R5F101BEANA UO R5F101BFANA UO R5F101BGANA U0 R5F101BAANA WO R5F101BCANAZWO R5F101BDANA WO R5F101BEANA WO R5F101BFANA WO R5F101BGANA WO D R5F101BADNA U0 R5F101BCDNA U0 R5F101BDDNA UO R5F101BEDNA U0 R5F101BFDNA U0 R5F101BGDNA U0 R5F101BADNAZWO R5F101BCDNAZWO R5F101BDDNA WO R5F101BEDNAZWO R5F101BFDNAZWO R5F101BGDNAZWO 0 5 mm pitch mm pitch 0 5 mm pitch Note For the fields of application refer to Figure 1 1 Part Number Memory Size and Package of RL78 G13 Caution The ordering part numbers represent the numbers at the time of publication For the latest ordering part numbers refer to the target product page of the Renesas Electronics website R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 5 of 194 Nov 15 2013 RL78 G13 1 OUTLINE Table 1 1 List of Ordering Part Numbers 3 12 Package Fields of Ordering Part Number Application Note 36 pin plastic WFLGA Mounted R5F100CAALA U0 R5F100CCALA U0 R5F100CDALA UO 4 x 4 mm 0 5 mm R5F100CEALA U0 R5F100CFALA U0 R5F100CGALA U0 pitch R5F100CAALA WO R5F100CCALA WO R5F100CDALA WO R5F100CEALA WO R5F100CFALAZWO R5F100CGALA WO Not R5F101CAALA U0 R5F101CCALA U0 R5F101CDALA UO mounted R5F101CEALA U0 R5F101CFAL
143. C This chapter describes the electrical specifications for the products Industrial applications Ta 40 to 105 Cautions 1 The RL78 microcontrollers have an on chip debug function which is provided for development and evaluation Do not use the on chip debug function in products designated for mass production because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used and product reliability therefore cannot be guaranteed Renesas Electronics is not liable for problems occurring when the on chip debug function is used With products not provided with an EVooi EVsso EVss pin replace EVooo and R with or replace EVsso and EVss with Vss 3 The pins mounted depend on the product Refer to 2 1 Port Function to 2 2 1 With functions for each product in the RL78 G13 User s Manual Hardware 4 Please contact Renesas Electronics sales office for derating of operation under 85 to 105 Derating is the systematic reduction of load for the sake of improved reliability There are following differences between the products Industrial applications TA 40 to 105 C and the products A Consumer applications and D Industrial applications Parameter Operating ambient temperature Application A Consumer applications D Industrial applications 40 to 85 C G Industrial applications Ta
144. C 0 46 1 90 LA 85 0 75 3 30 Notes and Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 65 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Notes 1 Total current flowing into and EVppo including the input leakage current flowing when the level of the input pin is fixed to EVppo or Vss EVsso The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instruction execution by flash memory When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When RTCLPC 1 and setting ultra low current consumption AMPHS1 1 The current flowing into the RTC is included However not including the current flowing into the 12 bit interval timer and watchdog timer 6 Not including the current flowing into the RTC 12 bit interval timer and watchdog timer 7 Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V lt Voo lt 5 5 V 1 MHz to 32 MHz 2 4 V lt lt 5 5 V 1 M
145. During communication at same potential CSI mode 1 2 Modification of description in 4 During communication at same potential CSI mode 2 2 Modification of table in 5 During communication at same potential simplified mode 1 2 Modification of table and caution 5 During communication at same potential simplified mode 2 2 Modification of table and notes 1 and 4 in 6 Communication at different potential 1 8 V 2 5 V 3 V UART mode 1 2 Modification of table and notes 2 to 7 in 6 Communication at different potential 1 8 V 2 5 V 3 V UART mode 2 2 Modification of remarks 1 to 4 in 6 Communication at different potential 1 8 V 2 5 V 3 V UART mode 2 2 Modification of table in 7 Communication at different potential 2 5 V 3 V CSI mode 1 2 Modification of table and caution in 7 Communication at different potential 2 5 V 3 V CSI mode 2 2 Modification of table in 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode 1 3 Modification of table note 1 and caution in 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode 2 3 Modification of table note 1 and caution in 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode 3 3 Modification of remarks 3 and 4 in 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode 3 3 Modification of table in 9 Communication at different potential 1
146. ED ON CHIP OSCILLATOR VOLTAGE REGULATOR INTERRUPT CONTROL KRO P70 to KR7 P77 POR LVD CONTROL TOOLO P40 RESET X1 P121 X2 EXCLK P 122 XT1 P123 XT2 EXCLKS P 124 REGC RxD2 P14 RxD2 P76 INTPO P137 INTP1 P46 INTP1 P56 CZ INTP2 P47 INTP3 P30 INTP3 P57 m INTP4 P31 INTP4 P146 INTP5 P16 INTP5 P12 INTP6 P140 INTP6 P84 m INTP7 P141 INTP7 P85 a INTP8 P74 INTP8 P86 INTP9 P75 INTP9 P87 INTP10 P76 INTP10 P110 INTP11 P77 INTP11 P111 Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral redirection register PIOR PIOR in the RL78 G13 User s Manual Hardware Refer to Figure 4 8 Format of Peripheral I O Redirection Register R01DS0131EJ0310 Rev 3 10 Nov 15 2013 RENESAS Page 47 of 194 RL78 G13 1 OUTLINE 1 6 Outline of Functions 20 pin 24 pin 25 pin 30 pin 32 pin 36 pin products Caution This outline describes the functions at the time when Peripheral I O redirection register PIOR is set to 00H 1 2 X90014S8H X9LOLASY X 0014S8H L0LJSH X80014S8H 810146 XV00L4SH XVL0OLJSH Xg0014SH XgL0ordsd X90014SH XOLOLJSH Code flash memory KB 16 to 64 16 to 64 16 to 64 16 to 128 16 to 128 16 to 128 Data flash memory KB 4 4 4 _ 4108 _ 4to8 4108 RAM KB 2 to 4 1 2 to 4 2 to 4 1 2 to 128 2 to 128 2 to 128
147. F100CEALA R5F100CFALA R5F100CGALA R5F101CAALA R5F101CCALA R5F101CDALA R5F101CEALA R5F101CFALA R5F101CGALA R5F100CADLA R5F100CCDLA R5F100CDDLA R5F100CEDLA R5F100CFDLA R5F100CGDLA R5F101CADLA R5F101CCDLA R5F101CDDLA R5F101CEDLA R5F101CFDLA R5F101CGDLA JEITA Package Code RENESAS Code Previous Code MASS g P WFLGA36 4x4 0 50 PWLGOOS6KA A P36FC 50 AA4 2 0 023 2 32x b 9 S AB D T Z OO OO OO OO OO INDEX MARK w B y A gt E E y DETAIL DETAIL C DETAIL D E UN r 0 70 0 05 0 17 0 05 RO 17 0 05 0 70 0 05 ITEM DIMENSIONS r 0 55 0 05 R0 12 0 05 R0 12 0 05 0 55 0 05 D 4 00 0 10 r 0 75 29 E 4 00 0 10 r 0 55 0 39 F 0 20 y4 Z ttt 0 50 1 0 69 0 07 b 0 24 0 05 ob LAND PAD i i i x 0 05 i y 0 08 0 34 0 05 Pod 7 00 APERTURE OF 0 55 0 55 0 275 0 05 y SOLDER RESIST 0 75 0 75 20 0 75 0 55 0 05 0 55 0 05 R0 3540 05 c 0 70 0 05 0 70 0 05 2012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev 3 10
148. F100LHGFB X0 R5F100LJGFB XO Not R5F101LCAFB VO0 R5F101LDAFB V0 R5F101LEAFB VO mounted R5F101LFAFB V0 R5F101LGAFB V0 R5F101LHAFB VO R5F101LJAFB V0 R5F101LKAFBz2VO R5F101LLAFB V0 R5F101LCAFB X0 R5F101LDAFB X0 R5F101LEAFB XO R5F101LFAFB X0 R5F101LGAFB X0 R5F101LHAFB XO R5F101LJAFB X0 R5F101LKAFB X0 R5F101LLAFB X0 R5F101LCDFB V0 R5F101LDDFB V0 R5F101LEDFB VO R5F101LFDFB V0 R5F101LGDFB V0 R5F101LHDFB VO R5F101LUDFB V0 R5F101LKDFB V0 R5F101LLDFB 2VO R5F101LCDFB X0 R5F101LDDFB X0 R5F101LEDFB X0 R5F101LFDFB X0 R5F101LGDFB X0 R5F101LHDFB X0 R5F101LUDFB X0 R5F101LKDFB X0 R5F101LLDFB X0 64 pin plastic VEBGA Mounted R5F100LCABG U0 R5F100LDABG U0 R5F100LEABG U0 4 x 4 mm 0 4 mm R5F100LFABG U0 R5F100LGABG U0 R5F100LHABG UO pitch R5F100LJABG amp UO R5F100LCABG WO R5F100LDABG WO R5F100LEABG WO R5F100LFABG WO R5F100LGABG W0 R5F100LHABG WO R5F100LJABG WO Not R5F101LCABG U0 R5F101LDABG U0 R5F101LEABG UO mounted R5F101LFABG U0 R5F101LGABG U0 R5F101LHABG UO R5F101LJABG UO R5F101LCABG WO R5F101LDABG WO R5F101LEABG WO R5F101LFABG WO R5F101LGABG W0 R5F101LHABG WO R5F101LJABG WO Note For the fields of application refer to Figure 1 1 Part Number Memory Size and Package of RL78 G13 Caution The ordering part numbers represent the numbers at the time of publication For the latest ordering part numbers refer to the target product page of the Renesas Electronics website
149. F101FHAFP V0 R5F101FJAFP V0 R5F101FKAFP VO R5F101FLAFPZVO R5F101FAAFP X0 R5F101FCAFP X0 R5F101FDAFP X0 R5F101FEAFP X0 R5F101FFAFP X0 R5F101FGAFP XO0 R5F101FHAFP X0 R5F101FJAFP X0 R5F101FKAFP X0 R5F101FLAFP X0 R5F101FADFP V0 R5F101FCDFPzVO0 R5F101FDDFP VO R5F101FEDFP V0 R5F101FFDFP V0 R5F101FGDFP VO R5F101FHDFPZVO R5F101FJDFP V0 R5F101FKDFP VO R5F101FLDFPzVO R5F101FADFP X0 R5F101FCDFP X0 R5F101FDDFP X0 R5F101FEDFP X0 R5F101FFDFP X0 R5F101FGDFP XO R5F101FHDFP X0 R5F101FJDFP X0 R5F101FKDFP XO R5F101FLDFP X0 Note For the fields of application refer to Figure 1 1 Part Number Memory Size and Package of RL78 G13 Caution The ordering part numbers represent the numbers at the time of publication For the latest ordering part numbers refer to the target product page of the Renesas Electronics website R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 7 of 194 Nov 15 2013 RL78 G13 1 OUTLINE Table 1 1 List of Ordering Part Numbers 5 12 Pin count Package Data flash Fields of Ordering Part Number Application Note 48 pin plastic LFQFP Mounted R5F100GAAFB VO0 R5F100GCAFB VO R5F100GDAFB VO 7 X 7 mm 0 5 mm R5F100GEAFB V0 R5F100GFAFBzVO R5F100GGAFB VO pitch R5F100GHAFB VO R5F100GJAFB V0 R5F100GKAFB VO R5F100GLAFB VO R5F100GAAFB X0 R5F100GCAFB X0 R5F100GDAFB XO R5F100GEAFB X0 R5F100GFAFB X0 R5F100GGAFB XO R5F100GHAFB XO R5F100GJAFB X0 R5F100GKAFB XO R5F100GLA
150. FB R5F101LLAFB R5F100LCDFB R5F100LDDFB R5F100LEDFB R5F100LFDFB R5F100LGDFB R5F100LHDFB R5F100LJDFB R5F100LKDFB R5F100LLDFB R5F101LCDFB R5F101LDDFB R5F101LEDFB R5F101LFDFB R5F101LGDFB R5F101LHDFB R5F101LJDFB R5F101LKDFB R5F101LLDFB R5F100LCGFB R5F100LDGFB R5F100LEGFB R5F100LFGFB R5F100LGGFB R5F100LHGFB R5F100LJGFB JEITA Package Code RENESAS Code Previous Code MASS TYP g P LFQFP64 10x10 0 50 064 P64GB 50 UEU 2 0 35 HD E D detail of lead end 48 33 NI 449 32 E HE n c UNIT mm 1 64 C 17 ITEM DIMENSIONS D 10 00 0 20 1 16 10 00 0 20 TT HD 12 00 0 20 LJE 12 00 0 20 1 60 ZD A1 0 10 0 05 A2 1 40 0 05 r bl x S A3 0 25 A b 0220 05 A24 c 0 145 0 022 Y L 0 50 m T s 0 60 0 15 EA M Ii L1 1 00 0 20 mim fs 1 0 50 0 08 y 0 08 ZD 1 25 NOTE ZE 1 25 Each lead centerline is located within 0 08 mm of its true position at maximum material condition
151. FB ZVO R5F100PFAFB XO R5F100PGAFB X0 R5F100PHAFB X0 R5F100PJAFB XO R5F100PKAFB X0 R5F100PLAFB X0 R5F100PFDFB VO R5F100PGDFB VO R5F100PHDFB VO R5F100PJDFB V0 R5F100PKDFB V0 R5F100PLDFB V0 R5F100PFDFB X0 R5F100PGDFB X0 R5F100PHDFB XO R5F100PJDFB X0 R5F100PKDFB X0 R5F100PLDFB X0 R5F100PFGFB VO R5F100PGGFB VO0 R5F100PHGFB VO R5F100PJGFB VO R5F100PFGFB XO R5F100PGGFB X0 R5F100PHGFB X0O R5F100PJGFB XO Not mounted R5F101PFAFB VO R5F101PGAFB VO0 R5F101PHAFB VO R5F101PJAFB VO0 R5F101PKAFB V0 R5F101PLAFB V0 R5F101PFAFB XO R5F101PGAFB X0 R5F101PHAFB X0 R5F101PJAFB XO R5F101PKAFB X0 R5F101PLAFB X0 R5F101PFDFB V0 R5F101PGDFB V0 R5F101PHDFB VO R5F101PJDFB V0 R5F101PKDFB V0 R5F101PLDFB V0 R5F101PFDFB X0 R5F101PGDFB X0 R5F101PHDFB XO R5F101PJDFB X0 R5F101PKDFB X0 R5F101PLDFB X0 100 pin plastic LQFP 14 x 20 mm 0 65 mm pitch Mounted R5F100PFAFA VO0 R5F100PGAFA VO R5F100PHAFA VO R5F100PJAFA VO R5F100PKAFA VO R5F100PLAFA VO R5F100PFAFA X0 R5F100PGAFA X0 R5F100PHAFA XO R5F100PJAFA XO R5F100PKAFA X0 R5F100PLAFA X0 R5F100PFDFA VO R5F100PGDFA VO R5F100PHDFA VO R5F100PJDFA VO R5F100PKDFA VO R5F100PLDFA VO R5F100PFDFA X0 R5F100PGDFA X0 R5F100PHDFA XO R5F100PJDFA X0 R5F100PKDFA X0 R5F100PLDFA X0 R5F100PFGFA VO R5F100PGGFA VO R5F100PHGFA VO R5F100PJGFA VO R5F100PFGFA X0O R5F100PGGFA X0 R5F100PHGFA XO R5F100PJGFA XO Not mounted R5F101PFAFA VO R5F101PGAFA VO
152. FB X0 R5F100GADFB VO0 R5F100GCDFB VO0 R5F100GDDFB VO R5F100GEDFB V0 R5F100GFDFB V0 R5F100GGDFB VO R5F100GHDFB VO0 R5F100GJDFB V0 R5F100GKDFB VO R5F100GLDFB V0 R5F100GADFB X0 R5F100GCDFB X0 R5F100GDDFBZXO R5F100GEDFB X0 R5F100GFDFB X0 R5F100GGDFB X0 R5F100GHDFB X0 R5F100GJDFB X0 R5F100GKDFB X0 R5F100GLDFB X0 R5F100GAGFB VO R5F100GCGFB VO R5F100GDGFB VO R5F100GEGFB VO R5F100GFGFBzVO R5F100GGGFB VO R5F100GHGFB VO R5F100GJGFB VO R5F100GAGFB X0 R5F100GCGFB XO R5F100GDGFB XO R5F100GEGFB XO0 R5F100GFGFB XO R5F100GGGFB XO R5F100GHGFB XO R5F100GJGFB XO Not R5F101GAAFB VO0 R5F101GCAFBz VO R5F101GDAFB VO mounted R5F101GEAFB V0 R5F101GFAFB V0 R5F101GGAFB VO R5F101GHAFB V0 R5F101GJAFB V0 R5F101GKAFB VO R5F101GLAFB VO R5F101GAAFB X0 R5F101GCAFB X0 R5F101GDAFB X0 R5F101GEAFB X0 R5F101GFAFB X0 R5F101GGAFB X0O R5F101GHAFB X0 R5F101GJAFB XO R5F101GKAFB X0 R5F101GLAFB X0 R5F101GADFB VO0 R5F101GCDFB VO0 R5F101GDDFB VO R5F101GEDFBZVO R5F101GFDFB V0 R5F101GGDFB VO R5F101GHDFB VO0 R5F101GJDFB V0 R5F101GKDFB VO R5F101GLDFBZVO R5F101GADFB X0 R5F101GCDFB X0 R5F101GDDFBZXO R5F101GEDFB X0 R5F101GFDFB X0 R5F101GGDFB X0 R5F101GHDFB X0 R5F101GJDFB X0 R5F101GKDFBZXO R5F101GLDFB X0 Note For the fields of application refer to Figure 1 1 Part Number Memory Size and Package of RL78 G13 Caution The ordering part numbers represent the numbers at the time of publication For the
153. FB X0 R5F100MLAFB X0 R5F100MFDFB ZVO R5F100MGDFB VO R5F100MHDFB VO R5F100MJDFB V0 R5F100MKDFBzVO R5F100MLDFB V0 R5F100MFDFB X0 R5F100MGDFB X0 R5F100MHDFB XO R5F100MJDFB X0 R5F100MKDFB X0 R5F100MLDFB X0 R5F100MFGFB VO R5F100MGGFB VO R5F100MHGFB VO R5F100MJGFB V0 R5F100MFGFB X0 R5F100MGGFB X0 R5F100MHGFB XO R5F100MJGFB X0 Not mounted R5F101MFAFB VO0 R5F101MGAFB VO R5F101MHAFB VO R5F101MJAFB V0 R5F101MKAFB VO R5F101MLAFB V0 R5F101MFAFB X0 R5F101MGAFB X0 R5F101MHAFBZXO R5F101MJAFB X0 R5F101MKAFB X0 R5F101MLAFB X0 R5F101MFDFB V0 R5F101MGDFB VO R5F101MHDFB VO R5F101MJDFB V0 R5F101MKDFBzVO R5F101MLDFB V0 R5F101MFDFB X0 R5F101MGDFB X0 R5F101MHDFB X0 R5F101MJDFB X0 R5F101MKDFB X0 R5F101MLDFB X0 For the fields of application refer to Figure 1 1 Part Number Memory Size and Package of RL78 G13 Caution The ordering part numbers represent the numbers at the time of publication For the latest ordering part numbers refer to the target product page of the Renesas Electronics website R01DS0131EJ0310 Rev 3 10 Nov 15 2013 ztENESAS Page 13 of 194 RL78 G13 Pin count 100 pins Package 100 pin plastic LFQFP 14 x 14 mm 0 65 mm pitch 1 OUTLINE Table 1 1 List of Ordering Part Numbers Data flash Mounted Fields of Application Note 11 12 Ordering Part Number R5F100PFAFBz VO R5F100PGAFB VO R5F100PHAFB VO R5F100PJAFB VO R5F100PKAFB VO R5F100PLA
154. Hz to 16 MHz LS low speed main mode 1 8 V lt Voo lt 5 5 V 1 MHz to 8 MHz LV low voltage main mode 1 6 V lt lt 5 5 V 1 MHz to 4 MHz 8 Regarding the value for current to operate the subsystem clock in STOP mode refer to that in HALT mode Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fiH High speed on chip oscillator clock frequency 3 fsu amp Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation and STOP mode temperature condition of the value is TA 25 R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 66 of 194 Nov 15 2013 RL78 G13 Parameter Supply current e 1 Operating mode 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 Flash ROM 96 to 256 KB of 30 to 100 pin products 40 to 85 C 1 6 V lt EVppo 1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 1 2 Conditions HS high fin 32 MHz Basic Voo 5 0 V 2 3 mA speed main operation Vpp 3 0 V 23 mA mo d le Note 5 Normal Voo 5 0 V 5 2 8 5 mA operation Von 3 0 V 52 85 mA fiu 24 MHz Normal Voo 5 0 V 4 1 6 6 mA operation Von 3 0 V 4 1 66 mA 16 MHz Normal Voo 5 0 V 3 0 4 7 mA operation Vo
155. IONS A D Ta 40 to 85 C Ta 40 to 85 C Vppr lt lt 5 5 V Vss 0 V Detection voltage Parameter Supply voltage level Conditions Power supply rise time lt Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Vivp10 Power supply rise time Power supply fall time Vivo11 Power supply rise time Power supply fall time Vivp12 Power supply rise time Power supply fall time Vivo13 Power supply rise time Power supply fall time Minimum pulse width Detection delay time R01DS0131EJ0310 Rev 3 10 Nov 15 2013 ztENESAS lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt Page 119 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C LVD Detection Voltage of Interrupt amp Reset Mode Ta 40 to 85 C VPpn lt lt 5
156. ITIPLY ACCUMULATOR DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT LOW SPEED ON CHIP OSCILLATOR RTC1HZ P30 TOOLRXxD P11 TOOLTxD P12 SDAAO P61 SDAAO P13 SCLAO P60 SCLAO P14 SDAA1 P63 SCLA1 P62 PCLBUZO P140 PCLBUZO P31 PCLBUZ1 P141 PCLBUZ1 P55 CRC WINDOW WATCHDOG TIMER 12 BIT INTERVAL TIMER O C PORT 10 K 3 gt P100 to P102 lt Pon K P110 P111 C PORT 12 pee P121 to P124 lt gt PORT 13 MES Be PORT 14 P140 to P147 PORT 15 C T P150 to P156 KRO P70 to KEY RETURN 8 KR7 P77 POWER ON RESET VOLTAGE DETECTOR POR LVD CONTROL RESET CONTROL ON cHIP DEBUG TOOLO P40 SYSTEM CONTROL RESET X1 P121 X2 EXCLK P122 XT1 P123 XT2 EXCLKS P124 HIGH SPEED ON CHIP OSCILLATOR VOLTAGE REGULATOR REGC RxD2 P14 RxD2 P76 INTPO P137 INTP1 P46 INTP1 P56 INTP2 P47 INTP3 P30 INTP3 P57 INTP4 P31 INTP4 P146 INTP5 P16 INTP5 P12 INTP6 P140 INTP6 P84 INTP7 P141 INTP7 P85 INTP8 P74 INTP8 P86 INTP9 P75 INTP9 P87 INTP10 P76 INTP10 P110 INTP11 P77 INTP11 P111 INTERRUPT CONTROL REAL TIME CLOCK Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral redirection register PIOR PIOR in the RL78 G13 User s Manual Hardware Refer to Figure 4 8 Format of Peripheral I O Redirection Register R01DS0131EJ0310 Rev 3 10 N
157. J0310 Rev 3 10 Nov 15 2013 ztENESAS TPw Page 172 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 3 6 4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode Ta 40 to 105 C lt lt 5 5 V Vss 0 V Parameter Conditions lt Detection Supply voltage level Power supply rise time voltage Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Power supply rise time Power supply fall time Minimum pulse width BIBI lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt Detection delay time LVD Detection Voltage of Interrupt amp Reset Mode 40 to 105 C VPpn lt lt 5 5 V Vss 0 V Parameter Conditions Interrupt and reset Vivopo Veoc2 Vroco 0 1 1 falling reset voltage mode LVIS1 LVISO 1 0 Rising release reset voltage Falling interrupt voltage Vivbp2 LVIS1 LVISO 0 1 Rising release reset voltage Falling interrupt voltage Vivops LVIS1 LVISO 0 0 Rising release reset voltage
158. KRS5 INTP9 P76 KR6 INTP10 RXD2 P77 KR7 INTP11 TXD2 P67 THM3 TO13 P66 TI12 TO12 P65 TM 1 TO11 64 7110 010 P31 TIOS TOOS INTP4 PCLBUZO P63 SDAA1 P62 SCLA1 2 When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced it is recommended to supply separate powers to the EVppo and EVpni pins and connect the Vss EVsso and EVsst pins to separate ground lines 3 Functions in parentheses in the above figure can be assigned via settings in the peripheral redirection register PIOR Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 Nov 15 2013 RENESAS Page 32 of 194 RL78 G13 1 4 Pin Identification ANIO to ANI14 ANI16 to ANI26 AVREFM AVREFP EVppo EVppt EVsso EVss1 EXCLK EXCLKS INTPO to INTP11 Nov 15 2013 Analog input A D converter reference potential side input A D converter reference potential side input Power supply for port Ground for port External clock input Main system clock External clock input Subsystem clock Interrupt request from REGC RESET RTC1HZ RxDO to RxD3 SCKOO SCKO1 SCK10 SCK11 SCK20 SCK21 SCLAO SCLA1 SCLAO SCLA1 SCLOO SCLO01 SCL10 SCL11 SCL20 SCL21 SCL30 SCL31 SDAAO SDAA1 SDAOO 1 OUTLINE Regulator capacitance Reset Real
159. LFDFA X0 R5F101LGDFA X0 R5F101LHDFA XO R5F101LUDFA X0 R5F101LKDFA X0 R5F101LLDFA X0 Note For the fields of application refer to Figure 1 1 Part Number Memory Size and Package of RL78 G13 Caution The ordering part numbers represent the numbers at the time of publication For the latest ordering part numbers refer to the target product page of the Renesas Electronics website R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 11 of 194 Nov 15 2013 RL78 G13 1 OUTLINE Table 1 1 List of Ordering Part Numbers 9 12 Pin count Package Data flash Fields of Ordering Part Number Application Note 64 pin plastic LFQFP Mounted R5F100LCAFB VO R5F100LDAFB V0 R5F100LEAFB VO 10 x 10 mm 0 5 mm R5F100LFAFB VO0 R5F100LGAFB VO0 R5F100LHAFB VO pitch R5F100LJAFBZ2VO R5F100LKAFB VO R5F100LLAFB VO R5F100LCAFB X0 R5F100LDAFB X0 R5F100LEAFB XO R5F100LFAFB X0 R5F100LGAFB X0 R5F100LHAFB XO R5F100LUAFB X0 R5F100LKAFB X0 R5F100LLAFB X0 R5F100LCDFB VO0 R5F100LDDFB V0 R5F100LEDFB VO R5F100LFDFB V0 R5F100LGDFBzVO R5F100LHDFB VO R5F100LUDFB V0 R5F100LKDFB V0 R5F100LLDFB VO R5F100LCDFB X0 R5F100LDDFB X0 R5F100LEDFB XO R5F100LFDFB X0 R5F100LGDFB X0 R5F100LHDFB X0 R5F100LUDFB X0 R5F100LKDFB X0 R5F100LLDFB X0 R5F100LCGFB V0 R5F100LDGFB VO0 R5F100LEGFB VO R5F100LFGFB VO R5F100LGGFB V0 R5F100LHGFB VO0 R5F100LUGFB VO R5F100LCGFB X0 R5F100LDGFB X0 R5F100LEGFB X0 R5F100LFGFB XO R5F100LGGFB X0 R5
160. O Poo TIO0 O O P63 SDAA1 P144 SO30 TxD3 O O P62 SCLA1 P143 SI30 RxD3 SDA30 O P61 SDAAO P142 SCK30 SCL30 O P60 SCLAO 3 9 1011 12 13 14 15 16 17 18 19 20 HH RoOOrrrytho o 5 8888 OOO o ix E O m gt gt zz od9occouoszxamg gl L s EK Em xQ Z Treats ress NNSNGaSoOEES qt9Z age osar E ag oa A RS a s e aa Cautions 1 Make EVsso pin the same potential as Vss pin 2 Make Voo pin the potential that is higher than EVppo pin 3 Connect the REGC pin to Vss via a capacitor 0 47 to 1 Remarks 1 For pin identification see 1 4 Pin Identification 2 When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced it is recommended to supply separate powers to the Vpp and EVppo pins and connect the Vss and EVsso pins to separate ground lines 3 Functions in parentheses in the above figure can be assigned via settings in the peripheral redirection register PIOR Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 QE NE S AS Page 29 of 194 Nov 15 2013 RL78 G13 1 OUTLINE 1 3 13 100 pin products 100 plastic LQFP 14 x 14 mm 0 65 mm pitch a8 98 or 8 oO es SESS Exo Q o a lt 2 lt 5
161. O3 TOO3 P51 INTP2 SO11 O P13 TxD2 SO20 SDAAO TIOA TOO4 O PI15 PCLBUZI1 SCK20 SCL20 TIO2 TOO2 N 5 1 5111 5 11 P30 INTP3 RTC1HZ SCK11 SCL11 P7O KRO SCK21 SCL21 P71 KR1 SI21 5DA21 P72 KR2 SO21 P73 KR3 P31 TIO3 TOO3 INTP 4 P CLBUZO P62 P61 SDAAO P60 SCLAO P137 NTPO O P122 X2 EXCLK O P121 X1 O Caution Connect the REGC pin to Vss via a capacitor 0 47 to 1 Remarks 1 For pin identification see 1 4 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware 3 It is recommended to connect an exposed die pad to Vss R01DS0131EJ0310 Rev 3 10 Nov 15 2013 ztENESAS Page 22 of 194 RL78 G13 1 OUTLINE 1 3 8 44 pin products e 44 pin plastic LQFP 10 x 10 mm 0 8 mm pitch P11 SIO0 RXDO TOOLRxD SDAOO TIO6 TOO6 P12 SO00 TxDO TOOLTxD TIOS TOO5 P13 TxD2 SO20 SDAAO TIO4 TOO4 P14 RxD2 SI20 SDA20 SCLAO TIO3 TOO3 P15 PCLBUZ1 SCK20 SCL20 T102 TO02 P16 TIO1 TOO1 INTPS RXDO P10 SCKO0 SCLOO TIO7 TOO7 P17 TIO2 TOO2 TXDO P51 INTP2 SO11 O P147 ANI18 O P146 P21 ANH AVngrM O P20 ANIO AVnerP O P01 TOOO RxD1 O POO TIOO TXD1 P120 ANI19 RESET O P124 XT2 EXCLKS O P123 XT1 O P137 INTPO O P12
162. OL X1 P121 S020 P13 z Py PCLBUZUIPS HIGH SPEED X2 EXCLKIP122 PCLBUZ1 P141 ON CHIP 1 12 CLOCK OUTPUT 123 SCK21 P70 PCLBUZ1 P55 CONTROL OSCILLATOR XT2 EXCLKS P124 SI21 P71 SO21 P72 MULTIPLIER amp CRC SCK30 P142 DIVIDER REGC SI30 P143 MULITIPLY ACCUMULATOR SO30 P144 RxD2 P14 RxD2 P76 SCK31 P54 DIRECT MEMORY INTPO P137 SI31 P53 ACCESS CONTROL INTP1 P50 031 P52 INTP2 P51 BCD INTP3 P30 SCL20 P15 SDA20 P14 ADJUSTMENT INTP4 P31 WINDOW INTERRUPT INTP5 P16 INTP5 P12 SCL21 P70 WATCHDOG CONTROL INTP6 P140 SDA21 P71 TIMER INTP7 P141 SCL30 P142 LOW SPEED INTP8 P74 SDA30 P143 INTP9 P75 SCL31 P54 INTP10 P76 INTP10 P1 10 SDA31 P53 INTP11 P77 INTP11 P111 redirection register PIOR REAL TIME RTC1HZ P30 a CLOCK C Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral PIOR in the RL78 G13 User s Manual Hardware Refer to Figure 4 8 Format of Peripheral I O Redirection Register R01DS0131EJ0310 Rev 3 10 Nov 15 2013 RENESAS Page 45 of 194 1 5 13 100 pin products TIMER ARRAY TIMER ARRAY UNITO Bch UNIT 4ch TI00 P00 C PORT 0 7 PO00 to P06 TOOO PO1 TH0 TO10 P64 TIO1 TOO1 P16 TH 1 TO11 P65 C PORT 1 P10toP17 102 002 17 TIO2 TO02 P15 12 7012 66 lt PORT 2 P20 to P27 TI03 TO03 P31 TH3 TO13 P67 TIO3 TOO3 P14 lt 2 PORT 3 K 2 gt P30 P31
163. ONS Ta 40 to 105 C 8 Communication at different potential 1 8 V 2 5 V 3 V simplified mode 2 2 Ta 40 to 105 C 2 4 V lt EVppo EVpni lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed main Mode MIN MAX Data setup time reception tsu DAT 4 0 V lt EVppo lt 5 5 V 1 fwck 340 ns 2 7 V lt Vo 4 0 V Co 50 pF Rb 2 7 2 7 V EVppo lt 4 0 V 1 340 ns 2 3 V lt Vo lt 27 V Note Co 50 pF Re 2 7 4 0 V EVppo lt 5 5 V 1 760 ns 2 7 V lt Vo 4 0 V Cs 100 pF Ro 2 8 KQ 2 7 V EVppo lt 4 0 V 1 760 ns 2 3 V lt Vo 2 7 V Note Co 100 pF Ro 2 7 KQ 2 4 V EVppo lt 3 3 V 1 570 ns 1 6 V lt Vo lt 2 0 V mee Co 100 pF Rb 5 5 Data hold time transmission tHD DAT 4 0 V EVppo 5 5 V 0 770 ns 2 7 V lt Vo 4 0 V Cb 50 pF Rb 2 7 2 7 V EVppo lt 4 0 V 0 770 ns 2 3 V lt Vo lt 2 7 V Co 50 pF Rb 2 7 4 0 V lt EVppo lt 5 5 V 0 1420 ns 2 7 V lt Vo 4 0 V 100 pF Rb 2 8 KQ 2 7 V EVppo lt 4 0 V 0 1420 ns 2 3 V lt Vo lt 2 7 V 100 pF Rb 2 7 KQ 2 4 V lt EVppo lt 3 3 V 0 1215 ns 1 6 V lt Vo 2 0 V 100 pF Rb 5 5 Notes 1 The value must also be equal to or less than 4 2 Set the fuck value
164. OO2 P15 TI03 TOO3 P31 103 003 14 104 004 13 05 05 12 TIO6 TOO6 P1 1 TI07 TOO7 P10 RxD2 P14 LOW SPEED ON CHIP OSCILLATOR 11 16 TxDO0 P12 TxDO P17 RxD1 P01 TxD1 P00 SCKO00 P10 100 11 000 12 SCK11 P30 SI 1 P50 SO11 P51 SCLOO P10 SDAOO P11 SCL11 P30 SDA11 P50 RxD2 P14 TxD2 P13 SCK20 P15 SI20 P14 SO20 P13 SCL20 P15 SDA20 P14 TIMER ARRAY UNIT 8ch WINDOW WATCHDOG TIMER 12 BIT INTERVAL TIMER REAL TIME CLOCK SERIAL ARRAY UNITO 4ch SERIAL ARRAY UNIT 2ch Q CODE FLASH MEMORY DATA FLASH MEMORY TOOLRxD P11 TOOLTxD P12 Voo Vss SDAAO P61 SDAAO P13 SCLAO P60 SCLAO P14 PCLBUZO P31 PCLBUZ1 P15 CLOCK OUTPUT E CONTROL MULTIPLIER amp DIVIDER MULITIPLY ACCUMULATOR DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT Cj roro gt POO PO1 lt rw Kx P10 to P17 lt row Kab to P23 lt Ports P31 E sos K P60 to P62 eem ee ken 2 P121 P122 em A D CONVERTER POWER ON RESET VOLTAGE DETECTOR SYSTEM CONTROL VOLTAGE REGULATOR INTERRUPT CONTROL P147 ANIO P20 to ANIS P23 ANI16 P01 ANI17 POO ANI18 P147 ANI19 P120 20 AVnerv P21 POR LVD CONTROL REGC RxD2 P14 INTPO P137
165. P P21 ANI1 AVREFM P30 INTP3 SCK11 SCL11 P16 TIO1 TOO1 INTP5 RxDO P12 SO00 TxDO TOOLTxD T105 TOOS P11 SI00 RxDO TOOLRxD SDAOO TIOG TO06 P24 ANI4 P23 ANI3 P51 INTP2 1 3011 P17 TIO2 TO02 TxDO P13 TxD2 SO20 SDAA0 T104 TO04 P10 SCK00 SCLOO TIO7 T007 Caution Connect the REGC pin to Vss via a capacitor 0 47 to 1 Remarks 1 For pin identification see 1 4 Pin Identification P147 ANI18 P25 ANI5 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 Nov 15 2013 zeENESAS Page 21 of 194 RL78 G13 1 3 7 40 pin products 1 OUTLINE e 40 pin plastic HWQFN 6 x 6 mm 0 5 mm pitch P26 ANI6 P25 ANI5 P24 ANI4 P23 ANI3 P22 ANI2 P21 ANIL AVrerm P20 ANIO AVrere P01 TOO0 RxD1 P00 TIOO TxD1 P120 ANI19 INDEX MARK P 10 SCKO00 SCLOO TIO7 TOO7 P147 ANI18 9 E S lt a x un E e Q X x amp a exposed die pad P124 XT2 EXCLKS O O P12 SOO0 TxDO TOOLTXxD TIO5 TOO5 P 16 TIO1 TOOl INTP 5 RXDO P 17 TIO2 TOO2 TXDO O P14 RxD2 SI20 S DA20 SCLAO TI
166. P05 05 05 12 TI06 TO06 P06 TI06 TO06 P11 TI07 TO07 P41 T107 TOO7 P10 RxD2 P14 RxD2 P76 WINDOW WATCHDOG LOW SPEED ON CHIP OSCILLATOR RTC1HZ P30 _ RxDO0 P11 RxD0 P16 TxDO P12 TxDO0 P17 RxD1 P03 TxD1 P02 SCK00 P10 SCK00 P55 SI00 P11 SI00 P16 SO00 P12 SO00 P17 SCK01 P75 SI01 P74 SO01 P73 SCK10 P04 SH 0 P03 SO10 P02 SCK11 P30 511 1 50 5011 51 SCLOO P10 SDAOO P11 SCLO1 P75 50 01 74 SCL10 P04 SDA10 P03 SCL11 P30 SDA11 P50 RxD2 P14 RxD2 P76 TxD2 P13 TxD2 P77 SCK20 P15 SI20 P14 SO20 P13 SCK21 P70 SI21 P71 5021 72 SCL20 P15 SDA20 P14 SCL21 P70 SDA21 P71 roducts TIMER ARRAY UNIT 8ch SERIAL ARRAY UNITO 4ch UART2 CODE FLASH MEMORY DATA FLASH MEMORY RAM Vss TOOLRxD P11 EVsso TOOLTxD P12 SDAAO P61 SDAAO0 P13 SCLAO P60 SCLAO P14 SERIAL INTERFACE IICAO BUZZER OUI PCLBUZO P140 rz y PCLBUZO PS1 PCLBUZ1 P141 CU OH PCLBUZ1 P55 CONTROL MULTIPLIER amp DIVIDER MULITIPLY ACCUMULATOR CRC DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT 1 OUTLINE porto Km P00 to P06 lt rori Km P10 to P17 lt gt PORT 2 P20 to P27 lt ros Kz Poo P31 lt rora to P43 PORT 5 6 _ gt 50 to P55 lt soms P60 to P63 lt uen
167. P125 to P127 P130 P140 to P147 4 0 V EVppo lt 5 5 V lou 3 0 mA 2 7 V EVopo 5 5 V 2 0 mA 2 4 V EVppo 5 5 V 21 5 mA P20 to P27 P150 to P156 2 4 V lt lt 5 5 V lone 100 LA Output voltage low POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 4 0 V EVppo lt 5 5 V lou 8 5 mA 4 0 V EVppo lt 5 5 V 3 0 mA 2 7 V lt EVopo 5 5 V lou 1 5 mA 2 4 V EVppo 5 5 V lou 0 6 mA P20 to P27 P150 to P156 2 4 V 5 5 V loi 400 u A P60 to P63 4 0 V EVppo lt 5 5 V lois 15 0 mA 4 0 V EVppo lt 5 5 V lots 5 0 mA 2 7 V EVopo 5 5 V lois 3 0 mA 2 4 V EVppo 5 5 V lois 2 0 mA Caution P00 P02 to P04 P10 to P15 P17 P43 to P45 P50 P52 to P55 P71 P74 P80 to P82 P96 P142 to P144 do not output high level in N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins R01DS0131EJ0310 Rev 3 10 Nov 15 2013 ztENESAS Page 130 of 194 RL78 G13 Ta 40 to 105 C 2 4 V x EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V 5 5 Input leakage current
168. P30 SDA11 P50 SERIAL ARRAY UNIT 2ch RxD2 P14 TxD2 P13 SCK20 P15 SI20 P14 SO20 P13 SCK21 P70 SI21 P71 021 72 SCL20 P15 SDA20 P14 SCL21 P70 SDA21 P71 CODE FLASH MEMORY DATA FLASH MEMORY RAM SERIAL INTERFACE IICAO BUZZER OUTPUT CLOCK OUTPUT CONTROL MULTIPLIER amp DIVIDER MULITIPLY ACCUMULATOR MEMORY DIREC ACCESS CONTROL BCD ADJUSTMENT TOOLRxD P11 TOOLTxD P12 Vss SDAAO P61 SDAAO P13 SCLAO P60 SCLAO P14 PCLBUZO P31 PCLBUZ1 P15 CRC gt roro K gt P00 P01 lt Kx P10 to P17 lt 26 lt rows P31 A lt rows 51 rows P60 to P62 Kj s Cm P70 to P73 PORT 12 PA 4 P121 to P124 PORT 13 P137 lt PORT14 P147 ANIO P20 to ANI6 P26 P40 C A D CONVERTER ANI18 P147 ANI19 P120 AVnere P20 AVnerv P21 C KEY RETURN 4 KRO P70 to KR3 P73 POWERONRESEU koi vp VOLTAGE CONTROL DETECTOR SYSTEM CONTROL RESET X1 P121 X2 EXCLK P122 XT1 P123 OSCILLATOR XT2 EXCLKS P124 VOLTAGE REGULATOR REGC RxD2 P14 INTPO P137 INTP1 P50 2 INTP2 P51 cn INTP3 P30 INTP4 P31 la INTP5 P16 INTERRUPT CONTROL Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral redirection register PIOR PIOR in the RL78 G13 User
169. PHAFA R5F100PJAFA R5F100PKAFA R5F100PLAFA R5F101PFAFA R5F101PGAFA R5F101PHAFA R5F101PJAFA R5F101PKAFA R5F101PLAFA R5F100PFDFA R5F100PGDFA R5F100PHDFA R5F100PJDFA R5F100PKDFA R5F100PLDFA R5F101PFDFA R5F101PGDFA R5F101PHDFA R5F101PJDFA R5F101PKDFA R5F101PLDFA R5F100PFGFA R5F100PGGFA R5F100PHGFA R5F100PJGFA JEITA Package Code RENESAS Code Previous Code MASS g P LQFP100 14x20 0 65 PLQP0100JC A P100GF 65 GBN 1 0 92 gt detail lead end 13 IP 1 e gt L Lp 1 gt UNIT mm ITEM DIMENSIONS D 20 00 0 20 E 14 00 0 20 HD 22 00 0 20 HE 16 00 0 20 AA A 1 60 MAX A1 0 10 0 05 2 1 40 0 05 Y A3 0 25 0 08 i b 0 32 9 07 40 055 0 1457 0 045 1 0 50 Lp 0 60 0 15 L1 1 00 0 20 o 5 0 3 239 0 65 0 13 y 0 10 ZD 0 575 ZE 0 825 2012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 193 of 194 Nov 15 2013 RL78 G13 4 PACKAGE DRAWINGS 4 14 128 pin Products R5F100SHAFB R5F100SJAFB R5F100SKAFB R5F100SLAFB R5F101SHAFB R5F101SJAFB R5F101SKAFB R5F101SLAFB R5F100SHDFB R5F100SJDFB R5F100SKDFB R5F100SLDFB R
170. RTC1HZ SCK1 1 SCL1 1 P10 SCK00 SCLOO TIO7 TOO7 P5O INTP1 SH 1 SDA11 O P147 ANI18 O P146 35 3433 32 O P70 KRO SCK21 SCL21 O P71 KR1 SI21 SDA21 O P72 KR2 SO21 P73 KR3 SO01 O P74 KR4 INTP8 SI01 SDA01 O P75 KR5 INTP9 SCKO1 SCLO1 O P76 KR6 INTP10 RXD2 O P77 KR7 INTP11 TXD2 O P31 TIO3 TOOS INTPA PCLBUZO O P63 O P62 O P61 SDAAO O P60 SCLAO O O G O oro o 8 EZBOORMNAXEOS m Z lt Oa O Z X aN S i C X GQ l S O o KK KK A N N aon gt gt ES Qi gt lt E d Mi x A n T a n S n Caution Connect the REGC pin to Vss via a capacitor 0 47 to 1 LF Remarks 1 For pin identification see 1 4 Pin Identification 2 Functions in parentheses in the above figure can be assigned via settings in the peripheral I O redirection register PIOR Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 26 of 194 Nov 15 2013 RL78 G13 1 OUTLINE 1 3 11 64 pin products e 64 pin plastic LQFP 12 x 12 mm 0 65 mm pitch e 64 pin plastic LFQFP 10 x 10 mm 0 5 mm pitch ee 5 or 8 Ex ze E SESS OS S optt Q ro ST _ lt En KERE x o
171. Resonator connection fsus 32 768 5 70 Square wave input Resonator connection fsue 32 768 kHz te5 Ta 85 C Square wave input Resonator connection fsue 32 768 kHz te5 Ta 105 Square wave input Resonator connection Note 6 1203 40 25 50 70 85 Ta 105 Notes and Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 134 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Notes 1 Total current flowing into Voo and EVppo including the input leakage current flowing when the level of the input pin is fixed to Voo EVppo or Vss EVsso The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instruction execution by flash memory When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When RTCLPC 1 and setting ultra low current consumption AMPHS1 1 The current flowing into the RTC is included Howeve
172. SS g P LQFP52 10x10 0 65 PLQPO0052JA A P52GB 65 GBS 1 0 3 detail of lead end E HE p UNIT mm ITEM DIMENSIONS 10 00 50 10 10 00 40 10 12 00 0 20 12 00 0 20 1 70 0 10 0 05 1 40 0 32 0 05 0 145 0 055 0 50 0 15 0 to 8 0 65 0 13 0 10 gt N T I m gt J NOTE 1 Dimensions X1 and X2 do not include mold flash 2 Dimension X3 does not include trim offset P 2012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev 3 10 QE NE S AS Page 186 of 194 Nov 15 2013 RL78 G13 4 PACKAGE DRAWINGS 4 11 64 pin Products R5F100LCAFA R5F100LDAFA R5F100LEAFA R5F100LFAFA R5F100LGAFA R5F100LHAFA R5F100LJAFA R5F100LKAFA R5F100LLAFA R5F101LCAFA R5F101LDAFA R5F101LEAFA R5F101LFAFA R5F101LGAFA R5F101LHAFA R5F101LJAFA R5F101LKAFA R5F101LLAFA R5F100LCDFA R5F100LDDFA R5F100LEDFA R5F100LFDFA R5F100LGDFA R5F100LHDFA R5F100LJDFA R5F100LKDFA R5F100LLDFA R5F101LCDFA R5F101LDDFA R5F101LEDFA R5F101LFDFA R5F101LGDFA R5F101LHDFA R5F101LJDFA R5F101LKDFA R5F101LLDFA R5F100LCGFA R5F100LDGFA R5F100LEGFA R5F100LFGFA R5F100LGGFA R5F100LHGFA MASS TYP g
173. TI04 TO04 P42 TI04 TO04 P13 lt PORT 4 lt 8 gt P40 to P47 TIO5 TOO05 P46 TIO5 TOO5 P12 06 06 102 lt gt PORT5 K 8_2 501 P57 TIOG TOO6 P11 107 7007 145 TI07 TO07 P10 Porte KCB Peo to P67 RxD2 P14 RxD2 P76 lt PORT 7 8 P70 to P77 SERIAL ARRAY UNITO 4ch ANIO P20 to 7 27 RxDO P1 1 RxDO P16 ANI8 P150 to ANI 4 P156 PORT 8 lt 87 P80 to P87 12 00 17 RxD1 P03 RxD1 P81 TxD1 P02 TxD1 P82 SCK00 P10 SCK00 P55 100 11 100 16 000 12 000 17 01 43 101 44 001 45 SCK10 P04 SCK10 P80 5110 03 5110 81 010 02 010 82 SCK11 P30 SH 1 P50 SO11 P51 SCLO00 P10 SDAOO P11 SCLO1 P43 50 01 44 SCL10 P04 SCL10 P80 SDA10 P03 SDA10 P81 SCL11 P30 SDA11 P50 RxD2 P14 RxD2 P76 TxD2 P13 TxD2 P77 RxD3 P143 TxD3 P144 SCK20 P15 SI20 P14 SO20 P13 SCK21 P70 5121 71 5021 72 SCK30 P142 SI30 P143 5030 144 SCK31 P54 SI31 P53 SO31 P52 SCL20 P15 SDA20 P14 SCL21 P70 SDA21 P71 SCL30 P142 SDA30 P143 SCL31 P54 SDA31 P53 SERIAL ARRAY UNIT1 4ch MH gt A D CONVERTER ANI16 P03 ANI17 PO2 ANI18 P147 ANH 9 P120 ANI20 P100 AVnere P20 AVneru P21 Voo Vss EVopo EVsso EVoo EVss1 SERIAL INTERFACE IICAO SERIAL INTERFACE IICA1 BUZZER OUTPUT L2 CLOCK OUTPUT CONTROL MULTIPLIER amp DIVIDER MUL
174. TIOO EVppo P121 X1 P137 INTP0 P124 XT2 EXCLKS P50 INTP1 SI11 SDA11 P55 PCLBUZ1 SCKO00 P10 SCK00 SCLOO TI07 TO07 P147 ANI18 P72 KR2 SO21 P06 TI06 TO06 P11 SI00 RxD0 TOOLRxD SDA00 TI06 TO06 P27 ANI7 P73 KR3 SO01 P17 TI02 TO02 SO00 TxD0 P12 SO00 TxD0 TOOLTxD INTP5 105 005 P26 ANI6 P76 KR6 INTP10 RxD2 P54 P21 ANI1 AVrerm P23 ANI3 P31 TIO3 TOO3 INTP4 PCLBUZO P42 T104 TO04 P04 SCK10 SCL10 P20 ANIO AVnere P40 TOOLO P43 P141 PCLBUZ1 INTP7 REGC P01 TOOO P140 PCLBUZO INTP6 Cautions 1 Make EVsso pin the same potential as Vss pin P122 X2 EXCLK P123 XT1 2 Make Voo pin the potential that is higher than EVppo pin 3 Connect the REGC pin to Vss via a capacitor 0 47 1 Remarks 1 For pin identification see 1 4 Pin Identification P120 ANI19 2 When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced it is recommended to supply separate powers to the and EVppo pins and connect the Vss and EVsso pins to separate ground lines 3 Functions in parentheses in the above figure can be assigned via settings in the peripheral redirection register PIOR Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10
175. TOO3 P14 C PORT 3 lt 2 gt P30 P31 TI04 TO04 P42 TI04 TO04 P13 lt PORT 4 5 P40 to P45 105 005 05 05 05 12 TI06 TO06 P06 C PORT 5 8 D P50 to P55 TIOG TOO6 P11 107 7007 41 107 7007 10 lt PORT 6 P60 to P67 RxD2 P14 RxD2 P76 lt PORT7 8 gt P70 to P77 SERIAL ARRAY UNITO 4ch 8 ANIO P20 to ANI7 P27 RxD0 P11 RxD0 P16 7 ANI8 P150 to 11 153 TxD0 P12 TxD0 P17 s ANI16 P03 ANI17 P02 noni ANIT8 P147 19 120 x ANI20 P100 A D CONVERTER TxD1 P02 ey SCKO0 P10 SCKO00 P55 PORT P100 SI00 P11 SI00 P16 SO00 P12 SO00 P17 Md ies SCKO01 P43 REM lt PORT 11 _2_ gt 110 P111 SI01 P44 SO01 P45 P120 SCK10 P04 TORIS P12110 P124 S110 P03 CODE FLASH MEMORY cone rs enor lt PORT 13 dec SCK11 P30 lt DATA FLASH MEMORY SI11 P50 P140 to P144 lt PORT14 SCL00 P10 PORT 15 K 4 gt P150 to P153 SDAOO P11 SCLO1 P43 SDAO1 P44 KRO P70 to KEY RETURN 8 SCL10 P04 RAM lt KR7 P77 SDA10 P03 SCL11 P30 POWER ON RESET POR LVD SDA11 P50 VOLTAGE DETECTOR CONTROL SERIAL ARRAY Vss TOOLRxD P11 UNIT1 4ch EVopo EVsso TOOLTxD P12 SERIAL SDAAO P61 SDAAO P13 Xx INTERFACE IICA0 SCLAO P60 SCLAO P14 TxD2 P13 TxD2 P77 ON CHIP DEBUG TOOLO P40 SDAA1 P63 RxD3 P143 SERIAL TxD3 P144 INTERFACE IICA1 SCLA1 P62 SCK20 P15 NIE BUZZER OUTPUT PCLBUZO P140 CONTR
176. TP1 to INTP11 1 6 V lt EVopoo lt 5 5 V 1 us Key interrupt input low level KRO to KR7 1 8 V lt EVppo lt 5 5 V 250 ns width 1 6 lt lt 1 8 1 us RESET low level width tRSL 10 us Note and Remark are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 77 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D 40 to 85 Note The following conditions are required for low voltage interface when Evppo lt 1 8 V lt EVppo lt 2 7 V MIN 125 ns 1 6 V lt EVppo lt 1 8 V MIN 250 ns Remark fwck Timer array unit operation clock frequency Operation clock to be set by the CKSmn0 CKSmn1 bits of timer mode register mn TMRmn m Unit number m 0 1 n Channel number n 0 to 7 Minimum Instruction Execution Time during Main System Clock Operation Tcv vs HS high speed main mode 10 10 When the high speed on chip oscillator clock is selected During self programming p When high speed system clock is selected 0 1 0 0625 0 05 0 03125 0 01 Supply voltage Vo V R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 78 of 194 Nov 15 2013
177. V lt AVrerp lt lt 5 5 V Vss EVsso EVssi 0 V Reference voltage AVrerp Reference voltage AVrerm 0 V Parameter Resolution Conditions Overall error 10 bit resolution EVppo AVnere Notes 4 1 8 V lt AVrere 5 5 V 1 6 V lt 5 5 V Note 5 Conversion time 10 bit resolution Target ANI pin ANI16 to ANI26 3 6 V lt VDD lt 5 5 V 2 7 V lt VDD lt 5 5 V 1 8 V lt Vpp lt 5 5 V 1 6 V lt VoD lt 5 5 V Zero scale error etes 2 10 bit resolution EVppo AVnere Ns 3 4 1 8 V lt AVrere lt 5 5 V 1 6 V lt 5 5 V Note 5 Full scale error Notes 1 2 10 bit resolution AVnere etes 3 4 1 8 V lt 5 5 V 1 6 V lt 5 5 V Note 5 Integral linearity error 1 Note 10 bit resolution EVppo AVnere Notes 4 1 8 V lt AVrere 5 5 V 1 6 V lt 5 5 V Note 5 Differential linearity error ete 1 10 bit resolution EVppo AVrerp Notes 4 1 8 V lt AVrere lt 5 5 V 1 6 V lt lt 5 5 V Note 5 Analog input voltage ANI16 to ANI26 Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 When AVrere lt the MAX values a
178. VO0 R5F100ACASP VO0 R5F100ADASP VO 7 62 mm 300 0 65 R5F100AEASP V0 R5F100AFASP VO R5F100AGASP V0O R5F100AAASP X0 R5F100ACASP X0 R5F100ADASP X0 R5F100AEASP X0 R5F100AFASP X0 R5F100AGASP X0 D R5F100AADSP VO0 R5F100ACDSP V0 R5F100ADDSP VO R5F100AEDSP V0 R5F100AFDSP V0 R5F100AGDSP V0 R5F100AADSP X0 R5F100ACDSP X0 R5F100ADDSP XO R5F100AEDSP X0 R5F100AFDSP X0 R5F100AGDSP X0 G R5F100AAGSP V0 R5F100ACGSP VO R5F100ADGSP V0 R5F100AEGSP VO R5F100AFGSP VO R5F100AGGSP V0 R5F100AAGSP XO R5F100ACGSP X0 R5F100ADGSP X0 R5F100AEGSP XO R5F100AFGSP X0 R5F100AGGSP X0 Not A R5F101AAASP V0 R5F101ACASP V0 R5F101ADASP VO R5F101AEASP VO R5F101AFASP VO0 R5F101AGASP V0 R5F101AAASP X0 R5F101ACASP X0 R5F101ADASP XO R5F101AEASP X0 R5F101AFASP X0 R5F101AGASP X0 D R5F101AADSP VO0 R5F101ACDSP VO0 R5F101ADDSP VO R5F101AEDSP V0 R5F101AFDSP V0 R5F101AGDSP V0 R5F101AADSP X0 R5F101ACDSP X0 R5F101ADDSP XO R5F101AEDSP X0 R5F101AFDSP X0 R5F101AGDSP X0 32 pins 32 pin plastic Mounted A R5F100BAANA U0 R5F100BCANA U0 R5F100BDANA UO HWQFN 5 x 5 mm R5F100BEANA U0 R5F100BFANA U0 R5F100BGANA U0 R5F100BAANA W0 R5F100BCANA W0 R5F100BDANAZWO R5F100BEANA W0 R5F100BFANA WO R5F100BGANA W0 D R5F100BADNA U0 R5F100BCDNA U0 R5F100BDDNA U0 R5F100BEDNA U0 R5F100BFDNA U0 R5F100BGDNA U0 R5F100BADNA W0 R5F100BCDNA ZWO R5F100BDDNA ZWO R5F100BEDNAZWO R5F100BFDNAZWO R5F100BGDNAZWO G R5F100BAGNA U0 R5F100BCGNAZUO R5F100
179. XDO P137 INTPO O 38 O P57 INTP3 P122 X2 EXCLK O O P56 INTP1 P55 PCLBUZ1 SCK00 P120 ANI19 O REGC O O P54 SCK31 SCL31 Vss O 34 O P53 SI31 SDA31 EVsso O O P52 S031 Voo 32 O P51 SO11 EVono 31 O P50 SI11 SDA11 OOOOOOOOOOOOOOOOOOOOOOOOOOOOO00 OQo Go WNoqaqooor oo0nbnicococeogortoor s o 4S moa EEEEQ gt Qut 22222 A mua ox Nec 5 q G Or gt TE G a E E E E eae Sees 20202 5 E E 5 RIO 2299 kannn 22 215 SEY z PE xc IE I x x Kx oon ES 5 or o 5 oR 202 ak a x e co e E n a E 2 a Cautions 1 Make EVsso EVss pins the same potential as Vss pin 2 Make Voo pin the potential that is higher than EVppo EVon1 pins EVppo EVpp 3 Connect the REGC pin to Vss via a capacitor 0 47 to 1 Remarks 1 For pin identification see 1 4 Pin Identification 2 When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced it is recommended to supply separate powers to the EVppo and EVpni pins and connect the Vss EVsso and EVsst pins to separate ground lines 3 Functions in parentheses in the above figure c
180. ain mode LV low 1 8 V lt V lt 5 5V 0 25 1 us voltage main mode External system clock 2 7 V lt Voo lt 5 5 V 1 0 20 0 MHz frequency 2 4 V lt Voo lt 2 7 V 1 0 16 0 MHz 1 8 V lt Voo lt 2 4 V 1 0 8 0 MHz 1 6 V lt Voo lt 1 8 V 1 0 4 0 MHz fexs 32 35 kHz External system clock input text 2 7V lt Vo0 lt s5 5V 24 ns high level width low level width DAV lt Vo lt 27V 30 ns 1 8 V lt Voo lt 2 4 V 60 ns 1 6 V lt Voo lt 1 8 V 120 ns texHs tExLs 13 7 Ls TIOO to TIO7 TI10 to TI17 input trix 1 fmck 10 nsNote high level width low level width TOO0 to TOO7 TO10 to TO17 fro HS high speed 4 0 V lt EVppo lt 5 5 V 16 MHz output frequency main mode 2 7 V lt EVooo lt 4 0 V 8 MHz 1 8 V lt EVppo lt 2 7 V 4 MHz 1 6 V lt EVopo lt 1 8 V 2 MHz LS low speed 1 8 V lt lt 5 5 V 4 MHz main mode 1 6 V lt EVppo lt 1 8 V 2 MHz LV low voltage 1 6 V lt lt 5 5 V 2 MHz main mode PCLBUZO PCLBUZ1 output fec HS high speed 4 0 V lt EVbppo 5 5 V 16 MHz frequency main mode 2 7 V lt EVo00 lt 4 0 V 8 MHz 1 8 V lt EVppo lt 2 7 V 4 MHz 1 6 V lt EVppo lt 1 8 V 2 MHz LS low speed 1 8 V lt lt 5 5 V 4 MHz main mode 1 6 V lt EVppo lt 1 8 V 2 MHz LV low voltage 1 8 V lt lt 5 5 V 4 MHz main mode 1 6 V lt EVppo lt 1 8 V 2 MHz Interrupt input high level width tintH INTP0 1 6 V lt Voo lt 5 5 V 1 us low level width tir IN
181. al reference voltage ADREFP1 1 ADREFPO 0 reference voltage ADREFM 1 target pin ANIO 2 to ANI14 ANI16 to ANI26 40 to 85 C 2 4 V lt Voo lt 5 5 V 1 6 V lt EVppo EVpni lt Vss EVsso EVssi 0 V Reference voltage Vear Reference voltage AVrerm 0 V HS high speed main mode Parameter Conditions Resolution RES bit Conversion time tcoNv 8 bit resolution 2 4 V lt Vpp lt 5 5 V 17 39 Ls Zero scale error 1 2 Ezs 8 bit resolution 2 4 V lt lt 5 5 V 0 60 FSR Integral linearity error ILE 8 bit resolution 2 4 V lt Vpp lt 5 5 V 2 0 LSB Differential linearity error 1 DLE 8 bit resolution 2 4 V lt Vpp lt 5 5 V 1 0 LSB Analog input voltage VAIN 0 3 Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 Refer to 2 6 2 Temperature sensor internal reference voltage characteristics 4 When reference voltage Vss the MAX values are as follows Zero scale error Add 0 35 FSR to the MAX value when reference voltage AVREFM Integral linearity error Add 0 5 LSB to the MAX value when reference voltage AVREFN Differential linearity error Add 0 2 LSB to the MAX value when reference voltage AVREFM R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NE SAS Page 1
182. an be assigned via settings in the peripheral redirection register PIOR Refer to Figure 4 8 Format of Peripheral I O Redirection Register PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 31 of 194 Nov 15 2013 RL78 G13 1 3 14 128 pin products e 128 pin plastic LFQFP 14 x 20 mm 0 5 mm pitch P156 ANI14 C P155 ANI13 C P154 ANI12 P153 ANI11 P152 ANI10 151 9 C P150 ANI8 P27 ANI7 O P26 ANI6 O P25 ANI5 O P24 ANI4 O P23 ANI3 P22 ANI2 P21 ANI1 AVrerm P20 ANIO AVnere puni S OE 8 Ex B E SESS _ ESOS sptt o SzturoSc eoazesoxs ENTERE k S e lt x 5509845868 Bx x Sge20 amp zo Qa zg 2888S9z8 a 8 2 04 K9 2288223 95 amp sS coosoOOoOs a HG o Qe ANN 9r elfsqagkraa Goer Pa zz 222 T T X SSQAQXSNEEOXSES EE lt lt lt lt lt Oro OLOxXxXxOLSS2ZZ7020 zz 5 5 o x 020 0 s o D I7 CO XP Pom cm Cx coco om XO LO xt CO QN O s 10 O ZX O IO OA O O Z 9 1 0 D 10 1D 10 D ID D aa gQagaqgaaognoanoananaaaoaoaaanaananaaaaaadnanad O O 00 S OQ O O OSO Q C O O O 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 103 104 105
183. ase reset voltage Falling interrupt voltage LVIS1 LVISO 0 0 Rising release reset voltage Falling interrupt voltage 2 6 5 Power supply voltage rising slope characteristics Ta 40 to 85 C Vss 0 V lt lt lt j lt j lt lt j lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt Pwer ay vores fom ve Caution R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Make sure to keep the internal reset state by the LVD circuit or an external reset until Voo reaches the operating voltage range shown in 2 4 AC Characteristics Page 120 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Ta 40 to 85 C Vss 0 V Parameter Symbol Conditions MIN MAX Unit TYP Note The value depends on the POR detection voltage When the voltage drops the data is retained before a POR reset is effected but data is not retained when a POR reset is effected 1 STOP mode Operation mode I Data retention mode 4 STOP instruction execution Standby release signal interrupt request 2 8 Flash Memory Programming Characteristics Ta 40 to 85 C 1 8 V lt Voo lt 5 5 V Vss 0 V Parameter Conditions CPU peripheral hardwa
184. ation Voo 5 0 V Voo 3 0 V 16 MHz No Normal operation Voo 5 0 V Voo 3 0 V HS high speed main mode Note 5 fux 20 MHz Voo 5 0 V Normal operation Square wave input Resonator connection fux 20 MHz 2 Voo 3 0 V Normal operation Square wave input Resonator connection fux 10 MHz 2 Voo 5 0 V Normal operation Square wave input Resonator connection fux 10 MHz 2 Voo 3 0 V Normal operation Square wave input Resonator connection Subsystem clock operation 32 768 kHz Note 4 Ta 40 Normal operation Square wave input Resonator connection 32 768 kHz Note 4 Ta 25 Normal operation Square wave input Resonator connection 32 768 kHz Note 4 Ta 50 C Normal operation Square wave input Resonator connection 32 768 kHz Note 4 Ta 70 C Normal operation Square wave input Resonator connection fsue 32 768 kHz Note 4 85 Normal operation Square wave input Resonator connection fsue 32 768 kHz Note 4 Ta 105 Notes and Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 ztENESAS Normal operation Square wave input Resonator connection k B5
185. ationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V lt Voo lt 5 5 V9 1 MHz to 32 MHz 2 4 V lt lt 5 5 V9 1 MHz to 16 MHz LS low speed main mode 1 8 V lt lt 5 5 V 1 MHz to 8 MHz LV low voltage main mode 1 6 V lt lt 5 5 V 1 MHz to 4 MHz 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fiH High speed on chip oscillator clock frequency 3 fsu amp Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation temperature condition of the value is TA 25 R01DS0131EJ0310 Rev 3 10 RENESAS Page 64 of 194 Nov 15 2013 RL78 G13 1 Flash ROM 16 to 64 KB of 20 to 64 pin products 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 40 to 85 C 1 6 V lt EVppo lt lt 5 5 V Vss EVsso 0 V 2 2 Parameter Supply current Note 1 Conditions Ipp2 HALT HS high 32 MHz Voo 5 0 V 054 1 68 mA e2 mode Sek Voo 3 0 V 0 54 1 63 mA 24 MHz Voo 5 0 V 0 44 1 28 mA Voo 3 0 V 0 44 1 28 mA fiu 16 MHz tote 4 Voo 5 0 V 040 1 00 mA Voo 3 0 V 0 40 1 00 mA LS low fiu 8 MHz Note 4 Vpp 3 0 V 260 5
186. ce voltage current Temperature sensor operating current Notes 1 D LVD operating lv current T Self lesp Notes t programming operating current BGO operating current SNOOZE ADC operation The mode is performed operating The A D conversion operations are current performed Loe voltage mode AVnerP Voo 3 0 V CSI UART operation Notes 1 Current flowing to the Voo 2 When high speed on chip oscillator and high speed system clock are stopped 3 Current flowing only to the real time clock RTC excluding the operating current of the low speed on chip ocsillator and the XT1 oscillator The supply current of the RL78 microcontrollers is the sum of the values of either Ipp1 or 002 and when the real time clock operates in operation mode or HALT mode When the low speed on chip oscillator is selected IF should be added Ipp2 subsystem clock operation includes the operational current of the real time clock 4 Current flowing only to the 12 bit interval timer excluding the operating current of the low speed on chip ocsillator and the XT1 oscillator The supply current of the RL78 microcontrollers is the sum of the values of either Ipp1 1022 and lir when the 12 bit interval timer operates in operation mode or HALT mode When the low speed on chip oscillator is selected Iri should be added 5 Current flowing only to the watchdog timer including t
187. ck 4 MHz 20 fuck SCKp high low level width 4 0 V lt EVppo lt 5 5 V 2 7 V lt lt 4 0 tkcy2 2 24 2 7 V lt lt 4 0 V 2 3 V lt lt 2 7 V tkcy2 2 36 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V 2 tkcy2 2 100 Slp setup time to SCKpT Note 4 0 V lt EVppo lt 5 5 V 2 V lt lt 4 0 1 fvck 40 2 7 V EVppo lt 4 0 V 2 3 V lt lt 2 7 V 1 fuck 40 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V 1 fuck 60 51 hold time from SCKpT ete 1 62 Delay time from SCKpl Note 4 to SOp output 4 0 V lt EVppo 5 5 V 2 7 V lt Vo 4 0 V Cb pF Ro 1 4 2 fuck 240 2 7 V lt EVppo lt 4 0 V 23V lt Vo lt 2 7 V pF Rb 2 7 2 fuck 428 2 4 V lt lt 3 3 V 1 6 V lt Ve lt 2 0 V Co 30 pF Re 5 5 Notes Caution and Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS 2 fuck 1146 Page 160 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Notes 1 Transfer rate in the SNOOZE mode MAX 1 Mbps 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes to SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKP
188. ctor control systems military equipment etc You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application for which it is not intended Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics 6 You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics
189. d CKPmn 1 or DAPmn 1 and CKPmn 0 4 C is the load capacitance of the SCKp and SOp output lines Caution Select the normal input buffer for the Slp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg Remarks 1 CSI number 00 01 10 11 20 21 30 31 m Unit number m 0 1 n Channel number 0 to 3 g PIM and POM numbers g 0 1 4 5 8 14 2 Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 146 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 3 During communication at same potential CSI mode slave mode SCKp external clock input Ta 40 to 105 2 4 V lt EVppo EVpni lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Note 5 SCKp cycle time Conditions 4 0 V EVppo 5 5 20 MHz lt fuck HS high speed main Mode MIN 16 fuck MAX V fuck 20 MHz 12 fuck 2 7 V lt EVppo 5 5 16 MHz fuck 16 fuck V fuck 16 MHz 12 fuck 24V lt EVpp0 lt 5 5 V 16 fuck 12 fmck and 1000 SCKp high low level width 4 0 V lt EVppo lt 5 5 V 2 7 V lt EVppo lt 5 5 V
190. d watchdog timer 7 Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V lt Voo lt 5 5 V9 1 MHz to 32 MHz 2 4 V lt Voo lt 5 5 V 1 MHz to 16 MHz 8 Regarding the value for current operate the subsystem clock STOP mode refer to that HALT mode Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fiu High speed on chip oscillator clock frequency 3 fsu amp Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation and STOP mode temperature condition of the TYP value is Ta 25 R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 139 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 3 Peripheral Functions Common to all products 40 to 105 C 2 4 V x EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions Low speedon lr chip oscillator operating current RTC operating Inrc current Notes 1 2 3 12 bit interval jj hotes 1 timer operating current 4 Watchdog timer fi 15 kHz operating Notes 1 2 5 current A D converter ADC When conversion Normal mode AVnere Voo 5 0 V operating at maximum current speed Low voltage mode AVnerP Voo 3 0 V A D converter referen
191. de Parameter Conditions MIN MAX LS low speed main Mode MIN MAX LV low voltage main Mode MIN MAX SCKp cycle time tkcvi 1 gt 2 4 0 V lt 5 5 V 62 5 250 500 ns 2 7 V lt EVppo lt 5 5 V 83 3 250 500 ns SCKp high low level 1 4 0 V EVppo lt 5 5 V 1 2 1 2 tkcvi 2 ns width 7 50 50 2 7 V lt lt 5 5 V tkcvi 2 tkcvi 2 tkcvi 2 ns 10 50 50 Slp setup time to SCKp7 tsi 4 0 V lt EVppo lt 5 5 V 23 110 110 ns t 2 7 V EVooo lt 5 5 V 33 110 110 ns 51 hold time from tksi 2 7 V lt lt 5 5 V 10 10 10 ns SCKpT Note 2 Delay time from SCKpl to SOp output Note 3 tkso1 C 20 4 10 10 10 ns Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The 51 setup time becomes to SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The 51 hold time becomes from SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpT when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 4 C is the load capacitance of the SCKp and SOp output lines Caution Select the normal input buffer for the Sip pin and the normal
192. dification of IICA serial transfer timing Addition of table in 3 6 1 A D converter characteristics Modification of table and notes 3 and 4 in 3 6 1 1 Modification of description in 3 6 1 2 Modification of description and note 3 in 3 6 1 3 Modification of description and notes 3 and 4 in 3 6 1 4 Modification of table and note in 3 6 3 POR circuit characteristics Modification of table of LVD Detection Voltage of Interrupt amp Reset Mode Modification from Supply Voltage Rise Time to 3 6 5 Power supply voltage rising slope characteristics Modification of 3 9 Dedicated Flash Memory Programmer Communication UART Modification of table figure and remark in 3 10 Timing Specs for Switching Flash Memory Programming Modes Caution 4 added Note for operating ambient temperature in 3 1 Absolute Maximum Ratings deleted All trademarks and registered trademarks are the property of their respective owners SuperFlash is a registered trademark of Silicon Storage Technology Inc in several countries including the United States and Japan Caution This product uses SuperFlash technology licensed from Silicon Storage Technology Inc C 4 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between VIL MAX and VIH MIN due to noise etc the device may malfuncti
193. e 3 Cb 100 pF Rb 2 7 KQ 3 1 8 V EVppo lt 3 3 V 1 fuck 1 fuck 1 fuck kHz 1 6 lt lt 2 0 2 190 190 190 Note 3 Note 3 Co 100 pF Rb 5 5 Data hold time tHD DAT 4 0 V EVppoo lt 5 5 V 0 305 0 305 0 305 ns transmission 2 7 V lt Vo lt 4 0 V Co 50 pF Re 2 7 2 7 V EVppo lt 4 0 V 0 305 0 305 0 305 ns 2 3 V lt Vo lt 2 7 V 50 pF Rb 2 7 4 0 V lt EVppoo lt 5 5 V 0 355 0 355 0 355 ns 2 7 V lt Vo lt 4 0 V 100 pF Rb 2 8 KQ 2 7 V lt EVppo lt 4 0 V 0 355 0 355 0 355 ns 2 3 V lt Vo lt 2 7 V 100 pF Rb 2 7 KQ 1 8 V lt EVppo lt 3 3 V 0 405 0 405 0 405 ns 1 6 V lt Vo lt 2 0 Ve Co 100 pF Rb 5 5 KQ Notes 1 The value must also be equal to or less than fuck 4 2 Use it with EVppo gt Vb 3 Set the fuck value to keep the hold time of SCLr L and SCLr H Caution Select the TTL input buffer and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SDAr pin and the N ch open drain output tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SCLr pin by using port input mode register g PIMg and port output mode register g POMg For and Vit see the DC characteristics with TTL input buffer selected Remarks are listed on the next page R
194. e next page R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 109 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MAX of is during normal transfer and a wait state is inserted in the ACK acknowledge timing Caution The values in the above table are applied even when bit 2 PIOR2 in the peripheral I O redirection register PIOR is 1 At this time the pin characteristics must satisfy the values in the redirect destination Remark The maximum value of Cb communication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Standard mode Cb 400 pF Rb 2 7 kQ R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 110 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D 40 to 85 2 fast mode Ta 40 to 85 C 1 6 V lt EVppo EVppi lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MAX MAX MAX SCLAO clock frequency fsc Fast mode 27V EVoo 55V 0 400 0 400 0 400 kHz 1023 5 MHZ gv lt EVoo lt 55v o 40 o 40 o 400 kHz Setup time of
195. ect the REGC pin Vss via a capacitor 0 47 to 1 uF This value regulates the absolute maximum rating of the REGC pin Do not use this pin with voltage applied to it 2 Must be 6 5 V or lower 3 Do not exceed AVrer 0 3 V in case of A D conversion target Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Remarks 1 Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins 2 AVnrer side reference voltage of the A D converter 3 Vss Reference voltage R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 124 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Absolute Maximum Ratings Ta 25 C 2 2 Parameter Symbols Conditions Ratings Output current high Per pin POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Total of all pins POO to P04 P07 P32 to P37 170 mA P40 to P47 P102 to P106 P120 P125 to P127 P130 P140 to P145 P05 P06 P10 to P17 P30 P31 P50 to P57 P64 to
196. enamed to 2 6 5 Power supply voltage rising slope characteristics Modification of table figure and remark in 2 10 Timing Specs for Switching Flash Memory Programming Modes Modification of caution 1 and description Modification of table and remark 3 in Absolute Maximum Ratings 25 Modification of table note caution and remark in 3 2 1 X1 XT1 oscillator characteristics Modification of table in 3 2 2 On chip oscillator characteristics Modification of note 3 in 3 3 1 Pin characteristics 1 5 Modification of note 3 in 3 3 1 Pin characteristics 2 5 Modification of notes 1 and 4 in 1 Flash ROM 16 to 64 KB of 20 to 64 pin products 1 2 Modification of notes 1 5 and 6 in 1 Flash ROM 16 to 64 KB of 20 to 64 pin products 2 2 Modification of notes 1 and 4 in 2 Flash ROM 96 to 256 KB of 30 to 100 pin products 1 2 Modification of notes 1 5 and 6 in 2 Flash ROM 96 to 256 KB of 30 to 100 pin products 2 2 Modification of 3 Peripheral Functions Common to all products Modification of table in 3 4 AC Characteristics Addition of Minimum Instruction Execution Time during Main System Clock Operation Modification of figure of AC Timing Test Points Modification of figure of External System Clock Timing Modification of figure of AC Timing Test Points Modification of description note 1 and caution in 1 During communication at same potential UART mode Modification of description in 2 During
197. es not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin 4 The applied current for the products for industrial application R5F100xxDxx R5F101xxDxx is 100 mA Caution P00 P02 to P04 P10 to P15 P17 P43 to P45 P50 P52 to P55 P71 P74 P80 to P82 P96 and P142 to P144 do not output high level in N ch open drain mode Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 58 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Ta 40 to 85 C 1 6 V x EVppo 1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 2 5 Output current low ote 1 Notes 1 Conditions Per pin for POO to PO7 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Per pin for P60 to P63 Total of POO to P04 P07 P32 to P37 P40 to P47 P102 to P106 P120 P125 to P127 P130 P140 to P145 20 0 Note 2 15 0 70 0 15 0 9 0 4 5 80 0 35 0 20 0 10 0 4 0 V lt EVppo lt 5 5 V 2 7 V lt EVomo lt 4 0 V 1 8 V lt lt 2 7 V 1 6 V lt lt 1 8 V 4 0 V lt lt 5 5 V 2 7 V lt EVppoo lt 4 0 V 1 8 V lt EVppo lt 2 7 V 1 6 V lt EVoppo lt 1 8 V
198. ev 3 10 QE NEC S AS Page 30 of 194 Nov 15 2013 RL78 G13 1 OUTLINE 100 plastic LQFP 14 x 20 mm 0 65 mm pitch lt 5 a on e 0 98 2290 Ege Om o RE or a oo NN QES 0 983 DISFE aoe 22 namo Sok lt lt e OOS oo O Sa Ww eed T A S 9m m sS sss 255353355 222222222 QPAPHOHEPOZSZSE ZZZZZZZZ lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt lt Mos Wb Wb xb CO Q C O O GQ LO LO LO LO LO LO O OOOO w AN QJ QJ GM Q w w w eee naacaadnaaaaaaonoanaaooaonnaoaaoaanonancann THE HINA 7 74 7372 71 70 6 7 66 6 3 62 5857 56 55 54 53 52 50 o P146 INTP4 47 49 2 O P111 INTP11 P46 INTP1 TI05 TO05 48 O P110 INTP10 P45 SO01 47 o P101 PA44 SI01 SDAO1 O 46 O P10 SCKO0 SCLOO TIO7 TOO7 P43 SCK01 SCLO1 O 45 O P11 SI00 RxD0 TOOLRxD SDA00 T106 TO06 P42 T104 TO04 44 O P12 S000 TxD0 TOOLTxD INTP5 T105 TO05 P41 O 43 o P13 TxD2 SO20 SDAA0 TI04 TO04 P40 TOOL0 O 42 O P14 RxD2 SI20 SDA20 SCLA0 TI03 TO03 RESET o o 44 o P15 SCK20 SCL20 TI02 TO02 P124 XT2 EXCLKS O 40 O P16 TI01 TO01 INTP5 SI00 RXD0 P123 XT1 O 39 O P17 TIO2 TO02 SO00 T
199. ferent potential R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 161 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcve 2 Output data CSI mode serial transfer timing slave mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 t cve lee t 2 Output data Remarks 1 p CSI number p 00 01 10 20 30 31 m Unit number n Channel number mn 00 01 02 10 12 13 g PIM and POM number g 0 1 4 5 8 14 2 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 162 of 194 Nov 15 2013 RL78 G13 8 Communication at different potential 1 8 V 2 5 V 3 V simplified mode 1 2 Ta 40 to 105 C 2 4 V lt EVppo EVpni lt lt 5 5 V Vss EVsso EVssi 0 V Parameter SCLr clock frequency Conditions 4 0 V EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V Cb 50 pF Rb 2 7 HS high speed main Mode MIN MAX 3 ELECTRICAL SPECIFICATIONS G Ta 40 to 105 C 2 7 V EVppo lt 4 0 V 2 3 V lt Vo
200. frequency Operation clock to be set by the CKSmn0 CKSmn1 bits of timer mode register mn TMRmn m Unit number m 0 1 n Channel number n 0 to 7 R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 142 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Minimum Instruction Execution Time during Main System Clock Operation Tcv vs HS high speed main mode 10 1 0 When the high speed on chip oscillator clock is selected During self programming When high speed system clock is selected Cycle time Tcv ps 0 1 0 0625 0 05 0 03125 0 01 0 10 20 530 40 50960 24 2 7 Supply voltage Voo V AC Timing Test Points V H VoH V H VoH T V u Vou PONS V u VoL External System Clock Timing EXCLK EXCLKS R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 143 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C TI TO Timing tri TIOO to TIO7 T110 to T117 m 1 fto TO00 to TOO7 TO10 to TO17 Interrupt Request Input Timing INTL tiNTH INTPO to INTP11 Key Interrupt Input Timing mi 1 KRO to KR7 RSL RESET RESET Input Timing R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 144 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C
201. he characteristics of alternate function pins are the same as those of the port pins ztENESAS Page 127 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Ta 40 to 105 C 2 4 V x EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V 2 5 Conditions Output current loti Per pin for POO to P07 P10 to P17 mA lowNote 1 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Per pin for P60 to P63 15 08 mA Total of POO to P04 P07 P32to 4 V lt EVopo lt 5 5 V 40 0 mA P37 2 7 V lt EVopo lt 4 0 V 15 0 mA P40 to P47 P102 to P106 P120 P125 to P127 P130 P140 to P145 When duty lt 70 e 3 Total of P05 PO6 P10 to P17 P30 4 0 V lt EVppo lt 5 5 V P31 P50 to P57 P60 to P67 27V lt EVow lt 40V P70 to P77 P80 to P87 P90 to P97 P100 P101 P110 to P117 P146 P147 When duty lt 70 3 2 4 V lt EVppo lt 2 7 V 9 0 mA 2 4 V lt EVppo lt 2 7 V Total of all pins 80 0 When duty lt 70 e e 3 Per pin for P20 to P27 P150 to P156 0 4 ete Total of all pins 2 4 V lt 0 lt 5 5 5 0 When duty lt 70 3 Notes 1 Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVsso EVss1 and Vss pin 2 Do not exceed the tota
202. he conditions described in the Conditions column are met Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer Select the TTL input buffer for the RxDq pin and the N ch open drain output tolerance When 20 to 52 pin products EVpo tolerance When 64 to 100 pin products mode for the TxDq pin by using port input mode register g PIMg and port output mode register g POMg For and Vu see the DC characteristics with TTL input buffer selected UART mode connection diagram during communication at different potential Vb E RL78 microcontroller User device RxDq R01DS0131EJ0310 Rev 3 10 RENESAS Page 153 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C UART mode bit width during communication at different potential reference 1 Transfer rate Low bit width High bit width Baud rate error tolerance es i TxDq 1 Transfer rate High Low bit width Baud rate error tolerance RxDq Remarks 1 Re O Communication line TxDq pull up resistance Communication line TxDq load capacitance Ve V Communication line voltage 2 q UART number q 0 to 3 g PIM and POM number g 0 1 8 14 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn
203. he operating current of the low speed on chip oscillator The supply current of the RL78 is the sum of 002 or Ibos and when the watchdog timer operates R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 140 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 6 Current flowing only to the A D converter The supply current of the RL78 microcontrollers is the sum of Ipp1 or Ipp2 and lanc when the A D converter is in operation 7 Current flowing only to the LVD circuit The supply current of the RL78 microcontrollers is the sum of Ipp Ippe or and ILvb when the LVD circuit is in operation 8 Current flowing only during data flash rewrite 9 Current flowing only during self programming 10 For shift time to the SNOOZE mode see 18 3 3 SNOOZE mode the RL78 G13 Users Manual Hardware Remarks 1 f L Low speed on chip oscillator clock frequency 2 Subsystem clock frequency XT1 clock oscillation frequency 3 CPU peripheral hardware clock frequency 4 Temperature condition of the value is TA 25 R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 141 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 3 4 AC Characteristics 40 to 105 C 2 4 V x EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V Conditions Instruction cycle minimum Main HS high speed 2 7 V lt Voo lt
204. iming Test Points Test points Vi VoL p Vi VoL 2 5 1 Serial array unit 1 During communication at same potential UART mode Ta 40 to 85 C 1 6 V lt EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Symbol Conditions HS high speed LS low speed LV low voltage Unit main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX Transfer rate N 2 4 V lt EVppo lt 5 5 V fuck 6 fuck 6 Theoretical value of the 1 3 0 6 maximum transfer rate Note 3 fuck fouk 1 8 V EVppo 5 5 V fuck 6 fuck 6 Theoretical value of the 1 3 0 6 maximum transfer rate Note 3 fuck 1 7 V lt EVppo 5 5 V fuck 6 6 Note 2 Theoretical value of the 1 3 0 6 maximum transfer rate Note 3 1 6 V EVppo 5 5 V fuck 6 6 Note 2 Theoretical value of the 1 8 0 6 maximum transfer rate Note 3 fuck Notes 1 Transfer rate in the SNOOZE mode is 4800 bps only 2 The following conditions are required for low voltage interface when Evppo lt Vpp 2 4 V lt EVppo lt 2 7 V 2 6 Mbps 1 8 V lt EVppo lt 2 4 V MAX 1 3 Mbps 1 6 V lt EVppo lt 1 8 V MAX 0 6 Mbps 3 The maximum operating frequencies of the CPU peripheral hardware clock fcuk HS high speed main mode 32 MHz 2 7 V lt Vpp
205. ing normal transfer and a wait state is inserted in the ACK acknowledge timing Caution The values in the above table are applied even when bit 2 PIOR2 in the peripheral I O redirection register PIOR is 1 At this time the pin characteristics loti must satisfy the values in the redirect destination Remark The maximum value of Cb communication line capacitance and the value of Rb communication line pull up resistor at that time in each mode are as follows Standard mode Cb 400 pF Rb 2 7 kQ Fast mode Cb 320 pF Rb 1 1 kQ IICA serial transfer timing SCLAn SDAAn Stop Start Restart Stop condition condition condition condition Remark 0 1 R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 166 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 3 6 Analog Characteristics 3 6 1 A D converter characteristics Classification of A D converter characteristics Input channel ANIO to ANI14 Reference AVREFP Reference voltage 4 voltage AVREFM Refer to 3 6 1 1 ANI16 to ANI26 Refer to 3 6 1 2 Internal reference voltage Temperature sensor output voltage Refer to 3 6 1 1 Reference Voltage Reference voltage VDD Reference voltage Vss Refer to 3 6 1 3 Reference voltage VBGR Reference voltage AVREFM Refer to 3 6 1 4 1 When reference voltage
206. is value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 92 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 3 The smaller maximum transfer rate derived by using 6 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 2 7 V lt EVppo lt 4 0 V and 2 3 V Vb lt 2 7 V 1 Maximum transfer rate 2 TEES Cb x Rb x In 1 V x 3 bps 1 2 0 Transfer rate vex Rex In 1 JY i Transfer rate Baud rate error theoretical value x 100 x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides 4 This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer 5 Use it with EVppo gt Vb 6 The smaller maximum transfer rate derived by using 6 or the following expression is the valid maximum transfer rate Expression for calculating the transfer rate when 1 8 V lt EVppo lt 3 3 V and 1 6 V lt Vb lt 2 0 V Maximum transfer rate bps x Rb x In 1 Ve x3
207. ister g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks are listed on the page after the next page R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 98 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 8 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 3 3 Ta 40 to 85 C 1 8 V lt EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX Slp setup time 4 0 V EVppo 5 5 V to SCKpJ ete 1 2 7V lt Vo lt 4 0V Co 30 pF Re 1 4 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V C 30 pF Rb 2 7 1 8 V lt EVppo lt 3 3 V 1 6 lt Vo lt 2 0 2 Cp 30 pF Re 5 5 Slp hold time 4 0 V EVppo 5 5 V from SCKpJ 2 7 Vo 4 0 V Co 30 pF Re 1 4 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V Co 30 pF Ro 2 7 1 8 V lt EVppo lt 3 3 V 1 6 V lt Vo lt 2 0 V 2 Co 30 pF Ro 5 5 Delay time from SCKpT 4 0 V lt EVppo lt 5 5 V to 2 7 V Vo 4 0 V Note 1 SOp output Co 30 pF Rb 1 4 KQ 2 7 V EVppo lt 4 0 V 2 3 V lt Vo lt 2 7 V C 30 pF Ro 2 7 1 8 V lt EVppo lt 3 3 V 1 6 V
208. ition of the value is TA 25 R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 137 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 2 Flash ROM 96 to 256 KB of 30 to 100 pin products 40 to 105 C 2 4 V x EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V 2 2 Parameter Supply current Note 1 HS high speed main mode Note 7 Conditions 32 MHz Vpp 5 0 V Voo 3 0 V 24 MHz tote 4 Vpp 5 0 V Voo 3 0 V 16 MHz Note 4 Vpp 5 0 V Voo 3 0 V HS high speed main mode Note 7 fux 20 MHz e 3 Voo 5 0 V Square wave input Resonator connection fux 20 MHz 3 Voo 3 0 V Square wave input Resonator connection fux 10 MHz 3 Voo 5 0 V Square wave input Resonator connection fux 10 MHz 3 Voo 3 0 V Square wave input Resonator connection Subsystem clock operation fsue 32 768 kHz te 5 Ta 40 C fsue 32 768 kHz te 5 Ta 25 C Square wave input Resonator connection Square wave input Resonator connection fsue 32 768 kHz te 5 Ta 50 Square wave input Resonator connection fsus 32 768 kHz 5 Ta 70 C Square wave input Resonator connection fsus 32 768 kHz 5 Ta 85 Square wave input Resonator connection
209. l current value 3 Specification under conditions where the duty factor lt 70 The output current value that has changed to the duty factor gt 70 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n e Total output current of pins lo x 0 7 n x 0 01 Example Where 80 and lot 10 0 mA Total output current of pins 10 0 x 0 7 80 x 0 01 8 7 mA However the current that is allowed to flow into one pin does not vary depending on the duty factor A current higher than the absolute maximum rating must not flow into one pin Remark Unless specified otherwise the characteristics of alternate function pins are the same as those of the port pins R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 128 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Ta 40 to 105 C 2 4 V x EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V 3 5 Input voltage high Conditions to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Normal input buffer 0 8EVppo P01 P03 P04 P10 P11 P13 to P17 P43 P44 P53 to P55 P80 P81 P142 P143 TTL input buffer 4 0 V lt EVppo lt 5 5 V TTL input buffer 3 3 V EVppo lt 4 0 V 2 0 TTL input buffer 2 4 V lt EVppo lt 3 3 V
210. latest ordering part numbers refer to the target product page of the Renesas Electronics website R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 8 of 194 Nov 15 2013 RL78 G13 1 OUTLINE Pin count Package 48 pin plastic HWQFN 7 x 7 mm 0 5 mm pitch Table 1 1 List of Ordering Part Numbers Data flash Mounted Fields of Application Note 6 12 Ordering Part Number R5F100GAANA U0 R5F100GCANA U0 R5F100GDANA UO R5F100GEANA U0 R5F100GFANA U0 R5F100GGANA UO R5F100GHANA UO R5F100GJANA U0 R5F100GKANA UO R5F100GLANA U0 R5F100GAANA WO R5F100GCANA WO R5F100GDANA WO R5F100GEANA WO R5F100GFANA WO R5F100GGANA WO R5F100GHANA WO R5F100GJANA WO R5F100GKANA WO R5F100GLANA WO0 R5F100GADNA U0 R5F100GCDNAZUO R5F100GDDNA UO R5F100GEDNA U0 R5F100GFDNA U0 R5F100GGDNA U0O R5F100GHDNAZUO R5F100GJDNA U0 R5F100GKDNA UO R5F100GLDNA U0 R5F100GADNA WO R5F100GCDNA WO R5F100GDDNA ZWO R5F100GEDNA WO R5F100GFDNA WO R5F100GGDNA WO R5F100GHDNA WO R5F100GJDNA WO R5F100GKDNA WO R5F100GLDNA WO R5F100GAGNA U0 R5F100GCGNA UO R5F100GDGNA UO R5F100GEGNA U0 R5F100GFGNA UO R5F100GGGNA UO R5F100GHGNA UO R5F100GJGNA U0 R5F100GAGNA WO R5F100GCGNA WO R5F100GDGNA WO R5F100GEGNA WO R5F100GFGNA WO R5F100GGGNA WO R5F100GHGNA WO R5F100GJGNAZWO Not mounted R5F101GAANA U0 R5F101GCANA U0 R5F101GDANA U0 R5F101GEANA U0 R5F101GFANA U0 R5F101GGANA UO R5F101GHANA U0 R5F101GJANA
211. load capacitance of the SCKp and SOp output lines Caution Select the normal input buffer for the Slp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 84 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Remarks 1 p CSI number p 00 01 10 11 20 21 30 31 m Unit number m 0 1 n Channel number n 0 to 3 g PIM and POM numbers g 0 1 4 5 8 14 2 Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 4 During communication at same potential CSI mode slave mode SCKp external clock input 1 2 Ta 40 to 85 C 1 6 V lt EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MAX MAX SCKp cycle time 4 0 V lt EVppo lt 5 5 20 MHz lt fuck 8 fucx Note 5 V fuck lt 20 MHz 6 fuck 6 fuck 6 fuck 2 7 V lt EVoo 5 5 16 MHz lt fuck 8 fuck V fuck 16 MHz 6 fuck 6 fuck 6 fuck 2 4 V lt EVppo 5 5 V 6 fuck 6 fuck 6 fuck and 500 and and 500 500 1 8 V lt EVppo 5 5 V 6 fuck 6 fmcK and 750 and and 750 750 1
212. mn 1 The Slp hold time becomes from SCKpJ when DAPmn 0 and 1 or DAPmn 1 and CKPmn 0 4 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpT when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Caution Select the TTL input buffer for the Sip and SCKp pin and the N ch open drain output tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SOp pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected CSI mode connection diagram during communication at different potential lt Slave gt Vb SCKp RL78 microcontroller 51 SO User device SOp SI Remarks 1 Re O Communication line SOp pull up resistance Ce F Communication line SOp load capacitance Ve V Communication line voltage 2 p CSI number p 00 01 10 20 30 31 m Unit number n Channel number mn 00 01 02 10 12 13 0 PIM and POM number g 0 1 4 5 8 14 3 Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 01 02 10 12 13 4 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at dif
213. n the RL78 G13 User s Manual Hardware 3 This is about 31 KB when the self programming function and data flash function are used For details see CHAPTER 3 the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 2 of 194 Nov 15 2013 RL78 G13 1 OUTLINE 1 2 List of Part Numbers Figure 1 1 Part Number Memory Size and Package of RL78 G13 PartNo RB5F100LEAxxxFB 0 g Packaging specification U0 Tray HWQFN VFBGA WFLGA V0 Tray LFQFP LQFP LSSOP W0 Embossed Tape HWQFN VFBGA WFLGA X0 Embossed LFQFP LQFP LSSOP Package type SP LSSOP 0 65 mm pitch FP LFQFP 0 80 mm pitch FA LFQFP 0 65 mm pitch FB LFQFP 0 50 mm pitch NA HWQFN 0 50 mm pitch LA WFLGA 0 50 mm pitch 1 BG VFBGA 0 40 mm pitch Note 1 ROM number Omitted with blank products Fields of application A Consumer applications operating ambient temperature 40 C to 85 C D Industrial applications operating ambient temperature 40 C to 85 C G Industrial applications operating ambient temperature 40 C to 105 C ROM capacity 16KB 32 48 64 96 KB 128 KB 192 KB 256 KB 384 KBNote 512 KB 2 Pin count 20 pin 24 pin 25 pinNote 1 30 pin 32 pin 36 pinNote 1 40 pin 44 pin 48 pin 52 pin 64 pin 80 pin 100 pin 128 pinNete 2 RL78 G13 group 100 Data flash is provided 10
214. n the SNOOZE mode MAX 1 Mbps 2 Use it with EVppo gt Vb 3 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slp setup time becomes SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 4 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The Slip hold time becomes from SCKpJ when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 5 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKpT when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 Caution Select the TTL input buffer for the Sip pin and the N ch open drain output tolerance When 20 to 52 pin products EVpp tolerance When 64 to 128 pin products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For Vin and Vit see the DC characteristics with TTL input buffer selected Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 103 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C CSI mode connection diagram during communication at different potential Slave Vb E SCKp SCK RL78 microcontroller 51 SO User device SOp 51 Remarks 1 Re O Communication line 50 pull up resistance Ce F Communication line 50 load capacitance Communication line voltage 2 p CSI number p
215. nator 0 28 0 71 mA connection fux 10 MHz 3 Square wave input 0 21 0 63 mA Vpp 3 0 V Resonator 0 28 0 71 mA connection LS low fux 8 MHz P Square wave input 110 360 uA speed main Von 3 0 V Resonator 160 420 mode connection fux 8 MHz ee Square wave input 110 360 uA Voo 2 0 V Resonator 160 420 HA connection Subsystem fsus 32 768 kKHz Square wave input 028 0 61 clock Ta 40 C Resonator 047 080 yA operation connection fsus 32 768 kHz 5 Square wave input 0 34 0 61 uA 25 Resonator 0 53 0 80 LA connection fsus 32 768 Square wave input 0 41 2 30 uA Ta 50 C Resonator 0 60 2 49 LA connection fsus 32 768 Square wave input 0 64 4 03 uA 70 C Resonator 0 83 4 22 connection fsus 32 768 kHz 5 Square wave input 109 8 04 LA Ta 85 Resonator 1 28 8 23 LA connection mode Ta 40 C 25 0 25 0 52 50 70 85 Notes and Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 69 of 194 RL78 G13 Notes 1 m gt ON Remarks 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Total current flowing into Vpp EVppo and 1 including the input leakage current flowing when the level of the input pin is fixed Vop EVpp
216. nd CSI21 cannot communicate at different potential Use other CSI for communication at different potential R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 100 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tki SOp Output data CSI mode serial transfer timing master mode during communication at different potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 koy SOp Output data Remarks 1 p CSI number p 00 01 10 20 30 31 m Unit number n Channel number mn 00 01 02 10 12 13 0 PIM and POM number g 0 1 4 5 8 14 2 CSIO1 of 48 52 64 pin products and CSI11 and CSI21 cannot communicate at different potential Use other CSI for communication at different potential R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 101 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 9 Communication at different potential 1 8 V 2 5 V 3 V CSI mode slave mode SCKp external clock input Ta 40 to 85 C 1 8 V lt EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V 1 2 Parameter Conditions HS high 15 low speed LV low voltage speed
217. nd subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When RTCLPC 1 and setting ultra low current consumption AMPHS1 1 The current flowing into the RTC is included However not including the current flowing into the 12 bit interval timer and watchdog timer 6 Not including the current flowing into the RTC 12 bit interval timer and watchdog timer m gt ON 7 Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V lt lt 5 5 V 1 MHz to 32 MHz 2 4 V lt 5 5 V9 1 MHz to 16 MHz LS low speed main mode 1 8 V lt lt 5 5 V 1 MHz to 8 MHz LV low voltage main mode 1 6 V lt Voo lt 5 5 V 1 MHz to 4 MHz 8 Regarding the value for current to operate the subsystem clock in STOP mode refer to that in HALT mode Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fiu High speed on chip oscillator clock frequency 3 fsuge Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation and STOP mode temperature condition of the TYP value is TA 25 R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 74 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 4 Peri
218. ng expression is the valid maximum transfer rate Expression for calculating the transfer rate when 2 7 V lt EVppo lt 4 0 V and 2 4 V lt Vb lt 2 7 V Maximum transfer rate L 2 0 bps Cb x Rb x In 1 Vb x3 1 2 0 Transfer rate x2 OP x Rex In 1 3 1 Transfer rate Baud rate error theoretical value x 100 96 x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides This value as an example is calculated when the conditions described in the Conditions column are met Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer R01DS0131EJ0310 Rev 3 10 RENESAS Page 152 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 5 The smaller maximum transfer rate derived by using 12 or the following expression is the valid Caution maximum transfer rate Expression for calculating the transfer rate when 2 4 V lt EVppo lt 3 3 V and 1 6 V lt Vb lt 2 0 V 1 Maximum transfer rate 15 bps Cb x Rb x In 1 Vb x 3 1 1 5 Transfer rate x2 Cb x Ro x In 1 Vo Baud rate error theoretical value 100 Transfer rate x Number of transferred bits This value is the theoretical value of the relative difference between the transmission and reception sides This value as an example is calculated when t
219. nterface 20 pin 24 pin 25 pin products e CSI 1 channel simplified IPC 1 channel UART 1 channel e CSI 1 channel simplified 1 channel UART 1 channel 30 pin 32 pin products e CSI 1 channel simplified 1 channel UART 1 channel e CSI 1 channel simplified IPC 1 channel UART 1 channel e CSI 1 channel simplified 1 channel UART UART supporting LIN bus 1 channel 36 pin products e CSI 1 channel simplified 1 channel UART 1 channel e CSI 1 channel simplified IPC 1 channel UART 1 channel e CSI 2 channels simplified IFC 2 channels UART UART supporting LIN bus 1 channel bus _ 1 channel 1 channel 1 channel 1 channel 1 channel Multiplier and divider multiply accumulator e 16 bits x 16 bits 32 bits Unsigned or signed e 32 bits 32 bits 32 bits Unsigned e 16 bits x 16 bits 32 bits 32 bits Unsigned or signed DMA controller 2 channels Vectored interrupt Internal 23 sources External 3 Key interrupt Reset Reset by RESET pin Internal reset by watchdog timer Internal reset by power on reset Internal reset by voltage detector Internal reset by illegal instruction execution Internal reset by RAM parity error Internal reset by illegal memory access Note Power on reset circuit Power on reset 1 51 V TYP Power down reset 1 50 V TYP Voltage detector 1 67 V to 4 06 V 14
220. nternal reset by illegal instruction execution Internal reset by RAM parity error Internal reset by illegal memory access Power on reset 1 51 V TYP Power down reset 1 50 V TYP 1 67 V to 4 06 V 14 stages 1 63 V to 3 98 V 14 stages Reset Note Power on reset circuit Voltage detector e Rising edge e Falling edge Provided Voo 1 6 to 5 5 V On chip debug function Power supply voltage TA 40 to 85 C A Consumer applications D Industrial applications TA 40 to 105 C G Industrial applications Operating ambient temperature Note The illegal instruction is generated when instruction code FFH is executed Reset by the illegal instruction execution not issued by emulation with the in circuit emulator or on chip debug emulator R01DS0131EJ0310 Rev 3 10 Page 51 of 194 Nov 15 2013 21 NESAS RL78 G13 80 pin 100 pin 128 pin products 1 OUTLINE Caution This outline describes the functions at the time when Peripheral I O redirection register PIOR is set to 00H Code flash memory KB 80 pin 100 pin 1 2 128 pin R5F100Mx R5F101Mx 96 to 512 R5F100Px R5F101Px 96 to 512 R5F100Sx R5F101Sx 192 to 512 Data flash memory KB RAM KB 8 to 32 ete 8 to 32 Note 1 16 to 32 ote Address space 1 MB Main system clock High speed system clock High speed on chip oscillator X1 crystal ce
221. o 3 0 V 30 47 mA LS low fiu 8 MHz Normal Voo 3 0 V 1 3 2 1 mA speed main operation Voo 2 0 V 13 21 mA mode LV low 4 MHz Normal Voo 3 0 V 1 3 1 8 mA voltage operation Von 2 0 V 1 3 1 8 mA main mode Note 5 HS high fmx 20 2 Normal Square wave input 3 4 5 5 mA 5 0 V operation Resonator connection 3 6 5 7 mA mode fux 20 2 2 Normal Square wave input 3 4 5 5 mA Voo 3 0 V operation Resonator connection 3 6 5 7 mA fux 10 2 Normal Square wave input 2 1 3 2 mA 5 0 V operation Resonator connection 2 1 3 2 mA fux 10 Normal Square wave input 2 1 3 2 mA Voo 3 0 V operation Resonator connection 2 1 3 2 mA LS low fmx 8 MHz Normal Square wave input 1 2 2 0 mA ee Vo 3 0 V operation Resonator connection 1 2 2 0 mode fux 8 MHz Normal Square wave input 1 2 2 0 mA Voo 2 0 V operation Resonator connection 1 2 2 0 mA Subsystem fsue 32 768 kHz Normal Square wave input clock SE operation Resonator connection operation Ta 40 C fsus 32 768 kHz Normal Square wave input Note 4 operation Resonator connection Ta 25 C 32 768 kHz Normal Square wave input Note 4 operation Resonator connection Ta 50 C 32 768 kHz Normal Square wave input Note 4 operation Resonator connection Ta 70 C 32 768 kHz Normal Square wave inpu
222. o 85 C 1 6 V lt lt 5 5 V Vss 0 V Oscillators High speed on chip oscillator Notes 1 2 clock frequency Parameters Conditions High speed on chip oscillator clock frequency accuracy 20 to 85 1 8 V lt Voos 5 5 V 1 6 V lt Vop 1 8 V 40 to 20 G 1 8 V lt Voos 5 5 V 1 6 V lt Vop 1 8 V Low speed on chip oscillator clock frequency Low speed on chip oscillator clock frequency accuracy Notes 1 High speed on chip oscillator frequency is selected by bits 0 to 3 of option byte 000C2H 010C2H and bits 0 to 2 of HOCODIV register 2 This indicates the oscillator characteristics only Refer to AC Characteristics for instruction execution time R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 57 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 3 DC Characteristics 2 3 1 Pin characteristics TA 40 to 85 C 1 6 V lt EVppo 1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 1 5 Conditions Output current Per pin for POO to PO7 P10 to P17 1 6 V lt EVppo 5 5 V 10 0 mA highNt 1 P30 to P37 P40 to P47 P50 to P57 P64 od to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Total of POO to P04 P07 P32 to P37 4 0 V lt EVppo lt 5 5 V 55 0 mA P40 to P47 P102 to P106 P120 27 V
223. o and EVpp1 or Vss EVsso and EVssi The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit port and on chip pull up pull down resistors and the current flowing during data flash rewrite During HALT instruction execution by flash memory When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When RTCLPC 1 and setting ultra low current consumption AMPHS1 1 The current flowing into the RTC is included However not including the current flowing into the 12 bit interval timer and watchdog timer Not including the current flowing into the RTC 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed mode 2 7 V lt Voo lt 5 5 V 1 MHz to 32 MHz 2 4 V lt 5 5 V 1 MHz to 16 MHz LS low speed main mode 1 8 V lt Voo lt 5 5 V 1 MHz to 8 MHz LV low voltage main mode 1 6 V lt lt 5 5 V 1 MHz to 4 MHz Regarding the value for current to operate the subsystem clock in STOP mode refer to that in HALT mode 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fiu High speed on chip oscillato
224. o and EVssi The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit port and on chip pull up pull down resistors and the current flowing during data flash rewrite When high speed on chip oscillator and subsystem clock are stopped When high speed system clock and subsystem clock are stopped When high speed on chip oscillator and high speed system clock are stopped When AMPHS 1 1 Ultra low power consumption oscillation However not including the current flowing into the RTC 12 bit interval timer and watchdog timer Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V lt Voo lt 5 5 V9 1 MHz to 32 MHz 2 4 V lt lt 5 5 V 1 MHz to 16 MHz LS low speed main mode 1 8 V lt Von lt 5 5 V 1 MHz to 8 MHz LV low voltage main mode 1 6 V lt Voo lt 5 5 V 1 MHz to 4 MHz Remarks 1 fmx High speed system clock frequency X1 clock oscillation frequency or external main system R01DS0131EJ0310 Rev 3 10 RENESAS Page 72 of 194 clock frequency 2 fiH High speed on chip oscillator clock frequency 3 fsus Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation temperature condition of the value is TA 25 Nov 15 2013 RL78 G13 3 128 pin products and flash ROM 384 to 512 KB of 4
225. oducts 65 Modification of table in 1 Flash ROM 16 to 64 KB of 20 to 64 pin products 66 Modification of notes 1 5 and 6 in 1 Flash ROM 16 to 64 KB of 20 to 64 pin products 68 Modification of notes 1 and 4 in 2 Flash ROM 96 to 256 KB of 30 to 100 pin products 70 Modification of notes 1 5 and 6 in 2 Flash ROM 96 to 256 KB of 30 to 100 pin products 72 Modification of notes 1 and 4 in 8 Flash ROM 384 to 512 KB of 44 to 100 pin products 74 Modification of notes 1 5 and 6 in 3 Flash ROM 384 to 512 KB of 44 to 100 pin products 75 Modification of 4 Peripheral Functions Common to all products 77 Modification of table in 2 4 AC Characteristics 78 79 Addition of Minimum Instruction Execution Time during Main System Clock Operation 80 Modification of figures of AC Timing Test Points and External System Clock Timing 3 00 Date Aug 02 2013 Description Page 81 81 83 84 85 86 88 89 91 92 93 94 95 96 97 98 99 100 102 103 106 107 109 111 112 112 113 113 114 115 116 117 Summary Modification of figure of AC Timing Test Points Modification of description and note 3 in 1 During communication at same potential UART mode Modification of description in 2 During communication at same potential CSI mode Modification of description in 3 During communication at same potential CSI mode Modification of description in 4
226. on Take care to prevent chattering noise from entering the device when the input level is fixed and also in the transition period when the input level passes through the area between VIL MAX and VIH MIN 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device 3 PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequate When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tool
227. on chip oscillator clock frequency accuracy Low speed on chip oscillator clock frequency 20 to 85 40 to 20 C 2 4 V lt Vpp lt 5 5 V 2 4 V lt Voo lt 5 5 V 85 to 105 C 2 4 V lt lt 5 5 V Low speed on chip oscillator clock frequency accuracy Notes 1 High speed on chip oscillator frequency is selected by bits 0 to 3 of option byte 000C2H 010C2H and bits 0 to 2 of HOCODIV register 2 This indicates the oscillator characteristics only Refer to AC Characteristics for instruction execution time R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 126 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 3 3 DC Characteristics 3 3 1 Pin characteristics TA 40 to 105 C 2 4 V x EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V 1 5 Output current high 1 Caution Remark R01DS0131EJ0310 Rev 3 10 Nov 15 2013 Conditions Per pin for POO to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 Total of POO to P04 P07 P32 to P37 P40 to P47 P102 to P106 P120 P125 to P127 P130 P140 to P145 When duty lt 70 Total of P05 P06 P10 to P17 P30 P31 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 P101 P110 to P117 P146 P147
228. on clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 CSI mode connection diagram during communication at same potential SCKp SCK microcontroller 5 SO User device SOp SI R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 147 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 tkcy1 2 t 12 1 2 CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 tkcy1 2 Input data tkso1 2 X Remarks 1 p CSI number p 00 01 10 11 20 21 30 31 2 m Unit number n Channel number mn 00 to 03 10 to 13 R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 148 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 4 During communication at same potential simplified Pc mode Ta 40 to 105 C 2 4 V lt EVppo EVpni lt lt 5 5 V Vss EVsso EVssi 0 V Parameter SCLr clock frequency Conditions 2 7 V EVppo lt 5 5 V 50 pF Rb 2 7 kQ HS high speed main Mode MIN MAX 2 4 V EVppo 5 5 V 100 pF Ro 3 KQ Hold time when SCLr
229. or The supply current of the RL78 microcontrollers is the sum of the values of either Ipp Ipp2 and IRrc when the real time clock operates in operation mode HALT mode When the low speed on chip oscillator is selected IF should be added Ipp2 subsystem clock operation includes the operational current of the real time clock 4 Current flowing only to the 12 bit interval timer excluding the operating current of the low speed on chip ocsillator and the XT1 oscillator The supply current of the RL78 microcontrollers is the sum of the values of either 1 1 1022 and lir when the 12 bit interval timer operates in operation mode or HALT mode When the low speed on chip oscillator is selected Iri should be added 5 Current flowing only to the watchdog timer including the operating current of the low speed on chip oscillator The supply current of the RL78 microcontrollers is the sum of Ipp2 or Ipps and when the watchdog timer is in operation R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 75 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 6 Current flowing only to the A D converter The supply current of the RL78 microcontrollers is the sum of Ipp1 or 002 and lanc when the A D converter operates in an operation mode or the HALT mode 7 Current flowing only to the LVD circuit The supply current of the RL78 microcontrollers is the sum of Ipp Ippe or and ILvb
230. ore 10 AS after the TOOLO pin is set to the the external reset is released low level Time to hold the TOOLO pin at tup POR and LVD reset must be released before 1 ms the low level after the external the external reset is released reset is released excluding the processing time of the firmware to control the flash memory time OOH reception la TOOLRxD TOOLTxD mode TOOLO 8 1 gt 2 lt 3 4 RESET 723 us processing tsu SUINIT 1 1 1 1 7 gt i 1 The low level is input to the TOOLO pin 2 The external reset is released POR and LVD reset must be released before the external reset is released 3 The TOOLO pin is set to the high level 4 Setting of the flash memory programming mode by UART reception and complete the baud rate setting Remark tsuinit Communication for the initial setting must be completed within 100 ms after the external reset is released during this period ts Time to release the external reset after the TOOLO pin is set to the low level tHo Time to hold the pin at the low level after the external reset is released excluding the processing time of the firmware to control the flash memory R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 122 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS TA 40 to 105 C 3 ELECTRICAL SPECIFICATIONS G TA 40 to 105
231. output mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg Remarks 1 This value is valid only when CSIOO s peripheral I O redirect function is not used 2 CSI number p 00 m Unit number m 0 n Channel number n 0 g PIM and POM numbers g 1 3 fwck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 83 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 3 During communication at same potential CSI mode master mode SCKp internal clock output Ta 40 to 85 C 1 6 V lt EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions HS high speed LS low speed LV low voltage main Mode main Mode main Mode MIN MAX MIN MAX MIN MAX SCKp cycle time tkcvi tkcvi gt 4 2 7 V lt lt 5 5 125 500 1000 ns V 2 4 V EVppo lt 5 5 250 500 1000 ns V 1 8 V lt EVppo lt 5 5 500 500 1000 ns V 1 7 V lt EVppo lt 5 5 1000 1000 1000 ns V 1 6 V EVppo 5 5 1000 1000 ns V SCKp high low level tku 4 0 V EVppo lt 5 5 V tkcvi 2 tkcvi 2 tkcvi 2 ns width 12 50
232. ov 15 2013 RENESAS Page 46 of 194 110 03 11 0 81 010 02 010 82 SCK11 P95 SH 1 P96 011 97 SCLOO P10 RL78 CODE FLASH MEMORY CPU CORE lt E DATA FLASH MEMORY 13 14 PORT 15 P130 P137 K 8 gt P140 to P147 KZZ gt P150 to P156 1 5 14 128 pin products TIMER ARRAY TIMER ARRAY UNITO Bch UNITI Bch E 06 AHU TOHO P R lt PORTO 8 P00 to P07 TI01 TO01 P16 TH 1 TO11 P65 PORT 1 P10to P17 TIO2 TOO2 P17 TIO2 TOO2 P15 112 7012 66 PORT 2 P20 to P27 TI03 TO03 P31 TH3 TO13 P67 0 1 lt PORTS P3010 P37 TIO4 TOO4 P42 14 014 103 104 04 13 lt PORT 4 gt P40 to P47 TI05 TO05 P46 15 015 104 105 005 12 Pos 50 to P57 106 006 102 TI16 TO16 P105 rows TIO6 TOO6 P11 107 007 145 1107 7007 10 TI17 TO17 P106 lt Ponte K gt Peo to P67 RxD2 P14 RxD2 P76 lt port7 8 P70 to P77 SERIAL ARRAY UNITO 4ch RxDO P1 1 RxDO P16 PORT8 KE P80 to P87 TxDO P12 TxDO P17 8 ANIO P20 to 7 27 RxD1 P03 RxD1 P81 ANIB P150 to ANI14 P156 K porto Cg Poo to P97 TxD1 P02 TxD1 P82 ANI16 P03 ANI17 P02 SOKOQPI0 SOKOOIPSE ANI18 P147 ANI19 P120 NDCONVERTER ANI20 P100 ANI21 37 portio KEZ P100 to P106 SI00 P11 SI00 P16 ANI22 P36 ANI23 P35 lt gt SO00 P12 SO00 P17 ANI24 P117
233. pheral Functions Common to all products TA 40 to 85 C 1 6 V lt EVppo 1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Parameter Conditions Low speedon l 0 20 uA chip oscillator operating current RTC operating Irto 123 0 02 uA current 12 bit interval Ir s4 0 02 uA timer operating current Watchdog timer 25 fi 15 kHz 0 22 uA operating current A D converter 1 6 When Normal mode AVrerp 5 0 V 1 3 1 7 operating conversion at ow voltage mode AVnere 3 0 V 05 07 mA current maximum speed A D converter lapner e 1 75 0 uA reference voltage current Temperature Itups Note 1 75 0 uA sensor operating current LVD operating j Ivo ees 7 0 08 uA current Self lesp Notes 1 9 2 50 12 20 mA programming operating current BGO operating Isao 8 2 50 12 20 mA current SNOOZE Isnoz Note 1 ADC operation The mode is performed 1 0 50 0 60 mA operating current The A D conversion operations are 1 20 1 44 mA performed Low voltage mode AVnere Voo 3 0 V CSI UART operation 0 70 0 84 mA Notes 1 Current flowing to Vpp 2 When high speed on chip oscillator and high speed system clock are stopped 3 Current flowing only to the real time clock RTC excluding the operating current of the low speed on chip ocsillator and the XT1 oscillat
234. ppo 4 0 V 2 3 V lt Vo lt 2 7 V Co 30 pF Rb 2 7 KQ 2 4 V lt EVbpo lt 3 3 V 1 6 V lt Vo lt 2 0 V Co 30 pF Re 2 7 Delay time from SCKpl to SOp output Note When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 4 0 V lt EVppo 5 5 V 2 7 V lt Vo 4 0 V 30 pF Rb 1 4 KQ 2 7 V lt EVpoo lt 4 0 V 2 3 V lt Vo lt 2 7 V Co 30 pF Ro 2 7 2 4 V lt EVppo lt 3 3 V 1 6 V lt Vo 2 0 V Cb 30 pF Ro 5 5 KQ Caution Select the TTL input buffer for the Sip pin and the N ch open drain output tolerance When 20 to 52 pin products EVpp tolerance When 64 to 100 products mode for the SOp pin and SCKp pin by using port input mode register g PIMg and port output mode register g POMg For and Vit see the DC characteristics with TTL input buffer selected Remarks are listed on the page after the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NE SAS Page 156 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 6 Communication at different potential 1 8 V 2 5 V 3 V CSI mode master mode SCKp internal clock output 3 3 Ta 40 to 105 2 4 V lt EVppo EVpp1 lt lt 5 5 V Vss EVsso EVssi 0 V HS high speed main Mode MIN Parameter Slp setup time to SCKpJ Conditions 4 0 V lt EVppo lt 5 5 V 2 7 V
235. product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or systems manufactured by you 8 Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations 9 Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction When exporting the Renesas Electronics products or technology described in this document you should comply with the applicable expor
236. r not including the current flowing into the 12 bit interval timer and watchdog timer 6 Not including the current flowing into the RTC 12 bit interval timer and watchdog timer 7 Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V lt lt 5 5 V 1 MHz to 32 MHz 2 4 V lt lt 5 5 V 1 MHz to 16 MHz 8 Regarding the value for current operate the subsystem clock in STOP mode refer to that in HALT mode Remarks 1 fux High speed system clock frequency X1 clock oscillation frequency or external main system clock frequency 2 fiu High speed on chip oscillator clock frequency 3 fsue Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation and STOP mode temperature condition of the TYP value is Ta 25 R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 135 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 2 Flash ROM 96 to 256 KB of 30 to 100 pin products Ta 40 to 105 C 2 4 V x EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V 1 2 Parameter Supply current 1 Note Operating mode HS high speed main mode Note 5 Conditions 32 MHz Note Basic operation Voo 5 0 V Voo 3 0 V Normal operation Voo 5 0 V Voo 3 0 V 24 MHz Notes Normal oper
237. r clock frequency 3 fsuge Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation and STOP mode temperature condition of the TYP value is Ta 25 R01DS0131EJ0310 Rev 3 10 RENESAS Page 70 of 194 Nov 15 2013 RL78 G13 3 128 pin products and flash ROM 384 to 512 KB of 44 to 100 pin products 40 to 85 C 1 6 V lt EVppo 1 lt Voo lt 5 5 V Vss EVsso EVssi 0 V 1 2 Parameter Supply current 1 Note Operating mode HS high speed main mode Note 5 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Conditions 32 MHz e Basic operation Voo 5 0 V Voo 3 0 V Normal operation Vpp 5 0 V Voo 3 0 V 24 MHz Noes Normal operation Vpp 5 0V Voo 3 0 V 16 MHz Note 3 Normal operation Vpp 5 0 V Voo 3 0 V LS low speed main m od le Note 5 8 MHz Note 3 Normal operation Voo 3 0 V Voo 2 0 V LV low voltage main mode Note 5 4 MHz 63 Normal operation Voo 3 0 V Voo 2 0 V HS high speed main mode Note 5 fux 20 2 Voo 5 0 V Normal operation Square wave input Resonator connection fux 20 MHz 2 Voo 3 0 V Normal operation Square wave input Resonator connection fux 10 MHz 2 Voo 5 0 V Normal operation
238. racteristics 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 3 2 1 X1 XT1 oscillator characteristics TA 40 to 105 C 2 4 V lt Vpp lt 5 5 V Vss 0 V Parameter X1 clock oscillation frequency fx Resonator Ceramic resonator crystal resonator Conditions 2 7 V lt Voo lt 5 5 V 2 4 V lt Voo lt 2 7 V XT1 clock oscillation Crystal resonator frequency Note Indicates only permissible oscillator frequency ranges Refer to AC Characteristics for instruction execution time Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics Caution Since the CPU is started by the high speed on chip oscillator clock after a reset release check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register OSTC by the user Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register OSTS after sufficiently evaluating the oscillation stabilization time with the resonator to be used Remark When using the X1 oscillator and XT1 oscillator refer to 5 4 System Clock Oscillator 3 2 2 On chip oscillator characteristics TA 40 to 105 C 2 4 V lt Vpp lt 5 5 V Vss 0 V Oscillators Parameters High speed on chip oscillator clock frequency gt Conditions High speed
239. ramic oscillation external main system clock input EXCLK 1 to 20 MHz 2 7 to 5 5 V 1 to 8 MHz Voo 1 8 to 2 7 V 1 to 4 MHz Vpp 1 6 to 1 8 V HS High speed main mode 1 to 32 MHz Voo 2 7 to 5 5 V HS High speed main mode 1 to 16 MHz Voo 2 4 to 5 5 V LS Low speed main mode 1 to 8 MHz 1 8 to 5 5 V LV Low voltage main mode 1 to 4 MHz Voo 1 6 to 5 5 V Subsystem clock XT1 crystal oscillation external subsystem clock input EXCLKS 32 768 kHz Low speed on chip oscillator 15 kHz TYP General purpose register 8 bit register x 8 x 4 banks Minimum instruction execution time 0 03125 us High speed on chip oscillator 32 MHz operation 0 05 us High speed system clock fux 20 MHz operation 30 5 us Subsystem clock fsue 32 768 kHz operation Instruction set e Data transfer 8 16 bits e Adder and subtractor logical operation 8 16 bits e Multiplication 8 bits x 8 bits e Rotate barrel shift and bit manipulation Set reset test and Boolean operation etc port Total 74 92 120 CMOS I O 64 N ch O D EVpp withstand voltage 21 82 N ch O D EVoo withstand voltage 24 110 N ch O D EVpp withstand voltage 25 CMOS input 5 5 5 CMOS output 1 1 1 N ch O D I O withstand voltage 6 V 4 4 4 16 bit timer 1
240. re as follows Overall error Add 1 0 LSB to the MAX value when AVe Voo Zero scale error Full scale error Add 0 05 FSR to the MAX value when AVrere Vov AVREFP and EVppo Integral linearity error Differential linearity error Add 0 5 LSB to the MAX value when AVnere Voo 4 When AVrere lt EVooo Von the MAX values are as follows Overall error Add 4 0 LSB to the MAX value when AVrerp Voo Zero scale error Full scale error Add 0 20 FSR to the MAX value when AVnere Vov Integral linearity error Differential linearity error Add 2 0 LSB to the MAX value when AVnere Voo 5 When the conversion time is set to 57 ws min and 95 ws max R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 115 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 3 When reference voltage Voo ADREFP1 0 ADREFPO 0 reference voltage Vss ADREFM 0 target pin ANIO to ANI14 ANI16 to ANI26 internal reference voltage and temperature sensor output voltage 40 to 85 C 1 6 V lt EVppo EVpni lt lt 5 5 V Vss EVsso EVssi 0 V Reference voltage Reference voltage Vss Parameter Conditions Resolution Overall error 10 bit resolution 1 8 V lt VDD lt 5 5 V 1 6 V lt VoD lt 5 5 V Note 3 Conversion time 10 bit resolution 3 6 lt lt 5 5 Target to ANI14
241. re clock 1 8 V lt VoD lt 5 5 V frequency Number of code flash rewrites Retained for 20 years TA 85 Notes 1 2 3 Number of data flash rewrites Retained for 1 years TA 25 1 000 000 Notes 1 2 3 Retained for 5 years 85 100 000 Retained for 20 years 85 10 000 Notes 1 1 erase 1 write after the erase is regarded as 1 rewrite The retaining years are until next rewrite after the rewrite 2 When using flash memory programmer and Renesas Electronics self programming library 3 These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation 2 9 Dedicated Flash Memory Programmer Communication UART Ta 40 to 85 C 1 8 V lt EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 121 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 10 Timing Specs for Switching Flash Memory Programming Modes Ta 40 to 85 C 1 8 V lt EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V Parameter Conditions Time to complete the tsuinit POR and LVD reset must be released before 100 ms communication for the initial the external reset is released setting after the external reset is released Time to release the external reset tsu POR and LVD reset must be released bef
242. restart tsu sta 2 7 V lt EVppo lt 5 5 V 0 6 0 6 0 6 us condition 1 8 V lt EVopo lt 5 5 V 0 6 0 6 0 6 us Hold time 1 tHo sTa 2 7 lt lt 5 5 V 0 6 0 6 0 6 us 1 8 V lt EVppo lt 5 5 V 0 6 0 6 0 6 Ls Hold time when SCLAO 2 7 V lt EVppo lt 5 5 V 1 3 1 3 1 3 Ls v 1 8 V lt EVopo lt 5 5 V 1 3 1 3 1 3 us Hold time when SCLAO 27 V lt EVomo lt 5 5 V 0 6 0 6 0 6 us H 1 8 V lt EVopo lt 5 5 V 0 6 0 6 0 6 us Data setup time tsupar 2 7 V lt EVppo lt 5 5 V 100 100 100 Ls reception 1 8 V lt EVopo lt 5 5 V 100 100 100 us Data hold time 2 7V lt EVppo lt 5 5 V 0 0 9 0 0 9 0 0 9 Ls transmission 1 8 V lt EVoo lt 5 5 V 09 09 09 us Setup time of stop tsu sro 2 7 V lt EVppo lt 5 5 V 0 6 0 6 0 6 us condition 1 8 V lt EVopo lt 5 5 V 0 6 0 6 0 6 us Bus free time 2 7 V lt EVppo lt 5 5 V us 1 8 V lt EVppo lt 5 5 V Ls Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MAX of is during normal transfer and a wait state is inserted in the ACK acknowledge timing Caution The values in the above table are applied even when bit 2 PIOR2 in the peripheral I O redirection register PIOR is 1 At this time the pin characteristics lou lot1 must satisfy the values in the redirect destination Remark The
243. ring Part Numbers 8 12 Pin count Package Data flash Fields of Ordering Part Number Application Note 64 pin plastic LQFP Mounted R5F100LCAFAzVO R5F100LDAFA V0 R5F100LEAFA VO 12 x 12 mm 0 65 R5F100LFAFA V0 R5F100LGAFAs VO R5F100LHAFA VO mm pitch R5F100LJAFAs VO R5F100LKAFA VO R5F100LLAFA VO R5F100LCAFA X0 R5F100LDAFA X0 R5F100LEAFA XO R5F100LFAFA X0 R5F100LGAFA X0 R5F100LHAFA XO R5F100LJAFA X0 R5F100LKAFA X0 R5F100LLAFA X0 R5F100LCDFA VO0 R5F100LDDFA V0 R5F100LEDFA VO R5F100LFDFA VO R5F100LGDFA VO R5F100LHDFA VO R5F100LUDFA V0 R5F100LKDFAzVO R5F100LLDFA VO R5F100LCDFA X0 R5F100LDDFA X0 R5F100LEDFA XO R5F100LFDFA X0 R5F100LGDFA X0 R5F100LHDFA XO R5F100LUDFA X0 R5F100LKDFA X0 R5F100LLDFA X0 R5F100LCGFA V0 R5F100LDGFA V0 R5F100LEGFA VO R5F100LFGFA VO R5F100LGGFA VO0 R5F100LHGFA VO R5F100LUGFA VO R5F100LCGFA X0 R5F100LDGFA X0 R5F100LEGFA XO R5F100LFGFA X0 R5F100LGGFA X0O R5F100LHGFA X0 R5F100LUGFA X0 Not R5F101LCAFA V0 R5F101LDAFA VO0 R5F101LEAFA VO mounted R5F101LFAFAZVO R5F101LGAFAzVO R5F101LHAFA VO R5F101LJAFAsVO R5F101LKAFAsVO R5F101LLAFA VO R5F101LCAFA X0 R5F101LDAFA X0 R5F101LEAFA XO R5F101LFAFA X0 R5F101LGAFA X0 R5F101LHAFA XO R5F101LUAFA X0 R5F101LKAFA X0 R5F101LLAFA X0 R5F101LCDFA VO R5F101LDDFA V0 R5F101LEDFA VO R5F101LFDFA VO0 R5F101LGDFA V0 R5F101LHDFA VO R5F101LUDFA V0 R5F101LKDFA V0 R5F101LLDFAZVO R5F101LCDFA X0 R5F101LDDFA X0 R5F101LEDFAZXO R5F101
244. ructions e Back up retention in all modes High speed On chip Oscillator e 32 MHz with 1 accuracy over voltage 1 8 V to 5 5 V and temperature 20 C to 85 C e Pre configured settings 32 MHz 24 MHz 16 MHz 12 MHz 8 MHz 6 MHz 4 MHz 3 MHz 2 MHz and 1 MHz Reset and Supply Management e Power on reset POR monitor generator Data Memory Access DMA Coniroller e Up to 4 fully programmable channels e Transfer unit 8 or 16 bit Multiple Communication Interfaces e Up to 8 x master e Up to 2 x multi master e Up to 8 x CSI SPI 7 8 bit e Up to 4 x UART 7 8 9 bit e Up to 1 x LIN Extended Function Timers e Multi function 16 bit timers Up to 16 channels e Real time clock RTC 1 channel full calendar and alarm function with watch correction function e Interval Timer 12 bit 1 channel e 15 kHz watchdog timer 1 channel window function Rich Analog e ADC Up to 26 channels 10 bit resolution 2 1 us conversion time e Supports 1 6 V e Internal voltage reference 1 45 V e On chip temperature sensor Safety Features IEC or UL 60730 compliance e Flash memory CRC calculation e RAM parity error check RAM write protection e SFR write protection e memory access detection e Clock stop frequency detection e ADC self test General Purpose I O e 5V tolerant high current up to 20 mA per pin e Open Drain Internal Pull up support e Different potential interface
245. s G Industrial applications Ta 40 to 105 C are different from those of the products A Consumer applications and D Industrial applications For details refer to 3 1 to 3 10 3 1 Absolute Maximum Ratings Absolute Maximum Ratings Ta 25 C 1 2 Parameter Supply voltage Voo Conditions Ratings 0 5 to 6 5 EVopo EVpp1 EVppo EVpp1 0 5 to 6 5 EVsso EVss1 EVsso EVssi 0 5 to 0 3 REGC pin input voltage VinEGC REGC 0 3 to 2 8 0 3 to 0 3 Input voltage Vin P00 to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P64 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 0 3 to EVppo 0 3 and 0 3 to 0 3 P60 to P63 N ch open drain 0 3 to 6 5 P20 to P27 P121 to P124 P137 P150 to P156 EXCLK EXCLKS RESET 0 3 to 40 3 ete Output voltage to P07 P10 to P17 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 0 3 to EVppo 0 3 and 0 3 to 0 3 e P20 to P27 P150 to P156 0 3 to Von 40 3 ete Analog input voltage ANI16 to ANI26 0 3 to EVppo 0 3 and 0 3 to AVrer 0 3Notes 2 3 ANIO to ANI14 0 3 to Voo 0 3 and 0 3 to AVrer 0 3 3 Conn
246. s including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices 4 STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of the device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do
247. s or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others 4 You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product 5 Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots etc High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems and safety equipment etc Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury artificial life support devices or systems surgical implantations etc or may cause serious property damages nuclear rea
248. support Can connect to a 1 8 2 5 3 V device Operating Ambient Temperature e Standard 40 C to 85 C e Extended 40 C to 105 C Package Type and Pin Count From 3mm x 3mm to 14mm x 20mm 44 48 52 64 80 100 128 QFN 24 32 40 48 e Low voltage detection LVD with 14 setting options SSOP 20 30 Interrupt and or reset function LGA 25 36 BGA 64 R01DS0131EJ0310 Rev 3 10 24 NEC SAS Page 1 of 194 Nov 15 2013 RL78 G13 1 OUTLINE O ROM RAM capacities RL78 G13 25 pins 30 pins R5F100AG R5F100BG R5F100CG R5F101AG R5F101BG R5F101CG R5F100AF R5F100BF R5F100CF R5F101AF R5F101BF R5F101CF R5F1006E R5F1007E R5F1008E R5F100AE R5F100BE R5F100CE R5F1016E R5F1017E R5F1018E R5F101AE R5F101BE R5F101CE R5F1006D R5F1007D R5F1008D R5F100AD R5F100BD R5F100CD R5F1016D R5F1017D R5F1018D R5F101AD R5F101BD R5F101CD R5F1006C R5F1007C R5F1008C R5F100AC R5F100BC R5F100CC R5F1016C R5F1017C R5F1018C R5F101AC R5F101BC R5F101CC R5F1006A R5F1007A R5F1008A R5F100AA R5F100BA R5F100CA R5F1016A R5F1017A R5F1018A R5F101AA R5F101BA R5F101CA RL78 G13 52 pins 64 pins 100 pins 128 pins R5F100FL R5F100GL R5F100JL R5F100LL R5F100ML R5F100PL R5F100SL R5F101FL R5F101GL R5F101JL R5F101LL R5F101ML R5F101PL R5F101SL R5F100FK R5F100GK R5F100JK R5F100LK 5 100 R5F100PK R5F100SK R5F101FK R
249. t Note 4 operation Resonator connection TA 85 G Notes and Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 Nov 15 2013 21 NESAS Page 67 of 194 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C Notes 1 Total current flowing into EVopo and 1 including the input leakage current flowing when the level of the input pin is fixed Vop EVppo and EVpo1 or Vss EVsso and EVssi The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite 2 When high speed on chip oscillator and subsystem clock are stopped 3 When high speed system clock and subsystem clock are stopped 4 When high speed on chip oscillator and high speed system clock are stopped When AMPHS1 1 Ultra low power consumption oscillation However not including the current flowing into the 12 bit interval timer and watchdog timer 5 Relationship between operation voltage width operation frequency of CPU and operation mode is as below HS high speed main mode 2 7 V lt lt 5 5 V 1 MHz to 32 MHz 2 4 V lt lt 5 5 V 1 MHz to 16 MHz LS low speed main mode 1 8 V lt Von lt 5 5 V 1 MHz to 8 MHz LV low voltage main mode 1 6 V lt Voo lt 5 5 V 1 MHz to 4 MHz
250. t control laws and regulations and follow the procedures required by such laws and regulations 10 It is the responsibility of the buyer or distributor of Renesas Electronics products who distributes disposes of or otherwise places the product with a third party to notify such third party in advance of the contents and conditions set forth in this document Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products 11 This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics 12 Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics RENESAS SALES OFFICES Renesas Electronics Corporation http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2880 Scott Boulevard Santa Clara CA 95050 2554 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 1
251. t numbers represent the numbers at the time of publication For the latest ordering part numbers refer to the target product page of the Renesas Electronics website R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 6 of 194 Nov 15 2013 RL78 G13 1 OUTLINE Table 1 1 List of Ordering Part Numbers 4 12 Package Data flash Fields of Ordering Part Number Application Note 44 pin plastic LQFP Mounted R5F100FAAFP V0 R5F100FCAFP VO R5F100FDAFP VO 10 x 10 mm 0 8 R5F100FEAFP VO0 R5F100FFAFPz2VO R5F100FGAFP VO mm pitch R5F100FHAFP VO R5F100FJAFP V0 R5F100FKAFP VO R5F100FLAFPZVO R5F100FAAFP X0 R5F100FCAFP X0 R5F100FDAFP X0 R5F100FEAFP X0 R5F100FFAFP X0 R5F100FGAFP XO R5F100FHAFP X0 R5F100FJAFP X0 R5F100FKAFP XO R5F100FLAFP X0 R5F100FADFP V0 R5F100FCDFP VO R5F100FDDFP VO R5F100FEDFP V0 R5F100FFDFP V0 R5F100FGDFP VO R5F100FHDFP V0 R5F100FJDFP VO0 R5F100FKDFP VO R5F100FLDFPzVO R5F100FADFP X0 R5F100FCDFP X0 R5F100FDDFP X0 R5F100FEDFP X0 R5F100FFDFP X0 R5F100FGDFP XO R5F100FHDFP X0 R5F100FJDFP X0 R5F100FKDFP XO R5F100FLDFP X0 R5F100FAGFP V0 R5F100FCGFP VO0 R5F100FDGFP VO R5F100FEGFP V0 R5F100FFGFP V0 R5F100FGGFP VO R5F100FHGFP VO R5F100FJGFP V0 R5F100FAGFP X0 R5F100FCGFP X0 R5F100FDGFP XO R5F100FEGFP X0 R5F100FFGFP X0 R5F100FGGFP XO R5F100FHGFP X0 R5F100FJGFP XO Not R5F101FAAFP VO0 R5F101FCAFP VO0 R5F101FDAFP VO mounted R5F101FEAFPzVO R5F101FFAFP VO0 R5F101FGAFP VO R5
252. tail of lead end 1 36 25 A3 37 24 Ge 1 1 b E HE Lp be L1 48 _ 13 UNIT mm 1 12 ITEM DIMENSIONS y D 7 00 0 20 E 7 00 0 20 TEE Y HD 9 00 0 20 9 00 0 20 gt ZD 1 60 A1 0 10 0 05 Aa 2 1 40 0 05 A3 0 25 A24 0 22 0 05 Y Y 0 145 0 055 0 045 0 50 S Y S Lp 0 60 0 15 i 1 L1 1 00 0 20 i 0D 0 89 S y JS A1 0 50 x 0 08 y 0 08 NOTE zD 0 75 ZE 0 75 Each lead centerline is located within 0 08 mm of its true position at maximum material condition 2012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev 3 10 QE NE S AS Page 184 of 194 Nov 15 2013 RL78 G13 4 PACKAGE DRAWINGS R5F100GAANA R5F100GCANA R5F100GDANA R5F100GEANA R5F100GFANA R5F100GGANA R5F100GHANA R5F100GJANA R5F100GKANA R5F100GLANA R5F101GAANA R5F101GCANA R5F101GDANA R5F101GEANA R5F101GFANA R5F101GGANA R5F101GHANA R5F101GJANA R5F101GKANA R5F101GLANA R5F100GADNA R5F100GCDNA R5F100GDDNA R5F100GEDNA R5F100GFDNA R5F100GGDNA R5F100GHDNA R5F100GJDNA R5F100GKDNA R5F100GLDNA R5F101GADNA R5F101GCDNA R5F101GDDNA R5F101GEDNA R5F101GFDNA R5F101GGDNA R5F101GHDNA R5F101GJDNA R5F101GKDNA R5F101GLDNA R5F100GAGNA R5F100GCGNA R5F100GDGNA R5F100GEGN
253. tion frequency or external main system clock frequency 2 fiH High speed on chip oscillator clock frequency 3 fsus Subsystem clock frequency XT1 clock oscillation frequency 4 Except subsystem clock operation temperature condition of the value is TA 25 R01DS0131EJ0310 Rev 3 10 RENESAS Page 133 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 1 Flash ROM 16 to 64 KB of 20 to 64 pin products Ta 40 to 105 C 2 4 V x EVppo lt Vpp lt 5 5 V Vss EVsso 0 V 2 2 Parameter Supply current Note 1 HS high speed main mode Note 7 Conditions fiu 32 MHz Voo 5 0 V Voo 3 0 V 24 MHz Voo 5 0 V Vop 3 0 V fin 16 MHz Voo 5 0 V Voo 3 0 V HS high speed main mode Note 7 fux 20 MHz 3 Voo 5 0 V Square wave input Resonator connection fux 20 MHz 3 Vop 3 0 V Square wave input Resonator connection fux 10 MHz ete Voo 5 0 V Square wave input Resonator connection fux 10 MHz e e3 Vpp 3 0 V Square wave input Resonator connection Subsystem clock operation 32 768 kHz te5 Ta 40 fsus 32 768 5 25 Square wave input Resonator connection Square wave input Resonator connection fsus 32 768 kHz 5 Ta 50 C Square wave input
254. tions of Note 8 in a table corrected 68 4 Common to RL78 G13 all products Descriptions of Notes corrected 69 2 4 AC Characteristics Symbol of external system clock frequency corrected 961098 2 6 1 A D converter characteristics Notes of overall error corrected 100 2 6 2 Temperature sensor characteristics Parameter name corrected 104 2 8 Flash Memory Programming Characteristics Incorrect descriptions corrected 116 3 10 52 pin products Package drawings of 52 pin products corrected 120 3 12 80 pin products Package drawings of 80 pin products corrected 1 Modification of 1 1 Features 3 Modification of 1 2 List of Part Numbers 41015 Modification of Table 1 1 List of Ordering Part Numbers note and caution 161032 Modification of package type in 1 3 1 to 1 3 14 33 Modification of description in 1 4 Pin Identification 48 50 52 Modification of caution table and note in 1 6 Outline of Functions 55 Modification of description in table of Absolute Maximum Ratings TA 25 57 Modification of table note caution and remark in 2 2 1 X1 XT1 oscillator characteristics 57 Modification of table in 2 2 2 On chip oscillator characteristics 58 Modification of note 3 of table 1 5 in 2 3 1 Pin characteristics 59 Modification of note 3 of table 2 5 in 2 3 1 Pin characteristics 63 Modification of table in 1 Flash ROM 16 to 64 KB of 20 to 64 pin products 64 Modification of notes 1 and 4 in 1 Flash ROM 16 to 64 KB of 20 to 64 pin pr
255. to 3 6 2 Temperature sensor internal reference voltage characteristics R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 170 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 4 When reference voltage Internal reference voltage ADREFP1 1 ADREFPO 0 reference voltage ADREFM 1 target pin ANIO 2 to ANI14 ANI16 to ANI26 Ta 40 to 105 C 2 4 V lt EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V Reference voltage Reference voltage AVrerm 0 V HS high speed main mode Parameter Resolution Conditions Conversion time 8 bit resolution 2 4 V lt Vpp lt 5 5 V Zero scale errorhetes 1 2 8 bit resolution 2 4 V lt VDD lt 5 5 V Integral linearity 8 bit resolution 2 4 V lt VDD lt 5 5 V Note 1 Differential linearity error 8 bit resolution 2 4 V lt Vpp lt 5 5 V Analog input voltage Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 Refer to 3 6 2 Temperature sensor internal reference voltage characteristics 4 When reference voltage Vss the MAX values are as follows Zero scale error Add 0 35 FSR to the MAX value when reference voltage AVREFM Note 3 Integral linearity error Add 0 5 LS
256. to P77 P120 PORT12 P121 to P124 P130 gt PORT 13 Se P140 P141 QC rom KD pie P147 ANIO P20 to ANI7 P27 ANI16 P03 ANI 7 PO2 ANI18 P147 ANI19 P120 AVnere P20 AVnerw P21 A D CONVERTER KRO P70 to KR7 P77 lt KEY RETURN 8 POWER ON RESET VOLTAGE DETECTOR POR LVD CONTROL RESET CONTROL lt gt ON CHIP DEBUG TooLo P40 SYSTEM RESET CONTROL X1 P121 HIGHSPEED X EXCLK P122 ON CHIP XT1 P123 QSCIEEATOR XT2 EXCLKS P124 VOLTAGE REGULATOR RECS RxD2 P 14 RxD2 P76 INTPO P137 NTP1 P50 NTP2 P51 NTP3 P30 NTP4 P31 NTP5 P16 INTP5 P12 NTP6 P140 NTP7 P141 NTP8 P74 NTP9 P75 NTP10 P76 INTP10 P52 NTP11 P77 INTP11 P53 CONTROL Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral redirection register PIOR PIOR in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 Nov 15 2013 RENESAS Refer to Figure 4 8 Format of Peripheral I O Redirection Register Page 44 of 194 1 5 12 80 pin products TIMER ARRAY TIMER ARRAY UNITO 8ch UNIT1 4ch TI00 P00 K gt PORT 0 P00 to P06 ODD TH O TO10 P64 lt TI01 TO01 P16 TI11 TO11 P65 qu PORT 1 KC 8 P10 to P17 102 002 17 TIO2 TOO2 P15 Dd lt PORT2 K P20 to P27 TIOS TOOS P31 TI13 TO13 P67 TIO3
257. to keep the hold time of SCLr L and SCLr H Caution Select the TTL input buffer and the N ch open drain output Voo tolerance When 20 to 52 pin products EVpp tolerance When 64 to 100 products mode for the SDAr pin and the N ch open drain output tolerance When 20 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SCLr pin by using port input mode register g PIMg and port output mode register g POMg For Viu and Vit see the DC characteristics with TTL input buffer selected Remarks are listed on the next page R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 164 of 194 Nov 15 2013 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Simplified mode connection diagram during communication at different potential SDAr RL78 microcontroller User device SCLr SCL Simplified mode serial transfer timing during communication at different potential 1 fsc tLow SCLr SDAr tHD DAT tsu DAT Caution Select the TTL input buffer and the N ch open drain output Vpp tolerance When 20 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SDAr pin and the N ch open drain output tolerance When 20 to 52 pin products EVpp tolerance When 64 to 100 pin products mode for the SCLr pin by using port input mode register g PIMg and port output mode register g POMg For
258. troller User device SCLr SCL Simplified mode serial transfer timing during communication at same potential 1 fsc tLow THIGH SCLr SDAr lt tsu DAT Remarks 1 Ro O Communication line SDAr pull up resistance Communication line SDAr SCLr load capacitance 2 r IIC number r 00 01 10 11 20 21 30 31 g PIM number g 0 1 4 5 8 14 h POM number g 0 1 4 5 7 to 9 14 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number m 0 1 n Channel number n 0 to 3 mn 00 to 03 10 to 13 R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 150 of 194 Nov 15 2013 RL78 G13 5 Communication at different potential 1 8 V 2 5 V 3 V UART mode 1 2 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C Ta 40 to 105 C 2 4 V lt EVppo EVpni lt lt 5 5 V Vss EVsso EVssi 0 V HS high speed main Parameter Transfer rate Reception Conditions 4 0 V EVppo lt 5 5 V 2 7 V lt Vo lt 4 0 V MIN Mode MAX fuck 12 ete Theoretical value of the maximum transfer rate fork 32 MHZ fuck folk 2 6 2 7 V lt 4 0 V 2 3 V lt Vo lt 2 7 V 12 Note Theoretical value of the maximum transfer rate 32 MHz fuck 2 6
259. uct in the RL78 G13 User s Manual Hardware R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 54 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 C 2 1 Absolute Maximum Ratings Absolute Maximum Ratings 25 1 2 Parameter Symbols Conditions Ratings Unit Supply voltage Voo 0 5 to 6 5 V EVppo EVpp1 EVppo 1 0 5 to 6 5 V EVsso EVssi EVsso EVssi 0 5 to 0 3 V REGC pin input voltage REGC 0 3 to 2 8 V and 0 3 to Voo 0 3 Input voltage Vin POO to P07 P10 to P17 P30 to P37 P40 to P47 0 3 to EVppo 0 3 V P50 to P57 P64 to P67 P70 to P77 P80 to P87 and 0 3 to 0 3 2 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P140 to P147 Vio P60 to P63 N ch open drain 0 3 to 6 5 Vis P20 to P27 P121 to P124 P137 P150 to P156 0 3 to Von 0 3 2 EXCLK EXCLKS RESET Output voltage Voi to P07 P10 to P17 P30 to P37 P40 to P47 0 3 to EVppo 0 3 V P50 to P57 P60 to P67 P70 to P77 P80 to 87 and 0 3 to Von 0 3 Nete2 P90 to P97 P100 to P106 P110 to P117 P120 P125 to P127 P130 P140 to P147 P20 to P27 P150 to P156 0 3 to Von 4 0 3 Note 2 Analog input voltage Van ANI16 to ANI26 0 3 to EVopo 0 3 and 0 3 to AVrer 0 3 23 Vai ANIO to ANI14 0 3 to Voo 0 3 V and 0 3 to AVrer 0 3Netes 2 3 Notes 1 Connect the REGC
260. v 3 10 Nov 15 2013 21 NESAS Page 169 of 194 RL78 G13 3 ELECTRICAL SPECIFICATIONS Ta 40 to 105 C 3 When reference voltage Voo ADREFP1 0 ADREFPO 0 reference voltage Vss ADREFM 0 target pin ANIO to ANI14 ANI16 to ANI26 internal reference voltage and temperature sensor output voltage Ta 40 to 105 C 2 4 V lt EVppo 1 lt lt 5 5 V Vss EVsso EVssi 0 V Reference voltage Voo Reference voltage Vss Parameter Conditions Resolution Note 1 Overall error 10 bit resolution Conversion time 10 bit resolution Target pin ANIO to ANI14 ANI16 to ANI26 10 bit resolution Target pin Internal reference voltage and temperature sensor output voltage HS high speed main mode Zero scale error es 1 2 10 bit resolution Full scale error gt 10 bit resolution Note Integral linearity error 10 bit resolution 1 Differential linearity error 10 bit resolution Note 1 Analog input voltage ANIO to ANI14 ANI16 to ANI26 Internal reference voltage output Vear Pte 3 2 4 V Vpp lt 5 5 V HS high speed main mode Temperature sensor output voltage Vrups s Notes 2 4 V lt Vpp lt 5 5 V HS high speed main mode Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 3 Refer
261. when the LVD circuit is in operation 8 Current flowing only during data flash rewrite 9 Current flowing only during self programming 10 For shift time to the SNOOZE mode see 18 3 3 SNOOZE mode in the RL78 G13 User s Manual Hardware Remarks 1 f L Low speed on chip oscillator clock frequency 2 Subsystem clock frequency XT1 clock oscillation frequency 3 CPU peripheral hardware clock frequency 4 Temperature condition of the value is TA 25 R01DS0131EJ0310 Rev 3 10 24 NEC S AS Page 76 of 194 Nov 15 2013 RL78 G13 2 4 AC Characteristics 2 ELECTRICAL SPECIFICATIONS A D Ta 40 to 85 TA 40 to 85 C 1 6 V lt EVppo 1 lt Voo lt 5 5 V Vss EVsso EVss1 0 V Conditions Instruction cycle minimum Tcv Main HS high 2 7 V lt Vpp lt 5 5 V 0 03125 1 Ls instruction execution time system speed main 24V lt Vro lt 27V 0 0625 1 us clock fma mode Operation LS low speed 1 8 V lt Vo lt 5 5V 0 125 1 5 main mode LV low 1 6V lt V lt 5 5V 0 25 1 us voltage main mode Subsystem clock fsus 1 8V lt Vo lt 55V 28 5 30 5 31 3 Ls operation In the self HS high 2 7 V lt V lt 5 5 V 0 03125 1 us programming speed main 24V Vmo 27 V 0 0625 1 us mode mode LS low speed 1 8 V Vop 55V 0 125 1 Ls m
262. x 0 20 NOTE y 0 10 Each lead centerline is located within 0 20 mm of ZD 1 00 its true position at maximum material condition ZE 1 00 2012 Renesas Electronics Corporation All rights reserved R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 183 of 194 Nov 15 2013 RL78 G13 4 PACKAGE DRAWINGS 4 9 48 pin Products R5F100GAAFB R5F100GCAFB R5F100GDAFB R5F100GEAFB R5F100GFAFB R5F100GGAFB R5F100GHAFB R5F100GJAFB R5F100GKAFB R5F100GLAFB R5F101GAAFB R5F101GCAFB R5F101GDAFB R5F101GEAFB R5F101GFAFB R5F101GGAFB R5F101GHAFB R5F101GJAFB R5F101GKAFB R5F101GLAFB R5F100GADFB R5F100GCDFB R5F100GDDFB R5F100GEDFB R5F100GFDFB R5F100GGDFB R5F100GHDFB R5F100GJDFB R5F100GKDFB R5F100GLDFB R5F101GADFB R5F101GCDFB R5F101GDDFB R5F101GEDFB R5F101GFDFB R5F101GGDFB R5F101GHDFB R5F101GJDFB R5F101GKDFB R5F101GLDFB R5F100GAGFB R5F100GCGFB R5F100GDGFB R5F100GEGFB R5F100GFGFB R5F100GGGFB R5F100GHGFB R5F100GJGFB JEITA Package Code RENESAS Code Previous Code MASS TYP g P LFQFP48 7x7 0 50 PLQPO0048KF A P48GA 50 8EU 1 0 16 m HD gt D i de
263. y 2 Use it with EVppo Vb 3 The following conditions are required for low voltage interface when Evppo lt 2 4 V EVppo 2 7 V MAX 2 6 Mbps 1 8 V lt EVppo lt 2 4 V 1 3 Mbps 4 The maximum operating frequencies of the CPU peripheral hardware clock are HS high speed main mode 32 MHz 2 7 V lt Vpp lt 5 5 V 16 MHz 2 4 V lt 5 5 V LS low speed main mode 8 MHz 1 8 V x Vop lt 5 5 V LV low voltage main mode 4 MHz 1 6 V lt Voo lt 5 5 V Caution Select the TTL input buffer for the RxDq pin and the N ch open drain output tolerance When 20 to 52 products EVpp tolerance When 64 to 128 pin products mode for the TxDq by using port input mode register g PIMg and port output mode register g POMg For and Vit see the DC characteristics with TTL input buffer selected Remarks 1 Vo V Communication line voltage 2 q UART number q 0 to 3 g PIM and POM number g 0 1 8 14 3 fuck Serial array unit operation clock frequency Operation clock to be set by the CKSmn bit of serial mode register mn SMRmn m Unit number n Channel number mn 00 to 03 10 to 13 4 UART2 cannot communicate at different potential when bit 1 PIOR1 of peripheral I O redirection register PIOR is 1 R01DS0131EJ0310 Rev 3 10 QE NEC S AS Page 91 of 194 Nov 15 2013 RL78 G13 2 ELECTRICAL SPECIFICATIONS A D Ta 4

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