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Performance Technologies CPC358 Manual

1. K36 39 42 46 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com y swi oy D Oo o S Bb dh o 5 SER ES HG 0000000009 QODODQ000D000O ib y son E E R jo 1000 mum lolo E E E oo 25 E a a PT CPC358 a a a oo See page 37 EEEE ome O y 0000000 0000000000000 00 2 id 5 g oajo 0 ool for itional T009 saga zool so E 00 i additiona 6000 85 25 5o 888 99 jumper von ga Be s 2 evene B mmm 00 O EBsjojpa sq Bo Og En ci j ol z E FO O Ag RAE locations RP Kit K12 s BROET ACT e a Ba B3 L a oO L1 2 oo Ba L 0 0 59o H O B ga E dm ORO Res Tol lo 5 e B Bn HO Bo m 0202 kea B Bh Bn 696 ka RD 000000 0505 Hoa I Bee DEL kos E aa m LE 383333 m 200000 So8o gs o B4 gt OY paro 2 an BB BB 000000 050 ol z fa on E 000000 050 Kia KIS 5 S 20 Ra7 0262 RPS OO m o da E E 0000 z 8o 3 BB BA 00000 0262 HQ i
2. RXC1 TXC1 always input bidirectional N E TCSL1 0 CTXCI NI u u 9 EN RCLK1 gt P RCSL1 0 TCSL1 gt TCSL1 1 0 w w gt oA d RCSL1 1 Ay Y qh TXCH lt lt OPTCK TXCH Na 42 AA AA 4 NS i buffer changes direction EXT based on DTE DCE osc MPC8255 MPC8255 RXC1 RCLK1 A Vv Vv 9 TCSL1 0 always input RCSL1 0 lt NG x X 49 TXC4 TCSL1 TCSL1 1 RCSL1 1 N LI OPTCK Des TXC1 EXT bidirectional osc CPC358 AS DTE CPC358 AS DCE 79 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description DTE DCE Control The Linear Technology LTC2844 and LTC2846 Transceivers can be set either DTE or DCE mode in the Transceiver Mode Control Registers on a port by port basis This has an effect on the signal directions Table 4 27 traces the Port 1 signals through a V 35 DTE to DCE connection Table 4 27 V 35 DTE DCE Signal Continuity 160P026920 cable 160P046510 cable DTE Mode DCE Mode male female Direction Direction 5 hemati Schematic Function SEND seen 80 pin M 34 M 34 80 pin seen Function Name Name locally locally DTE RXD RXD1 In 1 R R 5 Out TXD1 DTE_TXD DEEP xD in 2 T T 6 Out TXDj PARAAD DTE DTR DTR1 Out 3 H H 15 In DSR1 DTE DSR DCE DSR
3. Recommended ae Bit Nam Description P aii Setting p 29 CLPD 0 CPM does not enter low power mode when the core enters low power mode 30 31 DFBRG 01 Division factor of BRGCLK relative to VCO OUT twice the CPM clock Defines the BRGCLK frequency The BRGCLK is divided from the CPM clock 01 set the divisor to 16 Slave MPC8255 Reset Configuration Note The Slave MPC8255 will always get its initial settings from the Boot PROM The IRSTCONF signal is wired to the AO signal and the Slave MPC8255 will assume the 1 configuration slave identity 51 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description The MPC8255 will read its configuration from the Boot Flash device beginning at location 0x20 The format of the boot words is listed in the MPC8260 s user manual The information read from the PROM is loaded into the Hard Reset Configuration Word Register The address for this device is located in the memory map in the MPC8260 s user manual The standard configuration supplied with the Boot Flash is shown in Table 4 10 Table 4 10 Slave MPC8255 Hard Reset Configuration Word Settings in Field Recommended Description Position Setting p 0 EARB 1 External Arbitration located in the Master MPC8255 1 EXMC 1 External Memory Controller Selected as BRO for the Flash Note
4. 7 Completion Code 8 Checksum 2 Checksum of bytes 4 7 Get Device ID This command is used to retrieve specific information about the Intelligent Device PM The Request Message for this command is formatted as in Table 7 3 IPM Device Request Commands Message Format on page 159 The Response Message for the Get Device ID command is formatted the same as in Table 7 4 IPM Device Response Message Format on page 159 for the first 7 bytes with the additional response bytes formatted as in Table 7 5 below Table 7 5 Get Device ID Response Message Byte Response Field Description 8 Device ID This field is currently unspecified 0x00 9 Device Revision Device Rev bits 3 0 Bit 7 0 device does not provide SDRs 10 Major Firmware Revision Major Firmware Rev bits 6 0 in binary format AVAIL bit 7 0 Normal Operation 11 Minor Firmware Revision Minor FW Rev in BCD format 12 IPMI Version IPMI Version 1 0 encoded 0x01 13 IPMI Device Support Supports FRU Inventory Device 0x08 14 16 Manufacturer ID Performance Technologies 1556 0x614 LSB First 17 18 Product ID This field is currently unspecified 0x0000 19 Checksum 2 Checksum of bytes 4 18 Cold Reset This command directs the Responder to perform a Cold Reset This is a complete reset of all hardware variables and interrupts to their default power up values The Self Tests will also be
5. Description 0 7 8 Common Header Contains Offsets to other Areas 8 71 64 BoadlfoArea O 72 151 80 Product Info Area The Request Message for this command is formatted exactly as Table 7 10 on page 163 with the addition of one more byte definition as per Table 7 13 below Table 7 13 Get FRU Inventory Area Request Commands Byte Request Field Description 8 Checksum 2 Checksum of bytes 4 7 164 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com FRU Inventory Device Commands netFn 0x0A 0x0B The Response Message for the Get FRU Inventory Area Info command is formatted as Table 7 11 on page 164 with the following additions as per Table 7 14 below Table 7 14 Get FRU Inventory Area Response Message Byte Response Field Description 8 FRU Inventory Area Size in bytes LSB 152 bytes 0x98 9 FRU Inventory Area Size in bytes MSB 0x00 10 Access Size 0x00 Device accessed by bytes 11 Checksum 2 Checksum of bytes 4 10 Read FRU Inventory Data This command provides the requester with a low level read of the FRU inventory data at the specified offset address with the specified byte count Note IMPB allows a maximum of only 32 byte messages total The Request Message for this command is formatted as in Table 7 10 on page 163 with the addition of several more byte definitions as per
6. FCC1 TX EN MII PA27 FCC1 RX DV MII PA26 FCC1 RX ER MII PA25 LT1 PA24 LT2 PA23 LT3 PA22 LT4 PA21 FCC1 TxD 3 MII PA20 FCC1 TxD 2 MII PA19 FCC1 TxD 1 MII PA18 FCC1 TxD 0 MII PA17 FCC1 RxD 0 MII PA16 FCC1 RxD 1 MII PA15 FCC1 RxD 2 MII PA14 FCC1 RxD 3 MII PA13 RI1 PA12 RI2 PA11 RI3 PA10 RIA PA9 PA8 PA7 MDIO PA6 MDC PAS ISOLATE MII2 PA4 ISOLATE MII1 PA3 PA2 PA1 PAO IM2S_INT Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Master MPC8255 Parallel Port Pin Assignments Master MPC8255 Port B Pin Assignments Table 8 2 defines the Master MPC8255 s Port B Pin assignments Table 8 2 Master MPC8255 Port B Pin Assignments Pin Pin Function PPARB 1 PPARB 0 PSORB 0 PSORB 1 PDIRB 1 Out PDIRB 0 In PDIRB 1 Out PDIRB 0 In Out PDIRB 1 Out PDIRB 0 In PB31 FCC2 TX ER MII PB30 FCC2 RX DV MII PB29 FCC2 TX EN MII PB28 FCC2 RX ER MII PB27 FCC2 COL MII PB26 FCC2 CRS MII PB25 FCC2 TxD 3 MII PB24 FCC2 TxD 2 MII PB23 FCC2 TxD 1 MII PB22 FCC2 TxD 0 MII PB21 FCC2 RxD 0 MII PB20 FCC2 RxD 1 MII PB19
7. MPC8260UM D Rev 0 Motorola Incorporated Motorola Literature Distribution Center P O Box 5405 Denver Colorado 80217 U S A Tel 800 441 2447 More information at http e www motorola com webapp sps site prod_summary jsp code MPC8260 amp nodeld 01M98657 CA91L8260 Tundra PowerSpan Datasheet Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Tundra Semiconductor Corp 603 March Rd Kanata Ontario K2K 2M5 Canada Tel 613 592 0714 More information at http www tundra com page cfm tree id 100008 Table 1 1 Manufacturer Part Numbers Additional Documentation Part Part Number Manufacturer MPC8255 PowerQUICC Il Communications Processor MPC8255AZUMHBB Motorola http e www motorola com CA91L8260 PowerSpan Single Port PCI Bridge PIC Microcontroller 20 MHz 4 Megabit 512 K x 8 Bit CMOS 3 0 V only Flash Memory CA91L8260 100CE PIC16F877 20 PQ AM29LV040B 90JC Tundra Semiconductor Corp 603 March Road Kanata Ontario K2K 2M5 Canada Tel 613 592 0714 Microchip Technology Inc 2355 West Chandler Blvd Chandler AZ 85224 6199 USA Tel 602 786 7200 Advanced Micro Devices One AMD Place P O Box 3453 Sunnyvale CA 94088 3453 USA Tel 408 732 2400 3 V 128 Mbit StrataFlash Memory E28F128J3A 150 Intel Corp http www intel com SODIMM Memory 128 Mbyte 100 MHz MT4LSDT1664HG 10EB1 Micron Technology
8. 126P042712 08 18 04 Modification to RS 232C tables in Pinout and Rear Transition Modules Chapter 126P042713 03 11 09 Updated format Added to jumper K5 description 126P042714 04 29 09 Updated Table 6 4 EIA 530 Connector Pin Assignments on page 132 to add cable shield description Copyright Notice Copyright 2003 2009 Performance Technologies Inc All Rights Reserved The Performance Technologies logo is a registered trademark of Performance Technologies Inc All product and brand names may be trademarks or registered trademarks of their respective owners This document is the sole property of Performance Technologies Inc Errors and Omissions Although diligent efforts are made to supply accurate technical information to the user occasionally errors and omissions occur in manuals of this type Refer to the Performance Technologies Inc web site to obtain manual revisions or current customer information http www pt com Performance Technologies Inc reserves its right to change product specifications without notice Symbol Conventions in This Manual The following symbols appear in this document EN Caution There is risk of equipment damage Follow the instructions A Warning Hazardous voltages are present To reduce the risk of electrical shock and danger to personal health follow the instructions EN Caution Electronic components on printed circuit boards are extremely sensitive to static
9. 8255 arbitration IPB DBG 1 IDBG Data Bus Grant 8255 arbitration IPB DBB IDBB Data Bus Busy 8255 arbitration PB AP 0 3 AP 0 3 Address bus parity not used PB DP 0 7 DP 0 7 Data bus parity not used IPB CI ICI Cache Inhibit not used The following itemizes the Reset operation of the CPC358 PCI ports Table 4 24 PowerSpan Reset Pins Pin Name Direction Description Comments PO RST Input Power On Reset Voltage Level Sense HEALTHY Input Board Status Power Good Asserts Signal PB RST Input Processor Bus Hard Reset PB RST DIR 0 Input HRESET generated P1 RST Input PCI 1 Bus Reset P1 RST DIR 0 Input CPCI bus generated TRST Input JTAG Reset Voltage Level Sense Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 73 Chapter 4 Functional Description PowerSpan Interrupts Table 4 25 documents the interrupt connections from the PowerSpan Table 4 25 PowerSpan Interrupt Connections Power Span Signal Master MPC8255 Signal Description or comments IINT 3 Port C bit 4 Internal general interrupt IINT 5 IPQ SRESET via PLD logic Mailbox generates SRESET to Reset control logic Fast Ethernet Controller 74 There is a pair of 10 100 Ethernet interfaces on the CPC358 They are implemented using the Master MPC8255 s FCC1 and FCC2 connected to individual PHYs and magnetics VO connections are
10. A rtisan Artisan Technology Group is your source for quality Technology Group new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment EQUIPMENT DEMOS HUNDREDS OF Instra REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED CEP ala aed Contact us 888 88 SOURCE sales artisantg com www artisantg com Performance Technologies 205 Indigo Creek Drive Rochester NY 14626 USA 585 256 0248 support pt com www pt com 2009 Performance Technologies Inc All Rights Reserved CPC358 Octal Synchronous Serial Communications Processor Hardware Manual Ai AEE PERFORMANCE TECHNOLOGIES af Document Revision History Part Number Date Explanation of changes 126P042710 08 01 03 Initial Production Release 126P042711 11 18 03 Certification Modifications
11. All indicators are on the front panel and the RTM Diagnostic Facilities The diagnostic facilities of the CPC358 support a Power On Confidence test suite POC continuous network validation through detection of faults and a set of online utilities that provide for extensive network level diagnostics 30 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Power On Confidence POC These tests are a diagnostic suite run whenever the CPC358 is booted POC tests are enabled by default but the CPC358 also provides a method to disable them The POC test suite includes only those diagnostic tests that do not affect externally attached devices The CPC358 becomes available to the user within 30 seconds of a power on or reset Model Designations The CPC358 is available in the following model configurations Table 2 1 CPC358 Model Numbers Model Designations Product Number Description PT CPC358 11606 Rear I O no 80 pin connectors PT CPC358 11607 Front I O two 80 pin connectors on front panel PT RTM358 11608 Rear transition module rear I O two 80 pin connectors on rear panel PT RTM358 11609 Rear transition module front I O no 80 pin connectors The following accessory cables are available for the CPC358 Table 2 2 CPC358 Accessory Cables Product Number PT ACC334 10622 Description 4 port V 35 Hydra Style Cable DTE
12. CLK8 input PC23 PC22 PC21 SCC2 TX_CLK CLK11 input PC20 SCC2 RX CLK CLK12 input PC19 PC18 PC17 PC16 PC15 SCC1 CTS PC14 SCC1 CD PC13 SCC2 CTS PC12 SCC2 CD PC11 SCC3 CTS PC10 SCC3 CD PC9 SCC4 CTS PC8 SCC4 CD PC7 PC6 PC5 179 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 8 MPC8255 Parallel Port Pin Utilization Table 8 7 Slave MPC8255 Port C Pin Assignments Continued Pin Pin Function PPARC 1 PPARC 0 PSORC 0 PSORC 1 PDIRC 1 Out PDIRC 0In PDIRC 1 Out jede j PDIRC 1 Out PDIRC 0 In PC4 PC3 PC2 PC1 PCO 180 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Slave MPC8255 Parallel Port Pin Assignments Slave MPC8255 Port D Pin assignments Table 8 8 defines the Slave MPC8255 s Port D Pin assignments Table 8 8 Slave MPC8255 Port D Pin Assignments Pin Pin Function PPARD 1 PPARD 0 PSORD 0 PSORD 1 PDIRD 1 Out PDIRD 0 In PDIRD 1 Out PDIRD 0 In Out PDIRD 1 Out PDIRD 0 In PD31 SCC1 RXD PD30 SCC1 TXD PD29 SCC1 RTS PD28 PD27 PD26 SCC2 RTS PD25 PD24 PD23 PD22 SCC3 RTS SCC4 RXD PD21 PD20 SCC4 TXD SCC4 RTS PD19 PD18 DTR5 DTR6 PD17 PD16 DTR7 DTR8 PD15 PD14 PD13
13. Rear I O eneen eee Figure 6 2 RTM Diagrams Front I O eee Figure 7 1 CompactPCI SMB Block Diagram oen Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter ye I rmm EE pn Xy NA UA About This Guide Overview This manual describes the operation and use of the CPC358 Octal Synchronous Serial Communications Processor referred to as the CPC358 in this guide The following outline describes the focus of each chapter Chapter 2 Introduction provides a quick summary of the CPC358 features Chapter 3 Installation includes diagrams of the CPC358 descriptions of jumper functions and instructions for physical installation Chapter 4 Functional Description provides a detailed description of CPC358 architecture and functional blocks Chapter 5 Boot PROM and Forth Monitor provides information about the Forth monitor Chapter 6 Pinouts and Rear Transition Modules includes connector pinouts and descriptions and diagrams of the available RTMs Chapter 7 System Management Bus and Intelligent Platform Management describes the System Management Bus Chapter 8 MPC8255 Parallel Port Pin Utilization presents pinouts of the MPC8255 parallel ports Chapter 9 Agency Approvals provides agency approval and certification information Artisan Technology Group Quality Instrumentation Guaranteed
14. SEE ae cm Xy DAA AS Table 1 1 Manufacturer Part Numbers eee 21 Table 2 1 CPC358 Model Numbers oooccocccc ee tees 31 Table 2 2 CPC358 Accessory Gables 2 x ex aa 31 Table 3 1 JU TIBBFS o aseissa ni eee cosh breda teksermeetintitesrteerbendedanwenmsterss 38 Table 3 2 Routing Jumpers for Ethernet Port A eneen 41 Table 3 3 Routing Jumpers for Ethernet Port B eee 41 Table 3 4 Rear Transition Module Ground eee 42 Table 4 1 Preliminary Typical Board Power Consumption Estimates 44 Table 4 2 On Pin Control Sources 4224 aen e en te RR a EXE ER ERE 45 Table 4 3 Local Voltages s i utu vua ok e E branta use EGG eee re ia RE ROE LAN EE SEEK 45 Table 4 4 PQ HRESET Control Signals and Select Jumpers 46 Table 4 5 Peripheral Resets ene 48 Table 4 6 Master MPC8255 System Clock Control Register Bit Field Definitions 49 Table 4 7 Master MPC8255 Hard Reset Configuration Word Settings 49 Table 4 8 Master MPC8255 SIUMCR Register Settings neen 50 Table 4 9 Slave MPC8255 System Clock Control Register Bit Field Definitions 51 Table 4 10 Slave MPC8255 Hard Reset Configuration Word Settings 52 Table 4 11 Slave MPC8255 SIUMCR Register Settings eee eee 53 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Tables 11 Tables Table 4 12 Table 4 13 Table
15. prmi Out 4 nc nc 4 In DSR1 DCE_DTR DSR1 input buffer open DTE_TXD TXD1 Out 5 P P 1 In RXD1 DTE_RXD DCE_RXD ITxD1z Out 6 S S 2 In RXD1 DCE TXD DTE RTS RTS1 Out 7 C C 17 In CTS1 DTE CTS DCE CTS analog 8 B B 18 En Analog DCE_RTS RTS1 switch to switch to CTS1 input output buffer GND on GND on buffer open open RTS1 CTS1 wire wire DTE SCTE TXC1 Out 9 U U 19 In RXC1 DTE RXC DCE_RXC TXCIe Out 10 W W 20 In RXCT PCE_SCTE DTE_TXC TXCI1 In 11 Y Y 11 Out TXCI1 DTE TXC DCEDG Bel lin 12 AA AA 12 Out che PEERS DTE_DCD DCD1 In 13 F F 13 Out DCD1 DTE_DCD DCE DCD External in 14 J J 14 Out External DCE_DCD DCD1 input transceiver transceiver DCD1 buffer open for Ri on for RI1 on output buffer DCD1 DCD1 open wire wire DTE DSR DSR1 In 15 E E 3 Out DTR1 DTE DTR DCE DTR DCE DSR DSR1 input buffer open DTE LL LT1 on Out 16 K K 16 In LT1 on DTE LU DCE LL DSR1 DSR1 DCE LL wire wire 80 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table 4 27 V 35 DTE DCE Signal Continuity Continued General Purpose Registers 160P026920 cable 160P046510 cable DTE Mode male female DCE Mode Schematic Direction Direction Schematic Function Name seen 80 pin M 34 M 34 80 pin seen Nama Function locally locally DTE CTS CTS1 In 17 D D 7 Out RTS1 DTE RTS DCE RTS Analog 18 nc nc 8
16. 2 3 In Backplane Connection K2 1 2 In Rear Exit 2 3 In Backplane Connection K3 1 2 In Rear Exit 2 3 In Backplane Connection K4 1 2 In Rear Exit 2 3 In Backplane Connection Table 3 3 Routing Jumpers for Ethernet Port B Jumper Pin In Out Function K5 1 2 In Rear Exit 2 3 In Backplane Connection K6 1 2 In Rear Exit 2 3 In Backplane Connection K7 1 2 In Rear Exit 2 3 In Backplane Connection K8 1 2 In Rear Exit 2 3 In Backplane Connection 41 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 3 Installation The ground on the Rear Transition Module can be isolated from digital ground or connected to it by means of a jumper Table 3 4 shows the jumper settings for ground selection Table 3 4 Rear Transition Module Ground Jumper Pin In Out Function K9 1 2 In Connect chassis ground to digital ground 2 3 In Isolate chassis ground from digital ground Reset and Abort The reset and abort jumpers should be left open for normal operation and can be momentarily jumpered to issue a power on reset or abort Jumpering K29 1 to K29 2 issues a power on reset to the PowerQUICC II as defined in the MPC8255 manual and all the board logic is reset Jumpering K39 1 to K39 2 issues an abort non maskable interrupt INMI to the PowerQUICC These jumper locations can be a
17. 24 Chapter 1 About This Guide THIS WARRANTY IS IN LIEU OF ALL OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS INNO EVENT SHALL PERFORMANCE TECHNOLOGIES BE LIABLE FOR ANY INCIDENTAL OR CONSEQUENTIAL DAMAGES DUE TO BREACH OF THIS WARRANTY OR ANY OTHER OBLIGATION UNDER THIS ORDER OR CONTRACT Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter Bn AAA AAA AA lt A Wi Introduction This chapter provides an overview of the CPC358 It includes the following major topics Product Description on page 25 Features of the CPC358 on page 26 CPC358 Architecture Overview on page 27 CompactPCI Interface on page 30 Ethernet Ports on page 30 Diagnostic Facilities on page 30 Model Designations on page 31 Product Description The CPC358 is an eight channel synchronous serial l O communications processor for CompactPCl PSB based systems This provides OEMs end users and integrators with a high performance platform for use in both datacom and telecom applications Utilizing the Motorola MPC8255 PowerQUICC II processor running at 233 MHz the CPC358 can run protocols such as Frame Relay ISDN or any protocol using HDLC in Internet WAN environments In telecom applications the CPC358 will support MTP 2 on all 8 links The CPC358 like all Performance Technologies
18. 65 TXD4 A 103 P Port 4 Transmit Data 66 TXD4 B 103 S Port 4 Transmit Data 67 RTS4 105 C Port 4 Request To Send 68 GND4 102 B Port 4 Signal Ground 69 TXC4 A 113 U Port 4 Transmit Clock 70 TXC4 B 113 W Port 4 Transmit Clock 71 TXCI4 A 114 Y Port 4 Transmit Clock In 72 TXCIA B 114 AA Port 4 Transmit Clock In 73 DCD4 109 F Port 4 Data Carrier Detect 74 RI4 125 J Port 4 Ring Indicator 75 DSR4 107 E Port 4 Data Set Ready 76 LT4 K Port 4 Line Test 77 CTS4 106 D Port 4 Clear To Send 78 79 RXC4 A 115 V Port 4 Receive Clock 80 RXC4 B 115 X Port 4 Receive Clock Table 6 6 V 35 Signals and Pins DCE Pin T No Signal Name Direction Termination Description 1 TXD A 1 5 Input 100 Ohms differential V 35 Transmit Data port 1 or 5 125 Ohms to ground V 35 103 M 34 P 2 TXD B 1 5 Input 100 Ohms differential V 35 Transmit Data port 1 or 5 125 Ohms to ground V 35 103 M 34 S 3 DSR1 5 Output NA V 35 Data Set Ready port 1 or 5 V 35 107 M 34 E 5 RXD A 1 5 Output NA V 35 Receive Data port 1 or 5 V 35 104 M 34 R Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table 6 6 V 35 Signals and Pins DCE Continued Pinouts Pin No Signal Name Direction Termination Description 6 RXD B 1 5 Output NA V 35 Receive Data port 1 or 5 V 35 104 M 34 T 7 CTS1 5 Output NA V 3
19. 8000 S Federal Way PO Box 6 Boise ID 83707 0006 USA Tel 208 368 3900 SNAPHAT Battery 49 MAH M4T28 BR12SH1 ST Microelectronics 1000 E Bell Road Phoenix AZ 85022 USA Tel 602 485 6100 3 3V Software Selectable Multiprotocol LTC2844CG Linear Technology Transceiver 1630 McCarthy Blvd Milpitas CA 95035 7417 USA Tel 408 432 1900 3 3V Software Selectable Multiprotocol LTC2846CG Linear Technology Transceiver with Termination 1630 McCarthy Blvd Milpitas CA 95035 7417 USA Tel 408 432 1900 RS 232 Transmitter Receiver ICL3221ECV Intersil Corp 7585 Irvine Center Drive Suite 100 Irvine CA 92618 USA Tel 949 341 7000 21 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 1 About This Guide Text Conventions Conventions in This Guide describes the text conventions that are used in this guide Conventions in This Guide Convention Used For Monospace Monospace font represents sample code font Bold font Bold font represents paths file names UNIX commands user input Italic font Italic font represents notes that supply useful advice supplemental information referenced documents Customer Support and Services 22 Performance Technologies offers a variety of standard and custom support packages to ensure customers have access to the critical resources that they need to protect a
20. Clock drive to the module is provided from the same low skew clock driver that provides 66 MHz to the Master MPC8255 The clock enable signals CKEO and CKE1 are permanently enabled thus the SELF REFRESH command and operation are unavailable The Master MPC8255 can be programmed to provide refresh as needed The 64 bit data bus eight data read write mask signals and the three command signals WE CAS and RAS and the two chip selects SO and S1 are provided to the module directly from the Master MPC8255 The Master MPC8255 will automatically assert SO then S1 during refresh cycles Multiplexed row column address bits MAO through MA11 and bank select signals BAO and BA1 are driven to the module from PSM549 see Figure 4 3 External Master SDRAM Configuration on page 62 External Master SDRAM Configuration The PSM549 PLD creates these from the 60x bus address and bank select bits that have been latched with the processors ALE signal and multiplexed with the processors SDAMUX signal Burst address bits BADDR27 and BADDR28 are utilized directly to provide the least significant bits to the SODIMM during column address presentation The least significant three address lines 29 31 are unused due to the 8 byte wide data path The SODIMM module uses BADDR27 and BADDR28 to select one of four sequential locations as the first to be burst Bursts occur up toa maximum of four transfers The remaining three locations are addressed sequentially
21. Guaranteed 888 88 SOURCE www artisantg com Chapter 7 System Management Bus and Intelligent Platform Management The Response Message for the Set Card Power State command is formatted as Table 7 20 on page 167 with the following additions outlined in Table 7 28 below Table 7 28 Set Card Power State Response Message Byte Response Field Description 8 Checksum 2 Checksum of bytes 4 7 Get Card Power State 170 This OEM command returns to the Requester the Card Power and Control signals The CONTROLLER POWER and HOT SWAP LED are encoded in a single byte and returned to the Requester in the Response Data The Request Message for this command is formatted as in Table 7 19 on page 167 with the addition of one more byte definition as per Table 7 29 below Table 7 29 Get Card Power State Request Message Byte Request Field Description 7 Checksum 2 Checksum of bytes 4 6 The Response Message for the Set Card Power State command is formatted as Table 7 22 on page 168 with the following additions outlined in Table 7 30 below Table 7 30 Get Card Power State Response Message Byte Response Field Description 8 Card Power State Byte As per Table 7 26 on page 169 9 Checksum 2 Checksum of bytes 4 7 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter A AAN AAA AAA A d IA MPC8255
22. after a mod 4 operation is applied to BADDR27 and BADDR28 SDA10 passes through PSM549 and always drives MA10 on the SODIMM During the activate command this pin provides the row address for A10 During a PRECHARGE command this pin selects PRECHARGE all banks PSDA10 1 or PRECHARGE SELECTED BANK PSDA10 0 using BANKSEL 1 2 Four banks are supported and BANKSEL O is unused During READ and WRITE commands this pin selects AUTO PRECHARGE PSDA10 1 or no AUTO PRECHARGE PSDA10 0 Address bit ordering conventions are opposite between the 60x bus and the SODIMM A0 is most significant bit and the SODIMM AO is least significant bit these are resolved within PSM549 External Master Support When the Master MPC8255 is placed in 60x compatible mode external masters can access the SODIMM SDRAM as shown in Figure 4 3 on page 62 External masters will not multiplex row and column addresses for the SDRAM Therefore an SODIMM SDRAM interface PSM549 has been located between the 60x address bus and SODIMM address bus 60x addresses are latched with ALE at the start of each memory cycle The Master MPC8255 SDAMUX signal is used to multiplex address bits during row and column address presentation to the SDRAM The Master MPC8255 monitors the 60x address bus and asserts ALE SDAMUX BADDR and SDA10 appropriately for external masters 61 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com C
23. board by asserting its CARD RST signal The logic continues to issue PQ_HRESET as long as CARD RST is asserted As long as the jumper is in the logic drives PQ HRESET in response to the CARD RST signal no matter what the other jumper options are set to If K1 1 2 is open the ICARD_RST signal is ignored by the PLD Logic IP1 RST This signal is generated by the CompactPCI bus and is the CompactPCI reset The signal is buffered and fed to the PLD logic and the CompactPCI side of the Tundra chip as IP1 RST IN The signal always drives a PQ_HRESET unless the CT BMASTER signal is active controlled by jumper K4 1 2 If ICT BMASTER is active it means that there is no CompactPCI system master and that the CT bus has control of the subsystem The PQ HRESET signal is generated when the falling edge of P1 RST IN is detected and held low for approximately 11 50 ns clock cycles The PQ HRESET is then negated and not reasserted until the P1 RST IN has been negated for at least 50ns ICT RESET Input The ICT RESET signal is used to generate the PQ_HRESET only when the CT bus not part of CT BMASTER signal is active The ICT BMASTER indicates to the logic that there is no standard product CompactPCI bus in the system and that the CT is the controlling element for the board When Jumper K2 1 2 is in place the ICT BMASTER signal is driven true If the jumper is left open the reception of CT RESET is ignored by the logic ITOD RST O
24. continuous metal barrier around the signal wires that helps to contain the common mode noise that radiates from the cable Additionally the cable has a shield layer to provide this barrier The cable also has a trace wire that touches the shield and attaches to pin 1 of each 25 pin D Sub connector The trace wire is not assigned to a pin at the interface of the PCB 80 pin AMP connector V 35 Supported Signals This configuration supports the V 35 standard in a DTE or DCE format The V 35 Standard is also supported through a Hydra cabling option The signals supported and their positions in both of the 80 pin connectors are shown in Table 6 5 DTE and Table 6 6 on page 138 DCE Note Some of the 80 pins in the connector may not be included in the table For each electrical standard the pins that are not included in the table for that standard MUST BE LEFT UNCONNECTED 135 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 6 Pinouts and Rear Transition Modules Ports 1 4 are carried on J6 on the front panel and J1 on the Rear Transition Module Ports 5 8 are carried on J7 on the front panel and J2 on the Rear Transition Module Table 6 5 V 35 Connector Pin Assignments 80 Pin Amp Signal V 35 l M 34 Description Pin No Name Mnemonic Pin No 1 RXD1 A 104 R Port 1 Receive Data 2 RXD
25. n number of bytes to copy The boot flash is programmed with size bytes from address src The destis given as an explicit address in the boot flash If successful flag will be returned equal to zero Otherwise flag will be a flash error code See Flash Error Codes below Boot Erase Vector Oxfff0300c Arguments mailbox 1 sector Returns mailbox 1 flag Erase a sector of boot flash specified by sector Valid sectors are 5 6 and 7 If sector is 1 erase all three sectors If successful flag will be returned equal to zero Otherwise flag will be a flash error code See Flash Error Codes below Hardware Revision Vector Oxfff03004 Software Revision Vector Oxfff03008 Returns mailbox 1 string A null terminated string identifying the software revision of the boot PROM is returned in consecutive bytes starting with the most significant byte of mailbox 1 Monitor Update Vector Oxfff03018 Arguments mailbox 1 src address from which to begin the copy A new Boot PROM image is programmed into sectors 0 4 of the boot FLASH starting from address src Upon completion the monitor restarts 116 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Flash Error Codes Table 5 2 Flash Error Codes Resources Used by the Monitor Mnemonic Value Description E VOLTAGE RANGE 0x8000000 The StrataFLASH reported a voltage range error wh
26. 0x00 2 rsSA Responder s Slave Address 3 netFn rsLUN NetFn 0x06 rsLUN 0x00 4 Checksum 1 Connection Header Checksum 5 rqsA Requester s Slave Address 6 rqSeq rqLUN Sequence number and Requesters LUN 7 Command 0x01 Get Device ID 8 Checksum 2 Checksum of bytes 5 6 and 7 FRU Inventory Device Commands netFn 0x0A OxOB This section provides detailed descriptions of the FRU Inventory Device Commands supported by the PM These commands use Network Function Codes netFn for Storage Requests and Responses 0x0A and 0x0B The Board Info Area and the Product Info Area can be written by the IPMI Write FRU Inventory Data command Common FRU Inventory Device Commands Common Request Message formats are outlined in the Table 7 10 Take note of the command byte 6 which specifies the variable for each specific function All common Response Message functions are defined in Table 7 11 on page 164 There are slight differences among various commands Each command that differs from Table 7 10 or Table 7 11 is defined in other tables under the description of that particular command Table 7 10 FRU Inventory Device Request Formats Byte Request Field Description 1 rsSA Responder s Slave Address 2 netFn rsLUN NetFn 0x0A rsLUN 0x00 3 Checksum 1 Connection Header Checksum 4 rqsA Requester s Slave Address 5 rqSeq rqLUN Sequence number and Requester s LUN 6 Command 0x10 Get FRU I
27. 1 2 the bit will indicate a 0 This setting indicates to the CPC358 that the CT Bus is the master bus in the cardfile and that CT bus resets will produce hard resets to the CPC358 The CompactPCI reset signal will be ignored by the local reset control logic however the CompactPCI reset will still reset the PCI 1 logic in the PowerSpan part When the K4 jumper is connected 2 3 the bit indicates a 1 This setting means that there is a CompactPCI bus in the cardfile and it has control of the reset action CT bus not part of standard product 5 smben This bit reflects that state of the K1 jumper When the K1 jumper is connected 1 2 the bit will indicate a 1 This indicates that the System Management Bus controller is installed and active When the K1 jumper is connected 2 3 the bit indicates a 0 This setting means that the SMB is inactive 6 RESV Always 0 7 factdflt This bit reflects that state of the K5 jumper When the K5 jumper is connected 1 2 the bit will indicate a 0 This indicates the user wants the PT default software configuration loaded into all devices at boot up When the K5 jumper is connected 2 3 the bit indicates a 1 This setting means that the customer settings will be loaded at boot up This jumper is used internally at Performance Technologies to indicate burn in mode 86 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General Purpose Regi
28. 111 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 5 Boot PROM and Forth Monitor Soft Reset The soft reset mechanism is provided for a CompactPCI host to issue the MPC8255 a soft reset The PowerSpan s INT5 is connected to the MPC8255 s soft reset so that exercising any of the PowerSpan s resources mapped to its INT5 will assert the MPC8255 soft reset Dovetailing with the host PCI communication scheme it is sensible to use MBOXO mapped to INT5 in this manner int soft reset struct PowerSpan p p gt IDR 0x20000000 IRQ5 an output p gt IMR_MBOX OxE map MBOXO to IRQ5 p gt IERO 1 enable MBOXO interrupt p gt MBOXO 0 drive MBOXO interrupt p gt ISRO 1 clear MBOXO interrupt status P gt IERO amp 1 disable interrupt poll mailbox0 to see if reset completed if poll for completion p 3000 return FALSE return TRUE Forth Console 112 The Forth console is provided by John Sadler s ficl Forth Inspired Command Language It is a Forth which implements the ANS Forth CORE word set part of the CORE EXT word set SEARCH and SEARCH EXT TOOLS and part of TOOLS EXT LOCAL and LOCAL EXT EXCEPTION MEMORY and various extras Parts of the BLOCK and FACILITY word sets are added to support the editor introduced by Leo Brodie FACT Jumper When the FACT jumper is installed block 1
29. 3 Port 3 Receive Data 42 16 43 DTR3 CD 20 Port 3 Data Terminal Ready 44 23 45 TXD3 BA 2 Port 3 Transmit Data 46 14 47 RTS3 CA 4 Port 3 Request To Send 48 19 49 TXC3 DA 24 Port 3 Transmit Clock 50 11 51 TXCI3 DB 15 Port 3 Transmit Clock In 52 12 53 DCD3 CF 8 Port 3 Data Carrier Detect 54 10 55 DSR3 CC 6 Port 3 Data Set Ready 56 22 57 CTS3 CB 5 Port 3 Clear To Send 58 GND3 AB 7 Port 3 Signal Ground 59 RXC3 DD 17 Port 3 Receive Clock 60 9 61 RXD4 BB 3 Port 4 Receive Data 62 16 63 DTR4 CD 20 Port 4 Data Terminal Ready 64 23 128 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Pinouts Table 6 2 RS 232C Connector Pin Assignments Continued RS 232C UE M E MD Pin No 65 TXD4 BA 2 Port 4 Transmit Data 66 14 67 RTS4 CA 4 Port 4 Request To Send 68 19 69 TXC4 DA 24 Port 4 Transmit Clock 70 11 71 TXCI4 DB 15 Port 4 Transmit Clock In 72 12 73 DCD4 CF 8 Port 4 Data Carrier Detect 74 10 75 DSR4 CC 6 Port 4 Data Set Ready 76 22 77 CTS4 CB 5 Port 4 Clear To Send 78 GND4 AB YA Port 4 Signal Ground 79 RXC4 DD 17 Port 4 Receive Clock 80 9 RS 449 422 Supported Signals This configuration supports the RS 449 422 standard in a DTE format The EIA 530 Standard is also supported through a Hydra cabling option The signals supported and their positions in both of the 80 pin connectors are shown
30. 4 14 Table 4 15 Table 4 16 Table 4 17 Table 4 18 Table 4 19 Table 4 20 Table 4 21 Table 4 22 Table 4 23 Table 4 24 Table 4 25 Table 4 26 Table 4 27 Table 4 28 Table 4 29 Table 4 30 Table 4 31 Table 4 32 Table 4 33 Table 4 34 Table 4 35 Table 4 36 Table 4 37 Master MPC8255 Chip Select Assignments 0000 e eee eee eee eee 54 Slave MPC8255 Chip Select Assignments 0000 cee eee eee 54 Master MPC8255 Interrupt Sources nnee 55 CSO Base Register Settings cece tee 64 CS0 Option Register Settings sese veenandnsnndenne ARA 64 CS3 Base Register Settings nananana distri ridad t ada dde 66 CS3 Option Register Settings stos beropidin dv rior 67 CS8 Base Register SelindS espurisi aiidediaditeltrc rebasa 68 CS8 Option Register Settings ars sana 96RIERBDeRRS aia 68 CS2 Base Register Settings paaa oi604406 dica darte SAGALA desta DADA 70 CS2 Option Register Setllrigs suas vr xa GRE boat ee EK x NANG KKK AS Ra 71 Signal Variations From Between PowerSpan and the Master MPC8255 73 PowerSpan Reset PIAS paanan DAG dara AG Spy d dodo e M CE RC ER RR 73 PowerSpan Interrupt Connections oee eee 74 CS8952 Configuration PINS s ua dec tret LEER aed RR Rd eed d d 75 V 35 DTE 7 DCE Signal Continuity aaa 3233 hee a DIOE c n RC RC RE war 80 CS4 Base Register Settings eene 82 CS4 Option Register Settings lll
31. 888 88 SOURCE www artisantg com Chapter 1 About This Guide Additional Documentation This manual is not intended to be a stand alone document It is necessary to have a complete understanding of all the features and function of the hardware to adequately develop software for this product Consult the following list of additional documentation for sources of further information The most current documentation to support the additional components that you purchased from Performance Technologies is available at http www pt com under the product you are inquiring about 20 PICMG 2 16 Revision 1 0 CompactPCI Packet Switching Backplane Specification Sept 5 2001 PICMG 2 0 Revision 3 0 CompactPCI Core Specification Oct 1 1999 PICMG 2 1 Revision 2 0 Hot Swap Specification Jan 17 2001 PICMG 2 9 Revision 1 0 System Management Specification Feb 2 2000 PCI Industrial Computer Manufacturer s Group More information at http www picmg org IPMI Platform Management FRU Information Storage Definition V1 0 Document Revision 1 1 Sept 27 1999 Intel Hewlett Packard NEC Dell Computer More information at http developer intel com design servers ipmi spec htm PowerQUICC II Users Manual MPC8260UM D Rev 0 The CPC358 utilizes the Motorola MPC8255 which supports a subset of the MPC8260 s features The MPC8255 does not have its own manual please refer to the MPC8260 User s Manual for information regarding the MPC8255
32. Bit Fields 0 eee 88 P1 Reset Control Register Bit Field Definitions AA 88 Hot Swap Status and Control Register Bit Fields AA 88 Hot Swap Status and Control Register Bit Field Definitions 89 Board ID Register 1 Bit Fields ass eee Rm eee eee 90 Board ID Register 1 Bit Field Definitions ooo ooooooooo 90 Board ID Register 2 Bit Fields ssir es DARAAN rwn 90 Board ID Register 2 Bit Field Definitions o o ooooooooooooo 90 Board Status LED Control Register Bit Fields oooocoooocoooomoo 91 Board Status LED Control Register Bit Field Definitions 91 Compact PCI Geographic Address Register Bit Fields 92 Compact PCI Geographic Address Register Bit Field Definitions 92 CT Bus Shelf Address Register Bit Fields a 92 CT Bus Shelf Address Register Bit Field Definitions o o o 92 Transceiver Mode Control Selection Bits eee 95 Transceiver 1 2 5 6 Mode Control Register Bit Fields 95 Transceiver 1 2 5 6 Mode Control Register Bit Field Definitions 95 Transceiver 3 4 7 8 Mode Control Register Bit Fields 96 Transceiver 3 4 7 8 Mode Control Register Bit Field Definitions 96 Receive Clock Steering Control Register Bit Fields 97 Receiv
33. Bus and Intelligent Platform Management The Request Message for this command is formatted as in Table 7 10 on page 163 with the addition of several more byte definitions as per Table 7 17 below Table 7 17 Write FRU Inventory Data Request Commands Byte Request Field Description 8 FRU Inventory Offset Address LSB LS Byte of Offset from the beginning of the FRU Inventory Area to Start Reading Data 9 FRU Inventory Offset Address MSB MS Byte of Offset from the beginning of the FRU Inventory Area to Start Reading Data 10toN Data to Write Must be at least 1 but no more than 22 bytes N 1 Checksum 2 Checksum of bytes 4 N Note N in Table 7 16 refers to a byte count of between 10 and 31 The Response Message for the Write FRU Inventory Data command is formatted as in Table 7 11 on page 164 with the addition of several more byte definitions Table 7 18 Write FRU Inventory Data Response Message Byte Response Field Description 8 Count Returned Number of bytes written 9 Checksum 2 Checksum of bytes 4 8 OEM Vendor Specific Commands netFn 0x30 0x31 This section identifies the IPMI commands that are Vendor Specific NetFn 0x30 0x3f There are currently four vendor specific commands supported by this PM They are Diagnostic Echo Get Card Power Status Get Card Power State and Set Card Power State The Diagnostic Echo command Command Co
34. CompactPCI PSB telecom products supports Hot Swap and rear I O The heart of the CPC358 is a Motorola MPC8255 PowerQUICC II communications microprocessor running at 233 MHz The PQII includes an embedded communications processor module CPM that utilizes a 32 bit RISC controller residing on a separate local bus The CPM has an instruction set optimized for communications to off load the PowerPC core CPU from the task of handling lower level communications and DMA activity This architecture provides an ideal platform for running the Performance Technologies suite of protocol software 25 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 2 Introduction 26 The CPC358 is designed to operate in either CompactPCI systems as a peripheral or in CompactPCI PSB systems as a standalone The Tundra CA91L8260 PowerSpan that provides the PCI interface can be disabled using jumpers Features of the CPC358 Master MPC8255 PowerPC with 233 MHz microprocessor core Slave MPC8255 Power PC device with PPC core disabled CPM fully enabled PPC 66 MHz 60x Bus 128 Mbyte SDRAM 512Kb user programmable Boot Flash PROM 32Mb of Application Flash 2 devices 256K High Speed Static RAM for Communication Buffers Eight Synchronous Serial ports using 4 SCCs from each MPC8255 The serial ports have the following electrical features programmed on a port by port basis RS 232E DTE or DCE
35. Field Definitions Bit Name Description 0 RESV Always 0 1 ygoff4 A 1 in this bit position turns off the Port 4 8 Status LED This bit setting will turn off the LED ygoff8 regardless of the status of the yel4 yel8 bit A O in this bit position will enable the yel4 yel8 bit to turn on the LED and show one of the two LED colors available to the LED 2 RESV Always 0 3 ygoff3 A 1 in this bit position turns off the Port 3 7 Status LED This bit setting will turn off the LED ygoff7 regardless of the status of the yel3 yel7 bit A 0 in this bit position will enable the yel3 yel7 bit to turn on the LED and show one of the two LED colors available to the LED 4 RESV Always 0 5 yel4 With the ygoff4 ygoff8 bit set to a O a 1 in this bit position will set the Port 4 8 Status LED to yel8 yellow and a 0 in this bit position will set the LED to green 6 RESV Always 0 7 yel3 With the ygoff3 ygoff7 bit set to a 0 a 1 in this bit position will set the Port 3 7 Status LED to yel7 yellow and a 0 in this bit position will set the LED to green Transceiver Shutdown Control Register The Transceiver Shutdown Control Register allows software control of the Transceiver Boost Switching Regulator Individual ports can be powered down to reduce power consumption and EMI After a IPQ_SRESET all ports are powered down Software must enable the regulator before attempting to use a port Table 4 70 Tr
36. GND on DCE CTS CTS1 input switch to RTS1 RTS1 buffer open GND on wire output buffer CTS1 open wire DTE RXC RXC1 In 19 V V 9 Out TXC1 DTE_SCTE DCE SCTE RXC1 In 20 X X 10 Out TXC1 DCE_RXC General Purpose Registers The General Purpose Registers control and make available the status of the unique functions of the CPC358 that are not provided by the various peripheral devices on the board All of the registers are 8 bit and are located on the buffered data bus See Figure 4 11 Figure 4 11 General Purpose Registers Block Diagram BUF_AD 0 7 CS REG REG WR IBUF RD Processor Control and Status Signals PSM553 LED PHY amp Status Control GA SA PSM554 Ports 1 4 Control and Status Signals PSM554 groupsel 1 4 Ports 5 8 Control and Status Signals 81 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description The necessary control and timing for each cycle comes initially from the 60x bus and the BR4 and OR4 GPCM registers Table 4 28 and Table 4 29 reflect the required settings for this space Table 4 28 CS4 Base Register Settings Field Recommended Description Setting PS 01 8 bit DECC 00 Data Errors checking disabled WP 0 R
37. JEDEC single power supply Flash standard Commands are written to the command register using standard microprocessor write timings Register contents serve as input to an internal state machine that controls the erase and programming circuitry Write cycles also internally latch addresses and data needed for the programming and erase operations Device programming occurs by executing the program command sequence This initiates the Embedded Program algorithm an internal algorithm that automatically times the program pulse widths and verifies proper cell margin Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Application Flash Memory Device erasure occurs by executing the erase command sequence This initiates the Embedded Erase algorithm an internal algorithm that automatically pre programs the array if it is not already programmed before executing the erase operation During erase the device automatically times the erase pulse widths and verifies proper cell margin The host system can detect whether a program or erase operation is complete by reading the DQ7 Data Polling and DQ6 toggle status bits After a program or erase cycle has been completed the device is ready to read array data or accept another command The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors Device hardware data protect
38. K32 1 2 In M66EN signal is grounded forcing operation from 25 MHz to 33 MHz 2 3 In M66EN signal input from backplane When high it configures for operation above 33 MHz to a maximum of 66 MHz When low operation is from 25 MHz to 33 MHz K33 1 2 In DSR5 signal 2 3 In LT5 signal V 35 only K34 1 2 In DCD5 signal 2 3 In RI5 signal V 35 only K35 1 2 In V 35 DCE RI7 is output 2 3 Int V 35 DTE RI7 is input K36 1 2 In Connects PCI Bus signal BD_SEL to System Management Bus SMB micro controller Remove for in circuit programming of the micro controller Out Remove for in circuit programming of the micro controller K37 1 2 In Factory set It connects MPC8255 processor hardware reset to the System Management Bus SMB micro controller Out Remove for in circuit programming of the micro controller K38 1 2 In Factory set Install on systems with a PCI Bus PCI Bus clock is used by Tundra PowerSpan 2 3 In Install on busless systems Connects on board clock to Tundra PowerSpan K39 1 2 In Manually forces Non Maskable Interrupt to Master MPC8255 PowerQUICC II Out Factory set K40 1 2 In DSR7 signal 2 3 In LT7 signal V 35 only K41 1 2 In DCD7 signal 2 3 In RI7 signal V 35 only K42 1 2 In Enables CT bus signal CT_EN as Card Power signal Out Allows another power on control signal source K43 1 2 In Enables PCI Backplane signal BD_SEL as Card Power signal Out Allows another power on control signal source K44 1 2
39. PM Enable Switch 0 indicates SMB is Disabled 1 indicates that SMB is Enabled 0 POWER_GOOD POWER_GOOD output from 0 indicates POWER_GOOD is FALSE Hot Swap Controller 1 indicates that POWER_GOOD is TRUE The Request Message for this command is formatted as in Table 7 19 on page 167 with the addition of one or more byte definitions as per Table 7 24 Table 7 24 Get Card Power Status Request Message Byte Request Field Description 7 Checksum 2 Checksum of bytes 4 6 168 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com OEM Vendor Specific Commands netFn 0x30 0x31 The Response Message for the Diagnostic Echo command is formatted as in Table 7 22 on page 168 with the following additions outlined in Table 7 25 below Table 7 25 Get Card Power Status Response Message Byte Response Field Description 8 Card Power Status Byte As per Table 7 23 9 Checksum 2 Checksum of bytes 4 8 Set Card Power State This OEM command allows the Requester to set Card Power and Control signals The Requester can control the state of the CONTROLLER POWER and HOT SWAP LED signals by setting or clearing the corresponding bits in the Request Data field Table 7 26 Bit Assignments for Card Power State Byte Bit Signal Description Value 5 CONTROLLER POWER Controls the on board power controller O turns off Controller Power
40. SFFACFOOC SFFACFOOC SOC SFFA33004 SFFACF004 SFFACF004 SFFACF004 S10 SFFAFF005 SEFFFFF000 SFFFFFO000 SFFFFF000 14 SFFFFF000 SFFFFF000 SFFFFFO000 SFFFFFO000 18 00F33005 SFFFFFOOO SFFFFFOOO SFFFFFOOO SIC SFFFFF000 SEFFFFF000 SEFFFFF000 SFFFFFO000 20 00F3300C SOOFCFOOC SOOFCFOOC SOOFCFOOC 24 00F33004 00FCF004 00FCF004 00FCF005 28 SFFFFF000 SEFFFFF000 SFFFFFO000 SFFFFF000 2C SFFFFF000 SEFFFFF000 SFFFFFO000 SFFFFF000 30 SFFFFF005 SFFFFFO000 SFFFFF000 SFFFFF000 34 SFFFFFO000 SFFFFFO000 SFFFFF000 SFFFFFO000 38 SFFFFF000 SFFFFFO000 SFFFFF000 SFFFFFO000 3C SFFFFF005 SFFFFFO000 SFFFFFO000 SFFFFF000 CompactPCI Interface A Tundra PowerSpan PCI to 60x bus hot swap friendly interface chip supplies the CompactPCI interface The Tundra PowerSpan part number is CA91L8260 PowerSpan Signal Connections and Hardware Configuration The bus interface signals between PowerSpan and the 60x bus are directly connected External pull up resistors are connected to all bus control signals to ensure that they are held in an inactive state when not accessed Additionally pull up resistors are provided on the address and data bus interfaces to minimize current consumption of the buffers when tri stated Refer to the schematic documents for connection information No provision has been made for parity checking on either the address or data presented to the Tundra This choice was made due to the multiplexed nature of the 60x bus pins being use
41. Slave IPQ QACK Quiescent State Acknowledge not supported Slave PQ_TDI JTAG Test Data In signal Slave IPQ TRST JTAG Reset and Tri state signal Slave IPQ QREQ Quiescent State Request V3V Slave PQ_TCK JTAG Test Clock l Nf O of A j N Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com No Connection 143 Chapter 6 Pinouts and Rear Transition Modules Table 6 9 Slave JTAG Pinout Continued 9 Slave PQ_TMS JTAG Test Mode Select 10 No Connection 11 Slave IPQ SRESET MPC8255 Soft Reset 12 Ground 13 IPQ HRESET MPC8255 Hard Reset shared with Master 14 No Connection 15 Slave ICHKSTPO Checkstop output Not supported 16 Ground All of the control signals are pulled to V3V with a 10K resistor to prevent false actuation when no JTAG controller is connected Mictor Pinout The Mictor connector is typically used to connect a logic analyzer or similar type of device to the CPC358 board for use as engineering debug and diagnostic aids It is not installed on shippable standard product The pinout follows Table 6 10 J9 Mictor Pinout 60X Bus Address Pin Number Signal Name Signal Name Pin Number 1 NC NC 2 3 NC NC 4 5 IPQ TS CLK MICTOR 66 MHz 6 7 PQ Ao PQ A16 8 9 PQ A1 PQ A17 10 11 PQ A2 PQ A18 12 13 PQ A3 PQ A19 14 15 PQ A4 PQ A20 16 17 PQ A5 PQ A21 18 19 PQ A
42. Swap Status and Control Register Bit Field Definitions Bits Name Description 0 pi m66en Reads 1 when the PCI bus clock is 66 MHz Reads 0 when the PCI bus clock is 33 MHz 1 p1 pcixcap Reads 1 when the PCI bus clock is PCI X capable Reads 0 for non PCI X bus Note this bit added for future compatibility with PCI X It is not defined by the spec at this time 2 RESV Always 0 3 pcipresent Reads 1 when PCI bus is present card plugged in chassis with pin J1 B6 grounded or board configured for stand alone operation jumper K38 2 3 Reads 0 otherwise 4 esclosed Reads the state of the CPCI handle ejector switch 1 means closed and 0 means open This signal is direct from the switch and must be debounced in software 5 ledbit MPC8255 control of blue hot swap LED Writing a 1 turns it on and writing a 0 turns it off This bit defaults to 1 on and must be turned off by software Note that the LED is controlled by many sources including the PowerSpan and the System Management Bus PIC microcontroller in a wired OR configuration All sources must turn the LED off for it to actually extinguish 6 RESV Always 0 7 pcibusifen Reads jumper K6 This signal is used by PLD PSM552 to control the reset of the PowerSpan With K6 connected 1 2 this bit reads 1 meaning for PSM552 to enable the PCI interface for normal operation and let the PCI bus reset go through With K6 connected 2 3 the bit reads 0 in
43. Table 7 15 below Table 7 15 Read FRU Inventory Data Request Commands Byte Request Field Description 8 FRU Inventory Offset Address LSB LS Byte of Offset from the beginning of the FRU Inventory Area to Start Reading Data 9 FRU Inventory Offset Address MSB MS Byte of Offset from the beginning of the FRU Inventory Area to Start Reading Data 10 Count to Read Must be at least 1 but no more than 23 bytes 11 Checksum 2 Checksum of bytes 4 10 The Response Message for the Read FRU Inventory Data command is formatted as in Table 7 11 on page 164 with the addition of several more byte definitions as per Table 7 16 below Table 7 16 Read FRU Inventory Data Response Message Byte Response Field Description 8 Count Returned Number of bytes returned in the response data 9toN Requested Data At least 1 byte but no more than 23 bytes N 1 Checksum 2 Checksum of bytes 4 to N Note N in Table 7 16 refers to a byte count between 9 and 31 Write FRU Inventory Data This command provides the requester with a low level write of the FRU inventory data at the specified offset address It allows IPMI write access to any non write protected area in the PM FRU Inventory Area Note IPMB allows a maximum of 32 byte messages total 165 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 7 System Management
44. The PM stores the ACPI Power State s from this command and uses the values in the Response to a Get ACPI Power State Command 161 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 7 System Management Bus and Intelligent Platform Management The Request Message for this command is formatted exactly the same as Table 7 3 on page 159 for the first 6 bytes The additional response bytes are formatted as in Table 7 7 below Table 7 7 Set ACPI Power State Request Message Byte Request Field Description 7 ACPI System Power State See IPMI Specifications for this command 8 ACPI Device Power State See IPMI Specifications for this command 9 Checksum 2 Checksum of bytes 4 8 The Response Message for the Set ACPI Power State command is formatted as in Table 7 4 on page 159 Get ACPI Power State This command is issued by system software to retrieve the current ACPI Advanced Configuration and Power Interface power state from the controller PM The PM Responds with the values set by Set ACPI Power State command If the Set ACPI Power State command was not previously received the PM will respond with Unknown Ox2A in the Response data for both System and Device ACPI Power State fields The Request Message for this command is formatted as in Table 7 3 on page 159 The Response Message for the Get ACPI Power State command is formatt
45. The Slave device should never have to use this feature with the core disabled but it is defined to prevent inadvertent problems CDIS 0 Slave MPC8255 core is enabled EBM 1 External Bus Mode is 60x compatible bus mode 4 5 BPS 00 Boot port size is 64 bit Note The Slave device should never have to use this feature with the core disabled but it is defined to prevent inadvertent problems 6 CIP 0 Exceptions are vectored to Physical address 0x000n nnnn Note The Slave device should never have to use this feature with the core disabled but it is defined to prevent inadvertent problems ISPS 0 Internal Space port size is set to 64 bit 8 9 L2CPC 10 Bus address pins selected for layer 2 cache pin configuration BADDR Pins selected 10 11 DPPC 11 No data bus parity External Bus Grant pins for second and third devices selected and IRQ6 and IRQ7 selected 12 RSVD 0 Reserved must be set to 0 13 15 ISB 101 Base address of the Internal Memory space is OxXFOFO 0000 16 BMS 1 Boot memory space 0x0000 0000 to 0x01FF_FFFF Note The Slave device should never have to use this feature with the core disabled but it is defined to prevent inadvertent problems 17 BBD 0 Address Bus Busy and Data Bus Busy selected on multifunction pins 18 19 MMR 00 MMR Register initial value is no masking on Bus Request lines Note The Slave device should never have to use this feature with the core disabled but it is defined to prevent inadvertent problems 20
46. avoid draining the battery do not place SNAPHAT pins in a conductive foam For more information see Battery on page 29 183 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 9 Agency Approvals Certifications The CPC358 is certified for the following standards and safety certifications If a certification is not listed below the CPC358 may still comply Contact Performance Technologies for current product certifications and availability FCC Notice This device complies with Part 15 of the FCC rules Operation is subject to the following two conditions 1 this device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment uses generates and can radiate radio frequency energy and if not installed in accordance with the operator s manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause interference in which case the user will be required to correct the interference at his her own expense Changes or modi
47. convenient place to install a momentary push button to reset or abort the board without powering down the host system 42 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com A A Pana ss AAA lt gt IA Chapter Functional Description This chapter includes the following major topics Power Distribution on page 44 Reset Logic on page 46 General CPU Section on page 48 SDRAM on page 59 Boot Flash Memory on page 63 Application Flash Memory on page 65 Time of Day Timer on page 67 Communications Buffer Memory on page 69 CompactPCl Interface on page 71 Fast Ethernet Controller on page 74 Serial I O Interface on page 77 General Purpose Registers on page 81 System Management Bus on page 103 The CPC358 is a full featured eight port Synchronous Serial Communications processor The board has field programmable control over the port protocol and can supply RS 232 RS 422 or V 35 in a one port granularity In addition the ports can be programmed to have a Data Communications Equipment DCE or Data Terminal Equipment DTE port profile This can be programmed on a one port basis Figure 4 1 on page 44 is a block diagram of the CPC358 43 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description Figure 4 1 Block Di
48. electricity Ordinary amounts of static electricity generated by your clothing or work environment can damage the electronic equipment It is recommended that anti static ground straps and anti static mats are used when installing the board in a system to help prevent damage due to electrostatic discharge Additional safety information is available throughout this guide and in the topic Safety Precautions on page 183 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ATAR A SN PN Dd Ed Ge Chapter 1 About This Guide Overview o Additional Documentation Text Conventions ooo Customer Support and Services Customer Support Packages Other Web Support Return Merchandise Authorization RMA Product Warranty a Chapter 2 Introduction Product Description Features of the CPC358 Rear Transition Module Features CPC358 Architecture Overview Processors nn Serial Communication Controllers Ethernet Ports Selectable Line Interface Clock Steering Monitor Port oo oc oc oo o o Electrical CAP x kn Artisan Technology Group Quality Instrumentation Contents Guaranteed 888 88 SOURCE www artisantg com Contents Universal O PC 28 Media GONNSCIONS 5 aria diia a KAG KABABA LA ALA KA
49. help customers maximize engineering efforts and achieve time to market goals To find out more about our Customer Support packages visit http www pt com page support Other Web Support Support for existing products including manuals release notes and drivers can be found on specific product pages at http www pt com Use the product search to locate the information you need Return Merchandise Authorization RMA To submit a return merchandise authorization RMA request complete the online RMA form available at http pt com assets lib files rma request form doc and follow the instructions on the form You will be notified with an RMA number once your return request is approved Shipping information for returning the unit to Performance Technologies will be provided once the RMA is issued Product Warranty Performance Technologies Incorporated warrants that its products sold hereunder will at the time of shipment be free from defects in material and workmanship and will conform to Performance Technologies applicable specifications or if appropriate to Buyer s specifications accepted by Performance Technologies in writing If products sold hereunder are not as warranted Performance Technologies shall at its option refund the purchase price repair or replace the product provided proof of purchase and written notice of nonconformance are received by Performance Technologies within 12 months of shipment or in the case of s
50. is loaded automatically upon boot up This occurs after chip selects are initialized but before the PowerSpan is enabled to respond to PCI cycles This makes it possible to customize the PowerSpan s initialization particularly the size and translation of Base Address Register 2 aperture Truly anything that can be done in Forth can be done in this initialization script Format of mass storage supporting BLOCK word set Sector 7 of the boot PROM is reserved for block storage It is organized as an array of block structures starting at Oxfff70000 Each block structure is defined as these 1027 bytes struct BLOCK char id short size char data 1024 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Resources Used by the Monitor The single character id field is further subdivided into a valid bit in the MSB and a seven bit block number Block numbers may range from 1 126 Block numbers 0 and 127 are invalid The size field must be 1024 Following this header are 1024 characters the text screen Additional Forth Word Set In addition to the Forth language provided by ficl the following words exist Serial Download S0 s zero offset flag Interpret a Motorola S record file Returns flag Application Flash AERASE a erase block flag Erase a block of application flash specified by block Block numbers range from 0 255 If block is 1 erase all bl
51. management interface Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Figure 4 8 Ethernet Dual PHY Block Diagram Fast Ethernet Controller FCC1 MII TXD TXD 3 0 TX gt eg FCC1 MII TX EN TX EN TX DATA FCC1 MII TX ER gt TX ER TX m TX gt J3 FCC1 MII TX CLK TX cLk 10 100 CPSB 4 FCC1 MII COL coL MAGNETICS PORT B FCC1 MII RXD 4 RXDI3 0 comm RX RX gt FCC1 MII RX ER 4 RX ER RX RX FCC1 MII RX CLK RX CLK PHY 1 G FCC1 MII RX DV 4 RX DV CS8952 4 FCC1 MII CRS crs FRONT EOM UART ee LED BLINK AND MDC MDC LED2 RX ACT LOGIC PAL EM M REAR MDIO gt MDIO LED3 LINK LINK LEDS PHY1 INT INT ISOLATE MII 1 9 ISODEF PHY 1 RESET RESET BAY ABBR 25 MHZ FCC2 MII TXD TXD 3 0 TX gt TX FCC2 MII TX EN TX EN TX DATA FCC2 MII TX ER 9 TX ER TX gt I TX J3 FCC2 MII TX CLK TX cLk 10 100 CPSB FCC2 MII COL coL MAGNETICS PORT A FCC2 MII RXD 4 RXD 3 0 BIGA RX RX gt FCC2 MII RX ER 4 RX ER 4 FCC2MIIRX CLK ROC
52. page 163 OEM Vendor Specific Commands netFn 0x30 0x31 on page 166 Overview of SMB The PT CPC4400 includes Performance Technologies implementation of the System Management Bus SMB This conforms to PICMG 2 9 the specification that defines SMB in the CompactPCI environment SMB utilizes the IC bus hardware layer coupled with Intelligent Platform Management software Intelligent Platform Management Interface IPMI The Intelligent Platform Management Interface IPMI specification allows system components on the 12C hardware layer bus to communicate with each other It provides a standard interface to hardware used for monitoring a system s physical characteristics such as temperature voltage power supplies etc IPMI makes possible out of band management of a system s resources with an emphasis on controlling hot swap activities 155 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 7 System Management Bus and Intelligent Platform Management The CPC358 supports limited Peripheral Management PM controller functions The implementation that is described in this section is a CompactPCI Peripheral Management controller PM It supports one IPMB IPMBO and is designed to meet the PICMG 2 9 requirements for a Peripheral Management controller The PM supports the mandatory and some optional IPM Device Global commands as well as the IPMI Field
53. program and erase operations The device package is a 56 pin TSOP 65 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description Figure 4 5 Application Flash Block Diagram o1 BUF A 0 24 CS FLASHA BUF_WR IBUF_RD APPLICATION FLASH DEVICE BUF AD 0 7 PQ_HRESET 28F128J3A 2x16Mx8 The device is accessed by the MPC8255 through the Buffered Data bus The Buffered data bus supplies a buffered 60x address and a bi directional 8 or 16 bit data bus The CS_FlashA is supplied by the Master MPC8255 and acts as the device chip enable The BUF_RD is supplied by the PSM550 PLD logic and acts as the device output enable The PSM550 also supplies the BUF WR strobe which is the write enable The CPC358 has a write protect feature that will not allow the BUF WR signal to activate unless the flash wp bit is set in the General Purpose registers The default after reset is to disable writing to the Flash The read and write cycle is timed by the GPCM s wait state programming There is no cycle termination signal generated by the device Master MPC8255 Related Flash Settings 66 The Master MPC8255 uses its chip select 3 CS3 as the CS_FlashA signal The CS3 Base Register is set to define the address space as 1000 0000h to 11FF FFFF H Table 4 17 is a list of recommended Base and Option Register field settings other than the base addr
54. startup control signals The sources are outlined in Table 4 2 Table 4 2 On Pin Control Sources Signal Name Function ICNT_PWR This input is selected by jumpering K44 1 2 This signal is generated by the SMB controller and should only be selected if the SMB bus is configured and active IP1 BD SEL This input is selected by jumpering K43 1 2 This signal is generated by the CompactPCI backplane Hot Swap controller It is used when this device is to be controlled by the CompactPCI Host GND This setting is selected by jumpering K46 1 2 This setting turns the board power on as soon as the board is plugged into a powered backplane It is used to bypass all of the above modes The power distribution system has bypass capacitance at several points in the system The un switched portion of the distribution circuit connected directly to the CompactPCl has a limited amount of bulk and high frequency bypass as directed by the CompactPCI specification The switched portion of the board or back end has much more distributed capacitance As a rule a 1uf cap is used for every 5V and 3 3V power pin to each IC This rule is observed unless there is a placement or routing conflict that demands otherwise There is sufficient bulk capacitance distributed about the board on each of the power planes 5 3 3 12 and 12 There are some chip specific voltages generated on the board These voltages were created for specific chi
55. the P1 connector The connector is set up to support the extended 16 pin COP debugger signaling but the basic 10 pin signaling devices may be used with an interposing adapter The P1 pinout is found in Table 6 8 Table 6 8 Master JTAG Pinout Pin Number Signal Name Master PQ TDO JTAG Test Data Out signal Master PQ_QACK Quiescent State Acknowledge not supported Master PQ_TDI JTAG Test Data In signal Master PQ TRST JTAG Reset and Tri state signal Master PQ_QREQ Quiescent State Request V3V Master PQ_TCK JTAG Test Clock No Connection Of Of NI O aj A Oj N Master PQ_TMS JTAG Test Mode Select No Connection Master PQ_SRESET MPC8255 Soft Reset Ground IPQ HRESET MPC8255 Hard Reset shared with Slave No Connection 15 16 Master ICHKSTPO Checkstop output Not supported Ground Pinouts All of the control signals are pulled to V3V with a 10K resistor to prevent false actuation when no JTAG controller is connected Slave MPC8255 JTAG Support The JTAG testing port on the Slave MPC8255 is used to support the EST COP debugger on the P3 connector The connector is setup to support the extended 16 pin COP debugger signaling but the basic 10 pin signaling devices may be used with an interposing adapter The P3 pinout is found in Table 6 9 Table 6 9 Slave JTAG Pinout Pin Number Signal Name Slave PQ_TDO JTAG Test Data Out signal
56. the yel1 yel5 bit A O in this bit position will enable the yel1 yel5 bit to turn on the LED and show one of the two LED colors available to the LED 4 RESV Always 0 5 yel2 With the ygoff2 ygoff6 bit set to a 0 a 1 in this bit position will set the Port 2 6 Status LED to yel6 yellow and a 0 in this bit position will set the LED to green 6 RESV Always 0 7 yel1 With the ygoff1 ygoff5 bit set to a 0 a 1 in this bit position will set the Port 1 5 Status LED to yel5 yellow and a 0 in this bit position will set the LED to green Port 3 4 7 8 Status LED Control Register The Port 3 4 7 8 Status LED Control Register controls the Green Yellow Port 3 7 and Green Yellow Port 4 8 status LEDs in LED array D2 D3 The register controls whether the LEDs are on or off and what color the bi color LEDs will show Note that the default state on a PQ_SRESET is the LEDs off Table 4 68 Port 3 4 7 8 Status LED Control Register Bit Fields MPC8255 Bit O MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 O LSB Field yel3 RESV yel4 RESV ygoff3 RESV ygoff4 RESV yel7 yel8 ygoff7 ygoff8 Reset Value 0 0 0 0 1 0 1 0 R W R W R R W R R W R R W R Address Base 75H 85H Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General Purpose Registers Table 4 69 Port 3 4 7 8 Status LED Control Register Bit
57. to the rear of the CompactPCI chassis where the cables are then attached to two 80 pin high density connectors Rear I O boards have a build option field of 0b0000 Front I O means that two 80 pin high density connectors are provided on the CPC358 front panel for connection of serial communication cables directly to the front panel Front I O boards have a build option field of 050001 Table 4 46 Board ID Register 1 Bit Fields MPC8255 Bit O MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 O LSB Field RESERVED brdid 5 0 Reset Value 0 R W READ ONLY Address Base 4CH Table 4 47 Board ID Register 1 Bit Field Definitions Bits Name Description 5 0 brdid 5 0 00H Initial Board Revision 7 6 RESV Always 0 Table 4 48 Board ID Register 2 Bit Fields MPC8255 Bit O MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 O LSB Field optionid 3 0 revid 3 0 Reset Value OH OH R W READ ONLY Address Base 4DH Table 4 49 Board ID Register 2 Bit Field Definitions Bits Name Description 7 4 optionid OH Installed Build Options 0 means Rear I O 1H Installed Build Options 1 means Front I O 3 0 Revid OH Board Hardware version revision Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General Purpo
58. used when installing the board in a system to help prevent damage due to electro static discharge Lithium Battery A Warning The CPC358 has a lithium battery on it The battery may explode if mishandled Do not dispose of battery in fire Do not disassemble the battery or attempt to recharge it Compliance with RoHS and WEEE Directives In February 2003 the European Union issued Directive 2002 95 EC regarding the Restriction of the use of certain Hazardous Substances in electrical and electronic equipment ROHS and Directive 2002 96 EC on Waste Electrical and Electronic Equipment WEEE This product is compliant with Directive 2002 95 EC It may also fall under the Directive 2002 96 EC Performance Technologies complete position statements on the RoHS and WEEE Directives can be viewed on the Web at http www pt com rohs position html Non Performance Technologies Branded Products Performance Technologies platform products may be distributed with third party hardware and or software products Regulatory compliance of Performance Technologies platform products is based on Performance Technologies specific product payload configurations under controlled environments Performance Technologies makes no claims regarding compliance of third party products please contact the manufacturer of the product directly for specific regulatory compliance information 185 Artisan Technology Group Quality Instrumentation Guaranteed 8
59. when the core enters low power mode 30 31 DFBRG 01 Division factor of BRGCLK relative to VCO_OUT twice the CPM clock Defines the BRGCLK frequency The BRGCLK is divided from the CPM clock 01 set the divisor to 16 Note When the MPC8255 has the RSTCONF jumper in the Boot PROM program mode K16 1 2 the clock default modes for the PLL are invoked The MPC 8255 will function in this mode it will be able to use the SDRAM and program the Boot Flash PROM but no other operations CPM or peripherals are guaranteed or supported Master MPC8255 Reset Configuration The reset configuration has two modes If the RSTCONF is high jumpered in the K16 1 2 Boot Flash programming mode the MPC8255 will take the default settings and there will be no Reset Configuration cycles on the Bus because the MPC8255 will be set to be a RESET Slave and the PowerSpan will be held in reset If the RSTCONT jumper is in the Normal mode K16 2 3 the MPC8255 will be set up as the Reset Configuration Master The Slave MPC8255 will be the 1 configuration slave The PowerSpan device will be the gid configuration salve The MPC8255 will read its configuration from the Boot Flash device beginning at location 0 The format of the boot words is listed in the MPC8260 s user manual The information read from the PROM is loaded into the Hard Reset Configuration Word Register The address for this device is located in the memory map in the MPC8260 s user manu
60. 0 Tel 716 759 2868 Tel 870 864 3602 FAX 716 759 6034 FAX 870 864 3674 Chemical Waste Management TWI TOXCO 7 Mobile Ave PO Box 232 Sauget IL 62201 Trail BC Canada V1R 4L5 Tel 618 271 2804 Tel 250 367 9882 FAX 618 271 2128 FAX 250 367 9875 Mechanical The CPC358 meets the mechanical requirements specified in the PICMG 2 0 R3 0 CompactPCI and the IEEE 1101 11 specifications Form Factor The main board is a 6U 233 35 mm by 160 mm board size The Rear Transition Modules RTM are also 6U size 233 35 mm The RTMs are 80 mm in depth for standard applications CompactPCI Connectors The board uses standard 2 mm shielded non Type AB CompactPCI connectors 29 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 2 Introduction Front Panel The CPC358 front panel is compliant with IEEE 1101 10 It includes an RJ 11 serial port and LEDs that display port activity and system status see Figure 3 2 on page 35 CompactPCI Interface The CPC358 supports a fully compliant 66 MHz 32 64 bit CompactPCI bus interface for local bus based management and or high speed data movement applications Ethernet Ports Two 10BaseT 100BaseTX Ethernet ports are provided on the CPC358 for management and data transfer purposes The Ethernet subsystem provides a dual independent subnet mode of operation where each port provides access to a separate subnet The CPC358 is con
61. 07FF FFFF CS1 Flash Boot PROM FFFO_000 to FFF7_FFFF CS2 Slave Local Bus SSRAM 20A0 0000 to 20A3 FFFF CS3 Application Flash 1000 0000 to 11FF FFFF CS4 PLD General Purpose Registers 2000 0000 to 20000 OFFF CS5 Master Local Bus SSRAM 2080 0000 to 2083 FFFF CS6 Not Assigned CS7 Not Assigned CS8 Time of Day Chip 2030 0000 to 2030 7FFF CS9 System Management Bus Controller 2040 0000 to 2040 7FFF Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General CPU Section 60x Bus Connections Each MPC8255 has its external bus configured in the Power PC 60x mode The bus features a 32 bit non parity address bus The address bus is pulled up by 20K resistor packs to V3V to prevent unknown bus conditions during no drive periods on the bus The 64 bit non parity data bus is also pulled up to V3V with 20K resistor packs to prevent unknown bus conditions during no drive periods on the bus The bus runs at a 66 MHz clock rate and because of this the length of the bus is restricted to 6 in or less with a very limited number of peripheral connections There are some multifunction pins that are used for bus control These assignments have been made as follows For multiple beat transfers the MPC8255 is configured to supply the BADDRXX lines as the lower order address bits The MPC8255 The PBSx PSDDQMx PWEx lines are configured as PSDDQMx PGPL5 PSDAMUX is configured as PSDAMUX for SDRAM con
62. 1 B 104 T Port 1 Receive Data 3 DTR1 108 H Port 1 Data Terminal Ready 4 5 TXD1 A 103 P Port 1 Transmit Data 6 TXD1 B 103 S Port 1 Transmit Data 7 RTS1 105 C Port 1 Request To Send 8 GND1 102 B Port 1 Signal Ground 9 TXC1 A 113 U Port 1 Transmit Clock 10 TXC1 B 113 W Port 1 Transmit Clock 11 TXCI1 A 114 Y Port 1 Transmit Clock In 12 TXCI1 B 114 AA Port 1 Transmit Clock In 13 DCD1 109 F Port 1 Data Carrier Detect 14 RI1 125 J Port 1 Ring Indicator 15 DSR1 107 E Port 1 Data Set Ready 16 LT1 K Port 1 Line Test 17 CTS1 106 D Port 1 Clear To Send 18 19 RXC1 A 115 V Port 1 Receive Clock 20 RXC1 B 115 X Port 1 Receive Clock 21 RXD2 A 104 R Port 2 Receive Data 22 RXD2 B 104 T Port 2 Receive Data 23 DTR2 108 H Port 2 Data Terminal Ready 24 25 TXD2 A 103 P Port 2 Transmit Data 26 TXD2 B 103 S Port 2 Transmit Data 27 RTS2 105 C Port 2 Request To Send 28 GND2 102 B Port 2 Signal Ground 29 TXC2 A 113 U Port 2 Transmit Clock 136 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table 6 5 V 35 Connector Pin Assignments Continued Artisan Technology Group Quality Instrumentation 80 Pin Amp Signal V 35 l M 34 Description Pin No Name Mnemonic Pin No 30 TXC2 B 113 W Port 2 Transmit Clock 31 TXCI2 A 114 Y Port 2 Transmit Clock In 32 TX
63. 10 Port 2 Data Carrier Detect Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 133 Chapter 6 Pinouts and Rear Transition Modules Table 6 4 ElA 530 Connector Pin Assignments Continued 80 Pin Amp Signal EIA 530 l EIA 530 DB 25 Description Pin No Name Mnemonic Pin No 35 DSR2 CC A 6 Port 2 Data Set Ready 36 DSR2 CC B 22 Port 2 Data Set Ready 37 CTS2 CB A 5 Port 2 Clear To Send 38 CTS2 CB B 13 Port 2 Clear To Send 39 RXC2 DD A 17 Port 2 Receive Clock 40 RXC2 DD B 9 Port 2 Receive Clock N A Shield Shield 1 Port 2 See Note 41 RXD3 BB A 3 Port 3 Receive Data 42 RXD3 BB B 16 Port 3 Receive Data 43 DTR3 CD A 20 Port 3 Data Terminal Ready 44 DTR3 CD B 23 Port 3 Data Terminal Ready 45 TXD3 BA A 2 Port 3 Transmit Data 46 TXD3 BA B 14 Port 3 Transmit Data 47 RTS3 CA A 4 Port 3 Request To Send 48 RTS3 CA B 19 Port 3 Request To Send 49 TXC3 DA A 24 Port 3 Transmit Clock 50 TXC3 DA B 11 Port 3 Transmit Clock 51 TXCI3 DB A 15 Port 3 Transmit Clock In 52 TXCI3 DB B 12 Port 3 Transmit Clock In 53 DCD3 CF A 8 Port 3 Data Carrier Detect 54 DCD3 CF B 10 Port 3 Data Carrier Detect 55 DSR3 CC A 6 Port 3 Data Set Ready 56 DSR3 CC B 22 Port 3 Data Set Ready 57 CTS3 CB A 5 Port 3 Clear To Send 58 CTS3 CB B 13 Port 3 Clear To Send 59 R
64. 21 LBPC 00 Local Bus Pin Configuration LBPC pins function as a local bus Note The Slave device should never have to use this feature with the core disabled but it is defined to prevent inadvertent problems 22 23 APPC 00 Address Parity Pin configuration no address parity Bank Select Function Selected on Multifunction pins 24 25 CS10PC 01 CS10 pin configuration is set to be IBCTL1 Buffer control for byte lane 1 26 27 RSVD 00 Reserved must be set to 0 28 31 MODCK_H 0110 MODCK_H Clock Reset Configuration high order bits set to 0110 for 66 MHz input clock 166 MHz CPM 233 MHz core Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General CPU Section Slave MPC8255 Internal Initial Configuration The internal Initial configuration is obtained from the Boot Code running out of the Flash PROM The initial settings for the System Integration Unit module configuration register SIUMCR because its register fields are most closely tied to the hardware configuration Table 4 11 Slave MPC8255 SIUMCR Register Settings Recommended e Field Description Setting BBD 0 IABB IRQ2 pin is ABB DBB IRQ3 pin is IDBB ESE 1 External Snooping is enabled GBL IRQ1 pin is GBL PBSE 0 Parity byte select is disabled GPL4 is available for UPM use CDIS 1 MPC8255 core is disabled DPPC 00 Pins set to IRQx L2CPC 10 Level 2 cache pi
65. 255 Transmit Clock pin It is also sent back out to the DCE as the TXC DCE Mode The DCE mode of the CPC358 is a new implementation Again as seen by the DCE the Receive Clock is always an input You can select either the Receive Clock off the port connector pin or use the optionally installed oscillator You will notice in the diagram that the Transmit Clock of the DTE becomes the Receive Clock of DCE We are designing a new cable V 35 only that performs this crossover Looking at the block diagram you will see that the TXC and RXC clocks are cross wired but the TXCI is not This is because the Linear Technology LTC2844 amp 2846 chip set has a bidirectional buffer for this signal that changes direction based on DTE or DCE The DCE must be able to output both TXC to drive the DTE s Receive Clock and TXCI to ultimately be fed back to the DCE There are two selections again Transmit Clock pin of the MPC8255 is bidirectional The first uses the MPC8255 s Transmit Clock as an output It is sent out in parallel to the DTE as TXC and TXCI The other selection uses the optionally installed oscillator This independent clock is sent out the TXC and TXCI pins and also sent back to the MPC8255 Transmit Clock as an input Figure 4 10 Clock Steering
66. 5 Clear To Send port 1 or 5 V 35 106 M 34 D 8 GND1 5 NA V 35 port 1 or 5 Signal Ground V 35 102 M 34 B 9 TXC A 1 5 Output NA V 35 Transmit Clock port 1 or 5 V 35 113 M 34 V 10 TXC B 1 5 Output NA V 35 Transmit Clock port 1 or 5 V 35 113 M 34 X 11 TXCI A 1 5 Output NA V 35 Transmit Clock In port 1 or 5 V 35 115 M 34Y 12 TXCI B 1 5 Output NA V 35 Transmit Clock In port 1 or 5 V 35 115 M 34 AA 13 DCD1 5 Output NA V 35 Data Carrier Detect port 1 or 5 V 35 109 M 34 F 14 RI1 5 Output NA V 35 Ring Indicator port 1 or 5 V 35 125 M 34 J 15 DTR1 5 Input BK Ohms to ground V 35 Data Terminal Ready port 1 or 5 V 35 108 M 34 H 16 LT1 5 Output NA V 35 Line Test port 1 or 5 V 35 M 34 K 17 RTS1 5 Input 5K Ohms to ground V 35 Request To Send port 1 or 5 V 35 105 M 34 C 19 RXC A 1 5 Input 100 Ohms differential V 35 Receive Clock port 1 or 5 125 Ohms to ground V 35 114 M 34 U 20 RXC B 1 5 Input 100 Ohms differential V 35 Receive Clock port 1 or 5 125 Ohms to ground V 35 114 M 34 W 21 TXD A 2 6 Input 100 Ohms differential V 35 Transmit Data port 2 or 6 125 Ohms to ground V 35 103 M 34 P 22 TXD B 2 6 Input 100 Ohms differential V 35 Transmit Data port 2 or 6 125 Ohms to ground V 35 103 M 34 S 23 DSR2 6 Output NA V 35 Data Set Ready port 2 or 6 V 35 107 M 34 E 25 RXD A 2 6 Output NA V 35 Receive Data port 2 or 6 V 35 104 M 34 R 26 RXD B 2 6 Output NA V 35 Receive Data port 2 or 6 V 35 104 M 34 T 139 Artisan Techn
67. 59 RXC A 3 7 Input 100 Ohms differential V 35 Receive Clock port 3 or 7 125 Ohms to ground V 35 114 M 34 U 60 RXC B 3 7 Input 100 Ohms differential V 35 Receive Clock port 3 or 7 125 Ohms to ground V 35 114 M 34 W 61 TXD A 4 8 Input 100 Ohms differential V 35 Transmit Data port 4 or 8 125 Ohms to ground V 35 103 M 34 P 62 TXD B 4 8 Input 100 Ohms differential V 35 Transmit Data port 4 or 8 125 Ohms to ground V 35 103 M 34 S 63 DSR4 8 Output NA V 35 Data Set Ready port 4 or 8 V 35 107 M 34 E 65 RXD A 4 8 Output NA V 35 Receive Data port 4 or 8 V 35 104 M 34 R 66 RXD B 4 8 Output NA V 35 Receive Data port 4 or 8 V 35 104 M 34 T 67 CTS4 8 Output NA V 35 Clear To Send port 4 or 8 V 35 106 M 34 D 68 GND4 8 NA V 35 port 4 or 8 Signal Ground V 35 102 M 34 B 141 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 6 Pinouts and Rear Transition Modules Table 6 6 V 35 Signals and Pins DCE Continued Pin T ae a No Signal Name Direction Termination Description 69 TXC A 4 8 Output NA V 35 Transmit Clock port 4 or 8 V 35 113 M 34 V 70 TXC B 4 8 Output NA V 35 Transmit Clock port 4 or 8 V 35 113 M 34 X 71 TXCI A 4 8 Output NA V 35 Transmit Clock In port 4 or 8 V 35 115 M 34 Y 72 TXCI B 4 8 Output NA V 35 Transmit Clock In port 4 or 8 V 35 115 M 34 AA 73 DCD4 8 Output NA V 35 Data Carrier De
68. 5c7 SWSR sth r3 0xe r4 lis r3 0x4E24 SIUMCR Master 0x4E24 0000 OEL r3 r3 0x0000 stw r3 0x0 r4 Chip Select 1 SDRAM lis r3 0xf800 ORI 128MB ori r3 r3 0x2b10 stw Sr3 0x10c 3r4 106 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com lis ori stw li sth li stb li stb SDRAM Initialization lis ori stw li stb lis na a a 2 a G H ct is ri nor CW n rnm pi nuor 5 H r3 0x0000 r3 r3 0x0041 r3 0x108 r4 r3 0x3200 r3 0x184 r4 r3 0x08 r3 0x198 r4 r3 0x0e r3 0x19c r4 r3 0xabae r3 r3 0x24ae r3 0x0190 r4 r3 0x7f r3 0 r0 r3 0x8bae r3 r3 0x24ae r3 0x0190 r4 r3 0x7f r3 0 r0 r3 0 r r3 0 o o o9 o oP oe r3 0x9bae r3 r3 0x24ae r3 0x0190 r4 r3 0x00 r3 0x110 r0 r3 0xclae r3 r3 0x24ae r3 0x0190 r4 BR1 MPTPR PURT PSRT MODEPRCHG PRCHG MODECBRRF CBRRFRSH CBRRFRSH CBRRFRSH CBRRFRSH CBRRFRSH CBRRFRSH CBRRFRSH CBRRFRSH CBRRFRSH IAN 04 WN H O MODEREG WRITEIT NORMAL CPM SyncSRAM on Chip Select 2 static const long UPMBTable single read single writ Ox00f33005 Oxfffff000 Fffff000 Oxfffff000 Ox Ox Ox Ox Ox Ox Ox ffe33000 Oxffaff005 Fffff000 Oxfffff000 burst read offset ffe33008 Oxf
69. 6 PQ A22 20 21 PQ A7 PQ A23 22 23 PQ A8 PQ A24 24 25 PQ A9 PQ A25 26 27 PQ A10 PQ A26 28 29 PQ At PQ A27 30 31 PQ A12 PQ A28 32 33 PQ A13 PQ A29 34 35 PQ A14 PQ A30 36 37 PQ A15 PQ A31 38 144 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table 6 11 J10 Mictor Pinout 60X Bux Data Pin Number Signal Name Signal Name Pin Number 1 NC NC 2 3 NC NC 4 5 IPQ TA IPQ PSDVAL 6 7 PQ_D32 PQ DO 8 9 PQ D33 PQ D1 10 11 PQ_D34 PQ_D2 12 13 PQ_D35 PQ_D3 14 15 PQ_D36 PQ_D4 16 17 PQ_D37 PQ_D5 18 19 PQ_D38 PQ_D6 20 21 PQ_D39 PQ_D7 22 23 PQ_D40 PQ_D8 24 25 PQ_D41 PQ_D9 26 27 PQ_D42 PQ_D10 28 29 PQ_D43 PQ_D11 30 31 PQ_D44 PQ_D12 32 33 PQ_D45 PQ_D13 34 35 PQ_D46 PQ_D14 36 37 PQ_D47 PQ_D15 38 Table 6 12 J11 Mictor Pinout 60X Bus Data Pin Number Signal Name Signal Name Pin Number 1 NC NC 2 3 NC NC 4 5 NC NC 6 7 PQ_D48 PQ_D16 8 9 PQ_D49 PQ_D17 10 11 PQ_D50 PQ_D18 12 13 PQ_D51 PQ_D19 14 15 PQ_D52 PQ_D20 16 17 PQ_D53 PQ_D21 18 19 PQ_D54 PQ_D22 20 21 PQ_D55 PQ_D23 22 23 PQ_D56 PQ_D24 24 25 PQ_D57 PQ_D25 26 27 PQ_D58 PQ_D26 28 29 PQ_D59 PQ_D27 30 31 PQ_D60 PQ_D28 32 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Pinouts 145 Chapter 6 Pinouts and Rear Tran
70. 7 8 Mode Control Register selects the desired electrical interface for Ports 3 and 4 Ports 7 and 8 individually controlled It also selects whether the ports are DTE computer or DCE modem also individually controlled Table 4 59 Transceiver 3 4 7 8 Mode Control Register Bit Fields MPC8255 Bit 0 MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 O LSB Field dte 4 n m2 4 m14 m04 dte 3n m2_3 m1 3 mO 3 dte 8 n m2 8 m1 8 mo 8 dte 7 n m2 7 m1 7 m0 7 Reset Value 0 1 1 1 0 1 1 1 R W R W Address Base 71H 81H Table 4 60 Transceiver 3 4 7 8 Mode Control Register Bit Field Definitions Bits Name Description 0 mO 3 Port 3 7 Mode Select Pin 0 mO 7 1 m1 3 Port 3 7 Mode Select Pin 1 m1 7 2 m2 3 Port 3 7 Mode Select Pin 2 m2 7 3 die 3n 0 Port3 7 is DTE die 7 n 1 Port 3 7 is DCE 4 mO 4 Port 4 8 Mode Select Pin 0 m0 8 5 m14 Port 4 8 Mode Select Pin 1 m1 8 6 m2 4 Port 4 8 Mode Select Pin 2 m2 8 7 dte 4 n 0 Port 4 8 is DTE dte 8 n 1 Port 4 8 is DCE Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General Purpose Registers Receive Clock Steering Control Register The Receive Clock Steering Control Register is used to select the source of the Receive Clock on a port by port
71. 8 Switch SW1 The function of the four section dip switch SW1 is defined by user developed board software The settings are described in General Purpose Switch and P1 Reset Control Register on page 87 Jumpers The jumper settings in Table 3 1 reflect the factory default configuration for the CPC358 You may need to adjust these settings to comply with the requirements of any software application you may be using Consult the application documentation for more information No special tools are required to move jumpers An asterisk indicates the factory default Table 3 1 Jumpers In Out Jumper Pins Function p default K1 1 2 In System Management Bus SMB active 2 3 In System Management Bus SMB disabled K2 1 2 In CT bus is Reset Master 2 3 In Factory set K3 1 2 In Immediate HEALTHY signal presented to CompactPCI backplane resulting from IPWRGD signal 2 3 In IHEALTHY signal requires IAMOK bit set by processor in Miscellaneous Status and Control Register in addition to IPWRGD signal K4 1 2 In When no PCI Bus is in Card File CT bus is Master 2 3 In Factory set K5 1 2 In Reserved Factory Burn in and NexusWare auto boot Jumper K5 will be in the 1 2 position if the CPC358 was ordered with software Having the K5 jumper in the 1 2 positions allows the board to auto boot 2 3 In Normal position K6 1 2 In Installing this jumper allows for the cor
72. 8 LS BB BR O E la EEE 9090 ga com Huonoon 0000000 amp dn uU ec o9o joa NE Be paer o9o sol SES opem Es 0202 a7 IE Goe OO O ARABES ETT oooooo 26 96 EH Kia Kio 5 3 o oo Eg E po Inn rm O 000000 Be Ba Em E BB 1 ES m le 600000 0605 a E m oo EB RH kb Bn B E 0909 ses lol lo oo B BE Re Bh ka EB 000000 0202 EH 2 2 B 8 S E 000000 O O 5 o OO puoisP Tp1 C42 a i 000000 Ooo Ba o HG sa E 9090 kao RI a 00 000001 2Q E 000000 OO RPS E 1888 Hn BB 000000 2026 Boot he M ped cC S Elzo O B o 3 28583 H O IE 000000 o a cera Bios 2 B BEEBE BE 8 g 999000 oO jo o 3 o E oo 5 1 min PORT1 4 501 JO 3 B B HA a ooj E En E E ren O O zi tg ga FU om0 Blool 00000000 EB nn Al E BB e RIS 9 ans BA 3 99 3BEEH Ba B O de BE a BRA 00 3333 ttm EN NE E KH HM Foo BB ys C Ti 5 mi 0 0 peed a B o R132 C79 Hi a 06505 se OD e m BE 2626 EHO 9 3 ie HG a odo o lo 3 ba pa FE LJ B 16 0202 Rp14 K26 RIB og me aa 8838 5 Ooo O pa SG TPIS nido HA BB 6 2 ooo BEBE wks E ous Hi B m 8 o bo O of a Ha Sogo O B3 U32 TP16 DO Bn mn 2 0202 EE Em 8 ce Dnnnnnn 00000000 m m E 0909 S 4n 2 2 3 bi bb 0905 neis O O 3 D0000000 00000000 EE de 0202 EB O O gt us u37 0 R159 OO Ri 40 EA EA 0209 kao Rie x o 4 DE 1 K29 003 s Ooa z593 BH O AL ogee Eio NN Boum So s Lr 2E ia i 0505 ma i CR oO on 0902 BAO 3 Es FI K31 32 0200 elol lo o 5 ol Oj Olas ma 0909 ze O lO 3 OH Bes HI oom BB s
73. 8255 Port B Pin Assignments 178 Pin Pin Function PPARB 1 PPARB 0 PSORB 0 PDIRB 1 Out PDIRB 0 In PDIRB 1 Out PSORB 1 PDIRB 0 In Out PDIRB 1 Out PDIRB 0 In PB31 PB30 PB29 PB28 PB27 PB26 PB25 PB24 PB23 PB22 PB21 PB20 PB19 PB18 PB17 PB16 PB15 SCC2 RXD PB14 SCC3 RXD PB13 PB12 SCC2 TXD PB11 PB10 PB9 PB8 SCC3 TXD PB7 DSRS PB6 DSR6 PBS DSR7 PB4 DSR8 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Slave MPC8255 Port C Pin Assignments Table 8 7 defines the Slave MPC8255 s Port C Pin assignments Table 8 7 Slave MPC8255 Port C Pin Assignments Slave MPC8255 Parallel Port Pin Assignments Pin Pin Function PPARC 1 PPARC 0 PSORC 0 PSORC 1 PDIRC 0 PDIRC 1 Out PDIRC 0In PDIRC 1 Out In Out PDIRC 1 Out PDIRC 0 In PC31 SCC2 TX CLK BRG1 output PC30 PC29 SCC1 TX CLK SCC1 TX_CLK BRG2 output CLK3 input PC28 SCC1 RX CLK CLK4 input PC27 SCC3 TX CLK SCC3 TX CLK CLK5 input BRG3 output PC26 SCC3 RX_CLK CLK6 input PC25 SCC4 TX CLK SCC4 TX CLK CLK7 input BRG4 output PC24 SCC4 RX_CLK
74. 88 88 SOURCE www artisantg com Chapter 9 Agency Approvals 186 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com A rtisan Artisan Technology Group is your source for quality Technology Group new and certified used pre owned equipment FAST SHIPPING AND SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT DELIVERY Experienced engineers and technicians on staff Sell your excess underutilized and idle used equipment TENS OF THOUSANDS OF at our full service in house repair center We also offer credit for buy backs and trade ins IN STOCK ITEMS www artisantg com WeBuyEquipment EQUIPMENT DEMOS HUNDREDS OF Instra REMOTE INSPECTION LOOKING FOR MORE INFORMATION MANUFACTURERS Remotely inspect equipment before purchasing with Visit us on the web at www artisantg com 7 for more our interactive website at www instraview com information on price quotations drivers technical LEASING MONTHLY specifications manuals and documentation RENTALS ITAR CERTIFIED CEP ala aed Contact us 888 88 SOURCE sales artisantg com www artisantg com
75. 900 MOVE 0 0x70 reserved 14 bytes 0 0x7e checksum 2 bytes The 16 bit wide sum of all the bytes in this table not including these two NVRAM Word Set The NVRAM Word Set is used to manipulate the NVRAM structure Each word finishes by putting a valid checksum in the NVRAM structure to maintain its validity set nv cksum Validate the NVRAM data structure set bootaddr addr addr specifies the entry point of application code set autoboot flag This flag indicates whether to boot automatically or not set diagflg flag This flag indicates whether to run diagnostics or not set wdogboot flag This flag indicates whether to boot when the reset is caused by watchdog expiration or not set diagboot flag This flag indicates whether to boot upon encountering a diagnostic error or not 119 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 5 Boot PROM and Forth Monitor 120 set verbose flag This flag indicates whether to give verbose output from the boot process or not set pcimap len bs bs is the value of the BS field in the PowerSpan s P1_TIO_CTL register set move src dest size src dest and size are arguments to 6 1 1900 MOVE set nv defaults NVRAM is initialized to known good values boot implements the following flow chart Artisan Technology Group Quali
76. AKA KK NAKA IRR d Ed hee E p C enc ed 168 Set Card Power State teren dee BNG Wiede ceed GUN abe PERI ed ard 169 Get Card Power State s c cos da nce eyed Keeley ended adie weve ae 170 Chapter 8 MPC8255 Parallel Port Pin Utilization 171 Master MPC8255 20 BUS n5 aaa cbr RRREICs NAG riadas 171 Master MPC8255 Parallel Port Pin Assignments onee 171 Master MPC8255 Port A Pin Assignments eeen 171 Master MPC8255 Port B Pin Assignments neen 173 Master MPC8255 Port C Pin Assignments oenen eee 174 Master MPC8255 Port D Pin assignments neen 176 Slave MPC8255 Parallel Port Pin Assignments eneen 176 Slave MPC8255 Port A Pin assignments renee 177 Slave MPC8255 Port B Pin assignments nennen 178 Slave MPC8255 Port C Pin Assignments eenen 179 Slave MPC8255 Port D Pin assignments enen 181 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Contents Chapter 9 Agency Approvals 183 Safety POCOS samen Mee a ede Va ROO DR OU QU dc eet GAN odes NA M a 183 Gertificatio S 15 en A eee eere Ebens pede hh ee 184 FCC NOUR UP 184 GERO M rrr 184 Compliance with RoHS and WEEE Directives onee 185 Non Performance Technologies Branded Products 0 000 eee eee eee 185 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Contents 10 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com AA grum
77. B BEB mi Dn O0 OO DO 00 OO COO Beas gp amma E b ME iiis Du mice BB BH 2E E E a BB on So Baga szo seo aro 599 veg 260 mo Bee M0 gaga en moo wn END sn Do sen En ten Don een Don ven moo zen pa szzy DO Bu T in 8t fs sn ina NN D oin ain zen BZN ven Len gen ELN sin ven oen gen een Len s 8 5 Le DO HG U55 icu pr B geza DO Hn na n EELO seza ERI 0928 ao PA onn cel z DO trio 1x44 nG I EEH mm O oo orca 19 HE Spo B Do o 8 fa geze Da Hu B8 wali 29 E amp O 012 Ha rie sr Los ooloo Hoo Ho LET mum Q e orto RS O O gee Oa Nm I 00000000000000000000 00000000000000000000 8 EI LLILLITLTI LN wl m4 N X N N N ON LO o N LO oo St v ON CN CN e St Ng x x M NG NY Xx x Lo ol 000 Lo ol 000 Lo ol 000 Lo ol Hoo oo Hoo Hoo Hoo Hoo Hool Hool Hool Hool Hoo Hool Goo Hool Hool Moo Dood e E EEE 2 S8 5 3 S 5 8 8 8 S T mem x x Ne Y Y Y Y Y Y Y x Y Y Y Y Ng 37 Guaranteed 888 88 SOURCE www artisantg com Artisan Technology Group Quality Instrumentation Chapter 3 Installation Jumpers and DIP Switches This section describes the function and appropriate settings for the jumpers and DIP switches on the CPC35
78. BINE n 9 EET EE pa NE EE Rm ol dmm A se gd A pa BOER O mars resosi OO E oo O Bo 3 old o DOON a Ey mps E OO H nai gue Olg engg ah O o UB Sor O 5 A O ER Bens BB RP32 s amp n OO t g hilo lo lo EE dd KS7 PRGRST _ p m K43 B0SEL 50 pa Kaka ka Ear mao BG Eros 2 70 077 a NG Bi Icon o E Ka CTEN gt H KA6 FRCON pos y 8 FREH 3 x a oe td BG Ph E g 8 one pt Fed Sols g N gE fg SERE D 85 70 y S 99 L 33S 3 2 KG 58888 o 5 s BHBHEHSH HEHE ELLE S enso DCE E rd R239 eBEEHEEES BRRER RES E ES es E K47 O OO 0 ISOGND 3 O Sl oo BB o Oo O o nI Bp 255 EH i iii q g 9i mn i PDO ER O O K16 Working with the CPC358 Additional Jumper Locations Figure 3 4 Walo WELO N31NIB O O O D O O LOO LI O O D O O DO O s 1oV8NS H AHLIHI H B 19v H o signs OIS As e ga L A hae OS meo OO 50000 00000000 LI ONES CIR dis ea Dai O0 00000 10000000 apg prove os Dr won DO 3 Dols dd tale s o US pana cuo g mmo EO 80 Dols Bi EA Ee 959 099 EA 7 LSCH SE Do mg 5 BS 3 BE A B ES ES 3 BH Du B S Em 9 amp E B8 BE E y SLE d m PN E 2 HA 8 5 ind B6 Hn H Hm el ju E Bn Hu B BS a me ss E B He E Zeo 3 BE mo E Es 8 E m S E sam C Ha HE TO m Kam fe zs 26888 OD GEREBERH SS mo
79. C l2CSCL PD13 PD12 PD11 PD10 PD9 SMC1 SMTXD PD8 SMC1 SMRXD PD7 SMC1 RSVD SMSYN PD6 PD5 PD4 Slave MPC8255 Parallel Port Pin Assignments The following sections represent the Slave MPC8255 parallel port bit configurations for this 176 design Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Slave MPC8255 Parallel Port Pin Assignments Slave MPC8255 Port A Pin assignments Table 8 5 defines the Slave MPC8255 s Port A Pin assignments Table 8 5 Slave MPC8255 Port A Pin Assignments Pin PPARA 1 Pin Function PPARA 0 PSORA 0 PSORA 1 PDIRA 1 Out PDIRA 0 In PDIRA 1 Out PDIRA 0 In PDIR 1 Out PDIRA 0 In PA31 PA30 PA29 PA28 PA27 PA26 PA25 PA24 LTS LT6 PA23 PA22 LT7 LT8 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 RIS RI6 PA11 PA10 RI7 RI8 PA9 PAS PA7 PA6 PAS PA4 PA3 PA2 PA1 PAO 192M INT Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 177 Chapter 8 MPC8255 Parallel Port Pin Utilization Slave MPC8255 Port B Pin assignments Table 8 7 defines the Slave MPC8255 Port B Pin assignments Table 8 6 Slave MPC
80. C NC NC NC NC NC 22 NC NC NC NC NC NG 21 NC NC NC NC NG NG 20 NG NC NC NC NG NG 19 NG NC NC NC NC NC 18 NC NC NC NC NC NG 17 NC NC NC NC NG NG 16 NC NC NC NC NG NG 15 NG NC NC NC NC NG 14 13 Keying Area 12 11 NC NC NC HLVIO NC GND 10 NC EV3V NC LVDD NC GND 9 NC NC NC GND NC GND 8 NC NC NC LVDD NC GND 7 NC EVDD NC GND NC GND 6 NC NC NC GND NC GND 5 NG NG NG LV3V NC GND 4 NC EVDD NC LV3V NC GND 3 NC NG NG GND NG GND 2 NC NC NC NC GND GND 1 NC EV3V NC NC NC GND Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Pinouts 151 Chapter 6 Pinouts and Rear Transition Modules J5 Connector Pinouts RS 422 RS 449 RS 530 Signals Table 6 19 reflects the pinout of the CompactPCI J5 connector Note that these signals are only active on the rear I O version of the product with the exception of the TBD Table 6 19 J5 RS 422 RS 449 RS 530 Signal Pinouts Pin A B C D E F 22 TXD1 TXC1 TXCI1 RXD1 RXC1 GND 21 TXD1 TXC1 TXCI1 RXD1 RXC1 GND 20 RTS1 DCD1 DSR1 CTS1 DTR1 GND 19 RTS1 DCD1 DSR1 CTS1 DTR1 GND 18 GND GND GND GND GND GND 17 TXD3 TXC3 TXCI3 RXD3 RXC3 GND 16 TXD3 TXC3 TXCI3 RXD3 RXC3 GND 15 RTS3 DCD3 DSR3 CTS3 DTR3 GND 14 RTS3 DCD3 DSR3 CTS3 DTR3 GND 13 TXD2 TXC2 TXCI2 RXD2 RXC2 GND 12 TXD2 TXC2 TXCI2 RXD2 RXC2 GND 11 RTS2 DCD2 DSR2 CTS2 DTR2 GND 10 RTS2 DCD2 DSR2 CTS2
81. CD1 A RR A 13 Port 1 Data Carrier Detect 14 DCD1 B RR B 31 Port 1 Data Carrier Detect 15 DSR1 A DM A 11 Port 1 Data Set Ready 16 DSR1 B DM B 29 Port 1 Data Set Ready 17 CTS1 A CS A 9 Port 1 Clear To Send 18 CTS1 B CS B 27 Port 1 Clear To Send 19 RXC1 A RT A 8 Port 1 Receive Clock 20 RXC1 B RT B 26 Port 1 Receive Clock Shield Ground SG SG 1 Port 1 Shield Ground and Signal Ground 21 RXD2 A RD A 6 Port 2 Receive Data 22 RXD2 B RD B 24 Port 2 Receive Data 23 DTR2 A TR A 12 Port 2 Data Terminal Ready 24 DTR2 B TR B 30 Port 2 Data Terminal Ready 25 TXD2 A SD A 4 Port 2 Transmit Data 26 TXD2 B SD B 22 Port 2 Transmit Data 27 RTS2 A RS A 7 Port 2 Request To Send 28 RTS2 B RS B 25 Port 2 Request To Send 29 TXC2 A TT A 17 Port 2 Transmit Clock 30 TXC2 B TT B 35 Port 2 Transmit Clock 31 TXCI2 A ST A 5 Port 2 Transmit Clock In 130 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Pinouts Table 6 3 RS 449 Connector Pin Assignments Continued 80 Pin RS 449 RS 449 l RS 449 u No Signal Mnemonic DB 37 Description Name Name Pin No 32 TXCI2 B ST B 23 Port 2 Transmit Clock In 33 DCD2 A RR A 13 Port 2 Data Carrier Detect 34 DCD2 B RR B 31 Port 2 Data Carrier Detect 35 DSR2 A DM A 11 Port 2 Data Set Ready 36 DSR2 B DM B 29 Port 2 Data Se
82. CI2 B 114 AA Port 2 Transmit Clock In 33 DCD2 109 F Port 2 Data Carrier Detect 34 RI2 125 J Port 2 Ring Indicator 35 DSR2 107 E Port 2 Data Set Ready 36 LT2 K Port 2 Line Test 37 CTS2 106 D Port 2 Clear To Send 38 39 RXC2 A 115 V Port 2 Receive Clock 40 RXC2 B 115 X Port 2 Receive Clock 41 RXD3 A 104 R Port 3 Receive Data 42 RXD3 B 104 T Port 3 Receive Data 43 DTR3 108 H Port 3 Data Terminal Ready 44 45 TXD3 A 103 P Port 3 Transmit Data 46 TXD3 B 103 S Port 3 Transmit Data 47 RTS3 105 C Port 3 Request To Send 48 GND3 102 B Port 3 Signal Ground 49 TXC3 A 113 U Port 3 Transmit Clock 50 TXC3 B 113 W Port 3 Transmit Clock 51 TXCI3 A 114 Y Port 3 Transmit Clock In 52 TXCI3 B 114 AA Port 3 Transmit Clock In 53 DCD3 109 F Port 3 Data Carrier Detect 54 RI3 125 J Port 3 Ring Indicator 55 DSR3 107 E Port 3 Data Set Ready 56 LT3 K Port 3 Line Test 57 CTS3 106 D Port 3 Clear To Send 58 59 RXC3 A 115 V Port 3 Receive Clock 60 RXC3 B 115 X Port 3 Receive Clock Guaranteed 888 88 SOURCE www artisantg com Pinouts 137 Chapter 6 Pinouts and Rear Transition Modules 138 Table 6 5 V 35 Connector Pin Assignments Continued 80 Pin Amp Signal V 35 l M 34 Description Pin No Name Mnemonic Pin No 61 RXD4 A 104 R Port 4 Receive Data 62 RXD4 B 104 T Port 4 Receive Data 63 DTR4 108 H Port 4 Data Terminal Ready 64
83. D components on the CPC358 The one related to serial ports 1 through 4 begin at offset 0000 007xHin the ICS REG space The one related to serial ports 5 through 8 begin at offset 0000 008xH in the ICS REG space These registers include Transceiver 1 2 5 6 Mode Control Register at address offset 70H 80H Transceiver 3 4 7 8 Mode Control Register at address offset 71H 81H Receive Clock Steering Register at address offset 72H 82H Transmit Clock Steering Control Register at address offset 73H 83H Port 1 2 5 6 Status LED Control Register at address offset 74H 84H Port 3 4 7 8 Status LED Control Register at address offset 75H 85H Transceiver Shutdown Control Register at address offset 76H 86H LED Mode Slave Reset Control Register at address offset 77H 87H RESERVED Register at address offset 7AH through 7FH 8AH through 8FH A block diagram of the Port Control Registers PLD is presented in Figure 4 12 Port Control Registers Block Diagram on page 94 93 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description Figure 4 12 Port Control Registers Block Diagram LTC2846 Muliprotocol Transceiver INx Clock Steering LED C
84. DO ACK64 GND 23 EV3V AD4 AD3 LVDD AD2 GND 22 AD7 GND LV3V AD6 AD5 GND 21 EV3V AD9 AD8 M66EN CBEO GND 20 AD12 GND EVIO AD11 AD10 GND 19 EV3V AD15 AD14 GND AD13 GND 18 SERR GND EV3V PAR CBE1 GND 17 EV3V IPMB SCL IPMB SDA GND PERR GND 16 DEVSEL PCI XCAP EVIO STOP LOCK GND 15 EV3V FRAME IRDY BD_SEL TRDY GND 44 tr 13 Keying Area 12 11 AD18 AD17 AD16 GND CBE2 GND 10 AD2t GND EVSV ADO0 ADI9 GND 9 CBE3 IDSEL AD23 GND AD22 GND 8 AD2e X GND EVO AD25 AD4 GND 7 AD30 AD29 AD28 GND AD27 GND le REQR PCILPRESENT LV3V CLIK X ADS31 GND 5 RSVD RSVD RST GND GNT GND Pa IVSM HEALTHY lo NC TIN GND 3 INTA INTB NC INTC NC LVDD INTD NC GND 2 TCKNC flew TMS X TDO TD GND 1 EVDD 12V TRST 12 V EVDD GND Pinouts 147 Chapter 6 Pinouts and Rear Transition Modules 148 J2 Connector Pinout Table 6 14 J2 CompactPCI Connections Pin A B C D E F 22 GA4 GA3 GA2 GA1 GAO GND 21 NG NG NG NC NG GND 20 NG NG NG GND NG GND 19 NG NG NC NC NG GND 18 RSVD NG RSVD NG RSVD NC GND RSVD NC GND 17 RSVD NC GND NC NC NC GND 16 RSVD NC RSVD NC NG GND RSVD NG GND 15 RSVD NC GND NC NC NC GND 14 AD35 AD34 AD33 GND AD32 GND 13 AD38 GND EVIO AD37 AD36 GND 12 AD42 AD41 AD40 GND AD49 GND 11 AD45 GND EVIO AD44 AD43 GND 10 AD49 AD48 AD47 GND AD46 GND 9 AD52 GND EVIO AD51 AD50 GND 8 AD56 AD55 AD54 GND AD53 GND 7 AD59 GND
85. DTR2 GND 9 TXD4 TXC4 TXCI4 RXD4 RXC4 GND 8 TXD4 TXC4 TXCI4 RXD4 RXC4 GND 7 RTS4 DCD4 DSR4 CTS4 DTR4 GND 6 RTS4 DCD4 DSR4 CTS4 DTR4 GND 5 GND GND GND GND GND GND 4 TXD5 TXC5 TXCI5 RXD5 RXC5 GND 3 TXD5 TXC5 TXCI5 RXD5 RXC5 GND 2 RTS5 DCD5 DSR5 CTS5 DTR5 GND 1 RTS5 DCD5 DSR5 CTS5 DTR5 GND 152 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table 6 20 and Table 6 21 show adjustments to J5 for other electrical interfaces Table 6 20 DTE RS232 Adjustments for J5 Pin Signal Name Adjustment J5 D20 CTS1 Ground for RS 232 signal ground J5 D11 CTS2 Ground for RS 232 signal ground J5 D15 CTS3 Ground for RS 232 signal ground J5 D7 CTS4 Ground for RS 232 signal ground J5 D2 CTS5 Ground for RS 232 signal ground Table 6 21 DTE V 35 Adjustments for J5 Pin Signal Name Adjustment J5 D20 CTS1 Ground for V 35 unused wire J5 D11 CTS2 Ground for V 35 unused wire J5 D15 CTS3 Ground for V 35 unused wire J5 D7 CTS4 Ground for V 35 unused wire J5 D2 CTS5 Ground for V 35 unused wire J5 E20 DTR1 Ground for V 35 unused wire J5 E11 DTR2 Ground for V 35 unused wire J5 E15 DTR3 Ground for V 35 unused wire J5 E7 DTR4 Ground for V 35 unused wire J5 E2 DTR5 Ground for V 35 unused wire J5 A20 RTS1 Ground for V 35 signal ground J5 A11 RTS2 Ground
86. E Bit Name Description 0 tcsl1 0 Transmit Clock TXC1 5 is sourced from MPC8255 Transmit Clock pin TXCLKIN 1 5 PIN tcsl5 MUST BE PROGRAMMED AS OUTPUT 1 Transmit Clock TXC1 5 is sourced from serial port TXCI1 5 TXCI1 5 is also driven back to the MPC8255 Transmit Clock pin as TXCLKOUT 1 5 PIN MUST BE PROGRAMMED AS INPUT 1 tcsl2 0 Transmit Clock TXC2 6 is sourced from MPC8255 Transmit Clock pin TXCLKIN 2 6 PIN tcsl6 MUST BE PROGRAMMED AS OUTPUT 1 Transmit Clock TXC2 6 is sourced from serial port TXCI2 6 TXCI2 6 is also driven back to the MPC8255 Transmit Clock pin as TXCLKOUT 2 6 PIN MUST BE PROGRAMMED AS INPUT 2 tcsl3 0 Transmit Clock TXC3 7 is sourced from MPC8255 Transmit Clock pin TXCLKIN 3 7 PIN tesl7 MUST BE PROGRAMMED AS OUTPUT 1 Transmit Clock TXC3 7 is sourced from serial port TXCIS 7 TXCI3 7 is also driven back to the MPC8255 Transmit Clock pin as TXCLKOUT 3 7 PIN MUST BE PROGRAMMED AS INPUT 3 tcsl4 0 Transmit Clock TXC4 8 is sourced from MPC8255 Transmit Clock pin TXCLKIN 4 8 PIN tcsl8 MUST BE PROGRAMMED AS OUTPUT 1 Transmit Clock TXC4 8 is sourced from serial port TXCI4 8 TXCI4 8 is also driven back to the MPC8255 Transmit Clock pin as TXCLKOUT 4 8 PIN MUST BE PROGRAMMED AS INPUT Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General Purpose Registe
87. E www artisantg com Table 6 2 RS 232C Connector Pin Assignments Continued Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 80 Pin Signal RS 232C m b sorintion No Name Mnemonic Pin No 5 TXD1 BA 2 Port 1 Transmit Data 6 14 7 RTS1 CA 4 Port 1 Request To Send 8 19 9 TXC1 DA 24 Port 1 Transmit Clock 10 11 11 TXCI1 DB 15 Port 1 Transmit Clock In 12 12 13 DCD1 CF 8 Port 1 Data Carrier Detect 14 10 15 DSR1 CC 6 Port 1 Data Set Ready 16 22 17 CTS1 CB 5 Port 1 Clear To Send 18 GND1 AB YA Port 1 Signal Ground 19 RXC1 DD 17 Port 1 Receive Clock 20 9 21 RXD2 BB 3 Port 2 Receive Data 22 16 23 DTR2 CD 20 Port 2 Data Terminal Ready 24 23 25 TXD2 BA 2 Port 2 Transmit Data 26 14 27 RTS2 CA 4 Port 2 Request To Send 28 19 29 TXC2 DA 24 Port 2 Transmit Clock 30 11 31 TXCI2 DB 15 Port 2 Transmit Clock In 32 12 33 DCD2 CF 8 Port 2 Data Carrier Detect 34 10 Pinouts 127 Chapter 6 Pinouts and Rear Transition Modules Table 6 2 RS 232C Connector Pin Assignments Continued a RS 232C grin Sol LM Pin No 35 DSR2 CC 6 Port 2 Data Set Ready 36 22 37 CTS2 CB 5 Port 2 Clear To Send 38 GND2 AB 7 Port 2 Signal Ground 39 RXC2 DD 17 Port 2 Receive Clock 40 9 41 RXD3 BB
88. EVIO AD58 AD57 GND 6 AD63 AD62 AD61 GND AD60 GND 5 CEB5 64EN EVIO CBE4 PAR64 GND 4 EVIO RSVD NC CBE7 GND CBE6 GND 3 NC GND NG NG NG GND 2 NG NG NG NC NG GND 1 NG GND NG NC NG GND Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com J3 Connector Pinouts RS 422 RS 449 RS 530 Table 6 15 J3 RS 422 RS449 RS 530 Signal pinouts Pinouts Pin A B C D E F 19 GND GND GND REAR1_LED REAR2_LED GND 18 ETHTX1 ETHTX1 GND NC NC GND 17 ETHRX1 ETHRX1 GND NC NC GND 16 ETHTX2 ETHTX2 GND NC NC GND 15 ETHRX2 ETHRX2 GND NC NC GND 14 GND GND GND 3 3V 3 3V GND 13 GND GND GND GND GND GND 12 TXD7 TXC7 TXCI7 RXD7 RXC7 GND 11 TXD7 TXC7 TXCI7 RXD7 RXC7 GND 10 RTS7 DCD7 DSR7 CTS7 DTR7 GND 9 RTS7 DCD7 DSR7 CTS7 DTR7 GND 8 TXD6 TXC6 TXCI6 RXD6 RXC6 GND 7 TXD6 TXC6 TXCI6 RXD6 RXC6 GND 6 RTS6 DCD6 DSR6 CTS6 DTR6 GND 5 RTS6 DCD6 DSR6 CTS6 DTR6 GND 4 TXD8 TXC8 TXCI8 RXD8 RXC8 GND 3 TXD8 TXC8 TXCI8 RXD8 RXC8 GND 2 RTS84 DCD8 DSR8 CTS8 DTR8 GND 1 RTS8 DCD8 DSR8 CTS8 DTR8 GND These signals bypassed to ground with 1uf capacitor Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 149 Chapter 6 Pinouts and Rear Transition Modules 150 Table 6 16 and Table 6 17 reflect the adjus
89. FCC2 RxD 2 MII PB18 FCC2 RxD 3 MII PB17 PB16 PB15 SCC2 RXD PB14 SCC3 RXD PB13 PB12 SCC2 TXD PB11 PB10 PB9 PB8 SCC3 TXD 178 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 8 MPC8255 Parallel Port Pin Utilization Table 8 2 Master MPC8255 Port B Pin Assignments Continued Pin Pin Function PPARB 1 PPARB 0 PSORB 0 PSORB 1 PDIRB 1 Out PDIRB 0In PDIRB 1 Out PDIRB 0 In Out PDIRB 1 Out PDIRB 0 In PB7 DSR1 PB6 DSR2 PB5 DSR3 PB4 DSR4 Master MPC8255 Port C Pin Assignments Table 8 3 defines the Master MPC8255 s Port C Pin assignments Table 8 3 Master MPC8255 Port C Pin Assignments Pin Pin Function PPARC 1 PPARC 0 PSORC 0 PSORC 1 PDIRC 1 Out PDIRC 0 In PDIRC 1 Out PDIRC 0 In Out PDIRC 1 Out PDIRC 0 In PC31 SCC2 TX_CLK BRG1 output PC30 PC29 SCC1 SCC1 TX CLK TX CLK CLK3 input BRG2 output PC28 SCC1 RX_CLK CLK4 input PC27 SCC3 TX CLK SCC3 CLK5 input TX CLK BRG3 output PC26 SCC3 RX CLK CLK6 input PC25 SCC4 TX CLK SCC4 CLK7 input TX CLK BRG4 output PC24 SCC4 RX CLK CLK8 input PC23 FCC1 PHY1_TX_CLK PC22 FCC1 PHY1 RX CLK PC21 SCC2 TX CLK CLK11 input PC20 SCC2 RX CLK CLK12 input 174 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SO
90. H and Ports 5 8 and address base 87H before the Slave MPC8255 can initialize and run A bit to read back the state of the Slave MPC8255 s ISRESET output is provided to permit the Master MPC8255 to monitor when the Slave MPC8255 s 512 clock cycle extension of its software reset is complete With the led_jmpr K10 connected 1 2 hardware controlled activity indication by the LEDs is enabled PSM554 monitors the Transmit Data and Receive Data lines of each port for transitions If a rising edge occurs this event is captured Timed by a low frequency clock an individual port LED will illuminate GREEN if transmit activity is detected The LED will illuminate YELLOW if receive activity is detected If simultaneous transmit and receive activity are seen the LED will illuminate GREEN Table 4 72 LED Mode Slave Reset Control Register Bit Fields MPC8255 Bit 0 MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 0 LSB Field led_jmpr_1_4 RESERVED spq_sreset slv_sreset_1_4 led_jmp_5 8 slv sreset 5 8 Reset Value Current Value 0H Current Value 1 R W READ ONLY R W Address Base 77H 87H Table 4 73 LED Mode Slave Reset Control Register Bit Field Definitions Bits Name Description 0 slv_sreset_1_4 0 Slave MPC8255 Software Reset control bit not asserted slv sreset 5 8 1 Slave MPC8255 Software Reset control bit asserted 1 Spq sreset 0 Slave MPC8255 Software Reset p
91. ISB gt BR7 0 Timekeeper SRAM Initialization slaveISB gt OR8 Oxffff8e54 slaveISB gt BR8 0x20300811 SMB PIC Initialization slaveISB gt OR9 Oxffff8e54 slaveISB gt BR9 0x20400811 PowerSpan Initialization Boot PROM Initialization The PowerSpan responds to MPC8255 bus cycles at address 0x30000XXxX following power on reset PSPAN_BASE gt P1_ID DID 0x3580 device ID PSPAN_BASE gt P1_ID VID 0x1214 vendor ID PSPAN_BASE gt P1_SID SID 0x3580 device ID PSPAN_BASE gt P1_SID SVID 0x1214 vendor ID 109 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 5 Boot PROM and Forth Monitor PSPAN_BASE gt P1_CLASS BASE 0x07 PSPAN_BASE gt P1_CLASS SUB 0x80 PSPAN_BASE gt P1_CLASS PROG 0x00 if char 0x2000004d Oxf PSPAN_BASE gt P1_CLASS RID 0x00 else PSPAN_BASE gt P1_CLASS RID char 0x2000004d amp Oxf PSPAN_BASE gt P1_TIO_TADDR TADDR 0x00000000 put SDRAM in target image 0 PSPAN BASE gt P1 TIO CTL TA EN 1 PSPAN BASE 5P1 TIO CTL BS 8 ask for 16M PSPAN BASE gt P1 TIO CTL BAR EN 1 PSPAN BASE gt P1 TI1 CTL BAR EN 0 PSPAN BASE gt P1 TI2 CTL BAR EN 0 PSPAN BASE gt P1 TI3 CTL BAR EN 0 PSPAN BASE gt IDR P1 HW DIR 1 make P1 INTA an output Contact Performance Tec
92. In Gives System Management Bus SMB micro controller access to the CARD_PWR signal permitting backend power Out Allows another power on control signal source K45 1 2 In PCI Bus signals BD_SEL and CT_EN both must be asserted before backend power is applied to the board Out Allows another power on control signal source 40 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Jumpers and DIP Switches Table 3 1 Jumpers Continued In Out Jumper Pins default Function K46 1 2 In No external controller is necessary power always on Out Allows another power on control signal source K47 1 2 In Connect chassis ground to digital ground 2 3 In Isolate chassis ground from digital ground Rear Transition Module Ethernet Routing and Ground The Rear Transition Module has two Ethernet port connections that can be set to exit either through a pair of RJ 45 connectors mounted on the rear panel or through the J3 backplane connections There are also two LEDs one for each port They indicate no connection when off a link condition when on in a steady state condition and traffic on the link when blinking Table 3 2 and Table 3 3 show the jumper settings for Port A and Port B options Table 3 2 Routing Jumpers for Ethernet Port A 3 In Out 3 Jumper Pin default Function K1 1 2 In Rear Exit
93. Interface 12C Interface CompactPCI Host Port Interface Software PMI Port Interface Software IPMI IPMB Figure 7 1 CompactPCl SMB Block Diagram System Board omputer feseudued liggiedwog BMC IPMI U IPMB I C 3 U CompactPCl Peripheral CompactPCl Peripheral 156 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Intelligent Platform Management Interface IPMI Intelligent Platform Management Bus IPMB The CPC358 PM implementation utilizes a single IPMB IPMBO that resides on the CompactPCI backplane connector P1 This bus is based on the I2C hardware layer and uses Master Write transactions only The Baseboard Management Controller BMC normally sends and receives IPMI messages over the IPMB though the Get Message and Send Message commands The IPMI commands Requests and Responses pass between controllers on this IPMB IPMB Slave Addresses are determined by the CompactPCI Geographical Address assignment Table 7 1 below shows the mapping of Geographical Address and IPMB Slave Address Table 7 1 IPMB Slave Address Map Geographic Address IPMB Address Geographic Address IPMB Address 0 Disabled 16 DOh 1 Boh 17 D2h 2 B2h 18 D4h 3 B4h 19 D6h 4 B6h 20 D8h 5 B8h 21 DAh 6 BA
94. K pyy RA FCC2 MIIRX DV RXDV caeso ML E LED1 TX ACT ACTIVITY EB LED BLINK AND gt MDC LED2 RX ACT OGIC PAL qo REAR gt MDIO LED3 LINK LINK gt E LEDS PHY2 INT INT ISOLATE MII 2 94 ISODEF PHY2 RESET RESET IN apne Table 4 26 CS8952 Configuration Pins Signal Description RX EN Receive Enable Pulled high internally to enable MII bus receive signals 10BT SER 10Mb s Serial Mode Select Pulled down internally to select 4 bit parallel MII bus data ANO Auto Negotiate Control 0 These are left floating to select the maximum capability of 100 AN1 Auto Negotiate Control 1 or 10 Mb s Auto Negotiation enabled full or half duplex BP4B5B Bypass 4B5B Coders Pulled down internally so that 4B5B coding is NOT bypassed Some repeaters use a five bit mode faster Most network interface cards use four bit encoded data BPLDIGN Bypass Alignment Pulled down internally so that alignment is NOT bypassed BPSCR Bypass Scrambler Pulled down internally so that scrambler is NOT bypassed The scrambler is bypassed for 100BASE FX fiber optic only 75 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description 76 Table 4 26 CS8952 Configuration Pins Continued Signal Description ISODEF Isolate Default This is a programmable bit from the MISC register Set high to is
95. LED Control Register The Port 1 2 5 6 Status LED Control Register controls the Green Yellow Port 1 5 and Green Yellow Port 2 6 status LEDs in LED array D2 D3 The register controls whether the LEDs are on or off and what color the bi color LEDs will show Note that the default state on a PQ_SRESET is the LEDs off Table 4 66 Port 1 2 5 6 Status LED Control Register Bit Fields MPC8255 Bit O MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 0 LSB Field yel1 RESV yel2 RESV ygoff1 RESV ygoff2 RESV yel5 yel6 ygoff5 ygoff6 Reset Value 0 0 0 0 1 0 1 0 R W R W R R W R R W R R W Address Base 74H 84H Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 99 Chapter 4 Functional Description 100 Table 4 67 Port 1 2 5 6 Status LED Control Register Bit Field Definitions Bit Name Description 0 RESV Always 0 1 ygoff2 A 1 in this bit position turns off the Port 2 6 Status LED This bit setting will turn off the LED ygoff6 regardless of the status of the yel2 yel6 bit A 0 in this bit position will enable the yel2 yel6 bit to turn on the LED and show one of the two LED colors available to the LED 2 RESV Always 0 3 ygoff1 A 1 in this bit position turns off the Port 1 5 Status LED This bit setting will turn off the LED ygoff5 regardless of the status of
96. NA 28 Rear Transition Module Options a aaa paa aaneen 29 BAET ee ee eee ee dt ee eee ere eer eee er eee AO ee 29 Mechanical EE 29 Form Factor eee 29 CompactPCI Connectors e baca enten ie OR e REX n enb ace tein eben kes 29 Front Panel sur steen cete Pe a GNG NOD ANA ed Qo Ve ware S 30 OOGA INSEE ete xo dodo cow EVO aE ee YE EE he ee ee a icut 30 Ethernet Ports suceda eX ERG aS kan REO GR EGO REGE ROR REOR RUE Ee C RR Na da 30 Ethernet PHY o 30 Ethernet MII Management 2 2 00 cee I nne 30 Ethernet Status Indicators s aar rear neben AA 30 Diagnostic Facilities an aten AR eke een EYE LES LI SI eet ene ar e 30 Power On Confidence POG iesu so wapdkR S eR haa seen RA ERR ER GA wen beads 31 Model Designations PDT 31 Chapter 3 Installation 33 Working with the CROSS sorprende Sew eevee ERE 33 Installing the CPC358 ssa ssa RR RR we A te aed eee AA 33 Removing the CPC358 utes das o x ena ee edd aoc dees ee cae poc Re eoe E d OR 34 LEDS 25222222952 225E Sacra a cure PAA id das a dd EU dira dread as 35 Jumpers and DIP Switches sempre odes ever b Ro RE pne Sono dra pa RU pew Edese 38 cres ss cera rra PR a ee as ed 38 dilag AA PG AR AS po eene E 38 Rear Transition Module Ethernet Routing and Ground a 41 Reset and Abort eee 42 Chapter 4 Functional Description 43 Power DISIMDULON sn remote veen acne tiek a abled tls wha a bee deka eas 44 Reset LOGIC issus toad PDA Menke DID babba aah eae hed td Pa ea 46 Power ON AeSe asma
97. On Off when the card is configured for 1 turns on Controller Power SMB PM control of Power Up See Jumper options in the Installation chapter 4 NC 3 HOT_SWAP_LED Controls the hot swap LED 0 turns off the Hot Swap LED 1 turns on the Hot Swap LED 2 SMB_FAULT Asserts the SMB Managed FAULT 0 turns off the SMB Managed Fault condition on the board The HEALTHY 1 turns on the SMB Managed Fault signal on the PClbus will be de asserted and the FAULT LED on the faceplate will be illuminated if this bit is set Other conditions may independently create a Fault condition on the board such as POC Failure Watchdog Timeout or Integrity Test Failure 1 SMB_RESET Asserts the SMB Managed reset signal 0 turns off the SMB Reset Signal on the switch This will cause the board 1 turns on the SMB Reset Signal to be reset if the option is enabled see Jumpers on page 38 0 NC Note that if the board should also be taken offline then the SMB_RESET bit should be set in addition to this bit The Request Message for this command is formatted as in Table 7 19 on page 167 with the addition of two more byte definitions as per Table 7 27 below Table 7 27 Set Card Power State Request Message Byte Request Field Description 7 Card Power State Byte As per Table 7 26 on page 169 8 Checksum 2 Checksum of bytes 4 7 169 Artisan Technology Group Quality Instrumentation
98. PC8255 is in the first 32 bytes of the PROM Its value is 0x14B63246 Slave MPC8255 Rest Configuration Word The Slave MPC8255 is the first configuration slave RSTCONF AO is in the second 32 bytes of the PROM Its value is oxd2658046 105 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 5 Boot PROM and Forth Monitor PowerSpan Reset Configuration Word The PowerSpan is the MPC8255 s second configuration slave RSTCONF A2 It gets a reset configuration word of 0x000d0e0f from the third 32 bytes of the PROM Bootup and Initialization Following reset configuration initialization proceeds as follows Chip Select 0 Boot PROM lis r4 0xff01 Sr4 is the IMMR base address lis r3 0xfff8 ORO ori r3 r3 0x0e64 stw r3 0x104 r4 lis r3 0xfff0 BRO ori r3 r3 0x0801 stw r3 0x100 r4 lis r3 0xb5ft BCR ori r3 r3 0x2010 stw r3 0x24 r4 la Sr3 0x26 ACR st Sr3 0x28 r4 lis r3 0x6701 ALRH ori r3 r3 0x2345 stw r3 0x2c r4 lis r3 0x7655 ALRL OEL r3 r3 0xcdef stw r3 0x30 r4 lis r4 0xf0f1 Sr4 is the slave IMMR base address lis r3 0xffff disable slave watchdog Ori r3 r3 0xff03 stw Sr3 0x4 Sr4 lis r3 0x5224 SIUMCR Slave 0x5224 0000 ori r3 r3 0x0000 stw r3 0x0 r4 lis r4 0xff01 Sr4 is the master IMMR base address li r3 0x556c SWSR sth r3 0xe r4 li r3 0x5
99. PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 181 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 8 MPC8255 Parallel Port Pin Utilization 182 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter A AAN AAA AAA A d IA Agency Approvals This chapter describes product certifications and product safety information Major topics include Safety Precautions on page 183 Certifications on page 184 Compliance with RoHS and WEEE Directives on page 185 Non Performance Technologies Branded Products on page 185 Safety Precautions Performance Technologies recommends that all safety precautions be followed to prevent harm to the user or to the equipment Follow all warnings and instructions marked on the equipment Ensure that the voltage and frequency of your power source matches the voltage and frequency inscribed on the equipment s electrical rating label e Never push objects of any kind through the openings in the equipment Dangerous voltages may be present Conductive foreign objects could produce a short circuit that could cause fire electrical shock or damage to the equipment This equipment contains a lithium SNAPHAT battery as part of the Time of Day clock device located at U2 It is a replaceable device To
100. Parallel Port Pin Utilization This chapter provides an overview of the MPC8255 It includes the following major topics Master MPC8255 I2C Bus on page 171 Master MPC8255 Parallel Port Pin Assignments on page 171 Slave MPC8255 Parallel Port Pin Assignments on page 176 Master MPC8255 I7C Bus There is an I C Bus implemented on two Master MPC8255 port pins They are connected to the IC pins on the SODIMM connector that houses the SDRAM module This bus can be used to retrieve SDRAM setup parameters for memory controller operation The I C bus is implemented using the MPC8255 s internal I2C controller See the following section for the appropriate Master MPC8255 port pins Master MPC8255 Parallel Port Pin Assignments The following sections represent the master MPC8255 parallel port bit configurations for this design Master MPC8255 Port A Pin Assignments Table 8 1 on page 172 defines the Master MPC8255 s Port A Pin assignments 171 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 8 MPC8255 Parallel Port Pin Utilization 172 Table 8 1 Master MPC8255 Port A Pin Assignments Pin Pin Function PPARA 1 PPARA 0 PSORA 0 PSORA 1 PDIRA 1 Out PDIRA 0 In PDIRA 1 Out PDIRA 0 In PDIRA 1 Out PDIRA 0 In PA31 FCC1 COL MIl PA30 FCC1 CRS MII PA29 FCC1 TX ER MII PA28
101. Q6 A21 Slave MPC8255 jumper selectable for either the SPQ INT OUT interrupt signal K7 1 2 parallel I O port pin PAO signal K7 2 3 RQ7 E20 Ethernet PHY1 PCO AB26 System Management Bus Controller Chip Interrupt PC1 AD29 Time of Day Interrupt PC2 AE29 Ejector Switch Interrupt 55 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description Table 4 14 Master MPC8255 Interrupt Sources Continued IRQ Level Pin Number Controlled Device PC3 AE27 Ethernet PHY2 PC4 C21 PowerSpan General Interrupt 3 Slave MPC8255 Interrupt Sources When the Slave MPC8255 has its core disabled it is not able to service any of its internal or external interrupts by itself The external interrupts IRQO 7 NMI and PortC0 15 although configured and connected to the internal Interrupt Controller are pulled false and not used in this design The internal peripheral interrupts are connected to the Interrupt Controller but do not connect to the disabled Power PC interrupt vector generation logic Instead the Interrupt Controller s output is brought out on the INT_OUT line and tied to the Master MCP8255 s IRQ6 input Refer to the individual component subsections or the component s user manual for the complete breakdown of interrupt causes Master MPC8255 Local Bus Connections The Master MPC8255 Local Bus is configured to be a loc
102. R p2 DTR gt NG tt DCDn gt Tin lt PORTn CD D3 gt T i DCDn O X O XX O aa ENG DSRn gt gt 4 PORTn DSR lt R T gt SS DSRn O X O XX 0 3 de Pp k CTSn gt gt lt PoRTn CTS R3 T x CTs O X O XX 0 D FET SWITCH v E V lt PORTn LT 05 DO LTn LE p B Pe O lt R1 TM DN PORTn RI Do DO e L PORTn MODE 0 mo PORTn MODE 1 mi PORTn MODE 2 m2 LTC2846 Y PpORTn DTE DCE A Be P XO R1 ag PORTn SHDN xmit EN PORTn DTE DCE ENABLE MAX3221E 78 Artisan Technology Group Quality Instrumentation OKK XX Enabled for V 35 X All Other Protocols Guaranteed 888 88 SOURCE www artisantg com Serial I O Interface Clock Steering DTE Mode The Receive Clock is always an input to the MPC8255 see Figure 4 10 You can select either the Receive Clock off the port connector pin or use the optionally installed oscillator The Transmit Clock is a bidirectional signal on the MPC8255 There are two selections The first is use the MPC8255 Transmit Clock as an output It gets sent out to the port connector pins The TXCI clock coming in from the DCE is ignored in this mode Secondly use the MPC8255 Transmit Clock as an input The TXCI is received from the DCE and sent to the MPC8
103. RS 449 DTE or DCE RS 530 DTE or DCE V 35 DTE or DCE Programmable Termination for those signals and standards that require it One cable connection for each 4 port group pinned out using the Performance Technologies common standard used on the PCI334 CPC334 CPC340 H CPC344 CPC348 and PCI344 Each connector is an 80 pin connector with access on the front panel or Rear Transition Module Cables supported RS 232 DTE Hydra Cable RS 449 DTE Hydra Cable RS 530 DTE Hydra Cable V 35 DTE and DCE Hydra Cable Each SCC supports software programmable clock steering on a port by port basis Transmit clock for each port can be sourced from the line interface for that port or from the SCC for that port Receive clock can be sourced from the line interface or an optional crystal source unpopulated 1 2 size can position for odd frequencies Hot Swap CompactPCI interface conforming to PICMG 3 0 Core Spec and PICMG 2 16 Packet Switching Backplane Serial Management Controller SMC communication UART for front panel console function RJ11 Dual 10 100 Ethernet MACs with external PHYs conforming to PICMG R2 16 format Supports out of band signaling via 10 100 Ethernet links Support for PICMG 2 9 System Management Bus Supports Telecom J4 connector for shelf address and CT Bus cardfile control not part of standard product General Purpose DIP switches Mictor connectors for board debug support not part of standard pro
104. Replaceable Unit FRU Inventory commands for the Board and Product FRU Inventory Area A set of vendor specific OEM commands are also provided to allow custom System Management Software to control reset and power functions of the card assembly Control and Status signals unique to the CPC358 such as POWER_GOOD P1_BDSEL CONTROLLER_POWER HEALTHY HOT SWAP LED and EJECTOR SWITCH are made available through these OEM commands Custom System Management Software can be written to monitor the state of these signals as well as drive some of them such as HOT SWAP LED and CONTROLLER POWER Further descriptions of these signals can be found in OEM Vendor Specific Commands netFn 0x30 0x31 on page 166 Baseboard Management Controller The Baseboard Management Controller BMC is the primary management controller in an IPMI implementation It typically resides on the System Board Computer SBC and provides the intelligence behind the IPMI The BMC manages the interface between the System Management Software and the Platform Management Hardware Firmware to provide monitoring event logging and recovery control Peripheral Management Controller The Peripheral Management Controller PM is a basic intelligent device that responds to mandatory IPM Device commands In the Performance Technologies implementation of IPMI the PM represents the hardware and software needed to provide the following IPMI functions CompactPCI Board Host
105. Synchronous Static RAM SSRAM and the TUNDRA PowerSpan Dual PCI bridge It also controls all of the on board peripheral chips via a buffered data and address bus Master MPC8255 Initial Configuration A great deal of the initialization of the MPC8255 occurs during the hard reset process When the PQ HRESET signal is active the CPU selects its CPU PLL settings and several other initial configuration settings The following sections describe these settings 48 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General CPU Section Master MPC8255 Core Clock and PLL The board uses an MPC8255 with a 233 MHz Power PC Core PPC a 166 MHz CPM anda 66 MHz external 60x multi master bus The chip is supplied with a 66 MHz primary clock input CLKMASTER on the CLKIN input The clock PLL settings to select the core speed are driven into the part by the MODCLOCK lines from the PSM549 PLD logic while the PQ_HRESET signal is active The clock settings are as follows 233 MHz core 166 MHz CPM 66 MHz 60x Bus MODCLOCK 1 3 110 The following core clock configurations settings are suggested for operation with the Performance Technologies default software settings for system clocks refresh timers and baud rate generators Table 4 6 Master MPC8255 System Clock Control Register Bit Field Definitions Bits Name Recommended Setting Description 29 CLPD 0 CPM does not enter low power mode
106. TE DCE Control 1t uk Gaede behets RENO RE RR a EO RC Ra RR 80 General Purpose Registers scio kk ERE RR ER venetie a pe ees 81 PSM552 General Purpose Registers ooooooccoccccoocc 83 PSM553 General Purpose Registers eneen 91 PSM554 Port Control Registers zor KANG idad whet 93 System Management BIIS z 522 5 0 59 O LE Ee boots oi bebo kh AKALA GODS tone eh ees 103 Chapter 5 Boot PROM and Forth Monitor 105 Boot PROM Initializati N och a cene e en er EROS nedbet ne e hea 105 ReSECCONTIQUIAUON zo ek dara E RH RR REC REOR EFVEZRETENA bee POR SESE REESE E ESS 105 MPC8255 Reset Configuration Word neee 105 Slave MPC8255 Rest Configuration Word oenen 105 PowerSpan Reset Configuration Word 0 0 cee eee 106 Bootup and Initialization 2 2 esasi iee posed emo i a pis ac Ric Rod RR fco apo eo eee 106 Hot Swap High Availability System Support n aeea a 110 Resources Used by the Monitor oooooococoororee es 110 Boot PROM sanneke Rao dee SCRI ky Ecke eR SOC Rie E E RCNH e CR ed a 110 SDRAM sito tner UD A E e a a O 110 Console PON sicario Aa 110 POMC ONS weer vett PER GE E Es ME AMUSE AY 110 Power On Checks and POC Signature 0 000 tees 111 Host PCI Communication Interface eneen een 111 egg AA AA AA 112 Foni GONSDE KN KINANG LABAN PAANO Geet opende 112 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www a
107. Table 4 65 Transmit Clock Steering Control Register Bit Field Definitions DCE rs Bit Name Description 0 tcsl1 0 Transmit Clock TXC1 5 is sourced from MPC8255 Transmit Clock pin TXCLKIN 1 5 PIN tcsI5 MUST BE PROGRAMMED AS OUTPUT 1 Transmit Clock TXC1 5 is sourced from the external oscillator OPTCLK OPTCLK is also driven back to the MPC8255 Transmit Clock pin as TXCLKOUT 1 5 PIN MUST BE PROGRAMMED AS INPUT 1 tcsl2 0 Transmit Clock TXC2 6 is sourced from MPC8255 Transmit Clock pin TXCLKIN 2 6 PIN tcsl6 MUST BE PROGRAMMED AS OUTPUT 1 Transmit Clock TXC2 6 is sourced from the external oscillator OPTCLK OPTCLK is also driven back to the MPC8255 Transmit Clock pin as TXCLKOUT 2 6 PIN MUST BE PROGRAMMED AS INPUT 2 tcsl3 0 Transmit Clock TXC3 7 is sourced from MPC8255 Transmit Clock pin TXCLKIN_3 7 PIN tcsl7 MUST BE PROGRAMMED AS OUTPUT 1 Transmit Clock TXC3 7 is sourced from the external oscillator OPTCLK OPTCLK is also driven back to the MPC8255 Transmit Clock pin as TXCLKOUT 3 7 PIN MUST BE PROGRAMMED AS INPUT 3 tcsl4 0 Transmit Clock TXC4 8 is sourced from MPC8255 Transmit Clock pin TXCLKIN_4 8 PIN tcsl8 MUST BE PROGRAMMED AS OUTPUT 1 Transmit Clock TXC4 8 is sourced from the external oscillator OPTCLK OPTCLK is also driven back to the MPC8255 Transmit Clock pin as TXCLKOUT 4 8 PIN MUST BE PROGRAMMED AS INPUT Port 1 2 5 6 Status
108. Tundra web site search for the following documents in the PowerSpan Design Support Tools section which are current at the time of this release 80A1000 FB001 04 pdf PowerSpan Feature Brief 80A100B ANOO1 01 pdf PowerSpan CA91L8200 as a PCI to PCI bridge 80A100A ANOO1 01 pdf PowerSpan CA91L8200 MPC8255 Connection Application Note 80A1000 EROO1 06 pdf PowerSpan CA91L8200 CA91L8260 Device Errata and Design Notes 80A1000_MA001_08 pdf PowerSpan CA91L8260 CA91L8200 PowerPC to PCI Bus Switch Manual PowerSpan Reset Configuration Word The Master MPC8255 system provides support for a single Configuration Master and up to seven Configuration Slaves In the CPC358 the Master MPC8255 is setup to be the configuration master During the assertion of HRESET the Configuration Master Master MPC8255 supplies the appropriate address and control lines to the Boot Flash to allow the configuration words to appear on the 60x bus The Configuration Slaves are then responsible for capturing the appropriate configuration word for their position in the chain A total of seven 64 bit words are transferred over the data bus One of Address 0 6 lines is strobed to transfer each word The PowerSpan acts as a Configuration Slave because the following conditions have been preset by hardware PB RSTCONF connected to one of 60x bus Addresses 0 6 PB RST connected to 60x bus HRESET PB D 0 31 connected to 60x bus D 0 31 72 Artisan Technology Group Qua
109. URCE www artisantg com Table 8 3 Master MPC8255 Port C Pin Assignments Continued Master MPC8255 Parallel Port Pin Assignments Pin Pin Function PPARC 1 PPARC 0 PSORC 0 PSORC 1 PDIRC 1 Out PDIRC 0In PDIRC 1 Out PDIRC 0 In Out PDIRC 1 Out PDIRC 0 In PC19 FCC2 PHY1 TX CLK PC18 FCC2 PHY1 RX CLK PC17 PC16 PC15 SCC1 CTS PC14 SCC1 CD PC13 SCC2 CTS PC12 SCC2 CD PC11 SCC3 CTS PC10 SCC3 CD PC9 SCC4 CTS PC8 SCC4 CD PC7 PC6 PC5 PC4 TUNDRA_INT PC3 PHY2_INT PC2 ES INT PC1 TOD INT PCO SMB_INT 175 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 8 MPC8255 Parallel Port Pin Utilization Master MPC8255 Port D Pin assignments Table 8 4 defines the MPC8255 s Port D Pin assignments Table 8 4 Master MPC8255 Port D Pin Assignments Pin Pin Function PPARD 1 PPARD 0 PSORD 0 PDIRD 1 Out PDIRD 0 In PSORD 1 PDIRD 1 Out PDIRD 0 In Out PDIRD 1 Out PDIRD 0 In PD31 SCC1 RXD PD30 SCC1 TXD PD29 SCC1 RTS PD28 PD27 PD26 SCC2 RTS PD25 PD24 PD23 SCC3 RTS PD22 SCC4 RXD PD21 SCC4 TXD PD20 SCC4 RTS PD19 DTR1 PD18 DTR2 PD17 DTR3 PD16 DTR4 PD15 12C 12CSDA PD14 12
110. UT The ITOD RST OUT signal is a watchdog timer timeout signal that is part of the functionality of the Time Of Day timer M48T59Y If the watchdog timer is activated in the part and set to cause a pulse on the RST output the ITOD RST OUT signal is generated if the watchdog expires 46 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Reset Logic Soft Reset The soft reset for the board is accomplished by asserting the PQ_SRESET signal The signal is distributed to the MPC8255s PSM552 PLD PSM553 PLD PSM554 PLD and the COP8 JTAG header for the debug port The signal sources for PQ SRESET include the MPC8255 and the PSM552 PLD logic The MPC8255 will assert this signal in response to any power on reset or hard reset condition The effect of soft reset on the processor is different than power on reset or hard reset and is outlined in the Motorola MPC8255 User s Manual in the RESET chapter Logic inside the PSM552 PLD will also assert the PQ_SRESET signal when the Tundra PowerSpan chip asserts a level 5 interrupt This mechanism is used to let the system host cause a soft reset to the board under the control of the system software This feature is only active when the PQ_HRESET signal is inactive and the Reset Configuration jumper K16 is in the Normal Position K16 2 3 Tundra PowerSpan Resets The Tundra PowerSpan has two sources of Reset It can both receive and so
111. V 35 103 M 34 P 42 TXD B 3 7 Input 100 Ohms differential V 35 Transmit Data port 3 or 7 125 Ohms to ground V 35 103 M 34 S 43 DSR3 7 Output NA V 35 Data Set Ready port 3 or 7 V 35 107 M 34 E 45 RXD A 3 7 Output NA V 35 Receive Data port 3 or 7 V 35 104 M 34 R 46 RXD B 3 7 Output NA V 35 Receive Data port 3 or 7 V 35 104 M 34 T 47 CTS3 7 Output NA V 35 Clear To Send port 3 or 7 V 35 106 M 34 D Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table 6 6 V 35 Signals and Pins DCE Continued Pinouts Pin Am No Signal Name Direction Termination Description 48 GND3 7 NA V 35 port 3 or 7 Signal Ground V 35 102 M 34 B 49 TXC A 3 7 Output NA V 35 Transmit Clock port 3 or 7 V 35 113 M 34 V 50 TXC B 3 7 Output NA V 35 Transmit Clock port 3 or 7 V 35 113 M 34 X 51 TXCI A 3 7 Output NA V 35 Transmit Clock In port 3 or 7 V 35 115 M 34 Y 52 TXCI B 3 7 Output NA V 35 Transmit Clock In port 3 or 7 V 35 115 M 34 AA 53 DCD3 7 Output NA V 35 Data Carrier Detect port 3 or 7 V 35 109 M 34 F 54 RI3 7 Output NA V 35 Ring Indicator port 3 or 7 V 35 125 M 34 J 55 DTR3 7 Input 5K Ohms to ground V 35 Data Terminal Ready port 3 or 7 V 35 108 M 34 H 56 LT3 7 Output NA V 35 Line Test port 3 or 7 V 35 M 34 K 57 RTS3 7 Input 5K Ohms to ground V 35 Request To Send port 3 or 7 V 35 105 M 34 C
112. Vee ee eis Hee lad anes vete 153 Table 7 1 IPMB Slave Address Map neee eeen 157 Table 7 2 Supported Network Function Codes eneen 158 Table 7 3 IPM Device Request Commands Message Format 159 Table 7 4 IPM Device Response Message Format eee 159 Table 7 5 Get Device ID Response Message eenen eee eee 160 Table 7 6 Get Self Test Results Response Message 0a 161 Table 7 7 Set ACPI Power State Request Message 162 Table 7 8 Get ACPI Power State Response Message eee eee 162 Table 7 9 Broadcast Get Device IP Request Message eneen 163 Table 7 10 FRU Inventory Device Request Formats cee eee 163 Table 7 12 FRU Inventory Layout i is sez RE waded aye a RAE 164 Table 7 13 Get FRU Inventory Area Request Commands eee eee eee 164 Table 7 11 FRU Inventory Device Response Formats eeen 164 Table 7 14 Get FRU Inventory Area Response Message 165 Table 7 15 Read FRU Inventory Data Request Commands 165 Table 7 16 Read FRU Inventory Data Response Message 000 a 165 Table 7 17 Write FRU Inventory Data Request Commands 166 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 15 Tables Table 7 18 Table 7 19 Table 7 20 Table 7 21 Table 7 22 Table 7 23 Table 7 24 Table 7 25 Table 7 26 Table 7 27 Table 7 28 Table 7 29 Table 7 30 T
113. XC3 DD A 17 Port 3 Receive Clock 60 RXC3 DD B 9 Port 3 Receive Clock N A Shield Shield 1 Port 3 See Note 61 RXD4 BB A 3 Port 4 Receive Data 62 RXD4 BB B 16 Port 4 Receive Data 63 DTR4 CD A 20 Port 4 Data Terminal Ready 134 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Pinouts Table 6 4 EIA 530 Connector Pin Assignments Continued PinNo Name Mnemon Pinno Deseription 64 DTR4 CD B 23 Port 4 Data Terminal Ready 65 TXD4 BA A 2 Port 4 Transmit Data 66 TXD4 BA B 14 Port 4 Transmit Data 67 RTS4 CA A 4 Port 4 Request To Send 68 RTS4 CA B 19 Port 4 Request To Send 69 TXC4 DA A 24 Port 4 Transmit Clock 70 TXC4 DA B 11 Port 4 Transmit Clock 71 TXCI4 DB A 15 Port 4 Transmit Clock In 72 TXCI4 DB B 12 Port 4 Transmit Clock In 73 DCD4 CF A 8 Port 4 Data Carrier Detect 74 DCD4 CF B 10 Port 4 Data Carrier Detect 75 DSR4 CC A 6 Port 4 Data Set Ready 76 DSR4 CC B 22 Port 4 Data Set Ready 77 CTS4 CB A 5 Port 4 Clear To Send 78 CTS4 CB B 13 Port 4 Clear To Send 79 RXC4 DD A 17 Port 4 Receive Clock 80 RXC4 DD B 9 Port 4 Receive Clock N A Shield Shield 1 Port 4 See Note Note There is a shield conductor the shield connects the metal shell of each 25 pin D Sub connector together It also connects to pin 1 of each 25 pin D Sub connector This provides a
114. a cable supporting V 35 as a DCE Data Communications Equipment connection The ports will also be able to support a tri state mode on an individual port basis See Figure 4 9 Serial I O Port Block Diagram on page 78 77 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description Figure 4 9 Serial I O Port Block Diagram Charge Pump and Voltage Boost Regulator Q t TXDn gt gt E P OR Tn TXD or gt I Oo TXDn gt Q t TXCn gt PORTn SCTE D2 gt T E TXCn gt d n Ng to TXCIn gt PORTnTXC p3 gt E 4 TXCIn gt A A TP 4 PORTn SCTE lt Rt 5 DCE_DTE 1 Ot RXCn A lt lt PORTn RXC A R2 All 5 RXCn lt lt 0 4 RXDn 4 pORTn RXD T PORTn MODE 0 mo RXDn PORTn MODE 1 m POR Tn MODE 2 ma LTC2846 PORTn DTE DCE veo Nob vec voo RTSn gt PORTn RTS D1 P gt LA RTSn O X Oo o SO DTR Se PORTn DT
115. able 8 1 Table 8 2 Table 8 3 Table 8 4 Table 8 5 Table 8 6 Table 8 7 Table 8 8 Write FRU Inventory Data Response Message eee eee eee 166 Common OEM Request Commands 0000 cece eee eee eee 167 Common OEM Response Commands cece eee eee eee eae 167 Diagnostic Echo Request Commands eeen 167 Diagnostic Echo Response Message 0000 e cece eee eee eee 168 Bit Assignments for Card Power Status Byte eee 168 Get Card Power Status Request Message 0 eee eee eee 168 Get Card Power Status Response Message 0 eee eee eee 169 Bit Assignments for Card Power State Byte eeen 169 Set Card Power State Request Message 0 eee eee 169 Set Card Power State Response Message s nunana eneen 170 Get Card Power State Request Message 0 eee eee 170 Get Card Power State Response Message nnee 170 Master MPC8255 Port A Pin Assignments cece eee ee 172 Master MPC8255 Port B Pin Assignments 0c eee eee eee 173 Master MPC8255 Port C Pin Assignments oenen eeen 174 Master MPC8255 Port D Pin Assignments 0 cee eee ee 176 Slave MPC8255 Port A Pin Assignments ane 177 Slave MPC8255 Port B Pin Assignments 00 e eee 178 Slave MPC8255 Port C Pin Assignments nnee 179 Slave MPC8255 Port D Pin Assignments liliis leeren 181 Artisan Technology Gro
116. age All read erase and program operations are accomplished using only a single power supply Internally generated and regulated voltages are provided for the program and erase operations The device is entirely command set compatible with the JEDEC single power supply Flash standard Figure 4 4 Flash Block Diagram BUF A 0 18 BOOT FLASH EPROM 29LV040 90 512Kx8 BUF AD 0 7 The device is accessed by the Master MPC8255 through the Buffered Data bus The Buffered data bus supplies a buffered 60x bus address and a bi directional 8 or 16 bit data bus The ICS FlashB supplied by the Master MPC8255 acts as the device chip enable The BUF RD supplied by PSM550 PLD logic acts as the device output enable and BUF WR again supplied by the PSM550 logic is the write enable The CPC358 has a write protect feature that will not allow the IBUF WR signal to activate unless the flash wp bit is set in the General Purpose registers The default after reset is to disable writing to the Flash The read and write cycle is timed by the GPCM s wait state programming There is no cycle termination signal generated by the device ICS FLASHB B IBUF_WR gt IBUF RD 8 63 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description Master MPC8255 Related Flash Settings The Master MPC8255 uses its chip select 0 CSO as the CS_FlashB sig
117. agram of CPC358 J3 E opl a 2 J5 z 2 T z RS 232 RS 422 v 35 Programmable Termination eso Two four 3 Transceivers Linear Tech LTC2844 amp 2846 o 2 port Hydra oe 3 E 25 90 0 cables 26 00 no Ss required 5 Sa o t 25 Optional Osc 5 o 3 gt En 18 gt Clock Steering le RS pe RS 422 V 35 S S Front Panel Logic ranscelvers ED LED le ng Display SCC1 4 8 18 Bit Y Buffered 10 100 BaseT PS i gt Ethernet PHY Ed Switches KAP 1 E SCC1 4 18 General Purpose FCC1 CPSB A Logic 10 100 BaseT 2 gt J3 gt General Inputs Ethernet PHY FCC2 Front Panel Zi Console ad Port v Boot FLASH sMct s 512K x 8 MPC8255 MPC8255 Lo Master Slave Application 8 FLASH 32M x 8 Real Time n Clock Local Bus Local Bus y Address and Data bii o Comm Buff Memory Bus Buffer x 64K x 36 60x Power PC Bus 64 Bit To Control and Monitoring Points SDRAM 16M x 64 PPC to CPCI Interface Power Span CA91L8260 SMB CPCI Power Controller Controller A Serial SMB Connection A y Compact PCI 64 Bit 66 MHz y Power Distribution The power distribution network on the CPC358 starts with the contact pins on the CompactPCI backplane The pow
118. al The standard configuration supplied with the Boot Flash is shown in Table 4 7 Table 4 7 Master MPC8255 Hard Reset Configuration Word Settings Bit Position Field oa Description 0 EARB 0 No External Arbitration 1 EXMC 0 Internal Memory Controller Selected as BRO for the Flash 2 CDIS 0 MPC8255 core is enabled 49 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description Table 4 7 Master MPC8255 Hard Reset Configuration Word Settings Continued f En Recommended Bit Position Field Description Setting 3 EBM 1 External Bus Mode is 60x compatible bus mode 4 5 BPS 01 Boot port size is 8 bit 6 CIP 0 Core initial exception vector prefix vectors are prefixed with OxFFFn nnn ISPS 0 Internal Space port size is set to 64 bit 8 9 L2CPC 10 Bus address pins selected for layer 2 cache pin configuration BADDR Pins selected 10 11 DPPC 11 No data bus parity External Bus Grant pins for second and third devices selected and IRQ6 and IRQ7 selected 12 RSVD 0 Reserved must be set to 0 13 15 ISB 110 Base address of the Internal Memory space is OXFFOO 0000 16 BMS 0 Boot memory space OxFEOO 0000 to OxFFFF FFFF 17 BBD 0 Address Bus Busy and Data Bus Busy selected on multifunction pins 18 19 MMR 11 All external bus requests masked 20 21 LBPC 00 Local Bus Pin Co
119. al memory bus This bus is closely coupled to the Master MPC8255 s CPM processor and its most effective use is as memory for the CPM In the CPC358 implementation the bus is configured as a slave device that controls a local memory bus for a bank of Synchronous Static RAM SSRAM The local bus provides address data and control for the SSRAM The cycle control for the SSRAM is provided by the UPMB and the CS2 address space decode The Local Bus multifunction pins are configured for the SSRAM as follows LGPLO LSDA10 is configured as LGPLO and controls the SSRAM output enable signal LCL_OE LGPL1 LSDWE is configured as LGPL1 and controls the SSRAM Address Control Strobe signal ILCL ADSC LGPL2 LSDRAS LOE is configured as LGPL2 and controls the SSRAM Address Advance Strobe signal ILCL ADV LGPL3 LSDCAS is configured as LGPL3 and controls the SSRAM Chip Enable signal LCL_CE The LBSx LSDDQMx LWEx are configured as LBSx and control the SSRAM byte strobes ILCL LBSx The PCI C BEx LCL DPx are configured as DPX and control the SSRAM data parity bits LCL DPx LPL5 and LWR are not used in this design For Details on the SSRAM operation and UPM setup see the SSRAM section Slave MPC8255 Local Bus Connections Unsupported Option 56 The Slave MPC8255 Local Bus is configured to be a local memory bus for a bank of Synchronous Static RAM SSRAM This bus provides address data and control for the SSRAM The cycle control fo
120. al purpose RS 232 communications interfaces Only one is utilized on the CPC358 due to front panel space limitations The two SMCs are full duplex ports that can be configured independently to support one of three operating or modes UART Transparent General Circuit Interface GCI The CPC358 is designed to support UART operation on Master MPC8255 SMC port1 An RJ11 connector located on the CPC358 faceplate provides connectivity to the SMC The connector J8 is designated to be the Console port The console port can be used to provide a debug monitor or download function The console port also has the ability to generate a IPQ HRESET if it receives a RS 232 break signal that lasts for longer than 3 2ms The logic that watches the console receive line is located in the PSM552 PLD The reset on break detect can be enabled by setting jumper K9 1 2 Removing the jumper will disable the reset action See Master MPC8255 Parallel Port Pin Assignments on page 171 for the appropriate Master MPC8255 port pins Fast Ethernet 10 100BaseT on FCC 1 The MPC8255 s FCC 1 is used to support a 10 100BaseT Fast Ethernet connection through its MII Media Independent Interface A Cirrus Logic CS8952 is the PHY interface for this connection This port is designated as port B on the faceplate of the Rear Transition Module The Ethernet I O signal lines and the Link Activity LED status indicator lines are brought out to rear panel CompactPCI connector J3 usi
121. ansceiver Shutdown Control Register Bit Fields Table 4 71 Transceiver Shutdown Control Register Bit Field Definitions Bits Name Description 0 shutdown1 0 Port 1 5 powered up shutdown5 1 Port 1 5 powered down 1 shutdown2 0 Port 2 6 powered up shutdown6 1 Port 2 6 powered down 2 shutdown3 0 Port 3 7 powered up shutdown 1 Port 3 7 powered down 3 shutdown4 0 Port 4 8 powered up shutdown8 1 Port 4 8 powered down MPC8255 Bit O MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 0 LSB Field RESERVED shutdown4 shutdown3 shutdown2 shutdown1 shutdown8 shutdown7 shutdown6 shutdown5 Reset Value OH 1 1 1 1 R W READ ONLY R W Address Base 76H 86H Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 101 Chapter 4 Functional Description 102 LED Mode Slave Reset Control Register The LED Mode Slave Reset Control Register allows software to read the state of the LED mode jumper K10 This one jumper affects all eights ports The register also provides a software reset bit active high for the Slave MPC8255 SRESET pin AF6 After a IPQ SRESET from the Master MPC8255 the Slave MPC8255 is held in reset by the slv sreset 1 4andslv sreset 5 8 bits Software must clear the slv sreset bit in both occurrences of PSM554 for Ports 1 4 at address base 77
122. as 2080 0000h to 2083 FFFF H The Slave MPC8255 CS2 Base Register is set to define the address space as 20A0 0000 to 20A3 FFFF Table 4 21 is a list of recommended Base and Option Register field settings other than the base address and address masks Table 4 21 CS2 Base Register Settings Recommended m Field Description Setting PS 11 32 bit DECC 00 Data Errors checking disabled default WP 0 Read and write accesses are allowed MSEL 101 Machine Select UPMB for Local Bus EMEMC 0 Accesses are handled by the MSEL selected controller No external Memory controller allowed in this space ATOM 00 The address space is controlled by the memory controller bank and is not used for atomic operations DR 0 No data pipelining is done V 1 This bank is valid 70 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CompactPCI Interface The Option Register Settings follow the form outlined for the UPMB Machine Table 4 22 CS2 Option Register Settings Field Pocommengeg Description Setting BCTLD 1 IBCTLx is not asserted upon access to the current memory bank BI 0 This Bank of memory supports bursting EHTR 00 Normal Idle Timing UPMB Table Settings The Master MPC8255 UPMB Table settings are as follows 00 SFFE33000 SFFAFF005 SFFFFFOOO SFFFFFOOO 04 SFFFFFO000 SFFFFFO000 SFFFFF000 SFFFFFO000 08 SFFE33008 SFFACFOOC
123. ause a Master MPC8255 interrupt on the Port C1 line For information on how to setup the clock and watchdog timer please refer to the ST Micro MT48T59 64 Kbit 8Kb x8 TIMEKEEPER SRAM datasheet Communications Buffer Memory The Communications Buffer Memory is used by the Communications Processor Module CPM in the Master MPC8255 The Slave MPC8255 has an identical Communications Buffer Memory unsupported option The memory array is interfaced directly to the 8255 s Local Bus connection The Local Bus interface is tightly coupled to the CPM inside the part making it an ideal resource for use as a high speed buffer memory for data and commands Figure 4 7 Communications Buffer Memory Block Diagram Local Bus Address 29 14 ICS_LOC_RAM gt SYNCHRONOUS ILCL_ADSC STATIC RAM Data Parity 0 4 ILCL_ADV 64Kx36 ILCL OE Local Bus Data 0 31 ILCLCE gt 66Mhz CPU Clock The Communications Memory Buffer is implemented with synchronous static random access SSRAM memory operating at 3 3V 256KB of data are available and organized as 64K x 32 bits of data The flow through device is supported as opposed to the pipelined device 69 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description Individual parity for each byte lane is provided in 64K x 4 bits of memory The default controller setting
124. basis The Receive Clock is always an input to the MPC8255 The Receive Clock can be sourced from the serial port or from an optionally installed external oscillator Table 4 61 Receive Clock Steering Control Register Bit Fields MPC8255 Bit O MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 0 LSB Field RESERVED rcsl4 rcsl3 rcsl2 rcsl1 rcsl8 rcsl7 resl6 resl5 Reset Value OH 0 0 0 0 R W READ ONLY R W Address Base 72H 82H Table 4 62 Receive Clock Steering Control Register Bit Field Definitions Bits Name Description 0 rcsl1 0 Receive Clock RXCLK 1 5 is sourced from the serial port DTE RXC DCE SCTE 1 5 rcsl5 1 Receive Clock RXCLK_1 5 is sourced from the external oscillator OPTCLK 1 rcsl2 0 Receive Clock RXCLK_2 6 is sourced from the serial port DTE RXC DCE SCTE 2 6 rcsl6 1 Receive Clock RXCLK_2 6 is sourced from the external oscillator OPTCLK 2 rcs13 0 Receive Clock RXCLK 3 7 is sourced from the serial port DTE RXC DCE SCTE 3 7 rcs17 1 Receive Clock RXCLK 3 7 is sourced from the external oscillator OPTCLK 3 rcsi4 0 Receive Clock RXCLK 4 8 is sourced from the serial port DTE RXC DCE SCTE 4 8 rcsl8 1 Receive Clock RXCLK 4 8 is sourced from the external oscillator OPTCLK Transmit Clock Steering Control Register The Transmit Clock Steering Control Register is used to s
125. ble termination is provided for those signals and standards that require it Clock Steering Each SCC supports software programmable clock steering on a port by port basis The transmit clock for each port can be sourced from the line interface for that port or from the SCC for that port The receive clock can be sourced from the line interface or an optional crystal source unpopulated Ye size can position for odd frequencies Monitor Port A serial port allows for local access to the card through a standard terminal The SMC port supports ASCII UART communication Electrical The CPC358 is designed to meet the electrical and mechanical requirements of the CompactPCI Specification PICMG 2 0 Revision 3 0 October 1 1999 Universal I O The CPC358 is a universal I O board no key on J1 accepting either 5V or 3 3V for the PCI I O signals Media Connections The CPC358 in the Rear I O configuration provides connectivity to all media interfaces except the monitor port through the midplane J3 and J5 connectors The monitor port is presented at the faceplate via an RJ 11 connector A transition cable is provided to bring this interface out to a standard 25 pin RS 232 connector A factory built Front I O configuration is also available that brings the eight serial ports out through two 80 pin high density connectors on the front panel The Ethernet PHY connections are presented to J3 and the midplane as differential signal pairs that are trans
126. ch command that differs from Table 7 3 or Table 7 4 is defined in other tables under the description of that particular command Table 7 3 IPM Device Request Commands Message Format Byte Request Field Description 1 rsSA Responders Slave Address 2 netFn rsLUN NetFn 0x06 rsLUN 0x00 3 Checksum 1 Connection Header Checksum 4 rgSA Requesters Slave Address 5 rqSeq rqLUN Sequence number and Requesters LUN 6 Command 0x01 Get Device ID 0x02 Cold Reset 0x03 Warm Reset 0x04 Get Self Test Results 0x05 Set Manufacturing Test Mode 0x06 Set ACPI Power State 0x07 Get ACPI Power State 0x08 Get Device GUID 7 Checksum 2 Checksum of bytes 4 5 and 6 Table 7 4 IPM Device Response Message Format Byte Response Field Description 1 rqsA Requester s Slave Address 2 netFn rgL UN NetFn 0x07 rqLUN 3 Checksum 1 Connection Header Checksum 4 rsSA Responder s Slave Address 5 rqSeq rsLUN Sequence number and Responders LUN 0x00 159 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 7 System Management Bus and Intelligent Platform Management Table 7 4 IPM Device Response Message Format Continued Byte Response Field Description 6 Command 0x01 Get Device ID 0x02 Cold Reset 0x03 Warm Reset 0x04 Get Self Test Results 0x06 Set ACPI Power State 0x07 Get ACPI Power State
127. d for interrupts and bank selection of the SDRAM memory 71 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description Since there are multiple 60x bus masters and all of them have internal arbiters one part must be selected as the master The Master MPC8255 is selected as the master and uses its internal arbiter The PowerSpan connections for address bus or data bus requests are programmed to be outputs and are therefore inputs to the 8255 s arbiter The Master MPC8255 sees the Tundra 60x bus registers at 3000_0000 to 3000 Offfh which is the default 60x bus address decode for the Tundra device The CompactPCI P1 connections are designed to be a 64 bit interface and is selectable to be either 33 MHz or 66 MHz configurable by the backplane speed selection pin or forced by jumper K32 Jumper K32 1 2 for 66 MHz or K32 2 3 for 33 MHz CompactPCI Due to a Tundra component problem a circuit modification was included which adds an additional load on the P1 IDSEL line Also the present parts have timing issues with the PCI bus running at 66 Mhz Refer to the following document for explanation from Tundra 80A1000 ER001 06 pdf PowerSpan CA91L8200 CA91L8260 Device Errata and Design Notes For further information reference the following documents available on the Tundra web site for circuit connection description and operation http www tundra com At the
128. d to signal the Hot Swap Controller that the board is healthy or not This bit is logically anded with the inverted power good bit from the power controller IC and the M66EN backplane signal to form the Compact PCI IHEALTHY signal The logic for this bit is contained in the PSM552 PLD If the power good condition is true with this bit set to a 0 the IHEALTHY signal will be false and when set to a 1 the IHEALTHY will indicate true Note that iamok is not used in the Tundra PowerSpan Healthy or SMB Healthy equations in the PSM552 PLD 1 flashwpn When set to a 0 the flashwpn bit will prevent a write cycle to the Application or Boot Flash devices from being affected The write cycle will terminate normally for the MPC8255 but the addressed Flash device will not have its write strobe toggled When this bit is set to 1 write operations will be allowed to the Flash device 2 RESV Always 0 3 ctrmstr This bit reflects the state of jumper K2 When K2 jumper is connected 1 2 the bit will indicate a 0 This setting indicates that the CPC358 is the Reset Master of the CT bus and controls the ICT RESET signal The ICT RESET is controlled with the ctrst bit in the Peripheral Reset Control register When the K2 jumper is connected 2 3 the bit is set to a 1 and the CPC358 cannot assert the ICT RESET signal on the CT Bus CT bus not part of standard product 4 ctbmstr This bit reflects the state of the K4 jumper When the K4 jumper is connected
129. de 0x01 is intended to be used to verify the proper functionality of the IPC Bus and associated PM hardware The Get Card Power Status command Command Code 0x10 returns a byte that contains the status of certain card power signals The Get Card Power State and Set Card Power State commands Command Codes 0x12 and 0x11 respectively are used to actually determine and control the power state of the card On or Off Common OEM Commands 166 Common OEM Command Request Message formats are outlined in Table 7 19 Common OEM Request Commands on page 167 Take note of the command byte 6 which specifies the variable for each specific function All common Response Message functions are defined in Table 7 20 Common OEM Response Commands on page 167 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com OEM Vendor Specific Commands netFn 0x30 0x31 There are slight differences for various commands Each command that differs from Table 7 19 or Table 7 20 is defined in other tables under the description of that particular command Table 7 19 Common OEM Request Commands Request e Byt Description yie Field PERENA 1 rsSA Responder s Slave Address 2 netFn rsLUN NetFn 0x30 rsLUN 0x00 3 Checksum 1 Connection Header Checksum 4 rqsA Requester s Slave Address 5 rqSeq rqLUN Sequence number and Requester s LUN 6 Co
130. dicating that the PCI interface should be disabled The MPC8255 should hold the PowerSpan in reset using the tunrstbit of the P1 Reset Control Register Board ID Registers There are two board ID registers implemented as two consecutive bytes These two bytes are composed of four fields The first byte contains a 2 bit reserved field and a 6 bit Board ID field The second byte contains a 4 bit build option field and a 4 bit revision ID field Board ID Field The CPC358 Board ID field value is 06000101 Board ID values are specified by Document Number 129A000110 Revision Field The board revision field allows the specification of up to 16 revisions of the board This manual corresponds to a CPC358 revision field of value 0b0000 Build Option Field The build option field allows the specification of 16 build options for the board A build option is an option that is specified by the way in which the product is built These are options that cannot be modified in the field Build options are controlled by the Bill of Materials BOM for the product There are two build options for the CPC358 Rear I O and Front I O 89 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description 90 Rear I O means that there are no connectors on the CPC358 front panel other than the serial monitor port A Rear Transition Module RTM is required to bring the signals
131. duct JTAG serial debugger connectors for Master and Slave processor debug Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CPC358 Architecture Overview Front Panel Features Two 80 pin I O connectors for serial ports front panel I O version only One RJ11 RS 232 serial console port Two board status LEDs green yellow red green One green LED for each 10 100 Ethernet port to indicate link and activity One blue Hot Swap LED One green yellow LED for each Serial I O port indicating the electrical standard set for the port group Off RS 232E Green RS 422 449 530 Yellow V 35 Alternatively the LEDs can indicate individual port activity mode jumper selectable all 8 ports as a group with green blinking indicating transmitted data and yellow blinking indicating received data Rear Transition Module Features Two 80 pin connectors for Hydra Serial I O cable connections Optional Dual 10 100 Ethernet connections with integral Link Activity LEDs Passive design e Carries all Serial I O signals on the J3 and J5 connectors CPC358 Architecture Overview An overview of the major functional blocks is provided here Subsequent sections provide more detail Processors The processors used are a pair of MPC8255 PowerQUICC Ils a high performance PowerPC RISC microprocessor with a variety of communications peripheral controllers One of the processors is con
132. e 82 Peripheral Reset Control Register Bit Fields 0 ee 83 Peripheral Reset Control Register Bit Field Definitions 84 Ejector Switch Interrupt Enable Control Register Bit Fields 84 Ejector Switch Interrupt Enable Control Register Bit Field Definitions 84 Ejector Switch Interrupt Status Register Bit Field Definitions 85 Ejector Switch Interrupt Status Register Bit Field Definitions 85 Miscellaneous Status and Control Register Bit Fields 85 Miscellaneous Status and Control Register Bit Field Definitions 86 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table 4 38 Table 4 39 Table 4 40 Table 4 41 Table 4 42 Table 4 43 Table 4 44 Table 4 45 Table 4 46 Table 4 47 Table 4 48 Table 4 49 Table 4 50 Table 4 51 Table 4 52 Table 4 53 Table 4 54 Table 4 55 Table 4 56 Table 4 57 Table 4 58 Table 4 59 Table 4 60 Table 4 61 Table 4 62 Table 4 63 Tables General Purpose Latch Register Bit Fields a 87 Register Bit Field Definitions 2 0 0 eee 87 General Purpose Switch and P1 Reset Register Bit Fields 87 General Purpose Switch and P1 Reset Register Bit Field Definitions 87 P1 Reset Control Register
133. e Clock Steering Control Register Bit Field Definitions 97 Transmit Clock Steering Control Register Bit Fields 98 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 13 Tables Table 4 64 Transmit Clock Steering Control Register Bit Field Definitions DTE 98 Table 4 65 Transmit Clock Steering Control Register Bit Field Definitions DCE 99 Table 4 66 Port 1 2 5 6 Status LED Control Register Bit Fields 99 Table 4 67 Port 1 2 5 6 Status LED Control Register Bit Field Definitions 100 Table 4 68 Port 3 4 7 8 Status LED Control Register Bit Fields 100 Table 4 69 Port 3 4 7 8 Status LED Control Register Bit Field Definitions 101 Table 4 70 Transceiver Shutdown Control Register Bit Fields nanana aaaea 101 Table 4 71 Transceiver Shutdown Control Register Bit Field Definitions 101 Table 4 72 LED Mode Slave Reset Control Register Bit Fields 102 Table 4 73 LED Mode Slave Reset Control Register Bit Field Definitions 102 Table 4 74 CompactPCI SMB to CPC358 SMB Interface een 103 Table 5 1 POC Signaturen suu KERNEL KG PG AKA ER Ra des Se ae 111 Table 5 2 Flash Error Codes i i ox SR DU ARA ADA RR KAG Beken KGG dea eee anaes 117 Table 5 3 NVRAM SUSIE on nG Pa NARRA S
134. e000e64 ISB gt BR3 0x10000801 Bank of Registers Initialization ISB gt OR4 Oxffff8e34 ISB gt BR4 0x20000801 Not assigned ISB gt OR5 0x0 ISB gt BR5 0x0 Not assigned ISB gt OR6 0x0 ISB gt BR6 0x0 Not assigned ISB gt OR7 0x0 ISB gt BR7 0x0 Timekeeper SRAM Initialization ISB gt OR8 Oxffff8e54 ISB gt BR8 0x20300801 SMB PIC Initialization ISB gt OR9 Oxffff8e54 ISB gt BR9 0x20400801 Slave Chip Selects 1 9 Boot PROM slaveISB gt OR1 Oxfff80e64 slaveISB gt BR1 Oxfff00811 108 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SLAVE SRAM Initialization SLAVEISB gt OR2 Oxfffc1000 SLAVEISB gt BR2 Ox20A018a1 SLAVEISB gt MBMR 0x90004440 for p UPMBTable p lt UPMBTable 64 ptt SLAVEISB gt MDR pj volatile char SLAVEISB gt BR2 amp Oxffff8000 0 SLAVEISB gt MBMR 0x80004440 Application Flash Initialization slaveISB gt OR3 Oxfe000e64 slaveISB gt BR3 0x10000811 Bank of Registers Initialization slaveISB gt OR4 Oxffff8e34 slaveISB gt BR4 0x20000811 Use to access Master s SRAM slaveISB gt OR5 Oxfffc1000 slaveISB gt BR5 0x208018b1 Not assigned slaveISB gt OR6 0x0 slaveISB gt BR6 0x0 Not assigned slaveISB gt OR7 0 slave
135. ead and write accesses are allowed MSEL 000 Machine Select GPCM 60x bus EMEMC 0 Accesses are handled by the MSEL selected controller No external memory controller allowed in this space ATOM 00 The address space is controlled by the memory controller bank and is not used for atomic operations DR 0 No data pipelining is done V 1 This bank is valid The Option Register Settings follow the form outlined for the GPCM Machine Table 4 29 CS4 Option Register Settings Field necommendes Description Setting BCTLD 0 IBCTLx is asserted upon access to the current memory bank CSNT 1 ICS WE is negated a quarter of a clock early ACS 11 ICS is output half a clock after the address lines SCY 3 Clock Wait states SETA 0 IPSDVAL is generated by the GPCM TRLX 1 Relaxed timing is generated by the GPCM for this memory region EHTR 00 Normal Idle Timing Once the GPOM initiates the cycle on the 60x bus the logic in the PSM550 PLD then takes the 60x bus input and provides the BUF_ALE BUF_RD and IREG WR signals The logic in the register devices all use the BUF AD 7 0 of the buffered data bus for address decode The buffered data bus provides the requested address on the data bits during the first portion of an access cycle and the address is latched and decoded on the falling edge of the BUF_ALE signal The PSM550 logic then configures the buffered bus to either drive write data or receive read data from the register PLD The IBUF_RD and REG_WR
136. ed for the first 7 bytes as in Table 7 4 on page 159 with the additional response bytes formatted as in Table 7 8 on page 162 Table 7 8 Get ACPI Power State Response Message Byte Response Field Description 8 ACPI System Power State See IPMI Specifications for this command 9 ACPI Device Power State See IPMI Specifications for this command 10 Checksum 2 Checksum of bytes 4 9 Get Device GUID This command directs the Responder to return the Globally Unique Identifier This is a 128 bit identifier set at the factory The Request Message for this command is formatted as in Table 7 3 on page 159 The Response Message for this command is formatted as in Table 7 4 on page 159 Broadcast Get Device ID This is a broadcast version of the Get Device ID command and is used to discover Intelligent Devices on the IPMB The response by the PM to this command is identical to the response from the Get Device ID command in Table 7 4 on page 159 162 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com FRU Inventory Device Commands netFn 0x0A 0x0B The Request Message for this command has a format similar to other Request Messages but the order is different The format of the Broadcast Get Device ID command is as follows Table 7 9 Broadcast Get Device IP Request Message Byte Request Field Description 1 Broadcast Address
137. ees lees KAKA KA ban dae a Ses 118 Table 6 1 Ethernet Connector J3 and J4 Pinout neee 126 Table 6 2 RS 232C Connector Pin Assignments eenen 126 Table 6 3 RS 449 Connector Pin Assignments liliis 129 Table 6 4 ElA 530 Connector Pin Assignments annen 132 Table 6 5 V 35 Connector Pin Assignments eee 136 Table 6 6 V 35 Signals and Pins DCE 2 2 eee 138 Table 6 7 Console Pin Assignments neee eee een 142 Table 6 8 Master JTAG Pinout eneen ee 143 Table 6 9 Slave TAG PINBU vr mwn RE KG Me ceed ms SPARES been Dee EPA x XR RARE 143 Table 6 10 J9 Mictor Pinout 60X Bus Address oen 144 Table 6 11 J10 Mictor Pinout 60X Bux Data lllleeleeeee e 145 Table 6 12 J11 Mictor Pinout 60X Bus Data e 145 14 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Tables Table 6 13 J1 CompactPCI Connections neen 147 Table 6 14 J2 CompactPCI Connections liliis 148 Table 6 15 J3 RS 422 RS449 RS 530 Signal pinouts e ee ee 149 Table 6 16 DTE RS232 Adjustments for J3 AA 150 Table 6 17 DTE V 35 Adjustments ford cis Kwan sees beet Pewee Sis Mord ad anes vette 150 Table 6 18 J4 CompactPCI Connections lisse ene 151 Table 6 19 J5 RS 422 RS 449 RS 530 Signal Pinouts eenen 152 Table 6 20 DTE RS232 Adjustments for J5 eee 153 Table 6 21 DTE V 35 Adjustments tord sis sse zeer eed
138. eld Definitions Bits Name Description 1 stsgoff A1 in this bit position turns off the green General Board Status LED This bit setting will turn off the LED regardless of the status of the stsgrn bit A O in this bit position will enable the stsgrn bit to turn on the LED and show one of the two LED colors available to the LED 3 stsroff A 1 in this bit position turns off the red General Board Status LED This bit setting will turn off the LED regardless of the status of the stsred bit A 0 in this bit position will enable the stsred bit to turn on the LED and show one of the two LED colors available to the LED 5 stsgrn With the stsgoff bit set to a 0 a 0 in this bit position will turn the green General Board Status LED to green and a 1 in this bit position will set the LED to yellow 7 stsred With the stsroff bit set to a O a 1 in this bit position will turn the red General Board Status LED to red and a 0 in this bit position will set the LED to green 91 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description CompactPCI Geographic Address Register The CompactPCI Geographic Address Register contains the 5 bit value of the backplane slot identifier for the slot that the CPC358 is currently plugged into These bits are read from the backplane through the J2 CompactPCI connector and the J4 CT bus connector CT bus not part of standard
139. elect the source of the Transmit Clock on a port by port basis The Transmit Clock pin on the MPC8255 is bi directional Its direction must be programmed based on the Transmit Clock Steering selected It is important to understand that the Transmit Clock In TXCIx changes direction depending on whether the port is configured to be DTE or DCE When the port is DCE the Transmit Clock In from the PSM554 PLD is applied to the transceiver as an input to be driven out the serial port When the port is DTE the Transmit Clock In is received from the serial port by the transceiver as an input and driven to the MPC8255 through the PSM554 PLD Transmit Clock Steering changes mode depending on whether port is configured to be DTE or DCE based on the dte x n bit The DTE allows TXCIx as a selection and DCE allows OPTCLK Two Bit Field tables are provided to cover the DTE and DCE modes 97 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description 98 Table 4 63 Transmit Clock Steering Control Register Bit Fields MPC8255 Bit O MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 O LSB Field RESERVED tcsl4 tcsl3 tcsl2 tcsl1 tcsl8 tcsl7 tcsl6 tcsl5 Reset Value OH 0 0 0 0 R W READ ONLY R W Address Base 73H 83H Table 4 64 Transmit Clock Steering Control Register Bit Field Definitions DT
140. er pins are connected per the CompactPCI Specification PICMG 2 0 R3 0 recommendation The pins are staged per the CompactPCI Hot Swap Specification PICMG 2 1 R1 0 so that Ground makes first and then the various voltages Among them are 3 3V 5V 12 and 12V Table 4 1 Preliminary Typical Board Power Consumption Estimates Voltage Current Power 3 3V 5 0A 16 7W 5V 0 5A 2 4W 12V lt 10mA 0 1W 12V 10mA 0 1W 44 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Power Distribution The power control is accomplished using the LTC1643L Hot Swap controller The LTC1643 allows the board to be safely inserted and removed from a live PCI Bus slot Four external N channel transistors control the 3 3V and 5V supplies while on chip switches control the 12V and 12V supplies All supply voltages can be ramped up at a programmable rate An electronic circuit breaker protects all four supplies against overcurrent faults A foldback current limit feature limits current spikes and power dissipation when shorts occur and allows the board s large capacitances to be powered up without tripping the circuit breaker The PWRGD output indicates when all of the supply voltages are within tolerance and the FAULT output indicates an overcurrent condition The ON pin is used to cycle the board power or reset the circuit breaker The ON pin is controlled by one of several
141. er up reset state and the bit that controls the device in the general purpose registers Table 4 5 Peripheral Resets IPQ SRESET Peripheral Reset Signal Name Reset Signal State Register Bit Name Ethernet PHY 1 PHY1 RST 1 phy1 rst Ethernet PHY 2 PHY2 RST 1 phy2 rst Slave MPC8255 device ISPQ SRESET 0 slv sreset In addition to the above actions the Serial I O transceiver outputs are set to their tri state condition on a PQ SRESET The bit actions are described further in the General Purpose Registers Section General CPU Section The CPU that is used on the board is a Motorola MPC8255 The User Manuals for this device are the same as the MPC8260 For information on the internal portions of the chip obtain the latest documentation from the Motorola Semiconductor Web site http e www motorola com Please note that the MPC8255 is a subset of the MPC8260 processor It has the same register set and overall characteristics as the MPC8260 with the following exceptions Two FCCs FCC1 and FCC2 instead of three limiting the 10 100 Ethernet ports to two One Utopia II port instead of two 128 Multichannel HDLC ports instead of 256 The MPC8255 is the primary controller on the CPC358 It supplies the PowerPC CPU core the Communications Processor Module CPM and the 60X bus processor bus controller It has direct connections to and is the controller for the Synchronous DRAM SDRAM the local bus
142. es Unless otherwise specified for a given command standard completion code values are used A list of these completion codes is available in the IPMI specification The value 0x00 indicates that the Command Completed Normally IPMI Commands Supported The following IPM IPMI Commands are supported by the PM IPM Device Commands Get Device ID Get Self Test Results Broadcast Get Device ID Cold Reset Warm Reset Manufacturing Test On Get ACPI Power State Set ACPI Power State Get Device GUID FRU Inventory Device Commands Get FRU Inventory Area Read FRU Inventory Data Write FRU Inventory Data 158 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com IPM Device Commands netFn 0x06 0x07 OEM Vendor Specific Commands Diagnostic Echo Get Card Power Status Set Card Power State Get Card Power State IPM Device Commands netFn 0x06 0x07 This section provides detailed descriptions of the IPM Device Commands supported by the PM These commands use Network Function Codes netFn for Application Requests and Responses 0x06 and 0x07 Common IPM Device Command Format The Common IPM Device Request Message Format is outlined in Table 7 3 Take note of the command byte 6 which specifies the variable for each specific function All common Response Message functions are defined in Table 7 4 There are slight differences among various commands Ea
143. ess and address masks Table 4 17 CS3 Base Register Settings Recommended m Field Description Setting PS 01 8 bit DECC 00 Data Errors checking disabled WP 0 Read and write accesses are allowed MSEL 000 Machine Select GPCM 60x bus EMEMC 0 Accesses are handled by the MSEL selected controller No external memory controller allowed in this space ATOM 00 The address space is controlled by the memory controller bank and is not used for atomic operations DR 0 No data pipelining is done V 1 This bank is valid Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com The Option Register Settings follow the form outlined for the GPCM Machine Time of Day Timer Table 4 18 CS3 Option Register Settings Field Pecommengeg Description Setting BCTLD 0 IBCTLx is asserted upon access to the current memory bank CSNT 1 ICS WE is negated a quarter of a clock early ACS 11 ICS is output half a clock after the address lines SCY 6 Clock Wait states SETA 0 IPSDVAL is generated by the GPCM TRLX 1 Relaxed timing is generated by the GPCM for this memory region EHTR 00 Normal Idle Timing General Application Flash Information Flash access in the read mode is done as any normal PROM device including the jump from one device to another Block Commands have separate addresses for each device Selecting writing and e
144. est Message for this command is formatted as in Table 7 3 on page 159 The Response Message for this command is formatted as in Table 7 4 on page 159 Get Self Test Results This command requests the results of the Intelligent Devices Self Test The PM responds with No Error 0x55 in the Self Test Results data field in the Response Message if the self test passed If a self test failure occurred then the Self Test Results data field in the Response Message will be 0x02 Self Test Failed The Additional Information field will contain test specific failure code if the self test failed The Request Message for this command is formatted as in Table 7 3 on page 159 The Response Message for the Get Self Test Results command is formatted for the first 7 bytes as in Table 7 4 on page 159 with the additional response bytes formatted as in Table 7 6 below Table 7 6 Get Self Test Results Response Message Byte Response Field Description 8 Self Test Results 0x55 if Self Test Passed 0x02 if Self Test Failed 9 Additional 0x00 if Self Test Passed Information Test Specific ErrorCode if Self Test Failed 10 Checksum 2 Checksum of bytes 4 9 Set ACPI Power State This command is issued by system software to inform a controller the PM of the current Advanced Configuration and Power Interface ACPI power state of the system It does not actually change the ACPI power state but simply informs the PM of the state
145. executed if implemented This is equivalent to a Hard Reset of Card The Request Message for this command is formatted as in Table 7 3 IPM Device Request Commands Message Format on page 159 The Response Message for the Cold Reset command is formatted as in Table 7 4 IPM Device Response Message Format on page 159 160 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com IPM Device Commands netFn 0x06 0x07 Warm Reset This command directs the Responder to perform a Warm Reset The intention of this command is for the Responder to clean up its internal state but not reset the bus interface configuration The CPC358 does not provide a bus interface so this command is exactly the same as a Cold Reset The Request Message for this command is formatted as in Table 7 3 on page 159 The Response Message for the Warm Reset command is formatted as in Table 7 4 on page 159 Set Manufacturing Test Mode ON This command directs the Responder to enter Manufacturing Test Mode The response to this command only confirms that the CPC358 has accepted and processed the request It does not provide a completion status of the tests The switch will loop on its internal diagnostics until it receives a Cold Reset Global IPMI command which will take it out of this mode The Get Self Tests Results command will indicate the Pass Fail status from the tests The Requ
146. facf00c ffa33004 Oxffacf004 Ffaff005 Oxfffff000 Fffff000 Oxfffff000 offset 0x00 in UPM RAM Oxfffff000 Oxfffff Oxfffff000 Oxfffff in UPM RAM Oxffacf00c Oxffacf Oxffacf004 Oxffacf Oxfffff000 Oxfffff Oxfffff000 Oxfffff offset 0x18 in UPM RAM Oxfffff000 Oxfffff Oxfffff000 Oxfffff 00 00 Oc 04 00 00 00 00 Boot PROM Initialization 107 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 5 Boot PROM and Forth Monitor burst write offset 0x20 in UPM RAM Ox00f3300c Ox00fcf00c Ox00fcf00c Ox00f Ox00f33004 Ox00fcf004 Ox00fcf004 Ox00f OxfELLFOO0 OxffrrfO00 OxfffffO00 OxfTffrt Oxfffff000 Oxfffff000 Oxfffff000 Oxfffff refresh offset 0x30 in UPM RAM Oxfffff005 Oxfffff000 Oxfffff000 Oxfffff OxfIrffD00Q0 OxffrrfOOO0 OxffTLIrTODO Oxrfffrt Oxfffff000 Oxfffff000 OxfffffO00 Oxffftf exception offset 0x3C in UPM RAM 0c 00 00 Hy OOS C o al Cue O oo D o oM Oxfffff005 Oxfffff000 Oxfffff000 Oxfffff000 ISB gt OR2 Oxfffc1000 ISB gt BR2 0x208018a1 ISB gt MBMR 0x90004440 for p UPMBTable p lt UPMBTable 64 p ISB gt MDR p volatile char ISB gt BR2 amp Oxffff8000 0 ISB gt MBMR 0x80004440 Chip Selects 3 9 Application Flash Initialization ISB gt OR3 Oxf
147. fications made to this device which are not expressly approved by the party responsible for compliance could void the user s authority to operate the equipment CE Notice 184 The product s described in this manual conform to the EU 89 336 EEC C Electromagnetic Compatibility Directive amended by 92 31 EEC and 93 68 EEC The product described in this manual is the CPC358 The product identified above complies with the EU 89 336 EEC Electromagnetic Compatibility Directive by meeting the applicable EU standards as outlined in the Declaration of Conformance The Declaration of Conformance is available from Performance Technologies or from your authorized distributor ETSI EN 300 386 Electromagnetic Compatibility and Radio Spectrum Matters ERM Telecommunications Network Equipment Electromagnetic Compatibility EMC Requirements ISO 9002 Notice Performance Technologies is registered by BVQI as ISO 9002 Compliant Safety Certifications EN60950 1 2001 UL60950 1 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Compliance with RoHS and WEEE Directives Electrostatic Discharge Caution Electronic components on printed circuit boards are extremely sensitive to static electricity Ordinary amounts of static electricity generated by your clothing or work environment can damage the electronic equipment It is recommended that anti static ground straps and anti static mats are
148. figured with two IP addresses and two Ethernet MAC addresses The CPC358 Ethernet ports conform to all requirements of the IEEE 802 3 CSMA CD MAC interface These ports support symmetric flow control using the MAC Control Client interface Pause specified in IEEE 802 3u Ethernet PHY The Ethernet PHYs conform to the twisted pair PHY specification for 10 Mbps or 100 Mbps operation in Half Duplex or Full Duplex mode The Ethernets support auto negotiation of the proper speed and duplex settings with its link partner s The Ethernet signals may be connected on the midplane in accordance with PICMG 2 16 CompactPCI PSB specifications or brought out via the RTM to RJ 45 jacks If the Ethernet signals are to be embedded into the midplane then it is the integrator s responsibility to provide a midplane that simulates the Category 5 cable plant requirements specified in ANSI EIA TIA 568 for 100BaseTX Ethernet MII Management The Ethernet MAC to PHY connections of the CPC358 support the basic IEEE 802 3u MII management register set including MII Control and MII Status The Ethernet ports also support registers 2 6 of the extended IEEE 802 3u MII management register set including MII PHY Identifier MII Auto Negotiation Advertisement MII Auto Negotiation Link Partner Ability and MII Auto Negotiation Expansion Ethernet Status Indicators A single visible display LED is provided for each port to indicate Link and Activity transmit or receive
149. figured as a Master and the other as a Slave core disabled The CPC358 can operate as a standalone subsystem i e all functionality required for the CPC358 to operate as a synchronous communications controller is included on board The Master processor also oversees all of the functions of the CPC358 Serial Communication Controllers The Serial Communication Controllers SCCs can be configured independently to implement a variety of industry standard protocols such as Frame Relay ISDN or any protocol using HDLC in Internet WAN environments In Telecom applications the CPC358 supports MTP 2 on all 8 links 27 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 2 Introduction Ethernet Ports The CPC358 offers two independent Ethernet ports each with its own MAC interface and address The CPC358 supports midplane Ethernet wiring conforming to the PICMG 2 16 Packet Switching Backplane standard allowing for the cable free interconnect between the CPC358 and other CompactPCI based Ethernet components such as the Performance Technologies CPC4400 Ethernet switch It also supports Rear Transition Module RTM Ethernet access for traditional Ethernet connection schemes Selectable Line Interface Through the use of multiprotocol transceivers the serial ports can have the following electrical interfaces selected on a port by port basis RS 232E RS 449 RS 530 V 35 Programma
150. for V 35 signal ground J5 A15 RTS3 Ground for V 35 signal ground J5 A7 RTS4 Ground for V 35 signal ground J5 A2 RTS5 Ground for V 35 signal ground J5 B20 DCD1 Connected to V 35 Ring Indicator for port 1 J5 B11 DCD2 Connected to V 35 Ring Indicator for port 2 J5 B15 DCD3 Connected to V 35 Ring Indicator for port 3 J5 B7 DCD4 Connected to V 35 Ring Indicator for port 4 J5 B2 DCD5 Connected to V 35 Ring Indicator for port 5 J5 C20 DSR1 Connected to V 35 Line Test for port 1 J5 C11 DSR2 Connected to V 35 Line Test for port 2 J5 C15 DSR3 Connected to V 35 Line Test for port 3 J5 C7 DSR4 Connected to V 35 Line Test for port 4 J5 C2 DSR5 Connected to V 35 Line Test for port 5 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Pinouts 153 Chapter 6 Pinouts and Rear Transition Modules 154 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter nn PN PN Gn Dd IA System Management Bus and Intelligent Platform Management This chapter describes the Performance Technologies System Management Bus SMB and Intelligent Platform Management It includes the following major topics Overview of SMB on page 155 Intelligent Platform Management Interface IPMI on page 155 IPM Device Commands netFn 0x06 0x07 on page 159 FRU Inventory Device Commands netFn 0x0A 0x0B on
151. former isolated 28 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com CPC358 Architecture Overview Rear Transition Module Options Two RTM options are available for use with the CPC358 One of the RTM options is for use with the Rear I O CPC358 It features two 80 pin high density connectors for the eight serial ports and two Ethernet connectors RJ 45 wired as MDI The other RTM option has only the Ethernet connectors It is for use with the Front I O version of the CPC358 Either of the RTM options is compatible with PICMG 2 16 CompactPCI PSB which can be selected using jumpers Battery The M4T28 BR12SH SNAPHAT battery is a detachable lithium power source for the nonvolatile Timekeeper surface mount SOIC device The SNAPHAT top contains both the battery and the crystal to run the real time clock and is designed to be snapped on after the SOIC is surface mounted on the circuit board The SNAPHAT package can be snapped off for replacement The M4T28 BR12SH has been recognized by Underwriters Laboratories under their Component Recognition Program and carries U L File Number E89556 EN Caution To avoid draining battery do NOT place SNAPHAT pins in a conductive foam For battery disposal contact one of the following recyclers for more information Safety Kleen BDT Inc ENSCO 4255 Research Parkway 309 American Circle Clarence NY 14031 El Dorado AR 7173
152. generated by the device This particular device has 5 volt I O and passes through an extra 74LVC245A data buffer to connect to the 3 3 volt buffered data bus MPC8255 Related TOD Settings The Master MPC8255 uses its chip select 8 CS8 as the TOD_CS signal The CS8 Base Register is set to define the address space as 2030 0000h to 2030 7FFF H Table 4 19 and Table 4 20 are lists of recommended Base and Option Register field settings other than the base address and address masks Table 4 19 CS8 Base Register Settings Field necommended Description Setting PS 01 8 bit DECC 00 Data Errors checking disabled WP 0 Read and write accesses are allowed MSEL 000 Machine Select GPCM 60x bus EMEMC 0 Accesses are handled by the MSEL selected controller No external Memory controller allowed in this space ATOM 00 The address space is controlled by the memory controller bank and is not used for atomic operations DR 0 No data pipelining is done V 1 This bank is valid The Option Register Settings follow the form outlined for the GPCM Machine Table 4 20 CS8 Option Register Settings Field Recommended Description Setting BCTLD 0 IBCTLx is asserted upon access to the current memory bank CSNT 1 ICS WE is negated a quarter of a clock early ACS 11 ICS is output half a clock after the address lines SCY 5 Clock Wait states SETA 0 IPSDVAL is generated by the GM TRLX 1 Relaxed timing is genera
153. h 22 DCh 7 BCh 23 DEh 8 BEh 24 EOh 9 COh 25 E2h 10 C4h 26 E4h 11 C6h 27 E6h 12 C8h 28 E8h 13 CAh 29 EAh 14 CCh 30 ECh 15 CEh 31 Disabled IPMB Compatibility The PM utilizes a version of IPMB that is compatible with IPMB v1 0 as it pertains to the PICMG 2 9 requirements for a Peripheral Management Controller System Side IPMI Management IPMI uses message based Request Response Protocol interfaces for the Intelligent Platform Management Bus IPMB and for the system side interface to the BMC This section describes the system side management interface supported by the CPC358 157 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 7 System Management Bus and Intelligent Platform Management IPMI Network Function Codes netFn This implementation of the PM supports commands and responses with the following netFn codes Table 7 2 Supported Network Function Codes Name Request Response Commands Application 0x06 0x07 Get Device ID Get Self Test Results Broadcast Get Device ID Cold Reset Warm Reset Manufacturing Test On Get Device GUID Get ACPI Power State Set ACPI Power State Storage 0x0A 0x0B Get FRU Inventory Area Read FRU Inventory Data Write FRU Inventory Data OEM Vendor Specific 0x30 0x31 Diagnostic Echo Get Card Power Status Set Card Power State Get Card Power State Completion Cod
154. hapter 4 Functional Description Figure 4 3 External Master SDRAM Configuration SDWE SDRAS SDCAS gt CS1 gt SDRAM 64 BIT PORT SIZE DQM 0 7 o E TO lt x Sa x s m PSM549 SDAMUX MULTIPLEXOR MPC8255 A 0 3 1 TSIZ 0 PSDVAL BADDR27 BADDR28 TSIZ 1 3 c a gt BNKSEL 0 2 D 0 63 gt TS In a_i TA gt TBST i TT 0 4 gt y pull down A pull up Arbitration signals EXTERNAL MASTER TSIZ 0 2 SDRAM Controller Initialization Prior to SDRAM Controller Initialization the SCMR BSR SIUMCR and SWSR registers are initialized This initialization is done in the Boot PROM User alteration is not recommended 62 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Boot Flash Memory Boot Flash Memory The Boot Flash EPROM is used to store the initial startup code for the CPC358 s Master MPC8255 CPU The device is socketed on the board at position U1 The Boot Flash is a non volatile memory that has the following general characteristics The Flash is a single power supply 4 Mbit 3 0 V only Flash memory device organized as 524 288 bytes The data appears on DQ0 DQ7 The device is in a 32 pin PLCC pack
155. hapter includes the following major topics Rear Transition Modules on page 123 Pinouts on page 126 Rear Transition Modules There are two Rear Transition Modules RTMs available with the CPC358 PT RTM358 11608 provides rear I O via two 80 pin connectors on the rear panel PT RTM358 11609 is for use with front I O no 80 pin connectors Both RTMs feature passive design and include optional dual 10 100 Ethernet connections with integral Link Activity LEDs All serial I O signals are carried on the J3 and J5 connectors See page 124 for diagrams of the Rear I O RTM and page 126 for the pinout of the Ethernet ports 123 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 6 Pinouts and Rear Transition Modules Figure 6 1 RTM Diagrams Rear I O I Wels of CPC358 RTM RJ5 9609 0000 Solo 20 20 0000 A Jogo ABCDEF 62002 020 2020 2090 2090 20 0000 0000 0000 0000 Jumpers K1 K8 Bogo 0000 PORTS 1 4 ENET A X 80 Pin 1 2 REAR I O mE Connectors era O rear I O only 3 oBoS 020 Segoe S Sogo 0 0000 0000 0000 2020 gt 1 0308 5 ABC DEF 32 062 p 020 E 9595 0909 amp 0209 0909 0209 0209 0209 ed 10600 TEONNOLOGIBO joo PC358 RTM SIN TT E
156. hnologies Technical Support via e mail support pt com for more initialization information Hot Swap High Availability System Support Resources Used by the Monitor Boot PROM Sectors 0 4 Oxfff00000 Oxfff4ffff monitor code Sector 6 Oxfff60000 Oxfffeffff the first 6 bytes contain a LAN MAC addresses per ANSI IEEE Std 802 assigned by the factory Sector 7 Oxfff70000 Oxfff7ffff contains Forth editor data SDRAM The Monitor uses the top of DRAM starting at 0x07f80000 All other SDRAM is available for use by applications Console Port The console port uses SMC1 It is configured as a 9600 baud 8 N 1 UART It uses the last 0x80 bytes of DPRAM BRG7 and Port D bits 8 and 9 Port C bit 4 Port C bit 4 is enabled to receive commands from the PCI interface 110 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Resources Used by the Monitor Power On Checks and POC Signature During the boot up initialization process diagnostic information is collected into the top 32 bit word of the PCI aperture This bit field a POC signature is described in Table 5 1 Table 5 1 POC Signature Bits Name Description 31 3 msb reserved Reserved bits are set to 0 during initialization 2 SSRAM Result of SSRAM test master 0 good SSRAM 1 bad SSRAM 1 SDRAM Result of SDRAM test 0 good SDRAM 1 bad SDRAM 0 Isb PowerSpan Bus Cycle Indica
157. idad pinid os GAP aes BAG e 38 eens 46 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Contents Hard OSGi PP aus pe eee EPIS 46 SOMASS AA 47 Tundra Power span Resets 32 bot ws cad BA ABAKA SANG Haman that rennende 47 Peripheral Resets o esce edet eMe Quos sed bess p deb B acea senha Ried 48 General CPU EI ETT 48 Master MPC8255 Initial Configuration llis 48 Master MPC8255 Internal Initial Configuration eene 50 Slave MPC8255 Initial Configuration 222veicas dara a ns Kode den 51 Slave MPC8255 Internal Initial Configuration llle 53 Master MPCB255 Memory Map cua pa kawa ERE RERRRRREXREREFRRRREXRER REA 53 Slave MPC8255 Memory Map enen ene 54 60x Bus Connections os amak dae she narnia dead E RR RO EUR d 55 Master MPC8255 Interrupt Sources 15 iral ge be Rc aaa YT beken 55 Slave MPG8255 Interrupt Sources isses ek Ra xa RAW KARONG REX Re eed 56 Master MPC8255 Local Bus Connections eneen 56 Slave MPC8255 Local Bus Connections Unsupported Option 56 Master MPC8255 Parallel I O Ports ene 57 Slave MPC 8255 Parallel I O Ports stre br ben wedst RE EEEE eevee 59 SDRAM lt cintvoavesvesdeivaeawender yeahs ve vee lode tante wd ok yee Maes oes 59 External Master Support us nonr oe hie a Wan OSS SN Ce KG SESE deeded awed REO as 61 SDRAM Controller Initialization llli BRI 62 Boot Flash Memory at pa aaah RE RUE a ERR Ku RO RR ace deas 63 Maste
158. ignal V 35 only K15 1 2 In DCD4 signal 2 3 In RI4 signal V 35 only K16 1 2 In For factory programming of Boot Flash PROM 2 3 In Normal operation K17 1 2 In V 35 DCE RI1 is output 2 3 In V 35 DTE RI1 is input K18 1 2 In DSR1 signal 2 3 In LT1 signal V 35 only K19 1 2 In DCD1 signal 2 3 In RI1 signal V 35 only K20 1 2 In V 35 DCE RI3 is output 2 3 In V 35 DTE RI3 is input K21 1 2 In DSR3 signal 2 3 In LT3 signal V 35 only K22 1 2 In DCD3 signal 2 3 In RI3 signal V 35 only K23 1 2 In V 35 DCE RI8 is output 2 3 In V 35 DTE RI8 is input K24 1 2 In DSR8 signal 2 3 In LT8 signal V 35 only K25 1 2 In DCD8 signal 2 3 In RI8 signal V 35 only K26 1 2 In V 35 DCE RI6 is output 2 3 In V 35 DTE RI6 is input K27 1 2 In DSR6 signal 2 3 In LT6 signal V 35 only K28 1 2 In DCD6 signal 2 3 In RI6 signal V 35 only Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 39 Chapter 3 Installation Table 3 1 Jumpers Continued In Out Jumper Pins default Function K29 1 2 In Manually forces Power Up Reset to both Master and Slave MPC8255 PowerQUICC Ils Out Factory set K30 1 2 In V 35 DCE RI5 is output 2 3 In V 35 DTE RI5 is input K31 1 2 In ENUM open for busless systems 2 3 In Connects PCI Bus signal ENUM to Tundra PowerSpan
159. ignal Mnemonic DB 37 Description Name Name Pin No Shield Ground SG SG 1 Port 3 Shield Ground and Signal Ground 61 RXD4 A RD A 6 Port 4 Receive Data 62 RXD4 B RD B 24 Port 4 Receive Data 63 DTR4 A TR A 12 Port 4 Data Terminal Ready 64 DTR4 B TR B 30 Port 4 Data Terminal Ready 65 TXD4 A SD A 4 Port 4 Transmit Data 66 TXD4 B SD B 22 Port 4 Transmit Data 67 RTS4 A RS A 7 Port 4 Request To Send 68 RTS4 B RS B 25 Port 4 Request To Send 69 TXC4 A TT A 17 Port 4 Transmit Clock 70 TXC4 B TT B 35 Port 4 Transmit Clock 71 TXCI4 A ST A 5 Port 4 Transmit Clock In 72 TXCI4 B ST B 23 Port 4 Transmit Clock In 73 DCD4 A RR A 13 Port 4 Data Carrier Detect 74 DCD4 B RR B 31 Port 4 Data Carrier Detect 75 DSR4 A DM A 11 Port 4 Data Set Ready 76 DSR4 B DM B 29 Port 4 Data Set Ready 77 CTS4 A CS A 9 Port 4 Clear To Send 78 CTS4 B CS B 27 Port 4 Clear To Send 79 RXCA A RT A 8 Port 4 Receive Clock 80 RXC4 B RT B 26 Port 4 Receive Clock Shield Ground SG SG 1 Port 4 Shield Ground and Signal Ground 80 Pin Amp Signal EIA 530 ElA 530 DB 25 Pin No Name Mnemonic Pin No pesoripian 1 RXD1 BB A 3 Port 1 Receive Data 2 RXD1 BB B 16 Port 1 Receive Data 3 DTR1 CD A 20 Port 1 Data Terminal Ready 4 DTR1 CD B 23 Port 1 Data Terminal Ready Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Table 6 4 EIA 530 Connector Pin Ass
160. ignments Continued Pinouts 80 Pin Amp Signal EIA 530 l EIA 530 DB 25 Description Pin No Name Mnemonic Pin No 5 TXD1 BA A 2 Port 1 Transmit Data 6 TXD1 BA B 14 Port 1 Transmit Data 7 RTS1 CA A 4 Port 1 Request To Send 8 RTS1 CA B 19 Port 1 Request To Send 9 TXC1 DA A 24 Port 1 Transmit Clock 10 TXC1 DA B 11 Port 1 Transmit Clock 11 TXCI1 DB A 15 Port 1 Transmit Clock In 12 TXCI1 DB B 12 Port 1 Transmit Clock In 13 DCD1 CF A 8 Port 1 Data Carrier Detect 14 DCD1 CF B 10 Port 1 Data Carrier Detect 15 DSR1 CC A 6 Port 1 Data Set Ready 16 DSR1 CC B 22 Port 1 Data Set Ready 17 CTS1 CB A 5 Port 1 Clear To Send 18 CTS1 CB B 13 Port 1 Clear To Send 19 RXC1 DD A 17 Port 1 Receive Clock 20 RXC1 DD B 9 Port 1 Receive Clock N A Shield Shield 1 Port 1 See Note 21 RXD2 BB A 3 Port 2 Receive Data 22 RXD2 BB B 16 Port 2 Receive Data 23 DTR2 CD A 20 Port 2 Data Terminal Ready 24 DTR2 CD B 23 Port 2 Data Terminal Ready 25 TXD2 BA A 2 Port 2 Transmit Data 26 TXD2 BA B 14 Port 2 Transmit Data 27 RTS2 CA A 4 Port 2 Request To Send 28 RTS2 CA B 19 Port 2 Request To Send 29 TXC2 DA A 24 Port 2 Transmit Clock 30 TXC2 DA B 11 Port 2 Transmit Clock 31 TXCl2 DB A 15 Port 2 Transmit Clock In 32 TXCI2 DB B 12 Port 2 Transmit Clock In 33 DCD2 CF A 8 Port 2 Data Carrier Detect 34 DCD2 CF B
161. ile erasing E DEVICE PROTECT 0x80000002 The StrataFLASH reported block protection on a block while erasing E INVALID BLOCK 0x80000003 An invalid block sector number was given E INVALID ADDRESS 0x80000004 An invalid address was given to the programming operation E INVALID SIZE 0x80000005 An invalid number of bytes to program was given Locally Resident Applications Loading Applications Programming applications into application flash is a two step process 1 Load application data into SDRAM Data can be loaded via the console in Motorola S Record format with the SO Forth word More practically data can be loaded through a PCI aperture if the PCI bus is enabled 2 Program application flash Once in SDRAM the application is programmed into flash with the AFLASH Forth word or via the Host PCI Command Interface Running Applications At the console the Forth GO command is provided to start an application running The Host PCI Command Interface provides this same function Running Applications Automatically The FACT jumper causes block 1 to be loaded automatically By placing 10000000 GO in the boot script execution is called to the beginning of the application flash Scripts may be more complex as called for by the application Built In Boot Sequence with Initialization from NVRAM The Built In Boot Sequence is one way of launching a board resident application The sequence is di
162. in Table 6 3 Note Some of the 80 pins in the connector may not be included in the table For each electrical standard the pins that are not included in the table for that standard MUST BE LEFT UNCONNECTED Ports 1 4 are carried on J6 on the front panel and J1 on the Rear Transition Module Ports 5 8 are carried on J7 on the front panel and J2 on the Rear Transition Module Table 6 3 RS 449 Connector Pin Assignments 80 Pin No 1 2 RS 449 Signal Name RXD1 A RXD1 B RS 449 RS 449 Mnemonic DB 37 Name Pin No RD A 6 RD B 24 Description Port 1 Receive Data Port 1 Receive Data 129 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 6 Pinouts and Rear Transition Modules Table 6 3 RS 449 Connector Pin Assignments Continued 80 Pin RS 449 RS 449 l RS 449 o No Signal Mnemonic DB 37 Description Name Name Pin No 3 DTR1 A TR A 12 Port 1 Data Terminal Ready 4 DTR1 B TR B 30 Port 1 Data Terminal Ready 5 TXD1 A SD A 4 Port 1 Transmit Data 6 TXD1 B SD B 22 Port 1 Transmit Data 7 RTS1 A RS A 7 Port 1 Request To Send 8 RTS1 B RS B 25 Port 1 Request To Send 9 TXC1 A TT A 17 Port 1 Transmit Clock 10 TXC1 B TT B 35 Port 1 Transmit Clock 11 TXCI1 A ST A 5 Port 1 Transmit Clock In 12 TXCI1 B ST B 23 Port 1 Transmit Clock In 13 D
163. in not asserted 1 Slave MPC8255 Software Reset pin asserted 7 led jmpr 1 4 0 Jumper Out LEDs indicate Link Type with software led jmpr 5 8 control of LEDs 1 Jumper In LEDs indicate Activity hardware control of LEDs software control disabled Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com System Management Bus System Management Bus The Peripheral Management PM controller for the CPC358 System Management Bus SMB implementation utilizes the Microchip PIC16F877 micro controller as the core The PIC16F877 features an 12C interface capable of Slave or Master mode operation as well as the RAM program Flash memory and I O needed to implement the supported features The PM also has a bi directional 8 bit parallel slave port PSP that is used to interface the Master MPC8255 processor on the CPC358 The Master MPC8255 can write read this port to exchange messages between the PM and CPC358 host The PM has access to the CompactPCI Geographic Address through an 5 bit I O port on the PIC16F877 A mechanism exists to generate interrupts to the CPC358 host processor to facilitate PM initiated communications with the host using the Master MPC8255 Parallel Port pin PCO 12C is the accepted hardware layer for SMB on CompactPCI The 12C bus connections support Two wire serial interface for clock and data Open collector drain drivers Device arbitration for multiple bu
164. installing jumper K38 2 3 and the PCI Bus Interface is disabled using jumper K6 2 3 jumper not installed This bit provides the capability for the MPC8255 to hold the PowerSpan in reset Setting this bit to a 1 causes a reset IP1 RST pin of PowerSpan Clearing the bit to a 0 removes the reset condition In normal operation the PCI backplane reset P1 RST is passed to the PowerSpan through PSM552 1 0 RESV Always 0 Hot Swap Status and Control Register The Hot Swap Status and Control Register provides information about the PCI bus such as is the PCI bus present and is its interface enabled The state of the handle ejector switch can be read here PCI bus speed 33 MHz or 66 MHz can be identified in this register The PCI X capability bit future use is found in this register The MPC8255 can control the blue hot swap LED independently from the Tundra PowerSpan using a bit in this register Table 4 44 Hot Swap Status and Control Register Bit Fields MPC8255 O MSB 1 2 3 4 5 6 7 LSB Bit Buffered 7 MSB 6 5 4 3 2 1 O LSB Bus Bit Field pcibusifen RESV ledbit esclosed pcipre RESV p1 pcix pi m6 sent cap 6en Reset Current 0 1 Current Value 0 Current Value Value Value R W READ ONLY R W READ ONLY Address Base 4BH Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General Purpose Registers Table 4 45 Hot
165. ion Codes netFn eee Completo Codes 224264 tasas BASTA BABABA ridad tadas IPM Commands Supported ius prioridades IPM Device Commands netFn 0x06 0x07 neee Common IPM Device Command Format 00 cece eee eee Get Device ID uuo Ae bh ek eee de RR e De eh sca PARA Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Contents 115 117 117 117 123 123 126 126 126 129 135 142 143 143 144 146 155 Contents GORSSEL toner dns AP 160 Warm Reset in iss Ka mone dad NG PG RA NG a vad dea due dead dekaarde 161 Set Manufacturing Test Mode ON ssuarsssrvansananteers statie wannes 161 Get Self Test Results corras ae e ers praia 161 Set ACPI Power State P 161 Get ACPI Power State neee rr 162 Get Device GUID isse UR basi gence AYA TED bet GER KALA eee es OEE Shaw dete eed 162 Broadcast Get Device ID aman chee narren nebh eRe s 162 FRU Inventory Device Commands netFn 0x0A OXOB 0 000 eee eee 163 Common FRU Inventory Device Commands 0 eee eee eee 163 Get FRU Inventory Area neee eee 164 Read FRU Inventory Data 02400004 Seve Rx RR RA RR RR RR ps 165 Write FRU Inventory Dala xicos ctra RR ERR RR RE REGE REPE 165 OEM Vendor Specific Commands netFn 0x30 OX31 nnana aana aana 166 Common OEM Commands ane babad ue aha ate reerde ars 166 Diagnostic Echo usd ds teense ibe Che tie ee Redes 167 Get Gard Power Status a Ha B
166. ion measures include a low VCC detector that automatically inhibits write operations during power transitions The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory This is achieved via programming equipment The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from or program data to any sector that is not selected for erasure True background erase can thus be achieved Application Flash Memory The Application Flash PROM is used to store application code that will not be executed at boot up time There are two physical devices that make up this block of memory Each device is permanently mounted to the PCB at positions U4 and U58 Each Application Flash device is a non volatile memory that has the following general characteristics The Flash is a single power supply 16 Mbyte 3 0 Volt only Flash memory device Read accesses to the device are the same as any EPROM The data appears on DQ0 DQ7 on the buffered data bus For writing purposes the device has 127 blocks of byte wide data storage The storage blocks have 128K bytes of storage each Selecting writing and erasing the blocks is done by using a Common Flash Interface CFI and a Scaleable Command Set SCS All read erase and program operations are accomplished using only a single power supply Internally generated and regulated voltages are provided for the
167. is parity disabled Both data and parity are implemented in a monolithic component that is wired directly to the MPC8255 local bus The device is controlled by the MPC8255 s Universal Programmable Memory UPM controller A 66 MHz clock is provided to the memory from the same low skew clock driver that provides 66 MHz to the MPC8255 The active high and active low chip selects are permanently enabled via external resistors Global Write Enable GWE is pulled up to permanently disable the global override of byte write enable Address Status Processor ADSP is pulled up to permanently disable burst abort with READ override Snooze ZZ is grounded to permanently disable snooze Burst mode LBO is grounded to permanently select linear burst FT Vss is a ground pin on this device The memory interface consists of 32 data LCL D 0 31 4 byte parity LCL DP 0 4 4 byte write selects LCL LBS 0 3 1 write enable ICS LOC RAM 1 Address Status Controller ILCL ADSC 1 Address Advance ILCL ADV 1 output enable LCL_OE 1 chip enable ILCL CE and 16 address LCL A29 A14 The seventeenth address connection to memory is grounded LCL OE LCL_ADSC LCL ADV and LCL CE are driven from the MPC8255s LGPL 0 3 pins respectively MPC8255 Related Communications Buffer Memory Settings Both Master and Slave MPC8255 use their chip select 2 CS2 as the CS LOC RAM signal The Master MPC8255 CS2 Base Register is set to define the address space
168. ister 10h The possible selections are Carrier Integrity Monitor Link Unstable Link Status Change Descrambler Lock Change Premature End Error DCR Rollover FCCR Rollover RECR Rollover Remote Loopback Fault Reset Complete Jabber Detect Auto Neg Complete Parallel Detection Fault Parallel Fail Remote Fault Page Received Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Serial I O Interface Serial I O Interface The CPC358 supports eight identical individually programmable synchronous serial I O ports See PSM554 Port Control Registers on page 93 for the appropriate register bit settings The ports are capable of electrically interfacing to RS 232C RS 422 or V 35 equipment The ports are brought out in groups of four to an 80 pin connector that supports Performance Technologies quad connection Hydra line of serial I O cables All eight ports are identically pinned out on the main board and the Rear Transition Module The use of the Hydra cables allows the CPC358 to support two additional standards RS 530 and RS 449 The RS 530 Hydra cables though electrically supported are NOT offered as part of the standard product All of these interface standards are being supported as a DTE Data Terminal Equipment type of connection The CPC358 s port programmability will allow Performance Technologies to offer a new configuration in the V 35 format It will be a quad Hydr
169. lity Instrumentation Guaranteed 888 88 SOURCE www artisantg com CompactPCI Interface The reset configuration word consists of eight bits set on the 60x bus PB D 0 7 bits bit O O disable PB arbiter PowerSpan is not the 60x bus arbiter bit 1 O disable PCI 1 arbiter PowerSpan is not the PCI 1 arbiter bit 2 O disable the PCI 2 arbiter there is no PGI 2 bus present bit 3 0 PCI 1 is primary PCI bit 4 1 disable PCI 1 REQ64 bit 5 0 PB Boot get local configuration from the processor bus bit 6 O disable debug mode bit 7 O disable PLL bypass mode PCI Device and Vendor ID The following identification codes have been assigned to the CPC358 PCI Device ID 0x3580 Vendor ID 0x1214 PCI Device ID ESS 0x3581 Local 60x Bus Connections to the PowerSpan The design is similar to the referenced Tundra documentation except in the following signals described in Table 4 23 The variation being in the selection of making the Master MPC8255 the bus arbiter and the inability to select the pin modes due to the multiplexed pins on the 60x bus Also a different means of controlling the board reset is done either by the Master MPC8255 processor or CompactPCI bus Table 4 23 Signal Variations From Between PowerSpan and the Master MPC8255 Power Span Signal MPC8255 Signal Description or comments IPB BR 1 IBR Address Bus Request 8255 arbitration IPB BG 1 IBG Address Bus Grant
170. lled Table 4 56 presents the meaning of the Mode Control Selection Bits Table 4 56 Transceiver Mode Control Selection Bits Mode M2 M1 M0 Not Used Default V 11 0 0 0 RS530A 0 0 1 RS530 0 1 0 X 21 0 1 1 V 35 1 0 0 RS449 V 36 1 0 1 V 28 RS232 1 1 0 No Cable Z 1 1 1 Table 4 57 Transceiver 1 2 5 6 Mode Control Register Bit Fields MPC8255 Bit 0 MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 0 LSB Field dte 2 n m2 2 m 2 mO 2 dte 1 n m2 1 m11 mo 1 dte 6 n m2 6 m1 6 m0 6 dte 5 n m2 5 m1 5 mO 5 Reset Value 0 1 1 1 0 1 1 1 R W R W Address Base 70H 80H Table 4 58 Transceiver 1 2 5 6 Mode Control Register Bit Field Definitions Bits Name Description 0 mO 1 m0 5 Port 1 5 Mode Select Pin 0 1 m1 1 m1 5 Port 1 5 Mode Select Pin 1 2 m2 1 m2 5 Port 1 5 Mode Select Pin 2 3 dte 1 n dte 5 n 0 Port 1 5 is DTE 1 Port 1 5 is DCE 4 mO 2 mO 6 Port 2 6 Mode Select Pin 0 5 m1 2 m1 6 Port 2 6 Mode Select Pin 1 6 m2 2 m2 6 Port 2 6 Mode Select Pin 2 7 dte 2 n dte 6 n 0 Port 2 6 is DTE 1 Port 2 6 is DCE 95 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description 96 Transceiver 3 4 7 8 Mode Control Register The Transceiver 3 4
171. logy Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com LEDs Figure 3 2 CPC358 Front Panel Front I O Rear I O STATUS ENET Q1 2 A B Board Status Ethernet and Port Status LEDs 3 SE 0906 Oo SLYOd 80 Pin Connectors Front I O Only O 2 E o a T eo CompaciPCI CPC358 CompactPCI CPC358 OCTAL OCTAL SYNC SERIAL SYNC SERIAL Console Port CONSOLE CONSOLE Hot Swap LED O Node Glyph Artisan Technology Group Quality Instrumentation Working with the CPC358 Board Status LEDs There are two board status LEDs on the front panel LED1 can show green or yellow LED2 can show red or green The meaning of these indicators is determined by the end user s software Ethernet LEDs The two Ethernet LEDs Enet A and B show steady green to indicate Link and flashing green to indicate Activity Port Status LEDs Jumper K10 selects one of two Port LED display functions When K10 is jumpered 1 2 LEDs indicate activity flashing green to indicate transmit flashing yellow for receive When K10 is jumpered 2 3 LEDs indicate the electrical standard set for the group Off indicates RS 232 green indicates RS 422 449 530 yellow indicates V 35 35 Guaranteed 888 88 SOURCE www artisantg com Chapter 3 Installation 36 Figure 3 3 CPC358 Board Layout K1 6 K9 10 K7
172. ls This flexible memory controller allows the implementation of memory systems with very specific timing requirements The SDRAM machine provides an interface to synchronous DRAMs using SDRAM pipelining bank interleaving and back to back page mode to achieve the highest performance The GPCM provides interfacing for simpler lower performance memory resources and memory mapped devices The GPCM has inherently lower performance because it does not support bursting For this reason GPCM controlled banks are used primarily for boot loading and access to low performance memory mapped peripherals The UPM supports address multiplexing of the external bus refresh timers and generation of programmable control signals for row address and column address strobes to allow for a glueless Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 53 Chapter 4 Functional Description interface to DRAMs burstable SRAMs and almost any other kind of peripheral The refresh timers allow refresh cycles to be initiated The UPM can be used to generate different timing patterns for the control signals that govern a memory device These patterns define how the external control signals behave during a read write burst read or burst write access request Refresh timers are also available to periodically generate user defined refresh cycles The primary control of the devices served by the mem
173. made through the CompactPCI J3 rear connector The ports are wired per the PICMG 2 16 CompactPCI PSB standard The ports support all of the MPC8255 s normal Ethernet capabilities The PHY section is composed of two Cirrus Logic CS8952 Transceivers and two isolation transformers The PHYs each have an MII connection to an FCC on the Master MPC8255 The MII bus can be electrically isolated either by the CS8952 reading the ISODEF pin at RESET or by bit 10 Isolate of the Basic Mode Control Register 00h which is programmable by the MII Serial Management Interface As part of initialization the ISOLATE MII bit should be cleared and then the active high PHY RESET bit for the appropriate port should be set then cleared A 25 MHz shielded surface mount oscillator 100 ppm supplies the clock to both PHYs The MII bus of the CS8952 operates at 3 3V separate power supply pins for the MII core of the part needs 5V Series resistors are provided to reduce the rise fall times for EMI considerations For communication with Master MPC8255 PowerQUICC II serial management interface using the MDIO and MDC signals the B port PHY 1 has address 1 and the A port PHY has address 2 MII bus signals have pull up pull down resistors that are read at reset to obtain this address The CS8952 has configuration pins that determine its mode of operation at reset See Table 4 26 CS8952 Configuration Pins on page 75 These can be overridden using the serial
174. male M34 PT ACC334 10623 PT ACC334 10722 4 port RS 232C Hydra Style Cable DTE male DB 25 4 port RS 449 Hydra Style Cable DTE male DB 37 PT ACC358 11610 4 port V 35 Hydra Style Cable DCE female M34 We highly recommend you use Performance Technologies cables Our connector pin assignments assume unique unconnected pins Customers who have tried to use their own cables with signals on these unused pins have encountered problems Refer to Serial I O Interface and Connector Pin Assignments section for more information on which pins must be unconnected 31 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 2 Introduction 32 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter A pp me AAA Gn Dd A Installation This chapter describes the installation and set up the CPC358 It includes the following major topics Working with the CPC358 on page 33 e Jumpers and DIP Switches on page 38 Before installing the CPC358 make sure the board is correctly configured for your application See Jumpers and DIP Switches on page 38 Working with the CPC358 Installing the CPC358 The following instructions assume that the chassis power is on and that the host supports hot swap insertion If the system does not support hot swap power must be turned off prior to i
175. masters These include the Tundra PowerSpan PCI bridge and the master and slave MPC8255s The SDRAM architecture provides the ability to synchronously burst data at a high data rate with automatic column address generation the ability to interleave between internal banks in order to hide PRECHARGE time and the capability to randomly change column addresses on each clock cycle during a burst access Figure 4 2 on page 60 shows a Partial SDRAM State Diagram 59 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description 60 Figure 4 2 Partial SDRAM State Diagram CBR REFRESH ACTIVE POWER DOWN WRITEA SUSPEND SUSPEND PRECHARGE gt AUTOMATIC SEQUENCE cm MANUAL INPUT This synchronous DRAM design provides support for a 144 pin SODIMM module at 3 3V The I2C interface of the SODIMM module is connected to the IZC port of the Master MPC8255 but not supported in currently available software A density of 128MB is supported and has been verified at 66 MHz Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SDRAM Note The current configuration of the CPC358 has the SDRAM memory configuration set up parameters hard coded in the Boot Flash for a 128MB SODIMM Do not attempt to install larger memories They will not be recognized The data port size is 64 bits
176. ment Bus and Intelligent Platform Management The Response Message for the Diagnostic Echo command is formatted as shown in Table 7 22 with the following additions Table 7 22 Diagnostic Echo Response Message Byte Response Field Description 8toN Count Returned Must be at least 1 but no more than 24 bytes N 1 Checksum 2 Checksum of bytes 4 N Note N in Table 7 22 refers to a byte count of between 8 and 31 Get Card Power Status This OEM command provides the Requester with the current power status of the card The PM will Respond with the power status of the card as determined by the POWER GOOD signal pin on the general purpose parallel I O port of the PM microcontroller This signal is generated by an on board power management module and indicates that all voltage rails are within the specified limits This command also reports the state of additional card status signals such as EJECTOR_SWITCH HEALTHY P1 BDSEL and the SMB ENABLED signal Table 7 23 Bit Assignments for Card Power Status Byte Bit Signal Description Values 7 P1 BDSEL BDSEL from the PCI Bus 0 indicates BDSEL is FALSE 1 indicates that BDSEL is TRUE 6 NC 5 NC 4 EJECTOR_SWITCH Ejector Switch 0 indicates EJECTOR_SWITCH is Closed 1 indicates that EJECTOR SWITCH is OPEN 3 HEALTHY POWER_GOOD and no fault 0 indicates that HEALTHY is FALSE 1 indicates HEALTHY is TRUE 2 NC 1 SMB_ENABLE SMB
177. mmand 0x01 Diagnostic Echo 0x10 Get Card Power Status 0x11 Set Card Power State 0x12 Get Card Power State Table 7 20 Common OEM Response Commands Byte Response Field Description rqsA Requester s Slave Address netFn rqLUN NetFn 0x31 rqLUN Checksum 1 Connection Header Checksum rsSA Responder s Slave Address DA A WIN rqSeq rsLUN Sequence number and Responder s LUN 0x00 Command 0x01 Diagnostic Echo 0x10 Get Card Power Status 0x11 Set Card Power State 0x12 Get Card Power State Completion Code Diagnostic Echo This OEM command provides a means of verifying the functionality of the I2C Bus and associated PM hardware When a Diagnostic Echo Request is received the PM will echo the message data content back to the Requester in the Response data fields The Request Message for this command is formatted as in Table 7 19 on page 167 with the addition of several more byte definitions as per Table 7 21 below Table 7 21 Diagnostic Echo Request Commands Byte Request Field Description 7toN Data to Echo Must be at least 1 but no more than 24 bytes N 1 Checksum 2 Checksum of bytes 4 N Note N in Table 7 21 refers to a byte count of between 7 and 31 167 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 7 System Manage
178. nal The CSO Base Register is set to define the address space as FFFO 0000h to FFF7_FFFF H The following is a list of recommended Base and Option Register field settings other than the base address and address masks Table 4 15 CSO Base Register Settings Recommended Field Description Setting PS 01 8 bit DECC 00 Data Errors checking disabled WP 0 Read and write accesses are allowed MSEL 000 Machine Select GPCM 60x bus EMEMC 0 Accesses are handled by the MSEL selected controller No external memory controller allowed in this space ATOM 00 The address space is controlled by the memory controller bank and is not used for atomic operations DR 0 No data pipelining is done V 1 This bank is valid The Option Register Settings follow the form outlined for the GPCM Machine Table 4 16 CS0 Option Register Settings Field Recommend Description Setting BCTLD 0 IBCTLx is asserted upon access to the current memory bank CSNT 1 ICS WE is negated a quarter of a clock early ACS 11 ICS is output half a clock after the address lines SCY 6 Clock Wait states SETA 0 IPSDVAL is generated by the GPCM TRLX 1 Relaxed timing is generated by the GPCM for this memory region EHTR 00 Normal Idle Timing General Boot Flash Information Flash access in the read mode is done as any normal PROM device 64 The programming or write operations are entirely command set compatible with the
179. nd maximize hardware and software investments throughout the development integration and deployment phases of the product life cycle If you encounter difficulty in using this Performance Technologies Inc product you may contact our support personnel by 1 EMAIL Preferred Method Email us at the addresses listed below or use our online email support form Outline your problem in detail Please include your return email address and a telephone number 2 TELEPHONE Contact us via telephone at the number listed below and request Technical Support Our offices are open Monday to Friday 8 00 a m to 8 00 p m Eastern Standard Time Performance Technologies Support Contact Information Embedded Systems and Software SS7 Systems Includes Platforms Blades and Servers Includes SEGway Email support pt com ss7support pt com 1 585 256 0248 1 585 256 0248 Phone Monday to Friday 8 a m to 8 p m Monday to Friday 8 a m to 8 p m Eastern Standard Time Eastern Standard Time If you are located outside North America we encourage you to contact the local Performance Technologies distributor or agent for support Many of our distributors or agents maintain technical support staffs Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Product Warranty Customer Support Packages Our configurable development and integration support packages
180. ndard as a 10 100 port in the A position The CPC358 Ethernet interface implements the full set of IEEE 802 3 Ethernet CSMA CD media access control MAC and channel interface functions FCC1 configuration is set in GFMRx MODE register of the MPC8255 The CS8952 Ethernet PHY provides an optional MII IRQ interrupt signal line which is mapped to an interrupt on the MPC8255 called PHY1 There is an MII1 isolate line on MPC8255 that is connected to the PHY1 MII isolate line See Master MPC8255 Parallel Port Pin Assignments on page 171 for the appropriate Master MPC8255 port pins Master MPC8255 SCC Ports The Master MPC8255 has SCC ports SCC1 to SCC4 assigned to Serial I O ports on both the front panel on J6 and the Rear Transition Module on J1 The front or rear I O option is accomplished by a build option and the actual switching of the signals from the front connector to the rear is through a set of zero ohm jumpers Each port will also be able to have its electrical configuration set to either RS 232 RS 422 or V 35 by a set of registers located in PLD PSM554 Cabling options will allow RS 232 DTE RS 449 DTE RS 449 DCE V 35 DTE and V 35 DCE configurations Even though the ports are individually programmable current cabling constraints will limit the options to two groups of four identically programmed ports Each port will be able to be individually tri stated Each port will support Transmit Data Transmit Clock Receive Data Receive Cl
181. nfiguration LBPC pins function as a local bus 22 23 APPC 10 Address Parity Pin configuration no address parity Bank Select Function Selected on Multifunction pins 24 25 CS10PC 01 CS10 pin configuration is set to be IBCTL1 Buffer control for byte lane 1 26 27 RSVD 00 Reserved must be set to 0 28 31 MODCK H 0110 MODCK_H Clock Reset Configuration high order bits set to 0110 for 66 MHz input clock 166 MHz CPM 233 MHz core Master MPC8255 Internal Initial Configuration The internal Initial configuration is obtained from the Boot Code running out of the Flash PROM The initial settings for the System Integration Unit module configuration register SIUMCR because its register fields are most closely tied to the hardware configuration Table 4 8 Master MPC8255 SIUMCR Register Settings 50 Field Fincominonoed Description Setting BBD 0 IABB IIRQ2 pin is ABB IDBB IIRQ3 pin is IDBB ESE 1 External Snooping is enabled GBL IRQ1 pin is IGBL PBSE 0 Parity byte select is disabled GPL4 is available for UPM use CDIS 0 MPC8255 core is enabled DPPC 11 Pins set to external bus grant and IRQ6 and IRQ7 L2CPC 10 Level 2 cache pins set to BADDR 29 31 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General CPU Section Table 4 8 Master MPC8255 SIUMCR Register Settings Continued Field pecommenaed Description Setti
182. ng LBPC 00 Local Bus pins function as local bus APPC 10 MODCLK Pins function as BNKSEL 0 2 and IRQ7 out and CS11 CS10PC 01 ICS10 is IBCTL1 BCYLC 00 IBCTLO is used as W R IBCTL1 is OE control MMR 00 No masking on bus request lines LPBSE 0 Parity Byte disabled LGPL4 output of UPM is available for memory control Slave MPC8255 Initial Configuration A great deal of the initialization of the MPC8255 occurs during the hard reset process When the PQ HRESET signal is active the CPU selects its CPU PLL settings and several other initial configuration settings The following sections describe these settings Slave MPC8255 Core Clock and PLL The initial implementation of the board will be with a unit that has a 233 MHz Power PC Core PPC a 166 MHz CPM and a 66 MHz external 60x multi master bus The chip is supplied with a 66 MHz primary clock input CLKSLAVE on the CLKIN input The clock PLL settings to select the core speed are driven into the part by the MODCLOCK lines from the PSM549 PLD logic while the PQ HRESET signal is active The clock settings are as follows 233 MHz core 166 MHz CPM 66 MHz 60x Bus Initial Release Product MODCLOCK 1 3 110 The following core clock configurations settings are suggested for operation with the Performance Technologies default software settings for system clocks refresh timers and baud rate generators Table 4 9 Slave MPC8255 System Clock Control Register Bit Field Definitions
183. ng the PICMG 2 16 standard as a 10 100 port in the B position The CPC358 Ethernet interface implements the full set of IEEE 802 3 Ethernet CSMA CD media access control MAC and channel interface functions FCC1 configuration is set in GFMRx MODE register of the MPC8255 The MPC8255 CPM pin assignments for Fast Ethernet can be found in Rear Transition Module Ethernet Ports on page 126 The IEEE 57 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description 58 802 3 management interface MDIO and MDC are supported via general purpose I O pins PA7 and PA6 respectively The CS8952 Ethernet PHY provides an optional MII_IRQ interrupt signal line which is mapped to an interrupt on the MPC8255 called PHY2 There is an MII2 isolate line on MPC8255 that is connected to the PHY2 MIl isolate line See Master MPC8255 Parallel Port Pin Assignments on page 171 for the appropriate Master MPC8255 port pins Fast Ethernet 10 100BaseT on FCC 2 The MPC8255 s FCC 2 is used to support a 10 100BaseT Fast Ethernet connection through its MII Media Independent Interface A Cirrus Logic CS8952 is the PHY interface for this connection This port is designated as port A on the faceplate of the Rear Transition Module The Ethernet I O signal lines and the Link Activity LED status indicator lines are brought out to rear panel CompactPCI connector J3 using the PICMG 2 16 sta
184. ns set to BADDR 29 31 Note The Slave device should never have to use this feature with the core disabled but it is defined to prevent inadvertent problems LBPC 00 Local Bus pins function as local bus Note The Slave device should never have to use this feature with the core disabled but it is defined to prevent inadvertent problems APPC 10 MODCLK Pins function as BNKSEL 0 2 and IRQ7 out and CS11 CS10PC 01 ICS10 is IBCTL1 BCYLC 00 IBCTLO is used as W R IBCTL1 is OE control MMR 00 No masking on bus request lines Note The Slave device should never have to use this feature with the core disabled but it is defined to prevent inadvertent problems LPBSE 0 Parity Byte disabled LGPL4 output of UPM is available for memory control Master MPC8255 Memory Map The CPC358 Address Decode Scheme defines the memory map There are different levels of Address Decode built into the CPC358 The first level and primary decode is done by the MPC8255 s System Interface Unit SIU One of the SIU s subsections is the Memory controller The memory controller is responsible for controlling a maximum of twelve memory banks shared by a high performance SDRAM machine a general purpose chip select machine GPCM and three user programmable machines UPMs It supports a glueless interface to synchronous DRAM SDRAM SRAM EPROM Flash EPROM burstable RAM regular DRAM devices extended data output DRAM devices and other periphera
185. nstallation Figure 3 1 on page 34 shows a typical CompactPCI chassis 33 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 3 Installation Figure 3 1 CompactPCI Chassis Rear Transition Module required for rear access ee o o 4 E LJ o e o Front Rear 1 Unlock the ejector handles by depressing the red latch buttons Gently slide the CPC358 into the chassis aligning the board with the guides in the top and bottom of the slot When the board is fully inserted press the handles toward each other to lock the board in the chassis When the board makes contact with the CompactPCI backplane the blue Hot Swap LED turns ON and the hardware connection process begins When the board is operational the blue Hot Swap LED turns OFF 2 Insert the RTM board if required into the corresponding I O slot in the rear of the chassis and install the port cables to the RTM connectors Note RTMs may be installed hot but extreme care must be taken to insure proper pin alignment during insertion RTMs support alignment tabs to aid in insertion 3 Reconnect any cables from the peripheral devices Removing the CPC358 1 Unlock the handles by depressing the red latch buttons and then press the handles away from each other The board disconnects from the chassis and the blue Hot Swap LED turns ON 2 Remove the board from the chassis 34 Artisan Techno
186. nventory Area Info 0x11 Read FRU Inventory Data 0x12 Write FRU Inventory Data 7 FRU Device ID 0x00 Device ID 163 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 7 System Management Bus and Intelligent Platform Management Table 7 11 FRU Inventory Device Response Formats Byte Response Field Description 1 rgSA Requester s Slave Address 2 netFn rqLUN NetFn 0x0B rqLUN 3 Checksum 1 Connection Header Checksum 4 rsSA Responder s Slave Address 5 rqSeq rsLUN Sequence number and Responder s LUN 0x00 6 Command 0x10 Get FRU Inventory Area Info 0x11 Read FRU Inventory Data 0x12 Write FRU Inventory Data 7 Completion Code Get FRU Inventory Area This command returns the size in bytes of the FRU Inventory Data Area on the PM The format of the FRU Inventory Area is as described in the PMI Platform Management FRU Information Storage Definition V1 0 Document Revision 1 1 Sept 27 1999 by Intel Hewlett Packard NEC and Dell The PM at a minimum must include the Common Header and Board Info Area The Product Info Area can also be used to identify specific applications Note The Common Board and Product Info Area in the PM micro controller provide a maximum of 152 bytes of EEPROM The FRU Inventory layout for this PM implementation is as follows Table 7 12 FRU Inventory Layout ou Size Bytes
187. ock Clear to Send Request to Send Carrier Detect on the Master MPC8255 port pins assigned to each SCC In addition each port has Data Terminal Ready and Data Set Ready connected to general purpose I O pins on the Master MPC8255 See Master MPC8255 Parallel Port Pin Assignments on page 171 for the appropriate Master MPC8255 port pins Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com SDRAM Slave MPC8255 Parallel I O Ports The slave CPM supports four general purpose I O ports A B C and D Each pin in the I O ports can be configured as a general purpose I O signal or as a dedicated peripheral interface signal Port C is unique in that 16 of its pins can generate interrupts to the internal interrupt controller Each pin can be configured as an input or output and has a latch for data output read or written at any time and configured as general purpose I O or a dedicated peripheral pin Some of the pins can be configured as open drain the pin can be configured in a wired OR configuration on the board The pin drives a zero voltage but three states when driving a high voltage Note that port pins do not have internal pull up resistors Due to the CPM s significant flexibility many dedicated peripheral functions are multiplexed onto the ports The functions are grouped to maximize the pins usefulness in the greatest number of MPC8255 applications Refer to the MPC8255 user s man
188. ocks Note that erasing all blocks can take over 180 seconds Block numbers 0 127 will erase blocks 0 127 respectively of the first application flash and block numbers 128 255 will erase blocks 0 127 respectively of the second application flash A block number of 1 will erase all blocks of both application flash devices If successful flag will be returned equal to zero Otherwise flag will be a flash error code See Flash Error Codes below AFLASH dest src size flag The application flash is programmed with size bytes from address src The dest is given as an offset into the application flash from the application flash base address 0x10000000 Offsets from 0x0 OXFFFFFF will access the first application flash while offsets of 0x1000000 and above will access the second application flash Valid offsets would be from 0x0 to Ox1FFFFFF If successful flag will be returned equal to zero Otherwise flag will be a flash error code See Flash Error Codes below BERASE b erase sector flag Erase a sector of boot flash specified by sector Valid sectors are 5 6 and 7 If sector is 1 erase all three sectors If successful flag will be returned equal to zero Otherwise flag will be a flash error code See Flash Error Codes below 113 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 5 Boot PROM and Forth Monitor 114 BFLASH b flash dest src
189. oftware and integrated circuits within ninety 90 days of shipment and provided said nonconforming products are returned F O B to Performance Technologies s facility no later than thirty days after the warranty period expires Products returned under warranty claims must be accompanied by an approved Return Material Authorization number issued by Performance Technologies and a statement of the reason for the return Please contact Performance Technologies or its agent with the product serial number to obtain an RMA number If Performance Technologies determines that the products are not defective Buyer shall pay Performance Technologies all costs of handling and transportation This warranty shall not apply to any products Performance Technologies determines to have been subject to testing for other than specified electrical characteristics or to operating and or environmental conditions in excess of the maximum values established in applicable specifications or have been subject to mishandling misuse static discharge neglect improper testing repair alteration parts removal damage assembly or processing that alters the physical or electrical properties This warranty excludes all cost of shipping customs clearance and related charges outside the United States Products containing batteries are warranted as above excluding batteries 23 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com
190. olate MII bus Clear low to enable MII bus LPBK Loopback Enable Grounded externally to disable local loopback LPSTRT Low Power Start Pulled up externally so that PHY powers up immediately PWRDN Power Down Grounded externally so that PHY is not powered down REPEATER Repeater Mode Pulled down internally so that the Carrier Sense operates normally in a non repeater mode TCM Transmit Clock Mode Grounded externally so that TX_CLK is output and CLK25 disabled TESTO Factory Test Tied directly to VSS Ground for normal operation TEST1 TXSLEWO Transmit Slew Rate Control Left floating for 2 5 ns rise fall time the value from the ANSI TXSLEW1 _ standard The Link LED control signal LED3 and the TX and RX ACTIVITY LEDS LED1and LED2 are connected to PLDPSM553 The signals are connected to logic within the PLD so that the resulting output signal controls an LED for each port on the front and rear panel The LED will light up for a link indication on the port and it will blink if there is receive or transmit traffic on the port The rear panel connection is brought out to the J3 connector The others listed here are not supported LED4 Polarity Full Duplex active low LED5 Collision Descrambler Lock active low SPD10 10Mb s Speed Indication active high SPD100 100Mb s Speed Indication active high Each PHY can assert an interrupt to the Master MPC8255 The interrupt assertion is selected through the Interrupt Mask Reg
191. ology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 6 Pinouts and Rear Transition Modules 140 Table 6 6 V 35 Signals and Pins DCE Continued Pin T ae m No Signal Name Direction Termination Description 27 CTS2 6 Output NA V 35 Clear To Send port 2 or 6 V 35 106 M 34 D 28 GND2 6 NA V 35 port 2 or 6 Signal Ground V 35 102 M 34 B 29 TXC A 2 6 Output NA V 35 Transmit Clock port 2 or 6 V 35 113 M 34 V 30 TXC B 2 6 Output NA V 35 Transmit Clock port 2 or 6 V 35 113 M 34 X 31 TXCI A 2 6 Output NA V 35 Transmit Clock In port 2 or 6 V 35 115 M 34 Y 32 TXCI B 2 6 Output NA V 35 Transmit Clock In port 2 or 6 V 35 115 M 34 AA 33 DCD2 6 Output NA V 35 Data Carrier Detect port 2 or 6 V 35 109 M 34 F 34 RI2 6 Output NA V 35 Ring Indicator port 2 or 6 V 35 125 M 34 J 35 DTR2 6 Input 5K Ohms to ground V 35 Data Terminal Ready port 2 or 6 V 35 108 M 34 H 36 LT2 6 Output NA V 35 Line Test port 2 or 6 V 35 M 34 K 37 RTS2 6 Input 5K Ohms to ground V 35 Request To Send port 2 or 6 V 35 105 M 34 C 39 RXC A 2 6 Input 100 Ohms differential V 35 Receive Clock port 2 or 6 125 Ohms to ground V 35 114 M 34 U 40 RXC B 2 6 Input 100 Ohms differential V 35 Receive Clock port 2 or 6 125 Ohms to ground V 35 114 M 34 W 41 TXD A 3 7 Input 100 Ohms differential V 35 Transmit Data port 3 or 7 125 Ohms to ground
192. one for each port They indicate no connection when off a link condition when on in a steady state condition and traffic on the link when blinking See Rear Transition Module Ethernet Routing and Ground on page 41 for the RTM Ethernet jumper settings The Rear Transition Module Ethernet Port Aand Port B are wired as MDI Table 6 1 shows the pinout for these connections Table 6 1 Ethernet Connector J3 and J4 Pinout PinNumber Signal Name TX TX RX NC Bob Smith Termination NC Bob Smith Termination RX NC Bob Smith Termination NC Bob Smith Termination o N aj A O N RS 232 Supported Signals 126 The first standard supported is RS 232C in a DTE format The signals supported and their positions in both of the 80 pin connectors are shown in Table 6 2 Note Some of the 80 pins in the connector are not included in the table For each electrical standard the pins that are not included in the table for that standard MUST BE LEFT UNCONNECTED Ports 1 4 are carried on J6 on the front panel and J1 on the Rear Transition Module Ports 5 8 are carried on J7 on the front panel and J2 on the Rear Transition Module Table 6 2 RS 232C Connector Pin Assignments UE Pin No 1 RXD1 BB 3 Port 1 Receive Data 2 16 3 DTR1 CD 20 Port 1 Data Terminal Ready 4 23 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURC
193. ontrol PLD TXCLKx Bag Teste DTE_SCTE_DCE_RXCx gt TXCx gt TCSLx 1 Pg bo PA TCSLx ka OUTx TCSLx DCE_TXCx 3 TXCIx gt A DCE_ DTEx 0 DTE_TXCx C ft MPC8255 SCCx El DCE_ DTEx 1 K DCE_ DTEx a RCSLx 0 DTE RXC DCE SCTEx RXCx 4 RXCLKx ba RCSLx 1 3 RCSLx DCE DTEx OPTIONAL OSC 1 2 SIZE CAN TXD YGP1AN Y Lon gt Data Capture al PI lo BLINK amp LED Flasher 3 YGP1CAT v YGP2AN z p z G N BUF AD 7 0 YGP2CAT v N YGP3AN a lc YGP3CAT Sr TL gt o R REGEWR Control and Status I YGP4AN H BUF ALE Registers 8 YGP4CAT IBUF RD gt ICS_REG M2 4 1 gt M1 4 1 IPQ SRESET X MO 4 1 DCE DTE 4 1 IGROUPSEL 1 41 ISHDN 4 1 gt ISPQ_SRESET IPQ HRESET CLK33 gt possible future use Xransceiver Mode Control N AJ NA LED Q IN HARDWARE CONTROL FLASH ON ACTIVITY JUMPER i OUT SOFTWARE CONTROLLED BITS 94 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General Purpose Registers Transceiver 1 2 5 6 Mode Control Register The Transceiver 1 2 5 6 Mode Control Register selects the desired electrical interface for Ports 1 and 2 Ports 5 and 6 individually controlled It also selects whether the ports are DTE computer or DCE modem also individually contro
194. ory controller machines is through the MPC8255 s external Chip select lines The specific memory controller setups will be defined for each type of device in the section of the specification that describes the device Table 4 12 represents the primary address decode of the External chip select lines Table 4 12 Master MPC8255 Chip Select Assignments Chip Select Line Controlled Device Address Range ICSO Flash Boot PROM FFFO 0000 to FFF7 FFFF h ICS1 SDRAM 0000 0000 to O7FF_FFFF h ICS2 Local Bus SSRAM 2080_0000 to 2083_FFFF h ICS3 Application Flash 1000_0000 to 11FF FFFFh ICS4 PLD General Purpose Registers 2000 0000 to 2000 Offf h ICS5 Not Assigned ICS6 Not Assigned ICS7 Not Assigned ICS8 Time Of Day Chip 2030 0000 to 2030 7FFF h ICS9 System Management Bus Controller 2040 0000 to 2040 7FFF h ICS11 SDRAM 2 Reserved None Power Span mapped space 3000 0000 to 3000 Offf None Master MPC8255 Internal Memory Space FFOO 0000 to FF02 0000 None Slave MPC8255 Internal Memory Space FOFO 0000 to FOF2 0000 Slave MPC8255 Memory Map 54 The Slave MPC8255 has its own SRAM connected to the Slave s Local Bus this SRAM is not currently supported In addition the Slave MPC8255 uses BRO which is configured by the Hard Reset control word Table 4 13 Slave MPC8255 Chip Select Assignments Chip Select Line Controlled Device Address Range CSO SDRAM 0000 0000 to
195. owing sections Power On Reset A Dallas DS1233A initiates the Power on reset sequence for the board The device senses the 3 3V back end power and issues a IPORESET to both of the MPC8255s and the Tundra PCI bridge The DS1233A provides a 350ms reset pulse after the 3 3V power settles to an intolerance condition It will also signal IPORESET if there is a brownout condition In addition to the CPU and bridge the signal is provided to the PSM552 PLD for the PLD reset logic The device also de bounces a pushbutton or jumper on its output This feature is supported in the design with jumper K29 Shorting K29 1 2 causes a debounced IPORESET to be issued from the part Hard Reset The hard reset signal PQ HRESET is generated by the MPC8255 and the PSM552 PLD Logic The MPC8255 generates PQ_HRESET in response to a power on reset a software watchdog reset if enabled a bus monitor reset if enabled or a checkstop reset if enabled The PSM552 PLD generates a PQ_HRESET under several conditions The configuration of jumpers that feeds into the PSM552 PLD regulates which signals generate PQ_HRESET Table 4 4 shows the signals involved and the jumper settings required Table 4 4 PQ HRESET Control Signals and Select Jumpers Signal Name Function ICARD RST This input is enabled by jumpering K1 1 2 ISMBEN true This signal indicates to the PLD logic that the SMB controller is active and that it is configured to issue a hard reset to the
196. ox interface Simply map mailbox 0 to the PowerSpan INT3 which drives MPC8255 Port C bit 4 interrupt as described above Writing the following command vectors into mailbox 0 causes execution as described Application Flash Vector Oxfff03000 Arguments mailbox 1 dst destination as an offset into application flash mailbox 2 src address from which to begin the copy mailbox 3 size number of bytes to copy Returns mailbox 1 flag The application flash is programmed with size bytes from address src The dest is given as an offset into the application flash If successful flag will be returned equal to zero Otherwise flag will be a flash error code See Flash Error Codes below Application Erase Vector Oxfff03014 Arguments mailbox 1 block number of block to erase Returns mailbox 1 flag Erase a block of application flash specified by block Block numbers range from 0 127 If block is 1 erase all blocks Note that erasing all blocks can take over 90 seconds If successful flag will be returned equal to zero Otherwise flag will be a flash error code See Flash Error Codes below Boot Flash Vector Oxfff03010 Arguments 115 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 5 Boot PROM and Forth Monitor mailbox 1 dst destination as an offset into application flash mailbox 2 src address from which to begin the copy mailbox 3
197. product The two connections are wire ORed together on the board Table 4 52 Compact PCI Geographic Address Register Bit Fields MPC8255 Bit 0 MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 O LSB Field RESERVED ga 4 0 Reset Value 0 Current Value R W READ ONLY Address Base 5AH Table 4 53 Compact PCI Geographic Address Register Bit Field Definitions Bits Name 4 0 ga 4 0 Description CompactPCI Geographic Address CT Bus Shelf Address Register The CT Bus Shelf Address Register contains the 5 bit value of the Shelf identifier for the cardfile that the CPC358 is currently plugged into These bits are read from the backplane through the J4 CT bus connector CT bus not part of standard product Table 4 54 CT Bus Shelf Address Register Bit Fields MPC8255 Bit O MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 O LSB Field RESERVED sa 4 0 Reset Value 0 Current Value R W READ ONLY Address Base 5BH Table 4 55 CT Bus Shelf Address Register Bit Field Definitions Bits Name 4 0 sa 4 0 Description Shelf Address bits CT bus not part of standard product 92 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General Purpose Registers PSM554 Port Control Registers There are two identical PSM554 Port Control Registers PL
198. ps that require core voltages that are different than the I O voltages Future higher speed versions of the chip may require the core power to be changed to different values Table 4 3 Local Voltages Signal Name Function MVCORE PQ This is the voltage required by the Master MPC8255 core It is distributed on a sub plane SVCORE PQ This is the voltage required by the Slave MPC8255 core It is distributed on a sub plane VCORE PCI This is the voltage required by the Tundra PCI bridge This voltage is 2 5 volts for the A revision of the part It is distributed on a sub plane 9V Precharge This voltage is used to precharge the CompactPCI interface for hot plug in and hot swapping The precharge voltage is 9V 1V per the Tundra specification An LMC6582 OP AMP to creates the voltage via a resistor chain There is control logic that allows the precharge voltage to be driven high causing the CompactPCI inputs on the Tundra chip to be driven false if the logic detects the absence of a PCI bus This voltage is distributed on a sub plane 45 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description Reset Logic The reset logic for the board has many components There are Power on hard and soft resets There are resets caused by the external buses time of day timer watchdog and the System Management Bus Each of these will be discussed in the foll
199. r MPC8255 Related Flash Settings onee 64 General Boot Flash Information lt 23cecc2ese isd eee be Rebbe dies 64 Application Flash Memory ca ve ez ck sonore verden oes hennen eas dare keten 65 Master MPC8255 Related Flash Settings neee 66 General Application Flash Information eneen 67 Time of Day TS aux RU Roe wenken kennende e RO e ad 67 MPC8255 Related TOD Settings icis i ve dese Y a ke REP EUR enden DNS 68 General TOD Information amer orita Rad EI eR REPRE ER Pd edere REGE 68 Communications Buffer Memory 0000 eee nh 69 MPC8255 Related Communications Buffer Memory Settings 70 UPMB Table Settings uso o RR RR RE eR Rd RR X RO X RR RA Ra ek RO RC Goes 71 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Contents CompactPCI Interface uere der aC a RR SUR n RR E KERN AAA 71 PowerSpan Signal Connections and Hardware Configuration 71 PowerSpan Reset Configuration Word eneen 72 PCI Device and Vendor ID a aa kaba Na rar beau het deeqseunbax aie 73 Local 60x Bus Connections to the PowerSpan 0c eee eee eee 73 PowerSpan Interrupts icc aves ka Kaw aa GANG DANG NENG KANG Rede Far RCR MCA RACK eas 74 Fast Ethernet Controller a aa ser ara a NG SS RR at Ren beke KELAN KAL 74 Serial KO Interface ud nmm geb Set atk yoy daa 77 Clock m PT be Ve See WED END ae OE ON eae ete eek ee 79 D
200. r at address offset 43H Ejector Switch Interrupt Status at address 44H RESERVED Register at address offset 45H Miscellaneous Status and Control Register at address offset 46H RESERVED Register at address offset 47H General Purpose Latch Register at address offset 48H General Purpose Switch and P1 Reset Status Register at address offset 49H P1 Reset Control Register at address offset 4AH Hot Swap Status and Control Register at address offset 4BH Board ID Register 1 at address offset 4CH Board ID Register 2 at address offset 4DH RESERVED Register at address offset 4EH RESERVED Register at address offset 4FH Peripheral Reset Control Register The Peripheral Reset Control Register reflects the current state of all of the peripheral chip resets as well as allowing the user to enable reset the chip under program control Table 4 30 Peripheral Reset Control Register Bit Fields MPC8255 Bit O MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 0 LSB Field phy2rst phyirst ctrstn RESERVED Reset Value 1 1 0 0 0 0 0 0 R W R W READ ONLY Address Base 42H 83 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description 84 Table 4 31 Peripheral Reset Control Register Bit Field Definitions Bits Name Description 4 0 RESV Always 0 5 ctrstn If the CPC358 boa
201. r the SSRAM is provided by the UPMB and the CS2 address space decode The Slave SSRAM connection is identical to that of the Master Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General CPU Section Master MPC8255 Parallel I O Ports The CPM supports four general purpose I O ports A B C and D Each pin in the I O ports can be configured as a general purpose I O signal or as a dedicated peripheral interface signal Port C is unique in that 16 of its pins can generate interrupts to the internal interrupt controller Each pin can be configured as an input or output and has a latch for data output read or written at any time and configured as general purpose I O or a dedicated peripheral pin Some of the pins can be configured as open drain the pin can be configured in a wired OR configuration on the board The pin drives a zero voltage but three states when driving a high voltage Note that port pins do not have internal pull up resistors Due to the CPM s significant flexibility many dedicated peripheral functions are multiplexed onto the ports The functions are grouped to maximize the pins usefulness in the greatest number of MPC8255 applications Refer to the MPC8255 user s manual for more information on the various peripheral setups Serial Management Controller SMC 1 The MPC8255 features two general purpose serial management controllers SMCs that may be used as gener
202. rasing the blocks is done by using a Common Flash Interface CFI and a Scaleable Command Set SCS Please refer to the 3 Volt Intel STRATAFlash Memory Datasheet for the command set and the programming strategy Note that the address offsets for the first device begin with 1000 0000h and the second device begin with 1100 0000h Time of Day Timer The Time of Day TOD Timer is an integrated ultra low power SRAM Real time clock and power fail control circuit with a top mounted SNAPHAT battery The device is available to be used as a scratch SRAM a Real Time Clock or a watchdog timer Figure 4 6 TOD Block Diagram BUF_A 0 12 PQ_HRESET gt ITOD_CS IBUF WR IBUF RD B TOD M48T59 ITOD INT p ITOD RST OUT BUF AD 0 7 67 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description The device is accessed by the Master MPC8255 through the Buffered Data bus The buffered data bus supplies a buffered MPC8255 address and a bi directional 8 or 16 bit data bus The ITOD CS is supplied by the MPC8255 and acts as the device chip enable The BUF_RD is supplied by the PSM550 PLD logic and acts as the device output enable The PSM550 also supplies the IBUF_WR strobe which is the write enable The read and write cycle is timed by the GPCM s wait state programming There is no cycle termination signal
203. rd is the CT bus reset master as selected by jumper K2 1 2 then when this bit is set to a O the CT bus is held in reset The bit will always be set to O during a IPQ SRESET Setting the bit to a 1 will release the CT bus from the reset state CT bus not part of standard product 6 phy1rst When this bit is set to a 1 the Ethernet PHY 1 chip is held in reset The bit will always be set to 1 during a PQ_SRESET Setting the bit to a O will release the Ethernet PHY 1 chip from the reset state 7 phy2rst When this bit is set to a 1 the Ethernet PHY 2 chip is held in reset The bit will always be set to 1 during a PQ_SRESET Setting the bit to a O will release the Ethernet PHY 2 chip from the reset state Ejector Switch Interrupt Enable Control Register The Ejector Switch Interrupt Enable control register is used to enable the hot swap ejector switch as an interrupting source The ejector switch interrupt is mapped to the MPC8255 PC2 The individual interrupt source and its enable are listed in the sections following Table 4 32 Ejector Switch Interrupt Enable Control Register Bit Fields MPC8255 Bit 0 MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 0 LSB Field RESERVED esenb RESERVED Reset Value 0 0 0 R W READ ONLY R W READ ONLY Address Base 43H Table 4 33 Ejector Switch Interrupt Enable Control Register Bit Field Definitions Bits Name Description 3 0 RESV Always 0 4 e
204. rect precharge voltage 0 9V on PCI Bus pins for hot swap 2 3 In Allows 3V signal to be put on PCI Bus pins if no PCI Bus is present K7 1 2 In Connects Slave MPC8255 SPQ_INT_OUT interrupt signal to Master MPC8255 IRQ6 input Use when Slave CPU core is disabled 2 3 In Connects Slave MPC8255 parallel port PAO signal to Master MPC8255 IRQ6 input Use when Slave CPU core is enabled K8 1 2 In V 35 DCE RI2 is output 2 3 Int V 35 DTE RI2 is input K9 1 2 In Break Detect is enabled for serial line reset 2 3 In No effect when a break is sent on console port 38 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Jumpers and DIP Switches Table 3 1 Jumpers Continued Artisan Technology Group In Out Jumper Pins default Function K10 1 2 In Port LEDs indicate Activity hardware controlled blink green for transmit yellow for receive on port by port basis Affects all eight ports 2 3 In Port LEDs indicate Link Type software programmable using Port Status LED Control Registers Affects all eight ports K11 1 2 In DSR2 signal 2 3 In LT2 signal V 35 only K12 1 2 In DCD2 signal 2 3 In Rl2 signal V 35 only K13 1 2 In V 35 DCE RI4 is output 2 3 In V 35 DTE RI4 is input K14 1 2 In DSR4 signal 2 3 In LT4 s
205. rected by variables and flags stored in an NVRAM structure The NVRAM structure is manipulated by the NVRAM word set 117 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 5 Boot PROM and Forth Monitor 118 If the FACT jumper is installed and if screen 1 contains a script with a single word boot the Built In Boot sequence will run from power up The user is allowed a three second opportunity to give three enter keys at the console aborting the boot sequence and returning control to the Ficl monitor s ok gt prompt Then the NVRAM Word Set is used to configure the boot sequence NVRAM Structure The NVRAM structure holds all the data required by the Built In Boot Sequence It resides at 0x20300000 in the 8K SRAM provided by the M48T59Y TIMEKEEPER SRAM Table 5 3 NVRAM Structure ADDRESS NAME SIZE DESCRIPTION DEFAULT VALUE 0x00 boot_magic 4 bytes A valid structure will contain a magic number 0x00COFFEE 0x04 boot_rev 4 bytes The revision number of the structure 1 0x08 boot_addr 4 bytes The GO address where application starts 0x10000000 0x0c boot_opts 4 bytes Bit mapped boot options 0x00000017 BIT POSITION MEANING 0 lsb Run diagnostics if set to 1 1 Boot application if set to 1 2 Boot application if reset by RTC watchdog 3 Boot applica
206. rtisantg com Host PCI Interface Command Set anne Flash Error Codes accionada naa KABA PAK Shs ee d doa dia a Locally Resident Applications avan snare coh bodes dansk eat ree ieee Built In Boot Sequence with Initialization from NVRAM 0 0c e eee eee Chapter 6 Pinouts and Rear Transition Modules Hear Transition Modules 5 server wer ER RR ERE beets eel ees Seis ERES whos ERR ie PINOUIS aant hen ARN WA Sache KATAMAD AA ANA den oon ech Bee kek tote ee Be Rear Transition Module Ethernet Ports een RS 232 Supported Signals xus s rare daken Sowa eee a bA AEI kaw ae RS 449 422 Supported Signals aaa sa victors iedid un Re DUREE ERG RPG hr DEG D EUR ds V ab supported SIGNS Aus sate vene QU o en NEA LEI eds banders hd ende Front Panel Serial Port Console ane eee Master MPC8255 JTAG Support eenen Slave MPC8255 JTAG Support i cu es RE REOR ee heete ne keeway es Mictor PINOUT 1024 eden Ee eU LANES WRENN Bae Pee Ges Gee Pee Nee ae eee CompactPCI Bus Conneciors 00s enwas eked teehee es OSes here bee y o ee de Chapter 7 System Management Bus and Intelligent Platform Management Overview of SMB AA AA es san ob Gees Intelligent Platform Management Interface IPMI een Baseboard Management Controller eee Peripheral Management Controller oee Intelligent Platform Management Bus IPMB een PMB Compatibility 222 pere pair EEE RE EJ 3d RR System Side IPMI Management 0 00 eee ee IPMI Network Funct
207. s masters 100 Kbps data rate The CPC358 supports the CompactPCI Intelligent Platform Management Bus IPMB SMB J1 interface pins that are listed in Table 4 74 Table 4 74 CompactPCI SMB to CPC358 SMB Interface Pin Name Function Pin 1 0 IPMB_PWR VSM IPMB Backup power J1 A4 l IPMB_SDA SDAT Serial Data J1 C17 1 0 IPMB SCL SCLKSerialClock Ji B17 VO 103 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description 104 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter nn PN PN AAA lt A IA Boot PROM and Forth Monitor The Boot PROM provides initialization a host PCI interface and a Forth console This chapter provides provides information about these major topics Boot PROM Initialization on page 105 Hot Swap High Availability System Support on page 110 Resources Used by the Monitor on page 110 Boot PROM Initialization Reset Configuration Even before the Boot PROM program begins executing the MPC8255 retrieves configuration data from the PROM In the first 256 bytes are reset configuration words for the CA91L8260 PowerSpan PowerPC to PCI Bus Switch and the MPC8255 PowerQUICC II Master and MPC8255 PowerQUICC II Slave MPC8255 Reset Configuration Word As the configuration master the reset configuration word for the M
208. se Registers PSM553 General Purpose Registers The registers contained in the PSM553 PLD logic all begin at offset 0000 005xH in the ICS REG space These registers control the LED indicators for the general board status The CompactPCI bus Geographic Address and the CT Bus Shelf address CT bus not part of standard product are also located in this device The register list includes the following Board Status LED Control Register at address offset 50H RESERVED Register at address offset 51H through 59H Compact PCI Geographic Address Register at address offset 5AH CT Bus Shelf Address Register at address offset 5B CT bus not part of standard product RESERVED Register at address offset 5CH through 5FH Board Status LED Control Register The Board Status LED Control Register controls the Red Green and Green Yellow Board status LEDs in LED array D1 The register controls whether the LEDs are on or off and what color the bi color LEDs will show Note that the default state on a IPQ SRESET is the LEDs off Table 4 50 Board Status LED Control Register Bit Fields MPC8255 Bit O MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 0 LSB Field stsred RSV stsgrn RSV stsroff RSV stsgoff RSV Reset Value 0 0 0 0 1 0 1 0 R W R W RO R W RO R W RO R W RO Address Base 50H RSV Reserved RO Read Only Table 4 51 Board Status LED Control Register Bit Fi
209. senb When the esenb bit is set to a 1 the ejector switch interrupt is enabled A 0 in this bit position will disable the condition as an interrupting source A PQ_SRESET will cause the bit to be 0 7 5 RESV Always 0 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General Purpose Registers Ejector Switch Interrupt Status Register Ejector Switch Interrupt Status Register stores an occurrence of hot swap ejector switch activity When enabled in the Ejector Switch Interrupt Enable Control Register the source bit will create an interrupt on PC2 on the MPC8255 The register is also used to clear a latched bit The interrupt remains stored even if the interrupt source has been cleared The interrupt can only be cleared using this register The bit definition is reflected in Table 4 34 and Table 4 35 Table 4 34 Ejector Switch Interrupt Status Register Bit Field Definitions MPC8255 Bit O MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 0 LSB Field RESERVED essts RESERVED Reset Value 0 R W READ ONLY R W READ ONLY Address Base 44H Interrupt PC2 Table 4 35 Ejector Switch Interrupt Status Register Bit Field Definitions Bits Name Description 3 0 RESV Always 0 4 essts This bit is set to a 1 whenever the ejector switch changes state from open to closed or closed to open It remains a 1 un
210. sition Modules Table 6 12 J11 Mictor Pinout 60X Bus Data CompactPCI Bus Connectors 146 The following section contains the pinouts for the CPC358 CompactPCI connectors The J5 and J3 connectors are used to supply the line level Serial I O signals to the Rear Transition Module and are used in configurations that support uncommitted I O on J3 and J5 The J3 connector conforms to the PICMG 2 16 specification for Ethernet backplane connections The board connections on the J4 connector consist of the H 110 specified Shelf and Geographic Address lines and the power pins to support these lines The H 110 CT bus is not supported on the standard product The connector will not be installed in the initial versions of the product but may be offered as a build option The J1and J2 connectors support a Hot Swap connection to the PCI bus as well as a serial SMB interface The following sections contain the pinouts of each of these connectors Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 33 PQ_D61 PQ_D29 34 35 PQ_D62 PQ_D30 36 37 PQ_D63 PQ_D31 38 J1 Connector Pinout Table 6 13 J1 CompactPCI Connections Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Pin A B C D E F 25 EVDD REQ64 ENUM EV3V EVDD GND 24 AD1 EVDD LVIO A
211. size flag The boot flash is programmed with size bytes from address src The destis given as an explicit address in the boot flash If successful flag will be returned equal to zero Otherwise flag will be a flash error code See Flash Error Codes below BUPDATE b update src A new Boot PROM image is programmed into sectors 0 4 of the boot FLASH starting from address src Upon completion the monitor restarts Version Information HARDWARE code code is returned as O SOFTWARE cadar u Return a character string specification identifying the boot PROM software Program Execution GO go vector Execution is called to the specified vector Diagnostics DIAGS u u is the number of diagnostic tests provided by the boot PROM Usage hint DIAGS 0 do loop DIAGNAME u c adar u Return the character string specification for a description of diagnostic test u An ambiguous condition exists if u is not in the range of 0 DIAGS 1 Usage hint 0 DIAGNAME type space Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Resources Used by the Monitor DIAGRUN u flag Run diagnostic test u and return a pass fail flag An ambiguous condition exists if u is not in the range of 0 DIAGS 1 Usage hint 0 DIAGRUN if passed else failed endif Host PCI Interface Command Set The PCI host can issue commands through a mailb
212. sters General Purpose Latch Register The General Purpose Latch Register is an 8 bit Read Write storage location for any general purpose use The location is volatile Table 4 38 General Purpose Latch Register Bit Fields MPC8255 Bit O MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 0 LSB Field latch 7 0 Reset Value 0 R W R W Address Base 48H Table 4 39 Register Bit Field Definitions Bits Name Description 7 0 latch 7 0 This register is a general purpose 8 bit storage latch This location is volatile General Purpose Switch and P1 Reset Control Register The General Purpose Switch and P1 Reset Control Register is an 8 bit register It contains the bit values of the 4 bit general purpose switch SW1 and the current status of the CompactPCI reset bit Table 4 40 General Purpose Switch and P1 Reset Register Bit Fields MPC8255 Bit 0 MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 O LSB Field pirstn RESERVED gpsw 1 4 Reset Value Current 0 Current Value Value R W READ ONLY Address Base 49H Table 4 41 General Purpose Switch and P1 Reset Register Bit Field Definitions Bits Name Description 3 0 gpsw 1 4 Each bit of this field represents the position of one of the four switches of SW1 Bit 3 switch condition A 0 represents a closed switch posi
213. strobes are supplied as required during the data phase of the cycle Data is written into the registers on the rising edge of IREG WR BUF_RD is essentially asserted during the entire data phase of the read cycle causing the data from the registers to be driven onto the data lines as long as the strobe is true Read and Write cycles are completed by the GPCM s wait state timing There is no cycle complete signal generated by the register logic Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com General Purpose Registers The logic for the registers is contained in the PSM552 PSM553 and PSM554 PLD devices All of the registers are mapped into the 2000 0000H to 2000_00FF memory space on the MPC8255 chip select 4 The CPC358 select signal is ICS REG The explicit address of each register and its associated function are presented in the following sections Any register named RESERVED is a read only register that returns all zeros when accessed These registers have possible functional assignment on other Performance Technologies products PSM552 General Purpose Registers The registers contained in the PSM552 General Purpose PLD logic all begin at offset 0000 004xH in the ICS REG space These registers include the RESERVED Register at address offset 40H RESERVED Register at address offset 41H Peripheral Reset Control Register at address offset 42H Ejector Switch Interrupt Enable Control Registe
214. t Ready 37 CTS2 A CS A 9 Port 2 Clear To Send 38 CTS2 B CS B 27 Port 2 Clear To Send 39 RXC2 A RT A 8 Port 2 Receive Clock 40 RXC2 B RT B 26 Port 2 Receive Clock Shield Ground SG SG 1 Port 2 Shield Ground and Signal Ground 41 RXD3 A RD A 6 Port 3 Receive Data 42 RXD3 B RD B 24 Port 3 Receive Data 43 DTR3 A TR A 12 Port 3 Data Terminal Ready 44 DTR3 B TR B 30 Port 3 Data Terminal Ready 45 TXD3 A SD A 4 Port 3 Transmit Data 46 TXD3 B SD B 22 Port 3 Transmit Data 47 RTS3 A RS A 7 Port 3 Request To Send 48 RTS3 B RS B 25 Port 3 Request To Send 49 TXC3 A TT A 17 Port 3 Transmit Clock 50 TXC3 B TT B 35 Port 3 Transmit Clock 51 TXCI3 A ST A 5 Port 3 Transmit Clock In 52 TXCI3 B ST B 23 Port 3 Transmit Clock In 53 DCD3 A RR A 13 Port 3 Data Carrier Detect 54 DCD3 B RR B 31 Port 3 Data Carrier Detect 55 DSR3 A DM A 11 Port 3 Data Set Ready 56 DSR3 B DM B 29 Port 3 Data Set Ready 57 CTS3 A CS A 9 Port 3 Clear To Send 58 CTS3 B CS B 27 Port 3 Clear To Send 59 RXC3 A RT A 8 Port 3 Receive Clock 60 RXC3 B RT B 26 Port 3 Receive Clock 131 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 6 Pinouts and Rear Transition Modules Table 6 3 RS 449 Connector Pin Assignments Continued Table 6 4 ElA 530 Connector Pin Assignments 80 Pin RS 449 RS 449 l RS 449 o No S
215. tect port 4 or 8 V 35 109 M 34 F 74 RI4 8 Output NA V 35 Ring Indicator port 4 or 8 V 35 125 M 34 J 75 DTR4 8 Input 5K Ohms to ground V 35 Data Terminal Ready port 4 or 8 V 35 108 M 34 H 76 LT4 8 Output NA V 35 Line Test port 4 or 8 V 35 M 34 K 77 RTS4 8 Input 5K Ohms to ground V 35 Request To Send port 4 or 8 V 35 105 M 34 C 79 RXC A 4 8 Input 100 Ohms differential V 35 Receive Clock port 4 or 8 125 Ohms to ground V 35 114 M 34 U 80 RXC B 4 8 Input 100 Ohms differential V 35 Receive Clock port 4 or 8 125 Ohms to ground V 35 114 M 34 W The following tables show the connector pin assignments for the CPC358 Front Panel Serial Port Console The CPC358 front panel includes an RJ11 RS 232 serial port used for console connection at J8 The pinout is defined looking into the connector with the Token keying cutout at the bottom Pin numbering runs along the top starting at the left Table 6 7 Console Pin Assignments Pin Number Signal Name no connection GROUND Receive Data 1 Transmit Data 1 GROUND no connection ol A N o The default console settings are 9600 baud 8 bits 1 stop bit no parity 142 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Master MPC8255 JTAG Support The JTAG testing port on the Master MPC8255 is used to support the EST COP debugger on
216. ted by the GPCM for this memory region EHTR 00 Normal Idle Timing General TOD Information The M48T59 TIMEKEEPER RAM is an 8Kb x8 non volatile static RAM and real time clock The monolithic chip is a highly integrated battery backed up memory and real time clock solution Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Communications Buffer Memory The M48T59 is a non volatile pin and function equivalent to any JEDEC standard 8Kb x8 SRAM It also easily fits into many ROM EPROM and EEPROM sockets providing the non volatility of ROMs without any requirement for special write timing or limitations on the number of writes that can be performed The 28 pin 600mil DIP SNAPHAT battery houses the M48T59 59Y silicon with a quartz crystal and a long life lithium button cell in a single package The unique design allows the SNAPHAT battery package to be mounted on top of the package after the completion of the surface mount process Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface mounting The SNAPHAT housing is keyed to prevent reverse insertion The Watchdog and Real Time functions embedded in the part can be connected internally to either the TOD RST OUT reset line or the TOD_INT interrupt lines Activation of the reset lines causes a soft reset The interrupt will c
217. tes the PowerSpan is responding to bus cycles directed to it Indicator 0 good PowerSpan 1 bad PowerSpan The POC signature is located at the top of the PCI aperture so it is available both locally and to the PCI host If the PCI aperture size and or location is changed by a boot script that boot script may also move the POC signature Host PCI Communication Interface Upon bootup the monitor indicates it is ready for a command by leaving 1 in the PowerSpan s mailbox 0 Commands are received by the MPC8255 via Port C bit 4 Upon interruption the MPC8255 vectors to the address in PowerSpan s mailbox 0 Mapping PowerSpan mailbox 0 to PowerSpan INT3 most easily causes this The following code demonstrates this communication void run pci_device device long go INT3 is an output 1_bi_base device gt IDR 0x08000000 Clear out MBOXO map 1_bi_base device gt IMR_MBOX amp OxE map to tundra INT3 bi_base device gt IMR_MBOX OxA enable mailbox O interrupt bi base device gt IERO 0x1 say GO and cause interrupt 1_bi_base device gt MBOX0 go assume local side will clear it ENG NING NG NG CO If the vector of execution returns with the machine state intact the monitor will remove the LSB from the PowerSpan s IERO disabling mailbox 0 interrupts and leave a 1 flag in mailbox 0 indicating the monitor is ready for another command
218. thernet Ports Ethernet LEDs steady on Link Es flashing Activity L3 a O K9 GROUND 1 2 CHASSIS TO DIGITAL GND 2 3 ISOLATE co oo Y oo oo x ABRO 28888 2 0000 Is 0000 E nooo nooo LINK ENET B ENETA 124 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Rear Transition Modules Figure 6 2 RTM Diagrams Front I O CPC358 RTM Jumpers K1 K8 ENETA 1 2 REAR I O 2 3 2 16 CPSB ENETB O 120P0430XX 29 O ABC DEF oo 29 o PERFORMANCE o THOMNOLOGING PC358 RTM S N ENET A Ethernet Ports ENET B LINK Ethernet LEDs steady on Link flashing Activity 1 2 CHASSIS TO DIGITAL GND 2 3 ISOLATE K9 GROUND 125 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 6 Pinouts and Rear Transition Modules Pinouts Rear Transition Module Ethernet Ports The Rear Transition Module has two Ethernet port connections that can be set to exit either through a pair of RJ45 connectors mounted on the rear panel or through the J3 backplane connections There are also two LEDs
219. til cleared as follows If a 1 is written to this bit and the ejector switch has stabilized stopped bouncing the status bit will be cleared Writing a 0 to this bit will have no effect 7 5 RESV Always 0 Miscellaneous Status and Control Register The Miscellaneous Status and Control Register contains a number of functions that deal with various unrelated parts of the board The register contains status bits for the Factory Defaults burn in jumper the System Management Bus SMB Enable jumper and the CT Bus Mastership and CT Bus Reset Mastership jumpers CT bus not part of standard product It also has status and control bits for the Flash write protect and the I Am OK bit that is used to form the board Healthy signal on the Compact PCI Bus The bit definitions are as follows Table 4 36 Miscellaneous Status and Control Register Bit Fields PC8255 Bit O MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 0 LSB Field factdflt RESV smben ctbmstr ctrmstr RESV flashwp iamok Reset Value Current 0 Current Value 0 1 0 Value R W READ ONLY R W Address Base 46H 85 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description Table 4 37 Miscellaneous Status and Control Register Bit Field Definitions Bits Name Description 0 iamok The iamok bit is use
220. tion represents switch 1 bit 2 switch 2 bit 1 switch 3 and bit O switch 4 A 1 represents an open 6 4 RESV Always 0 pirstn This bit represents the current state of the CompactPCI reset signal A 0 indicates that the Compact PCI bus is reset A 1 indicates that the CompactPCI bus is activated Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 87 Chapter 4 Functional Description 88 P1 Reset Control Register The P1 Reset Control Register permits the MPC8255 to control the PowerSpan reset in the situation where the PCI bus is not present and the PCI bus interface is disabled Table 4 42 P1 Reset Control Register Bit Fields MPC8255 Bit O MSB 1 2 3 4 5 6 7 LSB Buffered Bus Bit 7 MSB 6 5 4 3 2 1 0 LSB Field RESERVED tunrstbit RESERVED Reset Value 0 See note below 0 R W READ ONLY R W READ ONLY Address Base 4AH Reset value of tunrstbit is pci_present_n output of NAND gate U74 indicating when low an actual PCI bus is present or being made to appear present when the board is operating in stand alone mode per jumper K38 2 3 pci busifen n jumper K6 2 3 Table 4 43 P1 Reset Control Register Bit Field Definitions Bits Name Description 7 3 RESV Always 0 2 tunrstbit This bit only has effect when the PCI bus is not present or configured to operate in a stand alone mode by
221. tion on diagnostic failure when set to IT 4 Give verbose output from boot process if set to 1 0x10 reserved 4 bytes 0x14 reserved 3 bytes 0x17 boot_stat2 1 byte Holds the flags from the real time clock 0x18 boot_stat3 4 bytes The number of the highest diagnostic to fail while booting Will be 0 if all diagnostics pass 0x1C boot_stat4 4 bytes 0 0x20 pci_cfg_did 2 bytes 0x3580 0x22 pci_cfg_vid 2 bytes 0x1214 0x24 pci_cfg_sdid 2 bytes 0x3580 0x26 pci_cfg_svid 2 bytes 0x1214 0x28 pspan_csr 4 bytes 0 0x2c pci_class 4 bytes 0x07800000 0x30 pspan_bst0 4 bytes 0 0x34 pspan bst1 4 bytes 0 0x38 pspan_bst2 4 bytes 0 0x3cC pspan_bst3 4 bytes 0 0x40 pspan tio0 ctl 4 bytes Oxe70a0240 0x44 pspan tioO ta 4 bytes 0x00000000 0x48 pspan tio1 ctl 4 bytes 0x000a0240 0x4c pspan tio2 ctl 4 bytes 0x000a0240 0x50 pspan_tio3_ctl 4 bytes 0x000a0240 0x54 pspan_idr 4 bytes 0x40000000 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Resources Used by the Monitor Table 5 3 NVRAM Structure Continued DEFAULT ADDRESS NAME SIZE DESCRIPTION VALUE 0x58 pspan_misc_csr 4 bytes 0x00000080 0x60 reserved 4 bytes 0 0x64 src 4 bytes First argument to 6 1 1900 MOVE MOVE is 0 executed before GO so that code linked to run in RAM may be copied from FLASH 0x68 dest 4 bytes Second argument to 6 1 1900 MOVE 0 0x6C size 4 bytes Third argument to 6 1 1
222. tments to J3 for other electrical Interfaces Table 6 16 DTE RS232 Adjustments for J3 Pin Signal Name Adjustment J3 D6 CTS6 Ground for RS 232 signal ground J3 D10 CTS7 Ground for RS 232 signal ground J3 D2 CTS8 Ground for RS 232 signal ground Table 6 17 DTE V 35 Adjustments for J3 Pin Signal Name Adjustment J3 D6 CTS6 Ground for V 35 unused wire J3 D10 CTS7 Ground for V 35 unused wire J3D 2 CTS8 Ground for V 35 unused wire J3 E6 DTR6 Ground for V 35 unused wire J3 E10 DTR7 Ground for V 35 unused wire J3 E2 DTR8 Ground for V 35 unused wire J3 A6 RTS6 Ground for V 35 signal ground J3 A10 RTS7 Ground for V 35 signal ground J3 A2 RTS8 Ground for V 35 signal ground J3 B6 DCD6 Connected to V 35 Ring Indicator for port 6 J3 B10 DCD7 Connected to V 35 Ring Indicator for port 7 J3 B2 DCD8 Connected to V 35 Ring Indicator for port 8 J3 C6 DSR6 Connected to V 35 Line Test for port 6 J3 C10 DSR7 Connected to V 35 Line Test for port 7 J3 C2 DSR8 Connected to V 35 Line Test for port 8 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com J4 Connector Pinout Note This connector is not installed on standard product Table 6 18 J4 CompactPCI Connections Pin A B C D E F 25 SGA4 SGA3 SGA2 SGA1 SGAO NC 24 GA4 GA3 GA2 GA1 GAO NC 23 N
223. trol MODCLKx Apx TCx BANKSELx are used as the MODCLKx inputs during hard reset and as BNKSELx for the SDRAM module PGPL3 IPSDCAS is used as the IPSDCAS for the SDRAM module PGPL2 PSDRAS POE is used as the PSDRAS for the SDRAM module and POE for custom registers PGPL1 PSDWE is used as the IPSDWE for the SDRAM module PGPLO PSDA10 is used as PSDA10 for the SDRAM module The external cache lines are not used and are therefore not connected The internal CPU arbiter is used as the bus arbiter All of the normal 60x bus transfer size TSIZE0 3 and transfer type TTO 4 lines are supported The rest of the transfer control signals are used in their normal mode All of the control signals are pulled to V3V with 10K resistors to prevent accidental activation during no drive periods on the bus Master MPC8255 Interrupt Sources Several multifunction pins are used to supply the MPC8255 with the direct connect interrupts from the various board peripherals The IRQO IRQ6 IRQ7 and Interrupt capable Port C lines are used The interrupt sources for the most part have multiple interrupt conditions Refer to the individual component subsections or the component s user manual for the complete breakdown of interrupt causes Table 4 14 shows the connections from these devices to the MPC8255 Table 4 14 Master MPC8255 Interrupt Sources IRQ Level Pin Number Controlled Device IRQO T1 NMI Interrupt from the Abort Jumper K39 1 2 IR
224. ty Instrumentation Guaranteed 888 88 SOURCE www artisantg com Figure 5 1 Boot Flow Chart part 1 llluminate yellow LED Pause for 3 seconds collecting characters at the console Has Enter been pressed 3 times Quit boot process If NVRAM is not initialized initialize it i Fetch and save RTC flags register Reset due to RTC Watchdog expiration Boot anyway Run diagnostics Resources Used by the Monitor Remove HEALTHY and illuminate blue LED Run all diagnostics Quit boot process Run last diagnostic PowerSpan Access only Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com 121 Chapter 5 Boot PROM and Forth Monitor Figure 5 2 Boot Flow Chart part 2 Diagnostic failure Boot anyway y Configure PCI Illuminate green LED Boot automatically YES Y Move code if nv size gt O GO at nv boot_addr Remove HEALTHY and illuminate blue LED Quit boot process Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter A AAN AAA AAA A d IA Pinouts and Rear Transition Modules This c
225. ual for more information on the various peripheral setups There is only one set of functions supported on the Slave MPC8255 They are the 4 SCC ports Slave MPC8255 SCC Ports The Slave MPC8255 has SCC ports SCC1 to SCC4 assigned to Serial I O ports on both the front panel on J7 and the Rear Transition Module on J2 The front or rear I O option is accomplished by a build option and the actual switching of the signals from the front connector to the rear is through a set of zero ohm jumpers Each port will also be able to have its electrical configuration set to either RS 232 RS 422 or V 35 by a set of registers located in PLD PSM554 Cabling options will allow RS 232 DTE RS 449 DTE RS 449 DCE V 35 DTE and V 35 DCE configurations Even though the ports are individually programmable current cabling constraints will limit the options to two groups of four identically programmed ports Each port will be able to be individually tri stated Each port will support Transmit Data Transmit Clock Receive Data Receive Clock Clear to Send Request to Send Carrier Detect on the Master MPC8255 port pins assigned to each SCC In addition each port has Data Terminal Ready and Data Set Ready connected to general purpose I O pins on the Master MPC8255 See Slave MPC8255 Parallel Port Pin Assignments on page 176 for the appropriate Master MPC8255 port pins SDRAM The SDRAM for CPC358 is connected to the 60x bus and is accessible by any of the 60x bus
226. up Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Figures y oa PN VN NA Xy DAA AS Figure 3 1 CompactPCI Chassis ester ra a ek ae NENENG ee 34 Figure 3 2 CPC358 Front Panel cues veto derredor dada ES 35 Figure 3 3 CPC358 Board Layout 1 usce venen bere Nu he Rae 36 Figure 3 4 Additional Jumper Locations AA 37 Figure 4 1 Block Diagram of CPC358 oe aaseters ennen a PE EP Ears 44 Figure 4 2 Partial SDRAM State Diagram eneen eee 60 Figure 4 3 External Master SDRAM Configuration eenen eee 62 Figure 4 4 Flash Block Diagram sies aser Ric vee Na ds gc ak A nie ane 63 Figure 4 5 Application Flash Block Diagram anean 66 Figure 4 6 TOD Block Diagram uei wr Bey eee SERO ee y REVERSA NIRE REGE EE 67 Figure 4 7 Communications Buffer Memory Block Diagram illii 69 Figure 4 8 Ethernet Dual PHY Block Diagram ccc ee 75 Figure 4 9 Serial I O Port Block Diagram neee eee 78 Figure 4 10 Clock Steering saci caged meent brek CRURA RR a Ee eR Ri ees 79 Figure 4 11 General Purpose Registers Block Diagram 0000 e eee eee eee 81 Figure 4 12 Port Control Registers Block Diagram 00000 cece eee 94 Figure 5 1 Boot Flow Chart part 1 eeen 121 Figure 5 2 Boot Flow Chart part 2 ee 122 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Figures Figure 6 1 RTM Diagrams
227. urce reset on the Primary PCI bus 1and the local processor or PB bus The setup on each source is as follows Primary PCI Reset In the CPC358 implementation the chip is set to receive a reset on the primary PCI 1 bus and to not be a source This is accomplished by setting the P1 RST DIR pin low The P1_RST signal from the PCI bus will cause logic within the chip to be reset as outlined in the Tundra users manual The P1 RST also causes a PQ_HRESET to the board as described in the Hard Reset section Processor Bus Reset The Power Span Processor Bus reset pin PB_RST is configured to be an input This is accomplished by setting the PB RST DIR pin low The source of the signal is the PSM552 logic The logic drives the PB RST pin with a standard driver output and it drives the signal true when PQ_HRESET is true or whenever the Reset Configuration jumper K16 is in the PROM Programming Position K16 1 2 47 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com Chapter 4 Functional Description Peripheral Resets Each peripheral chip on the CPC358 has an individual reset line The peripheral resets are driven by the PSM552 PLD logic The resets are all set to a reset state by anything that creates a PQ_SRESET on the board The devices will be held in reset until the appropriate bit in the general purpose registers is set Table 4 5 describes the individual peripheral reset signals the pow

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