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1. N OUT Koyo Ai CLASS 24VDC 5 6 rs 10 11 3 4 5 A No 9 9 9 T EEE EEE GB AB AAR OV G CA Xn 5 Xn 6 Xn 7 Xn 10 Xn 11 Yn 3 Yn 4 Yn 5 T 1 2 3 Xn 0 Xn 1 Xn 2 Xn 3 Xn 4 CB Yn 0 Yn 1 Yn 2 o o J P 12 24000 T 24006 S ol o External Input Wiring PANES Output Wiring Power Supply Solid State NPN Typical Input Circuit Typical Output Circuit Field Device Wiring 12 24VDC Common gt 9 PERPEN a Output aBa To LED To LED L G WE gt Output Se ee pial S KH ke Current Sourcing inputs Input solar omen NPN Current Sinking Current Sourcing inputs Current Sinking Output Field Device Derating Chart for Derating Chart for Points D4 SS 106Inputs Points _D4 SS 106 Outputs 10 6 Output Current 0 5A point 0 0 0 10 20 30 40 50 60 C 0 10 20 30 40 50 60 C 32 50 68 86 104 122 140 F 32 50 68 86 104 122 140 F Ambient Temperature C F Ambient Temperature C F P 12 Installation and Wiring D4 SS I O Field Device Wiring Diagram 16N Use the following wiring diagram to connect the field wiring to the I
2. X10 X1 2nd Slice Remote 0 6 07 3 ww ay iy Qy 076 as X10 x1 0 gt 6 0 gt 3rd Slice Remote CO TO 1 00 T Cy IN Gy 3 eR 9 E0 Align the arrow on the switch to any numbers between 01 and 15 decimal depending on which slave in sequence you are setting up and how many slaves are allowed per master Remember each addressing mode automatic manual and discrete has a particular limit on how many slaves can be connected to the master NOTE Always use consecutive numbers for slaves and always start with Address 01 not 00 don t skip numbers 3 0 Installation and Wiring Example Showing Herestheway Steps 3 and 4 would be carried out for a system with one master and ProperSettingof three slaves set to communicate at 153 6 kB Switches Main Base with Master Rotary Switches Dip Switch Master Address Baud Rate Module Can go in any slot ON CPU and N PS 1st Slice Remote 1000 oO N Nx CLS ch x 6 E18 AR x ES 2
3. The RLL shown to the right is only that part of the Slice I O 5000 C672 _ setup that configures the 2nd Master and its Slaves P ell CPU that this is 11 sET the beginning of setup Slaves belong to 2nd Master LDA Octal 40000 is the Configured Manually 040000 internal buffer address or GX0 This is GX0 GX17 GX60 GX77 determined by looking inputs outputs at the table in Appendix Slaves belong to 1st Master Second Master OUT nput Starting Address Configured Automatically bo Slice Slave Inputs V7444 Pointer for 2nd Master LD Total number of input K48 points BCD that are nt GX20 GX37 GX100 GK117 being configured cee inputs outputs f OUT Corresponding AAN E V7445 Pointer p 3 Second Master as Slice Slave Outputs LDA Octal 40003 is the Y220 Y237 Samay O40003 internal buffer go address for GX60 GX40 GX57 GX120 OUT Output Starting Address inputs output V7446 Pointer for 2nd Master X240 X257 l a Y240 Y257 LD Total number of output g el 6 48 points BCD that are e _ being configured OUT Corresponding V7447 Pointer Note From a point of consistency you might prefer to manually configure 60674 the Slice I O for both Masters This example is for illustration only 667 End setup for 2nd Master How the CPU Updates Slice I O Points The CPU and Slice Master work together to update the remote Slice I O points Below is an example showing how scannin
4. 2nd Slice Remote X10 X1 6 0 007 oy al PIRE i o o ws Cy N X10 X1 3rd Slice Remote 99 A l6 7 Ee lO KI 8 6 i Table for setting DIP switch Baud Rate 19 2kB 38 4kB 153 6kB 614 4kB Master 1 OFF ON OFF ON 2 OFF OFF ON ON Note Position 4 of the Master enables or disables the system s ability to make use of discrete addressing or the automatic slave removal 3 Not used should always be OFF a 4 See See feature Note Note ON Features enabled OFF Features disabled OFF ON Remote 2 OFF OFF Installation and Wiring Step 5 Connect the Communications Cable Cabling Between The following diagram shows the cabling between the master and its slaves We the Master and recommend Belden 9841 or its equivalent for connecting the Master and Slaves Slaves This is twisted pair cable The two inner wires are connected to terminals 1 and 2 of each module The shield wire is connected to terminal 3 NOTE Do not connect the shield wire to the Ground terminal Make sure the the connections between master and all slaves are always 7 to 1 2 to 2 and 3 to 3 Maste
5. z r 7 Direct SLICE 0 102 26 4Vpo 5 26 4Vpo VO STARTING LOGIC 4mA 12mA 0 2mA 0 5mA ADDRESS J CLASS 2 CLASS 2 Koyo CA 24VDC 4 5 6 7 4 5 6 7 025A L gt 104 pd 121 sce 0 1 2 3 CLASS 2 rT 1 2 3 9 5 9 le ol tH Op Ga 9 9 1 T No GE EEE CE EA 04 99 08 STS SS SS 24V OV G CA Xn 4 Xn 5 Xn 6 Xn 7 Yn 4 Yn 5 Yn 6 Yn 7 o 2 J o T 1 2 3 Xn 0 Xn 1 Xn 2 Xn 3 CB Yn 0 Yn 1 Yn 2 Yn 3 iJ iJ iJ tJ l ss 12 24VDC eh 24006 O EE ol o O Oo 1 a 5 24VDC as External Input Wiring Output Wiring Power Supply Solid State NPN Typical Input Circuit Typical Output Circuit Field Device Wiring 12 24VDC Common Optical R Conran Output lsolator L ij t i G To LED To LED L ED f FG Lg Sensor Output ew 4 TF a To LED T 0988 E g ut 6 4 j Optical Commo
6. 000 c cee eee eee eee eee 4 9 Sample Ladder Logic for Automatic Slave Removal LL 4 9 Rejoining Slaves NN 4 10 Whatis Ws EHIME eet Akane ey a em ee ae SE meee se cemere et ote 4 10 How ISt DONE oh sec ete a ec ae eda i Pa Rett ces date ste eck tg dae A 4 10 Example of Rejoining a Slave i 4 10 Special Relays Used for Slice OO 4 11 How to Use the Special Relays uu 4 12 2672 60670 6006 V4 ate a ea AM Sse sth NM MS a GAM Se Grit abel on Seacoast abel Sea Nat 4 12 C671 C675 I O Status OO et esd 4 12 C673 C677 Activate Removal or Rejoining of Slaves Li 4 13 C700 C720 Locate Communications Error i 4 14 C710 and C730 Mapping O K EEKNKKNKNK KN 4 15 Appendix A Slice I O Worksheet Appendix B Memory Tables Standard Input X Addresses uu B 2 Standard Output Y Addresses i cc cece cece eee B 3 Control Relay C Addresses OL OO B 4 Remote Input Output Global GX Addresses LL B 6 Appendix C Determining I O Update Time Overview De C 2 Calculating Input Signal Delay Time 1 C 3 Input Delay Time Formulas ea So scence vat So a eae a ra C 3 Example for Computing Input Delay ii C 3 Calculating Output Signal Delay Time C 4 Output Delay Time Formulas NN ave pt cenit AG cl a hast ny ahs meaner Qtek dats ave See C 4 Example for Computing Output Delay ii C 4 Calculati
7. ore O Operation Output Slave 1 of Slave 1 Input 6 Inputs TO Operation i lt lt Read Inputs of Slave N Output Slave N User Logic Execution input Scone Outputs T p ransfer of I O BE bo Update Outputs Information 1 0 Operation of Slave 1 Output Slave 1 i Input 3 Inputs 7O Operation Read Inputs lt i of Slave N E Output Slave N Scan 3 User Logic Execution npu Outputs Transfer of I O gt Update Outputs 2 Information edge Etc Etc Etc NOTE In some cases it may be helpful to understand the update time required for a Slice I O system Appendix C shows example calculations 3 Steps for Setting Up Slice I O Step One Design the System you how many Slice masters and Slice slaves you will need In Chapter 2 we will Step Two Install the Components Step Three Write the Setup Program First figure out how many I O points you will need at each remote drop This will tell show you how to use worksheets to plan and keep track of your data type assignments We ll also show you how to determine the correct addresses for reading and writing the Slice I O data eno t Slice Slave Worksheet TNPUT OUTPUT poe inpat naanss Ma inputs onarma Ni 1E only on vasso He 1 emU 71909 tectonly idee 3 passtos xeo TE Won heon ce Input
8. D 3 4 a t Writing the Setup Program How to Use the Special Relays C672 C670 C674 8 OU 2 5 D 09 C671 C675 O Status On Error Here are some example uses of these relays and an added explanation for each of the relays discussed on the previous page These are setup flags for marking the beginning and end of your ladder logic that sets up your Slice I O configuration C672 marks beginning of all addressing logic C670 is for ending setup for the 1st Master and C674 for the 2nd Example Begin End Setup for Manual Addressing of 1st Master SP00 C672 SET Begin setup LDA 040400 First Master OUT Slice Slave Inputs V7404 __ LD K48 __ OUT V7405 First Master Slice Slave outputs LDA 040500 __ OUT V7406 LD K48 __ OUT V7407 C670 SET End setup C671 is assigned to the 1st Master C675 is assigned to the 2nd Master When any master can t talk to one or more of its slaves the link LED will come on to indicate that there is a problem The system will stop updating the remote I O status in the CPU for that slave unit You have several options at that point One such option is either to freeze the last known input status that is in the CPU s memory image area or to write a zero to each point If these flags are OFF when the error occurs all inputs will be zeroed Example SPO C6
9. 04 68 07 DD AD AD DGB AD S AD 24V OV G CA Yn 4 Yn 5 Yn 6 Yn 7 Yn 14 Yn 15 Yn 16 Yn 17 o 2 o o o o T 1 2 3 Yn 0 Yn 1 Yn 2 Yn 3 CB Yn 10 Yn 11 Yn 12 Yn 13 tJ iJ 1 5 24VDC 24vDC TODO eee Toh E External Output Wiring Output Wiring Power Supply Typical Output Circuit Derating Chart for Points _D4 SS 16T Outputs 16 Output Current Optical B 0 35A point 7 Output lsolator 12 Output Current L 0 5Apoint _L 5 24 gt 8 3A common T VDC f 3 To LED 4 a Common Current Sinking Output 0 10 20 30 40 50 60 C 32 50 68 86 104 122 140 F Ambient Temperature C F S 14 Installation and Wiring Optional Features Connecting the The master module has a normally open Run Output Circuit relay that closes when communication is successfully made between the master and its slaves Each module has its own LED indicator labeled LINK that glows if there is a communications error or no link The Run Output relay of the master module can be wired to a 24 VDC sinking input module so that ladder logic can be H written to monitor the communications link The bottom two terminals of the terminal block are where the wires are connected from the input module The Run Output relay can handl
10. our When Bit 1 is OFF turn ON Y41 Problem with Slave 1 C710 C22 Y42 H e out When Bit 2 is OFFturn ON Y42 Problem with Slave 2 Continue with as many rungs as you have slaves Note C20 is not used here because the first bit does not mean anything for the mapping check Since bit 0 is not used the first control relay that contains slave information is C21 Also notice how the control relays relate to the slave number You should remember that control relays are numbered in octal not decimal For example you ll notice that slave 8 is represented by C30 in this example V7702 1st master showing that everything is O K except Slave 8 has not been mapped properly Remember the bit is off when a problem exists D D fa e Q Q 3 Slave bt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1111111111111101111111111 111110 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1111111111111101111111111111110 C37 C36 C35 C34 C33 C32 031 030 C27 C26 C25 C24 C23 022 C21 C20 V40601 Control Relays C20 C37 The only addressing mode that allows mapping of each individual slave is discrete addressing This is how individual slaves can be mapped improperly and result inthe error bit status shown above Appendix A Slice I O Worksheet A A 2 Slice I O Wor
11. 1022 1021 1020 V40641 1057 1056 1055 1054 1053 1052 1051 1050 1047 1046 1045 1044 1043 1042 1041 1040 V40642 1077 1076 1075 1074 1073 1072 1071 1070 1067 1066 1065 1064 1063 1062 1061 1060 V40643 1117 1116 1115 1114 1113 1112 1111 1110 1107 1106 1105 1104 1103 1102 1101 1100 V40644 1137 1136 1135 1134 1133 1132 1131 1130 1127 1126 1125 1124 1123 1122 1121 1120 V40645 1157 1156 1155 1154 1153 1152 1151 1150 1147 1146 1145 1144 1143 1142 1141 1140 V40646 1177 1176 1175 1174 1173 1172 1171 1170 1167 1166 1165 1164 1163 1162 1161 1160 V40647 1217 1216 1215 1214 1213 1212 1211 1210 1207 1206 1205 1204 1203 1202 1201 1200 V40650 1237 1236 1235 1234 1233 1232 1231 1230 1227 1226 1225 1224 1223 1222 1221 1220 V40651 1257 1256 1255 1254 1253 1252 1251 1250 1247 1246 1245 1244 1243 1242 1241 1240 V40652 1277 1276 1275 1274 1273 1272 1271 1270 1267 1266 1265 1264 1263 1262 1261 1260 V40653 1317 1316 1315 1314 1313 1312 1311 1310 1307 1306 1305 1304 1303 1302 1301 1300 V40654 1337 1336 1335 1334 1333 1332 1331 1330 1327 1326 1325 1324 1323 1322 1321 1320 V40655 1357 1356 1355 1354 1353 1352 1351 1350
12. 172 171 170 167 166 165 164 163 162 161 160 V40607 217 216 215 214 213 212 211 210 207 206 205 204 203 202 201 200 V40610 237 236 235 234 233 232 231 230 227 226 225 224 223 222 221 220 V40611 257 256 255 254 253 252 251 250 247 246 245 244 243 242 241 240 V40612 277 276 275 274 273 272 271 270 267 266 265 264 263 262 261 260 V40613 317 316 315 314 313 312 311 310 307 306 305 304 303 302 301 300 V40614 337 336 335 334 333 332 331 330 327 326 325 324 323 322 321 320 V40615 357 356 355 354 353 352 351 350 347 346 345 344 343 342 341 340 V40616 377 376 375 374 373 372 371 370 367 366 365 364 363 362 361 360 V40617 417 416 415 414 413 412 411 410 407 406 405 404 403 402 401 400 V40620 437 436 435 434 433 432 431 430 427 426 425 424 423 422 421 420 V40621 457 456 455 454 453 452 451 450 447 446 445 444 443 442 441 440 V40622 477 476 475 474 473 472 471 470 467 466 465 464 463 462 461 460 V40623 517 516 515 514 513 512 511 510 507 506 505 504 503 502 501 500 V40624 537 536 535 534 533 532 531 530 527 526 525 524 523 522 521 520 V40625
13. 557 556 555 554 553 552 551 550 547 546 545 544 543 542 541 540 V40626 577 576 575 574 573 572 571 570 567 566 565 564 563 562 561 560 V40627 617 616 615 614 613 612 611 610 607 606 605 604 603 602 601 600 V40630 637 636 635 634 633 632 631 630 627 626 625 624 623 622 621 620 V40631 657 656 655 654 653 652 651 650 647 646 645 644 643 642 641 640 V40632 677 76 675 674 673 672 671 670 667 666 665 664 663 662 661 660 V40633 717 716 715 714 713 712 711 710 707 706 705 704 703 702 701 700 V40634 737 736 735 734 733 732 731 730 727 727 742 724 723 722 721 720 V40635 Memory Tables This portion of the table shows additional Control Relays points available with the DL440 MSB DL440 Additional Control Relays C LSB 17 16 15 14 18 12 11 10 7 6 5 4 3 2 1 0 757 756 755 754 753 752 751 750 747 746 745 744 743 742 741 740 V40636 777 776 775 774 773 772 771 770 767 766 765 764 763 762 761 760 V40637 1017 1016 1015 1014 1013 1012 1011 1010 1007 1006 1005 1004 1003 1002 1001 1000 V40640 1037 1036 1035 1034 1033 1032 1031 1030 1027 1026 1025 1024 1023
14. A one shot turns ON a timer Note Use of the one shot ensures that the timer will not turn ON again unless XO transitions ON to OFF then ON again C1 C2 SET C2 TMR TO Timer used to make sure that C673 is K10 OFF for at least 500 msec Setup Bit for vo K5 1st Master C673 VO is the current count of the timer When it is greater our than or equal to 500ms 5 1 10ths of a second it will turn ON C673 TO C2 RST After 1 second 1000ms the timer contact is on which resets C2 Since C2 is the input contact for the Timer the timer is now disabled and C673 is turned off 4 Writing the Setup Program 4 11 Special Relays Used for Slice I O The Slice I O system has several relays that are used with your system Some of these relays can be used in RLL routines that will detect and solve errors as a troubleshooting tool In some cases i e C700 C720 C710 C730 you can use DirectSOFT to look in corresponding V memory addresses for more information on the error The following table lists all of the special relays assigned for Slice I O Function First Master Second Master Description of Relay Relay s Relay s End of Setup C670 C674 When set these relays signify the end of the setup for all addressing modes Clear I O on Error C671 C675 These two relays are for determining whether you want the remote Automatic Slave Removal input points to be set to zero when an error occurs or whether you want
15. baud rate for communication with Koya oa aoi the master module Located on the back of the unit Com Port 15 pin female D shell communications port This port is identical to the top port on the DL405 CPUs You can program or monitor the CPU with a handheld programmer or DirectSOFT through this port You can also connect a DV 1000 Operator Interface to this port Connection Screws For attaching power supply twisted pair communication cable and input and output points Varies by model number Rotary Switches Used to set unit address General Slaves per channel See text for details 15 12 or 7 depending on addressing mode Specifications Module Type Non intelligent slave Installation Requirements No base required Power Required 24 VDC external 15 60mA max at 24 VDC with no handheld programmer 250mA max at 24 VDC with a handheld programmer Run Output Relay Rating 250 VAC at 1A 30 VDC at 1A Communication Baud Rates 19 2 38 4 153 6 614 4 kB Switch Selectable Communication Cabling RS 485 twisted pair Belden 9271 or equivalent Operating Temperature 32 to 140 F 0 to 60 C Storage Temperature 4 to 158 F 20 to 70 C Relative Humidity 5 to 95 non condensing Environmental air No corrosive gases permitted Vibration MIL STD 810C 514 2 Shock MIL STD 810C
16. 1 DL405 handheld Half duplex programmer cable 9 24ft 3m ea D4 HPCBL 2 DL405 handheld programmer cable 4 6ft 1 5m e D4 1000CBL DV 1000 cable 6 56ft 2m Since the handheld programmer and the DV 1000 obtain their operating power from the Slave unit we strongly suggest that you use the standard cables for these devices However there may be an occasion where you need to quickly make your own programming cable for use with your laptop or personal computer In this case use the following cable pinout diagrams Personal Computer Slice Slave Personal Computer Slice Slave RS232C 1 YOP RS232C 1 YOP 2 TXD 2 TXD 2 TXD 3 RXD 3 RXD 3 RXD 3 RXD 2 TXD 5 GND 4 Online 7 GND 4 Online m 1 DCD 7 CTS 4 RTS 7 CTS 4 DTR 8 YoM L 5 CTS 8 YOM L 6 DSR 13 OV 6 DSR 13 OV 7 RTS 14 OV 8 DCD 14 0V 8 CTS 15 0V L 20 DTR 15 OV 9 pin DCE 15 pin Connector 15 pin Connector Connector 25 pin DTE Connector Pin labeling conforms to the IBM DTE and DCE standards Writing the Setup Program In This Chapter Choosing a Programming Device Writing Your Slice I O Setup Slave Removal Rejoining Slaves Special Relays Used for Slice I O How to Use the Special Relays 4 ane Writing the Setup Program Choosing a Programming Device You can write your setup logic by using either a handheld p
17. 12 ms 5 Solve the equation from Step 1 OUTmax 0 5 ms 2B C OUT max 0 5 ms 2 15 12 OUT max 42 5 ms Determining I O Update Time ono Calculating Total System Delay Time Output Delay Time Here we are calculating the total delay time for a simple Slice I O example Once the Formulas Table Showing Approximate Slice slave input comes on we want to know how long it will take the system to sense the input change transfer the data back to the CPU and then update the Slice slave output point The formulas for computing this are as follows bad TOTmax Imax 4B C TOTavg Imin 2B C TOTmin Minimum total signal delay TOT max Maximum total signal delay TOTavg Average total signal delay Imax Maximum input signal delay Imin Minimum input signal delay B Bus scan time See Table Below C CPU scan time follow instructions on Page C 3 Slot Location of V memory Location where the bus scan time is calculated and the Master stored as a hexadecimal number of milliseconds V7710 V7711 V7712 V7713 V7714 V7715 V7716 V7717 Before you actually do your own computations using the formulas above you may want to have an approximate idea of how much total delay time you should expect Signal Delay Times This table should provide that information We leave the actual computation up to you In this example we are assuming that we are using a 440 CPU and the scan time for ahypothetic
18. 1347 1346 1345 1344 1343 1342 1341 1340 V40656 1377 1376 1375 1374 1373 1372 1371 1370 1367 1366 1365 1364 1363 1362 1361 1360 V40657 1417 1416 1415 1414 1413 1412 1411 1410 1407 1406 1405 1404 1403 1402 1401 1400 V40660 1437 1436 1435 1434 1433 1432 1431 1430 1427 1426 1425 1424 1423 1422 1421 1420 V40661 1457 1456 1455 1454 1453 1452 1451 1450 1447 1446 1445 1444 1443 1442 1441 1440 V40662 1477 1476 1475 1474 1473 1472 1471 1470 1467 1466 1465 1464 1463 1462 1461 1460 V40663 1517 1516 1515 1514 1513 1512 1511 1510 1507 1506 1505 1504 1503 1502 1501 1500 V40664 1537 1536 1535 1534 1533 1532 1531 1530 1527 1526 1525 1524 1523 1522 1521 1520 V40665 1557 1556 1555 1554 1553 1552 1551 1550 1547 1546 1545 1544 1543 1542 1541 1540 V40666 1577 1576 1575 1574 1573 1572 1571 1570 1567 1566 1565 1564 1563 1562 1561 1560 V40667 1617 1616 1615 1614 1613 1612 1611 1610 1607 1606 1605 1604 1603 1602 1601 1600 V40670 1637 1636 1635 1634 1633 1632 1631 1630 1627 1626 1625 1624 1623 1622 1621 1620 V40671 1657 1656 1655 1654 1653 1652 1651 1650 1647 1646 1645 1644 1643 1642 1641 1640 V40672 1677 1676 1675
19. 1st master module of Slice Slave the example system shown on the previous page Worksheet for the ist Master Master Module No Slice Slave Worksheet elec INPUT OUTPUT Address Name Input Address Output Address D4 SS 88 X200 16 only 8 used Y200 16 only 8 used D4 SS 104 X220 16 only 10 used Y220 16 only 6 used D4 SS 104 X240 16 only 10 used Y240 16 only 6 used Input Bit Start Address X200 V Memory Address V__N A automatic Total Input Points Consumed_ 48 Input Points Used 28 Output Bit Start Address Y200 V Memory Address V__N A automatic Total Output Points Consumed_ 48 Output Points Used 20 For the 1st master we have decided to use automatic addressing for its slaves This means that inputs X s and outputs Y s will be assigned starting at X200 and Y200 respectively With automatic addressing we do not have to worry about looking up the V memory addresses for the master module s internal memory and the slave I O points because the information is automatically mapped to the CPU s memory image area Unlike manual or discrete addressing you do not have to write ladder logic to setup the mapping process This is why we have written N A in the V memory area of the form Now let s complete go to the next page and fill out a worksheet for the 2nd master 0 Designing the Slice I O System Filling Out the Slice Slave Worksheet for the 2nd Master The following Slice Slave work
20. 516 2 Noise Immunity NEMA ICS3 304 Slice Slave Input Specifications Slice Slave Output Specifications Rated Input Voltage 12 24 VDC Operating Voltage 10 2 26 4 VDC Input Current 3 8 mA 12 VDC 8 3 mA 24 VDC Maximum Voltage 26 4 VDC ON Current Voltage gt 3 5 mA 10 2 VDC OFF Current Voltage lt 1 5 mA 4 0 VDC OFF to ON Response lt 7 ms ON to OFF Response lt 12 ms Number of input points D4 SS 88 8 Consumes 16 inputs however D4 SS 16N 16 D4 SS 16T None D4 SS 106 10 Consumes 16 inputs however Commons D4 SS 88 8 points per common D4 SS 16N 16 points per common D4 SS 16T N A no input available D4 SS 106 10 points per common Wire Gauge AWG22 AWG18 Output Circuitry NPN Open Collector Operating Voltage 4 5 26 4 VDC Output Current 0 5A point subject to derating see Chapter 3 3 0A common Maximum Voltage 40 VDC Maximum Leakage Current 0 1mA 40 VDC ON Voltage Drop 1 0V 0 5A Smallest Recommended Load 0 2mA Maximum Inrush Current 1 0A for 100ms 2 0A for 10ms OFF to ON Response 0 5ms ON to OFF Response 0 5ms Fuses 1 5 0A fuse per output common Number of output points D4 SS 88 8 Consumes 16 outputs however D4 SS 16N None D4 SS 16T 16 D4 SS 106 6 Consumes 16 outputs however Commons D4 SS 88 1 8 point
21. Bit ftant addvess __ z0 Total mput Poimts co Output Bit Stat Addi Total dutput Points Consumed 95 Output Pomnts Used_1 Set the hardware switches so that the CPU can identify the master and slave units This also will set the baud rate for data transfer and designate how the slave units are numbered i e No 1 No 2 and so on Then insert the master s into the base and mount the slaves Wire all of your I O to match your information in Step 1 Covered in Chapter 3 Write the RLL setup program Covered 8000 0672 10 Chapter 4 SET Manual addressing for GX mapping for 60460096 the 1st Master The next two pages provide a complete ein overview of the entire process for an 7404 example Slice I O system Of course to Has learn all of the details you should read OOT each chapter carefully V7405 LDA 040003 __ OUT V7406 Lokas OUT V7407 C670 End setup for SET 1st Master 4 EXAMPLE Step 1 Design the Slice I O System In this example we are using only one The worksheet is included in Appendix A You don t master and three Slice slaves We are have to use a worksheet but it may help organize setting the baud rate to 153 6 kB and your planning and even make the task of writing we are using manual addr
22. External Resistor You add your own resistor using a resistor between 100 and 300 ohms to match the impedance of the cable Option 3 Slave Unit Internal Wiring External Resistor in Series jntermal i With this option you use an external 150 ohm Se resistor in series with the internal resistor resistor The series resistance should match the cabling impedance ab a Ob OB You add your own resistor in series with the 150 ohm internal resistor to JVV match the cable impedance External Resistor 3 3 Installation and Wiring Step 6 Connect the Field Wiring General Wiring You should consider the following wiring guidelines when wiring your system Guidelines 1 There is a limit to the size of wire the modules can accept 16 AWG to 24 AWG is recommended Smaller AWG is acceptable 2 Always use a continuous length of wire do not combine wires to attain a needed length Use the shortest possible cable length Where possible use wire trays for routing Avoid running wires near high energy wiring Avoid running input wiring in close proximity to output wiring where possible 7 To minimize voltage drops when wires must run a long distance consider using multiple wires for the return line 8 Where possible avoid running DC wiring or communication cabling in close proximity to AC wiring 9 Avoid cr
23. O terminal strip The I O point addresses have been labeled Xn and Yn to indicate the starting address The X and Y data types have only been used for illustration purposes Your exact starting addresses and data types depend on the addressing mode selected NPN Current Sinking Field Device Current Sourcing inputs D gt 16 12 24VDC INPUT a INPUT g PWR RUN DIAG LINK Direct SLICE 0 102 26 4VDC Ta Koyo cn 1 5 1 5 RA L oh Ti 7h PA mone HE Lp 2 6 2 6 C SS T T T ol 8 3 7 3 7 1 1 1 a 1 8 C Gre PEEEESEESEREE 64661 SOT Dee RBI S eo 24V ov G CA Xn 4 Xn 5 Xn 6 Xn 7 Xn 14 Xn 15 Xn 16 Xn 17 T 1 2 3 Xn 0 Xn 1 Xn 2 Xn 3 CB Xn 10 Xn 11 Xn 12 Xn 13 iJ iJ iJ o iJ iJ it iy 12 24VDC 24000 ol ol o 1 9 9 1 ol ol o j j o External Input Wiring ND Input Wiring Power Supply Solid State NPN Typical Input Circuit Derating Chart for Field Device Wir
24. X40 X51 actually used Input Bit Start Address X20 V Memory Address V_40401 Y60 Y77 consumed Y60 Y65 actually used Total Input Points Consumed_48 Input Points Used 30 3rd Slice Remote Output Bit Start Address Y40 V Memory Address V_ 40502 Total Output Points Consumed_48 Output Points Used__18 D4 SS 106 9 ro X60 X77 consumed X60 X71 actually used Y100 Y117 consumed Y100 Y115 actually used Note Manual addressing will support 15 slaves per master Automatic addressing will support 12 slaves per master Discrete addressing will support 7 slaves per Slice master Automatic addressing can only be used by one of two masters mounted in the CPU base Manual and discrete addressing can be used with both masters Getting Started Step 2 Set the Hardware Step 3 Write the Setup Program RLL Program Table for setting DIP switch SP00 K1 Go to remote I O Baud Rate 19 2kB 38 4kB 153 6kB 614 4kB GTS Sorouine 1 SEE ON EE ON Main Program Body Master END SBR Ki H H 2 OFF OFF ON ON Slice I O Subroutine Note Write as subroutine only if using D4 440 CPU For D4 430 this mu
25. address so that zeros 0 are in every bit position where you want a slave rejoined Leave 1 s in the bit positions where you have slaves removed that you wish to remain removed 2 Transition the setup bit C673 or C677 from OFF at least 500ms to ON at least 500ms NOTE The rejoining process causes the CPU to look at the bit pattern in the primary pointer address and REJOIN any slave that has a corresponding bit that is 0 and REMOVE any slave that has a corresponding bit that is set to 1 For example if you write a zero to bit 3 in order to rejoin Slave 3 but you have bits 6 and 7 with ones stored at the time you transition the setup bit C673 or C677 then Slave 3 will be rejoined but Slaves 6 and 7 will be removed If you don t want any slaves removed when you rejoin one or more slaves then make sure that all 0 s are written to the primary pointer address Example of Here s an example of rejoining Slaves 1 and 3 to a Slice I O configuration where Rejoining a Slave Slaves 1 3 and 5 were previously removed This means the bit pattern would be hex 20 because Bit 5 would still be a 1 and all the other bits would be 0 s E LD Hex 20 is the equivalent of the binary value 00 K2 when Slaves 1 and 3 are rejoined but Slave 5 D 0 remains removed eo OUT The value is stored in V7663 We know this V7663 from looking at the table on Page 4 8 C1 PD
26. and the CPU operate asynchronously from one another it is possible that the remote I O points may not be updated on every CPU scan Therefore if you have I O points that must be updated on every scan you should place them in the local and or expansion base In some applications it may helpful to understand the amount of time required to update the Slice I O points Depending on the number of I O points used in your Slice configuration and the baud rate you have selected for communication your update time requirements will vary This Appendix will show you how to estimate the total delay time for your system NOTE In most situations this delay will be so small that either it makes no difference to the particular application or the mechanical speeds of the field devices are slower than the delay itself If you have an application that requires a thorough understanding of the time delay you can use the following information in order to calculate the delay e Baud Rate this is the communication baud rate that you selected with the dipswitch settings on the slice master and slice slaves CPU Scan Time this is the total CPU scan time The easiest way is to use AUX53 from a DL405 Handheld Programmer or use the Diagnostics option under the PLC menu in our DirectSOFT Programming Software You can also use the DL405 User Manual to calculate the scan time but this is often very time consuming If you use the User Manual you will have
27. baud rate You have your choice of 19 2 38 4 153 6 and 614 4 Kb s All Slaves and the Master must be set to the same baud rate Let s now take a closer look at the Master module and the Slaves Slice Master Features D4 SM Slice Master PWR Turns ON at power up LINK Turns ON when there is a communications error DIP Switch Sets the communication baud rate On Back Run Relay Internal relay that is closed as long as there is a communications link present SLICE VO MASTER RUN Turns ON when the module is operating correctly DIAG Turns ON when there is a hardware failure I O Turns ON when the communications link is set up wrong or the rotary switch address is wrong or a slave unit controlled by the D4 SM causes an error T Terminating resistor terminal that should be jumpered with terminal 1 at the master and final slave base units Provides a connection to the internal termination resistor 1 1st wire of twisted pair 2 2nd wire of twisted pair 3 Shield of twisted pair G Ground connection Specifications Number of Masters per CPU 2 max for DL430 or DL440 Maximum No Slaves Supported 15 per master total 30 per 2 master system Number of Remote I O Points per CPU 512 Module Type Intelligent Installation Requirements Any slot CPU base only Intern
28. masters and which slaves you will be using you are now ready to do the installation and wiring Chapter 3 will cover this in detail Then later in Chapter 4 you will learn how to write the setup logic to actually tell the CPU how to assign these addressing choices Installation amp Wiring In This Chapter Introduction Step 1 Set the Baud Rate with the Rear DIP Switches Step 2 Install the Master s Step 3 Mount the Slave Units Step 4 Set the Slave Address with the Front Rotary Switch Step 5 Connect the Communications Cable Step 6 Connect the Field Wiring Optional Features ore Installation and Wiring Introduction 6 Steps NOTE It is advised that you read the previous chapter on Designing the Slice 1 0 System before you install your Slice master and slave units The decision making process explained in that chapter will help you understand how you should set the rotary switches and dip switches on the units It will also help you with writing your ladder logic in the next chapter There are six steps to install master module and slave units 1 Choose the baud rate by setting the dip switch on the rear of the master module and slave units 2 Disconnect the power and insert the master module s into the CPU base 3 Mount each of the slave units in their remote areas Set the address for each slave by using the rotary switch on the front of each slave unit 5
29. not want to disrupt anything else during the removal This is when you need the slave removal feature What is It The slave removal feature allows you to remove a slave on the fly and even add it back to the system later This can be triggered specifically in your program or it can occur upon detection of an error in the system When slave removal is accomplished the outputs for that slave go to zero 0 and the inputs are no longer read by the CPU Types of Slave You have a choice between two types of slave removal Removal Manual Slave Removal At any point in your program you can tell the CPU to ignore the I O points of a particular slave There does not have to be an error to trigger this feature Automatic Slave Removal This mode is triggered only by the occurrence of a Slice I O error for the slave unit designated Don t confuse the use of the words automatic and manual here with our earlier reference for addressing modes The terms here refer only to slave removal For example you can manually remove a slave from a system that has been automatically addressed You can also automatically remove a slave from a system that has been manually addressed With the one exception covered in the bottom paragraph your addressing mode for your slave I O points has nothing to do with slave removal How Pointer The slave removal feature has primary pointer and secondary pointer setup Addresses are loca
30. of the binary value formed when the bits representing the slaves K2A are set to one OUT The value is stored in V7663 We know this Anytime you remove slaves from V7663 s a system that was configured from looking at the table on Page 4 8 manually you must write FFFF LD This number must be written to the proper to the secondary pointer ad KFFFF secondary pointer address for slave removal dress Make sure FFFF is not in OUT this address when removing 77411 Secondary pointer address for 1st Master slaves from a system configured with either automatic or discrete c1 dd i L_ PD A one shot turns ON a timer Note Use of the one shot ensures that the timer will not turn ON again unless XO transitions ON to OFF then ON again C1 c2 86 C2 TMR 10 Timer used to make sure that C673 is OFF for at least 500 msec K10 Setup Bit for vo K5 ist Master C673 VO is the current count of the timer When it is greater gt OUT an or equal to 500ms 5 1 10ths of a second it will turn ON C673 To 2 After 1 second 1000ms the timer TO times out RST This causes C2 to reset so the timer is OFF Using the the same master and slaves of our example let s take a look at how you would setup the automatic removal of a slave Notice three differences e You use SPO to setup the slave removal on the first scan The V memory is found on the right hand side of the table Page 4 8 e There is no setup bit Suc
31. stored in V7663 We know this V7663 from looking at the table on Page 4 8 C1 PD A one shot turns ON a timer Note Use of the one shot ensures that the timer will not turn ON again unless XO transitions ON e o OFF then ON again 1st Master C1 C2 SET Slave 1 02 TMR 10 Timer used to make sure that C673 is A OFF for at least 500 msec g Active Ki0 Setup Bit for 68 go vo K5 1st Master C673 VO is the current count of the timer When it is greater OUT han or equal to 500ms 5 1 10ths of a second it Slave 2 To o will turn ON C673 RST After 1 second 1000ms the timer TO times out Active This causes C2 to reset so the timer is OFF which turns C673 OFF pe 5 Be V7663 Status before the above is executed e BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 al Rejoined 0 0 0 0 0 0 0 10 0 0I1 0 1 0 0 0 lo __ Jo go Slave No 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Slave 4 5 wie i V7663 Status after the above is executed by transitioning C673 el ctive BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6 9 ora 0101010101010101010111010101010 Slave 5 Slave No 15 14 13 12 11 10 9 8 7 6 5 4 3 2 4 i Removed oC Jo a Note Zero s in any of the bit positions mean that you want a slave to remain active if it is active or you want the slave rejoined if inactive One s in any of the bit positions means that you want a slave to be removed if it is active or you want a slave to remain remov
32. the slot occupied by the master or Setup Pointer for masters as well as the type of removal being used Storing the Bit Pattern V memory for Manual Removal V memory for Automatic Removal Slot 0 V7660 V7670 1 V7661 V7671 2 V7662 V7672 3 V7663 V7673 4 V7664 V7674 5 V7665 V7675 6 V7666 V7676 7 V7667 V7677 Example If we are using Manual slave removal and the Master is in Slot 3 We would store the hex number representing the slave or slaves being removed in V7663 Step 4 Write the Slave Removal Setup Program Sample Ladder Logic for Manual Slave Removal Sample Ladder Logic for Automatic Slave Removal Writing the Setup Program The ladder logic is only slightly different for manual and automatic slave removal Anytime you are using manual slave removal the last few commands of the setup must transition either C673 or C677 OFF for at least 500ms and ON for at least 500ms C673 is used for the 1st Master and C677 is used for the 2nd Master In the example below we have used a one shot and a timer to make sure we hold the OFF and ON states for the proper amount of time We have decided to remove Slaves 1 3 and 5 for the 1st Master when an ON signal is received from X0 This example configuration by assumption had its I O points configured using manual addressing xo LD Hex 2A is the equivalent
33. to estimate this time because it is dependent on the main program length and number of I O points in the local and expansion bases as well Slice Master Scan this is the time required for the Slice Master to scan the individual Slave stations to update the status of the I O modules Use the formula and table shown on the following page Module ON to OFF OFF to ON Response Time this is the amount of time that the module requires to see a transition in status For example when a switch connected to an input module closes it can take a few milliseconds 1 12 typical before the module actually makes the transition from OFF to ON Check the detailed specifications in Chapter 1 for the Slice slave response times This basic information is also available in the specifications of the Sales Catalog Total Delay Time this is the total delay time that takes all of the above factors into consideration There are several formulas that can be used to calculate this delay time The pages that follow will show you those formulas Once you have selected the applicable formula you will use the information you have gathered for the above items to calculate the total system delay time Since each application is different we cannot possibly show all of the options for the CPU scan time or the possible module response delays You can easily find this information in other publications However the next few pages will show you how to ca
34. to freeze the current input status If the relay is set all the input points are cleared when an error occurs Beginning of Setup C672 C672 When used in your ladder logic this relay indicates that you are beginning your setup of the addressing for a Slice I O system If this relay is set to 1 the CPU knows to use manual or discrete addressing If it is reset to 0 the CPU knows to use automatic addressing Activate Removal or C673 C677 When transitioned from OFF to ON these relays will either remove or Rejoining of Slaves rejoin slaves depending on what is stored in the primary pointer address Communication Error C700 C720 Automatically set by the CPU when there has been a communication error Check the individual bits at V7700 to find out if the 1st Master or any of its slaves are responsible Check the bits at V7701 to find out if the 2nd Master or any of its slaves are responsible A 1 in bit 0 of either V memory location means the master has been setup wrong i e baud rate does not match its slaves A 1 in any of the other bits indicates that there is either no response from the corresponding slave or the slave has failed a data test Mapping O K C710 C730 Check the individual bits at V7702 to find out which slaves of the 1st Master have been mapped properly Check V7703 for the mapping of the 2nd Master s slaves If correct there is a 1 in each bit position where there is an active slave D D fa e
35. 0 V40023 517 516 515 514 513 512 511 510 507 506 505 504 503 502 501 500 V40024 537 536 535 534 533 532 531 530 527 526 525 524 523 522 521 520 V40025 557 556 555 554 553 552 551 550 547 546 545 544 543 542 541 540 V40026 577 576 575 574 573 572 571 570 567 566 565 564 563 562 561 560 V40027 617 616 615 614 613 612 611 610 607 606 605 604 603 602 601 600 V40030 637 636 635 634 633 632 631 630 627 626 625 624 623 622 621 620 V40031 657 656 655 654 653 652 651 650 647 646 645 644 643 642 641 640 V40032 677 76 675 674 673 672 671 670 667 666 665 664 663 662 661 660 V40033 717 716 715 714 713 712 711 710 707 706 705 704 703 702 701 700 V40034 737 736 735 734 733 732 731 730 727 727 742 724 723 722 721 720 V40035 757 756 755 754 753 752 751 750 747 746 745 744 743 742 741 740 V40036 777 776 775 774 773 772 771 770 767 766 765 764 763 762 761 760 V40037 Appendix C Determining I O Update Time Overview Calculating Input Signal Delay Time Calculating Output Signal Delay Time Calculating Total System Delay Time S Determining I O Update Time Overview Since the Slice Master
36. 0 V40500 037 036 035 034 033 032 031 030 027 026 025 024 023 022 021 020 V40501 057 056 055 054 053 052 051 050 047 046 045 044 043 042 041 040 V40502 077 076 075 074 073 072 071 070 067 066 065 064 063 062 061 060 V40503 117 116 115 114 113 112 111 110 107 106 105 104 103 102 101 100 V40504 137 136 135 134 133 132 131 130 127 126 125 124 123 122 121 120 V40505 157 156 155 154 153 152 151 150 147 146 145 144 143 142 141 140 V40506 177 176 175 174 173 172 171 170 167 166 165 164 163 162 161 160 V40507 217 216 215 214 213 212 211 210 207 206 205 204 203 202 201 200 V40510 237 236 235 234 233 232 231 230 227 226 225 224 223 222 221 220 V40511 257 256 255 254 253 252 251 250 247 246 245 244 243 242 241 240 V40512 277 276 275 274 273 272 271 270 267 266 265 264 263 262 261 260 V40513 317 316 315 314 313 312 311 310 307 306 305 304 303 302 301 300 V40514 337 336 335 334 333 332 331 330 327 326 325 324 323 322 321 320 V40515 357 356 355 354 353 352 351 350 347 346 345 344 343 342 341 340 V40516 377 376 375 374 373 372 371 370 367 366 36
37. 040002 W446 kp k32 W447 C674 e set xo 1200 0 3 1 our x5 7223 0 i aur x 3 A 5 ouT Qa 3 D The DirectSOFT window shown above depicts a program that has already been written Of course your programming window will be empty when you first open it The following pages will show you how to write each part of your Slice I O setup program 4 Writing the Setup Program 4 3 Writing Your Slice I O Setup Step 1 Is your setup logic going to be in the main program body or is it going to be ina Decide How You subroutine If you have a DL430 the decision is made for you The DL430 does not Are Going to support the subroutine instructions so you have to put the setup logic in the main Execute Your body of the program The DL440 on the other hand does support the subroutine Program instructions The reason for using subroutines is because the setup logic only needs to be executed once In the example below we have suggested the use of SP00 so that the subroutine is only executed during the first scan This means it will not impact the scan time on subsequent scans When you write your setup logic it will be sandwiched in between rungs that affect the status of certain internal relays that are assigned to Slice I O setup These relays designate the beginning and end of your setup commands Sample RLL Structure for Slice I O Setup See 1 DirectSOFT Display 1 Main program body go
38. 10 1 fT SET the beginning of setup 7 Remember You must LDA i 40409 is si 12 set Pos 4 of the DIP 040400 Internal Duller adaress 13 a H or X0 X17 This is switch to ON in order determined by looking 75 for discrete addressing at the table in i Appendix B Input Bit Start Address __x0 V Memory ndaress C to be available First Master OUT nput Starting Address Total Input Points Consumed is _ Input Points Used jn Slice Slave 1 Input V7404 Pointer for 1st Master Output Bit Start Address vo VMemory Address V_sosoo 16 Number of input points Total Output Points Consumed js Output Points Used_s K16 in BCD that are be Ing eontiguieds Slave 2 OUT Corresponding Slice Slave Worksheet Pointer mwr oureur V7405 Unit vodet dees gt Octal 40500 is the Name put Address No puts Output 00655 Ne Outputs i O40500 internal buffer oe unna e oera Slice Slave 1 output address for Y0 Y17 D a OUT Corresponding 4 V7406 Pointer 5 LD Number of points in E K16 BCD that are being i configured 9 OUT Corresponding a a iti ai Pointer T Note Additional z worksheet would be a First Master LDA internal buffet address T completed for 5 Slice Slave 2 Input 040413 for X240 X257 19 Slave 3 COUT ii i V7410 emory pointer Input Bit Start Address otn V Memory Address Cut o L Number of input points Total Input Points Consumed js Input Points Used 10 _ 5 te in BCD that are Output Bit Start Address vs
39. 1674 1673 1672 1671 1670 1667 1666 1665 1664 1663 1662 1661 1660 V40673 1717 1716 1715 1714 1713 1712 1711 1710 1707 1706 1705 1704 1703 1702 1701 1700 V40674 1737 1736 1735 1734 1733 1732 1731 1730 1727 1726 1725 1724 1723 1722 1721 1720 V40675 1757 1756 1755 1754 1753 1752 1751 1750 1747 1746 1745 1744 1743 1742 1741 1740 V40676 1777 1776 1775 1774 1773 1772 1771 1770 1767 1766 1765 1764 1763 1762 1761 1760 V40677 Address z D 3 Q lt D n N 8 ek Memory Tables Remote Input Output Global GX Addresses MSB LSB 17 16 15 14 13 12 11 10 7 6 5 4 3 2 1 0 peices 017 016 015 014 013 012 011 010 007 006 005 004 003 002 001 000 V40000 037 036 035 034 033 032 031 030 027 026 025 024 023 022 021 020 V40001 057 056 055 054 053 052 051 050 047 046 045 044 043 042 041 040 V40002 077 076 075 074 073 072 071 070 067 066 065 064 063 062 061 060 V40003 117 116 115 114 113 112 111 110 107 106 105 104 103 102 101 100 V40004 137 136 135 13
40. 4 133 132 131 130 127 126 125 124 123 122 121 120 V40005 157 156 155 154 153 152 151 150 147 146 145 144 143 142 141 140 V40006 177 176 175 174 173 172 171 170 167 166 165 164 163 162 161 160 V40007 217 216 215 214 213 212 211 210 207 206 205 204 203 202 201 200 V40010 237 236 235 234 233 232 231 230 227 226 225 224 223 222 221 220 V40011 257 256 255 254 253 252 251 250 247 246 245 244 243 242 241 240 V40012 277 276 275 274 273 272 271 270 267 266 265 264 263 262 261 260 V40013 317 316 315 314 313 312 311 310 307 306 305 304 303 302 301 300 V40014 337 336 335 334 333 332 331 330 327 326 325 324 323 322 321 320 V40015 357 356 355 354 353 352 351 350 347 346 345 344 343 342 341 340 V40016 377 376 375 374 373 372 371 370 367 366 365 364 363 362 361 360 V40017 417 416 415 414 413 412 411 410 407 406 405 404 403 402 401 400 V40020 437 436 435 434 433 432 431 430 427 426 425 424 423 422 421 420 V40021 457 456 455 454 453 452 451 450 447 446 445 444 443 442 441 440 V40022 477 476 475 474 473 472 471 470 467 466 465 464 463 462 461 46
41. 5 364 363 362 361 360 V40517 417 416 415 414 413 412 411 410 407 406 405 404 403 402 401 400 V40520 437 436 435 434 433 432 431 430 427 426 425 424 423 422 421 420 V40521 457 456 455 454 453 452 451 450 447 446 445 444 443 442 441 440 V40522 477 476 475 474 473 472 471 470 467 466 465 464 463 462 461 460 V40523 Address z D 3 Q lt D n N 8 ek Memory Tables Control Relay C Addresses MSB LSB 17 16 15 14 13 12 11 10 7 6 5 4 3 2 1 0 2 017 016 015 014 013 012 011 010 007 006 005 004 003 002 001 000 V40600 037 036 035 034 033 032 031 030 027 026 025 024 023 022 021 020 V40601 057 056 055 054 053 052 051 050 047 046 045 044 043 042 041 040 V40602 077 076 075 074 073 072 071 070 067 066 065 064 063 062 061 060 V40603 117 116 115 114 113 112 111 110 107 106 105 104 103 102 101 100 V40604 137 136 135 134 133 132 131 130 127 126 125 124 123 122 121 120 V40605 157 156 155 154 153 152 151 150 147 146 145 144 143 142 141 140 V40606 177 176 175 174 173
42. 6 205 204 203 202 201 200 V40410 N ek 237 236 235 234 233 232 231 230 227 226 225 224 223 222 221 220 V40411 257 256 255 254 253 252 251 250 247 246 245 244 243 242 241 240 V40412 277 276 275 274 273 272 271 270 267 266 265 264 263 262 261 260 V40413 317 316 315 314 313 312 311 310 307 306 305 304 303 302 301 300 V40414 337 336 335 334 333 332 331 330 327 326 325 324 323 322 321 320 V40415 357 356 355 354 353 352 351 350 347 346 345 344 343 342 341 340 V40416 377 376 375 374 373 372 371 370 367 366 365 364 363 362 361 360 V40417 417 416 415 414 413 412 411 410 407 406 405 404 403 402 401 400 V40420 437 436 435 434 433 432 431 430 427 426 425 424 423 422 421 420 V40421 457 456 455 454 453 452 451 450 447 446 445 444 443 442 441 440 V40422 477 476 475 474 473 472 471 470 467 466 465 464 463 462 461 460 V40423 Memory Tables Standard Output Y Addresses MSB LSB 17 16 15 14 13 12 11 10 7 6 5 4 3 2 1 0 017 016 015 014 013 012 011 010 007 006 005 004 003 002 001 00
43. 75 After power up anytime a remote 1 0 error sr occurs for the 2nd Master the input status will be frozen for the slave that has caused the error 4 Writing the Setup Program Bat C673 C677 C673 is assigned to the 1st Master and C677 to the 2nd These relays have to be Activate Removal transitioned from OFF to ON in order to activate a setup written for removal and or Rejoining of rejoining of slaves They must be OFF for at least 500ms and ON for at least 500ms Slaves in order for the transition to be effective In the example below we are rejoining Slave 3 but Slave 5 remains removed In this example we are showing the 1st Master in slot 3 and I O assignments had been made previously using manual addressing ladder logic not shown here Example The diagram below shows the xo j Hex 20 is the equivalent of the binary value status after program EXCCUNON a when Slave 3 is rejoined but Slave 5 remains Slot 0 1 2 3 4 5 removed OUT The value is
44. Connect the communication cabling 6 After making sure the power is turned off connect the field wiring The following pages will cover each of these steps in detail This is all that is required to connect the masters and slaves There are also optional features that you may want to use Master unit Run Relay circuit Slave unit communications port These topics are covered at the end of the chapter Installation and Wiring o 9 3 Step 1 Set the Baud Rate with the Rear DIP Switches There are DIP switches on the rear of both the master and slave units These switches must be set to the same baud rate You have four choices but whatever baud rate you select for the master you must also use for its slaves Use the table below for setting the switches Also if you chose discrete addressing when you designed your system make sure you check switch 4 on the master It must be turned on to enable discrete addressing J aia Note that in this example we have turned pos 1 to OFF and pos 2 to ON 3 is not used and should always be set to OFF This sets the baud rate to 153 6 kB Position 4 is OFF unless you plan to use discrete addressing or the slave removal feature explained later Master The settings of pos 1 and pos 2 of the slaves must match the ON OFF state of these same positions on the master module s DIP switch Otherwise they will be set at diffe
45. DL405 Slice I O Master amp Slave Manual Number D4 SLICE M WARNING Thank you for purchasing automation equipment from PLCDirect We want your new DirectLOGIC automation equipment to operate safely Anyone who installs or uses this equipment should read this publication and any other relevant publications before installing or operating the equipment To minimize the risk of potential safety problems you should follow all applicable local and national codes that regulate the installation and operation of your equipment These codes vary from area to area and usually change with time Itis your responsibility to determine which codes should be followed and to verify that the equipment installation and operation is in compliance with the latest revision of these codes At a minimum you should follow all applicable sections of the National Fire Code National Electrical Code and the codes of the National Electrical Manufacturer s Association NEMA There may be local regulatory or government offices that can also help determine which codes and standards are necessary for safe installation and operation Equipment damage or serious injury to personnel can result from the failure to follow all applicable codes and standards We do not guarantee the products described in this publication are suitable for your particular application nor do we assume any responsibility for your product design installation or operation If you have
46. Slaves are linked together in a daisy chain fashion and are connected to the Master with a twisted pair cable Each slave must be powered externally by 24 VDC If you plan to connect a handheld programmer or some other operater interface requiring power from the RS232 port on the front of the unit then you will have to make sure your power supply has the proper current rating Slaves require 60mA max at 24 VDC without a handheld programmer but require 250mA max with a handheld programmer At time of publication Slice Slaves are available as follows D4 SS 88 8 inputs 8 outputs D4 SS 106 10 inputs 6 outputs D4 SS 16N 16 inputs D4 SS 16T 16 outputs Number of Masters Inasimple application you may want to use only one master in your CPU base and and Slaves then attach from 1 to 15 Slice I O units However in addition to this basic Allowed configuration more than one master can be placed in the CPU base You may usea maximum of two masters per CPU base The actual number of Slice I O units that can be connected depends on the addressing mode selected The various modes are discussed in more detail later e Automatic Addressing 12 slaves In a system with two master
47. V Memery Address V_ssts being configured lt b OUT Total Output Points Consumed is Output Points Used s 00 V7411 Memory pointer First Master nternal buffer address Slice Slave 2 output OkY240 Y257 Table of Reserved Memory for Discrete Addressin p First Master Module Second Master Module Input Numberof Output Number of Input Number of Output Number of Address Input Pts Address Output Pts Address Input Pts Address Output Pts Additional Slaves V7405 V7406 V7407 V7444 V7445 V7446 V7447 Continue from Here aS pee 740 V7411 V7412 V7413 V7450 V7451 V7452 V7453 8000 3 V7414 V7415 V7416 V7417 V7454 V7455 V7456 V7457 C670 SET 4 V7420 V7421 V7422 V7423 V7460 V7461 V7462 V7463 End setup for 1st Master If this were the setup for the 2nd 5 V7424 V7425 V7426 V7427 V7464 V7465 V7466 V7467 master you would use C674 to end your setup 6 V7430 V7431 V7432 V7433 7470 V7471 V7472 V7473 7 RT Return to program V7434 V7435 V7436 V7437 V7474 V7475 V7476 V7477 4 Writing the Setup Program 4 7 Slave Removal Why Would You There are certain types of applications where you might want slave stations to be Use Slave temporarily logged out Or there may be some point in the process where you want Removal to permanently remove one or more slaves You may also want a slave to be disconnected when there is any sort of communications error Of course you do
48. al I O NOTE There is a limit to how many slaves you can use with a master that has been configured automatically You can only attach a maximum of 12 slaves to a master that has been configured automatically Additionally if you use a second master only one of the masters can be addressed automatically e Manual With this mode you must select data types You have your choice of using X Y C or GX data types These data types will be explained in more detail a little later Manual addressing can be used with one or two masters Manual addressing allows a maximum of 15 slaves per master Unlike automatic addressing you choose the starting addresses for the manual mode There are tables in Appendix B to help you do this Everything is assigned in blocks of 16 bits so you can t just use 8 consecutive bits for your Slice I O assignment and assign the other 8 bits for local I O You are committed to 32 points for each slave 16 inputs 16 outputs Discrete This is very similar to manual addressing with two exceptions 1 You are not committed to 16 inputs and 16 outputs in some cases For example if you discretely addressed a D4 SS 106 slave the 32 point comsumption rule says that even you will consume 16 input points and 16 output points even though you are only actually using 10 inputs and 6 outputs But take another example where you are discretely addressing either the D4 SS 16N or the D4 SS 16T Each of these would only con
49. al Power Consumption 300 mA maximum Digital I O Consumed None Run Output Relay Rating 250 VAC at 1A 30 VDC at 1A Communication Baud Rates 19 2 38 4 153 6 614 4 kB Switch Selectable Communication Method Asynchronous half duplex Communication Cabling RS 485 twisted pair Belden 9271 or equivalent Maximum Transmission Distance 1000 ft approx 300 meters Operating Temperature 32 to 140 F 0 to 60 C Storage Temperature 4 to 158 F 20 to 70 C Relative Humidity 5 to 95 non condensing Environmental air No corrosive gases permitted Vibration MIL STD 810C 514 2 Shock MIL STD 810C 516 2 Noise Immunity NEMA ICS3 304 1500 V 1 minute e Slice Slave Features D4 SS xx The following Slice slave units are available e D4 SS 88 8 12 24VDC Inputs 8 5 24VDC Outputs e D4 SS 106 10 12 24VDC Inputs 6 5 24VDC Outputs e D4 SS 16T 16 5 24VDC Outputs e D4 SS 16N 16 12 24VDC Inputs Input LED s These correspond to the Output LED s These correspond to the numeral indicated plus the starting base numeral indicated plus the starting base address i e X200 1 X200 2 etc address i e Y200 1 Y200 2 etc DIP Switch Used to set the 8 12 24VDC IN 6 5 24VDC OUT PWR RUN DIAG LINK INPUT OUTPUT VO STARTING F 10 3 D4 SS 9e
50. al example program is 20 ms Use DirectSOFT or AUX53 to find the time for your program We are also assuming a baud rate of153 6 kB between the Slice Master and the Slice Slaves 70701 mg 70048 mg c rol D A D 3 D
51. any questions concerning the installation or operation of this equipment or if you need additional information please call us at 1 800 633 0405 This publication is based on information that was available at the time it was printed At PLCDirect we constantly strive to improve our products and services so we reserve the right to make changes to the products and or publications at any time without notice and without any obligation This publication may also discuss features that may not be available in certain revisions of the product Trademarks This publication may contain references to products produced and or offered by other companies The product and company names may be trademarked and are the sole property of their respective owners PLCDirect disclaims any proprietary interest in the marks and names of others Stage is a trademark of Koyo Electronics Industries Co LTD Texas Instruments is a registered trademark of Texas Instruments Inc TL TIWAY Series 305 Series 405 11305 and 11405 are trademarks of Texas Instruments Inc Siemens and SIMATIC are registered trademarks of Siemens AG GE is a registered trademark of General Electric Corporation Series One is a registered trademark of GE Fanuc Automation North America Inc MODBUS is a registered trademark of Gould Inc IBM is a registered trademark of International Business Machines MS DOS and Microsoft are registered trademarks of Microsoft Corporation Windows is a trademar
52. ave unit is 202mm in width 45mm in height and 70mm in depth The slave units have flanges located on each side for using mounting screws to attach them to a wall or mounting plate These mounting holes are located 192 mm apart from center to center The mounting screws do not come with the slave units Remember that the slave units cannot be located more than 1000 feet from the local base t 202mm J a 192mm gt t 45mm 8mm Tomm N gt N Re 4 5 mm dia N N Installation and Wiring 9 3 Step 4 Set the Slave Address with the Front Rotary Switch The Slice slave units have two small rotary switches on the front of their enclosure One switch iS marked X1 and the other X10 Dont confuse these with the conventional data type labeling these do not refer to inputs X1 and X10 Instead these set the unit address in decimal for each slave X1 is the one s position and X10 is the tens position For example 13 is set by turning the X10 switch to 1 and the X1 switch to 3 10 3 13 Since each Slice channel operates independently of the other you start the unit addressing for the 1st Master s slaves at 01 and you start the unit addressing for the 2nd Master s slaves also at 01 Unit Address X10 X1 1st Slice Remote 69 gt 1607 a O A NOAN PIRRE 8
53. bly be the only type of addressing you may ever need Using two masters however produces some additional requirements Automatic addressing can be used with either the 1st Master or the 2nd Master but it can only be used with one of them in any given system With automatic addressing you do not have to assign the individual slave I O addresses with your setup ladder logic because the CPU automatically assigns the data types X and Y and the respective addresses You do however have to make sure that the C672 is set to zero 0 and that either C670 or C674 are set to one 1 If you are using automatic addressing with the 1st Master then C670 must be set If you are using automatic addressing with the 2nd Master then C674 must be set Switch 4 must be ON in order to use Auto Addressing Automatic Addressing Setup for 1st Master SP00 6672 RST Beginning of setup 1 1 C670 Automatic addressing for 1st Master SET The use of automatic addressing for the 2nd Master is essentially the same except that you SET C674 instead of C670 Automatic Addressing Setup for 2nd Master 8000 ere RST Beginning of setup C674 SET Automatic addressing for 2nd Master When the CPU detects one of the above setups in your ladder logic it will assign slave inputs starting at X200 and slave outputs starting at Y200 It will consume 16 points for the inputs and 16 points for the outputs of each slave regardless
54. data as shown here Also if you examine this setup program you ll notice that the V40xxx addresses have been properly designated as shown in Appendix B The table at the bottom of the page is used for finding the CPU s V74xx pointer addresses 5000 1 615 Go to Slice I O subroutine Main Program Body END Slice I O Subroutine L k SBR K1 i 3 ae Note Write as subroutine only if using D4 440 CPU For D4 430 this must be in main program 5000 C672 ell CPU that this is Master Module No 4 Slave No _1 3 Slave 2 Inputs GX00 GX17 Outputs GX60 GX77 name 1 SET the beginning of setup Slice Slave Worksheet LDA Octal 40000 is the Uni ES he ee oe e 040000 beginning internal buffer Addresd Name fagur naars Output Address address for GX0 GX47 This is determined by looking at the table in Appendix B D4 SS 106 16 only 10 used Gx60 D4 SS 106 GX20 Maoniy 10 used GX100 First Master OUT V7404 nput Starting Address Pointer for 1st Master Slice Slave Inputs LD Number of input points K48 in BCD that are E being configured Slave 3 Inputs GX20 GX37 Outputs GX100 Y117 el ala EE 44 L sl TS EE 1 OUT Corresponding Pointer HIM ELL Heh LAT First Master Slic
55. e Slave oujputs LDA 040003 Oetal 40003 is the begisging internal buffer address for GX60 GX120 16 only 6 used 16 only 6 used 16 only 6 used A D 2 fa Q D 3 IN i Input Bit Start Address Gx00 Total Input Points Consumed 48 _ V Memory Address Input Points Used so LD Number of point Note Master module can be placed into any available slot You could also use a 2nd Master Separate worksheets should be filled out for each Master used nputs GX40 GX57 Outputs GX120 GX137 K48 in BCD that are Output Bit Start Address GX60 V Memory Address V40003 being configured Total Output Points Consumed 48 Output Points Used 18 OUT Corresponding V7407 Pointer C670 End setup for 1st Master If this were the SET setup for the 2nd master you would use C674 to end your setup RT Return to program k Table of Reserved Memory for Manual Addressing First Master Module Second Master Module Input Number f Output Number of Input Number of Output Number of Address Input Pj Address Output Pts Address Input Pts Address Output Pts D V7406 V7407 V7444 V7445 V7446 V7447 69 Writing the Setup Program Discrete The example shown below takes the same system shown on the previous page and uses Addressing discret
56. e ability to add Slice slave units or temporarily take a unit off line without disrupting the operation of the remaining system Compared to standard remote I O systems e g D4 RM and D4 RS combinations the Slice I O system is more economical and can support more slaves per channel It cannot however have as much distance between the master and slaves as the conventional remote I O system The furthest distance from the master that a slave can be located for the Slice system is 1000 feet For the conventional remote system the furthest distance that a slave can be located from its master is 3300 feet You must examine the needs of your application to determine which type of remote I O system is best for you How Does the DL405 Support Slice 1 0 With the DL405 system up to 512 remote I O points can be supported by the DL440 CPU or the DL430 CPU The Slice Master is placed in the CPU base The Master D4 SM controls up to 15 Slice Slaves D4 SS 88 D4 SS 16T D4 SS 16N and D4 SS 106 Slice Master The D4 SM can link up to 15 Slice slaves using discrete addressing per master module It is mounted in the CPU base Up to 2 masters can be used Note There are three different addressing modes available for assigning I O points to the system The number of slaves that can be used will vary depending on the method used This is discussed in detail later Slice Slave The
57. e addressing Notice that it uses an expanded reserved memory table for the CPU pointers and notice that each slave is setup individually Also the starting addresses can be out of sequence In the example we have used X0 X17and YO Y17 as the starting addresses for Slave 1 V40400 V40500 and X240 X257 and Y240 Y257 as the starting addresses for Slave 2 V40413 V40513 We have not shown Slave 3 but it could use any unused addresses from the X Y C or GX tables as well as be out of sequence With this method Its best to use separate worksheets for each slave You may have up to 7 slaves per master when using discrete addressing SP00 K1 ers Go to Slice I O subroutine Slave 1 1 Master Module No 1 Slave No 1 Slice Slave Worksheet H INPUT OUTPUT Main Program Body ee eee END 1 pessos gt o 16 only 10 we vo 16 oniy 6 used ON a SBR K1 Slice I O Subroutine Note Write as subroutine only if using D4 440 CPU 5 6 For D4 430 this must be in main program 6 wo S SP00 C672 _ ra ie ell CPU that this is 3 ji j
58. e choices System e Two channels to wire two different areas of some machine e Channel 1 uses 28 inputs and 20 outputs spread over three slave units e Channel 2 uses 24 inputs and 24 outputs spread over three slave units 1st Master CH 1 CH 2 2nd Master Slaves belonging to 2nd Master D4 SS 88 Slave 1 8 in 8 out belonging to 1st Master REI D4 SS 88 8 in 8 out l Slave 1 jo CSJ el _ D4 SS 88 D4 SS 106 l Slave 2 8 in 8 out 10 in 6 out Slave 2 ore D4 SS 1 06 D4 SS 88 10 in 6 out _ Slave 3 Tea 8 in 8 out J e C o Designing the Slice I O System a Choose the Addressing Mode Once you have determined the number of I O points masters and slave units required for your application you have to choose the addressing mode This allows you to assign the I O points that will be used by each slave unit You may recall that Chapter 1 provided a detailed description of the different modes The following table provides a quick overview of each choice Addressing Ease of Slave Number Special I O Point Assignments Number of Points Consumed Availability Mode Programming Limitations Easiest 12 per ma
59. e the following loads 250VAC 1 0A e 30VDC 1 0A Q Internal relay RUN OUTPUT RUN COMMON ap D 6262 If the RUN relay in the master goes OFF then the RUN relay in all of the slaves will turn off also If you choose to wire an input say X10 from the Run Output it is very easy to include a rung of logic to sound an alarm or to stop a process when a communication problem occurs X10 Y23 our Alarm Output Installation and Wiring vats Using the Each Slave unit has a 15 pin D shell 6 f SN ree SLICE 10 ms Slave Unit communications port This port is the Bere aii Communications same as the top port on the DL405 CPUs Port You can program or monitor the CPU through this port with DirectSOFT or the handheld programmer You can also connect the DV 1000 Operator Interface i to this port Note if you re using the Oo 0000000 handheld programmer or the DV 1000 OO00000 remember to add the power requirement 15 9 for the device when you select your 24VDC power supply Pin numbers only 15 pin Female You can order the necessary cables with Sow for illustration Bae p the following part numbers 8 Data Bits e D4 DSCBL DirectSOFT 1 Start Bit Programming cable for the DL405 Osa Parity e D4 HPCBL
60. eating sharp bends in the wires 10 Label all wires oa fF Power The master module is powered through the backplane of the local base The slaves Connections for however require an external 24VDC power supply The Slave units will not operate the Master and Its unless this supply is connected Slaves Note the earth ground terminal should not be used This helps improve noise immunity G 24 VDC Connect to these two screws NOTE If you are using 24VDC for your input and or output field devices it may be possible to use the above power supply for the field power as well If you use the same supply make sure you have calculated the maximum load required and that you size the power supply accordingly 3 10 Installation and Wiring D4 SS 88 I O Field Device Wiring Diagram Use the following wiring diagram to connect the field wiring to the I O terminal strip The I O point addresses have been labeled Xn and Yn to indicate the starting address The X and Y data types have only been used for illustration purposes Your exact starting addresses and data types depend on the addressing mode selected 8 12 24VDC IN 8 5 24VDC OUT PWR RUN DIAG LINK Fr IN O
61. ed if already removed D D fa e Q Q 3 oe Writing the Setup Program E 00 i dD yes Oo Q fod 020 C700 C720 Locate Communications Error These relays will be set when there is a communications error between the respective master and a slave or slaves assigned to the relay number C700 is for the 1st Master and C720 is for the 2nd Master In addition to these control relays there are also V memory locations that can be used to help pinpoint the error V7700 is assigned to the 1st Master and V7701 is assigned to the 2nd Master To specifically identify whether the problem is with the master or with one of its slaves you can have your logic check specific bits in the corresponding V memory One easy way to do this is to load the contents of the V memory location into the accumulator and then copy it to one of the V memory locations that is assigned to control relays that are available for general use Then you can use these individual control relays inside of your ladder logic program to help pinpoint the error In the following example we used the charts in Appendix B to determine the V memory address for CO C17 V40600 We loaded V7701 whichis the communication error location for the 2nd Master and then copied it to V40600 i Exam ple Y14 could be an output that i turns on an indicator light or an 20 yi4 alarm that indicates the 2nd our Master is not co
62. eee 1 7 Specifications e aatra EE tie ehh he Eke ever SE nebo Lee were eee be bey 1 7 Slice Slave Features D4 SS xxX LO 1 8 General Specifications 20856 as derrete EE Sei EEEE Lia PEE E eve wee bo ies os 1 8 Slice Slave Input Specifications ii 1 9 Slice Slave Output Specifications Li 1 9 Addressing Modes iseen ea ed vena waren wnare ODNaareADiae Shae 1 10 Whats Addressing esetre soa nee aiea eres One wane a relies eee tees 1 10 3 Modes of Addressing Available ii 1 10 Assigning the Remote Input and Output Addresses 1 11 Automatic Addressing for Local and Expansion PO 1 11 The Affect of Automatic Addressing on Slice I O 1 ee cece 1 11 Manual or Discrete Addressing for those Points Not Automatically Configured 1 11 How the CPU Updates Slice I O Points i 1 12 3 Steps for Setting Up Slice OL 1 13 Step Ones Design 416 System orreee recone e owas a Rha ia cone ta 1 13 Step Two Install the Components i 1 13 Step Three Write the Setup Program 1 13 La Table of Contents Chapter 2 Designing the Slice I O System Determine the System Layout LIL Determine I O Needed and How Many Masters amp Slaves Li An Example System 22244 sarees cea Res SEs tee ek ee SE coud eee ane See Choose the Addressing Mode 1 32 Point I O Consumption MBKRK KK 16 point Boundary Rule Li USN Example Syste
63. es here END SBR K1 Subroutine will go down here Start of Slice I O setup is indicated here by either SP00 C672 setting or resetting SET C672 i e SET manual or discrete RST automatic RLL for designating address pointers for mapping I O of 1st Master goes here uueJ5o d dnjes bo 6670 Setting this relay tells the sET CPU that your setup is complete for the 1st Master RLL for designating address pointers for mapping I O of 2nd Master goes here SP00 0674 Setting this relay tells the SET CPU that your setup is complete for the 2nd Master RT Return to the main program 62 Writing the Setup Program 00 i dD yes Oo Q fod 020 Step 2 Write the Setup Logic for Each Slice Master Automatic Addressing Whether you choose to write the Slice I O setup program as a subroutine or as a part of the main program the procedure is still the same If you are using automatic addressing the process is very simple NOTE You cannot use automatic addressing for both masters at the same time If you want to use automatic addressing you have to choose only one channel Also make sure that the X s and Y s that are automatically assigned to the slaves are not used by the other modules in the system Automatic addressing starts at X200 and Y200 If you are using only one master module then automatic addressing will proba
64. essing The your ladder logic a little easier You can have up to address assignments shown for the two masters per system If you use a second modules in the local base consume master you will have to fill out two of these sheets X0 X17 and YO Y27 Therefore we Even though we could have up to 30 slaves 15 are starting our manual addressing for per master with manual addressing we have only the slaves at X20 and Y40 We could used three in this simple example See note below not start at Y30 because the for other types of addressing and the respective addresses must start on a 16pt limitations on number of slaves supported boundary Master Module No Slice Slave Worksheet Main Base with Master are rare INPUT OUTPUT Address Name Master D4 SM Input Address No Inputs Output Address No Outputs Module Can go in any slo D4 SS 106 16 only 10 used yao 16 only 6 used CPU Br 1906 SPE EL D4 SS 106 16 only 10 used Yo 16 only 6 used and Input Output Input Output PS D4 SS 106 16 only 10 used Y100 16 only 6 used X00 X07 X10 X17 YO00 Y17 Y20 Y27 1st Slice Remote D4 SS 106 GL_ 9 ors X20 X37 consumed X20 X31 actually used Y40 Y57 consumed Y40 Y45 actually used Ley a Lew 11 and Slice Remote Ss errr E a a o EE X40 X57 consumed
65. g and updating takes place Notice that there are two independent scan cycles going on at the same time but asynchronously The CPU module is doing its scan which includes looking at the information that the master is writing to its internal buffers During every CPU scan the CPU examines the internal buffers of the Slice Master and updates input and output data from the Slice I O It is very possible for the CPU to be scanning faster than the Slice Master can do its scan It is largely dependent on the size of the application program the baud rate you have selected for the data transfer between the slaves and master as well as the number of I O points being monitored Sequence of Events Master s Memory Internal Buffers peration of Slave 1 lt Output Slave 1 i Input CPU s Memory 5 9 619 Read Inputs Inputs Operation of Slave N Output Slave N Scan 1 User Logic Execution Input Outputs Transfer of I O Update Outputs c i Information 6
66. h as C673 or C677 used SPO LD 1 K2A OUT V7673 LD The value FFFF is used only when removing KFFFF slaves from a system that was configured manually OUT 8 V7411 Secondary pointer address for 1st Master NOTE Remember when you determine the bit pattern value for automatic slave removal you have the option of merely setting Bit 0 This would indicate that you want any slave to drop out when it causes a communications error If you do this then you won t have to set each slave bit individually In the above example we only remove slaves 1 3 and 5 Therefore we decided not to use Bit 0 We instead set Bits 1 3 and 5 which resulted in the value HEX 2A O v fe Q o 3 ll Writing the Setup Program Rejoining Slaves What is It After removing a slave usually the application will call for the slave to be brought back on line with the system How is It Done In the case of automatic slave removal the rejoining of the slave or slaves is automatic That is as soon as the communications error is cleared the removed slave or slaves will be brought back on line You don t have to write any logic In contrast to this when slaves have been manually removed from the system you must write special ladder logic in order to bring them back on line There are two steps for doing this 1 Change the bit pattern in the primary pointer
67. igned to the 2nd Master If set these Mapping O K flags indicate that the I O points have been properly mapped If they are off then it indicates that a setup problem exists In addition to these control relays there are also V memory locations that can be used to help pinpoint the error V7702 is assigned to the 1st Master and V7703 is assigned to the 2nd Master To specifically identify the location of the setup error you can have your logic check specific bits in the corresponding V memory One easy way to do this is to load the contents of the V memory location into the accumulator and then copy it to one of the V memory locations that is assigned to control relays that are available for general use Then you can use these individual control relays inside of your ladder logic program to help pinpoint the error In the following example we used the charts in Appendix B to determine the V memory address for C20 C37 V40601 We loaded V7702 which is the communication error location for the 1st Master and then copied it to V40601 Y40 could be an output that turns on an indicator light or an Example oe Me alarm that indicates the 1st OUT Master is not communicating with one or more of the slaves LD V memory address where the V7702 status bits reside for the 1st Master OUT Copy the status of each bit in successive v40601 order starting with control relay C20 C710 C21 Y41
68. ing Points D4 SS 16N Inputs 12 24VDC 16 Common 12 24VDC i Common 424 TF ps To LED G TETO s Output i Sensor utpu Optical A KW Optical Current Sourcing inputs Input Isolator 10 20 30 40 50 50 68 86 104 122 Ambient Temperature C F 60 C 140 F D4 SS 16T I O Field Device Wiring Diagram Installation and Wiring 9 13 Use the following wiring diagram to connect the field wiring to the I O terminal strip The I O point addresses have been labeled Xn and Yn to indicate the starting address The X and Y data types have only been used for illustration purposes Your exact starting addresses and data types depend on the addressing mode selected D gt 16 5 24VDC OUTPUT 5 OUTPUT g 7 PWRRUN DIAG LINK DirectSLICEIO ERs Oae 4 7 rB GLASS 2 K 8 H 8 24VDC Koyo CA 4 5 6 7 4 5 6 7 2 6 2 6 0 25A L 101 ee 19108 1 101 111 E 3 3 7 8 7 ne UN POTTY tf I O SE
69. k of Microsoft Corporation OPTOMUX and PAMUX are trademarks of OPTO 22 Copyright 1997 PLCDirect Incorporated All Rights Reserved No part of this manual shall be copied reproduced or transmitted in any way without the prior written consent of PLCDirect Incorporated PLCDirect retains the exclusive rights to all information included in this document Manual Revisions If you contact us in reference to this manual be sure to include the revision number Title DL405 Slice Master Slice Slaves Manual Number D4 SLICE M Effective Effective Pages Description of Changes Original lssue Rev A 6 98 Entire Manual Downsize to spiral Manual Revisions Rev A Various pages Minor changes Table of Contents Chapter 1 Getting Started IntroduUcONn cscs snes enee wali RI asa aina ara sacar RR TR 1 2 The Purpose of this Manual LL 1 2 Contents OF the Manual ii 1 2 Supplemental Manuals i 1 2 Where to Begin UNSCRBIPS e a E Ce Re amg ee es Seed eas See REE Sees ene see 1 2 Technical Assistante aira pate EE ina soba dee SOSS ds eae Mia oe 1 2 How this Manual is Organized i 1 3 What is Slice 0 NKK 1 4 When Do You Need Slice O Ga GE SE a te gt 1 4 How Does Slice I O Compare to Standard Remote LL 1 4 How Does the DL405 Support Slice 1 0 1 1 5 Number of Masters and Slaves Allowed Li 1 6 Distance Between Slaves and Master Baud Rates 1 6 Slice Master Features D4 SM 2 20 cce cece eee eee
70. ksheet Master Module No Slave No Slice Slave Worksheet INPUT OUTPUT Input Address Output Address Input Bit Start Address V Memory Address V Total Input Points Consumed Input Points Used Output Bit Start Address V Memory Address V Total Output Points Consumed Output Points Used Appendix B Memory Tables Standard Input X Addresses Standard Output Y Addresses Control Relay C Addresses Remote Input Output Global GX Addresses Memory Tables Standard Input X Addresses MSB LSB 17 16 15 14 13 12 11 10 7 6 5 4 3 2 1 0 Address 017 016 015 014 013 012 011 010 007 006 005 004 003 002 001 000 V40400 037 036 035 034 033 032 031 030 027 026 025 024 023 022 021 020 V40401 057 056 055 054 053 052 051 050 047 046 045 044 043 042 041 040 V40402 077 076 075 074 073 072 071 070 067 066 065 064 063 062 061 060 V40403 117 116 115 114 113 112 111 110 107 106 105 104 103 102 101 100 V40404 137 136 135 134 133 132 131 130 127 126 125 124 123 122 121 120 V40405 157 156 155 154 153 152 151 150 147 146 145 144 143 142 141 140 V40406 177 176 175 174 173 172 171 170 167 166 165 164 163 162 161 160 V40407 217 216 215 214 213 212 211 210 207 20
71. lculate the delay time for the Slice Master Scan Also we show the total delay time for our example system that was used earlier in this manual Determining I O Update Time ons Calculating Input Signal Delay Time Input Delay Time The formulas shown below show you how much time is required for the CPU to Formulas detect an OFF to ON transition for an input switch at the slave station e Minimum Delay Imin F 910 S Maximum Delay Imax F 2B C F Time delay for input filter s ON to OFF 12 ms maximum OFF to ON 7 ms maximum B Bus scan time See table below C CPU scan time With DirectSOFT click on PLC Diagnostics Scan Time As an alternative use AUX53 of the handheld programmer to find this out Slot Location of V memory Location where the bus scan time is calculated and the Master 1 on stored as a hexadecimal number of milliseconds V7710 V7711 V7712 V7713 V7714 V7715 V7716 C Q o gt 7 V7717 Example for In this example we are examining the OFF to ON transition for the input delay of a ComputingInput slave belonging to a master that is located in Slot 2 of the CPU base Delay Use the maximum delay formula Imax F 2B C Use 7ms maximum filter delay time Place the CPU in RUN mode Use the table above to find the memory location that contains the bus scan time For example let s say it is 12ms 5 Use DirectSOFT or AUX 53 from a handheld programmer to dete
72. m Addressing i Other Examples ieties reni e a RE T E ENE E EE ESE EEE Complete the Programming Worksheets LO Filling Out the Slice Slave Worksheet for the 1st Master Lie Filling Out the Slice Slave Worksheet for the 2nd Master Chapter 3 Installation amp Wiring Introductio mm Se anne Rear sie erin a coer Sore eaten cor Vane ai Reg Coser Gr A EETA rer eae Reet OA 6 StebS pues wis Sh beeen ee reeke ce EE EE EE Step 1 Set the Baud Rate with the Rear DIP Switches Step 2 Install the Master S 2 000 eee ee eee cece eee ee eee nena Step 3 Mount the Slave Units LL Step 4 Set the Slave Address with the Front Rotary Switch Example Showing Proper Setting of Switches in Step 5 Connect the Communications Cable LLL Cabling Between the Master and Slaves Termination Resistors ies cee ae E oh aa he ae ee ls Step 6 Connect the Field Wiring General Wiring Guidelines LL Power Connections for the Master and Its Slaves ie D4 SS 88 I O Field Device Wiring Diagram D4 SS 106 I O Field Device Wiring Diagram D4 SS 16N I O Field Device Wiring Diagram en D4 SS 16T I O Field Device Wiring Diagram Optional Features xo lacie fea eeu i alte Catia e
73. mmunicating with one or more of the slaves LD V memory address where the V7701 status bits reside forthe 2nd Master OUT Copy the status of each bit in successive order V40600 starting with control relay CO C720 00 Y15 our When Bit 1 is ON turn ON Y15 Problem with Master C720 6 Y16 our When Bit 2 is ON turn ON Y16 Problem with Slave 1 C720 C2 Y17 our When Bit 2 is ON turn ON Y17 Problem with Slave 2 Continue with as many rungs as you have slaves Bit 0 is used to indicate a problem with the master so the first control relay that contains slave information is C1 Also notice how the control relays do not match up with the slave number after bit 7 This is because the control relays are numbered in octal not decimal For example you ll notice that slave 9 is represented by C11 V7701 2nd master with communication errors at Slaves 11 and 9 Slave bit 15 14 13 2 11 10 9 8 7 6 5 4 3 2 1 0 01010 10111 01 1101010101010101010 Bit 0 is for the Master BIT 15 14 13 12 11 40 9 8 7 6 5 4 3 2 1 0 01010 10111 1011101010101010101010 C17 C16 C15 C14 C13 C12 0611 010 C7 C6 C5 C4 C3 C2 C1 CO V40600 Control Relays C0 C17 4 Writing the Setup Program Baa C710 and C730 C710 is assigned to the 1st Master C730 is ass
74. n ag Current Sourcing inputs P Isolator NPN Current Sinking Current Sourcing inputs Current Sinking Output Field Device Derating Chart for Derating Chart for Points D4 SS 88 Inputs Points D4 SS 88 Outputs 8 8 Output Current 7 0 35A point 6 6 00 Output Current 0 5A point 4 4 4 3A common 24 2 0 1 ale 8 1 1 1 0 10 20 30 40 50 60 0 10 20 30 40 50 60 32 50 68 86 104 122 140 F 32 50 68 86 104 122 140 F Ambient Temperature C F Ambient Temperature C F Installation and Wiring 3 1 D4 SS 106 I O Field Device Wiring Diagram Use the following wiring diagram to connect the field wiring to the I O terminal strip The I O point addresses have been labeled Xn and Yn to indicate the starting address The X and Y data types have only been used for illustration purposes Your exact starting addresses and data types depend on the addressing mode selected 10 12 24VDC IN 6 5 24VDC OUT NEUT OUTPUT yO STARTING f 5 PWR RUN DIAG LINK Direct SLICE 0 Daae anea RSL
75. n the master and its slaves is provided by twisted pair cable Up to 512 remote I O points can be supported by either the DL430 or DL440 CPU s with baud rates of 19 2K 38 4K 153 6K and 614 4K Example Slice I O with one master and three slaves en SM 15 Slice I O Slaves per Master l bo GIO mm 1000 ft DirectSOFT can be used to write 300m ladder logic using a Windows based 69 or Max environment E bors baw Terminal Strip A SS Personal Zs Built in communication port Computer supports DirectSOFT and the Handheld programmer Slice I O offers tremendous savings on wiring materials and labor costs for systems with field devices that are in clusters at various spread out locations With the CPU in a main control cabinet or some other central area only the Slice I O communications cable is brought back to the CPU base This avoids the use of a large number of individual field wires over greatly separated distances to all the various field devices By locating the Slice I O modules close to the field devices wiring costs are reduced significantly Each slave has a built in communications port which supports connection to a computer or handheld programmer This permits system programming from a remote location Another inherent advantage of Slice I O is th
76. n to the CPU s memory image area You will also be shown how to use certain internal relays to monitor communications status build error traps and perform other useful functions Appendices Additional examples and reference information are in the following three appendices A Writing the Setup Program includes a blank worksheet that can be copied and used for designing your system gt Memory Tables for Remote Shows the reserved memory locations for the transfer of Slice I O data It is B I O Addresses cross referenced by data type NE shows you how to calculate the amount of delay inherent with the transfer Determining I O Update of data back and forth between the master and its Slice slaves Provides Time tables for all four baud rates available based on number of I O points used 4 What is Slice I O When Do You Need Slice 1 0 How Does Slice I O Compare to Standard Remote A Slice I O system is simply another cost effective form of remote I O which allows you to locate I O modules at remote distances from the CPU base without using separate I O bases These remote units have no CPU of their own and are completely controlled by the CPU in the main base via a special module called a Slice Master Each Slice Slave consisting of an internal power supply and I O adapter circuitry exchanges data with the CPU in the main base via the master module The communications link betwee
77. ne ae Sree re bone etree at eee Connecting the Run Output Circuit Using the Slave Unit Communications Port 1 Chapter 4 Writing the Setup Program Choosing a Programming Device 1 1 Writing Your Slice I O Setup i Step 1 Decide How You Are Going to Execute Your Program Step 2 Write the Setup Logic for Each Slice Master Automatie AddresSSING viva i cncos uae ow RE EE dues Gaya tae Goede pew a How About the Other Types of Addressing Manual AGGEGSSING 22 pereen hire eet open a Sees EoS eae ae Discrete Addressing 2 02445 ieai e Pere haa kes Sis Pag ee eee Seb ees Res ee ede Bee es Table of Contents O Slave Removal se ese EO tee eee i A ee Sa ee eet wae 4 7 Why Would You Use Slave Removal LL 4 7 WAU IS UT set hk Daas B iiet AM creas Earl at clan See EA a nl at cea 4 7 Types OF Slave Removal nunana aaeeeo rennara Seeetyat tt 3 4 7 How Pointer Addresses are Used for Slave Removal 0c cece eee eee eee 4 7 Sample Logic for Writing to Secondary Pointer 4 7 4 Steps for Using Slave Removal LLL 4 8 Step 1 Setting the DIP Switch SRA See alls 4 8 Step 2 Determining the Bit Pattern for Slave Removal LL 4 8 Step 3 Determining the Setup Pointer for Storing the Bit Pattern 0 4 8 Step 4 Write the Slave Removal Setup Program 4 9 Sample Ladder Logic for Manual Slave Removal
78. next available input point for the Slice slave will be X40 in this example Remember the DL405 uses octal addressing for the I O points The setup routines described later actually help make sure this happens You may recall that the CPU requires you to load an address into the pointer locations that setup the Slice I O These V memory addresses automatically start on 16 point boundaries so you cannot actually start the numbering incorrectly This is just important when you re trying to determine your starting address 4 bn Designing the Slice I O System Example System Addressing Other Examples In our example system we have only used 3 slaves per master This is well within the limit for each addressing mode so we can choose from any of the options shown in the previous table However we decided to choose e Automatic addressing for Channel 1 1st Master e Manual addressing for Channel 2 2nd Master With these choices our addressing assignments would be as shown in this diagram 1st Master CH 1 CH 2 2nd Master Slaves belonging to 2nd Master Configured Manually GX0 GX17 GX60 GX77 inputs outputs SE al Slave 1 Configured Automatically Slaves belonging to 1
79. ng Total System Delay Time 1 C 5 Output Delay Time Formulas Li C 5 Table Showing Approximate Signal Delay Times i C 5 Getting Started In This Chapter Introduction Manual Layout What is Slice I O Slice Master D4 SM Features Slice Slave D4 SS xx Features Addressing Modes Assigning the Remote Input and Output Addresses How the CPU Updates Slice I O Points 3 Easy Steps for Setting Up Slice I O Introduction The Purpose of this Manual Contents of the Manual Supplemental Manuals Where to Begin Technical Assistance This manual shows you how to install program and maintain the DL405 Slice I O system It also helps you understand the system operation characteristics If you understand PLC systems this manuals will provide all the information you need to get and keep your Slice I O V system up and running We will use sse tme examples and explanations to clarify our D4 SLICE D4 SLICE meaning and perhaps help you brush up on specific features used in the DL405 system This manual is not intended to be a generic PLC training manual but rather _ a user reference manual for the DL405 Slice I O system Depending on the products you have purchased there may be other ma
80. nuals necessary for your application You will want to supplement this manual with any other manuals written for other products We suggest e D4 USER M the DL405 User Manual e DA DSOFT M the DirectSOFT User Manual which is included with the DirectSOFT Programming software If you are in a hurry and already understand the basics of remote I O systems you may only want to skim this chapter and move on to Chapter 2 Installation and Wiring Be sure to keep this manual handy for reference when you run into questions If you are a new DL405 customer we suggest you read this manual completely so you can fully understand the Slice modules configurations and procedures used We believe you will be pleasantly surprised with how much you can accomplish with PLCDirect products If you re really in a hurry check the diagram shown on Pages 1 14 and 1 15 It shows how the system design hardware settings programming and memory map tables are used to develop a working system After completely reading this manual if you are not successful with implementing the OP 1500 or OP 1510 you may call PLCDirect at 800 633 0405 Monday through Friday from 9 00 A M to 6 00 P M Eastern Standard Time Our technical support group will work with you in answering your application questions If you have a comment or question about our products services or manuals which we provide please fill out and return the suggestion
81. of which type of Slice slave you are using For example a D4 SS 106 will consume 16 input points and 16 output points even though the slave does not have that many I O points available You may have up to 12 slaves for the corresponding master when using automatic addressing How About the Other Types of Addressing Manual Addressing n Master Slave 1 4 Writing the Setup Program 4 9 With manual or discrete addressing you have some additional steps In these cases you have to write ladder logic that tells the CPU which addresses and data types you want to use The CPU has predefined memory locations called pointers V74xx that you can use to accomplish this task Simply use the tables in Appendix B to find the V memory location V40xxx that corresponds to the data type and address that you want to use as the starting address Then you can use the setup logic shown in the following examples to load these V memory addresses into the pointers that the CPU uses to determine the Slice I O point addresses By doing this your setup logic merely tells the CPU where to store the slave I O points in the CPU image register area With manual addressing you may use up to 15 slaves per channel The following example system only uses 3 slaves We have decided to use global GX data types in this example for our inputs and outputs If you completed worksheets for your system simply transfer the worksheet
82. r Slave 1 Slave 2 Slave 3 1 2 3 1 2 3 1 2 3 DP D 63 ap Ep ep 62 62 18 2 sa VA 7 Termination At each end of amaster slave system it is necessary to have a termination resistor Resistors to prevent signal reflections from interfering with the communications Although the modules have a 150 ohm resistor built in for this purpose there are three options to consider Use the internal resistor Use an external resistor Use an external resistor in series with the internal resistor The following diagrams show these options in more detail Option 1 Slave Unit Internal Wiring Use Internal Resistor Only Internal 4 i With this configuration you use the 150 ohm Nx internal resistor of the module to provide resistor all the terminating resistance necessary A jumper wire is placed between the terminating terminal and terminal 1 De B Jumper Wire 3 8 Installation and Wiring Option 2 Slave Unit Internal Wiring Use an External Resistor Internal 4 To better match the impedance of the 150 ohm a cabling you can elect not to use the resistor internal resistor and instead use an external resistor of your choice This is connected between terminals 1 and 2 T 1 2 3 You do not use the jumper wire in this a g 23 case VVV
83. rent baud rates and will not be able to communicate Table for setting DIP switch Baud Rate 19 2kB 38 4kB 153 6kB 614 4kB Master OFF ON OFF ON 2 OFF OFF ON ON Note Position 4 of the Master enables or disables the system s ability to make use of discrete 3 Not used should always be OFF addressing or the automatic slave removal feature 4 See See See See ON Features enabled Note Note Note Note OFF Features disabled OFF ON OFF ON Remote 2 OFF OFF ON ON 3 4 Installation and Wiring Step 2 Install the Master S You can install up to two masters in the CPU base These can go into any available slot in the base The master can go into any slot in the local base WARNING To minimize the risk of electrical shock personal injury or equipment damage always disconnect the system power before installing or removing any system component Notice the master module has plastic tabs at the bottom and a screw at the top With the module tilted slightly forward hook the plastic tab on the module into the notch on the base Next gently push the top of the module back toward the base until it is firmly seated into the base Now tighten the screw at the top of the module to secure the module to the base Step 3 Mount the Slave Units Each sl
84. rmine the CPU scan time For illustration lets say you discover it is 20 ms 6 Solve the equation from Step 1 Imax F 2B C Imax 7 2 12 20 Imax 51ms IN 4 4 Determining I O Update Time Calculating Output Signal Delay Time Output Delay Time Here we are measuring the amount of time it takes for the CPU to turn ON an output Formulas at the Slice Slave The formulas for computing this are as follows e OUTmin 1 12 ms od OUT max 0 5 ms 2B C OUT min Minimum output signal delay OUT max Maximum output signal delay 0 5 ms Output hardware response time B Bus scan time See Table Below C CPU scan time follow instructions on Page C 3 Slot Location of V memory Location where the bus scan time is calculated and the Master gt A stored as a hexadecimal number of milliseconds D 08 i V7715 V7716 V7717 Example for In this example we are examining the maximum time an output point is delayed Computing Output when transitioning from OFF to ON Here we are measuring an output point on a Delay slave belonging to a master located in Slot 4 1 Use the maximum delay formula OUT max 0 5ms 2B C 2 Place the CPU in the RUN mode 3 Use the table to find where to check in memory for the bus scan time For illustration let s say you discover it is 15 ms 4 Use DirectSOFT or AUX53 of the handheld programmer to determine the CPU scan time For illustration lets say you discover it is
85. rogrammer or our Windows based DirectSOFT programming software It is generally much easier to use the software to generate the necessary setup logic The examples that follow show the instructions in this format Connect your computer through the CPU and not through one of the slave units Until you have completed the installation and the setup logic you cannot communicate with the CPU via the slave unit communication ports To get started enter DirectSOFT and carry out the normal DirectSOFT setup procedures for communicating with your DL405 CPU If you do not know how to do this refer to your DirectSOFT Manual Chapter 11 of your DL405 User Manual also has avery good explanation of the basic DL405 instruction set and examples of how these instructions are used for writing general ladder logic In this chapter we will only show you those instructions that are used to set up your Slice I O system First open DirectSOFT and establish a communication link with your CPU Then enter the Edit Mode for programming You should now be looking at a screen similar to the one shown below DirectSOFT Programming slice02 File Edit Search View Tools PLC Debug Window Help Haj fe e RIE leis For Help press FI T 0002 003 003 C672 1 RST 0670 s SFO ba 2 040000 UT W444 kp K32 OUT W4d5 DA
86. s Example 2 You need 28 slaves in your system What mode should you choose Solution You will have to use two masters and have manual addressing for both of them It s the only way you can address more than 27 slaves Example 3 You want to add a Slice I O system that requires nothing but inputs at each slave station You decide to use the D4 SS 16N for each slave location You are going to need as many I O points as possible for all of your local I O Solution Use discrete addressing This allows you to only consume 16 points at each slave station instead of the usual 32 required for the other modes You can have up to 7 slave stations per master depending on needs and I O address availability Designing the Slice I O System 2 S Complete the Programming Worksheets Once youve determined the addressing mode and the address assignments it is helpful to complete a programming worksheet to simplify the creation of the RLL setup program In Appendix A of this manual you will find a blank Slice Slave Worksheet We suggest that you photocopy this sheet and use it to map out the details of your system Assuming this will be your procedure this chapter will walk you through the worksheet by using the previous example system You can use the details from these worksheets when you set the switches on your hardware and when you write any necessary setup logic Filling Out the The following Slice Slave worksheet has been filled in for the
87. s you can only have one master using automatic addressing The other master is subject to the following limits Manual Addressing 15 slaves per master Discrete Addressing 7 slaves per master Here is an example where we have placed two masters in the CPU base and then attached a total of six Slice I O units Two Masters in the Same Base 2 Channel CH 1 Slice Masters CH2 Masters can go in any slot Maximum of gt 2 per CPU base 1000ft 6 30000 Slice Slaves ed l ta Max Maximum of 15 slaves gl pC o0 l E E per channel a eCo Allowable distance is from furthest slave to the Slice master Distance Between Each slave belonging to the same master is hooked together in a daisy chain usinga Slaves and Master shielded twisted pair cable The last slave unit in the daisy chain cannot be further Baud Rates than 1000 feet from the CPU base Each has an address and should be numbered sequentially from 1 through 15 decimal You assign this address by setting rotary switches on the front of each slave unit There are additional switches on the back of each unit to set the communication
88. s card included with this manual Chapters The main contents of this manual are organized into the following four chapters contains basic information you need to know in order to get started It includes a brief description of a Slice I O system an explanation of who 1 Getting Started needs such a system and an overview of the basic system components and the steps necessary to develop a working system i shows the steps required to design your system It includes a tutorial on 2 Designing the Slice I O how to use worksheets to keep track of all the I O address assignments It System provides the framework for developing the necessary information you will need for programming and hardware setup shows you how to install the Slice Master and Slice Slave units This Installation and chapter includes wiring information shows you how to set the rotary dial 40 ig Brde g pore y Communication Wiring and dip switch on each module how to daisy chain the remote units how Guidelines to size and use termination resistors and how to connect the Run Output circuit shows you how to use DirectSOFT to write the Slice I O setup program 4 This chapter takes the information developed from your worksheets and helps you develop a working program This includes showing you how to Writing the Setup Program map certain addresses together in order for the I O status of each Slice I O unit to be read and writte
89. s per common D4 SS 16N N A no outputs available D4 SS 16T 2 8 points per common D4 SS 106 1 6 points per common Wire Gauge AWG22 AWG18 U Addressing Modes What is Addressing 3 Modes of Addressing Available In order for the CPU to recognize the I O points in a Slice I O system the I O must first be configured by writing setup information to special V memory locations This configuration process is called addressing The addressing process links also referred to as maps the I O data stored in the Slice master module with the memory of the PLC We ll show you more about this addressing process in a moment Later in this manual you will learn how to use any of three possible modes to assign slice I O addresses Automatic With this mode your CPU will automatically assign your Slice inputs and Slice outputs starting with X200 and Y200 respectively This means the X200 Y200 I O points cannot already be assigned to some other module otherwise there would be an address conflict This mode also consumes at least 16 input points and 16 output points per slave even if the slave does not have 16 points This means the addresses associated with the Slice I O inputs start at X200 and extend to at least X220 and for the outputs start at Y200 extending to at least 220 Even if you don t use all of these I O points they are consumed by the system and you cannot have unused I O assigned to loc
90. sheet has been filled in for the 2nd master of the example system Master Module No 2 Slice Slave Worksheet Input Bit Start Address __ GX0 V Memory Address V 40000 See Appendix B Total Input Points Consumed 48 Input Points Used 24 Output Bit Start Address _ Gx60 _V Memory Address V_ 40003 See Appendix B Total Output Points Consumed_ 48 Output Points Used 24 For the 2nd master we have decided to use manual addressing for its slaves This means you must use the tables in Appendix B of this manual to determine the master module s internal V memory locations for mapping against the corresponding CPU s V memory In Chapter 4 we will show you how to write the ladder logic to setup the mapping process Right now you need only look at the table to find the master module s V memory locations corresponding to points GX0 and GX60 the starting points for the inputs and outputs of our example We have used global data types here because of simplicity If we had manually used X s and Y s we would have had to be concerned with what X s and Y s were already being used by the modules in the local and or expansion bases With global assignments you do not need this information This is a particularly good characteristic when you think that the configuration of the other I O in the base may be changed in the future i e new modules added removed etc Now that the amount of I O has been decided upon and you have determined how many
91. st Master poe inputs X200 X217 outputs Y200 Y217 Slave 1 GX20 GX37 GX100 GX117 BL_ 9 inputs outputs AN 3 Slave 2 inputs X220 X237 Slave 2 eC 79 ors outputs Y220 Y237 Ez ba GX40 GX57 GX120 GX13 inputs outputs inputs X240 X257 outputs Y240 Y257 Saves Slave 3 e gt eC 79 Note From a point of consistency you might prefer to manually configure the Slice I O for both Masters This example is for illustration only N Remember automatic addressing can only be used with one of the two possible masters in the CPU base We could not for example have used automatic addressing in CH2 because we have already used itforCH1 You do not have to use automatic addressing at all if you prefer not to do so For example both of these channels could have been configured using manual addressing Here are a few more examples that may help you understand addressing choices Example 1 You need a system with 12 slaves and you plan to use only one master The rest of your system does not use any points assigned to either X200 or above or Y200 or above You are not cramped for I O points in your total system Solution Choose automatic mode It takes just a few lines of ladder logic and it allows up to 12 slaves per master Although it can only be used with one master you only have one master so it s not an issue You ll consume 32 points per slave but you have plenty of I O for your other need
92. st be in main program 3 Not used should be set to OFF 4 See See See See C672 Chapter 3 Chapter 3 Chapter 3 Chapter 3 j Tell CPU that this is 1 SET the beginning of setup LDA Octal 40401 is the 1 OFF ON OFF ON k 040401 internal butter 00 Remote address for X20 This is determined by looking at the table in 2 Appendix B OFF OFF ON ON First Master OUT Input Starting Address Slice Slave Inputs V7404 Pointer for 1st Master e o ILD Total number of input Settings for this Example 48 points BCD that are being configured Baud Rate for Link OUT Corresponding 7405 Pointer Master and Slave must match First Master Slice Slave Outputs LDA Octal 40502 is the 1 OFF O40502 internal buffer 2 ON Set to 153 6 kB address for Y40 3 OFF __ OUT Corresponding 4 0FF V7406_ Pointer LD Total number of output K48 points BCD that are SS Se SOR SS SS Sat RR SS es ee being configured Baud Rate for Link 1st Slice Remote OUT Corresponding ee 07407 Pointer ES 2 ON g Ce70 0 B94 bre SET Pno aetu for st Master Set to 153 6 kB 5 RT Returntomain On Front 2nd Slice Remote On Back R Set to 153 6 kB On Back 3rd Slice Remote a Set to 153 6 kB On Back 6 In Chapter 3 you will learn ho
93. ster Inputs start at X200 32 per slave Can be used Outputs start at Y200 16 Input amp 16 Output with 1 master only Easy 15 per master Any available addresses 32 per slave Can be used with both masters Less Easy 7 per master Any available addresses Only the inputs and outputs Can be used needed per slave as long as it is with both in blocks of 8 pts each masters 32 Point I O When you use either automatic or manual addressing notice that a total of 32 I O points Consumption Rule are consumed for each slave 16 inputs and 16 outputs regardless of how many I O points are actually present on the slave However with the discrete addressing mode the Slice slaves may not necessarily consume 32 I O points It depends on which Slice slave you re using For example with discrete addressing the D4 SS 16N would only use 16 inputs and the D4 SS 16T would only use 16 outputs 16 point With manual or discrete addressing you can specify the starting address and the Boundary Rule data type X Y C etc These addresses must be on a 16 point boundary For example let s say you have a system that has consumed local base input points up through X27 Now let s say you want your first Slice slave to be aD4 SS 16N and you want to continue to use the X input data type for these points You may think that your first address for this slave will be X30 which is the next input address following X27 However X30 does not start on a 16pt boundary The
94. storing the bit pattern from Step 3 4 Write the slave removal setup program Step 1 Slave removal is only possible when you have placed Position 4 of the master Setting the DIP module s DIP switch to ON eee DIP switch of Master Module Must be placed in the ON position Step 2 To remove a slave from the system you set the bits in a 16 bit block according to the Determining the Bit scheme shown below This pattern must be converted to hex for programming Panarn for slave How the Bits are Set to Designate Which Slaves to Remove Removal BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Slave No 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L_ Not used for manual removal Set this bit to 1 to automatically Example for removing Slaves 1 3 and 5 remove any slave that has a communication problem Slave bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Since the Bit number is the 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 same as the Slave number it is easy to know which bits to set 8 4 1 8 4 2 1 8 4 2 1 8 4 2 1 Once you set these bits you can convert the binary value to H hex Notice how bits 1 and 3 0 0 2 A result in 10 which is hex A Hexadecimal 2A Step 3 The table shown below gives the pointer address for setting up the slave removal Determining the Notice that the addresses vary according to
95. sume 16 points per slave This is discussed in more detail in Chapter 2 2 Discrete addressing allows a maximum of 7 slaves per master Discrete addressing like manual addressing requires that you choose data types among the X Y C and GX options Again this will be discussed in detail later Assigning the Remote Input and Output Addresses Automatic Addressing for Local and Expansion I O The Affect of Automatic Addressing on Slice I O Manual or Discrete Addressing for those Points Not Automatically Configured Slave CH 1 If you ve used a DL405 CPU and local or expansion I O before then you probably know that the CPU will automatically assign the input and output addresses for local or expansion I O That is input points are automatically assigned starting at XO and output points are automatically assigned starting at YO A Slice I O system uses the automatic addressing concept but it is not related to the automatic configuration that is done by the CPU for the local and expansion I O The local and expansion addressing will start at XO and YO for inputs and outputs The Slice I O automatic addressing starts at X200 and Y200 for input and output points There are three key things to remember with the Slice I O and automatic addressing e If your local and or expansion I O uses input and or output points above X200 or Y200 then you can t use automatic addressing for the Slice I O e You can onl
96. tions The primary pointer address is a V memory assignment that is dependent Used for Slave on which type of slave removal is being used manual or automatic and the location Removal of the master in the base which slot In a moment we will show you a table of addresses so that you can determine where the primary pointers are located The secondary pointer address is always V7411 for the 1st Master and V7451 for the 2nd Master If you are removing slaves from a configuration that was addressed using manual addressing the secondary pointer address must have hexadecimal FFFF written to it In all other cases these addresses can have any number written to them except FFFF Below is a sample segment of RLL that shows FFFF being written to the secondary pointer address of the 1st Master fora system that had its I O points addressed manually D D fa Q D 3 Sample Logic for SPO LD The value FFFF is used only when removing slaves from a system that was configured Writing to 1 KFFFF manually Secondary Pointer ie Secondary pointer address for 1st Master Writing the Setup Program rogram A 2 5 00 4 Steps for Using Use the following steps to make use of the slave removal function Slave Removal 1 Properly set the DIP switch on the rear of the master s 2 Determine the binary bit pattern for slave removal 3 Determine the setup pointer for
97. w the setting of the binary switch on the master module affects the system s ability to make use of discrete addressing and the system s slave removal process program Note V memory pointer for 1st Master inputs start at V7404 with number of points being transferred in V7405 The output pointer starts at V7406 with number of points being transferred in V7407 If you were to use two channels the second master pointers would be as follows V memory pointer for inputs would start at V7444 with number of points being transferred in V7445 Output pointer starts at V7446 with number of points being transferred in V7447 A table showing all of the pointers is included in Chapter 4 C670 ends the setup for 1st Master but C674 must end the setup for 2nd Master Designing the Slice I O System In This Chapter Determine the System Layout Choose the Addressing Mode Complete the Programming Worksheets ene Designing the Slice I O System Determine the System Layout Determine I O The first step in putting any system together is to at least establish a mental picture of Needed and How the system components You should determine the number of input and output Many Masters amp points needed which in turn will allow you to determine the number and types of Slaves slave units required You may even want to draw a diagram An Example We ll use the following example system to help you understand thes
98. y use automatic addressing for one master in a Slice I O system With two masters one must use discrete or manual addressing e The CPU will assign Xs starting at X200 and assign Y s starting at Y200 at the rate of 16 input and 16 output points per slave unit For manual or discrete addressing the DL405 CPUs have specific memory locations called pointers that tell the CPU how to assign the Slice I O addresses The starting address for the pointers of the 1st Slice Master starts with V7404 and the starting address for the pointers of the 2nd Slice Master is V7444 Your RLL must store addresses in these pointer locations to tell the CPU where the Slice I O will appear in the I O image area In the example below the CPU will automatically configure the I O of the 1st Slice Master and use global GX I O points to manually configure the 2nd Slice Master Don t worry about understanding everything shown below Chapter 4 will provide the missing details Example Slice I O Address Assignment Setting C672 tells the CPU that this is the beginning of the Slice I O configuration setup

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