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1. VEEK User Manual p Video amp Embedded Evaluatio www terasic com Copyright 2003 2011 Terasic Technologies Inc All Rights Reserved CONTENTS CHAPTER 1 INTRODUCTION OF THE VEEK ccccccccssesscccccccccusnscssecceeeceseausceeeeeeeessaaaseeeeeeeeseuaaasseeeeeess 1 NM ore cR AD T e 5 LAG I a T PRETIO E E E 6 CHAPTER 2 VEEK ARCHITECTURE mmm esa oma 7 Jah La DU DA MONT RTT Em 7 2 Block Dragt ol e VEEE OT na T m Tr 8 CHAPTER 3 USING IHE VEEK ea oat naa 9 Da Le Ono Urine the Cyclone IV E FPGA sasi 9 22 BUS SO ih Keji la o aes eee adu an AN PD E AP MI E UMEN TO 12 3 9 Using the 3 LCD Touch Screen Module sasare san tito b an Sete ada anaa nia irane nang Beng a aa nani aana amen Lemas 13 3 4 Using 5 Megapixel Digital Image Sensor Module Wanna 14 2 5 Usine the Digital Acceleromet a an na 15 CHAPTER 4 VEEK DEMONSTRATIONG 11 cccccccccssesccsccccccceeesacsececeeeeeaeaasseecceeesessaaaasseeeeeeesenaaaseeeeeess 16 LANI SO Regue MIC on an an S 16 AD Raees ata an aga a E Rm 16 TIN BIBI Suner Demon iiO a en at 17 VEEE PICE VIN ak EN ni KK NE A mlam E EN NR NE KANE NA E 21 Zo Video and Image PrTOCSSSIT Se nenen sen kaan ng aaa ana aaa ia aan an a Ba ia aa gin sean daa DEN 24 2 0 BER Aine PaO BIC AION soon em amanat sate 43 90 a ka ga BA aa NG E a PENA E aa naa gk 27 4 7 Video and Image Proc2. 18 Slide Switches 18 Red LEDs 4 Push bullons 8 Green LEDs Figure 2 2 VEEK PCB and component diagram bottom view 2 2 Block Diagram of the VEEK Figure 2 3 gives the block diagram of the VEEK board To provide maximum flexibility for the user all connections are made through the Cyclone IV E FPGA device Thus the user can configure the FPGA to implement any system design HSMC DE2 115 CMOS Sensor LCD Touch Panel Figure 2 3 Block Diagram of VEEK Terasic VEEK User Manual www terasic com www terasic com Chapter 3 Using the VEEK This section describes the detailed information of the components connectors and pin assignments of the VEEK 3 1 Configuring the Cyclone IV E FPGA The VEEK board contains a serial configuration device that stores configuration data for the Cyclone IV E FPGA This configuration data is automatically loaded from the configuration device into the FPGA every time while power is applied to the board Using the Quartus II software it is possible to reconfigure the FPGA at any time and it is also possible to change the non volatile data that is stored in the serial configuration device Both types of programming methods are described below 1 JTAG programming In this method of programming named after the IEEE standards Joint Test Action Group the configuration bit stream is downloaded directly into the Cyclone IV E FPGA The FPGA will retain this configuration as long as
3. Color filter array Shutter type Maximum data rate master clock Full resolution Frame rate VGA mode ADC resolution Responsivity Pixel dynamic range SNRMAX Power Supply Voltage To B Digital Accelerometer e Upto 13 bit resolution at 16g e SPI 3 and 4 wire digital interface e Flexible interrupts modes Value 2592Hx1944V 2 2umx2 2um RGB Bayer pattern Global reset release GRR 96Mp s at 96MHz Programmable up to 15 fps Programmable up to 70 fps 12 bit 1 4V lux sec 550nm 70 1dB 38 1dB 3 3V 1 7V 3 1V Q Note for more detailed information of the LCD touch panel and CMOS sensor module please refer to their datasheets respectively 1 1 About the Kit The kit contains all users needed to run the demonstrations and develop custom designs as shown in Figure 1 2 The system CD contains technical documents of the VEEK which includes component datasheets demonstrations schematic and user manual Terasic VEEK User Manual w teresic com www terasic com 1 2 Getting Help VEEK Type A B USB Cable Power Supply VEEK Quick Start Guide Altera Complete Design Suite DVD for Windows DE2 115 amp VEEK System CD Remote Controller Q 2GB SD Card Two Wire Strips black and red 9 USB to SD Card Adapter Two 1 pin Headers Figure 1 2 VEEK kit package contents Here is information of how to get help if you encounter any problem e Terasic Technologies 886 3
4. timer as a regular interrupter and periodically updates the pen state and sampled coordinates 21 TTlasiC Terasic VEEK User Manual www terasic com www teresic com 50MHz SD Card Socket Figure 4 7 Block diagram of the picture viewer demonstration B Demonstration Source Code e Project directory VEEK Picture Viewer e Bitstream used VEEK Picture Viewer sof e Nios II Workspace VEEK Picture ViewenSoftware B Demonstration Batch File Demo Batch File Folder VEEK Picture ViewerNdemo batch The demo batch file includes the following files e Batch File VEEK Picture Viewer bat VEEK Picture Viewer bashrc e FPGA Configure File VEEK Picture Viewer sof e Nios II Program VEEK Picture Viewer elf B Demonstration Setup e Format your SD Card into FAT16 format e Place the jpg image files to the jpg subdirectory of the SD Card For best display result the image should have a resolution of 800x600 or the multiple of that e Insert the SD Card to the SD Card slot on the VEEK e Load the bitstream into the FPGA on the VEEK board 22 Yadasic Terasic VEEK User Manual www terasic com ANU S AYAN Run the Nios II Software under the workspace VEEK_Picture_Viewer Software Note After loading the application you will see a slide show of pictures on the SD Card The next image will be displayed after the delay period You can control the slide show as follows Press Forward je to advance Reverse ts to go back to prev
5. 10 Pixel data bit 11 Snapshot strobe Line valid Frame valid Image sensor reset Serial clock Snapshot trigger Serial data External input clock 3 5 Using the Digital Accelerometer 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V 2 5V The VEEK is equipped with a digital accelerometer sensor module the ADXL345 is a small thin ultralow power assumption 3 axis accelerometer with high resolution measurement Digitalized output is formatted as 16 bit twos complement and could be accessed either using SPI interface or I2C interface This chip uses the 3 3 V CMOS signaling standard Main applications include medical instrumentation industrial instrumentation personal electronic aid and hard disk drive protection etc Some of the key features of this device are listed below For more detailed information of better using this chip please refer to its datasheet which is available on manufacturer s website or under the datasheet folder of the system CD Table 3 4 contains the pin names and descriptions of the G sensor module Signal Name GSENSOR_INT1 GSENSOR_INT2 GSENSOR CS n GSENSOR ALT ADDR GSENSOR SDA SDI SDIO PIN E28 GSENSOR SCL SCLK Terasic VEEK User Manual rasic com Table 3 4 Pin assignment of the Digital Accelerometer FPGA Pin No PIN AE26 PIN AE27 PIN D28 PIN E27 PIN F27 Description Interrupt 1 output Interrupt 2 output Chip Select I2C Address Select Serial Dat
6. Bit stream used VEEK G sensor sof e Nios II Workspace VEEK G sensor Software B Demonstration Batch File Demo Batch File Folder VEEK G sensordemo batch The demo batch file includes the following files e Batch File VEEK G sensor bat VEEK G sensor bashrc e FPGA Configure File VEEK G sensor sof e Nios II Program VEEK_G_sensor elf B Demonstration Setup e Load the bitstream into the FPGA on the VEEK board e Run the Nios II Software under the workspace VEEK_G_sensor Software Note e After Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal the message is its ADXL345 s ID e5 e Tilt the VEEK board to the all directions you will find that the degree will change in the LCD 34 www terasic com ANU S AYAN display Figure 4 17 shows the result for running the demonstration Figure 4 17 VEEK Digital Accelerometer demonstration Q Note Execute VEEK G sensor Memo batcM VEEK_G_sensor bat will download sof and elf files 35 TTlasiC Terasic VEEK User Manual www terasic com www terasic com Chapter 5 Application Selector The application selector utility is the default code that powers on the FPGA and offers a graphical interface on LCD allowing users to select and run different demonstrations resides on SD Card 5 1 Ready to Run SD Card Demos You can find several Ready to Run SD Card demos in your SD Card root directory as well as in
7. Devices o 128MB SDRAM o 2MB SRAM o 8MB Flash with 8 bit mode o 32Kbit EEPROM Switches and Indicators o 18 switches and 4 push buttons o 18 red and 9 green LEDs o Eight 7 segment displays Terasic VEEK User Manual www terasic com www terasic co m Audio o 24 bit encoder decoder CODEC o Line in line out and microphone in jacks Display o 16x2 LCD module On Board Clocking Circuitry o Three 50MHz oscillator clock inputs o SMA connectors external clock input output SD Card Socket o Provides SPI and 4 bit SD mode for SD Card access Two Gigabit Ethernet Ports o Integrated 10 100 1000 Gigabit Ethernet High Speed Mezzanine Card HSMC o Configurable I O standards voltage levels 3 3 2 5 1 8 1 5V USB Type A and B o Provide host and device controller compliant with USB 2 0 o Support data transfer at full speed and low speed o PC driver available 40 pin Expansion Port o Configurable I O standards voltage levels 3 3 2 5 1 8 1 5V VGA out Connector o VGA DAC high speed triple DACs DB9 Serial Connector o RS232 port with flow control PS 2 Connector o PS 2 connector for connecting a PS2 mouse or keyboard TV in Connector o TV decoder NTSC PAL SECAM Remote Control o Infrared receiver module Terasic VEEK User Manual www terasic com www terasic com e Power o Desktop DC input o Switching and step down regulators LM3150MH B LCD touch screen module e Equipped with an 8 inch Amorphous TFT LCD Thin Fi
8. demonstration the application selector copies the hardware image to EPCS device and software image to flash memory and reconfigures the FPGA with your selection For more comprehensive information of the application selector factory configuration please refer to chapter 5 Terasic VEEK User Manual www terasic com www teresic com Altera VEEK Application Selector VEEK_Pic A MEEK VIP VEEK Camera VEEK Starter Figure 4 1 Application selector interface Q Note Please insert the supplied SD Card from this demonstration 4 3 VEEK Starter Demonstration The VEEK starter demonstration takes user the initial experience of an embedded system integrating a LCD Touch Panel This demonstration consists of two sub item Touch and Color pattern generator The Touch segment draws a circle on where you touch the screen and updates its coordinates on the top left corner The pattern generator can be treated as an upgrade version of the LCD test program The software successively generates different color patterns after a fixed time delay Users could use it to quickly investigate any flaw of the LCD Figure 4 2 shows the hardware system block diagram of this demonstration The system is clocked by an external SOMHz Oscillator Through the internal PLL module the generated 100MHz clock is used for Nios II processor and other components and there also a 40MHz pixel clock for the video pipeline and 10MHz for low speed peripherals Th
9. functional keys of the digital camera Figure 4 13 gives a run time photograph of the demonstration Table 4 2 The functional keys of the digital camera demonstration Component Function Description KEY 0 Reset circuit KEY 1 Set the new exposure time use with SW 0 KEY 2 Trigger the Image Capture take a shot KEY 3 Switch to Free Run mode Off Extend the exposure time SW O On Shorten the exposure time HEX 7 0 Frame counter Display ONLY 29 TTlasiC Terasic VEEK User Manual www terasic com rasic com Figure 4 13 Screen shot of the VEEK camera demonstration 4 7 Video and Image Processing for Camera The Video and Image Processing VIP for Camera Example Design demonstrates dynamic scaling and clipping of a standard definition video stream in RGB format and picture in picture mixing with a background layer The video stream is output in high definition resolution 800x600 on the HSMC LTC daughter card part of the VEEK The example design demonstrates a framework for rapid development of video and image processing systems using the parameterizable MegaCore functions that are available in the Video and Image Processing Suite Available functions are listed in Table 4 2 This demonstration needs the Quartus II license file includes the VIP suite feature These functions allow you to fully integrate common video functions with video interfaces processors and external memory controllers The example design uses an Alte
10. name it what you would like the title of your application to be shown as in the application selector e Using an SD Card reader copy the directory onto an SD Card into a directory named Application Selector The directory structure on the SD Card should look like this Application Selectorv Name of Application elf names SW bin sof name HW bin e Place the SD Card in the VEEK board and switch on the power The Application Selector will start up and you will now see your application appear as one of the selections Q 1 You may not need a CFI Flash controller when your design does not contain a Nios II processor or you store your software code within the on chip memory and use the hex initialization file 2 If you would like to use other memories such as SRAM or SDRAM as the program memory you may need to perform two steps to convert your elf file into bin file to make the software properly run on VEEK The commands seem to look like this elf2flash basezflash base address end flash end address resetzflash base address Input lt your software name gt elf output lt your software name flash bootZ SOPC KIT NIOS2 components altera nios2 boot loader cfi srec nios2 elf objcopy I srec O binary your software name gt flash your software name SW bin 3 You may pad a compress option for saving binary image space because the Cyclone IV E series support the decompress feature while loading
11. power is applied to the board the configuration information will be lost when the power is turned off 2 AS programming In this method called Active Serial programming the configuration bit stream is downloaded into the Altera EPCS64 serial configuration device It provides non volatile storage of the bit stream so that the information is retained even when the power supply to the VEEK board is turned off When the board s power is turned on the configuration data in the EPCS64 device is automatically loaded into the Cyclone IV E FPGA B JTAG Chain on VEEK Board To use JTAG interface for configuring FPGA device the JTAG chain on the VEEK must form a close loop that allows Quartus II programmer to detect the FPGA device Figure 3 1 illustrates the JTAG chain on the VEEK board Shorting pin and pin2 on JP3 can disable the JTAG signals on the HSMC connector that will form a close JTAG loopback on DE2 115 See Figure 3 2 Thus only the on board FPGA device Cyclone IV E will be detected by Quartus II programmer By default a jumper is placed on pinl and pin2 of JP3 To prevent any changes to the bus controller Max II EPM240 described in later sections users should not adjust the jumper on JP3 Terasic VEEK User Manual www terasic com www terasic com ANU S RYAN USB Embedded Blaster Connector A L TDI Tem USB 9 TDO Figure 3 1 JTAG Chain JP3 Figure 3 2 The JTAG chain configuration header B Confi
12. well as a LCD multimedia color touch panel and a 5 Megapixel digital image sensor module The VEEK is preconfigured with an FPGA hardware reference design including several Ready to Run demonstration applications stored on the provided SD Card Software developers can use these reference designs as their platform to quickly architect develop and build complex embedded systems By simply scrolling through the demo of your choice on the LCD multimedia color touch panel you can evaluate numerous processor system designs The all in one embedded solution offered on the VEEK in combination of the LCD touch panel and digital image module provide embedded developers the ideal platform for multimedia applications with unparallel processing performance Developers can benefit from the use of FPGA based embedded processing system such as mitigate design risk and obsolescence design reuse reducing bill of material BOM costs by integrating powerful graphics engines within the FPGA and lower cost Figure 1 1 shows a photograph of the VEEK Terasic VEEK User Manual www terasic com www teresic com Figure 1 1 The VEEK overview The key features of the board are listed below DE2 115 Development Board Cyclone IV EP4CE115 FPGA o 114 480 LEs o 432 MOK memory blocks o 3 888 Kbits embedded memory o 4 PLLs Configuration o On board USB Blaster circuitry o JTAG and AS mode configuration supported o EPCS64 serial configuration device Memory
13. 550 8800 e Email support terasic com e Tel www terasic com Chapter 2 VEEK Architecture This chapter describes the architecture of the VEEK including block diagram and components 2 1 Layout and Components The picture of the VEEK is shown in Figure 2 1 and Figure 2 2 It depicts the layout of the board and indicates the locations of the connectors and key components 5 Megapixel Digital Camera 8 LCD Touch Panel Figure 2 1 VEEK PCB and component diagram top view Terasic VEEK User Manual www terasic com www terasic co m TV Decoder NTSC PAL A dl Ethemet CODEC 2BMHz Kadi 21 da USB Oscillator s USB Device Ethernet Blaster Fort USB Mic LineLine Video VGA 10 100 1000M RS 232 Host In In Out In Out Fonto Port Jw anm T TT de 12V DC Power Supply Connector ML 2 LCS Fe or pakra NGABA mg A AEn Triple 8 bit VGA DAC Power ON OFF Switch pele Pe OE RR Digital Accelerometer Altera USB Blaster Controller chipset sa La i aa NG Bare Lu mn Tw Gigabit Ethernet PHY a T pen ff amp Ta USB Host Slave Controller ri Expansion Header Altera EPCS64 Configuration Device ue LUI Tm pu s with Protection Diodes a JIIIILIIE HA aan you Tb ais ra m n POPES A a d Altera 60 nm Cyclone IV E FPGA with 115K LEs LCD 16x2 Module SOMHz Oscillator BIME SDRAM x2 2MB SRAM BMB FLASH SMA Ext Clock Out SMA Ext Clock In IR Receiver T segment Displays Programming Mode Switch
14. a I O Standard 2 5V 2 5V 2 5V 2 5V 2 5V Serial Communications Clock 2 5V 15 www terasic com Chapter 4 VEEK Demonstrations This chapter gives detailed description of the provided bundles of exclusive demonstrations implemented on VEEK These demonstrations are particularly designed or ported for VEEK with the goal of showing the potential capabilities of the kit and showcase the unique benefits of FPGA based SOPC systems such as reducing BOM costs by integrating powerful graphics and video processing circuits within the FPGA 4 1 System Requirements To run and recompile the demonstrations you should e Install Altera Quartus II 10 0 and NIOS II EDS 10 0 or later edition on the host computer e Install the USB Blaster driver software You can find instructions in the tutorial Getting Started with Altera s DE2 115 Board tut inittalDE2 115 pdf which is available on the DE2 115 system CD e Copy the entire demonstrations folder from the VEEK system CD to your host computer 4 2 Factory Configuration The VEEK development kit comes preconfigured with a default utility that boots up on power on and allows users to quickly select load and run different Ready to Run demonstrations stored on an SD Card using the VEEK touch panel Figure 4 1 gives a snapshot of the default application selector interface Note Every demonstration consists of a FPGA hardware image and an application software image When you select a
15. anual www terasic com www terasic com 3 3 Using the 8 LCD Touch Screen Module The VEEK features an 8 inch Amorphous TFI LCD panel The LCD Touch Screen module offers resolution of 800x600 to provide users the best display quality for developing applications The LCD panel supports 18 bit parallel RGB data interface The VEEK is also equipped with an Analog Devices AD7843 touch screen digitizer chip The AD7843 is a 12 bit analog to digital converter ADC for digitizing x and y coordinates of touch points applied to the touch screen The coordinates of the touch points can be read through the serial port interface on the AD7843 To display images on the LCD panel correctly the RGB color data along with the data enable and clock signals must act according to the timing specification of the LCD touch panel as shown in Table 3 1 Table 3 2 gives the pin assignment information of the LCD touch panel Table 3 1 LCD timing specifications Parameter Symbol Min Ew Max Unit CLK Frequency FCPH 39 79 MHz CLK Period FCPH 25 13 Ns CLK Pulse Duty FCWH 40 50 60 Yo DE Period FDEH TDEL 1000 1056 TCPH DE Pulse Width FDH 800 TCPH DE Frame Blanking FHS 10 28 110 FDEH TDEL DE Frame Width FEP 600 FDEH TDEL OEV Pulse Width TOEV 150 TCPH OKV Pulse Width TCKV 133 TCPH DE internal STV Time T1 4 TCPH DE internal CKV Time T2 40 TCPH DE internal OEV Time T3 23 TCPH DE internal POL Time T4 157 TCPH STV Pul
16. arter bat under the batch file folder VEEK Starterdemo batch e After Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal e From on the touch panel tap any icon of the main interface and start the experience as shown in Figure 4 4 Figure 4 5 and Figure 4 6 e Under each sub item touch the Exit button on the left bottom corner will lead you back to the main interface 19 Terasic VEEK User Manual www terasic com www terasic com JL Figure 4 4 Main interface of the VEEK Starter demonstration Figure 4 5 The VEEK Starter Touch sub item 20 Tasic Terasic VEEK User Manual www terasic com www terasic com Figure 4 6 The VEEK Starter Pattern sub item 4 4 VEEK Picture Viewer This demonstration shows a simple picture viewer implementation using Nios II based SOPC system It reads JPEG images stored on SD Card and displays them on the LCD The Nios II CPU decodes the images and fills the raw result data into frame buffers in SDRAM The VEEK will show the image the buffer being displayed points to When users touch the LCD Touch Panel it will proceed to display the next buffered image or last buffered image Figure 4 7 shows the block diagram of this demonstration The Nios II CPU here takes a key roll in the demonstration It is responsible of decoding the JPEG images and coordinates the works of all the peripherals The touch panel handling program uses the
17. ce This function can be used to split and join video streams giving control over the routing of color plane samples Frame Buffer Buffers video frames into external RAM This core supports double or triple buffering with a range of options for frame dropping and repeating 2D Median Filter Provides a way to apply 3 x 3 5 x 5 or 7 x 7 pixel median filters to video images Gamma Corrector Allows video streams to be corrected for the physical properties of display devices Clocked Video These two cores convert the industry standard clocked video format BT 656 to Input Output Avalon ST video and vice versa These functions allow you to fully integrate common video functions with video interfaces processors and external memory controllers The example design uses an Altera Cyclone IV E EPACEIT15F29 featured VEEK board 24 Ti jasiC Terasic VEEK User Manual www terasic com erasic com A video source is input through an analog composite port on VEEK which generates a digital output in ITU BT656 format A number of common video functions are performed on this input stream in the FPGA These functions include clipping chroma resampling motion adaptive deinterlacing color space conversion picture in picture mixing and polyphase scaling The input and output video interfaces on the VEEK are configured and initialized by software running on a Nios II processor Nios II software demonstrates how to control the clocked video input clocke
18. ck diagram of the demonstration 27 TTlasiC Terasic VEEK User Manual www terasic com www terasic com ANU S AYAN As soon as the configuration code is downloaded into the FPGA the I2C Sensor Configuration block will initial the CMOS sensor via I2C interface The CMOS sensor is configured as follow e Row and Column Size 800 600 e Exposure time Adjustable Pix clock MCLK 2 25 2 50MHz e Readout modes Binning According to the settings we can calculate the CMOS sensor output frame rate is about 44 4 fps After the configuration The CMOS sensor starts to capture and output image data streams the CMOS sensor Capture block extracts the valid pix data streams based on the synchronous signals from the CMOS sensor The data streams are generated in Bayer Color Pattern format So it s then converted to RGB data streams by the RAW2RGB block After that the Multi Port SDRAM Controller acquires and writes the RGB data streams to the SDRAM which performs as a frame buffer The Multi Port SDRAM Controller has two write ports and read ports also with 16 bit data width each The writing clock is the same as CMOS sensor pix clock and the reading clock is provided by the LCD Controller which is 40MHz Finally the LCD controller fetches the RGB data from the buffer and displays it on the LCD panel continuously Because the resolution and timing of the LCD is compatible with SVGA 800 600 the LCD controller generates the same timi
19. covery Figure 4 14 shows the Video and Image Processing block diagram JTAG UART SDRAM suge USMS sng uejs s Figure 4 14 VIP Camera Example SOPC Block Diagram Key Components B Demonstration Source Code e Project directory VEEK VIP Camera e Bit stream used VEEK VIP Camera sof e Nios II Workspace VEEK VIP Camera Software 31 Terasic VEEK User Manual www terasic com B Demonstration Batch File Demo Batch File Folder VEEK VIP CameraMemo batch The demo batch file includes the following files e Batch File VEEK VIP Camera bat VEEK VIP Camera bashrc e FPGA Configure File VEEK VIP Camera sof e Nios II Program VEEK VIP Camera elf B Demonstration Setup e Connect the VGA output of the VEEK board to a VGA monitor both LCD and CRT type of monitors should work e Load the bit stream into FPGA note e Run the Nios Il and choose VEEK VIP Camera Software as the workspace Click on the Run button note e The system enters the FREE RUN mode automatically Press KEY 0 on the DE2 115 board to reset the circuit e Press KEY 2 to stop run you can press KEY 3 again to switch back to FREE RUN mode and you should be able to see whatever the camera captures on the VGA display e Press and drag the video frame box will result in scaling the playing window to any size as shown in Figure 4 10 Q Note 1 Execute VEEK VIP CameraMemo batclNVEEK VIP CameraA bat will download sof and elf files 2 You may need additi
20. d video output and mixer functions at run time is also provided The video system is implemented using the SOPC Builder system level design tool This abstracted design tool provides an easy path to system integration of the video processing data path with a NTSC or PAL video input VGA output Nios II processor for configuration and control The Video and Image Processing Suite MegaCore functions have common open Avalon ST data interfaces and Avalon Memory Mapped Avalon MM control interfaces to facilitate connection of a chain of video functions and video system modeling In addition video data is transmitted between the Video and Image Processing Suite functions using the Avalon ST Video protocol which facilitates building run time controllable systems and error recovery Figure 4 9 shows the Video and Image Processing block diagram SOPC auge YO MS sng wasis age yamg sng WajsAs La Figure 4 9 VIP Example SOPC Block Diagram Key Components 25 Terasic VEEK User Manual www terasic com www terasio com B Demonstration Source Code e Project directory VEEK_VIP e Bit stream used VEEK VIP sof e Nios II Workspace VEEK_VIP Software B Demonstration Batch File Demo Batch File Folder VEEK VIPldemo batch The demo batch file includes the following files e Batch File VEEK VIP bat VEEK VIP bashrc e FPGA Configure File VEEK VIP sof e Nios II Program VEEK VIP elf B Demonstration Setup e Connect a DVD p
21. dix 6 1 Revision History Change Log Initial Version Preliminary Add Description of Digital Accelerometer 6 2 Copyright Statement Copyright 2011 Terasic Technologies All rights reserved 42 TTlasiC Terasic VEEK User Manual www terasic com www terasic com
22. e Nios II CPU runs the application software and controls all the peripherals A scatter gather DMA is used to transfer pixel data from the video buffer to the video pipeline 17 Terasic VEEK User Manual www terasic com www rasic com hA ouqe J PAUUODIAJU ulejes S Figure 4 2 Block diagram of the VEEK Starter demonstration Figure 4 3 illustrates the software structure of this demonstration The touch panel s SPI HAL block responds to the bottom hardware requests and interface to upper layers The SGDMA HAL allocates required frame descriptor buffers to specified memory address and is responsible of handling frame buffer update issue Figure 4 3 Software stack of the VEEK Starter demonstration TagasiC Terasic VEEK User Manual www terasic com www terasic com B Demonstration Source Code e Project directory VEEK_ Starter e Bit stream used VEEK Starter sof e Nios II Workspace VEEK_Starter Software B Demonstration Batch File Demo Batch File Folder VEEK Starter demo_ batch The demo batch file includes the following files e Batch File VEEK Starter bat VEEK Starter bashrc e FPGA Configure File VEEK Starter sof e Nios II Program VEEK Starter elf B Demonstration Setup e Make sure Quartus II and Nios II are installed on your PC e Power on the DE2 115 board e Connect USB Blaster to the DE2 115 board and install USB Blaster driver if necessary e Execute the demo batch file VEEK St
23. egapixel Digital Image Sensor Module The VEEK 1s equipped with a 5 Megapixel digital image sensor module that provides an active imaging array of 2 592H x 1 944 V It features low noise CMOS imaging technology that achieves CCD image quality In addition it incorporates sophisticated camera functions on chip such as windowing column and row skip mode and snapshot mode The sensor can be operated in its default mode or programmed by the user through a simple two wire serial interface for frame size exposure gain settings and other parameters Table 3 3 contains the pin names and descriptions of the image sensor module Table 3 3 Pin assignment of the CMOS sensor Signal Name FPGA Pin No Description VO Standard CAMERA PIXCLK PIN J27 Pixel clock 2 5V CAMERA DO PIN F26 Pixel data bit 0 2 5V CAMERA_ D1 PIN_E26 Pixel data bit 1 2 5V CAMERA_ D2 PIN_G25 Pixel data bit 2 2 5V 14 www terasic com Terasic VEEK User Manual rasic com CAMERA D3 CAMERA D4 CAMERA D5 CAMERA D6 CAMERA D7 CAMERA D8 CAMERA D9 CAMERA D10 CAMERA D11 CAMERA STROBE CAMERA LVAL CAMERA FVAL PIN G26 PIN H25 PIN H26 PIN K25 PIN K26 PIN L23 PIN L24 PIN M25 PIN M26 PIN G28 PIN K27 PIN K28 CAMERA RESET NPIN M28 CAMERA SCLK PIN K22 CAMERA TRIGGER PIN H23 CAMERA SDATA CAMERA XCLKIN PIN H24 PIN G23 Pixel data bit 3 Pixel data bit 4 Pixel data bit 5 Pixel data bit 6 Pixel data bit 7 Pixel data bit 8 Pixel data bit 9 Pixel data bit
24. essing for Camera oooo Wanna 30 4 8 VEEK Digital Accelerometer Demonstration Wak 33 CHAPTERS APPLICATION SELECTOR siiaiestestovuvugeu nana anana nana naen aana anaa anana eaaa aana m oRFFLOGGUCE Min 36 34 Ready t0 R n oD Card Demos Le ente aan ka rec aba m 36 5 2 Running the Application Selector s edaran wanan eso aan abasa anan gadane ae ene wanan asen ed nayana nsns nnn ns 37 32 Application Selector WG FANG aa ap daana TT TO kaa pinaka 37 34 Me Or mi the Factory naek al ad TOT 39 1 Terasic VEEK User Manual www terasic com www terasic com ANU S RYA CF Mn na E anang ubah 42 AIR Gy USO OES COTY et on ne ma an aa ag aa sam anna uno baa an ian ba na ai 42 OLLO CD CIN oon cc sas nan A Na ag na Aa Ga Ta Ra BAE Wan E A a E Na aa AA A A 42 2 Terasic VEEK User Manual www terasic com Chapter 1 Introduction of the VEEK The VEEK FPGA Development Kit is a comprehensive design environment with everything embedded developers need to create processing based systems The VEEK delivers an integrated platform that includes hardware design tools intellectual property IP and reference designs tor developing embedded software and hardware platform in a wide range of applications The fully integrated kit allows developers to rapidly customize their processor and IP to best suit their specific application The VEEK features the DE2 115 development board targeting the Cyclone IV E FPGA as
25. guring the FPGA in JTAG Mode Figure 3 3 illustrates the JTAG configuration setup To download a configuration bit stream into the Cyclone IV E FPGA perform the following steps e Ensure that power is applied to the VEEK board e Configure the JTAG programming circuit by setting the RUN PROG slide switch SW19 to the RUN position See Figure 3 4 e Connect the supplied USB cable to the USB Blaster port on the VEEK board e The FPGA can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the sof filename extension 10 Terasic VEEK User Manual www terasic com www terasic co m USB Blaster Circuit PROG RUN Quartus II E amp EPM 240 E JTAG Config Signal QUARTUS II Greg Signals Cyclone IV RUN Figure 3 3 The JTAG chain configuration scheme SW19 Figure 3 4 The RUN PROG switch SW19 is set to JTAG mode B Configuring the EPCS64 in AS Mode Figure 3 5 illustrates the AS configuration set up To download a configuration bit stream into the EPCS64 serial configuration device perform the following steps e Ensure that power is applied to the VEEK board e Connect the supplied USB cable to the USB Blaster port on the VEEK board e Configure the JTAG programming circuit by setting the RUN PROG slide switch SW19 to the PROG position e The EPCS64 chip can now be programmed by using the Quartus II Programmer module to select a configuration bit stream file with the
26. hardware image from EPCS device 4 The command will use the default HAL boot loader and link it to the text section 5 You can also use the tool bin demo batch to convert your sof and elf to bin Copy your example sof and your example elf to the bin demo batch folder rename them to test sof test elf execute the test bat then the final test HW bin and test SW bin are your target files 5 4 Restoring the Factory Image This section describes some details about the operation of restoring the Application Selector factory image 39 Ti jasiC Terasic VEEK User Manual www terasic com www teresic com Combining factory recovery binary files In the factory settings you need to program Application Selector binary files to EPCS Before programming you should combine application selector software binary file and hardware binary file together by executing the instructions below e Copy both the VEEK Selector sof and VEEK Selector elf files into a common directory relying on your choice This directory is where you will convert the files e On your host PC launch a Nios II Command Shell from Start gt Programs gt Altera gt Nios II version gt EDS gt Nios II Command Shell e From the command shell navigate to where your SOF file is located and create your hardware binary file using the following command commands listed below e Convert VEEK Selector sof file into VEEK Selector HW flash file sof2flash epcs inpu
27. ility SD Card The Application Selector uses the SD Card for storing applications The SD Card must be formatted with the FAT 16 file system and can be any capacity up to 2GB Long file names are supported The Nios II CPU access the SD Card through an SD Card SPI controller Application Files Each loadable application consists of two binary files all stored on the SD Card The first binary file represents the software portion of the example and must be derived from an ELF file as described in the section of this document titled Creating Your Own Loadable Applications This binary file can be named anything supported by the FAT16 file system the only restriction being that the name must end with _SW bin The second binary file represents the hardware portion of the example and must be derived from a SOF file as described in the section of this document titled Creating Your Own Loadable Applications This file can be named anything supported by the FAT 16 file system the only restriction being that the name must end with HW bin SD Card Directory Structure All loadable applications on the SD Card must be located in a top level directory named Application_Selector Under the Application_Selector directory each application is located in its own subdirectory The name of that subdirectory is important because the application selector utility uses that name as the title of the application when displaying it in the main menu The subdirect
28. in a Nios II CPU whose reset address is set to CFI Flash at offset 0x0 e Before compiling the software make sure you have set your software s program memory text section in Flash memory under the System Library Properties Nios II IDE page or through BSP Editor Nios II SBT for Eclipse utility 2 Once you have your working SOF and ELF file pair perform the following steps to convert them to a loadable application selector compatible application e Copy both the SOF and ELF files into a common directory relying on your choice This directory is where you will convert the files e On your host PC launch a Nios II Command Shell from Start gt Programs gt Altera gt Nios II version gt EDS gt Nios II Command Shell e From the command shell navigate to where your SOF file is located and create your hardware binary file using the following commands e Convert sof file into flash file sof2flash epcs input your example sof output your example HW flash 3 e Convert flash file into binary file nios2 elf objcopy I srec O binary your example HW flash your example HW bin 38 Ti jasiC Terasic VEEK User Manual www terasic com www teresic com e From the command shell navigate to where your ELF file is located and create your software binary file using the following command nios2 elf objcopy O binary your example elf your example_SW bin 4 5 e Create a new subdirectory and
29. ious image Play Stop del to play the slide or stop it On the top corner you will see the Delay period in Sec You can increase or decrease the delay period by touching the Me or buttons The max delay is 120 seconds the min delay is 1 second default is 10 seconds You can hide the control buttons by clicking on the Hide button located at the top left corner of the touch screen Touch anywhere on the screen to resume and to return to menu Figure 4 8 VEEK picture viewer demonstration Q Note execute the VEEK Picture Viewer bat under VEEK Picture ViewerMemo batch will automatically download the sof and elf file 23 TTlasiC Terasic VEEK User Manual www terasic com www terasic com 4 5 Video and Image Processing The Video and Image Processing VIP Example Design demonstrates dynamic scaling and clipping of a standard definition video stream in either National Television System Committee NTSC or Phase Alternation Line PAL format and picture in picture mixing with a background layer The video stream is output in high definition resolution 800x600 on the HSMC LTC daughter card part of the VEEK The example design demonstrates a framework for rapid development of video and image processing systems using the parameterizable MegaCore functions that are available in the Video and Image Processing Suite Available functions are listed in Table 4 1 This demonstration needs the Quartus II license file incl
30. layer s composite video output yellow plug to the Video IN RCA jack J12 of the VEEK board The DVD player has to be configured to provide NTSC output or PAL output e Connect the VGA output of the VEEK board to a VGA monitor both LCD and CRT type of monitors should work e Load the bit stream into FPGA note e Run the Nios Il and choose VEEK_VIP Software as the workspace Click on the Run button note e Press and drag the video frame box will result in scaling the playing window to any size as shown in Figure 4 10 Q Note 1 Execute VEEK_VIP demo_batch VEEK VIP bat will download sof and elf files 2 You may need additional Altera VIP suite Megacore license features to recompile the project Figure 4 11 illustrates the setup for this demonstration 26 Terasic VEEK User Manual www terasic com www terasic com Figure 4 10 The VIP demonstration running result Video In CVBS Output 99 Ku DVD Player Figure 4 11 Setup for the VEEK VIP demonstration 4 6 VEEK Camera Application This demonstration shows a digital camera reference design using the 5 Megapixel CMOS sensor and 8 inch LCD modules on the VEEK The CMOS sensor module sends the raw image data to FPGA on DE2 115 Board the FPGA on the board 1s handling image processing part and converts the data to RGB format to display on the LCD module The I2C Sensor Configuration module 1s used to configure the CMOS sensor module Figure 4 12 shows the blo
31. lm Transistor Liquid Crystal Display module e Module composed of LED backlight e Support 18 bit parallel RGB interface e Converting the X Y coordination of touch point to its corresponding digital data via the Analog Devices AD7843 A D converter Table 1 1 shows the general physical specifications of the LTC Note Table 1 1 General physical specifications of the LCD Item Specification Unit LCD size 8 inch Diagonal Resolution 800 x3 RGB x 600 dot Dot pitch 0 0675 W x 0 2025 H mm Active area 162 0 W x 121 5 H mm Module size 183 0 W x 141 0 H x 7 2 D mm Surface treatment Anti Glare Color arrangement RGB stripe Interface Digital B 5 Megapixel digital image sensor module e Superior low light performance e High frame rate e Low dark current e Global reset release which starts the exposure of all rows simultaneously e Bulb exposure mode for arbitrary exposure times e Snapshot mode to take frames on demand e Horizontal and vertical mirror image e Column and row skip modes to reduce image size without reducing field of view e Column and row binning modes to improve image quality when resizing e Simple two wire serial interface e Programmable controls gain frame rate frame size exposure Table 1 2 shows the key parameters of the CMOS sensor Note 4 Terasic VEEK User Manual www terasic com www terasic com Table 1 2 Key performance parameters of the CMOS sensor Parameter Active Pixels Pixel size
32. ng and the frame rate can achieve about 25 fps CMOS RAW2RGB m Controller Capture P CMOS Sensor hd g Pa T Pi Configuration Mult Port SDRAM SDRAM tPad Figure 4 12 Block diagram of the digital camera design 28 Terasic VEEK User Manual www terasic com www terasic com B Demonstration Source Code e Project directory VEEK Camera e Bit stream used VEEK Camera sof B Demonstration Batch File Demo Batch File Folder VEEK Camera Memo batch The demo batch file includes the following files e Batch File VEEK Camera bat e FPGA Configure File VEEK Camera sof B Demonstration Setup e Load the bit stream into FPGA by execute the batch file VEEK Camera bat under VEEK CameraMemo batch folder e The system enters the FREE RUN mode automatically Press KEY 0 on the DE2 115 board to reset the circuit e Press KEY 2 to take a shot of the photo you can press KEY 3 again to switch back to FREE RUN mode and you should be able to see whatever the camera captures on the LCD display e User can use the SW 0 and KEY 1 to set the exposure time for brightness adjustment of the image captured When SW 0 is set to Off the brightness of image will be increased as KEY I is pressed longer If SW 0 is set to On the brightness of image will be decreased as KEY 1 is pressed shorter Q Note execute the VEEK Camera bat under VEEK CameraMemo batch will automatically download the sof file Table 4 2 summarizes the
33. onal Altera VIP suite Megacore license features to recompile the project Figure 4 15 illustrates the setup for this demonstration 32 Terasic VEEK User Manual www terasic com www terasic com VGA Out VGA LCD CRT Monitor AAR ANT ELS PHP Ti LI afer a Zu LE Ea Pa mn nu an 3 a Tz inii WRETREEEEREEEEEE T Jalalain Pena Na Figure 4 15 Setup for the VEEK_VIP_Camera demonstration 4 8 VEEK Digital Accelerometer Demonstration This demonstration shows a bubble level implementation based on a digital accelerometer We use LC protocol to control the ADXL345 digital accelerometer and the LCD display the interface of our game When tilt the VEEK board the ADXL345 measures the static acceleration of gravity In our Nios II software we compute the change of angle in the x axis and y axis and show angle data in the LCD display Figure 4 16 shows the hardware system block diagram of this demonstration The system is clocked by an external SOMHz Oscillator Through the internal PLL module the generated 150MHz clock is used for Nios II processor and other components and there also a 40MHz pixel clock for the video pipeline and 10MHz for low speed peripherals 33 Terasic VEEK User Manual www terasic com pa ouqe4joeuuoojeju WajasAS ADXL345 Figure 4 16 Block diagram of the digital accelerometer demonstration B Demonstration Source Code e Project directory VEEK G sensor e
34. orkspace e Choose Tools gt Flash Programmer to open the flash programmer e Choose Program a file into memory choose your VEEK Selector bin file See Figure 5 2 e Click Program Flash to start program VEEK Selector bin to EPCS in the board e When program finish power on again Q You can also use VEEK Selector batch to generate selector bin and restore the original binary file by executing the VEEK Selector bat under the VEEK Factory Recovery WEEK Selector batch folder Flash Programmer Program project to flash memory on target board Program flash with Veek Selector bin using script D SVN veek trunk cd VEEK Demonstration Veek Selector software Veek Selector Debug flash programmer sh lt zt rm 3x XL Name flash programmer type filter text CT ee Connection z Q Flash Programmer KP flash programmer Target Hardware Additional sofZflash arguments Additional nios2 flash programmer arguments Load JDI File Program FPG configuration data into hardware image region of flash memory Memory Offset v Program a file into flash memory File D S W veek trunk cd VEEK DenonstrationWeek Selector Week Selector bin Memory epcs flash controller v Offset 0x0 Validate Nios II system ID before software download v Frog He Figure 5 2 Programming Flash settings 4 Terasic VEEK User Manual www terasic com www terasic com Chapter 6 Appen
35. ory names can be anything so long as they adhere to the FAT file system long file name rules Spaces are permitted 37 Terasic VEEK User Manual www terasic com www teresic com CFI Flash CFI flash is used to store the software binary files of applications All software binary files used by the application selector contain a boot copier which is pre ended by the Nios2 elf objcopy utility during file conversion process described in the Creating Your Own Loadable Applications section The boot copier copies the software code to program memory before running it The Application software binary file is stored in flash at load time to an offset 0x0 EPCS Device EPCS is used to store both the binary file of the Application Selector both hardware and software image itself as well as hardware binary files of applications which are being loaded The Application Selector binary file is permanently stored in EPCS device at offset 0x0 Hardware binary files for the applications being loaded get written to EPCS at load time to an offset 0x400000 Creating Your Own Loadable Applications It is easy to convert your own Nios II design into an application which is loadable by the Application Selector utility All you need 1s a hardware image a SOF file and a software image which runs on that hardware a Nios II ELF file The only restrictions are e The hardware designs must contain a CFI Flash controller 1 e The SOF file must conta
36. pof filename extension e Once the programming operation is finished set the RUN PROG slide switch back to the RUN position and then reset the board by turning the power switch off and back on this action causes the new configuration data in the EPCS64 device to be loaded into the FPGA chip 11 Terasic VEEK User Manual www terasic com www teresic com ANU S AYAN USB Blaster Circuit Quartus FRONSISUN AS Mode Auto Power on NRhre BYA Programmer MAX Config Config an EPM 240 e E T QUARTUS II PROG Figure 3 5 The AS configuration scheme 3 2 Bus Controller The VEEK comes with a bus controller using the Max II EPM240 that allows user to access the touch screen module through the HSMC connector This section describes its structure in block diagram form and its capabilities B Bus Controller Introduction The bus controller provides level shifting functionality from 2 5V HSMC to 3 3V domains B Block Diagram of the Bus Controller Figure 3 6 gives the block diagram of the connection setup from the HSMC connector to the bus controller on the Max II EPM240 to the touch screen module To provide maximum flexibility for the user all connections are established through the HSMC connector Thus the user can configure the Cyclone IV E FPGA on the VEEK to implement any system design LCD Touch Panel EPM240 Figure 3 6 Block Diagram of the Bus Controller 12 Terasic VEEK User M
37. ra Cyclone IV E EPACEIT15F29 featured VEEK board A video source 1s input through the CMOS sensor on VEEK which generates a digital output in RGB format A number of common video functions are performed on this input stream in the FPGA These functions include clipping chroma resampling motion adaptive deinterlacing color space conversion picture in picture mixing and polyphase scaling The input and output video interfaces on the VEEK are configured and initialized by software running on a Nios II processor Nios II software demonstrates how to control the clocked video input clocked video output and mixer functions at run time is also provided The video system is implemented using the SOPC Builder system level design tool This abstracted design tool provides 30 TTlasiC Terasic VEEK User Manual www terasic com www terasic com ANU S AYAN an easy path to system integration of the video processing data path with a NTSC or PAL video input VGA output Nios II processor for configuration and control The Video and Image Processing Suite MegaCore functions have common open Avalon ST data interfaces and Avalon Memory Mapped Avalon MM control interfaces to facilitate connection of a chain of video functions and video system modeling In addition video data is transmitted between the Video and Image Processing Suite functions using the Avalon ST Video protocol which facilitates building run time controllable systems and error re
38. se Width 1 TH Note THS THA lt TH Table 3 2 Pin assignment of the LCD touch panel Signal Name FPGA Pin No Description O Standard LCD_DIM PIN_P27 LCD backlight enable 2 5V LCD_NCLK PIN_V24 LCD clock 2 5V LCD_RO PIN_V26 LCD red data bus bit 0 2 5V LCD R1 PIN R27 LCD red data bus bit 1 2 5V 13 TilasiC Terasic VEEK User Manual www terasic com rasic com LCD R2 PIN R28 LCD red data bus bit 2 2 5V LCD R3 PIN U27 LCD red data bus bit 3 2 5V LCD R4 PIN U28 LCD red data bus bit 4 2 5V LCD R5 PIN V27 LCD red data bus bit 5 2 5V LCD GO PIN P21 LCD green data bus bit 0 2 5V LCD G1 PIN R21 LCD green data bus bit 1 2 5V LCD G2 PIN R22 LCD green data bus bit 2 2 5V LCD G3 PIN R23 LCD green data bus bit 3 2 5V LCD G4 PIN T21 LCD green data bus bit 4 2 5V LCD G5 PIN T22 LCD green data bus bit 5 2 5V LCD BO PIN V28 LCD blue data bus bit 0 2 5V LCD B1 PIN U22 LCD blue data bus bit 1 2 5V LCD B2 PIN V22 LCD blue data bus bit 2 2 5V LCD B3 PIN V25 LCD blue data bus bit 3 2 5V LCD B4 PIN L28 LCD blue data bus bit 4 2 5V LCD B5 PIN J26 LCD blue data bus bit 5 2 5V LCD DEN PIN P25 LCD RGB data enable 2 5V TOUCH PENIRQ N PIN L22 AD7843 pen interrupt 2 5V TOUCH DOUT PIN L21 AD7843 serial interface data out 2 5V TOUCH BUSY PIN U26 AD7843 serial interface busy 2 5V TOUCH DIN PIN U25 AD7843 serial interface data in 2 5V TOUCH CS N PIN T26 AD7843 serial interface chip select input 2 5V TOUCH DCLK PIN T25 AD7843 interface clock 2 5V 3 4 Using 5 M
39. tZ VEEK Selector sof output VEEK Selector HW flash e Convert flash file into bin file nios2 elf objcopy I srec O binary VEEK Selector HW flash VEEK Selector HW bin e From the command shell navigate to where your ELF file is located and create your software bin image using the following command commands listed below e Convert VEEK Selector elf into VEEK Selector SW flash elf2flash epcs after VEEK_ Selector HW flash inputZ VEEK Selector elf output VEEK Selector SW flash e Convert VEEK Selector SW flash into VEEK Selector SW bin nios2 elf objcopy I srec O binary VEEK Selector SW flash VEEK Selector SW bin e Combine VEEK Selector HW bin and VEEK Selector SW bin using the following command cat VEEK Selector ZW bin VEEK Selector SW bin gt VEEK Selector bin e The generated VEEK Selector bin is our target binary file Restoring the original binary file e To restore the original contents of the Application Selector perform the following steps e Copy VEEK Selector project into a local directory of your choice The VEEK Selector project is placed in VEEK Demonstrations VEEK Selector 40 Ti jasiC Terasic VEEK User Manual www terasic com www terasic com e Power on the VEEK board with the USB cable connected to the USB Blaster port e Download the VEEK Selector sof to the board by using either JTAG or AS programming e Run the Nios II and choose VEEK_Selector Software as the w
40. the System CD under VEEK_Factory_Recovery Application_Selector folder Figure 5 1 shows the photograph while the Application Selector is loading an image Altera VEEK Application Selector VEEK Pic VEEK VIP VEEK Camera Figure 5 1 Application selector loading image Also you can easily convert your own applications to be loadable by the application selector For more information see Creating Your Own Loadable Applications in section 5 3 If you have lost the contained files in the SD Card you could find them on the VEEK System CD under the VEEK Factory Recovery folder 36 TTlasiC Terasic VEEK User Manual www terasic com www rasic com 5 2 Running the Application Selector Connect power to the VEEK board Insert the SD Card with applications into the SD Card socket of VEEK Switch on the power SW18 1 Scroll to select the demonstration to load using the side bar Tap on the Load button to load and run a demonstration 2 Q Note 1 If the board is already powered the application selector will boot from EPCS and a splash screen will appear while the application selector searches for applications on the SD Card 2 The application will begin loading and a window will be displayed showing the progress Loading will take between 2 and 30 seconds depending on the size of the application 5 3 Application Selector Details This section describes some details about the operation of the application selector ut
41. udes the VIP suite feature Table 4 1 VIP IP cores functions IP MegaCore Description Function Frame Reader Reads video from external memory and outputs it as a stream Control Synchronizes the changes made to the video stream in real time between two Synchronizer functions Switch Allows video streams to be switched in real time Color Space Converts image data between a variety of different color spaces such as RGB to Converter YCrCb Chroma Resampler Changes the sampling rate of the chroma data for image frames for example from 4 2 2 to 4 4 4 or 4 2 2 to 4 2 0 2D FIR Filter Implements a 3 x 3 5 x 5 or 7 x 7 finite impulse response FIR filter on an image data stream to smooth or sharpen images Alpha Blending Mixes and blends multiple image streams useful for implementing text overlay Mixer and picture in picture mixing Scaler A sophisticated polyphase scaler that allows custom scaling and real time updates of both the image sizes and the scaling coefficients Deinterlacer Converts interlaced video formats to progressive video format using a motion adaptive deinterlacing algorithm Also supports bob and weave algorithms Test Pattern Generates a video stream that contains still color bars for use as a test pattern Generator Clipper Provides a way to clip video streams and can be configured at compile time or at run time Color Plane Changes how color plane samples are transmitted across the Avalon ST Sequencer interfa
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