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Use of buffer-size mask in conjunction with address pointer to detect

1. 710 100 k WO 8 1988 06 9 46 cited by examiner Primary Examiner Paul R Myers 57 ABSTRACT A CAN microcontroller that supports a plurality of message objects and that includes a CAN processor core a plurality of message buffers associated with respective ones of the message objects CAN CAL module that processes incom ing messages that include a plurality of frames and a plurality of message object registers including at least one buffer size register that contains a message buffer size value and at least one buffer location register that contains an address pointer The CAN CAL module includes a message handling function that transfers successive frames of the current incoming message to the message buffer associated with a selected one of the message objects designated as a receive message object for the current incoming message an address pointer increment function The CAN CAL module further includes a frame status detection function and a buffer status detection function that retrieves the incre mented address pointer value retrieves the message buffer size value from the at least one buffer size register associated with the designated receive message object and decodes the retrieved message buffer size value into a buffer size mask and determines a message buffer fullness status of the mes sage buffer associated with the designated receive message object using the retrieved increment
2. ENGINE LT E TIMER 2 e WATCHDOG 1 2 0B CAN DLL TIMER 42 7 21 U S Patent Sep 2 2003 Sheet 3 of 7 US 6 615 302 B1 MMRs Address Offset Description Message Object Registers n 0 31 ea DUTIES So Wet OOo Byte Word Message n Fragmentation Count 000 MCR RO 00008 MER RO 00h ByteWord 10001 0000h Frame Error Enable Register SCP SPI Control and Status CCB Registers ae ra LM RW 204 RW 00 ________ __ 10000 Error Code Capture Register AR RO 0000h Global Control Bye MIF Registers XRAM Base Address FFh Legend RAW Read amp Write RO Read Only WO Write Only R C Read amp Clear W Writable only during F G 4 CAN Reset mode x undefined after reset U S Patent Sep 2 2003 Sheet 4 of 7 US 6 615 302 B1 Data Memory Segment 0 OOFFFFh LLLLLLLI 4K Bytes MMR Space MMR Base Address Off Chip 512 XRAM Base Address Off Chip 0003FFh Off Chip Data Memory Scratch Pad MMR Space Offset FFFh Aaa Offset gt 512 Bytes Object Registers FIG 6 Offset 000h U S Patent Sep 2 2003 Sheet 5 of 7 US 6 615 302 B1 Segment xy in Data Memory Space xyFFFFh Obiect nf Object n Me
3. 8 is a diagram illustrating formation of the base address of the on chip XRAM of the XA C3 microcontroller with an object n message buffer mapped into the on chip XRAM FIG 9 is a diagram illustrating the Screener ID Field for a Standard CAN Frame FIG 10 is a diagram illustrating the Screener ID Field for an Extended CAN Frame FIG 11 is diagram illustrating the message storage format for fragmented CAL messages and FIG 12 is a diagram illustrating the message storage format for fragmented CAN messages DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention is described below in the context of a particular implementation thereof i e in the context of the XA C3 microcontroller manufactured by Philips Semicon ductors Of course it should be clearly understood that the present invention is not limited to this particular implementation as any one or more of the various aspects and features of the present invention disclosed herein can be utilized either individually or any combination thereof and in any desired application e g in a stand alone CAN controller device or as part of any other microcontroller or system The following terms used herein in the context of describ ing the preferred embodiment of the present invention 1 the XA C3 microcontroller are defined as follows Standard CAN Frame The format of a Standard CAN Frame is depicted in FIG 1 Extended CAN Frame The format of an Exte
4. 2 Fragmented Message A lengthy message in excess of 8 bytes divided into data packets and transmitted using a sequence of individual CAN Frames The specific ways that sequences of CAN Frames construct these lengthy messages is defined within the context of a specific CAL The XA C3 microcontroller automatically re assembles these packets into the original lengthy message in hard ware and reports via an interrupt when the completed re assembled message is available as an associated Receive Message Object Message Buffer A block of locations in XA Data memory where incoming received messages are stored or where outgoing transmit messages are staged MMR Memory Mapped Register An on chip command control status register whose address is mapped into XA Data memory space and is accessed as Data memory by the XA processor With the XA C3 microcontroller a set of eight dedicated MMRs are associated with each Mes sage Object Additionally there are several MMRs whose bits control global parameters that apply to all Message Objects With reference now to FIG 3 there can be seen a high level block diagram of the XA C3 microcontroller 20 The XA C3 microcontroller 20 includes the following func tional blocks that are fabricated on a single integrated circuit IC chip packaged in a 44 pin PLCC or a 44 pin LOFP package an XA CPU Core 22 that is currently implemented as a 16 bit fully static CPU with 24 bit program and data add
5. A complete listing of all MMRs is pro vided in the Table depicted in FIG 5 a 2 0B CAN DLL Core 42 that is the CAN Controller Core from the Philips SJA1000 CAN 2 0A B Data Link Layer CDLL device hereinafter referred to as the CAN Core Block CCB and an array of standard microcontroller peripherals that are bi directionally coupled to the XA CPU Core 22 via a Special Function Register SFR bus 43 These standard microcontroller peripherals include Universal Asynchro nous Receiver Transmitter UART 49 an SPI serial inter face port 51 three standard timers counters with toggle output capability namely Timer 0 amp Timer 1 included in Timer block 53 and Timer 2 included in Timer block 54 a Watchdog Timer 55 and four 8 bit I O ports namely Ports 0 3 included in block 61 each of which has 4 programmable output configurations The DMA engine 38 the MMRs 40 and the CCB 42 can collectively be considered to constitute CAN CAL module 77 and will be referred to as such at various times through out the following description Further the particular logic elements within the CAN CAL module 77 that perform message management and message handling functions will sometimes be referred to as the message management engine and the message handler respectively at various times throughout the following description Other nomen clature will be defined as it introduced throughout the following description As previ
6. and the current frame of the current incoming mes sage is not the final frame of the current incoming message 5 The CAN microcontroller as set forth in claim 1 wherein the buffer status detection function determines the buffer fullness state of the message buffer associated with the designated receive message object by determining whether the number of available bytes of remaining storage capacity in the message buffer associated with the desig nated receive message object is less than the maximum number n of data bytes using the retrieved incremented address pointer value and the message buffer size mask US 6 615 302 B1 25 6 The CAN microcontroller as set forth in claim 5 wherein the buffer status detection function declares a mes sage buffer full condition if the determined number of available bytes is less than the maximum number n of data bytes and the current frame of the current incoming mes sage is not the final frame of the current incoming message 7 The CAN microcontroller as set forth in claim 2 wherein the buffer status detection function determines a second buffer fullness state of the message buffer associated with the designated receive message object by logically AND ing the first z ones of the x OR results to produce a second single bit AND result where 2 n wherein a 1 value of the second single bit AND result corresponds to the second buffer fullness state of the message buffer associated with the
7. current CAN application in response to the message complete interrupt retrieves a first number of the data bytes of the current incoming message from the first buffer portion and retrieves a second number of the data bytes of the current incoming message from the second buffer portion where the first number is the current byte count BRIEF DESCRIPTION OF THE DRAWINGS These and various other aspects features and advantages of the present invention will be readily understood with reference to the following detailed description of the inven tion read in conjunction with the accompanying drawings in which FIG 1 is a diagram illustrating the format of a Standard CAN Frame and the format of an Extended CAN Frame FIG 2 is a diagram illustrating the interleaving of CAN Data Frames of different unrelated messages FIG 3 is a high level functional block diagram of the XA C3 microcontroller FIG 4 is a table listing all of the Memory Mapped Registers MMRs provided by the XA C3 microcontroller US 6 615 302 B1 5 FIG 5 is a diagram illustrating the mapping of the overall data memory space of the XA C3 microcontroller FIG 6 is a diagram illustrating the MMR space contained within the overall data memory space of the XA C3 micro controller FIG 7 is a diagram illustrating formation of the base address of the on chip XRAM of the XA C3 microcontroller with an object n message buffer mapped into off chip data memory FIG
8. of the user programmer configuring programming some or all of the eight MMRs 40 dedicated to that Message Object In the XA C3 microcontroller 20 each of the 32 Message Objects is assigned its own block of address space in data memory which serves as its message buffer for data storage The size and location of each message buffer is programmable and thus reconfigurable on the fly by the user programmer The message buffers can be positioned in any desired location within the overall data memory space addressable by the XA C3 microcon troller 20 which is presently configured to be a 16 Mbyte overall memory space These message buffers can be located in the XRAM 28 and or in any off chip portion of the overall data memory space The location of the message buffer associated with each Message Object n is established by programming the MMR 40 designated MnBLR associated with that Message Object i e by programming the Message n Buffer Location Reg ister The size of the message buffer associated with each Message Object is established by programming the MMR 40 designated MnBSZ associated with that Message Object 1 by programming the Message n Buffer SiZe Register In the XA C3 microcontroller 20 allowable buffer sizes are 2 4 8 16 32 64 128 or 256 bytes Users can select the size of each message buffer based on the anticipated length of the incoming message or they can conserve memory by delib erately specifying smaller
9. that in response to a transfer of the current data byte to the message 10 15 20 25 35 40 45 50 55 60 65 24 buffer associated with the designated receive mes sage object increments the address pointer to the address of the storage location in that message buffer where the next data byte of the current incoming message is to be stored a flame status detection function that detects whether or not the current flame of the current incoming mes sage is the final flame of the current incoming message and a buffer status detection function that each time that the address pointer is incremented retrieves the incremented address pointer value retrieves the message buffer size value from the at least one buffer size register associated with the designated receive message object and decodes the retrieved message buffer size value into a buffer size mask comprised of a plurality x of bits where x is equal to a prescribed number of allow able buffer sizes and wherein y bits of the buffer size mask have a first logic state and the remaining X y bits have a second logic state where 2 equals the retrieved message buffer size value in terms of number of bytes and determines a message buffer fullness status of the message buffer associated with the designated receive message object using the retrieved incre mented address pointer value and the message buffer size mask 2 The CAN microcontroller as set f
10. the CAN Frame belongs to is a non fragmented single frame message or a fragmented message Each case 18 described below Non Fragmented Message Assembly For Message Objects that have been set up with automatic fragmented message handling disabled not enabled i e the FRAG bit in the MnCTL register for that Message Object is set to 07 the complete CAN ID of the accepted CAN Frame which is either 11 or 29 bits depending on whether the accepted CAN Frame is a Standard or Extended CAN Frame is written into the MnMIDH and MnMIDL registers associated with the Message Object that has been deemed to constitute a match once the DMA engine 38 has successfully transferred the accepted CAN Frame to the message buffer associated with that Message Object This will permit the user application to see the exact CAN ID which resulted in the match even if a portion of the CAN ID was masked for Acceptance Filtering As a result of this mechanism the contents of the MnMIDH and MnMIDL registers can change every time an incoming CAN Frame is accepted Since the incoming CAN Frame must pass through the Acceptance Filter before it can be accepted only the bits that are masked out will change Therefore the criteria for match and mask Acceptance Filtering will not change as a result of the contents of the MnMIDH and MnMIDL registers being changed in response to an accepted incoming CAN Frame being transferred to the appropriate message buffer Fragmente
11. the MCPLH or MCPLL register will be set This will occur regardless of whether the INT EN bit is set for that particular Message Object in its associated MnCTL register or whether Message Complete Status Flags have already been set for any other Message Objects In addition to these 32 Message Complete Status Flags there is a Tx Message Complete Interrupt Flag and an Rx Message Complete Interrupt Flag corresponding to bits 1 and 0 respectively of an MMR 40 designated CANINTFLG which will generate the actual Event inter rupt requests to the XA CPU Core 22 When an End of Message condition occurs at the same moment that the Message Complete Status Flag is set the appropriate Tx or Rx Message Complete Interrupt flip flop will be set pro vided that INT EN 1 for the associated Message Object and provided that the interrupt is not already set and pend ing Further details regarding the generation of interrupts and the associated registers can be found in the XA C3 Func tional Specification and in the XA C3 CAN Transport Layer US 6 615 302 B1 15 Controller User Manual both of which are part of the parent Provisional Application Serial No 60 154 022 the disclo sure of which has been fully incorporated herein for all purposes Message Buffers As was previously described in detail hereinabove the XA C3 microcontroller 20 supports up to 32 separate and independent Message Objects each of which is set up or defined by virtue
12. 0 The value Byte Count n will indicate how many times the address pointer has been incremented away from the bottom location of that message buffer 1 from the base address storage location When the end of message condition is detected 1 e the currently received frame is the final frame of the incoming message or when the buffer rollover point is reached the address pointer must be reset to its original programmed value i e the base address By definition the y LSBs of the of the address pointer where 2 the buffer size value must be cleared to 0 The remaining higher order bits of the address pointer must be left alone since the hardware would not have modified them anyway In accordance with the present invention address pointer reset logic within the CAN CAL module 77 logically ANDs each of the LSBs of the address pointer with the corresponding bit of the asso ciated buffer size mask and writes the resultant value back into the associated MnBLR register as the new address pointer value which will be the same as the initially programmed base address i e New Addr pointer n addr pointer n AND mask n where n27 0 in the current specific implementation of the XA C3 microcon troller 20 Although the present invention has been described in detail hereinabove in the context of a specific preferred embodiment implementation it should be clearly under stood that many variations modifications and or al
13. 77 determin ing the number of bytes that remain available for message data storage in the designated message buffer by subtracting the LSBs of the current address pointer i e the current address value in the MnBLR register from the buffer size value 1 the value in the MnBSZ register and comparing the result to 7 If seven bytes or more remain available for message data storage in the designated message buffer then there is definitely sufficient space to store at least one more frame so no buffer full condition exists If less than seven bytes remain available for message data storage in the designated message buffer then a buffer full condition is declared 10 15 20 25 30 35 40 45 50 55 60 65 20 In response to a buffer full condition logic in the XA C3 CAN CAL module 77 performs the following steps 1 The current byte count is derived from the contents of the MnBLR and MnBSZ registers 2 The address pointer for the associated Message Object n is reset to the bottom 0 location of the designated message buffer i e the current value of the MnBLR register associated with that message buffer is replaced with the base address initially programmed by the user into the MnBLR register associated with that message buffer 3 The current byte count is written into the 0 location i e base address of the designated message buffer and then the address pointer the value i
14. CT BUFFER FULL AND BUFFER ROLLOVER CONDITIONS IN A CAN DEVICE THAT EMPLOYS RECONFIGURABLE MESSAGE BUFFERS This application claims the full benefit and priority of U S Provisional Application Serial No 60 154 022 filed on Sep 15 1999 the disclosure of which is fully incorporated herein for all purposes BACKGROUND OF THE INVENTION present invention relates generally to the field of data communications and more particularly to the field of serial communications bus controllers and microcontrollers that incorporate the same CAN Control Area Network is an industry standard two wire serial communications bus that is widely used in automotive and industrial control applications as well as in medical devices avionics office automation equipment consumer appliances and many other products and appli cations CAN controllers are currently available either as stand alone devices adapted to interface with a microcon troller or as circuitry integrated into or modules embedded in a microcontroller chip Since 1986 CAN users software programmers have developed numerous high level CAN Application Layers CALs which extend the capabilities of the CAN while employing the CAN physical layer and the CAN frame format and adhering to the CAN specification CALs have heretofore been implemented primarily in software with very little hardware CAL support Consequently CALs have heretofore required a great deal of host CPU interv
15. MA engine 38 determines that it has reached the top location of that message buffer and that the message being written into that message buffer has not been completely transferred yet the DMA engine 38 will wrap around by generating addresses starting from the base address of that message buffer again Some time before this happens a warning interrupt will be generated so that the user application can take the necessary action to prevent data loss The message handler will keep track of the current address location of the message buffer being written to by the DMA engine 38 and the number of bytes of each CAL message as it is being assembled in the designated message buffer After an End of Message for CAL message is decoded the message handler will finish moving the com plete CAL message and the Byte Count into the designated message buffer via the DMA engine 38 and then generate an interrupt to the XA CPU Core 22 indicating that a complete message has been received Since Data Byte 1 of each CAN Frame contains the fragmentation information it will never be stored in the designated message buffer for that CAN Frame Thus up to seven data bytes of each CAN Frame will be stored After the entire message has been stored the designated message buffer will contain all of the actual informational data bytes received exclusive of fragmentation information bytes plus the Byte Count at location 00 which will contain the total number of
16. a United States Patent Birns US006615302B1 US 6 615 302 B1 Sep 2 2003 10 Patent No 45 Date of Patent 54 5 73 C Q1 Q2 60 G1 52 58 56 USE OF BUFFER SIZE IN CONJUNCTION WITH ADDRESS POINTER TO DETECT BUFFER FULL AND BUFFER ROLLOVER CONDITIONS IN A CAN DEVICE THAT EMPLOYS RECONFIGURABLE MESSAGE BUFFERS Inventor Assignee Notice Appl No Filed Neil Edward Birns Cupertino CA US Koninklijke Philips Electronics N V Eindhoven NL Subject to any disclaimer the term of this patent is extended or adjusted under 35 U S C 154 b by 407 days 09 630 290 Aug 1 2000 Related U S Application Data Provisional application No 60 154 022 filed on Sep 15 1999 Int GO06F 13 14 US CL iue 710 121 365 230 08 Field of Search 710 240 116 710 305 121 709 229 713 502 365 244 5 179 708 5 323 385 5 444 643 A 5 506 966 A 5 627 840 A 5 893 162 230 08 240 711 109 202 700 1 References Cited U S PATENT DOCUMENTS 1 1993 6 1994 8 1995 4 1996 5 1997 4 1999 Gyllstrom et al 709 314 Jurewicz et al 2 Haussler et al 709 229 6 304 908 B1 6 357 014 B1 6 430 164 B1 6 496 885 B1 FOREIGN PATENT DOCUMENTS WO 8806317 A1 10 2001 Kalajan 3 2002 Correia 713 502 8 2002 Jones et al 370 313 12 2002 Smart et al
17. able bandwidth for other tasks so that sys tem performance is greatly enhanced The present invention relates to a scheme employed by the XA C3 microcontroller to handle a message buffer full condition in such a manner that ensures no loss of data while minimizing the required processor intervention More particularly the present invention relates to a particular implementation of this scheme including specific tech niques for detecting the message buffer full condition and for determining the number of data bytes stored in a message buffer SUMMARY OF THE INVENTION present invention encompasses CAN microcontrol ler that supports a plurality of message objects and that includes a processor core that runs CAN applications a plurality of message buffers associated with respective ones of the message objects a CAN CAL module that processes incoming messages that include a plurality of frames each frame having a maximum number n of data bytes and a plurality of message object registers associated with each of the message objects including at least one buffer size register that contains a message buffer size value that specifies the size of the message buffer associated with that message object and at least one buffer location register that contains an address pointer that points to an address of the storage location in the message buffer associated with that message object where the next data byte of the current incoming mes
18. ad those remaining data bytes If option 2 is selected the data bytes already received will remain where they are 1 in the first portion of memory previously designated for that message buffer hereinafter referred to as the first buffer portion Subsequent data bytes of the incoming message will be written into the new message buffer memory space pointed to by the new base address in the associated MnBLR register hereinafter referred to as the second buffer portion The processor core 22 can wait until the entire message is completed 1 until after the final frame is received and stored and then retrieve and process the entire message at once In this case the bottom location of the first buffer portion will identify the number of data bytes stored therein and the bottom location of the second buffer portion will identify the num ber of data bytes stored therein This mechanism makes it extremely easy for the processor to assemble the entire message It will be appreciated by those skilled in the pertinent art that option 2 can be implemented using very few instructions thereby resulting in a much more efficient interrupt service routine As previously described the XA C3 microcontroller 20 permits the user to allocate different amounts of storage area for each of the message buffers by programming the asso ciated MnBSZ registers The amount of storage area reserved for each message buffer is termed its buffer siz
19. age In accordance with the present invention as implemented in the XA C3 microcontroller 20 this problem is solved i e this first requirement is met by defining a message buffer full condition as follows if after a complete frame is received and stored there are less than seven bytes remain ing in the designated message buffer and additional frames are expected for that message the designated message buffer is considered to be full and Rx Buffer Full Interrupt is generated If no additional frames are expected for that message an Rx Message Complete Interrupt is generated instead rationale for this approach is that since a message frame can contain up to seven data bytes there is the potential for the next frame to overflow the message buffer if less than seven byte of storage remain available for message data storage The processor core 22 must intervene at this point to ensure that a buffer overflow does not actually occur The specific mechanism employed by the XA C3 microcontroller 20 to accomplish this scheme will now be described More particularly when a message frame is received by the XA C3 CAN CAL module 77 and passes one of the input acceptance filters it is passed onto the DMA engine 38 DMA access to each of the message buffers 15 achieved US 6 615 302 B1 19 by using the 8 bits stored in the MBXSR register as the 8 MSBs of the address of that message buffer and the 16 bits stored in the MnBLR regis
20. age storage for such FRAG enabled Receive Message Objects will start with the second data byte Data Byte 2 and proceed in the previously described manner until a complete multi frame message has been received and stored in the appropriate message buffer This message storage format is illustrated in FIG 11 The message handler hardware will use the fragmentation infor mation contained in Data Byte 1 of each CAN Frame to facilitate this process Under the CAN protocol if a Message Object is an enabled Receive Message Object and its associated MnCTL 10 15 20 25 30 35 40 45 50 55 60 65 12 register has its FRAG bit set to 1 i e automatic frag mented message assembly is enabled for that particular Receive Message Object then the CAN Frames that match that particular Receive Message Object will be stored sequentially in the message buffer for that particular Receive Message Object using the format shown in FIG 12 When writing message data into a message buffer asso ciated with a Message Object n the DMA engine 38 will generate addresses automatically starting from the base address of that message buffer as specified in the MnBLR register associated with that Message Object n Since the size of that message buffer is specified in the MnBSZ register associated with that Message Object n the DMA engine 38 can determine when it has reached the top location of that message buffer If the D
21. ages of varying lengths without any CPU intervention THE PRESENT INVENTION As described hereinabove each incoming received CAN Frame that passes Acceptance Filtering will be auto matically stored via the engine 38 into the message buffer for the Receive Message Object that particular CAN Frame was found to have matched without interrupting the XA CPU Core 22 Under the CAN protocol if a Message Object is an enabled Receive Message Object and its associated MnCTL register has its FRAG bit set to 1 i e 10 15 20 25 30 35 40 45 50 55 60 65 18 automatic fragmented message assembly is enabled for that particular Receive Message Object then the CAN Frames that match that particular Receive Message Object will be stored sequentially in the message buffer for that particular Receive Message Object using the format shown in FIG 12 When writing message data into a message buffer asso ciated with a Message Object n the DMA engine 38 will generate addresses automatically starting from the base address of that message buffer as specified in the MnBLR register associated with that Message Object n Since the size of that message buffer is specified in the MnBSZ register associated with that Message Object n the DMA engine 38 can determine when it has reached the top location of that message buffer There is no guarantee that an incoming message will not contain more data bytes than ca
22. as set forth in claim 6 wherein each frame of each incoming multi frame message includes a header portion that indicates whether that frame is the last frame in its message 14 The CAN microcontroller as set forth in claim 13 wherein the frame status detection function detects whether the current frame of the current incoming message is the final frame of the current incoming message by deriving that information from the header portion of the current frame of the current incoming message 15 The CAN microcontroller as set forth in claim 14 wherein the CAN CAL module further includes a message complete interrupt generator function that generates a message complete interrupt to the processor core in response to the frame status detection function detecting that the current frame of the current incoming message is the final frame of the current incoming message 16 The CAN microcontroller as set forth in claim 12 wherein the CAN CAL module further includes a message complete interrupt generator function that generates a message complete interrupt to the processor core in response to the frame status detection function detecting that the current frame of the current incoming message is the final frame of the current incoming message 17 The CAN microcontroller as set forth in claim 1 wherein the size of each message buffer is programmable by 10 15 20 25 30 35 40 45 50 55 60 65 26 means of programmi
23. at generates a message buffer full interrupt to the processor core in response to a declaration of a message buffer full condition In the presently preferred embodiment the frame status detection function detects whether the current frame of the current incoming message is the final frame of the current incoming message by deriving that information from the header portion of the current frame of the current incoming message 10 15 20 25 30 35 40 45 50 55 60 65 4 In the presently preferred embodiment the CAN CAL module further includes a message complete interrupt gen erator function that generates a message complete interrupt to the processor core in response to the frame status detec tion function detecting that the current frame of the current incoming message is the final frame of the current incoming message Preferably the size of each message buffer can be selected by the user by programming a selected message buffer size value into the at least one message buffer size register associated with that message buffer and the base address of each message buffer can be selected by the user by pro gramming the address pointer associated with that message buffer to point to a selected base address In the presently preferred embodiment the message buffer full interrupt generator function determines a current byte count that indicates the number of data bytes of the current incoming message that hav
24. be masked bit position s in the appro priate MnMSKH and or MnMSKL registers associated with each particular Message Object n The user is responsible on set up for assigning a unique message buffer location for each Message Object n In particular the user can specify the least significant 16 bits of the base address of the message buffer for each particular Message Object n by programming the MnBLR register associated with that Message Object n The upper 8 bits of the 24 bit address for all Message Objects are specified by the contents of the MBXSR register as previously discussed so that the message buffers for all Message Objects reside within the same 64 KByte memory segment The user is also responsible on set up for specifying the size of the message buffer for each Message Object n In particular the user can specify the size of the message buffer for each particular Message Object n by programming the MnBSZ register associated with that Mes sage Object n The top location of the message buffer for each Message Object n is determined by the size of that message buffer as specified in the corresponding MnBSZ register The user can configure program the MnCTL register associated with each particular Message Object n in order to enable or disable that Message Object n in order to define or designate that Message Object n as a Tx or Rx Message Object in order to enable or disable automatic hardware assembly of fragmented Rx mes
25. buffers at the expense of increased processor intervention to handle more frequent buffer full conditions In the XA C3 microcontroller 20 Direct Memory Access DMA i e the DMA engine 38 is used to enable the XA C3 CAN CAL module 77 to directly access the 32 message buffers without interrupting the XA C3 processor CPU core 22 The XA C3 CAN CAL module 77 uses the values pro grammed into the buffer size registers MnBSZ to reserve the designated number of bytes of storage for each Message Object n For Receive Message Objects this field is also used by logic in the XA C3 CAN CAL module 77 to calculate the total number of bytes that have actually been stored in the message buffers and to identify when a buffer full condition is reached Each time a byte of data is stored in a message buffer associated with a Message Object n the XA C3 CAN CAL module 77 concurrently accesses the MnBSZ and MnBLR registers associated with that Message Object Logic incorporated within the XA C3 CAN CAL module 77 decodes the buffer size for that Message Object and compares the decoded buffer size to the address pointer to determine current byte count and avail able space left in that Message Object s message buffer The present implementation of the XA C3 microcontrol ler 20 requires that all of the 32 message buffers reside within the same 64 Kbyte memory segment or page The user may position the message buffers within any of the 256 pages in the
26. d Message Assembly For Message Objects that have been set up with automatic fragmented message handling enabled 1 with the FRAG bit in the MnCTL register for that Message Object set to 17 masking of the 11 29 bit CAN ID field is disallowed As such the CAN ID of the accepted CAN Frame is known unambiguously and is contained in the MnMIDH and MnMIDL registers associated with the Message Object that has been deemed to constitute a match Therefore there is no need to write the CAN ID of the accepted CAN Frame into the MnMIDH and MnMIDL registers associated with the Message Object that has been deemed to constitute a match As subsequent CAN Frames of a fragmented message are received the new data bytes are appended to the end of the previously received and stored data bytes This process continues until a complete multi frame message has been received and stored in the appropriate message buffer Under CAL protocols DeviceNet CANopen and OSEK if a Message Object is an enabled Receive Message Object and its associated MnCTL register has its FRAG bit set to 1 i e automatic fragmented message assembly is enabled for that particular Receive Message Object then the first data byte Data Byte 1 of each received CAN Frame that matches that particular Receive Message Object will be used to encode fragmentation information only and thus will not be stored in the message buffer for that particular Receive Message Object Thus mess
27. d with the designated receive message object in the storage location corresponding to the initial base address and generates a message buffer full interrupt 29 The CAN microcontroller as set forth in claim 28 wherein the message buffer full interrupt generator function includes a current byte count computation function that determines the current byte count by logically AND ing each of the x LSBs of the retrieved incremented address pointer value with the inverse of the corresponding bit of the buffer size mask 30 The CAN microcontroller as set forth in claim 28 further comprising a data memory space wherein the mes sage buffers are located in the data memory space 31 The CAN microcontroller as set forth in claim 30 wherein a current CAN application running on the processor core in response to the message buffer full interrupt reads the entire contents of the designated receive message buffer and then transfers the read out entire contents to another storage location in the data memory space thereby freeing up the designated receive message buffer to store the at least one remaining frame of the current incoming message 32 The CAN microcontroller as set forth in claim 30 wherein a current CAN application running on the processor core in response to the message buffer full interrupt 5 10 15 20 25 30 35 40 28 removes the currently stored data bytes of the current incoming message from the desi
28. ded in a flame of an incoming message This latter condi tion will hereinafter be referred to as simply the buffer full condition 4 When the frame status detection function within the CAN CAL module 77 determines that the current frame of the incoming message is not the final frame of the current incoming message the message buffer fill detection logic proceeds by logically AND ing the first z ones of the x OR results from step 3 above to produce a second single bit AND result where 2 the maxi mum number of bytes that can be contained in a frame of an incoming message In the present case x is 8 and 718 5 and x z is 3 so that when the second single bit AND result is 1 there are at most 8 1 272 23 bytes of storage area that remain available in the message buffer under consideration Thus a buffer full condition is declared when the second single bit AND result is 1 US 6 615 302 B1 23 In further accordance with the present invention current byte count computation logic within the CAN CAL module 77 computes the total number of bytes stored in a designated receive message buffer by simply logically AND ing each LSB of the address pointer contained in the associated MnBLR register with the inverse of the corresponding bit in the associated buffer size mask i e Byte Count n addr_ pointer n AND NOT mask n where 7 0 in the current specific implementation of the XA C3 microcon troller 2
29. designated receive message object 8 The CAN microcontroller as set forth in claim 7 wherein the buffer status detection function declares a mes sage buffer full condition if the value of the second single bit AND result 15 17 and the current frame of the current incoming message is not the final frame of the current incoming message 9 The CAN microcontroller as set forth in claim 8 wherein the CAN CAL module further includes a message buffer full interrupt generator function that generates a mes sage buffer full interrupt to the processor core in response to a declaration of a message buffer full condition 10 The CAN microcontroller as set forth in claim 6 wherein the CAN CAL module further includes a message buffer full interrupt generator function that generates a mes sage buffer full interrupt to the processor core in response to a declaration of a message buffer full condition 11 The CAN microcontroller as set forth in claim 1 wherein each frame of each incoming multi frame message includes a header portion that indicates whether that frame is the last frame in its message 12 The CAN microcontroller as set forth in claim 11 wherein the frame status detection function detects whether the current frame of the current incoming message is the final frame of the current incoming message by deriving that information from the header portion of the current frame of the current incoming message 13 The CAN microcontroller
30. e US 6 615 302 B1 21 Allowable buffer sizes are binary multiples 1 2 4 8 16 2 256 With the current specific implementation of the XA C3 microcontroller 20 the maximum allowable buffer size is 256 bytes but in general the maximum allowable buffer size can be extended to any other buffer size required or desired for a particular design or application With the current specific implementation of the XA C3 microcon troller 20 the buffer size field in the MnBSZ registers is 3 bit field since there are a total of only 8 allowable buffer Sizes i e 2 4 8 16 32 64 128 or 256 bytes Of course wider fields would be used for designs permitting more allowable buffer sizes As was also previously described the XA C3 microcon troller also permits the user to position each of the message buffers to any desired location within the overall XA C3 data memory space on chip and or off chip subject to one additional constraint which is that all message buffers must be located on a binary boundary for its particular buffer size i e for a 256 byte message buffer the 8 LSBs of the base address of that message buffer specified as the address pointer field in the associated MnBLR register associated with that message buffer must all be zero for a 128 byte message buffer the 7 LSBs of the base address of that message buffer specified as the address pointer field in the associated MnBLR register associated with
31. e already been stored in the message buffer associated with the designated receive message object resets the address pointer contained in the at least one buffer location register associated with the desig nated receive message object to the base address writes the current byte count into the message buffer associated with the designated receive message object in the storage loca tion corresponding to the base address and generates a message buffer full interrupt Preferably the current CAN application running on the processor core is provided with two options as to how to respond to the message buffer full interrupt Under the first option in response to the message buffer full interrupt the current CAN application reads the entire contents of the designated receive message buffer and then transfers the read out entire contents to another storage location in the data memory space thereby freeing up the designated receive message buffer to store the at least one remaining frame of the current incoming message Under the second option the current CAN application in response to the message buffer full interrupt modifies the base address of the designated receive message buffer by replacing the current base address with a new base address whereby the designated receive message buffer consists of a first buffer portion starting with the current base address and a second buffer portion starting with the new base address Preferably the
32. ed address pointer value and the buffer size mask Bain ges Hundertmark et al 714 726 Law et al eee 711 153 37 Claims 7 Drawing Sheets 20 ge i 34 i CORE DATA BUS XA CPU GORE ij PROGRAM BUS 32K BYTES sues ROM EPROM DAT l 1024 BYTES BUS i DATA RAM vanto 27 io EXTERNAL ADDRESS e Se DATABUS 36 i BUS MEMORY MMR BUS i T INTERFACE 53 ae ion TIMERO gt MA TIMER 1 Je i 554 mes f 2 0B Ta 42 i U S Patent Sep 2 2003 Sheet 1 of 7 US 6 615 302 B1 STANDARD Data Field IFS Bus Idle idle 1 bit 14 bits Abit Abit 1 bit 4 bit 0 1 8 Bytes 45 pits DEL f DEL a bits 08 64 015 41 bit 1 bit 11 01 Data Field 0 1 8 Bytes 048 64 bits EXTENDED RemoteTransmitRequest SRR SubstituleRemoteRequest IDE ID Extension r1 10 reserved bits DLC DataLengthCode 0 1 8 IFS InterFrameSpace FIG 1 CAN bus CAL Message B ba Same 8 H UM o BB U S Patent Sep 2 2003 Sheet 2 of 7 US 6 615 302 B1 Van Ou ee eee URS eae D DNA CORE DATA BUS XACPUCORE Ka PROGRAM BUS 32K BYTES SENBUS ROM EPROM m de i DAT 26 1024 BUS DATA RAM UARTO 27 EXTERNAL XRAM ADDRESS eB 2296 SPI DATABUS MEMORY MMR BUS r NAE ae EE 53 32 DMA TIMER 1
33. ention thereby increasing the processing overhead and diminishing the performance of the host CPU Thus there is a need in the art for CAN hardware implementation of CAL functions normally implemented in software in order to offload these tasks from the host CPU to the CAN hardware thereby enabling a great savings in host CPU processing resources and a commensurate improvement in host CPU performance One of the most demanding and CPU resource intensive CAL functions is message management which entails the handling storage and processing of incoming CAL CAN messages received over the CAN serial communications bus and or outgoing CAL CAN messages transmitted over the CAN serial com munications bus CAL protocols such as DeviceNet CANopen and OSEK deliver long messages distributed over many CAN frames which methodology is sometimes referred to as fragmented or segmented messaging The process of assembling such fragmented multi frame mes sages has heretofore required a great deal of host CPU intervention In particular CAL software running on the host CPU actively monitors and manages the buffering and processing of the message data in order to facilitate the assembly of the message fragments or segments into com plete messages Based on the above and foregoing it can be appreciated that there presently exists a need in the art for a hardware implementation of CAL functions normally implemented in software in order t
34. equentially During this process the DMA engine 38 will keep requesting the bus when bus access is granted the DMA engine 38 will sequentially read the transmit message data from the location in the message buffer cur rently pointed to by the address pointer logic and the DMA engine 38 will sequentially write the retrieved transmit message data to the CCB 42 It is noted that when preparing a message for transmission the user application must not include the CAN ID and Frame Information fields in the transmit message data written into the designated message buffer since the Transmit Tx logic will retrieve this information directly from the appropriate MnMIDH MnMIDL and MnMSKH registers The XA C3 microcontroller 20 does not handle the trans mission of fragmented messages in hardware It is the user s responsibility to write each CAN Frame of a fragmented message to the appropriate message buffer enable the asso ciated Transmit Message Object for transmission and wait for a completion before writing the next CAN Frame of that fragmented message to the appropriate message buffer The user application must therefore transmit multiple CAN Frames one at a time until the whole multi frame frag mented transmit message is successfully transmitted However by using multiple Transmit Message Objects whose object numbers increase sequentially and whose CAN IDs have been configured identically several CAN Frames of a fragmented transmit mes
35. ere 2 equals the retrieved message buffer size value in terms of number of bytes and determines a message buffer fullness status of the message buffer associated with the designated receive message object using the retrieved incremented address pointer value and the message buffer size mask In a present implementation the buffer status detection function determines a first buffer fullness state of the mes sage buffer associated with the designated receive message object by logically OR ing each of the x LSBs of the retrieved incremented address pointer value with a corre sponding bit of the buffer size mask to thereby produce x OR results and then logically AND ing the x OR results to thereby produce a first single bit AND result where the first logic state is 0 and the second logic state is 17 A 1 value of the first single bit AND result corresponds to the first buffer fullness state of the message buffer associated with the designated receive message object Also in the present implementation the buffer status detection function determines a second buffer fullness state of the message buffer associated with the designated receive message object by determining whether the number of available bytes of remaining storage capacity in the message buffer associated with the designated receive message object is less than the maximum number n of data bytes using the retrieved incremented address pointer value and the message b
36. f data bytes of the current incoming message that have already been stored in the message buffer associated with the designated receive message object 23 The CAN microcontroller as set forth in claim 22 wherein the current byte count computation function deter mines the current byte count by logically AND ing each of the x LSBs of the retrieved incremented address pointer value with the inverse of the corresponding bit of the buffer size mask 24 The CAN microcontroller as set forth in claim 1 wherein the CAN CAL module further includes an address pointer reset function that logically ANDs each of the x LSBs of the retrieved incremented address pointer value with the corresponding bit of the buffer size mask and writes the resultant value back into the at least one buffer location register associated with the designated receive message object 25 The CAN microcontroller as set forth in claim 1 wherein the CAN CAL module further includes an address pointer reset function that in response to a detection that the current frame of the current incoming message is the final frame of the current incoming message logically ANDs each of the x LSBs of the retrieved incremented address pointer value with the corresponding bit of the buffer size mask and writes the resultant value back into the at least one buffer location register associated with the designated receive message object 26 The CAN microcontroller as set forth in claim 2 where
37. gnated receive message buffer thereby freeing up the designated receive message buffer to store the at least one remaining frame of the current incoming message 33 The CAN microcontroller as set forth in claim 30 wherein a current CAN application running on the processor core in response to the message buffer full interrupt removes the currently stored data bytes of the current incoming message from the designated receive mes sage buffer thereby freeing up the designated receive message buffer to store the at least one remaining frame of the current incoming message and relocates the removed data bytes to a different portion of the data memory space 34 The CAN microcontroller as set forth in claim 28 wherein a current CAN application running on the processor core in response to the message buffer full interrupt modi fies the base address of the designated receive message buffer by replacing the current base address with a new base address wherein the designated receive message buffer is comprised of a first buffer portion starting with the current base address and a second buffer portion starting with the new base address 35 The CAN microcontroller as set forth in claim 34 wherein the CAN CAL module further includes a message complete interrupt generator function that generates a message complete interrupt to the processor core in response to the frame status detection function detecting that the current frame of the c
38. hed In an exemplary implementation the message buffers for all Message Objects are contained in the XRAM 28 Message Assembly In general the DMA engine 38 will transfer each accepted CAN Frame from the 13 byte pre buffer to the appropriate message buffer e g in the XRAM 28 one word at a time starting from the address pointed to by the contents of the MBXSR and MnBLR registers Every time the DMA engine 38 transfers a byte or a word it has to request the bus In this regard the MIF unit 30 arbitrates between accesses from the XA CPU Core 22 and from the DMA engine 38 In general bus arbitration is done on an alternate policy After a DMA bus access the XA CPU Core 22 will be granted bus access if requested After an XA CPU bus access the DMA engine 38 will be granted bus access if requested However a burst access by the XA CPU Core 22 cannot be interrupted by a DMA bus access Once bus access is granted by the MIF unit 30 the DMA engine 38 will write data from the 13 byte pre buffer to the appropriate message buffer location The DMA engine 38 will keep requesting the bus writing message data sequen tially to the appropriate message buffer location until the whole accepted CAN Frame is transferred After the DMA US 6 615 302 B1 11 engine 38 has successfully transferred an accepted CAN Frame to the appropriate message buffer location the con tents of the message buffer will depend upon whether the message that
39. in the CAN CAL module further includes an address pointer reset function that in response to the first message fullness state logically ANDs each of the x LSBs of the retrieved incremented address pointer value with the corre sponding bit of the buffer size mask and writes the resultant value back into the at least one buffer location register associated with the designated receive message object 27 The CAN microcontroller as set forth in claim 3 wherein the CAN CAL module further includes an address US 6 615 302 B1 27 pointer reset function that in response to either the first or second message fullness state logically ANDs each of the x LSBs of the retrieved incremented address pointer value with the corresponding bit of the buffer size mask and writes the resultant value back into the at least one buffer location register associated with the designated receive message object 28 The CAN microcontroller as set forth in claim 10 wherein the message buffer full interrupt generator function determines a current byte count that indicates the number of data bytes of the current incoming message that have already been stored in the message buffer associated with the designated receive message object resets the address pointer contained in the at least one buffer location register associated with the designated receive message object to an initial base address writes the current byte count into the message buffer associate
40. informational data bytes stored It is noted that there are several specific user set up programming procedures that must be followed when invok ing automatic hardware assembly of fragmented OSEK and CANopen messages These and other particulars can be found in the XA C3 CAN Transport Layer Controller User Manual that is part of the parent Provisional Application Serial No 60 154 022 the disclosure of which has been fully incorporated herein for all purposes Transmit Message Objects and the Transmit Process In order to transmit a message the XA application pro gram must first assemble the complete message and store it in the designated message buffer for the appropriate Trans mit Message Object n The message header CAN ID and Frame Information must be written into the MnMIDH MnMIDL and MnMSKH registers associated with that Transmit Message Object n After these steps are completed the XA application is ready to transmit the message To initiate a transmission the object enable bit OBJ bit of the MnCTL register associated with that Transmit Mes sage Object n must be set except when transmitting an Auto Acknowledge Frame in CANopen This will allow this ready to transmit message to participate in the pre arbitration process In this connection if more than one message is ready to be transmitted 1 if more than one Transmit Message Object is enabled a Tx Pre Arbitration US 6 615 302 B1 13 process will be perfo
41. ip to a maximum of 8 KBytes This off chip expansion capability can accommodate up to thirty two 256 Byte message buffers Since the uppermost 8 bits of all message buffer addresses are formed by the contents of the MBXSR register the XRAM 28 and all 32 message buffers must reside in the same 64K Byte data memory segment Since the XA C3 microcontroller 20 only provides address lines 0 19 for accessing external memory all external memory addresses must be within the lowest 1 MByte of address space Therefore if there is external memory in the system into which any of the 32 message buffers will be mapped then all 32 message buffers and the XRAM 28 must also be mapped entirely into that same 64K Byte segment which must be below the 1 MByte address limit After the memory space has been mapped the user can set up or define up to 32 separate Message Objects each of which can be either a Transmit Tx or a Receive Rx Message Object A Rx Message Object can be associated either with a unique CAN ID or with a set of CAN IDs which share certain ID bit fields As previously mentioned each Message Object has its own reserved block of data memory space up to 256 Bytes which is referred to as that Message Object s message buffer As will be seen both the size and the base address of each Message Object s message buffer is programmable As previously mentioned each Message Object is asso ciated with a set of eight MMRs 40 dedicated to tha
42. lete error free CAN frame has been successfully received If it is determined that a complete error free CAN Frame has been successfully received then the CAN CAL module 77 will initiate Acceptance Filtering in order to determine whether to accept and store that CAN Frame or to ignore discard that CAN Frame Acceptance Filtering In general because the XA C3 microcontroller 20 pro vides the user with the ability to program separate Match ID and Mask fields for each of the 32 independent Message Objects on an object by object basis as described previously the Acceptance Filtering process performed by the XA C3 microcontroller 20 can be characterized as a match and mask technique The basic objective of this Acceptance Filtering process is to determine whether a Screener ID field of the received CAN Frame excluding the don t care bits masked by the Mask field for each Message Object matches the Match ID of any enabled one of the 32 Message Objects that has been designated a Receive Mes sage Object If there is a match between the received CAN Frame and more than one Message Object then the received CAN Frame will be deemed to have matched the Message Object with the lowest object number n Message Storage Each incoming received CAN Frame that passes Accep tance Filtering will be automatically stored via the DMA engine 38 into the message buffer for the Receive Message Object that particular CAN Frame was found to have matc
43. message buffer in order to retrieve the current address pointer for the associated Message Object The DMA engine 38 concatenates the 8 MSBs stored in the global Message Buffer Segment Register i e the MBXSR register and the 16 LSBs stored in the MnBLR register for that message buffer to form a complete 24 bit message buffer address The DMA engine 38 then passes this address to the Memory Interface MIF unit 30 along with a flag indicating that the DMA engine 38 requires access to the memory As soon as the current set of XA C3 processor memory accesses are completed the MIF unit 30 will initiate a memory read or write to the address provided by the DMA engine 38 and then permit the DMA engine 38 to perform the required data transfer to from the desired mes sage buffer DMA accesses are typically done two bytes at a time 1 as a 16 bit operation However 8 bit operations are employed when there is only a single byte to be transferred As soon as the requested DMA operation is completed the DMA engine 38 increments the 16 bit address value stored in the MnBLR register associated with that message buffer by one or two depending upon whether a one byte or two byte access was performed and writes this value US 6 615 302 B1 17 back into the MnBLR register for that message buffer Thus the MnBLR registers along with the associated increment logic within the DMA engine 38 effectively function as a set of 32 binary counte
44. mit Message Object the user will be prevented from clearing the EN bit in the MnCTL register associated with that particular Transmit Message Object CAN CAL Related Interrupts The CAN CAL module 77 of the XA C3 microcontroller 20 is presently configured to generate the following five different Event interrupts to the XA CPU Core 22 1 Rx Message Complete 2 Tx Message Complete 3 Rx Buffer Full 4 Message Error 5 Frame Error For single frame messages the Message Complete con dition occurs at the end of the single frame For multi frame fragmented messages the Message Complete condition occurs after the last frame is received and stored Since the XA C3 microcontroller 20 hardware does not recognize or handle fragmentation for transmit messages the Tx Message Complete condition will always be generated at the end of each successfully transmitted frame As previously mentioned there is a control bit associated with each Message Object indicating whether a Message Complete condition should generate an interrupt or just set a Message Complete Status Flag for polling without generating an interrupt This is the INT EN bit in the MnCTL register associated with each Message Object n There are two 16 bit MMRs 40 MCPLH and MCPLL which contain the Message Complete Status Flags for all 32 Message Objects When a Message Complete Tx or Rx condition is detected for a particular Message Object the corresponding bit in
45. n be held by the designated message buffer ie there is no guarantee that the pro grammed buffer size specified in the MnBLR register will be sufficient to hold all frames of the incoming message This will always be the case for messages which exceed the maximum buffer size which in the case of the current version of the XA C3 microcontroller 20 is 256 bytes This buffer full condition can also occur in cases where the length of the expected message can not be predicted in advance of its receipt The user may also elect to conserve memory resources by deliberately specifying smaller buffer sizes at the expense of increased processor intervention to handle more frequent buffer full conditions As previously stated the XA C3 microcontroller 20 is designed to handle a message buffer full condition in such a manner that ensures no loss of data while minimizing the required processor intervention utilizing the following scheme The first requirement for message buffer full handling is that there be no loss of message data Waiting until the designated message buffer actually fills up before interrupt ing the processor core i e the XA CPU Core 22 is too late to ensure no loss of data The DMA operation can not be halted while the processor core 22 responds to a buffer full interrupt data bytes in the currently received frame must be transferred quickly in order to allow the XA C3 CAN CAL module 77 to handle the following incoming mess
46. n the MnBLR register is incremented to the next buffer address The data bytes of the next frame of the incoming message will be written into the designated message buffer starting at this location and 4 An Rx Buffer Full Interrupt is generated XA CPU Core 22 now has a sufficient period of time 1 at least the time required for another complete frame to be transmitted across the CAN bus to take action to free up the message buffer With the XA C3 microcontroller 20 the software is provided with two options as to how to respond to this Rx Buffer Full Interrupt namely 1 Read the entire contents of the message buffer and move them to elsewhere in the data memory thereby freeing up memory space for the remaining frames of the incoming message or 2 Reposition the message buffer for the associated Mes sage Object by modifying its base address in the associated MnBLR register If option 1 is selected the software will read and retrieve the current byte count from the bottom location of the designated message buffer Subsequent data bytes of the incoming message will be written into the designated mes sage buffer at buffer location 1 Once an End of Message condition or another buffer full condition occurs the new byte count reflecting any additional bytes received and stored will be written into buffer location 0 and a new interrupt to the processor core 22 will be generated At that point the software can re
47. nded CAN Frame is also depicted in FIG 1 Acceptance Filtering The process a CAN device imple ments in order to determine if a CAN frame should be accepted or ignored and if accepted to store that frame in pre assigned Message Object Message Object A Receive RAM buffer of pre specified size up to 256 bytes for CAL messages and associated with a particular Acceptance Filter or a Transmit RAM buffer which the User preloads with all necessary data to transmit a complete CAN Data Frame Message Object can be considered to be a communication channel over which a complete message or a succession of messages can be transmitted CAN Arbitration ID An 11 bit Standard CAN 2 0 Frame or 29 bit Extended CAN 2 0B Frame identifier field placed in the CAN Frame Header This ID field is used to arbitrate Frame access to the CAN bus Also used in Acceptance Filtering for CAN Frame reception and Transmit Pre Arbitration Screener ID A 30 bit field extracted from the incoming message which is then used in Acceptance Filtering The Screener ID includes the CAN Arbitration ID and the IDE bit and can include up to 2 Data Bytes These 30 extracted bits are the information qualified by Acceptance Filtering 5 10 15 20 25 30 35 40 45 50 55 60 65 6 Match ID A 30 bit field pre specified by the user to which the incoming Screener ID is compared Individual Match IDs for each of 32 Message Objects are prog
48. ng a selected message buffer size value into the at least one message buffer size register associated with that message buffer 18 The CAN microcontroller as set forth in claim 1 wherein a base address of each message buffer is program mable by means of programming the address pointer asso ciated with that message buffer to point to a selected base address 19 The CAN microcontroller as set forth in claim 1 further comprising a DMA engine that implements the message handling function without interrupting the proces core 20 The CAN microcontroller as set forth in claim 1 further comprising means for selectively enabling each message object as a transmit or receive message object 21 The CAN microcontroller as set forth in claim 20 wherein the CAN CAL module further includes an acceptance filtering function that performs acceptance filtering on each incoming message by comparing a screener field of the incoming message with an acceptance filter field associated with each receive enabled message object the current incoming message is accepted if its screener field matches the acceptance field of a receive enabled message object and the matching receive enabled message object comprises the designated receive message object 22 The CAN microcontroller as set forth in claim 1 wherein the CAN CAL module further includes a current byte count computation function that determines a current byte count that indicates the number o
49. o offload these tasks from the host CPU thereby enabling a great savings in host CPU processing resources and a commensurate improvement in host CPU performance assignee of the present invention has recently devel oped a new microcontroller product designated XA C3 10 15 20 25 40 45 50 55 60 65 2 that fulfills this need in the art The XA C3 is the newest member of the Philips XA eXtended Architecture family of high performance 16 bit single chip microcontrollers It is believed that the XA C3 is the first chip that features hardware CAL support The XA C3 is a CMOS 16 bit CAL CAN 2 0B micro controller that incorporates a number of different inventions including the present invention These inventions include novel techniques and hardware for filtering buffering handling and processing CAL CAN messages including the automatic assembly of multi frame fragmented mes sages with minimal CPU intervention as well as for man aging the storage and retrieval of the message data and the memory resources utilized therefor In particular the XA C3 CAN module has the unique ability to track and reassemble the packets constituting a fragmented message completely in hardware only interrupting the CPU processor core once a complete multi frame message is received and assembled This tremendously reduces the processor band width required for message handling thereby significantly increasing avail
50. orth in claim 1 wherein the buffer status detection function determines a first buffer fullness state of the message buffer associated with the designated receive message object by logically OR ing each of the x LSBs of the retrieved incremented address pointer value with a correspond ing bit of the buffer size mask to thereby produce x OR results and logically AND ing the x OR results to thereby produce a first single bit AND result wherein the first logic state is 0 and the second logic state is 1 and wherein a 1 value of the first single bit AND result corresponds to the first buffer fullness state of the message buffer associated with the designated receive message object 3 The CAN microcontroller as set forth in claim 2 wherein the buffer status detection function determines a second buffer fullness state of the message buffer associated with the designated receive message object by determining whether the number of available bytes of remaining storage capacity in the message buffer associated with the desig nated receive message object is less than the maximum number n of data bytes using the retrieved incremented address pointer value and the message buffer size mask 4 The CAN microcontroller as set forth in claim 3 wherein the buffer status detection function declares a mes sage buffer full condition if the determined number of available bytes 15 less than the maximum number n of data bytes
51. ously mentioned the XA C3 microcontroller 20 automatically implements in hardware many message man agement and other functions that were previously only implemented in software running on the host CPU or not implemented at all including transparent automatic re assembly of up to 32 concurrent interleaved multi frame fragmented CAL messages For each application that is installed to run on the host CPU 1 the XA CPU Core 22 the user software programmer must set up the hard ware for performing these functions by programming certain ones of the MMRs and SFRs in the manner set forth in the XA C3 Functional Specification and XA C3 CAN Transport Layer Controller User Manual The register programming procedures that are most relevant to an understanding of the present invention are described below followed by a 10 15 20 25 30 35 40 45 50 55 60 65 8 description of the various message management and other functions that are automatically performed by the CAL CAN module 77 during operation of the XA C3 microcon troller 20 after it has been properly set up by the user Following these sections a more detailed description of the particular invention to which this application is directed is provided Set up Programming Procedures As an initial matter the user must map the overall XA C3 data memory space as illustrated in FIG 5 In particular subject to certain constraints the user must specif
52. overall XA C3 data memory space 1 256x64 Kbytes 16 Mbytes Programming the locations of the mes sage buffers is accomplished in two steps first step is to program the page number in which all of the message buffers reside into the MMR 40 designated as the MBXSR register which is one of the CCB Registers 10 15 20 25 30 35 40 45 50 55 60 65 16 depicted in FIG 4 As was previously described the con tents of this register are subsequently used as the eight MSBs of address for all DMA accesses to any of the message buffers This register also establishes the memory page in which the XRAM 28 resides The second step is to program the base address 16 bits for each individual message buffer into the MnBLR asso ciated with that message buffer These 16 bit address values initially specified by the user programmer constitute the base addresses of the 32 respective message buffers within the 64 Kbyte memory page specified in the MBXSR register for all message buffers It should be noted that the message buffers can be placed apart from one another as there is no requirement that the message buffer space be continuous 1 that the message buffers reside in physically contiguous locations within the data memory space Further it should also be noted that some or all of the message buffers can be placed in off chip memory and others in the on chip XRAM 28 In the XA C3 microcontroller 20 it i
53. r bits thereof are never modified by the hardware For example in the case of a 32 byte message buffer only the 5 LSBs will ever toggle In further accordance with the present invention message buffer full detection logic within the CAN CAL module 77 detects a message buffer full condition in the following described manner 1 Each time that the address pointer contained in the MnBLR register associated with a Message Object n is incremented by the DMA engine 38 the message buffer full detection logic retrieves the buffer size value from the associated MnBSZ register and decodes that buffer size value into an x bit buffer size mask and also retrieves that address pointer 2 Logically OR ing each of the x LSBs of the retrieved address pointer with a corresponding bit of the x bit buffer size mask to thereby produce x OR results 3 Logically AND ing the x OR results to thereby pro duce a first single bit AND result When the first single bit AND result is 1 the message buffer asso ciated with the Message Object n is actually completely full i e additional data bytes of storage area remain available This condition will herein be referred to as an actual buffer full condition to distinguish it from the previously defined buffer full condition which is that the number of data bytes of storage are that remain available in the message buffer is less than the maxi mum number of bytes that can potentially be inclu
54. rammed by the user into designated Memory Mapped Registers MMRs Mask A 29 bit field pre specified by the user which can override Mask a Match ID comparison at any particular bit or combination of bits in an Acceptance Filter Individual Masks one for each Message Object are programmed by the user in designated MMRs Individual Mask patterns assure that single Receive Objects can Screen for multiple acknowledged CAL CAN Frames and thus minimize the number of Receive Objects that must be dedicated to such lower priority Frames This ability to Mask individual Message Objects is an important new CAL feature CAL CAN Application Layer A generic term for any high level protocol which extends the capabilities of CAN while employing the CAN physical layer and the CAN flame format and which adheres to the CAN specifica tion Among other things CALs permit transmission of Messages which exceed the 8 byte data limit inherent to CAN Frames This is accomplished by dividing each message into multiple packets with each packet being transmitted as a single CAN Frame consisting of a maxi mum of 8 data bytes Such messages are commonly referred to as segmented or fragmented messages The individual CAN Frames constituting a complete fragmented message are not typically transmitted in a contiguous fashion but rather the individual CAN Frames of different unrelated messages are interleaved on the CAN bus as is illustrated in FIG
55. ress range that is upwardly compatible with the 80C51 architecture and that has an operating frequency of up to 30 MHz program or code memory 24 that is currently imple mented as a 32K ROM EPROM and that is bi directionally US 6 615 302 B1 7 coupled to the XA CPU Core 22 via an internal Program bus 25 A map of the code memory space is depicted in FIG 4 a Data RAM 26 internal or scratch pad data memory that is currently implemented as a 1024 Byte portion of the overall XA C3 data memory space and that is bi directionally coupled to the XA CPU Core 22 via an internal DATA bus 27 an on chip message buffer RAM or XRAM 28 that is currently implemented as a 512 Byte portion of the overall XA C3 data memory space which may contain part or all of the CAN CAL Transmit amp Receive Object message buff ers a Memory Interface MIF unit 30 that provides interfaces to generic memory devices such as SRAM DRAM flash ROM and EPROM memory devices via an external address data bus 32 via an internal Core Data bus 34 and via an internal MMR bus 36 engine 38 that provides 32 CAL DMA Channels a plurality of on chip Memory Mapped Registers MMRs 40 that are mapped to the overall XA C3 data memory space a 4K Byte portion of the overall XA C3 data memory space is reserved for MMRs These MMRs include 32 Message Object or Address Pointers and 32 ID Screeners or Match IDs corresponding to the 32 CAL Message Objects
56. rmed to determine which enabled Transmit Message Object will be selected for transmission There are two Tx Pre Arbitration policies which the user can choose between by setting or clearing the Pre Arb bit in the GCTL register After a Tx Message Complete interrupt is generated in response to a determination being made by the message handler that a completed message has been successfully transmitted the Tx Pre Arbitration process is reset and begins again Also if the winning Transmit Message Object subsequently loses arbitration on the CAN bus the Tx Pre Arbitration process gets reset and begins again If there is only one Transmit Message Object whose EN bit is set it will be selected regardless of the Tx Pre Arbitration policy selected Once an enabled Transmit Message Object has been selected for transmission the DMA engine 38 will begin retrieving the transmit message data from the message buffer associated with that Transmit Message Object and will begin transferring the retrieved transmit message data to the CCB 42 for transmission The same DMA engine and address pointer logic is used for message retrieval of trans mit messages as is used for message storage of receive messages as described previously Further message buffer location and size information is specified in the same way as described previously In short when a transmit message is retrieved it will be written by the DMA engine 38 to the CCB 42 s
57. rs Thus at any given time each MnBLR register contains the address which will be used for the next data access to the message buffer associated with the Message Object n In this manner the MnBLR register for each message buffer serves as an address pointer pointer These address pointer fields are also readable at any time by the processor under software control above described approach to message storage also provides an extremely quick and efficient means of freeing up a message buffer when a message completes or when a message buffer is full The software can respond to a message complete interrupt or a buffer full interrupt by simply repositioning the message buffer space for that par ticular Message Object to somewhere else in the message buffer memory space This is accomplished by performing a single write operation to modify the buffer base address specified in the appropriate MnBLR register 1 address pointer This is essentially the extent of a very short interrupt handling routine These interrupts must be handled quickly because the message buffer must be freed up for subsequent message reception Interrupt response is particu larly critical if many completed messages are stacked up and need to be dealt with at once Once this buffer repositioning is accomplished the hardware is immediately ready to receive a new message over that Message Object channel or the continuation of the current message in the ca
58. s required that each message buffer start at a binary boundary for its size 1 the 8 LSBs must be zero for a 256 byte message buffer the 7 LSBs must be zero for a 128 byte message buffer etc DMA access to each of the message buffers is achieved by using the 8 bits stored in the MBXSR register as the 8 MSBs of the address of that message buffer and the 16 bits stored in the MnBLR register for that message buffer as the 16 LSBs of the address of that message buffer The base address initially programmed by the user into the MnBLR register for that message buffer is the address of the first bottom location of that message buffer When the first frame of a new receive message arrives the CAN CAL module 77 hardware writes a semaphore code into this bottom location before beginning to store actual data bytes starting at the next location in that message buffer At the end of the new receive message or when buffer full condition is detected the CAN CAL module 77 hardware computes the total number of bytes actually stored in that message buffer and writes this value into the bottom location of that message buffer The processor i e the XA CPU Core 22 can then read this value and determine precisely how many additional bytes must be read and processed Each time a new byte of data must be written to for receive messages or retrieve from for transmit messages a message buffer the DMA engine 38 reads the MnBLR register for that
59. sage can be queued up and enabled and then transmitted in order To avoid data corruption when transmitting messages there are three possible approaches 1 If the Tx Message Complete interrupt is enabled for the transmit message the user application would write the next transmit message to the designated transmit message buffer upon receipt of the Tx Message Complete interrupt Once the interrupt flag is set it is known for certain that the pending transmit message has already been transmit ted 2 Wait until the EN bit of the MnCTL register of the associated Transmit Message Object clears before writing 10 15 20 25 30 35 40 45 50 55 60 65 14 to the associated transmit message buffer This can be accomplished by polling the bit of the MnCTL register of the associated Transmit Message Object 3 Clear the EN bit of the MnCTL register of the associated Transmit Message Object while that Transmit Message Object is still in Tx Pre Arbitration In the first two cases above the pending transmit message will be transmitted completely before the next transmit message gets transmitted For the third case above the transmit message will not be transmitted Instead a transmit message with new content will enter Tx Pre Arbitration There is an additional mechanism that prevents corruption of a message that is being transmitted In particular if a transmission is ongoing for a Trans
60. sage is to be stored The CAN CAL module includes a message handling function that transfers successive frames of the current incoming message to the message buffer associated with a selected one of the message objects designated as a receive message object for the current incoming message an address pointer increment function that in response to a transfer of the current data byte to the message buffer associated with the designated receive message object increments the address pointer to the address of the storage location in that message buffer where the next data byte of the current incoming message is to be stored The CAN CAL module further includes a frame status detection function that detects whether or not the current frame of the current incoming message is the final frame of the current incoming message The CAN CAL module also includes a buffer status detection function that each time that the address pointer is incremented retrieves the incre US 6 615 302 B1 3 mented address pointer value retrieves the message buffer size value from the at least one buffer size register associated with the designated receive message object and decodes the retrieved message buffer size value into a buffer size mask comprised of a plurality x of bits where x is equal to a prescribed number of allowable buffer sizes and wherein y bits of the buffer size mask have a first logic state and the remaining x y bits have a second logic state wh
61. sages 1 automatic frag mented message handling for that Message Object n in order to enable or disable automatic generation of a Message Complete Interrupt for that Message Object n and in order to enable or not enable that Message Object n for Remote Transmit Request RTR handling In CANopen and OSEK systems the user must also initialize the MnFCR register associated with each Message Object n As previously mentioned on set up the user must con figure program the global GCTL register whose bits control global parameters that apply to all Message Objects 10 15 20 25 30 35 40 45 50 55 60 65 10 In particular the user can configure program the GCTL register in order to specify the high level CAL protocol if any being used e g DeviceNet CANopen or OSEK in order to enable or disable automatic acknowledgment of CANopen Frames CANopen auto acknowledge and in order to specify which of two transmit Tx pre arbitration schemes policies is to be utilized ie either Tx pre arbitration based on CAN ID with the object number being used as a secondary tie breaker or Tx pre arbitration based on object number only Receive Message Objects and the Receive Process During reception i e when an incoming CAN Frame is being received by the XA C3 microcontroller 20 the CAN CAL module 77 will store the incoming CAN Frame in a temporary 13 Byte buffer and determine whether a comp
62. se of a buffer full interrupt The memory space that was previously designated as the message buffer for that Message Object n still contains the previously received message data but this space now becomes just part of the long term data memory space The message information stored in this long term data memory space can then be processed by the software at its leisure This same buffer repositioning technique can be employed for Transmit Messages to facilitate fragmentation Unlike the receive case the XA C3 CAN CAL Module 77 does not automatically assemble fragmented outgoing mes sages It is incumbent upon the software to load a new message frame each time the previous frame is transmitted Using the XA C3 microcontroller 20 message storage scheme however the software can construct an entire fragmented message prior to enabling transmission As each frame is transmitted the processor XA CPU Core 22 only needs to reposition the buffer again using a single write operation to point to the location of the next frame This is much faster than competing devices which require the processor to move up to 13 bytes of data from memory to a dedicated transmit buffer It will be appreciated that with the above described mes sage buffer scheme of the present invention each message buffer can be regarded as a separate FIFO having an inde pendently programmable buffer length which provides a revolutionary approach to storing sequential mess
63. ssage Buffer a23 216 215 20 Buffer size E WR XRAM 512 Bytes 223 416 215 L a7 20 lt _wexsri7ol Dewwer no on xy0000h Segment xy in Data Memory Space NER ES 803 416 419 20 MBXSRIT 0 MnBLR Object n Message Buffer 2722 a a xy0000h FIG 8 Object if XRAM Buffer size 512 Bytes 416 215 a8 a7 20 223 lt MBxSRI7 0 10 ow U S Patent Sep 2 2003 Sheet 6 of 7 US 6 615 302 B1 Object n Match ID Field MnMIDH and MnMIDL Mid28 Mid18 Mid17 Mid10 Mid9 Mid2 MIDE Object n Mask Field MnMSKH and MnMSKL 5 28 18 Msk17 Mski0 Msk9 Msk1 Screener ID Field assembled from incoming bit stream Object n Match ID Field MnMIDH and MnMIDL Mid28 Midi8 Mid17 010 Mid9 MIDE Object n Mask Field MnMSKH and MnMSKL Msk28 Msk18 Msk17 5 10 Msk2 Mski Screener ID Field assembled from incoming bit stream FIG 10 U S Patent Sep 2 2003 Sheet 7 of 7 US 6 615 302 B1 Byte count Data Byte 2 Data Byte 3 Data Byte DLC Data Byte 2 next Data Byte 3 next Frameinfo Data Byte 1 Data Byte 2 Dala ta Byte DLC Framelnfo next Data Byte 1 next Data Byte 2 next FIG 12 DIRECTION OF INCREASING ADDRESS DIRECTION OF INCREASING ADDRESS US 6 615 302 B1 1 USE OF BUFFER SIZE MASK IN CONJUNCTION WITH ADDRESS POINTER TO DETE
64. t Message Object Some of these registers function differently for Tx Message Objects than they do for Rx Message US 6 615 302 B1 9 Objects These eight MMRs 40 are designated Message Object Registers see FIG 4 The names of these eight MMRs 40 1 MnMIDH Message n Match ID High 2 MnMIDL Message n Match ID Low 2 MnMSKH Message n Mask High 4 MnMSKL Message n Mask Low 5 MnCTL Message n Control 6 MnBLR Message n Buffer Location Register 7 MnBSZ Message n Buffer Size 8 MnFCR Message n Fragment Count Register where n ranges from 0 to 31 ie corresponding to 32 independent Message Objects In general the user defines or sets up a Message Object by configuring programming some or all of the eight MMRs dedicated to that Message Object as will be described below Additionally as will be described below the user must configure program the global GCTL register whose bits control global parameters that apply to all Message Objects In particular the user can specify the Match ID value for each Message Object to be compared against the Screener IDs extracted from incoming CAN Frames for Acceptance Filtering The Match ID value for each Message Object n is specified in the MnMIDH and MnMIDL registers associated with that Message Object n The user can mask any Screener ID bits which are not intended to be used in Acceptance Filtering on an object by object basis by writing a logic 17 in the desired to
65. ter for that message buffer as the 16 LSBs of the address of that message buffer The base address initially programmed by the user into the MnBLR register for that message buffer is the address of the first bottom location of that message buffer When the first frame of a new receive message arrives the CAN CAL module 77 hardware writes a semaphore code into this bottom location before beginning to store actual data bytes starting at the next location in that message buffer At the end of the new receive message or when a buffer full condition is detected the CAN CAL module 77 hardware computes the total number of bytes actually stored in that message buffer and writes this value into the bottom location of that message buffer The processor i e the XA CPU Core 22 can then read this value and determine precisely how many additional bytes must be read and processed As soon as the requested DMA operation is completed the DMA engine 38 increments the 16 bit address value stored in the MnBLR register associated with that message buffer by one or two depending upon whether a one byte or two byte access was performed and writes this value back into the MnBLR register for that message buffer Thus the MnBLR registers along with the associated increment logic within the DMA engine 38 effectively function as a set of 32 binary counters Thus at any given time each MnBLR register contains the address which will be used for the ne
66. ternative embodiments implementations of the basic inventive con cepts taught herein which may appear to those skilled in the pertinent art will still fall within the spirit and scope of the present invention as defined in the appended claims What is claimed is 1 A CAN microcontroller that supports a plurality of message objects comprising processor core that runs CAN applications a plurality of message buffers associated with respective ones of the message objects CAN CAL module that processes incoming messages that include a plurality of frames each frame having a maximum number n of data bytes a plurality of message object registers associated with each of the message objects including at least one buffer size register that contains a message buffer size value that specifies the size of the mes sage buffer associated with that message object and at least one buffer location register that contains an address pointer that points to an address of the storage location in the message buffer associated with that message object where the next data byte of the current incoming message is to be stored wherein the CAN CAL module includes a message handling function that transfers successive flames of the current incoming message to the mes sage buffer associated with a selected one of the message objects designated as a receive message object for the current incoming message an address pointer increment function
67. that message buffer must all be zero for a 64 byte message buffer the 6 1 585 of the base address of that message buffer specified as the address pointer field in the associated MnBLR register associated with that message buffer must all be Zero for a 32 byte message buffer the 5 LSBs of the base address of that message buffer specified as the address pointer field in the associated MnBLR register associated with that message buffer must all be zero for a 16 byte message buffer the 4 LSBs of the base address of that message buffer specified as the address pointer field in the associated MnBLR register associated with that message buffer must all be zero for an 8 byte message buffer the 3 1 585 of the base address of that message buffer specified as the address pointer field in the associated MnBLR register associated with that message buffer must all be Zero for a 4 byte message buffer the 2 LSBs of the base address of that message buffer specified as the address pointer field in the associated MnBLR register associated with that message buffer must all be zero and for a 2 byte message buffer the 1 LSB of the base address of that message buffer specified as the address pointer field in the associated MnBLR register associated with that message buffer must all be zero In accordance with the present invention each time that the DMA engine 38 increments the 16 bit address value address pointer stored in
68. the MnBLR register associated with a current receive enabled Message Object the corre sponding buffer size value from the associated MnBSZ register is retrieved and decoded into a buffer size mask In the current specific implementation of the XA C3 micro controller 20 this mask is 8 bits wide because there are 8 allowable buffer sizes as described above The resultant buffer size mask decoding table is as follows BUFFER SIZE BUFFER SIZE MASK 2 bytes 11111110 4 bytes 11111100 8 bytes 11111000 16 bytes 11110000 15 20 25 30 35 40 45 50 55 60 65 22 continued BUFFER SIZE BUFFER SIZE MASK 32 bytes 11100000 64 bytes 11000000 128 bytes 10000000 256 bytes 00000000 As will be readily appreciated by those skilled in the pertinent art the zero bits in the buffer size mask correspond to the bit positions of the LSBs of the address pointer which are required to be set to 07 in order to point to the starting location of a message buffer having the decoded buffer size In generic terms the total number of bits x of the buffer size mask is equal to the number of allowable buffer sizes the number y of bits of the buffer size mask equal to 0 is such that 2 the decoded buffer size value in terms of number of bytes In this connection it will be noted that as the DMA engine 38 increments the address pointer only the y lower order bits or y LSBs thereof are affected as the higher orde
69. uffer size mask Additionally in the present implementation the buffer status detection function determines the second buffer fullness state of the message buffer associated with the designated receive message object by logically AND ing the first z ones of the x OR results to produce a second single bit AND result where 2 2n 1 value of the second single bit AND result corresponds to the second buffer fullness state of the message buffer associated with the designated receive message object Preferably the buffer status detec tion function declares a message buffer full condition if the value of the second single bit AND result is 17 and the current frame of the current incoming message is not the final frame of the current incoming message The CAN CAL module preferably further includes a current byte count computation function that determines the current byte count by logically AND ing each of the x LSBs of the retrieved incremented address pointer value with the inverse of the corresponding bit of the buffer size mask and an address pointer reset function that logically ANDs each of the x LSBs of the retrieved incremented address pointer value with the corresponding bit of the buffer size mask and writes the resultant value back into the at least one buffer location register associated with the designated receive message object The CAN CAL module further includes a message buffer full interrupt generator function th
70. urrent incoming message is the final frame of the current incoming message 36 The CAN microncontroller as set forth in claim 35 wherein the current CAN application running on the pro core in response to the message complete interrupt retrieves a first number of the data bytes of the current incoming message from the first buffer portion and retrieves a second number of the data bytes of the current incoming message from the second buffer portion 37 The CAN microcontroller as set forth in claim 36 wherein the first number comprises the current byte count
71. xt data access to the message buffer associated with the Message Object n In this manner the MnBLR register for each message buffer serves as an address pointer These address pointer fields are also readable at any time by the processor under software control Each time a byte of data is stored in a message buffer associated with a Message Object n the XA C3 CAN CAL module 77 concurrently accesses the MnBSZ and MnBLR registers associated with that Message Object Logic incor porated within the XA C3 CAN CAL module 77 decodes the buffer size for that Message Object and compares the decoded buffer size the value in the associated MnBSZ register to the address pointer i e the current address value in the associated MnBLR register to determine current byte count and available space left in that Message Object s message buffer After the last byte of each frame of the incoming message has been written into the designated message buffer for that message logic within the CAN CAL module 77 checks to determine whether or not this is the final frame of the incoming message This information is derived from an encoded field contained in the header portion of the incom ing message that is transmitted as part of the frame and stored in a flip flop If the received frame is not the final frame of the incoming message then a check must be made for a buffer full condition as defined above This is accom plished by logie within the CAN CAL module
72. y the starting or base address of the XRAM 28 and the starting or base address of the MMRs 40 The base address of the MMRs 40 can be specified by appropriately programming Special Function Registers SFRs MRBL and MRBH The base address of the XRAM 28 can be specified by appro priately programming the MMRs designated MBXSR and XRAMB see FIG 4 user can place the 4 KByte space reserved for MMRs 40 anywhere within the entire 16 Mbyte data memory space supported by the XA architecture other than at the very bottom of the memory space 1 the first 1 KByte portion starting address of 000000h where it would conflict with the on chip Data RAM 26 that serves as the internal or scratch pad memory The 4 KBytes of MMR space will always start at a 4K boundary The reset values for MRBH and MRBL are OFh and FOh respectively Therefore after a reset the MMR space is mapped to the uppermost 4K Bytes of Data Segment OFh but access to the MMRs 40 is disabled The first 512 Bytes offset 000h 1FFh of MMR space are the Message Object Registers eight per Message Object for objects n20 31 as is shown in FIG 6 The base address of the XRAM 28 is determined by the contents of the MMRs designated MBXSR and XRAMB as is shown in FIGS 7 and 8 As previously mentioned the 512 Byte XRAM 28 is where some or all of the 32 Rx Tx message buffers corresponding to Message Objects 0 31 reside The message buffers can be extended off ch

Use of buffer-size mask in conjunction with address pointer to detect

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