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ATOM1 : MC68360 ATM Microcode User`s Manual

1. Transmitter Temporary Storage Empty Cell Empty Cell emporary H Temporary H Receive Data Stuffing Receive Data Stuffing EC storage EC storage ATOM1 status word Receiver Synchronisation Alpha Counter Receiver Synchronisation Delta Counter ATOM1 version number ATOM1 CAM Port Mask Receive Buffer Area Start Pointer Transmit Buffer Page Start Pointer Header Payload Location State area area Non Matching Address Cell Header Non Matching Address Cell Counter HEC Error Counter Receiver Scrambling Storage Receiver Scrambling Storage Transmitter Scrambling Storage Transmitter Scrambling Storage Cell Header Comparison Mask Cell Header Look Up Table Entry 1 Cell Header Look Up Table Entry 2 Cell Header Look Up Table Entry 3 Cell Header Look Up Table Entry 4 Cell Header Look Up Table Entry 5 Cell Header Look Up Table Entry 6 Cell Header Look Up Table Entry 7 Cell Header Look Up Table Entry 8 Cell Header Look Up Table Entry 9 Cell Header Look Up Table Entry 10 Cell Header Look Up Table Entry 11 Cell Header Look Up Table Entry 12 Cell Header Look Up Table
2. ATOM1 ZN ZN UCODE DEMO ATOM1 SRX ATOM1 ATOM1 SRC ATOM1 CMD ATOM1 C ATOM1 X Figure 14 ATOMI Disk Structure 11 MC68360 MASK SET APPLICABILITY ATOM1 microcode operates on revision B or later MC68360s and MC68EN360s Note there are slight differences to the initialisation software for revision B1 and later devices see section 3 1 2 The ATOMI microcode cannot be used in conjunction with the QMC protocol for multi channel operation on an MC68MH360 due to on chip RAM space constraints ATOMI User s Manual 1 0 30 No Restriction on Circulation 12 ORDERING INFORMATION The ATOM1 package contains relocatable ATOM1 object code object code for the QUADS board a User s Manual and demonstration software for the QUADS board ATOMI is available on DOS media by using the following part number M68360SWATM1 DOS PC disk 13 REFERENCES MC68360 User s Manual MC68360UM AD Rev 1 Motorola 1995 ITU 1 432 B ISDN User Network Interface Physical Layer Specification 1991 ATM Forum User Network Interface Specification version 3 0 1993 Draft Recommendation ITU G 804 ATM Cell Mapping into Plesiochronous Digital Hierarchy PDH 1993 5 ITU 1 363 B ISDN ATM Adaptation Layer Specification HON E ATOMI User s Manual 1 0 31 No Restriction on Circulation Appendix 1 STATE MACHINE DETAILS Al 1 ATOM1 Transmitter Figure 15 shows the
3. SCC Base 4 54 RSCRAM Long Receiver Scrambling Storage SCC Base 4 58 RSCRAM1 Long SCC Base 5C TSCRAM Long Transmitter Scrambling Storage SCC Base 60 TSCRAM1 Long SCC Base 64 HEADMASK Long Cell Header Comparison Mask UD SCC Base 68 HEAD1 Long Cell Header Look Up Table Entry 1 UD SCC Base 6C HEAD2 Long Cell Header Look Up Table Entry 2 UD SCC Base 70 HEAD3 Long Cell Header Look Up Table Entry 3 UD SCC Base 74 HEAD4 Long Cell Header Look Up Table Entry 4 UD SCC Base 78 HEAD5 Long Cell Header Look Up Table Entry 5 UD SCC Base 7C HEAD6 Long Cell Header Look Up Table Entry 6 UD SCC Base 80 HEAD7 Long Cell Header Look Up Table Entry 7 UD SCC Base 84 HEAD8 Long Cell Header Look Up Table Entry 8 UD SCC Base 88 HEAD9 Long Cell Header Look Up Table Entry 9 UD SCC Base 8C HEAD10 Long Cell Header Look Up Table Entry 10 UD SCC Base 90 HEAD11 Long Cell Header Look Up Table Entry 11 UD SCC Base 94 HEAD12 Long Cell Header Look Up Table Entry 12 UD SCC Base 98 HEAD13 Long Cell Header Look Up Table Entry 13 UD SCC Base 9C HEAD14 Long Cell Header Look Up Table Entry 14 UD SCC Base A0 HEAD15 Long Cell Header Look Up Table Entry 15 UD SCC Base A4 HEAD16 Long Cell Header Look Up Table Entry 16 UD UD User Defined Table 6 ATOMI SCC Parameter RAM Memory Map 4 0 1 BD Queue Pointers RBASE and TBASE The user configures RBASE and TBASE to define the starting location of the receive and transmit
4. 4 0 6 Transmit and Receive Buffer Queue Start Pointers TX BUFF1 RX BUFF1 The user configures TX BUFF1 and RX BUFFI to define the starting location of the transmit and receive buffer areas in main memory This is the starting address of the 16K byte areas where transmit and receive buffers reside TX BUFF1 and RX BUFF1 must be long word aligned addresses bits 0 and 1 must be zero TX BUFF1 and RX BUFF1 can be dynamically changed provided that care is taken to synchronise the buffer queues held in user software and the queues that the QUICC s CP sees The CPM reads TX BUFF1 and RX BUFFI every time that it opens a data buffer so it is advised that the transmit and receive queues are allowed to empty before TX BUFF1 and RX BUFF1 are changed 4 0 7 Buffer Counters R CNT and T CNT During ATM cell transmission and reception ATOMI uses R CNT and T CNT to count the number of bytes transmitter or received The user must not write to these locations 4 0 8 Receiver Delineation Counters ALPHA and DELTA ATOM1 applies the HEC delineation mechanism described in 1 432 with Alpha 7 and Delta 6 to locate and maintain cell synchronisation During reception ATOM1 updates the ALPHA and DELTA parameter locations and the user must not write to these locations There is no need to initialise these locations 4 0 9 Version Number AVERSION During operation ATOMI writes a version number to AVERSION The current version number stored in AVERSIO
5. PIP gt PBODR 0x0000 Port B open drain register End of config_parallel_ports J CREEK kk kk ko k o o o KK ee kok A AA AA ee kok k k k k kok I I I koe e ex f x QUICC TSA CONFIGURATION amp INITIALISATION I kk ko ko ko k oo k oko ok ok ok ok ok ok ok ko KK k k kk oo kk ee kok k AAA I koe e e ex f ATOMI User s Manual 1 0 44 No Restriction on Circulation Function name config tsa I kk oko oko ko ko k oo k kok kok ee ko kk kk o o ke kk ee ko kk k k k k kok kok I I I He He He He He f Configure Serial Interface and TSA as follows AL JE TDMA used to tx and rx 53 byte ATM cells via SCC1 and SCC2 Common rx and tx clock and synchronisation signals x 5 Tx data on falling clock edges and rx on rising edges Frame sync signal recognised on a rising clock edge x I oko oko ko ko ko k o o k ok kok ee ok kok k k k k o kc kk ko kk ee eA k k k k k okokokokokokokokokokokokok f Input Parameters global data structure SI and pointer SIRAM TA ZA y Output Parameters SI modified I kk kk k ko k o o k oko ok ok kok ko ko ko kk kok k o kk kk ee kok X AA AA I I koe e ex f config tsa int count SI registers SI gt SIGMR 0x00 Disable SI SI gt SIMODE 0x00000058 SI mode register without loopback SI SIMODE 0x00000858 SI mode register with TSA loopback SI gt SICR 0x00004040 SI clock route Clear SI RAM for
6. atil atil atil atil atil atil atil atil atil atil Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le Le ulong uword uword uword uword ulong ulong ulong ulong ulong uword uword uword uword ulong uword uword ulong ulong ulong ulong ulong ulong ulong ulong ulong ulong ulong ulong ulong ulong ulong ulong ulong ulong ulong ulong ulong struct CRC32_calculator volatile volatile volatile Define Pointers to QUICC Registers and SCC Parameter RAM struc struc struc struc struc struc struc struc struc volatile 17 t CP regs Int regs PortA regs t PortC regs t PIP regs t SI regs t SDMA regs SCC regs ATOM1 Params ulong uword ubyte ubyte ulong TTEMP ALPHA DELTA AVERSION CAM PORT RX BUFF1 TX BUFF1 EHEAD EPAYLOAD STUFF UFFLESTAT H HECTEMP HECTEMP Des SEE n A D gt B o O do pops GG p B NE p Ee PP BC gt U ol I Ei Ei bi p Dd Ei pl Dd E ob D b B b bl pd D U Co HEAD16 CRC_PTR CRC_CNT CRC_FC reservedl CRC RESULT CP Intr PortA PortC PIP XSI SDMA SCC1 ATOMI 1 ATOMI User s Manual 1 0
7. section 7 10 21 11 GLT A clock glitch was detected by the SCC on the transmit clock See description of the Transparent Mode SCCE in the MC68360 User s Manual section 7 10 21 11 GLR A clock glitch was detected by the SCC on the receive clock See description of the Transparent Mode SCCE in the MC68360 User s Manual section 7 10 21 11 3 2 4 SCC Mask Register SCCM The SCCM has the same bit definitions as the SCCE and allows the user to mask interrupts Further details are given in the MC68360 User s Manual section 7 10 8 2 ATOMI User s Manual 1 0 11 No Restriction on Circulation 3 2 5 SCC Status Register SCCS The function of the SCCS register is unchanged when ATOM1 uses an SCC 3 3 Serial Interface ATOM1 may use the MC68360 s serial interface SI in any mode although the time division multiplex mode to allows easy connection to E1 and T1 line interface devices This section of the User s Manual concentrates on the TDM interface although use of other serial interfaces is not precluded It is the user s responsibility to ensure that incoming cells are octet aligned with the SI handshake or synchronisation pulses ATOMI will then apply the cell HEC delineation mechanism correctly and synchronise with the incoming cell stream ATOMI can use either of the MC68360 TDM ports Programming information is given here for use of TDM A and can easily be converted for TDM B Further information about the SI is given in the MC68360 U
8. 18 TSTATE Transmitter Internal State use init rx tx SCC Base 20 TBD PTR Transmit BD Pointer command SCC Base 22 T CNT Transmit Internal Byte Counter SCC Base 24 TTEMP Transmitter Temporary Data Storage SCC Base 28 ALPHA Receiver Delineation Alpha Counter SCC Base 2A DELTA Receiver Delineation Delta Counter SCC Base 2C AVERSION ATOM1 Version Number SCC Base 2E CAM PORT CAM Port B Mask SCC Base 30 RX BUFF1 Receive Buffer Area Start Address SCC Base 34 TX BUFF1 Transmit Buffer Area Start Address Empty Cell Header 0000 0000 little endian byte format or 0100 0000 Empty Cell Payload little endian byte format SCC Base 38 EHEAD SCC Base 3C EPAYLOAD 6A6A 6A6A Receive Data Stuffing Location 53 SCC Base 40 RSTUFF Long to 52 byte conversion SCC Base 44 SHUFFLESTATE Word Receiver Data Shuffling State 0000 SCC Base 46 RHECTEMP Word Temporary HEC Storage SCC Base 48 THECTEMP Word Temporary HEC storage area SCC Base 4A ASTATUS Word ATOM1 status word 0000 SCC Base 4C NMA HEAD Long Non Matching Address Cell Header SCC Base 50 NMA CNT Word Non Matching Address Cell Counter 0000 SCC Base 52 HEC ERR Word HEC Error Counter 0000 Table 6 ATOMI SCC Parameter RAM Memory Map ATOMI User s Manual 1 0 14 No Restriction on Circulation Address Name Width Description User Writes hex
9. ATM cell Receive buffers may be scattered around a 16K byte area of memory but each buffer must start on a long word aligned address If the start address of a buffer is at the very end of the 16K byte area for example the BD is programmed with 8FFF then the end of the received cell will be 48 bytes outside of the 16K byte area When the user prepares an empty receive BD the address pointer to the start of the data buffer must be written into the BD When the Empty bit is set ownership if the BD is handed over from the user to the QUICC s CP and the user must not modify any part of the BD Once a cell is received and ATOMI returns the BD and buffer to the user the address pointer field is replaced with OAM and error status flags and the HEC of the incoming cell User software must maintain a copy of the address pointer for each receive BD in the receive queue 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E W l A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Empty Receive BD as Written by User E 7 W 5 OAM ERR HEC Used Receive BD after reception of a Cell Figure 9 ATOMI Receive Buffer Descriptor E Empty Control bit set by the user to indicate that the associated buffer is empty and ATOM1 can receive a cell into it W Wrap Control bit set by the user to wrap the receive BD queue after this BD I Interrupt Control bit set by the user When a cell is received into the buffer associated with this BD a re
10. IR All are made ready and the wrap bit in tenth BD is set pe The first nine buffers are actually in contiguous memory starting at the Z5 begining of the receive buffer area The tenth buffer at the end of the x receive buffer area Ey for count 0 count MAXBUFF count BD init ARXBD count NO YES O RXBUFF RXBUFF count 52 BD init ARXBD MAXBUFF NO YES YES RXBUFF RXBUFF Ox3ffc Clear receive buffer area for bytecnt 0 bytecnt MAXBUFF BUFFSIZE bytecnt ARXBuff bytecnt 0 Clear and set up ten transmit BDs x All are made ready and the wrap bit in tenth BD is set x JE The first nine buffers are actually in contiguous memory starting at the i begining of the transmit buffer area The tenth buffer at the end of the transmit buffer area Kp for count 0 count lt MAXBUFF count BD init ATXBD count NO YES NO TXBUFF TXBUFF count 52 BD init ATXBD MAXBUFF NO YES YES TXBUFF TXBUFF Ox3ffc ATOMI User s Manual 1 0 41 No Restriction on Circulation Fill transmit buffer area with ascending numbers dataval 1 for bytecnt 0 bytecnt MAXBUFF BUFFSIZE bytecnt ATXBuff bytecnt datavalt Initialisation is complete so enable SCC1 for ATM Reception SCC1 gt GSMRL 0x00000030 SCC1 Enabled Initialise the CRC 32 calculator and perform one s
11. L1IRXDA PA7 Receive data input x LIRSYNCA PC11 Synchronisation input y LIRCLKA PA8 Clock input x L1ST1 PB12 TSA strobe output x L1ST2 PB13 TSA strobe output L1ST3 PB14 TSA strobe output hV L1ST4 PB15 TSA strobe output x SDACK1 PC10 SDMA cycle output K yes SDACK2 PC8 SDMA cycle output PA15 PA15 CRC 32 PIO output pin for software use X 5 BRGO3 PB16 BRG3 Output Signal J CREEK oko oko kk k k k o o ok kok oko ko ko ko ko kk Ck kk ke ke kk kk ee kok X AAA I koe ee ex f Input Parameters global data structures PIP PortA and PortC A JA XU Output Parameters PIP PortA and PortC modified y I ko ko kk k k o o k kk kk A A k k o k o ooo ok oko ke kok AAA AA I I ee e ex f config parallel ports PIP gt PIPC 0x0000 i PIP configuration register PortA gt PADAT 0x0000 Port A data register PortA gt PADIR 0x80c0 Port A data direction register PortA gt PAPAR 0x01c0 Port A pin assignment register PortA gt PAODR 0x0000 Port A open drain register PortC gt PCDIR 0x0500 Port C data direction register PortC gt PCPAR 0x0d00 Port C pin assignment register PortC gt PCSO 0x0000 Port C secial option register PortC gt PCINT 0x0000 Port C interrupt control register PIP gt PBDIR 0x00010000 Port B data direction register PIP gt PBPAR 0x0001f000 Port B pin assignment register
12. Mj MOTOROLA ATOMI MC68360 ATM Microcode User s Manual Document Reference Version Comments Release date 0 1 First Release 18th Aug 1994 0 2 Updated User s Manual 1st Nov 1994 1 0 Updated for CRC 32 and buffer scattering 21st March 1996 Motorola reserves the right to make changes without further notice to any product herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product circuit or software described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such intended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or man
13. Note the value programmed into CPCR4 depends on the QUICC device version used Address Name Description User Writes hex REGB 5CC CPCR1 CP Control Register 1 8056 REGB 5CE CPCR2 CP Control Register 2 8076 REGB 5D0 CPCR3 CP Control Register 3 8036 8E18 rev B1 MC68360 REGB 5D2 CPCR4 CP Control Register 4 8818 rev B2 B3 B4 CO C1 and E MC68360s Table 1 CP Control Registers ATOMI User s Manual 1 0 9 No Restriction on Circulation 3 2 SCC Registers ATOM1 operates using an SCC and is enabled in the SCC s General SCC Mode Register GSMR The clock source is configured in the serial interface registers see section 3 3 1 3 2 1 General SCC Mode Register GSMR ATOM1 requires the following bits to be set in the GSMR TRX TTX CDP CTSP CDS and CTSS To enable ATOM1 s transmit and receive functions the ENT and ENR bits must be set when the initialisation sequence has been completed Full GSMR details are given in the MC68360 User s Manual section 7 10 2 Additionally the REVD bit in the GSMR bit 45 changes function to become the CAM control bit when ATOM1 is running CAM 0 Use the internal address table for address matching 1 Use the external CAM for address matching To enable an SCC to run ATOMI the SCC must be in transparent mode and have MRBLR 0 When MRBLR is programmed with a non zero value the SCC operates in transparent mode Mixed mode operation of an SCC where the
14. OUICC 0x1560 PIP struct PIP regs OUICC 0x16b2 ST struct SI_regs OUICC 0x16e0 SDMA struct SDMA_regs QUICC 0x15le sl struct SCC regs OUICC 0x1600 ATOM1 1 struct ATOM1 Params OUICC 0x0c00 CRC32 struct CRC32 calculator QUICC 0x0db0 SIRAM uword OUICC 0x1700 BRGC3 ulong OUICC 0x15f8 ATXBD uword ATXBDO ARXBD uword ARXBDO ATXBuff ubyte TXBUFF ARXBuff ubyte RXBUFF BDSpace uword BDArea Configure QUICC Parallel Ports config parallel ports Reset QUICC CPM CP gt RCCR CP gt CR 0 0x8001 xy Clear RCCR Reset CPM Configure BRG3 for external use BRGC3 0x0001000a ATOMI User s Manual 1 0 BRG3 40 4 17MHz clock at 25MHz No Restriction on Circulation Configure SDMA SDMA gt SDCR 0x0740 SDMA configuration register Configure Serial Interface and TSA config tsa Disable all interrupts Intr CIMR 0 Initialise and enable RAM microcode config ucode Configure SCC1 for ATOM1 atom init SCC1 ATOM1 1 CP gt CR 0x0001 Initialise SCC1 rx and tx parameters Configure ATOMI Data Buffers amp Buffer Descriptors Clear out the whole BD area for count 0 count MAXBDAREA count BDSpace count 0 Clear and set up ten empty receive BDs x
15. and receive scrambling mechanism is independent of the cell s virtual connection The seed value for the scrambling algorithm for a particular cell is obtained from the 43 cell payload bits transmitted or received immediately prior to the current cell Two consecutive cells may be from different connections and scrambling mechanism ignores this Al1 3 ATOM1 Receiver Figure 17 shows the ATOMI receiver procedure After start up when MRBLR is zero the HEC delineation procedure begins see below Once complete cell reception commences For each cell received the HEC is checked and if incorrect the cell is usually received It is not received only when the receiver losses cell delineation In the cell is an empty cell the payload is discarded If there is a header match using internal the header lookup table then the cell payload is received When the external CAM option is enabled the cell is received before the CAM match is checked Operation continues in this manner until the Restart Reception command or a FIFO overrun error occurs or the user disables the SCC receiver Received cells may have their payloads descrambled as described earlier A1 4 HEC Delineation Mechanism ATOMI applies the cell delineation mechanism specified in 1 432 and shown in Figure 18 to synchronise to the incoming cell stream The SDH based physical layer values for alpha and delta 7 and 6 respectively are used by ATOMI At start up the hunt mode is entered wher
16. channel number to the QUICC s Command Register CR The op codes for the initialisation Stop Transmit and Restart Transmit command are the same as for the QUICC s other protocols The op code for the Restart Reception command is and the CRC 32 calculator 1111 All other bits in the CR remain unchanged Command execution latency for the initialisation Stop Transmit and Restart Transmit command are the same as for the QUICC s other protocols The Restart Reception command is executed when the current cell being received is complete and execution time therefore depends on the data rate and when the command is given For all commands ATOMI clears the FLG bit in the CR to indicate completion of the command 5 1 Restart Reception Command The Restart Reception Command is similar to Enter Hunt Mode If ATOM1 is currently receiving an empty cell cell delineation is immediately lost and the resynchronisation process begins If the current cell being received is a data or control cell being received or discarded by ATOM T the current buffer is closed and cell delineation is lost at the end of the cell The Enter Hunt Mode command should not be used with ATOMI To restart the receiver immediately regardless of the current state the Init Rx Parameter command can be used The Restart Reception Command and the CRC 32 Calculator share the same op code in the command register To issue a Restart Reception Command the user must ensure that the cu
17. kok k k k k ko kk kk ee ko k kok AA AA I I koe e ex f Input Parameters Pointers to the SCC register SCC parameter x RAM and CP register data structures x Le Accesses global data structure CP EVA VE Output Parameters CP modified JE ep J CREEK A k ko RAK ee ok kok A AAA ee kok k k k k oko I I I He He ee xe x f atom_init SCC ATOM struct SCC_regs BUS jE struct ATOM1 Params ATOM SCC registers SCC gt GSMRL 0 SCC Disabled SCC gt GSMRH 0x00001F80 Set sync and transparent bits SCC gt PSMR 0x2100 Enable scrambling and HEC coset SCC PSMR 0 Disable scrambling and HEC coset SCC SCC 0 Mask out interrupts SCC gt SCCE Oxffff Clear SCC event register Configure SCC parameter RAM for ATOM1 ATOM gt RBASE ARXBDO QUICC Rx BD Base Address ATOM gt TBASE ATXBDO QUICC Tx BD Base Address ATOM gt RFCR 0x18 SDMA Rx Function Code ATOM gt TFCR 0x19 SDMA Tx Function Code ATOMI User s Manual 1 0 46 No Restriction on Circulation ATOM gt MRBLR 0 Transparent Receiver Max Buffer Length ATOM
18. of ATM cells that are not delay sensitive while the voice transmission circuit has less traffic but must be serviced at regular intervals The mixed voice and data example is used here to illustrate the bandwidth reservation system In most systems the number of transmit and receive buffer descriptors and buffers per SCC is fixed when the system software is designed For example the ATOMI transmit queue may be fixed at ten buffers The data transmission software can maintain its own software queue that may hold several hundred cells The voice task must transmit each cell as soon as it is generated and not store them in a queue If the voice cells were to be placed at the end of the software data transmission queue the latency would be too high The transmit bandwidth reservation system avoids this problem by allowing selected BDs to be reserved for the voice transmission When ten BDs are allocated to the data and voice transmission software tasks nine can be assigned for data and one for voice This reserves 10 of the transmission bandwidth for voice channels The reservation mechanism uses the Skip bit in the transmit BD As ATOM1 processes the transmit BD queue it transmits cells where the Skip bit is zero When a BD with the Skip is encountered it is skipped and an empty cell is transmitted in its place In the mixed data and voice example the data transmission software can control nine of the ten BDs and set their Ready bits to initi
19. provide synchronisation signals to the QUICC and octet align incoming cells to the synchronisation signals ATOM1 provide SDH PDH oriented cell delineation using the HEC mechanism defined in 1 432 on an octet basis The synchronisation signals need not delimit the start of cell but must be octet aligned with incoming cells When using E1 and T1 ATM links the cells are always octet aligned see ITU G 804 and synchronisation signals are provided by the E1 and T1 interface devices ATOMI User s Manual 1 0 7 No Restriction on Circulation When reception commences ATOM I takes a short while to acquire correct cell delineation Once ATOM1 has locked to the incoming cell stream it remains locked unless there are excessive errors An interrupt is generated whenever the cell lock status changes and a status bit will indicate the current delineation status Further details of the cell delineation mechanism are given in Appendix A 2 38 AAL Frame Check Sequences To increase software throughput of AAL5 frames a CRC 32 calculator is included This is not an integral part of the cell transmission and reception process in order that CRC 32 sequences may be calculated across long AAL5 frames made up of interleaved ATM cells The CRC 32 calculator is a command which ATOMI interprets by working through a data buffer generating the required CRC 32 sequence 2 4 PDH amp SDH Physical Layer Signalling amp OAM Functions PDH and SDH framing physical lay
20. time ATOMI User s Manual 1 0 17 No Restriction on Circulation 4 0 15 Incoming Header Mask and Look up Table HEADMASK and HEADn When the CAM option is disabled ATOM1 masks the header of each incoming cell with HEADMASK and then searches for the result in the HEADn table When a match is found the cell is received otherwise the cell header is logged in NMA HEAD and the remainder of the cell is discarded The HEADMASK masking process uses a bitwise AND function so bits can be masked out by clearing the relevant bit in HEADMASK The bit locations for HEADMASK are shown in Figure 6 Bit 0 must always be written with zero 31 28 27 20 19 4 3 1 0 GFC VPI VCI PT 0 Figure 6 HEADMASK The result of the masking is then compared with each of the HEADn values starting with HEAD1 Although sixteen locations are shown in the HEADn table the user may define fewer The final location in the table is denoted with the Last bit being set When multiple HEADn locations are being used the user should take care because the look up table can overlap other peripheral areas in memory see the MC68360 User s Manual section 3 2 for further details If the look up table is extended to overlap other peripheral s parameter RAM areas the other peripherals cannot be used The bit locations for the HEADn locations are shown in Figure 7 Bit 0 should be written with zero except for the last entry in the table 31 28 27 20 19 4 3 1 0 GF
21. 0 pe ES C HE EC E KE A B O EXER ER ERES EC z 3 Figure 5 ASTATUS Bits in the upper byte is set by ATOMI and cleared by the user Bits in the lower byte are set and cleared by ATOMI During initialisation the user must clear all bits in ASTATUS During operation the user can read and clear write zero to the upper byte but must only read the lower byte FIFO overruns and underruns are reported in the SCCE FIFO bit and further information is given in the ORUN and URUN bits ORUN 0 No Receiver FIFO Overrun 1 Receiver FIFO Overrun URUN 0 No transmitter FIFO underrun 1 Transmitter FIFO underrun Each change in state of the receiver cell delineation is reported in the SCCE SYNC bit The LOCK bit shows the current delineation status LOCK 0 The ATOM receiver is out of synchronisation and is not receiving cells 1 The ATOM receiver has gained cell delineation and is receiving cells 4 0 13 Non Matching Header Storage and Counter NMA HEAD and NMA CNT When a cell is received with a non matching header the header minus the HEC is written to NMA HEAD NMA CNT is incremented and the NMA bit set in the SCCE NMA HEAD isa location where headers from non matching cells are logged and NMA CNT is a counter of non matching cells The user is free to read and clear NMA CNT at any time 4 0 14 HEC Error Counter HEC ERR HEC ERR is a 16 bit counter of incoming cells with HEC errors The user is free to read and clear HEC ERR at any
22. 1 2 ATOM1 Scrambling 1 12 note 1 52 72 us 3 ATM SCC1 2 3 ATOM1 No Scrambling 1 12 note 1 52 76 us 3 ATM SCC1 2 3 ATOM1 No Scrambling 1 25 note 2 23 30 us 3 ATM SCC1 2 3 ATOM1 Scrambling 1 25 note 2 27 52 us 4 ATM SCC1 2 3 4 ATOM1 No Scrambling 1 25 note 2 26 34 us 4 ATM SCC1 2 3 4 ATOM1 Scrambling 1 25 note 2 40 65 us Notes 1 A frequency ratio of 1 12 equates to 2 083 MHz at 25 MHz 2 A frequency ratio of 1 25 equates to 1 MHz at 25 MHz Table 10 CRC 32 Calculator Performance 1 The experimental Ethernet data rate was 5 Mbps full duplex which equates to 10 Mbps on a conventional half duplex Ethernet system ATOMI User s Manual 1 0 29 No Restriction on Circulation 10 ATOMI DISK STRUCTURE ATOMI is shipped on a PC format disk Figure 14 shows the disk structure The microcode is held in the UCODE directory and demonstration software is stored in the DEMO directory ATOM1 SRX is the S record microcode file for the QUADS board memory map ATOMI SRC is an M68000 assembly code file for the ATOM1 microcode that can be assembled and linked to any system memory map The file ATOMI C contains the C source code for the initialisation and ping pong demonstration software given in Appendix B ATOM1 and ATOM1 CMD are the makefiles for the C demonstration software and ATOM1 X is the S record file of the demonstration software ready to download to a QUADS board
23. ATOM transmitter procedure After start up when MRBLR is zero an empty cell is transmitted before the first transmit BD is polled If the BD has the Skip bit set an empty cell is transmitted and the transmitter moves to the next BD If the BD is ready a user defined ATM cell is transmitted otherwise another empty cell is transmitted Operation continues in this manner until the Stop Transmit command or a FIFO underrun error occurs of the user disables the SCC transmitter The transmitted cells may have their payloads scrambled as described below Goto Transparent Mode ROM Microcode MRBLR 0 Y es Dial Transmit Empty Transmit Data uA y Cell Header Cell Header Transmit Data Cell Calculate Data Cell HEC Calculate Empty Cell HEC Transmit HEC Byte Transmit Transmit Data Cell Payload Transmit Empty Cell Payload Yes Skip Next BD No Data Cell Ready Figure 15 ATOM1 Transmitter Procedure ATOMI User s Manual 1 0 32 No Restriction on Circulation A1 2 ATM Cell Payload Scrambling ATOM1 provides a scrambling option on a per line basis for cell payload bytes using the polynomial X 1 Figure 16 illustrates the payload transmitter and receiver scrambling mechanism used by ATOMI Transmit Data Receive Data 43 Bit Delay 43 Bit Delay Transmitter Receiver Figure 16 ATM Cell Payload Scrambling Mechanism The context of the transmit
24. ATOM1 1 12 channel SCC1 Scrambling note 1 SCC2 3 4 HDLC 1 9 25 MHz ATOM1 1 390 33 MHz 3 HDLC SCC1 1 3 5 SCC2 3 4 HDLC channels No Scrambling note 2 SCC ATOMI 15 SCC2 34 HDLC P Scrambling note 2 ATM sco t Ho 1 6 SCC2 Ethernet 1 2 5 1 Ethernet ATOMI 25 MHz channel SCC1 1 7 SCC2 Ethernet 1 2 5 Scrambling 1 ATM SCC ATOM1 1 12 SCC2 Ethernet 1 2 5 1 Ethernet No Scrambling note 1 SCC3 HDLC 14 1 HDLC o ATOM1 1 12 SCC2 Ethernet 1 2 5 channel Scrambling note 1 SCC3 HDLC 15 1 ATM SCC1 No S 1 3 5 SCC2 Ethernet 1 3 3 1 Ethernet m P o I eT 33 MHz channel SCC1 1 4 SCC2 Ethernet 133 Scrambling 1 ATM SCC ATOM1 1 16 SCC2 Ethernet 1 3 3 1 Ethernet No Scrambling note 3 SCC3 HDLC 1 4 rte 1 HDLC me ATOM1 1 16 SCC2 Ethernet 1 3 3 channel Scrambling note 3 SCC3 HDLC 15 Notes 1 A frequency ratio of 1 12 equates to 2 048 MHz at 25 MHz 2 A frequency ratio of 1 390 equates to 64 KHz at 25 MHz 3 A frequency ratio of 1 16 equates to 2 048 MHz at 33 MHz Table 9 ATOMI and other Protocol Performance ATOMI User s Manual 1 0 28 No Restriction on Circulation This data traffic in the experiments represents typical worst case scenarios for real life applications where QUICC data structures were organised to maximise performance All frames were restricted to single buffers that were aligned to long word addresses and receive frame address comparisons were disabled The Ethernet figures quoted in Table 8 are for half dup
25. BD queues in the dual port RAM Further information is given in the MC68360 User s Manual section 7 10 7 1 4 0 2 SCC Function Code Registers RFCR and TFCR The user configures RFCR and TFCR to define the SDMA function code pin settings during SDMA transfers Further information is given in the MC68360 User s Manual section 7 10 7 2 4 0 3 Transparent Mode Receive Maximum Buffer Length MRBLR To run ATOMI on an SCC the user must program that SCC s MRBLR to zero When MRBLR is programmed with a non zero value the SCC operates in transparent mode as described in the MC68360 User s Manual section 7 10 21 4 0 4 SCC Internal State Parameters RSTATE and TSTATE ATOM1 uses RSTATE and TSTATE to store internal state variables and flags during operation The user must not write to these locations ATOMI User s Manual 1 0 15 No Restriction on Circulation 4 0 5 BD and Buffer Pointers R PTR RBD PTR T PTR and TBD PTR During cell transmission and reception ATOMI uses R PTR RBD PTR T PTR and TBD PTR as pointers to the current BD and data locations RBD PTR and TBD PTR point to the current or next BD to use and need to be initialized with the Init Rx Tx command to point to the locations given in RBASE and TBASE R PTR and T PTR point to the next data location in memory When ATOM1 is operating these locations should not be written by the user Further information is given in the MC68360 User s Manual sections 7 10 7 4 and 7 10 7 5
26. C VPI VCI PT Last Figure 7 HEADn ATOMI searches the HEADn table sequentially so the headers for the most frequently connections should be at the beginning of the table 4 0 16 Temporary Data Storage During ATM cell transmission and reception ATOM1 uses RTEMP TTEMP RSTUFF RHECTEMP THECTEMP RSCRAM RSCRAMI TSCRAM and TSCRAMI to store temporary data This data is for internal use and the user must not write to these locations 5 ATOM1 COMMANDS The following commands are understood by ATOM1 e Initialise Receiver and Transmitter Parameters e Initialise Receiver Parameters ATOMI User s Manual 1 0 18 No Restriction on Circulation e Initialise Transmitter Parameters e Stop Transmit Restart Transmit Restart Reception e CRC 32 Calculator Execution of other SCC commands may cause errant behaviour All commands are given through the Command Register and operate as with other protocols except Restart Reception The ATOM1 commands to initialise the receiver and transmitter parameters operate the same as for other SCC protocols If the initialisation commands are given during cell transmission and reception cell synchronisation will be lost The Stop Transmit Command stops cell transmission immediately and the transmit line goes high To stop transmission of data cells but continue with empty cells the user must wait for the transmit BD queue to empty The commands are run by writing the command and
27. Entry 13 Cell Header Look Up Table Entry 14 Cell Header Look Up Table Entry 15 Cell Header Look Up Table Entry 16 CRC 32 calculator pointer CRC 32 calculator CRC 32 calculator CRC 32 calculator 39 counter register Function Code preset and result register No Restriction on Circulation struct CRC32 calculator CRC32 SIRAM BRGC3 BDSpace ATXBD ARXBD ATXBuff ARXBuff uword ulong uword uword uword ubyte ubyte main Local Variables int buffnum int bytecnt int count char dataval int txcount int pperror xy 0 0 General buffer counting variable 32 bit General byte counting variable General counting variable 32 bit Pointer to 256 bytes of SI routing RAM Baud Rate Generator Pointer to start of Pointer to ATOMI Pointer to ATOMI x Rx Pointer to ATOMI Pointer to ATOMI x Rx 3 6 256 BD BD dat dat ontrol register byte BD space Queue Queue a queue a queue 32 bit un Ef General 8 bit data value rxcount 0 Ping pong error flag Initialise Memory Pointers Ping Pong receive and transmit cell counters CP struct CP regs QUICC 0x15c0 Intr struct Int regs OUICC 0x1540 PortA struct PortA regs OUICC 0x1550 PortC struct PortC regs
28. N is 0001 4 0 10 CAM Port Selection CAM PORT When the CAM interface is enabled the user should set one or more bits in CAM PORT to select which of the OUICC s Port B pins is the match input or inputs for this SCC Bit 0 of CAM PORT corresponds to PBO bit 1 to PB1 etc 4 0 11 Empty Cell Data EHEAD and EPAYLOAD ATOM1 transmits and receives empty cells using EHEAD and EPAYLOAD On transmission an empty cell is made up by transmitting EHEAD once calculating and transmitting a HEC and transmitting EPAYLOAD twelve times On reception the incoming header is compared with EHEAD to check for empty cells and EPAYLOAD is not used ATOMI User s Manual 1 0 16 No Restriction on Circulation The user is free to select whatever empty cell header and payload values are required the ATM Forum UNI Specification states that unassigned cells should be transmitted while the ITU mandates use of idle cells The user must write the EHEAD and EPAYLOAD parameters as required and these two locations must be written in little endian byte order Unassigned cells are used as empty cells when EHEAD 0000 0000 and idle cells when EHEAD 0100 0000 In both cases EPAYLOAD should be initialised to 6A6A 6A64A 4 0 12 Status Information ASTATUS The ATOM1 Status parameter provides the user with additional status information concerning FIFO errors and receiver synchronisation status ASTATUS is shown in Figure 5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
29. Rx A 1 2042 L1ST4 Receive one byte HEC field RxA2 007E Receive first sixteen bytes of cell payload Table 3 Serial Interface RAM Programming Example ATOMI User s Manual 1 0 12 No Restriction on Circulation SI RAM Entry User Writes hex Strobe Asserted Remarks RxA3 007E Receive second sixteen bytes of cell payload RxA4 007F Receive final sixteen bytes of cell payload TxAO 044E L1ST1 Transmit four bytes of cell header Tx A 1 0842 L1ST2 Transmit one byte HEC field Tx A2 007E Transmit first sixteen bytes of cell payload TxA3 007E Transmit second sixteen bytes of cell payload TxA4 007F Transmit final sixteen bytes of cell payload Table 3 Serial Interface RAM Programming Example 3 4 Parallel Port Registers For ATOM1 operation over TDM A the MC68360 parallel port pins should be set up to interface to external signals as shown in Table 4 The TSA strobes and SDMA Acknowledge pins are shown and common receive and transmit clocks are used Signal Pin Direction L1TXDA PA6 Output L1RXDA PA7 Input L1RSYNCA PC11 Input L1RCLKA PA8 Input L1ST1 PB12 Output L1ST2 PB13 Output L1ST3 PB14 Output L1ST4 PB15 Output SDACK1 PC10 Output SDACK2 PC8 Output Table 4 ATOM1 TDM A Port Pin Requirements To achieve this Table 5 shows an example of how the port registers may be programmed Reg
30. TOMI CAM INTERFACE Figure 13 shows the ATOM1 CAM interface and a timing diagram illustrating operation Operation is similar to the Ethernet CAM interface see the MC68360 User s Manual section 7 10 23 7 for further details The SDACK1 signal delimits a header write cycle on the data bus and SDACK2 delimits payload write cycles Both SDACK1 and SDACK2 are asserted during the final payload write cycle ATOMI samples the MATCH signal during the last data transfer of the cell ATOMI User s Manual 1 0 25 No Restriction on Circulation ETATM e TSA SCC lH SDMA RAM MC68360 QUICC CPU32 Core SDACK1 amp CAM MATCH SpACKO FC 3 0 BE CAM Control p Logic 4 Byt SDMA Bus Write Cycle 48 Bytes Payload SDACK1 Output Signal SDACK2 Output Signal MATCH Input Signal Figure 13 ATOMI CAM Interface The user selects the pin to be used as the MATCH input from the port B PBO PB15 pins using the CAM PORT parameter Multiple CAMs can be connected to a single SCC running ATOM1 by using multiple MATCH inputs ATOMI looks for one or more of the MATCH inputs to be active The port B pins being used as the MATCH input must be configured as input ports using the port B configuration registers PBPAR and PBDIR When ATOMI is operating on several SCCs concurrently each may be connected to a CAM To distinguish between the SDMA cycles for
31. TTY cotto stes etta Peu SAU aane abierta eds 30 I2 ORDERING INFORMATION anoni e pique quta Meo ide eto qur duh even 31 13 REFERENCES itenstiquqpisn dd mnt iota mi dui ti MM sazba ara tot A IE 31 Appendix 1 STATE MACHINE DEPALS oso etosetorec etos etuer ent eciae aee stand o ae eun 32 ATOMI Transinitter iordanian e a a E Adde 32 ATM Cell Payload Scrambling eese eee rennen 33 ATOMI RECEIyET iinoa ier a E R ie a EE oak NS 33 HEC Delineation Mechanism sssssesssesssesessseesseessersseresseessseesseesseesseresseee 33 Appendix 2 ATOMI DEMONSTRATION SOFTWARE eee 36 ATOMI User s Manual 1 0 3 No Restriction on Circulation LIST OF TABLES Table 1 CP Control Registets ui undo database Ote qutt tau tct Iud 9 Table 2 MC68360 Serial Interface Programming Example 12 Table 3 Serial Interface RAM Programming Example eee 12 Table 4 ATOM1 TDM A Port Pin Requirements 5 d e tea ert eu era pa ta d tn 13 Table 5 MC68360 Port Register Programming eee 13 Table 6 ATOM1 SCC Parameter RAM Memory Map eee 14 Table 7 ATOMI CRC 32 Calculator Parameter RAM Memory Map 20 Table 8 ATOMI POTORMARCE ag ei vehat tire tee pad Ead 28 Table 9 ATOM I and other Protocol Performance eee 28 Table 10 CRC 32 Calculator Performance ooi se tri Fes oa re e a hin ddege 29 LIST OF FIGURES Figure 1 Typical ATOM Application Sys
32. aintain the performance of ATOM1 it is recommended that the highest speed connection operates on SCC1 and the lowest speed connection on SCC4 ATOM1 uses the SCC in transparent mode with microcode performing ATM cell functions When ATOMI is loaded and RAM microcode is enabled transparent mode operation is available on any SCC other than ones running ATOMI 1 3 Conventions The reader is assumed to be familiar with the OUICC and ATM For further information about the QUICC please refer to the MC68360 User s Manual Full details of the ATM protocols can be found in the relevant ITU T recommendations and the ATM Forum UNI document listed at the end of this manual ATOMI User s Manual 1 0 6 No Restriction on Circulation In this manual the term user is used to describe the CPU software that drives ATOM1 In the MC68360 this may be the CPU32 or an external CPU 2 ATOMI OPERATION ATOM1 transmits and receives 53 byte ATM cells as defined in the ATM Forum UNI specification ATOMI also handles NNI cells Cells are transmitted from a single queue and the user has full control over each cell s GFC VPI VCI PT CLP and payload fields ATOM1 generates and inserts the cell HEC field on transmission and checks and strips it on reception An option is included to apply the HEC coset pattern binary 01010101 to transmitted and received cells ATOM1 performs cell rate adaptation to the capacity of the transmission link by the inserting e
33. ample calculation over the transmit buffer that was just created CRC32 gt CRC_PTR TXBUFF CRC32 gt CRC_CNT 48 CRC32 gt CRC_FC 0x18 CRC32 gt CRC_RESULT 0 Result register must be preset to zero at the start CP gt RTER Oxffff Clear RTER so that no interruprs are pending RTER is used to indicate that a CRC 32 calculation has completed 1 CP gt CR 0x0f01 Start the CRC 32 calculation Return to OUADS debugger TEMPORARY ENDING AFTER CONFIGURATION asm trap 415 asm dc w 0063 Now Enter the ATOM1 Ping Pong Demonstration dodi k k kK KK k ATOM1 PING PONG SOFTWARE Xokck ck ke ke He eeex f KI oko kk oko ko k k oo k kk kk ee ko kok k k k k ke kk kk ee ko koX AAA koe exe This routine uses SCC1 to transmit and receive ATM cells in a game of ping pong It is assumed that SCC1 is either connected with an external loopback or to another QUADs board also running this xy ping pong software Ef x SCC1 must be initialised before running this software x IR The PA15 pin is driven high by software for the duration of the x single cell CRC 32 calculations to allow an external counter or x oscilloscape to measure the CRC 32 calculation duration xy A ok oko oko oko oko ko k ko k ko o k kok oko ee ok kok kk k AA ee A k k k kok I I I He He He kok Tx enough frames to empty the
34. ate transmission The voice transmission software reserves one BD by setting its Skip bit When a voice cell is ready for transmission the voice transmission software inserts the header and payload in the relevant transmit data buffer clears the Skip bit and sets the Ready bit Next time that ATOM1 checks this BD it will see only the Ready bit set and therefore transmit the voice cell Figure 12 illustrates this example The tenth transmit BD is reserved for voice traffic While the voice transmission task is constructing an ATM cell and has nothing in the transmit BD queue ATOMI User s Manual 1 0 24 No Restriction on Circulation it reserves bandwidth by setting the Skip bit When the voice cell has been constructed and loaded into the tenth transmit buffer the Skip bit is cleared and the Ready bit set The voice cell is then transmitted with a maximum delay of nine cells Queue of Data 10 Tx BDs Transmission Task Controls Nine BDs Data Tx Task Tx BD 1 Tx BD2 Tx BD3 Tx BD 4 Tx BD 5 Tx BD6 Tx BD 7 Tx BD8 Tx BD 9 Tx BD 10 Internal Data Transmission Queue Incoming Data Traffic Bursty Voice Tx Task Incoming Voice Traffic Regular Voice Transmission Task Controls One BD Single Cell for Transmission Figure 12 Mixed Voice and Data Transmission Example 7 A
35. bler will attain synchronisation during reception of the first cell in the presync state ATOMI User s Manual 1 0 35 No Restriction on Circulation Appendix 2 ATOMI DEMONSTRATION SOFTWARE This appendix contains demonstration software for ATOM1 The software is assembled for use on the QUADS board and assumes that the ATOM1 microcode is downloaded separately Before running this software the user should either link two QUADS boards both running ATOM1 or externally loopback the master MC68360 transmitter and receiver on one QUADS board V CREEK oko oko oko ko k k o o oko oko ok ok ok ok ke ko ke kk KICK Kok kk ko kk ee kk X k k k oko I I I He He Oe ATOMI Microcode Initialisation and Ping Pong Software m KCkckckckckckckckck ck AA ck ckockckckckckckckckckckckckckckckckckckckckckckckckckck ck ck ckck ck ckckckckckckckckckckck ck kckckckckckckck ck Last Modified 21 March 1996 Rev 1 KCkckckckckckckckck ck AA KKK KK KK KKK KKK KKK KKK KKK KKK KKK ck ck ck ckckckckckckckckckckckckck ck kckckckckck kc kk Filename atoml c KCkCckckckckckckckck ck A A AA AZ KKK X XK K AK K Z AAA AAA KKK XK AX Z AA KKK ckckckckckckckckckckckckckckckckckckck kc KK C Copyright Motorola Inc 1996 Written by Kevin Godfrey Motorola EKB KCkCckckckckckckckckck ck AA AA KKK X K K K K KKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KKK Revision History 0 Initial software 1 CRC 32 Calculator and buffer s
36. cattering added m KAKKKKKKKKKKKK KKK KKK X XK K K K AAA AAA ckckckckckckckckckckckck ck ckckckckckckckckckckckck ck ck kckckckckckckc kk Associated Documentation n d ATOM1 User s Manual DATE 21 March 1996 REV 1 0 i KCkckckckckckckckck ck AA KKK KKK X XK K KKK KKK KKK KKK KK KKK KKK k ck ckckckckckckckckckckckckck ck KKK KKK KKK Target System Motorola QUADS board running QUICCbug As The target system must use an MC68360 or MC68EN360 Rev B or x later Fe kk kok k k k k Ae ko ko ko kk k k k AA kok k k k k k kk I He Oe I I oko oko oko ko ko k o aaa ooo ok ok ok ok ok ok ok kok kok k AA ee kok k k k AA He He He This software initialises SCC1 to transmit and receive ATM cells SCC1 runs ATOM1 microcode Ping Pong demonstration code is included to demonstrate simple receive and transmit buffer handling and CRC 32 calculations The ATOM1 microcode is loaded by other means before running this program To demonstrate ATOM1 receiver an external loopback is required between LITXDA and L1RXDA or the QUADS board can be connected to another QUICC running ATOM1 microcode External clock and synchronisation signals are required ck kk ck kk Ck kk Ck Ck KA C kk kk ck kk Ck kk kk kk Ck Ck Sk ck Ck Ck kk Ck kk kk AXA ck ck ck ckckckckokckckckckckckok oko kok kok k kok Definitions Xokck ke ke ke eee f typedef unsigned char ubyte t
37. ce initialisation is complete ATOM1 can be controlled through the transmit and receive BD queues and commands Example source code for initialisation and operation of ATOM1 is given in Appendix B 9 PERFORMANCE Tables 8 and 9 show the results of some performance characterisation experiments where ATOM1 is run concurrently with other SCCs All results are for zero wait state access to memory In the experiments all SCCs were continually transmitting and receiving data cells no commands or CRC 32 calculations and frames of the following size HDLC frames 24 bytes data 2 bytes CRC Ethernet frames 64 bytes data 4 bytes CRC ATM cells 5 byte header 48 bytes payload ATOMI User s Manual 1 0 27 No Restriction on Circulation Configuration ATOM1 SCCs Mode Frequency Ratio chive 1 ATM SCC1 ATOM1 No Scrambling 1 3 1 ATM SCC1 ATOM1 Scrambling 1 4 5 2 ATM SCC1 2 ATOM1 No Scrambling 1 8 25 MHz 2 ATM SCC1 2 ATOM1 Scrambling 1 10 33 MHz 3 ATM SCC1 2 3 ATOM1 No Scrambling 1 10 3 ATM SCC1 2 3 ATOM1 Scrambling 1 14 4 ATM SCC1 2 3 4 ATOM1 No Scrambling 1 13 4 ATM SCC1 2 3 4 ATOM1 Scrambling 1 19 Table 8 ATOMI Performance ATOM1 SCC Other SCCs Configuration Frequency Frequency m SCC Mode Rati SCC Mode Frequency atio Ratio ATOM1 1 12 J SCC1 No Scrambling note 1 SCC2 3 4 HDLC 1 8 1 ATM i
38. ceive interrupt is generated A2 A13 Address Address offset to the start of the data buffer from the start of the 16K byte receive data area OAM OAMCell Status bit set by ATOMI The associated cell is an OAM or reserved cell cell PT field 1xx ERR HEC Error Status bit set by ATOM1 The associated cell was received with an error in the header as detected by the HEC check ATOMI User s Manual 1 0 22 No Restriction on Circulation HEC HEC Byte Byte containing the received cell s HEC field ATOM1 stores received ATM cells in receive buffers after removing the HEC Receive data buffers have the same structure as transmit buffers The first byte of the buffer is the first byte received the GFC field and part of the VPI The HEC field is removed and stored in the receive BD 6 3 Transmit Buffer Descriptor and Data Buffer Transmit BDs are two bytes long as shown in Figure 10 Each BD is linked to one buffer that must hold the complete ATM cell to be transmitted Transmit buffers may be scattered around a 16K byte area of memory but must start on a long word aligned address If the start address of a buffer is at the very end of the 16K byte area for example the transmit BD is programmed with 8FFF then the end of the transmit cell will be 48 bytes outside of the 16K byte area 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SKIP W I A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 Figure 10 ATOM1 Transmit Buffer Descriptor R Ready Cont
39. count 0 count SI RAM SIZE count SIRAM count 0x0000 Configure SI RAM L1STl1 asserted during the first 4 tx bytes cell header except H L1ST2 asserted during the fifth tx byte HEC L1ST3 asserted during the first 4 rx bytes cell header except H L1ST4 asserted during the fifth rx byte HEC Ba a ti Q count 0 SIRAI count 0x104e Rx cell header SCC1 SIRAM count 0x2042 Rx cell HEC SCC1 x SIRAM coun payload 16 bytes SCC1 SIRAI coun payload 16 bytes SCC1 payload 16 bytes SCC1 0x007e Rx cel 0x007f Rx cel FE FFF 0x007e Rx cel SIRAM count count 0x40 SIRAM count 0x044e Tx cel SIRAI count 0x0842 Tx cel SIRAM count 0x007e Tx cel SIRAI count 0x007e Tx cel SIRAI count 0x007 Tx cel header SCC1 Ey HEC SCC1 a payload 16 bytes SCC1 payload 16 bytes SCC1 payload 16 bytes SCC1 Bbi bmpbmr Enable SI SI gt SIGMR 0x04 Enable TDMA End of config_tsa P ok ok oko oko oko ko A ko k o KKK ee ok kok A k k AA ee kok k k k k kok I IH He He e e ex f F QUICC RAM MICROCODE CONFIGURATION amp INITIALISATION 2 I kok oko ko ko ko k ko o oko kok ee ok kok kok k k o oko kk ee kok k k k k k
40. e volatile 17 struct SCC regs vol VOL VOL Vol vol Vol vol Vol latil atil atil atil latil atil latil atil Le Le Le Le Le Le Le Le uword uword uword ulong ulong uword uword ulong ulong ubyte ubyte ubyte ubyte ulong ulong uword ulong uword ulong ulong ulong uword uword uword uword uword uword uword ubyte ubyte PIPC reservedl PTPR PBDIR PBPAR PBODR reserved2 PBDAT SIMODE SIGMR reservedl SISTR SICMR reserved2 SICR reserved3 SIRP SDCR SDAR GSMRL GSMRH PSMR reservedl TODR DSR SCCE reserved2 SCC reserved3 SCCS ATOM1 SCC Parameter RAM struct ATOM1 vol Vol Vol vol Vol Vol vol Vol VOL Vol VOL vol VOL Vol latil atil atil latil atil atil latil atil atil atil atil latil atil atil Le Le Le Le Le Le Le Le Le Le Le Le Le Le Params uword uword ubyte ubyte uword ulong ulong uword uword ulong ulong ulong uword uword RBASE BASE RFCR TFCR RBLR RSTATE R PTR RBD PTR R CNT RTEMP STA T PTR TBD PTR CN E ATOMI User s Manual 1 0 PIP Configuration Register PIP Timing Parameter Register Port B Data Direction Regist
41. e increment rx counter else pperror 1 Check that received cells have the correct AAL5 CRC 32 value CRC32 gt CRC_PTR RXBUFF 4 CRC32 gt CRC_CNT 44 CRC3Z2 2CRC FC 0x18 gt CRC32 gt CRC_RESULT 0 Result register must be preset to zero at the start CP gt RTI ER RTE CP gt CR while while 0x8000 R is used to indicate that a CRC 32 calculation has completed 0x0f01 Start the CRC 32 calculation PortA gt PADAT 0x8000 Set PA15 pin CP gt CR 0x0f00 Wait for the CP command to complete CP gt RTER 0x8000 Wait for the CRC32 calculator to complete PortA gt PADAT 0x0000 Reset PA15 pin If incorrect CRC32 receiver set error flag if CRC32 5CRC RESULT 0x864d7f99 pperror 1 Return to QUADS debugger ATOMI User s Manual 1 0 43 No Restriction on Circulation asm trap 415 asm dc w 0063 End of Main I kk oko oko ko ko k o o k ok kok ok A KICK Kok k ko kk kk ee kok k k k k oko I IH He He e ex f ZX QUICC PARALLEL PORT CONFIGURATION I He A ko k k o o k ok oko ee ko kok k k k Kok k ko kk ee ko kok k k k k kok kok kok koe e e ex f Function name config parallel ports x I AR RA AK Ke ko ko ko kk AA Kok kc kk kk ee ke kk X k k k ooo I koe e exe x f Configure QUICC Parallel Ports as follows x LITXDA PA6 Transmit data output x
42. e the CRC 8 value is calculated on each incoming longword When this matches the next received byte it is assumed that the HEC is found and the state machine advances to the presync state Because the hunt state only finds a HEC field that is aligned to the start of reception it can take up to four correct cells to leave the hunt state ATOMI User s Manual 1 0 33 No Restriction on Circulation ATOM1 Rx Start MRBLR 0 Y es Goto Transparent Mode ROM Microcode Apply HEC Cell Delineated 25 NO Delineation lt Receive Cell Loss of Delineation Discard Cell Payload m Header Match BN Receive and Store Cell Payload Close Buffer and Update BD Figure 17 ATOM I Receiver Procedure ATOMI User s Manual 1 0 34 No Restriction on Circulation Initial Entry Point Bue com Alpha 7 Consecutive Incorrect HECs HUNT 4 Byte by 4 Byte Search for Single Correct Correct HEC HEC Restart Reception Command Single Incorrect SYNCH Cell by Cell Verification of HECs PRESYNC Cell by Cell Search for Correct HECs Command Delta 6 Consecutive Correct HECs Figure 18 Cell Delineation State Diagram 1 432 specifies that the hunt state searches for a correct HEC on a bit by bit basis but ATOM1 uses a longword by longword search For G 804 framing of ATM cells the HEC field is always aligned with the E1 or T1 frame octet timeslo
43. each SCC each receiver function codes should be programmed to a different value When the CAM interface is operating with ATOM1 the Ethernet CAM interface can still be used The CAM control logic will need to check the function codes and SDACK signals to determine which SCC has initiated a particular bus cycle and enable the appropriate CAM chip ATOMI User s Manual 1 0 26 No Restriction on Circulation 8 LOADING amp CONFIGURING ATOMI Before operation the ATOM1 microcode must be loaded into the MC68360 s internal RAM The microcode is delivered in a file of S records ready to download to a Motorola QUADS board and a general M68000 assembly code file Further details of QUADS download procedures are given in the QUADS User s Manual The microcode occupies the internal RAM blocks DPRBASE 0 to DPRBASE 3FF and DPRBASE 600 to DPRBASE 6FF These areas are unavailable for use by the user Once the ATOM1 microcode is loaded into the MC68360 s internal RAM it is initialized as follows Configure SDMA Configure parallel ports Configure serial interface Enable TSA Configure CP registers Enable RAM microcode Configure SCC registers Configure GSMR PSMR SCCE and SCCM to select required operation 8 Configure ATOMI parameter RAM 9 Initialize queue of empty receive BDs and buffers 10 Clear transmit BDs 11 Enable SCC by setting ENT and ENR bits in the GSMR lower long word ND OFF FP WN FE On
44. er Port B Pin Assignment Register Port B Open Drain Register Port B Data Register SI mode register SI global mode register SI status register SI command register SI clock route SI RAM pointer SDMA Configuration Register SDMA Address Register SCC General Mode Register lower long word SCC General Mode Register upper long word SCC protocol specific mode register SCC tx on demand register SCC data sync register SCC event register SCC mask register SCC status register ATOM1 rx BD Base Address ATOM1 tx BD Base Address ATOM1 SDMA rx Function Code ATOM1 SDMA tx Function Code Transparent receiver max buffer length ATOM1 rx internal state storage ATOM1 rx data pointer ATOM1 rx BD Pointer ATOM1 rx counter Receiver Temporary Storage ATOM1 tx internal state storage ATOM1 tx data pointer ATOM1 tx BD pointer ATOM1 tx counter 38 No Restriction on Circulation VOL VOL VOL latil vol Vol Vol latil vol VOL VOL latil vol Vol Vol Vol Vol latil vol Vol Vol latil vol Vol VOL latil vol Vol Vol Vol Vol latil vol Vol Vol latil vol VOL Vol latil vol Vol VOL VOL VOL latil vol Vol atil atil atil atil atil atil atil atil atil atil atil atil atil atil atil atil atil atil
45. er signalling and OAM functions are not provided by ATOM1 but the user can handle these by routing the PDH SDH OAM signalling and overhead timeslots to one of the QUICC s SMCs or another SCC 2 5 Traffic Control ATOM1 transmits cells from it s single transmission queue in the order that they are presented It is the user s responsibility to apply traffic management techniques to avoid congestion and breaking the UPC rules if the connection data rate is less than the transmit bit rate Failure to apply these techniques may result in bursty traffic on open connections When ATOM1 s transmit queue is empty ATOM will automatically transmit empty cells 2 6 Physical Interface The ATOMI microcode is independent of the physical interface standard used Generally one of the QUICC s TDM ports will be used with ATOM1 to allow easy connection to an E1 or T1 line interface device Other serial interfaces are not precluded and may be selected when programming the MC68360 serial interface This User s Manual describes the TDM interface using the Time Slot Assigner TSA 2 7 Buffer Descriptor and Buffer Structures ATOM1 uses an optimized version of the standard MC68360 data buffer and buffer descriptor BD structures The ATOMI structures are better suited to handling numerous small data buffers as is required in ATM The BDs are just two bytes long instead of the normal eight byte BDs and buffers are fixed length Data buffers are scattered in
46. eues Figure 8 shows an example of the transmitter BD and data buffer queues and the pointers associated with them In this example there are 20 BDs each linked to a buffer TBASE points to the start of the BD queue and TX_BUFF1 points to the start of the buffer area ATOM1 calculates the exact start address of a transmit buffer by adding TX BUFFI to the address field in the transmit BD Buffers may thus be scattered randomly throughout the 16K byte area Queue of 20 Queue of 20 Tx BDs Transmit Buffers TX_BUFF1 TBASE Tx Buffer 1 Address Offset in Tx BD 2 ee Tx Buffer 2 Tx Buffer 3 T_CNT T_PTR Tx Buffer 20 Tx Buffer 19 16K Byte Buffer Area Figure 8 ATOMI Transmit Buffer and BD Queue Example ATOMI User s Manual 1 0 21 No Restriction on Circulation In this example the first two buffers have been transmitted and ATOM1 has advanced the TBD PTR pointer to point at the current BD Similarly the T PTR pointer has been advanced to point to the current data being transmitted by ATOMI T CNT is the offset of T PTR from the start of the data buffer When the end of the BD queue is reached TBD PTR is wrapped back by loading it from TBASE Receive BD and buffer queues follow the same structure as shown here for transmission 6 2 Receive Buffer Descriptor and Data Buffer Receive BDs are two bytes long as shown in Figure 9 Each BD is linked to one buffer that can hold a received
47. gt ALPHA 0 Receiver Synchronisation Alpha Counter ATOM gt DELTA 0 Receiver Synchronisation Delta Counter ATOM gt CAM_PORT 0x0001 CAM Match signal on PBO ATOM gt RX BUFF1 RXBUFF Receive Buffer Area Start Pointer ATOM gt TX BUFF1 TXBUFF Transmit Buffer Page Start Pointer ATOM gt EHEAD 0x01000000 Empty Cell Header little endian ATOM gt EPAYLOAD 0x6a6a6a6a Empty Cell Payload ATOM gt RSTUFF 0 Receive Data Stuffing Location ATOM gt SHUFFLESTATE 0 Receive Data Stuffing State ATOM gt RHECTE 0x00ff Preset rx temp HEC storage area ATOM THECTE 0 Temporary HEC storage area ATOM gt ASTATUS 0 ATOM1 status word ATOM NMA HEAD 0 Non Matching Address Cell Header ATOM NMA CNT 0 Non Matching Address Cell Counter ATOM gt HEC ERR 0 HEC Error Counter ATOM gt RSCRAI 0 Receiver Scrambling Storage ATOM gt RSCRAM1 0 Receiver Scrambling Storage ATOM gt TSCRAI 0 Transmitter Scrambling Storage ATOM gt TSCRAM1 0 Transmitter Scrambling Storage ATOM gt HEADMASK 0 Cell Header Comparison Mask ATOM gt HEAD1 0 Cell Header Look Up Table Entry 1 ATOM gt HEAD2 0 Cell Header Look Up Table Entry 2 ATOM gt HEAD3 0 Cell Header Look Up Table Entry 3 ATOM gt HEAD4 0 Cell Header Look Up Table Entry 4 ATOM gt HEAD5 0 Cell Heade
48. hat area to tx 7 Output Parameters BD queue modified es J CREE oko oko oko oko k k k o KK ee ok A A AAA ee ok kok k AAA I I I He He ee ex f BD_init new_BD skip i_rupt wrap page address ATOMI User s Manual 1 0 47 No Restriction on Circulation uword new BD int Skip i rupt wrap ulong page address uword BD contents BD contents 0x8000 if skip 0 BD contents BD contents 0x4000 Set tx BD skip bit if i rupt 0 BD contents BD contents 0x1000 Set BD interrupt bit if wrap 0 BD contents BD contents 0x2000 Set BD wrap bit Append address BD contents BD contents uword address page gt gt 2 new BD BD contents End of BD init End File ATOMI User s Manual 1 0 48 No Restriction on Circulation
49. ister User Writes hex PIPC PIP Configuration Register 0000 PADIR Port A Data Direction Register 00C0 PAPAR Port A Pin Assignment Register 01C0 PAODR Port A Open Drain Register 0000 PBDIR Port B Data Direction Register 0000 0000 PBPAR Port B Pin Assignment Register 0000 F000 PBODR Port B Open Drain Register 0000 PCDIR Port C Data Direction Register 0500 PCPAR Port C Pin Assignment Register 0D00 PCSO Port C Special Option Register 0000 PCINT Port C Interrupt Control Register 0000 Table 5 MC68360 Port Register Programming ATOMI User s Manual 1 0 13 No Restriction on Circulation 4 ATOMI SCC PARAMETER RAM When ATOM1 operates on a particular SCC the SCC parameter RAM memory map is that shown in Table 6 The user must initialize the parameter RAM with the values given after reset or when re initializing ATOMI Address Name Width Description User Writes hex o SCC Base 02 TBASE Word Transmit BD Base Address UD n SCC Base 05 TFCR Byte Transmit Function Code UD comes mas Wor Tewpees ici Su LsgR m SCC Base 08 RSTATE Receiver Internal State use init rx tx command SCC Base 0C R PTR Receiver Internal Data Pointer use init rx tx command SCC Base 10 RBD PTR Receive BD Pointer SCC Base 12 R CNT Receive Internal Byte Counter SCC Base 14 RTEMP Receiver Temporary Data Storage use init rx tx command SCC Base 1C T PTR Transmit Internal Data Pointer SCC Base
50. it and receive data buffers located in main memory e On transmission ATOM1 constructs the cell header and appends the user defined payload e Bandwidth reservation option in the transmit queue to allow mixing of data and isochronous services e On reception ATOM verifies incoming cell headers and strips the HEC before passing the cell to the user e Automatic empty cell transmission when there are no pending data transfers e Receiver filters and discards empty cells and those with non matching addresses CAM support on reception for handling many connections User controlled cell scrambling option Incoming cells with incorrect HECs are received and marked as such e A CRC 22 calculator is available to reduce processor performance requirements when ATOMI User s Manual 1 0 5 No Restriction on Circulation handling AAL5 cells e Standard QUICC features are available when ATOMI is running E1 ATM E1 ATM Line Transceiver RISC CP CPU32 Core SIM Relay Driver E1 ATM E1 ATM Line D Transceiver 2 Frame E Dual Port RAM Relay Frame o E F System UART RS 232 2 IDMAs Generator Interrupt Memory CPM Controller Controller Chip Selects MC68360 DRAMC P SRAMC System System 8 bit Boot ROM 32 bit SRAM 32 bit DRAM Interface Figure 1 Typical ATOMI Application System 1 2 MC68360 SCCs ATOM1 can operate on any MC68360 SCC and can simultaneously operate on any two three or all four SCCs To m
51. lex operation The frequency ratios quoted are between the main QUICC clock and SCC bit clock 9 1 Command Execution Latency When ATOM1 is operating typical and worst case command execution latencies are slightly longer than when only the standard ROM microcodes are running Note The ATOM1 Restart Reception command is not executed until ATOM processes the end of the current cell being received Therefore command latency for the Restart Reception command depends on when the command is given and data rate 9 2 CRC 32 Calculation Execution Table 10 shows the results of some performance characterisation experiments where ATOMI is running on one or more SCCs while CRC 32 calculations are also running The QUICC s CP runs the CRC 32 calculator as its lowest priority task so the duration of a calculation varies depending on the exact loading and state of the CP The CRC 32 calculations were run over a buffer of 44 bytes representing the AAL5 payload of a single cell AAL5 frame with start of the data buffer aligned to a longword address All results shown in Table 10 are for system operation at 25MHz and can be scaled for operation at other frequencies Configuration ATOM1 SCCs Mode Frequency Ratio Sues Duration 1 ATM SCC1 ATOM1 No Scrambling 1 12 note 1 20 24 us 1 ATM SCC1 ATOM Scrambling 1 12 note 1 20 28 us 2 ATM SCC1 2 ATOM No Scrambling 1 12 note 1 28 37 us 2 ATM SCC
52. mpty cells when no cells are queued by the user On reception ATOM1 ignores empty cells The user can define the empty cell to be either an unassigned or idle cell Received cells with HEC errors are received and marked as such The HEC is passed to the user to allow user software to implement HEC correction algorithms as required ATOMI does not attempt to correct any HEC errors ATOM1 provides an option to scramble data on transmission and receive scrambled data using the X1 scrambling algorithm The first cell to be transmitted by ATOMI after initialisation will not be correctly scrambled because there is no valid data in the 43 bit delay line ATOM1 always transmits an empty cell first therefore avoiding data corruption On reception the descrambling algorithm self synchronises before the HEC delineation process is complete and cell reception begins 2 1 Number of Connections ATOM1 transmits one cell at a time on the virtual connection specified for that cell The user can transmit ATM cells with the whole range of the cell s address field VCI and VPI combined ATOM1 receives cells after matching the cell header with a header look up table or an external CAM The internal look up table has up to 16 entries and cell headers can have bits masked before the comparison The user must maintain enough open channels to receive OAM and signalling cells User software must handle OAM and signalling cells 2 2 Cell Delineation The user must
53. must be initialised to give the start address of the data block for the calculation block length starting CRC 32 seed and function code ATOM1 reads and writes these four parameters during a CRC 32 calculation so they must not be altered by the user while the calculation is in progress The CRC_PTR may be programmed with any address that corresponds to the start of the CRC 32 buffer in memory The length of the buffer must be programmed into the CRC_CNT parameter If CRC CNT is zero at the start of the command ATOM1 will run a Restart Reception command rather than the CRC 32 calculator The CRC RESULT parameter must be preset to zero at the start of a new CRC 32 calculation On completion of the calculation CRC RESULT holds the resulting 32 bit CRC value At the beginning of a CRC 32 calculation CRC RESULT may be programmed with the result of a previous CRC 32 calculation if buffers are being strung together The user configures CRC FC to define the SDMA function code pin settings when the SDMA reads the CRC 32 buffer Further information is given in the MC68360 User s Manual section 7 10 7 2 A CRC 32 calculation is started by writing 0F01 to the command register When the command has been accepted and CRC 32 processing begins ATOM1 clears the FLG bit in the command register Processing continues through the whole CRC 32 buffer and when the calculation is complete ATOMI sets bit 15 in the RISC Timer Even Register RTER This can be used t
54. o generate a processor interrupt by programming the QUICC s interrupt controller Bit 15 of the RTER should be cleared before a CRC 32 calculation is started ATOMI User s Manual 1 0 20 No Restriction on Circulation 6 BUFFER DESCRIPTORS amp BUFFERS ATOM1 uses a modified version of the standard MC68360 BD and buffer data structure better suited to the high number of and small size of ATM cells There is a single transmit BD queue and a single receive queue Associated with each BD queue is a buffer queue All ATOM1 BDs are two bytes long and buffers are all 52 bytes long These BD and buffer sizes maximise the number of BDs that can be located in the QUICC s dual port RAM when the ATOM1 microcode is also present and running The BDs are a subset of the standard QUICC BDs containing only a 16 bit status and control word Buffer length and pointer fields are not implemented as for other QUICC serial protocols BDs are located in the QUICC s dual port RAM All data buffers have a fixed length of 52 bytes and are located within 16K byte buffer areas in memory Receive BD1 is associated with buffer 1 receive BD2 with buffer 2 etc Transmit and receive buffers are scattered within a 16K byte memory area and use an eleven bit pointer within the transmit BD to locate the buffer exactly The transmitter and receiver each use different 16K byte buffer areas which may be located anywhere in memory 6 1 ATOMI Buffer Descriptor and Buffer Qu
55. o oso ta NERO pda a Lem Sue 11 3 2 4 BCC Mask Resister SC OM i cise eee e eos a eeo teal ea 030 esto edet eed 11 2 BOC Status Register SOG Sadeho i keel dead saku deste tudes Sdot aaa 12 3 3 S rial Int rface Me rU EI M E 12 3 3 1 Serial Interface Registers cscs eser t Dd ii n i n iia 12 33 2 DELI al Interface RAM aou baste o a ees db Fee etate dedica Orte kte Pocos dna 12 3 4 Parallel Port Registers secs svsessacisedeaccsdsaveisasndeadeassatesgasesedecadvasaceasoseeventecdaanesebaneceauneasees 13 4 ATOMI SCC PARAMETER RAM eee eee eee eee eee eee innen nennen 14 4 0 1 BD Queue Pointers RBASE and TBASE ccssccscssseccecesssccecesssnecessseeceees 15 4 0 2 SCC Function Code Registers RFCR and TFCR ee 15 4 0 3 Transparent Mode Receive Maximum Buffer Length MRBLR 15 4 0 4 SCC Internal State Parameters RSTATE and TSTATE ees 15 4 0 5 BD and Buffer Pointers R PTR RBD PTR T PTR and TBD PTR 16 4 0 6 Transmit and Receive Buffer Queue Start Pointers TX BUFFI RX BUFFI 16 4 0 7 Buffer Counters R CNT and T CNT eee eene enne 16 4 0 8 Receiver Delineation Counters ALPHA and DELTA eese 16 4 0 9 Version Number AVERSION a a AN nennen nete nen 16 4 0 10 CAM Port Selection CAM PORT eee ee eene 16 4 0 11 Empty Cell Data EHEAD and EPAYLOAD eee een 16 4 0 12 Status Information ASTATUS de
56. ok I I I He He He He f ATOMI User s Manual 1 0 45 No Restriction on Circulation Function name config ucode I He k kk ko k k o k oko ee ko kok k k k Kok oko kk ee ke kk X AAA I I I I koe e ex f Configure CP control registers and enable RAM microcode Ay I ko kk ko ko k AK ok ok ok ok ok ok kok kok k AA ee kok X k k kk I koe e He x f Input Parameters global data structure CP x JR xf Output Parameters CP modified x At I oko oko oko k ko k oo k ok oko ee kok kok k k ke kk kk ee ke kok k AAA I I koe e e ex f config ucode CP gt CPCR1 0x8056 CP Control Register 1 CP gt CPCR2 0x8076 CP Control Register 2 CP gt CPCR3 0x8036 CP Control Register 3 CP gt CPCR4 0x8e18 CP Control Register 4 QUICC rev B1 CP gt CPCR4 0x8818 CP Control Register 4 QUICC rev B2 CP gt RCCR 0x0003 Large RAM microcode now running End of config ucode BI ok oko oko oko oko k k k o ok kk kk ee ko kok kok k k ko kk kk ee k kok AAA I HH He He e ex f IX ATOM SCC CONFIGURATION amp INITIALISATION I oko oko oko kCKCKCKCICkCkCkCkCkCk ee ke kok kk k o o ke kk ee kok k k k k kok I I He He He He He f Function name atom init x RI A ko k k oo k oko kok A kk k k o ke kk ee kok k AAA I I He He He He He f This routine initialises an SCC to transmit and receive ATM cells The SCC is configured but not enabled p I kk ko ko k o o o k kok oko ee ko
57. r Look Up Table Entry 5 ATOM gt HEAD6 0 Cell Header Look Up Table Entry 6 ATOM gt HEAD7 0 Cell Header Look Up Table Entry 7 ATOM gt HEAD8 0 Cell Header Look Up Table Entry 8 ATOM gt HEAD9 0 Cell Header Look Up Table Entry 9 ATOM gt HEAD10 0 Cell Header Look Up Table Entry 10 ATOM gt HEAD11 0 Cell Header Look Up Table Entry 11 ATOM gt HEAD12 0 Cell Header Look Up Table Entry 12 ATOM gt HEAD13 0 Cell Header Look Up Table Entry 13 ATOM gt HEAD14 0 Cell Header Look Up Table Entry 14 ATOM gt HEAD15 0 Cell Header Look Up Table Entry 15 ATOM gt HEAD16 0 Cell Header Look Up Table Entry 16 End of atom init I oko oko ko ko ko k o o oo k ok oko ok ok kk ke ko ko kk k k k kk kk ko kk ee ok kok k AAA I I I IH He He e ex f ATOM1 TRANSMIT 4 RECEIVE BD INITIALISATION ROUTINE ay J CREEK oko oko oko oko ko k k AK ee ko ko kk AA AA ee kok k k k AA I I I He He e ex f Function name BD_init I ok oko oko kCKCKCKCkCkCkCkCkCkCk ee ko kk A AA k Kok kk kk ee k k AAA I I I koe e ex f This routine initialises an ATOM1 transmit or receive BD un I kk oko k ko k o o k ok kk ee ko kk k k k Kok o kk ee ke kk k AAA I I I ee ee ex f Input Parameters Pointer to the BD Ay 5 Flags for Skip Interrupt and Wrap bits Kf al The adresses of the start of data buffer x yos area and the actual data buffer within t
58. re or ATOM1 and must be reset by the user writing a one Bits 15 8 are set by the SCC hardware and some unused bits may be set The user should mask interrupts from all unused bits in the SCCM Bits 7 0 are set by ATOMI to indicate events that it has detected see Figure 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN ata aut occ nma sync ero Hec oam esy tx mx Figure 4 ATOM1 SCCE RX A cell has been received and a receive buffer used This bit is set on completion of reception TX A cell has been transmitted and a transmit buffer used BSY A cell was received and discarded due to lack of receive buffers OAM A control cell OAM or reserved for future use as indicated by the PT field been received and a receive buffer used This bit is set on completion of reception When this bit is set the RX bit is also set but about 10 system clocks later HEC A cell has been received with a HEC error This bit is also set when the SYNC bit is set The HEC bit is set as soon as a HEC error is detected it does not wait until the complete cell is received FIFO A transmit FIFO underrun or receive FIFO overrun error has occurred See ASTATUS for the exact status SYNC ATOMI has lost or gained cell delineation NMA ATOMI received a cell with a non matching address DCC The carrier sense status as generated by the DPLL has changed See description of the Transparent Mode SCCE in the MC68360 User s Manual
59. receive and transmit buffer memory areas each 16K bytes located anywhere in the processor s memory map ATOMI User s Manual 1 0 8 No Restriction on Circulation 3 REGISTERS ATOM1 requires several general MC68360 and SCC registers to be configured for operation and reports status in SCC registers 3 1 General Registers AI the MC68360 general registers SIM memory controller chip select SDMA etc must be configured as described in the MC68360 User s Manual with the exception of the CP Control Registers and RISC Controller Configuration Register Interrupts are generated by ATOMI and the MC68360 interrupt controller must be configured by the user see the MC68360 User s Manual section 7 15 for details 3 1 1 RISC Controller Configuration Register RCCR The MC68360 s RCCR controls microcode operation To run ATOMI the RCCR should be set as shown in Figure 2 Further details are given in the MC68360 User s Manual section 7 1 1 15 14 13 8 7 6 5 4 3 2 1 0 TIME TIMEP EX1M EXOM EX1P EIEE SCD LRAM ERAM ATOM1 0 0 0 0 0 00 0 0 1 1 Figure 2 ATOM1 RCCR Setting RCCR bit 0 enables RAM microcode operation and this should not be done until ATOM1 and the MC68360 are initialized Note the RISC timers are unavailable when ATOMI is running and the TIME and TIMEP bits must be cleared in the RCCR 3 1 2 CP Control Registers The user must configure CP Control registers as shown in Table 1
60. receive gueue The tx gueue was emptied by the initialisation code First transmit enough frames to empty the receive gueue while ATOM1 1 gt RBD PTR ATOM1 1 gt RBASE BD init ATXBD NO NO YES TXBUFF TXBUFF 0 ATOMI User s Manual 1 0 42 No Restriction on Circulation Configure tx buffer area with AAL5 sample frame given in I 363 appendix ulong ATXBuff 0 0x12345678 cell header 0x12345678 AAL5 single cell frame payload consists 40 bytes of zero CPCS UU 0 length 40 and CRC32 0x864d7 99 ky for bytecnt 4 bytecnt 44 bytecnt t bytecnt 0x00 AALS frame payload XBuff bytecnt 0x00000028 AAL5 frame control long word bytecnt bytecnt 4 ATXBuff ulong A1 ulong A1 pperror 0 I XBuff bytecnt 0x864d7f99 AAL5 frame CRC while pperror 0 SCC1 gt n SCCE Oxffff Clear SCCE1 Set up one rx BD with Int and Wrap bits set BD init ARXBD NO YES YES RXBUFF RXBUFF 0 Tx one ATM cell BD Int and Wrap bits set BD init ATXBD NO YES YES TXBUFF TXBUFF 0 txcount Increment transmit cell counter while SCC1 gt SCCE amp 0x007d 0x0000 Wait for reception or error if SCC1 gt SCCE amp 0x00f4 0x0000 On error set error flag rxcount t Otherwis
61. rol bit set by the user to initiate transmission of the associated cell ATOM1 clears the Ready bit when the associated buffer has been transmitted SKIP Skip BD Control bit set by the user When ATOM encounters a transmit BD with the Skip bit set an empty cell is transmitted and control passes to the next BD When the Skip bit is set the Ready bit is ignored W Wrap Control bit set by the user to wrap the transmit BD queue after this BD I Interrupt Control bit set by the user When the cell associated with this BD is transmitted a transmit interrupt is generated This bit is ignored when the Skip bit is also set A2 A13 Address Address offset to the start of the data buffer from the start of the 16K byte transmit data area ATOM1 transmits the ATM cell stored in the transmit buffer and automatically inserts the HEC Data buffers are all 52 bytes long with the first four bytes being the cell header as shown in Figure 11 The first byte of the buffer is the first byte to be transmitted ATOMI User s Manual 1 0 23 No Restriction on Circulation GFC VPI VCI PT CLP Payload Payload Payload Figure 11 Transmit Buffer 6 3 1 Transmit Bandwidth Reservation ATOMI includes a mechanism to reserve transmit bandwidth to aid tasks that require low latency transmission An example of such a system might be one that simultaneously handles voice and data transmissions the data transmission task can queue a large number
62. rrent CRC 32 calculation is complete and the CRC CNT parameter is zero 5 2 CRC 32 Calculator The CRC 32 Calculator command calculates the 32 bit CRC sequence used in AAL5 frames on a data buffer defined by a pointer and length Multiple buffers may be strung together by the ATOMI User s Manual 1 0 19 No Restriction on Circulation user to calculate the CRC 32 value over a large AAL5 frame made up of multiple CRC 32 buffers ITU 1 363 gives more details and examples of AAL5 CRC calculations Note The QUICC s CP runs the ATOM1 CRC 32 calculator as its lowest priority task High traffic throughput on the SCCs and other CP activity will adversely affect the CRC 32 calculator s performance The ATOMI CRC 32 calculator replaces four parameters in QUICC s RISC Timer Parameter RAM area starting at DPRBASE DB0 as shown in Table 7 The user must initialize the CRC 32 parameter RAM with the values given after reset or when re initializing ATOM1 Address Name Width Description User Writes hex DPRBASE DBO CRC PTR Long CRC 32 Calculator Pointer UD DPRBASE DB4 CRC CNT Word CRC 32 Calculator Counter UD DPRBASE DB6 CRC FC Byte CRC 32 Calculator Function Code UD DPRBASE DB8 CRC RESULT Long E Calculator Seed Value dnd sae nooner UD UD User Defined Table 7 ATOM1 CRC 32 Calculator Parameter RAM Memory Map To start a CRC 32 calculation the CRC PTR CRC CNT CRC RESULT and CRC FC parameters
63. ser s Manual section 7 8 3 3 1 The SI registers SIMODE SIGMR and SICR should be programmed for the required interface standard and the user must configure the SI RAM pointer SIRP as required in the system An example of programming the SI registers for connection to a line interface device with common transmit and receive clocks is shown in Table 2 In this example ATOM1 is running on SCC1 Serial Interface Registers Note the timeslot assigner TSA must not be enabled in SIGMR until the SI RAM and other registers have been configured Register User Writes hex SIMODE Serial Interface Mode Register 0000 0058 SIGMR Serial Interface Global Mode Register 04 SICR Serial Interface Clock Route Register 0000 0040 Table 2 MC68360 Serial Interface Programming Example 3 3 2 Serial Interface RAM ATOM1 can use the MC68360 TSA with independent receiver and transmitter routing RAM tables An example of programming these two tables for back to back ATM cell transmission and reception is given in Table 3 TDM A is used and data is routed to SCC1 Other SCCs and TDM B may be used For debug purposes all four SI strobes are asserted during various timeslots L1ST1 during cell header transmission L1ST2 on HEC transmission L1ST3 during cell header reception and L1ST4 on HEC reception SI RAM Entry User Writes hex Strobe Asserted Remarks RxAO 104E L1ST3 Receive four bytes of cell header
64. serteren kei eene enenatis nen 17 4 0 13 Non Matching Header Storage and Counter NMA HEAD and NMA_CNT 17 4 0 14 HEC Error Counter HEC BRN 52m E teehee thei tosh aa 17 4 0 15 Incoming Header Mask and Look up Table HEADMASK and HEADn 18 4 0 16 Temporary ata Storage acu de eco dodo idi e ee ee ae Beds 18 ATOMI User s Manual 1 0 2 No Restriction on Circulation 5 ATONMPCONNLIANDYS adasha odd ees sex ive aus A Feo ti od ses IR ANE Becas Rue E RR Renee qa EN US 18 5 1 Restart Reception Command 2 53 24 0 Heres Rell ada A E R E aS 19 5 2 CBRC 22 Calculator naan a a a S a Us tea Cc 19 6 BUFFER DESCRIPTORS amp BUFFERS soon o m entra ee exta Y QUSE Mn Don 21 6 1 ATOM Buffer Descriptor and Buffer Queues eee eee eee 21 6 2 Receive Buffer Descriptor and Data Buffer sse 22 6 3 Transmit Buffer Descriptor and Data Buffer esses 23 6 3 1 Transmit Bandwidth Reservation sitet adu odn pesi teres Onde plena ed nad dd 24 v ATOM LEAM TINT ERE CB sta odd o gs vp eie o tete ooo ooo look 25 8 LOADING amp CONFIGURING ATOMI 4 eee eee eee eee netten 27 9 PERFORMANCE sorasta Z 9 1 Command Execution Lateney By Gr soe ieni e aaa aa ES 29 9 2 CRC 32 Calculation EX CUUOD iio ceni e te ied ee ee PNE E HAIR esas SIR TI eI Re oak eb dash 29 10 A BOM DISK SOLRUCGCTUBRE dotaz Rea eda lge toa PR QI ad relie EE ps 30 IL MC68360 MASK SET APPLICABIL
65. tem uite ett e eh taoretieepes n a e nesn 6 Figure 2 ALOMURECR ELCHE 9 Figure 3 ATOM PSMI 3 tail Ronan teta rat sune aa od telas tein e Eis tpa us 10 Figure 4 ATOMISCCE etie tie Uti Cane skates Phi tint atest au Ease its oa rte vena bres 11 Figure 5 AS TATUS risit ae tdeo P R att ERE Les 17 Figure 6 HEAIDMLASK 15 5 2 t ee ie ertt en t eto ede ete ba trees 18 Figure 7 AEA Pic E 18 Figure 8 ATOM1 Transmit Buffer and BD Queue Example 21 Figure 9 ATOM1 Receive Buffer Descriptor sees 22 Figure 10 ATOMT Transmit Butler Descriptor zzz besides ps ted kena 23 Figure 11 ToansmltBUPEet s oe ea C En Totus sta d er wins tia etta she te E DAT 24 Figure 12 Mixed Voice and Data Transmission Example sss 25 Figure 13 ATOM1 CAM Inlerface 1 onpeititkt auske enatis ER ERE od e pA Eben aerei pa ea ee 26 Figure l4 ATOMI DISK Structures s rotate eiit torta qe ais p Mp d dados 30 Figure 15 ATOM Transmitter Procedure ies roten das pa oak 32 Figure 16 ATM Cell Payload Scrambling Mechanism eee 33 Figure 17 ATOMI Receiver Procedure er ee tenait ent oath ennt eon naa repro Rua ad 34 Figure 18 Cell Delineation State Diagram tetti there ted eni soenseeoes 35 ATOMI User s Manual 1 0 4 No Restriction on Circulation ATOMI Asynchronous Transfer Mode Microcode for the QUICC 1 INTRODUCTION ATOM1 is an MC68360 RAM based microcode that provides ph
66. transmitter runs ATOMI and the receiver is in transparent mode or vice versa running ATOM1 is not allowed When ATOM1 is loaded and running the maximum serial performance of an SCC in transparent mode is reduced very slightly 3 2 2 Protocol Specific Mode Register PSMR The SCC Protocol Specific Mode Register PSMR controls various SCC functions that are protocol specific Before enabling ATOM1 the user should initialize the PSMR The PSMR should only be written when the transmitter and receiver are disabled otherwise erratic behaviour could result For ATOMI the PSMR is used to control the scrambling and HEC coset functions of both the transmitter and receiver see Figure 3 SCRAM COSET Figure 3 ATOM1 PSMR SCRAM 0 Disable cell payload scrambling during transmission and reception 1 Enable cell payload scrambling during transmission and reception COSET 0 Do not apply the HEC coset rules 1 Apply the HEC coset to all transmitted and received cells ATOMI User s Manual 1 0 10 No Restriction on Circulation 3 2 3 SCC Event Register SCCE The SCC event register SCCE contains status bits for events recognized by ATOM1 and the SCC circuitry Whenever a bit is set in the SCCE an interrupt to the user is generated unless the corresponding bit in the SCC Mask register SCCM is set All bits in the SCCE are sticky bits they are set by the SCC hardwa
67. ts so bit by bit searching is not required To ease implementation this was taken a stage further and ATOMI uses a longword by longword search Over the course of four cells received 212 bytes with correct HECs there will be one matching and aligned HEC This is the point where the state machine jumps to the presync state In the presync state ATOMI has detected cell boundaries and is verifying that they are correct ATOMI leaves the presync state after a single cell with an incorrect HEC is received or the Restart Reception command is given When six consecutive cells with valid HECs are received ATOM1 jumps to the sync state and begins reception The state machine advances immediately after reception of the sixth correct HEC and is not delayed until the end of the cell This means that five cells with valid HECs are discarded and the sixth is received into a data buffer In the synch state ATOMI receives data and control cells and discards incoming empty cells When a stream of cells with incorrect HECSs are received the first six consecutive cells are received and on reception of the seventh incorrect HEC ATOM1 immediately jumps to the hunt state and does nor receive the cell with the seventh incorrect HEC ATOMI also jumps to the hunt state after the Restart Reception command When cell payload scrambling is enabled the descrambler will self synchronise with the incoming data after 43 bits Hence after starting the receiver the descram
68. ufacture of the part Motorola and the Motorola logo are registered trademarks of Motorola i M MOTOROLA ATOMI User s Manual 1 0 1 No Restriction on Circulation TABLE OF CONTENTS 1 INTRODUCTION cm 5 1 1 Key Features of ATOMI 4 eset e par eei eS Eee UV e ARN e i aata 5 1 2 MCEOSIGO SGEE a onto duo ob ro a E E a A o doo bo olo 6 1 3 CONVENUONS ECC sa ida bi Med bla EEEE eee ede ENESE da Siaa e Easa eee ai 6 2 ATOMT OPERATION 5nd e t e ERR EU REI DE E LU A RUNI AA UA 7 2 1 Number or Connections eaa TE E E E E OOo E E E 7 2 2 Cell D eltieaH OD 4 25e tense EE E Eu E E LUE 7 2 3 AAL Frame Check Seguehc s 2 ceto aee na a eot teo pda cued 8 24 PDH amp SDH Physical Layer Signalling amp OAM Functions eee 8 Za Trati Control a WP Cor OE 8 2 6 Physical iGo rh aCe ut oso pat sada Stod EAS ted eidps eiui e Le efe 8 2 7 Buffer Descriptor and Buffer Structures 2 ee tiere entier dee Le pe cese e Daci od 8 3 REGISTERS 25 Aaea ela 9 3 1 General R gisterS nenons e quu ha E A E E zit onu A E I ie tut iue 9 3 1 1 RISC Controller Configuration Register RCCR eee 9 3 1 2 CP Control Registers uso eettossescei ei qua nE gues ER E inser E n 9 3 2 SCC RePISIGIS Sore tli Se esit quee Du ue etus f 10 3 21 General SCC Mode Register GSMR pete ict ite bend ee ted eo pecia eeu Pepe 10 3 22 Protocol Specific Mode Register PSMR eene 10 322 5 SCC Event Resister OS CC Bb eo
69. uword CPCR3 CP Control Register 3 volatile uword CPCR4 CP Control Register 4 uword reserved4 volatile uword RTER RISC Timers Event Register used by CRC 32 calculator volatile uword RTMR p RISC Timers Mask Register r struct Int_regs volatile ulong CICR F CP Interrupt Control Register volatile ulong CIPR j CP Interrupt Pending Register volatile ulong CIMR CP Interrupt Mask Register volatile ulong CISR A CP Interrupt In Service Register p struct PortA regs volatile uword PADIR p Port A Data Direction Register volatile uword PAPAR Port A Pin Assignment Register volatile uword PAODR Port A Open Drain Register volatile uword PADAT s Port A Data Register 7 struct PortC regs volatile uword PCDIR H Port C Data Direction Register volatile uword PCPAR D Port C Pin Assignment Register volatile uword PCSO j Port C Special Option Register volatile uword PCDAT A Port C Data Register volatile uword PCINT Port C Interrupt Control Register ATOMI User s Manual 1 0 37 No Restriction on Circulation struct PIP regs vol vol vol vol vol vol latil latil latil latil latil latil jun struct SI regs vol vol vol vol vol vol latil latil latil latil latil latil 1 struct SDMA regs Le Le Le Le Le Le Le Le Le Le Le Le volatil
70. ypedef unsigned short uword typedef unsigned long ulong ATOMI User s Manual 1 0 36 No Restriction on Circulation Microtec compiler treats char variables as bytes short integers as 32 bit quantities and long integers as 32 bit quantities EJ JEKK e e e e e KK KKK QUADS Board memory Map Ok kk X eek f define QUICC 0x20000 QUICC address 0x20000 define BDArea 0x20400 256 bytes of BD space starts at 0x20400 define ARXBDO 0x20400 ATOM1 rx BDs start at 0x20400 define ATXBDO 0x20440 ATOM1 tx BDs start at 0x20440 define TXBUFF 0x4f0000 ATOMI tx Buffer page starts at 0x4F0000 define RXBUFF 0x4e0000 ATOM1 rx Buffers start at 0x4E0000 f eee ATOMI Demo Buffer Sizes Limits etc eeeeeee x define BUFFSIZE 52 ATM buffer size 52 bytes define CELLSIZE 53 ATM cell length 53 bytes define MAXBUFF 9 Maximum number of buffers 10 T define SI RAM SIZE 128 128 words of SI RAM define MAXBDAREA 128 256 bytes of BD space define NO 0 define YES 1 Define QUICC Registers and Parameter RAM Data Structures struct CP_regs volatile uword CR E Command Register uword reservedl volatile uword RCCR F RISC Configuration Register uword reserved2 ulong reserved3 volatile uword CPCR1 H CP Control Register 1 volatile uword CPCR2 H CP Control Register 2 volatile
71. ysical layer ATM functions by converting one or more of the QUICC s serial communication controllers SCCs into an ATM cell transmitter and receiver ATOM1 provides the user with cell streaming facilities cell reception and transmission and event indications The user can add AAL functions to ATOMI using software The primary application of ATOM1 is intended to be G 804 plesiochronous digital hierarchy PDH and synchronous digital hierarchy SDH E1 and DS1 ATM equipment Such equipment is used for signalling and low rate data transfer and may be part of the telecommunications infrastructure or terminal equipment Figure 1 shows an ATM communications module built around the QUICC running an ATOM1 microcode This module could be a board within a larger system or part of a larger ATM board The ATOMI microcode runs on the QUICC s RISC communications processor CP and is stored in the dual port RAM The user interface to ATOM1 is through buffer descriptors located in the QUICC s dual port RAM and data buffers located in external memory The QUICC s CPU32 controls the module and memory using the on chip memory controller and other integration features 1 1 Key Features of ATOMI The key features of ATOMI are e Cell transmission and reception for all AAL protocols e Handles serial data rates up to 8 Mbps with a 25 MHz QUICC and up to 11 Mbps with a 33 MHz QUICC e Any or all of the QUICC s SCCs can simultaneously handle ATM cells e Transm

ATOM1 : MC68360 ATM Microcode User`s Manual

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