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Methods for Verification of Network Timing and

1. nx T1 Spy nx 11 Gateway k LAN noe Switch y QoS Monitor QoS Monitor Packet Network e a a TDM Network Tiempo Tiempo a NTP Time Stamps Fig 26 Maintaining QoS for PWE 1 92 Page 28 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 1 8 4 There are two basic NTP implementations SNTP and NTP If you are going to install a single server in a small network less than 50 or so clients Simple Network Time Protocol SNTP will work fine However if your plan is larger serving hundreds of clients PCs Network Elements etc then you may need full NTP Full NTP has many expanded capabilities for discovering adjacent NTP servers configuration preferences such as ability to serve as a primary or secondary time source and more These are fully chronicled elsewhere check RESOURSES section for more info In the illustration below the BITS system contains a SNTP Server function providing Time Stamps to multiple Network Elements and PCs at the site It is possible to utilize a NTP server over several HOPS however this should be limited to less than 6 HOPS for critical applications GPS Antenna Router BITS w built in SNTP Server D Fig 27 BITS w Built In NTP Server Page 29 of 106 Copyright 2009 dB Levels Inc All Rights Reserved At
2. Is resistance between zero and twenty Ohms NO s resistance above 150 Ohms NO Vv Antenna circuit appears normal Probable failure in GPS Receiver Consult users manual for additional measures Test antenna cable for continuity from GPS Receiver to antenna element Resistance within YES Lightning arrestor failed or antenna cable damaged Locate lightning arrestor open cable connections and repeat tests in both directions Probable faulty antenna or improper cable size for length Consult users manual for maximum antenna circuit resistance limits Under this condition BITS system should have reported OPPEN antenna circuit ontinuity good Replace antenna system limits Replace or repair antenna cable or terminating connectors Locate and test lightning arrestor Test continuity both directions from arrestor to cable ends If resistance out of limits replace cable with larger gauge lower loss cable NO gt Most standard GSP antennas for BITS applications will have a resistance signature of around 100 Ohms However this may vary by manufacturer so consult datasheet Also certain antenna elements utilize a powering arrangement that may not produce a resistance signature In this case the antenna may appear open You may be able to achieve a measurement by reversing the p
3. SASE clock G 812 SASE clock G 812 a Normal operation the ring is b After fibre cut node 2 enters holdover c Synchronization restored the ring is synchronized by node 1 and becomes master of the ring synchronized again by node 1 gt Working traffic link gt Protection traffic link Synchronization propagatio Fig 22 SSM Messages on SONET PDH Ring 1 7 Use of SSM can significantly impact the planning of Network Synchronization but is fully chronicled in other industry literature Check REFERENCES Section for more information The TROUBLESHOOTING section will advise site technicians how to read SSM in the network Again it is worth noting the SSM does not guaranty signal quality but does identify traceability If a T1 E1 signal carries an SSM then at least it can be traced back to a BITS source at some point If not the SSM will say Don t Use me SSM codes are standardized worldwide so if equipped with a proper Timing Test Set such as the Guisys Model GbB310 RITS technicians can clearly read the SSM associated with T1 and E1 BITS links The Gb310 RITS can also evaluate the quality and performance of the T1 E1 BITS link as well as Composite Clock CC BITS links This will be thoroughly explored in the TROUBLESHOOTING section Page 24 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchroniz
4. Hi how are you doing Fig 5 Multiple synchronized PCM links Page 10 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 1 3 How Network Synchronization is achieved By connecting one end of the Channel Bank to a common frequency reference External Timing the far end Channel Bank could be configured to derive synchronization from the incoming T1 pulses Loop Timing also called Line Timing resulting in synchronization of both Channel Banks BITS Clock Channel Bank Channel Bank External T1 PCM Loop Timing Timing Fig 6 External and Loop Timing Of course if both ends of the PCM span had clock sources that were on par with each other then you could connect the Channel Banks at each end to their respective BITS as shown below BITS Clock BITS Clock Channel Bank Channel Bank External T1 PCM External Timing Timing Fig 7 External Timing only To insure the Building Integrated Timing Supply BITS in each office are in sync with one another a higher order signal is required for all BITS systems to reference equally In the USA this signal is derived from satellites in the Global Positioning System GPS Page 11 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links
5. Table 2 BITS Input Priority 1 5 Therefore if a GPS signal is present that is first priority and is Stratum 1 If GPS fails the external input may be considered the next best source This depends on a couple considerations Over a period of hours days the BITS system will compare the External Signal with the GPS reference If the signal is of sufficient quality the system will maintain it in the priority list Additionally if the signal is a T1 or E1 with SSM the system can immediately determine the traceability to a BITS source This will be explained in detail in the next section Page 15 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB evels and Synchronization Links Rev 1 1 July 2009 1 5 4 If neither GPS nor External Signal is acceptable the system will fall back to HOLDOVER Holdover quality is based on the type of Holdover Oscillator installed in the system If the GPS or External Signal is not restored within the range of the Holdover Oscillator the system will degrade to FREE RUN condition This is to say the output signals are likely at or below Stratum 4 and troubles at the local office are likely Even though the system is in FREE RUN at least all the outputs of the same BITS system are pretty close in quality However that creates additional problems when SONET equipment is used as SONET elements contain an internal Stratum 3 clock which may
6. BITS Input B Monitor Network Element behavior with SSM changes Emulate Generate dual T1 E1 with selectable SSM messages SONET PPDH MUX Fig 83 Manipulating SSM for Multiple Network Elements Page 106 of 106 Copyright 2009 dB Levels Inc All Rights Reserved
7. Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels 4 2009 6 11 02 FW 1 At Power Up tap TIMING from the touch sensitive Main Menu area ow COlock i _FREO_ Vpp T__uS_ Deg 7 2 The default is Composite Clock Bridged Tip Ring Input 00 While the Gb310 RITS is capable of measuring up to 10 simultaneous inputs we will view a single CC link eM Praveen help ond tos gt A 4 GutorTsa 6 03 39 Pm Clock ERES ie king 01 p FREQ Vpp R__u _Deg_ f 3 Tap the icon at top of screen g 1 6000 3300 125 00 180 08 Auto TSG and the test set will g 2 00 Ha Mo Clock 7 0 0 Mo Clock automatically begin sequencing 4 00 E Mo Clock through each of the ten inputs 5 0 0 Mo Clock 6 0 0 a Ho Chock f 0 0 Mo Chock 8 0 0 Mo clock 9 0 0 ooes hho Chock B10 0 0 Ho Chock help and tips gt Page 76 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 sry 2 Qe 11724 10 44 08 AN The Gb310 RITS automatically w CClock Y BROG w Tip Ring w 08 scans all 10 links performing FREQ Ypp T_PHASE_ analysis on the CC under test All readings in BLACK are acceptable all readings in RED are z 130745 7 Mo TIF 64000
8. Configuring Microsoft Windows NTPP for Internet Server 0000e NTP for Measuring QoS in Pseudo Wire Environment Networks 65 BITS System with Built In NTP Server ccc ceeeeeee cece eens seen eeeeees VIDE GINS Ck Ve 06 eee e eE A eO ar E NTP to BITS via Ethernet nnnussssssensecerreseseserrerreresssessrrcerrsssseese Modern Combination BITS NTP System snssnssnssunsusensessesseserserses oP NIN GOO eee e EE mi sidendsaucsateeeuereets BITS Site Survey of Network Elements 00 cccccceeeeeeeeeeeeeeeeeeeeees BHS LEocanon Pinih n c2z0ncnteneasvecaabevonsne eee ocuen yess EE EED GPS Antenna Loss BUGGC bicaesanaveadeeraceuddiavoencesdederdexsoniganea etc aE OO UC Ol VC esnie E AS Typical Antenna Installations ccc ccc ccc cece eee eeeeeneneenaaaaaenaes Avoid Metal SUPACE ATCAS cense sensei tosses EE ANENE AEEA Result of Inadequate Lightning Protection cccccc cece eee eeeeeeeeaeaaes Lightning Protection COnmeCtlONs lt 05cs00c0xsrcaedaccidcnsessveewsibeeteeeeenevenvass Inside vs Outside Mounting of Lightning Protection c cece cece eens Wire Wrap Directly to BITS Shelf 0 c cece cece cece cece eee eeeeeeees Wire Wrap Adapter for Output Connector 0 ccc cece cece eee e cece cece ee ens DSX Panel Winne Scheme eiseressen PEE ECN EAEE EROKET DSX Panel wi Bantan JACKS secs ciatcorea
9. If more than one NTP server exists the NTP client can reference both hosts further increasing accuracy of the end result However for most applications a single server is adequate GPS Antenna BITS w PC built in NTP Server PC to Server gt What time is it asked this question at xx xx xx xx Server to PC gt Time is xx xx xx xx you asked this question xx xx Xx xx ago PC to Server gt What time is it asked this question at xx xx xx xx Server to PC gt Time is xx xx xx xx you asked this question xx xx Xx xx ago PC to Server gt What time is it asked this question at xx xx xx xx Server to PC gt Time is xx xx xx xx you asked this question xx xx Xx xx ago PC to Server gt What time is it asked this question at xx xx xx xx Server to PC gt Time is xx xx xx xx you asked this question xx xx Xx xx ago PC to Server gt What time is it asked this question at xx xx xx xx Server to PC gt Time is xx xx xx xx you asked this question xx xx xx Xx ago Fig 23 NTP Client Server Query Response 1 71 Page 25 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels 1 8 1 To better understand NTP consider the clock in your personal computer Every PC contains an on board clock which plods along on its own This is not an extremely accurate
10. Links ccc cece eee e eee eees 64 3 0 1 Troubleshooting BITS Output Links Flowchartt 00 ccc ce eceeeeeeeeeeeeeees 64 IUe BLS CC Circuit TesiPO MS cs sascscatiauntanetx nae aeea aE 65 3 1 0 Step 1 Measuring CC Signal at Network Element 0 cece cece eens 65 3 1 0 1 Test Set Connection Set up and Results c ccc ccc cece eee eee eeeeeeeeaes 65 3 1 0 2 Test Set Termination Settings for CC Signals 0 ccc ccc cece cece cece eee 68 3 1 0 3 BITS CC Measurement Results Analysis 0 ccc cceeeeeeeeeeeeeeeeeeeeeeeeeees 69 3 1 0 4 BITS CC Signal Peak to Peak Analysis cccccccc cece cece ee eeeeneeeeeennnes 70 Sols LES CC Failure IUS S ereraa EEEE 70 3 2 0 Step 2 Measuring CC Signal at DSX 0 cece ccc e cece cece e eee e eee e eee e ncaa 72 3 2 0 1 Test Set Connection Set up and Results ccc ccc ccc ee eee cece eeeeeeeeaas J2 3 2 0 2 Physical Measurement of CC Cable 0 cece cece cece eee e eee e eee eeeneeeeeeeeeees 73 3 3 0 Step 3 Measuring CC Signal at BITS Shelf 0 ccc cece eens 74 3 3 0 1 Test Set Connection Set up and Results cccc cece eee eee eeeeeeeeees 74 3 4 0 Simultaneously Monitor Test Multiple CC Signals ccc eee ee eee e ee eees 75 3 4 1 Remote Monitoring of CC Signals 0 cece cece cece cece e cece cece cece eee e eee eenens
11. MUX GPS Antenna T1 SSM Stratum 1 PRS CLOCK OUTPUT On the T1 Facility Data Link the message looks like this F bits FPS 001011 CRC 010011 FDL 0000010011111111 Fig 21 SSM Message on T1 For SSM to be useful connected Network Elements must be configured with instructions for actions to be taken in event of degradation of the SSM code For example a normal SSM message of Stratum 1 PRS indicates the T1 or E1 signal is traceable back to a Stratum 1 source While the SSM is not a guarantee of signal quality it can be used to automatically alert connected Network Equipment if the BITS knowingly becomes degraded Page 23 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 1 7 1 SSM is especially useful in maintaining sync in SONET PDH rings The illustration below shows how SSM helps nodes on a ring network make changes to where each node picks timing off the network With SSM the ring is able to automatically reconfigure maintaining synchronization with no technician interaction offering ample time for repair of the original fault condition Network master clock Network Network aii master clock 59 master clock wil PRC G 811 PRC G 811 PRC G 811 Synchronization Synchronization ynchronization network network etwork SASE clock G 812
12. Stratum 3 3E for Crystal If no oscillator insure SSM is Traceability Unknown or Do Not Use for Synchronization dale ish 6 2 BITS Distribution Shelf Input and loss of Input Tests 1 Connect a GUISYS Model Gb310 RITS Intelligent Timing Test Set to the T1 E1 or Composite Clock CC signals at the BITS Distribution Shelf Input connectors 2 Confirm Input Signals pass performance tests NO ERRORS on screen for T1 E1 all readings BLACK for CC 3 Confirm T1 E1 Input signal SSM at Stratum 1 CC does not have SSM 4 Connect a GUISYS Model Gb310 RITS Intelligent Timing Test Set to the T1 E1 signals at the BITS Distribution Shelf Input connector and disconnect T1 E1 signals feeding BITS Distribution Shelf Observe SSM changes from Stratum Ito appropriate holdover value Stratum 2 2E for Rubidium Holdover Oscillator Stratum 3 3E for Crystal Holdover Oscillator 6 3 BITS Timing Loop Test 1 Connect a GUISYS Model Gb310 RITS Intelligent Timing Test Set to the T1 E1 signals at the BITS Distribution Shelf Input connectors 2 View SSM insure Stratum 1 3 Connect a 2 GUISYS Model Gb310 RITS Intelligent Timing Test Set to a T1 E1 signal at the BITS Distribution Shelf Output connector 4 Remove all Inputs to BITS Distribution Shelf Observe SSM change at Output 5 View T1 E1 signals that had been inputs to BITS Distribution Shelf ensure they are still at Stratum 1 The SSM status changes of the BITS Outputs should have no ef
13. not hand me a metronome so we could stay on beat with musical instruments In fact if I really am concerned about the time you gave me perhaps I Il check several other sources and compare the time displays arriving at some logical answer I will use all references available to determine exactly what I believe is the correct time While that is the premise behind NTP let s first examine legacy Synchronization methods Page 8 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels 1 2 The Need for Synchronization in Networks Modern technician lingo blurs the line between several aspects of Network Synchronization In practice it is normal for the following terms to be interchanged by technicians for the same meaning Timing BITS Clocking and Synchronization While the engineering purist objects to this we will delight technicians worldwide by not making a big deal out of it with exception of the sections relating to IP based Network Time Protocol NTP The introduction of Pulse Code Modulation PCM and digital transmission systems into the telephone network resulted in improved quality and efficiencies for transmitting voice and data A single PCM link worked just fine as the digital signals were governed by clocks built into the PCM Channel Banks Switch Channel Bank Channel Bank T1 PCM
14. ond Slips at bottom 051 A Test Chan 051 8 Reference Ti Test System lt help and tips gt a Auto TSG 8 55 29 PM 00 analyze then tap icon View Signal Freg Level and Slips at bottom 0S1 A Test Chan 051 6 Reference Set T1 Mode TERM Framing amp Coding Ti Test System help and tips gt Copyright 2009 dB Levels Inc All Rights Reserved dB levels Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 4 4 1 The SSM and or T1 E1 circuits may also be monitored remotely Long term SSM monitor Local Site NOC DS1 DSX T1 SSM BITS Clock Multiplex ois j elligent Taming System Enor 03292009 4052 00 Stratum 1 PRS 03292009 15 48 20 CHANGE STATE 03292009 15 48 21 Stratum 2 03292009 ihdns DES Betum 1 PRS na 03292009 15 48 20 CHANGE ala ZOO RANGE STATE Eae 03292009 15 48 21 Stratum 2 ae Seen Stratum a 03292009 23 01 20 CHANGE STATE 03292009 23 01 22 Stratum 1 PRS Fig 77 Remote Monitoring of T1 E1 Signals Page 91 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 5 0 Measuring Slips across BITS Outputs and Network Elements The preceding BITS Output measurements all dealt with a single or multip
15. 0 3 39 1 180 00 64000 0 3 356 180 00 64000 0 3 391 180 00 64000 0 3 379 180 00 64000 0 3 301 179 96 z 64000 0 3 397 180 00 0 0 SaaS Mo Clock 64000 0 ae 180 00 64000 0 3 400 180 00 unacceptable For the CC to be deemed acceptable all readings must be BLACK Any RED readings indicate a CC failure 3 4 1 NOTE This test may be performs locally or the Gb310 RITS may be monitored via IP connection from a remote site Long term CC monitor Local Site NOC DSO DSX Channel Banks Timing Test Set Fig 69 Remote Monitoring of Multiple CC Signals Page 77 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 4 0 Troubleshooting T1 E1 Synchronization Links including SSM 4 0 1 The flowchart below provides the basic direction for responding to a T1 Elailure to an existing Network Element This process is also useful for validating a new T1 E1 link connection Detailed steps for this flowchart appear on the following pages The next page contains a flowchart for troubleshooting SSM problems on T1 E1 links Troubleshooting BITS T1 E1 signal loss to Network Element Start BITS T1 E1 alarm report Only one network element in alarm Check NE configuration be sure correct BITS signal applied Be sure FRAMIING correct for
16. BITS T1 E1 SSM SSM is PRS Stratum 1 NO SSM is Stratum 2 or Stratum 3 NO SSM is DO NOT USE DUS NO SM is Traceability Unknown Only T1 E1 carry SSM messages lf any signal other than T1 E1 serving NO BITS shelf SSM is lost for traceability PRS has lost GPS internal Cesium failed ANO or SSM not provisioned BITS Inputs and or Outputs not configured AYES properly or failed cards Flow Chart 7 YES HOLDOVER mode YESp set closer to BITS shelf YES shelves for SSM If T1 E1 tests good and SSM is PRS Stratum 1 configuration physical fault in Network Element or ring failure alert on secondary path BITS has lost primary references and in Repair BITS Input signal s T1 E1 has lost traceability Move test to find good SSM or ring failure alert Go to PRS Bridge mode test all T1 E1 links serving BITS distribution Monitor T1 E1 for signal quality If good and SSM valid inks from PRS to BITS are T1 E1 YES 1 E1 links to BITS SSM of PRS Stratum 1 YES Vv Test BITS distribution shelf Outputs for SSM at BIN outputs is Traceability Unknown NO AA Since this process started at NE answer of NO is illogical Retest at NE and repeat steps Troubleshoot SSM on T1 E1 Page 79 of 106 dB levels Attachment 1 Methods for
17. Database Fig 3 Single PCM link Page 9 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 However when end to end connections traversed two or more PCM links subtle deviations in the Channel Bank clocks allowed frame slips causing audible clicks in the voice traffic and occasional interruption or slowness of data connections Channel Bank Channel Bank Hi how are you doing Switch T1 PCM clicks heard Hi how are CLICK doing Fig 4 Multiple PCM links The solution was to connect all Channel Banks with a common frequency reference synchronizing the internal Channel Bank clocks There were actually two clock signals in the Channel Bank 64kbps and 8kbps called BIT and BYTE respectively These clock signals are utilized to convert analog voice signals into a PCM data stream aligning the encoders and Framers which drive the T1 output signals Since it was impractical to wire BIT and BYTE clock leads from the Building Integrated Timing Supply BITS a composite signal was developed allowing a single link between BITS and Channel Bank The composite signal consisted of 64kbps stream with a purposeful error every 8kb and is called Composite Clock CC BITS Clock Ug Channel Bank Channel Bank Switch Hi how are you doing No Audible T1 PCM clicks heard
18. Intelligent Timing Test Set DS1 A RX jack directly to the T1 E1 signal at the BITS shelf or closest terminating point to the BITS shelf Configure the test set as per Step 1 and set Termination for TERM Test Point Gb310 RITS F Li d S Reference stem Facility Test System Fig 75 Test Set Connection at BITS Shelf If the T1 E1 signal passes all tests screen reads NO ERRORS the signal is within specification If the T1 E1 signal is useable at the BITS shelf Output but fails at the DS1 DSX location probable causes Mis wired DSI DSX jacks Faulty cable between BITS shelf and DS1 DSX Distance to DS1 DSX exceeds BITS system limits Improper T1 E1 cable type see OVERVIEW section for more information Use Volt Ohm Meter to measure T1 E1 cable between BITS shelf Output and DS1 DSX for physical faults such as opens shorts or grounds If continuity good with no physical faults review allowable distance from BITS system to DS1 DSX in BITS Users Manual If T1 E1 signal fails tests at BITS shelf Output Output Card is faulty or improperly configured Call NOC or review Users Manual for troubleshooting Output Card Page 88 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 4 4 0 Monitoring or testing multiple T1 E1 links simultaneously The GUISYS Model Gb310 RITS Intelligent Timing Test Set may
19. July 2009 3 2 0 Step 2 Measure CC Signal at Testpoint B 3 2 0 1 Connect a GUISYS Model Gb310 RITS Intelligent Timing Test Set to the CC signal at the DSO DSX connection or equiv access point Configure the test set as per Step 1 and set Termination for LIVE No GRD Ref Connect a Bantam to Bantam cable from the DSO DSX OUT jack facing the BITS system into the Gb310 RITS as shown below NOTE this will open the CC circuit toward the Network Element terminating the CC signal into the test set MON JACK MON JACK OUT JACK OUTJACK E l a a Digital BITS P m Equipment Gb310 RITS ry a i aE 5 Reference intei jent Timing System _ T1 cc Ground Swale Pulses Errors History Low Bat Facility Test System Fig 66 Test Set Connection at DSX For CC Test Page 72 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 If the CC signal passes all tests all readings BLACK be sure to review both Vpp T and Vpp R the signal is usable for synchronization If the CC signal is useable at the DSO DSX toward the BITS system but fails at the Network Element location probable causes Mis wired DSO DSX jacks Faulty cable between DSO DSX and Network Element Multiple NE terminations on CC cable Distance to Network Element ex
20. O Sync Traceability Unknown 0000 SSU A Traceable CT o Ooo o o O SSU B Traceable CT o o oloo S S O Synchronous Eq Timing Source o o O Don t Use for Sync DUS O O OU o S o O Table 6 SSM Codes for E1 2 7 The preceding examples showed T1 Below is a sample outputs for an E1 measurement w GERI CLEAR NO ERRORS Page 85 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 4 2 0 Step 2 Measure T1 E1 Signal at Testpoint B 4 2 1 Connect a GUISYS Model Gb310 RITS Intelligent Timing Test Set to the T1 E1 signal at the DSO DSX connection Configure the test set as per Step 1 and set Termination for TERM Connect a Bantam to Bantam cable from the DS1 DSX OUT jack facing the BITS system into the Gb310 RITS DS1 A RX as shown below NOTE this will open the T1 E1 circuit toward the Network Element terminating the T1 E1 signal into the test set ee eS a MON JACK MON JACK ouTJack J ouT Jack gt 3 IN JACK BITS Digital Equipment ap Gb310 RN S Reference l Ground ON z x4 xD aPulses z Errors BHistory A e B Ch BEY J Low Bat Facility Test System Fig 74 Test Set Connections at DSX for T1 E1 For non service affecting testing connect test cord to MON j
21. Rev 1 1 July 2009 1 4 Synchronization Signal Stratum Levels Prior to adoption of GPS for synchronization of BITS systems earlier attempts to provide network synchronization followed a hierarchical model as shown in Figure 8 A Cesium Beam oscillator provided precision frequency output and the synchronizing signal cascaded downward through the tiers of switching centers Stratum Level 1 was the most pure signal available so as the signal passed through each level switch transport etc it was of lesser quality more jitter etc Therefore by the time the signal reached the End Office the switching office closest to customers it was Stratum 4 in quality In short the higher the Stratum Level 1 is highest quality the higher the level of stability as compared to the ideal Therefore as the Stratum levels decrease 1 is best 2 is lesser quality 4 is much lesser quality so then do variances in stability Think of it this way the higher the Stratum Level designation number 1 e 4 the more frame slips will occur in the transmission equipment What does this matter Table 1 below provides a glimpse Remember Stratum 1 is as good as it gets followed by lesser quality Stratum 2 lesser still quality Stratum 3 and much lesser quality Stratum 4 This is like your golf score lower numbers are the goal A slip will cause a Voice compressed Primary Office click Cesium Beam Oscillator 7 7 e A slip can wipe out Facsimile sever
22. Synchronization Links Rev 1 1 July 2009 1 9 14 To aide in troubleshooting efforts many companies also wire BITS Outputs through test points such as Digital Signal Cross connect DSX panels The BITS Output circuit can quickly be monitored with a test set for repair efforts As shown below the BITS Output signal can be wired through the DSX panel so that Monitoring Testing or Patching can be quickly achieved greatly reducing troubleshooting time This process fully described in Troubleshooting section MONJACK MON JACK OUT JACK OUT JACK F namaa k P i IN JACK rs IN JACK K i 57 Digital alle se aa C Equipment a a w LY 1 cae PE DSX Fig 43 DSX Panel Wiring Scheme Page 46 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 Two basic types of DSX Panels are prevalent Bantam Jack and RJ45 Jack Both types are shown below m K r 00 24 a 33 Seeseccesscess eecccccceescce 00000000666006 j LLLLLLLLILLLLLL SHSSSSSSSCSECSSSES SESseseceseeess LLLELILLILILTEE TI E I EE IITE I II E CC p I ir ai es a a a ES ee m m o n w r v e m i TA j 7 1A E 7 SEER 8 STE SBEEEH H TY TyTYTT TTT TY Ti eccccccocoooos LLLLLLLLILILLITIEEILIILTLEIILTILIII I E Sseeseseneeceson oe ee poi ell SSS SOAS ee 5553
23. also be used to monitor or test up to 10 TI EE1 links simultaneously This is extremely useful for commissioning a new BITS system or long term monitoring a site for intermittent failures To monitor multiple T1 E1 links the GUISYS Model Gb310 RITS Intelligent Timing Test Set may be connected to an optional cable with various connector arrangements Select the appropriate connector type and connect up to 10 T1 E1 links to the cable The Gb310 RITS can be configured to scan all 10 T1 E1 inputs continuously as shown on next page Gb310 RITS iF L i S Reference stem Up to 10 T1 E1 Links Facility Test System Fig 76 Simultaneous Testing of Multiple T1 E1 Page 89 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 1 At Power Up tap TIMING from the touch sensitive Main Menu area 2 Tap CClock for dropdown menu tap T1 to select T1 Make sure far right number is 00 if 01 tap and change to 00 3 Tap the icon at top of screen Auto TSG and the test set will automatically begin sequencing through each of the ten inputs 4 2009 6 11 02 FW analyze then tap icon i 2 x 4 5 6 T 8 3 i w Ti Result_ Robe ae colin oe oa ai ot Goi sa be oo Page 90 of 106 PASS FAIL FAIL FAIL FAIL FAIL FAIL FAIL FAIL FAIL View Signal Freq Lewel
24. be better than the FREE RUN BITS signals supplied Again you will soon discover how the use of SSM can aide in such situations GPS Antenna CLOCK OUTPUT Strat 1 Fig 13 Output with good GPS Inputs The CLOCK section contains the backup oscillators which can Holdover the quality of the BITS outputs over time For example if you lost both GPS and the external signal the Holdover Oscillation would maintain as near Stratum as possible A Rubidium oscillator can hold outputs to Stratum 2 or 2e almost Stratum 1 but not quite while oven controlled crystal oscillator can hold outputs to Stratum 3 or 3e almost Stratum 2 GPS Antenna GPS X RECEIVER PRS OUTPUT Strat 2e Fig 14 Output with failed GPS Inputs Page 16 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels There is a big difference in cost between rubidium and crystal oscillators so some logic behind which is best for you If your system contains two GPS receivers then you have one layer of redundancy In other words both GPS receivers antennas or antenna cables would have to fail before any of the holdover oscillators would be utilized However if both GPS receivers failed a rubidium oscillator would Holdover at just less than Stratum 1
25. for several weeks unit you could repair the receiver antenna or cabling A crystal oscillator would Holdover several days but at a lower Stratum level than rubidium Therefore rubidium buys you longer holdover at higher quality than crystal oscillators Some companies equip BITS systems with two of every critical component two antennas two receivers two oscillators two output ports per connected element This is called Full Redundancy However before the second oscillator would be used both receivers and the primary oscillator would have to fail so in some cases it may be appropriate to have a primary rubidium and secondary crystal holdover oscillator Itis highly unlikely but not impossible that the secondary oscillator would ever have to carry the day The decisions for the number and type of receivers and oscillators are governed by your company guidelines and may vary by site GPS TTT TT TT TTA Antennas GPs GPS a INPUT RECEIV RECEIV INTER INTER OUT OUT Ble ee Ce CEE ane PRS PRS Fig 15 Redundant BITS System 1 5 5 The MANAGEMENT section of a BITS system is pretty self evident That is it allows communications via Serial and or Ethernet ports offers configuration menus manages and displays sends alarms and generally keeps track of the rest of the system The MANAGEMENT section provides a means for performing simple or exhaustive diagnostics on the BITS s
26. is suggested mostly to protect the cable from deterioration Avoid tree branches radio transmission antennas and low placement on high vertical walls Fig 36 Typical Antenna Installations 1 97 Page 38 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 1 9 9 RF Interference and Metal Surfaces It is not recommended to locate the antennas near broad metallic surfaces as shown below The metal can potentially act as a reflector for interfering signals and also be a magnet for lightning strikes This installation looks beautiful but should be relocated Fig 37 Avoid Metal Surfaces 1 98 Do not install GPS antennas near transmitting antennas or high power antenna feed lines RF leakage and direct radiation can wipe out or intermittently interfere with the GPS signals which are at 125dB Take note of any radiating elements and also beware of line of sight path violations where the GPS antenna is placed in the radiating pattern RF path of nearby antennas If the loss budget is respected the antennas free of interfering signals and away from broad metal surfaces and the lightning arrestors properly connected the BITS clock can provide decades of worry free service However if you break the rules be prepared for intermittent problems and lots of nighttime work tours Page 39 of 106
27. of the CC signal with detection of the 8 KHz element Both the 64 KHz and 8 KHz elements must be present for this to be acceptable Voltage Peak to Peak Tip or Ring Vpp T See box below MicroSecond uS This is a measure of the Tip and Ring of the CC link and will be around 125 uS when measuring Tip Ring This measurement along with Degrees Deg will be further explored when measuring one CC signal against another CC reference signal Degrees Deg For Tip Ring measures this is the delay between Tip Ring leading edges When measuring one CC signal against another CC reference signal this is the phase delta between the two signals Page 69 of 106 dB levels w Clock BRDG GND Ref _FREQ TERM GMD Ret k ode cat egies wate erie lt help and tips gt LIVE Mo SMD Ret FREQ___Vpp R__u _Deg_ 1 640000 3 300 help and tips gt Copyright 2009 dB Levels Inc All Rights Reserved Mo clack Mo clock Ma Chock ha Chock hho clock Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 3 1 0 4 _Vpp T_ 290 ae If all readings on the initial screen are BLACK you must also tap Vpp T to view the reading for Vpp R Each time you tap the Vpp _Vpp k header the reading will change to the next value and each is described below Voltage Peak to Peak Tip or Ring Vpp T This is a measure of the peak to peak CC signals re
28. over IP ccccccc cece eeeeeeeeeeneas 52 TAA eee NTP Failure to Network Elements cccc cece cece cece eeeeeeeeeeeeeeaaaannes 52 2 AA cease tee ING Testto NIP Servel ccweswonsetukce cetnewsooatanateocnsdwesencbuaaasmcanctire 53 2 1 1 Connections Directly t NTP Ser yeh icnsiec comntiteaciactesoseasissennewrenacdeasscianeies 55 2 AAs Seuns Test PE Address 4 2 ccancataetciruteeccine dace e TaT SEEE 55 2 1 1 3 Testing Assigned NTP Server IP Address with surrogate ccc cece neues 56 ZN 2 e Sle 2 Generate NTP Test Query cin crcctuceseveriedoninsecaesvenbicotisdatdacssetcend 57 2 1 2 1 Use Network Sniffer to Trap NTP Query Response ceee cence eee eeees 57 2 122 Analyze Network Sniffer TrapS srscssseisisssnrariiga saroia seniri ran AEn En EN beats 59 2 1 2 3 Testing to Multiple NTP Servers or PC Hosts nnsnnnnnnnnnnsunsensesseseesen 60 2 1 2 4 MS Windows w32tm monitor Command 0 cece cece cece cece cece cece eee eees 60 2 1 2 5 MS Windows w32tm stripchart Command ccccc cece eee eeeeeeeeeeaas 61 A k20 NIP Tesine to Mntermet Sry Crs iseseisana EEOSE ENESTE 61 2 2 0 NTP Failure to Specific Network Elements 0 0 cccceeeeeeeeeeeeeeeeeees 62 2 2 en Sezinenune NTP Network Falle Serenes erinan eerk derauka r irai enait 63 Troubleshooting Composite Clock CC Network Synchronization links DO seated Troubleshooting BITS Composite Clock CC
29. plugging into a MON jack at DSX select MON Page 96 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 The Gb310 RITS compares the input signal with the reference signal If the signals are both stable Slips will be zero 0 as shown at right above If Slips present trace BITS shelf Inputs to be sure both shelves are referenced to a PRS w BERT L AUTO TEST Bits NO ERRORS Hz Slips 0 0 Dew 00H cas ET 0 1 144 Bee DS1T RMDSX w ESF B25 7 BERT AJTO TEST Bits CLEAR NO ERRORS Slipste2 Dew 2 3h2 Page 97 of 106 Copyright 2009 dB Levels Inc All Rights Reserved dB levels Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 5 3 0 The setup shown below may be used to determine if the local BITS outputs are drifting However this setup is extremely useful when testing a T1 E1 signal with unknown origin of synchronization For example a small Central Office may be assumed to be timed by an incoming T1 E1 from a larger carrier However this is extremely risky and usually leads to future synchronization troubles Use the setup below to measure the stability of any T1 E1 signal You will quickly discover if the signal is traceable or if it is from a free run sourc
30. signal acceptable NO y Disconnect CC cable feeding NE and connect test set directly to BITS output Is CC signal acceptable NO y Check BITS port configuration and or replace output card Problem corrected NO y Trouble is in BITS shelf contact NOC Start BITS CC alarm report Only one network element in alarm Go to network element in YES alarm connect test set to CC signal Check NE configuration YES be sure correct BITS signal applied Repair open CC cable to NE Repair shorted CC cable or bad NE input port to Prose complete Flow Chart 5 Troubleshooting CC Page 64 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels 3 0 2 The BITS CC circuit will be tested at the following location s e Test Point A at the BITS card output connector or closest terminating point e Test Point B at the DSO DSX or equiv if present e Test Point C at the Network Element Input connector Test Point Test Point Test Point A B C CC shhh DSO DSX BITS Clock Network Element Fig 62 CC Circuit Test Points 3 1 0 Step 1 Measure CC Signal at Testpoint C 3 1 0 1 Connect a GUISYS Model G
31. your needs If the predominance of your output requirements are Synchronization based T1 E1 CC etc then the best solution is to add NTP capability to a new or existing BITS system However if the majority of your needs are on the IP side purchasing a GPS based NTP server is best Most commercial NTP servers also have a limited number of Synchronization outputs as well so today you can have both in a single package Below is the rear view of a modern combination BITS NTP system available in ANSI or ETSI versions that may be equipped with single or dual GPS Receivers up to 2 external inputs single or dual Rubidium crystal or mix of Rubidium crystal holdover oscillators and 64 outputs that can be programmed by port allowing you to skinny down or fatten up as needed The system also offers IP connections for SNMP management and up to two ports of SNTP and IEEE 1588 v2 all at only 2 Rack Units RU Just a few years ago this same capability would have consumed 10 RU The SNTP option for this system sells for under US 800 Today there is no reason to buy separate elements for providing Synchronization and Timing outputs MANUFACTURED BY FUSE ZA CXR LARUS CORP l r California USA i A 5 Ed 3 l ia ISSUE po S gt I B y F a S i iD AND UL CE LABEL th MAJ WES MAJ AUD 3 i CRIT AUD MIH vis m j 5 o 90 MHZ CRIT We MIN ALD J1 3 ja s
32. 3325255533 dahi Bakta PANEL r gt eeeatens ttssssessiesse s2sss0s _ ahs Fig 44 Fig 45 DSX Panel with RJ45 Jacks Page 47 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels 1 9 15 The drawing below is typical for SONET PDH transmission equipment connections Note this Network Element has connections for two BITS inputs BITS Input 1 amp BITS Input 2 for Protected Full Mode operation The BITS connection matrix is shown below the connecting pins Review the matrix carefully What pins would you naturally assume would be used In this example the primary BITS cable would tie down on pins A4 amp B4 BITS Input 1 The secondary BITS cable would tie down on pins A2 amp B2 Sync T1 w SSM Input 2 Output Card 1 Port 1 Output Card 2 Port 1 T1 w SSM Sync Input 1 BITS OUTPUT Pin BITS Output 2 negative B1 BITS Output 2 positive RITS input gt magat BITS Input 2 positive BITS Output 1 negative 63 DITS Output 1 postive BITS Input 1 megat BITS Input 1 positive i ve Fig 46 SONET PDH BITS Connections Local End In the above example a SONET PDH system is used to carry sync to a distant location off site where the T1 sync signals two T1 circuits extended from the local BITS will
33. 6 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels 1 5 6 3 In Protected Full Mode the Network Element will have two Sync Input connectors example Input A amp Input B or Input 1 amp Input 2 These may be wire wrap or RJ type connectors The BITS outputs are taken from adjacent output cards but the ports are not set up as Protected Port Rather the Network Element has two independent sync links so that in event a BITS card or cable fails the second sync input is unaffected In this case both BITS links are active all the time This is the most preferred method for connecting Network Elements to a BITS system MUX etc T1 E1 wW SSM Output Card 1 Port 1 Output Card 2 Port 1 T1 E1 w SSM sync BITS Input B OUTPUT Fig 18 Protected Full Mode Page 20 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 1 5 6 4 Timing Insertion Mode allows Network Equipment that has no external sync port no extra pins used just for sync input to be brought into the same level of synchronization as adjacent Network Elements that have dedicated BITS connections Basically the traffic bearing T1 E1 to the Network Element is looped through the BITS system where t
34. 77 Troubleshooting T1 E1 synchronization links including SSM 4 0 Troubleshooting T1 E1BITS Links Including Sync Status Messaging SSM 78 4 0 1 Troubleshooting T1 E1 BITS Output and SSM Flowcharts eeeees 78 4 0 2 BITS T1 E1 Circuit Testpoints 0 ccc ccc cccceeeeeeeeseeeceeeseescsecteeeees 80 4 1 0 Step 1 Measuring T1 E1 Signal at Network Element cee eee 80 4 1 1 Test Set Terminations for TI E1 Testing c cece ccc eeeeeeeeeeenes 82 4 1 2 Test Set Connection Set up and Resullts 00 ccc cece cece cece eee eeeeeeeeeeeeees 83 4 1 3 Test Set Set up and readout of Sync Status Messaging SSM 000008 84 4 2 0 Step 2 Measuring TI EI Signal at DSX ccc cece eee eee e eens 86 4 2 1 Test Set Connection Set up and Results 0 ccc cece cece cece eee eeeeeeeeeeeeeeees 86 4 3 0 Step 3 Measuring T1 E1 Signals at BITS Shelf 0 ccc ees 88 4 3 1 Test Set Connection Set up and Results 0 cece cece eee e eee e eee eeeeeeeeeeeees 88 4 4 0 Simultaneously Monitor Test Multiple TI E1 Signals ccc eee 89 4 4 1 Remote Monitoring of TI E1 Signals 0 cece cece cece eee e eee e ee eeeneeeeeee ees 91 Page 2 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization
35. A dB Levels White Paper d B I vel 5S Dallas TX USA 214 257 8823 www dblevels com Methods for Verification of Network Timing and Synchronization Links By Daniel B Burch July 2009 Contents Introduction Problem Statement Previous Options Recommended Solution Implementation Summary Attachment 1 Methods for Verification of Network Timing and Synchronization Links References Resources July 2009 A FP OO W DN ND Introduction Guidelines for Network Synchronization and Timing have been adequately chronicled for Network Planners and Engineers however there has been a void in materials and procedures to guide local site technicians and maintenance engineers regarding testing of BITS clock input and output links and troubleshooting of synchronization and timing related problems in general Problem Statement Telecommunications site technicians are tasked with maintaining a wide array and vintage of Network Elements including TDM voice switches Fiber Optic transmission equipment Channel Banks Add Drop Multiplexers and IP based routers gateways switches and management systems For the entire Network to be properly synchronized nearly all of these devices require connections to the Building Integrated Timing Supply BITS Equipment installations for local office and field locations were based on prevailing procedures of the day resulting in a myriad of possible connection arrangements test a
36. Clock ae Mo Clock Mo Clock a Mo Clock Mo Clock Mo Clock ae Mo Clock Mo Clock help and tips gt At right is example of a failed CC link with a severely attenuated Signal level Therefore the Vpp peak Tip Voltage Displays in red This CC cable was terminated onto multiple Network Elements in error While a CC signal may be connected to multiple Network Elements only a single NE may be in TERMINATE mode all others are in BRIDGED mode Once the additional NEs terminations were corrected the signal was acceptable so tial an tid tr boy he Hig ame Nearly all BITS CC failures are related to either the BITS Output card or the cable which extends CC to the Network Element The Output card may be failing or merely needs configured properly The cable may be too lengthy or exhibiting physical faults such as shorts or grounds At any rate the gB310 RITS can be used to sectionalize the fault condition If the CC signal passes all tests at Test Point C the signal is usable for synchronization If the Network Element does not sync on an acceptable CC signal the NE requires configuration or hardware adjustments or replacement parts However if any CC signal reading fails displays red at Test Point C move on to Step 2 Page 71 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1
37. Connect test set to external inputs NOP See Troubleshooting Antenna Circuit NOP Follow users manual for trouleshooting GPS receiver circuit Input signals acceptable eal Troubleshoot input signals YES gt Confirm system is provisioned for external inputs including configuration for termination and signal type If correct follow users manual for troubleshooting Input circuit failure Input signal may be T1 E1 CC or other If T1 E1 or CC connect test set and verify signal quality Also use reference signal from BITS to look for frame slips between external signal and reference signal If BITS GPS good and locked likely the input T1 E1 or CC signal is not from a stable source Flow Chart 1 BITS Input Signal Alarm Page 50 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels Troubleshooting BITS Antenna Circuit Start BITS antenna circuit failure When logged into BITS system antenna circuit test yields faulty antenna circuit System indicates open or shorted antenna SHORTED y Disconnect failed antenna lead from BITS system Measure DC resistance with VOM Measure center conductor to shield then center conductor to ground
38. Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 1 9 10 Antenna Lightning Protection As previously discussed the antenna element is the most likely point of failure in a BITS system excluding configuration errors It should go without saying that any element that breaches the office walls should be adequately protected from delivering harmful voltages into the equipment room Failure to do so routinely results in failures as shown below which can cost upwards of 8 000 to repair r 1 i a Tm _ _ PAra rR ii TALL reeeerrr aa rit Aen al Fig 38 Result of Inadequate Lightning Protection 1 99 For active GPS antennas special protection devices allow normal operation and isolation from ground except the duration of a lightning strike The isolation and protection elements activate and if not damaged or destroyed faithfully return to the previous state It is critical to observe the manufacturers recommended installation procedure for lightning protection hardware Failure to do so could actually increase the chance of permanent damage to the BITS system Page 40 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels In addition to t
39. F B25 7 BERT AJTO TEST Bits CLEAR NO ERRORS Slipste2 Dew 2 3h2 Page 103 of 106 Copyright 2009 dB Levels Inc All Rights Reserved dB levels Attachment I Methods for Verification of Network Timing dB evels and Synchronization Links Rev 1 1 July 2009 6 0 BITS System Turn Up Testing Once a PRS and BITS distribution system have been installed several commissioning tests will insure the system is properly configured and equipped PRS Output performance and SSM test PRS loss of GPS SSM test BITS Distribution Shelf Input test BITS Distribution Shelf loss of Input test BITS Timing Loop Test BITS Distribution Output test Instructions for performing the above tests are included in each preceding section The information below will provide a template for BITS System turn up testing 6 1 PRS Output performance Loss of GPS and SSM tests 1 Connect a GUISYS Model Gb310 RITS Intelligent Timing Test Set to the T1 E1 signal at the PRS Output connector Confirm Output signal passes performance tests NO ERRORS on screen View SSM insure Stratum 1 displayed Perform Steps 1 3 above for all PRS outputs Measure Slips from PRS Output Port 1 against all other PRS T1 E1 Output Ports Insure zero 0 Slips Disconnect GPS Antenna s view SSM on Output Ports Insure SSM changes from Stratum to appropriate holdover value if PRS equipped with internal oscillator Stratum 2 2E for Rubidium
40. Links Rev 1 1 July 2009 Measuring Slips 5 0 5 1 0 5 1 1 sA eee s HA P Io ree poi eee 5 4 0 IA kea across BITS Outputs and Network Elements Meas ring Frame S198 ix2c0 lt edcoteautiettinwtaseetuedeselovieeieaeermerseneinreidecteudes Slip Testing T1 E1 in Same BITS Shelf 0 ccc cece eee cece eee eeee Test Set Connection Set up and Results 0 0 cece cece cece cece eee eeeeees Slip Testing T1 E1 NOT in Same BITS Shelf 0 e cece Test Set Connection Set up and Results cccc ccc cee cece ee eeeeeeeeeneees Measuring Frame Slips against Temporary Portable GPS Clock Test Set Connection Set up and Results ccccc ccc cece cece eee eeeeeanenes Measuring Frame Slips across Network Elements cccccceeeeeeeeeees Test Set Connection Set up and Results cccccc ccc cece cece cece eeeeeeeenes Commissioning Testing of Newly Installed BITS Systems 6 0 Olas O72 scx Osis 6 3 1 BITS System Turn up Testing Commissioning Tests ccceeeeee eens PRS Output Performance SSM Tests 1 cidecsecacceiecsssesiawoatectiaiereaseeiansanand BITS Distribution Shelf Input and Loss of Input Tests cece Testa for BITS Timing 00 pS icc cn exsvatutnsciwsehsdooesauesesardsducasdawabiemsexacte BIHIS Erone Sp e ae eseespeeuratniecuadieta vane EE nseseuSeneseene Manufacturing Vendor Testing of N
41. NS The Gb310 RITS defaults to BRDG GND Ref for testing CC signals However if the termination status 1s unknown for the Network Element s the test set may show RED initially If a RED reading is obtained switch to LIVE No GND Ref and remove ground cable from test set The following scenarios provide guidance on which termination setting is appropriate Timing Signal Set Gb310 RITS for Generator TSG BRDG GND Ref and Output GROUND instrument on gt Network Element with ground reference termination Timing Signal Set Gb310 RITS for Generator TSG TERM GND Ref and Output GROUND instrument i Disconnected Network Element Set Gb310 RITS for Timing Signal LIVE No GND Ref and Generator TSG DO NOT GROUND Output instrument on Network Element with unknown termination Fig 65 Test Set Termination Options for CC Testing Page 68 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 To change the termination setting just tap BRDG for a drop down menu 3 1 0 3 Results Analysis The Gb310 RITS automatically performs analysis on the CC under test All readings in BLACK are acceptable all readings in RED are unacceptable For the CC to be deemed acceptable all readings must be BLACK Any RED readings indicate a CC failure Frequency Freq This is a measure of the 64 KHz portion
42. NTP Query Test sequence 2 1 1 STEP 1 PING the NTP Server Using a laptop PC disconnect one Network Element and replicate the IP address NOTE this is service affecting and may require maintenance window In below example a VoIP Gateway address 192 168 1 100 was replicated in the laptop As an alternative you may configure the laptop with a new IP address selected by the network administrator NOTE if no router is between you and the NTP Server you must use an address on the same sub net as the NTP Server address Open DOS window and at gt prompt enter ping 192 168 1 50 or the address of your NTP Server then press Enter If successful results similar to Fig 50 A good PING response does not guaranty NTP is working but is the first step in determining if you can see the NTP server on the network GPS Antenna Ole Fiber Switch MUX 192 168 1 50 192 168 1 24 192 168 1 83 SS 192 168 1 1 192 168 1 100 Router VolP Gatway Fig 49 PING the NTP Server Page 53 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 If PING successful results will be similar to the screen below CG M ping 1972 168 1 56 Pinging 192 168 1 580 with 32 bytes of data Reply from 192 168 1 58 bytes 32 time 2ms TTL 64 192 168 1 58 bytes 32 time lms TTL 64 192 168 1 58 bytes 32 time l
43. Newtork Element SF D4 vs ESF Go to network element in YES alarm connect test set to T1 E1 signal T1 E1 signal acceptable NO NO y y Trace T1 E1 cable back to DSX panel or BITS shelf See Troubleshooting BITS Shelf Repair open T1 E1 cable to NE Retest T1 E1 signal is Signal acceptable vE NO y Disconnect T1 E1 cable feeding NE and connect test set directly to BITS output Repair shorted T1 E1 YES cable or bad NE input port Is T1 E1 signal acceptable NO y Check BITS port configuration and or replace output card Problem corrected Pres compete NO y Trouble is in BITS shelf contact NOC Flow Chart 6 Unsuccessful PING of NTP Server Page 78 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 Multiple Network SSM alarms Go to network element in SSM alarm connect test set to T1 E1 signal If T1 E1 acceptable view SSM Valid SSM Message NO v YES SSM not provisioned Check BITS port configuration and or replace output card If Timing Insertion Unit TIU employed verify SSM is enabled in TIU Copyright 2009 dB Levels Inc All Rights Reserved Troubleshooting
44. ST SET e Guisys Corp 40W320 LaFox St Charles IL USA 60175 630 672 8540 www guisys com GbB310 RITS Intelligent Timing Test Set NETWORK SNIFFER free versions available for PC e WIRESHARK Network Protocol Analyzer Ver 1 0 7 freeware 1998 2009 Gerald Combs www wireshark org TECHNICIAN TESTING AIDES VIRTUAL HELP DESK e dB Levels Inc www dblevels com Page 6 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels 1 0 The term Timing has historically been associated with Time Division Multiplexed TDM Networks where a Building Integrated Timing Supply BITS utilized T1 E1 Composite Clock or other links to synchronize Network Elements A technician might express I ve got a Timing problem in my office Or I need to run external Timing to that Channel Bank Strictly speaking this is not Timing it is Synchronization Timing is a method for providing a reliable reference of exactly what time it is right now For example the answer might be that it s 10 23 00 or twenty three minutes past ten o clock AM Note that we still don t know what time zone we are referencing EST CST PST etc This is more commonly referred to as a Time Stamp signifying an exact moment in time One of the most widely deployed protocols for time stamping is called Network Time Protocol or NTP for short Whe
45. Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 4 0 2 Troubleshooting T1 synchronization links including SSM The BITS T1 E1 circuit will be tested at the following location s Test Point A at the BITS card output connector or closest termination point Test Point B at the DS1 DSX or equiv if present Test Point C at the Network Element Input connector Test Point Test Point Test Point A B C e e e e e eo o T1 E1 DS1 DSX Network Element T1 E1 BITS Clock Fig 70 Test Points for T1 E1 BITS Output Circuits 4 1 0 Step 1 Measure T1 E1 Signal at Testpoint C Connect a GUISYS Model Gb310 RITS Intelligent Timing Test Set to the T1 E1 signal at the Network Element Sync Input connection The Gb310 RITS is a portable multi purpose test set with special features for analyzing T1 El and CC BITS signals Gb310 RITS rj F L i Reference g S To power on instrument lift power switch toward top After configuring test set use the DS1 A RX Input Bantam jack Configuration steps are shown below Facility Test System Power Switch DS1 A RX Input Fig 71 Test Set Connections for T1 E1 Signals Page 80 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 1 At Power Up tap TIMING fro
46. a clear sky view on the outside of the building From this survey the Sync Plan will identify the size type and number of BITS systems required for the site including redundancy requirements Type Additional Number of Input Number of Input Additional Network Element Required Inputs Requirements Inputs Distance to BITS Alcatel Channel Bank CC 1 8 Alcatel Channel Bank CC 1 o J o o 120 ft Cisco SONET TIW SSM 2 NP 1 t SESS a a2 S y f OOA Fujitsu DSLAM CC 2 NP 1 20t O E e e Fig 32 BITS Site Survey NEs Once the audit of Network Elements is completed it is a simple thing to tally up the number of required outputs by type Note in the example above one Network Element Brand X MUX has no external sync input so will have to be Line Timed on the traffic bearing T1 This can be accomplished via a Timing Insertion Unit where the traffic bearing T1 is looped into and out of the BITS system In most small offices all Network Elements will be within allowable distance limits from the BITS system Larger offices especially with multi floor buildings will require up to several BITS Distribution Shelves The BITS Distribution Shelves have to be engineered so that the allowable output cable distances can be met without violating the distance limits between the BITS Distribution Shelf and Primary Reference Source locations These distance limits will be fully explored below Redundancy requirements va
47. abled in server YES y Use laptop PC to launch NTP request from NE location NTP query respons good YES Network Elements not pointed properly to NTP server Reconfigure NTP settings in Network Elements zan you PING IP address not provisioned in NTP server or incorrectly provisioned NO gt server when nected directly YES y NOP Two likely causes duplicate IP address in use Router or other IP equipment is filtering NTP packets Use Enable NTP when connected Network Sniffer moving from Network Element toward NTP server at each network segment to determine where NTP packets are blocked See Users Manual for advanced BITS system troubleshooting and or call manufacturer response g NO gt directly Router or other IP equipment is filtering NTP packets Use Network Sniffer moving YES p gt from Network Element toward NTP server at each network segment to determine where NTP packets are blocked Flow Chart 3 NTP Failure to Network Element Page 52 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 As shown in the Troubleshooting Flowchart above there are two processes for testing NTP failures PING Test Sequence
48. ack and set test set termination to MON Page 86 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 If the T1 E1 signal passes all tests NO ERRORS displayed on screen the signal is within specification If the T1 E1 signal is useable at the DS1 DSX toward the BITS system but fails at the Network Element location probable causes Mis wired DSI DSX jacks Faulty cable between DS1 DSX and Network Element Multiple NE terminations on T1 Elcable Distance to Network Element exceeds BITS system limits Improper T1 E1 cable type see OVERVIEW section for more information Use Volt Ohm Meter to measure T1 Elcable between DSO DSX and Network Element for physical faults such as opens shorts or grounds If continuity good and no physical faults review allowable distance from BITS system to Network Element in BITS Users Manual View SSM on T1 E1 link If not proper Sync level refer to Troubleshooting SSM flow chart for instructions If T1 E1 signal fails tests at DS1 DSX move on to Step 3 on next page Page 87 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 4 3 0 Step 3 Measure T1 E1 Signal at Testpoint A 4 3 1 Disconnect the cable to Network Element connect a GUISYS Model Gb310 RITS
49. acted for technical support on difficult synchronization troubles experts will always want a look at the Sync Plan You have to know where synchronization starts originates and where it ends what s connected It is crucial that Timing Loops be identified and corrected or the entire network will collapse upon a GPS failure A Timing Loop occurs when a BITS system is in some way referencing an input signal that is directly or indirectly derived from one of its own outputs GPS GPS traceable T1 E1 Antenna or other reference Inputs Unintentional use of reference signal traceable to the original output on the same BITS xN Fig 31 Timing Loop Page 33 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 1 9 3 What and How Many As previously discussed any BITS installation should be driven by specific dictates of the Synchronization Plan Sync Plan If the office is small with fewer than 64 Network Elements to be connected a Site Survey will provide the details from which a Sync Plan may be developed 1 9 4 A basic site survey consists of an audit of all Network Elements NEs determination of the type of synchronization signals required by each NE availability of suitable power and ventilation location and suitability of existing grounding scheme for the lightning arrestors and access to
50. al lines A slip can cause several seconds of Regional Office dropout Toll Tandem A slip can wipe out Office Compressed video or several lines More Video Conferencing slips can freeze frames End Office for several seconds Switches Channel Slips will reduce RANKS Encrypted data transmission protocol throughput Loss of key Loss of packets Fig 8 resulting in degraded Stratum Levels by office Packet data throughput and re transmission delays SS7 Networks Table 1 Effects of Frame Slips 1 4 Page 12 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 Since GPS based BITS systems are widely deployed End Office locations now enjoy the same Stratum Level as peer and Primary Offices However Network Synchronization does not end at the local Central Office End Office Strat Strat Strat Strat 1 1 1 1 Primary Regional Toll Tandem End Office Office Office Office Switches Channel Banks Fig 9 Stratum Levels on Par Network Synchronization Includes the Customer Loop As new services and bandwidth requirements increased T1 and fiber optic transmission systems were extended to customer locations The customer in turn connected terminal equipment of equal complexity often subscribing to service from multiple carriers In many cases ring based self healing fiber optic networks delive
51. andards and Technology is selected Therefore at regular intervals typically once week the PC sends an NTP query message to the NTP server requesting a Time Stamp If successful a message in middle of screen advises the exact time of the update and also displays the date time for the next scheduled query In this case the PC was updated 6 33 PM local time on 4 1 2009 and the next scheduled update will occur at 6 30 PM local time on 4 8 2009 Note you must check the box to automatically synchronize or you will have to manually click UPDATE NOW at regular intervals of your own choosing Date and Time Properties SSSSS__ _y Date amp Time Time Zone Internet Time i Automatically synchronize with an Internet time server Server time nistgqoy i Update Mow The time has been successfully synchronized with time nist gay on 4 1 2009 at 6 33 PM Next synchronization 4 8 2009 at 6 33 PM Synchronization can occur only when your computer is connected to the Internet Learn more about time synchronization in Help and Support Center Fig 25 Configuring Windows Client to Source a NIST NTP Server 1 9 It is notable that NTP has been around for a very long time but has only recently been more widely adopted deployed and utilized Over the past several years Network Providers have grown to rely heavily on NTP for time management of all critical network elements including call processor records for billing systems netwo
52. ation Links Rev 1 1 July 2009 1 8 NTP and IP type Outputs As discussed earlier TDM networks traditionally required only T1 E1 Composite Clock CC or similar synchronization links to Network Elements However it is also useful if some sort of reliable Time Stamp signal could be connected as this would become very useful when correlating alarm conditions across multiple Network Elements If the Network Element internal administrative clocks run free over time they will be a wide spread of accuracy between Network Elements Alarm events would appear to have occurred at different points in time The current preferred method for distributing Time Stamps is the Network Time Protocol NTP Utilization of NTP requires a host server and a remote client In the example shown below a PC is connected via Ethernet to a NTP server resident in a BITS system While this explanation is an oversimplification of NTP protocol the process works like this PC or remote Network Element sends NTP query to the server with a transmit Time Stamp server responds with multiple Time Stamps The query response contains information elements that allow the client to calculate round trip delay of the messages adjusting for the difference and yielding high accuracy as to actual time within milliseconds The PC repeats this process for as many times as necessary to establish the initial setting updating at specific periods once hour once day once week based on settings
53. avesetincndatetiardneamessiedintedeductecenssetdeseceaase 1 5 6 2 Protected Port MOG s si5 cn dcuieustsccaoelecetswadacibsraheiediedeaetnieate sens ieeeeswire L36 Protected Pull MOG sii sinns pocadientSeateendeatadinnsectadeenacdetes i Anasi beti 1 5 6 4 Timing Insertion Mode ccc cece cece cence eee e eee e eee e eee ee ee eeeeeeeeeeeeeeeeees 1 6 r eee ETA ee eee 1 8 1 1 8 2 1 8 3 BITS Distribution Shelves 0 c cece cece eee e cece cece eee e cece cece eee e eee e ee neey Sync Status Messaging SSM ccc esesceiseecnseceereennedandiacaaeteenwsseihsbiasaenenss SSM in SONET PDH NGtW OLS sen lt cunniwawsvenwnwtsoieceavaletondeemmenoereetsdaeceaees Network Time Protocol NTP wsnawsawes eine viensadesainendepaabethediaseunreetaeeessaan NTP in Personal OM pMlCi sis cccatcocwe ron idieatersioeoes eects lentiwacpsaaceteiasacaenedees IN TP Td CNG CPC er ecetecdocweee tess cee sidenote scGeaeeneeenadeetialaene Need tor Reliable Timo Stans vos sivetsnit eadesaewcasausiqucsasteneeninariansdoureeeses 1 8 3 1 Time Stamps for QoS in Pseudo Wire Emulation PWE Networks L84 LS Ssu 1 8 6 eee iB Eee LO iss LOA Le ces 1 9 6 LO ee 1 9 8 1 9 9 1 9 10 1 9 11 1 9 12 1 9 13 1 9 14 1 9 15 NTP and Simple Network Time Protocol SNTP cccccc cece eee eeeeees Deriving TDM Synchronization from NTP 0 cc cccc
54. b310 RITS Intelligent Timing Test Set to the CC signal at the Network Element Sync Input connection The Gb310 RITS is a portable multi purpose test set with special features for analyzing T1 El and CC BITS signals To power on instrument lift power switch toward top After configuring test set use the Single Circuit Testing Input male Bantam jack It is also suggested to connect a ground to the test instrument Configuration steps are shown below Fig 63 Gb310 RITS rj F LL Reference intelligent Timing System T1 2 i Single DS1 Pulse Error History A B a DRY Low Bat Facility Test Sy item Power Switch Single Circuit Test Input Male Bantam Timing Test Set Access Jacks 2 6 Page 65 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 4 1 2009 6 17 02 PH 1 At Power Up tap TIMING from the touch sensitive Main Menu area Cock w BROG Tip Ring w 00 2 The default is Composite j FREQ__Vpp T__uS_Deg_ ff Clock Bridged Tip Ring Input 00 While the Gb310 RITS is capable of measuring up to 10 simultaneous inputs we will view a single CC link AT A ETT lt help and tos I Y lock w BREG Tip Ringfoo FREQ___Vpp T__uS_ A 1 0 0 gt Ho dlor 2 3 4 5 6 T g 9 3 Tap the dropdown menu besi
55. bay location to the majority of Network Elements to be connected and the distance from the bay to an outdoor location where GPS antennas will be mounted Network GPS Elements Antennas Fig 33 BITS Location Planning The most labor intensive tasks associated with installation of a BITS system relate to installing antenna and antenna cabling running cables between BITS outputs and Network Elements Of the two antenna installation can be the most difficult so we will examine these issues first 1 9 7 GPS signals arrive at the antenna in the neighborhood of 125dBm which also happens to be near the upper range of sensitivity for GPS Receivers Most commercial GPS antennas feature 30dB of gain therefore the loss budget for antenna cabling is also around 30dB Antenna line loss varies by the size type and gauge of the cable For example coaxial RG 58U cabling burns through most of the 30dB loss budget with margin at around 100 feet This incorporates losses associated with connectors and insertion loss of the Lightning Arrestor and connections Therefore antenna runs longer than approximately 100 feet require lower loss cabling such as RG 213U LMR 400 or LMR 600 based on distance requirements Alternative schemes are available that utilize fiber optic cabling or frequency conversion units which allow longer runs of RG 58U up to 1 500 feet Page 35 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods
56. c Now The time has been successtully synchronized with 192 168 1 50 an 4 3 2009 at 6 31 FM Next synchronization 4 15 2009 at 6 31 PM Synchronization ean occur oniy wire four computor i corrected to tho Intemnet Leam more about time synchronization in Help and Support Center L ox J cce Ape Fig 55 Launch NTP Query from Test PC 2 4 If NTP query successful screen will update with new time and date of response If NTP query unsuccessful screen will not change However some Windows versions require the page be closed and reopened to display update SUCCESS 2 1 2 1 If the NTP query failed yet the NTP Server responds to a PING move the laptop PC to the NTP Server repeating the setup as for the direct PING test but launching the NTP query as shown above If the NTP query is successful use a Network Sniffer to sectionalize the Network as NTP packets are being filtered at some point Most Networks have multiple subnets routers and associated hardware Therefore you may have to move the Network Sniffer from the Test Laptop to other Network access points between the Test Laptop and NTP Server Your goal is to locate the point at which a captured NTP Server query is blocked in one direction or the other Page 57 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 GPS Antenna 192 168 1 50
57. c c cece cece eee eee e ee eennennaes BITS Composite Clock CC Output Signal Test Points 0 eee Hming Test Set Access JACKS 4420 siccwnsvineneistadecasdunenaniatancetetueientusetceoeds Test Set Connection at Network Equipment for CC Testing 008 Test Set Termination Options for CC Testing 0 cece ence eee eeeeeeeeeeeees Test Set Connection at DSX for CC Testing c cece cece cece eee e eee eees Page 4 of 106 Copyright 2009 dB Levels Inc All Rights Reserved dB levels Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 List of Figures continued Fig 67 Test Set Connection at BITS Shelf for CC Testing 0 ccc eee ee eee 74 Fig 68 Simultaneous Testing of 10 CC Circuits ccc cece cece eee cece ee ee en ennas 75 Fig 69 Remote Monitoring of CC Circults 0 cece ccc cc cece cece cece eee eeeeeeeeeeeaeeeen 17 Fig 70 BITS or PRS T1 E1 Output Signal Test Points nnnsnnnnnensensensensessnses 80 Fig 71 Test Set Connections for BITS TI E1 Signals cece cece eee eee e ees 80 Fig 72 Test Set Termination Options for T1 E1 testing 00 cece cece cece e eee eens 82 Fig 73 Test Set Connection at Network Element for T E1 Testing e eee 83 Fig 74 Test Set Connection at DSX for T E1 Testing cec
58. ccess points and cabling conventions Overall Synchronization Planning was thwarted by failure to properly connect all related Network Elements fueled by installations which did not follow strict standards Most locations adhered to some level of Synchronization Planning so the Network was generally stable for long periods of time Historically site technicians rarely needed to work on BITS so they possess little if any knowledge or understanding of neither the local BITS system nor its relevance to network troubles However as Network transmission rates and channel capacities have risen so also have outages related to Network Synchronization The implementation of Sync Status Messaging SSM on T1 and El timing links greatly increased reliability and complexity of Synchronization Planning and testing SSM provides a means for Network Elements downstream from the BITS to be aware of the traceability of the timing signal with a hierarchal system of coded messages Transmitted out of band on El and the Facility Data Link for T1 SSM allows Network Elements to follow an automatic pre determined process for selecting the timing source of the highest reference thereby eliminating outages due to timing failures Network Time Protocol NTP is now also widely implemented across carrier networks supported by little if any procedure for turn up and maintenance testing Currently site technicians lack 1 Test eq
59. cectaatiwamsstsoeeeeensgcseebeuteaseweerseersauss DSA Pano WIAD JI ESen iaraa NEE AE SONET PDH BITS Connections local end 0 0 0 00 cece eee c ence cee e eee eees lransport of BITS over SONET PDH iiciccciscaivancenctencnnncwabensiareganeanee dans SONET PDH BITS Connections remote end ccc cece cc cece cee eee eeeees SEEING Ain IN EP SES Eeee E E aa Successful PING of NTP Server ennnnesessssseccccessssssececcersesessecorocssssee Unsuccessful PING of NTP Server 0 ccc ccc cece cece cece eee eeeceeeseeneeeenes Testing Directly into NTP Server 0 cc cece cece cece cece cece cece eeeeeeeneeneeeaas setting IP Address Of Test PC we ssasancssnonssuvendsareesderdadieeweginewiialesvemenines Using Test PC laptop in Lieu of NTP Server for PING Testing Generating NTP Query from Test PC 0 cece cece cece cece cece eee eeeennes Network Sniffer Location Arrangement cc ceeeeeeee eee eeeeeeeeeeeeeee cece Network Sniffer NTP Query Trap cc cc cece cece eee e ence eee e eee eeeeeeeeeeeeens Network Sniffer NTP Response trap 0 ccc cece cece cece cece cece cece eee e eee ens Testing to Duel NTP Servers or PCS 0 ccc cece cece eee e eee e cece eeeeeeeeeeeees PC to NTP Server or PC NTP Delta Query ccc cece cece cece eee ence eee e ees Sectionalizing NTP Failures 0 0 ccc cece cece cece cc
60. ceeds BITS system limits 3 2 0 2 Use Volt Ohm Meter to measure CC cable between DSO DSX and Network Element for physical faults such as opens shorts or grounds If continuity good and no physical faults review allowable distance from BITS system to Network Element in BITS Users Manual If CC cable connected to multiple NEs remove one NE at a time to determine if one or more elements are shorted If CC signal fails tests at DSO DSX any readings display in red move on to Step 3 on next page Page 73 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 B Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 3 3 0 Step 3 Measure CC Signal at Testpoint A 3 3 0 1 Disconnect the cable to Network Element connect a GUISYS Model Gb310 RITS Intelligent Timing Test Set directly to the CC signal at the BITS shelf or closest terminating point to the BITS shelf Configure the test set as per Step 1 and set Termination for LIVE No GRD Ref Test Point Facility Test Sy item Single Circuit Test Input Male Bantam Fig 67 Test Set Connection at BITS Shelf for CC Test If the CC signal passes all tests all readings BLACK be sure to review both Vpp T and Vpp R the signal is usable for synchronization If the CC signal is useable at the BITS shelf Output but fails at the DSO DSX location probable causes e Mis wired DSO DSX jacks e Faulty cable between BITS she
61. de 00 and select 01 This will start the test process and you may hear beeps help and tips gt Page 66 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 Network Element CC Gb310 RITS iLL E MA Timing System 4 Use Bantam to Alligator Cable to tap onto the CC cable connection Insert Bantam plug into Single jack on Gb310 RITS as shown at right Connect ground cable from Ground terminal of test set to signal ground Facility Test System GUISYS Model GB10 RITS Intelligent Timing Test Set Fig 64 Test Set Connection at NE For CC Test Timing EE gda 3a Ph E w CCo v BROG w Tip Ring w 01 FREG Vpp R us_Deg_f i 6 amp 4003 0 3 300 1275 00 180 0 8 0 0 aor hho Clack 2 0 0 Mo Clock 0 0 Mo Chock 5 0 0 Ho Clock 0 0 m hho Chock f 0 0 Ho Clock amp 0 0 r Mo Clock Z 0 0 aa Meo Clock B10 0 0 Mo Clock heb and tips gt 5 A good CC signal will display characters in BLACK as shown at right The Gb310 RITS automatically measures all CC signal parameters and a RED reading signifies a FAILURE Page 67 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 3 1 0 2 NOTE ON TERMINATIO
62. e This includes traffic bearing T1 E1 circuits BITS System A OUTPUT Card 1 Port 1 S CoS R Intelligent Timing System we h ii A B DS1 Lowfat Facility Test System T1 E1 w SSM Portable GPS BITS clock Fig 80 Reference against a Temporary GPS source 2 8 Page 98 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 5 3 1 4 1 2009 6 11 02 PV 1 At Power Up tap TIMING from the touch sensitive Main Menu area 2 The default is Composite Clock but we will change this to T1 by tapping the dropdown menus beside CClock Select T1 or El then tap T1 TEST SYSTEM in lower portion of screen or El TEST SYSTEM if DS FA Test Chan DS I E Reference Set Ti Mode TERM Framing amp Codina dB levels selected S00 WU oo te Z2 051 MONITOR w ESF 051 TERM DSA 3 Tap the dropdown menu w B85 beside DS1 MONITOR and select the appropriate termination based on the drawing on the next BPW 96115 page After termination selected F Bit 2 eons g Den 2 sec tap Slip in lower left of screen CSU Emulation ESZ 2sec NOTE select proper termination from list below e If terminating a T1 E1 directly to the test set select TERM e If tapping onto a T1 E1 that is already terminated into a Network Element select BRDG e f plug
63. e cece cece eee eeeeeeeeeees IEEE 1588 v2 Precision Time Protocol PTP ccc ccc cece cece eee eee eens s BITS Installation COnsideraviOns sc06 oi ccveticusasserdateceusteeiwecekinesndacsseeucsieds TC iC a EEEE N E A E eases neucsidnitonnessubsdw E E Toe LOO esenea a E E DS IV CY A E TE E E E E EE E A Redundancy Rega ieme MS esrenesrorror cieri er e aa Physical BILS Shelf SINE eererisneinn r E E EE Amenia Cable OPON S sorone ree En EEE eNi AM SIRS a E E SEA a 20 RF Interference Considerations vu 515 c52 sdarnacaneeiwesieatemerueeuwiacesewlowwedesaveeads see bin IPT OVC CHONG naeuco nsec scan ange caseatandenediadenateeesendweatoutadaeddeoteidecsate Physical Placement of Lightning Protection Elements 00e eee eees BITS Output Cabling Guidelines 0 cc cece cece cece eee eeeeeeeeeaaaaes Connecting BITS Outputs to Network Elements cece cece eee eeeeees BITS Output Test Access Arrangement 0 cece ccccee eee ee cece eeeeeeeeenees Connecting BITS to SONET PDH Network Elements c cece cece ees Page 1 of 106 Copyright 2009 dB Levels Inc All Rights Reserved dB levels Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 Troubleshooting Section Timing and Synchronization Links dB levels Troubleshooting Network Time Protocol DAO sesirants Troubleshooting Timing links NTP
64. e cece een eeeeeeeees 86 Fig 75 Test Set Connection at BITS Shelf for TI EITesting eee 88 Fig 76 Simultaneous Testing of 10 TI E1 Circuits 0 e cece eee e cece eee e en ees 89 Fig 77 Remote Monitoring of 10 TI E1 Signals 0c ccc cece eee e eee eeeeeeeeeee ees 91 Fig 78 Reference Testing of T1 E1 Signals for Frame Slip Testing 008 92 Fig 79 Reference testing Multiple BITS Shelves for Frame Slips cece ees 95 Fig 80 Referencing against a Temporary GPS Signal for Frame Slip Testing 98 Fig 81 Testing Across a Network Element for Frame SIips cece cece eee e eee 101 Fig 82 Manipulating sending SSM for Single Network Element Testing 105 Fig 83 Manipulating sending SSM for SONET PDH Testing 00 cece eee 106 References 1 4 Stefano Bregni Synchronization of Digital Telecommunications Networks Wiley Press 2002 ISBN 0 71 61550 1 Chapter 4 Page 137 1 5 CXR Larus Getting it Right M Ritz Preso 1 7 Stefano Bregni Synchronization of Digital Telecommunications Networks Wiley Press 2002 ISBN 0 71 61550 1 Chapter 4 Page 185 1 71 David Mills Computer Network Time Synchronization The Network Time Protocol CRC Press 2006 Chapter 1 Pages 3 4 1 8 1 9 2 3 2 4 Microsoft Corp Windows Vista 1 92 CXR Larus QoS Measurements in PWE 1 93 CXR La
65. efault is Composite Clock but we will change this to T1 by tapping the dropdown menus beside CClock Select T1 EA u or E1 then tap T1 TEST DS1 B Referente SYSTEM in lower portion of l Set T1 Mode TERM screen or E1 TEST SYSTEM if Sei selected f 9 y Stei lt help ang tips gt a ESF DS1 TERM DSX v BSZS 3 Tap the dropdown menu beside DS1 MONITOR and select the appropriate termination based on the drawing on the next DROP amp INSERT BPW 96115 page After termination selected CSUYNIU Emulate P BIt 2 res Fractional T 1 Den 2 sec tap Slip in lower left of screen CSU Emulation ESZ 2sec NOTE select proper termination from list below e If terminating a T1 E1 directly to the test set select TERM e Iftapping onto a T1 E1 that is already terminated into a Network Element select BRDG e If plugging into a MON jack at DSX select MON Page 102 of 106 Copyright 2009 dB Levels Inc All Rights Reserved dB levels Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 The Gb310 RITS compares the input signal with the reference signal If the signals are both stable Slips will be zero 0 as shown at right above If Slips present Network Element is not configured properly to maintain synchronization on output ports w BERT L AUTO TEST Bits NO ERRORS Hz Slips 0 0 Dew 00H cas ET 0 1 144 Bee DS1T RMDSX w ES
66. ery amp Response 2 5 Page 59 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 The point of the preceding illustrations was that if the NTP query is never returned the packets must be traced from source all the way to destination Note the NTP query response contains Time Stamps which can aide also insure they are from your recent test packets The PING and NTP Query tests shown above are useful for ensuring NTP is passing through the IP Network However a couple other tests may help determine if an intermittent NTP failure exists especially if two or more NTP Servers are connected to the IP Network 2 1 2 3 Windows contains a program w32tm which is somewhat useful for ensuring a Network Element or PC can reach multiple NTP Servers or provide Strip Chart readouts for multiple Time Delta requests Our first example will display the delta between the host PC and two or more NTP servers 2 1 2 4 In a DOS window enter w32tm monitor computers xXxx Xxx X XX XXX XXX X XX then press Enter use valid addresses for the xxx Note there is a space preceding each and a comma between the computer addresses The result is a multiple output format which displays the round trip delay to each PC or NTP Server and delta of local clock to NTP clocks Note the NTP clock also identifies its source RefID C g
67. etwork Elements TO Makin piper dans VA MUA RUT CES CSS 2 eacaae cous metp set ossecseceawesasiuuneensnounee can E beste Single Network BICM ents s 05 5 enniveereedoastaiaciauseeieadddactoasudeweedesens PES UME SONE TPDH aoisean E EE NER List of Flow Charts FC duss PO vee PO eee FO Aisia FC 5 FC 6 FPO eee List of Tables List of Figures Fig 1 Fig 2 Fig 3 Fig 4 Fig 5 Fig 6 Fig 7 Fig 8 Fig 9 Fig 11 Fig 12 Fig 13 Troubleshooting BITS System Input Alarm 00 ccc cece eee e eee e eee e eee eeaes Troubleshooting GPS Antenna Circuit Failure c ccc ccc cece eee ee eee e Troubleshooting NTP Failure to All Network Elements NEs 605 Troubleshooting NTP Failure to Selective Network Elements 08 Troubleshooting BITS Composite Clock CC Signal Loss to NEs Troubleshooting BITS T1 E1 Signal Loss to NES 0 cece cece eee eee ee eens Troubleshooting Sync Status Messaging SSM ccceecceeeeeeeeseneeeeees IPCC S Ol tame SMG 5522 4 onc sasieesdesaciarohane daatenwattanencenatenascdtencees soneats BITS ipat POr canete ta een ctxt cnsteaaccatcreses aR ASEE ES BITS Output Cable Length Limits 0c cece ne eeeeeeeeeeeeeaenees Analysis of Composite Clock Failures ccc ccc cece cece cece ee eeeeeeennaenes T1 SSM Codes in Bittary AEX s2icssccerinieernesentacncecesns
68. fect on the SSM status of the BITS Input signals If the BITS Input SSM changes follow the BITS Output SSM changes a Timing Loop exists and must be corrected Page 104 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 6 3 1 BITS Frame Slip Test 1 Connect a GUISYS Model Gb310 RITS Intelligent Timing Test Set to all Output Ports on the BITS Distribution Shelf Record results for all outputs If any output fails determine if output is configured properly NOTE this can be quickly accomplished by utilizing an optional Multiple Input cable as the Gb319 RITS can qualify up to ten 10 inputs simultaneously 2 Perform Slip tests between at least one 1 port per card per shelf Correct any Slips prior to placing BITS into serve 7 0 Manufacturing Tests The Gb310 RITS Intelligent Timing Test Set can evaluate T1 E1 and Composite Clock CC signals providing direct SSM readout In the manufacturing community this is useful for validating such output signals and ensuring proper SSM codes are being sent from the Network Element under test Conversely the Gb310 RITS can emulate send T1 E1 signals with variable SSM codes allowing manufacturers to test Network Elements under simulated BITS degradation conditions Instructions for measuring BITS output signals and reading SSM codes are included previously in this publica
69. ferences from the normalized Tip to _ Upk T_ Ring view The acceptable range is 2 565 5 775 Volts 1 7653 Vpp R This is a measure of the peak to peak CC signals references from the normalized Ring to Tip view The acceptable range is 2 565 5 775 Volts pk R_ Jrad Under normal circumstances Vpp T and Vpp R are the only readings of interest However 1f either Vpp T or Vpp R are RED connect a ground cable to the Gb310 RITS and view the 4 _ Wpk T_ additional values shown at left to see if any are RED These are the 15714 base to peak readings and acceptable range for base to peak is 1 282 2 887 Volts Ypk K Again if all readings are BLACK the signal is acceptable for use 1 560 3 1 0 5 The likely causes of any RED readings are shown below RED Reading Likely Cause Additional Cause Frequency Freq Failing BITS Output Card Noisy or extended length CC cable to NE Voltages Vpp T etc Extended length faulty CC cable or multiple Failing BITS Output Card termination on cable BITS Shelf settings multiple BITS shelves l Tip Ring Mode 2 Ref CC Mode Table 4 Analysis of CC Failures Page 70 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 Rute Tso S 4132PmM ff w CClock LIYE Tip Ring 01 FREQ _ Vpp T__uS_ Deg_ 64000 0 22lf 125 00 180 0 Mo Clock aoe Mo
70. for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 Active antenna gain 30 dB 125 dBm Rx Sens Total losses wi A Madde ee 4 aan Gate Pe r can be no PPRT more than AMER 30 dB Cable Type 20 dB Loss 28 dB Loss RG58 70 feet 100 feet RG213 170 feet 240 feet Belden 9913 250 feet 350 feet LMR400 350 feet 490 feet LMR600 450 feet 630 feet LMR1700 1 000 feet 1 400 feet Fig 34 Antenna Loss Budget 1 95 Page 36 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels The larger size LMR cables can get quite expensive requiring special tools and skill for installing connectors At some point there is a cost advantage to installing a down up converter which will allow cheaper RG 58U cable runs of up to 1 500 feet Down UpConverter GPS Antenna L1 1 57 GHz ae Antenna LNA Down converter A MHz GPS data 16 MHz clock tone Si RG58 Coax cable lt 1 500 ft Up converter L1 1 57 GHz RG58 Coax cable 20 ft vas BITSIGPS receiver Fig 35 Down Up Converter 1 96 Since longer antenna runs tend to be pricy some companies economize by installing a single antenna splitting the signal at the receiver However this is extremely unwise as the antenna is the most likely element to fail over time One lightning strike would im
71. g Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig 14 15 16 17 18 PD ss 20 Z lies 22 255 24 2a 26 D fs 28 2D 30 31 32 33 34 Ja 36 Des 38 IJa 40 Al 42 43 44 45 46 47 48 49 50 51 D2 53 54 Do 56 IJa 58 59 60 61 62 63 64 65 66 BITS Clock Output w Failed Input 00 ccc c cece cece ence cece eee e eee e eee eeee eee Redundant BITS System ccc cece cece cece eee e eee e eee e eee e eee e eee eee eee e eee Unprotected Output Mode cece cece cece cece cence eee e ence cece eee e seen eee eeenes Protected Outp t Port Mod ats custocentoturcantenmmseemseiaeetindadadepesbiecniaduciense Protected Full Output Mode isss owwersnistuscneedeweeaasiasauuedusneeceseniestermiaaesees Retimer Mode Timing Insertion Unit 0 cece cece cece eee e cece cece eeeeeeees PRS Serving Multiple BITS Distribution Systems 0 cece cece eee eee eens BV ooo ie secre tears A ate sen canna ne iene tes en E E oo MOn 30 NIE PID Ie cian asabes ce i sinnir a EEE E NTP Client Server Example Query Response cccce cece cece eee eeeeeeeees Microsoft Windows NUP Sep xcorisncsarceatrasdastouseetedrsenkdevciaceucnsentaue
72. ging into a MON jack at DSX select MON Page 99 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 The Gb310 RITS compares the input signal with the reference signal If the signals are both stable Slips will be zero 0 as shown at right above If Slips present troubleshoot PRS and BITS system per previous Troubleshooting Flowcharts ay ET 0 06 57 w DS TERM BERT L_AUTO TEST Bits NO ERRORS H2 Sips 0 0 Dev 0 0H Alas ET 0 1 144 v DSITERMDS ESF ii I OCC Ce ote Bees BERT AUTO TEST J w Bits HE Slip 0 82 Dev 29H Page 100 of 106 Copyright 2009 dB Levels Inc All Rights Reserved dB levels Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 5 4 0 MUX Etc T1 E1 Payload T1 E1 Payload G 9310 RITS rj i i ye R ference intelligent Timing System Multi Channel Facility Test System Fig 81 Reference across a Network Element Page 101 of 106 Copyright 2009 dB Levels Inc All Rights Reserved dB levels Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 5 4 1 4 2009 6 11 02 FW 1 At Power Up tap TIMING from the touch sensitive Main Menu area 2 The d
73. he dropdown menu beside DS1 MONITOR and select the appropriate termination based on the drawing on the next page After termination selected tap Slip in lower left of screen DS 1 A Test Chan DS 1 B Reference Set TiMlode TERM Framing amp Coding DROP amp INSERT BPW 96115 CSUZNIU Emulate F Bit 2 Fractional T 1 z Den 2 sec CSU Emulation fEXZ 2 sec Page 93 of 106 Copyright 2009 dB Levels Inc All Rights Reserved dB levels Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rey 1 1 July 2009 NOTE select proper termination from list below If terminating a T1 E1 directly to the test set select TERM If tapping onto a T1 E1 that is already terminated into a Network Element select BRDG If plugging into a MON jack at DSX select MON do ET 00657 DSi TERMOSY ES GEE 7 BERT LAUTO TEST Bits EAR Insert Error NO ERRORS Hz Sips 0 0 Dev 0 0H The Gb310 RITS compares the input signal with the reference signal If the signals are both stable Slips will be zero 0 as shown at right above If Slips present BITS Output cards bad or not configured properly e ET 0 1144 051 TERM DSH TD BERT CLEAR NO ERRORS Hz Slips0 82 Dev 2 9Hz Page 94 of 106 Copyright 2009 dB Levels Inc All Rights Reserved dB levels Attachment 1 Methods for Ve
74. he hate lhe connections would be lap wrapped s Pa Non mielali ail N Ta These Polyphaser parte combine to be si rane pal cepeaa at a iis Equioment Pity About 10 68 we deep a pmen j CAR Lanes kit pin 0389 01525 0023 ee oe To antenna o earth ground point e Fig 39 Lightning Protection Connections 2 0 Page 41 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 1 9 11 Indoors or Outdoors Obviously the antennas are placed in an outdoor environment but what about the lightning protection kit Experts are split on two approaches install protection right at the point the antenna cable penetrates the building outside install protection at the nearest point the antenna cable enters the building inside Both concepts are radically opposed yet both agree that the point of entry or the wall through which the antenna cable passes is the right spot This stops the lightning surge from traversing all the way into the equipment room This will or course be governed by local ordinance codes and company policy Fig 40 Inside vs Outside 2 1 Page 42 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 1 9 12 BITS Output Cabling This section will explore the process f
75. he manufacturer s instructions local building codes must also be understood and applied The subject of grounding is very important and each site likely is equipped with appropriate grounding systems The building engineer should be consulted to locate the most appropriate grounding connection point for the antenna lightning arrestors If not appropriately installed these connections could introduce hazardous and destructive transient voltages into equipment ground circuits The point is you cannot merely grab any nearby ground lightning protection grounds are usually routed directly to the main ground buss away from normal equipment grounds Below is a typical lightning arrestor arrangement Note the Isolation Ground Adapter which actively ground the shield during a strike Someiras you will want the cable to eat hrough the back of the bow and heat THE go direcily mto the equipment ged maa TWC male amade TWC male Bs ie i z E ri a antenna equipment SURGE 2 PROTECTED SIDE j io o co I a H gE E z Isolated co ri Ground Eg 5 Adapter i ug aa agy ee el This is ihe copper surface thal musi be connacied 6 This shows thee allemala i earth ground and nat to power grownd green Mowing bracket ground ional ee oa ee eee wire The purpose of the non metallic jumchon a a eon box ta to keep 99 of the weather off the ia naii AE tha Polyphaser connections Incede the box K oft
76. he traffic bearing T1 E1 is re timed Therefore the T1 E1 bearer traffic is maintained but the Network Element is now synchronized with all other Network Elements connected directly to BITS To the Engineering purist re timer is a misnomer however it is the accepted term for this mode of synchronization The more correct term re synchronizer is just too clumsy Incoming Traffic bearing T1 E1 wi unknown sync NE with no external BITS port TIU Re Timed traffic bearing T1 E1 BITS OUTPUT Fig 19 Re timer Mode w Timing Insertion Unit Page 21 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 1 6 BITS Distribution Shelves In larger office locations a single Primary Reference Source PRS may provide Stratum 1 links to one or more BITS Distribution shelves Recall an earlier discussion that there are two configurations for BITS systems those with integrated GPS Receivers those with separate GPS Receivers Systems without GPS Receivers are referred to as BITS Distribution Shelves There is no need to install multiple sets of PRS in the same site so a large building can be surveyed placing BITS Distribution Shelves at strategic locations For example BITS Distributions Shelves may be installed on each floor of a multi story building or at distant e
77. hield The wire connects to a grounding point at the Network Element to eliminate noise and signals which may be couple to the cable In most cases the drain wire is not attached at the BITS end but is insulated with heat shrink tubing Unless dictated by local code or company policy it is not recommended that both ends be grounded as this will result in a ground loop that may actually cause more noise to be coupled to the inner wires When it comes to selection of wire types check the manufacturer s recommendations as they likely have tested their equipment with many cable types and best positioned to provide this information The distance limits shown above are for general planning and may vary based on the type of output cards installed However installing longer runs of cable than permitted will significantly degrade the signal which could lead to intermittent operation For existing installations this may pose a problem as the existing wiring may have been in place for many years In this case use of a test set to measure the quality and usefulness of the signal is in order This will be fully explained in the TROUBLESHOOTING section Page 43 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 1 9 13 Connecting BITS to Network Elements dB levels Multiple wiring schemes may be encountered when connecting cables
78. hment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 4 1 3 1 While the Gb310 RITS automatically displays the SSM in text advanced users may also desire to review the actual codes in binary or hex The tables below identify the appropriate codes for each SSM The SSM status of a source signal depends on the classification of the source generator For example a device classified as a Primary Reference Source has a differing set of criteria as a BITS Clock with internal GPS Receivers relating to the change status for SSM Generally speaking if a PRS or BITS Clock w GPS Receiver is warmed up it should be at Stratum Therefore for existing systems your expectation should always be Stratum 1 However the rules for SSM status change vary by class of elements so consult the User s Guide to determine the appropriate SSM for each condition loss of GPS etc Many Synchronization devices perform better than the standard so removing the GPS antenna on a system that is warmed will not cause an immediate change in SSM if the system can maintain Stratum 1 for a period without the GPS reference Consult the User s manual or manufacturer to determine proper test sequences for all Synchronization elements T1 Sync Status Message DS1 Data Link FDL Binary DS1 Data Link FDL HEX Table 5 SSM codes for T1 2 7 El Syne Status Message Sa Bit Message G 811 PRS Traceable CT o o
79. ispersion 12 0763 sec Reference Clock ID NULL Reference Clock Update Time Apr 13 2009 22 25 27 7813 UTC Originate Time Stamp NULL Receive Time Stamp NULL Transmit Time Stamp Apr 14 2009 00 19 39 1675 UTC fanaa AA FA en FN AN 462 AN AN alL rr aL FA AN AN Aar AA n kL a eeuef Expanding the NTP query response Line 17 14 1 Time Source Destination Protocol Info 28 110451 GemtekTe_56 7b 79 Broadcast who 28 112282 cCxrLarus_00 4a GemtekTe_56 7b 79 192 168 1 50 is at 00 50 c2 68 d0 4a Pa FS GEESE 192 168 1 50 192 168 1 100 NTP has 192 168 1 50 Tell 192 168 1 100 symmetric passive Frame Dea amp amp 17 90 bytes on wire 90 bytes captured Ethernet II Src CxrLarus_00 4a 00 50 c2 68 d0 4a Dst GemtekTe_56 7b 79 00 90 4b 56 7b 79 Internet Protocol Src 192 168 1 50 192 168 1 50 Dst 192 168 1 100 192 168 1 100 User Datagram Protocol Src Port ntp 123 Dst Port ntp 123 Network Time Protocol Flags Oxla Peer Peer Peer Root Root Clock Stratum primary reference 1 Polling Interval 10 1024 sec Clock Precision 0 000000 sec Delay 0 0000 sec Dispersion 0 0000 sec Reference Clock ID Global Positioning Service Reference Clock Update Time Apr 14 2009 00 19 40 1139 UTC Originate Time Stamp Apr 14 2009 00 19 39 1675 UTC Receive Time Stamp Apr 14 2009 00 19 40 1139 UTC Transmit Time Stamp Apr 14 2009 00 19 40 1139 UTC Fig 57 amp 58 NTP Qu
80. le signals viewed independently against the standard signal masks However even if the T1 E1 or Composite Clock CC signal meets the parametric measures it must still be examined against a reference to determine if it is truly in sync with similar synchronization signals of the same type The Introduction Section examined the need for synchronization of Network Elements timing slips are harmful to all transmission payloads Therefore several methods may be used to verify the stability of a timing signal e Reference against other signal from same BITS shelf e Reference against other signal not from the same BITS shelf e Reference against a temporary GPS source e Reference across the Network Element 5 1 0 Gb310 RIT 5 qt T1 E1 w SSM intelligent Timing System Output Card 1 Port 1 Multi Channe Output Card 2 Port 1 T1 E1 w SSM BITS OUTPUT Facility Test System Fig 78 Reference against other T1 E1 Signal from same BITS shelf Page 92 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 5 1 1 1 At Power Up tap TIMING from the touch sensitive Main Menu area 2 The default is Composite Clock but we will change this to T1 by tapping the dropdown menus beside CClock Select T1 or El then tap T1 TEST SYSTEM in lower portion of screen or El TEST SYSTEM if selected 3 Tap t
81. le to tap onto the T1 Elconnections Insert Bantam plug into DSI A RX Facility Test System jack on Gb310 RITS as shown at right Be sure test set input set to BRDG GUISYS Model GB10 RITS Intelligent Timing Test Set Fig 73 Test Set Connection at NE 5 Tap CLEAR then tap RESTART to restart T1 E1 analysis I or as BPW 96115 F Bit 2 1s Den 2 sec EX 2e Ee ET 0 00 06 6 If TI E1 is in spec and w DST TERMDSX w ESF Loopback v B25 table f NO ERRORS e T voi frequency and power level displayed at bottom of screen NO ERRORS I Gin 1544007 1He 05 d8D 5 6Vpp Page 83 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 4 1 3 Le ii i Auto Test User Patterns About DS1 7 To view Sync Status Messages SSM tap the DS1 tab at top of screen to reveal the OPTIONS menu Tap SSM MONITOR check ON and OK Ef on tap i for info gt A Slip 1544007 1Hz 0 5 dD 5 6 pp 8 The SSM is displayed in Binary HEX at bottom of screen but may also be viewed as text by tapping msg When viewing text switch to Binary HEX by tapping hex Fina OOOD0100 11111111 Ox04 hex Straturn 1 traceable Page 84 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attac
82. lf and DSO DSX e Distance to DSO DSX exceeds BITS system limits Use Volt Ohm Meter to measure CC cable between BITS shelf Output and DSO DSX for physical faults such as opens shorts or grounds If continuity good with no physical faults review allowable distance from BITS system to DSO DSX in BITS Users Manual If CC signal fails tests at BITS shelf Output Output Card is faulty or improperly configured Call NOC or review Users Manual for troubleshooting Output Card Page 74 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 3 4 0 Monitoring or testing multiple CC links simultaneously The GUISYS Model Gb310 RITS Intelligent Timing Test Set may also be used to monitor or test up to 10 CC links simultaneously This is extremely useful for commissioning a new BITS system or long term monitoring a site for intermittent failures To monitor multiple CC links the GUISYS Model Gb310 RITS Intelligent Timing Test Set may be connected to an optional cable with various connector arrangements Select the appropriate connector type and connect up to 10 CC links to the cable The Gb310 RITS can be configured to scan all 10 CC inputs continuously as shown on next page Gb310 RITS iF L i S Reference stem Up to 10 CC Links Facility Test System Fig 68 Simultaneous Testing up to 10 CC Signals Page 75 of 106
83. lol Network Sniffer BITS W NTP Server Router 192 168 1 1 Test Laptop Network Sniffer Fig 56 Suggested Network Sniffer Locations Page 58 of 106 Copyright 2009 dB Levels Inc All Rights Reserved dB levels Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels 2 1 2 2 Below are results of a standard Network Sniffer output Note the NTP query and response were both recorded at this test point as shown in Line Number 16 amp 17 Below is the outbound NTP query Line 16 which is expanded in the lower half of the display under the header Network Time Protocol No Time Source Destination Protocol Info 14 28 110451 GemtekTe_56 7b 79 Broadcast ARP 15 28 112282 cCxrLarus_00 4a GemtekTe_56 7b 79 ARP 16 28 112294 192 100 1 100 92 108 1 30 NTP has 192 168 1 50 7 Tell 192 168 1 100 168 1 50 is at 00 50 c2 68 d0 4a symmetric active DEHA amp Frame 16 90 bytes on wire 90 bytes captured Ethernet II Src GemtekTe_56 7b 79 00 90 4b 56 7b 79 Dst CxrLarus_00 4a 00 50 c2 68 d0 4a Internet Protocol Src 192 168 1 100 192 168 1 100 Dst 192 168 1 50 192 168 1 50 user Datagram Protocol Src Port ntp 123 Dst Port ntp 123 Network Time Protocol Flags Oxd9 Peer Clock Stratum unspecified or unavailable 0 Peer Polling Interval 10 1024 sec Peer Clock Precision 0 015625 sec Root Delay 0 0313 sec Root D
84. loss to the Network Element While this was standard practice over the years many companies now demand at least Protected Port Mode MUX etc T1 E1 w SSM Output Card 1 Port 1 BITS OUTPUT Fig 16 Unprotected Mode Page 18 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 1 5 6 2 As stated above most companies require single input Network Elements to be protected at least at the card level This means the primary output is coupled internally or via a Y cable to an output of the same type on an adjacent output card The outputs work as a pair with one working and the other in standby mode In event of failure the secondary card is quickly activated so that sync is maintained to the Network Element NOTE generally protected card arrangements must be configured in the BITS shelf with specific outputs assigned Some systems do offer automatic protection of cards without the need for Y cables Consult User s Manuals Also make sure the selected outputs are configured prior to connecting any Y cables or you will be shorting live outputs together which may result in card damage This is called Protected Port Mode MUX etc T1 E1 w SSM Output Card 1 Port 1 Output Card 2 Port 1 BITS OUTPUT Y Cable Fig 17 Protected Port Mode Page 19 of 10
85. lso may limit use of some of the w32tm applications To review all w32tm components at DOS prompt enter w32tm Page 61 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels 2 2 0 Scenario 2 NTP Failure to specific Elements In this scenario some but not all Network Elements are receiving NTP updates The same tests used previously PING and NTP Query will be employed to diagnose this trouble Troubleshooting NTP Failure NO NTP to Some NEs Start no NTP to sae etwork Elemen san you PING NJ server from failed Network Element Routing table probem in local router or address configuration problem in Network Element YES Vv l y Continue PING test of Use laptop PC to launch NTP request from NE location other Network Elements on same sub net as NTP Server If routing sub net problem will not be able to reach other NEs Use Network Sniffer to sectionalize Network NOp identify point at which NTP packets are filtered and dropped YES Network Elemenis not pointed properly to NTP server Reconfigure NTP settings in Network Elements Flow Chart 4 NTP Failure to Select NEs Page 62 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Ne
86. m the touch sensitive Main Menu area 2 The default is Composite Clock but we will change this to T1 by tapping the dropdown menus beside CClock Select T1 or E1 then tap T1 TEST SYSTEM in lower portion of an hea screen or El TEST SYSTEM if Set Ti Mode TERM selected While the Gb310 Fronning amp Coding RITS is capable of measuring up 9 to 10 simultaneous inputs we will view a single T1 E1 link 3 Tap the dropdown menu beside DS1 MONITOR and select the appropriate termination based on the drawing on the next DROP amp INSERT BPW 96115 page CSU MIU Emulate fF BIt 2 Fractional T 1 s Den 2 sec CSU Emulation EX 2 sec Page 81 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 4 1 1 BITS Set Gb310 RITS for THEI BRDG input Output p Network Element with terminated input BITS T1 E1 Set Gb310 RITS for Output TERM input Disconnected Network Element BITS T1 E1 Set Gb310 RITS for Output MON input DS1 DSX MON jack Fig 72 Test Set Termination Options for T1 E1 Page 82 of 106 Copyright 2009 dB Levels Inc All Rights Reserved dB levels Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 4 1 2 Network Element T1 E1 4 Use Bantam to Alligator Cab
87. mediately force the BITS system into holdover mode Think about it why would you spend the extra money to install two GPS Receivers two holdover oscillators and use redundant outputs yet bet the farm on just one antenna If the system is to be fully redundant install one antenna for each GPS Receiver Page 37 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 1 9 8 Antenna Siting The most critical step in BITS installations is careful selection of the antenna site If you get this wrong the BITS clock will be plagued by intermittent troubles for the life of the system While it is imperative to adhere strictly to the antenna cable loss budgets this will be for naught if the antenna is located in the presence of interfering signals or blocked from a clear view of the sky Basically the antennas need to be installed with no less than 30 feet of separation In fact use the most separation your cable length will allow The extra length could save one of the antennas in event of a lightning strike tree limb or vandalism shotgun blast etc Locating antennas away from public view is highly desirable The antennas should not be the highest object on the roofline Rather they should have a clear view of the sky with an angle of at least 45 degrees and also a view of the distant horizon if possible Use of conduits
88. ms TITL 64 Reply from 192 168 1 58 bytes 32 time 2ms TIL 64 Ping statistics for 192 168 1 5 Packets Sent 4 Received 4 Lost A loss Approximate round trip times in milli seconds Minimum ims Maximum 2ms Average ims GIN Fig 50 Successful PING of NTP Server If PING unsuccessful results will be similar to the screen below BC gt ping 192 168 1 50 Pinging 192 168 1 50 with 32 bytes of data Request timed out Request timed out Request timed out Request timed out Ping statistics for 192 168 1 50 Packets Sent 4 Received 0 Lost 4 100 loss C gt Fig 51 Unsuccessful PING of NTP Server Page 54 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 2 1 1 1 If the remote PING was unsuccessful connect the laptop PC directly to the NTP Server port This may require a SWAP Cable with TX RX transposed for older BITS Systems but modern version Ethernet Transceivers should be able to sense and correct TX RX if a straight thru cable is used GPS Antenna 192 168 1 100 192 168 1 50 RJ45 RJ45 Ethernet BITS Cable W NTP Server Fig 52 Direct Connection to NTP Server 2 1 1 2 Be sure the laptop is configured on the same subnet as the NTP Server address Set up the laptop as shown below Click Start gt Control Panel Click Netw
89. n you think of Timing think Time Stamps Synchronization then is a means for using a frequency reference to stabilize transmission equipment across a single or multiple locations Router Server Serial or Ethernet Timing Output Time stamp data Timing and sync Outputs T1 E1 w SSM Synchronization Output Frequency Reference SONET PDH MUX Fig 1 Timing vs Synchronization Page 7 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels In some cases Network Elements require connections for both Timing and Synchronization For example a Voice over IP Gateway needs to be synchronized on the TDM side yet requires Network Time Protocol NTP for accurate time stamping on the IP side Likewise a SONET PDH Node may require Synchronization for network traffic and NTP for accurate time stamping of events like alarms or status changes Ethernet VoIP HEE Gateway Timing Output Time Stamp Data For IP Side Timing and sync Outputs T1 E1 w SSM Synchronization Output Frequency Reference For TDM side Voice Switch Fig 2 Timing amp Synchronization Of Same Network Element 1 1 Allow this analogy to illustrate the difference between Timing and Synchronization If I ask you What time is it I d expect you to look at your watch and tell me the time
90. na il 28 F D FG ei EFP Ai He i a gt 14 os EI De Fi Ba i jam Heat De pI io nT itd fb t j 7 ie T ies ie amp 7 MF WF i LZ i Lf 5 L Eg tm B45 je ee Eb l LH ig LE d ii Zi Re EE ie i i 3 y l is kj eed ia j a j j gij E eh ajl it j i fem i A a E r Ei amp 1 AAt m 3 pi rA A in A A Ei a Fj PUTS Ft TIT ti hl a Sa bE CHE gD TG Aa Dl EH ES EG DG koug EEES EEE IE 4 dat Ba i CRR tol I 2 am g CH j i SSS SOSSSEH SSH SSSFS IS SST EAPS AEDS SSSHSS ASSES ESSEC ES OE GF zE rA aA roer onk TE Sar A A be ee A ee ee o E l ee ee ee ne n ii EL AE ae C Pi ai SHELDS m m 1 r F 1 aa F E H z y ky ak Lt MAFATU BY CUM OEN OE tA Fig 41 Wire Wrap Directly to BITS Shelf 2 2 Page 44 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 In addition to wire wrap some systems offer convenient connectors so that customers can install appropriate cables to test jacks or frame locations One popular connector is a 25 pair variety commonly found in the Telco world However with appropriate adapter you can also convert this connector to wire wrap as shown below Fig 42 Wire Wrap Adapter Page 45 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and
91. nce the NTP clock is more stable than the internal PC clock this number may vary slightly a few microseconds over time The default sample rate is every 2 seconds so if you set a long sample quantity of 50 the queries will continue for 100 seconds This provides multiple NTP samples over time for observing the Network Sniffer results CoNewse2tm stripchart computer 192 168 1 58 dataonly samples 18 Tracking 192 168 1 56 192 168 1 561 Collecting 186 samples The current time is 471372009 5 29 21 PM local time gt 17 239 00 868639745 ee HH 85750158 17 29 66 8576820 17 29 68 85722495 17 29 00 8576269 17 29 H 8571908 i7 29 H 8570998 H 7 29 66 856 7868s 17 29 H 85659575 17 29 06 85640658S Fig 60 Test for Delta to NTP Server or PC Host The results of this query can be analyzed in a couple ways firstly you want to see a good response every two seconds If a query fails the line will read error Therefore if you begin seeing successive or frequent errors then perhaps a network element is dropping some of the packets NOTE not all NTP Servers respond to this command consult Users Manual This program is also useful for comparing delta between two PCs 2 1 2 5 If you have no access to an NTP Server you may use w32tm with the NIST NTP Server at 192 43 244 18 but they do limit the number of successive queries so results may vary Other Internet based NTP Servers are available but a
92. nds of a large floorplan This will be determined by the number and type of BITS outputs required and the distance from the BITS shelf to the connected Network Elements This will be reviewed in greater detail in the section BITS Installation Considerations GPS Antennas DUAL GPS RECEIVERS PRS T1 E1 w SSM INPUT a INTERFACE clocks MANAGEMENT OUTPUT BITS A INPUT E apai INTERFACE clocks MANAGEMENT OUTPUT BITS B INPUT Ee INTERFACE clocks MANAGEMENT OUTPUT BITS C INPUT EE INTERFACE clocks MANAGEMENT OUTPUT BITS D Fig 20 PRS Serving Multiple BITS Distribution Shelves Page 22 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 1 7 Sync Status Messaging Sync Status Messaging SSM provides a means for Network Elements downstream from the BITS system to be alerted the Stratum Level of the timing signal With a system of coded messages transmitted out of band on a T1 ESF or El signal SSM allows Network Elements to follow an automatic pre determined process for selecting the timing source of the highest Stratum Level thereby eliminating outages due to timing failures For T1 ESF the Facility Data Link carriers the SSM codes as shown below SONET
93. nsider them as a whole The reason they are separate in large systems is that several distribution shelves may make use of the same GPS RECEIVERS The separate GPS RECEIVERS may also be labeled Primary Reference Source PRS as the literally are the primary source of Stratum 1 for the office Some PRS systems also contain their own holdover oscillator s apart from what may be in the BITS shelf Page 14 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB evels and Synchronization Links Rev 1 1 July 2009 1 5 2 The INPUT INTERFACE allows several types of signals to drive the system including single or dual GPS T1 El or Composite Clock CC and SMHz or 1OMHz from another BITS system or Stratum source However other than GPS all other input signals must be traceable to originate from a Stratum 1 source or equiv GPS T1 E1 w SSM INPUT INTERFACE CC 5 10 MHz Fig 12 BITS Clock Input Interface 1 5 3 The INPUT INTERFACE CLOCK and MANAGEMENT sections all work together to determine the best available reference for maintaining stable outputs with a default pecking order The priority list assumes GPS is reliable and the external T1 E1 or other signal is from reliable source While you may change the list in software typical default is 1 PRIORITY 2 PRIORITY 3 PRIORITY 4 PRIORITY
94. ntify troubleshoot and correct Network Synchronization and Timing troubles This must include practical examples for completion of required tasks analysis flowcharts and simplified overview of the concepts of Network Timing and Synchronization This white paper provides directions for connection of laptop PCs Network Sniffers and analysis of NTP links and also use of a timing test set analysis of test results corrective measures and installation guidelines for the three most widely used BITS timing link types worldwide 1 T1 with or without SSM 2 E1 with or without SSM 3 CC Composite Clock Benefit 1 This white paper will equip telecommunications site technicians to quickly evaluate the quality and usefulness of BITS timing signals with instructions for testing all the way to the Network Element and advanced troubleshooting of NTP related troubles This will result in significant reduction in restoral times for timing related outages and reduction of costly repeated chronic trouble reports Benefit 2 This white paper can be used to or serve as a guideline for establishing routine maintenance procedures that can reduce or eliminate potential timing related failures before they occur by introducing a method for remote long term monitoring of critical timing circuits Benefit 3 Lastly this white paper will provide a framework for testing of new Synchronization Plans as they are implemented ensu
95. olarity of the VOM leads NOTE The GPS Antenna is an active element requiring powering Many BITS system powering arrangements require that the antenna cable shield be isolated from ground for normal operation In event of a lightning strike the lightning protection elements will activate grounding the shield temorarily Check manufacturer recommendations as grounding the antenna shield permanently may cause a GPS Receiver failure Flow Chart 2 BITS Antenna Circuit Failure Page 51 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels 2 0 Troubleshooting Timing links NTP over IPv4 This section will provide instructions for troubleshooting Network Time Protocol NTP links As discussed in the Overview Section NTP provides accurate Time Stamps to any Network Element connected to an IP network However problems can be encountered during installation or anytime thereafter so the following steps will identify and eliminate 95 of failures 2 1 Scenario 1 NTP Failure to Network Elements In this scenario Network Elements are not receiving NTP updates Flowchart items below are more fully explained in the next several pages Troubleshooting NTP Failure NO NTP to NE Start NO NTP to etwork Elemen zan you PING N1 server from Network Element YES s NTP en
96. op shown below will be used only to determine if the assigned NTP Server address can be PING d from the distant Test Laptop If the 2 Laptop PC can be PING d but not the NTP Server when using the same address settings the trouble is in the NTP Server NOTE when configured with the same IP Address only the 2 Laptop or the NTP Server may be connected to the network but not at the same time as this would result in duplicate addressing 192 168 1 50 GPS Antenna 2 4 Laptop SS voles Fiber Switch MUX 192 168 1 24 192 168 1 83 J SS 192 168 1 1 192 168 1 100 Test Laptop Router VolP Gatway Fig 54 Using laptop in lieu of NTP Server for PING Test Page 56 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 2 1 2 STEP 2 Generate NTP Test Request If the NTP Server PING test results are satisfactory good response the next step is to generate a NTP query with the Test Laptop As explained in the Introduction Section most modern PC s have NTP Clients onboard which may be used to test the NTP Server Double Click Clock in lower right hand laptop display Click Internet Time tab Enter NTP Server address Click Update Now aS Date and Time Properties Date Time Time Zone Internet Tire ir automaticaly synchronize with an Internet time server Up
97. or connecting Network Elements to the BITS outputs Recall our earlier discussion that the Sync Plan should drive all requirements for connecting Network Elements provisioning links and ensuring no Timing Loops are constructed The Sync Plan should also yield an assignment record that instructs provisioning out each output designation of protected paths and CLLI code or other identifying code for the connected equipment Some BITS systems offer internal port assignment logs to maintain on site records However this information must be routinely updated or reliability will suffer as the network undergoes rearrangements For troubleshooting efforts nothing is more important than a record of output assignments on a per card basis As previously discussed each output type carries a set of requirements for staying within the useful range of proper operation While the main qualifier is cable length this can be greatly impacted by the size type and gauge of cabling used to connect the Network Elements Assuming proper cables installed typical distance limits are shown below eet Table 3 Output Limits For T1 E1 connections it is important to employ a suitable cable which is rated for T1 E1 signals Inexpensive fine gauge UTP will yield poor results The suggested cable is two conductor twisted pair shielded 22 gauge solid copper with a drain wire A drain wire is a bare solid copper wire that is wrapped tightly against but outside the s
98. ork Connections Right Click Local Area Connection in use Click Properties Highlight Internet Protocol TCP IP Click Properties Click Use the following IP address Enter new test IP address If directly connected to NTP Server use NTP Server address for Default gateway Click OK a ale a ae ae ala p gt internet Protocol TCP IP Properties fe Use the follo Prefered ONS server Altemate ONS server Fig 53 Setting Test PPC IP Address 2 3 Page 55 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 2 1 1 3 If you can PING the NTP Server when connected directly but cannot PING from a remote location it is likely that the IP address is duplicated on the network the IP address is invalid there is an address subnet issue or a router is blocking the address If you cannot PING the NTP Server even when directly connected the NTP Server is not configured properly If you desire to test the assigned NTP Server address you may want to configure a 2 laptop PC using the NTP Server address verify all settings with the network administrator including the proper Default Gateway Disconnect the Ethernet cable from the NTP Server port and connect it directly into the 2 Laptop PC as shown below This provides for a full test of all facilities up to the NTP Server In other words the 2 Lapt
99. r optimal reliability in the customer loop Therefore transmission systems beyond the local End Office must be included in Synchronization Planning GPS Antennas Central Office Customer Site Customer Site Fig 10 Sync of Customer Loops Page 13 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 1 5 Anatomy of a BITS Clock This overview will equip the reader with concepts of a Building Integrated Timing Supply BITS system Though BITS systems vary in complexity they really perform several simple tasks Here s a block drawing of a basic system Oa T GPS INPUT RECEIVER INTERFACE CLOCK MANAGEMENT OUTPUT PRS Fig 11 Basic BITS Clock 1 5 1 The GPS RECEIVER section contains one or two identical receiver units that provide power to the active GPS antenna decode signals from multiple GPS satellites and convert the data into reference signals and time stamps that will be distributed by various output ports The decoded GPS data and signals are first presented to the INPUT INTERFACE for further processing There are two configurations for BITS systems those with integrated GPS RECEIVERS those with separate GPS RECEIVERS Since even separated GPS RECEIVERS are usually mounted atop the BITS shelf we will co
100. rification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 5 2 0 BITS System A OUTPUT T1 E1 w SSM Card 1 Port 1 eee rd iit l es Card 4 Port 8 T1 E1 w SSM C BITS System B Facility Test System OUTPUT Fig 79 Reference against other T1 E1 Signal NOT from same BITS shelf 5 2 1 1 At Power Up tap TIMING from the touch sensitive Main Menu area Page 95 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 2 The default is Composite Clock but we will change this to T1 by tapping the dropdown menus beside CClock Select T1 PSA Test Chan or E1 then tap T1 TEST DEHE Referente SYSTEM in lower portion of Set T1Mode TERM screen or E1 TEST SYSTEM if romig E Coed selected 4 Ti Test System lt help and tips gt 3 Tap the dropdown menu beside DS1 MONITOR and select the appropriate termination based on the drawing on the next BPW 96115 page After termination selected F Bit 2 es ional s Den 2 sec tap Slip in lower left of screen CSU Emulation EXZ 2sec MO SIGNAL NOTE select proper termination from list below e If terminating a T1 E1 directly to the test set select TERM e If tapping onto a T1 E1 that is already terminated into a Network Element select BRDG e f
101. ring that the design objectives have been achieved in practice installation including recognition of timing loops which prove fatal to Network Operations July 2009 Implementation To achieve the deliverables in this white paper the end user company must acknowledge the identified deficiencies provide minimal to moderate funding of required test equipment review existing practice and procedure relating to BITS testing at the local site and finally condense and distribute the procedures herein inserting any additional safeguards required by your company Such additions may include escalation procedures authorizations for performing routine maintenance and safety procedures for wrist strap grounding where required This paper is not intended to supplant existing practice and procedure but can with permissions supplement or be incorporated into formal company documentation Summary Since deregulation of AT amp T in the 1980 s telecommunications networks have become interconnected islands of technology with no supreme arbiter to insure all the rules are obeyed As these interconnections span the globe carriers of all sizes can now impact overall network performance and reliability It is critical that every carrier develop a Synchronization Plan which fits well with the rest of the world ensuring reliable self healing transmission paths A key component then is to properly equip and train telecommunica
102. rk management devices including routers Ethernet switches and the management side of all switching and transmission systems Page 27 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 1 8 3 Need for Reliable Time Stamps While you may consider the PC clock to be a mild convenience consider the benefits of maintaining accuracy of the local clock Many clients PC programs make use of the time stamp for events such as email bank transactions stock purchases ebay activity etc Also Windows uses the clock to maintain files updates events so that if needed critical information can be retrieved to restore from a PC crash It really is best if you keep the clock current 1 8 3 1 The use of NTP has grown way beyond simple timekeeping for administrative and maintenance purposes Reliable Time Stamps form the basis for numerous Network Utilization and Performance measuring tools Customers now demand some form of proof for network performance such as availability throughput and latency Accurate Time Stamps are the key to delivering real time reports for network performance In the drawing below BITS systems Tiempo are used to supply T1 and NTP to appropriate Pseudo Wire Emulation PWE Network Elements PWE is the method for transporting TDM signals like T1 across a packet network
103. rus StarClock 6850 Grandmaster GPS NTP PTP Clock file photo 1 94 CXR Larus StarClock Tiempo 6400 Users Manual 1 95 CXR Larus Getting it Right M Ritz Preso 1 96 CXR Larus Getting it Right M Ritz Preso 1 97 2 0 2 1 CXR Larus Applications Note AN 96A RevA 21 May 2001 GPS Antenna Installation for Larus Timing Systems 1 98 CXR Larus file photo 1 99 CXR Larus lightning damage file photo 2 2 CXR Larus Starclock 200E Users Manual 2 5 WireShark Network Protocol Analyzer Ver 1 0 7 1998 2009 Gerald Combs 2 6 Guisys Corp Gb310 RITS Intelligent Timing Test Set all photos and Menus used with permission 2 7 Stefano Bregni Synchronization of Digital Telecommunications Networks Wiley Press 2002 ISBN 0 71 61550 1 Chapter 4 Page 182 183 2 8 CXR Larus StarClock 6800 Edge GPS NTP PTP Clock file Photo Page 5 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 Resources BOOKS Computer Network Time Synchronization The Network Time Protocol David L Mills CRC Press 2006 ISBN 0 8493 5805 1 e Synchronization of Digital Telecommunications Networks Stefano Bregni Wiley Press 2002 ISBN 0 71 61550 1 TIMING SYNC EQUIPMENT JOB AIDES TUTORIALS ETC e CXR Larus Corp 894 Faulstich Ct San Jose CA USA 95112 408 573 2700 www cxrlarus com CC T1 E1TIMING TE
104. ry and based on each companies synchronization philosophy Larger companies usually opt for dual antennas antenna cables GPS receivers and holdover oscillators employing Protected Card or Protected Full output redundancy For companies with SONET PDH networks placement of several non redundant clocks around the ring may eliminate the need for fully redundant systems at each site 1 9 5 Historically redundancy was thought of as ordering two of each critical component within the system proper However due to shrinking system footprints a new concept has emerged called Shelf Redundancy With Shelf Redundancy you order a non redundant system times 2 meaning you mount identical systems together achieving 100 redundancy down to the backplane You still have two antennas GPS receivers holdover oscillators and outputs they are just associated with completely separate shelves This arrangement is frequently lower cost that a fully loaded single shelf redundant system as newer technology offers significant improvements in cost per port as compared with older hardened designs Page 34 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 1 9 6 Where Planning and installing a BITS system into an office is a daunting task The two prime considerations relate to the distance from a proposed equipment rack
105. seesavaecatasecntaesauaers ELSSM Code igi ob erent ncea nena sum edied aoceemeeeocieea EEE ETEEN Timing vs Synchronization 0 cece cece cece eee eee eee eee eee e ee eeneeeeeeeeeneees Timing amp Synchronization of Network Element cece ee eeeeees ope OME PCM LDRK 06snsssreesiadseversstacestahetkemamnenes EAEE rn NEET Multiple POM LINKS aerrricissrisino to r oin E EARE E ea nii Synchronization of Multiple PCM Network Elements 0 ccc cccce eee eeees External Timing vs Loop Line Timing cece ccc ccc cece eee eeeeeeenees see eee Tal PIM AOA o226 snes oeniiss censdoateoeniwiescadundeeciane causa ben aanawoasneiart Stratum Levels by Office Hierarchy the old way ccceccceeeeeeeeeeeees Stratum Levels Now on PAR the new way cece cece cece cece cece ee eeeeeeees Fig 10 Synchronization Includes Customer LOops ccc cece eee e eee eeeeeeeeeeaes Aee ee MELO e PETE escraaaevece TE T E E ET ABIES Clock Inp t Interia CE snina aiaiai BITS Clock Output w Good Input 0c ccc cece eeeneeeeeaannaes Page 3 of 106 Copyright 2009 dB Levels Inc All Rights Reserved dB levels Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 List of Figures continued Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fi
106. serve as the inputs to the remote BITS shelf No GPS Receivers were installed into the far end the BITS is served by T1 s only Only T1 sync links are shown They provide only sync and do not carry customer traffic GPS Antennas BITS Clock BITS Clock LOCAL SITE DISTANT SITE Fig 47 Transport of BITS Signals Page 48 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 Note that pins A3 amp B3 are labeled BITS Output which would be utilized in cases where the SONET PDH systems was used to carry BITS timing off site to a distant location In this case the SONET PDH node at the distant site could be used to provide BITS timing to other equipment at that location At the distant site BITS Output 1 would pass on the T1 sync signal that was connected to BITS Input 1 at the near end where the SONET PDH Node is connected directly to the BITS system Likewise pins Al amp B1 at the distant site would pass on output the T1 sync signal that was connected to pins A2 amp B2 at the near end INPUT INTERFACE CLOCK CLOCK MANAGEMENT OUTPUT BITS input 2 positive BITS Ouiput 1 negative BITS Quipu 1 poolte i BITS input 1 negative t1 positive Fig 48 SONET PDH BITS Connections Distant End The above example was purposefully selected as it fully ill
107. t T a a ue CLOCK IH INPUT ALARM OT ETH HTP ToF e Fig 30 Modern Combination BITS NTP System 1 94 Page 32 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 1 9 BITS Installation Considerations This section provides an overview of basic considerations for typical BITS system installation at a site The need for BITS at a location should be driven by Network Planners utilizing an instrument called a Synchronization Plan or Sync Plan for short 1 9 1 The Sync Plan should be the guiding reference tool for all BITS installations decisioning of the BITS type size and redundancy connecting of Network Elements and management troubleshooting directives Routine maintenance of BITS output links does not require access to the Sync Plan Failed output cards or cables improper output configuration and basic BITS system analysis are pretty logical tasks If Lightning damages one of the antennas replace the antenna If an Output card fails replace output card However persistent unexplained troubles require a closer look at the entire synchronization strategy Frequent dropped calls sporadic errors in 56 64kbps DDS and or T1 E1 circuits bearer traffic issues on ISDN channels SS7 failures unexplained trunk failures and frequent multiple alarms are all indicators that synchronization problems exist 1 9 2 When cont
108. t w32tm monitor computers 192 43 244 18 72 18 205 156 192 43 244 18 192 43 244 18 ICHP 49ms delay NTP 3 25131ffs offset from local clock RefID ACTS 65 67 84 83 f2 18 205 156 72 18 205 156 ICHP 49ms delay NTP 3 2618376s offset from local clock RefID unknown 64 202 112 75 Fig 59 Test to Dual NTP Server The default number of PCs Servers that may be compared is 3 but if you append the command with threads lt number gt you can compare up to 50 systems This may be a useful tool for comparing the internal clocks on multiple PC s on a Network to determine if they are all referencing the same NTP source NOTE not all NTP Servers may respond to this command consult Users Manual Page 60 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 2 1 2 4 The second w32tm format we will examine is useful for conducting a longer test of NTP command responses For example this test may be appropriate when troubleshooting route path with a Network Sniffer as it can be launched in a mode which is repetitive providing a larger number of examples for tracing In a DOS window enter w32tm stripchart computer 192 168 1 50 dataonly samples 10 then press Enter Note there is a space preceding each The result is strip chart readout of the delta between the NTP clock and local PC clock Si
109. tachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 NTP is most accurate when multiple NTP servers are deployed One or two servers will source back to GPS and the remaining servers will poll each other This mesh configuration creates an extremely stable time reference system which may achieve nanosecond accuracy with redundancies to eliminate network outages GPS Antenna Servers Fig 28 Multiple NTP Servers X Qo Page 30 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 1 8 5 TDM Sync from an IP Based Network NTP may also be utilized to provide T1 E1 or other signals to locations where it is not possible or convenient to install an exterior GPS antenna First you must establish a site that will be GPS based and install a BITS system with NTP capabilities This will be termed a Grandmaster Clock At one or more remote sites a very small footprint Edge Client Edge BITS device accepts the NTP feed over Ethernet connection and converts the precision information into stable BITS outputs such as T1 El 1Pulse Per Second or 5 1OMHz The benefit of this arrangement is that the Grandmaster Clock is only moderately priced but the Edge Client devices are usually priced under 2 000 Therefore one Grandmaster can provide Stratum quality s
110. timekeeper so you may have noticed that over weeks or months the PC clock needs adjusted Look down into the bottom right corner of your PC screen and observe the time display If you have several PCs the time is likely to vary by several minutes or more However modern PCs now contain a small program which utilizes Network Time Protocol NTP for short which can constantly update the PC internal clock However for this program to work properly the PC must be connected to the Internet at least once per week so it can poll one of several NTP Servers If you double click the time display a window will appear titled Date and Time Properties Depending on the vintage of your PC WIN2K and previous are doubtful you should see three tabs one allows you to adjust the time and date a second let s you select the proper time zone and the third should be labeled Internet Time Date and Time Properties Date amp Time Time Zone Internet Time Time 6 30 40PM Pe Current time zone Central Daylight Time Fig 24 Windows NTP Setup 1 8 Page 26 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 1 8 2 Click on the Internet Time tab and you can select from a number of sites in a drop down window the NTP server of choice In this example the NTP server maintained by the US National Institute of St
111. tion The following instructions describe setups for emulating SSM into Network Elements under test e Simple Test Single Network Element e Advanced Test Validating SSM in SONET PDH Rings Gb310 RITS Gb310 RITS ej I ee 2 Gb310 RITS T11 costoarss Payload ate mn indall i Timing amp sa WCE Timing Ei Facility Teat System Input B Monitor Network Element behavior with SSM changes Emulate Generate dual T1 E1 with selectable SSM messages Measure T1 E1 Fig 82 Manipulating SSM for Single Network Element Page 105 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 7 1 Figure 82 above depicts manipulation and techniques for measuring results as various SSM messages are transmitted Fig 83 below depicts the setup for manipulating SSM messages on a SONE PDH ring network At the outset BITS Inputs A amp B would both be set to Stratum 1 After allowing the network to normalize BITS Input A would be changed to Do Not Use or any other code below Stratum 1 The Network Elements could all be polled to determine if they adjusted their timing to the BITS Input B on the opposite path 7 2 Intelliceert Timirg Svatem Gb310 RITS j i i re eg oy aime BITS Input A oe NE SS p Comms tb om O G T ps3
112. tions site technicians to adequately maintain timing and synchronization links at the local level If not services will be unreliable and noisy calls will be dropped Internet connections will slow and HDTV images will be irregularly pixilated ruining the quality so heavily touted by broadband connections Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 Table of Contents Overview Section Introduction to Timing amp Synchronization including NTP and SSM LO ak a ere Zes Leen 1 4 is ORF Pe eee es ee sic ae ee ee Le 1 5 6 so iming vs Synchronization c1crscunsecenataenieasesanearsetausassaeciosteriotawediccesd seg Wristwatch VS IMICTFONOING 2222220scscxancenanages seen cies senosdacanseteaasameseenenes ase Need for Synchronization in Networks 0 0 cceeee cece eee e eee eeeeeee eee ee eee eans How Synchronization Achieved ccccccccceee cess eee e eee e nent eee e eee ee nee e ens pos VIC SMAU LOVE la 252tocei sorserion EEan EAEE Anatomy of a BITS Cl0ck 0 ccc cece cece eee eeeneeeeeaeaaaaanaes OERS ROCCE reises kri En site caenandvesu ab EEEE R EE MUG MEIE esere EEEE AA SEEE Pa ine T een EEEE E A EE EEEE Holdover OSCINALOES sernir reirse nEn E EEEE BHS Clock Manas ement icci rccemect sanctus reuaiusases eo esiocesuranntasasswaasenesines BES OUUU erreen a a E A aa 1 35 06 Unprotected MOC oii cticnhwiessc
113. to BITS systems For many years wire wrap was the preferred method and many modern systems have maintained that feature The production system shown below has rows of familiar wire wrap pins for connecting up to 200 output cables R LATUS sTaARCLOCK 200 OUTPUT 54500 LIsT _ issue C i s pe mn al r a i gt ic j MG E ral oF ka F Taat il i a SS i al a J IM on EM se a Su mad ala i Fij cu ee eA EE al Ge Sg SPH ose aN Ht al Be ENA ie aJ e aN ya A ae H E a ai BE dj HE By ie j 5 m ai W Ej p H el Beit Se i i if amp Ji ad E ig Ss weer Heh PRS HBS BHF BOE BO Aho Me OS WA Od H Tagasi i E al i amp Li WY amp 3 t A RD jf ALUL NE g Hi a pJ H E anI g E ELN g 34 ferent week Been en ee 2erEeern Bees Be enh Be ea ween _ RGH u Wo a fh me et ee eM oy oe pH Seay bt ab wh eM Be eH Mt BS we eji S x 14 yo in E amp H iF 7 e OF fee yt EN y HT ub amp 7 y tT w mer A 7 in li te wee eth He eSB He PHBH ee wee eR nyt et wee eh ws eB we es a lz H T ai W e ei ye an yer ee es Pee ib e gy e eo we ee le E 7i lE aan goap jaan Teen ijae heen jaa Ha eH jle 7 jia tHg li Tyee piel Ja oT Deb yea ek Oe Hm aN ee Mn myar mwya ot 1 PRs Bas TT eae in aT ies laar Ne Ha al e wt De SF Be yT i Rad dea eae ef go oS 4 oe et Bet kta at amp uE gi al Qe ot be a oo Reed we el wee 2 Bt oN eed e 0 Eo aG ae wD oe el is eo j 1 bts i E p gr n E a eat 1 oes Ep j t HH pa gn fs Ai 7s el S i 5
114. twork Timing and Synchronization Links Rev 1 1 July 2009 dB levels GPS Antenna oe Fiber 192 168 1 50 Switch ac oa Good NTP Good NTP BITS W NTP Server Good NTP Good NTP VolP Router 5 Gatway SS aa Fiber E NO NTP MUX Network Router Sniffer Fig 61 Sectionalizing NTP Failures 2 2 1 As shown above the Network topology must be carefully scrutinized to determine if an entire segment is isolated from NTP or if the fault is restricted to only a few Network Elements The best method for locating this fault is to employ the PING and NTP Query tests as discussed in Scenario 1 using a Network Sniffer to locate the point in which the NTP Packets are being filtered and dropped Page 63 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 3 0 Troubleshooting Composite Clock CC Synchronization Links The flowchart below provides the basic direction for responding to a BITS Composite Clock CC failure to an existing Network Element This process is also useful for validating a new CC link connection Detailed steps for this flowchart appear on the following pages 3 0 1 Troubleshooting BITS CC signal loss to Network Element CC signal acceptable NO y See Troubleshooting Trace CC cable back to BITS Shelf DSX panel or BITS shelf Retest CC signal i
115. uipment to properly evaluate BITS output signals including readout of critical SSM codes for T1 and E1 signals 2 Procedures for testing BITS and NTP output links 3 Training to quickly identify Network Timing and Synchronization problems Previous Options The common fall back method has been to closely monitor alarms in the July 2009 BITS equipment at the System Level with hopes that individual timing output troubles could be detected at the higher level However this is often not the case Modern GPS based Network Synchronization Systems do provide alarm monitoring to determine overall system operation quality and usefulness of the GPS signal status of antenna cables and antenna operation and a limited number of output related faults such as shorted output cables Troubleshooting methods were generally directed from a distant Network Operations Center NOC with the local site technician performing eyes and ears function for the NOC engineer Cards could be swapped LEDs viewed for activity etc However at some point the NOC engineer must direct the site technician to perform physical maintenance activity such as cable testing tracing and Network Element connection verification At this point the local technician was very limited in availability of tools and training Recommended Solution The solution is to provide telecommunications site technicians with tools and information procedures to ide
116. ustrates the need for careful review of the User s Manual and Input Output pins prior to connecting BITS cables to the Network Equipment Itis very easy to see the BITS label and assume pins A1 amp B1 are the BITS input However that would be connecting a live BITS cable onto pins that themselves are outputting a live T1 signal NOTE this example is one of them most common errors when connecting BITS cables to Network Elements This concludes the Overview Section Page 49 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing and Synchronization Links Rev 1 1 July 2009 dB levels Troubleshooting BITS System Input Alarms Start BITS alarm report Is this an input alarm YES Is this a GPS receive alarm YES y Log into BITS system Test for antenna status Is antenna circuit good YES v Review signal strength and usable satellites detected signal strength and few satallites detected YES y Antenna cable too long damaged faulty antenna or antenna in wrong location Check for potential sources of nearby RF interference to antenna Avoid placing antenna near wide metal surfaces NOP If antenna alarm see Troubleshooting BITS Antenna Circuit For all other alarms consult users manuals or NOC for actions NOP
117. ynchronization signals to a dozen or more end locations served only by your internal Ethernet network GPS Antenna Edge Client Edge Clien Edge BITS Edge BITS hy hre nL Ethernet Grandmaster Edge Client Edge Client Edge BITS Edge BITS T1 E1BITS Signal Fig 29 NTP to BITS via Ethernet 1 93 Page 31 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment I Methods for Verification of Network Timing dB Jevels and Synchronization Links Rev 1 1 July 2009 1 8 6 Additional Packet Based Timing While NTP has been employed over two decades and more widely adopted in recent years another emerging protocol is shouldering its way to the front of the line EEE 1588 v2 PTP is nearing completion and already deployed in some form As with any cutting edge technology 1588 Precision Time Protocol continues to be refined and improved based on real world results The decision of which time protocol to use will be based on the current and future design of you IP network NTP may be utilized in almost any network configuration that meets minimal guidelines However 1588 requires some additional network topologies and performance enhancements already are in place such as QoS Therefore significant improvements may be required for existing networks However when developing a new network such issues will likely be mute Timing and Synchronization vendors will gladly assist in reviewing
118. ystem The most commonly used commands analyze the integrity of the antenna circuit for proper operation display the number of GPS satellites seen and the value of the received signals for timing purposes the length of time the system has remained at Stratum 1 and other critical issues like condition and status of holdover oscillators Page 17 of 106 Copyright 2009 dB Levels Inc All Rights Reserved Attachment 1 Methods for Verification of Network Timing dB levels and Synchronization Links Rev 1 1 July 2009 1 5 6 Finally the OUTPUT section provides physical access for connecting jumpers or cables to each connected Network Element The outputs generally have been wire wrap pins but a variety of modular connector types are in use including individual female RJ45 or BNC connectors There is a very wide variety of output types including T1 E1 Composite Clock CC 5 10MHz 2 048 MHz square wave RS422 1 5MHz RS422 8KHz 1PPS IRIG B NTP PTP and more How do you know which output is right for each Network Element Consult the user s manual There are four ways to connect Network Equipment to the BITS system Unprotected Protected Port Protected Full and Timing Insertion 1 5 6 1 Unprotected Mode means that the Network Element has only one Sync Input connector Channel Bank for example and does not warrant redundant card protection In this case an output card sync cable or Sync Input failure would result in sync

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