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CMX7164 Multi Mode Modem

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1. Figure 34 Channel Filtered UO Figure 35 Channel Filtered UO Signals Signals with UO DC Offset Estimate Note The images of receive diagnostic modes shown above are idealised In practice when using the I Output and Q Output signals to view diagnostics the transitions between constellation point are not instantaneous Using an analogue oscilloscope is the best way to observe these diagnostic signals See e 13 1 18 Modem Mode and Control 6B write 13 1 10 Signal Control 61 write 2015 CML Microsystems Plc Page 46 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 First FM Demodulator output 7164F1 6 x only A test mode to examine the FM demodulated signal is provided this utilises the IOUTPUTP N pins to produce a diagnostic output signal The diagnostic signal is produced by channel filtering the UO input signals FM demodulating the result and applying a low pass filter This reproduces the FFSK tones WI so0mv amp Ch2 soomV M ms Chi 7 smv Figure 36 Received Signal First FM Demodulator 7164F1 6 x 2015 CML Microsystems Plc Page 47 D 7164_FI 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Rx Eye Diagram Second FM Demodulator output 7164FI 6 x only A test mode to examine the second FM demodulated signal is provided this utilises the QOUTPUTP N pins to produce a diagnostic outp
2. 10 12 14 16 18 20 22 24 26 28 30 32 34 Signal to Noise Ratio dB Figure 73 Signal to Noise Performance Comparison of uncoded raw 4 FSK 8 FSK and 16 FSK 9 6 2 2 Co channel Performance The co channel rejection ratio Figure 76 is measured with an interferer modulated with 400Hz FM and having a deviation of 1 5kHz which is 12 of the nominal 12 5kHz channel bandwidth This particular interfering signal is used as it is specified in ETSI standard EN 300 113 for co channel tests The measurement uses wanted signal levels of 95dBm 8 FSK and 90dBm 16 FSK as required by EN 300 113 9 6 2 3 Coding Performance The performance of the 8 FSK and 16 FSK coding modes is shown in Figure 74 and Figure 75 The high rate coding mode gives adequate performance in a static channel AWGN but the low rate code gives much better performance in a faded channel Figure 75 Best performance particularly in faded channels is achieved with the largest block size block size 3 Typical Block Error Rate with the smallest block size 12 bytes is shown in Figure 77 2015 CML Microsystems Plc Page 96 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 8 FSK High rate code Block size 3 8 FSK Low rate code Block size 3 te 4FSK Uncoded H 8 FSK Uncoded i 16 FSK High rate code Block size 0 0 01 BER 0 001 0 0001 0 00001 10
3. i I I I I KS ac i Ke ONG erect el LNA Enable XL CMX7164 I Vee ped 1 1 eren I Danei GPIO Tx Rx NS x Q9 I Input ot LNA Lo 2 x ADC C BUS Q Q Input i CMX992 A Thru C BUS Local Oscillator PA Gain Control RAMDAC un I Aux DACO 2x DAG E ry A Directional Power x Coupler Amplifier L I Output at S O Output XO E zl i 90 Local Oscillato EN Q CMX998 Figure 56 Outline Radio Design UO in out for 2 or 4 FSK Use of UO receive mode brings with it the problem of I Q dc offsets There are dc offsets caused by the radio receiver resulting in the signal into the CMX7164 having a dc offset other than BIAS The offset needs to be removed prior to demodulation Offsets typically remain constant for a particular radio frequency selected but will vary if that frequency is changed Gain within the radio receiver may also affect the dc offset seen by the CMX7164 UO dc offset effects are a radio issue which is beyond the control of the CMX7164 However the CMX7164 does provide dc offset calculation and removal These are described in detail in the application note section 15 3 DC Offsets in UO Receivers 6 CMX998 is a Cartesian Feedback Loop Transmitter which is designed primarily for non constant envelope modulations such as QAM although it will also support GMSK
4. 0 SYMBOLS 4 Figure 51 Tx Modulation Spectra GMSK 8kbps BTz0 3 Two point Modulation 2015 CML Microsystems Plc Page 69 D 7164 Fl 1 x Fl 2 x F1 4 x F1 6 x 22 CMX7164 Multi Mode Modem CMX7164 8 5 7164Fl 1 x Typical Receive Performance The performance of the receiver will be different for any combination of bit rate and deviation To aid the designer some typical performance data has been measured using a realistic UO receiver 8 5 1 Signal to Noise and Co channel Performance The performance of the 7164F1 1 x when receiving is illustrated by the graphs shown in Figure 52 Figure 53 and Figure 54 It should be noted that error rate performance depends on the modulation rate deviation and BT results have been taken for typical channel bandwidths The 7164Fl 1 x supports multiple combinations of these factors but it is beyond the scope of this document to provide data for every combination Data is provided showing a selection of representative cases ranging from best case performance with coding to worst case where no coding is used raw mode plus the effect of using different BT values In the following graphs the modulation is GMSK and the data rate is dependent on channel bandwidth The 25kHz channel data rate is 9 6ksymbols s the 12 5kHz channel data rate is 8ksymbols s which is typical of the rate that may be achieved in each RF channel The signal to noise ratio is calculated as SNR Mean signal powe
5. Figure 64 Tx Modulation Spectra 8 FSK 9 6k symbols s 28 8kbps UO Modulation 2015 CML Microsystems Plc Page 87 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 RBW 500 Hz RF Att 30 dB Ref Lvl 11 56 dBm VEW 2 kHz D dBm 448 00219188 MHz SWT 1 35 s Unit dBm 0 Val er 11 56 Modulation 448 00219188 MHz Spectrum 20 CH PWR 65 ACP Up 72 69 20 ACP Lo 72 84 30 1RM 40 50 60 70 80 cul co 90 co 11 100 Center 448 MHz 6 6 kHz Span 66 kHz COO 2 6971 370 000 Eye Diagram 1 sym Figure 65 Tx Modulation Spectra 16 FSK 9 6k symbols s 38 4kbps UO Modulation 2015 CML Microsystems Plc Page 88 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Spectrum Analyser Vector Signal Analyser Creme IOUTPUT Mod1 or QOUTPUT Mod2 i CMX7164 EE RF Signal Generator DC FM Modulation Input Buffer Amplifier if required to drive RF signal generator modulation input Figure 66 Tx Spectrum and Modulation Measurement Configuration for Two point Modulation Using the test system shown in Figure 66 the 7164F1 2 x internal PRBS generator was used to modulate the RF FM signal generator Some typical results are shown in the following figures The desired deviation
6. Si ROS Frame sync Data Payload E Normal AGC operation reacts to M Timer expires Either small signals by framesync detected So increasing gain AGC behaves based on clipping and large Timer starts to count iv Full Auto Lock on FS or signals result in down when detect If timer gt allow high time AGC Down After FS decreasing gain threshold is met and signal gt high selection or a false threshold then backoff detect so continue running AGC normally Figure 41 AGC Behaviour During Burst Reception A general issue with I Q receivers is that of dc offsets Offsets are generated by the receiver hardware and typically vary with channel selection but depending on receiver architecture can also change with gain The CMX7164 is capable of calculating I Q dc offset corrections but if the gain steps suddenly and therefore the dc offset changes suddenly errors may occur Once again this may only be an issue for longer bursts when it is necessary to change gain during reception To overcome the dc offset issue the CMX7164 allows an I Q dc offset correction to be latched in for each AGC gain step When a gain step other than maximum gain is selected the tabulated dc offset correction will become active and tracking will be suspended Additionally in receivers with large dc offsets present a gain change may result in a sufficiently large step in dc offset that the signal will look small large to the AGC algorithm resulting i
7. 1 00E 06 22 0 24 0 26 0 28 0 30 0 32 0 340 36 0 38 0 40 0 420 Signal To Noise Ratio dB Figure 80 16 FSK Signal to Noise Performance Equalised and Non Equalised 2015 CML Microsystems Plc Page 102 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 1 00E 01 994 no equaliser 994 with equaliser 1 00E 02 BER 1 00E 03 1 00E 04 40 20 0 20 40 60 80 Temperature deg C Figure 81 Performance of Equalised Signals with Temperature Variation Tests were carried out using modulation with a signal to noise ratio of 13dB using the EV9942 CMX994 with temperature compensated baseband filter BER performance was measured with and without equalisation being applied then the temperature was varied and the equalised and non equalised bit error rate measurements repeated The results are shown in Figure 81 The results show that equaliser performance is maintained across the full operating temperature range For all results the frequency error between transmitter and receiver was less than 100Hz 2015 CML Microsystems Plc Page 103 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 10 7164Fl 4 x Features The 7164Fl 4 x uses a QAM modulation scheme switchable between 4 16 and 64 QAM on a burst by burst basis The symbol rate is configurable up to 20ksymbols s resulting in 106 000 user bits per second maximum
8. ssss 80 Table 6 Native Formatted Block Types Sizes and Rates for 16 FSK Fl 2 x 81 Table 7 RD LAP Block Types Sizes and Rates Fl 2 x sse 83 Table 8 Formatted Block Types Sizes and Rates Fl 4 x e 106 Table 9 ACR Rejection Performance eene nennen nennen nennen nennen 119 Figure Page Figure 1 Overall Block Diagram sss sees eee eree eee eee ee 12 Figure 2 Fl 4 x Block Diagram UO Tx and RX sese ee 14 Figure 3 Fl 1 x Fl 2 x Block Diagram UO Tx and Rx 14 Figure 4 Fl 1 x Fl 2 x Block Diagram two point Tx with WOH 14 Figure 5 Fl 6 x Block Diagram UO Tx and Px 15 Figure 6 Fl 6 x Block Diagram Two point Tx with UO HRS sese ee ee eee 15 Figure 7 CMX7164 Power Supply and De coupling seen 19 Figure 8 Recommended External Components Xtal Interface 20 Figure 9 Recommended External Components C BUS Intertace sss 20 Figure 10 Recommended External Components UO Output Reconstruction Filter 21 Figure TT CMX7164 VO Tx VQ FX eae tree aree tee t nae ee nea een ene nen 23 Figure 12 CMX7164 Two point Tx l Q Rx enne nnne nennen nnns nennen 24 Figure 13 Basic C BUS Transactions sees 26 Figure 14 C BUS Data Streaming Operation 27 2015 CML Microsystems Plc Page 6 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure
9. 2015 CML Microsystems Plc Page 67 D 7164 Fl 1 x Fl 2 x F1 4 x F1 6 x 22 CMX7164 Multi Mode Modem CMX7164 Spectrum Analyser Vector Signal Analyser Creme IOUTPUT Mod1 or QOUTPUT Mod2 i CMX7164 EE RF Signal Generator DC FM Modulation Input Buffer Amplifier if required to drive RF signal generator modulation input Figure 50 Tx Spectrum and Modulation Measurement Configuration for Two point Modulation Using the test system shown in Figure 50 the 7164FI 1 x internal PRBS generator was used to modulate the RF FM signal generator Some typical results are shown in the following figures The desired deviation was achieved by adjusting the deviation control in the RF signal generator 2015 CML Microsystems Plc Page 68 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 RBW 200 Hz RF Att 20 dB Ref Lvl 22 95 dBm VBW 1 kHz Mixer 20 diBm 0 dBm 448 00095892 MHZ SWT 4 2 S Unit dBm 10 odulation Spectrum N 300 113 Adjacent Channel easurement for 12 5kHz annel AGP 69dB 50 Integration window 8kHz 60 eak deviation 1 symbol P OkHz 90E Center 448 MHZ 3 3 kHz Span 33 kHz cr 448 MHz Meas Signal Ref Lvl SR 8 kHz Eye I 0 dem Demod 2FSK Eye Diagram
10. 2015 CML Microsystems Plc Page 118 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 the wanted signal is raised above the sensitivity limit and where the reference is taken The figures quoted here are based on the measurement method from EN 300 113 which tends to give lower figures than some other methods In these tests the adjacent channel signal is close to the maximum input signal amplitude allowed by the 7164F1 4 x The figures quoted in Table 9 are based on the difference between the interferer 400Hz FM modulation 3kHz deviation and the mean power of the wanted signal for less than 2096 PER 182 byte packets for 18ksymbols s It has been observed that adjacent channel rejection is limited by the headroom offered by the UO Inputs above the sensitivity level of the input signal This means that when the adjacent channel interferer reaches the maximum allowed input level of the I Q Inputs a rapid transition from almost zero BER to a large BER is observed Given the relative sensitivity levels of the 4 QAM 16 QAM and 64 QAM signals the result is a measured adjacent channel rejection of Table 9 ACR Rejection Performance 4 QAM 16 QAM 64 QAM Raw Data 62dB less than 1e 3 550B less than 1e 3 48dB less than 1e 3 BER BER BER Formaited Block Type 0 65dB for 6 PER 62dB 0 PER 58dB 19 PER Formatted Block Type 6 65dB for 0 PER 62dB 0 PER 58dB 0 PER Formaited Block Type 7
11. 4 e Added details of default and inverting gains to the description of the UO Output 3 8 11 Control 5D 5E registers e Pointed out correct use of handshaking when using signal control Register 61 to select and Q offset measurements Registers 75 and 76 e Clarified behaviour of the and Q offset registers Rx dc offset correction when using automatic Rx IQ dc mode e Clarified behaviour and scaling of RSSI measurements e Documented further AGC controls added in Fl 4 0 5 4 and described AGC operation in detail e Documented the PII On bit added to the mode register in Fl 4 0 5 4 which provides a fast idle mode for programming register modifications without powersave but with improved speed e Added parameters in Program Block 1 to reduce delay when transitioning from Idle to Tx or Rx modes e Added information about receive dynamic range e Corrected and clarified scaling of Tx output fine control 2015 CML Microsystems Plc Page 11 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 3 e Remove information indicating that a reset with no FI load is possible See 15 4 11 sections 11 1 1 Reset Operations 7 3 Function image loading e FIFO level interrupts to the host require re arming using 50 FIFO control See 11 1 4 FIFO Control 50 e Include description for HO Input dc correction loop gain See 11 1 10 Signal control 61 e Spectrum figure ACP mislabeled as for 25kHz when it i
12. GPIO Figure 39 AGC using SPI Thru Port 2015 CML Microsystems Plc Page 54 D 7164 Fl 1 x Fl 2 x F1 4 x F1 6 x 22 CMX7164 Multi Mode Modem CMX7164 HOST uP vi 3E CX CMX7164 RF Receiver IC e g CMX970 CMX972 CMX973 I Input Mm x BJ K c QI L T R Clip Level Sense Ce X LNA E s N VA Input ON OFF L E S raia Local Oscillator Baseband Gain Local Oscillator IF Control Register AGC Gain Step SPI Thru Port K C BUS Control gt Select Registers C BUS control of external device GPIO k Figure 40 AGC using SPI Thru Port and external LNA Note The external LNA control feature of the CMX7164 may be useful where an RF device does not provide an LNA control output like that available in the CMX991 or CMX992 An example of where CMX7164 control would be necessary is a receiver using the CMX994 but not using the IC s internal LNA in order to achieve the maximum operating dynamic range of a direct conversion receiver like the CMX994 the signal level to mixers must be controlled in order to minimise the chance of local oscillator pulling hence the need for LNA control Controlling the external device as shown in Figure 39 causes the gain to step suddenly This in itself may cause a short burst of errors so once sign
13. The CMX7164 operates from a 3 3V supply and includes selectable powersaving modes It is available in 64 VQFN and 64 LQFP packages Note that text shown in indicates features that will be supported in future versions of the device This Data Sheet is the first part of a two part document 2015 CML Microsystems Plc Page 3 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 CONTENTS Section Page T Brief DESCKPUON fee C 2 1 1 ni 10 2 Block Diagrammer ege Segen 13 REI e aA E EE EPEE 16 4 PCB Layout Guidelines and Power Supply Decoupling eese 19 5 External Components ettet eterne tente ce dicet se a aa aaa e eR E RC eL aaau aiaa 20 5 1 tal Iritetface an pa eate epe ob pes 20 5 2 COBUS Interface x ovata butt oet Ed 20 5 8 UO Output Reconstruction Filter 21 5 4 UO Input Antialias Eier 21 5 5 EN e NIE 21 6 General De scripliorn spos oeza svec apret ose nun tcc caeco cc So a adea Caec e asc s e Egret 22 6 1 GMX7164 E EE 22 6 2 Signal Interfaces UO Tx and HSI seene 23 6 3 Signal Interfaces Two point Tx and l Q Hax 24 7 Detailed DescriptiOns smrrrssnvennnnnnvnnnnnnnvennnnnnvnnnnnnnvnnnnnnnnennnnnnnnnnnnnnnennnnnnnennnnnnnennnnnnnennnnnneene 25 7 1 Xtal Freguercy EE
14. 1 0E 02 v Y N14 9p d aae BER Block Type 0 4 BER Block Type 6 X BER Block Type 7 50 EN e e PER Block Type 0 1 O PER Block Type 6 1 0E 03 M gt PER Block Type 7 40 Y ULUN a P 2 ee T E A ov N 90m i N a 1 0E 04 N N 28 4 V x W C N S N me N 3 s ES 1 0E 05 W ENS UNA a m eg 0 10 11 12 13 14 15 16 17 Signal to Noise Ratio dB Figure 98 Comparison of BER and PER for 16 QAM Modulation 1 0E 02 Ys TV S UN SCH 0 BER Block Type 0 N EN BER Block Type 6 ME s BER Block Type7 50 N 4 SCH e e PER Block Type 0 NS PER Block Type 6 1 0E 03 7 s ES PER Block Type7 40 E X LY x B 30 tc m x N 1 0E 04 e y M 20 N b UN V 2 S G WE N K i DH Nl N NN l N E 1 0E 05 ET sanis b emm a um em em am amm 0 18 19 20 21 22 23 24 Signal to Noise Ratio dB Figure 99 Comparison of BER and PER for 64 QAM Modulation 10 6 2 Adjacent Channel Performance The 7164FI 4 x provides excellent rejection of adjacent signals present on the UO inputs Assessment of the adjacent channel rejection ACR performance of the modem is normally made in terms of BER or PER for a given ratio between the wanted signal on channel and larger interferer on the adjacent channel Detailed measurement methods vary depending on the standards in use in particular whether
15. 12 14 16 18 Signal to Noise Ratio dB 20 22 Figure 74 8 FSK and 16 FSK Coding Performance in Static Channel 2015 CML Microsystems Plc Page 97 D 7164 Fl 1 x Fl 2 x F1 4 x F1 6 x 22 CMX7164 Multi Mode Modem CMX7164 1 000E 01 ie 8FSK High rate code Block size 3 8FSK Low rate code Block size 3 1 000E 02 4 1 000E 03 4 BER 1 000E 04 1 000E 05 4 1 000E 06 T t f t t t 30 32 34 36 38 40 42 44 46 48 Signal to Noise Ratio dB Figure 75 8 FSK Coding Performance in TU50 Fading Channel 150MHz 1 00E 01 1 00E 02 R E S N hae EN e N oc ie N 1 00E 03 ca N N N N N N 1 00E 04 8 FSK N 16 FSK N N N 1 00E 05 15 17 19 21 23 25 Co Channel Rejection dB Figure 76 8 FSK and 16 FSK Co channel Rejection with FM Interferer as EN 300 113 2015 CML Microsystems Plc Page 98 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 4 FSK Uncoded E 8 FSK Uncoded ai 16 FSK Uncoded 8 FSK Coded sj 16FSK Coded KI D e ke o ke ke ul e 9 ea 20 Signal to Noise dB Figure 77 8 FSK and 16 FSK Block Error Rate Block Size 0 High Rate Code 12 Byte Blocks of Data in Uncoded Mode 9 6 3 Receiver Dynamic Range The adjacent channel rejection results in section 9 6 1 2 also indicate that a wanted signal can be successfully received over
16. 9 6 1 4 FSK 9 6 1 1 Signal to Noise and Co channel Performance The performance of the 7164Fl 2 x when receiving is shown in the following graphs It should be noted that error rate performance depends on the modulation type symbol rate and deviation results have been taken for typical channel bandwidths The 7164F1 2 x supports multiple combinations of these factors but it is beyond the scope of this document to provide data for every combination Data is provided showing a selection of representative cases ranging from best case performance maximum coding to worst case where no coding is used raw mode plus the effect of using the two supported types of data pulse shaping plain Root Raised Cosine RRC filtering or RRC plus sinc filter In the following graphs the modulation is 4 FSK and the data rate is dependant on channel bandwidth The 25kHz channel data rate is 9 6ksymbols s the 12 5kHz channel data rate is 4 8ksymbols s and the 6 25kHz channel data rate is 2 4ksymbols s which is typical of the rate that may be achieved in each RF channel The signal to noise ratio is calculated as SNR Mean signal power 174 NF 10 logi RXBW Where NF receiver noise figure in dB RxBW receiver noise bandwidth Mean signal power is in dBm SNR Signal to Noise Ratio in dB The graph in Figure 68 compares the raw sensitivity performance of data transfer using a 6 25kHz a 12 5kHz and a 25kHz channel in each case the deviation of the
17. Ll IOUTPUTN 2 point modulation X QOUTPUTP Fl 4 x UO output ft fi Receive Functions L QOUTPUTN IINPUTP Channel IINPUTN Filter Channel Decoder Fl 1 x Fl 2 x Data gt amp Fl 4 x Demodulator QINPUTP Channel Frame Sync Detect FI 6 x QINPUTN Filter Auxiliary Functions Thresholds ADC 1 1 Averaging Thresholds IRON Averaging Command FIFO RDATA Thresholds AUXADC1 i CSN Buse Averaging Rx Data FIFO CDATA gt Thresholds AUXADC3 ADC 4 AUXADC4 Averaging Registers SCLK Auxiliary Multiplexed ADCs C BUS Interface GPIOA K gt GPIOB GPIO with O P i Sequencer System Clock Div 1 SYSCLK1 GPIOC System Clock Div 2 SYSCLK2 GPIOD FI Configured y System Clock PLL f Casi XTM AUXDAC1 Ramp profile RAM rystal CLOCK Main Oscillator Clock PLL f I XTALN AUXDAC2 System Clocks AUXDAC3 AUXDAC4 a Power Auxiliary DACs control MOSI S CLK Controller MISO SPI Thru k Flash Boot Port SSOUTO SSOUT1 Host Thru Device Commands Reset SSOUT2 C BUS SPI Thru Control AVDD gt
18. 65dB for 0 PER 62dB 0 PER 58dB 0 PER The figures in Table 9 are typical of what may be achieved with 7164F1 4 x and a typical I Q radio receiver with no adjacent channel selectivity in the radio circuits In a more normal RF architecture some adjacent channel selectivity will be provided making system results better than the measured values for the 7164F1 4 x alone Furthermore the results observed are not necessarily the maximum that the CMX7164 can achieve but are limited by the practical dynamic range of the CMX7164 combined with the system gain and noise figure of the receiver used in these tests 10 6 3 Receiver Dynamic Range The adjacent channel rejection results in section 10 6 2 also indicate that a wanted signal can be successfully received over the dynamic range stated in Table 9 without any need for an AGC Note that this is limited at the top end by the maximum allowed signal amplitude into the CMX7164 but performance at the bottom end is affected by noise added by the test receiver so these figures are not the absolute limit of CMX7164 Fl 1 x 2 x 4 x 6 x performance 10 6 4 Receiver Response Equaliser Performance The performance of the 7164Fl 4 x when receiving a signal through a typical IF crystal filter as used in EV9910B EV9920B is shown in the following graphs The nominal bandwidth of the filter is 15kHz however its response within that bandwidth is not flat both amplitude and group delay distortion is introdu
19. C Xtal Frequency 3 0 12 288 MHz External Clock Frequency 3 0 24 576 MHz 2015 CML Microsystems Plc Page 130 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 12 1 3 Operating Characteristics For the following conditions unless otherwise specified External components as recommended in Section 5 External Components Maximum load on digital outputs 30pF Xtal Frequency 9 6MHz 0 002 20ppm Tams 40 C to 85 C AVpp DVpp 3 0V to 3 6V Current consumption figures quoted in this section apply to the device when loaded with FI 1 x 2 x 4 x 6 x only Current consumption may vary with other valid Function Images DC Parameters Notes Min Typ Max Unit Supply Current see also section 12 1 5 11 All Powersaved Alpp Dipp 10 15 1 0 UA Idle Mode 12 15 Dlpp 13 550 UA Alpp 17 UA Additional Current for One Auxiliary 15 System Clock output running at 5MHz SYSCLKPLL active Diop DVpp 3 3V DVcore 1 8V 900 UA Additional Current for one Auxiliary 15 System Clock output running at 4 8MHz SYSCLKPLL not required Diop DVpp 3 3V DVconE 1 8V 675 UA Additional Current for Each Auxiliary ADC 15 Diop DVpp 3 3V DVconE 1 8V 190 UA Additional Current for Each Auxiliary DAC 14 15 Alpp AVpp 3 3V 210 to 370 uA Notes 10 Idle mode with Vgjas disabled 11 Tame 25 C not including any current drawn from the device pins by externa
20. PUR Up L CM IW alte 4 QAM Modulation spectrum with 18ksymbols s Adjacent Channel measurement for 25kHz channel ACP 76dB Integration window 16kHz Center 450 MHz 6 6 kHz Span 66 kHz cr 450 MW Meam Signs cr 450 MHs Meas Signal Ret Lv BR 18 Veeto Bet ivi HI 18 kHs Constellation 35 am Demod ar M 42a Den od Oper 31 dB Offser BURST NOT FOUND 1 8 so 011061011 10101100 4 1666667 PEAL 4 1666667 EXT er 450 MHz Bet ivi tp 16 kHz Syabol kzrors a5 40a Damod oper 31 dB Offrec Symbol Table o 00101010 11001111 11010100 01100111 10000101 ao 10100101 11111100 00000001 00111111 10111011 n 001002111 00111010 11111000 Error Summary Error Vector Mag Magnitude Error Phaze Error 1 97 REA 1 07 Freq Error Amplitude Droop 1Q Offset 62 ems 5 60 4 Pk ac sym 4 67 1 tns 4 70 Pk at sym 116 16 deg rns 3 20 deg Pk at syn 54 75 mHz 128 75 mHz Pk 40 db sym Rho Factor 0 9954 28 1 IQ Imbalance 1 18 4 Constellation Diagram Receiver filtered Error Vector Figure 88 Tx Modulation Spectra 4 QAM 18ksymbols s UO Modulation into CMX998 2015 CML Microsystems Plc Page 110 D 7164 Fl 1 x Fl 2 x F1 4 x F1 6 x 22 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 RBW 500 Hz RF Att 20 dB Ref Lvl 16 00 dBm VBW 2 kHz 30 dBm 450 00284365 MHz SWT 1 35 s Unit dBm quem EN 16 QAM Modulation spectrum wit
21. RESETN VBIAS AvsS gt ADCREF gt DVDD3V3 DVCORE Figure 1 Overall Block Diagram pvss gt DACREF gt BOOTEN1 gt BOOTEN2 gt Figure 1 illustrates the overall functionality of the CMX7164 detailing the auxiliary functions The following figures expand upon the transmit and receive functions 2015 CML Microsystems Plc Page 13 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Auto Frame Sync Detect Link Quality Detect RS Symbol Raw Mode Data ya nnel Pulse R gt RFRX Demod ping Filters piod RY S4 QAM Channel Decoder p Host S Coded Mode Data Errar ne S 4c Z Coded Mode Pe aa DAC if Construct Frame sl zk BET VO Mod Pulse Add Preamble Q Framesync and Tails lg Raw Mode Data lw wi Figure 2 Fl 4 x Block Diagram UO Tx and Rx Auto
22. TN NAN more data to send Y Load TxEnd Command 3 Yes v IRQ TxDone rampdown Execute RAMDAC yes gt mode if not automatically controlled by the GPIO pins Load data to Command FIFO Due to internal processing delays in the filters etc the host should wait for IRQ TxDone or implement its own delay to ensure all data has been transmitted See Rx Process flow diagram Goto Rx Process Set Modem Control to Idle The host should ensure Mode Idle that any external hardware is also set into Idle mode if not automatically controlled by the GPIO pins ps sg Goto Idle Mode SSS Figure 17 Host Tx Data Flow No Tx Sequence Carrier Sense 2015 CML Microsystems Plc Page 36 D 7164 Fl 1 x Fl 2 x F1 4 x F1 6 x 22 CMX7164 Multi Mode Modem 7 4 8 Rx Mode CMX7164 In Rx mode a frame sync must be detected then data is supplied to the host through the Rx Data FIFO Data should be read in response to a Cmd Done Rx Data FIFO IRQ or status indication The CMX7164 will continue decoding the input waveform until the host sets the mode bits Once initial timing is established timing corrections can be derived from to either Tx or Idle as required the data to track the received signal The Rx Tracking register allows selection of the tracking mode used to track the signal level UO dc offset and
23. AVDD 3 3V AUX ADC4 AUX ADC3 AUX ADC2 AUX ADG Figure 7 CMX7164 Power Supply and De coupling Notes DVpp DVss DVCORE 1 8V DVSS C28 C22 C23 C24 AVss Ass Ass To achieve good noise performance AVpp and Vous decoupling and protection of the receive path from extraneous in band signals is very important It is recommended that the printed circuit board is laid out with a ground plane in the CMX7164 analogue area to provide a low impedance connection between the AVSS pins and the AVpp and Vous decoupling capacitors 2015 CML Microsystems Plc Page 19 D 7164 Fl 1 x Fl 2 x F1 4 x F1 6 x 22 CMX7164 Multi Mode Modem CMX7164 5 External Components 5 1 Xtal Interface XTAL CLOCK C1 50 C2 49 X1 For frequency range see 12 1 2 Operating Limits C1 22pF Typical C2 22pF Typical Figure 8 Recommended External Components Xtal Interface Notes The clock circuit can operate with either a Xtal or external clock generator If using an external clock generator it should be connected to the XTAL CLOCK pin and the xtal and other components are not required For external clock generator frequency range see 12 1 2 Operating Limits When using an external clock generator the Xtal oscillator circuit may be disabled to save power see 13 2 3 Program Block 1 Clock Control for details Also refer to section 7 1 Xtal Frequency The tracks between the Xtal and the device pins should be as short as possible to achie
24. Att 7 dB SWT 1s VBW 300 Hz Mode Auto FFT 8 500 kHz 8 500 kHz 12 500 kHz 66 28 dB 8 500 kHz 25 000 kHz 77 81 dB leasuring GUND de EEE Date 4 NOV 2014 14 57 13 Modulation Spectrum EN 300 113 Adjacent Channel measurement for 12 5kHz channel ACP lt 66dB limit is 60dB Measurement bandwidth 8 5kHz MultiView Spum X Sema X spama x J vsa Ref Level 0 00 dBm Att 10 dB AQT 9 984 ms DBW 25 kHz Freq 455 0 MHz TRG FM CF 455 0 MHz 1001 pts 998 4 ys 4 Result Summary Carrier Power 2 63 dBm Carrier Offset 14 77 Hz Peak Peak iPeak 2 RMS Mod Freq SINAD THD 1 5393 kHz 1 5309 kHz 1 5351 kHz 1 0820 kHz 1 5810 kHz Aborted HK 6 Date 4 NOV 2014 14 52 07 Figure 108 Tx Modulation V 23 1200bps UO Modulation 2015 CML Microsystems Plc Page 126 D 7164 Fl 1 x Fl 2 x F1 4 x F1 6 x 22 CMX7164 Multi Mode Modem CMX7164 Modulation Spectrum Peak deviation 3 0 kHz Modulation Spectrum Ref Level 0 00 dBm RBW 100 Hz 7 dB SWT is amp VBW 3kHz Mode Auto FFT EXAM EN 300 113 Adjacent Channel measurement for 25kHz channel ACP lt 74dB limit is
25. FIFO levels and level IRQs may be used to manage the data flow This mode provides the ability to simply stream using streaming C BUS if desired multiple bytes into or out of the CMX7164 as FIFO content allows 7 4 16 Formatted Data Transfer When the transfer of formatted data is selected by the Modem Mode and Control 6B write register the FIFO Control byte indicates the block type to use in either sending or decoding the data The block type dictates the format or quantity of data transferred including how error detection and correction bits are added to the over air data stream 7 4 17 Pre loading Commands It is advisable to pre load data into the Command FIFO before transmission begins or to pre load receive data commands into the Command FIFO prior to frame sync reception 7 4 18 GPIO Pin Operation The CMX7164 provides four GPIO pins each pin can be configured independently as automatic manual input output and rising falling with the exception of the combination automatic input function which is only allowed for GPIOA Pins that are automatic outputs become part of a transmit sequence and will automatically switch along with the RAMDAC AuxDAC1 if it is configured as automatic during the course of a burst Pins that are manual are under direct user control When automatic a rising or a falling event at the start or end of transmission will cause the specified GPIO to be switched high or low accordingly GPIOA may be conf
26. No Yes Y Read and verify 32 bit checksum words from RxFIFO Word 4D Y N N 1 Y Is the next block the Activation Block No load next 4 Yes block Write Start Block N Length ACTIVATE_len to CmdFIFO Word 49 Y Write Start Block N Address ACTIVATE ptr to CmdFIFO Word 49 Y Poll Status 7E until Reg Done b14 1 PRG Flag is unmasked in Reg Done Select register 69 by default and indicates when the FI is loaded Vpp Y Read the Product ID Code and the E version code from the RxFIFO Word BOOTEN1 4D Y BOOTEN2 CMX7164 is now ready for use Figure 15 FI Loading from Host 2015 CML Microsystems Plc Page 29 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 7 3 2 Fl Loading from Serial Memory The Fl must be converted into a format for the serial memory programmer normally Intel Hex and loaded into the serial memory either by the host or an external programmer The serial memory should contain the same data stream as written to the Command FIFO shown in Figure 15 The most significant byte of each 16 bit word should be stored first in serial memory The serial memory should be interfaced to the CMX7164 SPI Thru Port using SSOUTO as the chip select The CMX7164 needs to have the BOOTEN pins set to Serial Memory Load and then on power on followng the RESETN pin becoming high o
27. Raw data can be transferred in addition to formatted data blocks Formatted data blocks may be of variable length from 15 to 416 bytes and support a combination of 16 bit or 32 bit CRC for error detection plus error correction 10 1 7164FI 4 x Modulation The 7164F1 4 x produces QAM modulation with three options 4 16 or 64 QAM see Figure 82 In each case the signal is Root Raised Cosine filtered The same filter is applied in receive to remove inter symbol interference Due to the way the signal is produced there is no deviation to select instead only the baud rate may be altered This has a direct effect on the signal bandwidth A baud rate of 18ksymbols s is typical of a 25kHz channel spacing and provides QAM Variant Bits per Symbol Base Over air Bit Rate Raw Mode Over air Bit 18ksymbols s Rate 18ksymbols s 4 QAM 2 36kbps 32kbps 16 QAM 4 72kbps 64kbps 64 QAM 6 108kbps 96kbps Q4 Q4 Q 01 00 0111 0110 0010 0011 oe e e je e e S 2 EE M ee et cer e 0101 0100 0000 0001 b D e D s s ha l e e e e een P Le gt gt 1101 1100 1000 1001 i e e e Ee CR Ce e L 11 10 1111 1110 1010 1011 OE ODO S e e e KE O der oM 4 QAM Mapping 16 QAM Mapping 64 QAM Mapping Figure 82 QAM Mappings The signal spectrum is identical in bandwidth when using 4 16 or 64 QAM however the peak to mean of each modulation type does vary 4 QAM has a peak to mean of 5 3dB
28. a 0 2 or 3 8dB a 0 35 16 QAM has a peak to mean of 7 8dB a 0 2 or 6 4dB a 0 35 64 QAM has a peak to mean of 9dB 020 2 or 7 5dB a 0 35 The difference between the base over air rate and the raw mode rate which is the actual user data rate in raw mode at 18ksymbols s is due to some symbols being used internally by the modem to perform channel equalisation A further implication of this is that any transmission must contain a multiple of 16 symbols the CMX7164 will automatically pad as necessary 2015 CML Microsystems Plc Page 104 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 10 2 7164FI 4 x Radio Interface QAM modulation requires control of both phase and amplitude in the transmitter and to measure both phase and amplitude in the receiver Therefore the 7164FI 4 x offers UO transmit and 1 0 receive interfaces This is shown in Figure 83 using the CMX9929 for reception and the CMX9981 for transmit with RF power amplifier linearisation The internal functions of the CMX7164 when operating in this mode are shown in Figure 2 HOST SJ TL Aen E seas ud sat M c CRM vidct eel rt o ut GPlOn UP i I Gei d x ENG ae NA Enable d CMX7164 Io at I E CH apo Ge A C9 I Input E LNA LO 2x ADC C BUS Q Q Input CMX992 Thru C BUS Local Oscillato
29. from a single measurement Therefore the gain applied to the calculated adjustment may be programmed and a number of iterations selected resulting in a damped feedback loop 2 The dc error to be corrected is usually large enough that if measured with the CMX998 in high gain mode the DCMEAS output would saturate This makes calculation of the magnitude of error impossible Therefore low gain mode should be used initially 3 When changing from low to high gain modes the circuit changes see dc calibration Application Note CMX998 Cartesian Feedback Loop DC Calibration therefore the correction needed changes However the low gain correction should at least be close to bringing the high gain measurement out of saturation The relationship between correction computed using low gain and high gain is consistent so may be noted and applied as an offset The calibration sequence implemented in the CMX7164 has the following stages Setup Initialise the SSP port AuxADC and select Refl as DCMEAS output from the CMX998 Refl Read Refl select DCMEAS RefQ RefQ Read RefQ select DCMEAS Error ErrorlLo Read Errorl assuming Low gain and adjust the Output accordingly ErrorQLo Read ErrorQ assuming Low gain and adjust the Q Output accordingly Iterate go to ErrorlLo after a delay for corrected signals to settle HighGain Select High gain mode of the CMX998 apply Low to High gain mode correction ErrorQHi Read ErrorQ assuming High gain and adjust the Q O
30. was achieved by adjusting the deviation control in the RF signal generator 2015 CML Microsystems Plc Page 89 D 7164 FI 1 x FI 2 xX Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 RBW 500 Hz RF Att 30 dB Ref Lvl 40 77 dBm VBW 5 kHz 0 dBm 450 00837836 MHz SWT 1 35 s Unit dBm Modulation Spectrum EN 300 113 Adjacent Channel measurement for 25kHz channel ACP 75dB Integration window 16kHz Peak deviation 3 symbol 2 85kHz Center 450 MHz 6 7 kHz Span 67 kHz CF 450 MHz Meas Signal Ref Lvl SR 9 6 kHz Eye I 0 dBm Demod 4FSK 5m REAL L Ti TS2 TS1 75m 0 SYMBOLS 4 Eye Diagram Figure 67 Tx Modulation Spectra 4 FSK 19 2kbps Two point Modulation 2015 CML Microsystems Plc Page 90 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 9 6 7164Fl 2 x Typical Receive Performance The performance of the receiver will be different for any combination of nFSK modulation bit rate and deviation To aid the user some typical performance data has been measured using a realistic I Q receiver This is provided to serve as guidance however each user must consider his own application requirements and then select both the receiver used and any coding whether used and if so block size and code rate where applicable
31. 17 describes operation when a transmit sequence is defined by the host by e Removing the need for the host to provide a ramp up instead the configured Tx sequence will deal with this e Inserting GPIO on off events before ramp up and after ramp down as specified by the transmit sequence 2015 CML Microsystems Plc Page 35 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem Tx Process vy CMX7164 This assumes that The transmit control sequence and frame syncs have been configured Load data to Command FIFO using the programming register v Set Modem Control toTxPreamble Frame sync and required data mode Mode Tx Here the device is waiting for a GPIO Ensure that RAMDAC speed is fast enough to trigger to start the transmission attempt As no carrier sense is S TX gt Yesp selected it is not p note receiving and is Wait for Tx Trigger lt triggered on GPIO lt Execute RAMDAC rampup committed to transmit d GPIO Tx Trigger The Modem will transmit the preamble frame sync and data The host should ensure that any external hardware is also set into Tx IRQ Error Modem status Underflow allow for hardware and note internal processing delays Gs No p TNR Ec nm P 4 IRQ CmdDone or Cmd FIFO yes may occur at this Y point if enabled note
32. 2 one H h 4 x GPIO 4 x ADC 4 x DAC i Synth H RERx gt apes Lp Disital A Filters FIFO o T i Modem Za C B Digital Configuration E SC S RF Tx lt DACs 4 Fi H or H H ilters d Moder EA E External Serial H C BUS SPI Devices master FEC Image i CMX7164 33V i3 33V Multi Mode Modem 1 Brief Description The CMX7164 Multi Mode Modem is a half duplex device currently supporting GMSK GFSK 4 16 64 QAM 2 4 8 16 Level FSK and V 23 modes in multiple channel spacings under host control Its Function Image Fl is loaded to initialise the device and determine modulation types The 7164Fl 1 x supports GMSK GFSK modulation with BT 0 5 0 3 0 27 or 0 25 User programmable filters are also possible contact CML Technical Support for further information The 7164F1 1 x supports up to 20kbps Flexible bit rates support a wide range of applications requiring a selectable bit rate and robustness The 7164Fl 1 x supports zero IF I Q and two point modulation Mod1 2 transmit modes with zero IF receive mode The GMSK GFSK data is over air compatible with the FX MX909B and the CMX7143FI 1 x The 7164FI 2 x supports 2 FSK 4 FSK 8 FSK and 16 FSK modulations root raised cosine filtered with a 0 2 with optional sinc filtering User programmable filters are also possible contact CML Technical Support for further information The 7164F1 2 x supports up to 10ksymbols s in a 25kHz channel Flexible bit rates support a wide r
33. 2 x supports two kinds of formatted data native formatted data and RD LAP formatted data both of which provide the ability to channel code blocks of data using trellis coding and CRCs RD LAP formatted data is only available when 4 FSK is selected When transmitting receiving 8 FSK or 16 FSK the 7164F1 2 x supports native formatted data in a range of block sizes and with two channel code rates high and low for each modulation type RD LAP formatting is not available Native formatted data The frame structure as used in a formatted data system is illustrated in Figure 58 It typically consists of a 24 symbol frame sync pattern followed by a Header Block one or more Intermediate Blocks and a Last Block Header Block Intermediate Blocks Last Block 1765 1413 12 110 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Data Bytes Data Bytes Byte 5 e g 10 e g 12 Byte 6 Byte 7 Byte 8 Byteo CRC2 wm en em p em ap en en gd a Byte 10 CRCI ES Byte 11 Q bytes T 07 0 7 0 ByteO Bytel Byte t 20883 Sch tri bits 10 1 2 3 4 5 29 130 31 132 FEC CODING DECODING ERROR CORRECTION ced 2 symbols INTERLEAVING DE INTERLEAVING Over air r o ES e e e e e e sm 0 0 00 9 0 mm symbols ts e eege e 0000000 e 24 66 66
34. 22 CMX7164 Multi Mode Modem CMX7164 RBW 500 Hz RF Att 30 dB Ref Lvl VBW 5 kHz 0 dBm SWT 1 35 e Unit dBm Modulation Spectrum d i N T I n Span 67 kHz La Comparison of 4 FSK inner trace and 2 FSK outer trace both at 9 6k symbols s with the same deviation setting in CMX7164 CF 450 MHz Meas Signal SR 9 6 kHz Eye I Demod 2FSK z r gt NN WH AVA N NV Vi VM G S NL PIN v VIA XY N Y AN A L JN f N XG i 7 Ay ES NTV i ZS A LO EX OW MAN f VAR N YN Z 0 SYMBOLS Eye Diagram Figure 63 Tx Modulation Spectra 2 FSK 9 6k symbols s 9 6kbps UO Modulation 2015 CML Microsystems Plc Page 86 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 RBW 500 Hz RF Att 30 dB Ref Lvl 12 49 dBm VEW 2 kHz 0 dBm 448 00219188 MHz SWT 1 35 s Unit dBm 0 Yi Ti 14 49 z 448 00219188 MHZ 10 CH PWR d 28 ACP Up 72 79 0 ACP Lo 73 78 Modulation 30 Spectrum 1RM 40 50 T 60 10 80 cul co 90 CO 1 100 Center 448 MHz 6 6 kHz Span 66 kHz win 2 8130 kHz 4 370 000 _ Eye Diagram 4 kHz TT 1sym i 1 sym
35. 25 ns tCDH CDATA hold time 25 ns tRDS RDATA setup time 25 ns tRDH RDATA hold time 0 ns Notes 1 Depending on the command 1 2 or more bytes of CDATA are sent to the peripheral MSB first LSB Bit 01 last RDATA is read from the peripheral MSB first LSB Bit 0 last 2 Commands are acted upon between the last rising edge of SCLK of each command and the rising edge of the CSN signal 2015 CML Microsystems Plc Page 144 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem 12 3 Packaging Index Area 1 em A N d 7 fo Top View C M DM STE c Exposed E Metal Pad G E 2 L Pin1 gt 5 ER Index Area 2 Bottom view T sele T CMX7164 DIM MIN TYP MAX A 9 00 BSC B 9 00 BSC C 0 80 0 90 1 00 F 7 00 7 80 G 7 00 7 80 H 0 00 0 05 J 0 18 0 25 0 30 K 0 20 L 0 30 0 40 0 50 L1 0 0 15 P 0 50 iT 0 20 NOTE A amp B are reference data and do not include mold deflash or protrusions All dimensions in mm Angles are in degrees Index Area 1 Index Area 2 FRE Se Dot Dot Chamfer Index Area 1 is located directly above Index Area 2 Depending on the method of lead termination at the edge of the package pull back L1 may be present L minus L1 to be equal to or greater than 0 3mm The underside of the package has an exposed metal pad which should ideally be soldered to the pcb to enhance the thermal conductivity and mechanic
36. 25 7 2 Host Interface eto ete he te et exe tte nte ge he ie en dd 25 7 2434 C BUS Operation eee eet eb eee 25 7 3 Function Image Loading eee ete pene ete e bed ete Peas 28 7 3 1 Fl Loading from Host Controller sss eene 28 Streaming C BUS may be used to load the Modem Command FIFO Word 49 write register with the Function Image and the sees eee eee eee 28 7 3 2 Fl Loading from Serial Memonm 30 7 4 Device CONTON s ete ta aA had etna ebbe fente rie dioc 31 7 4 1 Normal Operation Overview sese eee eee eee eee eee eee 31 7 4 Basic Tx and Rx Operation 32 7 4 3 Device Configuration Using the Programming Register 33 7 4 4 Device Configuration Using dedicated regisiers 34 7 4 5 Interrupt Operation nee mote eb easet 34 7 4 6 Signal Control tr eed e eet tdi ee eo Miete eb tete etis 34 Ke ge alte oet eerie eee ee rd trate 35 7 48 PFocCMOGG s dnte a etre e te thee etu e be ih td 37 7 4 9 Carrier Sense Mode TT 38 7 4 10 The Transmit Tee TT e lt T H 40 7 4 11 CMX998 DC Offset Calibration UO Transmit Only sess 40 7 4 12 Other Modem Modes sese enne entente nns 43 1 43 Data Transter una 4aa akk 48 TA TA Data Buor cei eia i areas e eite tete ak 50 415 Raw Data Transfer aeger eee e d ce 51 7 4 16 Formatted Data Trancio or iaai aa e E ER A AES E 51 7 4 17 Pre loading Commande sss sese sees eee eee 51 7 4 18 GPIO Pini Operation
37. 4 Source Output Impedance 50 Auxiliary 10 Bit ADCs Min Typ Max 24 10 225 S 512 26 5 30 3 3 5 18 2 t1 10 60 10 20 4 t1 CMX7164 Unit US mV kQ LSBs LSBs Denotes output impedance of the driver of the auxiliary input signal to ensure Resolution Conversion Time 51 Sample Rate Input Impedance Resistance 56 Capacitance 56 Offset Error 54 55 Integral Non linearity 54 55 Differential Non linearity 52 54 Auxiliary 10 Bit DACs Resolution Conversion Time 51 Settling Time to 0 5 LSB Offset Error 54 55 Resistive Load Integral Non linearity 54 55 Differential Non linearity 52 54 Notes 50 lt 1 bit additional error under nominal conditions 51 Typical based on 9 6MHz Xtal or external oscillator 52 Guaranteed monotonic with no missing codes 54 Specified between 2 5 and 97 5 of the full scale range 55 Calculated from the line of best fit of all the measured codes 56 The input signal internally drives a S H sample and hold circuit that is newly charged for one ADC conversion period on each ADC conversion That circuit connects the input pin to an internal Vpp 2 voltage source via a series resistor capacitor network The S H circuit s net time constant including the external source impedance of any input signal will determine the S H settling time Provided the external source impedance is of low value the resultant settling time will be correspo
38. 4 FSK conventional UO vector modulators such as the CMX993 would be more typical of solutions for GMSK 4 FSK modulation 2015 CML Microsystems Plc Page 77 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 9 2 20 Two point Modulation Transmit with UO Receive Interface An overview of how the CMX7164 might integrate with an UO receiver and two point modulation transmitter is shown in Figure 57 The internal functions of the CMX7164 when operating in this mode are shown in Figure 4 HOST Y Pee ee ee T GPlOn ___ uP H I 1 OG X T NS paste sl LNA Enable_____ 1 XL i CMX7164 1 EESE P I U ed d I Ca H GPIO Tx Rx ENG Gi K e INPUT LNA LO 2x ADC SER Q QINPUT CMX992 Local Oscillator A T Thru C BUS PA Gain Control RAMDAC EN M MICE NC CIR CC CE EE E LE l Aux DACH 2x DAC I I I i Reference IOUTPUT QOUTPUT x e g VCTCXO MOD1 MOD2 Ce Se PLL KL 4 Control vco Voltage Power Amplifier Input Figure 57 Outline Radio Design 2 or 4 FSK UO in two point mod out 2015 CML Microsystems Plc Page 78 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 9 3 7164Fl 2 x Formatted Data When transmitting receiving 4 FSK the 7164F1
39. 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Pin Description Name Type 26 NC NC Do not connect Internally generated bias voltage of approximately AVpp 2 If E A E a ooo ae a capacitor mounted close to the device pins 28 IINPUTP IP Differential inputs for I channel signals P is positive N is 29 IINPUTN IP negative Together these are referred to as the I Input 30 ADCREF ADC reference voltage connect to AVss 31 QINPUTP IP Differential inputs for Q channel signals P is positive N is 32 QINPUTN IP negative Together these are referred to as the Q Input 33 AUXADC 1 IP Auxiliary ADC input 1 34 AUXADC2 IP Auxiliary ADC input 2 35 AUXADC3 IP Auxiliary ADC input 3 36 AUXADC4 IP Auxiliary ADC input 4 Positive 3 3V supply rail for the analogue on chip circuit g uox NN capacitors mounted close to the device pins 38 AVSS PWR Se supply rail ground for the analogue on chip 39 AUXDAC 1 OP Auxiliary DAC output 1 Optionally the RAMDAC output 40 AUXDAC2 OP Auxiliary DAC output 2 41 AUXDAC3 OP Auxiliary DAC output 3 42 AUXDAC4 OP Auxiliary DAC output 4 43 DVSS PWR Negative supply rail ground for the digital on chip circuits Internally generated digital core voltage of approximately 44 DVCORE PWR 1 8V This pin should be decoupled to DVss by capacitors mounted close to the device pins 3 3V positive supply rail for the digital on chip circuits This 45 DVDD3V3 PWR pin should be decoupled to DVss by capacitors mounted close t
40. 5F 60 write 13 1 21 I Q Input Coarse Gain B1 B2 write 13 1 23 I Q Output Coarse Gain B4 B5 write 13 1 22 HO Output Configuration B3 write 13 1 20 HO Input Configuration BO write 13 1 5 AuxADC1 4 Control 51 to 54 write 13 1 6 AuxADC1 4 Threshold 55 to 58 write 13 1 10 Signal Control 61 write 13 1 14 AGC Control 65 write 7 4 5 Interrupt Operation The CMX7164 can produce an interrupt output when various events occur Examples of such events include detection of a frame sync an overflow of the internal data buffering in receive or completion of transmission whilst in transmit Each event has an associated IRQ Status register bit and an IRQ Mask register bit The IRQ Mask register is used to select which status events will trigger an interrupt on the IRQN line All events can be masked using the IRQ mask bit bit 15 or individually masked using the IRQ Mask register Enabling an interrupt by setting a mask bit 0 1 after the corresponding IRQ Status register bit has already been set to 1 will also cause an interrupt on the IRQN line The IRQ bit bit 15 of the IRQ Status register reflects the IRQN line state All interrupt flag bits in the IRQ Status register are cleared and the interrupt request is cleared following the command address phase of a C BUS read of the IRQ Status register See e 13 1 37 IRQ Status 7E read e 13 1 19 IRQ Mask 6C write 7 4 6 Signal Control The CMX7164 offers two signal inp
41. 66 66 FRAME gt PREAMBLE FRAME M Frame Sync xl l 1 43 3 3 3 1 1 3 143 143 1 1 3 3 43 1 3 1 o sent first last Symbol Sync at least 24 symbols of 3 3 3 3 sequence Figure 58 Native Formatted Data Over Air Signal Format 2015 CML Microsystems Plc Page 79 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 The Header block is self contained as it includes its own checksum CRC1 and would normally carry information such as the address of the calling and called parties the number of following blocks in the frame if any and miscellaneous control information The Intermediate block s contain only data the checksum at the end of the Last block CRC2 also checks the data in any preceding Intermediate blocks This checksum calculation should be reset as required using the Reset CRC2 block type so that any transmitted CRC2 contains the CRC of only the desired blocks In receive it must be reset to match the expected input data block sequence A variety of different frame formats are possible some examples are illustrated in Figure 59 A A SYMBOL FRAME e Socr ene HEADER BLOCKS B SS B SYMBOL l FRAME LAST SYNG U SYNC INTERMEDIATE BLOCKS BLOCK c SYMBOL FRAME ER SVE Ee INTERMEDIATE BLOCKS Figure 59 Suggested Frame Structures The CMX7164 performs all of the block formatting and de formatting the bi
42. 70dB Measurement bandwidth 16kHz 2 Result Summary USER 25k acp Channel Bandwidth Offset TX1 Ref 16 000 kHz Tx Total Bandwidth Offset _ 16 000 kHz 25 000 kHz B 16 000 kHz 50 000 kHz 78 23 dB Measuring WED 4 J Date 4 NOV 2014 15 05 53 Ref Level 0 00 dBm Att 10dB AQT 9 984ms DBW 25kHz Freq 455 0 MHz TRG FM TAP CIrw DC Ref 0 00 Hz Carrier Power 1 11 dBm Carrier Offset 40 79 Hz Peak Peak L Peak 2 l RMS Mod Freq SINAD 3 1008 kHz 3 0799 kHz 3 0904 kHz 2 1761 kHz 1 7242 kHz Aborted PRESS dE ren JL Date 4 NOV 2014 14 58 31 Figure 109 Tx Modulation V 23 1200bps I Q Modulation 2015 CML Microsystems Plc Page 127 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 11 5 7164F1 6 x Typical Receive Performance 11 5 1 Signal to Noise Performance Signal to noise performance was measured by sending 200 bursts of a known PRBS sequence Each burst contained 800 bytes for a total of 160 000 bytes or 1 280 000 bits Bit errors were detected by comparing with the known sequence A CMX994 based receiver was used for this test Tx Deviation was 1 5kHz and the default narrow c
43. FSK 1 4 FSK 3 8 FSK 7 and 16 FSK 15 symbols have the same frequency deviation Marker 1 T1 55 5000 sym CF 450 MHz Meas Signal Ref Lvl FreqDev 4 923 kHz SR 9 6 kHz Frequency 0 dBm Demod 4FSK 1 Vil qi 55 5000 sym zelten 4 924 kuz EM FREQ LN Di H N Hz H T1 L L BURST NOT FOUND 0 SYMBOLS 99 9375 Figure 55 PRBS Waveform Two point Modulation When receiving 8 and 16 FSK signals the initial acquisition of I Q dc offset correction is critical to good reception The 7164Fl 2 x is capable of calculating an I Q dc offset correction but performance will be improved by choice of preamble pattern If the deviation is small then a typical 3 3 3 3 preamble pattern can have a large dc component in or Q which will make dc offset calculation difficult A 3 3 3 3 pattern is a better choice with particular benefit to 8 and 16 FSK reception It is recommended that such a preamble pattern be chosen for 8 and 16 FSK reception along with an alternate 1 0 dc offset acquisition mode set using programming register P4 5 as described in 13 2 6 Program Block 4 Modulation Control 9 2 7164Fl 2 x Radio Interface The transmit radio interface of the 7164F1 2 x can be s
44. If frame sync is found during this period then it is indicated to the host via the status bits and normal reception resumes No carrier sense happens until GPIOA is used to start the transmit process at which point carrier sense begins and operation is as described above Note The Command FIFO and Command Buffer will automatically be flushed when a carrier sense attempt to transmit results in the CMX7164 reverting to receive mode This is to avoid accidentally processing transmit commands pre loaded by the host as receive commands This is the only situation in which the FIFOs or buffers will be flushed other than by direct host instruction 2015 CML Microsystems Plc Page 38 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 ERE re This assumes that la carrier sense threshold and period Carrier sense process have been defined using the programming register Wei lo uu m Clear Command FIFO Set Modem Control toTxPreamble Frame sync and required data type Rx Frame sync and required data type Mode Carrier Sense Here the device is in Tx triggered on receive and searching Yes for a frame sync as GPIO e well as waiting for a GPIO trigger to start Wait for Tx Trigger note the transmission attempt GPIO Tx Trigger IRQ FS Received No Here the dev
45. Modem Command data word control and data bytes is added to Cmd FIFO FIFO Word register Cmd FIFO control word updated for future writes read Receive FIFO Control Byte register Rx FIFO control word is returned no effect on Rx FIFO contents read Receive FIFO Data Byte register Oldest Rx FIFO data byte is removed from FIFO and returned Rx FIFO Word updated read Receive FIFO Data Word register Oldest Rx FIFO data word control and data bytes is removed from FIFO and returned Rx FIFO control word updated C BUS interface mE Rx Level Level CMD FIFO LEVEL RX FIFO LEVEL RX FIFO CTRL CMD FIFO CTRL al CMD FIFO RXFIFO WRITES READ16 CMD FIFO RX FIFO P WRITE8 CMD 128x16 CMD FIFO Level Lg 128x16 RX FIFO E Rx Level Figure 38 Command and Rx Data FIFOs 2015 CML Microsystems Plc Page 49 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Raw or formatted data may be transmitted with the CMX7164 adding preamble frame sync and tail bits Raw or formatted transmission reception is selected using the Modem Mode and Control 6B write register each whole transmission reception must continue in the selected mode Relevant registers are 13 1 18 Modem Mode and Control 6B write 13 1 3 Modem Command FIFO Data Control 48 49 and 4A write 13 1 26 Receive FIFO Data Control 4C 4D 4E read 13 1 25 Modem Co
46. PRBS Rx Frequency Error Tolerated 75 1 0 kHz Rx Co channel Rejection 73 dB Rx Adjacent Channel Rejection 73 S dB Notes 70 Determined by the accuracy of the Xtal oscillator provided 71 Transmitting continuous PRBS data This is a differential voltage I Output IOUTPUTP IOUTPUTN and Q Output IOUTPUTP IOUTPUTN 72 See section 9 5 7164F1 2 x Typical Transmit Performance 73 See section 9 6 7164F1 2 x Typical Receive Performance 75 Optimum performance is achieved with OHz frequency error The figure quoted is for a symbol rate of 9 6ksymbols s The frequency error tolerated is proportional to the symbol rate 2015 CML Microsystems Plc Page 139 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 12 1 6 7164Fl 4 x Parametric Performance For the following conditions unless otherwise specified External components as recommended in section 5 Maximum load on digital outputs 30pF Clock source 19 2MHz 0 002 20ppm clock input Tame 40 C to 85 AVpp DVpp 3 0V to 3 6V Reference signal level 308mV rms at 1kHz with AVpp 3 3V Signal levels track with supply voltage so scale accordingly Signal to Noise Ratio SNR in bit rate bandwidth Input stage gain OdB Output stage attenuation OdB All figures quoted in this section apply to the device when loaded with Fl 4 x only The use of other valid Function Images can modify the parametric performance of the device DC Parameters N
47. SYNC B TAS B SYMBOL FRAME LAST SYNG Ki INTERMEDIATE BLOCKS BLOCK C SYMBOL FRAME See INTERMEDIATE BLOCKS Figure 84 Suggested Frame Structures The CMX7164 performs all of the block formatting and de formatting When receiving header blocks and last blocks the CMX7164 will indicate CRC success or failure and will provide the data regardless The size of the data block can be varied as can the coding rate applied A lower coding rate more FEC bits will improve performance in noisy or faded conditions but will reduce the user data rate available Small data blocks provide the ability to produce a short burst or granularity in burst size However to cope with fading conditions longer coded blocks are necessary The 7164Fl 4 x provides blocks with the following formatted block sizes rates Table 8 Formatted Block Types Sizes and Rates FI 4 x User CRC bytes for a Total bytes Total bytes Block Block Size Coding Rate Coding Rate Header Inter Last excluding excluding Type Block Block Block frame symbol sync frame symbol sync 4 16 QAM 64 QAM 4 16 QAM 64 QAM 0 15 bytes 0 75 0 83 13 2 15 11 4 21 bytes 19 bytes 4 bits 1 60 bytes 0 75 0 83 58 2 60 56 4 81 bytes 73 bytes 4 bits 2 33 bytes 0 55 0 61 31 2 33 29 4 61 bytes 55 bytes 4 bits 3 37 bytes 0 62 0 69 35 2 37 33 4 61 bytes 55 bytes 4 bits 4 44 bytes 0 55 0 61 42 2 44
48. a change in status has occurred the uC should read the IRQ Status register across the C BUS and respond accordingly Interrupts only occur if the appropriate mask bit has been set see Interrupt Operation 7 2 1 C BUS Operation This block provides for the transfer of data and control or status information between the CMX7164 internal registers and the host uC over the C BUS serial bus Single register transactions consist of a single register address byte sent from the uC which may be followed by a data word sent from the uC to be written into one of the CMX7164 s write only registers or a data word read out from one of the CMX7164 s read only registers Streaming C BUS transactions consist of a single register address byte followed by many data bytes being written to or read from the CMX7164 All C BUS data words are a multiple of 8 bits wide the width depending on the source or destination register Note that certain C BUS transactions require only an address byte to be sent from the uC no data transfer being required The operation of the C BUS is illustrated in Figure 13 Data sent from the uC on the CDATA command data line is clocked into the CMX7164 on the rising edge of the SCLK input Data sent from the CMX7164 to the uC on the RDATA reply data line is valid when SCLK is high The CSN line must be held low during a data transfer and kept high between transfers The C BUS interface is compatible with most common UC serial interfaces and m
49. information covering 7164F1 6 x Section 7 4 22 AGC control algorithm can now be used to control a second device using one of the available GPIO pins Section 10 1 Updated Figure 82 QAM Mappings Section 12 2 Original C BUS timing diagram replaced by latest version Section 13 1 22 Register B3 changed reserved bit 9 set value and added example settings Section 13 1 31 description for register 77 b11 0 description corrected to describe RSSI averaging period set by P4 3 Section 13 2 6 Prog Block 4 Modulation Control P4 5 entry corrected to indicate that the parameter also supports Fl 1 x Section 13 2 6 Added description for P4 3 Section 13 2 7 Transmit sequence added description for minimum pulse period on GPIOA to trigger transmission and corrected the explanation of DC Calibration Sequence delays for default values Descriptions for registers 5D 5E 5F 60 61 65 added note regarding delay between successive writes Section 13 2 9 Added Program Block 7 17 for AGC control of external device via GPIO pins Section 15 10 App Note updated for clarification Section 12 Performance figures replace TBDs 11 05 15 21 Section 13 1 22 B3 register table corrected and note added describing correct settings for the I Q output drivers Section 13 2 2 Table for P0 0 b11 0 corrected to show value of 1 as invalid Section 13 2 5 Table showing new program registers P3 3 to P3 6 and associated description Sec
50. into the 7164FI 4 x 7164F1 2 x produces 2 FSK 4 FSK 8 FSK and 16 FSK modulation and can be configured to produce UO modulation in which case the signal interfaces are the same as for Fl 4 x 7164Fl 1 x produces GMSK GFSK modulation and can also be configured to produce UO modulation in which case the signal interfaces are the same as for FI 4 x In receive the UO interface provides amplitude information so the RSSI signal is calculated internally It is averaged in order to produce the RSSI measurement and to support the carrier sense decision whether to transmit X oe CMX7164 INPUT TR ki Radio Receiver QINPUT E Receive Processing Transmit Processing IOUTPUT QOUTPUT Mix onto RF carrier and linearise if required Figure 11 CMX7164 I Q Tx I Q Rx 2015 CML Microsystems Plc Page 23 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 6 3 Signal Interfaces Two point Tx and I Q Rx Fl 2 x produces 4 FSK modulation and can be configured to produce two point modulation Fl 1 x produces GMSK GFSK modulation and can also be configured to produce two point modulation This option is not applicable for Fl 4 x The UO interface is the only option available for receive XX PD CMX7164 IINPUT T R Receive Radio Receiver Processing QINPUT Transmit Processing
51. is used as it is specified in ETSI standard EN 300 113 for co channel tests The 2015 CML Microsystems Plc Page 114 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 2015 CML Microsystems Plc CMX7164 Multi Mode Modem CMX7164 EN 300 113 it means that the data presented here gives a true representation of the performance of the 7164Fl 4 x modem rather than being partially influenced by the thermal noise level The methodology is in line with standards for 6 25kHz channel spaced systems EN 301 166 measurement is taken at approximately 20dB above sensitivity and although this is not in line with 1 0E 02 N X E x en euni 4QAM Raw EN 16QAM Raw 64QAM Raw LI N i s 1 0E 03 D a N 1 D H H S M d n E 1 0E 04 Y m i s 1 1 U i B i Y H 1 0E 05 7 10 13 16 19 22 25 28 Co channel Rejection Ratio dB 1 0E 02 Figure 93 Modem Co channel Rejection with FM Interferer as EN 300 113 4QAM Raw P 4QAM Block Type 0 4QAM Block Type 6 4QAM Block Type 7 1 0E 03 tc LU m 1 0E 04 1 0E 05 Figure 94 4 QAM Performance with Different Coding Schemes 10 12 Signal to Noise Ratio dB Page 115 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 1 0E 02 16QAM Raw 16QAM Block Type 0 1 Seet H 1 0E 03 z E 16QAM Block T
52. o Deviation control without manual trim Tx o lO nms e C BUS host Serial Interface o SPHlke with register addressing o Read Write 128 byte FIFOs and data buffers streamline transfers and relax host service latency Q 9 00 Q O O O O O O Q O O 000006 2015 CML Microsystems Plc e Auxiliary Functions Four 10 bit DACs Autonomous RAMDAC sequencer Automatic support for dc calibration of CMX998 Four 10 bit ADCs ADC averaging and trip on high low watch modes o Four GPIO o Sequence GPIO on Tx or Rx trigger o Start Tx on digital trigger input e Master C BUS SPI Serial Interface o Forexternal slave devices e g RF transceiver and synthesiser o Pass through mode expands host C BUS SPI capacity e Two Synthesised Clock Generators e Low Power 3 3V Operation with Powersave Functions e Small 64 pin VQFN and LQFP Packages 000006 Applications e High Performance Narrowband Data Radio Telemetry SCADA data modems 6 25kHz to 25kHz RF channel spacing Compatible worldwide e g ETSI FCC ARIB etc FCC Part 90 per new spectral efficiency requirements Digital Software Defined Radio SDR High speed Wireless Data Mobile Data over Fading Channels V 23 compatibility for interoperability with legacy equipment in the field Oo Oo O O CMX7164 Multi Mode Modem CMX7164 KE a d Aux Aux Aux
53. symbol timing of the input signal as required Use of the recommended Rx Process note Y Load Command FIFO with Rx data command s Set Modem Control to Rx and receive either framesync If enabled i noe gt IRQ FrameSync will occur before IRQ DataRdy No p uum 5 IRQ Nn mdDone or Rx FIFO yes Y Load Command FIFO Load data from Rx FIFO with further Rx data automatic tracking modes is Data may be in variable size blocks and or EN may be processed irregularly by the hos The Modem will start to look for frame sync The host should ensure that any external hardware is also set into Rx mode if not automatically controlled by the GPIO pins m d Further data is requested the device will buffer data internally Therefore an internal data overflow can occur if the Command FIFO is not written command s An lt IRQ DataRdy No more data to may still be receive cl Ge pending at this I yes promptly Transmission No Set Modem Control to Idle hc Yes Y Goto Tx Process note AC See Tx Process Flow Diagram AH y LATT 8 n Goto Idle Process Figure 18 Host Rx Data Flow 2015 CML Microsystems Plc Page 37 The Modem will drop into Idle mode The host should ensure that any external hardware is also set into Idle mode if not automatica
54. the dynamic range shown in Figure 72 without any need for an AGC Note that this is limited at the top end by the maximum allowed signal amplitude into the CMX7164 but performance at the bottom end is affected by noise added by the test receiver so these figures are not the absolute limit of CMX7164 Fl 1 x 2 x 4 x 6 x performance Results for 8 FSK and 16 FSK operation should be corrected for the different Eb No of the modulation 9 6 4 Receiver Response Equaliser Performance The performance of the 7164Fl 2 x when receiving a signal using the EV9942 CMX994 with temperature compensated baseband filter is shown in the following graphs The EV9942 includes a baseband channel filter the nominal bandwidth of which is 8kHz 3dB 8 The following tests were carried out using a 4 8ksymbols s 8 FSK or 16 FSK signal and are representative for a typical 12 5kHz RF channel Where the results are quoted as using no equalisation the Receiver Response Equaliser was disabled Where the results are quoted as Equalised the Receiver Response Equaliser was provided with a training sequence at a level of 70dBm which produced 400mV 8 EV9942 with default components fitted and Mid channel bandwidth selected Rx Control Register 12 b4 b3 01 2015 CML Microsystems Plc Page 99 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 differential on the and Q inputs Equaliser gain was set to 1000 and training lasted for 100
55. the host detects a brownout the BOOTEN1 2 pins should be set to re load the Fl A General Reset should then be issued or the RESETN pin used to reset the CMX7164 and the appropriate FI load procedure followed Streaming C BUS may be used to load the Modem Command FIFO Word 49 write register with the Function Image and the Modem Command FIFO Level 4B read register used to ensure that the FIFO is not allowed to overflow during the load process The download time is limited by the clock frequency of the C BUS with a 5MHz SCLK it should take less than 250ms to complete even when loading the largest possible Function Image 2015 CML Microsystems Plc Page 28 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 BOOTEN2 1 BOOTEN1 1 i Power up or write General Reset to CMX7164 Y BOOTEN1 and BOOTEN2 may be Read the RxFIFO Level 4F until 3 device check changed once it is clear that the CMX7164 words appear in RxFIFO Word 4D Read and has comitted to C BUS boot i e when a discard them word has been read from the C BUS T command FIFO Block number N 71 4 bd Write Block 1 Length DBN_len to CmdFIFO Word 49 Y Write Start Block N Address DBN ptr to CmdFIFO Word 49 E SE Check CmdFIFO Level 4B Y Write up to 128 FIFO fill level words to CmdFIFO Word 49 K End of Block
56. to be 0dB the Fine Output adjustment has a maximum attenuation of 6dB and no gain whereas the Coarse Output adjustment has a variable attenuation of up to 14 2dB and 6dB gain The signals output from Output and Q Output may be independently inverted Inversion is achieved by selecting a negative value for the linear Fine Output adjustment When transmitting UO format signals inverting one of the I Q pair has a similar effect to swapping with Q DC offsets may be added to the signal however care must be taken that the combination of gain and dc offset does not cause the signal to clip at any point in the signal processing chain which is Fine gain followed by dc offset addition followed by coarse gain The nature of the QAM modulation produced by Fl 4 x means that the UO signal envelope naturally ramps up at the start of a transmission as symbols are modulated and ramps down at the end This has the effect of reducing switch on off transients especially when using the CMX998 Cartesian Loop IC The modulation created by Fl 1 x and Fl 2 x is constant envelope so there is no inherent ramping effect To address this when using Fl 1 x and Fl 2 the modulation envelope can be optionally ramped up and down at beginning and end of a transmission this option is selected using Program Block 4 Modulation Control See e 13 1 8 UO Output Control 5D 5E write e 13 1 23 I Q Output Coarse Gain B4 B5 write e 13 2 6 Program Block 4 Modul
57. transmitted modulation has been adjusted to give a realistic Tx ACP in the 6 25kHz and 12 5kHz case the Tx ACP was 63dBc and in the 25kHz case the Tx ACP was 73dBc The pulse shaping filter used was an RRC with no sinc filter in place The modulation parameters used in all of the figures that follow in this section are summarised below Channel Baud Rate Pulse Shaping Deviation Measured Receiver Noise Used in Bandwidth Symbols s Filter kHz Tx ACP Bandwidth kHz Figures kHz dBc 25 9600 RRC Only 2 85 72 18 Figure 68 12 5 4800 RRC Sinc 2 45 63 9 Figure 69 12 5 4800 RRC Only 1 9 63 9 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 6 25 2400 RRC Only 0 95 63 4 5 Figure 68 O 2015 CML Microsystems Plc Page 91 D 7164 Fl 1 X FI 2 X FI 4 X Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 1 00E 02 x im 6 25k Channel n DE m 12 5k Channel er SG 25k Channel 1 00E 03 Es H 1 00E 04 a 1 00E 05 1 00E 06 10 0 11 0 12 0 13 0 14 0 15 0 16 0 17 0 18 0 19 0 20 0 Signal to Noise Ratio dB Figure 68 Modem Sensitivity Performance Root Raised Cosine Pulse Shaping The 7164F1 2 x supports pulse shaping filters using an alternative RRC plus sinc filter option Simply switching from a RRC Only filter to this filter reduces the bandwidth of the modulated signal so an increased deviation was used to return th
58. x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 maximum that the CMX7164 can achieve but are limited by the practical dynamic range of the CMX7164 combined with the system gain and noise figure of the receiver used in these tests 2015 CML Microsystems Plc Page 129 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem 12 Performance Specification 12 1 Electrical Performance 12 1 1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device CMX7164 Min Max Units Power Supplies DVpp DV ze 0 3 4 0 V DVcore ig DVss 0 3 2 16 V AVpp AVss 0 3 4 0 V Voltage on any pin to Vss 0 3 lOVpp 0 3 V Voltage differential between power supplies DV np and AVpp 0 0 3 V DVss and AVss 0 50 mV L9 Package 64 pin LOFP Min Max Units Total Allowable Power Dissipation at Taus 25 C 1690 mW Derating 16 9 mW C Storage Temperature 55 125 C Operating Temperature 40 85 C Q1 Package 64 pin VQFN Min Max Units Total Allowable Power Dissipation at Tams 25 C 3500 mW Derating 35 0 mW C Storage Temperature 55 125 C Operating Temperature 40 85 C 12 1 2 Operating Limits Correct operation of the device outside these limits is not implied Min Typ Max Units DVpp DVss 3 0 3 8 3 6 V DVcore DVss 1 7 1 8 1 9 V AVpp AVss 3 0 3 3 3 6 V Voltage differential between power supplies DVpp and AVpp 0 0 3 V DVss and AVss 0 50 mV Operating Temperature 40 85
59. x Typical Receive Performance 95 Optimum performance is achieved with OHz frequency error The figure quoted is for a symbol rate of 18ksymbols s The frequency error tolerated is proportional to the symbol rate 96 A user programmable filter option is also provided allowing for compensation for external hardware and different o values than those provided 2015 CML Microsystems Plc Page 141 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 12 1 7 7164Fl 6 x Parametric Performance For the following conditions unless otherwise specified External components as recommended in Section 5 Maximum load on digital outputs 30pF Clock source 19 2MHz clock input Taus 40 C to 85 AVpp DVpp 3 0V to 3 6V All figures quoted in this section apply to the device when loaded with FI 6 x only The use of other valid Function Images can modify the parametric performance of the device DC Parameters Notes Min Typ Max Unit Supply Current Rx Mode Dipp search for FS 1 4 mA Dipp FS found 2 5 mA Alpp AVpp 3 3V 7 8 mA Tx Mode 70 Dinn 1200symbols s 1 3 mA Alpp AVpp 3 3V 7 8 mA Notes 70 Transmitting in UO mode continuous PRBS all GPlOs and RAMDAC set to manual 2015 CML Microsystems Plc Page 142 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 AC Parameters Notes Min Typ Max Unit Modem Symbol Rate 1200 sym s Modula
60. 00 symbol periods While training the received signal had less than 100Hz frequency error Once trained the resulting equaliser coefficients were used for the remaining tests Firstly the signal to noise performance of equalised and non equalised received signals are compared The test is similar to that described in 9 6 1 1 Signal to Noise and Co channel Performance 1 00E 01 1 00E 02 Not Equalised Equalised 1 00E 03 tc LU t 1 00E 04 1 00E 05 N 1 00E 06 8 0 9 0 10 0 11 0 12 0 13 0 140 15 0 16 0 17 0 18 0 Signal To Noise Ratio dB Figure 78 4 FSK Signal to Noise Performance Equalised and Non Equalised 2015 CML Microsystems Plc Page 100 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 1 00E 01 1 00E 02 Not Equalised Equalised 1 00E 03 D e N 1 00E 04 N N N N N N 1 00E 05 1 00E 06 15 0 17 0 19 0 21 0 23 0 25 0 27 0 29 0 31 0 Signal To Noise Ratio dB Figure 79 8 FSK Signal to Noise Performance Equalised and Non Equalised 2015 CML Microsystems Plc Page 101 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 1 00E 01 eat em dl wn 1 00E 02 Not Equalised 1 00E 03 Equalised ER 1 00E 04 1 00E 05
61. 0pF Clock source 19 2MHz 0 002 20ppm clock input Tams 40 C to 85 AVpp DVpp 3 0V to 3 6V Reference signal level 308mV rms at 1kHz with AVpp 3 3V Signal levels track with supply voltage so scale accordingly Signal to Noise Ratio SNR in bit rate bandwidth Input stage gain OdB Output stage attenuation OdB All figures quoted in this section apply to the device when loaded with Fl 2 x only The use of other valid Function Images can modify the parametric performance of the device DC Parameters Notes Min Typ Max Unit Supply Current Rx Mode Dipp 4 8ksymbols s search for FS 12 9 mA Dlpp 9 6ksymbols s search for FS 20 2 mA Dipp 4 8ksymbols s FS found 8 7 mA Dipp 9 6ksymbols s FS found 11 6 mA Alpp AVpp 3 3V 7 7 mA Tx Mode 69 Dipp 4 8ksymbols s 6 4 mA DIpp 9 6ksymbols s 9 2 mA Alpp AVpp 3 3V 8 0 mA Notes 69 Transmitting in UO mode continuous 4 FSK PRBS all GPIOs and RAMDAC set to manual 2015 CML Microsystems Plc Page 138 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 AC Parameters Notes Min Typ Max Unit Modem Symbol Rate 2 000 10000 syms Modulation 2 FSK or Filter RRC Alpha 0 2 Tx Bit rate Accuracy 70 ppm Tx Output Level I Output Q Output 71 Fl 2 x I Q modulation mode 2 6 Vp p Fl 2 x Two point modulation mode 4 1 Vp p Tx Adjacent Channel Power Output Q Output 72 dB
62. 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 FLO AGING TOM Foster pisa 29 FI Loading from Serial Memory sse eee eee eee eee eee 30 Host Tx Data Flow No Tx Sequence Carrier Genee 36 Host Rx Data Flow iiie ive tu ima bo eat bana 37 GCatrierSOnse ese eege dee s tL toS 39 Transmit Geouence ANERER A0 CMX998 DC Calibration Interfaces sese eee eee eee eee eee 41 Transmit Constellation 77164 A xl 43 Transmit Eye Diagram 7164Fl 2 X ssie nennen 43 Transmit Eye Diagram 7164F1 1 x sese ener nennen 43 Constellation Diagram no frequency or phase error eee ee eee eee eee 44 Constellation Diagram phase error sse 44 Constellation Diagram frequency error sse 44 Received Eye Diagram7164 Fl 2 x 4 FSK mode sss sees eee eee 44 Received Eye Diagram7164 Fl 1 x sssssssseseee eene eene eren 45 Sample at Symbol Timing with UO DC Offset Diagnostic Mode no frequency error 45 Sample at Symbol Timing with UO DC Offset Diagnostic Mode with frequency error 45 Normalised Constellation even with a frequency or
63. 40 4 81 bytes 73 bytes 4 bits 5 176 bytes 0 55 0 61 174 2 176 172 4 321 bytes 289 bytes 4 bits 6 73 bytes 0 52 0 58 71 2 73 69 4 141 bytes 127 bytes 4 bits 7 292 bytes 0 52 0 58 290 2 292 288 4 561 bytes 505 bytes 4 bits 8 88 bytes 0 55 0 61 86 2 88 84 4 161 bytes 145 bytes 4 bits 9 352 bytes 0 55 0 61 350 2 352 348 4 641 bytes 577 bytes 4 bits 10 104 bytes 0 65 0 72 102 2 104 100 4 161 bytes 145 bytes 4 bits 11 416 bytes 0 65 0 72 414 2 416 412 4 641 bytes 577 bytes 4 bits 2015 CML Microsystems Plc Page 106 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 10 4 7164FI 4 x Receiver Response Equaliser When receiving signals using a radio receiver the signal provided to the CMX7164 is likely to be distorted Considering the architecture of Figure 83 as typical the distortion will largely be caused by the crystal filter shown as a bandpass filter in the diagram The crystal filter operates on the received signal at an intermediate frequency its purpose is to attenuate unwanted signals such as those on adjacent channels before they get to the CMX7164 11 Typically the pass band of the crystal filter is not flat or perfectly linear phase resulting in the wanted QAM signal being distorted due to the amplitude phase response of the filter The result is usually a significantly degraded receive signal and therefore poor receive performance Other radio architectu
64. 448 MHz Span 66 kHz Modulation Spectrum EN 300 113 Adjacent Channel measurement for 25kHz channel ACP lt 81dB limit is 60dB Integration window 16kHz Peak deviation 1 symbol 2 4kHz Ref Lvl 0 dBm 448 MHz Meas Signal 9 6 kHz Eye I Demod 2FSK REAL Ti 100m SYMBOLS Eye Diagram Deviation for 1 symbol 2 4 kHz Figure 48 Tx Modulation Spectra GMSK 9 6kbps BT 0 5 UO Modulation 2015 CML Microsystems Plc Page 66 D 7164 Fl 1 x Fl 2 x F1 4 x F1 6 x 22 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 RBW 200 Hz RF Att 30 dB Ref Lvl 24 60 dBm VBW 1 kHz O dBm 447 99923948 MHz SWT 4 2 s Unit dBm Modulation Spectrum EN 300 113 Adjacent Channel measurement for 25kHz channel 30 ACP lt 73dB EX limit is 60dB Integration window 8kHz 60 70 Peak deviation 1 symbol 2 0kHz 80 90 e 100ll Center 448 MHz 3 3 kHz Span 33 kHz CF 448 MHz Meas Signal Ref Lvl SR 8 kHz Eye I 0 dem Demod 2FSK 100m REAL mi Eye Diagram EXT BURST NOT FOUND 100m 0 SYMBOLS 4 Figure 49 Tx Modulation Spectra GMSK 8kbps BT 0 3 UO Modulation
65. 8ksymbols s Adjacent Channel measurement for 25kHz channel ACP 75dB Integration window 16kHz Center 450 HHS 6 6 kHz Span 66 kHz Figure 90 Tx Modulation Spectra 64 QAM 18ksymbols s UO Modulation into CMX998 For a particular baud rate we can see that the spectral shape and adjacent channel power measurements for each QAM type are almost identical This is to be expected as each is generated using the same filters The average power generated will vary though as each type of QAM used has a different peak to mean ratio and the CMX7164 transmits each with the same peak power 2015 CML Microsystems Plc Page 112 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 RBW 200 Hz RF Att 20 dB Ref Lvl 6 40 dBm VBW l kHz 30 dBm 445 55742084 MHz SWT 4 2 s Unit dBm 30 d aa Ya emn os 16 QAM Modulation spectrum 449 959742 084 MHz 20 exu a with 9ksymbols s ACH Ug 76 58 dB 19 VT A i a Ge Adjacent Channel measurement for 12 5kHz channel D ax ACP 76dB 10 exr Integration window 8kHz 20 30 40 50 CO co ell cu ok LU PLUME RO rif HI d Omg Center 450 MHz 3 35 kHz Span 33 5 kHz REAI 1 87 Constellation Diagram Receiver filtered 450 MHz Meas Signal sh 9 KNS Constellation Demod 160AM BUR
66. 9 C10 pF 100 22 33 50 20 75 25 22 150 12 5 22 270 Figure 10 Recommended External Components UO Output Reconstruction Filter When transmitting an UO signal each I Q output will produce a signal with bandwidth half the channel bandwidth A reconstruction filter with a 3dB point close to half the channel bandwidth will therefore have significant roll off within the channel bandwidth which is undesirable An appropriate choice for channels occupying up to a 25kHz bandwidth channel bandwidth 2 12 5kHz would be a reconstruction filter of 25kHz bandwidth 5 4 VQ Input Antialias Filter The device has a programmable antialias filter in the UO input path which is controlled using the UO Input Configuration BO write or Signal Control 61 write registers This should be sufficient for most applications however if additional filtering is required it can be done at the input to the device The input impedance of the UO Input pins varies with the input gain setting see section 12 1 3 Operating Characteristics 5 5 GPIO Pins All GPIO pins are configured as inputs with an internal bus hold circuit after the Function Image has been loaded This avoids the need for users to add external termination pullup pulldown resistors onto these inputs The bus hold is equivalent to a 75kQ resistor either pulling up to logic 1 or pulling down to logic 0 As the input is pulled to the opposite logic state by the user the bus hold r
67. CML Microcircuits COMMUNICATION SEMICONDUCTORS CMX7164 Multi Mode Modem DATASHEET D 7164_FI 1 x Fl 2 x FI 4 x Fl 6 x 22 May 2015 Provisional Issue 7164FI 1 x 7164F1 2 x 7164FI 4 x and 7164Fl 6 x Multi Mode Modem Features e Half duplex modem supports multiple modulations and channel spacings e 7164Fl 1 x o GMSK GFSK with BT 0 5 0 3 0 27 or 0 25 o Over air compatible with FX MX909B and CMX7143FI 1 x Two frame sync detectors Automatic frame sync detect Rx carrier frequency correction Receive signal quality measurement e 7164Fl 2 x 2 4 8 16 FSK up to 10ksymbols s in 25kHz e g 40kbps for 16 FSK o Compatible FEC for CMX7143 and FX MX919B 4 FSK not 2 FSK o Over air compatibility with CMX969 for RD LAP Tx Rx Two frame sync detectors Automatic frame sync detect Rx carrier frequency correction Receive signal quality measurement e 7164Fl 4 x 4 16 64 QAM up to 96kbps in 25kHz Different rate robust FEC choices Channel estimation and equalisation Two frame sync detectors Automatic frame sync detect Rx carrier frequency and phase correction Receive signal quality measurement e 7164Fl 6 x V 23 modulation Two frame sync detectors Automatic frame sync detect Rx carrier frequency correction Receive signal quality measurement e High Performance UO Radio Analogue Interface o Txand Rx direct connect to zero IF transceiver o Simple external RC filters o Digital IF filter reconfigures for multiple RF channel spacings Rx
68. CMX998 Cartesian Feedback Loop DC Calibration are both available from the CML website www cmlmicro com and should be referred to for a more in depth understanding of the need for dc offset calibration The CMX7164 performs automatic dc offset calibration as either part of a transmit sequence or in a separate calibration stage DC offset calibration determines the dc offset that should be applied to the I Output and Q Output signals by the CMX7164 to minimise carrier leakage The results of calibration will be held by the CMX7164 for use in later transmissions and are made available to the host The interface is required to be as shown in Figure 21 CMX998 DC Calibration Interfaces I Input A I Output a Q Input A Q Output DCMEAS B AuxADC2 gt CMX998 CMX7164 SPI Thru Port gee In C Chip Sel SSOUT1 PA Cntrl D AuxDAC1 RAMDAC rai A The CMX7164 I and Q Outputs are used to provide dc levels which are adjusted to make the error I Q measurements equal to the Reference I Q measurements B AuxADC2 is used to sample DCMEAS To measure Reference signals and error signals C The SPI Thru Port is used to control the CMX998 selecting Reference UO and Error UO as measurements as well as high gain low gain modes of the CMX998 D The RAMDAC is typically used to ramp up the PA Control voltage after calibration is complete This is not a part of the calibration sequence but may be active as part
69. EIS a ze N S GE Ch L t Figure 28 Received Eye Diagram7164 Fl 2 x 4 FSK mode 2015 CML Microsystems Plc Page 44 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Figure 29 Received Eye Diagram7164 FlI 1 x Rx Diagnostics 7164FI 4 x only A diagnostic mode is provided that produces channel filtered I Q signals and an optional dc offset correction indication This aids in diagnosing reception issues that may be related to UO dc offsets in the CMX7164 input signal This diagnostic mode can still be of use when there is a frequency error present in the received signal As shown in Figure 30 and Figure 31 the estimated UO dc offset correction is an extra dot in the centre of the constellation d D 3 P la Go ill TS N v Pe i FT K te NAHE BR er 19 umm rs BB F d 8 EN BB Nr DE d a i amp jl m o amp Is fra b ai p Fi IT LTH be Plog dee Sat P A al asa e T Figure 30 Sample at Symbol Figure 31 Sample at Symbol Timing with UO DC Offset Timing with UO DC Offset Diagnostic Mode no frequency Diagnostic Mode with error frequency error A normalised received constellation diagnostic output is provided It relies on having d
70. Fax 44 0 1621 875600 Sales sales cmimicro com Tech Support techsupport cmlmicro com Tel 1 336 744 5050 800 638 5577 Fax 1 336 744 5054 Sales us sales cmlimicro com Tech Support us techsupport cmimicro com Tel 65 62 888129 Fax 65 62 888230 Sales sg sales cmimicro com Tech Support sg techsupport cmlmicro com www cmlmicro com 2015 CML Microsystems Plc Page 146 D 7164 Fl 1 x Fl 2 x F1 4 x F1 6 x 22
71. Frame Sync Detect Link Quality Detect va e Raw Mode Data RF Rx Iters RA e mapper Demod TTS na Gaange FSK Pulse Channel Decoder o Host Shaping Coded Error Correct uC Mode Data Si a Coded Mode Data Symbol Construct Frame Add OX Mapper BET UO Mod II 14 2 4 8 16 Ge FSK ramesync Pulse and Tails Raw Mode Data Shaping Filter Figure 3 Fl 1 x Fl 2 x Block Diagram UO Tx and Rx Auto Frame Sync Detect Link Quality Detect va c Raw Mode Data gt RF Rx Channel Filters PY e mapper Demod NTP 2418 16 FSK gt RZ Pulse Channel Decoder 2 Host Shaping Coded Error Correct E uc Filter Mode Data Detect gt ka Coded Mode Data FSK only Modi Symbol Construct Frame Add 2 Point RY Mapper RET weg TI 2741816 S Mod2 FSK ramesync Pulse nd tale Raw Mode Data Shaping Filter Figure 4 Fl 1 x Fl 2 x Block Diagram two point Tx with I Q Rx 2015 CML Microsystems Plc Page 14 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Auto Frame Sync Detect Link Quality Detect 5 PT va Raw M
72. IOUTPUT QOUTPUT MOD1 MOD2 Reference Y e g VCTCXO d Az PLL C2 Control VEQ Voltage Input Figure 12 CMX7164 Two point Tx I Q Rx 2015 CML Microsystems Plc Page 24 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 7 Detailed Descriptions 7 1 Xtal Frequency The CMX7164 is designed to work with a Xtal or an external frequency oscillator within the ranges specified in section 12 1 3 Operating Characteristics Program Block 1 see User Manual must be loaded with the correct values to ensure that the device will work to specification with the user selected clock frequency A table of configuration values can be found in Table 23 supporting baud rates up to 20ksymbols s when the Xtal frequency is 9 6MHz or the external oscillator frequency is 9 6 or 19 2 MHz Rates other than those tabulated within this range are possible see section 13 2 3 Program Block 1 Clock Control Further information can be provided on request The modem can operate with a clock or Xtal input frequency tolerance of 50ppm The receive performance will be compromised as the system tracks so a maximum tolerance of 20ppm is recommended 7 2 Host Interface A serial data interface C BUS is used for command status and data transfers between the CMX7164 and the host uC this interface is compatible with Microwire SPI and other similar interfaces Interrupt signals notify the host uC when
73. MX7164 Multi Mode Modem CMX7164 AC Parameters Notes Min Typ Max Unit Modulator UO Outputs I Output Q Output Power up to Output Stable 40 50 100 us UO Output Coarse Gain Attenuators Attenuation at OdB 42 0 2 0 0 2 dB Cumulative Attenuation Error 42 w r t attenuation at 0dB J 0 6 0 40 6 dB Output Impedance Enabled 41 600 Q J Disabled 41 gt 100 MO Output Voltage Range 43 44 0 3 AVpp 0 3 V Load Resistance 20 kQ Notes 40 Power up refers to issuing a C BUS command to turn on an output These limits apply only if Vgias is on and stable At power supply switch on the default state is for all blocks except the XTAL and C BUS interface to be in placed in powersave mode 41 Small signal impedance at AVpp 3 3V and Tamp 25 C 42 Figures relate to attenuator block only Design Value Overall attenuation input to output has a design tolerance of 0dB 1 0dB 43 For each output pin With respect to the output driving a 20kO load to AVpp 2 44 The levels of UO Output Fine Gain and Offset registers 5D and 5E should be adjusted so that the output voltage remains between 2096 and 8096 of AVpp on each output pin when OdB of coarse output gain is used This will produce the best performance when the device operates with AVpp 3 3V 2015 CML Microsystems Plc Page 134 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem AC Parameters cont Notes Auxiliary Signal Inputs AuxADC1
74. P udi I e o I AER GPIO Tx Rx Ny X Q9 I Input ot LNA Lo 2x ADC C BUS Q Q Input CMX992 A Thru C BUS Local Oscillator PA Gain Control RAMDAC a UE nn 1 Aux DACO 2x DAC E ry OS Directional Power x Coupler Amplifier L I Output at e Q Output HK eo zl gt 90 Local Oscillato ML Q9 CMX998 Figure 44 Outline Radio Design UO in out for GMSK GFSK Use of UO receive mode introduces the problem of UO dc offsets There are dc offsets caused by the radio receiver resulting in the signal into the CMX7164 having a dc offset other than BIAS The offset needs to be removed prior to demodulation Offsets typically remain constant for a particular radio frequency selected but will vary if that frequency is changed Gain within the radio receiver may also affect the dc offset seen by the CMX7164 UO dc offset effects are a radio issue which is beyond the control of the CMX7164 However the CMX7164 does provide dc offset calculation and removal These are described in detail in the application note Section 15 3 DC Offsets in I Q Receivers 2015 CML Microsystems Plc Page 62 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 8 2 2 Two point Modulation Transmit with UO Receive Interface An overview of how the CMX7164 might integrate with an UO receiver and two point
75. RBS conforming to ITU T O 153 Paragraph 2 1 is used to generate the PRBS The output created by transmitting a PRBS using 7164FI 4 x in 16 QAM mode is shown in Figure 22 The 16 constellation points are just visible on the plot Likewise the transmitted eye diagram when using 7164FI 2 x in two point modulation 4 FSK mode is shown in Figure 23 and the transmitted eye diagram when using 7164F1 1 x in two point modulation GMSK GFSK mode is shown in Figure 24 Figure 22 Transmit Constellation Figure 23 Transmit Eye Diagram 7164FI 2 x 7164FI 4 x Lap N w Figure 24 Transmit Eye Diagram 7164FI 1 x Rx Constellation 7164 Fl 4 x only A test mode to examine the Rx constellation diagram is also provided this utilises the IOUTPUTP N and QOUTPUTP N pins to produce a diagnostic signal where the RRC filtered UO signals are output This produces a two dimensional constellation diagram which may be displayed on an oscilloscope in X Y mode Note that best results are often obtained with an analogue oscilloscope 2015 CML Microsystems Plc Page 43 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Figure 25 Constellation Figure 26 Constellation Figure 27 Constellation Diagram no fr
76. ST NOT FOUND 1 8 4 1666667 PEAL a 1666667 exr cr 450 mur Bet ivi sp S kHz Syabol kzrors 25 ana Ben ed 160AM 21 dB Offrec Symbol Table o 00100011 01101110 11000111 01101100 00000010 ao 00011100 11000010 10100000 01110000 00111111 n DI 11100010 11001001 00000013 00001011 01010101 Error Summary Error Vector Mag Magnitude Error Phaze Error Freq Error Amplitude Droop IQ Offset 2 49 1 56 1 ems 71 deg rna 54 wHz 3 02 dh sym 0 25 1 5 71 4 Pk ac 4 51 3 Pk at 5 82 deg Pk at 81 54 mHz Pk Rho Faccor 0 9991 rns IQ Imbalance Error Vector Figure 91 Tx Modulation Spectra 16 QAM 9ksymbols s UO Modulation into CMX998 Comparing Figure 89 and Figure 91 demonstrates that changing baud rate simply scales the transmitted spectrum halving baud rate will halve the bandwidth occupied This relationship can be used to select the maximum baud rate for a given channel bandwidth 2015 CML Microsystems Plc Page 113 D 7164 FI 1 x FI 2 x FI 4 xX Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 10 6 7164FI 4 x Typical Receive Performance 10 6 1 Signal to Noise and Co channel Performance The performance of the 7164Fl 4 x when receiving is shown in the following graphs It should be noted that error rate performance depends on the modulation rate whether 4 QAM 16 QAM or 64 QAM is in use the coding type selected and the block size The 7164FI 4 x supports multiple combinations of these fac
77. a TxEnd command is processed or the mode is changed to Rx or Idle Data may be written to the Command FIFO prior to starting transmission enabling the host to create a buffer of data and therefore avoiding risk of the data running out during transmission Further buffering is provided to expand the amount of data that may be absorbed by the CMX7164 The host should write the initial data to the Command FIFO and then set modem control to the required transmit type with the Mode bits as Tx As soon as the data has been read from the C BUS TxData registers the Cmd Done IRQ and or Command FIFO IRQ will be asserted when configured correctly More data should be loaded into the Command FIFO at this stage before data buffered in the CMX7164 runs out otherwise an under run will occur To end the burst the host should send a TxEnd command signalling to the CMX7164 that the burst is to end and the imminent data under run is intentional It is possible to define a transmission sequence with defined RAMDAC ramp up down and GPIO on off events The transmission sequence is configured using Program Block 5 For precise control of the instant that transmission starts it is possible to trigger a transmission using GPIOA as an input Selecting a Tx mode with GPIOA configured as an automatic input places the device into a Tx pending state where it is neither receiving nor transmitting just waiting for a trigger on GPIOA to begin transmission In general Figure
78. address and data for a write operation or drives the address and receives the data for a read operation Commands can be called 0 1 or 2 byte reads or writes with a 0 byte write typically being a reset command As the word format is known then for convenience only the desired read data is returned to the host SPI mode is a little more flexible No assumption is made about the SPI word format nor any assumption that the length is a whole number of bytes See e 13 1 11 SPI Thru Port Control 62 write e 13 1 12 SPI Thru Port Write 63 write e 13 1 32 SPI Thru Port Read 78 read e 13 2 8 Program Block 6 SPI Thru Port Configuration 2015 CML Microsystems Plc Page 53 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 7 4 22 SPI C BUS AGC Using the SPI Thru Port the CMX7164 provides a method of controlling an external C BUS or SPI device capable of implementing variable gain steps When using I Q receive modes this allows for a fast response to large signals causing clipping and an increase in gain when the signal becomes too small Controlling the external device requires the host to program a table of eight SPI C BUS commands that the CMX7164 stores and outputs when a specific gain step is required In conjunction with each gain step that is output a second external device can also be enabled using one of the four available GPIO pins This feature is intended for use with RF systems using an external LNA o
79. al is being received it may be desirable to ensure that the gain is not changed unnecessarily This is typically the case with short bursts of data where it is likely that the signal amplitude will remain constant throughout the burst To help achieve this various AGC automatic modes are provided o Manual Gain Controlled manually always allowing user control and for control during latching in of I Q dc corrections o Full Auto Gain can increase and decrease during the search for frame sync and during burst reception o AGC lock on FS Gain can increase and decrease during the search for frame sync but once a frame sync is detected its level will be fixed o AGC down after FS Gain can increase and decrease during the search for frame sync but once a frame sync is detected its level will only decrease AGC changes during the frame sync can cause the frame sync to be corrupted and therefore not detected by the CMX7164 To avoid this problem the CMX7164 compares the incoming on channel signal to a Signal Detect Threshold the resulting AGC behaviour is as shown in Figure 41 2015 CML Microsystems Plc Page 55 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Clip threshold High threshold No backoff even if signal gt high threshold Detect threshold
80. al strength of the package fixing Where advised an electrical connection to this metal pad may also be required Figure 112 Mechanical Outline of 64 pin VQFN Q1 C teal i y I E B E B 2 PIN 1 Order as part no CMX7164Q1 DIM MIN TYP MAX A 9 80 10 20 B 9 80 10 20 C 1 40 1 60 D 11 80 12 20 E 11 80 12 20 H 0 05 0 15 J 0 17 0 27 L 0 45 0 75 P 0 50 T 0 09 0 20 X 0 7 Y 11 13 NOTE A amp B are reference data and do not include mold deflash or protrusions All dimensions in mm Angles are in degrees Co Planarity of leads within 0 4mm Figure 113 Mechanical Outline of 64 pin LQFP L9 Order as part no CMX7164L9 As package dimensions may change after publication of this datasheet it is recommended that you check for the latest Packaging Information from the Design Support Package Information page of the CML website www cmlmicro com 2015 CML Microsystems Plc Page 145 D 7164 Fl 1 x Fl 2 x F1 4 x F1 6 x 22 CMX7164 Multi Mode Modem CMX7164 h FirmASIC 0 Q UGU UU Gy About FirmASIC CML s proprietary FirmASIC component technology reduces cost time to market and development risk with increased flexibility for the designer and end application FirmASIC combines Analogue Digital Firmware and Memory technologies in a single silicon platform that can be focused to deliver the right feature mix performance and price for a target a
81. ange of applications requiring a selectable bit rate and robustness The 7164FI 2 x supports zero IF I Q and two point modulation Mod1 2 transmit modes with zero IF receive mode The data is over air compatible with the FX MX919B and the CMX 7143F1 2 x Additionally 4 FSK coded mode also supports RD LAP channel coding which is over air compatible with CMX969 The 7164F1 4 x supports 4 16 and 64 QAM modulations root raised cosine filtered with a 0 2 0 35 or a user programmable filter contact CML Technical Support for further information The 7164F1 4 x supports up to 96kbps in a 25kHz channel with channel estimation and equalisation to provide robust performance under realistic channel conditions The 7164Fl 4 x supports zero IF UO transmit and receive QAM data is over air compatible with the CMX7163F1 4 x The 7164Fl 6 x supports V 23 modulation at 1200 baud to provide half duplex modem functionality for interoperability with legacy equipment in the field The 7164FI 6 x supports 1 to 8 byte data blocks with start bit stop bit and parity generation in transmit and start bit stop bit and parity checking and removal in receive Within this Datasheet and the accompanying User Manual any reference to Fl1 x Fl 2 x Fl 4 x or FI 6 x is intended to refer to 7164Fl1 x 7164Fl 2 x 7164Fl 4 x or 7164F1 6 x respectively Forward error correction and raw modes are available and support user defined packet structures to support a range of app
82. anual 61 8ksymbols s 12 5kHz channel BT 0 3 9 6ksymbols s 25kHz channel BT 0 5 2015 CML Microsystems Plc Page 136 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 AC Parameters Notes Min Typ Max Unit Modem Symbol Rate 2 000 20000 syms Modulation GMSK GFSK Filter BT 0 25 0 27 0 3 or 0 5 Tx Bit rate Accuracy 62 ppm Tx Output Level I Output Q Output 63 FI 1 x I Q modulation mode 2 6 Vp p Fl 1 x Two point modulation mode 3 3 Vp p Tx Adjacent Channel Power Output Q Output 64 dB PRBS Rx Frequency Error Tolerated 66 1 0 kHz Rx Co channel Rejection 65 dB Rx Adjacent Channel Rejection 67 263 dB Notes 62 Determined by the accuracy of the Xtal oscillator provided 63 Transmitting continuous PRBS data This is a differential voltage Output IOUTPUTP IOUTPUTN and Q Output IOUTPUTP IOUTPUTN 64 See section 8 4 65 See section 8 5 66 Optimum performance is achieved with OHz frequency error The figure quoted is for a symbol rate of 9 6ksymbols s The frequency error tolerated is proportional to the symbol rate 67 Measured as per EN 300 113 offset 12 5kHz 8kbps BT 0 3 2015 CML Microsystems Plc Page 137 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 12 1 5 7164Fl 2 x Parametric Performance For the following conditions unless otherwise specified External components as recommended in section 5 Maximum load on digital outputs 3
83. ation Control 7 6 2 Receive Path Levels The Coarse Input has a variable gain of up to 22 4dB and no attenuation With the lowest gain setting 0dB the maximum allowable input signal level at the I Input or Q Input pins is specified in section 12 1 3 Operating Characteristics A Fine Input level adjustment is provided although the CMX7164 should operate correctly with the default level selected The primary purpose of the Fine Input level adjustment is to allow independent inversion of the UO Input signals Inversion is achieved by selecting a negative value for the linear Fine Input gain adjustment When receiving I Q format signals inverting one of the I Q pair has a similar effect to swapping I with Q DC offsets can be removed by the CMX7164 the offset to remove can be selected by the host or calculated automatically by the CMX7164 It should be noted that if the maximum allowable signal input level is exceeded signal distortion will occur regardless of the internal dc offset removal or attenuation See e 13 1 9 1 Q Input Control 5F 60 write e 13 1 20 I Q Input Configuration BO write 2015 CML Microsystems Plc Page 59 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 7 7 C BUS Register Summary Table 2 C BUS Registers Word ADDR Read Si Ize hex Write REGISTER bits C BUS General Reset WES 48 w Modem Command FIFO Data Byte 8 4A Ww Modem Command FIFO Co
84. ause of the different sensitivities of the EV9910B and EV9942 further plots are shown Figure 105 and Figure 106 where a constant signal to noise is used CMX992 No Equaliser 1 00E 01 CMX992 With Equaliser CMX994 No Equaliser 1 00E 02 CMX994 With Equaliser 1 00E 03 BER 1 00E 04 1 00E 05 1 00E 06 Temperature deg C Figure 105 Performance of 16 QAM Equalised Signals with Temperature Variation and Constant Signal to Noise Ratio 2015 CML Microsystems Plc Page 123 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 1 00E 01 1 00E 02 1 00E 03 BER 1 00E 04 N P CMX992 No Equaliser P N L CMX992 With Equaliser LER N P CMX994 No Equaliser L d CMX994 With Equaliser 1 00E 06 DM has m 7 x 7 1 00E 07 40 15 10 35 60 85 Temperature deg C Figure 106 Performance of 64 QAM Equalised Signals with Temperature Variation and Constant Signal to Noise Ratio 2015 CML Microsystems Plc Page 124 D 7164 FI 1 x FI 2 xX Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 11 7164Fl 6 x Features The 7164F1 6 x uses an FFSK modulation scheme compatible with ITU T V 23 with an over air bit rate of 1200bps Raw and formatted data can be transferred Formatting adds start stop and parity bits 11 1 7164FI 6 x Modulati
85. ay also be easily implemented with general purpose uC UO pins controlled by a simple software routine Section 12 2 C BUS Timing gives detailed C BUS timing requirements Note that due to internal timing constraints there may be a delay of up to 60us between the end of a C BUS write operation and the device reading the data from its internal register 2015 CML Microsystems Plc Page 25 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem C BUS single byte command no data CMX7164 CSN mete Pee ERA CIRCUM ces Note SCLK 1 The SCLK line may be high or low at the start and end of each CDATA 71615143 0 transaction MSB Address LSB RDATA Hi Z C BUS n bit register write CSN xmi mH SCLK s Er dr ISI sm qs cu OPER CDATA 71615141 3 0 n t n 2 n 3 2 0 MSB Address LSB MSB Write data LSB RDATA Hi Z C BUS n bit register read CSN Si s SCLK illl FL FL T FL DB B D B T B ZG Ls J LI LJ CDATA 7161514 3 0 MSB Address LSB RDATA Hiz ndM n 2 n3 2 0 MSB Read data LSB Repeated cycles Data value unimportant Either logic level valid but m
86. becomes v16 21 10 13 14 15 Added details of Fl 2 Equaliser operation 01 08 13 Added programming register control for I Q dc offset acquisition Added corrections to framesync programming register description Added power connection to pin 37 in Figure 7 Enhancements for custom filter support Added payload byte lengths to Tables 3 4 5 and 6 Document formatting corrected and typos clarifications 11 12 Added RD LAP channel coding block types in FI 2 x 15 03 13 18 Clarification of Fl 1 x channel coding 10 Add 8 FSK and 16 FSK operation in Fl 2 x 10 01 13 9 e Add GMSK GFSK operation in Fl 1 x 30 4 12 8 e Added details of Fl 4 Equaliser operation and control Mode register 9 1 12 programming block e Added details of programming block read mechanism Available for selected programming registers only e Updated receive performance curves for Fl 4 e Added description of soft decision output bits for Fl 2 only e Added details of bus hold function for unused inputs e Added details of Core regulator select e Corrected conditions under which current measurements were made e Changed reference to input impedance of I Q INPUTs e Typos clarifications 7 e Remove constraint on use of document with Fl 2 x as the latter is now 21 09 11 updated 6 e Advice in section 5 5 greyed out as not implemented in current FI 22 08 11 Wu e Added advice about terminating unconnected GPIO pins in section 5 5 17 8 11
87. ced into the signal The following tests were carried out using a 16ksymbols s 4 QAM 16 QAM or 64 QAM signal Where the results are quoted as using no equalisation the Receiver Response Equaliser was disabled Where the results are quoted as Equalised the Receiver Response Equaliser was provided a 4 QAM training sequence with level 70dBm which produced 400mV differential on the I and Q inputs Equaliser gain was set to 3000 and training lasted for 800 symbol periods While training the received signal had less than 100Hz frequency error Once trained the resulting equaliser coefficients were used for the remaining tests Firstly the signal to noise performance of equalised and non equalised received signals are compared The test is similar to that described in section 10 6 1 Signal to Noise and Co channel Performance except that as the baud rate is 16ksymbols s the RxBW parameter is 16000 Applying this factor also means that the results in section 10 6 1 may be directly compared to those below in Figure 100 12 Evaluation card for CMX991 CMX992 RF Quadrature Transceiver Receiver ICs 2015 CML Microsystems Plc Page 119 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 1 00E 01 PI Equalised 1 00E 02 Not Equalised 1 00E 03 BER 1 00E 04 1 00E 05 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 Signal To Noise Ratio dB Figure 100 4 QAM Signal t
88. ck 1 Clock Control The CMX7164 defaults to settings appropriate for a 19 2MHz externally generated clock with a baud rate of 9 6ksymbols s however if a different reference frequency is to be used or a different baud rate required then Program Block entries P1 1 to P1 6 will need to be programmed appropriately at power on A table of preferred values is provided in Table 23 along with details of how to calculate settings for other baud rates and crystal frequencies Prog Reg P1 2 bits8 0 PLL ClkIn 1 to Ref Clk XTAL VCO Clk MAIN PLL PLL ClkOut Main PLL out Tx Rx Active Prog Reg P1 5 Idle SYMBOL CLOCK Symbol DIVIDER Clock 1 to 256 Prog Reg P1 1 Idle P1 4 Active nterna CLK Internal Prog Reg P1 0 DIVIDER System Clk 1 to 64 Aux ADC CL DIVIDER Aux ADC Clock 3 to 1024 Figure 42 Main Clock Generation See e 13 2 3 Program Block 1 Clock Control 2015 CML Microsystems Plc Page 57 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 7 5 2 System Clock Operation Two System Clock outputs SYSCLK1 and SYSCLK2 are available to drive additional circuits as required The System Clock circuitry is shown in Figure 43 Digital System Clock Generation Schemes Having chosen the input frequency source system clock generation may be by simply dividing the input frequency source or via its own phase locked loop The syst
89. ck 11 Receiver Response Equaliser Fl 2 x and Fl 4 x e 15 9 Fl 4 x Receiver Response Equaliser Training Sequence 2015 CML Microsystems Plc Page 108 D 7164 Fl 1 x Fl 2 x F1 4 x F1 6 x 22 CMX7164 Multi Mode Modem CMX7164 10 5 7164FI 4 x Typical Transmit Performance The 7164F1 4 x transmits QAM modulation using an UO interface The modulation may be evaluated using a test system as illustrated in Figure 87 Tx Spectrum and Modulation Measurement Configuration for I Q Operation I Output O Spectrum Analyser pec CMX998 Vector Signal Analyser CMX7164 vo Transmitter Board Q Output Inputs CO PO Figure 87 Tx Spectrum and Modulation Measurement Configuration for UO Operation Some typical results are shown in the following figures The internal PRBS generator was used to generate the data in all the results shown Two baud rates are demonstrated 18ksymbols s which is typical of a 25kHz channel and 9ksymbols s which is typical of a 12 5kHz channel In all cases the transmit filter selected had a 0 2 Depending on transmitter requirements e g applicable standards faster baud rates may be possible 2015 CML Microsystems Plc Page 109 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 RBW 500 Hz RF Att 20 dB Ref Lvl 13 44 dBm VBW 2 kHz 30 dBm 450 00615030 MHz SWT 1 35 a Unit dBm i 0 00615H30 MHz 26 42 dBm 76 21 dB 76 aB
90. cond byte po Last byte Data value unimportant Either logic level valid but must not change from low to high Figure 14 C BUS Data Streaming Operation 1 For Command byte transfers only the first 8 bits are transferred 01 Reset 2 For single byte data transfers only the first 8 bits of the data are transferred 3 The CDATA and RDATA lines are never active at the same time The address byte determines the data direction for each C BUS transfer 4 The SCLK can be high or low at the start and end of each C BUS transaction 5 The gaps shown between each byte on the CDATA and RDATA lines in the above diagram are optional the host may insert gaps or concatenate the data as required 2015 CML Microsystems Plc Page 27 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 7 3 Function Image Loading The Function Image FI which defines the operational capabilities of the device may be obtained from the CML Technical Portal following registration and authorisation This is in the form of a C header file which can be included into the host controller software or programmed into an external serial memory The Function Image size can never exceed 128 kbytes although a typical FI will be considerably less than this Note that the BOOTEN1 2 pins are only read at power on when the RESETN pin goes high or following a C BUS General Reset and must remain stable throughout the FI loading process Once t
91. d UO Receive Intertaces eese nesrnssrnesrnssrnsens 125 11 3 X 7164Fl 6 x Formatted Data TT 125 11 4 7164Fl 6 x Typical Transmit Performance esee 125 11 5 7164Fl 6 x Typical Receive Performance AAA 128 11 5 1 Signal to Noise Performance eene 128 11 5 2 Adjacent Channel Performance see ee ee eee eee eee eee eee 128 12 Performance Specification rrnnnvrnnnvnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 130 12 1 Electrical Performance veniente iiia e i i ea 130 12 1 1 Absolute Maximum Ratings sese eee eee eee eee eee eee 130 121 2 Operating Sla coire e ee i a Edge gta amu tdg a 130 12 1 3 Operating Characteristics sse 131 12 1 4 7164FI 1 x Parametric Performance sse 136 12 1 5 7164FI 2 x Parametric Pertomance sese eee eee eee eee eee 138 12 1 6 7164Fl 4 x Parametric Performance eene 140 12 1 7 7164F1 6 x Parametric Performance sese eee eee eee eee eee 142 122 C BUS TIMING DEE 144 123 Packaging cendi tet ue det edn edet ae ie 145 Table Page T bl e 1 BO OTEN Pin States fis ugoe Eder EEN ei antalya die Vue ct pact T 28 Table 2 C BUS R istets oia certo qe e tora D eer Pee epu a e bee ago ada e drink sed 60 Table 3 Formatted Block Types and Sizes FL XT 65 Table 4 Native Formatted Block Types Sizes and Rates for 4 FSK Fl 2 x sssss 80 Table 5 Native Formatted Block Types Sizes and Rates for 8 FSK Fl 2 x
92. d general device control 9 CMX992 is an RF Quadrature IF Receiver 10 CMX998 is a Cartesian Feedback Loop Transmitter 2015 CML Microsystems Plc Page 105 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 10 3 7164FI 4 x Formatted Data The 7164Fl 4 x supports formatted data which provides the ability to channel code blocks of data using a variety of coding rates and CRCs A frame structure would typically consist of a 24 symbol frame sync pattern followed by a Header Block one or more Intermediate Blocks and a Last Block The Header block is self contained in that it includes its own checksum CRC1 and would normally carry information such as the address of the calling and called parties the number of following blocks in the frame if any and miscellaneous control information The Intermediate block s contain only data the checksum at the end of the Last block CRC2 also checks the data in any preceding Intermediate blocks This checksum calculation should be reset as required using the Reset CRC2 block type so that any transmitted CRC2 contains the CRC of only the desired blocks In receive it must be reset to match the expected input data block sequence A variety of different frame formats are possible some examples are illustrated in Figure 84 NORMAL SYMBOL FRAME HEADER LAST FAM SYNC SYNC INTERMEDIATE BLOCKS BLOCK SYMBOL FRAME LEADER BLOCKS SYNC
93. de baseband filtering in order to help reject unwanted adjacent channel signals Such filtering may also have a pass band that is not flat and therefore will degrade reception in a similar way The CMX7164 provides a Receiver Response Equaliser that will compensate for the group delay and variation in gain of the crystal filter or any other distortions present in the received signal The equaliser must be trained with a clean high level signal in order to establish the receiver response and produce a filter which compensates for it Once this filter is calculated it may be read from the CMX7164 and stored for later use The CMX7164 can be configured with up to two previously stored Receiver Response Equaliser filters which may for example be used to compensate for two different crystal filters in a radio designed to receive in two channel bandwidths Although trained using a signal the resulting filter is suitable to compensate for the receiver response whilst receiving 2 4 8 or 16 FSK signals A suitable training signal may either be produced using another 7 Note that the CMX7164 provides significant channel filtering itself but further rejection of unwanted signals is desirable in most applications to improve receiver dynamic range and prevent blocking or products generating intermodulation products reaching the low power back end of the receiver 2015 CML Microsystems Plc Page 83 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Mu
94. des a crystal filter Program Block 11 Receiver Response Equaliser Fl 2 x and Fl 4 x provides equaliser mode selection allows adjustment of the gain used in the feedback path when training the equaliser and allows the training time to be altered The same Program Block allows the filter resulting from training to be read for storage and to be programmed back in to the CMX7164 later for use when receiving An example of the effect of the receiver crystal filter on a 4 and 16 QAM signals is shown in Figure 85 Once the equaliser has been trained the resulting received signal was as shown in Figure 86 Each plot is gathered by using the Rx diagnostics mode of the 7164F1 4 x see section 7 4 12 Other Modem Modes for details 11 Note that the CMX7164 provides significant channel filtering itself but further rejection of unwanted signals is desirable in most applications to improve receiver dynamic range and prevent blocking or products generating intermodulation products reaching the low power back end of the receiver 2015 CML Microsystems Plc Page 107 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Figure 85 Received 4 and 16 QAM signals no equalisation Figure 86 Received 4 and 16 QAM signals with equalisation Results when using the Receiver Response Equaliser are shown in section 10 6 4 Receiver Response Equaliser Performance See e 13 1 18 Modem Mode and Control 6B write e 13 2 13 Program Blo
95. e Apply input signal The input signal should contain preamble Frame Sync 1 and then raw data The frame sync should be detected and Rx data made available Poll the IRQ Status 7E read register for bit 8 Cmd Done 1 Wait for data This indicates that the 4 data bytes requested have been received and are available Read the Receive FIFO Data Byte see Receive FIFO Data Control 4C 4D 4E read 4 times Retrieve the received data Data is read from the Receive Data FIFO Once 4 data bytes are read the IRQ Status register may be polled again to check if more data is available if required and then those data bytes read This step may be repeated as many times as needed End of reception Once enough data has been received a mode change using the Modem Mode and Control 6B write register will stop reception or start searching for another frame sync The procedure described above can be adapted making reception of different numbers of bytes bits or coded blocks possible The registers used for basic transmission and reception are e e 13 1 37 IRQ Status 7E read e e e 13 1 4 FIFO Control 50 write e 13 1 15 Rx Tracking 66 write 7 4 3 Features that can be configured include Full details of how to configure these aspects of device operation are given in section 13 2 in the User Manual 2015 CML Microsystems Plc 13 1 18 Modem Mode and Control 6B writ
96. e 13 1 3 Modem Command FIFO Data Control 48 49 and 4A write 13 1 26 Receive FIFO Data Control 4C 4D 4E read Device Configuration Using the Programming Register While in Idle mode the Programming register becomes active The Programming register provides access to the Program Blocks Program Blocks allow configuration of the CMX7164 during major mode change Flexible selection of Baud rates from 2k to 20k baud Pre amble and frame syncs to be using in transmit and receive Selection of Automatic control of 4 x GPIO and the RAMDAC during transmission Configuration of RAMDAC profile Configuration of RSSI averaging Configuration of the carrier sense window and thresholds Configuration of System Clock outputs Configuration of SPI Thru Port rate and word format Configuration of AGC commands using the SPI Thru Port Page 33 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 7 4 4 Device Configuration Using dedicated registers Some device features may be configured using dedicated registers This allows for configuration outside of Idle mode Configuration of the following features is possible Auxiliary ADC detect thresholds Auxiliary ADC input selection and averaging mode Output gain Output dc offsets Selection of AGC mode or manual control of the gain level The registers that allow configuration of these features are 13 1 8 I Q Output Control 5D 5E write 13 1 9 1 Q Input Control
97. e Sync Symbol Sync sent first last Figure 60 RD LAP Over Air Signal Format The Station ID and the Header block are self contained as they include their own checksums CRCO 6 bit CRC and CRC1 16 bit CRC respectively The Intermediate block s contains only data the checksum at the end of the Last block CRC2 32 bit CRC also checks the data in any preceding Intermediate blocks This checksum calculation should be reset as required using the Reset CRC2 block type so that any transmitted CRC2 contains the CRC of only the desired blocks In receive it must be reset to match the expected input data block sequence The CMX7164 performs all of the block formatting and de formatting the binary data transferred between the modem and its uC being that enclosed by the thick dashed rectangles near the top of Figure 60 When 2015 CML Microsystems Plc Page 82 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 receiving Station ID blocks Header blocks and Last blocks the CMX7164 will indicate CRC success or failure and will provide the data regardless In Figure 60 except for the Station ID block the size of data block illustrated is always 12 bytes when user bytes and CRC bytes are counted together The channel status symbols must be packed in a byte and provided along with the payload data as shown in Table 16 and Table 17 Table 7 RD LAP Block Types Sizes and Ra
98. e Tx ACP to 63dBc The graph in Figure 69 compares the performance of a 12 5kHz channel system with and without the sinc filtering included It can be seen that the sinc filter degrades the sensitivity by less than 0 5dB 2015 CML Microsystems Plc Page 92 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 1 00E 01 Pulse shaping RRC Only Pulse shaping RRC Sinc 1 00E 02 1 00E 03 BER 1 00E 04 1 00E 05 1 00E 06 l 10 0 11 0 12 0 13 0 14 0 15 0 16 0 17 0 Signal to Noise Ratio dB Figure 69 12 5kHz Channel Sensitivity With and Without Sinc Filter Comparison Data transfer may have channel coding applied to it when 4 FSK modulation is selected The graph in Figure 70 shows the improvement due to channel coding in the 12 5kHz channel case 4 8ksymbols s with an RRC only pulse shaping filter 1 00E 02 4 A 4FSK Raw 4FSK Block Type 2 1 00E 03 M 5 1 00E 04 E m N 1 00E 05 T 9 0 10 0 11 0 12 0 12 0 14 0 15 0 16 0 17 0 18 0 Signal to Noise Ratio dB Figure 70 Sensitivity 12 5kHz Channel 4 8ksymbols s With and Without Coding 2015 CML Microsystems Plc Page 93 D 7164_FI 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 The co channel rejection ratio Figure 71 is measured with an interferer modulated with 400Hz FM and having a deviation of 1 5kHz
99. ed independently of the others The following diagram illustrates transmit operation Time Modem Control Mode es z Mode CS or Tx X Reception mE Active if mode CS Inactive if Active High mode Tx E Carrier Sense Tx Trigger Input GPIOA Tx on Outputs S GPIOA D RAMDAC we Output Modulation i Preamble Data Tail Out N Sync Payload Bits Transmit i i i Calibration Cal Awaiting Tx Carrier Sense CMX9 i Pre Tx in Trigger on if selected may 98 DC ee ene Tx Ended Receive GPIOA if cause abort to Offset off if configured Configured Rx at any point Cal NEESS Figure 20 Transmit Sequence 7 4 11 CMX998 DC Offset Calibration UO Transmit Only When transmitting in UO mode the CMX7164 may be interfaced to a CMX998 Cartesian Loop IC The CMX998 is used to provide linearisation of the power amplifier used to transmit the modulation produced by the CMX7164 If the signal produced by the CMX7164 when no modulation is present does not exactly 2015 CML Microsystems Plc Page 40 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 match the dc reference of the CMX998 carrier leakage will result This worsens the transmitted signal quality DC offset calibration is intended to significantly reduce the carrier leakage The CMX998 Cartesian Feedback Loop Transmitter datasheet and an application note
100. eee eee eee eee eee eee 76 9 2 2 Two point Modulation Transmit with UO Receive Interface sss esse eee eee 78 9 3 7164F1 2 x Formatted Data ta eee cete re eee dae Ret 79 9 4 7164Fl 2 x Receiver Response Equaliser A 83 9 5 7164F1 2 x Typical Transmit Performance sese 84 9 6 7164F1 2 x Typical Receive Performance AA 91 9 6 1 E i eoe iere attt etm tet tet ets 91 9 6 2 8 FSKand 16 ESK iit ette ted eet Rem tette nte 95 9 6 3 Receiver Dynamic Range TTT 99 9 6 4 Receiver Response Equaliser Periormance se eee eee eee eee eee eee 99 T164Fl 4 x TE 104 10 1 7164F154 x ee E Le EE 104 10 2 7164Fl 4 x Radio Interface sss eee e sese enesenn ennenen 105 10 2 1 Control interfaces sse eee eee eee 105 10 3 7164Fl 4 x Formatted Data mener nnne nennen 106 10 4 7164Fl 4 x Receiver Response Equaliser AA 107 10 5 7164Fl 4 x Typical Transmit Performance sese 109 10 6 7164Fl 4 x Typical Receive Performance AAA 114 10 6 1 Signal to Noise and Co channel Pertommance 114 10 6 2 Adjacent Channel Performance sse eee ee eee eee eee eee eee 118 10 6 3 Receiver Dynamic Range sese 119 10 6 4 Receiver Response Equaliser Performance sene 119 alt Te ale 125 2015 CML Microsystems Plc Page 5 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 11 1 71 64F1 6 x Modulation et 2 EE RU e E E RAS 125 11 2 7164Fl 6 x Radio Interface sees 125 11 2 1 Q Transmit an
101. egister The 7164F1 2 x will search for Rx Payload modulation type is controlled by 0010 Sync1 and Sync2 P4 2 0100 Sync1 P4 2 0101 Sync2 P4 2 1001 Sync1 and Sync2 P4 2 1010 Sync1 P4 2 1011 Sync2 P4 2 1101 AutoModMode Sync1 and Sync2 P4 4 The bit to symbol mappings that this Function Image uses for 2 FSK and 4 FSK are 2 FSK bit to symbol mapping 4 FSK bit to symbol mapping Input Bit Relative Input Bit Relative Symbol Symbol Level Pair Level 0 3 00 1 01 3 1 3 10 1 11 3 The bit to symbol mappings that this Function Image uses for 8 FSK and 16 FSK are 2015 CML Microsystems Plc 8 FSK bit to symbol mapping 16 FSK bit to symbol mapping Input tri bits Relative Input quad Relative Symbol Symbol Level bits Level 000 1 0000 1 0001 3 001 3 0010 7 0011 5 010 7 0100 15 0101 13 011 5 0110 9 0111 11 100 1 1000 1 1001 3 101 3 1010 7 1011 5 110 7 1100 15 1101 13 111 5 1110 9 1111 11 Page 75 CMX7164 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 RRC filters are implemented in both Tx and Rx with a filter alpha of 0 2 Care has been taken to ensure that the maximum frequency deviation level is the same across all the different order modulations i e all of 2
102. em clock PLL does not affect any other internal operation of the CMX7164 so if a frequency that is not a simple fraction of the Xtal is required it can be used with no side effects There is one phase locked loop with independent output dividers to provide phase locked output signals SYSPLLCONO SYSPLLCON1 SYSPLLCON2 l VCO Clk SYSCLK PLL PLL ClkOut PLL ClkIn SysCikIn XTAL SYSCLKDIV1 b15 13 5 0 0 SYSCLKCON b1 0 SYSCLKT DIVIDER 1to 64 SYSCLK1 SYSCLKDIVI b11 6 SYSCLK2 DIVIDER SYSCLK2 SYSCLKDIV1 b12 d SYSCLKCON b5 4 Figure 43 Digital System Clock Generation Schemes See e 13 2 3 Program Block 1 Clock Control 7 6 Signal Level Optimisation The internal signal processing of the CMX7164 will operate with wide dynamic range and low distortion only if the signal level at all stages in the signal processing chain is kept within the recommended limits For a device working from a 3 3V supply the signal range which can be accommodated without distortion is specified in 12 1 3 Operating Characteristics Signal gain and dc offset can be manipulated as follows 2015 CML Microsystems Plc Page 58 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 7 6 14 Transmit Path Levels And Ramping For the maximum signal out of the I Q Outputs the signal level at the output of the modem block is set
103. equency or Diagram phase error Diagram frequency error phase error As shown in the third plot if there is any frequency error between transmitting and receiving CMX7164 devices then the diagram will spin and be difficult to interpret Therefore other diagnostic modes are provided as described below Any of the GPIO signals can be configured to produce a pulse train at the nominal symbol rate of the receiving CMX7164 to aid triggering whilst viewing the constellation diagram I Output or Q Output alone vs time or other diagnostic modes in receive In some cases it is advisable to obtain a trigger pulse that is synchronised to the transmitting modem symbol rate for example if the transmitted signal comes from a signal generator Rx Eye 7164FI 1 x and FI 2 x only A test mode to examine the Rx eye diagram is provided This utilises the IOUTPUTP N pins to produce a diagnostic output signal that may be used to create an eye diagram The diagnostic signal is produced by channel filtering the UO input signals FM demodulating the result and applying an Rx pulse shaping filter This produces a one dimensional eye diagram when displayed on an oscilloscope One of the CMX7164 GPIO pins may be used as an oscilloscope trigger signal that is locked to the symbol rate in order to display an eye diagram Note that best results are often obtained with an analogue oscilloscope ES SE I
104. er blocks one or more Intermediate blocks and a Last block Channel Status S symbols are included at regular intervals The first frame of any transmission is preceded by a Symbol Synchronisation pattern 2015 CML Microsystems Plc Page 81 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Station ID Header Block Intermediate Blocks Last Block 716 51413121110 161543 214191 74164 5 4 3 2 1 0 Byte 0 F 3 amp Byte 1 Byte2 E b Data bytes CRCO Ka Byte 3 Andes i 1 L 0 8 De Control L Data Bytes a H Byte 5 L 12 1 L Byte 6 10 bytes 4 L Es rw prer r 4 mm m m m m Byte 8 a Byte 9 I 1 CRC2 mm mm m mm m Byte 10 CRC1 L 1 4 bytes Byte 11 2 bytes i mm om mm mm m 7 07 rss 7 0 Byte11 Byte 11 x Ge ER RE B Eod KI KX S RSI ba Sd BSU RY FEC TRELLIS CODING DECODING ERROR CORRECTION FEC TRELLIS CODING DECODING ERROR CORRECTION Cary iaa SOOO symbols INTERLEAVING DE INTERLEAVING AO NX AEN 5 s s CSS S SC SCC SCC SC SCISCO SC SC SCC XC SCC XC XC XC XC XC XC XC XC X X Block Over air c c mmm symbols n 24 24 1 1 69 EL 69 E 69 FRAME is erc PACKET 1 TO 44 BLOCKS gt PREAMBLE NEXT FRAME Wen FRAME V OPTIONAL gt S Channel Status Symbol 3 Busy 1 Unknown 1 Unknown 3 Idle Fram
105. er devices Block diagrams of the device are shown in section 2 Block Diagrams Tx Functions Automatic preamble and frame sync insertion simplifies host control UO analogue outputs 7164F1 4 WO or two point modulation analogue outputs 7164 Fl 1 or Fl 2 Pulse shape filtering RAMDAC capability for PA ramping control Tx trigger feature allowing precise control of burst start time Tx burst sequence for automatic RAMDAC ramp and Tx hardware switching Carrier sense for listen before talk operation Raw and formatted channel coded data modes Flexible Tx coded data block size up to 416 bytes 7164FI 4 12 bytes 7164Fl 2 4 FSK 48 bytes 7164F1 2 8 16 FSK 18 bytes 7164FI 1 Rx Functions e Automatic frame sync detection simplifies host control UO analogue inputs Rx channel filtering and pulse shape filtering Channel estimation and equalisation Tracking of symbol timing and input UO dc offsets AGC using SPI Thru Port Raw and formatted channel coded data modes Flexible Rx coded data block size up to 416 bytes 7164F1 4 12 bytes 7164Fl 2 4 FSK 48 bytes 7164F1 2 8 16 FSK 18 bytes 7164FI 1 Auxiliary Functions e Two programmable system clock outputs e Four auxiliary ADCs with six selectable input paths e SPI Thru Port for interfacing to synthesisers Cartesian loop IC CMX998 direct conversion receiver CMX994 and other serially controllable devices e In build calibration routine to support CMX998 Cartesian loo
106. er which the CMX7164 will see Modem Command request more data from the host FIFO Data Control 48 49 and 4A write Write 8 data bytes to the Pre load the This provides a buffer of 8 data bytes before Modem Command FIFO Data Byte see Modem Command FIFO Data Control 48 49 and 4A write Command FIFO with data to transmit transmission starts so that the host does not need to write data as promptly for the rest of the burst Write 0042 to Modem Mode and Control 6B write Start transmission Initiates a transmission with preamble Frame Sync 1 and then the pre loaded data Poll the IRQ Status 7E read register for bit 8 Cmd Done 1 Wait until the data block has been read from the FIFO When this is complete a further 8 data bytes may be written to the Modem Command FIFO Data Byte see Modem Command FIFO Data Control 48 49 and 4A write and the IRQ Status 7E read register polled again This step may be repeated as many times as needed Write F000 to the Modem Command FIFO Word see Modem Command FIFO Data Control 48 49 and 4A write Indicate burst end is intended Indicate that no more data is to follow so when the data loaded into the Command FIFO is modulated the CMX7164 will terminate the burst with tail bits Poll the IRQ Status 7E read register for bit 9 Tx Last Tail 1 Wait until the burst ends The burst has completed
107. ering of data in addition to the Command and Rx FIFOs in both receive and transmit directions The amount of buffering offered is dependant on the mode in which the device is operating In the process of burst transmission or reception the most significant registers are 13 1 18 Modem Mode and Control 6B write 13 1 37 IRQ Status 7E read 13 1 19 IRQ Mask 6C write 13 1 3 Modem Command FIFO Data Control 48 49 and 4A write 13 1 26 Receive FIFO Data Control 4C 4D 4E read e Modem Command FIFO Level 4B read 2015 CML Microsystems Plc Page 31 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 e 13 1 27 Receive FIFO Level 4F read 7 4 2 Basic Tx and Rx Operation The CMX7164 has many features that provide a great deal of flexibility but basic data transmission and reception can be carried out fairly easily by understanding the operation of just a few registers There are other ways of controlling signal transmission and reception but basic examples are given below Basic Transmit Operation Transmission of raw data bytes uses the following procedure C BUS Operation Action Description Write 0080 to FIFO Control 50 write Flush the Command FIFO To ensure that no data is remaining from previous transmissions Write 18 to the Modem Select 8 byte data Selects blocks of data bytes to be transmitted Command FIFO Control Byte blocks 8 bytes in each aft
108. esistor will change so that it also pulls to the new logic state The internal bus hold can be disabled or re enabled using programming register P1 20 in Program Block 1 Clock Control If the device is reset either by asserting RESETN pin 7 issuing a C BUS General RESET or by triggering an internal power on reset all GPIO pins will be immediately configured as inputs Any GPIO pins not being pulled either up or down by an external load will be left in a floating state until the Function Image is loaded To avoid GPIO floating input states that may somewhat elevate supply current between a RESET and Function Image load it will be necessary to connect pull up or pull down resistors of 220kQ to these pins 2015 CML Microsystems Plc Page 21 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 6 General Description 6 1 CMX7164 Features The CMX7164 is intended for use in half duplex modems Transmission takes the form of a data burst consisting of preamble frame sync and data payload followed by a tail sequence Reception may utilise the preamble to assist with signal acquisition but is then followed by frame sync detection and data decoding A flexible power control facility allows the device to be placed in its optimum powersave mode when not actively processing signals The device includes a Xtal clock generator with phase locked loop and buffered output to provide a System Clock output if required for oth
109. et to two point modulation or UO When the 7164FI 2 x is in two point modulation mode the Output is used as Mod 1 and the Q Output is used as Mod 2 The receive signal must come from an UO radio receiver 9 24 IQ Transmit and I Q Receive Interfaces The 7164Fl 2 x can produce an WO modulated signal taking a baseband modulating signal and using it to frequency modulate an UO baseband signal with a user programmable deviation In receive the 7164F1 2 x will accept an UO input signal and provide significant channel filtering digitally It will then frequency demodulate the resulting signal which is treated as a limiter discriminator output signal would be internally An overview of how the CMX7164 might use the CMX992 for reception and the 5 CMX992 is an RF Quadrature IF Receiver O 2015 CML Microsystems Plc Page 76 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 CMX9988 for transmission is shown in Figure 56 The internal functions of the CMX7164 when operating in this mode are shown in Figure 3 Note that the transmit and receive interfaces are identical to those used for QAM modulation in Figure 83 facilitating multi mode modem operation However no linearisation is required when transmitting 2 4 FSK HOST Y dci feu ort Dea Le et ck nca EE GPlOn __ uP
110. etected a frame sync and therefore being able to output the signal level measured at the symbol timing instant with the frequency error removed and amplitude corrected So long as the CMX7164 remains locked to a suitable signal the normalised constellation output will remain static regardless of frequency error and amplitude of the input signal within limits see section 12 1 5 7164Fl 2 x Parametric Performance If the signal becomes noisy or its amplitude small then the constellation points will spread as shown in Figure 32 and Figure 33 2015 CML Microsystems Plc Page 45 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 a E amp der EA BES de lt E ud eh se g d ap x o By T JK L Jet e 8 4 E A EI Ke Q Figure 32 Normalised Figure 33 Normalised Constellation even with a Constellation noisy received frequency or phase error signal Rx Diagnostics 7164 FI 1 x Fl 2 x and FI6 x only A diagnostic mode is provided that produces channel filtered UO signals and an optional dc offset correction indication This aids in diagnosing reception issues that may be related to UO dc offsets in the CMX7164 input signal As shown in Figure 34 and Figure 35 the estimated UO dc offset correction is an extra dot in the centre of the constellation
111. file by writing to Program Block 0 The current profile may be scaled using the Signal Control 61 write register The AuxDAC outputs hold the user programmed level during a powersave operation if left enabled otherwise they will return to zero See 13 1 7 AuxDAC1 4 Control 59 to 5C write 13 2 2 Program Block 0 RAMDAC 13 2 3 Program Block 1 Clock Control 13 2 7 Program Block 5 Burst Tx Sequence 13 1 10 Signal Control 61 write 2015 CML Microsystems Plc Page 52 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 7 4 24 SPI Thru Port The CMX7164 offers an SPI Thru Port which allows the host using the main C BUS interface to command the CMX7164 to read or write up to three external SPI C BUS devices attached to the CMX7164 The CMX7164 acts as a SPI C BUS master in this mode controlling three chip selects clock and data out MOSI and receiving data in MISO Each individual SPI C BUS device can be independently configured using Program Block 6 SPI Thru Port Configuration to have clock speed inter frame guard period and clock phase polarity to match the specification of the slave SPI C BUS device attached In order to offer a simpler more convenient interface a device can be designated C BUS rather than SPI This means that data read written is assumed to be in the format Address byte data byte1 optional data byte 2 optional In each case the CMX7164 as the master drives the
112. gramming register P4 2 Applicable modulation type s for preamble and framesync Controlled by programming FEC available for payload data Controlled by Modem Mode and Control 6B write register register P4 2 2 FSK 2 FSK or 4 FSK No 4 FSK 4 FSK Yes 8 FSK 4 FSK Yes 16 FSK 4 FSK Yes Normally when receiving the 7164Fl 2 x can be programmed to receive data using a fixed modulation type In this case it will search for framesync 1 and or 2 and then continue to receive data according to the modulation type defined using the programming register P4 2 in Program Block 4 Modulation Control programming block This is the case for both raw and coded data reception Alternatively the device can be used in its AutoModMode selected using the Modem Mode and Control 6B write register In this mode the 7164F1 2 x will search for framesync 1 and 2 with the type of received framesync dictating the type of modulation for the payload data Programming register P4 4 in Program Block 4 Modulation Control programming block defines the relationship between the received framesync and the modulation type for the payload data in AutoModMode The following table lists the programming register which controls the payload modulation type for each receive mode 2015 CML Microsystems Plc Page 74 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem b11 8 of Modem Mode and Control 6B write r
113. h 18ksymbols s Ti 14 00 dam 50 00282369 MHz 26 u ua LT la Gp n uma Wd 1 1 1 Mtm Center 450 MHz 6 6 kHz Span 66 kHz d 10 Adjacent Channel measurement for 25kHz channel ACP 75dB Integration window 16kHz T 70 cr 450 MHz Meas Signal cr 450 HHs Neas Signal Ref Lv z le kHz Vector Bat ivi P 16 kHs Constellation ne ane Denod 160AM 35 dv peg eg regan 74 1666667 PEAL 4 166666 es c 450 MHz Pat ivl 5p 15 kHz Syabol Ecrocs 25 ana nas sd 160AM 31 dB Offset Symbol Table o 00111100 00000111 11110100 10000000 10001011 ao 01100011 01110101 00011110 10111100 00000000 ER Sp 01001000 01100010 00010000 90001110 01110011 Error Summary BURST NOT FOUND Brror Vector Mag 2 00 4 rus 4 32 4 Pk ac sys 125 Magnitude Error 1 25 ews 3 40 8 Pk at syn 106 Phaze Error 1 49 deg rms 5 06 deg Pk at zyn Sp Freq Error 257 49 wHz 257 49 m z Pk e P 9 72 t 998 SE EA em Amplitude Droop 3 72 dD sym Rho Factor H 3 1Q Offset 0 32 1 IQ Imbalance 1 17 8 Constellation Diagram Receiver filtered Error Vector Figure 89 Tx Modulation Spectra 16 QAM 18ksymbols s UO Modulation into CMX998 2015 CML Microsystems Plc Page 111 D 7164 FI 1 X FI 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Marker 1 Tl REW 500 Hz RF Att 20 dE Ref Lvl 11 62 dBm VBW 2 kHz 30 dBm 449 99742084 MHz SWT 1 35 s Unir dBm 64 QAM Modulation spectrum with 1
114. hannel filter was used Signal Level Input to CMX994 LNA dBm 121 120 119 118 117 116 115 1 00E 00 4 1 00E 01 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 00E 06 Figure 110 Signal Level vs BER 11 5 2 Adjacent Channel Performance Assessment of the adjacent channel rejection ACR performance of the modem is normally made in terms of BER or PER for a given ratio between the wanted signal on channel and larger interferer on the adjacent channel Detailed measurement methods vary depending on the standards in use in particular whether the wanted signal is raised above the sensitivity limit and where the reference is taken The figures quoted here are based on the measurement method from EN 300 113 The results are based on the difference between the interferer 400Hz FM modulation 1 5kHz deviation and the power of the wanted signal for 1 2ksymbols s Channel bandwidth Adjacent Channel rejection BER 12 5kHz 60dB lt 1 25kHz 70dB 196 The results shown here are typical of what may be achieved with 7164Fl 6 x and a typical UO radio receiver with no adjacent channel selectivity provided by receiver RF circuits Genuine RF receivers typically provide some adjacent channel selectivity that would make system performance better than the measured values for the 7164Fl 6 x alone Furthermore the results observed are not necessarily the 2015 CML Microsystems Plc Page 128 D 7164_Fl 1
115. he Fl load has completed the BOOTEN1 2 pins are ignored by the CMX7164 until the next power up or Reset The BOOTEN1 2 pins are both fitted with internal low current pull up devices For serial memory load operation BOOTEN2 should be pulled low by connecting it to DV e either directly or via a 47k resistor see Table 1 Whilst booting the boot loader will return the checksum of each block loaded in the C BUS Rx Data FIFO The checksums can be verified against the values provided with the FI to ensure that the Fl has loaded correctly Once the FI has been loaded the CMX7164 performs these actions 1 The product identification code 7164 is reported in the C BUS Rx Data FIFO 2 The FI version code is reported in C BUS Rx Data FIFO Table 1 BOOTEN Pin States BOOTEN2 BOOTEN 1 C BUS host load 1 1 reserved 1 0 Serial Memory load 0 1 reserved 0 0 7 89 4 Fl Loading from Host Controller The FI can be included into the host controller software build and downloaded into the CMX7164 at power up over the C BUS interface using the Command FIFO For Function ImageT load the FIFO accepts raw 16 bit Function Image data using the Modem Command FIFO Word 49 write register there is no need for distinction between control and data fields The BOOTEN1 2 pins must be set to the C BUS load configuration the CMX7164 powered or Reset and then data can then be sent directly over the C BUS to the CMX7164 If
116. i corte cete debet Men cte e tte rede 51 2015 CML Microsystems Plc Page 4 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 10 11 7 4 19 Auxiliary ADC Operation 52 7 4 20 Auxiliary DAC RAMDAC Operation 52 1 421 SP TMs PONE as EE 53 1 34 22 SPVG BUSAGG eek 54 7 5 Digital System Clock Generators nennen 56 7 5 1 Main Clock Operation 57 7 5 2 System Clock Operation 58 7 6 Signal Level Optimisation eessssssssesesseeeeenne enne nnne 58 7 6 4 Transmit Path Levels And Ramping eene 59 7 6 2 Receive Path Levels TTT 59 7 7 C BUS Register Gummam see eee eee eee eee eee eee eee 60 T164Fl 1 X Features mee 61 8 1 tal dese recette teet ee te tree ede 61 8 2 7164FI 1 x Radio Interface eerie ete ce eerie Del te 61 8 21 WO Transmit and UO Receive Interfaces sees eee eee eee eee 61 8 2 3 Two point Modulation Transmit with UO Receive Interface sss sese eee eee 63 8 3 7164Fl 1 x Formatted Data ernnnvonnnnnnvonnnnnnvnnnnnnnvnnnnnnnvnnnnnnnennnnnnneennnennennennrneennnennen 64 8 4 7164Fl 1 x Typical Transmit Performance sse 65 8 5 7164Fl 1 x Typical Receive Performance AA 70 8 5 1 Signal to Noise and Co channel Performance sse eee eee eee ee eee eee eee eee 70 Fal 19 Er dl TEE 74 9 1 ale E Modulation ica otc EE 74 9 2 7164El 2 x Radio Interface 5 ca coke cete ete ete ete tete ett 76 9 2 1 WO Transmit and UO Receive Interfaces sese
117. ice is in receive and searching for a frame Y Yes Gs sync as well as 4 note Carrier sense begins monitoring RSSI Rx Process Carrier sensing uud Yes IRQ FS Received v Rx Process No A Yes IRQ CS abort No Tx Process Yes 2015 CML Microsystems Plc Figure 19 Carrier Sense Page 39 D 7164 Fl 1 x Fl 2 x F1 4 x F1 6 x 22 CMX7164 Multi Mode Modem CMX7164 7 4 10 The Transmit Sequence The CMX7164 is capable of being configured to provide the following features 1 Selecting Tx mode results in transmission starting directly on entry to Tx mode or is delayed until GPIOA is used as an input trigger 2 Selecting carrier sense mode will result in behaviour as in point 1 followed by a carrier sense period where transmission is delayed reception continues until a carrier sense period is completed and no activity is sensed on the channel 3 Selecting Tx calibration will cause CMX998 cartesian loop dc calibration to be carried out prior to transmission as part of the programmable transmit sequence See section 7 4 11 CMX998 DC Offset Calibration for details 4 Once started transmission can be configured to be a simple modulation output or can include a programmable sequence of events including RAMDAC ramp up down and GPIO On Off Each of these operations can be select
118. ignal and using it to frequency modulate an UO baseband signal with a user programmable deviation In receive the 7164F1 1 x will accept an UO input signal and provide significant channel filtering digitally It will then frequency demodulate the resulting signal which is treated as a limiter discriminator output signal would be internally An overview of how the CMX7164 might use the CMX9923 for reception and the CMX998 for transmission is shown in Figure 44 The internal functions of the CMX7164 when operating in this mode are shown in Figure 3 Note that the transmit and receive interfaces are identical to those used for QAM modulation in Figure 83 facilitating multi mode modem operation However no linearisation is required when transmitting GMSK GFSK 3 CMX992 is an RF Quadrature IF Receiver CMX998 is a Cartesian Feedback Loop Transmitter which is designed primarily for non constant envelope modulations such as QAM although it will also support GMSK Conventional UO vector modulators such as the CMX993 would be more typical of solutions for GMSK modulation 2015 CML Microsystems Plc Page 61 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 HOST Y EE GPIOn ___ pr i i I I DE ao X Nes RENE LNAEnable ni CMX7164 I I J
119. igured as an automatic input This means that any attempted transmission will wait until GPIOA input is high if rising is selected or low if falling is selected See e 13 2 7 Program Block 5 Burst Tx Sequence e 13 1 13 GPIO Control 64 write e 13 1 33 GPIO Input 79 read 2015 CML Microsystems Plc Page 51 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 7 4 19 Auxiliary ADC Operation The inputs to the four Auxiliary ADCs can be independently routed from any of four dedicated AuxADC input pins or the two main inputs AuxADCs can be disabled to save power BIAS in the VBIAS Control B7 write register must be enabled for Auxiliary ADC operation Averaging can be applied to the ADC readings by selecting the relevant bits in the AuxADC1 4 Control 51 to 54 write registers This is a rolling average system such that a proportion of the current data will be added to the last value The proportion is determined by the value of the average counter in the AuxADC1 4 Control 51 to 54 write registers Setting the average counter to zero will disable the averager for an average value of 1 50 of the current value will be applied for a value of 2 25 3 12 5 continuing up to the maximum useful value of 11 0 0488 High and low thresholds may be independently applied to both ADC channels the comparison is applied after averaging if this is enabled and an IRQ generated when an input exceeds the high
120. ined state of BOOTEN1 and BOOTENe upon RESET determine the Function Image load interface Negative supply rail ground for the digital on chip circuits 3 3V positive supply rail for the digital on chip circuits This pin should be decoupled to DVSS by capacitors mounted close to the supply pins SPI Slave Select Out 2 Logic input used to reset the device active low General Purpose UO General Purpose UO Negative supply rail ground for the digital on chip circuits Do not connect Positive 3 3V supply rail for the analogue on chip circuit Levels and thresholds within the device are proportional to this voltage This pin should be decoupled to AVSS by capacitors mounted close to the device pins May also be connected to AVSS Do not connect Do not connect May also be connected to AVDD Differential outputs for channel P is positive N is negative Together these are referred to as the I Output When the 7164 FI 1 or Fl 2 is in two point modulation mode the Output is used as Mod 1 Differential outputs for Q channel P is positive N is negative Together these are referred to as the Q Output When the 7164 FI 1 or Fl 2 is in two point modulation mode the Q Output is used as Mod 2 Negative supply rail ground for the analogue on chip circuits DAC reference voltage connect to AVSS Do not connect Do not connect Do not connect 2015 CML Microsystems Plc Page 16 D 7164_Fl 1 x Fl 2 x Fl
121. ing register 61 I Paid RF Vector Spectrum Analyser Signal Vector Signal Analyser CMX7164 IO Generator Q Output E Inputs sf Buffer Amplifiers if required to drive RF signal generator modulation inputs Figure 61 Tx Spectrum and Modulation Measurement Configuration for UO Operation 2015 CML Microsystems Plc Page 84 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 13 82 dBm 449 99993387 MHz Modulation Spectrum EN 300 113 Adjacent Channel measurement for 25kHz channel ACP lt 72dB limit is 60dB Integration window 16kHz Peak deviation 43 symbol 2 85kHz mer Se WWAIAU NM hu Center 450 MHz 7 5 kHz Span 75 kHz CF 450 MHz Meas Signal CF 450 MHz Meas Signal Ref Lot SR 9 6 kHz Eye Ref Lvl SR 9 6 kHz Frequency 0 dBm Demod 4FSK 0 dBm Demod 4FSK 5k ES REQ n x A Ay 4 e g JAN EN V 3 n M K 4 KX QW i VE AD U e 1 0 SYMBOLS 49 9375 Eye Diagram Deviation Deviation for 3 symbol 2 85 kHz Figure 62 Tx Modulation Spectra 4 FSK 9 6ksymbols s 19 2kbps Q Modulation 2015 CML Microsystems Plc Page 85 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x
122. ised and Non Equalised 120 Figure 102 64 QAM Signal to Noise Performance Eoualteed 121 Figure 103 Performance of 16 QAM Equalised Signals with Temperature Variation 122 Figure 104 Performance of 64 QAM Equalised Signals with Temperature Variation 123 Figure 105 Performance of 16 QAM Equalised Signals with Temperature Variation and Constant Signal to Noise EE 123 Figure 106 Performance of 64 QAM Equalised Signals with Temperature Variation and Constant e E e EE EE 124 2015 CML Microsystems Plc Page 8 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Figure 107 Tx Spectrum and Modulation Measurement Configuration for UO Operation 125 Figure 108 Tx Modulation V 23 1200bps UO Modulation sss sese sese eee 126 Figure 109 Tx Modulation V 23 1200bps UO Modulation sss sss 127 Figure 110 Signal Level vs BER 128 Figure 111 C BUS Timing H 144 Figure 112 Mechanical Outline of 64 pin VQFN OQ sees eee 145 Figure 113 Mechanical Outline of 64 pin LQFP LO sss eee 145 Information in this datasheet should not be relied upon for final product design It is always recommended that you check for the latest product datasheet version from the CML website www cmlmicro com 2015 CML Microsystems Plc Page 9 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem 1 1 History CMX7164 Version Changes Date D M Y 22 Added
123. iver performance Typical BER assessment values are 5 1 or 0 1 whereas PER is most often assessed at 20 It will be observed from Figure 97 that a 4 QAM modem using no coding raw mode with 182 byte packets will achieve 2096 PER at just over 13dB SNR while 196 BER is achieved at 9 5dB SNR With formatted block type 6 see Table 8 approximately 7dB SNR gives 196 BER and 2096 PER It is recommended that designers assess the performance of the 7164Fl 4 x with the correct bit rate coding packet size etc for their particular application having in mind the regulatory requirements that may apply and paying careful attention to the test methods that will be used BER Raw Data 1 0E 02 al A S V IN l V BER Block Type 0 60 v BER Block Type 6 BER Block Type 7 L PER RAW Data 90 NM PER Block Type 0 x gt PER Block Type 6 1 0E 03 Y i x Block Type 7 40 ty xe i E 30 e HE S l B X 1 0E 04 Y 20 b R N U V 10 N U Wi k 1 0E 05 S e gen 0 2 4 6 8 10 12 14 Signal to Noise Ratio dB Figure 97 Comparison of BER and PER for 4 QAM Modulation 2015 CML Microsystems Plc Page 117 D 7164 Fl 1 x Fl 2 x Fl 4 x F1 6 x 22 CMX7164 Multi Mode Modem CMX7164
124. l circuitry 12 System Clocks Auxiliary circuits disabled but all other digital circuits including the Main Clock PLL enabled and Vpjas enabled 13 Using a 19 2MHz external clock input Xtal oscillator circuit powered down 14 A lower current is measured when outputting the smallest possible dc level from an AuxDAC a higher current is measured when outputting the largest possible dc value 15 Using a 19 2MHz external clock input 2015 CML Microsystems Plc Page 131 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 DC Parameters continued Notes Min Typ Max Unit XTAL CLK 20 Input Logic 1 70 DVpp Input Logic 0 30 DVpp Input Current Vin 2 DVpp 40 uA Input Current Vin DVss 40 UA C BUS Interface and Logic Inputs Input Logic 1 70 DVpp Input Logic 0 30 DV np Input Leakage Current Logic 1 or 0 11 1 0 1 0 uA Input Capacitance 7 5 pF C BUS Interface and Logic Outputs Output Logic 1 lop 2mA 90 DVpp Output Logic 0 lo 5mA 1096 DVpp Off State Leakage Current 11 1 0 1 0 UA VBlAS 21 Output Voltage Offset wrt AVpp 2 loi lt 1uA 2 AVpp Output Impedance 50 kQ Notes 20 Characteristics when driving the XTAL CLK pin with an external clock source 21 Applies when utilising Vgjas to provide a reference voltage to other parts of the system When using Vgjas as a reference VgiAs
125. lications For greater flexibility in Fl 4 x only different rate FEC modes are 2015 CML Microsystems Plc Page 2 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 provided Receive signal quality measurement is supported making a useful assessment of link conditions High performance digital IF filters may be reconfigured to support multiple channel spacings via host command This feature may eliminate the need to switch between multiple discrete IF filters An integrated analogue interface supports direct connection to zero IF I Q radio transceivers with few external components no external codecs are required Intelligent auxiliary ADC DAC and GPIO sub systems perform valuable functions and minimise host interaction and host I O resources Two synthesised system clock generators develop clock signals for off chip use The C BUS SPI master interface expands host C BUS SPI ports to control external devices Function Image The device utilises CML s proprietary FirmASIC component technology On chip sub systems are configured by a Function Image data file that is uploaded during device initialisation and defines the device s function and feature set The Function Image can be loaded automatically from a host uC over the C BUS serial interface or from an external memory device The device s functions and features can be enhanced by subsequent Function Image releases facilitating in the field upgrades
126. lly controlled by the GPIO pins D 7164 Fl 1 x Fl 2 x F1 4 x F1 6 x 22 CMX7164 Multi Mode Modem CMX7164 7 4 9 Carrier Sense Mode Carrier sense mode is a receive mode pending a transmission A carrier sense period averaging window length and threshold must be defined in the Program Blocks prior to entering this mode The signal strength is calculated internally as the UO signal contains amplitude information On entry to Carrier Sense mode reception will begin or continue if the previous mode was receive with an attempt to search for a frame sync During the defined carrier sense period average RSSI will be computed over a moving window Three outcomes are possible 1 If during the carrier sense period the average RSSI is above the carrier sense threshold then transmission will be aborted and search for frame sync will continue The device reverts to receive 2 There is a possibility that a valid frame sync will be detected during the carrier sense period If this is the case the transmission will be aborted immediately and the device will revert to receive 3 If the RSSI average remains below the carrier sense threshold then transmission will proceed In each of the three possible cases status bits will be used to indicate the result of the carrier sense period If the carrier sense mechanism is used in conjunction with GPIOA as a Tx trigger operation is as follows the device is put in receive searching for a frame sync
127. logue ground AVss No other electrical connection is permitted EXPOSED METAL PAD SUBSTRATE Notes IP Input PU PD internal pull up pull down resistor of approximately 75KQ OP Output BI Bidirectional TSOP 3 state Output PWR Power Connection NC No Connection should NOT be connected to any signal 2015 CML Microsystems Plc Page 18 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem 4 PCB Layout Guidelines and Power Supply Decoupling CMX7164 Sec be SSS SES SS AE EE Ses SEE SEES SS SS SSE SSS ESS see Se ser SS ESS See ESS ESS Bee ET Active low reset from supervisor IC or RC circuit DVpp C20 C21 C20 C21 C22 C23 C24 C25 GPIOB BOOTEN1 BOOTEN2 DVSS l DVDD 3 3V SSOUT2 RESETN GPIOC GPIOD DVSS AVDD 3 3V nic nic nic nic nic OUTPUT P 10uF 10nF 10nF 10uF 10nF 10nF 9 n o G J W K on CLK 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 OUTPUT N Q OUTPUT P SSOUTO MISO Q OUTPUT N C26 C27 DVss DVss C BUS s e e el 8 w E 4 lt lt SISI G DI 0 lt e 2 3 S S al sl sla 2 2 2 z 2 Z A S ol elal alal x x 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVSS DAC REF INPUT P I INPUT N ADC REF Q INPUT P Q INPUT N C26 22uF C27 10nF C28 10nF C31 100nF EL ee TI DVSS n c nic DVDD 3 3V AUX DACH AUX DACH AUX DACH AUX DAC1 AVSS
128. lti Mode Modem CMX7164 CMX7164 or a signal generator using preamble framesync and pseudo random data along with pulse shaping filters that are compatible with the Fl 2 x signal specification within this datasheet The Receiver Response Equaliser has two modes single mode produces better results when correcting for receivers with a simple baseband roll off for example in a direct conversion architecture Dual mode produces better results when compensating for a radio receiver which includes a crystal filter Program Block 11 Receiver Response Equaliser Fl 2 x and Fl 4 x provides equaliser mode selection allows adjustment of the gain used in the feedback path when training the equaliser and allows the training time to be altered The same Program Block allows the filter resulting from training to be read for storage and to be programmed back in to the CMX7164 later for use when receiving Results when using the Receiver Response Equaliser are shown in section 9 6 4 Receiver Response Equaliser Performance See e 13 1 18 Modem Mode and Control 6B write e 13 2 13 Program Block 11 Receiver Response Equaliser Fl 2 x and Fl 4 x 9 5 7164Fl 2 x Typical Transmit Performance Using the test system shown in Figure 61 the 7164F1 2 x internal PRBS generator was used to modulate the RF vector signal generator Some typical results are shown in the following figures The desired deviation was achieved by adjusting the CMX7164 peak deviation us
129. mmand FIFO Level 4B read 13 1 27 Receive FIFO Level 4F read 13 1 4 FIFO Control 50 write Note The Command FIFO and Command Buffer will automatically be flushed when a carrier sense attempt to transmit results in the CMX7164 reverting to receive mode This is to avoid accidentally processing transmit commands pre loaded by the host as receive commands This is the only situation in which the FIFOs or buffers will be flushed other than by direct host instruction 7 4 44 Data Buffering To expand the buffering capabilities of the CMX7164 two internal buffers are provided A Command buffer which buffers commands from the control FIFO which are yet to be processed An Rx data buffer which buffers received data yet to be loaded into the Rx data FIFO Transfer between the FIFOs and their respective buffers will occur during transmission reception and Idle mode Such transfer is not instantaneous so the FIFO fill levels should be used to indicate how much data the host may read or write at any time The Internal Buffer Fill Level 70 read register allows the buffer fill levels to be read their contents will be flushed when the respective FIFO is flushed 2015 CML Microsystems Plc Page 50 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 See e 13 1 4 FIFO Control 50 write e 13 1 28 Internal Buffer Fill Level 70 read Note The Command FIFO and Command Buffer will automatically be flushed when a carrie
130. modulation transmitter is shown in Figure 45 The internal functions of the CMX7164 when operating in this mode are shown in Figure 4 HOST Y Pee ee ee T GPlOn ___ uP D CN X i t LNA Enable e CMX7164 lu GPIO Tx Rx a Gi K E IINPUT LNA LO 2x ADC QBUS Q QINPUT CMX992 Local Oscillator A Thru C BUS Eege E II Ales i I i Reference IOUTPUT QOUTPUT e g VCTCXO MOD1 MOD2 7 VCO e Control Voltage Power Amplifier Input Figure 45 Outline Radio Design GMSK GFSK UO in two point mod out 2015 CML Microsystems Plc Page 63 D 7164 FI 1 xX Fl 2 X Fl 4 xX Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 8 3 7164Fl 1 x Formatted Data The 7164F1 1 x supports formatted data which provides the ability to channel code blocks of data using hamming coding and CRCs The frame structure as used in a formatted data system is illustrated in Figure 46 Typically it comprises a frame head consisting of a 16 bit sync word followed by a 16 symbol frame sync pattern control and data bytes and then one or more data blocks Frame Head Data Block MSB LSB MSB LSB 7 6 5 4 3 2 1 0 p GL EI PET LR Byte 0 Bit sync 1 Byte 0 T hl _ Byte 1 Bit sync 2 Byte 1 L L Byte 2 Frame sync1 B
131. must be buffered VgiAs must always be decoupled with a capacitor as shown in section 4 PCB Layout Guidelines and Power Supply Decoupling 2015 CML Microsystems Plc Page 132 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem Typ 30 200 CMX7164 Max Unit ns ns kQ pF kQ pF ms 250 MHz 20 MHz 13 5 ns 6 ns ms 140 kQ kQ 20 t080 AVpp 0 5 dB 1 0 dB AC Parameters Notes Min XTAL CLK Input High Pulse Width 30 15 Low Pulse Width 30 15 Input Impedance at 9 6MHz Powered up Resistance Capacitance Powered down Resistance Capacitance Xtal Start up Time from powersave SYSCLK1 2 Outputs SYSPLL Operating Frequency 38 SYSCLK1 2 Output Frequency Rise Time Fall Time Vgias Start up Time from powersave Differential I and Q Inputs Input Impedance Enabled 31 10 Input Impedance Muted or Powersaved Maximum Input Voltage Excursion 32 Programmable Input Gain Stage Gain at OdB 33 0 5 Cumulative Gain Error w r t attenuation at 0dB J 33 1 0 Notes 30 Timing for an external input to the XTAL CLOCK pin 31 With no external components connected 32 For each input pin and for AVpp 3 3V the maximum allowed signal swing is 8 3 x 0 8 3 3 x 0 2 2 0V 33 2015 CML Microsystems Plc Design Value Overall attenuation input to output has a design tolerance of OdB 1 0dB Page 133 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 C
132. n Figure 72 are typical of what may be achieved with 7164Fl 2 x and a typical UO radio receiver with no adjacent channel selectivity in the radio circuits In a more normal RF architecture some adjacent channel selectivity will be provided making system results better than the measured values for the 7164Fl 2 x alone Furthermore the results observed are not necessarily the maximum that the CMX7164 can achieve but are limited by the practical dynamic range of the CMX7164 combined with the system gain and noise figure of the receiver used in these tests 9 6 2 8 FSK and 16 FSK 9 6 2 1 Signal to Noise It should be noted that error rate performance depends on the modulation type symbol rate and deviation In the following graphs the modulation is 4 FSK 8 FSK and 16 FSK and the data rate is 4 8ksymbols s which is typical of the rate that may be achieved in a 12 5kHz RF channel The signal to noise ratio is calculated as SNR Mean signal power 174 NF 10 logi RXBW 2015 CML Microsystems Plc Page 95 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Where NF receiver noise figure in dB RxBW receiver noise bandwidth Mean signal power is in dBm SNR Signal to Noise Ratio in dB 1 00E 01 4 FSK 1 00E 02 S X PATREON 16 FSK 5S N l S 1 00E 03 Ne N E N H S N i 1 00E 04 X m y N N E 1 00E 05 5 A N 1 00E 06 1 00E 07
133. n by the CMX7164 UO dc offset effects are a radio issue which is beyond the control of the CMX7164 however the CMX7164 does provide dc offset calculation and removal This is described in Section 15 Application Notes 11 3 7164FI 6 x Formatted Data The 7164F1 6 x supports formatted data In this mode the CMX7164 will automatically add start stop and optionally parity bits to bytes in Tx and also check and remove start stop and parity bits in Rx Formatted data can be transferred in blocks of 1 to 8 bytes When receiving formatted data the CMX7164 will indicate errors in received data 11 4 7164F1 6 x Typical Transmit Performance Using the test system shown in Figure 107 the 7164F1 6 x internal PRBS generator is used to modulate the RF vector signal generator Some typical results are shown in the following figures The desired deviation is achieved by adjusting the CMX7164 peak deviation via register 61 Output RF Vector Spectrum Analyser Signal Vector Signal Analyser CMX7164 FI 6 VQ Generator Q Output Inputs Cessna PO Buffer Amplifiers if required to drive RF signal generator modulation inputs Figure 107 Tx Spectrum and Modulation Measurement Configuration for UO Operation 2015 CML Microsystems Plc Page 125 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Modulation Spectrum Peak deviation 1 5kHz Ref Level 0 00 dBm RBW 100 Hz
134. n unwanted gain changes The CMX7164 is able to use the lO dc offset information to correct for this effect AGC thresholds and parameters may be changed during reception for ease of setup and are controlled using the Signal Control 61 write register All times are measured in units of 6 5 of a symbol period All levels or thresholds are compared to the magnitude of signed 16 bit samples with max range therefore being 32767 to 32768 See 13 2 8 Program Block 6 SPI Thru Port Configuration 13 2 9 Program Block 7 AGC Configuration 13 1 14 AGC Control 65 write 13 1 10 Signal Control 61 write 15 3 1 Effect of AGC on DC Offsets 7 5 Digital System Clock Generators The CMX7164 includes a two pin Xtal Oscillator circuit This can either be configured as an oscillator as shown in section 4 or the XTAL CLK input can be driven by an externally generated clock The crystal Xtal source frequency is typically 9 6MHz and if an external oscillator is used the input frequency is typically 9 6 or 19 2 MHz For both cases reference frequencies in the range specified in 12 1 2 Operating Limits may be used 2015 CML Microsystems Plc Page 56 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 7 5 1 Main Clock Operation A digital PLL is used to create the main clock for the internal sections of the CMX7164 The configuration of the main clock and the internal clocks derived from it is controlled using Program Blo
135. nal to Noise and Co channel Performance The response of crystal filters varies with temperature This will affect the ability of an equaliser which is trained at room temperature to compensate effectively for crystal filter distortions at a different temperature Other types of filter may be more stable with temperature for example the baseband filters in the CMX99413 Measurements showing the degradation in signal to noise performance over temperature when the equaliser was trained at room temperature are shown in plots Figure 103 to Figure 106 13 Direct Conversion Receiver IC 2015 CML Microsystems Plc Page 121 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 1 00E 01 CMX992 No Equaliser CMX992 With Equaliser CMX994 No Equaliser 1 00E 02 CMX994 With Equaliser 1 00E 03 BER 1 00E 04 1 00E 05 1 00E 06 Temperature deg C Figure 103 Performance of 16 QAM Equalised Signals with Temperature Variation Tests were carried out using 16 QAM modulation with a signal level of 103dBm Figure 103 and a signal level of 95dBm for 64 QAM Figure 104 using the EV9910B 4 CMX991 with GMCF 45 45G15B1 crystal filter and the EV9942 CMX994 with temperature compensated baseband filter BER performance was measured with and without equalisation being applied then the temperature was varied and the equalised and non equalised bit e
136. nary data transferred between the modem and its uC being that enclosed by the thick dashed rectangles near the top of Figure 58 When receiving header blocks and last blocks the CMX7164 will indicate CRC success or failure and will provide the data regardless In Figure 58 the size of data block illustrated is always 12 bytes when user bytes and CRC bytes are counted together The CMX7164 adds further flexibility by supporting other block sizes depending on the modulation type in use The reference to tri bits and symbol count for the 12 byte block in Figure 58 is specific to 4 FSK coded data The resulting data content for each block size and modulation type is shown below Table 4 Native Formatted Block Types Sizes and Rates for 4 FSK Fl 2 x User CRO bytes for a Total bytes Block Block Size Coding Rate Header Inter Last excluding Size Bytes Block Block Block frame symbol sync 0 6 bytes 0 75 Excluding pad tri bit 4 2 6 2 4 8 bytes 4 bits 1 9 bytes 0 75 Excluding pad tri bit 7 2 9 5 4 12 bytes 4 bits 2 12 bytes 0 75 Excluding pad tri bit 10 2 12 8 4 16 bytes 4 bits Table 5 Native Formatted Block Types Sizes and Rates for 8 FSK Fl 2 x User CRO bytes for a Total bytes Block Block Size Coding Rate Header Inter Last excluding frame symbol Size Bytes Block Block Block sync 0 12 bytes 2 3 high rate 10 2 12 8 4 18 bytes 6 bits high
137. ndingly small Using the above figures and calculating time t 9 time constants x R x C the result would be 9 30kQ 3 5pF 0 95us 2015 CML Microsystems Plc Page 135 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 12 1 4 7164Fl 1 x Parametric Performance For the following conditions unless otherwise specified External components as recommended in section 5 Maximum load on digital outputs 30pF Clock source 19 2MHz 0 002 20ppm clock input Tam 40 to 85 AVpp DVpp 3 0V to 3 6V Reference signal level 308mV rms at 1kHz with AVpp 3 3V Signal levels track with supply voltage so scale accordingly Signal to Noise Ratio SNR in bit rate bandwidth Input stage gain OdB Output stage attenuation OdB All figures quoted in this section apply to the device when loaded with Fl 1 x only The use of other valid Function Images can modify the parametric performance of the device DC Parameters Notes Min Typ Max Unit Supply Current Rx Mode Dipp 8ksymbols s search for FS 61 10 3 mA Dipp 9 6ksymbols s search for FS 61 10 8 mA Dipp 8ksymbols s FS found 61 9 2 mA Dipp 9 6ksymbols s FS found 61 9 4 mA Alpp AVpp 3 3V 8 7 mA Tx Mode 60 Dinn 8ksymbols s 4 9 mA Diop 9 6ksymbols s 5 0 mA Alpp AVpp 3 3V 7 7 mA Notes 60 Transmitting in UO mode continuous GMSK GFSK PRBS all GPIOs and RAMDAC set to m
138. nel 8ksymbols s With and Without Coding 72 Modem Co channel Rejection with FM Interferer as EN 300 113 73 PRBS Waveform Two point Modulation seen 76 Outline Radio Design UO in out for 2 or 4 FSK see eee 77 Outline Radio Design 2 or 4 FSK UO in two point mod ou 78 Native Formatted Data Over Air Signal Format snrnnnnrnnnnrrnnnnvnnnnnrnnerrnnnnrrnnnnrnnrnnnnrnnn 79 Suggested Frame Structures seer eee eee ee eee eee eee 80 RD LAP Over Air Signal Format 82 Tx Spectrum and Modulation Measurement Configuration for HO Operation 84 Tx Modulation Spectra 4 FSK 9 6ksymbols s 19 2kbps UO Modulation 85 2015 CML Microsystems Plc Page 7 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Figure 63 Tx Modulation Spectra 2 FSK 9 6k symbols s 9 6kbps HO Modulation 86 Figure 64 Tx Modulation Spectra 8 FSK 9 6k symbols s 28 8kbps Q Modulation 87 Figure 65 Tx Modulation Spectra 16 FSK 9 6k symbols s 38 4kbps Q Modulation 88 Figure 66 Tx Spectrum and Modulation Measurement Configuration for Two point Modulation 89 Figure 67 Tx Modulation Spectra 4 FSK 19 2kbps Two point Modulation 90 Figure 68 Modem Sensitivity Performance Root Raised Cosine Pulse Shaping 92 Figure 69 12 5kHz Channel Sensitivity With and Wi
139. nnel coding in the 12 5kHz channel case 8ksymbols s with Gaussian pulse shaping filter with BT 0 3 1 0E 02 8kbps Bt 0 3 Raw 8kbps Bt 0 3 code 2 1 0E 03 1 0E 04 BER 1 0E 05 1 0E 06 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 16 0 17 0 Signal to Noise Ratio dB Figure 53 Sensitivity 12 5kHz Channel 8ksymbols s With and Without Coding 2015 CML Microsystems Plc Page 72 D 7164 Fl 1 x Fl 2 x F1 4 x F1 6 x 22 CMX7164 Multi Mode Modem CMX7164 The co channel rejection ratio Figure 54 is measured with an interferer modulated with 400Hz FM and having a deviation of 1 5kHz which is 1296 of the nominal 12 5kHz channel bandwidth This particular interfering signal is used as it is specified in ETSI standard EN 300 113 for co channel tests 1 00E 01 1 00E 02 BER 1 00E 03 1 00E 04 3 5 4 4 5 5 Co Channel Rejection dB Figure 54 Modem Co channel Rejection with FM Interferer as EN 300 113 2015 CML Microsystems Plc Page 73 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 9 7164Fl 2 x Features The 7164Fl 2 x uses a 2 4 8 or 16 FSK modulation scheme with a configurable over air symbol rate up to 10ksymbols s which corresponds to a maximum bit rate of 40kbps when using 16 FSK In each case the modulating signal is root raised cosine filtered with a filter alpha of 0 2 Raw data can be transferred and in addi
140. ntrol Byte 8 4B R Modem Command FiFOLevel 8 4C R Receive FiFODataByte 1 8 4D R Receive FIFOWord amp 16 4E R Receive FIFO Control Byte 1 8 4F R Receive FIFO Level 8 5910 5C W AuxDAC1 4 Control 16 7110 74 R AuxADCi4Read 146 5D WN Output Control Le 5E W QOutputControl 16 5F w flinputControl 0 0 46 60 Ww QinputControl 416 6 CW Signal Control 5h h3hPM e 65 WL AGC Control 3 16 6 w RxtTacding 16 69 w RegDoneSelet 16 L 7 R lntemalBufferfFilleve E 75 R ee 0 76 r aot e Hi R AGCQainandRSS Le S7A R RxErorMagnitude 416 7B R Frequency Error 78 R SPiThuPorRead 1 16 79 R GRIOInput HT 68 Ww ModemModeandControl 16 370 R Programming Register Read 16 SE R IRQStaus Er R ens 80 W VQ Input Configuration 16 B1 W flinputCoarseGan 416 All other C BUS addresses are reserved and must not be accessed 2015 CML Microsystems Plc Page 60 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 8 7164Fl 1 x Features The 7164Fl 1 x uses a GMSK GFSK modulation scheme with a configurable over air bit rate up to 20kb
141. o Noise Performance Equalised and Non Equalised 1 00E 01 Equalised 1 00E 02 Not Equalised 1 00E 03 BER 1 00E 04 1 00E 05 1 00E 06 16 0 18 0 20 0 22 0 24 0 26 0 28 0 30 0 32 0 34 0 36 0 Signal To Noise Ratio dB Figure 101 16 QAM Signal to Noise Performance Equalised and Non Equalised 2015 CML Microsystems Plc Page 120 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 1 00E 00 Equalised 1 00E 01 1 00E 02 BER 1 00E 03 1 00E 04 1 00E 05 20 0 21 0 220 23 0 240 250 26 0 27 0 28 0 29 0 30 0 Signal To Noise Ratio dB Figure 102 64 QAM Signal to Noise Performance Equalised Figure 100 Figure 101 and Figure 102 show that equaliser training improves the received signal performance in all cases 4 QAM 16 QAM and 64 QAM We can see that without equalisation 16 QAM signals have a residual bit error rate even with a high signal level as the non equalised curve flattens off 64 QAM is unusable without equalisation producing a residual bit error rate of greater than 1e 2 regardless of signal to noise ratio The 4 QAM curves show that 4 QAM is less affected by the receiver response therefore the improvement made by equalisation is less Once equalisation is present the measured figures compare well to the results with no crystal filter in the receive path in section 10 6 1 Sig
142. o the supply pins 46 NC NC Do not connect 47 NC NC May also be connected to DVSS 48 DVSS PWR Negative supply rail ground for the digital on chip circuits 49 XTALN OP Output of the on chip Xtal oscillator inverter 50 XTAL CLOCK IP ee e ern MIL from the Xtal circuit or 51 SYSCLK1 OP Synthesised digital clock output 1 2015 CML Microsystems Plc Page 17 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Description SYSCLK2 Synthesised digital clock output 2 SCLK C BUS serial clock input from the uC 3 state C BUS serial data output to the uC This output is high impedance when not sending data to the uC RDATA CDATA C BUS serial data input from the uC CSN C BUS chip select input from the UC wire Orable output for connection to the Interrupt Request input of the uC This output is pulled down to DVss when active and is high impedance when inactive An external pull up resistor is required IRQN Internally generated digital core voltage of approximately 58 DVCORE 1 8V This pin should be decoupled to DVss by capacitors mounted close to the device pins 59 MOSI SPI Master Out Slave In 60 SSOUT1 SPI Slave Select Out 1 61 MISO SPI Master In Slave Out 62 SSOUTO SPI Slave Select Out 0 63 CLK SPI Serial Clock 64 GPIOA General Purpose UO On this device the central metal pad which is exposed on the Q1 package only may be electrically unconnected or alternatively may be connected to Ana
143. ode Data RF Rx Demod Channel Filters RY RO X Low Pass Start Stop amp g Hos Filter Formatted Parity Checking 2 H Data Formatted Data Construct Start Stop Frame Add and Panty V 23 Tone P bl Insertion RFTx Q Mod Generation Da Framesync Raw Mode Data and Tails Figure 5 FI 6 x Block Diagram UO Tx and Rx Auto Frame Sync Detect Link Quality Detect 7 gt va Raw Mode Data il gt RFR Demod Channel Filters RY LK Buffer p RE s Low Pass Start Stop amp g Host Filter Formatted Parity Checking 2 uc Data 2 Formatted Data Construct EE FIFO Frame Add n V 23 Tone 4 RFTx KW Ganerien Buffer Preamble Insertion o Framesync Raw Mode Data and Tails SSS Figure 6 FI 6 x Block Diagram Two point Tx with I Q Rx 2015 CML Microsystems Plc Page 15 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem 3 Signal List Oo ON OD a O 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name Type GPIOB Bl BOOTEN 1 IP PU BOOTEN2 IP PU DVSS PWR DVDD 3V3 PWR SSOUT2 OP RESETN IP GPIOC BI GPIOD BI DVSS PWR NC NC AVDD PWR NC NC NC NC NC NC NC NC IOUTPUTP OP IOUTPUTN OP QOUTPUTP OP QOUTPUTN OP AVSS PWR DACREF NC NC NC NC NC NC CMX7164 Description General Purpose UO The combined state of BOOTEN1 and BOOTEN2 upon RESET determine the Function Image load interface The comb
144. of the transmit sequence Figure 21 CMX998 DC Calibration Interfaces During calibration the CMX998 is controlled by the CMX7164 using the SPI Thru Port The CMX998 is assumed to be device 1 to select one of the following to be output to the CMX998 DCMEAS output Reference The CMX998 dc reference for the in phase signal path Q Reference The CMX998 dc reference for the quadrature signal path Error Low high gain The CMX998 measure of the dc produced by the input signal on the in phase signal path Q Error Low high gain The CMX998 measure of the dc produced by the input signal on the quadrature signal path During calibration the CMX7164 uses AuxADC2 to measure Reference and Reference Q It then puts outputs a dc level on the I Output Q Output signals AuxADC2 is used to measure the DCMEAS I and Q The low and high gain states are created by adjusting the gain of the error amplifiers in the CMX998 see the CMX998 datasheet for more information 2015 CML Microsystems Plc Page 41 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Error and I Output Q Output are adjusted to make the DCMEAS I and Q errors equal to the DCMEAS I Reference and Q Reference measurements There are three complications to this process 1 The total gain of the feedback loop I Output to CMX998 DCMEAS Error signal to AuxADC is unknown so the adjustment to the I Output signal may not be calculated completely accurately
145. on The modulation bandwidth is dependent on the peak frequency deviation of the modulating signal The user can set the deviation in order to meet the requirements of a particular application 11 2 7164FI 6 x Radio Interface The transmit radio interface of 7164F1 6 x can be set to two point modulation or I Q When the 7164F1 6 x is in two point modulation mode the Output is used as Mod 1 and the Q Output is used as Mod 2 The 7164F1 6 x receive input signal must come from a zero IF l Q radio receiver 11 2 1 1 Q Transmit and UO Receive Interfaces The 7164F1 6 x can produce a zero IF modulated UO Tx output signal of user configured deviation In receive the 7164FI 6 x accepts a zero IF UO input signal and provides significant digital channel filtering It frequency demodulates the resulting signal which is then treated internally in the same manner as a limiter discriminator output signal Note that the transmit and receive interfaces are identical to those used by other CMX7164 FIs Use of UO receive mode introduces the issue of UO dc offsets These are dc offsets caused by the radio receiver resulting in the signal into the CMX7164 having a dc offset other than that present on the VBIAS pin The offsets need to be removed prior to demodulation Offsets typically remain constant for a particular radio frequency selected but will vary if that frequency is changed Gain within the radio receiver may also affect the dc offset see
146. or low threshold or on every sample as required The thresholds are programmed via the AuxADC1 4 Threshold 55 to 58 write register Auxiliary ADC data is read back in the AuxADC1 4 Read 71 to 74 read registers and includes the threshold status as well as the actual conversion data subject to averaging if enabled The AuxADC sample rate is selected using Program Block 1 Clock Control See 13 1 5 AuxADC1 4 Control 51 to 54 write 13 1 6 AuxADC1 4 Threshold 55 to 58 write 13 1 29 AuxADC1 4 Read 71 to 74 read 13 2 3 Program Block 1 Clock Control 13 1 24 VBIAS Control B7 write 7 4 20 Auxiliary DAC RAMDAC Operation The four auxiliary DACs are programmed via the AuxDAC1 4 Control 59 to 5C write registers AuxDAC1 may also be programmed to operate as a RAMDAC which will autonomously output a pre programmed profile at a programmed rate The RAMDAC may be configured as automatic or manual using Program Block 5 Burst Tx Sequence The AuxDAC1 4 Control 59 to 5C write register with b12 set controls the RAMDAC mode of operation when configured as a manually triggered RAMDAC The RAMDAC ramp rate is controlled by the Internal system clock rate which changes between active CS Tx Rx modes and Idle mode Therefore it is inadvisable to return to Idle mode prior to RAMDAC ramp completion The default profile is a Raised Cosine see Table 21 in the user manual but this may be over written with a user defined pro
147. otes Min Typ Max Unit Supply Current Rx Mode Dipp 9 6ksymbols s search for FS 80 15 7 to 21 0 mA Dipp 18ksymbols s search for FS 80 24 1 to 34 1 mA Dipp 9 6ksymbols s FS found 11 0 mA Dipp 18ksymbols s FS found 15 4 mA Alpp AVpp 3 3V 7 7 mA Tx Mode 81 Dipp 9 6ksymbols s 7 5 mA Dipp 18ksymbols s 11 1 mA Alpp AVpp 3 3V 8 0 mA Notes 80 A lower current is measured when searching for Framesync1 a higher current is measured when doing automatic modulation detection 81 Transmitting continuous 16 QAM PRBS all GPIOs and RAMDAC set to manual 2015 CML Microsystems Plc Page 140 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 AC Parameters Notes Min Typ Max Unit Modem Symbol Rate 2 000 20000 syms Modulation QAM Filter RRC Alpha 96 0 2 or 0 35 Tx Bit rate Accuracy 90 ppm Tx Output Level I Output Q Output 91 Fl 4 x I Q modulation mode 2 6 Vp p Tx Adjacent Channel Power Output Q Output 92 dB PRBS Rx Frequency Error Tolerated 95 1 0 kHz Rx Co channel Rejection 93 dB Rx Adjacent Channel Rejection 93 dB Notes 90 Determined by the accuracy of the Xtal oscillator provided 91 Transmitting continuous PRBS data This is a differential voltage I Output IOUTPUTP IOUTPUTN and Q Output IOUTPUTP IOUTPUTN 92 See section 10 5 7164F1 4 x Typical Transmit Performance 93 See section 10 6 7164F1 4
148. p transmitter IC e Four auxiliary DACs one with built in programmable RAMDAC The frame sync detection algorithm of the CMX7164 is capable of detecting a frame sync without having bit synchronisation so preamble is not required for obtaining bit sync Some preamble is still needed to ensure that the beginning of the frame sync is transmitted and received without distortion Preamble may also be used to provide a known signal on which to acquire UO dc offset corrections 2015 CML Microsystems Plc Page 22 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Interface e Optimised C BUS 4 wire high speed synchronous serial command data bus interface to host for control and data transfer including streaming C BUS for efficient data transfer Open drain IRQ to host Four GPIO pins Tx trigger input Provided by GPIOA Serial memory or C BUS host boot mode Both transmit and receive data can be raw or coded data blocks Fl 4 x provides a variety of coding rates for flexibility and very large block sizes having the potential to improve performance in fading conditions considerably Fl 2 x provides coding compatible with CMX7143FI1 2 x Fl 1 x provides coding compatible with CMX7143FI 1 x 6 2 Signal Interfaces UO Tx and Rx Fl 4 x produces QAM modulation The transmitted signal is provided as an UO baseband for mixing up onto an RF carrier with amplification For reception an I Q baseband signal should be interfaced
149. phase error 46 Normalised Constellation noisy received signal esee 46 Channel Filtered UO Signals sse eee eee 46 Channel Filtered UO Signals with UO DC Offset Estimate eee eee eee 46 Received Signal First FM Demodulator 7164F1 6 x sse 47 Received Signal Second FM Demodulator 7164F1 6 X see 48 Command and Rx Data FIFOS sse eee eee eee 49 AGC using SPI R u asla OTT 54 AGC using SPI Thru Port and external NA 55 AGC Behaviour During Burst Reception c cccceceeeeceeeeeeeceeeeeeaeeeeeeeseeeeseaeeesaaeeennees 56 Main Clock Generation sessi eene enne enne nennen nnns 57 Digital System Clock Generation SCHEMES sse 58 Outline Radio Design UO in out for GMSK GFSK sse 62 Outline Radio Design GMSK GFSK I Q in two point mod out 63 Formatted Data Over Air Signal Format ss sees eee eee eee eee eee 64 Tx Spectrum and Modulation Measurement Configuration for UO Operation 65 Tx Modulation Spectra GMSK 9 6kbps BT 0 5 HO Modulation 66 Tx Modulation Spectra GMSK 8kbps BT 0 3 I Q Modulation 67 Tx Spectrum and Modulation Measurement Configuration for Two point Modulation 68 Tx Modulation Spectra GMSK 8kbps BT 0 3 Two point Modulation 69 Modem Sensitivity Performance sse eee eee ee eee ee 71 Sensitivity 12 5kHz Chan
150. pplication family Specific functions of a FirmASIC device are determined by uploading its Function Image during device initialization New Function Images may be later provided to supplement and enhance device functions expanding or modifying end product features without the need for expensive and time consuming design changes FirmASIC devices provide significant time to market and commercial benefits over Custom ASIC Structured ASIC FPGA and DSP solutions They may also be exclusively customised where security or intellectual property issues prevent the use of Application Specific Standard Products ASSP s Handling precautions This product includes input protection however precautions should be taken to prevent device damage from electro static discharge CML does not assume any responsibility for the use of any circuitry described No IPR or circuit patent licences are implied CML reserves the right at any time without notice to change the said circuitry and this product specification CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification Specific testing of all circuit parameters is not necessarily performed CML Microcircuits UK Ltd COMMUNICATION SEMICONDUCTORS CML Microcircuits eu USA Inc COMMUNICATION SEMICONDUCTORS CML Microcircuits en Singapore Pte Ltd COMMUNICATION SEMICONDUCTORS Tel 44 0 1621 875500
151. ps The modulating signal is Gaussian filtered with a filter BT selectable from 0 5 0 3 0 27 or 0 25 Raw data can be transferred in addition to formatted data blocks Formatted data blocks may be of variable length up to 18 bytes and support 16 bit CRC for error detection plus hamming coding for error correction The modulation scheme and coding are designed to produce a signal that is over air compatible with the CML FX MX909B and CMX7143 7143F1 1 x modems 8 1 7164Fl 1 x Modulation The GMSK GFSK modulation running at 8kbps with BT of 0 3 or less can be accommodated within a 12 5kHz channel bandwidth A rate of 9 6kbps with BT 0 5 is typical in 25kHz bandwidth channels while meeting the transmit and receive requirements of international standards such as EN 300 113 Channel bandwidth is dependent on the deviation that the modulating signal causes the carrier to deviate by as well as the data rate and the BT As a result the user can choose to configure the device to suitable settings for a particular application 8 2 7164Fl 1 x Radio Interface The transmit radio interface of the 7164Fl 1 x can be set to two point modulation or UO When the 7164FI 1 x is in two point modulation mode the Output is used as Mod 1 and the Q Output is used as Mod 2 The receive signal must come from an UO radio receiver 8 24 IQ Transmit and I Q Receive Interfaces The 7164FI 1 x can produce an WO modulated signal taking a baseband modulating s
152. r 174 NF 10 log RXBW Where NF receiver noise figure in dB RxBW receiver noise bandwidth Mean signal power is in dBm SNR Signal to Noise Ratio in dB The graph in Figure 52 compares the raw sensitivity performance of data transfer using a 12 5kHz and a 25kHz channel Pulse shaping was achieved using a Gaussian filter with BT 0 5 in the 25kHz channel and BT 0 3 in the 12 5kHz channel The modulation parameters used in all of the figures that follow in this section are summarised below Channel Baud Rate Pulse Shaping Deviation Measured Receiver Noise Used in Bandwidth Symbols s Filter KHz Tx ACP Bandwidth kHz Figures KHz dBc 25 9600 Gaussian 2 4 81 16 Figure 52 BT 0 5 12 5 8000 Gaussian 2 0 73 8 Figure 52 BT 0 3 Figure 53 Figure 54 2015 CML Microsystems Plc Page 70 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 1 0E 02 8kbps Bt 0 3 9 6kbps Bt 0 5 1 0E 03 uj 1 0E 04 B 1 0E 05 1 0E 06 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 16 0 Signal to Noise Ratio dB Figure 52 Modem Sensitivity Performance 2015 CML Microsystems Plc Page 71 D 7164_FI 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Data transfer may have channel coding applied to it when GMSK GFSK modulation is selected The graph in Figure 53 shows the improvement due to cha
153. r PA Gain Control RAMDAC IN C EE MEL ie ELE Aux DACO 2x DAC Directional Power Coupler Amplifier I Output 4 Q Output OG Ge 90 Local Oscillator Q CMX998 Figure 83 Outline Radio Design UO in out for QAM Use of UO receive mode brings with it the problem of UO dc offsets There are dc offsets caused by the radio receiver resulting in the signal into the CMX7164 having a dc offset other than Voss The offset needs to be removed prior to demodulation Offsets typically remain constant for a particular radio frequency selected but will vary if that frequency is changed Gain within the radio receiver may also affect the dc offset seen by the CMX7164 UO dc offset effects are a radio issue which is beyond the control of the CMX7164 However the CMX7164 does provide dc offset calculation and removal These are described in detail in the application note section 15 3 DC Offsets in UO Receivers 10 2 1 Control interfaces As can be seen in Figure 83 the CMX7164 provides control interfaces to assist with controlling the radio transmitter and receiver These include e ASPI Thru Port port which may be used to control radio ICs with C BUS SPI interfaces s ARAMDAC which can be used to control PA ramp up and ramp down e Four GPIO pins which may be used for Tx Rx switching LNA off an
154. r Sense selecting the frame sync to use Frame Sync 1 or 2 and selecting formatted or raw data Such a selection is required at the beginning of transmission or reception of a burst In transmit or following a carrier sense period where no signal is detected on channel the CMX7164 will begin by switching GPIO signals as configured by the transmit sequence The RAMDAC can also be configured to ramp up at this point Transmission then begins with preamble and the selected frame sync The main payload of user data comes next ending with selectable tail bits The burst ends with the transmission sequence ramping the RAMDAC down and or switching GPIO signals In receive or following a carrier sense period where signal is detected on channel the CMX7164 will begin by searching for either or both of the configured frame sync patterns On detection of a frame sync reception and delivery of Rx data will begin Reception continues until the CMX7164 is switched into a different mode determined by the host During the burst data must be transferred into or out of the CMX7164 Transfers use the Command FIFO to transfer data and commands about data type into the CMX7164 and the Rx FIFO to transfer data out of the CMX7164 The IRQ Status register is used to indicate that the data has been dealt with The CMX7164 can be configured to interrupt the host when a specified data block has been transferred or on FIFO fill level The CMX7164 offers internal buff
155. r following a C BUS General Reset the CMX7164 will automatically load the data from the serial memory without intervention from the host controller BOOTEN2 0 BOOTEN1 1 K Power up or write General Reset to CMX7164 R Poll Status 7E until Reg Done b14 1 PRG Flag is unmasked in Reg Done Select register 69 by default and indicates when the FI is loaded BOOTEN1 and BOOTEN2 may be changed from this Y Read and discard 3 device check words from point onyif required the RxFIFO Word 4D I Von Read and verify the 32 bit checksum word of each block loaded found in the RxFIFO i Word 4D e Jumper for rogrammin Y BOOTEN1 Prog g Read the Product ID code and the FI version i Gen al memory code from the RxFIFO Word 4D i if 5 d i nr Ir BOOTEN2 if required 2 CMX7164 is now ready for use Figure 16 Fl Loading from Serial Memory The CMX7164 has been designed to function with the AT25F512 serial flash device however other manufacturers parts may also be suitable The time taken to load the FI should be less than 500ms even when loading the largest possible Function Image 2015 CML Microsystems Plc Page 30 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 7 4 Device Control Once the Function Image is loaded the CMX7164 can be set into one of four main modes using the Modem Mode and Cont
156. r other stages prior to a SPI C BUS controlled device The commands may be produced by the AGC function or the CMX7164 can be commanded to output them manually if required Commands are programmed using Program Block 7 AGC Configuration AGC is controlled by sensing over range in the received signal in which case the gain is backed off While searching for a frame sync the gain will also be backed off when the signal is considered large this ensures that after frame sync is detected there is headroom for the amplitude to increase a little If the signal is sensed to be small for a period of time the gain can also be increased The signal magnitude low or high threshold considered to require a gain change the time for which it should remain low before making a change and the time to allow a gain adjustment to take effect are all programmable The overall system is shown in Figure 39 HOST uP Y aie OG CMX7164 RF Receiver IC e g CMX991 or CMX992 K Es amp Bey L AP L CA A p Clip Level X SI f Sense c p AJ Q Input I Input T R Local Oscillator Baseband Gain Local Oscillator IF Quadrature Control Register AGC Gain Step Select C BUS Control SPI Thru Port amp le Registers UNA Control Output 1 C BUS control of external device
157. r sense attempt to transmit results in the CMX7164 reverting to receive mode This is to avoid accidentally processing transmit commands pre loaded by the host as receive commands This is the only situation in which the FIFOs or buffers will be flushed other than by direct host instruction 7 4 15 Raw Data Transfer When transferring raw data the FIFO Control byte indicates the amount of data that will be transferred in a block before the CMX7164 interrupts the host Byte and bit wise transfers are possible providing the facility to transmit or receive a burst of arbitrary length not just a whole number of bytes It is suggested that data is transferred in the maximum size blocks possible until the end of a burst where the remaining bits or bytes can be transferred in a single transaction of the required size When using byte wise or bit wise transfers the most significant bit of the data byte is transmitted or received first When using bit wise transfers with a bit count of less than 8 the most significant bits are used In all cases the bits are combined into symbols according to the selected modulation type It is also possible to ignore the concept of blocks of data whilst in raw mode Instead a transmission can just be treated as a series of bytes to transmit and FIFO levels level IRQs used to manage the data flow Likewise in receive the host can request continual data reception and the resulting bytes will be placed in the Rx Data FIFO
158. rate 1 2 low rate 24 bytes 6 bits low rate 1 24 bytes 2 3 high rate 22 2 24 20 4 36 bytes 6 bits high rate 1 2 low rate 48 bytes 6 bits low rate 2 36 bytes 2 3 high rate 34 2 36 32 4 54 bytes 6 bits high rate 1 2 low rate 64 bytes 6 bits low rate 3 48 bytes 2 3 high rate 46 2 48 44 4 72 bytes 6 bits high rate 1 2 low rate 96 bytes 6 bits low rate 2015 CML Microsystems Plc Page 80 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Table 6 Native Formatted Block Types Sizes and Rates for 16 FSK FI 2 x User CRO bytes for a Total bytes Block Block Size Coding Rate Header Inter Last excluding frame symbol Size Bytes Block Block Block sync 0 12 bytes 3 4 high rate 10 2 12 8 4 17 bytes high rate 9 16 low rate 22 bytes low rate 1 24 bytes 3 4 high rate 22 2 24 20 4 33 bytes high rate 9 16 low rate 43 bytes low rate 2 36 bytes 3 4 high rate 34 2 36 32 4 49 bytes high rate 9 16 low rate 64 bytes low rate 3 48 bytes 3 4 high rate 46 2 48 44 4 65 bytes high rate 9 16 low rate 85 bytes low rate RD LAP formatted data The frame structure in RD LAP mode is illustrated in Figure 60 RD LAP Over Air Signal Format and typically consists of a Frame Preamble comprising a 24 symbol Frame Synchronisation pattern and Station ID block followed by one or more Head
159. res may provide baseband filtering in order to help reject unwanted adjacent channel signals Such filtering may also have a pass band that is not flat and therefore will degrade reception The CMX7164 provides a Receiver Response Equaliser that will compensate for the group delay and variation in gain of the crystal filter or any other distortions present in the received signal The equaliser must be trained with a clean high level 4 QAM signal in order to establish the receiver response and produce a filter which compensates for it Once this filter is calculated it may be read from the CMX7164 and stored for later use The CMX7164 can be configured with up to two previously stored Receiver Response Equaliser filters which may for example be used to compensate for two different crystal filters in a radio designed to receive in two channel bandwidths Although trained using a 4 QAM signal the resulting filter is suitable to compensate for the receiver response whilst receiving 4 16 or 64 QAM signals A suitable training signal may either be produced using another CMX7164 or the training sequence described in section 15 9 Fl 4 x Receiver Response Equaliser Training Sequence The Receiver Response Equaliser has two modes single mode produces better results when correcting for receivers with a simple baseband roll off for example in a direct conversion architecture Dual mode produces better results when compensating for a radio receiver which inclu
160. rol 6B write register Idle mode for configuration or low power operation Transmit mode for transmission of raw or formatted data Receive mode for detection and reception of bursts containing raw or formatted data Carrier sense mode for attempting to transmit if the channel is free otherwise continuing to receive These four modes are described in the following sections All control is carried out over the C BUS interface either directly to operational registers in transmit receive and carrier sense modes or for parameters that are not likely to change during operation using the Programming Register 6A write in Idle mode To conserve power when the device is not actively processing a signal place the device into Idle mode Additional power saving can be achieved by disabling unused hardware blocks however most of the hardware power saving is automatic Note that Vgias must be enabled to allow any of the Input or Output blocks to function It is only possible to write to the Programming register whilst in Idle mode See 13 1 17 Programming Register 6A write 13 1 18 Modem Mode and Control 6B write 13 2 Programming Register Operation 13 1 24 VBIAS Control B7 write 7 4 1 Normal Operation Overview In normal operation after the CMX7164 is configured the appropriate mode must be selected and data provided in transmit or retrieved in receive This process is carried out by selecting the mode Tx Rx or Carrie
161. rror rate measurements repeated The results are shown in Figure 103 and Figure 104 The results show that with a crystal filter equalisation is most effective at the temperature at which calibration was carried out and that performance degrades away from this temperature In contrast it will be observed that with the CMX994 equaliser performance is maintained across the full operating temperature range For all results a frequency error between transmitter and receiver of less than 100Hz As the crystal filter was used in EV9910B EV9920B we should note that its specified range of operation is 20 to 55 deg C It was also observed that a re calibration at a given temperature would result in equalisation coefficients capable of producing a much improved BER at that temperature 14 Evaluation card for CMX991 CMX992 RF Quadrature Transceiver Receiver ICs O 2015 CML Microsystems Plc Page 122 D 7164 FI 1 x FI 2 xX Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 1 00E 01 1 00E 02 1 00E 03 D UU a 1 00E 04 X 7 CMX992 No Equaliser d X Al ieee CMX992 With Equaliser X N p CMX994 No Equaliser 1 00E 05 Ee CMX994 With Equaliser N pg MC Ba 1 00E 06 p pue Ne be ee ee 40 15 10 35 60 85 Temperature deg C Figure 104 Performance of 64 QAM Equalised Signals with Temperature Variation Bec
162. s data This causes the control byte to be held in the Command FIFO Control Byte register 2015 CML Microsystems Plc Page 48 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Byte wide FIFO writes involve writing to the Modem Command FIFO Data Byte register using either single access or streaming C BUS This causes the Modem Command FIFO Control Byte MSByte and data written to the Modem Command FIFO Data Byte LSByte registers to be put into the command FIFO as one word The control byte can be written separately as a single byte this does not result in anything being added to the FIFO or is preserved from a previous 16 bit Modem Command FIFO Data Byte write Likewise a word read from the Rx Data FIFO will return the Receive FIFO Control Byte in the MSByte and the Receive FIFO Data Byte at the top of the FIFO in the LSByte Both registers will be updated so that when read next time they will provide details of the next item in the FIFO Reading the Receive FIFO Control Byte only will not change the FIFO content Reading the Receive FIFO Data Byte only will provide the data and remove the item from the FIFO updating both control and data registers In summary Operation Effect write Modem Command FIFO Control Byte register Cmd FIFO control word updated nothing added to Cmd FIFO write Modem Command FIFO Data Byte register Cmd FIFO control word data byte written are added to Cmd FIFO write
163. s for 12 5kHz See fig 58 e Expand description of Fl 2 4 FSK deviation configuration See 11 1 10 Signal control 61 e Include over air symbol sequence for Fl 2 2 FSK and 4 FSK and FI 4 data See 7 4 15 11 1 3 and 11 1 26 Specifically this matters for bit wise transfers indicating which bits are valid e Default values in 11 1 9 to be changed 07FF becomes 0400 0801 becomes 0C00 e Addition of Tx Done flag set on completion of DC Calibration to 7 4 11 11 1 18 and 11 1 36 Also indicate that AuxADC paths etc in 7 4 11 are fixed permanently by changing the description assumed to required Figure 34 to show Main PLL out sourced directly from the Xtal in Idle mode Update Figure 3 and correct minor typographical errors Fig 43 Clarify text at the end of section 12 3 2 22 3 11 Change b11 to b9 in section 11 1 14 Remove FI Load Activation Block references and describe default states in section11 1 2 and Table 5 Clarify bit names in section 11 1 20 to avoid duplication e Add missing action 20 in section 11 2 1 no e e ele o 1 e Original document prepared for first alpha release of FI 24 2 11 2015 CML Microsystems Plc Page 12 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 2 Block Diagrams Transmit Functions Fl 1 x FI 2 x amp FI 4 x Channel Coder Data Modulator X IOUTPUTP Fl 1 x FI 2 x amp FI 6 x UO or
164. tes FI 2 x Channel Status Byte User CRC bytes for a Total bytes Block Block Size Coding Rate Header Inter Last Station ID excluding Type only Block Block Block Block frame symbol Sync 3 12 bytes 3 channel RD LAP 1 10 2 1 12 1 8 4 17 bytes status coding 2 bits symbols 0 30 bits 1 channel RD LAP 1 3 5 bytes status symbol coding 6 bits 6 bits Note that in order to be compatible with CMX969 RD LAP coding the initial CRC value must be configured to 0 as shown in Program Block 3 Preamble Tail 9 4 7164Fl 2 x Receiver Response Equaliser When receiving signals using a radio receiver the signal provided to the CMX7164 is likely to be distorted Considering the architecture of Figure 56 as typical the distortion will largely be caused by the crystal filter shown as a bandpass filter in the diagram The crystal filter operates on the received signal at an intermediate frequency its purpose is to attenuate unwanted signals such as those on adjacent channels before they get to the CMX7164 7 Typically the pass band of the crystal filter is not flat or perfectly linear phase resulting in the wanted signal being distorted due to the amplitude phase response of the filter The result is usually a degraded receive signal which will result in poor receive performance for 8 or 16 FSK reception and a small degradation in 2 or 4 FSK reception Other radio architectures may provi
165. thout Sinc Filter Comparison 93 Figure 70 Sensitivity 12 5kHz Channel 4 8ksymbols s With and Without Coding 93 Figure 71 Modem Co channel Rejection with FM Interferer as EN 300 113 94 Figure 72 ACR Rejection Petomance sse eee ee ee eee ee 95 Figure 73 Signal to Noise Performance Comparison of uncoded raw 4 FSK 8 FSK and 16 aT T 96 Figure 74 8 FSK and 16 FSK Coding Performance in Static Channel 97 Figure 75 8 FSK Coding Performance in TU50 Fading Channel 150MHz sssss 98 Figure 76 8 FSK and 16 FSK Co channel Rejection with FM Interferer as EN 300 113 98 Figure 77 8 FSK and 16 FSK Block Error Rate Block Size 0 High Rate Code 12 Byte Blocks of Data in Hees aea 99 Figure 78 4 FSK Signal to Noise Performance Equalised and Non Equalised 100 Figure 79 8 FSK Signal to Noise Performance Equalised and Non Equalised 101 Figure 80 16 FSK Signal to Noise Performance Equalised and Non Equalised 102 Figure 81 Performance of Equalised Signals with Temperature Variation 103 Figure 82 QAM Mapping eee eee ee ee eee 104 Figure 83 Outline Radio Design UO in out for OAM sss sse eee eee 105 Figure 84 Suggested Frame Structures sese eee ee 106 Figure 85 Received 4 and 16 QAM signals no equalisation see eee eee eee eee eee eee 108 Fig
166. ting data content is Table 3 Formatted Block Types and Sizes Fl 1 x Block type User bytes CRC bytes FEC bytes Total bytes Frame Head With bit frame sync 2 0 1 3 Frame Head User data CRC only 6 0 1 7 4 byte data block without CRC 4 0 2 6 6 byte data block without CRC 6 0 3 9 12 byte data block without CRC 12 0 6 18 18 byte data block without CRC 18 0 9 27 4 byte data block with CRC 4 2 3 9 6 byte data block with CRC 6 2 4 12 12 byte data block with CRC 12 2 7 21 18 byte data block with CRC 18 2 10 30 8 4 7164Fl 1 x Typical Transmit Performance Using the test system shown in Figure 47 the 7164FI1 1 x internal PRBS generator was used to modulate the RF vector signal generator Some typical results are shown in the following figures The desired deviation was achieved by adjusting the CMX7164 peak deviation using register 61 I Output o RF Vector Spectrum Analyser Signal Vector Signal Analyser NATOS VQ Generator Q Output Inputs PO 3 Buffer Amplifiers if required to drive RF signal generator modulation inputs Figure 47 Tx Spectrum and Modulation Measurement Configuration for UO Operation 2015 CML Microsystems Plc Page 65 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 Marker 1 T1 21 71 dBm 448 00072745 MHz Unit RF Att Center
167. tion formatted data blocks are supported which may be of variable length up to 48 bytes with a combination of 16 bit or 32 bit CRC for error detection plus trellis coding for error correction In 4 FSK mode the modulation scheme and coding is designed to produce a signal that is over the air compatible with the CML FX MX919B and CMX7143 7143FI 2 x modems 4 FSK mode also supports RD LAP coded block types which are over air compatible with CMX969 9 1 7164Fl 2 x Modulation The 4 FSK scheme running at 2 4ksymbols s 4 8kbps can be used to fit inside a 6 25kHz channel bandwidth a rate of 9 6ksymbols s 19 2kbps can be used in 25kHz bandwidth channels Similarly the 2 FSK scheme running at 2 4ksymbols s 2 4kbps can be used to fit inside a 6 25kHz channel bandwidth a rate of 9 6ksymbols s 9 6kbps can be used in 25kHz bandwidth channels A 12 5kHz channel bandwidth is possible with data rates in between these extremes Channel bandwidth is dependent on the peak deviation that the modulating signal causes the carrier to deviate by as well as the data rate The 7164F1 2 x can also transmit and receive 8 FSK and 16 FSK modulated signals When the device is in 8 16 FSK mode the preamble and the framesync will always be transmitted using 4 FSK modulation The following table shows the list of possible modulation types along with choices for their corresponding preamble and framesync modulation types Payload modulation type Controlled by pro
168. tion 13 2 6 Summary table and subsequent description Program Block 4 P4 5 corrected to say that two of the values apply also to Fl 1 x Section 13 2 6 Summary table for Program Block 4 P4 8 b15 2 corrected to say reserved set to 1 Section 15 10 New Application Note Aborting Rx and Restarting Frame Sync Search Miscellaneous typographical and editorial improvements 02 09 14 20 Section 13 2 4 Clarification to description on frame sync detection and error tolerance Section 13 2 6 Entries and descriptions for P4 8 to P4 10 which offer additional control 19 06 14 Added 16 FSK operation Section 11 Performance figures replace TBDs Section 12 2 4 Entire section rewritten to improve clarity 12 05 14 Described the state of GPIO pins after reset and before a Function Image is loaded Added voltage differential between power supplies to section 11 specification Added description of RAMDAC ramp profile scaling Added description of modulation envelope ramp control Added control method for narrower channel filter options in FI 1 x Added information on 8 16 FSK channel coding Figure 5 replaced by new drawing showing removal of unused components Miscellaneous typographical and editorial improvements 12 02 14 2015 CML Microsystems Plc Page 10 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 16 17 Update of graphs to improve datasheet clarity in v14 Datasheet
169. tion V 23 Tx Bit rate Accuracy 72 Ppm Tx Output Level I Output Q Output 73 2 6 Vp p Tx Adjacent Channel Power I Output Q Output 74 dB PRBS Rx Frequency Error Tolerated 76 2 kHz Rx Co channel Rejection dB Rx Adjacent Channel Rejection 75 dB Notes 72 Determined primarily by the accuracy of the Xtal oscillator provided 73 Transmitting continuous default preamble 74 See Section 11 4 75 See Section 11 5 76 Optimum performance is achieved with OHz frequency error 2015 CML Microsystems Plc Page 143 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 12 2 C BUS Timing CSN m Das d kk 1CSH uc Mil su FU UU UU uu L E CDATA Iz e s s o 1 o v o s 4 s 2 0 7 s s fe tz RDATA HiZ 47 654 4 por Level undefined or not important 70 VDDIO 30 VDDIO SCLK Figure 111 C BUS Timing AC Parameters Notes Min Typ Max Unit C BUS Timing 1 2 Input pin rise fall time 1096 9096 of VDDIO 3 ns Capacitive load on RDATA and IRQN 30 pF tCSE CSN enable to SCLK high time 40 ns tCSH Last SCLK high to CSN high time 40 ns tLoz SCLK low to RDATA output enable time 0 ns tHiz CSN high to RDATA high impedance 40 ns tCSOFF CSN high time between transactions 50 ns tck SCLK cycle time 100 ns CDC SCLK duty cycle 40 60 CDS CDATA setup time
170. tors and it is beyond the scope of this document to provide data for every combination however graphs are provided showing a selection of representative cases ranging from best case performance maximum coding and block size to worst case where no coding is used raw mode Formatted block types 0 6 and 7 See Table 8 and section 10 3 7164FI 4 x Formatted Data for details show different levels of error correction performance formatted block type 7 giving the best performance see Table 8 In all of the following graphs Figure 92 Figure 99 the data rate is 18ksymbols s which is typical of the rate that may be achieved in a 25kHz RF channel The selected transmit and receive filters had a 0 2 The signal to noise ratio is calculated as SNR Mean signal power 174 NF 10 logio RxBW Where NF receiver noise figure in dB RxBW receiver noise bandwidth which in Figure 92 Figure 99 is 18kHz Mean signal power is in dBm SNR Signal to Noise Ratio in dB 1 0E 02 4QAM Raw 16QAM Raw 64QAM Raw 1 0E 03 x DI m 1 0E 04 1 0E 05 8 10 12 14 16 18 20 22 24 26 28 30 32 Signal to Noise Ratio dB Figure 92 Modem Sensitivity Performance The co channel rejection ratio Figure 93 is measured with an interferer modulated with 400Hz FM and having a deviation of 3kHz which is 1296 of the nominal 25kHz channel bandwidth This particular interfering signal
171. ure 86 Received 4 and 16 QAM signals with equalisation cccccesseceeseceeeeeseeeeeeneeeeeeees 108 Figure 87 Tx Spectrum and Modulation Measurement Configuration for UO Operation 109 Figure 88 Tx Modulation Spectra 4 QAM 18ksymbols s I Q Modulation into CMX9996 110 Figure 89 Tx Modulation Spectra 16 QAM 18ksymbols s UO Modulation into CMX998 111 Figure 90 Tx Modulation Spectra 64 QAM 18ksymbols s UO Modulation into CMX998 112 Figure 91 Tx Modulation Spectra 16 QAM 9ksymbols s I Q Modulation into CMX9996 113 Figure 92 Modem Sensitivity Performance sse eee ee ee e ee eee eee ee eee 114 Figure 93 Modem Co channel Rejection with FM Interferer as EN 300 113 115 Figure 94 4 QAM Performance with Different Coding Schemes see 115 Figure 95 16 QAM Performance with Different Coding Schemes sss 116 Figure 96 64 QAM Performance with Different Coding Schemes sess 116 Figure 97 Comparison of BER and PER for 4 QAM Moudulation sese 117 Figure 98 Comparison of BER and PER for 16 QAM Modulation eee 118 Figure 99 Comparison of BER and PER for 64 QAM Modulation eee 118 Figure 100 4 QAM Signal to Noise Performance Equalised and Non Equalised 120 Figure 101 16 QAM Signal to Noise Performance Equal
172. ust not change from low to high 2015 CML Microsystems Plc Figure 13 Basic C BUS Transactions Page 26 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 To increase the data bandwidth between the uC and the CMX7164 certain of the C BUS read and write registers are capable of data streaming operation This allows a single address byte to be followed by the transfer of multiple read or write data words all within the same C BUS transaction This can significantly increase the transfer rate of large data blocks as shown in Figure 14 Example of C BUS data streaming 8 bit write register CSN SCLK CDATA 7 615141312111017 615141312 11017161514 3 211 6 514 312 110 Address First byte Second byte Js Last byte RDATA Hi Z Example of C BUS data streaming 8 bit read register CSN SCLK bare CDATA 7 6 5 4 3 2 1 0 Address RDATA Hiz 7le s a a 2 t o v e s a s a2 t o 76 5 4 3j2j1jo First byte Se
173. ut signal The diagnostic signal is produced by FM demodulating the FFSK tones from the first FM Demodulator output WIE i00mv amp Ch2 soomv M2530us Chi 7 smv Figure 37 Received Signal Second FM Demodulator 7164F1 6 x 7 4 13 Data Transfer The payload data is transferred to and from the host via the C BUS Command and Rx Data FIFOs each of which provide efficient streaming C BUS access FIFO fill level can be determined by reading the Receive FIFO Level and Modem Command FIFO Level and controlled using FIFO Control 50 write register Interrupts may be provided on FIFO fill thresholds being reached or successful transfer of a block of host requested FIFO data between CMX7164 modem and FIFOs Each FIFO word is 16 bits with the least significant byte LSByte containing data and the most significant MSByte containing control information The control information indicates to the CMX7164 what type or how much data is in the LSByte for example if the byte belongs to a header block or contains only 4 valid bits The control and data bytes may be written or read together using the Receive FIFO Word and Modem Command FIFO Word registers or individually using their byte wide registers Word wide FIFO writes involve writing 16 bit words to the Modem Command FIFO Word register using either a single write or streaming C BUS The whole word written is put into the Command FIFO with the upper byte interpreted as control and the lower byte a
174. utput accordingly ErrorlHi Read Errorl assuming High gain and adjust the Output accordingly Iterate go to ErrorQHi after a delay for corrected signals to settle Tidyup Restore the CMX998 to its stage pre calibration ready to output modulation Note Despite no modulation being produced the Tx Done flag of IRQ Status 7E read register will be set at the completion of the CMX998 DC Offset Calibration task The timings of each calibration step can be configured using Program Block 5 Burst Tx Sequence To reduce calibration time a calibration sequence may be configured that omits some stages of the calibration process However there must always be a Setup and TidyUp stage and if ErrorQHi and ErrorlHi are included then the high gain stage must be included as well The registers used during Tx dc offset calibration are 13 1 18 Modem Mode and Control 6B write 13 2 7 Program Block 5 Burst Tx Sequence 13 1 30 I Q Offset 75 76 read 13 1 8 1 Q Output Control 5D 5E write 2015 CML Microsystems Plc Page 42 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 7 4 12 Other Modem Modes Tx Preamble In Tx mode a transmit preamble feature is provided to aid setup the preamble may be programmed to any useful repeating 8 bit pattern Tx PRBS In Tx mode a fixed PRBS pseudo random bit sequence or a repeated preamble transmission is provided and may be used for test and alignment A 511 bit P
175. uts I Input Q Input and two modulator outputs I Output Q Output The analogue gain attenuation of each input and output can be set individually During UO modulation transmit I Output and Q Output will output in phase and quadrature output signals They may be independently inverted and their gains changed During UO modulation receive Input and Q Input will accept in phase and quadrature modulated signals They may be independently inverted and their gains changed During two point modulation transmit the 7164F1 2 x or 7164F1 1 x will output two signals that may be used to drive VCOs in order to create FM modulation The two signals are provided on the and Q Outputs they may be independently inverted and their gains changed Note When transmitting or receiving in UO mode it may be necessary to swap the I and Q signals This effect can be achieved by negating either the I or Q signals 2015 CML Microsystems Plc Page 34 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 See 13 1 8 I Q Output Control 5D 5E write 13 1 9 1 Q Input Control 5F 60 write 13 1 21 I Q Input Coarse Gain B1 B2 write 13 1 23 I Q Output Coarse Gain B4 B5 write 13 1 22 HO Output Configuration B3 write 13 1 20 HO Input Configuration BO write 7 4 7 Tx Mode In typical Tx operation the preamble and FS1 or FS2 are transmitted automatically and then data from the Command FIFO is transmitted directly until
176. ve maximum stability and best start up performance It is also important to achieve a low impedance connection between the Xtal capacitors and the ground plane The DVss to the Xtal oscillator capacitors C1 and C2 should be of low impedance and preferably be part of the DVss ground plane to ensure reliable start up For correct values of capacitors C1 and C2 refer to the documentation of the Xtal used 5 2 C BUS Interface DVpp T 57 56 55 54 53 R2 10k 100kQ Figure 9 Recommended External Components C BUS Interface Note If the IRQN line is connected to other compatible pull down devices only one pull up resistor is required on the IRQN node 2015 CML Microsystems Plc Page 20 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 5 3 VQ Output Reconstruction Filter The CMX7164 WO Outputs provide internal reconstruction filtering with four selectable bandwidths 3dB point shown in section 13 1 22 The bandwidth of the internal reconstruction filter may be selected using the HO Output Configuration B3 write or Signal Control 61 write registers To complete the UO output reconstruction filter one of the following external RC networks should be used for each of the differential outputs The external RC network should have a bandwidth that matches the bandwidth of the selected internal reconstruction filter IOUTPUTP 17 18 19 20 Bandwidth kHz R3 R6 KOhms C
177. which is 1296 of the nominal 12 5kHz channel bandwidth This particular interfering signal is used as it is specified in ETSI standard EN 300 113 for co channel tests 1 00E 01 D 1 00E 02 a 1 00E 03 8 8 2 8 4 8 6 8 8 9 9 2 9 4 9 6 9 8 10 Co Channel Rejection dB Figure 71 Modem Co channel Rejection with FM Interferer as EN 300 113 2015 CML Microsystems Plc Page 94 D 7164_FI 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 9 6 1 2 Adjacent Channel Performance The 7164 Fl 2 x provides excellent rejection of adjacent signals present on the UO inputs Assessment of the adjacent channel rejection ACR performance of the modem is normally made in terms of BER or PER for a given ratio between the wanted signal on channel and larger interferer on the adjacent channel Detailed measurement methods vary depending on the standards in use in particular whether the wanted signal is raised above the sensitivity limit and where the reference is taken The figures quoted here are based on the measurement method from EN 300 113 The BER curve shown in Figure 72 is based on the difference between the interferer 400Hz FM modulation 1 5kHz deviation and the power of the wanted signal for 4 8ksymbols s 1 00E 02 4 mad amp 1 00E 03 a 1 00E 04 60 61 62 63 64 65 66 67 68 Adjacent Channel Rejection dB Figure 72 ACR Rejection Performance The results i
178. with all data and tail bits having been modulated It is now possible to transition to other modes or transmit another burst using the Modem Mode and Control 6B write register The procedure described above can be adapted making transmission of different numbers of bytes bits or coded blocks possible Basic Receive Operation Reception of raw data bytes uses the following procedure C BUS Operation Action Description Write 8000 to FIFO Control 50 write Flush the Command FIFO To ensure that no data is remaining from previous data reception Write 1400 to the Modem Command FIFO Word see Modem Command FIFO Select 4 byte data block reception repeat forever Selects blocks of data bytes to be received after frame sync is detected 4 bytes in each at which point the host will be notified This will continue until the mode is changed 2015 CML Microsystems Plc Page 32 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 C BUS Operation Action Description Data Control 48 49 and 4A write Write 0033 to Rx Tracking 66 write Select tracking modes Selects automatic I Q dc offset correction and symbol timing tracking Write 0401 to Modem Mode and Control 6B write Start reception Initiates a frame sync search searching for Frame Sync 1 Once it is detected then Rx data will be made availabl
179. ype 6 16QAM Block Type 7 V LN L X BEH i 1 0E 04 A U N 1 0E 05 i 10 12 14 16 18 20 22 Signal to Noise Ratio dB Figure 95 16 QAM Performance with Different Coding Schemes 1 0E 02 AUN S 64QAM Raw EN N04 N NI 64QAM Block Type 0 x Fc X 64QAM Block Type 6 S 1 0E 03 p N 64QAM Block Type 7 i A loa d b I m H d 1 0E 04 OE 0 i i VW I g rit N X d 1 0E 05 N 18 20 22 24 26 28 30 Signal to Noise Ratio dB Figure 96 64 QAM Performance with Different Coding Schemes The required performance of a modem may be assessed in terms of either Bit Error Rate BER or Packet Error Rate PER The performance of both measures is affected by coding type and block size but the PER also depends on the size of the packet Short packets with strong coding will exhibit a much lower PER then a long packet with no coding A comparison of PER vs BER for 4 QAM modulation is shown in Figure 97 based on packets of 182 bytes The same comparisons for 16 QAM and 64 QAM are shown in Figure 98 and Figure 99 respectively 2015 CML Microsystems Plc Page 116 D 7164 Fl 1 x FI 2 x Fl 4 x F1 6 x 22 CMX7164 Multi Mode Modem CMX7164 Regulatory standards for radio modem designs using the 7164FI 4 x commonly use either BER or PER to assess the rece
180. yte 2 Byte 3 Frame sync 2 Byte 3 T 8 Byte4 Control byte 1 Bye4 L L R Byte5 Control byte 2 Byte5 Byte 6 FEC FEC2 Byte 6 T Byte 7 D Byte 8 F n T Byte9 18 bytes FEC Byte 10 Byte 11 F T _ Byte 121 L Byte 13 _ Byte 141 T _ Byte 15 l Byte 16 _ pue T Byte 18 CRC E Byte 19 2 bytes Over Air signal BIT FRAME CTRL rec T DD SYNC SYNC BYTES BLOCKS 16 16 24 FRAME PATABLOCKS gt HEAD 0 to 32 FRAME gt Figure 46 Formatted Data Over Air Signal Format The Frame head may be used to contain addressing and control flag information The Data block s contain user data and an optional checksum The CMX7164 performs all of the block formatting and de formatting the binary data transferred between the modem and its UC being that enclosed by the thick dashed rectangles near the top of Figure 46 When receiving data blocks with CRCs the CMX7164 will indicate CRC success or failure and will provide the data regardless 2015 CML Microsystems Plc Page 64 D 7164_Fl 1 x Fl 2 x Fl 4 x Fl 6 x 22 CMX7164 Multi Mode Modem CMX7164 In Figure 46 the size of data block illustrated is 20 bytes when user bytes and CRC bytes are counted together The CMX7164 adds further flexibility by supporting block sizes of 4 6 12 or 18 user bytes with an optional 2 byte CRC The resul

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