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AT-AO-6/10 User Manual

1. o s Bate bus trom counter 1 Reading EREBENEBEREEE I NNNM EEES Data bus in high impedance status e Mode M2 M1 MO setting CT eme Fo o o mode o timrap on Termine Coun Foo Moser reprammabie Oneshot OOO mee Trim Genero NNNM Aia Fx o Mode 4 Gore Tred ote x 9 1 mese arias Tiger Stabe x denotes not specified Operation waveform mode e BCD Operation count mode setting CO Fo Binary coum 6i Bey EE BCD Count 4 decades Binary Coded Decimal After setting Read Load Mode and BCD in each counter as outlined above next set the desired count value in some Modes counting is started immediately after the count value has been written This count value setting must conform with the Read Load format set in advance Note that the internal counters are reset to OOOOH during control word setting The counter value OOOOH can t be read If the two bytes LSB and MSB are written at this stage RLO and RL1 1 1 take note of the following precaution Although the count values may be set in the three counters in any sequence after the control word has been set in each counter count values must be set consecutively in the LSB MSB order in any one Counter National Instruments Corporation Appendix C MSM82C53 Data Sheet A 1 0 MSM82C53 2RS GS JS e Example of contro word and count value setting Counter 0 Read Load
2. DESCRIPTION OF BASIC OPERATIONS Data transfers between the internal registers and the external data bus is outlined in the following table Fe as wma ao 5 58 o remm 00 O o o o o dewbustocounter owriing o o o Dusnceme Win 000000 o o 1 o0 Dmebuswo coumer 2wriins AT AO 6 10 User Manual x denotes not specified DESCRIPTION OF OPERATION 82C53 functions are selected by a control word from the CPU in the required program sequence the contro word setting is followed by the count value setting and execution of the desired timer operation Contro Word and Count Value Program Each counter operation mode is set by control word programming The control word format is out lined below D7 DG DS D4 D3 D2 DI DO Sot see Ae mee oe we Select Counter 6 0 A0 A1 111 RD 1 WR 0 Read Losd Load BCD e Select Counter SCO SC1 Selection of set counter sor se CN o 0 esmero m n o 1 coume 1 sion 1 e coumer zen 3 3 ga comino e Reed Losd RL1 RLO Count value Reading Loading format setting COCO CN o o Goumertatch operation Resding Loading of Least Significant byte LSB ES Reading Loading of Most Significant byte MSB Reading Loading of LSB followed by MSB 310 C 8 o 1 bata bus to contrat word register Writing Data bus from counter 0 Reading o
3. setting the corresponding LDACx bits for the channels to be scanned e setting or clearing corresponding DAC2Sx bits for selecting straight binary or two s complement format Set the SCANEN bit in the CFG3 Register Read the FIFO Clear Register and ignore the result Write the data to the FIFO until all of the data is loaded into the FIFO Sv queo Initialize the output channels by using Counter 1 to generate a single pulse to write the desired first data to the DACs Thus the next update pulse will dump the proper output to the channels To initialize the output channels you must do the following write Ox18 to the CNTRCMD Register e write 2 to the CNTR1 Register 7 Set the FFRTEN bit in the CFG2 Register 8 Set or clear the EXTUPDEN bit to select the update source signal 9 If OUTI is selected as the update signal write 0x34 to the CNTRCMD Register e write the scan cycle period low byte first then high byte in usec to the CNTR1 Register AT AO 6 10 User Manual 4 44 National Instruments Corporation Chapter 4 Programming After writing the high byte the counter starts counting Each update pulse updates the DACS output and loads the new value to each DAC The minimum update cycle is equal to 0 5 usec number of channels in Group 1 The process can be terminated by stopping the update signal or by clearing the FFRTEN or the FIFOEN bits Group 1 Single Channel Mode Using DMA or Interrupt If the SCANE
4. Counting possible Start of counting Counting possible Counting possible possible o 2 1 0 OUT GATE H i n pp C 10 O National Instruments Corporation Appendix C MSM82C53 Data Sheet 22 A 1 0 MSM82C53 2RS GS JS uw WR n 4 n 2 4 3 2 1 4 3 2 1 2 1 2 OUT GATE H LJ L LJ GATE fie gt cso 4 3 2 1 4 4 3 2 1 OUT n 4 l J l WR in 4 f Lin 3 f LE RE 3 4 2 4 2 4 2 4 2 3 2 3 OUT GATE H l l j l J GATE f 5 4 2 5 2 5 4 2 5 2 5 4 OUT n 5 l f LU ra rers OUT GATE H l j GATE l f GATE a ap ee a ee C ee ee 4 3 2 1 0 OUT n 4 l j GATE f l f l 4 3 2 1 4 3 2 1 OUT n 4 f Note n is the value set in the counter Figures in these diagrams refer to counter values 313 National Instruments Corporation C 11 AT AO 6 10 User Manual MSM82C53 Data Sheet Appendix C O MSM82C53 2RS GS JS Reeding of Counter Values All 82C53 counting is down counting the counting being in steps of 2 in mode 3 Counter values can be read during counting by 1 direct reading and 2 counter latching read on the fly 314 Direct reading Counter values can be read by direct reading opera tions Since the counter value read according to the timing of the RD and CLK signals is not guaranteed it is necessary to stop the counting
5. Programming Chapter 4 The formula for the voltage output versus digital code for a unipolar analog output configuration is as follows digital code M tet 4 096 Y out where V is the reference voltage applied to the analog output channel The digital code in the above formula is a decimal value ranging from 0 to 4 095 Table 4 2 Analog Output Voltage Versus Digital Code Unipolar Mode Digital Code Voltage Output 9m w ow ee 5V Vier 3 7 5 V 4 a V ref 4 095 9 9976 V 4 096 The formula for the voltage output versus digital code for a bipolar straight binary analog output configuration is digital code 2 048 2 048 Vout Vref where V e is the reference voltage applied to the analog output channel The digital code in the preceding formula is a decimal value ranging from 0 to 4 095 AT AO 6 10 User Manual 4 36 National Instruments Corporation Chapter 4 Programming Table 4 3 Analog Output Voltage Versus Digital Code Bipolar Straight Binary Mode Digital Code Voltage Output 0 0 PES 10 V Vier 2 047 9 9951 V 2 048 Vref 5V 2 Vref 2 048 0 V ref 2 048 Vref 5V 2 Viet 2 047 9 9951 V 2 048 The formula for the voltage output versus digital code for a bipolar two s complement analog output configuration is as follows digital code Vout zi Vef V ref i 2 048 where V e is the reference voltage applied to the analog output chann
6. Table 2 6 External Reference Selection Channel Jumper Setting External Reference Configuration AT AO 6 10 User Manual 2 10 National Instruments Corporation Chapter 2 Configuration and Installation Internal Reference Selection Factory Setting You select the onboard 10 V reference for each analog output channel by setting the following jumpers as shown in Table 2 7 Table 2 7 Internal Reference Selection Channel Jumper Factory Setting Internal Reference Configuration Analog Output Channel 0 ABC Analog Output Channel 1 ABC Analog Output Channel 2 ABC Analog Output Channel 3 ABC Analog Output Channel 4 c BC B ABC Analog Output Polarity Selection W9 B C A Analog Output Channel 5 W10 B C A C Each analog output channel can be configured for either unipolar or bipolar output A unipolar configuration has a range of 0 to Vref at the analog output A bipolar configuration has a range of National Instruments Corporation 2 11 AT AO 6 10 User Manual Configuration and Installation Chapter 2 Vref to Vref at the analog output Vier is the voltage reference used by the DACs in the analog output circuitry and can be either the 10 V onboard reference or an externally supplied reference between 10 V and 10 V Each channel is configured independently at the factory all channels are configured for bipolar output Bipolar Output Selection Factory Setting You select the bipolar output configuration for e
7. V output corresponds to a digital code word of 0 One LSB is the voltage increment corresponding to an LSB change in the digital code word For unipolar output 1 LSB Vref 4 096 For bipolar output 1 LSB Vref 2 048 AT AO 6 10 User Manual 3 4 National Instruments Corporation Chapter 3 Theory of Operation The voltage reference source for each DAC is jumper selectable and can be supplied either externally at the EXTREF input or internally The external reference can be either a DC or an AC signal If an AC reference is applied the analog output channel acts as a signal attenuator and the AC signal appears at the output attenuated by the digital code divided by 4096 unipolar output or 2048 bipolar output The internal reference is an amplified version of the internal 5 V signal supplied in the input offset section Using the internal reference supplies an output voltage range of 0 V to 9 9976 V in steps of 2 44 mV for unipolar output and an output voltage range of 10 V to 49 995 V in steps of 4 88 mV for bipolar output Gain calibration for the DACs applies only to the internal reference not the external reference Offset calibration can be applied to both references Note Each DAC presents an impedance of 11 KQ unipolar mode or 7 KQ bipolar mode to ground at the EXTREF input when the external reference option is selected Current Output Each channel of the AT AO 6 10 includes a 4 to 20 mA current transmitter for use with
8. 10 board e PCI O channel interface circuitry e Analog output circuitry e Digital VO circuitry RTSI bus interface circuitry The internal data and control buses interconnect the components The theory of operation of each of these components is explained in the remainder of this chapter PC I O Channel Interface Circuitry The AT AO 6 10 board is a full size 16 bit PC I O channel adapter The PC I O channel consists of a 24 bit address bus a 16 bit data bus a DMA arbitration bus interrupt lines and several control and support signals The components making up the AT AO 6 10 PC I O channel interface circuitry are shown in Figure 3 2 Address Address Register Latches Decoder Selects PC I O Channel Read and Write 1 O Channel Timing Signals Control Lines Interface Data 16 Data Internal Buffers Dash E i O O Q Pa AT AO 6 10 DMA DMA Request Control DMA Request DMA Circuitry AT AO 6 10 Acknowledge DMAAcknowledge and Terminal Count IRQ slay AT AO 6 10 es Gqmterrupt Circuitry Request Figure 3 2 PC I O Channel Interface Circuitry Block Diagram AT AO 6 10 User Manual 3 2 National Instruments Corporation Chapter 3 Theory of Operation The PC I O channel interface circuitry consists of address latches address decoder circuitry data buffers PC I O channel interface timing signals interrupt circuitry and DMA arbitration circuitry The PC I O channel interface circu
9. AO 6 10 User Manual change H to L or L to H in the next counter output to be executed The counting opera tion at the gate input is done the same as in mode 2 Mode 4 software trigger strobe The counter output is switched to H level by the mode setting Counting is started in the same way as described for mode 0 A single L pulse equiva lent to one clock width is generated at the counter output when the terminal count is reached This mode differs from 2 in that the L level out put appears one clock earlier in mode 2 and that Pulses are not repeated in mode 4 Counting is f eee NEN MNT NN ees a O Counting posible Counting not possible 1 Counting not possible 2 Counter output forced to H level 1 Counting not possible put Counter a d forced to H level Counting not possible not possible 1 Start of counting 2 Retriggering stopped when the gate input is switched to L level and restarted from the set count value when switched back to H level Mode 5 hardware trigger strobe The counter output is switched to H level by the mode setting Counting is started and the gate input used in the same way as in mode 1 The counter output is identical to the mode 4 out put The various roles of the gate input signals in the above modes are summarized in the following table 1 Start of counting 2 Retriggering Start of counting
10. Chapter 3 The RTSICLK line can be used to source a 10 MHz signal across the RTSI bus or to receive another clock signal from another AT board connected to the RTSI bus BRDCLK is the system clock used by the AT AO 6 10 A multiplexer selects how these clock signals are routed The RTSI switch is a National Instruments custom integrated circuit that acts as a 7x7 crossbar switch Pins B 6 0 are connected to the seven RTSI bus trigger lines Pins A 6 0 are connected to six signals on the board The RTSI switch can drive any of the signals at pins A lt 6 0 gt onto any one or more of the seven RTSI bus trigger lines and can drive any of the seven trigger line signals onto any one or more of the pins A lt 6 0 gt With this capability a signal interconnection scheme is completely flexible for any AT Series board sharing the RTSI bus The RTSI switch is programmed via its chip select and data inputs On the AT AO 6 10 board six signals are connected to six pins of A lt 6 0 gt of the RTSI switch The signal EXTUPDATE is shared with the I O connector and is bidirectional on the RTSI switch EXTUPD is an active low pulse triggered by the EXTUPDATE falling edge on the board and can be driven to the RTSI bus OUT1 OUT2 and OUT3 are onboard counter output and can be driven to the RTSI bus GATES can be an input signal connected to the Counter 3 gate Because Counter 3 output can be selected as the source clock of Counters 1 and 2 theref
11. DGND Digital input specifications referenced to DGND Viy input logic high voltage 2 V minimum Vit input logic low voltage 0 8 V maximum I input current load logic high input voltage 40 LA maximum Ij input current load logic low input voltage 120 LA maximum Digital output specifications referenced to DGND Vox output logic high voltage 2 4 V minimum Voy output logic low voltage 0 5 V maximum Iog output source current logic high 2 6 mA maximum Io output sink current logic low 24 mA maximum With these specifications each digital output line can drive 11 standard TTL loads and over 50 LS TTL loads Figure 2 7 shows signal connections for three typical digital I O applications AT AO 6 10 User Manual 2 18 National Instruments Corporation Chapter 2 Configuration and Installation Port B BDIO lt 3 0 gt Switch T O Connector AT AO 6 10 Board Figure 2 7 Digital I O Connections In Figure 2 7 Port A is configured for digital output and Port B is configured for digital input Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch in Figure 2 7 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 2 7 Power Connections Pin 50 of the I O connector provides 5 V from the PC power supply This pin is referenced to DGND and can be used to power external digital cir
12. Kit Component Board Part Number AT AO 6 776541 01 AT AO 6 board 181435 06 AT AO 10 776542 02 AT AO 10 board 181435 10 National Instruments Corporation 1 1 AT AO 6 10 User Manual Introduction Chapter 1 The board part number is printed on your board along the top edge on the component side You can identify which version of the AT AO 6 10 board you have by looking up the part number in the preceding table In addition to the board each version of the AT AO 6 10 kit contains the following components Kit Component Part Number AT AO 6 10 User Manual 320379 01 NI DAQ software for DOS Windows LabWindows with manuals 776250 01 NI DAQ Software Reference Manual for DOS Windows LabWindows 320498 01 NI DAQ Function Reference Manual for DOS Windows LabWindows 320499 01 If your kit is missing any of the components or if you received the wrong version contact National Instruments Your AT AO 6 10 is shipped with the NI DAQ software for DOS Windows Lab Windows NI DAQ has a library of functions that can be called from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation digital I O counter timer SCXI RTSI and self calibration NI DAQ maintains a consistent software interface among its different versions so you can switch between platforms with minimal modifications to y
13. MSM82C53 2RS GS JS s AC CHARACTERISTICS Vcc 4 5V 5 5V Ta 40 85 C MSM82C53 2 Parameter T boi Max Unit Conditions Pe ms rane Ts no 200 0 Read Recovery Time a Address Set up Time before writing Address Hold Time after writing Write Pulse Width Write Data Input Set up Time before writing TOW 100 ns cycle Data Input Hold Time after writing TWD 20 ns Write Recovery time TRVW 200 ns omc rewire se o m acte wien 7 9 o ces H Gate Pulse Width TGW so pin Output Floating Delay Time after 5 90 ns reading Output Delay Time after gate TODG Output Delay Time after clock Output Delay Time after address TAD Note Timing measured at V4 0 8V and Vg 2 2V for both inputs and outputs Delay time TIME CHART Write Timing 307 National Instruments Corporation C 5 AT AO 6 10 User Manual MSM82C53 Data Sheet Appendix C a MSM82C53 2RS GS JS i Reed Timing HIGH IMPEDANCE HIGH IMPEDANCE EH Clock amp Gate Timing 308 AT AO 6 10 User Manual C 6 O National Instruments Corporation Appendix C MSM82C53 Data Sheet MSM82C53 2RS GS JS DESCRIPTION OF PIN FUNCTIONS National Instruments Corporation D7 DO CLKO 2 OUTO 2 Pin Symbol Name input output Function Bidirectional data bus Chip
14. Register This sequence leaves the AT AO 6 10 circuitry in the following state e FIFO is cleared e All interrupts are disabled e DMA is disabled Digital I O lines are in high impedance state in other words in input mode Calibration is disabled e Both outputs of Counter 1 and Counter 2 are in high state Logic One Programming the Analog Output Circuitry The voltage at the analog output circuitry output pins is controlled by writing to the corresponding DAC Registers and updating the analog output The analog output can be updated in one of two ways immediately when the DAC Register is written or when an active low update pulse is detected Immediately Updating the Analog Output The bits LDACO through LDACS in the CFG2 Register control the update method Each LDAC bit controls two analog output channels LDACO controls Channels 0 and 1 LDAC2 controls Channels 2 and 3 etc If the LDACx bit where x refers to 0 through 8 is cleared writing to the corresponding DAC Register s updates the channel s analog output immediately If the LDACx bit is set writing to the DAC Register does not change the analog output until the LDACx bit is cleared or an update signal is received Using the Update Signal for Waveform Generation When the LDAC bit for the corresponding two DACS is set the DACS are configured in double buffered mode In this mode when a new value is written to a DAC the output of the DAC is not changed until a
15. Write only INTICLR Register Write only CFG3 Register Write only INT2CLR Register Write only DMATCCLR Register Write only MSMS2C53 Counter Timer Register Group CNTRI Register Read and Write CNTR2 Register Read and Write CNTR3 Register Read and Write CNTRCMD Register Read and Write RTSI Bus Register Group RTSISHFT Register Write only RTSISTRB Register Write only Digital I O Register Group DIN Register Read only DOUT Register Write only continues National Instruments Corporation 4 AT AO 6 10 User Manual Programming Chapter 4 Table 4 1 AT AO 6 10 Register Map continued Register Name Offset Address Size Type Hex Analog Output Register Group FIFO WRITE Register Write only FIFO CLEAR Register Read only DACO Register Write only DACI Register Write only DAC2 Register Write only DAC3 Register Write only DAC4 Register Write only DACS Register Write only DAC6 Register Write only DAC7 Register Write only DACS Register Write only DAC Register Write only The registers in the parentheses share the same address with other registers If the GRP2WR bit in the CFG1 Register is set the registers in parentheses are accessed Otherwise the registers without parentheses are accessed when writing to these addresses The DAC6 through DAC9 Registers are available on the 10 channel version of the board only Register Sizes Two different transfer sizes can be used for read and write operations with
16. and Installation Chapter 2 The base address DIP switch is arranged so that you select a logical 1 or true state from the associated address selection bit by pushing the toggle switch down or toward the bottom of the board Alternately you select a logical 0 or false state by pushing the toggle switch up or toward the top of the board In Figure 2 2B for example A9 is up false A8 through A6 are down true and A5 is up false This represents a hex value of ICO The AT AO 6 10 decodes the five least significant bits of the address A4 through AO to select the appropriate AT AO 6 10 register Table 2 3 lists the possible switch settings the corresponding base I O address and the base I O address space used for that setting A Switches Set to Base I O Address of Hex 000 oo o mr Ow XX XXX U72 B Switches Set to Base I O Address of Hex 1C0 Factory Setting Figure 2 2 Example Base I O Address Switch Settings AT AO 6 10 User Manual 2 4 National Instruments Corporation Chapter 2 Configuration and Installation Table 2 3 Switch Settings with Corresponding Base I O Address and Base I O Address Space Switch Setting Base I O Address Base I O Address A9 A8 A7 A6 AS hex Space Used hex 000 O1F 020 03F 040 OSF 060 07F 080 09F 0AO0 OBF 0CO ODF OEO OFF 100 11F 120 13F 140 15F 160 17F 180 19F 1A0 1BF 1C0 IDF 1E0 LFF 200 21F 220 23F 240 25F 260 27F 280 29F 2A0 2B
17. be used when the FIFO is used as a data buffer The program sequence is similar to the DMA program sequence except the DMA is disabled 1 Write a pattern to the CFG1 Register The pattern should include setting the FIFOEN bit aproper value in the CH lt 0 3 gt bit field to select channels to be scanned clearing the EXTUPDEN bit at this time 2 Write a pattern to the CFG2 Register The pattern should include e setting the corresponding LDACx bits for the channels to be scanned setting or clearing corresponding DAC2Sx bits for selecting straight binary or two s complement format respectively Set the SCANEN bit in the CFG3 Register Read the FIFO Clear Register and ignore the result Write the data to the FIFO until it is full we CN cope nen Initialize the output channels by using Counter 1 to generate a single pulse to write the desired first data to the DACs Thus the next update pulse will dump the proper output to the channels To initialize the output channels you must do the following AT AO 6 10 User Manual 4 42 National Instruments Corporation Chapter 4 Programming write 0x18 to the CNTRCMD Register write 2 to the CNTRI Register 7 Set the TCINTEN bit in CFGI Register 8 Program the system interrupt controller and enable the proper interrupt level 9 Set or clear the EXTUPDEN bit to select the update source signal 10 If OUTI is selected as the update signal write 0x34 to the CNTRCMD Regis
18. falling edge of the EXTUPDATE line Address Base address 04 with the GRP2WR bit in the CFG1 Register set Type Write only Word Size 16 bit Bit Map Not applicable no bits used National Instruments Corporation 4 15 AT AO 6 10 User Manual Programming Chapter 4 DMATCCLR Register Writing to the DMATCCLR Register clears the interrupt request caused by either the DMA TC signal or the low to high transition of the Half Full signal of the FIFO Address Base address 00 with the GRP2WR bit in the CFG1 Register set Type Write only Word Size 16 bit Bit Map Not applicable no bits used AT AO 6 10 User Manual 4 16 National Instruments Corporation Chapter 4 Programming MSMS2C53 Counter Timer Register Group The four registers making up the MSM82C53 Counter Timer Register Group access the onboard MSM82C53 Counter Timer The MSM82C53 contains three counters Counters 1 and 2 can be used to generate update signals or interrupts for waveform generation Counter 3 can be used to generate an alternative clock source for Counters 1 and 2 Bit descriptions of the four registers making up the MSM82C53 Counter Timer Register Group are given on the following pages National Instruments Corporation 4 17 AT AO 6 10 User Manual Programming Chapter 4 CNTRI Register The CNTRI Register contains eight bits that are used to load a value into Counter 1 or to read back the value of Counter 1 The CNTR1 Register can be u
19. if the B4 control field contains the pattern 1011 the signal connected to pin A5 appears at pin B4 With this arrangement Trigger Line 4 can be driven by the AT AO 6 10 OUT1 signal In this way boards connected via the RTSI bus can send signals to each other over the RTSI bus trigger lines To program the RTSI switch complete these steps 1 Calculate the 56 bit pattern based on the desired signal routing a Clear the OUTEN bit for all input pins and for all unused pins b Select the signal source pin for all output pins by setting bits S2 through SO to the source pin number c Setthe OUTEN bit for all output pins AT AO 6 10 User Manual 4 48 National Instruments Corporation Chapter 4 Programming 2 For i 0 to 55 follow these steps a Copy bit i of the 56 bit pattern to bit 0 of an 8 bit temporary variable b Write the temporary variable to the RTSI Switch Shift Register 8 bit write 3 Write 0 to the RTSI Switch Strobe Register 8 bit write This operation loads the 56 bit pattern into the RTSI switch At this point the new signal routing goes into effect Step 2 can be completed by simply writing the low order 8 bits of the 56 bit pattern to the RTSI Switch Shift Register then shifting the 56 bit pattern right once and repeating this two step operation a total of 56 times Only bit 0 of the word written to the RTSI Switch Shift Register is used The higher order bits are ignored National Instruments Corporati
20. industry standard 4 to 20 mA current loops An external voltage supply between 7 and 40 V must be used to power each current loop This supply must be in series with the IOUTX connection and the load See Figure 3 5 for a typical current output connection The current output is available on the I O connector between the IOUTX and AGNDX pin for each channel Each transmitter consists of an N channel power MOSFET current sink to ground The output sink current is related to the output voltage by the following equation AV ut 2 5 Link 625 where I is the output current in amperes and V out is the output voltage in volts This equation is correct as long as the result is non negative The AT AO 6 10 current outputs do not source current For example if the reference voltage is 10 V and the board is configured for unipolar output an input digital code of zero yields an output voltage of 0 V and an output current as shown in the following equation 0 2 5 625A 4mA With the same configuration an input code of 4095 yields an output voltage of 9 9976 V and an output current that is shown in the following equation 9 9976 2 5 625 A 19 996 mA The transfer function relating output current to output voltage is graphed in Figure 3 4 National Instruments Corporation 3 5 AT AO 6 10 User Manual Theory of Operation Chapter 3 Figure 3 4 Output Sink Current Versus Output Voltage Maintaining the voltage at the out
21. load 12 VDC 60 mA typical load AT AO 10 5 VDC 1 6 A typical AT AO 6 10 User Manual A 2 National Instruments Corporation Appendix A Physical Board dimensions T O connector Operating Environment Component temperature Relative humidity Storage Environment Temperature Relative humidity National Instruments Corporation Specifications 13 3 in by 4 5 in 50 pin male ribbon cable connector 0 to 70 C 596 to 9096 noncondensing 55 to 150 C 596 to 9096 noncondensing A 3 AT AO 6 10 User Manual Appendix B I O Connector This appendix shows the pinout and signal names for the AT AO 6 10 50 pin I O connector including a description of each connection Figure B 1 shows the AT AO 6 10 I O connector IOUTO RGNDO IOUTI AGNDI IOUT2 RGND2 IOUT3 AGND3 IOUT4 RGND4 IOUTS AGNDS IOUT6 RGND6 IOUT7 AGND7 IOUTS RGND8 IOUT9 DIOO DIO2 DIO4 DIO6 EXTUPDATE 5 V w ju uy Fw Jo m pe pe 15 p efa la f E fe S le fe fe S f fe fS IB E E lo fo lu Jo gt NTS TR a TR a o JW JW o o ro ro to JY e JE 5 j amp l 8 5 2 8 2 5 3 e S 2 8 8 z 5 E 5 3 Jo TIOUTO is used as the internal reference voltage 2 5 V output in the reference calibration mode Figure B 1 AT AO 6 10 I O Connector National Instruments Corporation B 1 AT AO 6 10 User Manual I O Connector Appendix B Signal Connec
22. once and the update pulse updates them together The update source can be either the OUTI or the EXTUPDATE signal If the SCANEN bit of the CFG3 Register is cleared only the DAC CH lt 3 0 gt register uses the FIFO data and is updated by the update pulse The other registers are written individually by programmed I O Address Base Address OC with GRPWR2 set DACO Register Base Address OE hex DACI Register Base Address 10 hex DAC2 Register Base Address 12 hex DAC3 Register Base Address 14 hex DACA Register Base Address 16 hex DACS Register Base Address 18 hex DAC6 Register Base Address 1A hex DACT7 Register Base Address 1C hex DACS Register Base Address 1E hex DAC Register Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C a I a a Bit Name Description 15 12 Sign Bits Sign Extension Bits If the two s complement format of analog output is selected these bits are sign extension bits equal to D11 If the straight binary format is selected these bits are zero AT AO 6 10 User Manual 4 34 National Instruments Corporation Chapter 4 Programming Bit Name Description continued 11 0 D lt 11 0 gt The digital code to be loaded into the DAC This 12 bit data ranges from 0 to 4095 decimal if straight binary format is selected or from 2048 to 2047 decimal if two s complement format is selected National Instruments Corporation 4 35 AT AO 6 10 User Manual
23. or by an active low signal FF generated by the FIFO whenever the FIFO is full DMA Operation Enable Bit When DMAEN is set the DMA operation is enabled The data transferred by the DMA operations is first stored in the FIFO and then written to DAC Group 1 Analog Output Channel Select Bits A value written to these four bits divides the analog output channels into two DAC groups The channels that are equal to or lower than the value of CH lt 3 0 gt form DAC Group 1 The remaining channels form DAC Group 2 If the value of CH lt 3 0 gt is equal to zero Channel 0 is in Group 1 The remaining channels are in Group 2 If the value of CH 3 0 is equal to nine all 10 channels are in Group 1 If the SCANEN bit in the CFG3 Register is set Channels 0 through Channel CH lt 3 0 gt make up DAC Group 1 If the SCANEN bit is cleared Channel CH lt 3 0 gt is DAC Group 1 The channels in the same DAC group have the same update source If the FIFO is enabled the data written to the channels in Group 1 is from the FIFO National Instruments Corporation 4 7 AT AO 6 10 User Manual Programming Chapter 4 STATUS Register The STATUS Register contains 7 bits that reflect the status of the FIFO the interrupts and the output data bit of the EEPROM Address Base address OA hex Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Description 15 7 X Don t care bits When read the
24. pages AT AO 6 10 User Manual 4 28 National Instruments Corporation Chapter 4 Programming DIN Register Reading the DIN Register returns the logic state of the eight AT AO 6 10 digital I O lines Address Base address 00 hex with the GRP2WR bit in the CFGI Register cleared Type Read only Word Size 16 bit Bit Map 15 14 13 12 11 10 HA 7 6 5 4 3 2 1 0 BDI3 BDD BDII BDIO ADI3 ADD ADII ADIO Bit Name Description 15 8 X Don t care bits 7 4 BDI lt 3 0 gt These four bits represent the logic state of the digital lines BDIO lt 3 0 gt 3 0 ADI lt 3 0 gt These four bits represent the logic state of the digital lines ADIO lt 3 0 gt National Instruments Corporation 4 29 AT AO 6 10 User Manual Programming Chapter 4 DOUT Register Writing to the DOUT Register controls the eight AT AO 6 10 digital I O lines The DOUT Register controls both Ports A and B When either digital port is enabled the pattern contained in the DOUT Register is driven onto the lines of the digital port Address Base address 00 hex with the GRP2WR bit in the CFGI Register cleared Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 AAA AA AAA 7 6 5 4 3 2 1 0 BDO3 BDO2 BDOI BDOO ADO3 ADO2 ADOI ADOO Bit Name Description 15 8 X Don t care bits 7 4 BDO lt 3 0 gt These four bits control the digital lines BDIO lt 3 0 gt The bit DOUTEN2 in the CFG3 Register must be set for BDO lt 3 0 gt to be driven onto the
25. reference signals Pins 7 8 15 16 23 24 31 32 and 39 are the ground reference points for the analog output channels Figure 2 6 shows how to make analog voltage output connections and the external reference input connection to Channel 0 and Channel 1 as an example EXTREFO External Channel 0 Reference 1 VOUTO Signal Optional o 7 AGNDO Channel 1 5 VOUTI Analog Output Channels AT AO 6 10 Board Figure 2 6 Analog Voltage Output Connections An example of the analog current output connection is given in Chapter 3 Theory of Operation The external voltage source is required to power the current loops The external reference signal can be either a DC or an AC signal This reference signal is multiplied by the DAC code to generate the output voltage National Instruments Corporation 2 17 AT AO 6 10 User Manual Configuration and Installation Chapter 2 Digital I O Signal Connections Pins 40 through 47 of the I O connector are digital I O signal pins Pins 40 41 42 and 43 are connected to the digital lines ADIO lt 3 0 gt for digital I O Port A Pins 44 45 46 and 47 are connected to the digital lines BDIO lt 3 0 gt for digital I O Port B Pin 49 is the digital ground pin for both digital I O ports Ports A and B can be programmed individually to be inputs or outputs The following specifications and ratings apply to the digital I O lines Absolute maximum voltage input rating 5 5 V with respect to
26. state of the digital I O lines Digital I O lines ADIO lt 3 0 gt are connected to bits lt 3 0 gt of the DIN Register Digital I O lines BDIO lt 3 0 gt are connected to bits lt 7 4 gt of the DIN Register When a port is enabled for output the DIN Register serves as a read back register returning the digital output value of the port When a port is not enabled for output reading the DIN Register returns the state of the digital I O lines driven by an external device Both the DIN and DOUT Registers are TTL compatible The digital output ports when enabled are capable of sinking 24 mA of current and sourcing 2 6 mA of current on each digital I O line When the ports are not enabled for output the digital I O lines act as high impedance inputs RTSI Bus Interface Circuitry The AT AO 6 10 is interfaced to the National Instrument RTSI bus The RTSI bus has seven trigger lines and a system clock line All National Instruments AT Series boards with RTSI bus connectors can be wired together inside the PC to share these signals A block diagram of the RTSI bus interface circuitry is shown in Figure 3 7 10 MHz Oscillator RTSICLK OUTI GATE3 NC EXTUPD OUT3 OUT2 EXTUPDATE E S 9 v S g OQ un za Laa z aa RTSI SEL SEL Internal DATA Data Bus RTSI Switch Figure 3 7 RTSI Bus Interface Circuitry Block Diagram National Instruments Corporation 3 9 AT AO 6 10 User Manual Theory of Operation
27. static operation 28 pin PLCC QFJ28 P S450 e Three independent 16 bit down counters 32 pin V Plastic SOP SSOP32 P 430 VK e 3V to 6V single power supply FUNCTIONAL BLOCK DIAGRAM COUNTER COUNTER mius INTERNAL BUS d DATA READ CONTROL WRITE i WORD REGISTER 304 AT AO 6 10 User Manual C 2 O National Instruments Corporation Appendix C MSM82C53 Data Sheet a MSM82C53 2RS GS JS m PIN CONFIGURATION MSMB2C53 2RS Top View 24 pin Plastic DIP MSMB2C53 2GS Top View 32 pin Plastic Small Outine Package NC denotes not connected E MSM82C53 2JS Top View 28 pin Plastic Leaded Chip Carrier 19 GATE2 305 O National Instruments Corporation C 3 AT AO 6 10 User Manual MSM82C53 Data Sheet Appendix C 1 0 MSM82C53 2RS GS JS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Conditions Ssupply Voltage a 0 5 to 7 V Output Votgs OPERATING RANGES puer T 2 um Supply Voltage Vit 02V Vin Vcc 02V aaa frequency 2 6 MHz Pees bb aaa 010788 RECOMMENDED OPERATING CONDITIONS eee eme m Tom oem om supply Voge ve ss 5 ss v Gewwneweun te s e Lema OO 9 Y votos vw 2 veer Y DC CHARACTERISTICS EET H Output Voltage VoH cs F TT 0 2V Vin Z Vcc 0 2V Vit 0 2V 306 AT AO 6 10 User Manual C 4 National Instruments Corporation Appendix C MSM82C53 Data Sheet
28. the PC byte 8 bit and word 16 bit Table 4 1 shows the size of each AT AO 6 10 register For example reading the Status Register requires a 16 bit word read operation at the selected address whereas writing to the RTSISHFT Register requires an 8 bit byte write operation at the selected address Register Description Table 4 1 divides the AT AO 6 10 registers into five different register groups A bit description of each of the registers making up these groups is included later in this chapter The Configuration and Status Register Group controls the overall operation of the AT AO 6 10 hardware The configuration registers are used to program the DAC output mode the DAC channel selection the DAC calibration the digital mode and to enable DMA or interrupt requests The status registers reflect the state of the FIFO interrupt requests and DMA requests The registers in the Analog Output Register Group access the DACSs or FIFO The registers in the Digital I O Port Group access the two 4 bit digital I O ports The MSM82C53 Counter Timer Register Group selects the counting mode and initial count of the three counters The RTSI Bus Register Group configures the RTSI bus switch AT AO 6 10 User Manual 4 2 National Instruments Corporation Chapter 4 Programming Register Description Format The remainder of this section discusses each of the AT AO 6 10 registers in the order shown in Table 4 1 Each register group is introduced foll
29. the analog outputs set up for a bipolar output range with the internal reference If you want to use a different analog output configuration it may be necessary to recalibrate the analog output offsets and gains Calibration DACs There are 21 8 bit DACs on the AT AO 10 and 13 8 bit DACs on the AT AO 6 that are used for calibration The AT AO 6 10 is shipped fully calibrated The factory determined calibration values are stored in the location byte 96 through byte 116 of the EEPROM see Figure 5 1 and a copy is stored the location word 0 through 20 Upon startup the copied values are read and written to the corresponding calibration DAC by software The user determined calibration value can be stored in any portion of User 2 through User 4 of the EEPROM The offset adjustment range for each channel is 200 mV in bipolar mode and 100 mV in unipolar mode The resolution is 8 bit that is the adjustment range divided by 128 The gain adjustment range is 0 5 of full AT AO 6 10 User Manual 5 2 National Instruments Corporation Chapter 5 Calibration Procedures output scale for each channel The resolution is 8 bit Recalibration is seldom necessary Making a recalibration every year or so is sufficient The following sections describe the recommended calibration procedure which requires a voltmeter with 0 005 resolution and accuracy Reference Calibration The AT AO 6 10 has built in 5 V 10 V and 2 5 V references for the DACs These refere
30. the user s discretion and these new calibration constants can be stored in one of four user slots in the EEPROM The EEPROM constants written to the calibration DAC can either be factory calibrated values or user defined values to accommodate differing testing situations A map of the EEPROM location can be found in Chapter 5 Calibration Procedures Digital I O Circuitry The AT AO 6 10 has eight digital I O lines These lines are divided into two ports of four lines each and are located at pins ADIO lt 3 0 gt and BDIO lt 3 0 gt on the I O connector Figure 3 6 shows a block diagram of the digital I O circuitry DOUTA Digital 4 DOUTA ENABLE DO REG WR DATA lt 7 4 gt 4 Digital BDIO lt 3 0 gt Output DOUTB ENABLE Register I O Connector D S S O 9 O a DATA lt 7 0 gt DINA Digital m DINB Figure 3 6 Digital I O Circuitry Block Diagram AT AO 6 10 User Manual 3 8 National Instruments Corporation Chapter 3 Theory of Operation The digital I O lines are controlled by the DOUT Register and monitored by the DIN Register The DOUT Register is an 8 bit register that contains the digital output values for both Ports A and B When Port A is enabled bits lt 3 0 gt in the DOUT Register are driven onto digital output lines ADIO lt 3 0 gt When Port B is enabled bits lt 7 4 gt in the DOUT Register are driven onto digital output lines BDIO lt 3 0 gt Reading the DIN Register returns the
31. 00 Len o S P s xu 000000000 2 Pogooos National Instruments Corporation iagram Configuration and Installation 00000000000000 gopovococoocoo oo oo cd P ng Vii Ed nw posui sn len seil conos Ud SO Al a Oi wi i m ay y Z 00000 dafs fad mc 1253 opo wrest il HINAS a dd ssn EL uns a9xro pu gena 3 onaoaonenp esca go 8H af meade oap9gaceo d I d ro na ES EI REEREPI 3 poseav 0 0 jj K 00000800 aloe A O OLOlra AR lo fen 088744 00000000 000000000 see 00000060 ago seee BB r 000000001 41 21s0Emz O it2vs 0000001 i M ro ra b af Toosoo 54 a o 92 El 1000000080000 gan 20 vby00L 0000000000000 of 88 SEPvIBIASSY 8 3 n ja 661 1HDIMAdDO A 01 9 Dv jv o SNARE N S SLM 6 10 Parts Locator D AT AO 1 2 igure F 2 2 AT AO 6 10 User Manual Chapter 2 Configuration and Installation Base I O Address Selection The base I O address for the AT AO 6 10 is determined by the switches at position U72 see Figure 2 1 The switches are set at the factory for the base I O address 1CO hex This factory setting is used by National Instruments software packages as the default base I O address value for the AT AO 6 10 The AT AO 6 10 uses the base I O address space 1CO hex through 1DF hex with the factory setting Note Verify that this space is not alread
32. 2 FSR vii H hardware installation 2 14 hex vi I I O vii I O channel interface circuitry 3 2 to 3 3 I O connector B 1 to B 2 pin assignments 2 15 initializing the board 4 39 to 4 40 input signal connections See signal connections installation 2 14 INTICLR Register 4 12 INT2CLR Register 4 15 internal reference 2 0 selection 2 11 interrupt jumper setting IRQ11 and IRQ12 2 7 interrupt selection 2 7 J jumper configuration 2 1 to 2 8 K ksamples vi National Instruments Corporation Index 3 Index AT AO 6 10 User Manual Index L LabVIEW for Windows software 1 2 to 1 3 LabWindows for DOS software 1 2 to 1 3 LSB vii M MSM82C53 Counter Timer Register Group 4 1 4 17 to 4 25 MSMS82C53 data sheet C 1 to C 3 N NI DAQ software for DOS Windows LabWindows 1 2 O operating environment A 3 operation of AT AO 6 10 3 1 to 3 10 optional equipment for AT AO 6 10 1 3 optional software for AT AO 6 10 1 2 to 1 3 output signal connections See signal connections output sink current versus output voltage 3 6 P parts locator diagram 2 2 PC I O channel interface circuitry 3 2 to 3 3 physical specifications A 3 polarity selection analog output 2 11 to 2 14 bipolar output selection 2 12 to 2 13 unipolar output selection 2 13 to 2 14 power connections 2 19 power requirements A 2 programming 4 1 to 4 49 analog output circuitry 4 40 to 4 46 digital I O circuitry 4 46 ini
33. 2 Re9lStet eiie detis ees a dotati tute E 4 10 INTICER RO EE E E RE a ERI Hie qns 4 12 CPG RESISTE o ho ete ar a E E E E 4 13 INTZCLR RESISIGE toalla bree Mea I M S r 4 15 DMATCCER Rep ista iia 4 16 MSM82C53 Counter Timer Register Group eere 4 17 ENTER DAS COTS IE us ds 4 18 ENTRA REIS GS Gods Desc itas qae Monde danas ate se pu iae it ar sd 4 19 CINTRS Re9ISIEEG ioo qridop de aee gata ede shea antes ee it heaves 4 20 CINTRCMD Riera eue Ee a 4 21 Read Back Command 5n ep da 4 23 Status Bo lem saccade oo ais meii a N na M ma Me tesi e ictu 4 24 RISIB s Register Oro uii iioii oe rii doce in Aci edges 4 25 RESISHFT Register oco oia dedu 4 26 RISISTRBABOSISIEE S etos e do as 4 27 Digital I O Register Gro ai citas 4 28 DIN Recio it 4 29 A E A 4 30 Analog Output Register OTI ti A ii tn 4 31 FIFO WRITE Register adoro 4 32 FIFOCLEAR Reir oia 4 33 DACO through DACO Registers ui crei etit pdt eoe tend 4 34 Programming Considerations is roe A ie doen eere dioe dae d pn Behe 4 39 Register Programming Considerations eene 4 39 Initializing the AT AO 6 10 Board itte hdiei ened 4 39 Programming the Analog Output Circuitry eee 4 40 Immediately Updating the Analog Output esee 4 40 Using the Update Signal for Waveform Generation 4 40 Analog Output Channel Group eee 4 40 Select Update So
34. AT AO 10 configure the analog output circuitry Jumper W21 is used for initial calibration functions and should not be changed so it is removed from the board prior to shipping The DIP switch is used to set the base I O address The jumpers and DIP switch are shown in the parts locator diagram in Figure 2 1 AT Bus Interface The AT AO 6 10 is configured at the factory to a base I O address of 1CO hex to use DMA Channel 5 and to use interrupt levels 11 and 12 These settings shown in Table 2 1 are suitable for most systems However if your system has other hardware at this base I O address DMA channel or interrupt level you need to change these factory settings on the AT AO 6 10 as described in the following pages or on the other hardware Table 2 1 AT Bus Interface Factory Settings Base I O Address Hex 1CO factory setting The white portion indicates the position of the raised part of the slide switch DMA Channel DMA Channel 5 W22 DROQS DACK5 factory setting W24 no jumpers Interrupt Level Group 1 interrupt level 11 selected W23 Row 11 Group 2 interrupt level 12 selected W23 Row 12 factory setting National Instruments Corporation 2 1 AT AO 6 10 User Manual Chapter 2 ETM vZM SLM ZZM Ln 61M IU UB UL JU A l 4 na MITT ECC S rie Atria 0000068 2 oog dcm saoo amp neto d NE nE di O pedis lip ERE pei zl bris git en Spies um Bp 80S oo 9 t OS 00007 0001 00000000000 00000000 2615 1000
35. AT AO 6 10 User Manual Expansion Board for the PC AT EISA September 1994 Edition Part Number 320379 01 Copyright 1991 1994 National Instruments Corporation All Rights Reserved National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin TX 78730 5039 512 794 0100 Technical support fax 800 328 2203 512 794 5678 Branch Offices Australia 03 879 9422 Austria 0662 435986 Belgium 02 757 00 20 Canada Ontario 519 622 9310 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Italy 02 48301892 Japan 03 3788 1921 Mexico 95 800 010 0793 Netherlands 03480 33466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 20 51 51 Taiwan 02 377 1200 U K 0635 523545 Limited Warranty The AT AO 6 and AT AO 10 are warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation Na
36. D lt 0 8 gt PC I O Channel T O Connector OUTI 2 RD WR From AT Bus WR RD I Interface DACK FF HF EF Channel 9 3x l D A Control To AT Bus p PRQ DACWR UPDATEI 2 Interface 0 oc lt EXTUPDATE Figure 3 3 Analog Output Circuitry Block Diagram Each analog output channel contains a 12 bit D A converter DAC output operational amplifiers op amps reference selection jumpers unipolar bipolar output selection jumpers and a current transmitter Each two channels share an EXTREF input line on the I O connector Voltage Output The DAC in each analog output channel generates a current proportional to the input voltage reference Vref multiplied by the digital code loaded into the DAC Each DAC can be loaded with a 12 bit digital code The output op amps convert the DAC current output to a voltage output on the I O connector VOUTX pins The DAC output op amps can be jumper configured to generate either a unipolar voltage output or a bipolar voltage output range A unipolar output has an output voltage range of 0 to Vref 1 LSB V A bipolar output has an output voltage range of Vref to Vref 1 LSB V For unipolar output 0 V output corresponds to a digital code word of 0 For bipolar output the format of the digital code input is software selectable from Command Register 2 If straight binary format is selected 0 V output corresponds to a digital code word of 2 048 If two s complement format is selected 0
37. F 2C0 2DF 2E0 2FF 300 31F 320 33F 340 35F 360 37F 380 39F 3A0 3BF 3C0 3DF 3E0 3FF cooooooooeoeu o ocooooooco rR OOCOrRr FP OOOCOrR Fr FP rPOCOOrRFR rr OoOCoOoO PROOF FP OOF rFOOrF FP OOF rFOOrFFOOrFrFrOOrFF OO RPOrOrFOrFOrFOrOFOFOFOFrOFOFOFOFrOFOFO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Base I O address values 000 through OFF hex are reserved for system use Base I O address values 100 through 3FF hex are available on the I O channel National Instruments Corporation 2 5 AT AO 6 10 User Manual Configuration and Installation Chapter 2 DMA Channel Selection The DMA channels used by the AT AO 6 10 are selected by jumpers W22 and W24 see Figure 2 1 The AT AO 6 10 is set at the factory to use DMA Channel 5 This channel is the default DMA channel used by the AT AO 6 10 software handler Verify that this DMA channel is not also used by equipment already installed in your computer If any device uses DMA Channel 5 change the DMA channel used by either the AT AO 6 10 or the other device Unless the appropriate DMA modes have been enabled on the AT AO 6 10 through software the DMA channel is by default in the high impedance state at startup The DMA channels supported by the AT AO 6 10 hardware are Channel 0 through Channel 3 and Channel 5 through Channel 7 If the AT AO 6 10 is used in an AT type computer only DMA C
38. LSB only Mode 3 Binary count count value 3H Counter 1 Read Load MSB only Mode 5 Binary count count value AAOOH Counter 2 Read Load LSB and MSB Mode O BCD count count value 1234 MVI A 1EH E OUT n3 Counter 0 control word setting MVI A aul s QUT n3 Counter 1 control word setting MVI A BIH OUT n3 Counter 2 control word setting MVI A 03H OUT nO Counter 0 count value setting MV A AA Z OUT nt Counter 1 count value setting MVI A 34H OUTn2 Counter 2 count value setting MVI A 12H LSB then MSB OUT n2 Note nO Counter 0 address nt Counter 1 address n2 Counter 2 address n3 Control word register address e The minimum and maximum count values which can be counted in each mode are listed below As ditto in other modes RE E AAA 2 2 o eannorbe counted s 2 1 executes 10001H count CHIENS IN eee EA d Mode Definition e Mode 0 terminal count The counter output is set to L level by the mode setting f the count value is then written in the counter with the gate input at H level that is upon completion of writing the MSB when there are two bytes the clock input counting is started When the termina count is reached the output is switched to H level and is maintained in this status until the control word and count value are set again Counting is interrupted if the gate input is switched to L level and restarted when switched back
39. N bit in the CFG3 Register is cleared Group 1 is in the single channel mode In this mode only Channel CH lt 3 0 gt is used for waveform generation If the FIFO is used the data in the FIFO is only sent to channel CH lt 3 0 gt and the update signal only updates this channel and the channel controlled by the same LDACx bit The rest of the channels in Group 1 are in the immediate update mode that is they are written by software and immediately updated The programming steps are the same as those in the Scan Mode except the SCANEN bit in the CFG3 Register is cleared that is step 3 in the preceding programming sequence is not needed Group 2 Using Interrupt The channels beyond CH lt 3 0 gt if there are any left make up Group 2 Group 2 does not use the FIFO and DMA operation It can use either the Counter 2 Interrupt or the External Update Interrupt 2 to write values to the DACs and update the output channels The Group 2 output channels are always updated together The program steps are as follows 1 Write a proper value to the CH lt 0 3 gt bit field of the CFG1 Register to group the DACs 2 Write a pattern to the CFG2 Register The pattern should include e setting the corresponding LDACx bits for the channels in Group 2 for waveform generation e setting or clearing corresponding DAC2Sx bits for straight binary or two s complement format 3 Write the first data to the DACs 4 Set the CNTINT2EN or the EXTINT2EN bi
40. O 6 10 signal lines through special metal conduits if it is necessary to pass them through these areas Cabling Considerations National Instruments has a cable termination accessory the CB 50 for use with the AT AO 6 10 board This kit includes a terminated 50 conductor flat ribbon cable and a connector block Signal I O leads can be attached to screw terminals on the connector block and thereby connected to the AT AO 6 10 I O connector The CB 50 can be used for prototyping an application or in situations where AT AO 6 10 interconnections are frequently changed However once a final field wiring scheme has been developed you may want to develop your own cable The AT AO 6 10 I O connector is a 50 pin male ribbon cable header The manufacturer part numbers for this header are as follows Electronic Products Division 3M part nnmber 3596 5002 T amp B Ansley Corporation part number 609 5007 The mating connector for the AT AO 6 10 is a 50 position ribbon socket connector polarized with strain relief National Instruments uses a polarized keyed connector to prevent inadvertent misconnection to the AT AO 6 10 Recommended manufacturer part numbers for this mating connector are as follows Electronic Products Division 3M part number 3425 7650 T amp B Ansley Corporation part number 609 5041CE Recommended manufacturer part numbers for the standard ribbon cable 50 conductor 28 AWG stranded that can be used with these connectors are E
41. O THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks LabVIEWS NL DAQ and RTSI are trademarks of National Instruments Corporation Product and company names listed are tr
42. a stored in the FIFO to the desired DACs The data is loaded into the FIFO once before the loading of the DACs begins The AT AO 6 10 uses dual DAC integrated circuits Each integrated circuit can be software configured for double buffering mode This feature is usually used for waveform generation In waveform generation mode the new value loaded to a DAC does not change the channel s output until an update signal is detected The ten DACs on the AT AO 10 and the six DACs on the AT AO 6 can be divided into two groups to use different update signal sources The following sources can be used to generate update signals e The onboard counter Counter 1 output is for Group 1 of the DAC and Counter 2 output is for Group 2 of the DAC e The EXTUPDATE signal on the I O connector This update source can be used by either group The EXTUPDATE signal derived from the RTSI bus Software controlled update The AT AO 6 10 incorporates onboard calibration circuitry to individually adjust the gain and offset for each analog output channel The startup calibration process is accomplished by retrieving constants stored in the AT AO 6 10 EEPROM and writing them to the calibration DAC The board is calibrated at the factory and these calibration values are stored in unmodifiable National Instruments Corporation 3 7 AT AO 6 10 User Manual Theory of Operation Chapter 3 locations in the EEPROM see Figure 5 1 The board can also be recalibrated at
43. ach analog output channel by setting the following jumpers as shown in Table 2 8 Table 2 8 Bipolar Output Selection Channel Jumper Factory Setting Bipolar Output Configuration Analog Output Channel 0 ABC Analog Output Channel 1 ABC Analog Output Channel 2 ABC Analog Output Channel 3 ABC Analog Output Channel 4 BC C C C C B Analog Output Channel 6 A Analog Output Channel 7 B Analog Output Channel 8 A B Analog Output Channel 9 ABC AT AO 6 10 User Manual 2 12 National Instruments Corporation WII B C A Analog Output Channel 5 WI2 A B A Chapter 2 Configuration and Installation Data can be written to the DAC in either straight binary mode or two s complement mode depending on certain configuration register bits When you use bipolar configuration you must select whether to write to the DAC in straight binary mode or two s complement mode In straight binary mode data values written to the analog output channel range from 0 to 4 095 decimal 0 to OFFF hex In two s complement mode data values written to the analog output channel range from 2 048 to 2 047 decimal F800 to 07FF hex Unipolar Output Selection You select the unipolar output configuration for each analog output channel by setting the following jumpers as shown in Table 2 9 Table 2 9 Unipolar Output Selection Channel Jumper Setting Unipolar Output Configuration Analog Output Channel 0 ABC Analog Output Channel 1 ABC Analog Output C
44. ademarks or trade names of their respective companies WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of established process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment Contents About This Manual eee nettement tne tn cian ix Organization of This Manual 5 2 eniti ter teen vob pido cusses sacs soeatasvsvaaevucacceus densos ix Conventions Used in This Man al sensia ieiti aiin X Related Documentatii Nissisen eene nennen TE ese e ese ese esas eis X Customer Communicatio
45. all register bits simultaneously You cannot read these registers to determine which bits have been set or cleared in the past therefore you should maintain a software copy of the write only registers This software copy can then be read to determine the status of the write only registers To change the state of a single bit without disturbing the remaining bits set or clear the bit in the software copy and write the software copy to the register Initializing the AT AO 6 10 Board Upon startup the AT AO 6 10 hardware is auto initialized All bits in the three CFG Registers are cleared The voltage output of each analog output channel is set to 0 V in the bipolar mode or 5 V in the unipolar mode if the internal 10 Ver is selected or it is set to the medium value of the external reference voltage The hardware can be also initialized by the software To initialize the AT AO 6 10 hardware complete these steps 1 Write 0 to the CFGI Register Write 18 to the CNTRCMD Register Write 3 to the CNTRI Register Write 58 to the CNTRCMD Register Write 0 to the CFG2 Register Write 0 to the CFG3 Register Read the FIFO CLEAR Register Ignore the result Write 80 to the CFG1 Register ne 800 es Fy os ipu el Write 0 to the INTICLR Register e Write 0 to the INT2CLR Register ER mO Write 0 to the DMATCCLR Register National Instruments Corporation 4 39 AT AO 6 10 User Manual Programming Chapter 4 12 Write 0 to the CFGI
46. and from the AT AO 6 10 Noise pickup and crosstalk can be minimized and signal accuracy optimized if the following recommendations for analog signal connections are followed e Use individually shielded twisted pair connections for voltage output signals In such cases the voltage output and its corresponding analog ground signal wire are twisted together and the shield is connected to the analog ground at the AT AO 6 10 The other end of the shield is left disconnected AT AO 6 10 User Manual 2 20 National Instruments Corporation Chapter 2 Configuration and Installation e Reference inputs should also be connected via shielded twisted pair connection The shield should be grounded at the signal source e Current outputs are relatively immune to line loss and noise pickup and should be used for signal transmission over long distances e All AT AO 6 10 signal lines should be physically separated from high current or high voltage lines These lines can induce currents into the AT AO 6 10 signal lines if they are run in parallel paths at a close distance Reduce the magnetic coupling by separating the lines by a reasonable distance if they run in parallel or by running the lines at right angles to each other e Do not run AT AO 6 10 signal lines through conduits that also contain power lines e Protect AT AO 6 10 signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running the AT A
47. apter 4 Programming CNTR2 Register The CNTR2 Register contains eight bits that are used to load a value into Counter 2 or to read back the value of Counter 2 The CNTR2 Register can be used as an 8 bit register or as a 16 bit register by two successive write read operations Address Base address 07 hex with the GRP2WR bit cleared Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 CNTR2B7 CNTR2B6 CNTR2B5 CNTR2B4 CNTR2B3 CNTR2B2 CNTR2B1 CNTR2BO Bit Name Description 7 0 CNTR2B lt 7 0 gt Counter 2 Load Read Bits Writing a data value to these bits loads the starting value into Counter 2 Reading these bits returns the current count of Counter 2 or latched data for Counter 2 If the Counter Latch command or the Read Back command is used to latch the count or status of Counter 2 reading these bits returns the latched information The latched data remains latched until it is read If multiple Latch commands or Read Back commands are issued before the latched data is read only the data from the first Status Latch command and the first Counter Latch command are latched all commands after the first are ignored If 16 bit data is latched the first read from this register returns the least significant byte and the second read returns the most significant byte If status and count information are both latched the first read to this register returns the status byte and the next one read for 8 bit mode
48. ared It is cleared by writing to the DMA TC CLR Register 0 PROMOUT EEPROM Output Bit This bit reflects the value of the data shifted out of the EEPROM using SCLK with the PROMEN bit set National Instruments Corporation 4 9 AT AO 6 10 User Manual Programming Chapter 4 CFG2 Register The CFG2 Register contains 16 bits that control the DAC calibration the DAC input data format and the DAC output modes Address Base address 02 hex with the GRP2WR bit in the CFG1 Register cleared Type Write only Word Size 16 bit Bit Map 15 14 13 12 is 1 10 CALLD1 CALLDO FFRTEN DAC2S8 DAC2S4 DCSE CR 7 6 5 4 3 LDAC6 LDAC4 LDAC2 RONEN DAT Bit Name Description 15 14 CALLD lt 1 0 gt Calibration DAC Load Bits Pulsing these bits loads the corresponding calibration DAC with the bits that have been clocked in by SCLK The following table shows the pulsing pattern MON emum Fonction Lv qo eoe Co E 7 A 777 Bor sd 13 FFRTEN FIFO Retransmit Enable Bit When FFRTEN is set the retransmit function of the FIFO is enabled The retransmit function resets the read pointer of the FIFO so the data that was previously read can be read again This function is useful when the data for DAC waveform generation does not exceed the FIFO s depth that is 1 024 12 8 DAC2S lt 8 0 gt DAC Input Data Format Select Bits When DAC2S0 is cleared a two s complement format is used for the 16 bit data written to DACO and DACI Th
49. by a gate input signal or to interrupt the clock input temporarily by an external circuit to ensure that the counter value is correctly read Counter latching In this method the counter value is latched by writing counter latch command thereby enabling a stable value to be read without effecting the counting in any way at all An example of a counter latching program is given below Counter latching executed for counter 1 Read Load 2 byte setting MVIA 0100xxxx Denotes counter latching OUT n3 Write in control word address n3 The counter value at this point is latched IN n1 Reading of the LSB of the counter value latched from counter 1 nt Counter 1 address MOVB A IN n1 MOV C_A Reading of MSB from counter 1 AT AO 6 10 User Manual C 12 Example of Practical Application e 82CS3 used as a 32 bit counter 82C53 2 Use counter 1 and counter 2 Counter 1 mode Q upper order 16 bit counter value Counter 2 mode 2 tower order 16 bit counter value This setting enables counting up to a maximum of 2 National Instruments Corporation Appendix D Customer Communication For your convenience this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation Filling out a copy of the Technical Support Form before contacting National Instruments helps us help you bett
50. chanical and electrical aspects of the AT AO 6 10 board and contains information concerning its operation and programming The AT AO 6 10 is a high performance analog output and digital I O board for the IBM PC AT and compatibles and EISA personal computers PCs The AT AO 6 10 refers to two versions of the board the six digital to analog converter DAC AT AO 6 and the ten DAC AT AO 10 It contains six ten 12 bit DACS with both voltage and current outputs and eight lines of transistor transistor logic TTL compatible digital I O Organization of This Manual The AT AO 6 10 User Manual is organized as follows e Chapter 1 Introduction describes the AT AO 6 10 lists the contents of your AT AO 6 10 kit the optional software and optional equipment and explains how to unpack the AT AO 6 10 kit e Chapter 2 Configuration and Installation describes the AT AO 6 10 jumper configuration installation of the AT AO 6 10 in the PC signal connections to the AT AO 6 10 and cable wiring Chapter 3 Theory of Operation contains a functional overview of the AT AO 6 10 and explains the operation of each functional unit making up the AT AO 6 10 e Chapter 4 Programming describes in detail the address and function of each of the AT AO 6 10 registers This chapter also includes important information about programming the AT AO 6 10 e Chapter 5 Calibration Procedures discusses the calibration procedures for the AT AO 6 10 analog output cir
51. ctor as well as the 5 VDC supply 50 5 V This pin is the 5 VDC source This pin is fused for up to 1 A of 5 V supply The signals on the connector can be classified as analog output signals digital I O signals digital power connections or update timing signals Signal connection guidelines for each of these groups are given in the following section Analog Output Signal Connections Pins 1 through 39 of the I O connector are analog output signal pins Pins 1 5 9 13 17 21 25 29 33 and 37 are the analog voltage output signal pins for analog output Channels 0 through 9 respectively Pins 2 6 10 14 18 22 26 30 34 and 38 are the analog current output signal pins for Channels 0 through 9 AT AO 6 10 User Manual 2 16 National Instruments Corporation Chapter 2 Configuration and Installation Pins 3 11 19 27 and 35 are the external reference inputs for analog output channels Each analog output channel must be configured individually for external reference selection so the signal applied at the external reference input is used by that channel Analog output configuration instructions are included under the Analog Output Configuration section earlier in this chapter The following ranges and ratings apply to the EXTREFX input Useful input voltage range 10 V peak with respect to RGND Absolute maximum ratings 25 V peak with respect to RGND Pins 4 12 20 28 and 36 are the ground reference points for the external
52. cuitry Power Rating 1 0 A at 5 V 10 fused Warning Under no circumstances should this 5 V power pin be connected directly to analog or digital ground or to any other voltage source on the AT AO 6 10 Doing so can damage the AT AO 6 10 and the PC National Instruments is not liable for damage resulting from such a connection National Instruments Corporation 2 19 AT AO 6 10 User Manual Configuration and Installation Chapter 2 Update Timing Signal The EXTUPDATE signal on pin 48 is a TTL compatible input signal for analog output channel updating This signal line is pulled up to 5 V on the board and is also connected to the RTSI switch The external device can drive this line low The high to low edge on this line triggers an internal active low pulse EXTUPD The high to low edge of EXTUPD initiates the update of the selected double buffered analog output channels and the rising edge of the EXTUPD signal can generate a DataWriteEnable signal or an interrupt request to write new data to the selected output channels Figure 2 8 shows the timing diagram of these signals EXTUPDATE Data Write Enable or Interrupt Request 20 nsec lt t lt tq 80 nsec max 50 nsec typical ta 50 nsec max 20 nsec typical tupa 500 nsec Figure 2 8 Update Timing Field Wiring Considerations Accuracy of signals generated by the AT AO 6 10 can be seriously affected by environmental noise when signal wires are run to
53. cuitry e Appendix A Specifications lists the specifications for the AT AO 6 10 e Appendix B O Connector shows the pinout and signal names for the AT AO 6 10 50 pin I O connector including a description of each connection e Appendix C MSM82C33 Data Sheet contains the MSM amp 2C53 Programmable Interval Timer Oki Semiconductor data sheet This counter timer is used on the AT AO 6 10 e Appendix D Customer Communication contains forms for you to complete to facilitate communication with National Instruments concerning our products The ndex alphabetically lists topics covered in this manual including the page where the topic can be found National Instruments Corporation ix AT AO 6 10 User Manual About This Manual Conventions Used in This Manual The following conventions are used in this manual italic Italic text denotes emphasis a cross reference or an introduction to a key concept NI DAQ NI DAQ is used throughout this manual to refer to the NI DAQ software for DOS Windows LabWindows unless otherwise noted PC PC refers to the IBM PC AT and compatibles and to EISA personal computers AT AO 6 10 AT AO 6 10 refers to the AT AO 6 and the AT AO 10 boards Related Documentation The following document contains information that you may find helpful as you read this manual e IBM Personal Computer AT Technical Reference manual You may also want to consult the following Oki Semiconductor manual if you plan t
54. der calibration and adjusts the value written to the corresponding 8 bit calibration DAC until the reading of the voltmeter is 0 volts Then the result is stored in the proper location of the EEPROM Gain error in the analog output circuitry is the sum of the gain errors contributed by each component in the circuitry This error also appears as a voltage difference between the desired voltage and the actual output voltage generated but it is proportional to the DAC output voltage To correct this gain error the routine writes a full scale positive value to the 12 bit DAC under calibration and adjusts the value written to the corresponding 8 bit calibration DAC until the reading of full scale voltage is reached on the voltmeter The result is stored in the EEPROM by the routine To perform the output calibration 1 Connect the voltmeter to the desired DAC output between the VOUT pin and AGND pin 2 Run the interactive calibration software Follow the software prompt until the operation is finished 3 Repeat steps 1 and 2 for each desired channel National Instruments Corporation 5 3 AT AO 6 10 User Manual Appendix A Specifications This appendix lists the specifications of the AT AO 6 10 These are typical at 25 C unless otherwise stated The operating temperature range is 0 to 70 C Analog Output Number of output channels Type of DAC Relative accuracy nonlinearity Differential nonlinearity Gain error Internal
55. digital lines BDIO lt 3 0 gt 3 0 ADO lt 3 0 gt These four bits control the digital lines ADIO lt 3 0 gt The bit DOUTEN in the CFG3 Register must be set for ADO lt 3 0 gt to be driven onto the digital lines ADIO lt 3 0 gt AT AO 6 10 User Manual 4 30 National Instruments Corporation Chapter 4 Programming Analog Output Register Group Ten of the twelve registers making up the Analog Output Register Group load the ten analog output channels DACO through DAC9 control analog output Channel 0 through Channel 9 respectively These registers can be written to individually or scanned automatically The analog output can be updated immediately or each time an update pulse is detected on either the EXTUPDATE line or on the output of one of the two onboard counters The update method is selected with the LDAC bit in the CFG2 Register The other two registers in this group are the FIFO WRITE Register and the FIFO CLEAR Register The FIFO WRITE Register is a write only register It can be written to by the programmed I O or by the DMA transfer The FIFO CLEAR Register is a read only register Reading this register clears the whole FIFO memory The result of the reading should be ignored Descriptions of the registers making up the Analog Output Register Group are given on the following pages National Instruments Corporation 4 31 AT AO 6 10 User Manual Programming Chapter 4 FIFO WRITE Register Writing to the FIFO WRITE Registe
56. e returned shows the current status of the I O connector When this bit is cleared bits O through 3 of the digital I O port are configured for input Reading an input port returns the current status of the I O connector 2 5 V Output Enable Bit When EN2 5V is set a 2 5V reference output is enabled on the IOUTO line If EN2 5V is cleared the IOUTO line is the current output of DAC Channel 9 To obtain the 2 5V output Channel 9 current output must be shut off To do this the Channel 9 must be configured in bipolar mode with two s complement format and a negative value 1000 decimal must be written to DACO DAC Channel Scan Mode Enable Bit When SCANEN is set DAC Channel 0 through Channel CH 3 0 are scanned sequentially In this mode the FIFO should be enabled A rising edge of an update signal starts a scan sequence Data from the FIFO is written to DAC Channel 0 through Channel CH lt 3 0 gt sequentially Then the next active low update signal updates the output of these channels and the rising edge of the update signal starts another scan sequence If the SCANEN is cleared and FIFO is enabled the data from the FIFO is written to channel CH lt 3 0 gt only 4 14 National Instruments Corporation Chapter 4 Programming INT2CLR Register Writing to the INT2CLR Register clears the interrupt request asserted either by a rising edge on the Counter 2 output or by a rising edge of the EXTUPD signal that is triggered by the
57. e signal write 0x34 to the CNTRCMD Register e write the scan cycle period low byte first then high byte in usec to the CNTR1 Register After writing the high byte the counter starts counting National Instruments Corporation 4 43 AT AO 6 10 User Manual Programming Chapter 4 Each time an update signal updates the channels output and causes an interrupt The interrupt handler should write the new value to each DAC To write a value to the DACO the GRP2WT bit in the CFG1 Register must be set Group 1 Scan Mode Using Retransmission Feature of FIFO If the total number of words to be written to the DACs for waveform generation is less than the size of the FIFO which 1s 1 024 words the retransmission feature of the FIFO can be used to improve the performance In this mode the data in the FIFO is written to the DACS repeatedly In other words when the last data in the FIFO is written out the writing pointer points to the beginning of the FIFO and the writing sequence continues Therefore the FIFO has to load only once before the process starts The Update signal works in the same way as other scan modes The programming steps are listed as follows 1 Write a pattern to the CFG1 Register The pattern should include e setting the FIFOEN bit a proper value in the CH lt 0 3 gt bit field to select channels to be scanned clearing the EXTUPDEN bit at this time 2 Write a pattern to the CFG2 Register The pattern should include
58. el The digital code in the preceding formula is a decimal value ranging from 2 048 to 2 047 National Instruments Corporation 4 37 AT AO 6 10 User Manual Programming Chapter 4 Table 4 4 Analog Output Voltage Versus Digital Code Bipolar Two s Complement Mode Digital Code Voltage Output mm ow 0 pee F 800 10V F 801 Vier 2 047 9 9951 V 2 048 F C00 Vref 5V 2 F FFF Vref 2 048 0 0 400 5V 0 7FF E 9 9951 V AT AO 6 10 User Manual 4 38 National Instruments Corporation Chapter 4 Programming Programming Considerations This section contains programming instructions for operating the circuitry on the AT AO 6 10 board Programming the AT AO 6 10 involves writing and reading from the various registers on the board The programming instructions list the sequence of steps to take The instructions are language independent that is they instruct you to write a value to a given register to set or clear a bit in a given register or to detect whether a given bit is set or cleared without presenting the actual code Register Programming Considerations Several write only registers on the AT AO 6 10 contain bits that control a number of independent pieces of the onboard circuitry In the instructions for setting or clearing these bits specific register bits should be set or cleared without changing the current state of the remaining bits in the register However writing to these registers affects
59. elect Bits Both bits must be one for the Read Back command to be used 5 COUNT Read Back Count Command If COUNT is cleared the current count in each of the selected counters is latched The next read from the selected counter returns the latched data 4 STATUS Read Back Status Command If STATUS is cleared the current status in each of the selected counters is latched The next read from the selected counter returns the latched data 3 1 CNTR lt 3 1 gt Counter Select Bits for Read Back Command These bits select the counters for the Read Back command that is if CNTR3 and CNTRI are set the Read Back command latches data for Counter 3 and Counter 1 0 0 Reserved Bit This bit must be set to zero for proper operation of the AT AO 6 10 National Instruments Corporation 4 23 AT AO 6 10 User Manual Programming Chapter 4 Status Byte If the STATUS bit is zero in the Read Back command status information for the selected counters is latched The status byte format is as follows 7 6 5 4 3 2 1 0 NULL MODE2 MODE MODEO Bit Name Description 7 OUT Counter Output The OUT bit reflects the current status of the counter output 6 NULL Last Count Written Status If NULL is zero the last count written to the selected counter has been loaded into the counter If NULL is set the last count written to the counter has not been loaded 5 4 RW 1 0 RWSEL1 and RWSELO Status The RW1 and RWO bits reflect the status
60. er and faster National Instruments provides comprehensive technical assistance around the world In the U S and Canada applications engineers are available Monday through Friday from 8 00 a m to 6 00 p m central time In other countries contact the nearest branch office You may fax questions to us at any time Corporate Headquarters 512 795 8248 Technical support fax 800 328 2203 512 794 5678 Branch Offices Phone Number Australia 03 879 9422 Austria 0662 435986 Belgium 02 757 00 20 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 00 Germany 089 741 31 30 Italy 02 48301892 Japan 03 3788 1921 Netherlands 03480 33466 Norway 32 848400 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 20 51 51 U K 0635 523545 National Instruments Corporation D 1 Fax Number 03 879 9179 0662 437010 19 02 757 03 11 45 76 71 11 90 502 2930 1 48 14 24 14 089 714 60 35 02 48301915 03 3788 1923 03480 30673 32 848600 91 640 0533 08 730 43 70 056 20 51 55 0635 523154 AT AO 6 10 User Manual Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Ins
61. g output auto calibration circuitry eight digital I O lines able to sink up to 24 mA of current timer generated and externally generated interrupts a high performance RTSI bus interface analog output auto initialization at startup and full PC I O channel DMA capability with analog output The AT AO 6 10 is designed for applications such as automation of machine and process control instrumentation and electronic test signal generation The analog voltage outputs can be used for functions such as 12 bit resolution voltage sourcing analog function generation and control signal output The 4 to 20 mA current outputs can be used in industrial control loops or any other application that benefits from the inherent noise immunity of two wire current loop communication The eight TTL compatible digital I O lines can be used for machine and process control intermachine communication and relay switching control The AT AO 6 10 is interfaced to the National Instruments RTSI bus With this bus National Instruments AT Series boards can send timing signals to each other The AT AO 6 10 can send signals from the onboard counter timer to another board or another board can send control signals to the AT AO 6 10 Detailed specifications for the AT AO 6 10 are listed in Appendix A Specifications What Your Kit Should Contain Each version of the AT AO 6 10 board has a different part number and kit part number listed as follows Kit Name Kit Part Number
62. hannel 2 ABC Analog Output Channel 3 ABC Analog Output Channel 4 ABC A B ABC National Instruments Corporation 2 13 AT AO 6 10 User Manual mew QW E Configuration and Installation Chapter 2 Notice that the straight binary format for data should be used when in unipolar output mode Hardware Installation The AT AO 6 10 can be installed in any available 16 bit expansion slot AT Series in your computer The AT AO 6 10 does not work if installed in an 8 bit expansion slot PC Series After you have made any necessary changes verified and recorded the switch and jumper settings a form is included for this purpose in Appendix D Customer Communication you are ready to install the AT AO 6 10 The following are general installation instructions but consult the user manual or technical reference manual of your PC for specific instructions and warnings 1 Turn off your computer Remove the top cover or access port to the I O channel Remove the expansion slot cover on the back panel of the computer Insert the AT AO 6 10 into a 16 bit slot Do not force the board into place Screw the mounting bracket of the AT AO 6 10 to the back panel rail of the computer Check the installation ud OQ A A QQ N Replace the cover The AT AO 6 10 board is installed and ready for operation Signal Connections This section describes input and output signal connections to the AT AO 6 10 board via the AT AO 6 10 I O connec
63. hannels 5 through 7 should be used because these channels are the only 16 bit channels If the board is used in an EISA computer all of the channels are 16 bit and can be used The AT AO 6 10 does not use and cannot be configured to use the 8 bit DMA channels on the PC I O channel Each DMA channel consists of two signal lines as shown in Table 2 4 Table 2 4 DMA Channels for the AT AO 6 10 DMA DMA DMA Channel Acknowledge Request EISA bus EISA bus EISA bus EISA bus EISA and AT bus EISA and AT bus EISA and AT bus Two jumpers must be installed to select a single DMA channel The DMA acknowledge and DMA request lines selected must have the same number suffix for proper operation Figure 2 3 shows the jumper positions for selecting DMA Channel 5 W22 W24 EISA or AT Bus EISA Only eE prof DACK lt DRQ Figure 2 3 DMA Jumper Settings for DMA Channel 5 Factory Setting AT AO 6 10 User Manual 2 6 National Instruments Corporation Chapter 2 Configuration and Installation The DMA channel circuitry can be programmed for high impedance state Interrupt Selection The AT AO 6 10 board can connect to any two of the eleven interrupt lines of the PC I O channel Each interrupt line is selected by a jumper with the triple rows of pins located above the I O slot edge connector on the AT AO 6 10 refer to Figure 2 1 To use the interrupt capability of the AT AO 6 10 select an interrupt
64. he pin Figure 4 1 shows the bit map of the RTSI switch 56 bit pattern National Instruments Corporation 4 47 AT AO 6 10 User Manual Programming Chapter 4 Bit Number 55 51 47 43 39 35 31 27 23 SEPT AO Control s js o Pa Bit Number 30 29 28 Figure 4 1 RTSI Switch Control Pattern In Figure 4 1 the fields labeled A6 through AO and B6 through BO are the 4 bit control fields for each RTSI switch pin of the same name The 4 bit control field for pin AO is shown in Figure 4 1 The bits labeled S2 through SO are the signal source selection bits for the pin One of seven source signals can be selected Pins A6 through AO can select any of the pins B6 through BO as signal sources Pins B6 through BO select any of the pins A6 through AO as signal sources For example the pattern 011 for S2 through SO in the A1 control field selects the signal connected to pin B3 as the signal source for pin Al The bit labeled OUTEN is the output enable bit for that pin If the OUTEN bit is set the pin is driven by the selected source signal the pin acts as an output pin If the OUTEN bit is cleared the pin is not driven regardless of the source signal selected instead the pin can be used as an input pin If the preceding A1 control field contains the pattern 0111 the signal connected to pin B3 Trigger Line 3 appears at pin Al On the AT AO 6 10 board this arrangement allows the GATE2 signal to be driven by Trigger Line 3 Conversely
65. hexadecimal hertz input output inches 1 000 samples least significant bit megabytes of memory parts per million root mean square Real Time System Integration signal conditioning eXtensions for instrumentation seconds transistor transistor logic volts volts output high volts output low reference voltage volts direct current National Instruments Corporation Glossary 1 AT AO 6 10 User Manual Index A abbreviations used in the manual vi acronyms used in the manual vii analog output calibration 5 3 circuitry 3 3 to 3 4 programming 4 40 to 4 46 application hints 4 46 configuration 2 8 jumper settings 2 8 external reference selection 2 10 internal reference selection 2 11 jumper settings 2 8 polarity selection 2 11 to 2 14 bipolar output selection 2 12 to 2 13 unipolar output selection 2 13 to 2 14 signal connections 2 16 to 2 17 specifications A 1 to A 2 voltage versus digital code bipolar straight binary mode 4 37 bipolar two s complement mode 4 39 unipolar mode 4 36 Analog Output Register Group 4 2 4 31 to 4 36 analog voltage output connections 2 17 AT bus interface 2 1 factory settings 2 1 AT AO 6 10 block diagram 3 1 configuration 2 1 to 2 8 contents of kit 1 1 to 1 2 introduction 1 1 to 1 3 optional equipment 1 3 optional software 1 2 to 1 3 registers 4 1 to 4 49 specifications A 1 to A 3 AWG vii B base I O address 2 5 selection 2 3 switch setting exa
66. ificant byte If status and count information are both latched the first read to this register returns the status byte and the next one read for 8 bit mode or two reads for 16 bit mode return the count bytes regardless of the order in which the information was latched AT AO 6 10 User Manual 4 20 National Instruments Corporation Chapter 4 Programming CNTRCMD Register The CNTRCMD Register contains eight bits that determine the counter selection counter size counting format and operation mode Address Base address 09 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 CNTRSEL1 CNTRSELO RWSEL1 RWSELO MODESEL2 MODESEL1 MODESELO BCDSEL Bit Name Description 7 6 CNTRSEL lt 1 0 gt Counter Select Bits These bits select the counter on which the command operates CNTRSELI CNTRSELO Select Counter 1 Select Counter 2 Select Counter 3 Read Back command 5 4 RWSEL lt 1 0 gt Read Write Select Bits These bits select data written to or read from a counter or these bits send a Counter Latch command asin wena Counter Latch command Read and write least significant byte only Read and write most significant byte only Read and write least significant byte then most significant byte National Instruments Corporation 4 21 AT AO 6 10 User Manual Programming Bit Name 3 1 MODESEL lt 2 0 gt 0 BCDSEL AT AO 6 10 User Manual Chapter 4 Description con
67. ifications A 1 to A 3 analog output A 1 to A 2 digital I O A 2 operating environment A 3 physical A 3 power requirements A 2 storage environment A 3 STATUS Register 4 8 to 4 9 storage environment A 3 National Instruments Corporation Index 5 AT AO 6 10 User Manual Index switch settings base I O address examples 2 4 corresponding base I O address and space 2 5 T TTL vii U unipolar output selection 2 13 to 2 14 unpacking AT AO 6 10 board 1 3 update timing signal 2 20 V VDC vii Von vi Vor vi voltage output 3 4 to 3 5 Vref vi AT AO 6 10 User Manual Index 6 National Instruments Corporation
68. ing DMA channel Read the FIFO Clear Register and ignore the result Set the DMARQ bit in the CFGI Register to enable the DMA transfer cl Je E xxx 3 Initialize the output channels by using Counter 1 to generate a single pulse to write the desired first data to the DACs Thus the next update pulse will dump the proper output to the channels To initialize the output channels you must do the following National Instruments Corporation 4 41 AT AO 6 10 User Manual Programming Chapter 4 write 0x18 to the CNTRCMD Register write 2 to the CNTRI Register 8 Wait for about 5 usec 9 Set or clear the EXTUPDEN bit in the CFGI Register to select the update source signal 10 If OUTI is selected as the update signal e write 0x34 to the CNTRCMD Register e write the scan cycle period low byte first then high byte in usec to the CNTRI Register After writing the high byte the counter starts counting The DMA transfer operation may terminate on terminal count You can also terminate it by clearing either the DMAEN bit or the DMARQ bit After the termination of the DMA transfer the remaining data in the FIFO is continually written to the DACSs until the FIFO is empty or the FIFOEN bit is cleared Group 1 Scan Mode Using Interrupt Three interrupts can be used with the Group 1 waveform generation operation the Counter 1 Interrupt the External Update Interrupt 1 and the FIFO Half Full Interrupt The FIFO Half Full Interrupt should
69. ingle bit to both the EEPROM and calibration DACs National Instruments Corporation 4 11 AT AO 6 10 User Manual Programming Chapter 4 INTICLR Register Writing to the INTICLR Register clears the interrupt request asserted either by a rising edge on the Counter 1 output or by a rising edge of the EXTUPD signal that is triggered by the falling edge of the EXTUPDATE line Address Base address 02 with the GRP2WR bit in the CFG1 Register set Type Write only Word Size 16 bit Bit Map Not applicable no bits used AT AO 6 10 User Manual 4 12 National Instruments Corporation Chapter 4 Programming CFG3 Register The CFG3 Register contains seven bits that control digital I O mode analog output channel scan mode and select the clock source on the RTSI bus Address Base address 04 hex with the GRP2WR bit in the CFG1 Register cleared Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 PEE o IT 0 T 0 0o 0o o ee 7 6 5 4 3 2 1 0 Lo DMAMODE CLKOUT RCLKEN DOUTEN2 DOUTEN Bit Name Description 15 7 0 Reserved Bits These bits are reserved for future use and should always be cleared 6 DMAMODE DMA Request Mode Select Bit When DMA is enabled if this bit is cleared the DMA request generated by the board is a continuously high signal until the FIFO is full If this bit is set the DMA request signal goes to low during the active low DMA acknowledge signal period In most PC sys
70. is enabled the contents of the DOUT Register are driven onto the digital lines corresponding to that port The digital output for both Port A and Port B is updated by writing the desired pattern to the DOUT Register For an external device to drive the digital I O lines the input ports must be enabled Clear the DOUTENI bit in the CFG3 Register if an external device is driving digital I O lines ADIO lt 3 0 gt Clear the DOUTEN2 bit in the CFG3 Register if an external device is driving digital lines BDIO lt 3 0 gt The DIN Register can then be read to monitor the state of the digital I O lines as driven by the external device The logic state of all eight digital I O lines can be read from the DIN Register If the digital output ports are enabled the DIN Register serves as a read back register that is you can determine how the AT AO 6 10 is driving the digital I O lines by reading the DIN Register If any digital I O line is not driven it floats to an indeterminate value If more than one device is driving any digital I O line the voltage at that line can also be indeterminate In these cases the digital line has no meaningful logic value and reading the DIN Register can return either 1 or 0 for the state of the digital line Upon start up both ports are enabled for input RTSI Bus Trigger Line Programming Considerations The RTSI switch connects signals on the AT AO 6 10 to the seven RTSI bus trigger lines The RTSI switch has seven pin
71. is format is useful for the bipolar analog output mode When DAC2S0 is set a straight binary format is used for the 16 bit data written to DACO and DACI This format is useful for the unipolar analog output mode Bit DAC2S2 controls the data format of DAC2 and DAC3 and in the same way bits DAC2S4 to DAC2S8 control the corresponding DACs AT AO 6 10 User Manual 4 10 National Instruments Corporation Chapter 4 Bit 7 3 Name LDAC lt 8 0 gt PROMEN SCLK SDATA Programming Description continued Double Buffered DAC Output Bits When LDACO is cleared DACO and DAC1 output are updated when they are written to If LDACO is set both DACO and DACI are updated when an active low pulse is detected on an update source line that is either an output line of a counter either counter 1 or 2 or the EXTUPDATE line The LDAC2 bit controls DAC2 and DAC3 and LDAC4 through LDACS control DAC4 through DACO respectively EEPROM Chip Enable Bit When PROMEN is set the onboard EEPROM used to store the calibration constant is enabled Before PROMEN is brought high SCLK should be pulsed high to initialize the EEPROM circuitry Serial Clock for EEPROM and Calibration DACs A low to high transition of this bit clocks data into the EEPROM when PROMEN is set and the calibration DACs If PROMEN is cleared togging SCLK does not affect the EEPROM Serial Data for EEPROM and Calibration DACs This bit is used to transfer a s
72. ith the GRP2WR bit in the CFG1 Register cleared Type Read only Word Size 16 bit Bit Map Not applicable no bits used National Instruments Corporation 4 33 AT AO 6 10 User Manual Programming Chapter 4 DACO through DAC Registers Writing to any of the DAC Registers loads the corresponding analog output channel DAC The voltages generated by the analog output channels are updated either immediately or when an update pulse is detected The update method is selected by the LDAC bit in the CFG2 Register These registers are further divided into two groups by 4 bits CH lt 3 0 gt of the CFGI Register The registers that have channels numbers higher than CH lt 3 0 gt make up DAC Group 2 The registers of DAC Group 2 are written by programmed I O individually and they are updated together if the corresponding LDAC bits are set upon the detecting of an update pulse The source of the update pulse for this group is either OUT2 or the EXTUPDATE signal The rest of the DAC registers make up DAC Group 1 The data written to the DAC Group 1 registers can be either from I O writing or from onboard FIFO directly depending on the status of the FIFOEN bit in the CFGI Register If the SCANEN bit of the CFG3 Register is set the DAC Group registers are scanned sequentially from DACO through DAC CH lt 3 0 gt The data written to these registers is from the FIFO the FIFOEN bit must be set Between two successive update pulses each DAC is written
73. itry generates the signals necessary to control and monitor the operation of the AT AO 6 10 multiple function circuitry The PC I O channel has 24 address lines the AT AO 6 10 uses 10 of these lines to decode the board address Therefore the board address range is 000 to 3FF hex SA5 through SA9 are used to generate the board enable signal SAO through SA4 are used to select onboard registers These address lines are latched by the address latches at the beginning of an I O transfer The latched address lines send the same address to the address decoding circuitry during the entire I O transfer cycle The address decoding circuitry generates the register select signals that identify which AT AO 6 10 register is being accessed The data buffers control the direction of data transfer on the bidirectional data lines based on whether the transfer is a read or write The PC I O channel interface timing signals are used to generate read and write signals and to define the transfer cycle A transfer cycle can be either an 8 bit or a 16 bit data I O operation The AT AO 6 10 returns signals to the PC I O channel to indicate when the board has been accessed when the board is ready for another transfer and the data bit size of the current I O transfer The interrupt control circuitry routes any enabled interrupt requests to the selected interrupt request line The AT AO 6 10 board can share the interrupt line with other devices because the interrupt requests a
74. lectronic Products Division 3M part number 3365 50 T amp B Ansley Corporation part number 171 50 National Instruments Corporation 2 21 AT AO 6 10 User Manual Chapter 3 Theory of Operation This chapter contains a functional overview of the AT AO 6 10 and explains the operation of each functional unit making up the AT AO 6 10 Functional Overview The block diagram in Figure 3 1 is a functional overview of the AT AO 6 10 board RTSI BUS RTSI Bus To Update Interface Generator 0 VOUT4 VOUT2 E AT vO e VOUTO CHANNEL INTERFACE Double Buffered e IOUTO Dual AGNDO e VOUTI D A Converter e IOUT I O Connector DMA Interface AGND 1 e REF REF GND PC I O Channel Interrupt Interface DIGITAL I O 82C53 DIGITAL I O MUX CTRO UPDATE GENERATOR MUX EXT UPD CTR 1 CTR2 To RTSI Bus Interface Figure 3 1 AT AO 6 10 Block Diagram National Instruments Corporation 3 1 AT AO 6 10 User Manual Theory of Operation Chapter 3 The following are the major components making up the AT AO 6
75. line and place the jumper in the appropriate position to enable that particular interrupt line The jumper on the upper two rows of interrupt line 11 selects the interrupt level for Group 1 of the analog output channel and the jumper on the lower two rows of interrupt line 12 selects the interrupt level for Group 2 of the analog output channel The AT AO 6 10 can share interrupt lines with other devices Unless the appropriate interrupt modes have been enabled on the AT AO 6 10 through software the interrupt line is by default in the high impedance state at startup The interrupt lines supported by the AT AO 6 10 hardware are IRQ3 IRQ4 IRQS IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 and IRQIS Note Do not use interrupt line 6 or 14 Interrupt line 6 is used by the diskette drive controller and interrupt line 14 is used by the hard disk controller on most PCs Once you have selected an interrupt level place the interrupt jumper on the appropriate pins to enable the interrupt line The interrupt jumper set is W23 The default interrupt lines are IRQ11 for Group 1 and IRQI2 for Group 2 These interrupt lines are selected by placing one jumper on the upper pins in row 11 and the other jumper on the lower pins in row 12 Figure 2 4 shows the default interrupt jumper settings IRQ11 and IRQ12 To change to other lines remove the jumpers from IRQ11 and IRQ12 and place them on the new pins IRQ 15 14 1211 109 7 6 5 4 3 for Group 1 for Grou
76. mer Communication sess D 1 GIOSSAEY oen tutatus bates e e ose atat Glossary 1 MUNN estne UA ec MM LM ROOM MC EA Ce Index 1 National Instruments Corporation vii AT AO 6 10 User Manual Contents Figures Figure 2 1 AT AO 6 10 Parts Locator Diagram eene 2 2 Figure 2 2 Example Base I O Address Switch Settings esses 2 4 Figure 2 3 DMA Jumper Settings for DMA Channel 5 Factory Setting 2 6 Figure 2 4 Interrupt Jumper Setting IRQ11 and IRQ12 Factory Setting 2 7 Figure 2 5 AT AO 6 10 VO Comet uscar aid 2 15 Figure 2 6 Analog Voltage Output Connections esee enne 2 17 Figure 2 7 Digital l O Connecnons ss uu eeu ei A ta PN SU ada 2 19 Figure 2 8 Update TIO eee quedan enata dece De odi audi eal edn ae 2 20 Figure 3 1 AT AO 6 I0 Block Dt gr m 2 uccatet cede aetna dee eens 3 1 Figure 3 2 PC I O Channel Interface Circuitry Block Diagram sees 3 2 Figure 3 3 Analog Output Circuitry Block Diagram eee 3 4 Figure 3 4 Output Sink Current Versus Output Voltage seen 3 6 Figure 3 5 Possible Current Loop Connection seen 3 6 Figure 3 6 Digital VO Circuitry Block Diagram eene 3 8 Figure 3 7 RTSI Bus Interface Circuitry Block Diagram eene 3 9 Figure 4 1 RTSI Switch Control Patte
77. mples 2 4 bipolar output selection 2 12 to 2 13 board configuration 2 1 to 2 8 National Instruments Corporation Index 1 AT AO 6 10 User Manual Index C cabling 2 21 calibration analog output 5 3 DACs 5 2 to 5 3 EEPROM map 5 2 reference 5 3 CFGI Register 4 5 to 4 7 CFG2 Register 4 10 to 4 11 CFG3 Register 4 13 to 4 14 CMOS vii CNTRI Register 4 18 CNTR2 Register 4 19 CNTR3 Register 4 20 CNTRCMD Register 4 21 to 4 25 configuration analog output 2 8 of AT AO 6 10 2 1 to 2 8 Configuration and Status Register Group 4 1 4 4 to 4 17 contents of AT AO 6 10 kit 1 1 to 1 2 current loop connection 3 6 current output 3 5 to 3 7 D D A vii DAC vii calibration 5 2 to 5 3 registers 3 7 to 3 8 calibrating 3 7 to 3 8 loading 3 7 updating 3 7 DACO through DAC registers 4 34 to 4 36 default settings 2 3 digital I O circuitry 3 8 to 3 9 programming 4 46 signal connections 2 18 to 2 19 specifications A 2 Digital I O Register Group 4 1 4 28 to 4 31 DIN Register 4 29 DIP vii DMA vii channels 2 6 selection 2 6 jumper settings for DMA channel 5 2 6 DMATCCLR Register 4 16 DOUT Register 4 30 AT AO 6 10 User Manual Index 2 National Instruments Corporation E EEPROM map 5 2 EISA vii environment operating A 3 storage A 3 external reference 2 9 to 2 11 selection 2 10 F field wiring 2 20 to 2 21 FIFO vii FIFO CLEAR Register 4 33 FIFO WRITE Register 4 3
78. n is shifted into the RTSI switch internal 56 bit control register The data in the control register routes information for switching signals to and from the RTSI bus trigger lines The RSI bit must be written to 56 times to shift the 56 bits of routing data into the internal control register See Programming the RTSI Switch later in this chapter for more information AT AO 6 10 User Manual 4 26 National Instruments Corporation Chapter 4 Programming RTSISTRB Register Writing to the RTSISTRB Register loads the contents of the RTSI Shift Register into the RTSI Switch Control Register thereby updating the RTSI switch routing pattern The RTSISTRB Register is written to after shifting the 56 bit routing pattern into the RTSISHFT Register Address Base address 07 hex with the GRP2WR bit set Type Write only Word Size 8 bit Bit Map Not applicable no bits used National Instruments Corporation 4 27 AT AO 6 10 User Manual Programming Chapter 4 Digital I O Register Group The two registers making up the Digital I O Register Group monitor and control the AT AO 6 10 digital I O lines The DIN Register returns the digital state of the eight digital I O lines A pattern written to the DOUT Register is driven onto the digital I O lines when the digital output drivers are enabled see the description for the CFG3 Register Bit descriptions for the registers making up the Digital I O Register Group are given on the following
79. n sss ieissa nsss i in ai re s i Ea SISESE X Chapter 1 BABOL OTE AKON i oe as rst meatu cule E a SE em 1 1 What Your Kit Should Contain occcccnnnnnnnicccncnnononinanicnaccnnnonononanenacccnccnononananacociconononanens 1 1 O eade tela un UL Le E e 1 2 Optional Equipment ii A AE a e tei ote es ene ides 1 3 MAG Sir t NP 1 3 Chapter 2 Configuration and Installation 1 eese 2 1 B rd Configuration spss M 2 1 AT Bus Intetface ee aUe IERI 2 1 Base l O Address Selection tet ette teet er E eter egere petes 2 3 DMA Channel Selection eite esl eie ee ere ceteri teret ere creed ris 2 6 Interrupt Selection enine ntes ble ea sip tums evt ene aeu PY udo ode TRIS VOD Eel iR DR IUS 2 7 Analog Output Configuration oe enit ttn da Un Sn eee Rea qe T Po eeu eL Unas an Peas bes 2 8 Internal and External Reference occccccccccnnnncnononononononononononononononononononininananess 2 9 External Reference SelectiOM cocccccccccccncnnnncononinononinononinonononononininaness 2 10 Internal Reference Selection Factory Setting sss 2 11 Analog Output Polarity Selection oooonnncccnnncccnnncccnoncnonnncnonnncnononaconnncnonnnaninnnos 2 11 Bipolar Output Selection Factory Setting coooococnnocccconcccnoncconananonnnos 2 12 Unipolar Output Selection i iei tert ertet eee en segeanssasgeaccesoadenetane 2 13 Hardware Install ati Onn eet tecti eerte tene tte emer eem et ete tr e
80. n update signal is received The following sections describe how to program the analog output circuitry for waveform generation using the update signal Analog Output Channel Group The analog output channels on the AT AO 6 10 can be programmed into two groups Writing a channel number n to the CH lt 0 3 gt bit field of the CFG1 Register selects Channels 0 through n to include in Group 1 The rest of the channels make up Group 2 Different update sources can be used for Group 1 and Group 2 Select Update Source Signal for a Group The available update sources for Group 1 are Counter 1 output OUT1 and EXTUPDATE AT AO 6 10 User Manual 4 40 National Instruments Corporation Chapter 4 Programming e Writing one to the EXTUPDEN bit of the CFG1 Register selects the EXTUPDATE signal as the update source for Group 1 e Writing zero to the EXTUPDEN bit of the CFG1 Register selects the OUT1 signal as the update source for Group 1 The update sources for Group 2 are Counter 2 output OUT2 and EXTUPDATE e Writing one to the EXTINT2EN bit of the CFGI Register selects the EXTUPDATE signal as the update source for Group 2 Writing one to the CNTINT2EN bit of the CFGI Register selects the OUT2 signal as the update source for Group 2 The EXTINT2EN bit and the CNTINT2EN bit should not be set at the same time Group 1 Scan Mode Using DMA In waveform generation operations using DMA transfers Group 1 always uses onboard FIFO memor
81. nal factory setting W10 B C Unipolar W12 B C Bipolar factory setting W12 A B continues AT AO 6 10 User Manual 2 8 National Instruments Corporation Chapter 2 Configuration and Installation Table 2 5 Analog Output Jumper Settings continued Output Channel Configuration Jumper Settings Reference Internal factory setting W13 B C Unipolar W15 A B Bipolar factory setting W15 B C Reference Internal factory setting W14 B C Unipolar W16 B C Bipolar factory setting W16 A B Reference Internal factory setting W17 B C Unipolar W19 A B Bipolar factory setting W19 B C Reference Internal factory setting W18 B C Channel 9 External W18 A B Unipolar W20 B C Bipolar factory setting W20 A B Internal and External Reference Each DAC can be connected to the AT AO 6 10 internal reference of 10 V or to the external reference signal connected to the EXTREFX pin on the I O connector This signal applied to EXTREFX must be between 10 V and 10 V Each EXTREFX signal is shared by two DACs that are in the same chip that is DACO and DACI share EXTREFO DAC2 and DAC3 share EXTREF etc Both channels need not be configured the same way National Instruments Corporation 2 9 AT AO 6 10 User Manual Configuration and Installation Chapter 2 External Reference Selection You select the external reference signal for each analog output channel by setting the following jumpers as shown in Table 2 6
82. nces are stable with respect to time and temperature The 5 V and 10 V references do not need to be calibrated and they are not available on the I O connector The 2 5 V reference is available on pin 38 when the 2 5 V OUT bit of the CFG3 Register is set It is seldom necessary to calibrate the 2 5 V reference Every one or two years should be sufficient To calibrate the 2 5 V reference signal 1 If you have an AT AO 10 ensure that channel 9 is in the bipolar mode 2 Connect the positive probe of the voltmeter to the 2 5 V output on the connector pin 38 Connect the negative probe of the voltmeter to the corresponding analog ground pin pin 39 3 Run the interactive calibration software for 2 5 V reference calibration Follow the software prompt until the finishing of the calibration Analog Output Calibration To null out error sources that affect the accuracy of the output voltages generated the output calibration routine calibrates the analog output circuitry by adjusting the following potential sources of error e Analog output offset error e Analog output gain error Offset error in the analog output circuitry is the total of the voltage offsets contributed by each component in the circuitry This error which is independent of the DAC output voltage appears as a voltage difference between the desired voltage and the actual output voltage generated To correct this offset error the routine writes a value of 0 to the 12 bit DAC un
83. o program the MSM82C53 Counter Timer used on the AT AO 6 10 Oki 82C53 Programmable Interval Timer technical manual Customer Communication National Instruments want to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix D Customer Communication at the end of this manual AT AO 6 10 User Manual x National Instruments Corporation Chapter 1 Introduction This chapter describes the AT AO 6 10 lists the contents of your AT AO 6 10 kit the optional software and optional equipment and explains how to unpack the AT AO 6 10 kit The AT AO 6 10 is a high performance analog output and digital I O board for the PC There are two versions of the AT AO 6 10 a version with six analog output channels and a version with ten analog output channels In this manual the descriptions of analog output Channels 6 through 9 apply to the AT AO 10 only The AT AO 6 10 has six ten double buffered multiplying 12 bit DACs unipolar and bipolar voltage output 4 to 20 mA current output an onboard DAC reference voltage of 10 V internal timer and external signal update capability for waveform generation an onboard 1 024 word FIFO buffer transfer rates up to 200 ksamples sec per channel onboard analo
84. of the RWSEL1 and RWSELO bits of the selected counter 3 1 MODE lt 2 0 gt MODE2 MODEI and MODEO Status The MODE2 MODEI and MODEO bits reflect the state of the MODESEL2 MODESEL1 and MODESELO bits of the selected counter 0 BCD Binary Coded Decimal Select BCDSEL Status The BCD bit reflects the status of the BCDSEL bit of the selected counter Refer to Appendix C MSM82C53 Data Sheet for more information on programming the counters AT AO 6 10 User Manual 4 24 National Instruments Corporation Chapter 4 Programming RTSI Bus Register Group The two registers making up the RTSI Bus Register Group program the AT AO 6 10 RTSI switch for routing of signals on the RTSI bus trigger lines to and from several AT AO 6 10 signal lines Bit descriptions of the two registers making up the RTSI Bus Register Group are given on the following pages National Instruments Corporation 4 25 AT AO 6 10 User Manual Programming Chapter 4 RTSISHFT Register The RTSISHFT Register contains one bit RSI that is a serial input to the RTSI switch RSI must be written to 56 times to load the internal 56 bit RTSI control register Address Base address 06 hex with the GRP2WR bit set Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 Bit Name Description 7 1 X Don t care bits 0 RSI RTSI Switch Serial Input This bit is the serial input to the RTSI switch Each time the RSI bit is written to the value writte
85. on 4 49 AT AO 6 10 User Manual Chapter 5 Calibration Procedures This chapter discusses the calibration procedures for the AT AO 6 10 analog output circuitry The AT AO 6 10 is calibrated at the factory before shipment An onboard EEPROM stores the calibration constants which must be written to the 21 calibration DACs on the AT AO 10 or 13 calibration DACs on the AT AO 6 to be properly calibrated To maintain the 12 bit accuracy of the AT AO 6 10 analog output circuitry periodic self calibration is recommended This self calibration is performed under software control Calibration constants are stored in an onboard EEPROM see Figure 5 1 Calibration software is included with the board package as part of the utility application and utility library Using the self calibration feature eliminates most errors due to drift of offset and gain with time and temperature National Instruments Corporation 5 1 AT AO 6 10 User Manual Calibration Procedures Chapter 5 Reserved Channel 9 Gain Factor y Channel 9 Offset Channel 8 Gain Channel 8 Offset User 4 Channel 7 Gain Channel 7 Offset Channel 6 Gain User 3 2 Channel 6 Offset 2 5 V Offset Channel 5 Gain User 2 Channel 5 Offset Channel 4 Gain Channel 4 Offset User 1 Channel 3 Gain Channel 3 Offset decimal Channel 2 Gain Channel 2 Offset Channel 1 Gain Channel 1 Offset Channel 0 Gain Channel 0 Offset Figure 5 1 EEPROM Map Factory calibration is valid with
86. or two reads for 16 bit mode returns the count bytes regardless of the order in which the information was latched National Instruments Corporation 4 19 AT AO 6 10 User Manual Programming Chapter 4 CNTR3 Register The CNTR3 Register contains eight bits that are used to load a value into Counter 3 or to read back the value of Counter 3 The CNTR3 Register can be used as an 8 bit register or as a 16 bit register by two successive write read operations Address Base address 08 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 CNTR3B7 CNTR3B6 CNTR3B5 CNTR3B4 CNTR3B3 CNTR3B2 CNTR3B1 CNTR3BO Bit Name Description 7 0 CNTR3B lt 7 0 gt Counter 3 Load Read Bits Writing a data value to these bits loads the starting value into Counter 3 Reading these bits returns the current count of Counter 3 or latched data for Counter 3 If the Counter Latch command or the Read Back command is used to latch the count or status of Counter 3 reading these bits returns the latched information The latched data remains latched until it is read If multiple Latch commands or Read Back commands are issued before the latched data is read only the data from the first Status Latch command and the first Counter Latch command are latched all commands after the first are ignored If 16 bit data is latched the first read from this register returns the least significant byte and the second read returns the most sign
87. ore the GATE3 signal can be used not only to control Counter 3 but also Counters 1 and 2 With these onboard interconnections the DACs update timing can be controlled over the RTSI bus as well as externally and the AT AO 6 10 can send timing signals to other AT boards connected to the RTSI bus AT AO 6 10 User Manual 3 10 National Instruments Corporation Chapter 4 Programming This chapter describes in detail the address and function of each of the AT AO 6 10 registers This chapter also includes important information about programming the AT AO 6 10 Note If you plan to use a programming software package such as NI DAQ DOS Windows or LabWindows with your AT AO 6 10 board you need not read this chapter Register Map The register map for the AT AO 6 10 is shown in Table 4 1 This table gives the register name the register address offset from the slot base address the register type read only write only or read and write and the size of the register in bits Some registers share the same address with others The GRP2WR bit in the CFG1 Register determines which registers are being accessed at the shared address If the GRP2WR bit is set the registers in the parentheses are accessed If GRP2WR is cleared the other registers are accessed Table 4 1 AT AO 6 10 Register Map Register Name Offset Address Size Type Hex Configuration and Status Register Group CFGI Register Write only Status Register Read only CFG2 Register
88. our code NI DAQ comes with language interfaces for Professional BASIC Turbo Pascal Turbo C Turbo C Borland C and Microsoft C for DOS and Visual Basic Turbo Pascal Microsoft C with SDK and Borland C for Windows NI DAQ software is on high density 5 25 in and 3 5 in diskettes Optional Software This manual contains complete instructions for directly programming the AT AO 6 10 Normally however you should not need to read the low level programming details in the user manual because the NI DAQ software package for controlling the AT AO 6 10 is included with the board Using NI DAQ is quicker and easier than and as flexible as using the low level programming described in Chapter 4 Programming You can use the AT AO 6 10 with LabVIEW for Windows or LabWindows for DOS LabVIEW and LabWindows are innovative program development software packages for data acquisition and control applications LabVIEW uses graphical programming whereas LabWindows enhances Microsoft C and QuickBASIC Both packages include extensive libraries for data acquisition instrument control data analysis and graphical data presentation AT AO 6 10 User Manual 1 2 National Instruments Corporation Chapter 1 Introduction Part numbers for these software packages are listed in the following table LabVIEW for Windows 776670 01 LabWindows for DOS Standard package 776473 01 Advanced Analysis Library 776474 01 Standard package with the Advanced Analysis Lib
89. owed by a detailed bit description of each register The individual register description gives the address type word size and bit map of the register followed by a description of each bit The register bit map shows a diagram of the register with the MSB bit 15 for a 16 bit register bit 7 for an 8 bit register shown on the left and the LSB bit 0 shown on the right A square is used to represent each bit Each bit is labeled with a name inside this square An asterisk after the bit name indicates that the bit is inverted negative logic In many of the registers one or more bits are labeled with an X indicating don t care bits When a register is read these bits may appear set or cleared but should be ignored because they have no significance When a register is written to setting or clearing these bit locations has no effect on the AT AO 6 10 hardware National Instruments Corporation 4 3 AT AO 6 10 User Manual Programming Chapter 4 Configuration and Status Register Group The seven registers making up the Configuration and Status Register Group can be used for general monitoring and control of the AT AO 6 10 hardware The three configuration registers CFG1 CFG2 and CFG3 control the DAC output modes DAC calibration interrupt and DMA operations All the bits of these three configuration registers are cleared upon startup The other three configuration registers INTICLR INT2CLR and DMATCCLR clear various interrupt s
90. p 2 W23 Figure 2 4 Interrupt Jumper Setting IRQ11 and IRQ12 Factory Setting Interrupts for both groups can be enabled or disabled via control bits on the AT AO 6 10 These control bits are described in the programming configuration registers See Chapter 4 Programming for more information National Instruments Corporation 2 7 AT AO 6 10 User Manual Configuration and Installation Chapter 2 Analog Output Configuration The AT AO 6 10 is shipped from the factory with the following configuration 10 V analog output range with internal reference selected You can select different analog output configurations by using the jumper settings shown in Table 2 5 Table 2 5 lists all the available analog output configuration jumpers and notes the factory settings The following paragraphs describe each of the analog output configurations in detail Table 2 5 Analog Output Jumper Settings Output Channel Configuration Jumper Settings Reference Internal factory setting W B C Unipolar W3 A B Bipolar factory setting W3 B C Reference Internal factory setting W2 B C Unipolar W4 B C Bipolar factory setting W4 A B Reference Internal factory setting WS B C Unipolar W7 A B Bipolar factory setting W7 B C Reference Internal factory setting W6 B C Unipolar W8 B C Bipolar factory setting W8 A B Reference Internal factory setting W9 B C Unipolar Wil A B Bipolar factory setting Wil B C Reference Inter
91. ption continued 2 6 10 14 IOUTO through IOUT9 These pins are the analog current outputs of Channel 18 22 26 0 through Channel 9 The IOUT9 signal is 30 34 38 programmable and can be either analog current output from Channel 9 or the 2 5 V onboard reference signal In the reference calibration mode this pin is used to monitor the internal 2 5 Vef 3 11 19 EXTREFO through These pins are the analog external reference inputs 27 35 EXTREF8 for Channel 0 through Channel 9 Each external reference input signal is shared by two channels Channel 0 and Channel 1 share EXTREFO Channel 2 and Channel 3 shares EXTREF2 etc 4 12 20 RGNDO through RGND8 These pins are the analog external reference ground 28 36 pins Each of these five ground pins is the ground reference to the corresponding EXTREFX signal 7 8 15 16 AGNDO through AGND8 These pins are the analog output ground pins for 23 24 31 each channel Channel 8 and Channel 9 share one 32 39 ground pin AGNDS 40 41 42 ADIOO through ADIO3 These pins are the digital I O Port A signals 43 44 45 46 BDIOO through BDIO3 These pins are the digital I O Port B signals 47 48 EXTUPDATE This pin is the external DAC Update If selected a high to low edge on EXTUPDATE results in the selected outputs of DACs being updated with the value written to them 49 DGND This pin is the digital ground This pin supplies the reference for the digital signals at the I O conne
92. put within the specified range of 7 to 40 V is important If the voltage is too low the AT AO 6 10 cannot sink the full 20 mA If the voltage is too high overheating can occur and the board can be damaged Figure 3 5 shows a possible current loop connection Current Output P gt N 250 Q Load Floating Analog Ground AT AO 6 10 Back Panel Connector Figure 3 5 Possible Current Loop Connection AT AO 6 10 User Manual 3 6 National Instruments Corporation Chapter 3 Theory of Operation The combination of power supply voltage and load impedance used in Figure 3 5 keeps the voltage at the connector between 19 V 20 mA and 23 V 4 mA The voltage at the connector is always as follows Moon Mass E Tout Ry where Vo 15 the voltage at the connector in volts e V 1s the external power supply voltage in volts e is the output sink current in mA R isthe resistance of the load in KQ Loading Updating and Calibrating the DACs There are three ways to load a new value to a DAC register 1 Write a value to the DAC register directly by the software 2 Use the onboard 1 024 word deep FIFO as a data buffer between the host computer and the DACs The software or the DMA transfer data to the FIFO and concurrently the data from the FIFO is loaded to the desired DACS upon detecting the update signals The transfer cycle between FIFO and DAC is 500 nsec 3 Use the FIFO retransmit feature to repeatedly load dat
93. r e Clock Frequency e Type of Video Board Installed DOS Version e Programming Language e Programming Language Version e Other Boards in System e Base I O Address of Other Boards DMA Channels of Other Boards e Interrupt Level of Other Boards Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title AT AO 6 10 Manual Edition Date September 1994 Part Number 320379 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address Phone Mail to Technical Publications Fax to Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway MS 53 02 MS 53 02 Austin TX 78730 5039 512 794 5678 Glossary mem Meaning Vae hex Hz IO in ksamples LSB M ppm rms RTSI SCXI sec Vou degrees ohms percent amperes American Wire Gauge Celsius complementary metallic oxide semiconductor digital to analog digital to analog converter dual inline package direct memory access Extended Industry Standard Architecture farads first in first out Full Scale Range
94. r loads a 16 bit value to the FIFO memory Address Base address OC hex with the GRP2WR bit in CFG1 Register cleared Type Write only Word Size 16 bit Bit Map 15 14 13 12 11 10 9 8 lo SigmExtensionBits Du DIO D9 D8 7 6 5 4 3 2 1 0 D w ps Ds ps j bz Di Do Bit Name Description 15 12 Sign Bits Sign Extension Bits If the two s complement format of analog output is selected these bits are sign extension bits equal to D11 If the straight binary format is selected these bits are zero 11 0 D lt 11 0 gt Data Bits The 12 bit data ranges from 0 to 4095 decimal 0000 to OFFF hex if straight binary format is selected or from 2048 to 2047 decimal F800 to 07FF hex if two s complement format is selected The data written to this register is loaded into the 1 024 word deep FIFO memory This register can be accessed by either program I O or by DMA transfer The data stored in the FIFO memory can only be loaded to DAC Group 1 When the FIFO memory is full the data written to the FIFO WRITE Register is lost The status of the FIFO can be obtained by reading the STATUS Register With DMA transfers when the FIFO is full the DMA request is automatically masked to stop the writing to this register AT AO 6 10 User Manual 4 32 National Instruments Corporation Chapter 4 Programming FIFO CLEAR Register Reading the FIFO CLEAR Register clears the entire FIFO memory Address Base address OC w
95. rary 776475 01 Optional Equipment Equipment Part Number CB 50 I O connector block 50 screw terminals with 0 5 m type NB1 cable 776164 01 with 1 0 m type NB1 cable 776164 02 AT Series RTSI bus cables for 2 boards 776249 02 3 boards 776249 03 4 boards 776249 04 5 boards 116249 05 Unpacking Your AT AO 6 10 board is shipped packaged in an antistatic package to prevent electrostatic damage to the board Several components on the board can be damaged by electrostatic discharge To avoid such damage in handling the board take the following precautions e Touch the antistatic package to a metal part of your PC chassis before removing the board from the pacakge e Remove the board from the package and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any way Do not install a damaged board into your computer National Instruments Corporation 1 3 AT AO 6 10 User Manual Chapter 2 Configuration and Installation This chapter describes the AT AO 6 10 jumper configuration installation of the AT AO 6 10 in the PC signal connections to the AT AO 6 10 and cable wiring Board Configuration The AT AO 6 10 contains 24 jumpers only 16 are used on the AT AO 6 version and one DIP switch Jumpers W22 W23 and W24 on the AT AO 6 10 select the DMA channel and the interrupt level Jumpers W1 through W13 on the AT AO 6 and Jumpers W1 through W20 on the
96. re dependent FIFO to output channel s 1 6 Mwords sec maximum Each channel can drive 5 mA current maximum But the total output power consumption is 200 mW Thus if all 10 channel outputs are 10 V the maximum current output is 2 mA per channel Explanation of Analog Output Specifications Relative accuracy in a D A system is the same as nonlinearity because no uncertainty is added due to code width Unlike an ADC every digital code in a D A system represents a specific analog value rather than a range of values The relative accuracy of the system is therefore limited to the worst case deviation from the ideal correspondence a straight line excepting noise If a D A system has been calibrated perfectly then the relative accuracy specification reflects its worst case absolute error Differential nonlinearity in a D A system is a measure of deviation of code width from 1 LSB In this case code width is the difference between the analog values produced by consecutive digital codes A specification of 1 LSB differential nonlinearity ensures that the code width is always greater than O LSB guaranteeing monotonicity and is always less than 2 LSBs Digital I O Compatibility TTL compatible Output current source capability Can source 2 6 mA and maintain V og at 2 4 V Output current sink capability Can sink 24 mA and maintain Voy at 0 5 V Power Requirements from PC AT I O Channel AT AO 6 5 VDC 0 6 A typical 12 VDC 60 mA typical
97. re edens 2 14 Signal Connections seite ene EY GV ETRAS riales 2 14 Signal Connection DescEIDEIOTIS scidit a Pe chee shades Ve Man es eoo visage De 2 15 Analog Output Signal CONNECTIONS ooooconccccnoncccnoncnonnncnononcnononanononanonnncnonnneninnnos 2 16 Digital l O SigtialC Onnee lH OBS oae uic aves tede edt jaca ip as 2 18 Power Connectlorns4 sebum ee I ee N A NEA a ete 2 19 Update Timing SMA rota 2 20 Field Wiring Considerations eni laicas dt dnde o NEN E DES PA ELLA ee Ya SESS a ences 2 20 Cabling CONSENSO lacoste 2 21 Chapter 3 Theory of Operation cusses sca panes ees ees eee uae ennt 3 1 Functional OVetVIeW o ccce coco ld da tdi aci 3 1 PC I O Channel Interface Circuitry uis cosas esequi neca codec ined trad s rH Ee Ne pe aces 3 2 Analog Output CIPCUIEFPY deti oce tede Shee a eae eod idest itii Dedi tn 3 3 OMA CMU ee ES 3 4 Current OUtDUL odo ode Positano A ii 3 5 Loading Updating and Calibrating the DACS sse 3 7 Disttal VO Cretti dcm 3 8 RESLBus nterface CECI Wy ue oon pi edens rete ua ai we Ma reU qas 3 9 National Instruments Corporation v AT AO 6 10 User Manual Contents Chapter 4 A ots pea qaad mortel ctn ette 4 1 RGslster M sees eise scade Rh d bp eM m 4 Registet SIZES ee A AA A R TE TA 4 2 Register Descrip Orosco ice pipas 4 2 Register Deseription Format 4 3 Configuration and Status Register Group seen 4 4 CPGI REGIS CR nt A a 4 5 STATUS RES letales 4 8 CEG
98. re tri state output signals Eleven interrupt request lines are available for use by the AT AO 6 10 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQIO IRQ11 IRQ12 IRQ14 and IRQ15 Interrupts can be generated by the AT AO 6 10 in the following three situations When the D A FIFO is half full e When a DMA terminal count pulse is received When a falling edge signal is detected on either the internal or the external DAC update signal Each one of these interrupts is individually enabled and cleared See Chapter 4 Programming for more information about programming with interrupts The DMA control circuitry generates DMA requests whenever the D A FIFO is not full and the DMA transfer is enabled The DMA circuitry supports full PC I O channel and EISA bus 16 bit DMA transfers DMA Channels 5 6 and 7 of the PC I O channel and Channels 0 1 2 and 3 of the EISA bus are available for such transfers Analog Output Circuitry The AT AO 6 and AT AO 10 have six and ten channels of 12 bit D A output respectively Unipolar or bipolar output voltage or current output and internal or external reference voltage selections are available with each analog output channel Figure 3 3 shows a block diagram of the analog output circuitry National Instruments Corporation 3 3 AT AO 6 10 User Manual Theory of Operation Chapter 3 REF Selection EXTREF 5 V INT REF x2 O L EXTREF lt 0 8 gt Channel 0 Counters 1 2 anne and 3 FIFO AGN
99. reference includes adjustment range Temperature coefficient External reference Temperature coefficient Voltage offset includes adjustment range Voltage Output Ranges Current drive Output impedance Capacitive drive Protection Settling time to 0 5 LSB 20 V step 10 V step V step Slew rate Noise Current Output Type Output resistance Excitation voltage Accuracy National Instruments Corporation 6 for the AT AO 6 10 for the AT AO 10 12 bit multiplying 0 01596 of FSR maximum 1 5 mV Unipolar 3 mV Bipolar 0 006 of FSR typical 6 mV Unipolar 1 2 mV Bipolar 1 LSB maximum monotonic over temperature 0 2 LSB typical 1 0 adjustable to lt 0 005 10 ppm C 0 1 not adjustable 5 ppm C 100 mV bipolar mode adjustable to lt 0 5 mV 50 mV unipolar mode adjustable to 0 3 mV 0 to 10 V 10 V O to Vref Vref 5 mA each Voyt maximum 0 1 maximum 500 pF maximum Short circuit to ground 10 usec 5 usec 4 usec 20 V usec minimum mV rms DC to 1 MHz 4 to 20 mA sink to ground 1 GQ minimum 7 to 40 VDC at connector pins 0 1 FSR A 1 AT AO 6 10 User Manual Specifications Appendix A Slew rate 7 5 mA usec Protection Short circuit and open circuit External reference input impedance 11 KQ unipolar mode 7 KQ bipolar mode for each output channel Transfer rate System memory to onboard FIFO 300 kwords to 500 kwords sec maximum system and softwa
100. rns uei ied iea dux iet Pipe ee 4 48 Figure 5 1 EEPROM MIS cede A eene dodi et E aie uds 5 2 Figure Bal AT AO 6 10 UO Connector tesi di eats B 1 Tables Table 2 1 AT Bus Interface Factory Sets ocior IT I ance fp siepe tre PRU te een e eius 2 1 Table 2 2 Default Settings of National Instruments Products for the PC 2 3 Table 2 3 Switch Settings with Corresponding Base I O Address and Base DO Address SPACES esse eu o ER 2 5 Table 2 4 DMA Channels for the AT AO 6 10 sese 2 6 Table 2 5 Analog Output Jumper Settings mi 2 8 Table 2 6 External Reference Selection ii he Ser deti aede ee 2 10 Table 2 7 Internal Reference Selection sener de o tee ceu dq a 2 11 Table 2 8 Bipolar Output Selection orien mech eoe nO o rios 2 12 Table 2 9 Unipolar Output Selectloni ou etnies dote edes ftit nae ene 2 13 Table 4 1 AT A0 0 10 Resister NM ap aseo A RUE e dpa e edt 4 1 Table 4 2 Analog Output Voltage Versus Digital Code Unipolar Mode 4 36 Table 4 3 Analog Output Voltage Versus Digital Code Bipolar Str sht Binaty Mo inca sce dre teo e RU AER de eR NETS 4 37 Table 4 4 Analog Output Voltage Versus Digital Code Bipolar Two s Complement Model tio vert re ipee EM a 4 38 Table 4 5 RTSI Switch Signal C nnections oe toes o sop oes ot thor dyn aden fee SP EDRU i HE 4 47 AT AO 6 10 User Manual Viii National Instruments Corporation About This Manual This manual describes the me
101. ruments Corporation Appendix C MSMS2C53 Data Sheet This appendix contains the M M82C53 Programmable Interval Timer Oki Semiconductor data sheet This counter timer is used on the AT AO 6 10 Copyright O Oki Semiconductor 1990 Reprinted with permission of copyright owner All rights reserved Oki Semiconductor Microprocessor Data Book 1990 1991 O National Instruments Corporation C 1 AT AO 6 10 User Manual MSM82C53 Data Sheet Appendix C OKI semiconductor MSM82C53 2RS GSUS CMOS PROGRAMMABLE INTERVAL TIMER GENERAL DESCRIPTION The MSM82C53 2RS GS JS are programmable universal timers designed for use in microcomputer syste ms Based on silicon gate CMOS technology it requires a standby current of only 100A max when the chip is in the nonselected state During timer operation power consumption is still very low with only 8 mA max at 8 MHz of current required The devices consist of three independent counters and can count up to a maximum of 8 MHz MSM82C53 2 The timer features six different counter modes and binary count BCD count functions Count values can be set in byte or word units and all functions are freely programmable FEATURES e Maximum operating frequency of 8 MHz MSMB2C53 2 e Six counter modes available for each counter High speed and low power consumption achieved e Binary and decimal counting possible through silicon gate CMOS technology 24 pin Plastic DIP DIP24 P 600 Completely
102. s at H level counting is started by the next clock after the count value has been written And if the gate input is at L level counting is started by using the rising edge of the gate input as a trigger after the count value has been set An L level output pulse appears at the counter output during a single clock duration once every n clock inputs where n is the set count value If a new count value is written during while counting is in progress counting is started at the new count value following output of the pulse currently being counted And if the gate input is switched to L level during counting the counter output is forced to switch to H level the counting being restarted by the rising edge of the gate input e Mode 3 square waveform rate generstor The counter output is switched to H level by the mode setting Counting is started in the same way as described for mode 2 above The repeated square wave output appearing at the counter output contains half the number of counts as the set count value If the set count value n is an odd number the repeated square wave output consists of only n 1 2 clock inputs at H level and n 1 2 clock inputs at L level H a new count value is written during counting the new count value is reflected immediately after the 311 C 9 AT AO 6 10 User Manual MSM82C53 Data Sheet Appendix C a O MSM82C53 2RS GS JS m 312 AT
103. s labeled A lt 6 0 gt connected to the AT AO 6 10 signals and seven pins labeled B lt 6 0 gt connected to the seven RTSI bus trigger lines Table 4 8 shows the signals connected to each pin AT AO 6 10 User Manual 4 46 National Instruments Corporation Chapter 4 Programming Table 4 5 RTSI Switch Signal Connections RTSI Switch Pin Signal Name Signal Direction Connection on the RTSI Bus OUTI Output GATE3 Input N C EXTUPD Output OUT3 Output OUT2 Output EXTUPDATE Bidirectional TRIGGERO Bidirectional TRIGGERI Bidirectional TRIGGER2 Bidirectional TRIGGER3 Bidirectional TRIGGER4 Bidirectional TRIGGER5 Bidirectional TRIGGER6 Bidirectional Programming the RTSI Switch The RTSI switch can be programmed to connect any of the signals on the A side to any of the signals on the B side and vice versa To make this connection a 56 bit pattern is shifted into the RTSI switch by writing one bit at a time to the RTSI Switch Shift Register and then writing to the RTSI Switch Strobe Register to load the pattern into the RTSI switch The 56 bit pattern is made up of two 28 bit patterns one for side A and one for side B of the RTSI switch The low order 28 bits select the signal sources for the B side pins The high order 28 bits select the signal sources for the A side pins Each of the 28 bit patterns are made up of seven 4 bit fields one for each pin The 4 bit field selects the signal source and the output enable for t
104. se bits return a value of 1 but should be ignored because they have no significance 6 FH FIFO Half Full Flag Bit The FH bit is active low when the net balance of the words written into the FIFO exceeds the number of words read out by 512 or more 5 FE FIFO Empty Flag Bit The high state of FE indicates the FIFO is ready to output data The low state indicates the FIFO is empty 4 FF FIFO Full Flag Bit The high state of FF indicates the FIFO is ready to input data The low state of FF indicates the FIFO is full 3 INT2 Interrupt 2 Status Bit This bit reflects the status of interrupt 2 It is set by either the rising edge of Counter 2 output with the CNTINT2EN bit set or the rising edge of the internal EXTUPD signal with the EXTINT2EN bit set It is cleared by writing to the INT2CLR Register 2 INT1 Interrupt 1 Status Bit This bit reflects the status of interrupt 1 It is set by either the rising edge of Counter 1 output with the CNTINTIEN bit set or the rising edge of the internal EXTUPD signal with the EXTINTIEN bit set It is cleared by writing to the INTICLR Register AT AO 6 10 User Manual 4 8 National Instruments Corporation Chapter 4 Programming Bit Name Description continued 1 TCINT DMA TC Interrupt or Half Full Interrupt Status Bit This bit reflects the status of the DMA TC or Half Full Interrupt It is set by either the DMA TC signal with the DMAEN bit set or the active low FH signal with DMAEN cle
105. sed as an 8 bit register or as a 16 bit register by two successive write read operations Address Base address 06 hex with the GRP2WR bit cleared Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 CNTRIB7 CNTRIB6 CNTRIB5 CNTRIB4 CNTRIB3 CNTRIB2 CNTRIBI CNTRIBO Bit Name Description 7 0 CNTRIB lt 7 0 gt Counter 1 Load Read Bits Writing a data value to these bits loads the starting value into Counter 1 Reading these bits returns the current count of Counter 1 or latched data for Counter 1 If the Counter Latch command or the Read Back command is used to latch the count or status of Counter 1 reading these bits returns the latched information The latched data remains latched until it is read If multiple Latch commands or Read Back commands are issued before the latched data is read only the data from the first Status Latch command and the first Counter Latch command are latched all commands after the first are ignored If 16 bit data is latched the first read from this register returns the least significant byte and the second read returns the most significant byte If status and count information are both latched the first read from this register returns the status byte and the next one read for 8 bit mode or two reads for 16 bit mode returns the count bytes regardless of the order in which the information was latched AT AO 6 10 User Manual 4 18 National Instruments Corporation Ch
106. select input Read input Input Data can be transferred from MSM82C53 to CPU when this pin is at low level Write input Address input Clock input m cen Input output Three state 8 bit bidirectional data bus used when writing control words and count values and reading count values upon reception of WR and RD signals from CPU Data transfer with the CPU is enabled when this pin is at low level When at high level the data bus Do thru D is Switched to high impedance state where neither writing nor reading can be executed Internal registers however remain unchanged Input Data can be transferred from CPU to MSMB2C53 when this pin is at low level Input One of the three internal counters or the control word regis ter is selected by AO A1 combination These two pins are normally connected to the two lower order bits of the address bus Input Supply of three clock signals to the three counters incorpo rated in MSM82C53 Control of starting interruption and restarting of counting in the three respective counters in accordance to the set con trol word contents ADDRESS BUS 16 bits CONTROL BUS DATA BUS EU D7 0 R Q Al AQ cs 82053 2 COUNTER 0 COUNTER 1 COUNTER 2 OUT GATE CLK OUTGATE CLK OUT GATE CLK 309 AT AO 6 10 User Manual MSM82C53 Data Sheet Appendix C a 1 O MSM82C53 2RS GS JS amp _ __ _ ____
107. t in the CFG1 Register depending on the update source signal selected 5 Program the system interrupt controller and enable the proper interrupt level 6 If OUT2 is selected as the update signal write 0x74 to the CNTRCMD Register e write the scan cycle period low byte first then high byte in usec to the CNTR2 Register After writing the high byte the counter starts counting Each time an update signal updates the channel output and causes an interrupt The interrupt handler should write the new value to each DAC National Instruments Corporation 4 45 AT AO 6 10 User Manual Programming Chapter 4 Application Hints If you want to use the external DAC update pin to generate an interrupt without updating the DACs clear the EXTUPDEN bit in the CFG1 Register and set EXTINTIEN bit in the CFG1 Register Now a falling edge at the EXTUPDATE line will not update the DACs in Group 1 but an active low output signal from Counter 1 will This interrupt procedure is possible only with Group 1 Programming the Digital I O Circuitry The digital I O circuitry is controlled and monitored using the DIN Register the DOUT Register and the two bits DOUTENI and DOUTEN2 in CFG3 Register See the register bit descriptions earlier in this chapter for more information To enable digital output Port A set the DOUTENI bit in the CFG3 Register To enable digital output Port B set the DOUTEN2 bit in the CFG3 Register When a digital output port
108. tatus bits The Status Register reflects the DMA interrupt and FIFO status Bit descriptions of the seven registers making up the Configuration and Status Register Group are given on the following pages AT AO 6 10 User Manual 4 4 National Instruments Corporation Chapter 4 Programming CFG1 Register The CFG1 Register contains 16 bits that control the analog output channel selection DMA and interrupt operations Address Base address OA hex Type Write only Word Size 16 bit Bit Map 15 14 12 11 EXTINT2EN EXTINTIEN CNTINT2EN CNTINTIEN TCINTEN Gris ao 7 6 5 4 3 2 1 0 GRP2WR EXTUPDEN DMARQ DMAEN CH3 CH2 CHI CHO Bit Name Description 15 EXTINT2EN External Interrupt 2 Enable Bit When EXTINT2EN is set a high to low transition on the EXTUPDATE line triggers an active low pulse EXTUPD The rising edge of the EXTUPD pulse generates an interrupt 2 request The interrupt 2 request is cleared by writing to the INT2CLR Register When this bit is set the EXTUPD pulse also becomes the update signal for Group 2 of the DACS that have channel numbers higher than CH lt 3 0 gt 14 EXTINT1EN External Interrupt 1 Enable Bit When EXTINTIEN is set a high to low transition on the EXTUPDATE line triggers an active low pulse EXTUPD The rising edge of the EXTUPD pulse generates an interrupt 1 request The interrupt 1 request is cleared by writing to the INTICLR Register 13 CNTINT2EN Co
109. tems it does not make any difference when using single data DMA transfer mode 9 CLKOUT Onboard Clock Output Enable Bit Tf this bit is set the onboard 10 MHz clock is enabled to output to the RTSI bus When this bit is set the RCKLEN bit must be cleared If this bit is cleared the onboard clock cannot be sent to the RTSI bus 4 RCKLEN RTSI Bus Clock Enable Bit When the RCKLEN bit is set a clock signal from the RTSI bus is enabled to replace the onboard 10 MHz clock When the RCKLEN bit is cleared the clock from the RTSI bus is disabled 3 DOUTEN2 Digital Output Enable 2 Bit When this bit is set the high nibble bits 4 through 7 of the 8 bit digital port is enabled for output Data written to an output port is driven to the I O connector An output port can be read back and the value returned shows the current status of the I O connector When this bit is cleared bits 4 through 7 of the digital I O port are configured for input Reading an input port returns the current status of the I O connector National Instruments Corporation 4 13 AT AO 6 10 User Manual Programming Bit Name 2 DOUTEN1 1 EN2 5V 0 SCANEN AT AO 6 10 User Manual Chapter 4 Description continued Digital Output Enable 1 Bit When this bit is set the low nibble bits 0 through 3 of the 8 bit digital port is enabled for output Data written to an output port is driven to the I O connector An output port can be read back and the valu
110. ter e write the scan cycle period low byte first then high byte in usec to the CNTRI Register After writing the high byte the counter starts counting Whenever a half space or more is free in the FIFO an interrupt is generated The interrupt handler should write 512 words to the FIFO if there is data to be written Each update pulse updates the DACs output and loads the new value to each DAC The minimum update cycle must be longer or equal to 0 5 usec the number of channels in Group 1 If the FIFO is not used either the Counter 1 Interrupt or the External Update Interrupt can be used depending on which update source is selected The program steps are listed as follows 1 Write a pattern to the CFG1 Register The pattern should include e a proper value in the CH lt 0 3 gt bit field to select channels to be written clearing or setting the EXTUPDEN bit to select the desired update source 2 Write a pattern to the CFG2 Register The pattern should include e setting the corresponding LDACx bits for the channels to be scanned e setting or clearing corresponding DAC2Sx bits for straight binary or two s complement format 3 Setthe SCANEN bit in the CFG3 Register 4 Write the first data to the DACs 5 Set the CNTINTIEN or the EXTUPDEN bit in the CFGI Register depending on the update source signal selected 6 Program the system interrupt controller and enable proper interrupt level 7 If OUTI is selected as the updat
111. ter 2 Source Select Bit If CNT2SRC is cleared a 1 MHz clock is used as the counting source for Counter 2 If CNT2SRC is set the output of Counter 3 is used as the counting source for Counter 2 FIFO Memory Enable Bit If FIFOEN is set the FIFO memory is enabled Thus the data written to the analog output channel or channels which form DAC Group 1 and are selected by bits CH lt 3 0 gt are transferred through the FIFO When the DMA transfer is used this bit must be set because all DMA transfers are through the FIFO Register Group Select Bit Some onboard registers share the same I O addresses The following table shows which registers are accessed for each bit setting Bit Setting Registers Accessed GRP2WR 0 CFG2 CFG3 Digital I O Counter 1 Counter 2 FIFO WRITE FIFO CLEAR GRP2WR 1 INTICLR INT2CLR DMATCCLR RTSISHFT RTSISTRB DACO DAC Group 1 Update Source Select Bit If EXTUPDEN is set internal active low pulse EXTUPD which is triggered by the falling edge of the EXTUPDATE line is the update source signal for DAC Group 1 If EXTUPDEN is cleared the active low output of Counter 1 is the update source signal for DAC Group 1 4 6 National Instruments Corporation Chapter 4 Bit Name 5 DMARQ 4 DMAEN 3 0 CH lt 3 0 gt Programming Description continued DMA Request Bit If DMARQ and DMAEN are set a DMA request is asserted The DMA request can be cleared either by clearing this bit
112. tializing the board 4 39 to 4 40 register programming 4 39 RTSI bus trigger line 4 47 switch 4 48 to 4 49 R reference calibration 5 3 register map 4 1 to 4 2 register programming 4 39 AT AO 6 10 User Manual Index 4 National Instruments Corporation Index register sizes 4 2 registers 4 1 to 4 49 Analog Output Register Group 4 2 4 31 to 4 36 DACO through DAC registers 4 34 to 4 36 FIFO CLEAR Register 4 33 FIFO WRITE Register 4 32 Configuration and Status Register Group 4 1 4 4 to 4 17 CFGI Register 4 5 to 4 7 STATUS Register 4 8 to 4 9 Configuration and Status Registers CFG2 Register 4 10 to 4 11 CFG3 Register 4 13 to 4 14 DMATCCLR Register 4 16 INTICLR Register 4 12 INT2CLR Register 4 15 Digital I O Register Group 4 1 4 28 to 4 31 DIN Register 4 29 DOUT Register 4 30 MSM82C53 Counter Timer Register Group 4 1 4 17 to 4 25 CNTRI Register 4 18 CNTR2 Register 4 19 CNTR3 Register 4 20 CNTRCMD Register 4 21 to 4 25 RTSI Bus Register Group 4 1 4 25 to 4 28 RTSISHFT Register 4 26 RTSISTRB Register 4 27 rms vi RTSL vii bus interface circuitry 3 9 to 3 10 bus trigger line programming 4 47 switch programming 4 48 to 4 49 RTSI Bus Register Group 4 1 4 25 to 4 28 RTSISHFT Register 4 26 RTSISTRB Register 4 27 S signal connections 2 14 to 2 20 B 2 analog output 2 16 to 2 17 descriptions 2 16 digital I O 2 18 to 2 19 power connections 2 19 update timing signal 2 20 spec
113. tinued The Counter Latch command latches the current count of the register selected by CNTRSEL1 and CNTRSELO The next read from the selected counter returns the latched data Counter Mode Select Bits These bits select the counting mode of the selected counter The following table lists six available modes and the corresponding bit settings Refer to Appendix C MSM62C53 Data Sheet for additional information MODESEL2 MODESEL1 MODESELO Mode 0 Interrupt on Terminal Count Mode 1 Hardware Retriggerable One Shot Mode 2 Rate 1 Generator 1 1 Mode 4 Software Retriggerable Strobe 1 Mode 5 Hardware Retriggerable Strobe EMES 1 Mode 3 Square Wave Mode Miike Binary Coded Decimal Select Bit If BCDSEL is set the selected counter keeps count in BCD If BCDSEL is cleared the selected counter keeps count in 16 bit binary 4 22 National Instruments Corporation Chapter 4 Programming Read Back Command When bits 7 and 6 CNTRSEL1 and CNTRSELO are 1 the CNTRCMD Register can be used to execute the Read Back command With the Read Back command the current totals of multiple counters can be latched in one command The Read Back command also can latch the status of selected counters The control word format used for the Read Back command is as follows 7 6 5 4 3 2 1 0 CNTRSELI CNTRSELO COUNT STATUS CNTR3 CNTR2 CNTRI 0 Bit Name Description 7 6 CNTRSEL lt 1 0 gt Counter S
114. tion Descriptions Pin Signal Name 1 5 9 13 VOUTO through VOUT9 17 21 25 29 33 37 2 6 10 14 IOUTO through IOUT9t 18 22 26 30 34 38 3 11 19 EXTREFO through 27 35 EXTREF8 4 12 20 RGNDO through 28 36 RGND8 amp 7 8 15 16 AGNDO through 23 24 31 AGND8 Description Analog voltage outputs of Channel 0 through Channel 9 Analog current outputs of Channel 0 through Channel 9 Analog external reference inputs for Channel 0 through Channel 9 Each external reference input signal is shared by two channels Channel 0 and Channel 1 share EXTREFO Channel 2 and Channel 3 share EXTREF2 etc Analog external reference ground Each of these five ground pins is the ground reference to the corresponding EXTREFx signal where x refers to 0 through 8 Analog output ground for each channel Channel 8 and Channel 9 share one ground pin AGNDS Digital I O Port A signals Digital I O Port B signals External DAC Update If selected a high to low edge on EXTUPDATE results in the selected outputs of DACS being updated with the value written to them Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 32 39 40 41 42 ADIOO through 43 ADIO3 44 47 BDIOO through BDIO3 48 EXTUPDATE 49 DGND 50 5 V AT AO 6 10 User Manual 5 VDC supply 5 VDC Source This pin is fused for up to 1 A of 5 V supply B 2 National Inst
115. tional Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this manual is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED T
116. to H level When Count Values are written during counting the operation is as follows National Instruments Corporation 1 byte Read Load When the new count value is written counting is stopped immediately and then restarted at the new count value by the next clock 2 byte Read Load When byte 1 LSB of the new count value is written counting is stopped immediately Counting is restarted at the new count value when byte 2 MSB is written e Mode 1 programmabie one shot The counter output is switched to H level by the mode setting Note that in this mode counting is not started if only the count value is written Since counting has to be started in this mode by using the leading edge of the gate input as a trigger the counter output is switched to L level by the next clock after the gate input trigger This L level status is maintained during the set count value and is switched back to H level when the terminal count is reached Once counting has been started there is no inter ruption until the terminal count is reached even if the gate input is switched to L level in the mean time And although counting continues even if a new count value is written during the counting Counting is started at the new count value if another trigger is applied by the gate input e Mode 2 rate generator The counter output is switched to H level by the mode setting When the gate input i
117. tor and includes specifications and connection instructions for the signals given on the AT AO 6 10 I O connector Warning Connections that exceed any of the maximum ratings of input or output signals on the AT AO 6 10 can result in damage to the AT AO 6 10 board and to the PC Maximum input ratings for each signal are given in this chapter under the discussion of that signal National Instruments is not liable for any damages resulting from such signal connections Figure 2 5 shows the pin assignments for the AT AO 6 10 I O connector AT AO 6 10 User Manual 2 14 National Instruments Corporation Chapter 2 Configuration and Installation VOUTO IOUTO EXTREFO RGNDO VOUTI IOUTI AGNDO AGNDI VOUT2 IOUT2 EXTREF2 RGND2 VOUT3 IOUT3 AGND2 AGND3 VOUT4 IOUT4 EXTREF4 RGND4 VOUTS IOUTS AGND4 AGNDS VOUT6 IOUT6 EXTREF6 RGND6 VOUT7 IOUT7 AGND6 AGND7 VOUTS IOUT8 EXTREF8 RGND8 VOUT9 IOUTOT AGNDS ADIOO ADIOI ADIO2 ADIO3 BDIO4 BDIOS BDIO6 BDIO7 EXTUPDATE DGND 5 V TIOUTO is used as the internal reference voltage 2 5 V output in the reference calibration mode Figure 2 5 AT AO 6 10 I O Connector Signal Connection Descriptions Pin Signal Name Description 1 5 9 13 VOUTO through VOUT9 These pins are the analog voltage outputs of Channel 17 21 25 0 through Channel 9 29 33 37 National Instruments Corporation 2 15 AT AO 6 10 User Manual Configuration and Installation Chapter 2 Pin Signal Name Descri
118. truments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessary Name Company Address Fax ___ Phone ___ Computer brand Model Processor Operating system Speed MHz RAM M Display adapter Mouse yes no Other adapters installed Hard disk capacity M Brand Instruments used National Instruments hardware product model Revision Configuration National Instruments software product Version Configuration The problem is List any error messages The following steps will reproduce the problem AT AO 6 10 Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently National Instruments Products e AT AO 6 10 Revision e Base I O Address of AT AO 6 10 Factory Setting Hex 0220 e DMA Channels of AT AO 6 10 Factory Setting 6 and 7 e Interrupt Level of AT AO 6 10 Factory Setting 10 e NI DAQ or LabWindows Version Other Products e Computer Make and Model e Microprocesso
119. unter Interrupt 2 Enable Bit When CNTINT2EN is set the rising edge of OUT2 of Counter 2 generates an interrupt 2 request The interrupt 2 request is cleared by writing to the INT2CLR Register When this bit is set the active low OUT2 pulse also becomes the update signal for Group 2 of the DACs that have channel numbers higher than CH lt 3 0 gt 12 CNTINT1EN Counter Interrupt 1 Enable Bit When CNTINTIEN is set the rising edge of OUT1 of Counter 1 generates an interrupt 1 request The interrupt 1 request is cleared by writing to the INTICLR Register National Instruments Corporation 4 5 AT AO 6 10 User Manual Programming Bit Name 11 TCINTEN 10 CNTISRC 9 CNT2SRC 8 FIFOEN 7 GRP2WR 6 EXTUPDEN AT AO 6 10 User Manual Chapter 4 Description continued DMA TC Interrupt or FIFO Half Full Interrupt Enable Bit When TCINTEN and DMAEN are set the DMA terminal count TC signal generates an interrupt 1 request If TCINTEN is set and DMAEN is cleared the rising edge of the half full signal HF generated from the FIFO causes an interrupt 1 request FH is low when there are 512 or more words remaining in the FIFO and FH is high otherwise Both interrupt requests are cleared by writing to the TCINTCLR Register Counter 1 Source Select Bit If CNTISRC is cleared a 1 MHz clock is used as the counting source for Counter 1 If CNT1SRC is set the output of Counter 3 is used as the counting source for Counter 1 Coun
120. urce Signal for a Group 4 40 Group 1 Scan Mode Using DMA eee 4 4 Group 1 Scan Mode Using Interrupt eese 4 42 Group 1 Scan Mode Using Retransmission Feature of FIFO 4 44 Group 1 Single Channel Mode Using DMA or Interrupt 4 45 Group 2 Using Interrupt acces Bates aa 4 45 Application FUNES uico cosciente id cs 4 46 Programming the Digital I O Circuitry eene 4 46 RTSI Bus Trigger Line Programming Considerations eee 4 46 Programming the RTSI SwItCBi ei sides i Seca ewe Bese ee 4 47 AT AO 6 10 User Manual vi National Instruments Corporation Contents Chapter 5 Calibration Procedures reete reed deine rds Pee HU tnb ode 5 1 Calibtatiom DAC Sc ove Sasso A mts diete addas ede eee Leod Der d 5 2 Reference Calibration etas aded ves eq last t sse LUE d M C 5 3 Analog Output CaliBratlOni naaa idos 5 3 Appendix A Specifications coactos no d LA A 1 O A 1 Explanation of Analog Output Specifications essere A 2 A O O A A 2 Power Requirements from PC I O Channel eese A 2 PHVSICAL O A 3 Operating Environments eoi ped potete dali Vercisbo dent latest ae ie rida Oii us utes A 3 Storage ONO NEHME A 3 Appendix B VO Comme ads B 1 Signal Connection DES Crip ONS noia obs B 2 Appendix C NSMS2 53 Data Sheet RSS qui ftem qan C 1 Appendix D Custo
121. y as a data buffer The FIFO is 1 024 words deep The data is read from the system memory to the FIFO by DMA operation Then the data is written to the Group 1 DACs In the scan mode after detecting the update pulse each channel in Group 1 is written once sequentially from Channel 0 to Channel n The next update pulse updates the output of the channels and initializes another writing cycle Each writing of a channel lasts 500 nsec Therefore a scan cycle or update interval must last longer than 500 nsec number of channels in Group 1 The DMA continuously transfers data to the FIFO unless the FIFO is full In addition data is continuously written to the DACS unless the FIFO is empty These two operations are independent and concurrent To set up this mode use the following programing steps 1 Write a pattern to the CFG1 Register The pattern should include e setting the following bits FIFOEN DMAEN and TCINTEN if DMA TC interrupt is desired e a proper value in the CH lt 0 3 gt bit field to select channels to be scanned clearing the EXTUPDEN bit at this time 2 Wirite a pattern to the CFG2 Register The pattern should include e setting the corresponding LDACx bits for the channels to be scanned setting or clearing corresponding DAC2Sx bits where x refers to 0 through 8 for selecting straight binary or two s complement format Set the SCANEN bit in the CFG3 Register Program the system DMA controller enable the correspond
122. y used by other equipment installed in your computer If any equipment in your computer uses this base I O address space change the base I O address of the AT AO 6 10 or of the other device If you change the AT AO 6 10 base I O address make a corresponding change to any software packages you use with the AT AO 6 10 Table 2 2 lists the default settings of other National Instruments products for the PC For more information about the I O address of your PC refer to the technical reference manual for your computer Table 2 2 Default Settings of National Instruments Products for the PC DMA Channel Interrupt Level Base I O Address AT A2150 None None 120 hex AT AO 6 10 Channel 5 Line 11 12 1C0 hex AT DIO 32F Channels 5 6 Lines 11 12 240 hex AT DSP2200 None None 120 hex AT GPIB Channel 5 Line 11 2C0 hex AT MIO 16 Channels 6 7 Line 10 220 hex AT MIO 16D Channels 6 7 Line 10 220 hex AT MIO 16F 5 Channels 6 7 Line 10 220 hex AT MIO 16X None None 220 hex AT MIO 64F 5 None None 220 hex GPIB PCII Channel 1 Line 7 2B8 hex GPIB PCIIA Channel 1 Line 7 02E1 hex GPIB PCIII Channel 1 Line 7 280 hex Lab PC Channel 3 Line 5 260 hex Lab PC Channel 3 Line 5 260 hex PC DIO 24 None Line 5 210 hex PC DIO 96 None Line 5 180 hex PC LPM 16 None Line 5 260 hex PC TIO 10 None Line 5 1A0 hex These settings are software configurable and are disabled at startup time National Instruments Corporation 2 3 AT AO 6 10 User Manual Configuration

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