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LPC1311/13/42/43

1. Sor U C LPC1311 13 42 43 32 bit ARM Cortex M3 microcontroller up to 32 kB flash and 8 kB SRAM USB Device Rev 00 14 20 August 2009 Preliminary data sheet 1 General description 2 Features The LPC1311 13 42 43 are ARM Cortex M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption The ARM Cortex M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration The LPC1311 13 42 43 operate at CPU frequencies of up to 72 MHz The ARM Cortex M3 CPU incorporates a 3 stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals The ARM Cortex M3 CPU also includes an internal prefetch unit that supports speculative branching The peripheral complement of the LPC1311 13 42 43 includes up to 32 kB of flash memory up to 8 kB of data memory USB Device LPC1342 43 only one Fast mode Plus I2C bus interface one UART four general purpose timers and up to 42 general purpose I O pins m ARM Cortex M3 processor running at frequencies of up to 72 MHz m ARM Cortex M3 built in Nested Vectored Interrupt Controller NVIC W 32kB LPC1343 13 16 kB LPC1342 8 kB LPC1311 on chip flash programming memory m 8kB LPC1343 13 4 kB LPC1342 11 SRAM m In System Programming ISP and In
2. 2 PIO2 0 DTR RESET PIOO 0 PIOO 1 CLKOUT CT32B0 MAT2 XTALIN XTALOUT VpD IO PIO1 8 CT16B1 CAPO 7 PIO0_2 SSEL CT16B0_CAPO GT Gol G Q8 C7 Cs LPC1311FHN33 LPC1313FHN33 33 Vss 10 10 AE C5 TRST PIO1 2 AD3 CT32B1 MAT1 TDO PIO1 1 AD2 CT32B1 MATO TMS PIO1_0 AD1 CT32B1_CAPO TDI PIOO 11 ADO CT32BO MATS PIO1 10 AD6 CT16B1 MAT SWCLK PIO0_10 SCK CT16B0_MAT2 PIO0_9 MOSI CT16B0_MAT1 SWO PIO0_8 MISO CT16B0_MATO wje EG S GIGS co PIOO_3 PIOO_4 SCL PIOO 5 SDA PIO1 9 CT16B1 MATO PIO3 4 PIO3 5 PIOO 6 SCK Transparent top view e F N e o n 002aae517 Fig5 LPC1311 13 HVQFN33 package 6 2 Pin description Table3 LPC1313 43 LQFP48 pin description table Symbol Pin Type Description RESET PIOO 0 3 RESET External reset input A LOW on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 VO PIOO 0 General purpose digital input output pin PIOO 1 CLKOUT ah VO PIOO 1 General purpose digital input output pin A LOW level on this pin CT32BO MAT2 during reset starts the ISP command handler or the USB device USB FTOGGLE enumeration USB on LPC1343 only see description of PIOO 3 O CLKOUT Clockout pin O CT32B0_MAT2 Match output 2 for 32 bit timer 0 O USB FTOGGLE USB 1 ms Start of Frame signal LPC1343 only PIOO 2
3. General purpose digital input output pin high current output driver CTS Clear To Send input for UART PIOO 8 MISO 1711 VO PIOO 8 General purpose digital input output pin CT16B0 MATO VO MISO Master In Slave Out for SSP O CT16B0 MATO Match output 0 for 16 bit timer 0 PIOO 9 MOSI 184 VO PIOO 9 General purpose digital input output pin lh eM VO MOSI Master Out Slave In for SSP O CT16B0_MAT1 Match output 1 for 16 bit timer 0 O SWO Serial wire trace output SWCLK PIOO 10 SCK 191 l SWCLK Serial wire clock and test clock TCK for JTAG interface CT16B0 MAT2 y o PIOO 10 General purpose digital input output pin O SCK Serial clock for SSP O CT16B0_MAT2 Match output 2 for 16 bit timer 0 TDI PIOO_11 AD0 218 TDI Test Data In for JTAG interface CT32B0_MAT3 VO PIOO 11 General purpose digital input output pin ADO A D converter input 0 O CT32B0_MAT3 Match output 3 for 32 bit timer 0 TMS PIO1_0 AD1 22031 l TMS Test Mode Select for JTAG interface CT32B1 CAPO VO PIO1 0 General purpose digital input output pin LPC1311 13 42 43 0 AD1 A D converter input 1 CT32B1 CAPO Capture input 0 for 32 bit timer 1 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 12 of 52 NXP Semiconductors LPC1311 13 42 43 Table 4 LPC1311 13 42 43 HVQFN33 pin description table continued Symbol
4. Preliminary data sheet Rev 00 14 20 August 2009 20 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 7 15 7 16 7 16 1 7 17 7 17 1 LPC1311_13_42_43_0 Set LOW on match Set HIGH on match Toggle on match Do nothing on match System tick timer The ARM Cortex M3 includes a system tick timer SYSTICK that is intended to generate a dedicated SYSTICK exception normally set to a 10 ms interval Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state When enabled the watchdog will generate a system reset if the user program fails to feed or reload the watchdog within a predetermined amount of time Features Internally resets chip if not periodically reloaded Debug mode Enabled by software but requires a hardware reset or a watchdog reset interrupt to be disabled Incorrect incomplete feed sequence causes reset interrupt if enabled Flag to indicate watchdog reset Programmable 32 bit timer with internal prescaler Selectable time period from Tcy wDCLK x 256 x 4 to Tcy wDCLK x 232 x 4 in multiples of Tey WDCLK x 4 e The Watchdog Clock WDCLK source can be selected from the Internal RC oscillator IRC the watchdog oscillator or the main clock This gives a wide range of potential timing choices of watchdog operation under different power reduction conditions It also provides t
5. TDO PIO1 1 AD2 CT32B1 MATO TRST PIO1 2 AD3 CT32B1_MAT1 SWDIO PIO1 3 AD4 CT32B1 MAT2 PIO1 4 AD5 CT32B1 MAT3 WAKEUP PIO1 5 RTS CT32B0 CAPO PIO1 6 RXD CT32B0 MATO PIO1 7 TXD CT32B0 MAT PIO1 8 CT16B1 CAPO PIO1 9 CT16B1 MATO PIlO1 10 AD6 CT16B1_MAT1 PIO1 11 AD7 PIO2 0 DTR PIO3 2 PIO3 4 PIO3 5 USB DM USB DP LPC1311 13 42 43 0 Pin 2301 2481 2513 2613 30H 314 321 7H 1201 2019 27 5 11 28L 130 1411 13 4 144 Type O VO Description TDO Test Data Out for JTAG interface PIO1 1 General purpose digital input output pin AD2 A D converter input 2 CT32B1 MATO Match output 0 for 32 bit timer 1 TRST Test Reset for JTAG interface PIO1 2 General purpose digital input output pin AD3 A D converter input 3 CT32B1_MAT1 Match output 1 for 32 bit timer 1 SWDIO Serial wire debug input output PIO1 3 General purpose digital input output pin AD4 A D converter input 4 CT32B1 MAT2 Match output 2 for 32 bit timer 1 PIO1 4 General purpose digital input output pin AD5 A D converter input 5 CT32B1 MATS Match output 3 for 32 bit timer 1 WAKEUP Deep power down mode wake up pin PIO1 5 General purpose digital input output pin RTS Request To Send output for UART CT32B0 CAPO Capture input 0 for 32 bit timer 0 PIO1 6 General purpose digital input output pin RXD Receive
6. pull down current pull up current High drive output pin PIOO 7 li lin loz Vi Vin ViL Vhys VoH VoL loH loL lod lou LOW level input current HIGH level input current OFF state output current input voltage output voltage HIGH level input voltage LOW level input voltage hysteresis voltage HIGH level output voltage LOW level output voltage HIGH level output current LOW level output current pull down current pull up current I C bus pins PIOO_4 and PIOO 5 VH VL Vhys LPC1311 13 42 43 0 HIGH level input voltage LOW level input voltage hysteresis voltage Conditions lot 4mA Vou Vpp o 0 4 V VoL lt 0 4 V Vau 20V VoL Vpb o V 5V V 0V Vppno lt Vi lt 5 V Vi 0 V on chip pull up resistor disabled V Vppiio on chip pull down resistor disabled Vo 0 V Vo Vpp oy on chip pull up down resistors disabled pin configured to provide a digital function output active lou 20 mA lo 4 mA Vou Vpp o 0 4 V Vpp 0 gt 2 5V Vol 0 4 V V lt B V Vi lt 0 V Vpp o lt Vi 5 V Min 10 15 0 4 HA Vppiio 0 4 DZ 20 10 15 0 7Vpp o Typ 0 5Vpp I0 Max 0 4 5 5 Vpb to 0 8 0 3Vpp 0o Unit mA mA mA mA uA uA uA lt mA mA uA uA uA V V V NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14
7. 25 C nominal supply voltages Conditions Vss 0 V Vpp 3v3 3 3 V The ADC is monotonic there are no missing codes The differential linearity error Ep is the difference between the actual step width and the ideal step width See Figure 8 The integral non linearity E aj is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors See Figure 8 The offset error Eo is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve See Figure 8 The gain error Eg is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error and the straight line which fits the ideal transfer curve See Figure 8 The absolute error Er is the maximum difference between the center of the steps of the actual transfer curve of the non calibrated ADC and the ideal transfer curve See Figure 8 LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 32 of 52 NXP Semiconductors LPC1311 13 42 43 offset gain error error Eo Eg 1023 1022 1021 L 1020 1019 1018 7L code out 6 L 5L 4 L 9 E 2 sin 1 1LSB ideal 7 n L u Z i 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 PETE
8. Also used as the ADC reference voltage 4 Input to the oscillator circuit and internal clock generator circuits Input voltage must not exceed 1 8 V 5 O Output from the oscillator amplifier 33 Thermal pad Connect to ground 1 5V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis 2 PC bus pads compliant with the I2C bus specification for I2C standard mode and I C Fast mode Plus 3 5V tolerant pad providing digital I O functions with configurable pull up pull down resistors configurable hysteresis and analog input When configured as a ADC input digital section of the pad is disabled and the pin is not 5 V tolerant 4 Pad provides USB functions It is designed in accordance with the USB specification revision 2 0 Full speed and Low speed mode only 7 Functional description 7 1 7 2 7 3 7 4 LPC1311 13 42 43 0 Architectural overview The ARM Cortex M3 includes three AHB Lite buses the system bus the I code bus and the D code bus see Figure 1 The l code and D code core buses are faster than the system bus and are used similarly to TCM interfaces one bus dedicated for instruction fetch I code and one bus for data access D code The use of two core buses allows for simultaneous operations if concurrent operations target different devices ARM Cortex M3 processor The ARM Cortex M3 is a general purpose 32 bit microproce
9. 0 PIOS 1 PIO3 2 PIO3 3 PIO3 4 PIO3 5 USB DM USB DP Vpp 0 Vpp ava Vssio XTALIN XTALOUT Vss Pin 1 20 0 1l 1101 120 24 25 31 36 37 43 481 1801 21 19 4 20 8 44 7 41 1 1 D 1 1 1 1 D 4 Type VO VO VO VO VO VO VO VO VO VO VO VO VO VO VO VO O l Description PIO2_5 General purpose digital input output pin LPC1313 only PIO2_6 General purpose digital input output pin PIO2_7 General purpose digital input output pin PIO2_8 General purpose digital input output pin PIO2_9 General purpose digital input output pin PIO2_10 General purpose digital input output pin PIO2_11 General purpose digital input output pin SCK Serial clock for SSP PIO3 0 General purpose digital input output pin PIO3 1 General purpose digital input output pin PIO3 2 General purpose digital input output pin PIO3 3 General purpose digital input output pin PIO3 4 General purpose digital input output pin LPC1313 only PIO3 5 General purpose digital input output pin LPC1313 only USB DM USB bidirectional D line LPC1343 only USB DP USB bidirectional D line LPC1343 only 3 3 V input output supply voltage 3 3 V supply voltage to the internal regulator and the ADC Also used as the ADC reference voltage Ground Input to the oscillator circuit and internal clock generato
10. 1 ms Start of Frame signal LPC1342 43 only NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 11 of 52 NXP Semiconductors LPC1311 13 42 43 Table 4 LPC1311 13 42 43 HVQFN33 pin description table continued Symbol Pin Type Description PIOO 2 SSEL all VO PIOO 2 General purpose digital input output pin CT16B0 CAPO O SSEL Slave select for SSP CT16B0 CAPO Capture input 0 for 16 bit timer 0 PIOO_3 USB_VBUS gli UO PIOO 3 General purpose digital input output pin LPC1342 43 only A LOW level on this pin during reset starts the ISP command handler a HIGH level starts the USB device enumeration l USB VBUS Monitors the presence of USB bus power LPC1342 43 only PIOO 4 SCL 10 2 UO PIOO 4 General purpose digital input output pin UO SCL I C bus clock input output High current sink only if 12C Fast Mode Plus is selected in the I O configuration register PIOO 5 SDA 11121 VO PIOO 5 General purpose digital input output pin Vo SDA I2C bus data input output High current sink only if IC Fast Mode Plus is selected in the I O configuration register PIOO 6 USB CONNECT 1501 O PIOO 6 General purpose digital input output pin SCK O USB_CONNECT Signal used to switch an external 1 5 KQ resistor under software control Used with the SoftConnect USB feature LPC1342 43 only VO SCK Serial clock for SSP PIOO 7 CTS 160 VO PIOO 7
11. 13 42 43 0 11 LPC1311 13 42 43 0 10 Modifications Changed TRACE SWV to SWO and SWD to SWDIO Figure 3 and Figure 6 add 33 Vss to thermal pad Add pin 33 to Table 4 with pin description Thermal Pad Connect to ground LPC1311 13 42 43 0 10 lt tbd gt Objective data sheet LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 50 of 52 NXP Semiconductors LPC1311 13 42 43 16 Legal information 17 Data sheet status Document statusl11l21 Product statusi Definition Objective short data sheet Development Preliminary short data sheet Qualification Product short data sheet Production This document contains data from the objective specification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 17 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal a
12. 5 SDA 16 PIO2 4 18 USB DM 19 USB DP 20 PIO2 5 21 PlO2 9 24 PIO1 9 CT16B1 MATO 17 PIO2 1 DSR 13 PIOO 3 USB VBUS 14 PIOO_7 CTS 23 PIOO_6 USB_CONNECT SCK 22 Fig 2 LPC1343 LQFP48 package LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 5 of 52 NXP Semiconductors LPC1311 13 42 43 terminal 1 index area PIO2 0 DTR RESET PIOO 0 PIOO_1 CLKOUT CT32B0_MAT2 USB_FTOGGLE XTALIN XTALOUT VDD 10 PIO1 8 CT16B1 CAPO PIOO 2 SSEL CT16B0 CAPO Fig 3 LPC1342 43 HVQFN33 package PIO1 7 TXD CT32B0 MATT a ul X lt z o e Fa E lt lt lt 2 9 oo mm m a a a e FE E E Q Oo LO ao a 0 x E lt O Cir SZ OB Sar F E E a rr RARR oOO0nOooQo aa gt D D DL SWDIO PIO1 3 AD4 CT32B1 MAT2 G2 GT Go Q3 Q8 C7 Qs G5 30970008 9 mo 15 ED LPC1342FHN33 LPC1343FHN33 lt a o ED 16 TRST PIO1 2 AD3 CT32B1 MAT1 TDO PIO1 1 AD2 CT32B1 MATO TMS PIO1_0 AD1 CT32B1_CAPO TDI PIOO_11 ADO CT32B0_MAT3 PIO1_10 AD6 CT16B1_MAT1 SWCLK PIOO 10 SCK CT16B0 MATS PIO0_9 MOSI CT16B0_MAT1 SWO PIO0_8 MISO CT16B0_MATO FARIA AR PIO0 S USB VBUS PIOO 4 SCL PIOO 5 SDA PIO1 9 CT16B1 MATO PIOO 6 USB CONNECT SCK Transparent top view PIOO 7 CTS 002aae516 LPC1311 13 42 43 0 NXP B V 2009 All rights reserve
13. Application Programming IAP via on chip bootloader software W Selectable boot up UART or USB USB on LPC134x only W Serial interfaces USB 2 0 full speed device controller with on chip PHY for device LPC1342 43 only UART with fractional baud rate generation modem internal FIFO and RS 485 EIA 485 support SSP controller with FIFO and multi protocol capabilities C bus interface supporting full I2C bus specification and Fast mode Plus with a data rate of 1 Mbit s with multiple address recognition and monitor mode W Other peripherals Up to 42 General Purpose I O GPIO pins with configurable pull up pull down resistors founded by Philips NXP Semiconductors LPC1 31 1 1 3 42 43 3 Applications Four general purpose timers counters with a total of four capture inputs and 13 match outputs Programmable WatchDog Timer WDT System tick timer Serial Wire Debug and Serial Wire Trace Port High current output driver 20 mA on one pin High current sink drivers 20 mA on two I C bus pins in Fast mode Plus Integrated PMU Power Management Unit to minimize power consumption during Sleep Deep sleep and Deep power down modes Three reduced power modes Sleep Deep sleep and Deep power down Single 3 3 V power supply 2 0 V to 3 6 V 10 bit ADC with input multiplexing among 8 pins GPIO pins can be used as edge and level sensitive interrupt sources Clock output function with
14. SSEL 1011 VO PIOO 2 General purpose digital input output pin CT16B0_CAPO O SSEL Slave select for SSP LPC1311_13_42_43_0 CT16BO CAPO Capture input 0 for 16 bit timer 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 8 of 52 NXP Semiconductors LPC1311 13 42 43 Table 3 LPC1313 43 LQFP48 pin description table continued Symbol Pin Type Description PIOO 3 USB VBUS 1411 VO PIOO 3 General purpose digital input output pin LPC1343 only A LOW level on this pin during reset starts the ISP command handler a HIGH level starts the USB device enumeration USB_VBUS Monitors the presence of USB bus power LPC1343 only PIOO 4 SCL 1512 VO PIOO 4 General purpose digital input output pin UO SCL l C bus clock input output High current sink only if IC Fast Mode Plus is selected in the I O configuration register PIOO 5 SDA 1612 VO PIOO 5 General purpose digital input output pin UO SDA I C bus data input output High current sink only if 12C Fast Mode Plus is selected in the I O configuration register PIOO0 6 USB CONNECT 2201 1 0 PIOO 6 General purpose digital input output pin SCK O USB CONNECT Signal used to switch an external 1 5 kO resistor under software control Used with the SoftConnect USB feature LPC1343 only VO SCK Serial clock for SSP PIOO 7 CTS 2301 VO PIOO 7 General purpose digital input output pin high current outpu
15. bits e All I O default to inputs with pull up resistors enabled after reset Pull up pull down resistor configuration can be programmed through the IOCONFIG block for each GPIO pin NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 17 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 7 9 7 9 1 7 9 1 1 7 10 LPC1311 13 42 43 0 USB interface LPC1342 43 only The Universal Serial Bus USB is a 4 wire bus that supports communication between a host and one or more up to 127 peripherals The host controller allocates the USB bandwidth to attached devices through a token based protocol The bus supports hot plugging and dynamic configuration of the devices All transactions are initiated by the host controller The LPC1342 43 USB interface is a device controller with on chip PHY for device functions Full speed USB device controller The device controller enables 12 Mbit s data exchange with a USB Host controller It consists of a register interface serial interface engine and endpoint buffer memory The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer The status of a completed USB transfer or error condition is indicated via status registers An interrupt is also generated if enabled Features Fully compliant with USB 2 0 specification full speed Supports 10 physical 5 logical endpoints with up to 64 by
16. in either master or slave mode depending on whether the chip has to initiate a data transfer or is only addressed The I2C is a multi master bus and can be controlled by more than one bus master connected to it Features e The I2C bus interface is a standard C bus compliant interface with open drain pins The I2C bus interface also supports Fast Mode Plus with bit rates up to 1 Mbit s Easy to configure as master slave or master slave Programmable clocks allow versatile rate control Bidirectional data transfer between masters and slaves NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 19 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 7 13 7 13 1 7 14 7 14 1 LPC1311 13 42 43 0 Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The I2C bus can be used for test and diagnostic purposes The I C bus controller supports multiple address recognition and a bus monitor mode 10 bit ADC The LPC1311 13 42 43 contains one ADC It is a single 10 bit successive approximation ADC with eight channels Features 10 bit successive approximation ADC Inpu
17. process 7 17 5 Power control lt 7 17 5 1 Sleep mode founded by 7 17 5 2 7 17 5 3 7 18 7 18 1 7 18 2 7 18 3 7 18 4 7 18 5 7 18 6 7 18 7 7 18 8 7 19 9 1 10 10 1 10 2 10 3 11 11 1 11 2 11 3 11 4 11 5 11 6 12 12 1 12 2 12 3 12 4 13 14 15 16 17 17 1 17 2 17 3 18 19 Deep sleep mode nnn nanan a 24 Deep power down mode 24 System contro a aaea 24 OSE Ua Ek Ll e ye 24 Brownout detection nassau u nnna 25 Code security Code Read Protection CRP 25 Boot loader lt 25 APB interface 2 ccc eee 26 Amoy ER mRereT EAT 26 External interrupt inputs 26 Memory mapping control 26 Emulation and debugging 26 Limiting values Lise 27 Thermal characteristics 28 Thermal characteristics 28 Static characteristics 29 BOD static characteristics 34 Power consumption 34 Electrical pin characteristics 36 Dynamic characteristics 39 Flash memory 39 External clock 0 000000 eeee 39 Internal oscillators lt lt 40 PC DUS aid oid hed a RA abe d Aneta dential 41 SSP interface cc ee 42 USB interface LPC1342 43 only 44 Application information 45 Suggested USB interface solutions LPC134
18. warranty intellectual property rights infringement and limitation of liability unless explicitly otherwise agreed to in writing by NXP Semiconductors In case of any inconsistency or conflict between information in this document and such terms and conditions the latter will prevail No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from national authorities 17 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I2C bus logo is a trademark of NXP B V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com LPC1311_13 42 43 0 NXP B V 2009 All rights reserved 51 of 52 Preliminary data sheet Rev 00 14 20 August 2009 NXP Semiconductors LPC1311 13 42 43 19 Contents 1 General description 2 Features 5 voe ac ewes 3 Applications lesser 4 Ordering information 4 1 Ordering options 5 B
19. 11 1 Flash memory Table 11 Flash characteristics Tamp 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Nendu endurance 1 10000 cycles tret retention time powered 10 years unpowered 20 years 1 Number of program erase cycles 11 2 External clock Table 12 Dynamic characteristic external clock Tamb 40 C to 85 C Vpp ava over specified ranges Symbol Parameter Conditions Min Typi Max Unit fosc oscillator frequency 1 25 MHz Tey clk clock cycle time 40 1000 ns tcHcx clock HIGH time Toy clk x 0 4 ns tcLcx clock LOW time Toy clk x 0 4 ns toLoH clock rise time 5 ns tcHcL clock fall time 5 ns 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages Fig 18 External clock timing with an amplitude of at least VyRms 200 mV 002aaa907 LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 39 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 11 3 Internal oscillators Table 13 Dynamic characteristic internal oscillators Tamb 40 C to 85 C 2 7 V lt Vpp sva 3 6 VT Symbol Parameter Conditions Min Typ 2 Max Unit fosc RC internal RC oscillator frequency 11 88 12 12 12 MHz 1 Par
20. 2 43 Only 5 nicus suns nach teo aet ES 45 XTAL input 2 2 0 eee 45 XTAL Printed Circuit Board PCB layout guidelines 00 eee eee 46 Standard I O pad configuration 46 Package outline sLe 47 Abbreviations lreeee 49 Revision history lesse 50 Legal information Lee 51 Data sheet status n n naaa aa unnn 51 Definitions o cactaceae aia i eala ho inana 51 Disclaimers 000 cc eee eee eee 51 Trademarks eee 51 Contact information 51 Contents lilii bRRILAEEdRG h IX bes 52 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2009 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 20 August 2009 Document identifier LPC1311 13 42 43 0
21. 20 August 2009 30 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 Table8 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit VoL LOW level output loLs 20 mA n2 0 4 V voltage lu input leakage current Vi Vpp io 4 2 4 uA Vi lt B V 10 22 uA Oscillator pins Vi xtal crystal input voltage 0 1 8 1 95 V Vo xtal crystal output voltage 0 1 8 1 95 V USB pins LPC1342 43 only loz OFF state output OV lt V lt 33V 10 uA current Vaus bus supply voltage 5 25 V Vol differential input D D 0 2 N V sensitivity voltage Vem differential common includes Vp range 0 8 2 5 V mode voltage range Vtn rs se single ended receiver 0 8 2 0 V switching threshold voltage VoL LOW level output for low full speed 0 18 V voltage R of 1 5 KQ to 3 6 V Vou HIGH level output driven for low full speed 2 8 3 5 V voltage RL of 15 kQ to GND Cirans transceiver capacitance pin to GND 20 pF Zprv driver output with 33 series resistor 15 36 44 1 Q impedance for driver steady state drive which is not high speed capable 1 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 2 IRC enabled system oscillator disabled system PLL disabled 3 BOD disabled 4 All peripherals disabled in the AHBCLKCTRL register Peripheral clocks to UART SSP
22. 2009 9 of 52 NXP Semiconductors LPC1311 13 42 43 Table 3 LPC1313 43 LQFP48 pin description table continued Symbol TRST PIO1 2 ADS CT32B1 MAT1 SWDIO PIO1 3 AD4 CT32B1 MAT2 PIO1 4 AD5 CT32B1 MAT3 WAKEUP PIO1 5 RTS CT32B0 CAPO PIO1 6 RXD CT32B0 MATO PIO1 7 TXD CT32B0 MAT1 PIO1 8 CT16B1 CAPO PIO1 9 CT16B1 MATO PIO1 10 AD6 CT16B1_MAT1 PIO1 11 AD7 PIO2 0 DTR PlO2 1 DSR PIO2 2 DCD PIO2 3 RI PIO2 4 PIO2 4 PIO2 5 LPC1311 13 42 43 0 Pin 3513 3913 4083 45 4611 4701 gt 1711 302 1301 26 1 38 1811 1911 21 H Type VO Description TRST Test Reset for JTAG interface PIO1 2 General purpose digital input output pin AD3 A D converter input 3 CT32B1 MAT1 Match output 1 for 32 bit timer 1 SWDIO Serial wire debug input output PIO1 3 General purpose digital input output pin AD4 A D converter input 4 CT32B1 MAT2 Match output 2 for 32 bit timer 1 PIO1 4 General purpose digital input output pin AD5 A D converter input 5 CT32B1 MAT3 Match output 3 for 32 bit timer 1 WAKEUP Deep power down mode wake up pin PIO1 5 General purpose digital input output pin RTS Request To Send output for UART CT32B0 CAPO Capture input 0 for 32 bit timer 0 PIO1 6 General purpose digital input output pin RXD Receiver input for UART CT32B0 MATO Match output 0 for 32 b
23. 4000 8000 0x4000 4000 0x4000 0000 reserved 0x0000 8000 0x0000 4000 515 byte active interrupt vectors 0x0000 0000 8 kB on chip flash LPC1311 00000 0000 32 kB on chip flash LPC1313 43 0 GB 002aae723 Fig 6 LPC1311 13 42 43 memory map 7 6 Nested Vectored Interrupt Controller NVIC The Nested Vectored Interrupt Controller NVIC is an integral part of the Cortex M3 The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts 7 6 1 Features Controls system exceptions and peripheral interrupts e On the LPC1311 13 42 43 the NVIC supports 16 vectored interrupts In addition up to 40 of the individual GPIO inputs are NVIC vector capable LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 16 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 7 6 2 rer 7 8 7 8 1 LPC1311 13 42 43 0 8 programmable interrupt priority levels with hardware priority level masking Relocatable vector table Software interrupt generation Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags Individual interrupt flags may also represent more than one interrupt source Any GPIO pin total of up to 42 pins regardless of the selected function can be programmed to generate an interrupt on a
24. C PHY PLL SEO SPI SSI SoF TTL UART USB Description Analog to Digital Analog to Digital Converter Advanced High performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection End Of Packet Embedded Trace Macrocell First In First Out General Purpose Input Output Input Output Least Significant Bit Mass Storage Class Physical Layer Phase Locked Loop Single Ended Zero Serial Peripheral Interface Serial Synchronous Interface Start of Frame Transistor Transistor Logic Universal Asynchronous Receiver Transmitter Universal Serial Bus LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 49 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 15 Revision history Table 18 Revision history Document ID Release date Data sheet status Change notice Supersedes LPC1311 13 42 43 0 14 Preliminary data sheet LPC1311 13 42 43 0 13 Modifications SSP SPI mode timing data added e C bus timing parameters added Data sheet status changed to preliminary LPC1311 13 42 43 0 13 LPC1311 13 42 43 0 12 Modifications Power consumption data added Padcharacteristics added SSP SPI mode timing diagrams updated LPC1311 13 42 43 0 12 LPC1311 13 42 43 0 11 Modifications Changed pin name TCK to SWCLK e Changed pin name Vppcone to Vpp ava Changed pin name USB FRAME TOGGLE to USB FTOGGLE LPC1311
25. IOO 7 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 36 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 LPC1311_13 42 43 0 001aac984 X X Measured on pins Pn m Vpp avs X X V Fig 14 Typical LOW level output loj current versus LOW level output VoL 001aac984 X X Measured on pins Pn m Vpp ava XX V Fig 15 Typical HIGH level output lop current versus HIGH level output voltage Voy NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 37 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 LPC1311_13 42 43 0 001aac984 X X Measured on pins Pn m Vpp avs X X V Fig 16 Typical pull up current ly versus input voltage V 001aac984 X X Measured on pins Pn m Vpp ava XX V Fig 17 Typical pull down current lpa versus input voltage V NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 38 of 52 NXP Semiconductors LPC1311 13 42 43 11 Dynamic characteristics
26. MS 026 ET 03 02 25 Fig 29 Package outline SOT313 2 LQFP48 LPC1311_13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 47 of 52 NXP Semiconductors LPC1311 13 42 43 HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 terminals body 7 x 7 x 0 85 mm terminal 1 index area terminal 1 index area Dimensions detail X Unit AD Ai b DU Dh E0 y1 max 1 00 0 05 0 35 7 1 mm nom 0 85 0 02 0 28 0 2 7 0 min 0 80 0 00 0 23 6 9 4 85 7 1 4 85 0 75 4 70 7 0 4 55 6 9 4 55 0 45 4 70 0 65 4 55 4 55 0 60 0 1 0 05 0 08 0 1 Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included Outline References version JEDEC JEITA European projection hvqfn33 po Issue date Fig 30 Package outline HVQFN33 LPC1311 13 42 43 0 co 99 9317 09 03 23 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 48 of 52 NXP Semiconductors LPC1311 13 42 43 14 Abbreviations Table 17 Abbreviations Acronym A D ADC AHB AMBA APB BOD EOP ETM FIFO GPIO VO LSB MS
27. NS Via LSB offset error 1a LSBideal E A o 1LSB Vpp 3v3 1024 002aae787 1 Example of an actual transfer curve 2 The ideal transfer curve 3 Differential linearity error Ep 4 Integral non linearity E aq b Center of a step of the actual transfer curve Fig 8 ADC characteristics LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 33 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 10 1 BOD static characteristics Table 10 BOD static characteristics Tamb 25 Symbol Parameter Conditions Min Typ Max Unit Vin threshold voltage interrupt level 0 assertion 1 69 V de assertion 1 84 V interrupt level 1 assertion 2 29 V de assertion 2 44 V interrupt level 2 assertion 2 59 V de assertion 2 74 V interrupt level 3 assertion 2 87 V de assertion z 2 98 V reset level 0 assertion 1 49 V de assertion 1 64 V 1 Interrupt levels are selected by writing the level value to the BOD control register BODCTRL see LPC13xx user manual 10 2 Power consumption LPC1311 13 42 43 0 001aac984 X X Conditions Tamp 25 C active mode entered executing code from flash Supply voltage 3 3 V all peripherals enabled but not configured to run Fig 9 Supply current at different co
28. PB 8 16 32 kB BRIDGE RXD ETE SHA CIS uant ADI7 9 DTR DSR CTS s DCD 2 RI 2 RTS SCK SSEL Milieu edipi 32 bit COUNTER TIMERO lt MISO DI CT32B0 CAPO MOSI SCL oreet MATBO I countenmment Ky CL es 3 SDA CT32B1 CAPO 32 bit COUNTER TIMER 1 16 bit COUNTER TIMER 0 CT16B0 CAPO C WDT 16 bit COUNTER TIMER 1 CT16B1 CAPO i GONE CY SYSTEM CONTROL 002aae722 1 LPC1342 43 only 2 LOFP48 package only Fig 1 Block diagram LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 4 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 6 Pinning information 6 1 Pinning 5 UE mE m F xxm lt 8 z A5 Ske oo o D m mam ma QN A a N BEP PS O00 SSE o B 5 Q x E 2 dO E tlt gt sale L lek ud S E I cr r Sor roan 9000 800 FQZQ9D D onn 0n0 5 n00n0 n N col to CO V e oj o r lt v vl 4 0 mjn PIO2 6 PIO3 0 PIO2 0 DTR TRST PIO1 2 AD3 CT32B1 MAT1 RESET PIOO 0 PIO0 1 CLKOUT CT32BO0 MAT2 USB FTOGGLE TDO PIO1 1 AD2 CT32B1 MATO TMS PIO1 0 AD1 CT32B1 CAPO Vssio TDI PIOO 11 ADO CT32B0 MAT3 XTALIN LPC1343FBD48 PIO2 11 SCK XTALOUT PIO1_10 AD6 CT16B1_MAT1 VDD IO SWCLK PIO0_10 SCK CT16B0_MAT2 PIO1 8 CT16B1 CAPO PIO0_2 SSEL CT16B0_CAPO PIO2 7 PIO2 8 PIO0_9 MOSI CT16B0_MAT1 SWO PIO0_8 MISO CT16B0_MATO PIO2 2 DCD PIO2 10 002aae505 PIOO_4 SCL 15 PIOO
29. PC134x R1 1 5 kQ USB_VBUS USB DP Rs 330 USB B lt connector USB DM Rs 332 Vssio 002aae609 Fig 26 LPC1342 43 USB interface on a bus powered device 12 2 XTAL input The input voltage to the on chip oscillators is limited to 1 8 V If the oscillator is driven by a clock in slave mode it is recommended that the input be coupled through a capacitor with C 100 pF To limit the input voltage to the specified range choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Cj C Cg In slave mode a minimum of 200 mV RMS is needed LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 45 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 12 3 12 4 LPC1xxx 002aae788 Fig 27 Slave mode operation of the on chip oscillator XTAL Printed Circuit Board PCB layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip Take care that the load capacitors C44 C and Cy3 in case of third overtone crystal usage have a common ground plane The external components must also be connected to the ground plain Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible Also parasitics should stay as small as possible Values of Cy and Cy shou
30. ameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 001aac984 X X conditions lt tbd gt Fig 19 Internal RC oscillator frequency vs temperature 001aac984 conditions lt tbd gt Fig 20 Internal RC oscillator frequency vs regulator supply voltage LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 40 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 11 4 I2C bus Table 14 Dynamic characteristic I2C bus pins Fast mode Plus Tamb 40 C to 85 C Vppyava over specified anges D Symbol Parameter Conditions Min Typ 2lis Max Unit fscL SCL clock freguency 1 MHz ti o output fall time Vin to Vy 20 0 1x Cl ns ti rise time tbd 27 lt tbd gt ns t fall time lt tbd gt 39 lt tbd gt ns tLow LOW period of the SCL clock lt tbd gt 541 lt tbd gt ns tHIGH HIGH period of the SCL clock lt tbd gt 375 lt tbd gt ns tsu DAT data set up time lt tbd gt 23 lt tbd gt ns 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed
31. anced very thin quad flat package no leads 33 n a terminals body 7 x 7 x 0 85 mm LPC1342FHN33 HVQFN33 HVQFN plastic thermal enhanced very thin quad flat package no leads 33 n a terminals body 7 x 7 x 0 85 mm LPC1343FBD48 LQFP48 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm sot313 2 LPC1343FHN33 HVQFN33 HVQFN plastic thermal enhanced very thin quad flat package no leads 33 n a terminals body 7 x 7 x 0 85 mm 4 1 Ordering options Table 2 Ordering options for LPC1311 13 42 43 Type number Flash Total USB UART PC SSP ADC Pins Package SRAM RS 485 Fast channels LPC1311FHN33 8 kB 4 kB 1 1 1 8 33 HVQFN33 LPC1313FBD48 32kB 8kB 1 1 1 8 48 LQFP48 LPC1313FHN33 32kB 8kB 1 1 1 8 33 HVQFN33 LPC1342FHN33 16kB 4kB Device 1 1 1 8 33 HVQFN33 LPC1343FBD48 32kB 8kB Device 1 1 1 8 48 LOFP48 LPC1343FHN33 32kB 8kB Device 1 1 1 8 33 HVQFN33 LPC1311_13_42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 3 of 52 NXP Semiconductors LPC1311 113 42 43 5 Block diagram s XTALIN USB pins XTALOUT RESET LPC1311 13 42 43 1 TEST DEBUG USB PHY INTERFACE IRC CLOCK t GENERATION POWER CONTROL CLKOUT ARM USB DEVICE SYSTEM CORTEX M3 CONTROLLER FUNCTIONS clocks and code D code system slave controls bus bus bus slave SEE AHB LITE BUS slave SRAM 4 8 kB slave GPIO ports HIGH SPEED d slave U slave U alias S AHB TO FLASH A
32. and SysTick timer disabled in the syscon block 5 IRC disabled system oscillator enabled system PLL enabled 6 All oscillators and analog blocks turned off in the PDRUNCFG register 7 WAKEUP pin pulled HIGH externally 8 ForLPC134x USB DP and USB DM pulled LOW externally 9 Including voltage on outputs in 3 state mode 10 Vpp sva and Vppiio supply voltages must be present 11 3 state outputs go into 3 state mode when Vpp sva is grounded 12 Accounts for 100 mV voltage drop in all supply lines 13 Allowed as long as the current limit does not exceed the maximum current allowed by the device 14 To Vss 15 Includes external resistors of 33 O 1 96 on USB DP and USB DM LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 31 of 52 NXP Semiconductors LPC1311 13 42 43 Table 9 ADC static characteristics Tamb 40 C to 85 C unless otherwise specified ADC frequency 4 5 MHz Vpp ava 2 5 V to 3 6 V Symbol Parameter Conditions Min Via analog input voltage 0 Cia analog input capacitance Ep differential linearity error BBA Ei adj integral non linearity BB Eo offset error 26 EG gain error 27 ET absolute error 28 Typ 1 3 Max Vppv3 1 Unit pF LSB LSB LSB 96 LSB 1 2 3 4 5 6 7 8 Typical ratings are not guaranteed The values listed are at room temperature
33. are at room temperature 25 C nominal supply voltages 3 Main clock frequency 10 MHz system clock divider AHBCLKDIV 0x1 I2C bus interface configured in master transmitter mode 4 Bus capacitance Cp in pF from 10 pF to 400 pF tHIGH tsU DAT 002aae860 Fig 21 I2C bus pins clock timing LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 41 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 11 5 SSP interface Table 15 Dynamic characteristics of SSP pins in SPI mode Tamb 25 C Symbol Parameter Conditions Min Typ Max Unit Tey PCLK PCLK cycle time 139 ns Toy clk clock cycle time pn 278 S ns SSP master tps data set up time in SPI mode 10 N Toy clk ns toH data hold time in SPI mode 0 ns twa data output valid time in SPI mode 10 ns tha data output hold time in SPI mode 0 ns SPI slave tps data set up time in SPI mode lt tbd gt ns Iou data hold time in SPI mode lt tbd gt ns tva data output valid time in SPI mode lt tbd gt ns tha data output hold time in SPI mode gt lt tbd gt ns 1 Toyrek SSPCLKDIV x 1 SCR x CPSDVSR fmain The clock cycle time derived from the SPI bit rate Ty eix is a function of the main clock frequency fmain the SSP peripheral clock divider SSPCLKDIV the SSP SCR parameter specified in the SSPOCRO register and the SSP CPSDVSR parameter specifi
34. cts are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental 18 Contact information damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 may cause permanent damage to the device Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied Exposure to limiting values for extended periods may affect device reliability Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms including those pertaining to
35. d Preliminary data sheet Rev 00 14 20 August 2009 6 of 52 NXP Semiconductors LPC1311 13 42 43 Vss 48 PIO3 3 PIO2 6 PIO2 0 DTR RESET PIOO 0 PIO0 1 CLKOUT CT32BO MATS Vssio XTALIN XTALOUT VDD IO PIO1 8 CT16B1 CAPO PIOO 2 SSEL CT16B0 CAPO 47 PIO1 7 TXD CT32BO MAT1 46 PIO1 6 RXD CT32BO MATO 40 PlO1_4 AD5 CT32B1_MAT3 WAKEUP 39 SWDIO PIO1_3 AD4 CT32B1_MAT2 45 PIO1 5 RTS CT32B0 CAPO 44 VpD sv3 43 PIO3 2 42 PIO1 11 AD7 38 PIO2 3 RI 37 PIO3 1 41 PIO3 0 TRST PIO1 2 AD3 CT32B1 MAT1 TDO PIO1 1 AD2 CT32B1 MATO TMS PIO1 0 AD1 CT32B1 CAPO TDI PIOO 11 ADO CT32BO MAT3 PIO2 11 SCK PIO1 10 AD6 CT16B1 MAT1 SWCLK PIOO 10 SCK CT16B0 MAT2 PIO0 9 MOS CT16B0 MAT1 SWO PIO0 8 MISO CT16B0 MATO LPC1313FBD48 PIO2 7 PIO2 2 DCD PIO2 8 PIO2 10 Gl lt o o o lonl leal l INI leal l sr m mm mm m m a aula ao 002aae513 tcc 9 o S 2 S M 5 gp e Do a O oa lt Ra Aa O ON S992529 99926 2 BJ sh n nn n o o n 8 988 99 a co n T oa e o o a Fig 4 LPC1313 LQFP48 package LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 7 of 52 NXP Semiconductors LPC1311 13 42 43 PIO1 6 RXD CT32B0 MATO terminal 1 index area PIO1 7 TXD CT32BO MAT1 SWDIO PIO1 3 AD4 CT32B1 MAT2 PIO1 5 RTS CT32B0 CAPO PIO1 11 AD7 PIO1 4 AD5 CT32B1 MAT3 WAKEUP VDD 3V3 PIO3 2
36. divider that can reflect the system oscillator clock IRC clock CPU clock or the watchdog clock Processor wake up from Deep sleep mode via a dedicated start logic using up to 40 of the functional pins Brownout detect with four separate thresholds for interrupt and one threshold for forced reset Power On Reset POR Crystal oscillator with an operating range of 1 MHz to 25 MHz 12 MHz internal RC oscillator trimmed to 1 96 accuracy that can optionally be used as a system clock PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal May be run from the main oscillator the internal RC oscillator or the Watchdog oscillator Code Read Protection CRP with different security levels Available as 48 pin LQFP package and 33 pin HVQFN package LPC1311 13 42 43 0 eMetering Lighting Industrial networking Alarm systems White goods NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 2 of 52 NXP Semiconductors LPC1311 13 42 43 4 Ordering information Table 1 Ordering information Type number Package Name Description Version LPC1311FHN33 HVQFN33 HVQFN plastic thermal enhanced very thin quad flat package no leads 33 n a terminals body 7 x 7 x 0 85 mm LPC1313FBD48 LQFP48 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm sot313 2 LPC1313FHN33 HVQFN33 HVQFN plastic thermal enh
37. e chip wakes up from deep sleep The IRC can be switched on and off glitch free and provides a clean clock signal after start up If power consumption is not a concern any of the oscillators and or PLLs can be left running in Deep sleep mode to obtain short wake up times when waking up from deep sleep Deep power down mode In Deep power down mode power is shut off to the entire chip with the exception of the WAKEUP pin The LPC1311 13 42 43 can wake up from Deep power down mode via the WAKEUP pin System control Reset Reset has four sources on the LPC1311 13 42 43 the RESET pin the Watchdog reset power on reset POR and the Brown Out Detection BOD circuit The RESET pin is a Schmitt trigger input pin Assertion of chip reset by any source once the operating voltage attains a usable level starts the IRC and initializes the flash controller NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 24 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 7 18 2 7 18 3 When the internal reset is removed the processor begins executing at address 0 which is initially the reset vector mapped from the boot block At that point all of the processor and peripheral registers have been initialized to predetermined values Brownout detection The LPC1311 13 42 43 includes four levels for monitoring the voltage on the Vpp ava pin If this voltage falls below one of the four select
38. ed in the SSP clock prescale register LPC1311_13 42 43 0 SCK CPOL 0 SCK CPOL 1 twa Rl a tha tps tpH CPHA 1 r lt ______ MISO DATA VALID DATA VALID tva th Q MOSI DATA VALID DATA VALID tps tpH CPHA 0 lt o o ea MISO DATA VALID DATA VALID 002aae829 Fig 22 SSP master timing in SPI mode NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 42 of 52 NXP Semiconductors LPC1311 13 42 43 LPC1311 13 42 43 0 SCK CPOL 0 SCK CPOL 1 MOSI wa tha CPHA 1 MISO DATA VALID DATA VALID MOSI MISO Tey clk okn ik A ee V tos TOU a DATA VALID DATA VALID tps tDH DATA VALID DATA VALID twa qp4 DATA VALID DATA VALID Fig 23 SSP slave timing in SPI mode tha gt CPHA 0 002aae830 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 43 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 11 6 USB interface LPC1342 43 only Table 16 Dynamic characteristics USB pins full speed C 50 pF Hy 1 5 KQ on D to Vpp avya unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 to 90 8 5 13 8 ns tr fall time 10 96 to 90 7 7 13 7 ns tFRFM diff
39. ed levels the BOD asserts an interrupt signal to the NVIC This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt if not software can monitor the signal by reading a dedicated status register An additional threshold level can be selected to cause a forced reset of the chip Code security Code Read Protection CRP This feature of the LPC1311 13 42 43 allows user to enable different levels of security in the system so that access to the on chip flash and use of the JTAG and ISP can be restricted When needed CRP is invoked by programming a specific pattern into a dedicated flash location IAP commands are not affected by the CRP There are three levels of Code Read Protection 1 CRP1 disables access to chip via the JTAG and allows partial flash update excluding flash sector 0 using a limited set of the ISP commands This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased 2 CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands 3 Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP This mode effectively disables ISP override using PIOO 1 pin too It is up to the user s application to provide if needed flash update mechanism using IAP calls or call reinvoke ISP command to enable flash u
40. erential rise and fall time t t 109 matching Vcns output signal crossover voltage 1 3 2 0 V FEOPT source SEO interval of EOP see Figure 24 160 175 ns tFDEOP source jitter for differential transition see Figure 24 2 5 ns to SEO transition UR1 receiver jitter to next transition 18 5 18 5 ns tyre receiver jitter for paired transitions 10 96 to 90 9 9 ns TEOPR1 EOP width at receiver must reject as O 40 ns EOP see Figure 24 TEOPR2 EOP width at receiver must accept as 1 82 ns EOP see Figure 24 1 Characterized but not implemented as production test Guaranteed by design PERIOD lt gt crossover point extended crossover point se differential data lines source EOP width tFEOPT differential data to SEO EOP skew gt nxt t cope Neer aam receiver EOP width teopri tmoPR2 002aab561 Fig 24 Differential data to EOP transition skew and EOP width LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 44 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 12 Application information 12 1 Suggested USB interface solutions LPC1342 43 only USB CONNECT LPC134x USB B connector 002aae608 Fig 25 LPC1342 43 USB interface on a self powered device VDD IO L
41. he ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability Clocking and power control Crystal oscillators The LPC1311 13 42 43 include three independent oscillators These are the system oscillator the Internal RC oscillator IRC and the watchdog oscillator Each oscillator can be used for more than one purpose as required in a particular application Following reset the LPC1311 13 42 43 will operate from the internal RC oscillator until switched by software This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency See Figure 7 for an overview of the LPC1311 13 42 43 clock generation NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 21 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 AHB clock 0 system SYSTEM CLOCK System clock DIVIDER AHB clock 1 ROM D AHBCLKCTRL AHB clock enable AHB clocks 14 2to 15 memories and peripherals AHBCLKCTRL AHB clock 16 IOCONFIG AHBCLKCTRL l SSP PERIPHERAL SSP IRC oscillator main clog CLOCK DIVIDER watchdog oscillator UART PERIPHERAL nae CLOCK DIVIDER MAINCLKSEL main clock select SYSTICK TIMER SYSTICK IRC oscillator CLOCK DIVIDER timer system oscillator SYSTEM PLL watchdog oscill
42. he instruction I code and data D code CPU buses of the ARM Cortex M3 to the flash memory the main static RAM and the boot ROM External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs Memory mapping control The Cortex M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map This is controlled via the Vector Table Offset Register contained in the NVIC The vector table may be located anywhere within the bottom 1 GB of Cortex M3 address space The vector table must be located on a 128 word 512 byte boundary because the NVIC on the LPC1311 13 42 43 is configured for 128 total interrupts Emulation and debugging Debug functions are integrated into the ARM Cortex M3 Serial wire debug is supported NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 26 of 52 NXP Semiconductors LPC1311 13 42 43 8 Limiting values Table 6 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 1 Symbol Parameter Vpp 3v3 supply voltage 3 3 V VDpD 0 input output supply voltage Vi input voltage Ipp supply current Iss ground current liatch I O latch up current Tstg storage temperature Ptot pack total power dissipation per package Vesp electrostatic discharge voltage Conditions core and external rail 5 V tolerant I O pins only valid when
43. it timer 0 PlO1 7 General purpose digital input output pin TXD Transmitter output for UART CT32B0_MAT1 Match output 1 for 32 bit timer 0 PIO1 8 General purpose digital input output pin CT16B1 CAPO Capture input 0 for 16 bit timer 1 PIO1 9 General purpose digital input output pin CT16B1 MATO Match output 0 for 16 bit timer 1 PIO1 10 General purpose digital input output pin AD6 A D converter input 6 CT16B1_MAT1 Match output 1 for 16 bit timer 1 PIO1 11 General purpose digital input output pin AD7 A D converter input 7 PIO2 0 General purpose digital input output pin DTR Data Terminal Ready output for UART PIO2 1 General purpose digital input output pin DSR Data Set Ready input for UART PIO2 2 General purpose digital input output pin DCD Data Carrier Detect input for UART PIO2 3 General purpose digital input output pin RI Ring Indicator input for UART PIO2 4 General purpose digital input output pin LPC1343 only PIO2 4 General purpose digital input output pin LPC1313 only PIO2 5 General purpose digital input output pin LPC1343 only NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 10 of 52 NXP Semiconductors LPC1311 13 42 43 Table 3 LPC1313 43 LQFP48 pin description table continued Symbol PIO2 5 PIO2 6 PIO2 7 PIO2 8 PIO2 9 PIO2 10 PIO2 11 SCK PIO3
44. lator IRC oscillator i WDT CLOCK WDT SYSPLLCLKSEL DIVIDER system PLL clock select watchdog oscillator WDTUEN WDT clock update enable system oscillator USB PLL USB 48 MHz CLOCK is DIVIDER USBPLLCLKSEL USB clock select USBUEN USB clock update enable IRC oscillator system oscillator CLKOUT PIN CLOCK CLKOUT pin watchdog oscillator DIVIDER CLKOUTUEN CLKOUT update enable 002aae859 The USB clock is available on LPC1342 43 only Fig 7 LPC1311 13 42 43 clocking generation block diagram 7 17 1 1 Internal RC oscillator The IRC may be used as the clock source for the WDT and or as the clock that drives the system PLL and subsequently the CPU The nominal IRC frequency is 12 MHz The IRC is trimmed to 1 96 accuracy over the entire voltage and temperature range LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 22 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 7 17 1 2 7 17 2 7 17 3 7 17 4 7 17 5 LPC1311 13 42 43 0 Upon power up any chip reset or wake up from Deep power down mode the LPC1311 13 42 43 use the IRC as the clock source Software may later switch to one of the other available clock sources System oscillator The system oscillator can be used as the clock source for the CPU with or without using the PLL On the LPC134x the system oscillator must be used to provide the clock source to USB The system o
45. ld be chosen smaller accordingly to the increase in parasitics of the PCB layout Standard I O pad configuration Figure 28 shows the possible pin modes for standard I O pins The pull up and pull down resistors Rp and Rpg can be enabled or disabled The default value for each standard port pin is input with Rp enabled For details on pin modes and hysteresis control see the LPC13xx user manual enable 4d ouput E input pedl l ZX hysteresis control Vss 002aae828 Fig 28 Standard I O pad configuration LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 46 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 13 Package outline LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 detail X DIMENSIONS mm are the original dimensions A UNIT max A1 A2 A3 bp c 1 6 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION ISSUE DATE IEC JEDEC JEITA PROJECTION SOT313 2 136E05
46. level or rising edge or falling edge or both IOCONFIG block The IOCONFIG block allows selected pins of the microcontroller to have more than one function Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt s being enabled Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined Fast general purpose parallel I O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers Pins may be dynamically configured as inputs or outputs Separate registers allow setting or clearing any number of outputs simultaneously The value of the output register may be read back as well as the current state of the port pins LPC1311 13 42 43 use accelerated GPIO functions GPIO registers are a dedicated AHB peripheral and are accessed through the AHB so that the fastest possible I O timing can be achieved s Entire port value can be written in one instruction Additionally any GPIO pin total of up to 42 pins providing a digital function can be programmed to generate an interrupt on a level a rising or falling edge or both Features Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port Direction control of individual
47. lock diagram 6 Pinning information 6 1 Pinflng s exem ete teuit tenda 6 2 Pin description 7 Functional description 7 1 Architectural overview 7 2 ARM Cortex M3 processor 7 3 On chip flash program memory 7 4 On chip SHAM aaaaaaaaaaaan 7 5 Memory map eee 7 6 Nested Vectored Interrupt Controller NVIC 7 6 1 Features eee 7 6 2 Interrupt Sources a u unuauauauanan 7 7 IOCONFIG block sss 7 8 Fast general purpose parallel I O 7 8 1 Features 2 7 9 USB interface LPC1342 43 only 7 9 1 Full speed USB device controller 7 9 1 1 F atureS i lt uz usual beire nerasi 7 10 VART 3 236 cone bc ser TAK cared 7 10 1 Fealules eeri Seine peus d ex Rd 7 11 SSP serial I O controller 7 11 1 Features nananana nna 7 12 I2C bus serial O controller 7 12 1 Eeat l6s ess wr ra 7 13 10 bit ADC 7 13 1 Features 0 00 eee eee eee 7 14 General purpose external event COUnterS himers s enna nnn nnn 7 14 1 FeatureS 0 0200 eee 7 15 System tick timer 7 16 Watchdog timer 7 16 1 Feat tes cvs kr ERR 7 17 Clocking and power control 7 17 1 Crystal oscillators n n anaana 7 17 1 1 Internal RC oscillator 7 17 1 2 System oscillator 7 17 2 System PLL and USB PLL 7 17 3 Clock output 2 7 17 4 Wake up
48. o the core is stopped Resumption from the Sleep mode does not need any special sequence but re enabling the clock to the ARM core In Sleep mode execution of instructions is suspended until either a reset or interrupt occurs Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution Sleep mode eliminates dynamic power used by the processor itself memory systems and related controllers and internal buses Deep sleep mode In Deep sleep mode the chip is in Sleep mode and in addition analog blocks are shut down for increased power savings The user can configure the Deep sleep mode to a large extend selecting any of the oscillators any of the PLLs the USB PHY LPC134x only BOD the ADC and the flash to be shut down or remain powered during Deep sleep mode The user can also select which of the oscillators and analog blocks will be powered up after the chip exits from Deep sleep mode The GPIO pins up to 40 pins total serve as external wake up pins to a dedicated start logic to wake up the chip from Deep sleep mode The timing of the wake up process from Deep sleep mode depends on which blocks are selected to be powered down during deep sleep For lowest power consumption the clock source should be switched to IRC before entering Deep sleep mode all oscillators and PLLs should be turned off during deep sleep and the IRC should be selected as clock source when th
49. ock to an output pin Wake up process The LPC1311 13 42 43 begin operation at power up and when awakened from Deep power down mode by using the 12 MHz IRC oscillator as the clock source This allows chip operation to resume quickly If the main oscillator or the PLL is needed by the application software will need to enable these features and wait for them to stabilize before they are used as a clock source Power control The LPC1311 13 42 43 support a variety of power control features There are three special modes of processor power reduction Sleep mode Deep sleep mode and Deep power down mode The CPU clock rate may also be controlled as needed by changing clock sources reconfiguring PLL values and or altering the CPU clock divider value This allows a trade off of power versus processing speed based on application requirements In addition a register is provided for shutting down the clocks to individual on chip NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 23 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 7 17 5 1 7 17 5 2 7 17 5 3 7 18 7 18 1 LPC1311 13 42 43 0 peripherals allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application Selected peripherals have their own clock divider which provides even better power control Sleep mode When Sleep mode is entered the clock t
50. pdate via UARTO CAUTION A If level three Code Read Protection CRP3 is selected no future factory testing can be performed on the device 7 18 4 LPC1311_13_42_43_0 In addition to the three CRP levels sampling of pin PIOO_1 for valid user code can be disabled For details see the LPC13xx user manual Boot loader The boot loader controls initial operation after reset and also provides the means to program the flash memory This could be initial programming of a blank device erasure and re programming of a previously programmed device or programming of the flash memory by the application program in a running system The boot loader code is executed every time the part is reset or powered up The loader can either execute the ISP command handler or the user application code or on the LPC134x it can obtain the boot image as an attached MSC device through USB A LOW NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 25 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 7 18 5 7 18 6 7 18 7 7 18 8 7 19 LPC1311 13 42 43 0 level during reset at the PIOO 1 pin is considered an external hardware request to start the ISP command handler or the USB device enumeration The state of PIOO 3 determines whether the UART or USB interface will be used LPC134x only APB interface The APB peripherals are located on one APB bus AHB Lite The AHB Lite connects t
51. pproval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail 17 2 Disclaimers General Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors produ
52. pt vector area supports address remapping The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals Each peripheral of either type is allocated 16 kB of space This allows simplifying the address decoding for each peripheral LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 15 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 LPC1311 13 42 43 AHB peripherals 0x5020 0000 4GB OxFFFF FFFF 127 4 reserved ES reserved B 0x5004 0000 r4 0x5003 0000 asa AHB peripherals eo i R PES l 0x5002 0000 r 0x5001 0000 0x5000 0000 APB peripherals 0x4008 0000 31 19 reserved 0x4004 C000 reserved 0x4008 0000 1GB APB peripherals BCuPPOCW Y eee aa x4000 0000 reserved z 0x2400 0000 AHB SRAM bit band alias addressing 0x2200 0000 reserved 141 0x4003 8000 0 5 GB 0x2000 0000 10 18 reserved 0x4002 8000 0x4002 4000 USB LPC1342 43 only 0x4002 0000 reserved gt oe Ox1FFF 4000 reserved 16 kB boot ROM 0x1FFF 0000 0x4001 C000 reserved s 32 bit counter timer 1 0x4001 8000 32 bit counter timer 0 0x1000 2000 0x4001 4000 code D code 8 kB SRAM LPC1313 1343 0x1000 1000 memory space 4kB SRAM LPC1311 1342 16 bit counter timer 1 0x4001 0000 16 bit counter timer 0 0x4000 C000 1 0x1000 0000 0x
53. r circuits Input voltage must not exceed 1 8 V Output from the oscillator amplifier Ground 1 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis 2 1 C bus pads compliant with the I2C bus specification for I2C standard mode and I C Fast mode Plus 3 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors configurable hysteresis and analog input When configured as a ADC input digital section of the pad is disabled and the pin is not 5 V tolerant 4 Pad provides USB functions It is designed in accordance with the USB specification revision 2 0 Full speed and Low speed mode only Table 4 LPC1311 13 42 43 HVQFN33 pin description table Symbol RESET PIOO 0 PIOO_1 CLKOUT CT32B0_MAT2 USB_FTOGGLE LPC1311 13 42 43 0 Pi 2 n 3l Type UO UO Description RESET External reset input A LOW on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 PIOO 0 General purpose digital input output pin PIOO 1 General purpose digital input output pin A LOW level on this pin during reset starts the ISP command handler or the USB device enumeration USB on LPC1342 43 only see description of PIOO 3 CLKOUT Clock out pin CT32B0_MAT2 Match output 2 for 32 bit timer 0 USB FTOGGLE USB
54. r input for UART CT32B0 MATO Match output 0 for 32 bit timer 0 PIO1 7 General purpose digital input output pin TXD Transmitter output for UART CT32B0 MAT1 Match output 1 for 32 bit timer 0 PIO1 8 General purpose digital input output pin CT16B1 CAPO Capture input 0 for 16 bit timer 1 PIO1 9 General purpose digital input output pin CT16B1 MATO Match output 0 for 16 bit timer 1 PIO1 10 General purpose digital input output pin AD6 A D converter input 6 CT16B1 MAT Match output 1 for 16 bit timer 1 PIO1 11 General purpose digital input output pin AD7 A D converter input 7 PIO2 0 General purpose digital input output pin DTR Data Terminal Ready output for UART PIO3 2 General purpose digital input output pin PIO3 4 General purpose digital input output pin LPC1311 13 only PIO3 5 General purpose digital input output pin LPC1311 13 only USB DM USB bidirectional D line LPC1342 43 only USB DP USB bidirectional D line LPC1342 43 only NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 13 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 Table 4 LPC1311 13 42 43 HVQFN33 pin description table continued Symbol Vporo Vpp ava XTALIN XTALOUT Vss Pin Type Description 6 3 3 V input output supply voltage 29 l 3 3 V supply voltage to the internal DC DC converter and the ADC
55. re frequencies in active mode NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 34 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 LPC1311 13 42 43 0 001aac984 X X Conditions T amp 25 C active mode entered executing code from flash all peripherals enabled but not configured to run Fig 10 Supply current at different regulator supply voltages in active mode 001aac984 X X Conditions active mode entered executing code from flash supply voltage 3 3 V all peripherals enabled but not configured to run Fig 11 Supply current at different temperatures in active mode NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 35 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 10 3 Electrical pin characteristics LPC1311 13 42 43 0 002aae336 2000 500 o BR o co o 120 IL mA Conditions Vpp 0 3 3 Vi Tam 25 C Fig 12 I2C bus current ly vs V 002aae337 VoH V o D o B o o o co o 100 loH mA Conditions Vpp 0 3 3 V Tamb 25 C Fig 13 High drive output lou vs Vou on pin P
56. scillator operates at frequencies of 1 MHz to 25 MHz This frequency can be boosted to a higher frequency up to the maximum CPU operating frequency by the system PLL The ARM processor clock frequency is referred to as CCLK elsewhere in this document System PLL and USB PLL The LPC134x contain a system PLL and a dedicated PLL for generating the 48 MHz USB clock The LPC131x contain the system PLL only The system and USB PLLs are identical The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator CCO The multiplier can be an integer value from 1 to 32 The CCO operates in the range of 156 MHz to 320 MHz so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency The output divider may be set to divide by 2 4 8 or 16 to produce the output clock Since the minimum output divider value is 2 it is insured that the PLL output has a 50 duty cycle The PLL is turned off and bypassed following a chip reset and may be enabled by software The program must configure and activate the PLL wait for the PLL to lock and then connect to the PLL as a clock source The PLL settling time is 100 us Clock output The LPC1311 13 42 43 features a clock output function that routes the IRC oscillator the System oscillator the watchdog oscillator or the main cl
57. ssor which offers high performance and very low power consumption The ARM Cortex MG offers many new features including a Thumb 2 instruction set low interrupt latency hardware divide interruptable continuable multiple load and store instructions automatic state save and restore for interrupts tightly integrated interrupt controller and multiple core buses capable of simultaneous accesses Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously Typically while one instruction is being executed its successor is being decoded and a third instruction is being fetched from memory The ARM Cortex M3 processor is described in detail in the Cortex M3 Technical Reference Manual which is available on the official ARM website On chip flash program memory The LPC1311 13 42 43 contain 32 kB LPC1313 and LPC1343 16 kB LPC1342 or 8 kB LPC1311 of on chip flash memory On chip SRAM The LPC1311 13 42 43 contain a total of 8 kB LPC1343 and LPC1313 or 4 kB LPC1342 and LPC1311 on chip static RAM memory NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 14 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 7 5 Memory map The LPC134x incorporates several distinct memory regions shown in the following figures Figure 6 shows the overall map of the entire address space from the user program viewpoint following reset The interru
58. t driver CTS Clear To Send input for UART PIOO 8 MISO 2701 VO PIOO 8 General purpose digital input output pin CT16B0 MATO VO MISO Master In Slave Out for SSP O CT16BO MATO Match output 0 for 16 bit timer 0 PIOO 9 MOSI zalil VO PIOO 9 General purpose digital input output pin Md VO MOSI Master Out Slave In for SSP O CT16BO MAT Match output 1 for 16 bit timer 0 O SWO Serial wire trace output SWCLK PIOO 10 2901 SWCLK Serial wire clock and test clock TCK for JTAG interface SCK CT16B0 MAT2 VO PIOO 10 General purpose digital input output pin o SCK Serial clock for SSP O CT16BO MAT2 Match output 2 for 16 bit timer 0 TDI PIOO 11 32181 TDI Test Data In for JTAG interface ADO CT32B0 MATS VO PIOO 11 General purpose digital input output pin ADO A D converter input 0 O CT32BO MATS Match output 3 for 32 bit timer 0 TMS PIO1 0 33181 TMS Test Mode Select for JTAG interface AD1 CTS2B1 CAPO VO PIO1 0 General purpose digital input output pin AD1 A D converter input 1 CT32B1 CAPO Capture input 0 for 32 bit timer 1 TDO PIO1 1 34181 O TDO Test Data Out for JTAG interface AD2 CT32B1 MATO VO PIO1 1 General purpose digital input output pin AD2 A D converter input 2 O CT32B1 MATO Match output 0 for 32 bit timer 1 LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August
59. t multiplexing among 8 pins Power down mode Measurement range 0 V to Vpp sva 10 bit conversion time 2 2 44 us Burst conversion mode for single or multiple inputs Optional conversion on transition of input pin or Timer Match signal Individual result registers for each ADC channel to reduce interrupt overhead General purpose external event counters timers The LPC1311 13 42 43 includes two 32 bit counter timers and two 16 bit counter timers The counter timer is designed to count cycles of the system derived clock It can optionally generate interrupts or perform other actions at specified timer values based on four match registers Each counter timer also includes one capture input to trap the timer value when an input signal transitions optionally generating an interrupt Features A 32 bit 16 bit timer counter with a programmable 32 bit 16 bit prescaler Counter or timer operation One capture channel per timer that can take a snapshot of the timer value when an input signal transitions A capture event may also generate an interrupt Four match registers per timer that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation e Up to four external outputs corresponding to match registers with the following capabilities NXP B V 2009 All rights reserved
60. tes buffer RAM per endpoint see Table 5 Supports Control Bulk Isochronous and Interrupt endpoints Supports SoftConnect feature Double buffer implementation for Bulk and Isochronous endpoints Table 5 USB device endpoint configuration Logical Physical Endpoint type Direction Packet size Double buffer endpoint endpoint byte 0 0 Control out 64 no 0 1 Control in 64 no 1 2 Interrupt Bulk out 64 no 1 3 Interrupt Bulk in 64 no 2 4 Interrupt Bulk out 64 no 2 5 Interrupt Bulk in 64 no 3 6 Interrupt Bulk out 64 yes 3 7 Interrupt Bulk in 64 yes 4 8 Isochronous out 512 yes 4 9 Isochronous in 512 yes UART The LPC1311 13 42 43 contains one UART Support for RS 485 9 bit mode allows both software address detection and automatic address detection using 9 bit mode The UART includes a fractional baud rate generator Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 18 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 7 10 1 7 11 7 11 1 7 12 7 12 1 LPC1311 13 42 43 0 Features 16 byte receive and transmit FIFOs Register locations conform to 16C550 industry standard Receiver FIFO trigger points at 1 B 4 B 8 B and 14 B Built in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular val
61. the Vpp o supply voltage is present other I O pins per supply pin per ground pin 0 5Vppiio lt Vi 1 5Vpp 0 Tj 125 C based on package heat transfer not device power consumption human body model all pins 2 8 4 4 5 e Min 2 0 2 0 0 5 5000 Max 3 6 3 6 6 0 Vpp o 0 5 100 100 100 150 1 5 5000 Unit mA mA mA C 1 The following applies to the limiting values a This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum b Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted 2 Including voltage on outputs in 3 state mode B Not to exceed 4 6 V 4 The peak current is limited to 25 times the corresponding maximum current 5 Dependent on package type 6 Human body model equivalent to discharging a 100 pF capacitor through a 1 5 KQ series resistor LPC1311_13_42_43_0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 27 of 52 NXP Semiconductors LPC1 31 1 1 3 42 43 9 Thermal characteristics 9 1 Thermal characteristics The average chip junction temperat
62. ues Fractional divider for baud rate control auto baud capabilities and FIFO control mechanism that enables software flow control implementation Support for RS 485 9 bit mode Support for modem control SSP serial I O controller The LPC1311 13 42 43 contain one SSP controller The SSP controller is capable of operation on a SSP 4 wire SSI or Microwire bus It can interact with multiple masters and slaves on the bus Only a single master and a single slave can communicate on the bus during a given data transfer The SSP supports full duplex transfers with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master In practice often only one of these data flows carries meaningful data Features Compatible with Motorola SPI 4 wire Texas Instruments SSI and National Semiconductor Microwire buses Synchronous serial communication Master or slave operation 8 frame FIFOs for both transmit and receive 4 bit to 16 bit frame I2C bus serial I O controller The LPC1311 13 42 43 contain one I2C bus controller The I2C bus is bidirectional for inter IC control using only two wires a serial clock line SCL and a serial data line SDA Each device is recognized by a unique address and can operate as either a receiver only device e g an LCD driver or a transmitter with the capability to both receive and send information such as memory Transmitters and or receivers can operate
63. ure Ty C can be calculated using the following equation T Tip PpX Rag ap 1 Tamb ambient temperature C Ria the package junction to ambient thermal resistance C W e Pp sum of internal and I O power dissipation The internal power dissipation is the product of Ipp and Vpp The I O power dissipation of the I O pins is often small and many times can be negligible However it can be significant in some applications Table 7 Thermal characteristics Vpp 2 4 V to 3 6 V Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Rtn j a thermal resistance from LOFP48 HVOFN33 S lt tbd gt C W junction to ambient packages Titmax maximum junction 150 C temperature LPC1311 13 42 43 0 NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 28 of 52 NXP Semiconductors LPC1311 13 42 43 10 Static characteristics Table 8 Static characteristics Tamb 40 C to 85 C unless otherwise specified Symbol Vpp ava Vpp o Ipp Ippo Parameter supply voltage 3 3 V input output supply voltage supply current I O supply current Standard port pins and RESET pin li liu loz Vi LPC1311 13 42 43 0 LOW level input current HIGH level input current OFF state output current input voltage output voltage HIGH level input voltage LOW level inp
64. ut voltage hysteresis voltage HIGH level output voltage Conditions Active mode Vpp ava 3 3 V Tamb 25 C code while 1 executed from flash CCLK 12 MHz CCLK 72 MHz Sleep mode Vpp ava 3 3 V Tamb 25 C while 1 executed from flash CCLK 12 MHz Deep sleep mode Vpp ava 3 3 V Tamb 25 C Deep power down mode Vpp 3va 3 3 V Vpp o 3 3 V Tamb 25 C Deep power down mode Vpp ava 3 3 V Vpp o 3 3 V Tamo 25 C Vi 20 V on chip pull up resistor disabled Vi Vpp ioy on chip pull down resistor disabled Vo 0 V Vo Vpp oy on chip pull up down resistors disabled pin configured to provide a digital function output active lou 4mA 211114 BIAIS 211114 6 D 7118 12 Min 2 0 2 0 0 4 Vpb o 0 4 Typlil 3 3 3 3 17 30 220 20 Max Unit 3 6 V 3 6 V mA mA mA uA nA nA 3 uA 3 uA 3 uA 5 5 V Vpb o V V 0 8 V V V NXP B V 2009 All rights reserved Preliminary data sheet Rev 00 14 20 August 2009 29 of 52 NXP Semiconductors LPC1311 13 42 43 Table 8 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified Symbol VoL loH Parameter LOW level output voltage HIGH level output current LOW level output current HIGH level short circuit output current LOW level short circuit output current

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