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1. 25 30 35 40 45 50 55 60 SUPPLY VOLTAGE V 1196 98 606 Gain Error vs Reference Voltage 0 5 0 0 5 1 0 15 20 25 3 0 35 40 45 5 0 REFERENCE VOLTAGE V 1196 98 G09 AL Ue 7 LTC1196 LTC1198 TYPICAL PERFORMANCE CHARACTERISTICS Gain vs Supply Voltage 0 5 19 _ 04 TA 25 P 3MHz 17 gt 02 S 15 amp 13 lt 0 2 x a 2 04 5 02 2 5 03 7 0 4 0 5 25 30 35 40 45 50 55 640 SUPPLY VOLTAGE V 1196 98 610 Minimum Clock Rate for 5 25 30 35 40 45 50 55 60 Maximum Clock Frequency vs Supply Voltage TA 25 VREF Voc SUPPLY VOLTAGE V 1196 98 G11 ADC Noise vs Reference and 0 1LSB Error Supply Voltage 100 0 35 90 Vcc 5 TA 25 C 5V az 0 30 Vngr Voc lt 80 an gt 70 0 25 g 60 5 020 50 a 40 5 015 30 E 0 10 20 5 T 10 i 0 0 55 35 15 5 25 45 65 85 105 125 25 30 35 40 45 50 55 60 TEMPERATURE C SUPPLY VOLTAGE V 1196 98 G13 1196 98 014 Digital Input Logic Threshold v
2. 8 50 es Vggr Voc 2 7V g 7 383kHz LTC1196 44 fsMPL 287kHz LTC1198 pty c EE m Veer 5V m 5 fsmpL 1MHz LTC1196 E SMPL 750kHz LTC1198 4 s 3 z 2 E 1 0 1k 10k 100k 1M INPUT FREQUENCY Hz 1196 98 G24 AL Ue LTC1196 LTC1198 ABSOLUTE MAXIMUM RATINGS notes 1 2 Supply Voltage Voc to GND 7V Operating Temperature Range Voltage LTC1196 1AC LTC1198 1AC LTC1196 1BC Analog Reference 0 3V to Vec 0 3V LTC1198 1BC LTC1196 2AC LTC1198 2AC Digital INDU S 0 3V to 7V LTC1196 2BC LTC1198 2BC 0 C to 70 C Digital Outputs 0 3V to Voc 0 3V Storage Temperature Range 65 C to 150 C Power 015 500mW Lead Temperature Soldering 10 5 300 C PACKAGE ORDER INFORMATION ORDER PART ORDER PART NUMBER NUMBER TOP VIEW TOP VIEW T A LTC1196 1ACS8 A LTC1198 1ACS8 Ww Hak LTC1196 1BCS8 5 A cik LTC1198 1BCS8 Me ZI LTC1196 2ACS8 T zm LTC1198 2ACS8 ze LTC1196 2BCS8 afa oy LTC1198 2BCS8 8 LEAD PLASTIC SOIC 58 PART MARKING PLASTIC SO
3. UNITS No Missing Codes Resolution e 8 8 Bits Offset Error e 1 2 1 LSB Linearity Error Note 3 1 2 1 158 Full Scale Error 1 2 1 LSB Total Unadjusted Error Note 4 LTC1196 Vper 2 500V 1 2 t1 LSB LTC1198 Vcc 2 700V Analog and REF Input Range LTC1196 0 05V to Voc 0 05V V Analog Input Leakage Current Note 5 ti ti DIGITAL DC ELECTRICAL CHARACTERISTICS Vec 2 7V 2 5V unless otherwise noted SYMBOL PARAMETER CONDITIONS MIN MAX UNITS Vin High Level Input Voltage Vec 3 6V e 1 9 V VIL Low Level Input Voltage Vec 2 7V 0 45 V High Level Input Current Vin Voc 2 5 li Low Level Input Current Vin OV 2 5 High Level Output Voltage Vec 2 7V 10 100A e 2 3 2 60 V Vec 2 7V 10 21 2 45 V VoL Low Level Output Voltage Vcc 2 7V 10 400A 0 3 V loz Hi Z Output Leakage CS High e 3 ISOURCE Output Source Current Vout OV 10 mA Output Sink Current Vout Vec 15 mA IREF Reference Current LTC1196 CS Vec e 0 001 3 0 HA SMPL SMPL MAX e 025 05 mA lec Supply Current CS 3 3V LTC1198 Shutdown e 0 001 3 0 CS Voc 3 3V 1701196 1 5 4 5 mA 1 LTC1196 LTC1198 2 0 6 0 mA LI Ue LTC1196 LTC1198 DYNAM IC ACCURACY Voc 2 71 2 5V fork as defined in Recommended Operating Conditions unle
4. as defined in Recommended Operating Conditions unless otherwise noted LTC1196 LTC1198 SYMBOL PARAMETER CONDITIONS MIN MAX MIN TYP MAX UNITS S N D Signal to Noise Plus Distortion 500kHz 1MHz Input Signal 47 45 47 45 dB THD Total Harmonic Distortion 500kHz 1MHz Input Signal 49 47 49 47 dB Peak Harmonic or Spurious Noise 500kHz 1MHz Input Signal 55 48 55 48 dB IMD Intermodulation Distortion fina 499 37kHz 51 51 dB fi 502 446kHz Full Power Bandwidth 8 8 MHz Full Linear Bandwidth S N D gt 4408 1 1 MHz Vec 5V VREF 5V fork ferax as defined in Recommended Operating Conditions unless otherwise noted LTC1196 1 LTC1196 2 LTC1198 1 LTC1198 2 SYMBOL PARAMETER CONDITIONS MIN MAX MIN MAX UNITS tconv Conversion Time See Figures 1 2 600 710 ns 710 900 ns fsmpL max Maximum Sampling Frequency LTC1196 1 20 1 00 MHz LTC1196 e 100 0 80 MHz LTC1198 0 90 0 75 MHz LTC1198 075 0 60 MHz Delay Time to Dour Data Valid Ci oAp 20pF 55 64 68 78 ns e 73 94 ns ipis Delay Time CST to Dour Hi Z e 70 120 88 150 ns ten Delay Time CLK to Dour Enabled CLoap 20pF 30 50 43 63 ns thoo Time Output Data Remains Valid CLoap 20pF 30 45 30 55 ns After CLKT tr Dour Fall Time Ci oAp 20pF e 5 15 10 20 ns tf Doyr Rise Time Ci oAp 20pF e 15 10 20 ns CIN Input Capacita
5. 2 d 15 287kHz LTC1198 S D Voc 5V IN amp gt E 5 fsmpL 1MHz 1701196 25 750kHz LTC1198 0 0 4 o 34 2 2 3 D PEE E m m E 4 i zs Ta 25 C 0 5 5 95 o LL 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 1k 10k 100k 1M CODE CODE INPUT FREQUENCY Hz 1196 98 G22 1196 98 G23 119698 924 FFT Output of 455kHz AM Signal 4096 Point FFT Plot at 5V 4096 Point FFT at 2 7V Digitized at 1MSPS 0 10 Voc 5V fin 455kHz WITH 20kHz 20 fsmpL 1MHz 780 S 40 p 50 60 4 70 d ul MIR li pa 100 0 100 200 300 400 500 0 50 100 150 200 0 100 200 300 400 500 FREQUENCY kHz FREQUENCY kHz FREQUENCY kHz 1196 98 G25 1196 98 G26 1196 98 G27 LI Ue 9 LTC1196 LTC1198 TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Feedthrough vs Ripple Frequency Power Supply Feedthrough vs Ripple Frequency S N D vs Reference Voltage and Input
6. 17 LTC1196 LTC1198 APPLICATIONS INFORMATION Clock Frequency The maximum recommended clock frequency is 14 4MHz at 25 C for the LTC1196 LTC1198 running off a 5V supply With the supply voltage changing the maximum clock frequency for the devices also changes see the typical curve of Maximum Clock Rate vs Supply Voltage If the supply is reduced the clock rate must be reduced also At 3V the devices are specified with a 5 4MHz clock at 25 Mixed Supplies It is possible to have a digital system running off a 5V supply and communicate with the LTC1196 LTC1198 operating on a 3V supply Achieving this reduces the outputs of Dour from the ADCs to toggle the equivalent input of the digital system The CS CLK and D y inputs of the ADCs will take 5V signals from the digital system without causing any problem see typical curve of Digital Input Logic Threshold vs Supply Voltage With the LTC1196 operating on a 3V supply the output of Doyr only goes between and 3V This signal easily meets TTL levels see Figure 6 MPU e g 8051 P1 4 DIFFERENTIAL INPUTS P1 3 COMMON MODE RANGE TO 3V N p is 1196 98 F06 Figure 6 Interfacing a 3V Powered LTC1196 to a 5V System BOARD LAYOUT CONSIDERATIONS Grounding and Bypassing The LTC1196 LTC1198 are easy to use if some care is taken They should be used with an analog ground plane and single point grounding techniques The GND pin should be tied dir
7. 21 If the two input sine waves are equal in magnitudes the value in dB ofthe 2nd order IMD products can be expressed by the following formula amplitude f f IMD f fp 20109 ias st amplitude at f For input frequencies of 499kHz and 502kHz the IMD of the LTC1196 LTC1198 is 51dB with a 5V supply Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spec tral component excluding the input signal and DC This value is expressed in dBs relative to the RMS value ofa full scale input signal Full Power and Full Linear Bandwidth The full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is re duced by 3dB for a full scale input The full linear bandwidth is the input frequency at which the effective bits rating of the ADC falls to 7 bits Beyond this frequency distortion of the sampled input signal increases The LTC1196 LTC1198 have been designed to optimize input bandwidth allowing the ADCs to undersample input signals with frequencies above the converters Nyquist Frequency 22 LI VIE LTC1196 LTC1198 APPLICATIONS INFORMATION 3V VERSUS 5V PERFORMANCE COMPARISON Table 1 shows the performance comparison between 3V and 5V supplies The power dissipation drops by a factor of five when the supply is reduced to 3V The converter slows down somewhat but still gives excellent perfor mance on a 3V rail With a 3V supply th
8. Eight registers control the operation of the Test ASIC Appendix A lists the Test ASIC s register description Note that most write registers cannot be read back It is up to the programmer to maintain an image of the write registers since a read modify write operation is not possible for most of the register bits Testing the 16 bit PC Card interface involves writing various test patterns to the PCCtest unit through the host socket controller Status read back through these registers verify the functionality of the various portions of the interface 3 1 Initializing the PCCtest The PCCtest must be powered through the host socket before any test operations can begin The PCCtest model 172 can be powered to 3 3 or 5 0 Volts The PCCtest 172 requires a power on reset to initialize the internal operating circuitry Care must be taken when switching operating voltages on the PCCtest Do not switch from 3 3V to 5 0V or 5 0V to 3 3V without allowing the power to go to first go to OV PCCtest on board circuitry requires a minimum of 1200ms after Vcc is stable to initialize Note Vppl and Vpp2 can be measured by the PCCtest but are not required for PCCtest operation 3 2 Opening a Memory and I O Window to the PCCtest In order to access the test resources in the PCCtest an 8 bit attribute memory and an 8 bit I O window must be opened to the PCCtest Both an I O and memory window is required to fully test the PC Card interface The PCCtest contains
9. eight 8 bit registers These registers are accessed as 8 consecutive bytes Note For information on opening an I O window consult your socket controller chip user s manual A memory window with a length of at least 8 bytes is required to test the interface s memory interface Most socket controllers provide a minimum window length of 4K bytes 3 2 1 PCCtest Memory and I O Map The PCCtest 172 supports all three address spaces defined in the PC Card Standard On power up the PCCtest 172 responds to attribute memory accesses Attribute memory reads from address OH FFH access the on board Card Information Structure CIS The CIS contains tuples that identify the PCCtest 172 Appendix B contains a listing of the tuples contained in the CIS Attribute Memory addresses 100H 107H contains the control registers used to test the PC Card Interface The function of these registers are described in Appendix A Attribute Space OH OFFH Card Information Structure 100H 107H Control Registers 108H FFFFFFFH Control Registers mirrored Table 3 2 1 Attribute Memory Space The MODE register offset 6 controls which address spaces the PCCtest responds to Once the PCCtest unit it programmed out of its power on mode the control registers are accessed through I O or common memory space When accessing these registers in I O or common memory mode the registers appear at offset 0 Since there is no address decode for I O or common memory mode th
10. 2 SEE NOTE 2 10 NOTE 1 WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL NOTE 2 WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL 1196 98 06 12 AL VIE LTC1196 LTC1198 TEST CIRCUITS Voltage Waveforms for ten LTC1196 CLK Dout 1196 98 TCO7 Voltage Waveforms for ten LTC1198 CLK 1196 98 08 AL YR 13 LTC1196 LTC1198 APPLICATIONS INFORMATION OVERVIEW The LTC1196 LTC1198 are 600ns sampling 8 bit A D converters packaged in tiny 8 pin SO packages and oper ating on 3V to 6V supplies The ADCs draw only 10mW from a 3V supply 50mW from a 5V supply Both the LTC1196 and the LTC1198 contain an 8 bit switched capacitor ADC a sample and hold and a serial port see Block Diagram The on chip sample and holds have full accuracy input bandwidths of 1MHz Although they share the same basic design the LTC1196 and LTC1198 differ in some respects The LTC1196 has a differential input and has an external reference input pin It can measure signals floating on a DC common mode voltage and can operate with reduced spans below 1V The 1701198 has a 2 channel input multiplexer and can con vert either channel with respect to ground or the difference between the two It also automatically powers down when not performing co
11. 2 7V supply and 5MHz CLK NULL 7 HORIZONTAL 1500ns DIV VERTICAL 5V DIV 1196 98 F16 Figure 16 Scope Trace the LTC1198 Running Off 5V Supply in the Circuit of Figure 15 MEAN CLK mum VERTICAL 5V DIV NULL MSB LSB BITS B7 BO HORIZONTAL 500ns DIV 1196 98 F17 Figure 17 Scope Trace the LTC1198 Running Off 2 7V Supply in the Circuit of Figure 15 Software Description The software configures and controls the serial port of the 5320025 The code first sets up the interrupt and reset vectors On reset the TMS320C25 starts executing code at the label INIT Upon completion of a 16 bit data transfer an inter ruptis generated and the DSP will begin executing code at the label RINT In the beginning the code initializes registers in the TMS320C25 that will be used the transfer routine The interrupts are temporarily disabled The data memory page pointer register is set to zero The auxiliary register pointer is loaded with one and auxiliary register one is loaded with the value 200 hexadecimal This is the data memory location where the data from the LTC1198 will be stored The interrupt mask register IMR is configured to recognize the RINT interrupt which is generated after receivingthe last of 16 bits on the serial port This interrupt is still disabled atthis time Thetransmit framing synchro nizat
12. 3 988 Y 1 2 3 4 0 010 0 020 lt 0 053 0 069 0 254 0 508 1 346 1 752 0 008 0 010 0 004 0 010 0 203 0 254 0 8 0 101 0 254 Lo mun lt 00180290 0 014 0 019 3 0 050 0 355 0 483 1270 BSC 508 0493 Information furnished by Linear Technology Corporation is believed to be accurate and reliable y LINTAR However no responsibility is assumed for its use Linear Technology Corporation makes no represen TECHNOLOGY tation thatthe interconnection of its circuits as described herein will not infringe on existing patent rights LTC1196 LTC1198 NORTHEAST REGION Linear Technology Corporation One Oxford Valley 2300 E Lincoln Hwy Suite 306 Langhorne PA 19047 Phone 215 757 8578 FAX 215 757 5631 Linear Technology Corporation 266 Lowell St Suite B 8 Wilmington MA 01887 Phone 508 658 3881 FAX 508 658 2701 FRANCE Linear Technology S A R L Immeuble Le Quartz 58 Chemin de la Justice 92290 Chatenay Malabry France Phone 33 1 41079555 FAX 33 1 46314613 GERMANY Linear Techonolgy GMBH Untere Hauptstr 9 D 85386 Eching Germany Phone 49 89 3197410 FAX 49 89 3194821 U S Area Sales Offices SOUTHEAST REGION Linear Technology Corporation 17060 Dallas Parkway Suite 208 Dallas TX 75248 Phone 214 733 3071 FAX 214 380 5138 CENTRAL RE
13. CIS Page B 1 Appendix B PCCtest 172 Rev 1 01 CIS This section describes the Card Information Structure CIS stored in the attribute memory space of the PCCtest 172 Byte OOH Tuple link Device Info Field 1 Function Specific Memory type 16K buffer 250nS 2 units of 8K 16K End of tuple CISTPL VERS 1 Tuple link Byte OFFH E Peau oy gt r m mimimimimimiu r m mimimimiu 200052 03 1994 2002 Sycard Technology Page 2 Appendix B PCCtest 172 CIS 52H 76H 318 1 2 E O oo o O 52H 65H 76H 20H 31H 2EH 30H 31H OFF 20H 04H 16H 02H 72H 01H 21H 02H FEH 14H 04H 16H Manufacturer 02H Manufacturer 1D SB 72H Product Number L5B o 01H Product Number O S zig cisreL FUNG ID 02H Link O gg Rm E CISTPL NO LINK OOO 5CH 5EH 62H 64H 6AH 6CH 6EH 70H 72H 74H 76H 78H 7AH 7EH 82H 84H 1994 2002 Sycard Technology M200052 03 Appendix B PCCtest 172 CIS Page B 3 Appendix B 1 PCCtest 172 Rev 1 02 CIS This
14. per conversion These current spikes settle quickly and do not cause a problem However if source resis tances larger than 1000 are used or if slow settling op amps drivethe inputs care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins Input Settling The input capacitor of the LTC1196 is switched onto input at the end of the conversion and samples the input signal until the conversion begins see Figure 1 The input capacitor ofthe LTC1198 is switched onto input during the sample phase tewp see Figure 7 The sample phase is 2 5 CLK cycles before conversion starts The voltage on the input must settle completely within for the LTC1196 LTC1198 Minimizing Rsounce will improve the input settling time If a large input source resis tance must be used the sample time can be increased by allowing more time between conversions for the LTC1196 or by using a slower CLK frequency for the 1701198 LT Ue 19 LTC1196 LTC1198 APPLICATIONS INFORMATION Input Settling At the end of the the input capacitor switches to the input and conversion starts see Figures 1 and 7 During the conversion the input voltage is effectively held by the sample and hold and will not affect the conversion result However it is critical that input voltage settle complet
15. that do not support 8 bit I O windows e g StrongArm SA 1100 On power up the PCCtest 170 and 172 will put the WP IOIS 16 signal into a low state Socket controllers that do not support 8 bit windows will use the IOIS16 signal to determine if the register is 16 bit or 8 bit These socket controllers will not be able to access the odd numbered registers in the PCCtest 170 Since the control of the WP IOIS 16 is located in an odd numbered register in the PCCtest 170 it is impossible to put the card into 8 bit mode The PCCtest 172 solves this problem by placing the WP IOIS 16 control in an even numbered register Table 1 1 1 illustrates the differences between the PCCtest 170 and 172 Control Bit PCCtest 170 PCCtest 172 WP IOIS163 MISC Register offset 3 bit 6 CNTL Register offset 4 bit O RDY BSY IREQ MISC Register offset 3 bit 7 CNTL Register offset 4 bit 1 ADCCE CNTL Register offset 4 bit MISC Register offset 3 bit 6 ADCLK CNTL Register offset 4 bit 1 MISC Register offset 3 bit 7 Table 1 1 1 PCCtest 170 and 172 differences In addition to register changes the PCCtest 172 CIS has been modified to identify the model 2 0 Architecture of the PCCtest Figure 2 0 1 Illustrates the architecture of the PCCtest model 172 The functional blocks be partitioned in to the following major sub sections e Tester ASIC Test ASIC e Converter and Logic interfaces to the PCCtest unit is via eight registers c
16. 196 98 G25 Figure 10 LTC1196 Non Averaged 4096 Point FFT Plot Signal to Noise Ratio The Signal to Noise plus Distortion Ratio S N D is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other fre quency components at the ADC s output The output is band limited to frequencies above DC and below one half the sampling frequency Figure 10 shows a typical spec tral content with a 882kHz sampling rate Effective Number of Bits The Effective Number of Bits ENOBs is a measurement of the resolution of an ADC and 15 directly related to S N D by the equation N S N D 1 76 6 02 where N is the effective number of bits of resolution and S N D is expressed in dB At the maximum sampling AL Ue 21 LTC1196 LTC1198 APPLICATIONS INFORMATION rate of 1 2MHz with a 5V supply the LTC1196 maintains above 7 5 ENOBs at 400kHz input frequency Above 500kHz the ENOBs gradually decline as shown in Figure 11 due to increasing second harmonic distortion The noise floor remains low Veer 2 7V MPL 383kHz LTC1196 287kHz LTC1198 REF Voc SV fsmpL 1MHz LTC1196 SMPL 750kHz LTC1198 ap N s EFFECTIVE NUMBER OF BITS ENOBs N C 1k 10k 100k 1M INPUT FREQUENCY Hz 1196 9
17. 196 LTC1198 are permanently configured for unipolar only The input span and code assignment for this conversion type are shown in the following figures Unipolar Transfer Curve 11111111 11111110 00000001 00000000 Q lt 9511 FEITA FEITA 433A 1196 98 A104 Unipolar Output Code INPUT VOLTAGE OUTPUT CODE INPUT VOLTAGE Vnrr 5 000V 11111111 1LSB 4 9805V 11111110 VREF 2158 4 9609V 00000001 1LSB 0 0195V 00000000 OV OV 1196 98 105 Operation with Diy and Doyr Tied Together The LTC1198 can be operated with and Dour tied together This eliminates one of the lines required to communicate to the digital systems Data is transmitted in both directions on a single wire The pin of the digital systems connected to this data line should be configurable as either an input or an output The LTC1198 will take control of the data line and drive it low on the 5th falling CLK edge after the start bit is received see Figure 4 Therefore the port line of the digital systems must be switched to an input before this happens to avoid a conflict REDUCING POWER CONSUMPTION The LTC1196 LTC1198 can sample at up to a 1MHz rate drawing only 50mW from a 5V supply Power consump tion can be reduced in two ways Using a 3V supply lowers the power consumption on both devices by a factor of five to 10mW The LTC1198 can reduce power even further because it shuts down whenever it is not conver
18. 320 25 which is 5MHz The supply voltage for 5MHz CLK CHO CH1 1196 98 F15 Figure 15 Interfacing the 1701198 to the TMS320C25 DSP the 1701198 in Figure 15 can be 2 7V 6V with fci 5MHz At 2 7V folk 5MHz will work at 25 C See Recommended Operating Conditions for limits over tem perature Hardware Description The circuit works as follows the LTC1198 clock line controls the A D conversion rate and the data shift rate Data is transferred a synchronous format over D y and Dour The serial port of the 5320 25 is compatible with that of the LTC1198 The data shift clock lines CLKR CLKX are inputs only The data shift clock comes from an external source Inverting the shift clock is necessary because the LTC1198 and the 5320625 clock the input data on opposite edges The schematic of Figure 15 is fed by an external clock source The signal is fed into the CLK pin of the LTC1198 directly The signal is inverted with a 74HC04 and then applied to the data shift clock lines CLKR CLKX The framing pulse of the 5320 25 is fed directly to the CS of the 1701198 DX and DR are tied directly to Diy and Doyr respectively 24 LI UE LTC1196 LTC1198 TYPICAL APPLICATIONS The timing diagram of Figure 16 was obtained from the circuit of Figure 15 The CLK was 5MHz for the timing diagram and the TMS320C25 clock rate was 40MHz Figure 17 shows the timing diagram with the LTC1198 running off a
19. 7 2 BIT 1 CONVERTER ENA CS 1196 98 F12 Figure 12 An Equivalent Circuit of the 5064 goes high for one CLK cycle with every 12 CLK cycles The inverted signal EN of the CS output makes the 8 bit data available on the BO B7 lines Figures 13 and 14 show the interconnection between the LTC1196 and EPM5064 and the timing diagram of the signals between these two devices The CLK frequency in this circuit can run up to CLK MAX of the LTC1196 RESERVE PINS OF EPM5064 2 4 8 15 20 22 24 26 30 9 13 21 31 32 43 1196 98 F13 Figure 13 Intefacing the LTC1196 to the Altera EPM5064 PLD AL Ue 23 LTC1196 LTC1198 TYPICAL APPLICATIONS LT ck FLL LLU LU LL LU LL LL LLL 5571 1 B7 B6 B5 B4 ___ _ _______ B3 B2 BO Selene Pe 70 140 210 280 350 420 490 560 630 700 770 840 910 980 1050 1120 ME ns 1196 98 F14 Figure 14 The Timing Diagram Interfacing the LTC1198 to the 5320 25 DSP Figure 15 illustrates the interface between the LTC1198 8 bit data acquisition system and the TMS320C25 digital signal processor DSP The interface which is optimized for speed of transfer and minimum processor supervi sion can complete a conversion and shift the data in 4 5 With fcLk 5MHz The cycle time 4us of each conversion is limited by maximum clock frequency of the serial port ofthe 5
20. 8 G24 Figure 11 Effective Bits and S N D vs Input Frequency Total Harmonic Distortion Total Harmonic Distortion THD is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself The out of band harmonics alias into the frequency band between DC and half of the sampling frequency THD is defined as 2 02 SES Mi 1 THD 20100 where V4 is the RMS amplitude of the fundamental fre quency and Vo through are the amplitudes of the second through the harmonics The typical THD speci fication in the Dynamic Accuracy table includes the 2nd through 5th harmonics With a 100kHz input signal the LTC1196 LTC1198 have typical THD of 50dB and 49dB with Voc 5V and Vec respectively Intermodulation Distortion Ifthe ADC input signal consists of more than one spectral component the ADC transfer function nonlinearity can produce intermodulation distortion IMD in addition to THD IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency If two pure sine waves of frequencies fa and fp are applied to the ADC input nonlinearities in the ADC transfer func tion can create distortion products at sum and difference frequencies of mf where m and n 0 1 2 3 etc For example the 2nd order IMD terms include fa fp and fa fp while 3rd order IMD terms include 21 fp 214 fp fa 2 and fa
21. 87 9887 nj nj Hil dD OF Of Of Cf Co A OO FP SY WJ FRIDI DJ RP N LGI GI eo AGI bl hl bI bI eG GI A Lc OFFH TH GJ GI H PCE IR Interrupt Mask 1 All interrupts allowed PCE IR Interrupt Mask 2 A interrupts allowed CISTPL END That s all folks 1994 2002 Sycard Technology M200052 03 Appendix C Linear Technology LTC 1196 A D Converter Page C 1 Appendix C Linear Technology LTC 1196 A D Converter M200052 03 1994 2002 Sycard Technology TECHNOLOGY FEATURES High Sampling Rates 1MHz LTC1196 750kHz LTC1198 Low Cost S0 8 Plastic Package Single Supply 3V and 5V Specifications Low Power 10mW at 3V Supply 50mW at 5V Supply Auto Shutdown 1nA Typical 1701198 1 2LSB Total Unadjusted Error over Temperature 3 Wire Serial 1 0 1V to 5V Input Span Range 1701196 Converts 1MHz Inputs to 7 Effective Bits Differential Inputs LTC1196 2 Channel MUX 1761198 APPLICATIONS High Speed Data Acquisition Disk Drives Portable or Compact Instrumentation L L L ow Power or Battery Operated Systems D LTC1196 LTC1198 8 Bit SO 8 IMSPS ADCs with Auto shutdown Options DESC
22. C1196 LTC1198 Operating on 5V and 2 7V Supplies When the CS pin is high supply voltage the LTC1198 is in shutdown mode and draws only leakage current The status of the D y and CLK input has no effect on the supply current during this time There is no need to stop Diy and CLK with CS high they can continue to run without drawing current Minimize CS Low Time LTC1198 In systems that have significant time between conver sions lowest power drain will occur with the minimum CS low time Bringing CS low transfering data as quickly as possible then bringing it back high will result in the lowest current drain This minimizes the amount of time the device draws power OPERATING ON OTHER THAN 5V SUPPLIES The LTC1196 LTC1198 operate from single 2 7V to 6V supplies To operate the LTC1196 LTC1198 on other than 5V supplies a few things must be kept in mind Input Logic Levels The input logic levels of CS CLK and D y are made to meet TTL on 5V supply When the supply voltage varies the input logic levels also change see typical curve of Digital Input Logic Threshold vs Supply Voltage For these two ADCs to sample and convert correctly the digital inputs have to be in the logical low and high relative to the operating supply voltage If achieving micropower consumption is desirable on the 1701198 the digital inputs must go rail to rail between supply voltage and ground see Reducing Power Consumption section AL Ue
23. CCtest provides a flexible timing measurement circuit providing 5Ons resolution This circuit can measure from the rising falling edge of any of the control strobes to the rising falling edge of the same set of signals The following table lists the various control strobes that can be measured Signal Description TCR Value Memory Read Strobe Memory Write Strobe Table 3 7 1 Common Strobe Measurements TCR Values The signal and polarity that start the timer is selected via the STR 2 0 and the STRPOL bits in the TCR register The STP 2 0 and STPPOL bits determine the signal that stops the timer The following examples illustrate the values programmed into the TCR register offset 2 for various timing measurements 1994 2002 Sycard Technology M200052 03 PCCtest 172 Technical Reference Manual Page 7 TCR Value Falling edge of CE1 to rising edge of Pulse width of IORD 6EH Pulse width of IOWR 7FH Rising edge of 1 to rising edge of 20H Pulse width of WE 19H Table 3 7 2 Various Strobe Measurements TCR Values As with the address latching circuit the timing logic is armed and the next access to the card is measured The timing measurement is armed through an I O write to the TRST register offset 5 Once armed the timer will start on first instance of the value programmed into the STR 2 0 register The value can be read from the TIM register offset 6 The value read from the TIM register is mult
24. Frequency 0 21 _ 30 TA 25 C 10 VRIPPLE 20mV 10 PLE 10mV folk 12MHz Hz 6 fin 200kHz 20 20 8 a e fin 100kHz 5 30 5 30 e a 3 E 4 amp c B W 3 H H S 50 _50 30 60 60 70 70 25 1k 10k 100k 1M 1k 10k 100k 1M 125 175 2 25 2 75 325 3 75 425 4 75 5 25 RIPPLE FREQUENCY Hz RIPPLE FREQUENCY Hz REFERENCE VOLTAGE V 1196 98 G28 1196 98 G29 1196 98 G30 Intermodulation Distortion at 2 7V Intermodulation Distortion at 5V S N D vs Input Level 0 0 50 Voc 2 7V _ Vec 5V VREF Vec 5V 10 H 100kHz 10 ft 200kHz fin 20 f2 110kHz 20 f2 210kHz S 40 fsyp 1MHz SMPL 420kHz SMPL 750kHz cc 30 30 2 40 40 a 30 3 3 E 50 E 50 a 60 60 amp 20 zm 70 70 APTUM 80 Fal dui 80 d 10 90 90 1 TI T n 100 100 0 0 50 100 150 200 250 0 100 200 300 400 40 35 30 25 20 15 10 5 0 FREQUENCY kHz FREQUENCY kHz INPUT LEVEL dB 1196 98 G31 1196 98 632 1196 98 G33 Output Amplitude vs Spurious Free Dynamic Range vs Input Frequency Frequency 100 70 e Vec 5V 60 12MHz 80 fe 5 50 Voc 3V z 2 4 5 5 a a
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26. IC 58 PART MARKING 1961A 1981A 1961B 1981B Tymax 150 C Oja 175 C W 1 962A Tymax 150 C Oja 175 C W 1 982A 1962B 1982B Parts available in N8 package Consult factory for N8 samples RECOMMENDED OPERATING CONDITIONS LTC1196 1 LTC1196 2 LTC1198 1 LTC1198 2 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Voc Supply Voltage 2 7 6 2 7 6 V Vcc 5V Operation Clock Frequency 0 01 144 0 01 12 0 MHz e 0 01 12 0 0 01 9 6 MHz Total Cycle Time LTC1196 12 12 CLK LTC1198 16 16 CLK tSMPL Analog Input Sampling Time 2 5 2 5 CLK thts Hold Time CS Low After Last CLKT 10 13 ns touts Setup Time CSJ Before First 20 26 ns See Figures 1 2 Hold Time Diy After CLKT LTC1198 20 26 ns LI VIE LTC1196 LTC1198 RECOMMENDED OPERATING CONDITIONS LTC1196 1 LTC1196 2 LTC1198 1 LTC1198 2 SYMBOL PARAMETER CONDITIONS MIN MIN MAX UNITS Setup Time D y Stable Before LTC1198 20 26 ns tWHCLK CLK High Time CLK foLK max 40 40 l feik WLCLK CLK Low Time CLK CLK MAX 409 409 l feik CS High Time Between Data Transfer Cycles 25 32 ns twi CS CS Low Time During Data Transfer LTC1196 11 11 CLK LTC1198 15 15 CLK CONVERTER AND MULTIPLEXER CHARACTERISTICS Vec 5V Veer 5V fei as defined in Recommended Oper
27. MUX Address The 2 bits ofthe input word following the START bitassign the MUX configuration for the requested conversion For a given channel selection the converter will measure the voltage between the two channels indicated by the and signs in the selected row of the following table In single ended mode all input channels are measured with respect to GND LTC1198 Channel Selection MUX ADDRESS CHANNEL SGL DIFF ODD SIGN 0 1 GND SINGLE ENDED E DE DIFFERENTIAL MUX MODE 1196 98 103 AL Ue 15 LTC1196 LTC1198 APPLICATIONS INFORMATION Dummy Bits The last 2 bits of the input word following the MUX Address are dummy bits Either bit can be a logical one or a logical zero These 2 bits allow the ADC 2 5 clocks to acquire the input signal after the channel selection A D Conversion Result Both the LTC1196 and the LTC1198 have the A D conversion result appear on the Dour line after two null bits see Operating Sequence in Figures 1 and 2 Data onthe Dour line is updated on the rising edge of the CLK line The Doyt data should also be captured on the rising CLK edge by the digital systems Data on the Dout line remains valid for a minimum time of typo 30ns at 5V to allow the capture to occur see Figure 3 CLK Dout 1196 98 TC03 Figure 3 Voltage Waveform for Dgyr Delay Time tano and Unipolar Transfer Curve The LTC1
28. Mux control bit 1 INPKEN INPACK Enable 0 Force BVD1 STSCHG output low 1 Force BVD1 STSCHG output high 0 Enable BVD2 SPKR output 1 Tri state BVD2 SPKR output 0 Force BVD2 SPKR output low 1 Force BVD2 SPKR output high Table A 4 CNTL Register Control Signal Latch Offset 4 D4 BVD1_EN 0 Enable BVD1 STSCHG output 1 Tri state BVD1 STSCHG output CLR_RST 1 Clear LRESET bit in STBLAT 7 0 Arm reset latch M200052 03 1994 2002 Sycard Technology Page 4 Appendix A Register Description 5 LADRMID Address latch for A 15 8 read A read of this register returns the value of the specified latched address bits Address are latched after the address latch circuitry is armed through the ADLAT bit located in the CNTL control register offset 4 5 TRST Reset strobe to pulse counter A write to the TRST register will arm the strobe timer circuitry Once a write to the TRST register is complete the counter will be armed and waiting for the selected PC card strobe 6 0 7 Timer Register read The Timer Register is a read only register containing the results of the strobe timer An 8 bit value represents the number of clocks that occurred between the selected start transition and the end transition specified in the TCR register The actual value in nanoseconds can be calculated by multiplying the count by the sample clock period The sample clock period for the PCCtest 172 is 50nS The time
29. RIPTION The LTC1196 LTC1198 are 600ns 8 bit A D converters with sampling rates up to 1MHz They are offered in 8 pin 50 packages and operate on 3V to 6V supplies Power dissipation is only 10mW with 3V supply or 50mW with 5V supply The LTC1198 automatically powers down to atypical supply current of 1nA whenever it is not perform ing conversions These 8 bit switched capacitor succes sive approximation ADCs include sample and holds The LTC1196 has a differential analog input the LTC1198 offers a software selectable 2 channel MUX The 3 wire serial 1 0 50 8 packages 3V operation and extremely high sample rate to power ratio make these ADCs an ideal choice for compact high speed systems These ADCs can be used in ratiometric applications or with external references The high impedance analog inputs and the ability to operate with reduced spans below 1V full scale 1701196 allow direct connection to signal sources in many applications eliminating the need for gain stages The A grade devices are specified with total unadjusted error of 1 2LSB maximum over temperature TYPICAL APPLICATION Single 5V Supply 1MSPS 8 Bit Sampling ADC Vcc SERIAL DATA LINK TO IN LTC1196 CLK 8 ASIC PLD MPU DSP ANALOG INPUT OR SHIFT REGISTERS OV TO 5V RANGE Bam 1196 98 01 Effective Bits and S N D vs Input Frequency
30. SYCARD TECHNOLOGY 2 2 2 PCCtest 172 Technical Reference Manual M200052 03 January 2002 Preliminary Sycard Technology 1180 F Miraloma Way Sunnyvale CA 94085 408 749 0130 408 749 1323 FAX http www sycard com PCCtest 172 Technical Reference Manual Page 1 1 Introduction The PCCtest 172 16 bit PC Card tester is designed to provide manufacturers of PCMCIA based hosts a quick method of testing and verifying the operation of the PC Card sockets The PCCtest is Type II PC Card that plugs into a standard PC Card Type II or III socket The board is designed for both automated GO NO GO testing and component level debug Test software is required on the host system A custom ASIC is the core of the PCCtest 172 testing logic is contained in this ASIC The PCCtest contains an on board A D to provide accurate measurement of VCC and VPP voltages Sycard Technology provides a DOS application to test Intel 8236551 compatible socket controllers Simple command line invocation allows tests to be embedded into batch test files OEMs that wish to use the PCCtest on a non DOS platform can use this specification to develop custom test applications 1 1 Differences between the PCCtest 172 and the PCCtest 170 Although the PCCtest 170 and the 172 appear to be the same there are slight differences that make the PCCtest 172 suitable for certain applications The PCCtest 172 was created to solve a problem with socket controllers
31. TEMPERATURE 90 1196 98 618 8 LI YR LTC1196 LTC1198 TYPICAL PERFORMANCE CHARACTERISTICS Input Channel Leakage Current Integral Nonlinearity vs Differential Nonlinearity vs vs Temperature Code at 5V Code at 5V 1000 0 5 506 Voc 5V o I Voc 5V VREF 5V IRE 100 Q F folk 12MHz 5 amp 10 lt E 0 0 ON CHANNEL n amp 1 z 5 a sz uj OFF CHANNEL a 0 1 er a y f ce E u 0 01 2 0 5 0 5 60 40 20 0 20 40 60 80 100 120 140 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 TEMPERATURE CODE CODE 1196 98 G19 1196 98 G20 1196 98 G21 Integral Nonlinearity vs Differential Nonlinearity vs Effective Bits and S N D vs Code at 2 7V Code at 2 7V Input Frequency 0 5 _ 05 8 50 Vc 27V Vggr Voc 2 7V VREF 2 5V g 7 fsmpL 383kHz LTC1196 44 I fork
32. V Reference 1 2 Out Analog Vref Mux LTC1196 2BCS Select AID B Converter AMUX1 gt ADCCE ADCLK y ADDAT lt Figure 3 18 1 PCCtest 172 A D Subsystem The A D converter I O pins are controlled via internal register bits The following control bits are tied to the A D converter Register Location Register Bit MISC 7 ADCLK Controls the A D clock signal MISC 6 ADCCE Controls the A D chip enable signal LATMISC 1 ADDAT A D data output MISC 5 AMUX0 Analog Mux control bit 0 CNTL 2 AMUXI Analog Mux control bit 1 Table 3 18 1 A D Control Bits A four input analog multiplexer selects which voltage is to be measured M200052 03 1994 2002 Sycard Technology Page 10 PCCtest 172 Technical Reference Manual A D Input Select AMUXI 2 Oo oo 1 Vpp1 Oo oi o e Table 3 18 2 A D Mux Control The A D converter is implemented using the Linear Technology LTC1196 The programming interface to the A D converter is contained in the LTC1196 data sheet A copy of the LTC1196 datasheet is contained in Appendix C 3 19 PCCtest 172 versions There are currently two versions of the PCCtest 170 in circulation The following table describes the differences between the two PCCtest 170 First release of the PCCtest 172 Second release of the PCCtest 172 CISTPL_CONFIG added to CIS 1994 2002 Sycard Technology M200052 03 Appendix Register D
33. X VREF 256 d Vec 5V e c2 o SUPPLY CURRENT mA Vec 2 7V N A Ci DN O c gt MAGNITUDE OF OFFSET LSB 0 05 10 15 20 25 30 35 40 45 50 REFERENCE VOLTAGE V 55 35 15 5 25 45 65 85 105 125 TEMPERATURE C 1196 98 G04 1196 98 GOS Linearity Error vs Reference Voltage Linearity Error vs Supply Voltage e 0 4 Ta 25 VREF Vcc fCLK 3MHz a TY ERROR LSB 1 LINEARITY ERROR LSB LINEAR 5 2S a 0 05 10 15 20 25 30 35 40 45 50 25 30 35 40 45 50 55 60 REFERENCE VOLTAGE V SUPPLY VOLTAGE V 1196 98 G07 1196 98 G08 Supply Current vs Sample Rate 10 LT1196 Vec 5V EN SUPPLY CURRENT mA 0 MAGNITUDE OF OFFSET MAGNITUDE OF GAIN ERROR LSB 2 Ta 25 C 100k 1M 001 100 1k 10k SAMPLE RATE Hz 1196 98 G03 Offset vs Supply Voltage 0 5 04 Ta 25 C VREF Voc 0 3 3MHz 0 4
34. alog Input Equivalent Circuit REFERENCE INPUT The voltage on the reference input of the LTC1196 defines the voltage span of the A D converter The reference input has transient capacitive switching currents which are due to the switched capacitor conversion technique see Fig ure 9 During each bit test of the conversion every CLK cycle a capacitive current spike will be generated on the reference pin by the ADC These high frequency current spikes will settle quickly and do not cause a problem if the reference input is bypassed with at least a 0 1 uF capacitor The reference input can be driven with standard voltage references Bypassing the reference with a 0 1 uF capacitor is recommended to keep the high frequency impedance low as described above Some references require a small resistor in series with the bypass capacitor for frequency Stability See the individual reference data sheet for details LTC1196 1196 98 F09 Figure 9 Reference Input Equivalent Circuit Reduced Reference Operation The minimum reference voltage of the LTC1198 is limited to 2 7V because the Vcc supply and reference are inter nally tied together However the LTC1196 can operate with reference voltages below 1V The effective resolution of the LTC1196 can be increased by reducing the input span of the converter The LTC1196 exhibits good linearity and gain over a wide range of reference voltages see typical curves of Linearity and Fu
35. and CD2 are low SR SNS If any of these tests fail further testing is not possible 3 4 Basic Tests Once the socket controller has been verified and card detects are active the PCCtest functions can be accessed This part of the test procedure verifies the basic read write operation of the card If any failures are detected in the basic test more advanced tests may return erroneous results In order to run the first set of tests an attribute memory window to the card must be opened a Read the CIS and compare with values contained in Appendix B b Basic 8 bit attribute memory read write to the DATALO register Verify basic 8 bit memory read c Basic 16 bit attribute memory read write to the DATALO DATAHI register Verify basic 16 bit memory read 1994 2002 Sycard Technology M200052 03 PCCtest 172 Technical Reference Manual Page 5 Once these tests pass further more detailed tests can be run Note Basic 8 bit operation of the PCCtest requires the following signals to be working D 7 0 OE WE 1 2 0 3 5 Data Tests The 16 bit PC Card data bus may be tested through several methods When the PCCtest 172 is in MODE 0 the host writes data to the data latches DATALO at attribute memory offset 100H or DATAHI at 101H Both 8 and 16 bit accesses are allowed Data is latched into these registers on an attribute memory write to the DATALO and DATAHI registers Once data is written it can be read back to verify that a
36. ating Conditions unless otherwise noted LTC1196 XA LTC1196 XB LTC1198 XA LTC1198 XB PARAMETER CONDITIONS MIN MIN MAX UNITS No Missing Codes Resolution 8 8 Bits Offset Error e 1 2 1 LSB Linearity Error Note 3 1 2 1 LSB Full Scale Error e 1 2 1 LSB Total Unadjusted Error Note 4 LTC1196 VREF 5 000V e 1 2 1 LSB LTC1198 5 000V Analog and REF Input Range LTC1196 0 05V to Vcc 0 05V V Analog Input Leakage Current Note 5 e 1 1 HA DIGITAL AND DC ELECTRICAL CHARACTERISTICS Vec 5V Vper 5V unless otherwise noted SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS High Level Input Voltage Vcc 5 25V e 2 0 V VIL Low Level Input Voltage Vec 4 75V 0 8 V High Level Input Current ViN Vcc e 2 5 li Low Level Input Current Vin OV 2 5 pA High Level Output Voltage Voc 4 75V Ig 100A e 4 5 4 74 V Vec 4 75V Ig 360pA 24 4171 V VoL Low Level Output Voltage Vcc 4 75V Ig 1 6mA e 0 4 V loz Hi Z Output Leakage CS High e t3 ISOURCE Output Source Current Vout OV 25 mA ISINK Output Sink Current Vour Vcc 45 mA IREF Reference Current LTC1196 CS Vec e 00001 3 SMPL SMPL MAX 05 1 mA lec Supply Current CS LTC1198 Shutdown e 0 001 3 CS Voc LTC1196 7 15 mA SMPL SMPL MAx LTC1196 LTC1198 e 11 20 mA AL Ue LTC1196 LTC1198 DYNAM IC ACCURACY Vec 5V Veer 5V fei
37. be rapidly time varying just as in single ended mode However the volt age on the selected input must remain constant and be free of noise and ripple throughout the conversion time Otherwise the differencing operation may not be per formed accurately The conversion time is 8 5 CLK cycles Therefore a change in the input voltage during this interval can cause conversion errors For a sinusoidal voltage on the input this error would be VERROR MAX V PEAK f X 8 5 fci k Where f is the frequency of the input voltage Vpgakis its peak amplitude and fc is the frequency of the 18 LI VIE LTC1196 LTC1198 APPLICATIONS INFORMATION SAMPLE HOLD INPUT MUST SETTLE DURING THIS TIME cs e SMPL mi tconv Dout 1ST BIT TEST INPUT MUST gt SETTLE DURING THIS TIME 1 INPUT INPUT 1196 98 F07 Figure 7 LTC1198 and Input Settling Windows CLK VEnnon is proportional to f and inversely pro portional to For 60Hz signal on the input to generate a 1 4LSB error 5mV with the converter running at CLK 12MHz its peak value would have to be 18 7V ANALOG INPUTS Because of the capacitive redistribution A D conversion techniques used the analog inputs of the LTC1196 LTC1198 have one capacitive switching input current spike
38. ccess after this arm will result in the latching of all 26 address signals on the interface The following C code is used to arm the address latch outportb tester_addr 4 reg4_image amp Oxfb outportb tester addr 4 reg4 image 0x04 Note tester addr is the base I O address programmed into the host socket controller I O mapping registers M200052 03 1994 2002 Sycard Technology 6 PCCtest 172 Technical Reference Manual The latched values of the address and REG signal may be read directly from the registers A 7 0 15 8 A 23 16 A25 OE WE Table 3 6 1 Address Latch Locations The following procedure is used to latch the address and read the data from the address latches to create a 26 bit address Clear the ALAT bit in CNTL register at offset 4 2 Setthe ALAT bit in the CNTL register The address latch is now armed Access the card with IORD IOWR or WE strobe The address of the access is latched on the falling edge of the strobe Read the lower 8 bits A 7 0 from the LADDRLO register at offset 4 Read the contents of the A 15 8 latch from the LADDMID register at offset 5 Read the contents of the A 23 16 latch from the LADDHI register at offset 2 Read the contents of the A 25 24 and REG latch from the LATMISC register at offset 3 Read the contents of the CE1 CE2 OE WE IORD IOWR from the STBLAT register at offset 7 RON 3 7 Timing Measurements The P
39. e DATAHI register to be gated onto the PC card data bus D 15 8 An 8 bit I O read qualified by CE1 and A 0 2 001 will gate the contents of DATAHI onto the PC Card data bus D 7 0 2 LADRHI Address latch for A 23 16 read A read of this register returns the value of the specified latched address bits Address is latched after the address latch circuitry is armed through the ADLAT bit located in the CNTL control register at offset 4 M200052 03 1994 2002 Sycard Technology Page 2 Appendix A Register Description 2 TCR Timer control register write The TCR is a write only register that controls the operation of the strobe measurement circuitry STR 2 0 selects the strobe that will cause the measurement to start STRPOL selects which edge of the signal will start the timer STP 2 0 selects the strobe that will stop the timer STPPOL selects which edge terminates the timer STR 2 0 Start Pulse select o Emacs 5 00 d 0 _ 1 0 JNtUxd 1 1 JForeVS2RLow ____ 1 1 0 EE STRPOL Start polarity 0 Start timer on positive edge 1 Start timer on negative edge STP 2 0 End Pulse Select o o ob _ p Wd ___ 0 0 0 pp o _ 1 1 __ ____ __ _ 1 0 IR LX 1 ae STPPOL Stop polarity 0 Stop time
40. e LTC1196 converts in 1 6us samples at 450kHz and provides a 500kHz linear input bandwidth Dynamic accuracy is excellent on both 5V and 3V The ADCs typically provide 49 3dB of 7 9 ENOBs of dynamic accuracy at both 3V and 5V The noise floor is extremely low corresponding to a transition noise of less than 0 1LSB DC accuracy includes 0 5LSB total unadjusted error at 5V At 3V linearity error is 0 5LSB while total unadjusted error increases to 1LSB Table 1 5V 3V Performance Comparison LTC1196 1 5V 3V Ppiss 50mW 10mW Max f supr 1MHz 383kHz Min tcony 600ns 1 6us INL Max 0 5LSB 0 5LSB Typical ENOBs 7 9 at 300kHz 7 9 at 100kHz Linear Input Bandwidth ENOBs 7 1MHz 500kHz LTC1198 1 Ppiss S0mW 10mW Ppiss Shutdown 15uW 9uW Max f supr 750kHz 287kHz Min 600ns 1 6us INL Max 0 5LSB 0 5LSB Typical ENOBs 7 9 at 300kHz 7 9 at 100kHz Linear Input Bandwidth ENOBs 7 1MHz 500kHz TYPICAL APPLICATIONS PLD Interface Using the Altera EPM5064 The Altera 5064 has been chosen to demonstrate the interface between the LTC1196 and PLD The 5064 is programmed to be a 12 bit counter and an equivalent 74HC595 8 bit shift register as shown in Figure 12 The circuit works as follows bringing ENA high makes the CS output high and the EN input low to reset the LTC1196 and disable the shift register Bringing ENA low the CS output 8 BIT SHIFT REGISTER B0 B
41. ection to a microprocessor or a DSP serial port is quite simple see Data Transfer section It requires no additional hardware but the speed will be limited by the clock rate of the microprocessor or the DSP which limits the conversion time of the LTC1196 LTC1198 Data Transfer Data transfer differs slightly between the LTC1196 and the LTC1198 The LTC1196 interfaces over 3 lines CS CLK and A falling CS initiates data transfer as shown in the LTC1196 Operating Sequence After CS falls the first CLK pulse enables Doyr After two null bits the A D conversion result is output on the Dour line Bringing CS high resets the LTC1196 for the next data exchange The 1701198 can transfer data with 3 or 4 wires The additional input is used to select the 2 channel MUX configuration The data transfer between the LTC1198 and the digital systems can be broken into two sections Input Data Word and A D Conversion Result First each bit of the input data word is captured on the rising CLK edge by the LTC1198 Second each bit of the A D conversion result on the Dour line is updated on the rising CLK edge by the 1701198 This bit should be captured on the next rising CLK edge by the digital systems see A D Conversion Result section Data transfer is initiated by a falling chip select CS signal as shown in the LTC1198 Operating Sequence After CS falls the LTC 1198 looks for a start bit After the start bit is received the 4 bi
42. ectly to the ground plane The Vcc pin should be bypassed to the ground plane with a 1uF tantalum with leads as short as possible Ifthe power supply is clean the LTC1196 LTC1198 can also operate with smaller 0 1uF surface mount or ceramic bypass capacitors All analog inputs should be referenced directly to the single point ground Digital inputs and outputs should be shielded from and or routed away from the reference and analog circuitry SAMPLE AND HOLD Both the LTC1196 and the LTC1198 provide a built in sample and hold S amp H function to acquire the input signal The S amp H acquires the input signal from input during tsmpL as shown in Figures 1 and 2 The S amp H of the LTC1198 can sample input signals in either single ended or differential mode see Figure 7 Single Ended Inputs The sample and hold of the 1701198 allows conversion of rapidly varying signals The input voltage is sampled during the time as shown in Figure 7 The sampling interval begins as the bit preceding the first DUMMY bit is shifted in and continues until the falling CLK edge after the second DUMMY bit is received On this falling edge the S amp H goes into hold mode and the conversion begins Differential Inputs With differential inputs the ADC no longer converts just a single voltage but rather the difference between two volt ages In this case the voltage on the selected input is still sampled and held and therefore may
43. ed as parallel port bits in the CNTL register offset 4 bits 1 and 0 The host software writes various patterns to these bits and verifies continuity by reading the status through the socket controller s status registers 3 13 Testing Card Interrupts De assert IREQ by clearing RDY BS Y IREQ bit in MISC register offset 4 bit 1 Configure interrupt routing in host socket controller for desired interrupt Insert interrupt handler for desired interrupt Assert interrupt by setting RDY BSY IREQ bit in MISC register offset 4 bit 1 Interrupt Service routine clears RDY BS Y IREQ bit to disable interrupt Disable interrupt routing in host socket controller 3 14 Testing Status Change 5 5 Interrupts Enable the BVD1 output by clearing BVD1_EN in the CNTL register offset 4 bit 4 De assert STSCHG by setting BVD1 STSCHG bit in CNTL register offset 4 bit 5 Configure interrupt routing in host socket controller for desired interrupt Insert interrupt handler for desired interrupt Clear BVD1 STSCHG bit in CNTL register offset 4 bit 5 Interrupt Service routine sets BVD1 STSCHG bit to disable interrupt Disable interrupt routing in host socket controller 3 15 Testing Voltage Sense VS1 VS2 The PCCtest model 172 support testing of the VS1 and VS2 signals On card initialization 5 1 and VS2 are both set inactive high VS1 and VS2 can be independently forced active lo
44. ely during the first CLK cycle of the conversion time and be free of noise Minimizing will improve settling time If a large input source resistance must be used the time allowed for settling can be extended by using a slower CLK frequency Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time see Figures 1 and 7 Again the and input sampling times can be extended as described above to accommodate slower op amps To achieve the full sampling rate the analog input should be driven with a low impedance source lt 100Q or a high speed op amp e g the LT1223 LT1191 or 171226 Higher impedance sources or slower op amps can easily be accommodated by allowing more time for the analog input to settle as described above Source Resistance The analog inputs of the LTC1196 LTC1198 look like a 25pF capacitor in series with a 1200 resistor Ron as shown in Figure 8 gets switched between the selected and inputs once during each conversion cycle Large external source resistors will slow the settling of the inputs It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle within Rsource INPUT LTC1196 Vin T LTC1198 TtsMPL Ron 1200 Reounce IMEUT tsmPLY posu 1196 98 F08 Figure 8 An
45. escription Page 1 Appendix A Register Description This section describes the configuration of PCCtest registers on initial power up PCCtest registers are written via attribute memory or I O write commands depending on the setting of the MODE register There are eight writable 8 bit registers within the PCCtest unit A 2 0 will select which register is written by the write strobe The following table describes at which offset the PCCtest registers are located in each PCCtest mode O 100H 1 yo __ 4 Common o 5 Common 0 io 0 DATALO Low Data Byte to PC card bus Any memory write WE qualified with a valid CE1 and A 0 2 000 will cause the DATALO register to be updated with contents of the PC card data bus D 7 0 In addition an I O write qualified with CE1 and A 0 2 000 will also cause a write to this register Any memory read qualified with a valid CE1 will cause the value of the DATALO register to gated onto the PC card data bus D 7 0 An I O read qualified with CE1 and A 0 2 000 will gate the contents of DATALO onto the PC Card data bus 1 DATAHI High Data Byte to PC card bus Any memory write memory qualified with a valid CE2 will cause the DATAHI register to be updated with contents of the PC card data bus D 15 7 Note An 8 bit I O write to the DATAHI register is not possible A memory read qualified with a valid CE2 will cause the value of th
46. ese registers are accessible on any 8 bit boundary The following table describes the various PCCtest modes M200052 03 1994 2002 Sycard Technology Page 4 PCCtest 172 Technical Reference Manual common memory accesses disabled memory space disabled DOLCE NE common memory space disabled space at 170H 177H enabled attribute and common memory space disabled EE 6 aiii I O space disabled BANKEN Attribute space disabled Table 3 2 2 PCCtest modes accessed through MODE register Note Once Mode 1 2 3 or 5 is enabled all access to attribute memory space is disabled Access to the PCCtest internal registers should be made through the enabled common memory or I O space Note The RESET signal will NOT put the PCCtest into its power on state To reset the PCCtest unit cycle power to the slot 3 3 Preliminary Tests Before accessing the PCCtest hardware the test software should verify the basic operation of the socket controller and that the PCCtest is properly inserted into the socket This will avoid any unnecessary delays or erroneous error messages The following sequence is used in Sycard s PCT172 software Verify socket controller is present by executing a simple register test Power up socket Verify that the socket controller has powered up the slot through the socket controller status Wait 1200ms for PCCtest to initialize Verify card detects are active CD1
47. ion pin FSX is configured to be an output The FO bit of the status register 511 is initialized to zero which sets up the serial port to operate in the 16 bit mode Next the code in TXRX routine starts to transmit and receive data The word is loaded into the ACC and shifted left eight times so that it appears as in Figure 18 This Diy word configures the LTC1198 for CHO with respect to CH1 The D y word is then put in the transmit register and the RINT interrupt is enabled The NOP is repeated 3 times to mask out the interrupts and minimize the cycle time of the conversion to be 20 clock cycles All clocking and CS functions are performed by the hardware B15 B8 0 1 0 0 0 1 0 0 START S D 0 5 DUMMY DUMMY 11196 98 F18 Figure 18 Word ACC of 145320025 for the Circuit in Figure 15 AY MYR ZO LTC1196 LTC1198 TYPICAL APPLICATIONS Once RINT is generated the code begins execution at the label RINT This code stores the Doyr word from the 1701198 inthe ACC and then stores it in location 200 hex The data appears in location 200 hex right justified as shown in Figure 19 The code is set up to continually loop so at this point the code jumps to label TXRX and repeats MSB LSB XIXIXIX IX X X X 7 6 5 4 3 2 1 0 5200 11196 98 F19 Dour FROM LTC1198 STORED IN 5320025 RAM Figure 19 Memory Map for the Circ
48. iplied by the sample rate 50ns to obtain the strobe width 3 8 Testing RESET The RESET signal is an input to the PCCtest unit RESET is only monitored by the PCCtest and will not reset the PCCtest The current state of the RESET signal can be read from RESET bit in the LATMISC register offset 3 bit 4 Testing of RESET involves forcing the state of RESET and reading the status in the RESET bit in the LATMISC register In some socket controllers when RESET is asserted the PC Card interface is tri stated or disabled In systems such as these the previously described method of testing RESET will not work With socket controllers such as these the PCCtest 172 contains a RESET latch that stores the fact that a transition occurred RESET The status of this latch can be read from LRESET bit in the STBLAT register offset 7 bit 7 This latch is armed by setting then clearing the CLR RST bit the CNTL register offset 4 bit 4 Once the reset latch is armed the test software will then strobe the RESET signal from high to low The latch will capture the low to high transition of the reset signal Software can verify this by reading the LRESET bit in the STBLAT register 3 9 INPACK Tests PCCtest can generate INPACK on all I O reads Most socket controllers can use INPACK to gate the PC Card data on to the host system data bus Setting the INPKEN bit in the CNTL control register offset 4 bit 3 enables INPACK generation on all I O reads 3 10 Tes
49. is only 0 1LSB peak to peak In this case the LTC1196 noise will contribute virtually no uncertainty to the output code However for reduced references the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code For example with a 1V reference this same 2mV noise is 0 515 peak to peak This will reduce the range of input voltages over which a stable output code can be achieved by 1LSB If the reference is further reduced to 200mV the 2mV noise becomes equal to 2 5LSB and a stable code is difficult to achieve In this case averaging readings is necessary This noise data was taken in a very clean setup Any setup induced noise noise or ripple on Vcc VREF or Vin will add to the internal noise The lower the reference voltage to be used the more critical it becomes to have a clean noise free setup DYNAMIC PERFORMANCE The LTC1196 LTC1198 have exceptionally high speed sampling capability Fast Fourier Transform FFT test techniques are used to characterize the ADC s frequency response distortion and noise at rated throughput By applying a low distortion sine wave and analyzing the digital output using a FFT algorithm the ADC s spectral content can be examined for frequencies outside the fundamental Figure 10 shows a typical 1701196 FFT plot Vec 5V fin 29kHz fe up 882kHz 0 100 200 300 400 500 FREQUENCY kHz 1
50. ll Scale Error vs Reference Voltage However care must be taken when operating at low values of because of the reduced LSB step size and the resulting higher accuracy requirement placed on the converter The following factors must be considered when operating at low Veer values 1 Offset 2 Noise 20 LI VIE LTC1196 LTC1198 APPLICATIONS INFORMATION Offset with Reduced Vpgr The offset of the LTC1196 has a larger effect on the output code when the ADC is operated with reduced reference voltage The offset which is typically a fixed voltage becomes a larger fraction of an LSB as the size of the LSB is reduced The typical curve of Unadjusted Offset Error vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of Vos For example a Vos of 2mV which is 0 1LSB with a 5V reference becomes 0 5LSB with a 1V reference and 2 5LSB with a 0 2V reference If this offset is unacceptable it can be corrected digitally by the receiving system or by offsetting the input of the LTC1196 Noise with Reduced VREF The total input referred noise of the LTC1196 can be reduced to approximately 2mVp p using a ground plane good bypassing good layout techniques and minimizing noise on the reference inputs This noise is insignificant with a 5V reference but will become a larger fraction of an LSB as the size of the LSB is reduced For operation with 5V reference the 2mV noise
51. ll data bits that have been written are correct The data pattern test can be also run via I O or common memory accesses The test software enables I O or common memory accesses via the MODE register at attribute memory offset 106H See table 3 2 2 for the valid modes Data pattern tests can be run through attribute memory common memory or I O space depending on the setting of the MODE register Common and attribute memory data pattern tests can be accomplished by accessing the same DATALO and DATAHI registers starting at offset O in I O or memory space On power on reset access to these registers through the memory space are disabled Prior to running the data test the lower 8 bits of the data bus can be verified by reading the CIS data A listing of the CIS is contained in Appendix B 3 6 Address and REG Tests Writing various address patterns to the PCCtest unit can test the PC Card s 26 bit address bus All address bits can be latched and read through the PC Card host interface The address latching circuit must be armed prior to the access that triggers the latching circuitry Addresses are latched on the falling edge of the control strobes WE OE IORD or IOWR Note The latching signal is a logical OR of the OE WEZ IORD and IOWR strobes qualified by either CE1 or CE2 Arming of the address latches is accomplished through the ALAT bit in CNTL register offset 4 A low to high transition of this bit will arm the latch Any a
52. mp 40 UN ge amp x 20 n 8 20 g 10 TA 25 C 0 0 1k 10k 100k 1 10M 1k 10k 100k 1 10M INPUT FREQUENCY Hz FREQUENCY Hz 1196 98 G34 1196 98 G35 10 AL VIE LTC1196 LTC1198 PIN FUNCTIONS LTC1196 CS Pin 1 Chip Select Input A logic low on this input enables the LTC1196 A logic high on this input disables the 1701196 IN Pin 2 Analog Input This input must be free of noise with respect to GND Pin 3 Analog Input This input must be free of noise with respect to GND GND Pin 4 Analog Ground GND should be tied directly to an analog ground plane Pin 5 Reference Input The reference input defines the span of the A D converter and must be kept free of noise with respect to GND Dour Pin 6 Digital Data Output The A D conversion result is shifted out of this output CLK Pin 7 Shift Clock This clock synchronizes the serial data transfer Vcc Pin 8 Power Supply Voltage This pin provides power to the A D converter It must be kept free of noise and ripple by bypassing directly to the analog ground plane LTC1198 CS SHUTDOWN Pin 1 Chip Select Input A logic low on this input enables the 1701198 A logic high on this input disables the LTC1198 and DISCONNECTS THE POWER THE 17061198 CHO Pin 2 Analog Input This input must be free of noise with respect to GND CH1 Pin 3 Analog Input This input must be free of noise with respect
53. nce Analog Input On Channel 30 30 pF Analog Input Off Channel 5 5 pF Digital Input 5 5 pF Vee 2 7V Operation LTC1196 1 LTC1196 2 LTC1198 1 LTC1198 2 SYMBOL PARAMETER CONDITIONS MIN MIN MAX UNITS CLK Clock Freguency 0 01 5 4 0 01 4 MHz e 0 01 4 6 0 01 3 MHz Total Cycle Time LTC1196 12 12 CLK LTC1198 16 16 CLK SMPL Analog Input Sampling Time 2 5 2 5 CLK thes Hold Time CS Low After Last CLKT 20 40 ns touts Setup Time CS4 Before First CLKT 40 78 ns See Figures 1 2 4 LI VIE LTC1196 LTC1198 RECOMMENDED OPERATING CONDITIONS Vec 2 7V Operation LTC1196 1 LTC1196 2 LTC1198 1 LTC1198 2 SYMBOL PARAMETER CONDITIONS MIN MIN UNITS Hold Time D y After LTC1198 40 78 ns Setup Time D y Stable Before CLKT LTC1198 40 78 ns twHCLK CLK High Time foLK MAX 40 40 l feik tWLCLK CLK Low Time foLK MAX 40 40 l feik twucs CS High Time Between Data Transfer Cycles 50 96 ns twi CS CS Low Time During Data Transfer LTC1196 11 11 CLK LTC1198 15 15 CLK CONVERTER AND MULTIPLEXER CHARACTERISTICS Vec 2 71 2 5V fork fCLK Max as defined in Recommended Operating Conditions unless otherwise noted LTC1196 XA LTC1196 XB LTC1198 XA LTC1198 XB PARAMETER CONDITIONS MIN MIN
54. ne 44 276 677676 FAX 44 276 64851 08 16 93 LT GP 0893 10K REV 0 PRINTED IN USA TECHNOLOGY LINEAR TECHNOLOGY CORPORATION 1993
55. nput Off Channel 5 5 pF Digital Input 5 5 pF The denotes specifications which apply over the full operating temperature range Note 1 Absolute maximum ratings are those values beyond which the life of a device may be impaired Note 2 All voltage values are with respect to GND multiplexer and hold step errors Note 3 Integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve The deviation is measured from the center of the quantization band Note 4 Total unadjusted error includes offset full scale linearity Note 5 Channel leakage current is measured after the channel selection 7 LINEAR TECHNOLOGY LTC1196 LTC1198 TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Clock Rate Supply Current vs Supply Voltage 14 12 ACTIVE MODE CS 0V LTC1196 LTC1198 5 TA 25 C CS 0V Veer Voc SUPPLY CURRENT mA SUPPLY CURRENT mA Vec 2 7V SHUTDOWN MODE LTC1198 CS Voc 0 eene 0 2 4 6 8 10 12 14 16 25 30 35 40 45 50 55 640 FREQUENCY MHz SUPPLY VOLTAGE V 1196 98 G01 1196 98 G02 Supply Current vs Temperature Offset vs Reference Voltage CS 0V gt
56. nversion drawing only leakage current SERIAL INTERFACE The LTC1196 LTC1198 will interface via three or four wires to ASICs PLDs microprocessors DSPs or shift registers see Operating Sequence in Figures 1 and 2 To run attheir fastest conversion rates 600ns they must be clocked at 14 4MHz HC logic families and any high speed ASIC or PLD will easily interface to the ADCs at that speed see Data Transfer and Typical Application sections Full speed operation from a 3V supply can still be achieved with 3V ASICs PLDs or HC logic circuits 12 CLKs gt lt tsucs gt lt tano NULL Dour 80 wer 87 86 85 a BITS SMPL tconv 8 5 CLKs tsMPL AFTER COMPLETING THE DATA TRANSFER IF FURTHER CLOCKS ARE APPLIED WITH CS LOW THE ADC WILL OUTPUT ZEROS INDEFINITELY 1196 98 01 Figure 1 LTC1196 Operating Sequence teyc 16 CLKs gt pown 77 ODD START SIGN DUMMY MY DIFF tapo Hi Z HI Z Bits 87 86 B5 B2 Bi BO tcony 8 5 1 5 lt 2 501 6 AFTER COMPLETING THE DATA TRANSFER IF FURTHER CLOCKS ARE APPLIED WITH CS LOW THE ADC WILL OUTPUT ZEROS INDEFINITELY 1196 98 F02 Figure 2 LTC1198 Operating Sequence Example Differential Inputs CHO 14 AL VIE LTC1196 LTC1198 APPLICATIONS INFORMATION Conn
57. ontained in the test ASIC These eight registers control the various test functions contained within the PCCtest unit The location at which these registers are accessed depends on which mode the PCCtest unit is in On power up these test registers are located in attribute memory space The test software can then enable I O and or common memory modes to test the various access modes of the PC Card interface There are two major types of tests performed by the PCCtest unit those implemented by the Test ASIC and the A D tests The Test ASIC based tests are designed to test the basic functionality of the interface These tests will verify the basic operation of the interface including access strobes data bus and address bus Once these basic access modes are verified the A D test verifies the Vcc and Vpp levels M200052 03 1994 2002 Sycard Technology Page 2 PCCtest 172 Technical Reference Manual A28 gt Gate Array D 0 15 REG 1 2 WAIT READY IREQ WP IOIS16 IORD IOWR BVD1 STSCHG4 BVD2 SPKR INPACK RESET gt Figure 2 0 1 PCCtest 172 block diagram 1994 2002 Sycard Technology M200052 03 PCCtest 172 Technical Reference Manual Page 3 3 0 Testing the 16 bit PC Card Interface Most of the basic interface tests are handled in the Test ASIC
58. r is armed by a write to the TRST register offset 5 6 MODE Mode Control Register write The mode control register is used to enable the various PCCtest test modes Bits in this register enable common memory and I O modes Description MODE 0 2 Mode Control Attribute memory enabled I O space and common memory not enabled I O space enabled common and attribute memory disabled space at 1FOH 1F7H enabled common and attribute memory disabled I O space at 170H 177H enabled common and attribute memory disabled Common and attribute space enabled I O space disabled Common memory space enabled I O space enabled attribute memory space disabled Not Used Not Used Not Used Not Used Not Used Table A 5 MODE Register Mode Control Register Offset 6 1994 2002 Sycard Technology M200052 03 Appendix Register Description Page A 5 7 STBLAT Latched Control Bits read The STBLAT register is a read only register that contains the latched status of various control signals on the PC Card interface All latched signal except LRESET are latched using the same mechanism at the address latch Bit 10 LOR e LIORD Latched IORD LIOWR Latched IOWR D6 ___ D7 LRESET Latched RESET status Cleared by setting bit 4 in the CNTL register Table A 6 STBLAT Register Latched Status Bits read M200052 03 1994 2002 Sycard Technology Appendix B PCCtest 172
59. r on positive edge 1 Stop timer on negative edge Table A 1 Register Offset 2H TCR Timer Control Register 3 LATMISC Misc Latched Bits read The LATMISC register contains various realtime and latched status signals from the PC Card interface D0 LA JjLathedAddrss24 00 5 D6 WP OISlGReadback O Z o o 0 0 Table A 2 LATMISC Register Misc Latched Bits Offset 3 1994 2002 Sycard Technology M200052 03 Appendix Register Description Page A 3 3 MISC Control Register write The MISC Control register is a read write register that contains various control bits for the PCCtest unit WAIT 0 2 Wait State Select control the number of wait states that are inserted for any I O or memory access The wait state generator must be enabled through bit 3 of this register WAIT2 0 Nowaitstates 0 l00nswat 0 400nswat 0 160005 wait D4 0 CIS ROM Enabled Default 1 CIS ROM Disabled D5 D7 Table A 3 MISC Register Misc control bits offset 3 BS SS HETE HEC 122071 4 LADRLO Address latch for A 7 0 read A read of this register returns the value of the specified latched address bits Address are latched after the address latch circuitry is armed through the ADLAT bit located in the CNTL control register at offset 4 4 CNTL Control Register write CNTL is a write only register AMUXI A D
60. s Dour Delay Time vs Supply Voltage Supply Voltage 19 140 Ty 25 C 17 120 A 15 72 100 a a 2 1 3 80 gt E 14 5 60 S e 09 5 40 eai 0 7 20 0 5 0 25 30 35 40 45 50 55 60 25 30 35 40 45 50 55 60 SUPPLY VOLTAGE V SUPPLY VOLTAGE V 1196 98 G16 1196 98 G17 AS THE FREQUENCY IS DECREASED FROM 12MHz MINIMUM CLOCK FREQUENCY AERROR x 0 1LSB REPRESENTS THE FREQUENCY AT WHICH A 0 1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 12MHz VALUE IS FIRST DETECTED Maximum Clock Frequency vs Source Resistance 5 amp e LLI amp 1 10 100 1k 10k 100k SOURCE RESISTANCE 0 1196 98 G12 Sample and Hold Acquisition Time vs Source Resistance 10000 Ta 25 C L Vec VREF 5V 2 2 RsoURCE Vin IN e 1000 SN 5 CT lt wn 100 1 10 100 1k 10k SOURCE RESISTANCE Q 1196 98 G15 Dour Delay Time vs Temperature 160 140 2 120 E gt 100 gt 80 gt lt 60 a 2 40 a 20 0 60 40 20 0 20 40 60 80 100 120 140
61. section describes the Card Information Structure CIS stored in the attribute memory space of the PCCtest 172 Rev 1 02 Addr Fl I ojo HS DO TL J L uU JE Lr I D Lu I a 1 1 1 1 1 1 1 o 200052 03 Byte ojojo gt 6 I I I I OFFH 15 30 05 DW co LO Do AS CO CO I Ed r m m mimimimimimimimimimimimimimimimimimimimiu r m m mimimimimimiu Gy oo gat Description CIS Tup CIS P 3 4 1 PL DEVIC le link Device I buffer 8250nS 2 units of 8K End of tuple PL VERS 1 le link V1 MAJOR E 1_ nfo Field 1 Function Specific Memory type 16K 16K 1994 2002 Sycard Technology Page 4 Byte WN J O1 Gd GI Gl I Appendix B PCCtest 172 CIS Description TPFID FUNCTION Vendor Specific Function CISTPL CONFIG Tuple Link H H H H H H H H H H H H PI INDEX 5 6087 ELEN 6887 8087 9087 96
62. ss otherwise noted LTC1196 LTC1198 SYMBOL PARAMETER CONDITIONS MIN MIN TYP MAX UNITS S N D Signal to Noise Plus Distortion 190kHz 380kHz Input Signal 47 45 47 45 dB THD Total Harmonic Distortion 190kHz 380kHz Input Signal 49 47 49 47 dB Peak Harmonic or Spurious Noise 190kHz 380kHz Input Signal 53 46 53 46 dB IMD Intermodulation Distortion fina 189 37 2 51 51 dB fina 192 446kHz Full Power Bandwidth 5 5 MHz Full Linear Bandwidth S N D gt 4408 0 5 0 5 MHz Vec 2 7V 2 51 fork ferax as defined in Recommended Operating Conditions unless otherwise noted LTC1196 1 LTC1196 2 LTC1198 1 LTC1198 2 SYMBOL PARAMETER CONDITIONS MIN MIN UNITS Conversion Time See Figures 1 2 1 58 2 13 us 1 85 2 84 us Maximum Sampling Frequency LTC1196 450 333 kHz LTC1196 e 383 250 kHz LTC1198 337 250 kHz LTC1198 e 287 187 kHz Delay Time to Dour Data Valid Ci oAp 20pF 100 150 130 200 ns e 180 250 ns tois Delay Time CST to Doyr Hi Z 110 220 120 250 ns Ten Delay Time CLK to Dour Enabled Ci oAp 20pF e 80 130 100 200 ns thoo Time Output Data Remains Valid CLoap 20pF 45 90 45 120 ns After CLKT tr Dour Fall Time Ci oap 20pF e 10 30 15 40 ns tr Dour Rise Time Ci oap 20pF e 10 30 15 40 ns Cin Input Capacitance Analog Input On Channel 30 30 pF Analog I
63. t input word is shifted into the D y input The first two bits of the input word configure the LTC1198 Thelasttwo bits ofthe input word allow the ADC to acquire the input voltage by 2 5 clocks before the conversion starts After the conversion starts two null bits and the SHIFT MUX ADDRESS IN T 2 NULL BITS SHIFT A D CONVERSION RESULT OUT 1196 98 101 conversion result are output on the Dour line At the end of the data exchange CS should be brought high This resets the LTC1198 in preparation for the next data ex change Input Data Word The LTC1196 requires word It is permanently configured to have a single differential input The conver sion result is output on the Dour line in an MSB first sequence followed by zeros indefinitely if clocks are continuously applied with CS low The LTC1198 clocks data into the D y input on the rising edge of the clock The input data word is defined as follows SGL ODD START DIFF SIGN DUMMY DUMMY MUX ADDRESS BITS 119698 102 Start Bit The first logical one clocked into the input after CS goes low is the start bit The start bit initiates the data transfer The LTC1198 will ignore all leading zeros which precede this logical one After the start bit is received the remaining bits of the input word will be clocked in Further inputs onthe D y pin then ignored until the next CS cycle Multiplexer
64. ting Figure 5 shows the supply current versus sample rate for the LTC1196 and LTC1198 on 3V and 5V To achieve such a low power consumption especially for the 1701198 several things must be taken into consideration Shutdown LTC1198 Figure 2 shows the operating sequence of the 1701198 The converter draws power when the 65 pin is low and powers itself down when that pin is high For lowest power consumption in shutdown the CS pin should be driven with CMOS levels OV to Vcc so that the CS input buffer of the converter will not draw current 16 LI VIE LTC1196 LTC1198 APPLICATIONS INFORMATION DUMMY BITS LATCHED CS BY LTC1198 1 2 3 4 5 DATA Diy Dour START SGL DIFF ODD SIGN DUMMY DUMMY B7 B6 THE DIGITAL SYSTEM CONTROLS DATA LINE AND SENDS MUX ADDRESS TO LTC1198 THE DIGITAL SYSTEM MUST RELEASE 1 DATA LINE AFTER 5TH RISING CLK LTC1198 CONTROLS DATA LINE AND SENDS I A D RESULT BACK TO THE DIGITAL SYSTEM 1 i LTC1198 TAKES CONTROL OF DATA LINE ON 5TH FALLING CLK 1196 98 F04 AND BEFORE THE 5TH FALLING CLK Figure 4 LTC1198 Operation with Diy and Doyr Tied Together LT1196 Vec 5V 0 1 SUPPLY CURRENT mA 0 001 E 100 1k 10k 100k 1M SAMPLE RATE Hz 1196 98 F05 Figure 5 Supply Current vs Sample Rate for LT
65. ting WAIT A programmable wait state generator is used to generate wait states to simulate slow I O or memory devices The wait state generator is capable of generating wait states up to 3160ns This covers the full range of PC card access times Used in conjunction with the pulse measuring circuits can result in accurate measurement of read write strobe widths Timing for the wait state generator is based on the PCCtest main crystal 20Mhz The wait state generator is accessed through WAIT 0 2 bits in the MISC control register at offset bits 0 2 In addition to the WAIT 0 2 bits the WAITEN bit at offset 3 bit 3 must be set to enable wait states M200052 03 1994 2002 Sycard Technology Page 8 PCCtest 172 Technical Reference Manual un wair Table 3 10 1 Wait state delays 3 11 Testing BVDI and BVD2 The BVD1 and BVD2 signal are outputs from the PCCtest card They are implemented as parallel port bits in the CNTL register at offset 4 The host software writes various patterns to these bits and verifies continuity by reading the status through the socket controller s status registers There are four bits used to control the BVD1 and BVD2 outputs BVD1_EN and BVD2_EN must be set to 0 to enable the BVD1 and BVD2 tri state outputs The BVD1_OUT and BVD2 OUT bits control the state of the corresponding outputs 3 12 Testing Ready and WP The RDY BSY IREQ and WP IOIS 16 signal are outputs from the PCCtest card They are implement
66. to GND GND Pin 4 Analog Ground GND should be tied directly to an analog ground plane D y Pin 5 Digital Data Input The multiplexer address is shifted into this input Dour Pin 6 Digital Data Output The A D conversion result is shifted out of this output CLK Pin 7 Shift Clock This clock synchronizes the serial data transfer Vcc Vner Pin 8 Power Supply and Reference Voltage This pin provides power and defines the span of the A D converter It must be kept free of noise and ripple by bypassing directly to the analog ground plane BLOCK DIAGRAM Voc cs CS SHUTDOWN CLK PIN NAMES IN PARENTHESES REFER TO THE LTC1198 BIAS AND SHUTDOWN CIRCUIT HIGH SPEED COMPARATOR Dour SERIAL PORT CAPACITIVE DAC VREF Din 1196 98 BD LT Ue 11 LTC1196 LTC1198 TEST CIRCUITS On and Off Channel Leakage Current 5V lon ON CHANNEL OFF CHANNEL POLARITY 1196 98 TCO1 Voltage Waveform for Doyr Rise and Fall Times Dour lt lt ir 1196 98 04 Load Circuit for tgis and ten TEST POINT Vec tgis WAVEFORM 2 ten saj WAVEFORM 1 1196 98 05 Load Circuit for typo t and ty 14V 3k Dour TEST POINT 100pF uL 1196 98 TC02 Voltage Waveform for Doyr Delay Time typo and CLK Dout 1196 98 TCO3 Voltage Waveforms for tic Dout WAVEFORM 1 SEE NOTE 1 Dou WAVEFORM
67. uit in Figure 15 from here LABEL MNEMONIC COMMENTS AORG 0 ON RESET CODE EXECUTION STARTS AT 0 B INIT BRANCH TO INITIALIZATION ROUTINE AORG gt 26 ADDRESS OF RINT INTERRUPT VECTOR B RINT BRANCH TO RINT SERVICE ROUTINE AORG gt 32 MAIN PROGRAM STARTS HERE INIT DINT DISABLE INTERRUPTS LDPK gt 0 SET DATA MEMORY PAGE POINTER TO 0 LARP gt 1 SET AUXILIARY REGISTER POINTER TO 1 LRLK AR1 gt 200 SET AUXILIARY REGISTER 1 gt 200 LACK gt 10 LOAD IMR CONFIG WORD INTO ACC SACL gt 4 STORE IMR CONFIG WORD INTO IMR STXM CONFIGURE FSX AS AN OUTPUT FORT 0 SET SERIAL PORT TO 16 BIT MODE TXRX LACK gt 44 LOAD LTC1198 Din WORD INTO ACC SFSM FSX PULSES GENERATED ON XSR LOAD RPTK 7 REPEAT NEXT INSTRUCTION 8 TIMES SFL SHIFTS WORD TO RIGHT POSITION SACL gt 1 PUT Diy WORD IN TRANSMIT REGISTER EINT ENABLE INTERRUPT DISABLED ON RINT RPTK 2 MINIMIZE THE CONVERSION CYCLE TIME NOP TO BE 20 CLOCK CYCLES RINT ZALS 0 STORE LTC1198 DOUT WORD IN ACC SACL 0 STORE IN LOCATION gt 200 B TXRX BRANCH TO TRANSMIT RECEIVE ROUTINE END Figure 20 11453200625 Code for the Circuit in Figure 15 26 LY VIE LTC1196 LTC1198 PACKAGE DESCRIPTION Dimension in inches millimeters unless otherwise noted 8 Package 8 Lead Plastic SOIC 0 189 0 197 4 801 5 004 8 7 6 5 0 228 0 244 0 150 0 157 5 791 6 197 3 810
68. w through the TCR register at offset 2 VS1 can be forced active low by setting STP 2 0 equal to 101 52 can be forced active low by setting STR 2 0 1994 2002 Sycard Technology M200052 03 PCCtest 172 Technical Reference Manual Page 9 to 101 The test software is required to verify the state of VS1 and VS2 through the host controller s status registers 3 16 Speaker SPKR Testing The Card s digital audio output SPKR can be tested by enabling the host socket controller s speaker out signal The host test software can then toggle the BVD2 OUT bit offset 4 bit 7 at an audible frequency to verify the signal path between the PCCtest and the systems audio subsystem In addition the BVD2_EN control offset 4 bit 6 must be low to enable the SPKR output The test software is responsible for enabling the host socket controller s speaker output pin and any other hardware required to enable the speaker drivers 3 17 Identifying the PCCtest Test software can identify that a PCCtest unit has been inserted by reading the Card Information Structure CIS The CIS contains an ID string identifying the PCCtest along with the version of PCCtest hardware Appendix B contains a listing of the PCCtest CIS 3 18 Measuring Vcc Vppl and Vpp2 The PCCtest 172 unit contains an on board 8 bit A D converter An input analog multiplexer selects which voltage is to be measured Figure 3 18 1 details the A D converter subsystem 2 5

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