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1. yoXo y3X3 Y2X3 Y1X3 YoxX3 VA VEN VN FA FA y2 eva yo rt y2 y Yo J P7 P P s P P3 P o Figure 4 A 4x4 array multiplier with column bypassing 4 C Array Multiplier with Column Bypassing Wen et al 4 proposed an array multiplier with column bypassing Figure 4 shows their 4x4 bit array structure in which the modified full adder only requires two tri state buffers and one 2 to 1 multiplexer This design bypasses columns of full adders and does not need extra circuits as Int l Conf Embedded Systems and Applications ESA 12 indicated by the dotted line area in Fig 3 The column addition can be bypassed when the bit of multiplicand y is 0 0 lt i lt n 2 This causes all partial products y x 0 0 lt j lt n 1 thus full adders can be disabled in the 1 th column Because disabled full adders may cause incorrect multiplication results this design includes an AND gate at the outputs of the carry save adder in the last row as Fig 4 shows Tri state buffer IEN in pees seen in ENV out out _ eee Figure 5 a Full adder cell in the multiplier with the row bypassing method 3 b Full adder cell in the multiplier with the column bypassing method 4 4000n Time s b Figure 6 a Transmission gates in the transistor level are used in the modified FA cell b The HSPICE softw
2. 80 F 100 4 3 0 0 5 1 1 5 2 sample tick Fig 6 Synthetic radar waveforms of high and low gain channel of Fig 1 with both gain and phase separations Int l Conf Embedded Systems and Applications ESA 12 waveform When derivative based phase detection is used the detected phase are used to generate a new set of FIR coefficients for both high and low gain channel to make the filtered output phase aligned before merging a matter of simple switch between these two channels to use only unsaturated output from corresponding channel One criterion to judge the accuracy of both phase detection and correction is the phase noise of the merged waveform ideally perfectly aligned Fig 7 shows the merged waveform with a general noise power high gain channel relative to low gain channel of 60dB merged wave Xx 10 time series samples 1 5 i mT ITI II ES AEE Il Lat _ eth s I t 4 iH mI Ici P Ct i Ha a 0 5 0 0 5 Feat R l i E i I iA t w p 215 1E k f TI
3. Q TER 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 a 4 6b Filtered sEMG Signal with Wavlet Daubechies Filter x 10 1 0 8 0 6 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 Time 30 Secs x 10 Fig 6 6a Unfiltered sSEMG Signal from the Proposed Acquisition System Using DE 3 1 Electrodes 6b Filtered SEMG signal with Wavelet Daubechies 44 Filter 7a Unfiltered sEMG Siganl COAT TT TTT ih i ull V ii NNT NNN nin j il il iH KH IM I nan iN i Al ASA Wall Wht i Il Hi at il PAMA AORN I non Mi Lh i i MIN iy Mi 0 2 4 6 8 10 12 14 7b Filtered sEMG Signal with Wavelet Daubechies 44 Filter m Amplitude gt n 0 2 4 6 8 10 12 14 7c Filtered Skeletal Muscle Force x10 6 8 Time 30 Secs x10 Fig 7 7a Unfiltered sEMG Signal from the Standard Acquisition System 7b Filtered sSEMG signal with Wavelet Daubechies 44 Filter 7c Filtered Skeletal Muscle Signal from Chebyshev Type H Filter The sEMG signals and the corresponding skeletal muscle force acquired from the standard acquisition system are given in Fig 7a 7b and 7c Since the sEMG is a random signal corrupted with noise it is hard to achieve the same correlation every time This proposed acquisition and filtering system is working better than the Half Gaussian filtering that wa
4. m 5 Scene Matching DB Send DB Debug File Save a SLAM result red line odometry path green line SLAM path blue line ceiling map b Actual data red dot SLAM path green dot odometry path black dot ground truth Figure 7 Experiment result in our test bed 109 KETI AZo eI Configuration Manager CM Save Keyframe Info Robot View Figure 8 Experiment result in the hall 5 2 Front view based localization Figure 9 shows the experimental results for scene matching For the experiments we captured the images by driving a robot in a hall environment in real time Figure 9 Secne matching results in the hall 6 Conclusions We This paper proposed the localization modules using scene recognition and ceiling segmention method The modules we developed are a single camera look at the front of the robot and looking up the ceiling which are inexpensive and easy to get everywhere Line features are extracted from images by the ceiling grouping method and parameterized as a measurement form The line features have advantages over point features for its robustness to environmental var
5. 40 30 20 Megabits sec Jas salAqesalN 10 32 Figures 5 and 6 shows the throughput tests and results of the external USB controller using only a 6MHz clock which in this case tops out at approximately 10 Megabytes sec FX2 TOP_INTERFACE otu n d x ATN RFA ADRS jpeg_top r x b H 4 kk oa a x f F nd 7 f 3 s r o D i x D 4 Ti 5 2 q jpeg_top FX2_TOP_INTERFACE Figure 7 Completed Verilog Modules to be used Now that the FPGA has a way to transport data between itself and the host computer additional modules are required interconnecting modules to pass data between the USB module and the JPEG encoder which are shown in the figure above 5 3 Planning and Developing the Interconnecting Modules JPEG Encoder gt Check Figure 8 Top level Module Connection Diagram Figure 8 above shows the top level module connection diagram of the entire project which includes the beginning and ending interconnection modules In Figure 8 the initial interconnecting module colored in yellow has been tested and verified of its output data towards the JPEG Encoder by reinterpreting the included testbench from the encoder The next step is to plan build and finalize the ending interconnecting module Combine_final_data in red SO that the USB_FX2_Control module is able to accept the output data and send it to the host co
6. CI 1 54 Lt 0 0 5 1 1 5 2 sample tick 7 10 Fig 7 The merged waveform phase detection using derivative based 4 Further Discussions The accuracy of phase delay detection is fundamentally based on cross correlation of two channels where the number of total correlated samples used will play an important role depending on the channel noise This is more important for the derivative based cosine term detection than the sine term itself as seen from equation 3 at the critical boundary crossing angle 90 degree Besides using more correlated samples in a closed loop system more iteration may be used to remedy inadequate accuracy of cosine term detection around the critical point to control the system in a stable state 5 1 References J Ge and A Siggia Weather Radar Virtual Signal Generator as Test Bench for Algorithm Development The 16 Symposium of Meteorological Observations and Instrumentation 92 AMS Annual Meeting New Orleans USA 22 26 January 2012 2 J Ge Model and Algorithm for Fractional Delay HPF 3 4 The 2011 International Conference on Scientific Computing Las Vegas USA 18 21 July 2011 T Laakso V Valimaki M Karjalainen and U Laine Splitting the Unit Delay IEEE Signal Processing Magzine Jan 1996 RVP900 User s Manual Vaisala Feb 2010 67 68 Int l Conf Embedded Systems and Applications ESA 12 Int l Conf Embedded Systems an
7. Figure 1 Tradeoffs between different fault tolerant schemes 93 94 iv Check pointing 7 in check pointing Safety Critical task is divided into n sub tasks and each sub task contains a check point appended by either a programmer 8 or by the compiler 9 Fault is detected based on these check points In case of fault there are two options either to roll back or roll forward This scheme is helpful in avoiding the transient faults However a combination of active replication and re execution Fig 1 e provides more optimized system design and better CPU performance from the scheduling point of view and thereof provide Fault tolerance under limited resources 2 Problem Statement The primary objective of FCSA is to provide QoS in terms of CPU performance and resource utilization by keeping CPU utilization at schedulable bound However the design methodologies of the real time embedded systems having Feedback based scheduling algorithms are based on the separation of the concerns 15 These concerns are derived from the assumptions that the feedback controllers can be designed by assuming the fixed predefined mapping fixed time period and hard deadlines These assumptions are widely used in the control community because they help the control embedded system designer to design control loops without concerning the dependability of the over all system in the presence of faults This paper presents a new methodology of attaini
8. Methodolgy Results and Discussion are presented The paper is concluded with the section of Conclusion and Future Work 144 Il EXPERIMENTAL SET UP Using a muscle stimulator Richmar HV 1100 the motor point for the ring finger of the dominant hand of a healthy male subject is identified Prior to affixing the sEMG sensors the skin surface of the subject was prepared according to International Society of Electrophysiology and Kinesiology ISEK protocols Different sets of experiments were conducted with DE 2 1 and DE 3 1 DELSYS Bagnoli sEMG sensors One sensor was placed on top of the motor point location and two sensors were placed next to the motor point The subject was asked to squeeze the stress ball with the ring finger which has a 0 5 inch force sensing resistor from Interlink Electronics mounted on it The sEMG and skeletal muscle force signals were acquired using the 16 channel DELSYS Bagnoli sEMG and NI ELVIS respectively Using a PIC 32 embedded platform A similar experimental set up was designed where the sEMG and the force data was acquired In both the cases data was captured at a sampling frequency of 2000Hz Fig 1 and 2 show the two experimental set ups DELSYS sEMG System Fig 1 Experimental Set Up with NI ELVIS and DELSYS EMG System IHI SIGNAL PRE PROCESSING From the authors previous research 16 shows that the Bayesian based filtering method yields the most suitable sE
9. IGLOO Low Power Flash FPGAs Datasheet Available on https www actel com products igloo docs aspx 21 Teich J et al Invasive Computing A novel Parallel Computing Paradigm 47 Design Automation Conference DAC The USA 2010 Int l Conf Embedded Systems and Applications ESA 12 OEDF Optimal Earliest Deadline First Preemptively Scheduling for Real Time Reconfigurable Sporadic Tasks Hamza Gharsellaoui Mohamed Khalgui Samir Ben Ahmed INSAT Institute University of Carthago Tunisia ITIA Institute CNR Research Council Italy SF ST Faculty University of Tunis El Manar Tunisia ABSTRACT This paper deals with the problem of scheduling the mixed workload of both uniprocessor on line spo radic and off line periodic tasks in a hard reconfig urable real time environment by an optimal EDF based scheduling algorithm Two forms of automatic reconfigurations which are assumed to be applied at run time Addition Removal of tasks or just modifi cations of their temporal parameters WCET and or deadlines Nevertheless when such a scenario is ap plied to save the system at the occurrence of hardware software faults or to improve its performance some real time properties can be violated at run time We define an Intelligent Agent that automatically checks the system s feasibility after any reconfiguration sce nario to verify if all tasks meet the required deadlines Indeed if the system is unf
10. 10 11 12 13 14 113 REFERENCES E D Adamides P Lliades I Argyrakis P Tsalides A Thanailakis Cellular logic bus arbitration IEE Proc Computers and Digital Techniques vol 140 no 6 pp 289 296 Nov 1993 S Murugesan Use priority encoders for fast data comparison Electronic Engineering vol 42 pp 24 July 1989 H M Lam C Y Tsui A MUX based high performance single cycle CMOS comparator IEEE Trans on Circuits and Systems Part II Express Briefs vol 54 no 7 pp 591 595 July 2007 J L Hennessy D A Patterson Computer Architecture A Quantitative Approach 3 edition Morgan Kaufmann Publishers NY 2002 R Hashemian Highly parallel increment decrement using CMOS technology Proc 33 IEEE International Midwest Symposium on Circuits and Systems vol 2 pp 866 869 1991 C H Huang J S Wang Y C Huang Design of high performance CMOS priority encoders and _ incrementer decrementers using multilevel lookahead and multilevel folding techniques JEEE Jour of Solid State Circuits vol 37 no 1 pp 63 76 Jan 2002 J G Delgado Frias J Nyathi D H Summerville A programmable dynamic interconnection router with hidden refresh IEEE Trans on Circuits and Systems Part I vol 45 pp 1182 1190 Nov 1998 D H Summerville J G Delgado Frias S Vassiliadis A flexible bit pattern associative router for interconnection network
11. 2 The minimum number of satellites to determine the user s PVT on the moon 3 The optimized orbital parameters for the constellation a The time it takes for the satellite to orbit around the moon b The shape of the orbit Int l Conf Embedded Systems and Applications ESA 12 c The altitude and inclination d The number of orbital planes to be used 4 The signal transmitter power 5 The optimal level of redundancy First there is a relation between points one and two where one can be thought of as a subset of two This is generally because the minimum number of satellites to cover the planet is related to how many are visible at a given time from a specific position on the planet Since this number is usually less than the minimum number of four visible satellites for GPS then this is why it is a subset Next point three modifies the first two since those parameters are used to determine the minimum number of satellite coverage Point four affects 3 3 because the more powerful the transmitter the higher the satellite altitude can be Finally point five is important because although to create redundancy one simply needs to place more satellites or planes in orbit placing too many extra satellite is not only costly but if the number of satellites is too large they can cause a singularity to arise in the pseudorange vectors causing errors to grow in the PVT measurements Therefore an optimal number of redundant
12. The top left corner of the window shows the 3D depth map and the top right portion shows the skeletal frame The color video stream from the RGB camera is displayed on the right bottom to show the ambient lighting in the room The text display shows whether there is a danger condition or not and the frame rate of the captured data at the bottom left Figure 4a shows the simulation window in a well lit room 800 lumens and Figure 4b shows the simulation window in a poorly lit room 10 lumens In Figure 4c the simulation is shown in a dark room 0 lumens It can be seen that the skeleton of the subject is tracked despite the absence of ambient lighting in the room Int l Conf Embedded Systems and Applications ESA 12 For simulation purposes the pre determined gesture that the system was programmed to recognize was raising both arms up and holding it perpendicular to the body This gesture was chosen as it is a highly unlikely event when someone lies down in bed The subject will have to hold that position for a set amount of time for the gesture to be recognized The time required for testing purposes was set to 3 seconds If the position is not held for 3 seconds the predictable matching algorithm will re analyze the frames from the following frame onwards Figure 5a shows a danger scenario recognized by the MR BEAS Recognition of the danger condition by this system in a dark room is shown in Figure 5b The performance of the
13. There are several technologies to monitor hard disk drive errors and correct them As Error handling mechanism like Error Correcting Codes ECCs Low Density Parity Check Codes LDPC used in hard disk drives In additional Self Monitoring Analysis and Reporting Technology S M A R T keep surveillance of hard disk health and make a pre Alert before hard disk going to die But practically about 56 of the hard disk drives failed without any S M A R T warning 1 That conditions come due to firmware corruption electrical components burn or moving mechanical parts can deteriorate and break 3 1 1 Main causes of hard disk drive failure There are some main causes of hard disk failure e Head failure e Degradation of magnetic media e Firmware Corruption e HDD Electronic failure e Failure of the Motor Int l Conf Embedded Systems and Applications ESA 12 3 2 IT admin or user error Human error accounts the second most data loss causes on NAS storage A person organization can face the problem of Accidental Deletion Re Formatting making wrong configuration can lose most sensitive data And there some critical situations can created by admin users as modification and overwrite of data that arise up unrecoverable condition Sometime admin user does not notice or ignore the error massages by NAS device or application software That makes admin to follow wrong decision and maintenance procedures If A NAS device needed maintena
14. ack public static native void setInput0 int input ye input PCLK APB Signals public static native int getMac0O input 31 0 PADDR ae input PWRITE native processing method TE public static native void process output PREADY loading library static System loadLibrary AesCmac output 31 0 req request signal output 31 0 key0O input signals input 31 0 mac3 output signals input 31 0 ack acknowledge signal always posedge PCLK APB register write if PSEL amp PADDR BASE 32 h00000000 amp req lt PWDATA always posedge PCLK APB register write Fig 9 AesCmac java Translated if PSEL amp PADDR BASE 32 h00000004 amp AES CMAC Device Driver ce xy always posedge PCLK APB register read if PSEL amp PWRITE amp PENABLE case PADDR BASE 32 h00000024 PRDATA lt mac0 BASE 32 h00000028 PRDATA lt macl include lt jni h gt include AesCmac h user defined base address define BASE Oxffff0000 native set get functions JNIEXPORT void JNICALL Java_AesCmac_setKey0 JNIEnv env jclass cls jint i volatile int BASE 0x00000004 i endcase endmodule Fig 11 AesCmacReglF v JNIEXPORT void JNICALL Java_AesCmac_setInput0O JNIEnv env jclass cls jint i volatile int BASE 0x00000014 i Fig 11 sh
15. Boosting the Performance of Embedded Vision Systems Using a DSP FPGA Co processor System IEEE International Conference on Systems Man and Cybernetics pp 1142 1146 2007 11 Kumar A et al gt Mapping Algorithms for NoC based Heterogeneous MPSoC Platforms 12 Euromicro Conference on Digital System Design Architectures Methods and Tools 2009 12 Meyer Baese U Digital Signal Processing with Field Programmable Gate Arrays 2 Edition Springer October 2003 Estimating Power for ADSP Blackfin Processors December 13 Analog Devices BF53 1 BF532 BF533 2007 14 Actel Power Calculators for Igloo Available on http www actel com techdocs calculators aspx Accessed on July 2012 15 Tung D and Yang G H 264 AVC Video Encoder Realization and Acceleration on TI DM642 DSP 2009 16 Fraunhofer Institute H 264 AVC Reference Software Encoder Available on http Aphome hhi de suehring tml 2011 ADSP BF533 Hardware 17 Analog Devices Inc Reference 2009 18 Intel Inc Absolute Difference Motion Estimation for Intel Pentium 4 Processors available on http software intel com en us articles absolute difference motion estimation for intel pentiumr 4 processors 2011 19 Analog devices Inc Cycle Counting and Profiling July 2007 Available on http www analog com static imported files application_notes EE 332 20 pdf 20 Actel
16. Hyper jmt W Sanaitieity m 1 0 70 Rabe Srmoitesy 4 WHS ines oo 0 Figure 9 Select mode VVI Note that the mode VVI supports hysteresis and rate smoothing so the corresponding default values for those parameters are shown and they may be changed by the user To program the pacemaker the user simply needs to click on the button to Connect to the Pacemaker if they are not already connected and then click on the Program Pacemaker button to download the parameters to the pacemaker via the DCM Agent where they will be stored in EEPROM The PIC 18F4520 has 256 bytes of EEPROM Once the new parameters are downloaded a mode change is initiated and the new real time data can be observed In this case pacing rate changes are displayed using up and down arrows as shown in Figure 10 Note that even though some heart beats are not sensed the pace generator may not automatically pace for up to two regular heart cycles For this example the signal generated to represent a heart beat is still a square wave with a peak of 59 mV generated at 60 beats per second We found that some beats were not detected at 59 mV but all beats were detected with an amplitude of 69 mV A variety of different tools can be used to generate input signals with different shapes and 19 20 amplitudes including National Instruments Signal Express MATLAB or pydagqtools a Pacem ae Tees Cero Lion oceans HF Paben mimin Perai Comihgp
17. In the study of the EDF policy it is necessary to us to know at the certain moments the workload in wait of treatment of which the execution must be ended be fore a certain deadline So we propose one function of workload with deadline e In the instance level Win t d Skan Akit d fi IT n u d du a Where Mra id Meg ji Mae a Wk n t d is the amount of job with lower deadline to d brought by the instance Tk n which again is to be executed at the moment t If Ag 0 we restreint to the case of synchronous tasks e In the task level W t d S Agi t d i Due Want d Where W t d is the amount of job with lower dead line to d brought by all the instances of 7 which again is to be executed at the moment t u d du e For a set of tasks I for the Currentp t Enew U Eola We propose Weourrentr t t d Dit rinCurrentr t W t d Sure Akit d fi Ir u d du Where Wourrenty t t d is ahe amount of job with lower deadline to d brought by all the instances of tasks that composed C urrentr t which again is to be executed at the moment t Int l Conf Embedded Systems and Applications ESA 12 4 CONTRIBUTION 2 AGENT BASED REAL TIME RE CONFIGURABLE MODEL this section aims to propose an intelligent Agent based architecture which is able to propose technical solu tions for users after any dynamic reconfiguration sce nario 4 1 Agent s Principal Let I
18. Jorge Estrada Adrienne Lam Sergio Mendoza Aleksander Milshteyn Dr Helen Boussalis Dr Charles Liu Structures Propulsion and Control Engineering University Research Center SPACE URC California State University Los Angeles 5151 State University Drive Los Angeles CA 90032 Abstract This paper focuses on porting specific ubiquitous computing applications by providing acceleration for a Semantic Information System SIS 1 The necessary connectivity protocol for multimedia data transfer on a Field Programmable Gate Array FPGA chip via USB has been fully implemented The SIS network applications that were designed by the CSULA SPACE Center are geared towards providing education oriented users with a real time virtual environment that allows collaboration in conjunction with distant communication and interaction The SIS includes applications for its network participants such as the multicasting Ubiquitous Video Conferencing the Scraping Tool for metadata processing multi touch user interface etc However the power consumption and computing resources of the client system can be in heavy demand by the SIS participants due to real time video decompression and compression respectively The proposed approach can help by conserving the client s resources which can lead to an acceleration of SIS functionalities Keywords FPGA Semantic Conferencing Ubiquitous connectivity 1 Introduction The Ad
19. Keywords Real Time System Scheduling analysis EDF dPTPN 1 Introduction Multiprocessor architectures are becoming increasingly used in several systems such as the Real Time system RTS It can explain the growth of the variety of research results The main research area is the scheduling analysis of the real time application running on a multiprocessor architecture Hence two main scheduling families exist The first family is called the global scheduling in which all the tasks are charged on only one queue In fact although each task can migrate among the processor resources to achieve its execution the cost of migration is so important and there are no optimal scheduling algorithm 16 As for the second family it is the partitioned scheduling in which each processor resource has its own queue When a task is assigned to one processor then it cannot migrate to another In fact this strategy presents a reduction of the multiprocessor scheduling to single processor where the optimality is proved 19 The partitioned scheduling is based on two procedures the first of which is assigning tasks to processors and the second is analyzing the scheduling of each partition 20 It is so important to detect the scheduling faults at an early stage in order to minimize the costs for its correction Therefore to protect such systems from problems and fail ure it is necessary to implement formal techniques intended to make reliable the de
20. Technology AC164127 gs sGAEpiMZZMu6TJb8E8Cjryzyow YGDGw 252b 6 MPLAB IDE http www microchip com stellent idcplg IdcService SS_GET PAGE amp nodeld 1406 amp dDocName en019469 7 MPLAB C Compiler for Academic Use http www microchip com stellent idcplg IdcService SS_GET PAGE amp nodeld 1406 amp dDocName en536656 8 http www microchip com stellent idcplg IdcService SS_GET_PAGE amp nodeld 2680 amp dDocName en554272 9 http www microchip com stellent idcplg IdcService SS_GET_ PAGE amp nodelId 2680 amp dDocName en554265 10 Microchip Graphics Library http www microchip com stellent idcplg IdcService SS_GET PAGE amp nodeld 2680 amp dDocName en54309 1 11 Whitman Neal A Peer Teaching To Teach is to Learn Twice ASHE ERIC Higher Education Report No 4 Washington D C Association for the Study of Higher Education 1988 Int l Conf Embedded Systems and Applications ESA 12 131 A Hardware Software Co Design Method for Java Virtual Machine Oriented to High Level Synthesis Hitoki ITO Kiyofumi TANAKA School of Information Science Japan Advanced Institute of Science and Technology Nomi Ishikawa Japan Abstract We propose a _ hardware software co design method that covers the weakness of high level synthesis and maximizes the benefits of high level synthesis We view the high level synthesis process from the standpoint of granularity of operations and I Os and introduce an I O library composed of
21. be the set of all possible tasks that can imple ment the system and let us denote by Currentp t the current set of periodic asynchronous tasks implement ing the system at t time units These tasks should meet all required deadlines defined in user require ments By considering a feasible System I before the application of the reconfiguration scenario each one of the tasks of osi is feasible e g the execution of each instance is finished before the corresponding deadline In this case we note that Feasibility Currentp t True An embedded system can be dynamically reconfigured at run time by changing its implementation to delete old or to add new real time tasks We denote in this research by Enew a list of new asynchronous tasks to be added to Currentp t after a particular reconfigura tion scenario In this case the intelligent agent should check the system s feasibility that can be affected when tasks violate corresponding deadlines and should be able to propose technical solutions for users 4 2 First Case Minimizing the re sponse time of periodic tasks In this case the objective is to reduce the periodic response times as much as possible still guaranteeing that all periodic tasks complete within their deadlines 1 We define in this solution a perfect admission con troller as a new heuristic which is defined as an ad mission control scheme in which we always admit a task if and only
22. events such as click drag and drop and so on There are three kinds of GUI test technique Record Play Back RPB technique is the most famous and is known well among them because to use it is easier than the others In the RPB technique one event is called the Record and script includes several records 7 In testing phase with GUI test technique one developer makes an event script which contains sequence of events and then feed each event from the script For applying the RPB technique to the android software testing it firstly needs to consider how to adopt concepts of android software such as Activity Intent and so on It also adds new method to reduce effort for making test case because there is no support to generate a test case automatically 2 2 Design of ACSF Developers have several tasks for software test for example making a test case running the test case analyzing a log Some logs are generated during running software via logging instructions Developers try to detect potential errors in the logs A role of ACSF reduces tasks of developer hence architecture of ACSF is considered android platform and technique about automatic comparison logs like Fig 1 Program Analysis Component Monitoring CodeGenerating Component Monitoring Sensor Gen Program Analysis gt E Q 3 3 Program Auto Analysis Info Monitering Sensor Monitoring Generator T lat Code Gen Sopan Test Component Compi
23. no pp 1160 1163 27 30 Oct 2010 What 1S Android i Available http developer android com guide basics what is android html MC9S08JM60 Microcontroller Data Sheet January 2012 Available http www freescale com webapp sps site prod_summary jsp code S08JM amp nodeld 0162468449 1437 10 ADS1298 Technical Reference Manual Available http www ti com product ads 1298 11 DM37x Applications Processor Texas Instruments Technical Reference Manual January 2012 Available http www ti com lit ds symlink dm3730 pdf 105 106 Int l Conf Embedded Systems and Applications ESA 12 Ceiling view and Front view Localization Module with Single Camera for Mobile Robot Seung Hun Kim Changwoo Park Intelligent Robotics Research Center Korea Electronics Technology Institute Bucheon Gyeonggi do Korea Abstract This paper presents a localization module for mobile robot that travels around indoor environments Our module uses the only one sensor a single camera that looks at the front of a robot or looks up the ceiling There is no efficient enough SLAM algorithm working on embedded system The initial difficulty of vision based SLAM is computational complexity to acquire reliable feature on their algorithm To reduce the computational complexity we use the ceiling segmentation to extract line features of ceiling area Line features are extracted from the boundaries between the ceiling and walls Extended
24. 2007 6 Z Karakehayov Hierarchical Design Model for Embedded Systems IEEE International Workshop on Intelligent Data Acquisition and Advanced Computing Systems Technology and Applications September 2009 7 M Muller J Cerlach and W Rosenstiel RTOS Aware Modeling of Embedded Hardware Software Systems IEEE International Conference on Computer Design ICCD 2010 8 A Dunkels Protothreads Simplifying Event driven Programming of Memory constrained Embedded System in ACM Sensys 2006 9 S Bhatti J Carlson H Dai J Deng J Rose A Sheth B Shucker C Gruenwald A Torgerson and R Han MANTIS OS An Embedded Multithreaded Operating System for Wireless Micro Sensor Platforms Mobile Networks and Applications MONET Journal Special Issue on Wireless Sensor Networks Aug 2005 10 J Lee and J Yi Improving Memory Efficiency of Dynamic Memory Allocators for Real Time Embedded Systems ETRI Journal Volume 33 Number 2 April 2011 11 C Jang S Lee S Jung B Song R Kim S Kim and C Lee OPRoS A New Component Based Robot Software Platform ETRI Journal Volume 32 Number 5 Oct 2010 64 Int l Conf Embedded Systems and Applications ESA 12 Derivative Based Quadrature Identification of Channel Delays Jinming Ge Vaisala Inc Louisville CO 80027 USA Abstract Real time detection of phase or time delay between two ADC sample channels especially
25. 4 2 Software The various software portions of the home automation system enable the full energy conserving potential of the system By using assembly language to integrate the aforementioned hardware components with the ZigBee RF standard the home automation system becomes a wireless device Use of an iDigi ConnectPort X4 ZigBee to Ethernet gateway and the proper Python programming makes the system internet enabled Finally in order to provide a user friendly interface the HTML and CSS programming languages are used to develop a web based control interface 4 096MHz U1 Figure 7 SPI and Data Connections between the CS5460A and the PIC16F882 REYMCLRivee 28 REMICSPDAT RAO ANO ULPWUICI2INO 2 27 _ RBBICSPCLK RAVANICI2INI 3 26 RBS ANI3 T1G RAZIAN2 VREF CVREFIC2INe 4 25 _ e RB4 ANIIPID RAVANSVREF iCiIN 5 2 REVANSPGMICIZ2INZ2 RASITOCKUCIOUT 6 fal 230 RBJANAPIB RASIANA ISSIC2Z0UT 7 22 RBI ANIO PICICI2IN3 Vss 8 n 31 RBVANIMNT RATIOSCIICLKIN 9 5 RABIOSC2ICLKOUT _ 10 RCOTIOSOTICK 11 a RCUTIOSUCCP 2 12 RC2IPIAICCP1 e 13 16 RCS SDO RCVSCKISCL e 14 15 _ RC4 SDUSDA Figure 8 USART Connections between the XBee and PIC16F882 4 2 1 Assembly The PIC16F882 microprocessor used in the system was programmed with the Micr
26. 95 96 Notation Transpose of a matrix M is denoted by M M gt 0 or M lt 0 when is a symmetric positive or negative definite matrix and a symmetric matrix E A as i T Limit from below of a signal y t by y t where y t lima y d At kt time and time dealy in the it subtask is denoted by sampling interval st delay time d At the sampling time s where k N the process s state x s is sent to the processor responce arrives at st diand the next sampling interval is updated at si dt For simplicity SISO system mentioned in Fig 5 is considered However the similar procedure can be extended to MIMO 22 The resulting SISO close loop system mentioned in Fig 6 with sampling interval st delay time di and having a time varing job x t is molded as x t 1 Ax t Bu s ti lt t lt ti andk eN 3 B Bk amp Where x E L and u E L System mentioned in 3 represents an impulsive hybrid system as a new state can be defined as q1 t x st with ti lt t lt ti So 3 can be written as where tj Sk dpa S t FS t 6 Ste TE 4 S t ieN 5 where F i amp S t bird Equations 4 5 completely define the behaviour of the system Equation 4 indicates the response of the system between two sampling intervals and 5 addresses the abrupt changes in the system at the edges of each sampling interval Since faults can occur at any time in the system so the sampling
27. CPU performance and resource usage System response in presence of Fault and recovery schemes for hard real time systems to achieve dependability in X by Wire XBW systems is presented in 29 and 30 A fault tolerant scheduling for hard real time systems is addressed in 38 but this work only focuses on maintaining CPU scheduling with specified scheduling bound by making sure that SC tasks will meet their deadlines Moreover this work doesn t capture the state of the task in Fault mode and provides less information about data loss To the best of our knowledge this is the first work that addresses dependability and feedback based control scheduling together for real time embedded systems 4 System Model System architecture constitutes a distributed shared Hardware HW platform with a network topology where every hardware node can communicate with every other node Fig 2 shows the high level model of the system architecture and resources elaborating the partitioning concepts It also describes the application execution environment where nodes are connected through a network bus Each node has two cores one core is completely dedicated for the safety critical tasks and second one is dedicated for the non safety critical tasks Each node has a capability of executing both SC and non SC tasks Node resource consists of a CPU I O controller sensors and actuators RAM ROM and a Feedback based scheduling Controller FSC Every nod
28. Idaho State University Pocatello Idaho 83209 USA email srirgiri isu edu Shiwei Liu is with MCERC School of Engineering Idaho State University Pocatello Idaho 83209 USA email liushiw isu edu Steve Chiu is with Department of Electrical Engineering and Computer Science MCERC Idaho State University Pocatello Idaho 83201 USA email chiustev isu edu Alex Urfer is with Dept of Physical and Occupational Therapy Idaho State University Pocatello Idaho 83209 USA e mail urfealex isu edu The sEMG is the result of the electrical activity during skeletal muscle contraction It ranges between 5 and 5 mV The sEMG signals are widely used for the position and force control of the hand prosthesis 5 6 Since the skeletal muscle force and the sEMG signals are directly proportional an increase in force production results in increased sSEMG activity Therefore the latter is used as a control input to realize force and motion control of a prosthetic hand This makes the precise interpretation of the sEMG signal an essential task In the present research environment embedded systems have become pervasive and as research advances more and more functions of analog circuits are being realized by microcontrollers Analog to Digital Converters ADCs and Digital to Analog Converters DACs In a modern control system data acquisition processing and control functions are performed by embedded systems A well designed embedded cont
29. ItemNumber Change TaskChange void pdata while 1 ItemNumber int OSMboxPend Change 0 amp err j j Communication among key tasks Int l Conf Embedded Systems and Applications ESA 12 3 4 Checkout logic In Fig 1 the area where was circled by dashed line is the brain of the vending machine When 7askCheck is running to here vending machine will decide how to respond to the customers according to such logic as Fig 2 This frame will have checkout logic deal with as many as items under the current situation meanwhile pause the TotalMoney item waiting K 1 Deliver 2 Remind inputting money or give up shopping 2 Update total money 3 Remind going on select 2 item or give up shopping 1 Deliver 49 TaskCheck so to deal with the input of customers to show its humanization As the interaction between vending machine and customer goes on the whole system will definitely fall into one of three situations 1 The total money is equal to the value of current item 2 The total money is more than the value of current item 3 The total money is less than the value of current item current itemvalue Totalmoney gt current itemvalue 1 Deliver 1 Recover item queue to previous status Remind inputting money or give up shopping Fig 2 checkout logic Table 3 Testing Case Summa Operation type Testing goal To make sure the hardware resource Single operatio
30. The considered application Robot Footballer requires the transmissions of data between the tasks Indeed some tasks are preceded by some others as indicated in Fig 1 Thus the preceded task can be activated only after receiving data from its corresponding preceding task Hence the transmissions Int l Conf Embedded Systems and Applications ESA 12 time of data between tasks is negligible thanks to the high speed of the used DMA As a consequence the input task sends the information as soon as it finishes all or a part of its activity without the risk of waiting Formally the precedence relations between all tasks are described in Q via the Prec function Fig 7 shows the dPTPN model for the communication P1UnCreated P1Deadline P1Remaining Period P1Received Data PiReady T1Receiving Q P1DataToSend P1Release Proc T toT T1Sending P4UnCreated P4Deadline P4Remaining P4Received Period Data T4Receiving P4Ready TaskC amp P4getProc P4Release Proc T toT P4DataToSend T4toT4 T4Sending Fig 7 Communication between T1 and T4 between 7 1 and T4 The current marking presents a mark in the output place P1DataToSent of the TaskC It in dicates that the task 7 1 has finished an instance of execution during its period and is ready to send the necessary data for the activation of T4 The immediate transition J 1Sending is enabled and its firing allows th
31. affects the performance and their results show that bigger sizes does not deliver better performance all the time however they didn t consider power in selecting the cache sizes that deliver optimum performance per power which is one of the most important parameters in embedded applications In this paper we reduce the search space of a DSE of cache for various embedded applications considering 84 a wide range of parameters to calculate the energy consumption of the cache based on the performance analysis of 20 The aim of this research is to explore the optimum range of cache size for embedded applications based on the performance area and power constraints considering feature size effects that has not studied deeply enough 2 Performance analysis This part is based on 20 Authors of 20 did an exhaustive exploration of cache size for embedded applications considering the performance and introduced the cache size that produces lowest cycles for running an embedded application Their research showed that there is a range for L1 and L2 caches that can be applied for embedded applications They showed that although performance is improved by increasing the cache size however over a threshold level performance is saturated and then decreased Their proposed ranges for cache size are too big so in this paper by considering another important parameter of embedded processors i e power or energy consumption the range is reduced a
32. and Alfons F Sinnaeve Caridiac Pacemakers and Resynchronization Step byStep An Illustrated Guide 2nd Edition Blackwell Publ Inc 2010 4 John G Webster Design of cardiac pacemakers IEEE Press 1995 5 Richard Barry FreeRTOS Reference Manual API Functions and Configuration Options Real Time Engineers Ltd 2012 http www freertos org 6 C Nixon J Smith T Ulrich R Davis C Larson and K Cha Academic Dual Chamber Pacemaker Univ of Minnesota Final Report May 2007 7 Z Jiang M Pajic S Moarref R Alur and R Mangharam Modeling and verification of a dual chamber implantable pacemaker In Proceedings of the 18th International Conference on Tools and Algorithms for the Construction and Analysis of Systems TACAS 2012 2012 8 M L Neilsen Model checking task sets with preemption thresholds in Proceedings of the 17 International Conference on Parallel and Distributed Processing Techniques and Apps PDPTA 11 Paper No PDP4007 July 2011 9 M L Neilsen Symbolic schedulability analysis of task sets with arbitrary deadlines in Proceedings of the 16 International Conference on Parallel and Distributed Processing Techniques and Applications PDPTA 10 Paper No PDP4851 July 12 14 2010 21 22 Int l Conf Embedded Systems and Applications ESA 12 2LGC An Atomic Unit Garbage Collection Scheme with a Two Level List for NAND Flash Storage Sanghy
33. c arar F Hela ltt w m m a o a MW tommo M N MO Figure 9 CPU Utilization for Experiment 2 12 Conclusion This paper provides a novel technique of designing a dependability driven feedback based control scheduling for real time embedded systems System architecture presented in this paper is robust against the execution variation CPU utilization of jobs schedulable to a certain extent 9 It is also evident from the experiments that in order to achieve a system with higher dependability reliability and security tradeoffs have to make between the CPU utilization and the number of SC tasks to be scheduled on a particular processor It is also observed that from g 1 25 7 0 dependability driven FCSA remains robust schedulable after that the number of sampling intervals jobs over the network exceeds the upper bound 9 and the completion time of SC tasks exceeds their WCET and SC tasks started missing their deadlines Greater number of sampling intervals leads to higher reliability avoid greater number of faults but on the other hand the task execution time increases Increasing sampling intervals beyond required bound can also leads to network instability To achieve high QoS CPU utilization and resource allocation a balance has to be made by the designer between the numbers of SC tasks to be scheduled on a particular processor the degree of replication and sampling intervals 9 for each SC task CPU utilization and bandwidth
34. cache is for reading or writing so E is affected by both reads and writes so Etd Edr Edw 2 Where Ez and Em are dynamic read and write energy dissipation respectively In our exploration we explore the cache memory in all levels including instruction cache level 1 L data cache level 1 D and unified cache level 2 L3 E4 is related to the number of reads Nreaq from all caches number of read multiply by dynamic read energy of cache SO Edr Nread L1 Edr L1 Nread D1 Edr D1 Nread L2 Edr L2 Nread Maim_memory Edr Main_memory 3 And Edw Nwrite L1 Edw L1 Nwrite D1 Edw D1 Nwrite L2 Edw L2 Nwrite Main_memory Edw Main_memory 4 Where Nwrite 1s the number of writes and for example Egy D1 is equal to the dynamic write energy of D1 On the other hand E is calculated from accumulating the consumed static energy E of all caches In case of a cache miss miss penalty which is related to the idle cache must be tolerated by the system In this way for a cache miss penalty is considered as the cycles which are required for accessing the lower layer cache Therefore Es Nmiss miss penalty cycle idle cycles 5 static energy per access And Ets Es L1 Es D1 Es L2 6 To use this power model effects we have used CACTI 5 0 18 a tool from HP that is a platform for extracting parameters relevant to cache size considering fabr
35. d z er min 272 cJ Ca C and 8 resulting at yi and y resulting Int l Conf Embedded Systems and Applications ESA 12 Eo d is the limit when n aims towards the infin ity of the suite l 1 C and Ep 2 d E d Eo d is the limit when n aims towards the infinity m Boa d D sn min EE 89 of the suite Ef d e E 3 d p nn 5 Where is a positive and unimportant but necessary real value to affect the convergence For every value of d D respectively D and D2 the corresponding response time is E Rg Eo d d Dx the biggest value is the border of the response time Rik ymax i Rg 2 Eo 2 d d Dx the biggest value is the border of the response time Rik 2maz i Rg 3 Eo 3 d d Dx the biggest value is the border of the response time Rik 3 maz We define now Rp optimal noted R according to the previous three solutions calculated by the intelli gent Agent Solution 1 Solution 2 and Solution 3 by the following expression R min Rk a1 Ree Reg the minimum of the three values h So the calculation of R allows us to obtain and to calculate the minimizations of response times values and to get the optimum of these values 5 3 Algorithm Begin Algorithm Codel1 Removal_Tasks U 0 e For each partition O C Eola U Enew 1 x U Ci
36. flag The number of entries in a page map table is the same as the number of pages in the flash storage If the storage access request from the host is issued to the flash storage the FTL searches the 31 bit PPNs of the page map table using the LPNs if a physical page size of 8KB is assumed the 31 bit page number can represent 2 bytes or 16TB On the other hand the FTL has to check the page validation mark flag using the PPNs in order to confirm whether or not the data in physical page space are valid The address space can be more efficiently saved by combining a 31 bit PPN and a 1 bit page validation mark flag into a single 32 bit I O bus width regis ter There are six entries in the block map table as shown in Figure 2 b The usage of each entry is as follows First 2LGC uses three flags for supporting address translation A 1 bit bad block mark flag a 1 bit free mark flag and a 1 bit erase mark flag represent whether the physical block is bad or not free or not and erased or not respectively Second 2LGC uses two page offset entries for maintaining page in formation within a block An 8 bit invPage offset shows how many invalid pages are involved within a block and an 8 bit curPage offset explains which page of the block is available for programming Lastly the 13 bit eCount number stands for the number of times each block has been erased 4 2 Single Block Garbage Collection The FTL selects multiple victim blocks copies
37. frequency multiplication in DSP applications multipliers cause a lot of power consumption Therefore low power multiplier design is required for power aware devices A conventional array multiplier 2 has higher switching activity To avoid redundant switching transitions can reduce the dynamic power thus the low power multiplier with the row bypassing method 3 and the low power multiplier with the column bypassing method 4 reduce switching transitions to save dynamic power Previous designs 5 6 use the same bypassing methods but modify the full adder circuit to reduce power consumption Another design is based on a simplified add operation 7 that combines multiplexers tri state buffers and other logic gates to form a full adder circuit Their full adder circuits design can reduce power consumption because they use few transistors This paper presents a low leakage and low dynamic power multiplier with alternative bypassing implementation The rest of this paper is organized as follows Section II reviews the conventional array multiplier design and previous work on multiplier with bypassing methods Section HI describes the proposed multiplier design The Section IV gives simulation results and analysis Finally Section V offers some brief conclusions Il RELATED WORKS A Conventional Array Multiplier Consider two unsigned N bit binary numbers Y Yn 1Yn 2 Yo and X Xp 1Xp 2 X9 Which represent the multiplicand and
38. intelligent thinking mode Intelligent thinking mode comes from effective communication among those related tasks Intelligent thinking mode will make vending machine humanized 6 References 1 LIU Fang 1997 17 4 24 25 2 Jean J Labross MicroC OS II The Real time Kernel Second Edition Beijing University of aeronautics amp astronautics press China 2006 3 3 Zhou Ligong Notebook about ARM Embedded System application technology based onLPC2400 Guangzhou Zhiyuan Electronic Co Ltd 4 Zhou Ligong Architecture of ARM7 LPC2400 Guangzhou Zhiyuan Electronic Co Ltd WEI Lili Science and management Int l Conf Embedded Systems and Applications ESA 12 NAS Storage and Data Recovery Deepak Kumar Amity School of Engineering and Technology Amity University Universe Infosoft Noida Uttar Pradesh India Abstract Today NAS is a common storage device wildly used by home users small offices or even medium size organization to storing theirs information NAS provides greater data protection and higher storage capacities with different types of RAID configuration on its specialised hardware software combination Even though it provides much higher protection as compared to traditional storage media yet it cannot use as a complete fault tolerant perfect reliable storage device In spite of NAS device importance here is relatively little research work on the failure patterns of NAS device T
39. using CMOS technology the longest signal propagation path usually consists of a series connection of either pMOS or nMOS transistors with the latter being preferred on account of improved speed 6 Hence higher order priority encoders are constructed by cascading smaller size priority encoder blocks based on a look ahead scheme similar to that of adders Few novel look ahead schemes have been proposed by researchers 11 6 13 among which the parallel priority look ahead strategy discussed in 13 appears to be elegant enables high speed and also results in low power The novel 8 bit CMOS priority encoder module to be described in this paper is suitable for composing higher order priority encoders based on the look ahead architecture elucidated in 13 The remaining part of this paper is organized as follows The proposed 8 bit CMOS priority encoder design is discussed in Section 2 and its operation is described using the output equations The simulation method and design metrics estimated for different 8 bit priority encoder blocks are given in Section 3 Finally the conclusions are made in Section 4 II PROPOSED 8 BIT CMOS PRIORITY ENCODER DESIGN The fundamental equations governing the proposed 8 bit priority encoder shown in Figure 1 are given below where PI_1 to PI_8 signify the primary inputs while PO_1 to PO_8 represent the primary outputs It is to be noted here that the primary outputs are allowed to evaluate to the co
40. 12 in which a crossing date is associated with each temporal event In fact a transition is valid when the clock shows the date of firing In addition PTPN uses a new method of priorities integration to address the problem of transitions conflict In this method a priority is inserted on the input arcs of the dependent transitions 12 Moreover this method allows to master the complexity of the PTPN model by eliminating the use of another component such as inhibitor arcs to specify priorities In 13 the authors have proposed the first PNs extension dPTPN dynamic Priority Time Priority Time Petri Nets dealing with dynamic priority via a new component Indeed the priority is relative to model state The scheduling analysis is shown through the scheduling policy LLF Least Laxity First 8 and a set of independent periodic tasks running on a multiprocessor architecture However the LLF is not frequently used in practice because the cost of preemption is so high compared to the Earliest deadline First EDF 19 In the same vein the authors have proven the capacity of the dPTPN to deal with EDF as well as with the dependent tasks in 14 However the size and the complexity is increased even though the considered RTS is more complex Hence the execution of the model and the checking of its properties is more difficult The main contribution in this paper is the proposition of a new modeling strategy to master the complexity of the
41. 2004 the first revision of the course was implemented by modifying it to use the Freescale HCS12 microcontroller Since this processor was gaining greater popularity in academic and industrial environments many useful development kits and software tools became available The HCS12 has a simple architecture that is easy to master and write programs for in assembly as well as C The hardware development kit used in the course had several built in input output devices to experiment with in labs for interfacing to external devices In the latest improvement of the MS II course we adopted Microchip s 16 and 32 bit processors as the target platforms Preceding this change the MS I course was updated to adopt HCS12 This was considered a timely move since the MC6811 that MS I had used for over a decade was getting dated Therefore the change in MS I necessitated yet another upgrade in the MS II course The use of both 16 and 32 bit architectures in the new revision of MS II allows the students to appreciate the architectural differences as well as other factors that need to be considered when evaluating processors for particular applications Both PIC24 and PIC32 are RISC processors with easy to learn programming models and come with several built in standard peripheral modules for interfacing to external devices The rest of this paper focuses on the MS II course and the recent curriculum improvements we introduced in it The main objectives fo
42. 2005 2006 CHENGDU YIWO Tech Development Co Ltd http www easeus com 10 Nick Sundby Consulting Director European Storage Copyright 2007 IDC www idc com 2012 55 56 11 Robert L Scheier Study Hard Drive Failure Rates Much Higher Than Makers Estimate Friday March 02 2007 12 Richard R Muntz and John C S Lui Performance Analysis of Disk Arrays Under Failure UCLA Computer Science Department LA CA 90024 1596 USA 13 Jeffrey Doto Brandon Krakowsky RAID Technology and Data Storage Today April 15th 2007 14 Dr Michael Cohen RAID Reconstruction LCA 2005 Security Miniconf April 2005 15 Michael J Leaver 2BrightSparks Pvt Ltd RAID is Not a Backup Solution www 2brightsparks com 16 THE BENEFITS OF NETWORK ATTACHED STORAGE Iomega Corporation www iomega com NAS Online Available http cn 1omega com nas resources nasro1 pdf 2009 Int l Conf Embedded Systems and Applications ESA 12 Int l Conf Embedded Systems and Applications ESA 12 57 Modeling and Development of a Large Application on RTOS Sang Cheol Kim Young Jin Choi and Seon Tae Kim Embedded Software Research Department ETRI Daejeon S Korea Department of Computer Software and Engineering UST Daejeon S Korea Abstract Since development environment on embedded system is usually poor it is not easy to develop a large application efficiently on RTOS If the large application can be divided in
43. 60 The left side is IX and the top side is TX where t TE In this example there are four threads t tz t3 and t The numbers in the parenthesis are the priorities for each thread The arrow indicates the relation of function calls and the black dot on cross means that the relation is only valid here e g The init creates four threads In this example the start function does not involve in threads This dot representation is used in order not to draw multiple arrows The details of the interface functions and threads were not expressed here They may be described in UML But the advantage of this model is that it is easy to understand the behavior of the sub application at a glance i init start create activate L activate shutdown f Fig 2 An example of sub application model 4 3 Modeling large application Let the large application be denoted as L Then L A D X consists of a set A of sub applications a set D of their dependencies and a connecting program X where A A An D A Aj m A Aj A m E start terminate and X is an additional program code when constituting a large program by connecting them The program code X becomes more important when there is much interaction among sub applications for integration When sub applications are merged into a big one there are two considerations One is the code with the main function and the
44. After making monitoring code it will be run on the various platforms or devices Those tasks are really Int l Conf Embedded Systems and Applications ESA 12 troublesome works because it is repetitive Compile the code first to make an APK file and then upload the APK file to emulator Finally run test cases The program auto test component supports above process automatically Users select first what device is needed a test and then they choose test case which is made in previous step They click the test case create button to generate selected test case For making the test case we use compilation technique which parses the source code and then makes an Abstract Syntax Tree AST transform the AST and travel the tree to generate the test code Transform the tree means that search several parts of code which the position for inserting the monitoring code and then insert special AST node into the tree The special AST node is made from a code which has special instruction such as printing log capturing screen and so on ACSF Project Editor Run oo Emulator List Test Case List Android_Emulator 4 Android 1 6 Android 1 6 Android_Emulator_7 Android 2 i updatel Android 2 1 7 Device List Figure 4 Automatic Execution Test case 3 3 Analyze portability Software may generate several logs post run Actually developers compare and analyze those logs They try to find differences among the logs because those must be no chang
45. Agrawal Fault tolerance in multiprocessor systems without dedicated redundancy IEEE transactions on computers 37 358 362 March 1988 P A Bernstein Sequoia A fault tolerant tightly coupled multiprocessor for transaction processing Computer 21 37 45 February 1988 J C Laprie amp B Randell Basic Concepts and Taxonomy of Dependable and Secure Computing IEEE Transactions on DependableSecure Computing TDSC 1 1 pages 11 33 2004 R M Keichafer C J Walter A M Finn amp P M Thambidurai The MAFT Architecture for Distributed Fault Tolerance IEEE Transactions on Computers 37 4 pages 398 405 1988 S Poledna P Barrett A Burns amp A Wellings Replica Determinism and Flexible Scheduling in Hard Real Time Dependable Systems JEEE Transactions on Computers 49 2 pages 100 111 2000 S Poledna P Barrett A Burns amp A Wellings Replica Determinism and Flexible Scheduling in Hard Real Time Dependable Systems JEEE Transactions on Computers 49 2 pages 100 111 2000 Avi Ziv jehoshua Bruck Analysis of checkpointing schemes for multiprocessor systems 13th Symposium on Reliable Distributed Systems 1994 K M Chandy and C V Ramamoorthy Rollback and recovery strategies for computer programs IEEE Transactions on computers 21 546 556 June 1972 J Long W K Fuchs and J A Abraham Fowrawd recovery using checkpointing in parallel systems In the 19 International Conference on Parallel Pr
46. Aperiodic OS Tasks Scheduling for Hard Real Time Reconfigurable Uniprocessor Systems Tarek Amari Hamza Gharsellaoui Mohamed Khalgui Samir Ben Ahmed Laboratory of Computing for the Industrial Systems LISI INSAT Institute Tunisia ITIA Institute CNR Research Council Italy SFST Faculty University of Tunis El Manar Tunisia abstract The scheduling of tasks is an essential requirement in most real time and embedded systems but invariably leads to unwanted CPU overheads This paper presents real time scheduling techniques for reducing the response time of aperiodic tasks scheduled with real time periodic tasks on uniproces sor systems Two problems are addressed in this pa per i the scheduling of aperiodic when they arrive in order to obtain a feasible system and ii the schedul ing of periodic and aperiodic tasks to minimize their response time In order to improve the responsiveness to both types of problems efficient hybrid approach is proposed based on the combination of the Polling Server PS and the Background Server BS The ef fectiveness and the performance of the designed ap proach is evaluated through simulation studies 1 INTRODUCTION Real time systems are used to control physical pro cesses that range in complexity from automobile igni tion systems to controllers for flight systems and nu clear power plants In these systems the correctness of system functions depends upon not only
47. B Extended Frame Format The composition of the 29 bit identifier is shown in Figure 3 The Start Of Frame SOF bit 1 the Substitute Remote Request SRR bit 13 and the ID identifier Identifier Extension IDE bit 14 is not considered for the identifier length 2 4 Navigation system messages The set of navigational messages defined in ISO 11783 7 8 is provided by the installation of a global positioning system GPS or differential global positioning system DGPS receiver on the tractor A special classification N shall be appended to the class number when the tractor is able to provide navigational information on the implement bus For example a class 3 tractor implement interfaces is able to support navigational messages can be classified as class 3N and supports the following parameters navigational system high output position navigational system position data navigational pseudorange noise statistics The navigation location parameters specified in IEC 61162 3 NMEA 2000 9 The configuration of a tractor implement connection and the offset to and from the tractor implement reference 42 points are used in the navigational parameters and in the implement configuration of process data messages 3 Test environment The task controller applications layer which defines the requirements and services needed for communicating between the task controller and electronic control units 10 Task controller is used
48. Control for Prosthesis International Conference on Embedded Systems and Applications ESA 2010 Las Vegas Nevada USA July 12 15 2010 8 C Potluri P Kumar M Anugolu S Chiu A Urfer M P Schoen and D S Naidu sEMG Based Fuzzy Control Strategy with ANFIS Path Planning For Prosthetic Hand 3rd IEEE RAS amp EMBS International Conference on Biomedical Robotics and Biomechatronics Tokyo Sept 26 30 2010 9 C Potluri Y Yihun P Kumar J Molitor S Chiu D S Naidu and S H Mousavinezhad sEMG Based Real Time Embedded Force Control Strategy for a Prosthetic Hand Prototype IEEE International Conference on Electro Information Technology Mankato Minnesota USA May 15 17 2011 10 M Anugolu A Sebastain P Kumar M P Schoen A Urfer and D S Naidu Surface EMG Array Sensor Based Model Fusion Using Bayesian Approaches for Prosthetic Hands 2009 ASME Dynamic Systems and Control Conference Hollywood California USA Oct 12 14 2009 11 C Potluri P Kumar M Anugolu A Urfer S Chiu D S Naidu and M P Schoen Frequency Domain Surface EMG Sensor Fusion for Estimating Finger Forces 32nd Annual International Conference of the IEEE Engineering in Medicine and Biology Society Buenos Aires Argentina Aug 31 Sept 4 2010 12 P Kumar A Sebastian C Potluri A Urfer D S Naidu and M P Schoen Towards Smart Prosthetic Hand Adaptive Probability Based Skeletal Muscle Fa
49. Frequency Ratio Power Consumption mW O O O O Figure 6 Overall power consumption These results emphasize the potential of the embedded MPSoC architecture for high performance computing and provide an efficient energy saving 5 Conclusions Concerning the advent of embedded multicore architectures this paper described a typical and modern scenario for these systems and from simulations it presented the feasibility to decentralize a critical path to a dedicated circuit able to run the code in parallel Besides this study presented the trade off between energy consumption and performance enhancement illustrating the potential of the embedded MPSoC architectures Also it was possible to verify that the 159 160 communication path between the PEs is a crucial point when a large amount of data needs to be transmitted Thus the current bus system is a bottleneck to handle a high amount of cores Therefore Networks on Chip NoC applying the concepts of invasive computing 22 tend to solve these limitations although it tends to increase the power consumption 6 References 1 Ventroux N et al SESAM an MPSoC Simulation Envirnment for Dynamic Application Processing In 10 IEEE International Conference on Computer and Information Technology CIT 2010 2010 1 Leupers R et al Cool MPSoC Programming In Design Automation amp Test in Europe Conference amp Exhibition DATE 2010 2 Ch
50. Keywords senior living motion recognition predictable matching algorithm emergency response sleep discomfort 1 Introduction The population above 65 years is a rapidly growing segment of the United States population The growth rate of this population is 15 1 as opposed to 9 7 of the general population between the year 2000 and 2010 1 This demands a need for more assisted living facilities Eighteen states already made statutory regulatory or policy changes in 2010 and 2011 impacting assisted living residential care communities The focal points of state assisted living policy development include life safety disclosure of information Alzheimer s dementia standards medication management background checks and regulatory enforcement The fast growing 65 or older population demands more and more caregivers working at assisted living facilities round the clock This demands automated systems to substitute certain monitoring activities Alwan et al conducted a study to assess the acceptance and some psychosocial impacts of monitoring technology in assisted living 2 They installed Monitoring systems in 22 assisted living units to track the activities of daily living ADLs and key alert conditions of residents 15 of who were non memory care residents The Activity reports and alert notifications were sent to professional caregivers who provided care to residents participating in the study They assessed the diagnostic use
51. OS APIs edre C wo thread_chain ChainTask But AVOS is slightly different from OSEK OS standard in that it supports time sliced round robin task scheduling for equal priority tasks OSEK OS supports only round robin scheduling for these tasks without time slices Another different thing is that it extended OSEK OS API shown in Table 1 OSEK OS task terminates only itself with TerminateTask function whereas AVOS thread can terminate other threads as well with thread_terminate function In this paper the term thread in AVOS was used as thread wait thread_sleep Int l Conf Embedded Systems and Applications ESA 12 the similar meaning as the term task in OSEK OS though both are not the same in practice One way to describe RTOS is to present the state diagram of thread The thread state diagram in AVOS is shown in Fig 1 The created thread is in suspended state at first with the NORMAL START option and becomes in ready state after it is activated For direct activation of thread the AUTO START option can be used All activated threads are ready to run and they will eventually run by a scheduler A thread exit thread _wait SELF thread_sleep event wait thread_terminate SELF thread_chain thread create NORMAL_START thread activate thread_resume hirea chaint event_set thread create AUTO_START Fig 1 The thread state diagram in AVOS thread can be
52. P Fournaris Fault and simple power attack resistant RSA using Montgomery modular multiplication Proc of IEEE International Symposium on Circuits and Systems pp 1875 1878 2010 10 A Pellegrini V Bertacco T Austin Fault based attack of RSA authentication Proc of Design Automation amp Test in Europe Conference amp Exhibition DATE pp 855 860 2010 11 JeaHoon Park SangJae Moon DooHo Choi YouSung Kang JaeCheol Ha Fault attack for the iterative operation of AES S Box Proc of 5th International Conference on Computer Sciences and Convergence Information Technology pp 550 555 2010 12 A Barenghi G M Bertoni L Breveglieri M Pellicioli G Pelosi Fault attack on AES with single bit induced faults Proc of Sixth International Conference on Information Assurance and Security IAS pp 167 172 2010 13 K J Kulikowski Wang Zhen M G Karpovsky Comparative Analysis of Robust Fault Attack Resistant Architectures for Public and Private Cryptosystems Proc of Sth Workshop on Fault Diagnosis and Tolerance in Cryptography pp 41 50 2008 Int l Conf Embedded Systems and Applications ESA 12 Design and Analysis of Academic Dual Chamber Pacemakers Mitchell L Neilsen Dept of Computing and Information Sciences Kansas State University Manhattan KS USA Abstract In this paper we describe a relatively inexpensive framework for the design of an academic dual chamber pacemaker that can be used
53. PDD EXT 450 m PDD INT Power Consumption mW Figure 5 Software processor energy consumption The internal module is basically composed by the core and the external module consists of an external bus unit interface and one DMA controller In this case due to the internal frequency of the processor which increases from 100 MHz to 600 MHz the curve regarding this unit is higher than the external unit controlled by SCLK which is configured as shown by Table I The higher consumption for the software processor was about 450 mW when the core is running at 600 MHz and the SCLK at 120 MHz It means when the device is configured with the ratio 5 1 In average the total needed by the internal module is more than 250 mW and by the external module is around 100 mW resulting in the consumption of 350 mW After evaluated the consumption for this PE based on software Figure 6 shows the estimated energy needed to run the both processor elements It is well know that reconfigurable hardware should spent a large amount of energy Thus in order to mitigate these issues this evaluation is considering a FPGA Igloo AGL125 21 running at 100 MHz due to it is a low cost and low power device able to compute parallel codes Since the average consumption is around 580 mW the power spent by the both processors is really small when compared with the performance achieved Average 700 600 500 40 30 20 10 0 1 1 2 1 3 1 4 1 5 1
54. Recently a great amount of development has happened in the field of agriculture by using information technology over the world Most important part has developed by German European and some of American researchers Now in Asia Korea has been started developing their own agricultural field by using recent information technology and for this purpose our research team initially doing some important research work on this sector like developed application program for agricultural tractor electronic control units ECUs and virtual terminal etc All application procedures are followed by ISO 11783 and some other standards For the development of our application program for agricultural tractor GPS sensor we use an open source library with object oriented way In our research result we found that our GPS sensor can receive CAN messages frequently with expected time So it works perfectly without any fault In our future work we are going to compose application program for every ECU of an agricultural tractor ECU Data Source ECU Display ECU GPS Sensor ECU Tractor Bridge etc and developed the virtual terminal Int l Conf Embedded Systems and Applications ESA 12 7 Acknowledgment This work was supported in part by Brain Korea 21 and the Center for IT Convergence Agricultural Machinery ITAM grant NO RO9 6 funded by the Ministry of Knowledge Economy Republic of Korea References 1 ISO11783 6 Tractors and machinery for a
55. Software Proc of the Korea Computer Congress 2011 Vol 38 No 1 A pp 202 205 2011 140 Int l Conf Embedded Systems and Applications ESA 12 Int l Conf Embedded Systems and Applications ESA 12 141 SESSION EMBEDDED SYSTEMS AND NOVEL APPLICATIONS AND ALGORITHMS Chair s Prof Hamid Arabnia 142 Int l Conf Embedded Systems and Applications ESA 12 Int l Conf Embedded Systems and Applications ESA 12 143 PIC 32 MICROCONTROLLER BASED sEMG ACQUISITION SYSTEM AND PROCESSING USING WAVELET TRANSFORMS Chandrasekhar Potluri Member IEEE Madhavi Anugolu Member IEEE Alex Jensen Girish Sriram Shiwei Liu Steve Chiu Member IEEE Alex Urfer Abstract In this paper an embedded system platform is used for signal acquisition and processing On a healthy male subject the motor unit of the ring finger is marked The surface Electromyographic sEMG signals and their corresponding skeletal muscle force signals are acquired using a PIC 32 microcontroller at a sampling rate of 2000 samples per second The filtration is achieved by using a Wavelet transform Daubechies 44 filter at 5 levels of decomposition for sEMG and a Chebyshev Type II filter for Skeletal muscle force signals The data is acquired through the Universal Asynchronous Receiver Transmitter UART model of the PIC 33MX360F512L embedded test bed and is compared to data acquiredwith standard sEMG Delsys Bagnoli 16 acquisition System Keywords
56. Systems SRDS pages 152 161 2001 Ali Sharif Ahmadian Mahdieh Hosseingholi and Alireza Ejlali A Control Theoretic Energy Management for Fault Tolerant Hard Real Time Systems Real Time Systems Symposium RTSS 2011 S Ghosh R Melhem and D Mosse Fault Tolerant Scheduling on a Hard Real Time Multiprocessor System in Proc 8th Int Symp Parallel Processing pp 775 782 1994 Y Zhang and K Chakrabarty Dynamic Adaptation for Fault Tolerance and Power Management in Embedded Real Time Systems ACM Trans Embedded Computing Systems vol 3 no 2 pp 336 360 2004 99 100 Int l Conf Embedded Systems and Applications ESA 12 Design of biomedical signal acquisition equipment with real time constraints using Android platform J Yepes J Aguirre S Villa ARTICA University of Antioquia Medellin Antioquia Colombia Electronics Department University of Antioquia Medellin Antioquia Colombia Abstract Android is an open source platform which includes operating system core application program interfaces APIs and middleware originally designed for mobile devices This platform has become quite popular extending its use to several electronic devices However communications with other digital devices such as Microcontrollers FPGA s Microprocessors data acquisition systems and ASICs have been a bottleneck in the application development process The main reason for this issue is that Andro
57. T is activated lower priority threads stop until it terminates typedefstruct_inf int app_num void init void void start void void shutdown void static void touch callback _distributor int x int y f i if app_num 1 A1 callback x y else if app_num 2 A2 callback x y else if app_num 3 A3 callback x y else if app_num 4 void callback int x int y INF A4 callback x y else if app_num 5 A5 callback x y a b Fig 7 The C data structure of a the standard interface and b the callback distributor Table 3 The interface description in sub applications and a connecting program _ Component _____ Description Empty Draw the menu window and Ai start icons app_num callback app_num A E ER Activate thread 3 and call the start of Ay Create 5 alarms and 9 threads As Initialize OS os_init eInitialize all sub applications X and call the start of A eStart OS os_start Distribute an OS callback to the sub application identified by app num Int l Conf Embedded Systems and Applications ESA 12 A l init init gt 5 start shutdown a Ay e e e e e e Ld t e e e e e e tivat 4 e gt tivat re wait activate terminate d init i hd gt create shutdown f t activate e e a activate c activate tegninat
58. T T T T T T T T T l 12346678 830 1 2 3 4 5 6 7 8 9 1 14 12 cfg cfg Fig 2 g Area analysis Fig 2 h MIPS per area analysis Figure2 Analysis of 12 cache configurations related to the core 88 4 6 Area analysis Area remains one of the key design constraints to keep the cost of designs under control because die costs are proportional to the second power of the area At very small feature sizes little margin exists between design rules and manufacturing process variations leading to an average 5 decrease in expected die yield with each successive technology node for mature IC designs 23 Therefore on chip resources including cores caches and interconnects must be carefully designed to achieve good trade offs between performance and cost Also as mentioned before area is one of the most important parameter for embedded applications By changing the configuration of cache hierarchy area cost of embedded cores will change Result of fig 2 g shows the effect of changing of this parameter Like power analysis results the best point for all feature sizes is configuration 1 But there is more important result from this table Based on analysis results in 90nm up to 76 of core area will be occupied in the cache hierarchy Another important factor in embedded system design is MIPS per area parameter This parameter shows the area efficiency of different configuration considering a limited area budget for multi core embedded
59. Telegram mapping and transmission tasks are SC tasks Both master and Slave processors build their own telegram and then validates it before transmission using I2C communication network Similarly task that decodes information on MCU is also a SC task FCSA modelled is constructed in Matlab Simulink Based on this Simulink model a C code is generated with is then integrated with the system code implemented on industrial standards MISRA C EN954 1 and EN13849 performance level d in Hardware Embedded Workshop HEW Transient faults are injected in the system by using test scripts at software level Steady state response of the system is investigated through Matlab and actual CPU execution time is monitored by using a software time 10 Experiments The purpose of first experiment is to test the robustness variation of tasks execution in the presence of faults of the system with and without FT integration to investigate the FT integration tradeoffs One microcontroller is configured as the Master controller and the Second micro controller served as the slave controller For this experiment two Telegram mapping tasks are considered as the SC tasks Both controllers map their own telegram independently and compare at different sampling intervals using I2C bus network to validate the correctness of the telegram There are two SC tasks that perform the mapping For this experiment two sampling intervals for each tasks is allocated and a software
60. analyze periodic tasks on a multiprocessor architecture It is able to support a fixed priority scheduling policy such as RM Rate Monotonic 19 thanks to the use of the inhibitor arcs The contribution of its proposal lies in the calculation of a reduced state space compared to that evoked by 3 Such proposal has been improved by 18 and 17 to support the tasks with variable time execution Before the crossing of transitions the STPN 24 adds con straints to check the respect for the firing interval Therefore the check of these constraints is a new dimension added to the problem of scheduling analysis The PrTPNs Priority Time Petri Nets 4 also utilized the inhibitor arcs to present the notion of fixed priority The authors propose a method of temporal analysis of the net work Indeed from a sequence of non temporal transitions his method was to recover the possible durations between the firing of transitions in order The durations are the solutions of a linear programming problem Both of PrTPN and STPN present the priority through the inhibitors arcs added as new components to those of Int l Conf Embedded Systems and Applications ESA 12 PNs The RTS modeling with Petri nets gives rise to the models that are often complex Moreover the addition of an inhibitor arc makes the model more complex and therefore the extraction of properties more difficult A new extension PTPN Priority Time Petri Nets was proposed in
61. and L2 64KB will Int l Conf Embedded Systems and Applications ESA 12 deliver highest MIPS between all 12 cache configuration for selected embedded applications Interesting point is that configuration 5 also deliver minimum power product delay PDP that is one of the most important parameter in designing modern processors Area analysis shows that up to 76 of core area will be occupied in the cache hierarchy in 90nm MIPS per power analysis like power analysis encourages the designer to use smaller cache sizes In the future we will do these explorations for future feature sizes considering more detailed parameters like thermal and hot spots and put all together to show the best cache size for embedded applications considering more than 8 parameters simultaneously 6 References 1 Daniel D Gajski Samar Abdi Andreas Gerstlauer and Gunar Schirner Embedded system design modeling synthesis and verification springer 2009 2 Embedded processors top 10 billion units in 2008 available online at http www vdcresearch com _documents pressrelease press attachment 1503 pdf 3 Jong Wook Kwak Ju Hee Choi Selective access to filter cache for low power embedded systems 43rd Hawaii International Conference on System Sciences HICSS pp 1 8 2010 4 P Ranganathan S Adve and N P Jouppi Reconfigurable caches and their Application to Media Processing Proceedings of the 27th International Symposium
62. and practices of embedded system design using digital logic technology in DS I and microcontrollers in MS I The courses also have laboratory components that use software and hardware kits that aid in the understanding of the basic concepts offered in each of the courses The labs allow the students to design implement and debug simple to intermediate scale embedded systems based on digital logic or microcontrollers The DS II course focuses on computer aided design simulation synthesis and implementation techniques for systems targeted on programmable logic devices such as FPGAs Hardware description languages are extensively used in the course for building systems with a wide range of complexities This course prepares the students for a course on computer architecture as well as for a career in embedded systems for real world applications with strict requirements in speed power consumption and physical size The MS II course focuses on contemporary 16 and 32 bit general purpose microcontroller architectures We use Microchip PIC24 and PIC32 MCUs in this course although the concepts taught also apply to most general purpose MCUs with little modifications In addition to the lecture materials on the essential MCU internal details and various built in peripheral interface modules we offer several practical laboratory activities that help enhance the understanding of the concepts and demonstrate real world applications The lab exerci
63. and send it to Virtual terminal through CAN bus Developing the electronic control systems a lot of ECUs interconnected inside agriculture tractor 2 Such as ECU Data Source ECU Display ECU GPS Sensor ECU Tractor Bridge etc All ECUs connected with CAN bus Controller Area Network or CAN bus is an ISO standard computer network protocol and bus standard designed for microcontrollers and devices to communicate with each other without a host computer and exchanging data between control units take place on a uniform platform This platform is called a protocol The CAN bus acts as a so called data highway This research illustrates the design of an application program for agricultural tractor GPS sensor It also gives some idea about tractor software design The principle idea of this application is developing software for tractor ECUs On the other hand open source library provides the main resources for this research work with following some standards Using C C programming methods for the application program and the software environment is embedded workbench In our application design we chose our test board is STM32F107 ARM _ 32 bit Cortex M3 board for ECU hardware of GPS sensor 3 We also use RealSYS CANPro USB device for analyzing CAN messages received by GPS sensor and AMTEL mini JLINK is an optimizing C C compiler for ARM Cortex M3 microcontroller We select the embedded workbench IAR Embedded Workbench and the open
64. ant 4 E N 5 re EF 1 3 l fis 12 GA Wire sZ L J _ s L q L LM7805 TO92 11m outH 4 siia GNO A lai L j 4 IK 02 s 2 C12 lt Ris e VT ING 1000F _ D D A Figure 3 Voltage Current Sense and Power Supply Circuit The two regulated DC voltages are used to power the PIC microcontroller the CS5460A energy metering IC and an XBee RF module The Cirrus Logic CS5460A is an integrated circuit designed to measure and calculate energy instantaneous power and RMS voltage current values for single phase applications 12 These measurements are obtained from the voltage and current sensing transformers The Vins Vm and Im signals shown in Figure 3 are conditioned before being input to the associated input terminals of the CS5460A The resistor capacitor networks used to condition these inputs are shown in Figure 6 Data is written to and read from the CS5460A via an on chip serial peripheral interface SPI Through the use of Microchip Technology s PIC16F882 microcontroller 13 14 data is read from the CS5460A interpreted and formatted The PIC16F882 is also interfaced with an XBee RF module via the PICI6F882 universal synchronous asynchronous receiver transmitter module The XBee RF module 15 allows data to be transmitted and received by the system thus allowing the ability to monitor and control devices a
65. application of Global Positioning System GPS for agricultural tractor Electronic Control Unit ECU is Global Positioning System GPS sensor using IAR IAR Embedded Workbench and an open source library which follows the most important characteristics of International Organization for Standardization ISO 11783 communication protocol in the serial communication network of agricultural vehicles These applications are written in C C programming methods We explain some test connection configuration between working Personal Computer PC and test board for studying the application program and GPS sensor working status This research work mainly describes the system architecture and programming methodology of an application program which follows some standards for agricultural machinery Keywords Electronic control unit isobus controller area network open source library embedded workbench 1 Introduction Since the past few years manufacturers of agricultural machineries have increasingly turned to electronics to provide products with enhanced functionality productivity and performance to clients Electronic content in agricultural equipment has increased A natural outcome of adding electronic components to agricultural equipment has been realization of the advantages of allowing the components to communicate A GPS sensor on a tractor for example may communicate with a virtual terminal 1 receiving the CAN message continuously
66. are merged there is only one main function which calls all init functions of each sub applications Then the whole large application is tested and run This process is known as the bottom up integration testing 2 and shown in Fig 4 The advantage of this approach is to reduce development time and cost by using the common interface of each sub application A e sen st shutdown callback touch callback touch aa Testing A Testing A Testing A A A Fig 4 Testing procedure in application development 5 Implementation and case study To validate our model we used it for writing a menu driven GUI application The menu driven GUI application shows the GUI front page that contains the icons to be selected and executes the corresponding sub application Though it is a simple form it is popularly used for developing GUI applications It is tested on a Cortex A8 32 bit microprocessor board as shown in Fig 5 which is a mobile device with a battery 2GBytes of flash memory 512Mbytes of SRAM 2 4GHz WiFi chip and 800x480 TFT 24 bit LCD display Fig 6 An embedded board for experiment 61 Fig 5 An experimented model of our large application Our model of the menu driven GUI application is shown in Fig 6 Our application is divided into five sub applications Table 2 Each sub application is written in C and use external variables to call the start and terminate functions in t
67. are necessary for the project Int l Conf Embedded Systems and Applications ESA 12 e Xilinx Virtex 5 XCSVLX110T e 10 100 1000 tri speed Ethernet e USB host peripheral controller Cypress CY 7C67300 4 FPGA Data Connectivity There are two ways to connect the FPGA to the SIS network Ethernet can be connected to a LAN for ease of use in terms of functionality sharing among clients or by using the USB 2 0 protocol which requires a client PC to connect to the SIS network The USB 2 0 protocol supports three speed ratings 6 1 low speed USB 1 0 rate of 1 5 Mbit s 183 kB s 2 full speed USB 1 1 rate of 12 Mbit s 1 43 MB s 3 high speed USB 2 0 rate of 480 Mbit s 57 MB s The USB 2 0 protocol will initially be used for multimedia streaming purposes particularly using one of the specific USB transfer protocols In the USB 2 0 protocol there are four types of data transfer modes but only one will be mainly used e Bulk Transfer Mode This transfer mode is used by mass storage devices for any amount of non time sensitive data transfer This transfer mode guarantees data delivery only 5 Project Developments When implementing a MJPEG codec it is necessary to visualize its process as a series of sequential JPEG images being rendered at high speed An open source JPEG Encoder 7 written in Verilog will be used since its internal processing does not rely on any proprietary code or license This particular encod
68. as Controller This vending machine looks like a patient salesperson who is helping customers out of a satisfying shopping process regardless of shopping experience they have ever had 2 System Features A humanized vending machine built on this framework will have two significant features 1 No Constraint on operation process Customers will be allowed to operate a vending machine with random operation instead of following a fixed process As customers initiate shopping process they also initiate an interactive process between salesperson and customers so will he be directed to fulfill shopping process 2 No limitation on purchase Under the circumstance that customers can afford more items they will be directed to purchase consecutively without initiating a new shopping process Under the circumstance that money is not enough to pay the item they want to buy salesperson can still assist customers to reach their goal by Int l Conf Embedded Systems and Applications ESA 12 reminding customers to input more money as long as customer don t quit actively 3 System Design This framework is a general purposed framework which can be implemented into a vending machine on the platform having uC OS II implanted and supporting I O interrupt 3 1 Information storage Humanized services from a vending machine partially lie in effective storage of money information and item information To sell whatever customers wa
69. cannot cover all the possible states of the system dPTPN starts from an initial state to succeed in determining the error source if it occurs e Pertaining to the other extensions presented in Section 2 dPTPN offers a strategy that accelerates the marking and avoids the combinatorial explosion in front of a large number of states This strategy is based on partial order theory and simultaneous crossing of a set of 119 120 enabled transitions 13 5 1 Model execution To show how dPTPNS can be used to specify and analyze the robot footballer application we consider the following table Tab 1 to present the specification of the system Q The generation of the different partitions is made through Table 1 The specification of each partition T10 al Qo NYAS eA A DA D NI N a Lj ol o o o ol ol Gy ol ol ol ol o oj T13 a specific partitioning tool such as RTDT 27 and for each partition the dPTPNS is used for analysis For modeling the instances of TaskC we just indicate the input and output places for each instance in the editor dPTPNS To model the system Q we create 13 instances of TaskC The initial marking corresponds to initialize P Increated T tol with one mark and 7 Ci 7 RemainingPeriod with the corresponding C and P marks from Tab 1 respectively The dPTPNS is accompanied with a simulator that imple ments the semantics of the dPTPN formalism After
70. computer hardware the atomic frequency standard AFS clock the transmitters the battery and the solar panels During the course of this research it was also found that NASA had discovered that there is an ionosphere in the moon s atmosphere 10 This discovery dates back as far as the Apollo missions but had never been qualified until recently by T J Stubbs of NASA 10 11 It is postulated that the explanation for the lunar ionosphere is from ionized dust particles in the lunar atmosphere 10 11 This is impor tant since this ionosphere can have adverse affects on signals sent from orbiting space vehicles down to the lunar surface producing errors in PVT determination 1 Assuming the ionosphere is the result of ionized dust particles it should increase as human exploration expands Quite possibly the largest hurdle that needed to be over came was determining a suitable AFS that would fit within a CubeSat All GPS satellites use an AFS to ensure a reliable clock frequency to reference However these are usually large heavy and expensive Recently there has been much advancement with this technology and now there has been developed chip scale atomic clocks CSAC which are about 10 mm in volume and consume only 30 mW 4 making it suitable for an embedded design In addition this CSAC has a Allan Deviation less than 1x10 4 Referencing the Galileo GPS specification and the Allan Deviation the clock validity time
71. creating the Q model with dPTPN editor the simulation is started At instant t Oms T1 T2 and T3 are enabled and T1 T3 have the highest priority on P1 and P4 respectively After the execution of 7 l at t 8ms 7 4 receives all the necessary data to be activated At this moment the deadline of T4 is earlier than T2 so T4 takes the processor P1 The dPTPNS simulator indicates at t 30 the activation of a new instance of 7 2 when the previous one does not achieve its execution on the P1 processor As a consequence the simulator shows the crossing of the T4deadline transition and puts a mark in the output place P4Deadline of the TaskC4 As presented in a the model construction with dPTPN section the marking of P4Deadline is a stop Marking Thus the simulation is stopped and the dPTPNS indicates that 71 T2 T4 and T6 are non schedulable on the processor P1 This description presents not only the scheduling analysis results but also a useful feedback to the portioning tools to eliminate this task combination during the next generation Int l Conf Embedded Systems and Applications ESA 12 6 Conclusion The development of dynamic Priority Time Petri Nets dPTPN 13 models for the scheduling analysis of a multi processor system has given very important results 13 14 In fact it presents on the one hand a detailed specification of Real Time System behavior On the other hand it is able to indicate the exact descrip
72. dPTPN Model Building on Object modeling we propose a new dPTPN component and identify how it can be instanced to specify the scheduling analysis model The present paper is organized as follows Firstly we start with presenting the experimentation robot footballer in sec tion 2 Next the definitions of the dPTPN and its semantics are detailed in section 3 Next section 4 shows the Object modeling approach and the creation of a new component In this section the modeling of the experiment is shown with different instances of the new component In section 5 we present the dPTPN Scheduling analysis tool dPTPNS Finally the proposed approach is briefly outlined and future perspectives are given 2 Robot footballer experimentation The experiment presents a football player robot appli cation 22 in which the video tasks for object detection wireless communications for message exchanging with other devices motors controls sensor acquisition image process ing and decision computation are included The studied system is composed of four major parts e Acquiring and processing image It is handled through tasks T2 T5 T7 T8 and T9 e Communication HF The information exchanges be tween the robot the players and coaches are made by the following tasks T1 T4 e T6 and T12 Knowing that while T12 is used to send data T1 T4 and T6 are used for reception e Data fusion by task T10 and path computation through T11 e Cont
73. designs Fig 2 h shows the exploration of MIPS per area for all 12 mentioned cache hierarchy Based on this table maximum MIPS per area will be created in configuration 1 but based on performance analysis section this configuration has 7 8 performance penalties for all selected embedded applications as mentioned before 5 Conclusions In this paper we used a cache energy model considering both dynamic and static energy By using these design space exploration and energy model we introduced 2 points for cache sizes of embedded applications called HCP and LCE that are the best point considering performance and energy respectively Considering these 2 points we introduced optimum ranges for cache size and made a reduction of search space from 36 to 12 configurations of L1 and L2 cache sizes by using very simple but efficacious algorithm After that we did a multi objective exploration for 12 extracted cache configurations considering most important parameters in designing future processors such as leakage and dynamic power MIPS power product delays and area cost related to an embedded core that has not considered in previous researches Results show that in average in 90nm up to 17 of whole static power of an embedded core consumed in cache hierarchy Also in average in 90nm up to 40 dynamic power and up to 32 of total power of an embedded core consumed in cache hierarchy Based on MIPS exploration cache hierarchy that apply L1 32KB
74. down derives IDs using Gparted Open Gparted with administrator right go on System at the top menu bar Move down to Administration and click on Gparted Enter Administrator password if required Menu bar gt System gt Administration gt Gparted On Gparted graphical windows click on top menu and move your cursor to Devices Select the NAS drives one by one and look for the largest partition on each drive GParted gt Device gt Note the largest drive name i e dev sdc3 of each device hard disk drive on which you want to perform recovery Now open command prompt For this go in Application menu from top menu bar of Ubuntu in Accessories click on the Terminal Application menu gt Accessories gt Terminal 1 2 3 4 5 6 Int l Conf Embedded Systems and Applications ESA 12 7 Recovery commands need to be run as root To get root access run below command on terminal and enter admin password if required gt sudo su If command prompt change to its show you got root access Start NAS recovery with testing of the NAS drive Here we are using the drive IDs as we note in previous section Type following command replacing dev sdc3 with actual partition showed in your devices gt mdadm examine dev sdc3 gt mdadm examine dev sdd3 gt mdadm examine dev sde3 8 It retrieves information from superblocks as RAID Level stripe size
75. during overload it can guarantee the deadlines of critical tasks even though it is impossible to meet all task deadlines The qual ity of a scheduling algorithm for real time systems is judged by how well the algorithm meets these objec Int l Conf Embedded Systems and Applications ESA 12 tives This article develops advanced hybrid approach to schedule aperiodic tasks For soft deadline aperi odic tasks the goal is to provide fast average response times For hard deadlines aperiodic tasks sporadic tasks the goal is to guarantee that their deadlines will always be met The new hybrid approach pre sented here meet both of these goals and are still able to guarantee the deadlines of hard deadline periodic tasks Each periodic task 7 is characterized according to 2 by an initial offset S a release time a worst case execution time C a relative deadline D and a period T Each aperiodic task 7 is characterized by a worst case execution time C and a relative deadline D A task is synchronous if its release time is equal to 0 Otherwise it s asynchronous We assume in this work that all the tasks are independent periodic and aperiodic A tool named RT Reconfiguration is devel oped in our research laboratory at INSAT university to support this new proposed approach The organi zation of this original paper is as follows The next section formalizes some known concepts in the real time scheduling theory sec
76. each frame of interest The distance between the joints being analyzed and the angles between them are used to check each frame against the danger situation If successive frames meet the condition for danger situation then an alarm is generated by posting a danger message If the subject shows the danger gesture by accident Int l Conf Embedded Systems and Applications ESA 12 store Skeletal Retrieve body Frame joints Check for completeness of data Calculate co ordinates of required joints Calculate angles and distances b w joints Duration gt Figure 3 Process flow in the Predictable Matching Algorithm module the system will not mistake it as a danger situation since the gesture has to be performed for a predefined duration It is highly unlikely to have this situation emulated by mistake 3 Evaluation of the MR BEAS The Kinect device was connected to a PC The program was running in the NET environment for capturing and analyzing the image of the subject For simulation purposes the subject was allowed to stand at a distance of 6 feet from the Kinect sensor bar This would simulate a person lying on a bed and the sensor mounted on the ceiling The first scenario involves monitoring a person in a well lit room 800 lumens the second is a poorly lit room 10 lumens and the third is a dark room 0 lumens The simulation windows for each case are shown in Figures 4a 4b and 4c respectively
77. for the timed analysis of scheduling extended time petri nets In RTSS 04 Proceedings of the 25th IEEE International Real Time Systems Symposium pages 187 196 Washington DC USA 2004 IEEE Computer Society C L Liu and James W Layland Scheduling algorithms for mul tiprogramming in a hard real time environment J ACM 20 46 61 January 1973 L Sha T Abdelzaher K E arz n A Cervin T Baker A Burns G Buttazzo M Caccamo J Lehoczky and K A Mok Real time scheduling theory A historical perspective Real Time Systems 28 101 155 2004 10 1023 B TIME 00000453 15 61234 le A Mahfoudhi Y Hadj Kacem W Karamti and M Abid Compo sitional specification of real time embedded systems by priority time petri nets The Journal of Supercomputing pages 1 26 2011 doi 10 1007 s11227 011 0557 9 H Kitano M Veloso E Pagello Robocup 99 Robot soccer world cup ii In Velsoso Eds C A Petri Fundamentals of a theory of asynchronous information flow In IFIP Congress pages 386 390 1962 O H Roux and A M D planche A t time Petri net extension for real time task scheduling modeling European Journal of Automation JESA 36 7 973 987 2002 Douglas C Schmidt Model driven engineering JEEE Computer 39 2 February 2006 F Singhoff J Legrand L T Nana and L Marc Cheddar a flexible real time scheduling framework ACM Ada Letters journal 24 4 1 8 ACM Press ISSN 1094 3641 November 2004 H T
78. for the support in the development of this work SIMMIT is being funded by COLCIENCIAS the ICT Ministry of Colombia and ARTICA Research Center of Excellence in ICT in the project Design methodology of embedded systems with high reliability and performance focused on critical applications 9 References 1 Android com Available http www android com 2 R Kamal Embedded Systems Architecture Programming and Design McGraw Hill First Edition 2003 3 Android SDK Android Developers http developer android com sdk index html 4 J Yepes L Cobaleda J Villa J Aedo Design a medical application for Android platform using model driven development approach Published in the 9th International Conference on Modeling Simulation and Visualization Methods Las Vegas USA 2012 5 C Maia L Nogueira and L M Pinho Evaluating Android OS for Embedded Real Time Systems Published in Proceedings of the 6th International Workshop on Operating Systems Platforms for Embedded Real Time Applications Brussels Belgium July 2010 pp 63 70 6 Dalvik Virtual Machine http www dalvikvm com Available insights Available 7 Sangchul Lee Jae Wook Jeon Evaluating performance of Android platform using native C for embedded Int l Conf Embedded Systems and Applications ESA 12 8 9 systems Control Automation and Systems ICCAS 2010 International Conference on vol
79. hardware prototype shown as the green board on the right in Figure 1 is used in our framework as well However the focus of this paper is on the software framework used for pacing device control and management A pacemaker is a medical device that delivers electrical pulses to the heart muscles to regulate the beating of the heart The goal is to maintain a sufficient heart rate to compensate for irregularity or blockage in the patient s heart s electrical conduction system Current pacemakers can be programmed by a cardiologist to select optimal pacing modes for individual patients In some cases a cardiologist may use a complex combination of pacemaker and defibrillator in a single implantable device and or multiple electrodes placed on different positions in contact with the heart For this framework only a simple pacemaker with up to two electrodes one for the ventricle and one for the atrium are considered For permanent pacing the electrodes are placed in a chamber or several chambers of the heart To simulate the heart we use software to control a relatively low cost 150 for academic use 12 Bit 10 kS s multi function Data AcQuisition DAQ system from National Instruments the USB 6008 as shown below in Figure 1 The MicroChip PICkit 2 or PICkit 3 can be used to program and debug the PICI8F4520 chip on the pacemaker board Both devices can be connected via any available USB ports on any computer It is very convenient to
80. have the programmer debugger data acquisition and signal generation software all conveniently located on a single development system they are currently all running on a low end laptop running Windows 7 Figure 1 Basic hardware configuration 15 16 There are basically three different types of permanent pacemakers based on the number of chambers involved and their basic operation 2 In a single chamber pacemaker only one pacing lead is placed into a chamber of the heart either atrium or ventricle As shown above in Figure 1 only the ventricle is being paced and sensed in this example setup However the system shown above allows both chambers to be paced and sensed With a dual chamber pacemaker electrodes are placed in both heart chambers This type of pacemaker more closely resembles what happens with the natural pacing of the heart Finally a rate responsive pacemaker has sensors that detect changes in the patient s physical activity and automatically adjust the pacing rate to fulfill the body s metabolic needs On board the pacemaker shown in Figure is an accelerometer that is used to monitor activity and enable the development of software that is rate responsive In a real patient the pacemaker generator is hermitically sealed with a power source usually a lithium battery a sensing amplifier which processes the electrical impulses of the patient s naturally occurring heartbeats as sensed by the heart electrod
81. input PI_1 and eventually PO_1 is accorded the highest priority among the input bits of the 8 bit priority encoder block The order of priority descends sequentially from PI_1 to PI_8 likewise for outputs PO_1 to PO_8 Nevertheless it is to be noted that priority assignment for primary inputs outputs is ideally user defined During the precharge phase CLK signal is active low hence transistors pcl to pc8 turn ON and the primary outputs PO_1 to PO_8 are driven to logic low state We now describe two scenarios during the evaluate phase when CLK undergoes a rising transition and eventually becomes active high with input signal LS also assuming logic high state These two scenarios are representative of typical circuit operation Int l Conf Embedded Systems and Applications ESA 12 e PI I is high In this case transistor evl is turned ON and PO_1 is driven to logic high this occurs irrespective of the data values of other primary inputs Minimum data path latency occurs for this scenario as bits PI_1 and PO_1 assume the highest priority e PI 8is high and PI_1 to PI_7 are low In this case nMOS transistors ev2 ev4 ev6 ev8 ev10 ev12 evl4 and ev15 are turned ON leading to logic high state for PO_8 Complementarily nMOS transistors evl ev3 ev5 ev7 ev9 ev11 and ev13 remain OFF Maximum data path delay is encountered for this scenario as PI_8 and PO_8 are associated with the lowest prior
82. into the request handling process without putting a bookmark in the garbage collection sequence because the block addresses already exist in the Candidate list In the same way background garbage collection can be implemented atomically The 2LGC has only to add the block address to the Garbage block list when finishing background single block garbage collection 5 Experiments 5 1 Performance Evaluation In order to verify the effectiveness of 2LGC scheme we conducted real system based experiments using a flash proto type platform board 16 equipped with an INDILINX bare foot SSD controller The SSD controller of the platform board consists of hardware parts 1 e NAND flash controllers 20 memory controllers and a CPU and software parts e FTL so an algorithmic evaluation can be performed by rede signing the firmware inside the SSD controller Moreover the most accurate and reliable experiments can be conducted through this platform because the platform board is connected 26 by a SATA2 interface using a notebook or desktop as storage 21 The platform board and the specification of INDILINX barefoot SSD controller are shown in Figure 5 and Table 1 respectively LER TE LES IE LES LES i LES wee f p a z J g 3 TERT HEHE HAH HA HH F Me Fig 5 Flash prototype platform board Table 1 SSD controller specification of platform board Component Specification Core processor ARM7TDMI S 87 5MHz Host inter
83. it into practice hardware interface should be implemented according to different platform which has been implanted uC OS 1 and support VO interrupt A vending machine model with basic functionalities based on this framework has been implemented based on platform with LPC24 W 78 as Controller Keywords Humanized Vending Machine uC OS II 1 Introduction In developed countries such as America and Japan different diversities of vending machine are in extensive use in busy areas like the metro stations supermarkets shopping malls and public facilities On one hand tremendous revenue was gained On the other hand people s living is becoming more and more convenient Meanwhile beneath those superficial influences people s living mode is changing unwittingly with the advent of vending machine Under the circumstance that the same item is supplied instead of going towards a salesperson people prefer to go towards a vending machine It is consumption psychology living mode and confidence in merchandise that decide 1 But in China people use vending machine less frequently One of the reasons is that vending machine 1s still not popularized as extensively as in developed countries The commercial chance underlying vending machine is promising enough to dig Along with accelerating human life rhythm changing life mode improving product quality vending machine will play a more and more important role in shopping process When
84. it is the third situation that holds the system will recover the previous status by posting the item message back to the front of the item queue then wait until the customers input more money or quit actively 4 System Testing Base on this framework an embedded system which simulated the key functions of a vending machine was developed on the platform with LPC2470 2478 as controller 3 4 The key resource was made full use of to simulate inputting money selecting item and delivering change Furthermore a black box test was executed The testing cases were categorized into 3 types single operation consecutive operation and compound operation Each type was categorized further according to different situation Because the test was related to hardware resource in order to guarantee all the hardware resource function correctly the number of testing cases was more than doubled than ordinary software engineering project with similar logic The testing result show the control system can correctly direct customers Int l Conf Embedded Systems and Applications ESA 12 fulfill their circumstance shopping process under any complicated 5 Conclusion Though hardware resource of an embedded system 1s limited with the help of the embedded operating system the function of an embedded system is becoming more and more advanced This humanized vending machine design framework which is based on uCOS II endowed vending machine an
85. min T Di IfU lt 1 x Then display 8 save m1 else display i 1 Code2 Modify_Periods_Deadlines e Compute 4 Computel e For min T Di E Enew U Eola Display_parameters Code3 generate_parameters m1 6i yi e Compute R 1 e Compute R 2 e Compute R 3 e Generate R End Algorithm 6 EXPERIMENTAL ANALY SIS AND DISCUSSION In this section in order to check the suggested con figurations of tasks allowing the system s feasibility and the response time minimization we simulate the agent s behavior on a Blackberry Bold 9700 presented by 14 and on a Volvo system presented by 16 The Blackberry Bold 9700 is assumed to be initially com posed of 50 tasks and dynamically reconfigured at run time to add 30 new ones in which a task can be a missed call a received message or a skype call In this paper any real time reconfiguration and re sponse time minimization is based on the real time embedded control system reconfiguration Moreover in order to meet all real time constraints both initial WCETs Ci the relative deadline D and also peri ods T of each task are reconfigured by the intelligent agent RT Reconfiguration The goal is to minimize the response time of the whole system and to meet their relative deadlines The very important observa tion was obtained by the comparison of our proposed approach against the others from the literature about the current values We te
86. multiplier respectively The numbers Y and X can be expressed as n 1 n 1 Y 2P Vie X D 0 4 2 The resulting product is defined as follows P YXX Dizo Dito vix 2 4 78 Figure 1 illustrates unsigned 4x4 bits multiplication Y y3 y2 y yo XxX X X3 X2 X1 Xo Y3Xo0 Y2Xo Y Xo Yoxo Multiplicand Multiplier Y3X1 Y2X1 Y X YoX Partial products Y3X2 Y2X2 Y X2 Yox2 Y3X3 Y2X3 Y X3 Yox3 p7 pe p5 p4 p3 p2 p po Result Figure 1 Unsigned 4 x 4 bits multiplication Y3X0 Y2X0 Y1X0 YoxXo Y3X1 Y2X1 9 Y X 0 Yox1 0 ii n 7 P7 P Ps Pa P3 P Pi Po Figure 2 A conventional 4x4 array multiplier Figure 2 shows an implementation of conventional array multiplier known as the Braun multiplier 2 This multiplier combines three functions partial product generation partial product accumulation and final addition First partial product generation requires Nx N AND gates of two inputs Second partial product accumulation requires N 1 rows of carry save adders in which every row consists of N 1 full adders and the final addition that contains a N 1 bit ripple carry adder in the last row is for carry propagation Therefore a N x N bits array multiplier requires N x N 1 full adders Because conventional array multipliers have higher switching activity one way to reduce dynamic power is to avoid redundant switching transitions The following section describes two
87. names are used The common interface is important for final integration though some of them may be empty functions In a real implementation it may be represented as C data structure As an example if an interface data structure INF is defined as a set of the mentioned variable and functions a sub application Should declare INF app inf 1 init start shutdown callback where 1 is the sub application number and the rest is the function pointers used in the sub application 4 2 Modeling sub application The sub application is an application object that has the common interface Let the sub application be simply defined as A IX TX M where IX is the common interface set T is a set of threads used in the kt sub application and M is the mapping relationship between functions and threads or between threads The common interface set Ik appyum init start shutdown callback where aPPnum 1S a constant and init start shutdown are the corresponding interface functions The callback is a set of callback functions to be called In real sub application it has functions and variables much more than the mentioned interfacing functions A sub application may be thread driven or not If the sub application is not thread driven TX The M describes the calling relationship between elements in IX and TE An example of a sub application is depicted in Fig 2 The relationship between IX and TE is represented as crossbar
88. of the silicon oxide film which is located between the floating gate and the transistor gate in a cell The electron leakage problem mainly causes uncorrecta ble bit errors and therefore the lifespan of flash memory expires after performing a limited number of program erase P E cycles In order to hide these constraints of NAND flash memo ries current flash based storage systems use a special inter face called a flash translation layer FTL 2 5 which is supported by the storage firmware The main role of the FTL is to make flash storage a virtual in place updatable storage device For example the FTL redirects each write request to the physical flash area and marks the previously programmed page invalid when the host repetitively issues write opera tions on the same address space The flash storage can gener ate a relatively small number of page copy operations and block erase operations from this FTL emulation technique so it is helpful for improving NAND flash memory durability However a problem may arise when pages marked invalid remain in blocks and occupy flash space Therefore it is necessary to physically eliminate invalid pages and col lect valid pages from the victim blocks in order to sustain flash write performance and storage lifespan This sequence of operation processes is called garbage collection 6 7 The performance and durability of the flash storage can be kept stable if the garbage collection mechanis
89. old periodic tasks which are asynchronous and not affected by the reconfig uration scenario e g they implement the system before the time t and ne is a subset of ng new asynchronous tasks in the system To estimate the amount of work more priority than a certain under EDF we propose one function of job arrival with deadline one function of workload with deadline and finally we propose the function of major job arrival with deadline for periodic asynchronous tasks 3 1 New function of job arrival with deadline We propose new functions of job arrival which inte erate the deadlines by the following levels 150 e In the instance level Orale to d Crea H Sk n ti t2 Opp lt a Where Sk n t1 t2 d is the amount of job with lower deadline or equal to d brought by the instance Tk n meanwhile of time t1 t2 and Hja 1 if the predicat a true t1 lt Ak n lt to praza e In the task level we propose Si t1 ta d X ner Cen Ut lt a lt to lp lt a Where Sp t t2 d is the amount of job with lower deadline or equal to d brought by all the instances of Tk meanwhile of time fy t l e For a set of tasks we propose SCurrenis t Lis to d D o SA t Silti t2 d Where SCurrentr t t1 t2 d is the amount of job with lower deadline or equal to d brought by all the in stances of tasks that composed Currentp t mean while of time lti t l 3 2 New function of workload with deadline
90. power consumption and speedup performance applied on embedded multiprocessor architectures For a better exposition this work is organized into five sections Section II presents the architecture model that promotes synergy environment between different PEs and describes the methodology applied to evaluate the efficiency of the architecture Section III describes the case study Section IV presents the achieved results and finally Section V lists some considerations and main conclusions 2 System Architecture In order to simulate the cooperation between hardware and software for embedded systems a computing architecture based on the model discussed in 8 was investigated However there are other similar architectures that could be evaluated For instance it is possible to employ a embedded processors available on FPGAs to create a good scenario to split code between hardware and software Though generally they do not provide a high performance and have as bottlenecks the power consumption and the amount of area required due to these cores are based on configurable logic Concerning the amount of area spent to embedded these processors the benchmark provided by Altera 9 allow us conclude that the processor NIOS consumes more than 46 of area when optimized for speed and aimed to be embedded into a cheap FPGA like Cyclone Il EP3CSE144C8N The communication model used for the evaluated architecture consists of a shared memory b
91. presents T1UnCreated T1Remaining T1IncPeriod T1Elapsed Period T1Deadline T1deadline T1Releasing T1DataToSend Fig 4 RTS Task internal behavioral with dPTPN the completed dPTPN model of the internal behavior of the task T 0 4 2 Task It can be noted that this model is composed of 16 places 7 T Transitions and 3 Tep Transitions and for modeling the system Q those numbers are increased Thus the complexity of the modeling and its interpretation become more and more difficult We distinguish that for each task of 2 the model dPTPN is similar In fact just the initialization of the model with the firing times and the weights of arcs change The modification correspond to the chosen task for modeling We can consider the dPTPN model as an Object and each task T Task is an instance of this Object In the coming section we propose the definition of the Object Task Next we define the new model of Q using the instances of the proposed Object 4 Object modeling with dPTPN Using Petri Nets to specify the behavioral specification of objects is a major tendency to integrate between objects and PNs Indeed the networks are used to describe the internal behavior of objects Besides the internal state of objects is indicated by the marks in the network places Moreover the execution of the methods of an object is described with the transitions So the net structure specifies the availabili
92. proposed by the agent that reduces the response time To obtain these results the intelligent agent calcu lates the residual time R before and after each ad dition scenario and calculates the minimum of those proposed solutions in order to obtain Resp optimal noted Resp Where Resp is the minimum of the response time of the current system under study given by the following equation Resp min Respz 1 Respp 2 Respr 3 Respr s Respr s Respro To calculate these previous values Resp 1 Respk 2 kRespg 3 Respg 4 Respg s5 and Respk e we proposed a new theoretical concepts Ri Si Si fi and L for the case of real time sporadic operating system OS tasks Where R is the residual time of task o S de notes the first start time of task o s is the last start time of task o f denotes the estimated finishing time of task o and L denotes the laxity of task o A tool RT Reconfiguration is developed at INSAT in stitute in university of Carthago Tunisia to support all the services offered by the agent The minimization of the response time is evaluated after each reconfigu ration scenario to be offered by the agent The organization of the paper is as follows Section 2 introduces the related work of the proposed approach and gives the basic guarantee algorithm In Section 3 we present the new approach with deadline tolerance for optimal scheduling theory Section 4 presents the performance study showing how th
93. rate of the subtasks over network is also variable 8 System Analysis In order to ensure the stability of the system the network should be stable exponentionally and feedback control scheduling should keep CPU utilization within the required utilization bound This can only be ensured by keeping the sampling intervals and time delay St dt within upper bound The purpose of this section is to find the upper bounds Pimax and di on the sampling intervals and time delay for which all jobs over the network will remain stable So Sk 1 a Sk lt Pimax di dimax VkEN 6 The above equation shows that by characterizing admissible sampling intervals results in a deterministic delay impulsive system for which there are a few stability results 20 This analysis is based on the Discontinuous Lyapunov functional Other methods for verification and analysis can be found in 29 and 30 For the analysis of the system Int l Conf Embedded Systems and Applications ESA 12 represented in 4 and 5 Lyapunov functional of the below given form is used t W x Lx Dimax t s x s R x s ds t p1 f E Pimax SRT s x s Rox s ds Binax By wYX e w 7 Where L X R R are the approximately chosen positive definite matrices and w t x ti pO t st DOUS t t Het a su su Pimax t p t P2max t af P2 t Variables p and p serves as timers and their values reset tt times These variables
94. real time computing constraints While a general purpose computer is designed to be flexible and meet a wide range of end user requirements Embedded systems are used to control many devices in common use today 1 such that more than 10 billion embedded processor have been sold in 2008 and more than 10 75 billion in 2009 2 In embedded processors generally there are on chip caches and usually the major part of chip area is used by cache more than 50 3 and 80 of processors transistor budget is consumed in caches 4 On the other hand although cache is primarily used to overcome the performance gap between processor and main memory 5 6 however researches show that in processors the major part of energy is consumed in caches 6 14 Hence the methods which lead to optimum performance power ratio for embedded processors will be applicable Design space exploration is one of the most used approaches in this field 9 11 15 17 19 20 However the previous explorations didn t have any constraints on the cache size and some of them explored one level of cache or only considered data or instruction cache or didn t consider power consumption In this paper we introduce a model that considers a range of parameters that contribute in total energy consumption Author of 20 introduce an optimum cache size ranges for embedded applications Their results show the cache sizes in which the selected embedded applications reach the highe
95. result concerning the feasibility of re configuration with minimizing the response time of asynchronous periodic real time OS tasks in the litera ture and we focus in this paper to determine schedu lability under optimal scheduling algorithm So we note that the first and the only research work dealing with asynchronous periodic real time OS tasks is that we propose in the current original work in which we give solutions computed and presented by the intelli gent agent for users to respond to their requirements 3 CONTRIBUTION 1 NEW THEORETICAL PRELIMI NARIES This section aims to define a new theoretical pre liminaries for a set of asynchronous real time tasks scheduling under EDF based on the concepts defined n 7 8 which compute a feasible schedule for a set of synchronous real time tasks scheduling under EDF These new theoretical preliminaries will be used in the following two contributions Our main contribution is the optimal schedulability algorithm of uniprocessor periodic real time tasks implementing reconfigurable systems By applying a preemptive scheduling the as sumed system is characterized by periodic tasks such that each one is defined by a tuple Si Ci Di Ti Running Example Let us suppose a real time embedded system Volvo to be initially implemented by 5 characterized tasks These tasks are feasible because the processor utiliza 149 tion factor U 0 87 lt 1 These tasks should meet all req
96. sampling with high normalized frequency Ideal ADC wave of the alias 12MHz in blue solid dash ideal derivative cos of 12MHz wave in cyan actual derivative in red dash and fitting in red dot 2 2 Improved Derivative and Phase Detection The derivative error is a function of sampling frequency as shown in Fig 4 or more precisely of normalized frequency It is also related to the relative phase delay itself when used for phase time delay Phase Delay Detection Error of Two ADC Waves 45 l phase detection error degree 45l i 180 90 0 90 180 actual phase delay degree Fig 5 The phase detection error cos for quadrature identification in blue and the overall phase detection error in cyan Note that although the acos in blue can have as high as 30 degree absolute error at non critical 0 and 180 degree it can still identify the quadrature correctly since only the sign of cos is used Int l Conf Embedded Systems and Applications ESA 12 detection in this case both the sin and cos terms can be deduced using cross correlation of the two channel waves as shown in Fig 1 The derivative error around the critical boundary crossing points i e 90 degree can be reduced by using a proprietary algorithm as shown in Fig 5 As indicated in section 2 1 only the sign of cosine term is used to identify whether the phase is to the left or right of the qudrature plane
97. satellites in a lunar synchronous orbit where they would orbit the moon at the same rate it rotates 27 322 Earth Days or with an orbital period equal to half of the moon s rotation period similar to that of the Earth s GPS altitude 9 However this would have caused the satellites to have an orbital altitude of 8 7x10 km which is higher than the L1 Lagrangian point 6 3x10 km for the synchronous orbit which would have caused the satellites to be pulled in by the Earth s gravity As for the half moon period orbit with an altitude of 5 4x10 km the satellites would have been too close to the L1 point causing the orbits to become unstable Once the altitude was determined this was used to determine the minimum number of satellites per plane Referring back to Figure 1 using the calculated altitude the minimum number of satellites to cover the moon would be approximately 2 5 satellites per plane Now if this design was simply for having coverage by at least one satellite then taking the ceiling of this would give us three satellites per plane totaling six satellites In the aforementioned section GPS is shown to require more satellites Therefore a min imum coverage of at least three visible satellites anywhere on the moon calculates to 7 5 satellites per plane totaling 15 satellites Note One plane would have one less satellite or to make it even there could be 16 satellites and a coverage of at least six satellites would be 15
98. secret keys can be derived from the fault The validity of the proposed platform is verified through evaluation experiments performed on an actual device 2 Fault Attack 2 1 Principle of Fault Generation A fault can be generated using three methods 1 laser irradiation 2 lowering the power supply voltage and 3 inserting a glitch in a clock The method of using laser irradiation is ineffective since it needs circuit information in LSI Moreover a laser irradiation apparatus is expensive The method of lowering the power supply voltage induces an abnormal circuit operation by applying a voltage that is lower than the reference voltage This method may destroy the circuit since it manipulates the power supply voltage The method of inserting a glitch in a clock induces data errors by mixing a short clock pulse glitch in a clock signal during a specific round of the processing operation In this process no possibility of destroying a circuit exists Therefore this study adopts the method of inserting a glitch in a clock to generate a fault In fault attacks using a glitch a malfunction fault is generated by inserting a glitch in a clock signal since the setup time constraint of a flip flop cannot be satisfied 2 2 Key Specification in Fault Attack In fault attacks secret keys are specified using a fault which has been intentionally generated during the operation of a cryptographic circuit A pair of cryptograms that contain d
99. slidel pdf Int l Conf Embedded Systems and Applications ESA 12 Measuring and Evaluating the Power Consumption and Performance Enhancement on Embedded Multiprocessor Architectures Ericles Rodrigues Sousa and Luis Geraldo Pedroso Meloni School of Electrical and Computer Engineering University of Campinas Campinas Sao Paulo Brazil e mail ericles meloni decom fee unicamp br Abstract Nowadays MPSoCs Multiprocessors system on chip have been employed in embedded systems which require high computing complexity and power consumption savings For multiprocessor architectures a metric for measuring the speedup provided by different cores is one of the main characteristics which can be verified Besides showing the performance enhancements reached by hardware and software partitioning this paper also presents a study about the power consumption achieved by a reconfigurable multicore architecture Therefore in order to conduct the current case study it was conceived a scenario based on motion estimation vector used by H 264 AVC encoder which is an efficient algorithm used by many standards for video compressing Keywords MPSoC Embedded Systems Speedup Power Consumption 1 Introduction The benefits of the MPSoCs Multiprocessors System on Chip pose several challenges to system designers for exploring the potential of these architectures in order to compute efficiently high complex algorithms Nowadays applicatio
100. source programming library TSOAgLib 4 for developing our application program This paper is organized as follows In section 2 3 4 and 5 we have described an overview of standards test environment embedded workbench applications workbench results and discussion respectively Finally Conclusions are presented in section 6 2 An overview of standards 2 1 ISO 11783 communication protocol The ISO 11783 is a new standard for electronic communications protocol for tractors and machinery in agriculture and forestry This ISO 11783 standard is sometimes called as ISOBUS 5 The network has messages defined to allow communications between any of the components like communication between the Task Controller and the GPS ECU Navigational messages are defined and allow positional information to be received by the Task Controller The task controller can then deliver the prescription to an implement as needed based on position measured by an onboard GPS system It consists of several parts general standard for mobile data communication physical layer data link layer network layer network management virtual terminal implement messages applications layer power train messages tractor ECU task controller and management information system data Int l Conf Embedded Systems and Applications ESA 12 interchange mobile data element dictionary diagnostic and file server The structure of electronic data communication according
101. store the code to be executed and even more limiting only 1536 bytes of data memory RAM Because of this a very limited amount of buffering is done on ECG data This also limits the number of tasks that can be generated For example it might be logical to separate the DCM Agent and ECG Transmitter to run on two separate tasks but the hardware limits don t allow this many tasks We plan to consider other processor options and build our own pacemaker board in the future 3 Analysis of Pacemaker Software A major goal of this new framework is to provide a convenient mechanism to easily compare different abstract pacemaker models verify the correctness of those models and empirically analyze the designs using the empirical framework described above At the present the abstract models are manually converted to C source which is compiled and executed within the framework In this section we introduce an abstract model for the VVI mode which is the fail safe mode as described in the pacemaker specification Different modes can be selected by the user from the DCM as shown in Figure 9 To switch to another pacemaker mode the user only needs to select the new mode from the drop down list When the user selects another mode a new Set of parameters are listed for input Mgr eecorredd irom Alona Per Pacers Lewer Flaster Limit pga VE wh a0 YODA LHH 1 Lippi Fete Limi ppm Y Pulso Wiiih m Fall 1 4 l
102. t True 4 APERIODIC TASK SCHEDUI ING The scheduling problem for aperiodic tasks is very dif ferent from that for periodic tasks Scheduling algo rithms for aperiodic tasks must be able to guarantee the deadlines for hard deadline aperiodic tasks and provide good average response times for soft dead line aperiodic tasks even though the occurrence of the aperiodic requests are nondeterminstic The aperiodic scheduling algorithm must also accomplish these goals without compromising the hard deadlines of the peri odic tasks 4 1 Contribution One hybrid approach composed of the combination of two common approaches for servicing aperiodic re quests are background processing and polling tasks Background servicing of aperiodic requests occurs whenever the processor is idle i e not executing any periodic tasks and no periodic tasks pending If the load of the periodic task set is high then utilization left for background service is low and background ser vice opportunities are relatively infrequent Polling consists of creating a periodic task for servicing aperi odic requests At regular intervals the polling task is started and services any pending aperiodic requests However if no aperiodic requests are pending the polling task suspends itself until its next period and the time originally allocated for aperiodic service is not preserved for aperiodic execution but is instead used by periodic tasks Note that if an ap
103. the proposed design uses 2 to 1 multiplexers see Fig 10 to replace original NAND gates because a 2 to 1 multiplexer consumes less power than a static CMOS NAND gate The multiplier design in Fig 9 uses the column bypassing method 4 Compared to Fig 4 and for the same reason the proposed design uses 2 to 1 multiplexers to replace static CMOS AND gates at the outputs of the carry save adder in the last row IV EXPERIMENTAL METHOD AND RESULTS This section compares the performance of the proposed design to a conventional array multiplier an array multiplier with row bypassing 3 and an array multiplier with column bypassing 4 Because these designs do not change their full adder structure their full adders can be replaced by other types of full adder In other words it is possible to use a full adder that has few transistors to implement these multipliers All these designs use a 40 transistor static CMOS full adder 3 and 6 transistor 2 to 1 multiplexers as Fig 10 shows All the multiplier circuits in this study were implemented using UMC 90 nm process technology using HSPICE with a supply voltage of 1 0V at room temperature The length of every PMOS transistor and NMOS transistor is 80nm and the width is 120nm This study evaluates the circuit performance of these array multipliers in terms of average dynamic power leakage power delay and number of transistors In Tables I through to IV the Base is a conventio
104. the signal 17 The latent driving signal x is discretized into bins of These free parameters of the nonlinear Half Gaussian filter model are optimized by a simple elitism based Genetic Algorithm GA GA is an optimization algorithm which is based on observing nature and its corresponding processes to imitate solving complex problems most often optimization or estimation problems 18 20 A wavelet transform is used with a Daubechies mother wavelet filter The order of the wavelet is chosen as 44 at 8 levels of decomposition 21 Continuous wavelet transform of a signal is computed by 21 CWT t 2 fse _t dt w 0 0 s t y 0 r The inner product of the signal s t and Y eL R 0 is the mother wavelet function It must satisfy the following condition 0 lt C 2r f P A lt 0 5 Skeletal muscle force signal from FSR is filtered utilizing a Chebyshev type II low pass filter with a 550 Hz pass band frequency IV METHODOLGY The acquisition and transmission of the sEMG signals are done by using Analog Input ADC Module and the UART module of the PIC 32 The outputs from the DELSYS Bagnoli system are connected to the analog input channels of the PIC 32 micro controller In this work the signal from the Int l Conf Embedded Systems and Applications ESA 12 motor unit middle sensor is acquired and pre processed A C code is generated by a dsPIC block set for the PIC32 from SIMULINK The d
105. the source of the event and it has also to storage data for context change Thus even quickly recognized by the software processor the latency to attend interrupt requests shall take several clock cycles and it must be taken into consideration for a complete evaluation 2 3 Measuring the power consumption This section will briefly mention some possible strategies applied to manage the energy consumption and some characteristics considered on estimation of the total power consumption The energy consumption is an important topic which has been investigated during decades Nowadays there are different strategies to mitigate the power spent by processors For instance modern devices can operate in different modes such as full on active sleep deep sleep or hibernate 14 For software processors the transition between a stopped state to a running mode can be done easily from a programmed or external wake up signal Thus the ability to manage the operating transition between different states is a feasible option for optimizing energy consumption Also power can be saved by switching from high to low frequencies Although these transitions need a time to be done this paper will not consider this characteristic in analysis since these values are generally very short The methodologies for estimating the consumption are based on 14 15 which provides an accurately estimation since the hardware and software modules are connected by
106. to the module Tap sensors where attached to the ends to prevent movement against a barrier that is impenetrable avoiding in this way the overload of the motors We also implemented a lightning sensor systems that gets on and off automatically according to the environment 8 Int l Conf Embedded Systems and Applications ESA 12 2 4 Central Module The central module is designed to control the data transmission between the operator and the robotic module Basically it is a minicomputer with limited size and capacity An optimized Linux Kernel was compiled and installed with only the modules required for the application The central module communicates with the control module via serial communication and the modulus operator via 802 11g WiFi network A specific port for communication was defined and data is transmitted from to the central through an encrypted protocol Finally the central module has an attached USB camera The camera data is transmitted directly from the central module to the operator through another port using UDP protocol and no encryption Figure 2 Terrestrial Robotic Module 22 Actuators The actuators are responsible for handling the module Furthermore two servo motors are used to enable the operator to control the camera without the need for displacement of the module This system provides two degrees of freedom allowing a vertical axis above and below the display and the 2 5 Operador other
107. utilization of communication network 13 Future Work In this paper delay time is modeled as the bounded time varying delay however if sampling intervals are known such Int l Conf Embedded Systems and Applications ESA 12 that there exists two scalar values d and d2 and the variation exists between these two scalar values then this kind of delays can be modeled as Interval time varying Delay 0 lt d lt d t lt d3 Also if the sample interval time function varies in a piecewise manner than Piecewise time varying delay model will be very helpful For example an increasing sequence of signal S can be seen as a delayed signal with S t t t This paper only focuses on the system having the identical processor and same CPU utilization model is adapted for both processors However if system has different hardware nodes in terms of processor speed power and dedicated ASIC application then hardware constraints and time delay model has to capture these constraints as well while keeping the system stability intact 14 References 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 B Bouyssounouse J Sifakis Embedded Systems Design The ARTIST Roadmap for Research and Development Springer 2005 P Agrawal Fault tolerance in multiprocessor systems without dedicated redundancy IEEE transactions on computers 37 358 362 March 1988 P
108. verified in order to meet deadlines and to minimize their response time Also we present and discuss the results of experiments that compare the accuracy and the performance of our algorithm with others 1 INTRODUCTION Today in academy and manufacturing industry many research works have been made dealing with real time scheduling of embedded control systems The new generations of these systems are adressing today new criteria as flexibility and agility To reduce their cost these systems have to be changed and adapted to their environment without any disturbance This pa per aims to study the reconfiguration of reconfigurable systems to be supposed as sets of OS tasks such that it s implemented by a particular set at a particular time A disturbance is defined in this current paper as any internal or external event allowing the addition or removal of tasks to adapt the system s behavior For this reason many reconfigurable embedded con trol systems have been developed in recent years A reconfiguration scenario means the addition removal or update of tasks in order to save the whole system on the occurence of hardware software faults or also to improve its performance when disturbances happen at run time Usually these systems are modelled as sets of periodic real time tasks Each task 7 is char acterized according to 3 by an initial offset S a release time a worst case execution time C a rela tive deadline
109. when fractional delay filter is involved often uses quadrature filter which may not be cost effective since two filter channels have to be constructed to deal with each live ADC sample stream This paper presents a phase delay quadrature detection method based on derivatives of the sample stream The challenge is to deal with the inherent detection error of the naive derivative when high normalized frequency has to be used in RF IF applications The cause of the error is analyzed and a proprietary algorithm is developed to cancel the error at the critical quadrature crossing boundary namely 0 90 and 180 degree Keywords phase delay quadrature derivative fractional delay filter real time cost effective 1 Introduction The phase of a complex waveform described as AZ I jQ 1 can often be obtained by atan Q Z 2 If the waveform is passing through a digital signal processing DSP device ADC sampled filtered two filters I and Q have to be constructed which may not be cost effective in some applications Fig 1 illustrated a real application in which signal 3 put Merger Sena Fig 1 An example application where phase detection with complex filters I Q is not cost effective a waveform 1 is received from a radar front end processing unit with wide dynamic range Since the ADC doesn t have enough dynamic range to match the signal s range the signal is split into two ADC c
110. 06 108 93 PL 1 53E 06 38 23 3 50E 06 81 88 4 87E 06 116 52 1 25E 06 31 07 2 99E 06 70 04 4 54E 06 108 76 V CONCLUSION This paper proposes a low power multiplier with alternative bypassing implementation The advantage of the proposed multiplier design is that it does not require the use of tri state buffers and can be used in the row bypassing or column bypassing methods Based on UMC 90nm_ technology experimental results show that the proposed 16x16 bit multiplier design with row bypassing method reduces dynamic power by 17 16 and reduces the leakage power consumption by 18 12 on average The proposed 16x16 bit multiplier design with column bypassing method reduces dynamic power by 26 9 and reduces the leakage power consumption by 29 96 on average REFERENCES 1 Jan M Rabaey Anantha Chandrakasan and Borivoje Nikolic 2003 Digital Integrated Circuits A Design Perspective second edition Prentice Hall 82 2 3 4 5 I S Abu Khater A Bellaouar and M Elmasry Circuit techniques for CMOS low power high performance multipliers IEEE J Solid State Circuits vol 31 pp 1535 1546 1996 J Ohban V G Moshnyaga and K Inoue Multiplier energy reduction through bypassing of partial products Asia Pacific Conf on Circuits and Systems vol 2 pp 13 17 2002 M C Wen S J Wang and Y M Lin Low power parallel multiplier with column bypassing IE
111. 4 2 3 4 5 6 7 8 9 10 11 Int l Conf Embedded Systems and Applications ESA 12 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Y Hadj Kacem W Karamti A Mahfoudhi and M Abid A petri net extension for schedulability analysis of real time embedded systems In PDPTA pages 304 314 2010 W Karamti A Mahfoudhi Y Hadj Kacem and M Abid A formal method for scheduling analysis of a partitioned multiprocessor system dynamic priority time petri nets In PECCS pages 317 326 2012 W Karamti A Mahfoudhi and Y Hadj Kacem Using dynamic priority time petri nets for scheduling analysis via earliest deadline first policy In ISPA page to appear 2012 V Kimmo On combining the stubborn set method with the sleep set method In Robert Valette editor Application and Theory of Petri Nets 1994 15th International Conference Zaragoza Spain June 20 24 1994 Proceedings volume 815 of Lecture Notes in Computer Science pages 548 567 Springer Verlag Berlin Germany 1994 I Springer Verlag Berlin Heidelberg 1994 S H Kwang and J Y T Leung On line scheduling of real time tasks In IEEE Real Time Systems Symposium pages 244 250 1988 D Lime and O H Roux Formal verification of real time systems with preemptive scheduling Real Time Syst 41 2 118 151 2009 D Lime and O H Roux A translation based method
112. Allocation and T2Allocation for T1 and T2 respectively The processor will be attributed to the task component having the transition J Allocation with the highest priority having the earliest deadline Indeed the allocation is modeled by a registration of a mark in theinput place P getProc of the corresponding task component In Fig 6 the earliest deadline value is presented with the marking of the place PlRemainingPeriod and P2RemainingPeriod The main interest of coef matrix is to provide a solution for presenting the arithmetic operators Indeed in 13 it is used to model the equation L to calculate the Laxity with dPTPN In the current study we intercalate the coefficient 1 on the arc connecting the place TlRemainingPeriod and the T1Allocation associated with TaskC as well as for T2RemainingPeriod and the T2Allocation associated with TaskCo Based on the semantics of dPTPN the priority of TIAllocation is the multiplication of the T1RemainingPeriod marking and the corresponding coefficient of coef matrix coef 1 In Fig 6 T1Allocation is the highest priority because it has the earliest deadline After execution the task T1 releases the processor P1 on firing the transition TlReleasing associated to the TaskC component The crossing allows the liberation of the processor by putting a token in the place Procl Fig 6 4 3 Modeling of the communication between the instances of TaskC
113. Candidate list does not have such blocks any more the 2LGC sorts the blocks of the Candidate list in the order of invalid marked page numbers and removes a block address from the tail of Candidate list The block address currently being added to the Candidate list is quickly demoted to the Garbage block list if pages in the block are sequentially programmed 2 When garbage collection is triggered the 2LGC firstly checks the Garbage block list and selects a block from the head of the Garbage block list as the victim If the Gar bage block list is empty the 2LGC then checks the Candidate list and selects a block from the head of the Candidate list New element is added if its Element is discarded if Aumber of iawalidamarked Candidate list the candidate list is full pages is over a threshold gt he Elements are sorted by the number of invalid marked pages Element is demoted if the number of invalid marked pages reaches N Garbage block list fh The next victim candidate block for garbage collection FIFO order Element physical block address N number of page in a block Fig 4 Two level lists in the 2LGC algorithm In 2LGC the FTL is designed to use a single block garbage collection scheme as mentioned in Section IV B Although the host issues storage access requests during garbage collection the FTL can back
114. D and a period T In general a task s relative deadline can be different from its period A task is synchronous if its release time is equal to 0 Otherwise it s asynchronous Reconfiguration poli cies are classically distinguished into two strategies static and dynamic reconfigurations Static reconfig urations are applied off line to modify the assumed system before any system cold start 9 whereas dy namic reconfigurations can be divided into two cases manual reconfigurations applied by users 10 and au tomatic reconfigurations applied by intelligent agents 11 12 This paper focuses on the dynamic reconfigu rations of assumed asynchronous real time embedded control systems that should meet deadlines defined ac cording to user requirements 13 The organization of this original paper is as follows The next section formalizes some known concepts in the EDF theory section II analyzes the Background section IV presents the state of the art In section V we define a new theoretical concepts In section VI we define an intelligent agent based architecture for the system s feasibility and in section VII we propose a new algorithm for optimization of response time Our proposed architecture is implemented simulated and analyzed in section VIII Finally section IX concludes this paper 2 State of The Art In the following we only consider periodic tasks Few results have been proposed to deal with deadline as sig
115. Development Board 3 supports 16 bit PIC microcontrollers MCUs and digital signal controllers DSCs as well as 32 bit MCU devices The board has a socket for installing one of the supported processor modules It has some I O capability with 4 push button switches 8 LEDs a 2x16 character LCD an RS 232 serial port an on board temperature sensor a program debug port small prototyping area and PICtail plus expansion ports 128 lt lt ae pe Y wor Int l Conf Embedded Systems and Applications ESA 12 Fig 1 Hardware kits used in the lab 2 PIC24 and PIC32 plug in modules 4 PIMs that can be installed on the Explorer 16 processor socket 3 In house developed I O board This board has a 16 key keypad and four 7 segment display modules It is designed and built to be compatible to the PICtail plus standard interface available on the Explorer 16 board 4 Microchip graphics LCD module 5 that is compatible to the PICtail plus standard interface available on the Explorer 16 board The software tools utilized in the lab are 1 MPLAB IDE 6 is an integrated embedded program development environment It is used to create assemble compile link download and debug assembly and C programming projects for Microchip PIC MCUs and DSCs It also comes with a built in simulation tool that facilitates testing of programs without a need for the actual target hardware 2 C 30 and C 32 compilers 7 for the 16 bi
116. E oi Ci D i to m 3 2 CONTRIBUTION AN ALGO RITHM FOR FEASIBILITY TESTING WITH RESPECT TO SPORADIC TASK SYSTEMS In the current paper we suppose that each system amp can be automatically and repeatedly reconfigured is initially considered as and after the ip reconfigu ration turns into where i nO We define V P and V Py two virtual processors to virtually execute old and new sporadic tasks implementing the system after the iz reconfiguration scenario In all old tasks from are executed by the newly updated VP and the added sporadic tasks are executed by VP The proposed intelligent agent is trying to minimize the response time Resp of after each reconfiguration scenario For example after the first addition scenario turns into E is automatically decomposed into VP and VP for old and new tasks with the pro cessor utilization factors U VP and U VPIP respec tively Formalization We assume in this work a system to be composed of a mixture of n periodic and m sporadic tasks An assumed system CTI 1 T2 Tn turns after a Int l Conf Embedded Systems and Applications ESA 12 reconfiguration scenario to fris Tos Tm Oya On 2 0m by considering that m n new sporadic tasks are added to After each addition the tasks are logically divided into two subsets One con tains the so called new sporadic tasks wh
117. EE International Symposium on Circuits and Systems pp 1638 1641 2005 Y T Hwang J F Lin M H Sheu and C J Sheu Low Power Multiplier Designs Based on Improved Column Bypassing Schemes Int l Conf Embedded Systems and Applications ESA 12 6 7 8 TEEE Asia Pacific Conference on Circuits and Systems pp 594 597 2006 Y T Hwang J F Lin M H Sheu and C J Sheu Low Power Multipliers Using Enhanced Row Bypassing Schemes IEEE Workshop on Signal Processing Systems pp 136 141 2007 J T Yan Z W Chen Low cost low power bypassing based multiplier design IEEE International Symposium on Circuits and Systems pp 2338 2341 2010 Se Hun Kim Mooney VJ Sleepy Keeper a New Approach to Low leakage Power VLSI Design IFIP International Conference on Very Large Scale Integration 2006 Int l Conf Embedded Systems and Applications ESA 12 83 Performance Power and Area Exploration of Cache for Embedded Applications Mehdi Alipour Esmaeil Zeinali Kh Kamran Moshari and Ensiyeh S F Moghaddam l Allameh Rafiei Higher Education Institute of Qazvin Iran Dept of Electrical Computer and IT Engineering Islamic Azad University Qazvin Branch Qazvin 34185 1416 Iran mehdi alipour qiau ac ir mehdi_10f yahoo com Abstract Power dissipation and the resulting heat issues has become possibly the most critical design constraint of modern and future processors that c
118. Fig 2 not the absolute phase acos value so the results shown in Fig 5 is not surprising Although the acos value around the phase 0 and 180 degree is far off from the actual about 30 degree error but the quadrture left right can still be correctly identified based on the sign of cosine For example around phase angle 0 the acos produces value as about 30 degree instead of 0 but the sign of cos O and cos 30 are the same 1 e positive around the phase 180 degree the acos produces value as around 150 degree instead of 180 but both have the same sign in terms of cos so they will not affect the quadrature identification either Around the critical 90 degree where the sign of cos term is abruptly switching the derivative method produces smooth angle transition error nearly as zero as clearly shown in Fig 5 3 An Example of Derivative based Phase Delay Detection As shown in Fig l waveforms from two channels can have intended gain separation and unintended phase time delay separation 1 The waveforms are shown in Fig 6 Both the gain and phase delay can be detected and then adjusted before merging into a wider dynamic range bandlimited radar IF wave before ADC time series samples 100 ot tp to ot ater ime LI i liy Li lily ee EEJ it tt 805 60 40 20 20 40 60 F3 B
119. Ginew ai At S4 By applying equation 1 that notices d i a D we have R a D t CG Or to obtain a feasible system after a reconfiguration scenario the following formula must be enforced Ri gt 0 gt a Di t C gt 0 By this result we can write Qinew Di t Ci gt 0 where ainew a At So we obtain a At D t Ci gt 0 gt At gt t C a Dj e Solution 5 Tolerate some non critical Tasks m among n m n firm for a reasonable cost S5 E 7 Ci Di mi Ii t lton m 1 it tolerates missing deadline mM 0 it doesn t tolerate missing deadline I H Hard task I S Soft task e Solution 6 Removal of some non critical tasks to be rejected S6 amp 7 C34 D Mli L i lto ny m 1 it tolerates missing deadline m i 0 it doesn t tolerate missing deadline I H Hard task mi S Soft task For every solution the corresponding response time is Resp 1 the response time calculated by the first 166 solution kRespk 2 the response time calculated by the second solution Respk 3 the response time calculated by the third solution Respg 4 the response time calculated by the fourth solution Respx 5 the response time calculated by the fifth solution kespgk e the response time calculated by the sixth solution We define now Resp optimal noted Resp accord ing to the previous three solutions ca
120. ION Given the proliferation of portable electronic devices and the batteries they require to operate low power very large scale integrated circuits VLSI design has become an important issue A low power design can extend the operating time of portable systems and reduces the cooling and packaging costs of integrated circuits The power consumption of CMOS devices generally includes two categories The first category is static power consumption which includes gate leakage sub threshold current and drain junction leakage Transistor power leakage has increased exponentially in recent years due to continued scaling down of the transistor threshold voltage and transistor size in CMOS technology The second category is the dynamic power consumption incurred by charging and discharging capacitances The dynamic power consumption of CMOS circuits can be expressed 1 by Paynamic CLVpp Po if where Ci is the fan out capacitance Vpp is the supply voltage Po is the probability of switching activities every clock cycle and f is the clock frequency Therefore reducing the switching activity can reduce dynamic power consumption Taiwan phd9704 csmail nchu edu tw Taiwan ychang cs nchu edu tw A multiplier is an important arithmetic operation circuit in many digital signal processing DSP applications including fast Fourier transform FFT discrete cosine transform DCT Histogram Processing filtering etc Because of the high
121. Int l Conf Embedded Systems and Applications ESA 12 SESSION NOVEL APPLICATIONS ALGORITHMS SUPPORTING SYSTEMS AND EMBEDDED DEVICES Chair s TBA Int l Conf Embedded Systems and Applications ESA 12 Int l Conf Embedded Systems and Applications ESA 12 Constellation Design of a Lunar Global Positioning System Using CubeSats and Chip Scale Atomic Clocks A Batista E Gomez H Qiao and K E Schubert armani r2labs org ernesto csusb edu hqiao csusb edu keith r2labs org School of Computer Science and Engineering California State University San Bernardino 5500 University Parkway San Bernardino CA USA Abstract Accurate navigation on the moon Mars or any other astronomical body is essential to scientific investi gation The research presented in this paper covers the constellation design of a Lunar Global Positioning System GPS using the CubeSat platform Since CubeSats have significantly smaller dimensions than most current satellites their associated cost is much less to place into orbit This creates a compelling reason to use them for a Lunar GPS However CubeSats require a much smaller atomic clock which has not been available Fortunately there have been recent advancements in chip scale atomic clocks CSAC which can fit within the CubeSat platform We propose a Rider constellations of two orbital planes and eight satellites per plane for minimum position determination or fifteen satel
122. It will update the total money information Afterwards ZaskCheck will go on executing based on the past money information instead of the latest one so the data inconsistency occur Int l Conf Embedded Systems and Applications ESA 12 As shown in Fig1l the scheme for solving this problem is to find the critical regions in 7askMoney and TaskCheck Through the control of semaphore Occupying ZaskMoney and ZaskCheck can be executed mutual exclusively to guarantee the information consistency Suppose that the checkout logic is just executed to the point between information accessing and information processing of total money when customer choose extra items Even though without semaphore to control the execution of Zask tem and 7askCheck due to the special way of dealing with item information append the item to item queue no data inconsistency will be incurred Table2 Message Type Task Name Variable Name Type TaskMoney TaskCheck Msg Queue TaskItem TaskCheck Msg Queue TaskCheck TaskChange Msg Box TaskMone TaskCheck Semaphore TaskItem void pdata while 1 OSQPost QItem void value TaskMoney void pdata ee while 1 i Occupying i OSSemPend Occupying 0 amp err OSQPost QMoney void TotalMoney OSSemPost Occupying Fig 1 TaskCheck void pdata while 1 i ItemNumber int OSQPend QItem 0 amp err OSSemPend Occupying 0 amp err OSSemPost Occupying OSMboxPost Change void
123. Kalman Filter is used to estimate the pose of a robot and build the ceiling map with line features The experiment is practiced in our indoor test bed and the proposed algorithm is proved by the experimental results Keywords Mobile robot Localization Embedded module Ceiling vision Ceiling segmentation Scene matching 1 Introduction When a mobile robot performs their missions the localization is needed basically Several past researches established how to obtain their location information from the environment by using a distance sensor or a camera However these methods have map making problem when the environment changes and localization problem while the robot moves from sensing features has typical affine and occlusion characteristics To deal with these difficulties ceiling vision based robot navigation has been popular that adopts landmark from ceiling which has less changes of environments relatively Existing ceiling vision localization uses point feature matching at their researches Almost every point features like Harris corner 1 SIFT 2 and SURF 3 are sensitive to environmental variations and it is a major cause of incorrect data association This limitation of monotonous patterns in ceiling makes researcher use molding line of ceiling area or another feature mounted on ceiling such as fire sensor sprinkler or lamp on ceiling In spite of these approaches the researches still have problem of affine and lack of feat
124. Layout Total Devices failed drives which drive failed first and much more Recall this step no 8 until all drives has been 9 tested 10 That step constructs the damage RAID from the components Again you have to replace dev sdc3 with whatever actual partition is gt mdadm assemble run dev mdO dev sdc3 gt mdadm assemble run dev md1 dev sdd3 11 After all process completion creates an empty directory in active user home or in the mnt directory to mount the recovered RAID array gt mkdir mnt Raid 12 Mount RAID array on this directory To mounting multiple drive devices as we construct in second last step repeat next command according to the constructed drive gt mount dev mdO mnt Raid gt mount dev md1 mnt Raid 13 Now you can access files and folders of the NAS RAID from desktop As we complete recovery process in with root access So there are no permissions for others To change permissions for anyone get access of recovered files type these command on prompt gt chmod R 777 mnt Raid 14 Now take back up recovered data at network or on portable storage device Data copy will time according the data size and data transfer speed of storage device These all steps are for RAID O striped and RAID 1 mirrored array For RAID array recoveries that have no fault tolerance you must require all original drive or drive clone On fault tolerance you recovery is possible with less drive equ
125. MG signals These nonlinear filters extract a signal by significantly reduces the noise The latent driving signal x results in the EMG which can be computed using an instantaneous conditional probabilityP EMG x 17 Research work in 16 describes the EMG signal as an amplitude modulated zero mean Gaussian noise sequence This estimation algorithm uses the model of the conditional probability of the rectified EMG signal emg EMG 17 Equation 1 gives an Exponential Measurement Model for the rectified EMG signal 17 em exp TS P emg x 1 Int l Conf Embedded Systems and Applications ESA 12 Equation 2 gives a Poisson Measurement Model for the rectified EMG signal 15 P emg x x 22 2 n In equation 2 n is the number of events Equation 3 presents the Half Gaussian measurement model for the rectified EMG signal 17 2 exp gg P emg x ae 3 The model for the conditional probability of the rectified EMG is a filtered random process with a random rate The likelihood function for the rate evolves in time according to a Fokker Planck partial differential equation 16 The discrete time Fokker Planck Equation is given by Equation 4 p x t ax p x e t 1 2 a p t 1 a xp x e t 1 6 1 f p x t 1 4 In Equation 4 and p are two free parameters where is the expected rate of gradual drift and p is the expected rate of sudden shift in
126. Microsoft called Kinect is used to identify and detect an emergency condition Kinect sensor bar was released by Microsoft for use with their Xbox 360 video game system 7 The sensor bar consists of a VGA camera two 3D depth sensors multi array microphones and a motorized tilt mechanism The sensing range for Kinect is 3 9 11 feet The Software Development Kit SDK was released for the Windows 7 operating system It enables the development of applications with C C or Visual Basic by using Microsoft Visual Studio 2010 The SDK will let the programmer have access to low level sensor streams from the depth sensor color camera sensor and _ four element microphone array The depth sensor that is primarily utilized for this system consists of an infrared laser projector combined with a monochrome CMOS sensor which captures video data in 3D under any ambient light conditions The 320x240 depth stream has an 11 bit depth The Kinect has received interest from the academic and research world as a tool for various research areas including security medical archeology 1 e 3D scanning of digging sites Natural User Interface NUI etc Researchers at the University of Missouri have been using the depth sensor in Kinect to detect early signs for fall indication for senior citizens 8 Derive Skeleton Object Capture Depth Stream Predictable Matching Algorithm Generate Alarm Figure 1 Architecture of the Motion Recognition Bas
127. Minnetonka MN USA Int l Conf Embedded Systems and Applications ESA 12 7 Low Power Multiplier with Alternative Bypassing Implementation Guan Lin Jiang Tung Chi Wu Yen Jen Chang Department of Computer Science and Department of Computer Science and Department of Computer Science and Engineering Engineering Engineering National Chung Hsing University National Chung Hsing University National Chung Hsing University No 250 Kuo Kuang Road Taichung 402 No 250 Kuo Kuang Road Taichung 402 No 250 Kuo Kuang Road Taichung 402 Taiwan s9856047 cs nchu edu tw Abstract As portable devices have become increasingly popular power reduction has become an important issue in device design Because traditional row bypassing multipliers and column bypassing multipliers use tri state buffers they create the floating point problem This problem in turn increases leakage power consumption This paper presents a low power multiplier with an alternative design The advantage of this multiplier design is that it does not use tri state buffers and can be used in the row bypassing method or column bypassing method Based on UMC 90nm technology experimental results show that the proposed multiplier design with column bypassing method reduces dynamic power by 26 9 and reduces the leakage power consumption by 29 96 on average Keywords dynamic power bypassing floating point problem leakage power multiplier I INTRODUCT
128. OS transistor and a NMOS transistor to turn off full adder and then the partial product yi1Xjcan bypass full adder to the output The operation of the b design is similar to the a design when the bit of multiplicand y 0 a partial product y x is zero so the full adder is turned off and the partial product y x can bypass full adder to the output Compared with Fig 5 the proposed design does not use tri state buffers which not only reduces power consumption but also solves the floating point problem Figure 8 shows the 4x4 bit multiplier design with the row bypassing method and Fig 9 shows the 4x4 bit multiplier design with the column bypassing method 80 U lt o Figure 8 Proposed 4x4 multiplier design with row bypassing method y3X0 y2X0 y Xo yoXo E mM FA y3X1 TH yixi 0 TH Ieal Liral 1 Y3X2 y2X2 Tfeal A aT g Losccosocsocoococooosocsoosonoonosooooooeooe Lacosoosononssososossssonesososonosossonnensosnnonononnsononnnsoononnnsed Figure 10 A 2 to 1 multiplexer Int l Conf Embedded Systems and Applications ESA 12 The multiplier design in Fig 8 uses the row bypassing method 3 and needs extra circuits to produce the correct result The extra circuits are in the dotted line area Compare to Fig 3
129. PC COM1 port for sending time acknowledgement ACK of GPS messages CAN message to PC In this relationship scheme we use AMTEL mini JLINK USB driven JTAG interface for ARM cores including mini USB cable is an optimizing C C compiler i e download and debug the application program for ARM Cortex M3 microcontroller and attach between test board Channell and PC USB3 port Universal Serial Bus This connection is main platform of our application program development Because of this connection download application program from PC to the microcontroller for debugging and make sure the ECU test board becomes a GPS sensor CAN controller has some ports but for our test purpose we use only two ports for CAN L and CAN H 11 and connect with CAN analyzer Here we also make a connection between test PC and CAN analyzer i e Real SYS CAN Pro USB device for hardware by USB2 port through USB cable After establishing all the connections we can verify the GPS message status by CAN Pro Analyzer v1 0 software in PC USB1 port is for test board power supply through the USB cable and LCD display is only showing some information about GPS manufacturer 4 Embedded workbench application 4 1 System architecture For the application program of GPS sensor we use an Open source programming library named ISOAgLib The IsoAgLib is a C library in development of ISO 11783 standard applications in an Object Oriented way to serve as a software layer betwee
130. Systems and Applications ESA 12 Table 2 Workloads Trae Read W rite Random Sequential Ratio Access Ratio Workload 1 r 80 w 20 r 100 s 0 Workload 2 r 80 w 20 r 0 s 100 Workload 3 r 20 w 80 r 100 s 0 Workload 4 r 20 w 80 r 0 s 100 5 2 IOPS and Execution Time Figure 6 shows the flash storage IOPS varied with the garbage collection scheme during the time intervals In this experiment the IOPS represents the number of page level commands generated by the FTL not the number of request level commands issued by the host The IOPS of the 2LGC scheme were compared to that of the on demand victim selec tion technique using the IOMeter benchmark workloads shown in Table 2 As shown in the figure the average IOPS of the 2LGC scheme is superior to that of the on demand victim selection technique because 2LGC saves garbage col lection costs There is a significant decrease in the IOPS of the on demand victim selection technique because it causes entire block searching and victim selection overhead when garbage collection is triggered see Section III B for more details of garbage collection latency On the other hand the 2LGC scheme can reduce the system latencies caused by garbage collection because it maintains victim candidate blocks within the two level lists during system run time Moreover the peak delays can be minimized and responsive ness to the host improved because of the effectiveness of the s
131. Window gt p Depth Stream et O Skeleton rendered if full body fits in frame Color Video Stream Safe 31 fps a o s ih MainWindow i Depth Stream Skeleton rendered if full body fits in frame Color Video Stream Figure 6 a Lower and b upper boundary conditions for gesture recognition The system was made more robust by incorporating a tolerance that was determined experimentally The tracking of angular positions lies between 27 degrees 90 degrees for the current experimental setup This constitutes a 30 percent tolerance The simulation results are summarized in Table 1 The outstretched arm held approximately at 90 degrees from the body is considered as normal position The frames were captured in three different lighting conditions The first scenario involved the simulation is a well lit room that has approximately 800 lumens The second scenario was a poorly lit room with about 10 lumens Finally the third situation was a totally dark room 0 lumens The MR BEAS successfully tracked and identified the danger situation irrespective of the ambient lighting conditions within the tolerance lt 28 degrees angle between arms and body Int l Conf Embedded Systems and Applications ESA 12 Angle between Lighting eae ie Lumens Table 1 Evaluation Results of the MR BEAS Normal 15 0 10 800 degrees Normal 15 Normal 30 0 10 800
132. _file bitstream _count data_ready and eof_data_partial_ready The output data from this module is in terms of 16 bit data signal to the USB_IF module JPEG_Ingut_IF_top F y sa 2 sy ee T m i k beginning module comt ne final JPEG_data_top F a el Ww n gS ee oe 2 5 ei ie AE jj mi i EEE a inslanco_ narma Figure 9 Integration of Interconnection Modules and JPEG Encoder The figure above shows the integration of both the interconnecting modules and the JPEG Encoder module 5 6 USB Application Interfacing to the SIS Network The development environment that is being used to build the SIS Network is Nokia s Qt with the OpenCV library for image processing QIODevice is the base Qt interface class of all I O devices 9 where it is responsible for instantiating communication with external devices e g USB Raw RGB data that is being captured within the UVC Application will be transported via USB link to the FPGA device for JPEG compression Then the compressed image data will be 33 transmitted via QudpSocket class to the user specified destination parties 10 Cypress provides a USB library CyAPI for application interaction with the EZ USB FX2 USB Development Board 6 Conclusion The proposed approach of using FPGA systems for off loading specific computationally intensive processing in real time will benefit the SIS clients by streaming video with minimal bandwidth usag
133. a fide array and can on request fiddle superblock information GParted is a free graphical partition manager It visualizes the drive partition layout in a graphical way and enables you to resize copy and move partitions without data loss Here it provides information about the drives volumes of the hard disk drive xxdiff is an old Graphical File And Directories compare tool it start from command line give output is legacy X It required later for data integrity check 5 1 1 Caution There are possibilities of mistake on the time of Ubuntu installation on wrong drive That cans destroy the original drive by overwriting To prevent this situation does not connect the NAS hard disk drives to the computer system until you complete installation of Ubuntu OS 5 2 Analysis of single drive failure Using the redundant scheme of parity on NAS can only tolerant single disk failure but RAID 0 configuration offers no redundancy so it is need an appropriate data recovery To know the chances of single disk failure let take a NAS box having four disks drive The chance of at least failure of one drive per year is 2 4 and up to 13 4 When NAS is working and one first drive was lost generally nobody notice it on single drive fault tolerance NAS Device starting working in degraded mode and it s still running as same you should stop uses of NAS or if it is not possible decrees overhead if possible Immediate take action t
134. ably because Google allows to modify source code of the platform if the platform can be passed CTS test Android platform is also well known that it is not support interoperability among various platform versions It means that there are a lot of difficulties in testing software on various platforms and devices For instance a developer make an application based android platform version 2 0 but he does not sure about that his application executes well on the version 2 1 because of the interoperability Therefore the android software is needed huge tests process for diverse devices and android platform versions Many tools and techniques exist for automating the testing of mature well established applications such as desktop or server programs However the physical constraints of various device as well as interoperability problem of android platform make android software prone to new kinds Corresponding author of bugs 2 To resolve this problem we suggested a new tool named Android Conversion Support Framework ACSF The ACSF support several functions and those functions help developers to reduce a time for doing repetitive or unnecessary tasks on the software testing Those functions are mostly automatic and detect potential bugs in the software Developers get helpful information from the tool without their effort when they only use the tool To find potential error first developer generates monitoring code Secondly the monitor
135. acitive touch screens b Layered architecture of the Microchip Graphics Library c Use of widgets in the Object Layer of the Microchip Library d Library functions to recognize inputs from touch screen e Implementation of call back function to respond to user inputs f Implementation of interactive application programs 8 Digital Thermometer Core concepts a Understanding different A D operating modes and their configuration b Reading analog input signals using A D channels c Writing device driver for character LCD module d Reading temperature sensor values using A D interface e Displaying thermometer readings on LCD module The course has been continuously evolving over time in response to changes in technology as well as desire to incorporate independent project component to it In its latest form we have the first six labs as required for all the students The last two labs are selected by the students based on their focuses of interest and their final project topic choices Students working on projects that require the use of touch screen graphics module for user interface component of their applications benefit by taking Lab 7 Those students who work on tasks that interact with the user using simple character LCD modules and or utilize A D modules for analog signal interfacing benefit by taking Lab 8 3 Laboratory Kits This section presents the hardware and software kits utilized for the labs 1 Explorer 16
136. al life application result and further discussions are in Section 4 2 Derivative Based Detection 2 1 Fundamentals of Naive Derivatives To cover the full range 180 degree angle phase delay detection the quadrature information of the angle can be derived from the cosine alone When the angle detected from asin term which covers 0 90 degree is known the actual phase can be deduced as cos gt 0 asin sin gt 0 180 asin 180 asin 3 Fig 2 shows the identification of quadrature Note that only the sign of the cosine term not necessary its accurate value is needed to identify the quadrature correctly as long as the quadrature crossing critical points namely the 90 boundaries can be identified uniquely 90 A II I COS cos sin asin 0790 sin asin 0790 180 180 gt 0 COS cos sin asin 9070 sin asin 9070 IIT IV 90 Fig 2 Quadrature Identification with cosine The cos term can be derived by using derivatives of the incoming waveform stream especially in baseband sampling where the normalized frequency is low or equivalently the ADC sampling frequency is far higher than signal frequency as a result many samples per cycle can be sampled and used to calculate the derivative or the sampling period T is relatively very short as defined mathematically sin t At sin ft At gt 0 AtasT 4 At cos t But in RF IF signa
137. al to tolerant than the total number of original RAID drive The whole recovery process is more complex cannot be made detailed explanation in that paper Int l Conf Embedded Systems and Applications ESA 12 5 5 3 Finishing the whole Process After completely of backup process here is optional task to checking recovered data Integrity Instructions to running integrity check 1 In this command replaces media drive Backup with the directory path where the recovered data was copied gt xxdiff media drive Backup mnt Raid Use n and p key hit to navigate previous and next difference in the difference list on graphical split windows 2 And last action is unmounts the attached portable storage devices and RAID array with these commands gt umount mnt Raid 3 Finally stop RAID array by all component drives First stop the last RAID array component and in end the first one Pas gt mdadm stop dev md1 gt mdadm stop dev md0 Next exit from the root session and terminal window by executing exit command twice And shutdown the computer system remove all NAS hard disk drives and portable storage device s 5 6 How to increases chances of data recovery and save critical files Data recovery is an alternative method this is not the solution to keep safe data Create backup of important data regularly keep one on safe side If one is want to update or making any major change on NAS RAID configu
138. anayake and J Valls Miro Extending the Limits of Feature Based SLAM With B Splines Robotics IEEE Transactions on vol 25 pp 353 366 2009 7 S Se D Lowe and J Little Mobile Robot Localization and Mapping with Uncertainty using Scale Invariant Visual Landmarks The International Journal of Robotics Research vol 21 pp 735 758 August 1 2002 8 S Se D G Lowe and J J Little Vision based global localization and mapping for mobile robots Robotics IEEE Transactions on vol 21 pp 364 375 2005 9 S Se D Lowe and J Little Efficient Feature Tracking for Scene Recognition using Angular and Scale Constraints International Conference on Intelligent Robots and Systems pp 4086 4091 Sept 22 2008 Int l Conf Embedded Systems and Applications ESA 12 111 Power Delay and Area Optimized 8 B t CMOS Priority Encoder for Embedded Applications J Mohanraj Department of Electronics and Communication Engineering Vel Tech Technical University Avadi Chennai 600 062 TN India mohanvit 86 gmail com Abstract A n input n output priority encoder implemented in hardware often serves as a polling device that permits access to a single hardware resource whenever access requests initiated by multiple devices are received at its inputs either on chip or off chip Data buses data comparators fixed and floating point units and interconnection network routers are important sub systems whi
139. ance evaluation platform for fault analysis attacks against the key generation section of an actual device Using this platform the resistance of the actual LSI against fault analysis attacks which has been uncertain can be evaluated Keywords Hardware security Fault attack Encryption LSI Encryption standard 1 Introduction Confidential information in credit and cash cards is protected against illegal reading through the use of cryptographic circuits It has been sufficiently confirmed that the decryption of the encryption standards used in cryptographic circuits is computationally impossible However it was recently reported that when a theoretically safe encryption algorithm was embedded in the hardware confidential information could be illegally specified by fault analysis attacks fault attacks 1 13 Here fault attacks specify the secret keys by intentionally generating a fault during the encryption processing and by comparing the fault and normal cases This study develops an evaluation platform that can verify resistance against fault attacks tamper resistance in an actual device through the use of encryption LSI In the evaluation platform a fault is generated through a glitch ina clock which is supplied to the encryption LSI Based on the results of the encryption processing on which a fault is generated the fault generation position is specified This study also develops a new algorithm that will determine whether
140. ant The ECU sending the recessive bit must sense the bus is at a dominant state when the bit was sent and must cease transmitting the message at that time and retry the next time the bus becomes idle This strategy allows more dominant identifiers those with a lower value to have a higher priority on the bus To allow this feature to work properly CAN synchronizes messages at the beginning of each transmission to assure bits are aligned The result is that ISO 11783 provides a communication system where ECUs share a communications link and messages at any point in time are allowed access to the bus based on their priority 41 ECU of ECU of ECU of ECU of ECU of Display DataSource GpsSensor ProprietaryCan TractorBridge BUS BUS terminator CAN BUS terminator Application Program Figure 2 Structure of CAN bus 2 3 CAN Message Structure The implementation of the CAN message for tractors and machinery for agriculture is based on CAN Version 2 0B 7 This describes a 29 bit identifier and a data rate of 250 kbit s CAN Extended Data Frame ACK EOF o Identifier a i Identifier r DLC Data field CRC Field Field 11 bits RIE 18 bits 4 bits 0 to 64 bits 15 bits 2 bits 7 bits e Sap Lg No bit stuffing Arbitration field SjI ilmel PDU Format PDU Format PDU Specific Source Address a 5 6 a aa 14 is 1617 24 25 ben Figure 3 Message frame format of CAN Data CAN 2 0
141. application Thus using Android for what it does best managing UI graphical user interface and cellular connectivity and a subsystem that is responsible for managing the signal acquisition system 103 That is why we use the MC9SO08JM60 microcontroller descripted in section 3 2 This microcontroller was used in order to overcome the synchronization drawback It must fulfill the task of attaching the data acquisition system with the Android platform seeking to meet the necessary requirements for the correct time sampling of the ECG signal and avoiding the overlapping loss of data problems The MCU provide two serial interfaces SPI one to communicate with the data acquisition system and other to communicate with the Blizzard platform the connection is illustrated in Figure 7 The SPI1 is configured as master mode with a frequency of 1Mbps The SPI2 is configured as slave mode for this reason the operation frequency is imposed by the master device Blizzard platform with a frequency of 500 Kbps Furthermore it implements a First Input First Output FIFO memory management The FIFO implementation is very important because it decouples the data processes offered from the ADS1298 and demand from the Blizzard platform Data Acq Blizzard DAS ARM Figure 7 Connection diagram among subsystems MCU MC9S08JM60 In conclusion we have 3 subsystems as it can be seen in figure 3 the subsystem based on android the MCU to decou
142. application utilizes the Motion JPEG algorithm 2 for video encoding and decoding where JPEG encoding is the first step JPEG is a lossy image compression standard named after its creators the Joint Photographic Experts Group 3 3 Integration to the UVC System Data Processing Certain SIS applications running on the client machine will send the uncompressed data to the FPGA which in turn will send the compressed data back to the PC for concatenation and header processing using a high speed communication link A Field Programmable Gate Array FPGA is a reprogrammable logic chip that provides the ability for real time parallel processing that increases computational performance ease of hardware scalability fast prototyping and reconfigurability of its hardware fabric to change to any computational algorithms that are desired 30 Algorithm HW Solution 2 clock cycles SW Solution 12 clock cycles Figure 1 Software Vs Hardware Processing Figure 1 above shows hardware advantages over software in terms of clock cycles needed to perform certain calculations The ability of parallel processing makes FPGAs the preferred choice for time sensitive applications that are computationally intensive 4 Waring for tne ir as JPEG compreczion pa Re ae Read a 96x06 gut 24 Send the RAW Read PEG Witte the JPEG to z fie Ad Pa P a Pel cooky tetera le merce bala k USR tata Imen USR awi chow il on ihe syre
143. are waveform simulates the floating point problem D Floating Point Problem Figures 5 a and b depict modified full adder cells that can be used in an array multiplier with the row bypassing method 3 and an array multiplier with column bypassing method 4 respectively Because these designs use tri state buffers to eliminate redundant signal transitions they experience the floating point problem In the floating point problem one point does not connect to VDD supply voltage and GND ground and makes the current unstable In Fig 5 Ao Bo Co D and E are floating points when x is 0 y is O and the tri state buffers are turned off 79 Consider the case in Fig 6 a where the initial Xj is lv volts A A lv B B Ov and C C Ov at Ons to 10ns At 10ns x changes to Ov A changes to Ov B changes to lv and C changes to lv Because Xj is Ov the transmission gates are turned off and A Bo and Co are floating points These points are susceptible to sub threshold leakage From 10ns to 4000ns because A Ov A 1v in the beginning A and A have different voltages This causes the sub threshold current to transmit from A to A and thus the A voltage drops to near Ov Conversely the B and C voltages drop to near lv as Fig 6 b shows The floating point problem also called the DC power problem 6 not only causes unstable voltage but also prevents transistors in full adder from turning off co
144. art as it ages However mode changes must be carefully applied so that they don t interrupt the current operation of the pacemaker Revise NASPE BPEG generic code for antibradycardia pacing Chamber s paced Multisite pacing Chamber s Response Rate sensed to modulation sensing A Atrium T Triggered R Rate modulation A Atrium Ve V l Ventricle Ventricle Inhibited V Ventricle D Dual A V Figure 2 Pacemaker modes 3 Figure 3 shows a typical example of a pacemaker pulse generator hermitically sealed and with leads implanted in the heart Left Atrium Left ventricle Figure 3 Pacemaker Pulse Generator 6 Int l Conf Embedded Systems and Applications ESA 12 The original hardware sensing circuit was reported to have high noise immunity with the ability to sense down to 37uV 6 This was achieved by providing a variable gain and reference level for the circuit under the control of a microprocessor The pacing circuit is able to provide a nearly continuous range of selectable voltage amplitudes ranging from 1 2 to 7 volts and the pulse width is only limited by the maximum frequency of the clock The original hardware lead impedance measurement circuit has the ability to provide an accurate impedance measurement with less than 1 error The focus of this paper is on developing a complementary software framework In particular Section 2 describes a simple and extensi
145. ary for the EDF based scheduling of real time tasks e A hard real time task is never allowed to miss a deadline because that can lead to complete fail ure of the system A hard real time task can be safety critical and this means that if a deadline is missed it can lead to catastrophically conse quences which can harm persons or the environ ment e A soft real time task is a task when a deadline is allowed to be missed while there is no complete failure of the system it can lead to decreased performance e Polling Server is a periodic task whose purpose is to service aperiodic requests with a period Ts a computation time C s capacity and scheduled in the same way as periodic tasks e Background Server schedules aperiodic tasks in background when no periodic task is run ning and schedule of periodic tasks is not changed 3 STATE OF THE ART A real time system often has both periodic and ape riodic tasks Lehoczky Sha and Strosnider 1987 in 3 developed the Deferrable Server algorithm which is compatible with the rate monotonic scheduling al gorithm and provides a greatly improved average re sponse time for soft deadline aperiodic tasks over polling or background service algorithms while still guaranteeing the deadlines of periodic tasks The scheduling problem for aperiodic tasks is very dif ferent from the scheduling problem for periodic tasks Scheduling algorithms for aperiodic tasks must be able to guarantee
146. as heartbeats and this causes the pacemaker to generate a pacing signal with an amplitude of 3 5 volts However with an amplitude of 69 mV all signals are sensed as shown in the DCM output shown in Figure 6 The data displayed on the DCM in Figure 6 is sent from the DCM agent running on the pacemaker board to the DCM client running on the PC via the serial link In practice this serial link would be replaced with a wireless link This allows a doctor to see what the pacemaker is sensing within the patient fy Figerrever Devens Cortege Monnari Paceeakoor 1 Patentiniornaten Pacemaker Conkguraton Flea Tere Ota Wientrecth 0 F 142 FIE Aps AP gn VERak VP le Real Time Events 0 LF ra soe AF OR Woon Von Leggi Parcemiadoor Dati Figure 6 DCM real time ECG output The overall system architecture consists of two major components the Device Controller Monitor and the Pulse Generator The Device Controller Monitor DCM has a graphical user interface with three tabs Patient Information to specify a patient and retrieve historical data from a database the current pacemaker configuration is automatically populated in the second tab when a patient s data is loaded If the patient is new then system default values are loaded The Pacemaker Configuration tab allows a cardiologist to select a mode from those shown in Figure 2 Depending on the mode a set of configuration parameters can be specified and sent to the pace
147. asa gov science news science at nasa 20 11 14nov_lunarionosphere 11 T J Stubbs D A Glenar W M Farrell R R Vondrak M R Collier J S Halekas G T Delory On the role of dust in the lunar ionosphere Planetary and Space Science vol 59 pp 1659 1664 Oct 2011 12 2004 The James Madison University website Online Available http maic jmu edu sic gps satellite htm 13 2011 The CubeSat Kit website Pumpkin Inc Online Available http www cubesatkit com index html Available Int l Conf Embedded Systems and Applications ESA 12 Remote Controlled Terrestrial Robotic Module Alessandro Brawerman Mauricio Perretto Felipe Augusto Przysiada Computer Engineering Department University of Positivo Curitiba Parana Brazil Abstract This paper presents the development of a low cost terrestrial robotic module small dimensions and great autonomy which allows the user to control it over long distance The module may be used for investigation in critical environments of difficult access Communication between the module and the operator is accomplished through an 802 11g network This communication occurs over a secure protocol that allows encryption of information so that attacks by malicious people on the communication protocol are hampered A camera captures and transmits images to the operator who can then recognize the surround environment and remote control the module environment inspection Keywo
148. ased localization module Figure 6 Localization with scene recognition 5 Experimental results 5 1 Ceiling view based localization We use the extended Kalman filter EKF for localization and map building EKF has been most popularly used for SLAM work for its simplicity and cost effective performance 4 5 6 We have completed the EKF framework for SLAM with line features Since we extract robust line Int l Conf Embedded Systems and Applications ESA 12 features from the ceiling and the features are not too rare or crowded measurement is very steady and has advantages for data association The EKF should work well under this situation The robot travels around the room in our test bed The embedded module takes a picture of the ceiling at every step The robot performs the localization and map building by EKF based SLAM in real time as shown in Figure 7 We verified the SLAM result and the actual data The ground truth is measured by 3D tracker It takes 49 8sec to complete to SLAM and localization error mean error is 9 6cm in 5m by 5m Figure 8 shows the result of SLAM in the hall Mi p Mapping Stai p Area Control Mapping een cas start E C Localization Large Remote STOP Tr Window Ploaia mE SSS ooe ety lex Y TETA START Odo 3 78 2 42 100 Debug win stop Slam 3 71 2 43 2934 sree mace ae Ty aT MEAN
149. ata errors cryptogram with the fault and a correct cryptogram is also used Previous studies on fault attacks can be roughly classified into 1 attacks against the key generation section key attacks and 2 attacks against the cryptographic operation section intermediate value attacks This study investigates the key attacks During key attacks when a fault is generated in the key generation section an intermediate key at the 9th round 9 R can be obtained using a pair of cryptograms with the fault and a correct cryptogram In this study the case where a fault mixed in an intermediate key at 9 R is propagated to an intermediate key at 10 R is examined Subsequently the difference between a cryptogram with the fault and a correct cryptogram is obtained By using the obtained difference and inverse operation of the cryptographic operation section before the AddRoundKey process at 9 R the key is specified Int l Conf Embedded Systems and Applications ESA 12 The procedure of the key attacks is shown as follows Stepl The position where a fault has been generated is already known 9 R and two pairs of a cryptogram with the fault mixed in the position of an intermediate key at 9 R and a correct cryptogram are prepared The values of the mixed in faults e OxO1 OxFF are assumed to be different between the two pairs Step2 Based on the already known position in the intermediate key at 9 R where the fault has been generated
150. ated signal conditioning hardware as shown in Figure 12 Next the PIC16F882 is interfaced with the CS5460A A crystal oscillator is used for the CS5460A while the PIC16F882 uses its internal oscillator This allows the PICI6F882 to also provide the serial signal needed to establish SPI communications The CS5460A serial timing diagram is included as Figure 13 E mi 10a O71 pF Rater e pul Praia Sefer to h eeg Figure 12 Cirrus Logic CS5460A Typical Connection Diagram SDI Write Timing Not to Scale gt J J J IL Tsili LI I1 TI jwlwlejf J I I J rear er AMNA Aman fom mM rn atatatatateatatetatea rth nny AVAUAURU RU AU RU AU AUAUAVAUAEAe UU U UU U pu Ul i p gp j when reading each byts of data trom SOO SDO Read Timing Not to Scale Figure 13 CS5460A Serial Read and Write Timing Diagram SPI With the ability to send and receive serial data to and from the CS5460A the next design step is to access the various data registers and to format the data that is transmitted across the network The registers of the CS5460A store hexadecimal data as scaled values ranging from O to 1 and from 1 to 1 The PICI6F882 processes this data by multiplying the scaled value by the full scale value This data is then placed into temporary variables in order to be transmitted across the XBee network 76 Before data can be transmitted via XBee the USART module of the PIC16F882 needs to be
151. ation for development to the level of outline and is helpful for performing a collaborative team project From our case study our model was adapted well for menu driven GUI application on RTOS Using this approach we could build a large application rapidly with minor modification of sub applications In the future we will improve this model and adapt it to another large application on RTOS that consistently monitors embedded mobile devices connected by adhoc networks 7 References 1 H Tung C Chang C Lu and W C Chu From Applications to Models and to Embedded System Code A 63 Modeling Approach in Action 10th International Conference on Quality Software QSIC pp 488 494 2010 2 M A Tsoukarellas V C Gerogiannis and K D Econolmides Systematically Testing a Real Time Operating System IEEE Micro pp 50 60 1995 3 J C Maeng J Kim and M Ryu An RTOS API Translator for Model driven Embedded Software Development 12th IEEE International Conference on Embedded and Real Time Computing RTCSA 06 2006 4 S Seo Sang Lee S Hwang and J W Jeon Analysis of Task Switching Time of ECU Embedded System ported to OSEK RTOS SICE ICASE International Joint Conference Oct 18 2 1 2006 5 C Bunse H Gross and C Peper Applying a Model based Approach for Embedded System Development 33rd EUROMICRO Conference on Software Engineering and Advanced Applications SEAA 2007
152. ations Interesting results based on this table is that between all configurations the minimum PDP is reached in configuration 5 L1 32 and L2 64KB MIPS per power metric is the inverse of PDP formulation where delay refers to average execution time per instruction Configurations with higher MIPS per power are good choices for embedded systems Results of this parameter can be seen in figure 2 f Based on this figure and PDP results configurations to 5 deliver better MIPS per power and the best configuration in different explored feature sizes 1s configuration 5 Int l Conf Embedded Systems and Applications ESA 12 87 18 Te 16 14 JIT 4 12 9 P 10 E x E 32 go 8 5 6 4 27 2 0 T T T T T T T T T T 22 1 2 3 4 5 6 7 8 9 10 11 12 1 Z a 4 5 G T 8 a 10 11 12 cfg ctg Fig 2 a leakage power analysis Fig 2 b dynamic power analysis 54 d 41 J2 4 a0 40 3 2p a 26 ag 24 22 20 38 18 16 37 1 2 a 4 5 6 T 8 9 10 11 12 1 2 3 4 6 7 8 9 10 11 12 efg cfg Fig 2 c Total power analysis Fig 2 d MIPS analysis 47 215 210 46 205 45 ri 44 5 195 g 190 a 4 3 2 185 42 180 175 4 1 170 T T T T T T T T T T T E 4 ee aL 1 2 3 4 6 6 7 8 9 0 n 42 cfg ctg Fig 2 e PDP analysis Fig 2 f MIPS per power analysis 72 67 S amp A 62 57 52 T
153. ator of AES CMAC calculation and AesCmacApp java is a user program which invokes the acceleration method described in AesCmac java These two input files can be compiled immediately and are executable on JVM Five files on the right side are translation outputs among which AesCmacApp java is not changed Therefore AesCmac java is to be translated to four files We show details of them in the following subsections 5 1 Inputs of translation Fig 7 shows AesCmacApp java defines AesCmacApp class This is a user program which invokes the acceleration method defined in AesCmac java In the main method the set get methods are called to set keys and data and to get calculation results before after the processing This code is not a target of translation AES CMAC Application E class AesCmacApp public static void main String args set inputs AesCmac setKey0 0x16157e2b AesCmac setKeyl Oxa6d2ae28 AesCmac setKey2 0x8815f7Vab AesCmac setInput0 OQxe2becl16b proc AES CMAC Accelerator AesCmac process j get outputs System out printf 0xS08x n AesCmac getMac0 System out printf 0xS08x n AesCmac getMacl System out printf 0xS08x n AesCmac getMac2 Fig 7 AesCmacApp java 133 Fig 8 shows original AesCmac java defines AesCmac class This is an accelerator of AES CMAC calculation The algorithm of AES CMAC in this file is described with some cares for synthesiza
154. becomes more severe when the ASIC operates under continuous conversion mode because the data acquisition times must be accurately respected for the sake of ensuring Int l Conf Embedded Systems and Applications ESA 12 correct signal sampling Android operating system cannot guarantee such conditions as shown in Figure 6 E D 7 08 em Sistema de Integraci n de Monitoreo M dico e Interoperabilidad para Teleasistencia Create by Eng Jaiber Yepes Figure 5 Distorted sinusoidal signal For testing a GPIO pin toggles when the OS makes a sample request to the data acquisition system As it can be seen in Figure 6 the samples are requested at different time periods This phenomenon generates a distorted version of the acquired signal Figure 6 Communication task is not periodically handled by the OS 5 2 Solution Strategy In order to meet real time constraints imposed by the target application and so solving synchronization problems mentioned above it is necessary to find a mechanism to efficiently handle the sampling times required by the signal acquisition system without leaving aside the many advantages which the Android platform has As mentioned in the section on related work the alternatives currently available to use Android in real time applications do not provide an optimal solution Because of this the paper presents an approach that seeks to separate the real time processing demand of the rest of the
155. bility The private static fields correspond to setting registers and set get methods correspond to device driver APIs The process method will be translated to high level synthesizable C source codes AES CMAC Accelerator x7 public final class AesCmac input fields private static int key0 private static int input0 output fields private static int mac0 set methods public static void setKey0 int key key0 key get methods public static int getMac0 return mac0 synthesizable method public static void process int k new int 4 INE I3 k 0 key0 aes128 k mLast m mac3 m 3 Fig 8 AesCmac java Original 5 2 Outputs of translation Fig 9 shows translated AesCmac java defines AesCmac class This is a wrapper of device drivers The original set get methods are translated to Java Native Interface JNI connected to device driver APIs This file does not include substantial definitions of methods and private static fields 134 Int l Conf Embedded Systems and Applications ESA 12 AES CMAC Accelerator AES CMAC Register Interface x Bi public final class AesCmac user defined base address input output fields removed define BASE 32 hffff0000 native set get methods module AesCmacRegIF public static native void setKey0 int key PCLK PADDR PWRITE PREADY req key0 input0 mac0
156. ble Automatic Reconfig urations of Real Time OS Tasks book chap ter in Handbook of Research on Industrial In formatics and Manufacturing Intelligence Inno vations and Solutions Ed Mohammad Ayoub Khan amp ABDUL QUAIYUM ANSARI ISBN13 9781466602946 2012 Published by IGI Global Knowledge USA Y Al Safi and V Vyatkin An ontology based reconfiguration agent for intelligent mechatronic systems in Proc 4th Int Conf Hol Multi Agent Syst Manuf Regensburg Germany 2007 vol 4659 pp 114 126 R West and K Schwan Dynamic window constrained scheduling for multimedia applica tions in Proc IEEE 6th Int Conf Multi Com put Syst Jun 1999 P Balbastre I Ripoll and A Crespo Schedu lability analysis of window constrained execution time tasks for real time control in Proc 14th Euromicro Conf Real Time Syst 2002 T Tia J W S Liu J Sun ad R Ha A linear time optimal acceptance test for scheduling of hard real time tasks Technical report Depart ment of Computer Science University of illinois at Urbana Champaign Urbana Champaign E 1994 Mani B Srivastava Miodrag Potkonjak Inki Hong On Line Scheduling of Hard Real Time Tasks on Variable Voltage Processor Interna tional Conference on Computer Aided Design ICCAD 98 San Jose California United States of America 1998 167 168 Int l Conf Embedded Systems and Applications ESA 12
157. ble software framework that can be used to design and analyze academic dual chamber pacemakers Section 3 provides a simple analysis verification and plans for future work and Section 4 concludes the paper 2 Software Framework The main functions of an academic pacemaker can be divided into two categories pace generation which must run in disconnected mode on the pacemaker and device control and management which are components used to monitor and program the pacemaker The majority of the code for device control and management the device controller monitor DCM runs on the PC and communicates with the pacemaker DCM agent via a serial link The controller passes pacemaker parameters from the PC to the pacemaker These parameters are also logged in a database as they are changed In this way the controller client runs on the PC and the agent server runs on the pacemaker In contract data on electrical pulses that are sensed or pulsed on the pacemaker may need to be monitored Although an external monitor such as an _ electrocardiogram ECG could be used to monitor the heart the monitor here can be used to observe the pacemaker activity directly This information can also be logged by the DCM To model an electrocardiogram a data acquisition DAQ card can also be used In our framework signals sensed by the pacemaker are generated by the DAQ and on the flip side pace signals generated by the pacemaker ranging from 1 2 t
158. bus as described previously For software module power consumption has been estimated based on data for voltage supply core frequency and junction temperature estimate Regarding the hardware module the power consumption can be analyzed in several ways As described by 6 at lower abstraction levels like transistors gates among others the simulations are the most common approach used for it It is possible estimate the power consumption from an accurately specification of the logic cells memory banks clock sources and IOs which can be obtained by estimation or synthesis from hardware description language Therefore this paper considers the description of the amount of resources to measure the power consumption of the hardware module and the total of energy spent by the architecture will be the sum of the energy dedicated to each processor element based on hardware or software 3 Case Study This case study uses the SAD Sum of Absolute Difference algorithm which is a computational procedure widely applied to encoding digital images in order to determine the motion estimation ME vector of a given picture Despite being a relatively simple algorithm it demands high processing load due to be applied to all frames As illustrated by Figure 2 the inner loop of search algorithm contains a SAD operation computed in parallel The operation consists of a subtraction an absolute value and the addition of the resulting value with the p
159. bypassing multiplier designs to reduce dynamic power and explains the floating point problem in the original bypassing multiplier design B Array Multiplier with Row Bypassing Ohban et al 3 proposed an array multiplier with row bypassing Figure 3 illustrates their 4x4 bit array structure in which each modified full adder requires three tri state buffers and two 2 to 1 multiplexers The row addition can be bypassed when the bit of multiplier x is 0 1 lt j lt n 1 it causes all partial products y x 0 0 lt i lt n 1 thus the carry save adders Int l Conf Embedded Systems and Applications ESA 12 can be disabled in the j th row and using 2 to 1 multiplexers transmit the outputs from the j 1 th row to the inputs of carry save adders in the j 1 th row For example if x3 is 0 the carry save adders in the third row do not need to be active and the outputs from the second row can be transmitted to the carry save adders in the fourth row This design requires extra circuits shown in the area of dotted line in Fig 3 to ensure the correct result of multiplication because the rightmost full adder in the third row is disabled Tri state buffer y3Xo Y2Xo0 Y3X1 Y2X1 0 Y1X1 0 y Xo YoxXo Yox1 9 V Gh y YAY VAV ic 07 X 1 0 7 0 P7 Pe P5 Pa P3 P2 P Po Figure 3 A 4x4 array multiplier with row bypassing 3
160. bytes information of pressed keys Cyclic Redundancy Check CRC and the stop sequence Telegram is sent periodically to MCU MCU receives that telegram decodes the data bytes and performs action accordingly One OCU can communicate to several MCU if all MCUs have the same address and the frequency band 433MHz 960MHz and 360MHz are the frequency bands supported by the RFID modules Both OCU and MCU contain a Liquid Crystal Display LCD attached Fig 7 which shows the current status of the OCU and MCU respectively There is an emergency stop switch attached to OCU whenever this switch is pressed MCU should stop instantly Master Controller Master Controller m SC tasks Non SC tasks Figure 7 OCU and MCU system architecture The system contains some Safety Critical SC and non SC tasks associated to this system Degree of the task replication depends upon the safety level of the SC task and is defined by Safety Integrity Level SIL Table 1 Safety integrity levels SIL Criticality System failure Probability of dangerous failure per hour 1078 1077 Server failure 1077 1076 failure 2 1 Safety relevant Critical Non critical Major failure 1076 107 Minor failure No dependability requirements Tasks responsible to display information on LCD are all non SC tasks Tasks that scan the push buttons are SC tasks especially the task associated to monitor emergency stop button
161. c Output Input Proc Output Fig 1 Granularity of information processing In case of Von Neumann Architecture especially RISC architecture input output is represented as load store instruction and processing corresponds to other operation The amount of contribution of hardware to processing depends on processor architecture Fig 2 For example in case of ASIP Application Specific Instruction set Processor the weight of the hardware becomes large 132 Programs Pentium Programs Xtensa General Purpose ARM i ASIP MeP Processor i etc Hardware etc Hardware Fig 2 A case of Von Neumann Architecture Therefore we understand that the high level synthesized hardware is the special case of application specific processor Many instructions described in source code are assembled and integrated into custom integrated circuit Fig 3 LD OP ST LD OP ST LD OP ST lace eeh ee ates eee See Hg ee ee ee RE ppp s High Level Synthesized Hardware Fig 3 High level synthesized hardware However the load store operations have not been well cared about in high level synthesis hence we have conceived a new method that covers this weak point with I O library that encapsulates handshakes between hardware and software 3 2 Application suitable for high level synthesis The best suitable application of high level synthesis is the complex finite state machine FSM whi
162. c tasks hp 0 2 LCM mazxz ax1 where LCM is the well known Least Common Multiple of all task periods and apx is the earliest activation time of each task Tk 7 We use their technique for acceptance test The extension of the proposed algorithm should be straightforward when this assumption does not hold and its running time is O n m 11 So Intu itively we expect that our algorithm performs better than the Buttazo and Stankovic one We show the results of our optimal proposed algorithm by means of experimental result s evaluation 4 EXPERIMENTAL RESULTS In order to evaluate our optimal OEDF algorithm we consider the following experiments 4 1 Simulations To quantify the benefits of the proposed approach OEDF algorithm over the predictive system shut down PSS approach over the MIN algorithm the OPASTS algorithm and over the HPASTS algorithm We performed a number of simulations to compare the response time and the utilization processor under the four strategies The PSS technique assumes the complete knowledge of the idle periods while the MIN algorithm assumes the complete knowledge of the ar rivals of sporadic tasks For more details about the both four techniques you can see 12 Processor Utilization Figure 1 Processor Utilization Int l Conf Embedded Systems and Applications ESA 12 The OEDF scheduling result is shown in figure 1 4 2 Discussion In experimen
163. caling enabled Fig 3a shows the sEMG signal acquired by the proposed acquisition system using DE 2 1 electrodes Fig3b shows the filtered sEMG signal using a wavelet transform Daubechies 44 filter Fig 4a and 4b shows the raw EMG and wavelet transform based Daubechies 44 filtered sEMG signals at 5 levels of decomposition acquired by the proposed acquisition system using DE 3 1 electrodes 145 3a Unfiltered sEMG Signal aa i Mh N 0 5 j It BENENNEN i anim ea Ig DRINA N A A 0 AN Vil al IM la He jel hal ha Ml IM Ae dall il AA vk p ji Mh ee A i MIRT T 0 05 1 15 2 25 3 3 5 4 4 5 5 4 3b Filtered sEMG Signal with Wavlet Daubechies 44 Filter x10 E 1 a 0 5 i 3 5 4 4 5 5 T 1 1 5 2 2 5 3 Time 30 Secs x10 Fig 3 3a Unfiltered sEMG Signal from the Proposed Acquisition System Using DE 2 1 Electrodes 3b Filtered SEMG signal with Wavelet Daubechies 44 Filter 4a Unfiltered sEMG Signal 1 TTI 0 Beet ERUEN i Ea os H l f i j j j l all M i i Hh LN li il i ih l i i i LLL d l Wika i i il Ml J 0 0 5 1 1 5 2 2 5 3 3 5 Z x 10 F 4b Filtered sEMG Signal with Wavelet Doubech
164. can be estimated given a desired distance tolerance 1 t Cerrar dy T c i In this estimation o 7 is the Alan Deviation c is the speed of light in a vacuum derror is the allowable distance error and t is the amount of time that can elapse before a clock update needs to be sent to the satellite from the control segment before the distance error grows past its tolerance 4 Results To determine the minimum number of satellites for the proposed constellation using the Rider method a program was made to test various orbital altitudes The graph below shows the results of the minimum number of satellites for coverage on the moon at these altitudes These results show 2 85 2 807 2 75 2 707 2 657 2 607 Min Number of Satellites 2 557 2 507 2 457 2 40 T T j T j T j T T T T T T T T 10000 20000 30000 40000 50000 60000 70000 80000 90000 Altitude km Fig 1 Minimum Number of Satellites For Moon Coverage Using Rider s Method of Inclined Circular Orbits vs Orbital Altitude that as the orbital altitude of the satellites is increased the minimum number of satellites needed to provide coverage exponentially decays Once this was determined the desired altitude was calculated to be 3 34x10 km using Kepler s third law This altitude was determined by choosing an orbital period equal to that of one fourth of a moon day which equals 6 8305 Earth days Again it was desired to have the
165. cations data network Physical Layer 2002 12 PM0056 STM32F107 Cortex M3 manual STMicroelectronics 1998 2012 programming 13 RM0008 STM32F107 Reference manual for advanced ARM based 32 bit MCUs STMicroelectronics 1998 2012 14 Florian Hartwich Armin Bassemir Robert Bosch GmbH The Configuration of the CAN Bit Timing 6th International CAN Conference 1999 Turin Italy 15 ISO11783 5 Tractors and machinery for agriculture and forestry Serial control and communications data network Network management 2002 45 46 Int l Conf Embedded Systems and Applications ESA 12 Design of a Humanized Vending Machine Framework A LiXin Zhao B Ping Li Automation College Beijing Union University Beijing China Abstract developed countries vending machines are playing very important role in everyday life Usually people operate the vending machines following the given instructions mechanically which make the shopping experience less humanized In this paper current development situation of vending machine was presented Limitations in functionality were outlined A humanized vending machine design methodology was proposed Meanwhile a framework for design based on uC OS H was illustrated in detail including storage of information the functionality of key tasks the synchronization and mutex among key tasks communication among key tasks The key checkout logic was presented in detail To put
166. ce For the development of robots in the last case it is necessary to know the environment in which this will be used Actuators Sensors and define a number of factors like size length methods of communication between robot and operator robotic actuators present in the project 5 The project presented in this paper is to develop a robot with long distance control for preliminary investigation of critical environment for humans 2 Development This project aims to develop a robotic system with the following characteristics low cost long range small sized and controlled by humans to perform the inspection tasks in critical environments The diagram of Figure 1 shows the block interconnection of the developed system Note that a control block is responsible for receiving information from the sensors and sending them to the actuators Besides a mini computer type E box is responsible for ensuring communication between the control block and the operator and transmitting the images obtained by the camera to the operator Figure 2 depicts the robotic module prototype N Oper Control ator Figure 1 Block diagram of the robotic system Following it will be described each of the blocks developed and communication between them 2 1 Sensors As an operator controls the developed robotic module the sensing system contains only a few elements to protect the module from user commands that may provide risk of damage
167. ce mentioned before as HCP and Lowest Cache Energy LCE LCEs are for cache size that creates the lowest energy consumption for each application HCP and LCE are shown in fig 1 b Results of this figure show that for all applications size of LCE is smaller than HCP so LCE and HCP are the left and right margins of the cache size range respectively and they introduce a range for Ll and L2 considering both performance and energy consumption Based on figure 1 L1 L2 range is from minimum L1 L2 size for LEC column to maximum L1 L2 size for HCP column Table 1 Important parameters we have applied for running CACTI 18 Cache size Cache line size p Associatively Read write ports Pae oo ooo Exclusive write ports wwe e e o o Change tag Temperature K K 300 400 300 400 He cell transistor type in ITRS HP Global data array RAM cell transistor type in tag ITRS HP Global array In this way and based on fig 1 L1 ranges are from 8KB to 128KB and L2 ranges from 16KB to 128KB These ranges specify an important point any size for L1 and L2 out of this range is not recommended because the right side of these ranges leads to the maximum performance and the left side have the minimum power consumption for caches in selected embedded applications For each application in the LCE point highest performance penalty minimum performance in lowest energy will be achieved and HCP point leads to the highes
168. ch has many states but its I Os can be presented in simple graphic form Fig 4 Request gt amp Inputs Acknowledge amp Outputs Fig 4 Application suitable for high level synthesis Int l Conf Embedded Systems and Applications ESA 12 The FSM starts state transition when a request arrives and stops after acknowledge output We focused on the request acknowledge and inputs outputs to encapsulate them 3 3 Implementations of I Os There are many variations of request acknowledge and input output For example an acknowledge is implemented as a polling function or an interrupt signal and its handler These variations should be encapsulated to library and should be provided to co design users as design options 4 Co design environment by Java Now we suggest the co design environment composed of four translators and libraries Fig 5 This co design environment accepts synthesizable Java source codes that can be compiled by Java compiler immediately and are executable on Java Virtual Machine JVM as a pure Java application Java Application Synthesizable Java Application ee a Source Code Source Code Pe ae Our Product Java to Java Java to C Java to Verilog Java to C Translator Translator Translator Translator Se ee JNI Wrapper Device Driver ee E Java Java Complete High Level Compiler Compiler P Synthesizer oe Byte Code Byte Code Native Binary Java Virtual Machin
169. ch predominantly use the priority encoder function In this context the design of a new 8 bit 8 inputs and 8 outputs CMOS priority encoder module suitable for embedded system applications is presented in this work In comparison with the latest 8 bit priority encoder based on existing literature 14 it is found from SPICE simulations that the proposed 8 bit dynamic CMOS priority encoder reduces total power dissipation by 4 7 and requires 27 6 less transistors for physical realization However in terms of propagation delay the proposed design is neck and neck with the 8 bit priority encoder constructed on the basis of Huang and Chang s approach 14 I INTRODUCTION Data bus 1 and comparators 2 3 fixed and floating point arithmetic units 4 incrementer decrementer circuits 5 6 interconnection network routers 7 8 sequential address encoder of content addressable memories 9 10 are important sub systems located on chip or off chip which predominantly utilize the priority encoder function In general priority encoding can be either hardware based or software based With regard to the hardware implementation a generic priority encoder would feature n inputs and n outputs where n specifies the number of data inputs outputs which usually range from 16 to 64 bits An n bit priority encoder is basically a priority resolver that accepts request activations on its input pins and based on the priority assignment faci
170. cient wear leveling for large scale flash memory storage systems Proceedings of the ACM SAC 2007 Int l Conf Embedded Systems and Applications ESA 12 15 Du Y Cai M Dong J Adaptive garbage collection mechanism for N log block flash memory storage systems Proceedings of the ICAT 2006 16 http www openssd project org wiki The_OpenSSD_Project 17 Yangsup Lee Sanghyuk Jung and Yong Ho Song FRA A flash aware redundancy array of flash storage de vices Proceedings of the CODES ISSS 2009 18 Yuan Hao Chang Jen Wei Hsieh and Tei Wei Kuo Endurance enhancement of flash memory storage systems An efficient static wear leveling design Proceedings of the IEEE ACM International Conference on DAC 2007 19 Li Pin Chang and Chun Da Du Design and implemen tation of an efficient wear leveling algorithm for solid state disk microcontrollers ACM Transactions on Design Auto mation of Electronic Systems vol 15 no 1 December 2009 20 Samsung flash memory Spec K9LCGO8UI1A Datasheet 21 Technical Committee T13 AT Attachment Information Technology ATA ATAPI Command Set 2 ACS 2 T13 2015 D Revision 2 August 3 2009 22 http www iometer org Int l Conf Embedded Systems and Applications ESA 12 29 Fast Prototyping of an Image Encoder using FPGA with USB Interfacing Airs Lin Evan Tsai Gabriel Nunez Gregory Carter Neil Arellano
171. clly merged into VP where subset T1 T2 03 04 and os is considered as old tasks to be executed by this virtual processor In this case subset og o7 is executed by the second newly created virtual processor V PY which is located in idle periods of VP After each addition scenario the proposed intelli gent agent proposes to modify the virtual processors to modify the deadlines of old and new tasks the WCETs and the activation time of some tasks or to remove some soft tasks as following e Solution 1 Moving some arrival tasks to be sched uled in idle times idle times are caused when some tasks complete before its worst case execution time S1 e Solution 2 maximize the d S2 By applying equation 3 that notices Ri d fi we have R d t Cj 165 Or to obtain a feasible system after a reconfiguration scenario the following formula must be enforced R gt 0 By this result we can write dinew t Ci gt 0 where dinew Gee h So d i 0 t C 2 0 gt e Solution 3 minimize the c S3 By applying equation 3 that notices Ri d fi we have i di t C Or to obtain a feasible system after a reconfiguration scenario the following formula must be enforced R gt 0 By this result we can write di t Cinew gt 0 where Cem Ci a Di So di t Ci Bi 2 0 gt di t Ci gt Pi e Solution 4 Enforcing the starting time to come back aj gt GQinew
172. clocks are Joys o Or feys a eee 2 Nominal CAN Bit Time E Sync_ Prop_Seg Seg Phase_Seg1 Phase_Seg2 1 Time Quantum ta Sample Point Figure 7 CAN bit timing Table 1 CAN Bit Timing Parameter Finally make a loop for frequently CAN message received by our GPS sensor within a fixed time period In additionally we also create our device driver and startup STM32 driver and startup configuration After complete all steps we can build and execute our application program completely Figure 8 shows the application program of GPS sensor in IAR Embedded Workbench 44 IAR Embedded Workbench GPS SENSOR Application Program Header files int main unsigned int count version aniani ar ani vl SOSH HHH RHR E TEE 1 unsigned char str1 50 r Developed By MULIMEDIALAB unsigned char str2 50 r ECU GPS SENSOR 1 unsigned char str2 50 r CBNU SOUTH KOREA unsigned char str4 S0 r SERRE REREREEEREE EERE REED I n USART1_Configuration USART1Write u8 str0 sizeof strO USART1Write u8 str1sizeof str1 USART1Write w8 str2 sizeof str2 USART1Write u8 str3 sizeof str3 USART1Write u8 str4 sizeof str4 ecuMain while lsoAgLib iSystem_c canEn Source files Test board Driver amp Startup configuration files int32_t 32_idleTimeSpread IsoAgLib getiSchedulerinstance timeEvent if i32_idieTimeSpread gt 0 tsoAgLib iCanlo_c wai
173. completely lost communication with the robot Table 1 Protocol for communication between Control and Central Module Table 3 presents the results obtained for the internal and external tests tabulating the maximum distance the minimum distance and the average of the thirty tests Int l Conf Embedded Systems and Applications ESA 12 Maximum Minimum Average meters meters meters Table 2 Results distance 3 2 Autonomy The maximum power consumption was calculated as 2 2A thus to power the robot two batteries of 6V 5 2 Ah were employed According to equation 1 the robotic module autonomy when using maximum consumption is two hours and twenty five minutes Aut Load consumption In tests conducted in different environments where the average use was not requiring maximum power the autonomy was extended for up to three hours and thirty minutes using it constantly 3 3 Response time The objective of this test was to assess the response time between the operator module and the robotic module according to the distance between the two elements To evaluate the response time of the robotic module ten measurements were performed at varying distances always indoor Table 4 presents the delay obtained according to the distance meters time ms Table 3 Distance x Response The image transmission has reached up to three frames per second but in most indoor cases the refresh rate was in one frame ev
174. ctim block sorting costs during garbage collection Figure 1 rep resents the controller archi tecture of a NAND flash storage and the location of the 2L list Figure 2 shows the 2LGC map entries First the page map table is an essential data structure of a page mapping FTL The main role of this table is to translate logical page numbers LPNs from a host system into physical page num bers PPNs in NAND flash memories Second the aim of the block map table is to store physical block information whether the block is available or not when the FTL allocates free blocks The block map table is also an essential data Int l Conf Embedded Systems and Applications ESA 12 structure for supporting garbage collection or wear leveling algorithms NAND Storage Controller DRAM Data Buffer Tables 2L List Processor Core DRAM Controller Host Interface Controller FTL G C High speed bus NAND Array NAND Flash NAND Flash NAND Flash NAND Flash Controller Controller SRAM ROM NAND Array Controller Fig 1 Flash storage controller architecture PPN 31 bit Valid Flag a b Fig 2 2LGC map entries a page map entry and b block map entry As shown in Figure 2 a each page map table entry is composed of a 31 bit PPN and a 1 bit page validation mark
175. d we plan also to apply these contributions to other complex reconfigurable systems that we have chosen to not cover in this paper In addition we would like to consider its use in distributed systems REFERENCES 1 M L Dertouzos Control robotics The procedural control of physical processes Information Processing 1974 2 L N L M F Singhoff J Legrand Cheddar a Flexible Real Time Scheduling Framework in ACM SIGAda Ada Letters volume 24 number 4 pages 1 8 Edited by ACM Press ISSN 1094 36 41 2004 3 C Liu and J Layland Scheduling algorithms for multi programming in a hard real time environment in Journal of the ACM 20 1 46 61 1973 4 J Y T Leung and M L Merrill A note on preemptive scheduling of periodic real time tasks Information Processing Letters 11 1980 pp 115 118 5 K Hnninen and T Riutta Optimal Design Mas ters thesis Mlardalens Hgskola Dept of Computer Science and Engineering 2003 l6 STANKOVIC J SPURI M RAMAMRITHAM K BUTTAZZO C Deadline Scheduling for Real Time Systems Kluwer Academic Publishers Norwell USA 1998 Int l Conf Embedded Systems and Applications ESA 12 8 www loria fr nnavet cours DEA 2004 2005 slide2 pdf 9 C Angelov K Sierszecki and N Marian Design models for reusable and reconfigurable state machines in L T Yang et al Eds Proc of Embedded Ubiq uitous Comput pp 152 163 2005 10 M N Rooke
176. d Applications ESA 12 69 SESSION POWER EFFICIENCY AND MANAGEMENT TOOLS FOR ENERGY CONSERVATION Chair s TBA 70 Int l Conf Embedded Systems and Applications ESA 12 Int l Conf Embedded Systems and Applications ESA 12 Optimizing Energy Conservation Using Embedded Microcontrollers B Shaer A Fuchs J B Arango and D A Craig Electrical and Computer Engineering Department University of West Florida Shalimar Florida United States Abstract Energy conservation in homes has become imperative due to rising energy costs increasing energy consumption and a world wide shift in environmental protection concerns Thus there is a growing demand for new technologies that will help to provide energy conservation techniques Automating the control of energy consumption in common household devices provides a starting point for establishing efficient usage Through use of existing technologies consumption Statistics and the appropriate algorithms can be combined with the ability to remotely and independently control individual devices for the purpose of energy conservation The home automation system proposed in this paper aims to provide a method for monitoring and controlling energy consuming devices common to households Keywords home automation conservation microprocessors energy 1 Introduction As the global population continues to increase the resources required to sustain the energy demand are gro
177. data structures The key point is the sender and the receivers understand the protocol they have agreed so to get the correct information from the function call Communications among key tasks are illustrated in Fig 1 The checkout task ZaskCheck will wait until TaskMoney and Taskltem to send message to message queue so to execute checkout logic If the customers input money first then money will be accumulated but ZaskCheck won t respond Only when customers select the items will TaskCheck execute checkout logic Suppose customers select items first then ZaskCheck will execute but only find no money so reset the item queue by calling OSQPostFront to put the item back to the front of the item queue QO rem If customers input more money during shopping process every time ZaskMoney will update the money information by using OSQFlush to clear the money Queue QOmoney then call OSQPost to send the latest information 48 3 3 2 Mutual exclusion among key tasks Because customers can input money at any time in the beginning middle or end of shopping process due to the way of updating the money it will lead to the data inconsistency if the mutex among the tasks were not handled correctly Suppose that the checkout logic is just executed to the point between information accessing and information processing of total money when customer input extra money Since the priority of Zask Money is higher than TaskCheck TaskMoney is executed
178. dating the tasks C G and H by the new value of period equal to 43 and the task set becomes schedulable feasible e Solution 2 Modification of Worst Case Execution Times 3 The agent proceeds now as a third solution to modify the Worst case Execution Times WCET of tasks of Enew and oa To obtain a feasible system the follow ing formula should be satisfied ni J Ci n2 n C a De min T D ae n j 1 min Ti Di 1 n2 n Cit n j De n j 1 main D JUT a a 1 min TD nearny nag Ci o Do n j 1 ant D sm 1 min T D yo C t n1 j 1 Oe _ ci s Do C i n j 1 a D i 1 min T Di Let yj be the following constant y aj Constante 1 yin a 5 y mat min constante i n 1 j 1 TATER D The new WCET of IT tasks is therefore deduced from yy running example The agent should react to propose useful solutions for users in order to re obtain the system s feasibility In our Volvo system the agent computes the constant values y j 0 5 corresponding respectively to the new values of the Worst Case Execution Times WCET Here y 44 and the minimum value of WCET in the Volvo system is equal to 1 so y 44 Minimum WCET 1 43 lt 0 Therefore the agent deduces that modifications of Worst Case Execution Times WCET can not solve the problem 5 CONTRIBUTION 3 OPTI MIZATION OF RESPONSE TIME this section aims to present the principle of response t
179. ded or offline RAID array runs the risk of overwriting the striping and parity NAS data recovery is a time consuming process Time required to recover a NAS RAID depends on the storage hardware factors as storage capacity data transfer speed NAS controller and most important is complexity of failure 5 NAS Data Recovery 5 1 Required hardware and software A computer system with enough free SATA IDE According to NAS drive interface connecting port to attach NAS all hard disk drives A CD DVD ROM Drive Enough free storage space and Internet connectivity If NAS have SCSI drive then arrange a SCSI adapter for installation of NAS drives Get Ubuntu Desktop 12 04 LTS from Ubuntu website or the Ubuntu shop Complete Installation of the Ubuntu 12 04 LTS and Installation must be a complete and stable with mdadm gparted and xxdiff applications For installation instructions see the Graphical Install page on the Ubuntu community documentation site mdadm is a command line RAID array utility that create manage and monitor MD multiple devices devices mdadm can provide information about RAID arrays and assemble a pre existing damage array Before using it read its manual and be careful on its use Remember that it can destroy easier than it can repair mdadm has 7 major modes of operation mdadm Assemble is one of them that can recreates a faulty array by checks that the components do form a bon
180. degrees Normal 30 0 10 800 degrees The MR BEAS was designed implemented and analyzed for senior living that alerts emergency responders in regardless of ambient lighting conditions This system was evaluated under different ambient lighting conditions The subject s movements and accurately identified emergency situations automatically Unlike traditional motion frames of depth data for performing the emergency alert This results in significant reduction of hardware complexity and predictable matching algorithm accurately analyzes the skeletal data derived from the depth map A low end will be capable of accommodating MR BEAS without heavy video processing that required in prior arts In addition MR and intelligent system The predictable matching algorithm is incapable of monitoring dual subjects simultaneously but can Furthermore MR BEAS is expandable to utilize voice recognition technology by integrating to the microphone array This algorithm can incorporate more artificial intelligence to track and identify candid emergency situations without the position degrees ml o e 4 Conclusions and Future Work case of an illness or discomfort based on motion recognition implemented predictable matching algorithm sensed the recognition systems the MR BEAS system requires only two resources to achieve the low cost objective The proposed computer with 2 GB RAM on a 2 66 GHz or faster processor BEAS offers a platform for extending this t
181. destructed by calling the thread_exit function when it is running If a thread terminates it must call thrad_terminate SELF or thread chain to be in the suspended state The thread _terminate SELF function simply terminates a thread whereas the thread_chain function is a method to designate the next thread to be activated when a thread terminates The thread _wait function stops the thread control temporarily before the thread _resume function is called The thread_resume function starts the program control from the exact point when it is stopped but the thread _activate function starts the program control from the beginning no matter where the thread terminates The thread sleep function lets the thread stop its program control during desired period of time Developing an application in AVOS is very simple like other RTOS 8 9 An AVOS application needs os h header file and os init and os start functions in the main function The os_start function drives the entire operating system by launching threads All functions that need memory allocation such as thread_create and alarm _create must be called before the os_start function An example of typical AVOS application programming is shown below in a text box form Here two threads and one alarm are executed When the os start calls two threads are automatically activated due to AUTO START option If NORMAL START option is used they will be activated when thr
182. e ibi e activate o i f i terminate E3 shutdown T g e gt set event touch callback alarm 1 activate callback alarm2 activate K activate gt activate alarm4 setevent alarm5 Fig 8 An experimented model of sub applications Int l Conf Embedded Systems and Applications ESA 12 Fig 9 shows the experimented application which consists of five sub applications Fig 9 a is the result of the main front page sub application with icons and Figs 9 b c d e are the result of the corresponding sub applications executed by clicking the icons Whenever each sub application terminates the program control goes back to the main front page sub application d Fig 9 Result from running the example large application the sub applications a b c d and e are from A through As respectively 6 Conclusion This paper presents a model based approach for developing a large application on RTOS Our proposed model treats the large application as a sum of divisible application objects referred to as sub applications connects the divided sub applications with a derived common interface The sub applications are represented by relationship between threads and the interface functions It is quite a simple form but an elegant solution by using the divide and conquer approach Our two step model is enough to describe the large embedded applic
183. e The reconfigurability of hardware provided by an FPGA allows the engineer to be able to update the firmware to re accommodate and process different workloads to maximize the usability flexibility and lifetime of the embedded system compared to regular microcontrollers The future work is to currently optimize the JPEG encoder to reduce the color space size which will further lower bandwidth and FPGA resource usage Once that is completed MJPEG will be the next step for incorporating the off loading of video streams from the client computer 7 References 1 J P Adigwu Dr H Boussalis Semantic Information System Applicaitons in K 12 Education The Journal of Computing Sciences in Colleges Vol 26 Num 4 April 2011 2 RFC 2435 RTP Payload Format for JPEG compressed Video URL http tools ietf org html rfc2435 3 JPEG Homepage URL http www jpeg org jpeg index html 4 Connecting Customized IP to the MicroBlaze Soft Processor URL http www xilinx com support documentation application_notes x app529 pdf 5 Xilinx University Program XUPV5 LX110T Development Platform URL http www xilinx com products boards and kits X UPV5 LX110T htm http www xilinx com univ xupv5 1x110t htm 6 USB org Documents USB 2 0 Specification URL http www usb org developers docs usb_20_101111 zip 7 JPEG Encoder Verilog URL http opencores org project jpegencode 8 Cy
184. e Verilog Verilog Register I F FSM CPU amp RAM amp Bus Model RTL Simulator Fig 5 Co design flow chart Synthesizable Java source codes are translated to four parts JNI wrapper device driver register interface described in Verilog and high level synthesizable C source codes Both device driver and register interface have physical base address information and register interface implements a concretized bus protocol such as APB Advanced Peripheral Bus 4 High level synthesizable C source codes should be synthesized to structural Verilog description with external tools 5 Application to AES CMAC Now we show an example application of our co design method that calculates the AES CMAC 5 This example Int l Conf Embedded Systems and Applications ESA 12 presents the whole automatic translation path from Java source codes to hardware AesCmacApp java Java Application AesCmacApp java Java Apprication Method Invocation Method Invocation AesCmac java JNI Wrapper Native Method Invocation Device Driver AesCmacDrv c Synthesizable AesCmac java Java Register Access pee aoe Register I F AesCmacReglF v implements APB Protocol Wires between Modules High Level N AesCmacProc c Synthesized FSM Fig 6 Translation overview Fig 6 shows the translation overview of our co design environment AesCmac java on the left side is an acceler
185. e After the ceiling grouping straight lines should be extracted from the boundaries of the ceiling by the following procedure 1 Pick a boundary point at the image edge and save the consecutive points along the boundary of the ceiling 2 Find the farthest point on the boundary from the Figure 5 Result of ceiling segmentation virtual line between two end points of the boundary 3 If the distance between the point and the virtual line is 4 Front view based localization over the threshold the boundary is divided into two We adopt the scene recognition algorithm 9 to know boundaries at the point where robot is roughly The proposed approach hierarchically combines the maximization of the inter cluster score to detect 4 If a boundary segment is too short then it is discarded outliers that do not satisfy angular constraints and the detection of the remaining false matches by scale constraints 5 Repeat 1 4 until no division happens and draw a imposed by SIFT descriptors The proposed approach was line between two end points of each boundary segment used for global localization which is the task of finding an image corresponding to a query image among data images Figure 5 shows the result of the ceiling segmentation in because it is robust to initial false matches and we can detect our test bed following the mentioned procedure outliers with low computational complexity Figure 6 shows which floor the robot is using the front view b
186. e if software is not modified Existing difference means that the software is affected by android platform or device hence ACSF finds candidates which are expected to generate error and then generate a report ACSF DemoAndroidProject 1 3 Portability Analysis o Log Information Figure 5 Portability Analysis Int l Conf Embedded Systems and Applications ESA 12 To make a report developer should select two kinds of logs One of them is generated by software which has no errors and finished already software development It is to be the criteria for comparison logs and is named default platform Another one is generated by the others except default platform and it seems to expect making an error ACSF Portability Report Figure 6 Report of the ACSF Information of a report is largely divided by summary information compilation information execution information like Fig 6 The summary information contains of description statistics it help understand structure of the software recognize status of test phase and explains what devices are tested Developers can decide how much effort is needed to fix bugs of this software via the summary information The compilation information explains how many errors are occurred during compile source code and which platforms make problems Moreover it also contains compilation error logs Developers can recogniz
187. e Constellation In this section the high level design for the lunar GPS constellation will be shown Satellite constellations are based upon several factors including the requirements of the system and their orbital parameters The requirements of the system may include whether constant signal visibility with the satel lites are needed Another could be if worldwide coverage is needed which it would almost always be These constraints determine the number of satellites in a constellation and the altitude of their orbits 2 1 General Constellation Design Theory The general requirements for a GPS constellation design are as follows 1 1 For PVT determination at least four satellites must be visible at all times anywhere in the world assuming worldwide access is required 2 The position offsets of the visible satellites need to be such that there pseudoranges with the receiver are as non singular as possible 3 The amount of updates from ground based station needs to be kept to a minimum 4 There needs to be a balance between orbit altitude and transmitter power for the signal 5 There needs to be a certain level of redundancy in the event of failures Considering point 1 one can get away with three satellites if only position determination is necessary However consid ering point 5 as well the number of visible satellites should be about six 1 Point 3 is important since if a trajectory needs to be updated then this re
188. e Dalvik Dalvik is an optimized virtual machine VM for mobile devices and runs classes compiled by a Java language compiler that have been transformed for Android The Dalvik VM relies on the Linux kernel for underlying functionality such as threading and low level memory management Android offers developers the ability to build applications in an easy way Developers are free to take advantage of the device hardware access location information run background Services set alarms add notifications to the status bar and much more At the top Android offers Java programming language approach to development community with total access to framework 4 Description of hardware platform This work has involved three hardware platforms A system based on TI s DM3730 processor for multimedia application called Blizzard a data acquisition system from Texas Instruments called ADS1298 specialized for medical applications and a Freescale 8 bit microcontroller unit MC9S08JM60 9 The block diagram of the complete ECG signals acquisition system is shown in Figure 2 Processor DM3730 Data Acq ADS1298 Figure 2 Hardware block diagram 4 1 Data Acquisition Platform The ADS1298 is a fully integrated analog front end AFE for patient monitoring It belongs to family of integrated circuits manufactured by TI which incorporates all the features that are required in medical applications such as electrocardiogram ECG and electr
189. e any type of data that appear in the form of file NAS appears on the network as a single node over TCP IP NAS follows a client server design and clients can use any of several higher level protocols built on top of TCP IP Sun Network File System NFS and Common Internet File System CIFS are most common application protocols used on NAS Many NAS devices are little more than a storage device or several in a box with some networking electronics However some having additional functionality like email server or stream multimedia content or some having multi talented USB sockets that are used for data transfer or attach more storage space or one can attach a printer and share among all computers on the network Due to these specific advantages to home and business users are making more demands of NAS devices Today NAS are providing about 24 of the total amount of on site disk based backup capacity 3 NAS uses growth is driving increased adoption of NAS storage Despite the importance of the subject there are very few published studies on failure characteristics of NAS drives NAS failure have many factors like hard drive s failure NAS electronics failure computer viruses or user errors and overwriting a file or deleting it that cause data loss Most of the available information of failure comes from the NAS manufacturers and their data are typically based on Statistics from returned unit databases We have been known to be poor p
190. e end user The software also is friendly as well as secure and stable The project accessibility is ensured through the use open source hardware software and standards 4 Implementation Development of the proposed home automation system consists of two distinct sections hardware and software The seamless integration of the two requires the use of the various tools shown in Figure 1 Hardware level programming is used to allow for a more intricate interaction among the devices The 1Digi gateway is programmed with Digi ESP for Python an IDE designed specifically for the Python language and the gateway Finally the design of a web interface is made Int l Conf Embedded Systems and Applications ESA 12 possible by using Aptana Studio and the HTML and CSS languages 4 1 Hardware The hardware portion of the proposed home automation system directly interfaces with a variety of devices found in residences The ZigBee RF wireless standard enables communication among individual devices The system allows for the voltage current power and energy to be measured at individual devices in addition to providing the means to control the device operations The data obtained from the devices is transmitted across the ZigBee wireless mesh network to a gateway which enables the use of a web based user interface A block representation of the system is shown in Figure 2 The current system revision is rated for 120Vac and 6 3A but can be
191. e in the system integrated architecture utilizes the same configuration Feedback based control scheduling algorithm is implemented on the top of OS layer It is assumed that the allocations of tasks are predefined and faults can occur at any time Sensors Actuators Non SC Core VO controller VO controller VO controller Partition A Partition B controlle Device driver management Device driver management OS service A CPU RAM OS service B OS services for driver Service interface OS services for driver Service interface FSC ROM SC OS service provider Kernel OS service provider Kernel Node resources Network Figure 2 Integrated system architecture Jobs of mix criticality executes on the same node Int l Conf Embedded Systems and Applications ESA 12 5 Processor Scheduling Model In order to ensure that all tasks assigned to a particular processor are schedulable the processor should be kept under the scheduling bound In case of classic real time scheduling algorithms for example RM in which each task is assigned a fixed priority and the task with smallest period is assigned the highest priority The scheduling can be ensured if CPU utilization is kept under schedulable CPU utilization bound t 2 1 where is the number of tasks assigned to same processor 21 This is called the Lui and Layland bound For EDF the utilization bound is 1 CPU utilization model is defin
192. e next Rider equation cos 6 cos c cos 3 Int l Conf Embedded Systems and Applications ESA 12 In this equation c is a parameter that is defined by Rider as a relation between s and 0 1 Then solving for s gives the number of satellites TT The reason for taking the ceiling of this equation is to ensure we get an integer value for the satellites since there cannot be a fractional value of a satellite Next the number of satellites for GPS purposes can be determined First the orbital altitude of the satellites needs to be determined In order to do this Kepler s third law was used 2 t B An 5 r3 Gm For this equation t is the orbital period r is the orbital radius G is the gravitational constant and m is the mass of the body being orbited Lastly solving for r and subtracting the moon s radius yields the satellite altitude 3 Gmt V 4r 9 Satalt T Tmoon 7 3 The Lunar Space Segment The space segment for this GPS is the only segment focused on in this paper It is worth mentioning that the control segment will be used for sending clock updates for the satellites There are two major requirements for the space segment The first is to adhere to the aforementioned constellation design in section 2 The second is to keep the design within the constraints of the CubeSat platform The major components which contribute to the payload of each satellite would be the electronic and
193. e putting of one mark in the place 7 toT and one in TitoT4 The main object for using the place T toT is to indicate the precedence between the different instances of execution of the task T i The new marking enables and validates the transition T4Receiving Since its crossing the task T4 has all necessary data to activate a new instance 5 Tool and model execution The dPTPN is accompanied with a scheduling analysis tool called dPTPNS 14 dynamic Priority Time Petri Nets for Scheduling analysis Indeed it presents a Petri Nets editor and executer model The editor is implemented under the Graphical Modeling Framework GMF founded on Eclipse Modeling Frame work EMF Hence the dPTPN Meta Model represents the starting point of the editor s generation process The ordinary Petri Nets Meta Model is extended with the addition of two Meta class Temporal and Tcp The created models are checked through a set of constraints expressed with the Object Constraint Language OCL 9 The validation doubles through the verification during and after constructing the model It is obvious that the created model is built around a drawing 1 dPTPN Name String Name String weight Integer Name String NbToken Integer weight Integer Tcp priority Integer Temporal Tf Integer CoefArc Coef Integer a Fig 8 dPTPN Metamodel compos
194. e what kinds of errors are occurred without running their software on the platform They just find why error is occurred on that platform and then resolve the problem The execution information describe comparing image of execution activity on each platforms and explain differences between logs It is difficult to find a problem which is made by difference between resolutions of two devices hence ACSF just support two kinds of images of each platforms 4 Conclusion Most developers have a difficult time finding the bug which is due to portability To overcome this difficulty they use tool which support several functions to reduce their repetitive and unnecessary tasks The ACSF generates a report from analyzing and running software The report contains diverse information such as summary information compilation information execution information Especially candidate of error in the execution information is the most important one We are not sure about that the candidates will 139 make an error during running the software but developer must know existence of the potential error Developer should fix it or prevent problem due to it To use the tool it may reduce the time for software testing therefore developers concentrate on the service of their software and improve software quality In future we will make more meaningful information for developers to help their development process 5 Acknowledgments This research was suppor
195. e workloads that should meet deadlines defined according to user re quirements The extension of the proposed algorithm should be straightforward when this assumption does not hold and its running time is O n m 11 To illustrate the key point of the proposed dynami cally approach we define a new real time embedded control system in the study Sys LU Sys2 where Sys is a set of n periodic tasks i e Sys 71 T2 5T m and Sys is a set of m active sporadic tasks o ordered by increasing deadline in a linked list i e Sys 01 02 0m o1 being the task with the shortest absolute deadline 2 1 STATE OF THE ART Nowadays several interesting studies have been pub lished to develop reconfigurable embedded control sys tems In 5 Marian et al propose a static reconfigu ration technique for the reuse of tasks that implement a broad range of systems The work in 6 proposes a methodology based on the human intervention to dynamically reconfigure tasks of considered systems In 8 an ontology based agent is proposed by Vyatkin et al to perform systems reconfigurations according to user requirements and also the environments evo lution Window constrained scheduling is proposed in 9 which is based on an algorithm named dy namic window constrained scheduling DWCS The research work in 10 provides a window constrained based method to determine how much a task can Int l Conf Embedded Systems a
196. ead _activate is called since the os_start call The alarm calls the alarm_callback function at every 5 seconds Int l Conf Embedded Systems and Applications ESA 12 include os h UINTS tid1 tid2 UINTS alid void alarm_callback void i uart_printf Alarm Callback n j void task void args while 1 i uart_printf Task id d Got d n id 1 delay_ms 100 j j int main void os_init thread_create task NULL 0 PRIORITY NORMAL AUTO START amp tid1 thread_create task NULL 0 PRIORITY NORMAL AUTO START amp tid2 alarm create alarm_ callback SEC 5 SEC 5 amp alid alarm start alid os_start return 0 4 Model 4 1 Common interface of sub application As described in Section 3 there are some rules of writing applications in AVOS e g the placement of os init and os start functions However when we create a large application by combining sub applications common factors must be extracted so that they can be used for sub application to run with minor modification as well as a single application to run and be tested Actually these factors are the interface with which each sub application handles the other sub application From our observation of AVOS behavior five common factors are identified as listed below l sub application number sub application ID This number must be kept within a scope of sub application When program control is switching fr
197. easible then the Intelligent Agent dynamically provides precious technical solu tions for users to send sporadic tasks to idle times by modifying the deadlines of tasks the worst case exe cution times WCETs the activation time by toler ating some non critical tasks m among n according to the m n firm and a reasonable cost or in the worst case by removing some soft tasks according to pred ifined heuristic We implement the agent to support these services in order to demonstrate the effectiveness and the excellent performance of the new optimal al gorithm in normal and overload conditions 1 INTRODUCTION Nowadays due to the growing class of portable sys tems such as personal computing and communica tion devices embedded and real time systems con tain new complex software which are increasing by the time This complexity is growing because many available software development models don t take into account the specific needs of embedded and systems development The software engineering principles for embedded system should address specific constraints such as hard timing constraints limited memory and power use predefined hardware platform technology and hardware costs On the other hand the new gen erations of embedded control systems are adressing new criteria such as flexibility and agility 7 For these reasons there is a need to develop tools methodolo gies in embedded software engineering and dyna
198. easily modified to accommodate other voltages and larger currents Through the use of voltage and current sensing transformers the wireless metering and control circuit is interfaced with the line voltage as shown in Figure 3 The two low voltage power supplies 3 3 and 5 Vdc are derived from the 120Vac line By using a center tapped 120 30Vac transformer and by connecting the center tap to ground two 15Vac waveforms which are 180 out of phase are half wave rectified to produce a DC voltage A large capacitor is incorporated to remove the DC ripple voltage The two transformed AC phases can be viewed in Figure 4 while the DC output is shown in Figure 5 In order to provide constant DC voltages to the various circuit components the rectified DC output was connected to 3 3 and 5Vdc voltage regulators HARDWARE TOOLS PROGRAMMING Sensing Circuit MPLAB IDE Assembly Language MPLAB X IDE C CS5460 a ansaa oa PIC16F882 XBEE 2 RF Aptana Studio HTML CSS A Y iDigi Gateway INTERNET Coe ecocceees gt _ Network Router iDigi Cloud Interface o Figure 1 Overview of System Design Aspects Int l Conf Embedded Systems and Applications ESA 12 CURRENT SENSE Z at tabs ihn aa aa ee ee ee ae T aoe EERTE E a ee ns os i TH PIC16F882 I SP T TE MICROCHIP F TE MICROCONTRO R ti y Oaa ps XB24 Z7WIT 004 E i SOURCE f J3 o E g J6 1 m 1 LOAD ilnj DF
199. ed Emergency Alarm System MR BEAS An architecture is presented for the MR BEAS and is shown in Figure The architecture consists of modules for Capture Depth Stream Derive Skeleton Object Predictable Matching Algorithm and Generate Alarm An NUI Application Programming Interface API is used for capturing the raw depth stream from the depth sensors The NUI API is part of the SDK for Kinect This API allows the retrieval of sensor streams and also controls the Kinect device The depth data stream delivers frames in which each pixel represents the Cartesian distance in millimeters from the camera plane to the nearest object at that particular x and y coordinates in the depth sensor s field of view Applications can process data from a depth stream to provision various custom features such as tracking users motions or identifying background objects to ignore during application play A depth data value of 0 indicates that no depth data is available at that position because all the objects may be too close to the camera or too far away from it 36 Check for active connection Retrieve joints from the Skeleton Data Retrieve Depth Sensor Data Derive Skeleton Data from Depth Image Perform Predictable Match Algorithm Figure 2 Process flow for the MR BEAS Application code acquires the latest frame of the image data using a frame retrieval method and passes on to a buffer If the a
200. ed in the following equation which holds for any number of processors 22 y t 1 Ay t BAr t 1 Where y L represents the processor utilization vector with size n Ar L represents the change to task execution rate from the m number of tasks running on the processor B e L and is defined as B GK 2 Where K is the available subtask allocation matrix that record which number of particular tasks are running on which processors G diag g4 g2 gn is a diagonal matrix and gi where i 1 2 3 n are scalar values that denote the ratio between the change to the actual utilization of processor i and its estimationAr t The size of g measures the estimation error 1 e how much the actual execution time of each task on processor 7 deviates from its estimated value 6 Attaining Dependability Faults in real time embedded systems can occur at any time In order to make sure that the system guarantees its services even in the presence of fault fault tolerant scheme re execution with replication is integrated with FCSA to achieve dependability However the methodology is flexible for integration of any FT schemes In _ re execution with replication whenever a fault is detected by the error detecting processor 7 the job is re executed on the same processor and a new replica of the same job is executed on a different processor Since at the detection of each fault a new job is assigned to a different pr
201. ed of places transitions and arcs In fact we need to easily extract the existing data from the editor Fortunately the created model can also be serialized to generate an XML Extensible Markup Language or XMI XML Metadata Interchange file The generated file conforms to the dPTPN Meta Model and presents the entry port point of the executer Due to the structure of the editor output the properties of the modeled net are easily interpreted The verification framework is sufficiently flexible and ex pressive to support module inclusion and extension The use of the editor tool makes it easier and faster to create dPTPN models Despite the representation of dPTPN ele ments provided by the editor the palette is equipped with dPTPN components in order to facilitate the illustration of complex tasks and computing resources So it is sufficient for the developer to select the structured dPTPN class from the palette with the communication means Compared to the existing Time Petri Nets simulators such as ROMEO 7 and TINA 5 the impetus of our tool is the integration of the dynamic priority concept and its structured input output files and Petri components which guarantee interaction with the existing PNs simulators and Eclipse features If we are to situate our extension with regard to the existing tools in addition to the dynamic priority we note the following distinctions e Contrary to Cheddar tools 26 Mast 10 Times 1 which
202. edded in the field programmable gate array FPGA the phase of the basic CLK signal CLK_A is shifted to generate basic CLK and phase shift CLK CLK_B On the other hand the round is counted from the busy signal in a cryptographic circuit to realize the change over at an arbitrary round Figure 2 shows the fault generation block of the proposed evaluation platform 3 2 Key Analysis Block An analysis algorithm determines whether the keys specified by the key attacks can be derived First the fault generation position in the key generation section which is to be investigated is examined Switch from CLK_A to CLK_B CLK 24MHz JUL Switch from CLK _A to CLK B Hl E CLK A Base CLK F CLK B ase Sin MUX Width of Glitch a a a Fig 2 Fault generation block of the proposed evaluation platform 12 Tables 1 and 2 show the number of keys that were obtained through the application of key attacks to the key generation section according to the fault diffusion pattern Table 1 shows the case where the fault diffuses in columns As shown in this table the number of specified keys increases as the number of fault generation positions increases In contrast as shown in Table 2 despite the increase of the number of fault generation positions the key still could not be specified This study investigates the case where the fault generation position in the key generation section diffuses in columns 4 Evalua
203. eeded for reclaiming invalid marked pages scattered over blocks so that the invalid marked pages can again become free pages The garbage collection sequence and its operational cost are summarized as follows The FTL selects some blocks which are expected to have the lowest garbage collection cost as victim blocks when garbage collection is triggered The P E cycles or hot cold identification of each block as well as the num ber of invalid pages can be considered when selecting victim blocks The FTL targets entire blocks as victim candidate blocks of flash storage which may cause a se rious operational cost The FTL implements block erase operations in order to physically remove the invalid marked pages from the se 23 lected victim blocks However the FTL should allocate a free block and then copy all the valid pages from vic tim blocks to the free block because the victim blocks may have valid pages Consequently the valid pages scattered over victim blocks are copied to one free block The FTL updates the mapping information after generat ing a data block full of valid pages and the victim blocks are then physically erased The erased blocks are logical ly located in the free block pool and reallocated when necessary 2 2 Latency Hiding of Garbage Collection The storage access frequency of a host system is called data access intensity and is affected by workload characteris tics Storage I O performance is directly influe
204. ehavior of a Real Time task TaskC is characterized by two interfaces which assure the communication with its environment input and output In fact each interface is a finite set of places The graphical definition of TaskC is presented in Fig 5 and defined with the triplet TaskC dPTPN II OT 10 with 117 118 TiUnCreated TiDeadline T1ReceivedDat i TiReady Cw eee TiReleaseProc Fig 5 The Task Object with dPTPN 1 dPTPN is the dPTPN model presented in Fig 4 2 Il Pinoso P recniued Datos Perro is the places that composed the Input Interface 3 OI PReadys F Deadlines ERenaining erod PSendData PReleasing is the places that composed the Output Interface Let T 0 4 2 Task from Q Its corresponding TaskC component instance of T askC is created as follows e The firing time of the creation event is initialized with ies see Toreon 0 e The period is initialized on putting the weight 4 on the coming arcs of the place PremainingPeriod and on the outgoing arcs of the place PElapsedPeriod Praska PRemaining Periods il Gpedtion A Praska FRemamni Perot T Restart A Braskc Pp iipsed Periods T hestar _ A e The execution time is initialized with adding the weight 2 on the input arcs of the place Po from the transition T Restar and on the outgoing arc from the place Per to Tendo Braskc Foi Tendci 2 ET Geko Poi Trosa zr 2 4 2 Modeling of
205. elative percentage of the cache dynamic power are the same According to fig 2 b and dynamic power consumption configuration 1 is the best cache size for selected embedded application Based on the dynamic power consumption results in 90nm feature size up to 40 of core dynamic power will be consumed in the cache hierarchy 4 3 Total power Fig 2 c shows the percentage of the cache hierarchy total power leakage dynamic consumption related to the core for all 12 configurations Here like the previous sections the best cache hierarchy configuration is cfg number 1 because this configuration consumes the lower percentage of the core total power Based on the total power analysis results in 90nm up to 32 of core total power will be consumed in the cache hierarchy In another point of view performance is also one of the most important parameters to tune a cache configuration for embedded application So the cost functions that consider Int l Conf Embedded Systems and Applications ESA 12 both power and performance simultaneously can deliver better results So in the next section we will explore some important parameters based on power and performance of all 12 configurations which are more effective for embedded applications 4 4 Million instructions per second MIPS As mentioned in previous sections although power analysis is one of the most important constraints for embedded applications however designers should cons
206. ell as UI components contained in activity The manual mode is used for alerted software error due to malfunctions of the software Fig 2 illustrates manual test case generator r r S RPB TestCase Generator D E 3 Rs Testcase Generator D a Record Record List Sequence Test Case List Testcase Name M_010001_HelloAndroid2 M_010001_Hel Testcase Name M_010001 HelloAndroid2 Starteitton_ MN E E O EE e e a onal L Record List saveButton 1 StartButton Button Abcdef 3 saveButton Button StartButton HelloAndroid2 Button Stat a exitButton Button HelloAndroid2 EditText Abcdef HelloAndroid2 Button Record Name StartButton pathCheckBox saveButton exitButton Cancel O OK Cancel J a i d Figure 2 Manual Test case Generator On the automatic mode user only chooses pair of activity name and sensor type It means that selected activity will be generated logs from selected sensor The sensor is a source code for making various logs and is used for various 138 purposes such as verification status making screenshot and so on Table 1 illustrates types of sensors Table 1 Types of monitoring sensor Sensor Type Description purpose of this sensor TIA Whether activities run well or not TIE Whether events run well or not TIC Capture device s screen DIV Important variable value DIS System status UIU User defined log TIA and TIE are function to verify whether activity or event is running well or no
207. elp improve the course term after term For example in the first offering of the peer teaching activity an important improvement suggested by a number of students was to add a quiz at the end of each presentation to make sure the class is paying good attention to the student presentations This and other important feedbacks were incorporated in the subsequent offerings of the course A few quotes of students comments are given below On peer teaching Strength J enjoyed this activity It provided us an opportunity to show a detailed level of understanding revolving around a single topic It also is one of the only classes I ve had where I was able to teach the class something and interact with the students in that manner I felt that was a good experience Improvement Provide an outline of what material should be covered minimum for each topic to ensure that all material is covered Insight Best way to learn something is to try to teach it 130 On final projects Strength I like how the topics were left open to the students but also suggestions were made by the professor I m a firm believer that if students are able to work on a topic that genuinely interests them they will put more time and effort into it resulting in a better outcome as well as a better educational experience throughout the project Improvement Help students reign in the project to realistic proportions for the time th
208. emory controllers and a CPU and software parts 1 e FTL in order to verify the effectiveness of the 2LGC scheme The resulting 2LGC scheme offered significant benefits such as a high perfor mance storage access ability and a host command delay drop compared to an on demand victim search technique in our experiments The rest of this paper is organized as follows A prelim inary overview of garbage collection mechanisms and latency hiding skills is described in the next section Related works including victim block selection techniques and their laten cies are reviewed in Section III The proposed garbage collec tion scheme is explained in Section IV and its feasibility is discussed A comparison of the 2LGC scheme to the on demand victim selection technique in terms of responsiveness is analyzed in Section V Finally conclusions are drawn from this study in Section VI 2 Preliminaries 2 1 Garbage Collection Mechanism The FTL address re mapping technique has a problem in that invalid marked pages occupy the flash area without being erased If these invalid marked pages accumulate in the flash storage the problem of no more available free blocks arises although the capacity of used space is much smaller than that of the flash storage Therefore it is necessary to physically eliminate invalid marked pages and make free blocks available in order to sustain flash write performance and storage capacity Garbage collection is thus n
209. en C et al Communication Synchronous Scheme for MPSoC In International Conference on Anti Counterfeiting Security and Identification in Communication ASID 2010 3 Martin G Challenge 43 Conference 2006 Overview of the MPSoC Design ACM IEEE Design Automation 4 Wolf W Embedded Computer Architectures in the MPSoC Age In 32 International Symposium on Computer Architecture 2005 5 H bner M and Becker J Multiprocessor System on Chip Hardware Design and Tool Integration Springer 1 ed 2011 6 Kissler D Power Effcient Tightly Coupled Processor Arrays for Digital Signal Processing PhD Thesis from University of Erlangen Nuremberg 2011 7 Sousa E R and Meloni L G P An Analytical Model Proposed for Evaluating Efficiency of Partitioning Code in Hybrid Architectures Based on DSP and FPGA 13 International Conference on High Performance Computing and Communications HPCC Canada 2011 Performance www altera com 8 Altera Corporation Nios H Benchmarks Available on literature ds ds_nios2_perf pdf 9 Brogioli M et al Hardware Software Co design Methodology and DSP FPGA Partitioning A Case Study for Meeting Real Time Processing Deadlines in 3 5G Mobile Receivers 49 IEEE International Midwest Symposium on Circuits and Systems Puerto Rico 2006 Int l Conf Embedded Systems and Applications ESA 12 10 Rinnerthaler F F et al
210. ents will encounter in the professional world b to actively engage students in the course delivery and learning process and c to provide opportunities for students to explore their interests related to applications of the subject matter covered in the course This paper presents the experiences from all aspects of the improved course curriculum and results of the assessment Keywords Embedded Systems Curriculum 1 Introduction Courses in embedded systems form the core of the undergraduate Computer Engineering curriculum at our institution We have the following courses focusing in the area of Embedded Systems DS I Digital Systems I Sophomore II MS I Microcomputer Systems I Junior I MS II Microcomputer Systems II Junior II or Senior I DS II Digital Systems II elective Junior I or Senior DES Distributed Embedded Systems elective Junior II or Senior 6 IMR Introduction to mobile Robotics elective Junior II or Senior ae ee The main reasons for offering a series of two courses in each stream of the Embedded Systems field is because of the shortage of time to cover the required material in greater breadth and depth Unlike semester systems Kettering University uses a term system with each term having only 10 weeks of classes DS I and MS I are required courses for all students majoring in Computer Engineering Computer Science and Electrical Engineering They provide the foundation on the principles
211. er designed by Kun et al 13 and the 76 transistors 8 bit CMOS priority encoder constructed on the basis of Huang and Chang s approach 14 Huang et al s priority encoder cell 6 corresponds to 4 bits and two such encoders are incorporated into a multi level look ahead structure to realize an 8 bit encoder it suffers from increased power dissipation and is also observed to be relatively slow On the other hand Kun et al s 8 bit CMOS priority encoder 13 is an optimized circuit that is found to be competitive with the proposed priority encoder in terms of Int l Conf Embedded Systems and Applications ESA 12 device count and operating speed An 8 bit dynamic CMOS priority encoder was designed manually based on Huang and Chang s 4 bit priority encoder cell 14 68 transistors were required for the 8 bit encoder module However to configure it as a basic building block for constructing higher size encoders on the basis of the parallel priority lookahead architecture given in 13 provision for a lookahead signal input was also included which necessitated adding 8 more transistors bringing the total device count to 76 From the simulation results mentioned in Table 1 it can be inferred that the proposed 8 bit CMOS priority encoder secures a clear edge over other priority encoders with respect to total power dissipation and area occupancy represented in terms of number of transistors 4 7 less power consuming tha
212. er does not perform any sub sampling of the final image data which makes the processed output bitstream larger 4 4 4 color space than the preferred 4 2 0 color space The reduction of the color space effectively reduces overall size by half with little discernable visual deficiency 5 1 Connectivity USB 2 0 Testing According to the datasheet of CY7C67300 from Cypress the USB chip included on the FPGA board only meets the USB 2 0 specification requirements for supporting USB 1 0 1 1 speeds as USB 2 0 high speed is not actually supported Therefore the maximum burst throughput of CY7C67300 on the board is approximately Megabytes per second USB 1 1 so an alternative method is to integrate an external USB development board Cypress EZ USB FX2 8 to provide the necessary connectivity bridge at full bandwidth between the client machine and the FPGA board Int l Conf Embedded Systems and Applications ESA 12 31 The test and benchmark configuration is as follows e The FX2 module FX2_TOP_INTERFACE will clock the external USB chip at 6MHz for Asynchronous transfer on A _ f e USB packet size 512 1024 2048 4096 and 8192 at gt ae bytes USB Interface or pm Khe t po Throughput Test Bulk Trans P USB Device Cypress tts Figure 3 Cypress EZ USB FX2 Development Board Packoge See m2 a M dabee 0 oe i Total Package Length 5KB 5120Byte i Out Pipe lo Endpoint 1 OUT In Pipe fo E
213. er lawyer communication thus an implementation with real time support could take a long development time Alternatively in 7 native C code library has been used from developed applications with some time restrictions They report the time execution of a native application has a significant improvement over a similar Java application running over Dalvik Virtual Machine However the improved time doesn t imply real time support and the native approach cannot guarantee the timing requirements 3 Android architecture Android is a software platform rather than just an OS which has the potential to be utilized in a much wider range of devices In practical terms Android is an application framework on top of Linux which facilitates its rapid deployment in many domains 8 Android s framework is divided in lawyers as it can be seen in Figure 1 Applications Android Application Framework Dalvik VM Figure 1 Android Architecture Linux kernel gives support to low level components mainly hardware drivers are managed by this lawyer Peripherals as cameras printers flash memories Wi Fi displays etc Have to be directly controlled by the kernel Android includes a set of C C libraries used by various components of the Android system These capabilities are exposed to developers through the Android application framework 101 Every Android application runs into its own process with its own instance of th
214. er teaching activity is meant to take students out of their passive comfort zone and motivate them to take the lead in learning an assigned course topic and teach it to the class The inspiration for peer teaching came from previous research in the literature 11 which describes the effectiveness of the method in actively engaging the participants and enhancing learning in both the peer teachers and learners After the first four weeks of lectures and labs students will have the necessary background to make informed decisions about the topics they would like to investigate further Most of the peer teaching topics identified are microcontroller peripheral modules such as the various serial communication interface protocols analog interfacing and low power wireless communication etc Students are required to submit electronic copy of their presentation three days ahead to the professor for review and feedback The presenters also prepare short quizzes which could be modified by the professor and given to the class at the end of the presentations The presentations typically run for 30 to 40 minutes followed by 10 to 20 minutes of discussions with the last 10 minutes left for quiz 7 Assessment The assessment techniques employed is of qualitative nature including SII surveys completed by the students at the end of the course and the university wide course evaluations completed by the students Feedback received from these assessments h
215. ere able to get support from the company for course development resources including sensors and actuators utilized by different final projects in the course FPGA based platforms are also possible choices for embedded systems course The DS II course actually teaches Int l Conf Embedded Systems and Applications ESA 12 digital systems design and implementation using FPGA with most of the programming done in VHDL The DS II course also addresses system on programmable chip SOPC design using hard or soft processor cores built in the FPGA along with hardware accelerator implemented in the logic fabric Since MS II is a microcontroller based embedded systems course we decided to use an MCU rather than an FPGA as the target device 5 Final Projects In the past two years of the course offering a final project component has been introduced The main motivation for this component of the course is to allow the students explore their interests and apply what they have learnt in the course to solve real world problems This is in line with a bigger undertaking by the University to instill innovation and entrepreneurship mindset in the students University wide workshops and seminars are conducted to inspire students to become innovative and enhance their problem solving team work and leadership skills Students work in groups of two to three students They make their project proposal with five minute class presentations discussing
216. eriodic request occurs just after the polling task has suspended then the aperiodic request must wait until the beginning of the next polling task period or until background pro cessing resumes before being serviced Even though polling tasks and background processing can provide time for servicing aperiodic requests they have the drawback that the average wait and response times for these algorithms can be long especially for back ground processing Figure 2 illustrates the operation of background and polling aperiodic service using the periodic task set presented in the table of the same Po Period Activation Calcul Priority Utilisation Response T1 e o ay 17 T 7 DPs it Polling Server PS Figure 1 The simulation with only Polling Server We suppose that a reconfiguration scenario is applied at tl and t2 time units with the arrival of 2 new aperiodic tasks eq at tl 7 and eg at t2 11 time units Therefore the system is feasible by applying the polling server to schedule the system but the response time is equal to 17 and 33 for both eq and eg respec tively Now by applying our new hybrid approach the response time of the second arrival aperiodic task is decreased from 33 to 25 time units as we observe in figure 2 Period activation Calul Priority utisation Response T1 I Backgroundsever t delo ja 0 3 0 4 0 25 5 1 a fl Polli
217. ery three seconds 4 Conclusion This work showed the development of a remote tele operated robotic module through the 802 11g protocol The paper presented the development of the whole system platform including control systems image capture and transmission protocols defined to ensure a secure communication between the robot and the remote operator In tests considering the communication distance similar results to the ones presented in 1 4 5 were obtained The autonomy of the platform reached values even higher than what was expected for the project being interesting even to replace the battery pack for only one element of charge The delay produced in the response time tests 1s insignificant considering that they were performed on a wireless network in an indoor environment and with a protocol for encrypted communication The major problem was the transmission time of the image between the robot and the operator which reached only one image at each trhee second interval Finally currently and future work include the development of a more efficient method of image compression allowing the capture display and transmission of a greater number of frames per second to the remote operator station 5 References 1 Sanchez A Hernandez X Torres O Alfredo Toriz P Mobile Robots Navigation in Industrial Environments Mexican International Conference on Computer Science ENC 2009 2 Menon C Murphy M Sitt
218. es the pacing logic for the pacemaker and the output circuitry which delivers the pacing impulses to the electrodes These are all embedded in the system shown in Figure 1 Even though the pacemaker will operate on a 9 volt battery it is more convenient to power it using an external AC adapter Modern pacemakers have several functions The most basic pacemaker monitors the heart s native electrical rhythm When the pacemaker fails to sense a heartbeat within a normal beat to beat time period it will stimulate the ventricle of the heart with a short low voltage pulse This sensing and stimulating activity continues on a beat by beat basis The more complex pacemakers also have the ability to sense and or stimulate both chambers of the heart The basic ventricular fail safe pacing mode is VVI or with automatic rate adjustment for exercise VVIR These are suitable when no synchronization with the atrial beat is required The wide range of available pacemaker modes is shown in Figure 2 Electronic pacemakers play an important role in society Several advancements have been made in pacemaker technology over the last fifty years making current pacemakers highly sophisticated cardiac rhythm managers with thousands of lines of code They are capable of correcting a wide range of complex heart abnormalities They can also be easily Int l Conf Embedded Systems and Applications ESA 12 reprogrammed to accommodate changes in the state of the he
219. es and procedure to recover its data on Linux platform This procedure addresses all small and medium NAS devices NAS are fault tolerant but not fault proof and as a result usually leave customers with a false sense of reliability 7 References 1 Eduardo Pinheiro Wolf Dietrich Weber and Luiz Andr e Barroso Google Inc Failure Trends in a Large Disk Drive Population 5th USENIX Conference February 2007 2 Universe Infosoft NAS Data Recovery http www universeinfosoft com DataRecovery nas data recovery html 3 Enterprise Strategy http www enterprisestrategygroup com Group 4 Jin H Hwang K Zhang J A RAID reconfiguration scheme for gracefully degraded operations Proceedings of the 7th Euromicro Workshop on Parallel and Distributed Processing 1999 Funchal Portugal 3 5 February 1999 p 66 73 5 Microsoft Corporation amp Dell Using Network Attached Storage for Reliable Backup and Recovery Microsoft Corporation Published July 2003 6 Aaron Harper Embedded NAS RAID Data Recovery Procedure Alpha Dog Technical Services LLC 06 AUG 2010 7 Julius Bud Younke How To Handle RAID Array Failures 2004 2012 Reclamere Inc Online Available http www reclamere com uploads RAID 20whitepaper1 ll pdf pdf 8 DRG Data Recovery Group An Ebook on Data Recovery and Data Protection Online Available http www datarecoverygroup com pmebook pdf 9 DATA RECOVERY BOOK V1 0 Copyright
220. essentially measures the time elapsed since last sampling interval and last updated input time respectively Based on the configuration this Lyapunov functional does not increase at the update times that which it is discontinuous To ensure stability Lyapunov functional should decrease at these discontinuities 30 This condition holds if Linear Matrix Inequalities LMIs in the below mentioned theorem is satisfied These LMIs are solved using Matlab Simulink 34 Theorem I The system mentioned in the 4 and 5 are exponentionally stable over the sampling intervals defined by 4 if there exist symmetric positive matrices L X R1 R2 and not necessarily symmetric matrices M7 N2 that satisfy the following LMIs m T Pimax dimax M2 M3 dima Ni lt 0 8 X a TES and M Pimax dimax M2 dimaxN1 Pimax dimax Ny N2 y A marha 0 lt 0 Dia dimas Ry R2 where 7 P 7 I IT M F P 0 o l o F olx o N I ol 0 I I I N N U 0 I 0 N 0 I M F R R2 F I paaa M I XF F XU 0 II 0 and F A B 0 The feasibility of the LMIs mentioned in 8 for the given pairs OfPimax Aimax characterizes admissible sample time delay sequence in 4 for the processor i Int l Conf Embedded Systems and Applications ESA 12 Theorem I can be extended to MIMO case to characterize sampling intervals of other SC jobs mentioned in Fig 5 w
221. etween the Central Control Unit and Co processing units which are constituted by one digital signal processor DSP and by one reconfigurable hardware able to accelerate the critical tasks Because different constraints like energy and cost the communication model applied allows full independence of the processes Furthermore from an AMC Asynchronous Memory Controller usually embedded on modern processors a high throughput with minimal latency and jitter may be achieved Int l Conf Embedded Systems and Applications ESA 12 Theoretical values show that running the DSP at 133 MHz and using a bus of 16 bit values of up to 2 128 Gbps can be reached It means a higher rate offered by the most common peripheral devices available for communication such as SPI and USB 2 0 8 2 1 Hardware Software Co design Hardware and software co design offer the possibility to improve the performance of a particular application Accelerators when properly designed significantly enhance the system performance However the application to be partitioned must be carefully analyzed in order to promote an overall improvement 11 12 Thus to achieve a good partitioning that will yield significant results of optimization it is necessary to first identify what are the critical points of the application and which paths will provide a performance improvement when executed in parallel On the other hand there are many applications written sequentia
222. ework that supports comprehensive design space exploration for multi core and many core processor configurations ranging from 90nm to 22nm and beyond MCPAT 23 can model both a reservation station model and a physical register file model based on real architectures 4 1 Leakage power Fig 2 a shows the percentage of the cache leakage power related to the selected core for all 12 configurations Based on leakage power results up to 17 of total core leakage power is consumed in the cache hierarchy If the most important parameter for cache configuration selection is leakage power that has not been considered as a separate parameter in recent researches cfgl in deep submicron technology is the best cache configuration for selected embedded applications Based on the performance results of MIPS section figure 2 d and also 20 this size will deliver 7 85 performance penalty in average related to the 9th configuration that delivers highest MIPS So by using these tradeoffs designer has to select the best configuration So in the following sections performance parameters will be calculated to consider such tradeoffs 4 2 Dynamic power Fig 2 b shows the percentage of cache dynamic power related to the core for all 12 configurations Result of fig 2 a and 2 b together show that when the selection parameter is only dynamic power configuration selection is harder than when the parameter is leakage power because in many configurations r
223. ey have to work on it Do more planning milestones to keep students on track Insight The project allows students who have passion to really continue on beyond a normal classroom limitation and really explore the potential of that area of study in this case microcomputers Conclusions The paper presented curriculum improvements introduced in a microcontroller based embedded systems course at our institution and the experiences from the past two years of the course offering The assessment results and the feedback received from the students at the completion of the course demonstrate that the improvements in the curriculum achieved the intended goals by providing opportunities for active engagement in classrooms and motivating the students to be innovative in their design projects Int l Conf Embedded Systems and Applications ESA 12 9 References 1 Programming 32 bit Microcontrollers in C Exploring the PIC32 by Lucio Di Jasio 2008 2 Microcontrollers From Assembly Language to C Using the PIC24 Family by R Reese B Jones and J W Bruce 2008 3 Explorer 16 development board http www microchip com stellent idcplg IdcService SS_GET PAGE amp nodeld 1406 amp dDocName en024858 4 Microchip PIC plug in modules PIMs http www microchip com stellent idcplg IdcService SS_GET PAGE amp nodeld 1406 amp dDocName en53 1260 5 Microchip graphics LCD module http www mouser com ProductDetail Microchip
224. f the polling server and the background server in our hybrid scenario We have set up a real time reconfiguration tool named RT Reconfiguration that allows us to randomly generate task sets sched ule them according to the proposed hybrid method and displays the schedules for visual control Our test rows have been on each 1000 randomly generated task sets while the number of tasks is significantly higher We have scheduled task sets with the polling server and the proposed hybrid method 5 2 Discussion In each of these examples many aperiodic requests occur at any moment of the time The response time performance of only polling service or only background service for the aperiodic requests is poor Since back ground service occurs when the resource is idle with the polling server the response time performance for the aperiodic requests is better than both single back ground service and single polling service for all re quests For these examples a polling server is cre ated with an execution time of 1 time unit and a pe riod of 5 time units Also note that since any ape riodic request only needs half of the polling server s capacity the remaining half is discarded because no other aperiodic tasks are pending Thus these ex amples demonstrate how polling and background can provide an improvement in aperiodic response time performance over background service or polling one and are always able to provide immediate service
225. face SATA2 3Gbps Internal SRAM size 96KB Mobile SDRAM size 64MB 175MHz Number of channels 8 Number of ways 2 Clustered page size 32KB NAND flash model ID K9LCGO0O8UIM NAND package die size 8GB 4GB SSD capacity 64GB ECC module 8 12 16 bit BCH per sector The OMeter benchmark 22 is used for generating meaningful workloads in the experiments In order to extract the accurate experimental data we exclude data I Os caused by operating systems or file systems The platform board is connected to the host as flash storage without installing any operating systems or formatting any file systems because the IOMeter benchmark can handle direct storage access opera tions to the unformatted data storage The IOMeter bench mark can also organize workloads of various read write and random sequential access intensities thus configurable work loads with the desired properties can be generated The work load variation is shown in Table 2 the minimum storage access unit size is 32KB due to the page clustering technique Finally the flash storage is programmed with a ran dom sequential write ratio r 50 s 50 for aging entire pages to enable the measurement of garbage collection operation latencies In this experiment the threshold value is defined as 3 4 of the number of pages in a block the Candidate list size is 1 20 of storage capacity and the Garbage block list size is 1 10 of storage capacity respectively Int l Conf Embedded
226. for aperiodic requests Finally for both the polling server and the background server in our hybrid scenario ap proach performs best and yield improved average re sponse times for aperiodic requests 6 CONCLUSION AND FU TURE WORKS In this paper we propose a new theory for the mini mization of the response time of aperiodic real time tasks with the polling server and the background server that can be applied to uniprocessor systems and proved it correct We showed that this theory is ca pable to reconfigure the whole system Previous work in this area has been described several and best solu tion has been suggested This hybrid solution is pri marily intended to reduce the processor demand and the response time of each task set independent of the number of tasks in a uniprocessor system A tool is developed and tested to support all these services As future work we are planning to extend our study to the case of distributed systems and we plan also to ap ply this contribution to other complex reconfigurable systems that we have chosen to not cover in this pa per References 1 Dertouzos M L 1974 Control robotics The procedural control of physical processes Informa tion Processing Layland J and Liu C 1973 Scheduling algo rithms for multi programming in a hard real time environment in Journal of the ACM 20 1 46 61 cs Lehoczky J P L Sha and J K Stros nider 1987 Enhanced Aperiodic Respo
227. for research and teaching in real time embedded system design and verification In order to design a system no matter what its purpose the area of intended use must be researched in order to obtain adequate knowledge to develop a comprehensive system level understanding of the system The pacemaker specification includes several advanced features such as telemetry digital signal processing and power management Thus there are many interesting well documented directions to extend this work Since the pacemaker is used for academic purposes the primary operating environment will be in an indoor lab setting The system is relatively durable and can be easily transported between labs The system can also be used in the classroom to demonstrate more abstract concepts in a concrete fashion In the future we plan to port the hardware to a more advanced controller that doesn t suffer from the limitations imposed by the PIC 18F4520 Acknowledgements Boston Scientific released the specifications used in this design to promote academic interest in pacemaker technology Several discussions with Brian Larson were very helpful in completing this initial framework References 1 Boston Scientific Inc PACEMAKER system specification http www cas mcmaster ca sqrl SQRLDocuments PACEMAKER pdf 2007 2 Heart Rythm Society Patient information http www hrsonline org PatientInfo 2011 3 S Serge Barold Roland X Stroobandt
228. g 0 k 0 key0O aesl128 k mLast m will be unrolled mac3 m 3 assert acknowledge ack 1 while req 0 ack 0 Fig 12 AesCmacProc c Fig 12 shows AesCmacProc c generated from a part of AesCmac java This is an input of high level synthesis and should be synthesized to Verilog description of finite state machine FSM This description contains substance of the processing method and has some additional codes taken from library that handles request acknowledge signals 5 3 Generality brought by Java and JNI This co design methodology stands on Java and JNI Therefore this methodology has architecture independent generality and can be applied to any platform that has JVM and JNI such as Android platform 5 4 Future Work This co design methodology covers Java applications synthesized hardware and interfaces between synthesized hardware and Java applications This is a sufficient solution to control synthesized hardware but not enough to transfer large data between the hardware and Java applications The next step of this study is to extend this methodology to manage large data placed on native memory shared by synthesized hardware and Java applications and to cover the interfaces between native shared memory and synthesized hardware Java applications 6 Conclusions We proposed a hardware software co design method that covers the weakness of high level synthesis We observed h
229. gram operations from victim blocks and improve the performance and durability of NAND flash storage However the subsequently proposed algorithms such as the Cost benefit scheme 9 indicate a problem in that the Greedy algorithm is not suitable for prolonging the lifespan of flash storage because the Greedy algorithm selects victim blocks without considering their P E cycles Therefore many subsequent studies 10 15 have pro posed victim block selection techniques considering wear leveling costs However the dynamic wear leveling and static wear leveling schemes 18 19 have already been adopted inside flash storages so there is no need to consider both 24 wear leveling and garbage collection issues together Conse quently if the wear leveling cost is not taken into considera tion the Greedy algorithm shows the highest performance in terms of garbage collection cost compared with other victim selection techniques 3 2 Victim Selection Latency Measuring computational latencies from garbage collec tion is a totally different issue because the previously pub lished research on garbage collection schemes did not focus on victim block management costs such as victim selection overheads and sorting delays Thus victim block manage ment costs must be carefully analyzed in order to decrease garbage collection latencies The garbage collection operational delays based on previous research are as follows First the FTL extracts
230. griculture and forestry Serial control and communications data network Virtual Terminal 2002 2 ISO11783 9 Tractors and machinery for agriculture and forestry Serial control and communications data network Tractor ECU 2002 3 The STMicroelectronics Available http www st com 1998 2012 Online 4 IsoAgLib Development of ISO 11783 applications in an Object Oriented way Online Available http Asoaglib org 2009 5 Peter Felimeth CAN based tractor agricultural implement communication ISO 11783 CAN Newsletter 2003 9 6 Bosch Robert GmbH CAN Specification Version 2 0 Germany 1991 7 ISO11783 3 Tractors and machinery for agriculture and forestry Serial control and communications data network Data link layer 1998 8 ISO11783 7 Tractors and machinery for agriculture and forestry Serial control and communications data network Implement messages application layer 2002 9 NMEA 2000 The National Marine Electronic Association s NMEA 2000 Standard for Serial Data Networking of Marine Electronic Devices has been approved by the International Electrotechnical Commission IEC 2008 10 ISO11783 10 Tractors and machinery for agriculture and forestry Serial control and communications data network Task controller and management information system data interchange 2009 11 ISO11783 2 Tractors and machinery for agriculture and forestry Serial control and communi
231. hannels with one channel deals with attenuated signal so the overall system will not saturate when input signal reaches its highest level During the pre processing the original signal maybe also has been phase transformed separated in these two channels besides the intended gain separation Before merging into an output signal that ideally has the same characteristics of the original signal both the intended gain separation and unintended phase separation must be corrected The phase correction is done through a reconfigurable fractional delay finite impulse response filter RFDFIR 2 3 together with a phase sensitive detection PSD module To construct two separate I and Q filters for both the high and low gain channels will significantly increase the implementation cost the FPGA area budget within a radar video processing RVP 4 device Int l Conf Embedded Systems and Applications ESA 12 A novel real time detection of phase delay over 180 degree range without using IQ filter is presented in the following Section 2 describes the challenge of using naive derivative method the inherent quardarature detection error when very high normalized frequency has to be used in radar IF domain A proprietary algorithm is used to counter the naive quadrature detection error by realizing that it is the quadrature identification itself instead of the absolute error affects the accuracy of overall phase detection Section 3 presents a re
232. haracters on a terminal window Core concepts a b eA d Basic concept of keypad Keypad scanning techniques Configuration of UART to interface to a PC serial port Setting up a HyperTerminal window for accepting serial inputs Displaying characters sent from the keypad on the HyperTerminal window 5 Kitchen timer Core concepts a Oe OO Using CPU core timer and or one or more standard timer modules PIC32 Interrupt system Writing code for an interrupt service routine ISR Using timer module for accurate timing applications Writing device driver program for interfacing to multiple 7 segment display units using a shared data interface Supporting multiple modes of operation of the kitchen timer set time run time alarm Accept input for the kitchen timer from keypad module 6 Programming a Graphic LCD using the Microchip Primitive Layer Graphics Library Core concepts a b Basic concept of graphic LCD display Pixels colors how they are represented screen size and resolution Images their representation and Primitive Layer functions to display and manipulate them 127 d Fonts their representation and Primitive Layer functions to display them e Image and Font converter utilities f Primitive layer functions for drawing basic geometrical objects 7 Interactive application programming with touch screen interface Core concepts a Basic concepts of different types of resistive and cap
233. hardware and device drivers We apply this method to the Java Virtual Machine JVM and use the Java Native Interface JNI for handshake between synthesized hardware and Java applications In addition we show an example of application of our co design method that calculates the AES CMAC to explain the possibility of whole automatic translation from Java language to hardware and generality of this co design method brought by Java and Java Native Interface Keywords High Level Synthesis Co Design Java JVM JNI Android 1 Introduction Formerly design methodology of LSI was circuit diagram editing however HDL Hardware Description Language and logic synthesis have become popular as increase of circuit scale In recent years we have new option of circuit design methodology called high level synthesis It allows behavioral C source codes as input and outputs structural HDL We can raise the abstraction level of our circuit designing by this methodology can expect decrease of source code lines and can also expect the architecture exploration with trade off in speed area and power In our experience this partially showed the decrease of description amount and the flexibility of exploration while it partially revealed its weak points The effect of high level synthesis is erratic in actual LSI design so we have conceived a new method that covers the weak points of high level synthesis with libraries We also use the Java language fo
234. hat CAN messages follow the standards perfectly without error Int l Conf Embedded Systems and Applications ESA 12 Data 00 EE 00 A AR FG 4 40 CAN2 08 Data Frane ne sr Message 2 CON 08 Data Franel enath 8 WD 18tEFF St ID 18 EA FF FE c np Sbit 8bit 8bit 8bit 2 PDU Format EAis 111010102 23410 PDU Specific FF1s 111111112 25510 Source Address FE 1cs 25410 Broadcast mode OOEEOO ic 6092810 EEic 111011102 238 0 DA Destination Address PTT AT TP Tee foe 59 904 4 234 DA SAP 3 60 928 ass le Self Industry Device Device Reserved Function Identity config group class class instance number ZONAN instance aE COTAR oes a FF OE 00 i Figure 10 Analysis CAN messages First and seceond See IS011783 3 7 Message Request for address claimed request PG ogress Claimed Now we can clarify all messages with standards which are received by our GPS sensor e DNW v0 50M E 6 578894 578993 579693 579194 579294 579394 Figure 11 Time difference between CAN messages Figure 11 shows the time difference between two CAN messages received by GPS sensor is 100milisec This mean the events of CAN interrupt and System timer is working perfectly i e when events are changed it takes Imilisec So we can get CAN messages continuously with standard time Therefore we have no error in our application program and our developed GPS show s great performance 6 Conclusions
235. hat detects abnormal behavior using wireless sensor networks in an assisted living environment They modeled an episode that is a series of events which includes spatial and temporal information about the subject being monitored An abnormal behavior that has similar sequence of events and does not differ from each other for duration could be identified as a normal event In this research a novel method is proposed to recognize an emergency situation in an assisted living facility using motion recognition while the subject is in bed Senior citizens may not have the infrastructure for emergency response in case of discomfort especially while in bed at night This research focuses on alerting emergency response in case of an illness or discomfort based on motion recognition based MR 2 Motion Emergency BEAS The proposed research on Motion Recognition Based Emergency Alarm System VR BEAS focuses on detecting discomfort illness in real time without invasion of privacy automatically during sleep for senior citizens The automatic detection is done by the system using a pre defined gesture performed by the subject in the event of a discomfort or illness This system will work irrespective of the ambient lighting conditions The staff care takers will need to respond only when an alarm signal is generated by this system Recognition Alarm System 35 An expandable platform having a software development kit manufactured by
236. he PICI6F882 A data request causes the PICI6F882 to read from the CS5460A perform the necessary calculations and return the data in a three byte packages The first byte of each package is an identifier relating to the data being read e g 0x16 refers to an RMS current reading The remaining two bytes are the full scale values requested A block diagram of the assembly code operation is shown in Figure 9 4 2 2 Python and HTML CSS In order to enable internet connectivity to the system the iDigi gateway must be programmed to recognize the devices with which it communicates In addition the gateway must be properly configured to accept data and relay it to the web interface The frontend of the home automation system is a user friendly GUI that can be accessed from any internet connection This web interface can be hosted by the Google App Engine and iDigi s Client Web Service By using a hosted web service the need for server infrastructure within the home automation system is removed Customers can use their devices from afar and check their applications reliably through Google servers Some of the items necessary for the development of the web interface are Digi s Python Development Environment DigiESP the Python 2 5 programming language and Google s App Engine Software Development Kit The iDigi DIA projects include the drivers for the XBee module These projects are created with Digi ESP and Int l Conf Embedded Sys
237. he bus which connect the software and hardware processors They will be used in the next evaluations for considering the times involved in each operation as described in Section II Table I Ratio between clock of the core and the clock of the bus Ratio CCLK SCLK CCLK MHz SCLK MHz 100 100 200 100 400 133 500 Based on estimations Figure 4 illustrates how much faster was the parallel processing provided by a given reconfigurable hardware instead the serial execution provided by software processor 125 120 Speedup 8X8 16X8 16x16 32X32 64X32 64X64 32X16 SAD Figure 4 Performance enhancement according to the core clock and system clock ratio These results show that the parallel processing is more efficient to compute the SAD algorithm However the speedup tends to achieve a stability and stop to increase as described by Amdahl s law In our case this fact occurs mainly because the mechanism for core communication is not running as faster as the complexity increases Therefore when the amount of Int l Conf Embedded Systems and Applications ESA 12 data transmitted between the processors start to increase in a fast way the speedup start to decrease as well For performance analysis it was considered the time needed to synchronize the processors Thus it was evaluated the characteristics of the Blackfin processors 18 when a given signal is configured as inputs Therefore
238. he other sub applications Table 2 The description of sub applications The menu front page no thread in which clicking each icon executes the corresponding application Multi threaded demo application 7 threads in which LCD window is divided into quadratic sections In two sections a ball and a cube are moving around The other section is displaying picture and the rest is to control threads freely for demo Touch keyboard application no thread in which the key is displayed on the LCD window whenever a key is touched A Game application that breaks blocks 4 threads Program demo application 9 threads which is the example program of how event driven As program and thread driven program are different The data structure of the common interface and callback distributor for sub applications is represented like Fig 7 The callback function in Fig 7 takes two arguments of x and y as the touch screen coordinates in LCD The CFD is the touch screen callback functions and all the sub applications need the callback functions as shown in Fig 6 The five sub applications are summarized in Table 3 and depicted in Fig 8 In Fig 8 a it is a simple form since no threads are used in A and A which means that application is very easy to understand In case of A six threads are activated by the start function and the highest priority 62 thread T is activated by the callback function If the thread
239. his paper addresses various types of failures cause in NAS storage device and step by step procedure for successful NAS data recovery on Linux platform using normal computer system NAS data recovery is different with other type of data recovery and it is a challenge in itself Keywords NAS NAS data recovery NAS data loss causes NAS recovery on Linux 1 Introduction Continued growth of digital data and having more than one computer in regular use it becomes difficult to keep track of particular data One is required an affordable smaller and more energy efficient storage solution Network Attached Storage NAS provides a central place to store securely and serving all type of computer files on a local network or over the Internet NAS provide good performance stability reliability and security Network attached storage NAS is file level computer data storage connected to a computer network providing data access to heterogeneous clients NAS not only operates as a file server but is specialized for this task either by its hardware software or configuration of those elements NAS systems contain one or more hard disk drives often arranged as RAID arrays NAS use smaller faster and specialized operating system instead of general purpose operating system like UNIX and Windows NT NAS devices do not require any monitor keyboard or mouse and are controlled and configured over the network often using a browser A NAS can stor
240. i M Gecko Inspired Surface Climbing Robots IEEE International Conference on Robotics and Biomimetics 2004 ROBIO 2004 3 Rodic A Katie D Mester G Ambient intelligent robot sensor networks for environmental surveillance and remote sensing 7th International Symposium on Intelligent Systems and Informatics 2009 SISY 09 4 Hamel W R Murray P Observations concerning Internet based teleoperations for hazardous environments IEEE International Conference on Robotics and Automation 2001 Proceedings 2001 ICRA 5 Hamel W R e maintenance robotics in hazardous environments IEEE RSJ International Conference on Intelligent Robots and Systems 2000 IROS 2000 Proceedings 2000 10 Int l Conf Embedded Systems and Applications ESA 12 Development of an Encryption LSI Resistance Evaluation Platform for Fault Analysis Attacks against the Key Generation Section and Its Evaluation Masaya Yoshikawa Masato Katsube Department of Information Engineering Meijo University Nagoya Japan Abstract The algorithm of the advanced encryption standard AES has been sufficiently studied to confirm that its decryption is computationally impossible However its weakness against fault analysis attacks has been pointed out in recent years Nonetheless a method that uses actual large scale integration LSI to evaluate resistance against fault analysis attacks has been scarcely reported This study develops a new resist
241. ial Peripheral Interfaces SPIs communication ports and other variety of modules SPI communication speed can be established based on the MCU bus frequency and is configurable through control registers to facilitate communication with a large number of devices 4 3 Main Display System Android platform is supported by Texas Instrument s DM3730 processor The DM37x generation of high performance applications processors are based on_ the enhanced device architecture and are integrated on TI s advanced 45 nm process technology This architecture is designed to provide best in class ARM and Graphics performance while delivering low power consumption This balance of performance and power allows the device to support a huge variety of multimedia applications 11 The DM3730 integrates a GPP General Purpose Processor ARM Cortex A8 1GHz a DSP digital signal processor TMS320C64x 800MHz plus a graphics accelerator 2D and 3D PowerVR SGX 530 The GPP controls all hardware resources using a generic operating system like Linux Windows CE or in this case Android The DSP acts as coprocessor of GPP It also integrates various peripherals and interfaces to connect the different types of external devices Int l Conf Embedded Systems and Applications ESA 12 5 Application description In this paper we develop a prototype for biomedical monitoring The main objective of this system is collect and transmit first hand bio signal infor
242. iated to real time embedded systems can occur either in hardware or in software These faults are categorised into i transient faults occur only for a short period of time and ii permanent faults affects the system everlastingly 4 Dependability is the ability of the system to perform services that can justifiably be trusted in open and uncertain environment Dependability can be attained by means of i Fault prevention to prevent the introduction or occurrence of fault ii Fault tolerance to avoid service failure in the presence of faults iii Fault removal to reduce the number and severity of faults and iv Fault forecasting to estimate the present number the future occurrence and the likely consequences of faults Traditional Fault tolerant schemes are based on the hardware redundancy 2 5 and can avoid a single transient or a single permanent fault but this method incurs high hardware cost to add a new functionality On the other hand FT schemes can also be implemented in software Most promising FT schemes are i Active replication in which a task is replicated on two or processors and replicas perform the required services 6 ii Re execution in re execution when a fault is detected task is re executed from the start which increases execution overhead to a large extent iii Primary back up in this scheme each task has a backup whenever a fault is detected backup task is executed to perform the required services
243. iation and structural information helpful to data association With the measurements the EKF based SLAM localizes the robot and draws the map in the indoor environment in real time Acknowledgment This work was supported by Cognitive Model Based Real Time Environment Mapping and Global Localization Technology of the Ministry of Knowledge Economy Republic of Korea 110 Int l Conf Embedded Systems and Applications ESA 12 7 References 1 C Harris and M Stephens 1988 A combined corner and edge detector Proceedings of the 4th Alvey Vision Conference pp 147 151 2 T Lemaire S Lacroix and J Sola A practical 3D bearing only SLAM algorithm in Intelligent Robots and Systems 2005 IROS 2005 2005 IEEE RSJ International Conference on 2005 pp 2449 2454 3 T Lemaire C Berger I K Jung and S Lacroix Vision Based SLAM Stereo and Monocular Approaches Int J Computer Vision vol 74 pp 343 364 2007 4 J E Guivant and E M Nebot Optimization of the simultaneous localization and map building algorithm for real time implementation Robotics and Automation IEEE Transactions on vol 17 pp 242 257 2001 5 R Smith M Self and P Cheeseman A stochastic map for uncertain spatial relationships in on The fourth international symposium robotics research Univ of California Santa Clara California United States MIT Press 1988 6 L Pedraza D Rodriguez Losada F Matia G Diss
244. ication technology Most important parameters that are used in this research are listed in table 1 Based on this proposed model each access consumes some energy considering the cache configuration and miss penalty Although any access may lead to a miss or hit however any events cause some energy dissipation 17 We have calculated the energy consumption of each cache configuration by using the proposed model which considers the effect of all parameters i e number of cache misses hits access time of cache cache level type of access read or write and static dynamic energy on the energy dissipation of the cache By using this power model we can see that there is good overlapping cache sizes for selected heterogeneous embedded applications that can be seen in fig 1 a Int l Conf Embedded Systems and Applications ESA 12 Lisize range 8 16 32 64 128 Flow class Ipv4_Ictrie Ipsec Dijkstra String_serach Susan corners L2 size range 8 16 32 64 128 Flow class Ipv4_Ictrie Ipsec Dijkstra String_serach Susan corners 85 oe L1I L2 Ave Pp to cig 5 8 12 2 3 1 83 5 4 0 1 9 6 35 3 1 3 86 8 43 4 1 4 56 c Fig 1 a overlaping rang based on HCP and LCE b HCP amp LCE points c perfromance penalty of each cache configuration Based on the performance and energy analysis results we introduce two best points for cache configuration These points are Highest Cache Performan
245. ich are added to the system and the rest of tasks taken from are considered as old tasks to form the second subset After any addition scenario the response time can be increased and or some old new tasks miss their deadlines When a reconfiguration scenario is au tomatically applied at run time the proposed agent logically decomposes the physical processor of into two virtual processors VP and VP with different utilization factors U VP and U VP to adapt the system to its environment with a minimum response time For more explaining after any reconfiguration scenario and in order to keep only two virtual proces sors in the system the proposed intelligent agent automatically merges VP and VPY into VP and creates also a new V Py named VP to adapt old and new tasks respectively The VP is assumed to be a located logical pool in idle periods of VP For example we have 2 initial tasks Ti and To in an assumed system sys with 71 T2 First we add 03 o4 and a5 to E that automatically turns into ED 1 T2 03 a4 and os In EM subset T1 T2 is considered as old tasks to be executed by VP whereas subset o3 o4 and o5 is considered as new sporadic tasks to be executed by VP V PY 1s located in idle periods of VPM We propose there after the arrival of new sporadic tasks og and o7 to be added to E that evolves into EP 4715 T2 03 04 05 06 and o7 VP and VP are automat i
246. icrophone Audio support For debugging 3 Ceiling view based localization b Segmented image c Extracted ceiling area Figure 3 Ceiling area extraction We adopt an efficient graph based segmentation to extract ceiling area and find molding line and implemented on embedded system We can obtain the molding edges immediately from the ceiling area with simple edge detection algorithm and we extracted Harris Conner feature only included in ceiling area Extracting ceiling area has two advantages at upward E 6 6 i p as shown in Figure 4 camera based robot localization First this system is scale invariant All of features are on ceiling and their depth is fixed as the distance from the mobile robot to ceiling Second the field of view of ceiling view SLAM is less likely to disturbed than front view SLAM The space between the mobile robot and the ceiling is usually empty space and the visual field is usually guaranteed The absence of moving objects is a strong point for SLAM When a camera locates on center of robot the center segmented area of the camera image belongs to ceiling area a Molding edge between ceiling and wall generally This can be strong candidate of ceiling area Then we eliminated mounted stuff such as fluorescent light or sprinkler gradually using our algorithm as shown in Figure 3 b Conner feature in ceiling area Figure 4 Ceiling area extraction a Original image As we use the ce
247. icy EDF Finally the dpfm fires all transitions in the updated sets The firing is described by the following equation VFT VT FT or Firing FT gt FT VT BMW SMIS aar SB 9 Te bha A amp M M S HEFT Fr best Br Go Int l Conf Embedded Systems and Applications ESA 12 More details about the dpfm and the firing process can be found in 13 3 2 Model construction with dPTPN In the 13 and 14 the authors have suggested a spec ification with dPTPN of the important component of the RTS the Real Time Task In fact the internal behavior of tasks 1s presented through two major patterns the first of which describes the creation the activation and the deadline model of the tasks This pattern is critical at the scheduling analysis of the RTS It is modeled for describing a stop Marking when it was a temporal fault in the system As for the second pattern it is the modeling of the al location and execution of the task on the processor The processor is a shared resource between the tasks of the same partition The allocation event is modeled through a Tep transition and the transition having the highest priority under a defined policy EDF in 13 LLF 14 allocates the processor and begins its execution The execution modeling is dedicated to discrete time and for each tic of clock the task is asked for liberation of the processor if a new coming task has the highest priority Figure Fig 4
248. id OS doesn t have support for real time operations This paper presents the development and implementation of a medical application using an Android based platform for management and visualization of an Electrocardiogram ECG signal and a specialized ASIC for data acquisition tasks which involves time critical management converting the device communications in a delicate requirement for this develop This paper describes the strategy for real time solutions on the communication process and shows results awarded in final implementation Keywords Android Embedded System Design Real Time Applications 1 Introduction The Android platform 1 is a complete set of integrated software tools It consists of an adapted version of the Linux kernel middleware application framework and a set of specialized APIs Application Programming Interfaces to develop mobile applications It was initially designed for using on mobile phones however its use has spread to a lot of heterogeneous embedded systems 2 Among the several advantages that Android offers for developing applications we may quote the following it is an open source provides a free development platform for creating mobile applications It has a large community of developers working on it and facilitates the administration of a wide range of peripherals such as sensor displays communication interfaces and others Nowadays All those features make Android one of the most attrac
249. ider performance and power analysis together At first we use the very popular performance metric called MIPS MIPS is a metric for measuring the execution speed of a computer s CPU Fig 2 d shows the result of comparing MIPS of all 12 configurations The most important result from this figure is that MIPS exploration shows that the best configurations are 5 and 9 e g L1 32 and L2 64 and L1 64 and L2 128 KB So to reach the highest MIPS and in another view highest performance designer should select configuration 5 or 9 As mentioned before from one point of view we want to reach the highest performance per power for selected embedded applications and from other point of view we want to consider performance per area 4 5 Power delay product PDP and MIPS per power Since power consumption varies depending on the program being executed the benchmarking issue is also relevant in assigning an average power rating In measuring power and performance together for a given program execution we may use a fused metric such as the power delay product PDP or energy delay product EDP In general the PDP based formulations are more appropriate for low power portable system in which battery life is the primary concern of energy efficiency PDP being dimensionally equal to energy is the natural metric for such systems Lower PDP means better architecture for such kind of systems Fig 2 e shows the results of PDP exploration for all 12 configur
250. ies 44 Filter 4 1 0 8 0 6 0 5 1 1 5 2 2 5 3 3 5 Time 30 Secs x 10 Fig 4 4a Unfiltered sSEMG Signal from the Proposed Acquisition System Using DE 3 1 Electrodes 4b Filtered SEMG signal with Wavelet Daubechies 44 Filter The following experiment was repeated several times to check the consistency and the accuracy of the proposed acquisition system Fig 5 and 6 show the validation for the proposed acquisition system for repeated experiments using DE 2 1 and DE 3 1 electrodes 5a Unfiltered sEMG Signal i i ne eee 05 474 Danae TTT 1 ati Tia SUGeneeel WM A I IM IE M I MI A i Ii W M A 0 i I bali l j p i hd mT Mp Ih il wi vi Nn i all lit Ul i il Wh ih ii IN W i ae ii I HW Ih i ji TT 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 a 4 x 10 lt 5b Filtered sEMG Signal with Wavelet Doubechies 44 Filter 1 0 5 i l 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 Time 30 Secs x10 Fig 5 Sa Unfiltered sSEMG Signal from the Proposed Acquisition System Using DE 2 1 Electrodes 4b Filtered SEMG signal with Wavelet Daubechies 44 Filter 146 6a Unfiltered sEMG Signal 1 ii HAA A AAAA T U SA j AMA IME NW WH MLA l i Muh i i TER A ii I WN i Ll Ll Al ul i Mt i tl Ih L i IN AVL S in
251. ies grow and as the standards are implemented it is envisioned that appliances will be available with the proposed home automation system Homeowners will simply log on to their computers and add their new devices to their home automation networks This system will have a significant impact on the home automation industry in the realm of energy conservation and environmentalism The proposed system will merge the luxury of home automation controls with the necessity of reducing energy consumption Int l Conf Embedded Systems and Applications ESA 12 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 References S I Rodriguez M S Roman S C Sturhahn and E H Terry Sustainability Assessment and Reporting for the University of Michigan s Ann Arbor Campus Internet http css snre umich edu css_doc CSS02 04 pdf and http axiomamuse files wordpress com 2010 12 sustain ability_spheres1 png 3 March 2011 Institute of Electrical and Electronics Engineers Inc IEEE Std 802 15 4 2003 Wireless Medium Access Control MAC and _ PhysicalLayer PHY Specifications for Low Rate Wireless Personal Area Networks LR WPANSs New York IEEE Press Oct 2003 Tasshik Shon Yongsuk Park A Hybrid Adaptive Security Framework for IEEE 802 15 4 based Wireless Sensor Networks KSII Transactions on Internet and Information Systems vol 3 no 6 Dec 2009 V Singhvi et al I
252. if it can be scheduled Such a control policy can be implemented as follows Whenever a task arrives the agent computes the processor utiliza tion of each task 7 and generates the feasible superset O feasible Which defines the different feasible subsets of tasks in achieving good periodic responsiveness where USS anD is enforced O feasible T C Currentr Feasibility T True Each subset T corresponds to a possible implementa tion of the system such that e Solution 1 Removal of Tasks Int l Conf Embedded Systems and Applications ESA 12 T Enew U fold ae Asynchronous tasks min T Di lt 1 6 In this case we remove all tasks of Enew we stock them in a list and we begin by using an acceptance test e g periodic tasks new that would cause U t to exceed this bound are not accepted for processing There are two possible cases e First case if the arrival task is hard then it will be accepted and we will randomly remove another soft task from the 1 n j 1 previ ous tasks to be rejected and still guaranteeing a feasible system e Second case if the arrival task is soft it will be dropped rejected immediately The Ci min Ti Di superset Q feasible Which defines the different feasible subsets of tasks The agent suggests all possible combinations of tasks for users who have the ability to choose the best com bination that satisfies functional requirements Running Example The agent shou
253. igh level synthesis co design environment from another viewpoint of granularity of operations and I Os and introduced an I O library composed of hardware and device drivers We choose the Java as both a programming language 135 and a software execution environment and use the JNI for handshake between synthesized hardware and Java applications In addition we showed an example of application of our co design method that calculates the AES CMAC with actual source codes to explain the whole automatic translation path from Java source codes to hardware Also we discussed the generality of this co design method brought by Java and JNI 7 References 1 Josef Fleischmann Klaus Buchenrieder Rainer Kress Codesign of embedded systems based on Java and reconfigurable hardware components DATE 99 Proceedings of the conference on Design automation and test in Europe January 1999 2 David Hwang Bo Cheng Lai Patrick Schaumont Kazuo Sakiyama Yi Fan Shenglin Yang Alireza Hodjat Ingrid Verbauwhede Design flow for HW SW acceleration transparency in the thumbpod secure embedded system DAC 03 Proceedings of the 40th annual Design Automation Conference June 2003 3 Sheng Liang The Java Native Interface Programmer s Guide and Specification Addison Wesley 1999 4 ARM AMBA 3 APB Protocol Specification v1 0 http www arm com 2004 5 JH Song R Poovendran J Lee T Iwata RFC4493 The AES CMAC Alg
254. iling images as measurement input the line feature is the most suitable feature in view of the indoor SLAM Thus we need more structural features which are robust to environmental variations and contain structural information like direction and size Moreover the structural information can be used as a simple descriptor which is significantly helpful for correct data association The ceiling has a strongly robust structural feature that is the boundary between the ceiling and the wall at the sides and the boundary 108 Int l Conf Embedded Systems and Applications ESA 12 of rectangular electric lights Any kind of the ceiling has these boundaries and they are apparently detected in any situations like dark bright rotated or translated In addition for its flatness the ceiling can be abstracted in 2 D space 2 D representation of lines can achieve significant reduction of computational and memory cost The lines on the ceiling are parameterized by just two parameters p and which are the length and angle of the perpendicular foot from the origin to the line To extract the line features we have to group the ceiling part in an image The ceiling grouping is based on some assumptions First the image center is always on the ceiling part Second the ceiling part always occupies more than half of the image With these assumptions we expanded the ceiling region from the image center until the region occupies more than half of the imag
255. ime minimization For this reason we present the function of major job arrival with deadline in the fol lowing paragraph 151 152 5 1 New function of major job arrival with deadline In the background we defined the function of job arrival with deadline Now and in order to analyze the feasibility we shall have to quantify the maximal amount of job of term less than or equal to one cer tain date was engendered on an interval of time it is the function of major job arrival with deadline This function applied to the task Tg noted limits the function of major job arrival with deadline of the task Tk On everything interval of time of duration At Sk ki Aka At Aka F d lt Sk At d VAK j the beginning of the interval in which the function is estimated gt 0 VAt gt 0 Vd gt 0 We assume now the case where Dkn Akn D Vk n We consider an interval of time Ak j Ak Atl We know that most high time of execution of an in stance is Ck Let us determine the maximum num ber of instances in an interval of time of the type Ak j Ak j Atl We note Ak no the first instance of Tk after Ak j and Ak n the last one before Ag At with n n no 1 the number of instances in this interval Akis Aki F Atl There are two conditions so that the job of an instance Tk i is counted it is necessary that 1 Aki lt k j At the maximum number of in stances is most big n which verifies Ak no
256. in cache design 15 annual international symposium on computer architecture ISCA 88 pp 290 298 1988 20 Mehdi Alipour and Mostafa E Salehi Design Space Exploration to Find the Optimum Cache and Register File Size for Embedded Applications 9 Int l Conf Embedded Systems and Applications Pp 214 219 ESA July 18 21 2011 21 Ramaswamy Ramaswamy Tilman Wolf PacketBench A tool for workload characterization of network processing in Proc of IEEE 6th Annual Workshop on Workload Characterization pp 42 50 Oct 2003 22 M R Guthaus J S Ringenberg D Ernst T M Austin T Mudge and R B Brown MiBench a free commercially representative embedded benchmark suite in Proceedings of the IEEE InternationalWorkshop onWorkload Characterization pp 3 14 2001 23 Sheng Li Jung Ho Ahn Jay B Brockman and Norman P Jouppi McPAT 1 0 An integrated power area and timing modeling framework for multicore architectures available online at http www hpl hp com research mcpat McPAT Alpha_ TechRep pdf 90 Int l Conf Embedded Systems and Applications ESA 12 Int l Conf Embedded Systems and Applications ESA 12 91 SESSION REAL TIME SYSTEMS EMBEDDED MODULES Chair s TBA 92 Int l Conf Embedded Systems and Applications ESA 12 Int l Conf Embedded Systems and Applications ESA 12 Dependability Driven Feedback Control Scheduling for Real Time Embedded Systems Ou
257. inaries con cepts and we will describe our contribution after In 2 Buttazo and Stankovic present the Guarantie Algorithm without the notion of deadline tolerance and then we will extend the algorithm in our new pro posed approach by including tolerance indicator and task rejection policy For this reason and in order to more explain these notions we will present some pre liminaries 3 1 PRELIMINARIES denotes a set of active sporadic tasks g ordered by increasing deadline in a linked list 0 being the task with the shortest absolute deadline a denotes the arrival time of task o i e the time at which the task is activated and becomes ready to execute C denotes the maximum computation time of task o i e the worst case execution time WCET needed for the processor to execute task o without interruption ci denotes the dynamic computation time of task o i e the remaining worst case execution time needed for the processor at the current time to complete task Oi k without interruption d denotes the absolute deadline of task 7 i e the time before which the task should complete its execu tion without causing any damage to the system D denotes the relative deadline of task o i e the 163 164 time interval between the arrival time and the abso lute deadline S denotes the first start time of task Oi 1 e the time at which task g gains the processor for the first time s denotes the las
258. ing any backup software that facilitate backup and recovery Although NAS confers some protection against data loss due to hard drive failure but here are still relatively common occurrences like Hard disk drive failure IT Admin or user error Software error Firmware upgrade failed or firmware corruption controller failure Disaster and Crime First two data loss causes having the partnership of more than 75 Depending on the type of data loss that occurs it may be possible to recover most if not all of the data using various data recovery existing methods 3 1 Hard disk drive failure Manufacturers of magmatic hard drive quote average hard drive life as Mean Time Between Failures MTBF These manufacturers claim hard drive MTBF 500 000 to 1 5 million hours These drives will continue work 57 to 171 years 24x7 year having average failure rate of at 1 754 to 0 585 per year However the study showed typical annual replacement rates of among 2 and 4 and up to 13 observed on some systems 8 Hard disk drive is a combination of electrical mechanical and magnetic component Its most of components are hermetically sealed on a chamber to forbid dust humidity and air flow There are various palpable points of failure in a hard disk as a very sensitive magnetic read write heads move above across the 7200 10000 RPM spinning disks the disk motor head assembly actuator motor electronics controls microchip and Firmware
259. ing a model based approach for embedded systems However it is not easy for normal developers to adapt them to real 58 embedded systems directly because they require additional tasks like making translator or instrument software codes In this paper what we are trying to do is not to develop a modeling language such as UML nor a generalized designing process in developing embedded applications Instead we describe the development process of a large embedded application based on our proposed two step model on a specific RTOS and show how it works in developing real embedded system by a case study This is the difference between our work and the rest of the other works 3 AVOS In this section we introduce our RTOS referred to as AVOS Our model can be adapted to any kinds of RTOS but it 1s always good to have a reference for illustration The AVOS is a small sized RTOS for 32 bit ARM based microprocessor It supports OS APIs corresponding to OSEK OS APIs and adopts the philosophy of OSEK OS OSEK is the international standard for automotive ECUs and well defined set of APIs 4 Though some RTOS supports the dynamic memory allocation at runtime 10 all system memory should be reserved before the actual application is running for more accurate prediction of program behavior AVOS keeps minimal sized kernel while supporting network stack GUI and file system due to its modularized structure Table 1 Comparison in some part of two
260. ing code is compiled and is executed on emulator automatically Finally the ACSF try to detect errors in logs generated from the software In this paper we show several components of the tool and explain characteristics of the tool in detail Developers who use the tool can fix problems of their software which are related with portability on the porting process easily and quickly The rest of the paper is organized as follows Section 2 describes related works and ACSF we suggested Section 3 then presents characteristics of the tool in detail Finally Section 4 concludes and explains future works 2 Related works 2 1 Previous Test Techniques To test android software is needed to verify whether functions of the software have some problems or not Developers usually use a tool or framework for functionality test such as JUnit 4 Robotium 6 Android Testing Framework 1 Those solutions support developers to make test case for testing android software easily For instance JUnit for android has a function to generate test source for Activity Intent and so on Developer can define an action when an activity is creating or destroying via the function of JUnit In testing phase with JUnit once developer makes a test case using them and then they run the test case Android software is GUI software therefore it require GUI test which verify to be executed well by some GUI Int l Conf Embedded Systems and Applications ESA 12
261. ingle block garbage collection technique 6 Conclusion In this paper we have studied the operational mecha nisms and the computational overheads of garbage collection The garbage collection was found to have too much computa tional overhead to find victim blocks resulting in unendura ble host system access latency very low responsiveness and performance degradation However the proposed 2LGC_ garbage collection scheme eliminated the computational overheads due to victim block selection from the critical path of the garbage collection operations The responsiveness to host system requests was also improved by making the garbage collection operation preemptive The 2LGC scheme achieved significant performance improvement in flash storage bandwidth and request processing latency in comparison to the on demand victim selection technique in our experiments 7 Acknowledgement This work was supported by the National Research Foundation of Korea NRF grant funded by the Korea gov ernment MEST No 2011 0017147 Int l Conf Embedded Systems and Applications ESA 12 On demand victim selection 2 2LGC 1200 1200 a a a S enlaces inital alae te mma A clin intact site 900 T l V T 900 n N a 600 S 600 300 300 0 0 0 50 100 150 200 0 50 100 150 200 Time interval Time interval a 2500 2500
262. iojo jams 7 6 e h mos Figure 9 Planning State Machine for beginning Interface JPEG_USB_IF The reason for an internal buffer within JPEG_IF shown in Figure 9 is to correctly align the incoming 16 bits of data from the USB module into the 24 bits of data that the JPEG encoder module requires For the first 16 bits coming from the USB module it holds only 2 3 of the Ist pixel data then the second 16 bits of input data contains the last 1 3 of the Ist pixel data and the first 1 3 of the 2nd pixel data so on and so forth The buffer size is appropriately sized in terms of being the least common denominator of 16 and 24 bits so data going into from this internal buffer will not have any skewed unaligned outputs or inputs which greatly decreases code complexity Therefore the module uses 3 clocks of 16 bit data in order to output 2 clocks of 24 bit data into the JPEG encoder and continue to do so until the end of the raw pixel input Int l Conf Embedded Systems and Applications ESA 12 5 5 Developing the ending interconnecting module The purpose of the Combine_final_data module is to format the data output of the JPEG_ENC into a suitable format that the USB_IF module can use to send it back to the host computer The input data to this module is a 32 bit JPEG_bitstream that is outputted from the jpeg_enc module as well as 7 bit control bits such as end_of
263. ions ESA 12 worn by the subject The body sensor network implemented in this solution is considered as an invasive technology and requires special treatment by users with respect to proper body placements battery replacement etc Stroiescu Daly and Kuris presented the design for wireless event detection and in building location awareness system 5 This system used a body worn sensor to detect events such as falls when they occur in an assisted living environment Event detection algorithms were developed and used an in house wireless network to transmit the information to the assisted living facility and to an off site monitoring facility The project did not provide enough data to validate the system or associated algorithms Few of the limitations are low battery life and the need for frequent charging incapability to integrate the sensor into a garment and not being water resistant Fleck and Staber presented a distributed and automated smart camera based approach to analyze the real world and identify only relevant information that could be used for geo referenced person tracking and activity recognition in case of a fall 6 The performance of the system relied on the performance of the automated video analysis algorithms These would not complement the human operators but replace them from sensor level all the way up to a level where the information is not directly privacy related anymore Park et al suggested a method t
264. ions To validate our model it was adapted to a menu driven GUI application on our RTOS called AVOS This paper is organized as follows Related works are given in Section 2 and AVOS is in detail presented in Section 3 and the modeling approach for large embedded applications is proposed in Section 4 The case study and conclusion are given in Section 5 and Section 6 respectively 2 Related work There are some research works with model based approach for designing embedded applications and systems UML modeling language is typically used to describe the embedded system 1 and the paper 5 developed a model based approach called MARMOT MARMOT s product and process models facilitate component based structuring and reuse in embedded systems It states that UML is a powerful tool to apply object oriented and component based design J C Maeng et al 3 introduced RTOS API translator using a model driven approach This approach derives generic RTOS APIs from application behavior model and then RTOS specific code is produced by API translator Z Karakehayov 6 presented a hierarchical design model for large and complex distributed embedded systems M Muller et al 7 proposed RTOS aware modeling for embedded systems which is to refine highly abstract application models automatically with platform characteristics This approach requires automatic calculation and instrumentation of software runtimes They made achievement in develop
265. is work is a signifi cant extension to the state of the art of EDF schedul ing and discusses experimental results of the proposed approach research Section 5 summarizes the main results and presents the conclusion of the proposed approach and describes the intended future works Int l Conf Embedded Systems and Applications ESA 12 2 BACKGROUND We present related works dealing with reconfigura tions and real time scheduling of embedded systems According to 7 each periodic task is described by an initial offset a activation time a worst case execu tion time WCET C a relative deadline D and a period Tj According to 2 each sporadic task is described by minimum interarrival time P which is assumed to be equal to its relative deadline D and a worst case execution time WCET C Hence a sporadic task set will be denoted as follows Sys a C Di i 1 to m Reconfiguration policies in the current paper are classically distinguished into two strategies static and dynamic reconfigurations Static recon figurations are applied off line to modify the assumed system before any system cold start whereas dynamic reconfigurations are dynamically applied at run time which can be further divided into two cases man ual reconfigurations applied by users and automatic reconfigurations applied by intelligent agents 7 4 This paper focuses on the dynamic reconfigurations of assumed mixture of off line and on lin
266. it was possible to estimated and take into account the potential latency between the core and system clocks Thus assuming that a signal is using edge sensitive interrupts it will take at least 5 SCLK cycles to register the interrupt Approximately 10 CCLK cycles to go to vector the interrupt service routine and push the appropriate registers to the stack save state and around 3 CCLK cycles add to 2 SCLK cycles to load the register and then changes the output of the port pin It means the process will result in at least 20 cycles of latency only for detecting and recognizing the interrupt generated by one external signal Also the approach for performance measurements often considers the amounts of instructions for execution of a specific task This metric is so called MIPS Millions of Instructions per Second Therefore considering that the software processor is capable of performing both operations addition and multiplication in one single clock cycle from decentralizing the loop program to a dedicated circuit the capacity of expansion in MIPS for this PE grows exponentially as the complexity of the code increases Thus it is able to execute more than 570 MIPS when SAD 64x64 is off loaded Concerning the power efficiency Figure 5 shows the consumption by the internal and external modules of the 400 software processor 350 300 250 200 150 100 50 0 11 2 1 3 1 4 1 5 Agag Freq Ratio between CCLK and SCLK 300
267. ith more than one connection 29 and 30 When the upper bound of the maximum number of sub tasks over network Pimax Where i depends on the number of processors are given one can use LMIs inequality to find the number of sampling intervals and maximum time delay dimax for which LMIs holds and consequently stability of all jobs on network holds 9 Practical Implementation The implementation of Dependability driven feedback based control scheduling for real time embedded systems is done on an industrial system Embedded software architecture of mining cranes which consists of an Operator control unit OCU and a Machine Control Unit MCU Both OCU and MCU contain two microcontrollers Renesas dual core V850E2 Mx4 31 which is the most popular microcontroller used in motor industry for industrial automation and it contains a built in I2C for multi processor communication OCU has multi level push button keypad installed at the outer surface Each button is a three steps press push button to control the speed of the machine attached with MCU Both OCU and MCU has Radio Frequency Identification RFID chip OCU and MCU communicate through RFID module 35 RFID chip contains OCU identification number and the address of that particular OCU This information is transmitted through RFID module in the form of a telegram Each telegram is 32 byte information and contains a start sequence telegram identification bytes timing information data
268. ity The complete operation of the priority encoder is further illustrated using the truth table given in the Appendix IHI SIMULATION METHOD AND RESULTS Four 8 bit dynamic CMOS priority encoders including the proposed design have been designed at the transistor level and simulated using Tanner tools based on 0 25um bulk CMOS process technology with a supply voltage of 2 5V and their corresponding power and delay metrics were estimated using TSPICE The functionality of all the priority encoder modules was completely verified using SPICE simulations by feeding in distinct test vectors at a nominal data rate of 500Hz The total power dissipation and critical path delay metrics of different 8 bit dynamic CMOS priority encoders are given in Table 1 along with the device count required for physical design The device count in terms of number of transistors is assumed to be representative of the area occupancy of the circuit PDP stands for power delay product and EDP refers to energy delay product in the Table below TABLE I COMPARISON OF DESIGN PARAMETERS OF DIFFERENT 8 BIT DYNAMIC CMOS PRIORITY ENCODERS Design metrics 2 85 5 47 0 28 0 26 0 25 The device count of the proposed 8 bit priority encoder module equates to just 55 transistors much less than the 102 transistors dynamic 8 bit priority encoder block presented by Huang et al 6 and more optimized in comparison with the 62 transistors 8 bit dynamic priority encod
269. l assuming that the pacemaker and heart are declared with a reasonable set of input parameters e g VRP 320 msec etc e A not deadlock check for deadlock freedom e A not P hysteresis and P WaitBeat imply P y lt P LRI the minimum interval between pacing and sensing events is the lower rate interval LRI with no hysteresis e A P hysteresis and P WaitBeat imply P y lt P URI the minimum interval between events is the upper rate interval with hysteresis e A P WaitBeat imply P y gt P VRP while waiting for a heart beat the pacemaker must wait for the ventricle refactory period VRP to expire before sensing or pacing and e P WaitBeat gt P WaitVRP being in the state waiting on a heartbeat always leads to being in the state waiting on the VRP to pass 4 Conclusions Biomedical electronic systems are increasing in both complexity and functionality It is vital to have an understanding of both the human body and the embedded computer software in order to implement functional and reliable systems This framework is a step in this direction bridging the gap between biology electrical and computer engineering and computer science In this paper we described a relatively inexpensive extensible framework that can be used to design new academic pacemakers and analyze existing designs The goal of this framework is to provide a convenient platform that can be used
270. l execution time of SC task deviates from 116 to 140 of its estimated completion execution time For Slave microcontroller g 1 35 1 55 which means that the actual execution time of SC tasks on slave processor deviates from 135 to 155 of its estimated completion execution time Both microcontrollers have different values of g because total number of tasks executed on Slave microprocessor is more than Master microcontroller Table 2 CPU Utilization of FCSA with and without dependability integration for 2 SC tasks including 4 transient faults SC Non CPU CPU CPU SC task Tasks SC Type Utilization of Utilizat execution Tasks Dependability ion of overhead driven FCSA FCSA Steady state response of Master and Slave CPUs are shown in Fig 9 Both CPUs are robust against uncertain task variation Initially both CPUs are underutilized due to System model estimation inaccuracies but model become more accurate later Variation of task execution time is evident at sampling interval 300 where g 1 26 126 execution overhead of SC task and at sampling interval 700 where g 1 30 130 for master CPU and at 300 g 1 30 130 execution deviation at 600 g 1 35 135 execution deviation SC Core CPU 1 SC Core CPU 2 gt T sidani 7 iii Mant ottein EE e j j A f j a 1 A A d j Figure 8 CPU Utilization for Experiment 1 For the second experiment variation in g 0 6 2 40 for Master microcontr
271. l processing quite often bandpass sampling where low sampling frequency is used Even processing at aliasing frequency the normalized frequency is still very high Fig 3 shows an example where a 60MHz IF signal is sampled at 72MHz Only 6 samples Bandpass Sampling of 60 MHz IF with 72 MHz ADC 100 r _ 50 wave magnitude oO 50H 60 1 20 1 80 240 300 360 aliasing wave phase degree tick as sample clock Fig 3 Relative high normalized frequency often used in bandpass RF IF sampling with only few samples per cycle to be used for derivatives 60MHz IF in green 12MHz in blue with dash line represents sampled wave while solid line for the analog wave sample frequency as 72MHZ every 60 degrees of the aliasing wave per cycle can be obtained even at the relatively lower aliasing frequency 12MHz Therefore the assumption in equation 4 is not valid and considerable error will be resulted for the derivative as shown in Fig 4 the phase error between the ideal derivative when T is tiny shown in cyan and the actual one when T is corresponding to 60 degree shown in red is corresponding to about half of the sampling period 65 66 Phase Error Derivative of ADC Samples wave magnitude 100 i 2 0 60 120 180 240 300 360 tick as sample clock Fig 4 The challenge for phase detection from ADC wave when bandpass
272. l skew or deterioration the phase could not be correctly shifted in the hardware In the experiment for a control circuit in which the glitch width was changed the glitch width was measured five times using an oscilloscope and the average was used 4 2 Fault Generation Experiment In the AES_KL a path with 0 8 16 or 24 bits was lengthened to correspond to the least significant bit LSB of the state at the third column in the key generation section An investigation was then made to determine whether a fault was generated in the lengthened path Figure 4 shows the experimental results obtained when the glitch width was set to 10 78 ns Int l Conf Embedded Systems and Applications ESA 12 13 Glitch width 10 78ns Output cipher text ee ae D Correct cipher text CIII Position of registers and wiring g on oe pmccesns unit Wrong cipher text with fault Ty Wl Ml Ty N Generated fault position on 9R of Key generation processing i i H Concentrated a he Ha RU initi HIR Su lL Position of registers and wiring on z aioi unit nira TAH iii Dispersed 1 placement Glitch width 10 78ns Output cipher text Correct cipher text IIIT Wrong cipher text with fault ii Hii Tis Generated fault position on 9R of Key generation processing Glitch width 10 78ns Output cipher text Correct cipher text CT TT 11T a Bull 3 y fick ti ri l Wrong ciphe
273. lated work Real time applications have become a necessity for some embedded and mobile systems Android features facilitate the development tasks however it is known the Android platform doesn t have reliable support for real time applications Some strategies have been explored searching a solution for this trouble Specifically four solutions have been proposed in 5 The first approach contemplates the replacement of the Linux operating system by one that offers real time features and it considers the inclusion of a real time Virtual Machine VM The second one respects the Android standard architecture by proposing the extension of Dalvik 6 as well as the substitution of the standard operating system by a real time Linux based operating system The third one only substitutes the Linux operating system for a Linux real time Int l Conf Embedded Systems and Applications ESA 12 version and real time applications use the kernel directly Finally the fourth one suggests the addition of a real time hypervisor that supports the parallel execution of the Android platform in one partition while the other partition is dedicated to the real time applications Solutions previously mentioned have a complex background They suggest delicate modifications to the virtual machine and or kernel lawyer inside the Android s standard architecture This kind of modifications implicates a detailed knowledge about the operator system and _ int
274. lculated by the intelligent Agent Solution 1 Solution 2 Solution 8 Solution 4 Solution 5 and Solution 6 by the following expression Resp min Respz1 Respr2 Respe3 Respx a Respk 5 and Resp k e the minimum of the six val ues So the calculation of Resp allows us to obtain and to calculate the minimizations of response times values and to get the optimum of these values 3 3 The General OEDF Scheduling Strategy When dealing with the deadline tolerance factor mi each task has to be computed with respect to the deadline tolerance factor Algorithm GUARANTEE ca begin t get current time Ro 0 do t Insert o in the ordered task list E E U oa k position of ga in the task set for each task g such that i gt k do R Rii ar d d _1 if R gt 0 then return Guaranteed else return You can try by using solution 1 or You can try by using solution 2 or You can try by using solution 3 or You can try by using solution 4 or You can try by using solution 5 or You can try by using solution 6 e Compute Respk 1 Compute e Compute Resp 2 Respx 3 Compute Resp 4 Int l Conf Embedded Systems and Applications ESA 12 e Compute Respz 5 e Compute Resp z e Generate Resp end This algorithm assumes that sporadic tasks span no more than one hyperperiod of the periodi
275. ld react to propose useful solutions for users in order to re obtain the system s feasibility In our Volvo system the agent proposes the task C to be removed to re obtain the system s feasibility The processor utilization factor U becomes equal to 0 954 after removing the task C and the task set becomes schedulable feasible agent computes the processor utilization of each task 7 and generates the feasible 4 3 Second Case Meeting deadlines of periodic tasks e Solution 1 Modification of Periods 2 The agent proceeds as a second solution to change the periods of tasks of Eney and ola To obtain a feasible system the following formula should be satisfied Ser Ci n2 n Ci _ min T D T De n j 1 min Ti Di 80 1 Where j 0 11 yee Ci i n j 1 min Ti Di 8 Let a be Tas Gy ARIS as St Ce Ta n NIO 1 Dial min T D mied R Dae a1 min RE Se C apse ny j 1 S bj E See j Ci i 1 min Ti Di i The new See of T tasks is therefore deduced from bj running example constante The agent should react to propose useful solutions for users in order to re obtain the system s feasibility In our Volvo system the agent computes the constant values 3 j 0 5 corresponding respectively as fol lows Go 43 G1 77 until Gs 42 time units where Loa and new 14 B D E F C G A The processor utilization factor U becomes equal to 0 942 after up
276. le aM Automation Acquire log Execute Component Automation Communicati Repository Reporte Log Analysis Component Log Analyzer Report Gen Report Template on Module i Log Gen il Figure 1 Architecture of Portability Analysis Tool A process of android software is very similar development phase of embedded software Testing software on emulator or real device is vital element in development of the embedded software A testing on emulator is rather important than a testing real device because a testing on real one takes more time and it is difficult to test whole devices due to its price Moreover it needs more tasks for testing For instance once developer prepares a device and copy software in the device And then they tests software using the device After testing they move a log which is made during running the software to the desktop computer Finally they analyze the log However testing on emulator it just requires configuration of emulator Architecture of ACSF is based on conceptual development process for android _ software 8 The Architecture is largely divided into five components The 137 program analysis component analyzes software for making an Analysis Information which contains scope of analysis The monitoring code generating component makes a meta file and generate source code as a test case using the meta file 3 9 The program auto test compo
277. le Fault Proc of 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography FDTC pp 35 42 2011 2 Chong Hee Kim J J Quisquater Faults Injection Methods and Fault Attacks IEEE Design amp Test of Computers Vol 24 No 6 pp 544 545 2007 3 Gaoli Wang Shaohui Wang Differential Fault Analysis on PRESENT Key Schedule Proc of 2010 International Conference on Computational Intelligence and Security CIS pp 362 366 2010 Int l Conf Embedded Systems and Applications ESA 12 4 Wei Li Dawu Gu Yong Wang Juanru Li Zhiqiang Liu An Extension of Differential Fault Analysis on AES Proc of Third International Conference on Network and System Security NSS pp 443 446 2009 5 P Maistri R Leveugle Double Data Rate Computation as a Countermeasure against Fault Analysis IEEE Transactions on Computers Vol 57 No 11 pp 1528 1539 2008 6 Li Yang K Ohta K Sakiyama New Fault Based Side Channel Attack Using Fault Sensitivity IEEE Trans on Information Forensics and Security Vol 7 Issue 1 Part 1 pp 88 97 2012 7 Z Wang M Karpovsky A Joshi Secure Multipliers Resilient to Strong Fault Injection Attacks Using Multilinear Arithmetic Codes EEE Trans on Very Large Scale Integration VLSI Systems pp 1 13 2011 8 H Li S Moore Security evaluation at design time against optical fault injection attacks IEE Proc on Information Security Vol 153 Issue 1 pp 3 11 2006 9 A
278. lectrical impedance and acceleration in two dimensions and it can generate pacing pulses for the ventricle or atrium as shown in Figure 7 The overall software architecture is shown in Figure 8 The Device Controller Monitor is executed on a laptop and is used to program the pacemaker On the pacemaker three real time tasks are executed The Pulse Generator runs at the highest priority the DCM Agent ECG Transmitter at the next highest priority and finally the idle task These three tasks are executed on top of the FreeRTOS real time operating system http www freertos org The Pulse Generator is responsible for generating electrical pulses as needed to keep the heart Int l Conf Embedded Systems and Applications ESA 12 operating Thus it is the most critical task The DCM Agent ECG Transmitter interacts with the DCM Manager to enable a cardiologist to reprogram the pacemaker parameters or select a different pacing mode e g update parameters stored in the EEPROM and passed to the Pulse Generator It is also used to used to pass real time ECG data to the DCM Manager This data is displayed as shown in Figure 6 Pacemaker Device Controller Monitor Pulse Generator DCM Agent ECG Transmitter FreeRTOS USB 6008 NI Signal Express or PDAQtools DAQ monitor controller Figure 8 Software architecture The pacemaker is controlled by a Microchip PIC 18F4520 with a limit of 32KB of program memory flash memory to
279. led file for application on PC should be transferred to the target embedded system to be tested It takes much time if the file size 1s too big If there is a formal way e g model in developing embedded applications the cost and time can be reduced by minimizing the number of trials and errors 3 6 For a large embedded application it is an obvious fact In many cases a This work was supported in part by the IT R amp D program of Ministry of Knowledge Economy Institute for Information Technology Advancement Republic of Korea under Grant no 10035470 Development of Audio Video Group Communication System Platform in Mobile Ad hoc Environment large application can be divided into smaller sub applications which have some dependencies among them each other 11 In this case sub applications can be written and tested individually and then they are combined together for efficient and reliable integration later 2 This divide and conquer approach is very useful for a collaborative team project in which each member takes a responsibility for a part of the whole application and the divided parts are combined later In this paper we introduce a two step model for developing a large RTOS application for embedded systems The first step is to describe the sub application by drawing the relationship between functions and threads and the second step is to describe the overall application by presenting how to interconnect the sub applicat
280. lgorithm calculation as shown in next Section 4 Results Once the snippets performed by different modules of the architecture were defined it was possible compare some metrics that show the feasibility to decentralize the loop programs to a dedicated hardware Concerning the software processor as mentioned before we have considered an optimized code written in language C and executed by Blackfin ADSP BF533 simulator To measure the performance enhancement for this processor a specific function was used to count the clock cycles 20 taking in account all factor concerning the architecture such as memory access latency etc 3 50E 003 3 00E 003 2 50E 003 2 00E 003 1 50E 003 Time s 1 00E 003 5 00E 004 64X64 0 00E 000 8X8 16X8 16x16 SAD 32X16 32X32 64X32 Figure 3 Performance results for the software processor computing the SAD algorithm The first analyses show that before split the code the time spent by software processor is really high For the worst case when the processor is running at 100 MHz it achieves almost 3 ms to perform one macro block 64x64 per frame The all values obtained to compute the algorithm is depicted by Figure 3 Int l Conf Embedded Systems and Applications ESA 12 Table I presents the relationship between the frequencies which control the bus SCLK and the core of the DSP CCLK These values correspond how much faster is the core in relation to the frequency of t
281. litates data transfer access grant to any one output pin Either the least significant or most significant input bit of a data word can be assigned the highest priority The priority encoder can be thought of as a combined multiplexing demultiplexing unit In a priority encoder priority token is passed sequentially from the highest priority bit to the lowest priority bit as the high priority bits lose their priority Thus the maximum operating speed of a priority encoder module is usually dependent on the propagation delay encountered by the priority token while traversing a signal path of descending priority assignment In This research work was performed when the author was affiliated with the Department of Electronics and Communication Engineering Vel Tech Technical University Avadi Chennai 600 062 TN India P Balasubramanian Department of Electronics and Communication Engineering S A Engg College aff to Anna Univ Chennai 600 077 TN India spbalan04 gmail com K Prasad Department of Electrical and Electronic Engineering Auckland University of Technology Auckland 1142 New Zealand krishnamachar prasad aut ac nz other words the critical path delay of a priority encoder is proportional to the number of primary inputs As a result the design of a CMOS priority encoder is usually restricted to small sizes typically of the order of 4 bits or 8 bits 11 12 13 14 Moreover when such encoder blocks are realized
282. lites per plane for redundancy at an altitude of 3 34x10 km The CSAC considered is estimated to have an update interval of almost an hour with a ten meter distance error Keywords CubeSat Chip Scale Atomic Clock CSAC GPS Lunar Constellation 1 Introduction Navigation has always been a critical necessity throughout human history With the advent of the Global Positioning System GPS accurate navigation here on Earth is quickly becoming ubiquitous As people begin to explore beyond the Earth navigation will become all the more crucial Upon the return of people to the moon navigation will be just as important there as it is here on Earth not only for exploration on the moon but also for the astronauts safety GPS allows us to determine our position velocity and time PVT with a high level of accuracy here on Earth Therefore a GPS system on the moon would be just as essential of a system This research was to provide a first look at a CubeSat constellation for such a lunar GPS 1 1 The CubeSat Platform The CubeSat platform was designed by California Poly technic State University San Luis Obispo and Stanford University 6 Their purpose was to develop a pico satellite a satellite lt 1kg in weight platform and delivery system that was affordable and standardized yet robust enough for other colleges and universities to begin satellite and space research programs 6 7 8 A major constraint and challenge of
283. lly Certainly it is a great advantage to run these codes into parallel manner However it is not a trivial task to do mainly when the codes have a tight data dependency between many variables Therefore several researches have been developed in order to optimize and reduce the data dependency looking for a better way to split a code In addition there are different techniques to identify the bottlenecks of a system For processor simulators it is possible to use the statistical profile tools which are provided by different manufacturers Indeed these tools are only one of the many ways that may be considered for this purpose More holistic analysis are required in order to identify which processes are overloading the CPU and the data dependency between the several variables and processes Besides it should guarantee that by splitting a code the channel of communication will have enough bandwidth in order to do not compromise the system performance Furthermore another issue to be considered is the fact that many core embedded on a chip usually work at different frequencies rates Thus the latency to synchronize these processes should be considered 2 2 Measuring the enhancement performance FPGAs have been used for reconfigurable and parallel computing systems 13 This work shows the feasibility of a complex algorithm being processed in parallel Thus it was analyzed the performance enhancement using a reconfigurable hardwa
284. m is efficiently de signed There has been much research 8 15 on efficient gar bage collection techniques and various victim block selection methods that cut down on operational overhead have been proposed However these research studies have only focused on victim block selection methodologies and have not pro posed any solutions for the cost overhead of victim selection processes Indeed the host system quite often suffers unen durable storage access delays because garbage collection produces great computational overhead when performing victim selection processes Therefore the storage access performance and responsiveness of flash storage can be im proved by reducing the cost overhead of victim selection processes Int l Conf Embedded Systems and Applications ESA 12 A novel garbage collection mechanism known as Two Level list based Garbage Collection 2LGC is proposed in this paper In the proposed scheme the FTL stores block addresses into two level lists when the numbers of invalid marked pages in those blocks pass a threshold The stacked block map addresses in two level lists are used for victim selection processes The FTL can efficiently reduce the vic tim block selection overhead in this manner hence the re sponsiveness to host requests is significantly improved Flash storage performance was analyzed using a flash storage prototype platform 16 which consists of hardware parts 1 e NAND flash controllers m
285. m of jobs arriving at irregu lar intervals Soft deadline aperiodic tasks typically re quire a fast average response time Sporadic tasks A sporadic task is an aperiodic task with a hard deadline and a minimum interarrival time Mok 1983 Note that without a minimum interarrival time restriction it is impossible to guarantee that a sporadic task s deadline would always be met To meet the timing constraints of the system a scheduler must coordi nate the use of all system resources using a set of well understood real time scheduling algorithms that meet the following objectives Guarantee that tasks with hard timing constraints will always meet their dead lines Attain a high degree of schedulable utilization for hard deadline tasks periodic and sporadic tasks Schedulable utilization is the degree of resource uti lization at or below which all hard deadlines can be guaranteed The schedulable utilization attainable by an algorithm is a measure of the algorithm s utility the higher the schedulable utilization the more appli cable the algorithm is for a range of real time systems Provide fast average response times for tasks with soft deadlines aperiodic tasks Ensure scheduling stabil ity under transient overload In some applications such as radar tracking an overload situation can de velop in which the computation requirements of the system exceed the schedulable resource utilization A scheduler is said to be stable if
286. mair Naseer Arshad jhumka Atif Ali Khan Department of Computer Science University of Warwick Coventry UK School of Engineering University of Warwick Coventry UK O naseer wariwck ac uk 7H A Jhumka wariwck ac uk Atif khan warwick ac uk Abstract Use of Feedback Control Scheduling Algorithm FCSA in the control scheduling co design of real time embedded system has increased since some years ago to provide the Quality of Service QoS in terms of overall CPU performance and resource allocation in open and unpredictable environment FCSA uses control feedback loop to keep CPU utilization under desired unitization bound by avoiding overloading and deadline miss ratio FCSA design methodology is based on the principles of separation of concerns and doesn t guarantee that the Safety Critical SC tasks will meet their deadlines in the presence of faults In order to provide the services that can justifiability be trusted dependability has to be integrated in the control scheduling co design of real time embedded systems This paper presented a novel methodology of designing a dependability driven feedback control scheduling for real time embedded systems This procedure is important for control scheduling co design for real time embedded systems Keywords Dependability Real time Embedded System Quality of Service Feedback based control scheduling Control Scheduling Co design 1 Introduction Since some year
287. maker to reprogram the pacemaker Once a user connects to a given pacemaker and optionally reprograms the parameters then real time ECG data can be transmitted periodically from a DCM agent Int l Conf Embedded Systems and Applications ESA 12 running on the pacemaker board back to the DCM The pacemaker parameters are also recorded in an EEPROM on the pacemaker board so that it can continue to operate in disconnected mode without intervention from the DCM The Pulse Generator PG on the pacemaker board is responsible for sensing and generating pulsing signals as needed to keep the patient s heart beating To facilitate automated generation of PG code we have divided the code running on the pacemaker into two different categories hardware dependent and hardware independent The Hardware Abstraction Layer HAL provides the majority of the code which is not dependent on the particular hardware with a clean interface to the hardware dependent code which consists of device drivers timers etc In this way we hope to facilitate the automated generation of hardware independent code from models used to verify the correctness of the pacemaker Alnal Paong Pulte Generator 2 ae Airiai Heartbeat q ki m 7 isolator Pik d 7 EE z l ICROCHIP ee E Mi Pranegint easement e E Ventical Heartbeat i Sengr Vinica Paang Pulse Generpior Figure 7 Pulse generation and sensing using PIC 6 The pulse generator can sense heartbeats e
288. mappings Proceed ings of the ACM International Conference on ASPLOS 2009 5 Sanghyuk Jung Yangsup Lee and Yong Ho Song A process aware hot cold identification scheme for flash memory storage systems IEEE Transactions on Consumer Electronics vol 56 no 2 pp 339 347 May 2010 6 Li Pin Chang Tei Wei Kuo and Shi Wu Lo Real time garbage collection for flash memory storage systems of 28 real time embedded systems ACM Transactions on Embed ded Computing Systems vol 3 no 4 November 2004 7 Ohhoon Kwon Kern Koh Jaewoo Lee Hyokyung Hahn FeGC An efficient garbage collection scheme for flash memory based storage systems The Journal of Systems and Software pp 1507 1523 2011 8 Wu M Zwaenepoel W eNVy a non volatile main memory storage system Proceedings of the ACM Interna tional Conference on ASPLOS 1994 9 Kawaguchi A Nishioka S Motoda H A flash memory based file system Proceedings of USENIX Tech nical Conference 1995 10 Chiang M Lee P C H Chang R Cleaning algo rithms in mobile computers using flash memory Journal of Systems and Software 1999 11 Kim H Lee S A new flash memory management for flash storage system Proceedings of the COMPSAC 1999 12 Manning C Wookey YAFFS Specification Aleph One Limited 2001 13 M Systems TrueFFS Wear Leveling Mechanism 14 Chang L On effi
289. mar J P Diguet A Azzedine M Abid and J L Philippe Rtdt A static qos manager rt scheduling hw sw partitioning cad tool Microelectronics Journal 37 11 1208 1219 2006 121 122 Int l Conf Embedded Systems and Applications ESA 12 Int l Conf Embedded Systems and Applications ESA 12 123 SESSION SOFTWARE TOOLS AND ENVIRONMENTS DEVELOPMENT ISSUES EDUCATION Chair s TBA 124 Int l Conf Embedded Systems and Applications ESA 12 Int l Conf Embedded Systems and Applications ESA 12 125 Curriculum Improvements in a Microcontroller Based Embedded Systems Course Girma S Tewolde Electrical and Computer Engineering Department Kettering University Flint MI USA Abstract Microcontroller based Embedded Systems course is commonly offered in most Electrical Engineering Computer Engineering and Computer Science degree programs Microcontrollers form core components of a wide spectrum of embedded systems in use for various applications Typical course contents include material on processor architecture instruction set low and high level language programming memory models interrupts and various peripheral modules This paper presents curriculum improvements introduced in one such course at our institution and the experiences from the past two years of the course offering The main motivations for initiating the curriculum improvements are a to keep up with advancements in the technology that stud
290. mation to a host for medical tracking and recording when a patient in emergency state within a medical assistance vehicle or when he s located in other place far from a medical center The signals derived from monitoring equipment such as ECG heart rate respiratory rate oxygen saturation and blood pressure should be integrated with patient s record This information will be placed in an appropriate way at the patient s electronic medical records using a standard format in order to send it to a remote location through a wireless network whenever the medical staff requires it Figure 4 illustrates the system functionality and its environment Figure 4 System Diagram Here we focus on ECG signal acquisition process because this signal has the highest time variability and therefore it demands resources for processing tasks and high bandwidth capability 5 1 Synchronization Problem Initially the ADS1298 was directly connected to Blizzard platform through SPI ports in both devices because it was thought that the system would operate properly However the acquired signal did not show the expected behavior For example for sinusoidal test waveform we got a distorted version Figure 5 Some strategies were implemented trying to fix the problem The issue was related with the fact that the OS in the Blizzard platform does not support the real time demands of the application necessary for the communication Such a problem
291. me Environment J ACM vol 20 no 1 pp 46 61 1973 C Lu J A Stankovic G Tao and S H Son Feedback Control Real Time Scheduling Framework Modeling and Algorithms Real Time Systems J vol 23 no 1 2 pp 85 126 2002 Feng Xia and Youxian Sun Control scheduling codesign A prespective on integrating control and computing Dynamics of Continuous Discrete and Impulsive Systems Series B vol 13 no S1 2008 Jianguo Yao and Xue Liu Mingxuan Yuan Zonghua Gu Online Adaptive Utilization Control for Real Time Embedded Multiprocessor Systems ACM 2008 Payam Naghshtabrizi and Jo ao P Hespanha Analysis of Distributed Control Systems with Shared Communication and Computation Resources American Control Conference 2009 J Liu Real Time Systems Prentice Hall PTR 2000 C Lu X Wang and K X Feedback utilization control in distributed real time systems with end to end tasks Parallel and Distributed Systems IEEE Transactions on vol 16 no 6 pp 550 561 2005 CAN Specification Controller Area Network Specification and Implementation Robert Bosch GmbH http www semiconductors bosch de pdf can2spec pdf 1991 The FlexRay Group FlexRay Communications System Protocol Specification Version 2 1 http www exray com 2005 Daniel Simon NeCS INRIA and Alexandre Seuret NeCS CNRS Peter Hokayem and John Lygeros Eduardo Camacho State of the art in control computing co design The Joint Labora
292. mented wirelessly on a large scale 4 8 Such a product will offer end users the tools necessary to monitor and control the use of energy throughout their homes By using well known and well supported open source hardware and software standards long term support through existing online communities will be available The current version of the home automation system consists of a simple 120Vac 6 3A design The device plugs in to a standard 15A receptacle and provides a standard outlet rated at 6 3A Electrical measurements RMS voltage RMS 1 12 current Apparent Power True Power Kw Hr and Power Factor are taken internally An internally housed control relay provides convenient on off capability at the touch of a button while the measurements can be recorded for reference or used to automatically control the device The user can monitor and control individual devices wirelessly With the addition of a gateway an end user has access to their devices from anywhere in the world through an internet connection 3 Design Objectives The design objectives for the proposed home automation system encompass hardware and software specifications and project accessibility and are described more in what follows The hardware consists of ZigBee compatible hardware components 9 11 that are interoperable with ZigBee devices from multiple vendors In addition the hardware requires minimal user configuration and is reliable and safe for th
293. mic reconfigurable embedded control systems as an inde pendent discipline Each system is a subset of tasks Each task is caracterized by its worst case execution times WCETs C an offset starting time a a pe riod T and a deadline Di The general goal of this paper is to be reassured that any reconfiguration sce nario changing the implementation of the embedded system does not violate real time constraints i e the system is feasible and meets real time constraints even if we change its implementation and to correctly allow the minimization of the response time of this system after any reconfiguration scenario 7 To obtain this optimization minimization of response time we pro pose an intelligent agent based architecture in which a software agent is deployed to dynamically adapt the system to its environment by applying reconfiguration scenarios A reconfiguration scenario means the addi tion removal or update of tasks in order to save the whole system on the occurrence of hardware software faults or also to improve its performance when ran dom disturbances happen at run time Sporadic task is described by minimum interarrival time P which is assumed to be equal to its relative deadline D and a worst case execution time WCET C A ran dom disturbance is defined in the current paper as any random internal or external event allowing the addition of tasks that we assume sporadic or removal of sporadic periodic tasks to adap
294. mpletely This in turn increases power consumption To solve the floating point problem this study proposes a multiplier design with alternative bypassing implementation I THE PROPOSED DESIGN This study proposes a low power multiplier with alternative bypassing implementation to solve the problem of increase power consumption when using a tri state buffer The basic idea is to turn off the full adder when the bit of multiplier x or the bit of multiplicand y is zero Figure 7 shows that to turn off the full adder a PMOS transistor can be added between the pull up network of the full adder and power supply VDD and a NMOS transistor can be added between the pull down network of the full adder and ground GND A PMOS transistor connects to VDD because it cannot efficiently pass GND A NMOS transistor connects to GND because it cannot efficiently pass VDD This traditional method called the sleep approach 8 turns off the full adder Cutting the power source can reduce leakage power effectively and the value in the full adder does not keep the original state when a full adder is turned off Figure 7 shows the proposed modified full adder cell where the a design can be used in a row bypassing multiplier and the b design can be used in a column bypassing multiplier The operation of a design is that when the multiplier bit x 0 a partial product y x 1s zero so the full adder doesn t need to operate we turn off a PM
295. mption flash characteristics The unit price of flash memory is con stantly decreasing because the vendors of flash memories are trying to squeeze more capacity into constantly shrinking silicon dies and adopting multi level cell MLC technology 1 NAND flash storage devices i e solid state drives are becoming a viable solution for satisfying the high perfor mance and low power consumption demands of notebooks and desktop PCs as well as portable embedded systems with continuing improvements in both capacity and price However NAND flash memory has several restrictions resulting from its architectural characteristics First pages the minimum data access unit of a flash memory are de signed to share an identical word line and blocks consisting of several pages are designed to share an identical bit line in order to provide high density memory devices The unit sizes of the erase and read write operations are asymmetric for this reason read write operations are performed in a page unit while erase operations should be executed in a block unit Second electrons in the flash memory data cells can only be removed through an erase operation once the floating gates of the data cells are charged with electrons thus the write oper ation may have to be preceded by an erase operation This characteristic is sometimes called erase before write Third NAND flash causes an unpredictable electron leakage prob lem due to the wearing out
296. mputer Once all Verilog modules are completed software development on the PC will commence which is tasked to send raw pixel data over the USB protocol and onto the FPGA device itself as well as re concatenate the output data from the device with the necessary header data to finally form a compliant and readable JPEG image file Int l Conf Embedded Systems and Applications ESA 12 5 4 Developing the beginning interconnecting module The initial problem is the differences in the amount of data per clock between the USB interfacing module USB_FX2_ Control and the JPEG Encoder module JPEG_ENC as well as the formatting of said data In order to correctly format the input and output data interconnecting modules are built which are internally called JPEG_IF USB to JPEG Encoder Interfacing and Combine_final_data JPEG Encoder Output to USB Interfacing The main details of the USB _FX2 Control is that the module inputs and outputs data at 16 bits per clock within a shared bi directional bus The main details of the inputs outputs of the JPEG Encoder is the 24 bits of input data per clock 8 bit values per color per pixel The output is 32 bits of processed JPEG bitstream asynchronous and 7 bits total of end process control data FX2 USB Clock Cycle JPEG USE IF 1 Input 16 bits ol chala Do _ 0 maS e a ma 2 1 O MiteRRalStates Slelelet7 le T e asa j
297. n IT lt Akg At Where Aine Aka Ax A Tkl If Akno Ak j we have n maximum and we obtain the following expression n lt T 1 b The biggest integer n which satisfies b is n At a 2 Dki lt Ak d the respect for this condition involves that the deadline of Tk n will have to verify Diery Akm t Dies Ag Fad As Ape gt Akno n 1 Tk we have Akno Where Akra C Ak j Ak j Tel If ARs Figs we have n maximum and we obtain the following expres sion _ n lt ok 1 c The biggest integer n which satisfies c is n e 1 a An implicit condition is that n gt 0 notice in d that as D can be arbitrarily big n can be negative The biggest n which verifies three conditions b c and d is finally n min Pe 1 Where a max 0 a We obtain finally the function of major job arrival with following deadline for T S At d min l Ea 25 1 Ck e Int l Conf Embedded Systems and Applications ESA 12 5 2 Calculation of response time bor ders under EDF The value of the biggest possible period of interfer ence of the system noted L is common to all the tasks This maximal period occurs after the simulta neous provision of an instance of all the tasks L min At gt 0 S1 m 0 At At f With S1 m 0 t Si m 0 t 00 is the function of major job arrival who adds the job of all the instances whatever are their deadlines In
298. n eas a Bae USB 2 0 Protocol Pee nat oe F Top Module Stato Machine Resi mass Jata from end BiockMemi inte Ip uy Wieb SB Chip to BiockMem code Bda back 5 x pee y apse e Ve ee Smee Sena I ta eae OF Jebel vis i he USH data Read a Word dipeg ete USE i hannel pakel iom hit stear 3 Ghanned i i i RiwkMemn eni j m i I a TN i a rvert h stmam 3 Word i tead a Word l mver It to mio 2 16 7 om USE chp i on BiockMenr2 I b i ats 7 pui a i e ws Lao l J n py TETAY o WT 7 j ies Mest nd the Cake LSockMern _ Brockvier USB chip USe_F JpogEncoder_IF Comb_Data USBF State mathine ne State machine State rro chir Figure 2 Overall System State Machine Diagram Figure 2 above shows an overall project state machine diagram of the system that drives the Verilog modules within the FPGA as well as the software tasks on the computer side The application that will run within the computer is responsible for converting and sending the raw pixel values as well as receiving the output bitstreams from the FPGA to be reassembled into a final compressed JPEG image via the USB protocol 3 1 Embedded Hardware Specifications The FPGA hardware used for this project is a Xilinx XUPV5 LV110T Development System 5 which has been prepared by the Xilinx University Programs for educational use The development board offers the following key features which
299. n will differ under the different To make sure consecutive operation Consecutive of inputting money and selecting item operation works The number of testing case will differ under the different platform To make sure under the circumstance Compound that any order of inputting money and operation selecting item system respond correctly Sub operation type Inputting money works The number of testing case platform Selecting item Consecutive inputting money Consecutive selecting items Single inputting money single selecting item single selecting item Single inputting mone Consecutive inputting money Single selecting item Consecutive selecting item Single inputting mone Consecutive inputting money Consecutive selecting items Consecutive selecting items Consecutive inputting mone Consecutive inputting money Consecutive selecting items Consecutive inputting mone Consecutive selecting items Consecutive inputting money Consecutive selecting items 50 Suppose it is the first situation that holds then a successful deal should be made afterwards The code will check whether there are other waiting items by calling OSQAccept If yes reminding customer to put more money to fulfill the purchase If not put the shopping process into the end Suppose it is the second situation that holds the system simply make a deal by updating the total money and then return to the beginning of the loop Suppose
300. n and D S Naidu Implementation of sEMG Based Real Time Embedded Adaptive Finger Force Control for a Prosthetic Hand submitted to JEEE CDC 2011 24 C Potlun M Anugolu Y Yihun A Jensen S Chiu M P Schoen and D S Naidu Optimal Tracking of a sEMG based Force Model for a Prosthetic Hand submitted to JEEE EMBS 2011 148 Int l Conf Embedded Systems and Applications ESA 12 Optimal Real Time Scheduling for Reconfigurable Periodic Asynchronous OS Tasks with Minimizations of Response Times Hamza Gharsellaoui Mohamed Khalgui Samir Ben Ahmed INSAT Institute University of Carthago Tunisia ITIA Institute CNR Research Council Italy SF ST Faculty University of Tunis El Manar Tunisia ABSTRACT In this paper we present a sufficient real time schedu lability algorithm for preemptable asynchronous and periodic reconfigurable task systems with arbitrary relative deadlines scheduled on a uniprocessor by an optimal scheduling algorithm based on the EDF prin ciples and on the dynamic reconfiguration A recon figuration scenario is assumed to be a dynamic auto matic operation allowing addition removal or update of operating system s OS functional asynchronous tasks We propose an intelligent agent based architec ture where a software agent is used to respect real time constraints The agent dynamically provides precious technical solutions for users when these constraints are not
301. n for low power embedded systems in Proceedings of the 36th Annual ACM IEEE Conference on Design Automation pp 140 145 New Orleans La USA 1999 13 M B Kamble and K Ghose Analytical energy dissipation models for low power caches in Proceedings of the International Symposium on Low Power Electronics and Design pp 143 148 Monterey Calif USA August 1997 14 T M Taha and D S Wills An instruction throughput model of superscalar processors EEE Transactions on Computers vol 57 no 3 pp 389 403 2008 15 T S R Kumar C P Ravikumar and R Govindarajan Memory Architecture Exploration Framework for Cache Based Embedded SoC VLSI design pp 553 559 2008 16 M Y Qadri and K D M Maier Data Cache Energy and Throughput Models Design Exploration for Embedded Processors EURASIP Journal on Embedded Systems 2009 89 17 Abel G Silva Filho Filipe R Cordeiro Cristiano C Ara ujo Adriano Sarmento Millena Gomes Edna Barros and Manoel E Lima An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms International Journal of Reconfigurable Computing pp 1 12 2011 18 Shyamkumar Thoziyoor Naveen Muralimanohar and Norman P Jouppi CACTI 5 0 technical report form Advanced Architecture Laboratory HP Laboratories HPL 2007 Available online www hpl hp com research cacti 19 Przybylski S Horowitz M Hennessy J Performance tradeoffs
302. n Huang and Chang s encoder and having 11 3 reduced device count than Kun et al s encoder Although the proposed encoder features roughly the same critical path delay as that of Huang and Chang s encoder the former requires 27 6 less number of transistors for physical implementation in comparison with the latter The above savings translate to optimal power delay and energy delay products for the former highlighting its efficacy over its counterparts IV CONCLUSION A novel 8 bit dynamic CMOS priority encoder design was presented in this paper The proposed 8 bit priority encoder requires just 55 transistors for physical realization the best in its category in terms of device count Moreover it is found to effect good optimization of the power delay area envelope Compared to the 8 bit CMOS priority encoder hand designed on the basis of Huang and Chang s 4 bit encoder cell 14 including provision of an extra lookahead input signal the proposed 8 bit priority encoder exhibits better design metrics especially with respect to power and area In terms of propagation delay though the proposed design is found to be neck and neck with the former The proposed 8 bit CMOS priority encoder design belonging to domino logic style can be incorporated into the parallel priority look ahead architecture of Kun et al 13 for realizing higher order specifications APPENDIX 1 2 3 4 5 6 7 8 9
303. n application specific program and communication protocol details The author of IsoAgLib library Dipl Inform Achim Spangler licensed with exceptions under the terms of the GNU General Public Int l Conf Embedded Systems and Applications ESA 12 License GPL By providing simple function calls for jobs like starting a measuring program for a process data value on a remote ECU the main program has not to deal with single CAN message formatting This way communication problem between ECU s which use this library should be prevented The IsoAgLib has a modular design pursuant to the various functional components of the standard ISO 11783 The library has this design to make sure the minimum use of IsoAgLib in program memory of Implement ECU The IsoAgLib demonstrates the layered architecture to be easily familiar with new hardware platforms Most of the software can be used without alteration on all platforms The layered architecture 1s described by the diagram in Figure 6 Driver Communication DATA Network Virtual Application Process Task Diagnostic Link Management Terminal Layer Data Controller Services Extension Common CAN Actor System Access Se ee Ce Se ee Hardware anaes Layer HAL System Access a Sa a Ce ees Hardware Drivers Figure 6 System architecture of embedded workbench applications The IsoAgLib was developed to be suitable with different systems and these systems can be an element of proce
304. nal array multiplier with the structure shown in Fig 2 Design 3 includes an array multiplier with row bypassing as Fig 3 shows Design 4 is an array multiplier with column bypassing as Fig 4 shows The proposed design P1 includes the row bypassing method as Fig 8 shows while the proposed design P2 includes the column bypassing method as Fig 9 shows To calculate the average dynamic power 50 input patterns were randomly generated for 4x4 8x8 and 16x16 array multipliers respectively The random input patterns show that the probabilities of O and 1 are both 50 respectively Table I shows dynamic power consumption Compared to Base for 16x16 bit multipliers design P1 reduces the dynamic power consumption by 17 16 while design P2 reduces the dynamic power consumption by 26 9 Because design 3 requires extra circuits consumes more power Table II depicts the area overhead of the transistors Compared to design 3 design P1 reduces the transistor area by 8 Compared to design 4 design P2 reduces the transistor area by 4 Table III shows the multiplier delay the delay time is calculated from least significant bit LSB of input change to most significant bit MSB of output change Designs P1 and P2 have greater delay than 3 4 because they have long charge and discharge path in the full adder Int l Conf Embedded Systems and Applications ESA 12 Tables IV through VI show the leakage powe
305. nce on Artificial Intelligence ICAI 11 Las Vegas Nevada USA July 18 21 2011 17 T D Sanger Bayesian Filtering of Myoelectric Signals J Neurophysiol 97 2007 pp 1839 1845 18 M B I Reaz M S Hussain and F Mohd Yasin Techniques of EMG signal analysis detection processing classification and applications Biol Proced Online 2006 8 1 pp 11 35 19 E Kral L Vasek V Dolinay P Varacha Usage of PSO Algorithm for Parameter Identification of District Heating Network Simulation Model The 14th World Scientific and Engineering Academy and Society WSEAS International Conference on Systems Corfu Island Greece July 22 24 2010 20 A Neubaur The Intrinsic System Model of the Simple Genetic Algorithm with a Selection Uniform Crossover and Bitwise Mutation The 14th World Scientific and Engineering Academy and Society WSEAS International Conference on Systems Corfu Island Greece July 22 24 2010 21 J Rafiee M A Rafiee N Prause and M P Schoen Wavelet basis functions in biomedical signal processing Expert systems with Applications 2010 22 C Potluri M Anugolu P Kumar A Fassih Y Yihun S chiu Naidu DS Real time sEMG Acquition and Processing Using a PIC 32 Microcontroller ESA 11 9 Intl conference on Embedded Systems and Applications Las Vegas Nevada USA July 18 21 2011 23 C Potluri Y Yihun M Anugolu P Kumar S Chiu M P Schoe
306. nce to resolve its software or a drive failure related issue and system maintenance engineer does not take the right decision on time it will arise an undesirable situation of data loss 3 3 Software error Many users use client based applications to create backup and schedule backup the data on their PC to the NAS Sometime application is corrupted or not working properly If a software application faces a bad sector to reading the drive while working with database it may cause for further data loss Data goes corrupt is the deterioration by software error or virus Computer viruses are developed to damage the computer system software file systems or make unwanted changes in user data without making any notice It can corrupt or delete user files e mail or even delete everything on NAS storage 3 4 Firmware upgrade failed or firmware corruption controller failure Sometime things often go wrong for NAS devices As earlier explain NAS itself is a combination of hardware components that are work with software A NAS device contain it hardware set to functioning or controlling storage drives It has disk array controller to manage the physical disk drives and presents them to the user as logical units over multiple RAID configuration As other NAS also have firmware or software update function on controller card The firmware update may be failed or compatibility problems with existing configuration A firmware corruption can stop its func
307. nced by the factor of data access intensity During the high data access intensity the host event queue can be filled with storage access requests and hence must be handled immediately On the other hand during the low data access intensity the stor age system becomes largely idle and its bandwidth is greatly under utilized 17 Therefore a large portion of the run time garbage collection cost can be saved if the FTL implements time consuming operations during low data access intensity However the reguest pending problem must be consid ered when adopting an idle time garbage collection technique The FTL should suspend garbage collection and immediately back into the request handling process when the host issues storage access requests during low data access intensity Therefore the responsiveness to the host storage access re quests can be improved if the garbage collection operations are preemptively designed 3 Related Works In this section victim block selection techniques of garbage collection are analyzed and an explanation is given for the operational latencies incurred by those techniques 3 1 Victim Block Selection Various cost based garbage collection techniques 6 15 have been proposed over the past several years In the Greedy algorithm Wu et al 8 first suggested that the FTL selects blocks having the largest number of invalid marked pages as victim blocks In this way the FTL can reduce the number of page pro
308. nd Applications ESA 12 increase its computation time without missing its deadline under EDF scheduling In 10 a window constrained execution time can be assumed for recon figurable tasks in n among m windows of jobs In the current paper a window constrained schedule is used to separate old and new tasks that assumed sporadic Old and new tasks are located in different windows to schedule the system with a minimum response time In 4 a window constrained schedule is used to sched ule the system with a low power consumption In the following we only consider periodic and spo radic tasks Few results have been proposed to deal with deadline assignment problem Baruah Buttazo and Gorinsky in 7 propose to modify the deadlines of a task set to minimize the output seen as sec ondary criteria of this work So we note that the optimal scheduling algorithm based on the EDF prin ciples and on the dynamic reconfiguration is that we propose in the current original work in which we give solutions computed and presented by the intelligent agent for users to respond to their requirements Running Example To illustrate the key point of the proposed dynamic reconfiguration approach we consider Sys U Sys a set of 5 characterized tasks shown in Table l as a motivational example Sys TA Tp and Sysg oC Op and og TA and Tp are periodic tasks and all the rest oc op and og are sporadic tasks Each task can be exec
309. nd just a few cache sizes for embedded applications are introduced Exploration of 20 reduced 300 cache configurations to 36 configurations 6 sizes for L1 and 6 sizes for L2 In this paper we make more reduction on cache size configurations that have to be explored by considering both dynamic and static power consumption of each configuration using the cache power model introduced in next section The proposed exploration in 20 has calculated the best cache size for each application based on performance From now we call this point of cache size the highest cache performance HCP HCP point produces the lowest cycle simulation and HCP of all selected embedded applications from 21 22 are shown in figurel b in the right most column Author of 19 did somehow the same research However neither 19 nor 20 considered the power constraints of cache which are very important in embedded processors 3 Power analysis For calculating the power consumption of each configuration we have proposed the following model Total energy that is consumed by a hardware module here a cache is calculated by adding total dynamic and static energy Dynamic energy is related to the supply voltage module activity output capacitance and clock frequency Et Etd Ets 1 Where E is total energy dissipation E equals to total dynamic energy and E is total static energy Any access to Int l Conf Embedded Systems and Applications ESA 12
310. ndpoint 2 IN 70 75 80 85 90 95 100 105 110 115 120 Current Throughput 2662733 Bps 2 54 MBps Max Burst Rate 306971 4 Bps 8 65 MBps Max Throughput 2056373 Bps 2 91 MBps Figure 4 EZ USB FX2 and XUPVS5 Interconnected Figure 5 EZ USB FX2 Benchmarking Tool Figure 4 above shows the USB Development System EZ USB FX2 connected to the breakout pins of the FPGA board XUPV5 Once the USB development board and the FPGA board has been set up correctly a customized benchmark program is built and run on the client machine to test the throughput of the new USB 2 0 chip using various packet sizes and clock rates The speed limitations of the USB protocol is dictated by the clock rate supplied as the upper speed limit 8MHz maximum for asynchronous transfers 483MHz maximum for synchronous transfers The max theoretical bandwidth for asynchronous transfers between the USB chip and the FPGA chip is 2 bytes 16 bits per clock cycle 16Megabyes sec constant on The USB Verilog module uses the 48MHz clock line 512bytes 1024bytes 2048bytes 409Sbytes 8192 bytes from the EZ USB FX2 board which is divided by 8 to Sa provide a 6MHz clock for asynchronous USB data transfer Figure 6 EZ USB FX2 Benchmarking Results With a 6MHz clock the maximum throughput is estimated to be 12 Megabytes sec sustained 5 2 Connectivity USB 2 0 Benchmark Summary USB 2 0 Asynchronous Throughput 6Mhz 90 80 70 60 50
311. ne in a linked list the residual time R of each task g at time t can be computed by the following recursive formula Ri d t q 5 R Ri t d dici Cj 6 2 Proof By the residual time definition equation 3 we have Ri di fi By the assumption on set at time t the task c1 in execution and cannot be preempted by other tasks in the set hence its estimated finishing time is given by the current time plus its remaining execution time fj tta and by equation 3 we have Ri d fi d t c Int l Conf Embedded Systems and Applications ESA 12 For any other task o with i gt 1 each task c will start executing as soon as o _ completes hence we can write fafa Pee and by equation 3 we have Ri di fi di fi 1 Gi di di 1 Ri 1 ci Ri 1 di di 1 Ci and the lemma follows Lemma 2 A task g is guaranteed to complete within its deadline if and only if R gt 0 2 Theorem 3 A set o i 1 to m of m ac tive sporadic tasks ordered by increasing deadline is feasibly schedulable if and only if R gt 0 for all g 2 In our model we assume that the minimum interar rival time P of each sporadic task is equal to its relative deadline D thus a sporadic task o can be completely characterized by specifying its worst case execution time C and its relative deadline D Hence a sporadic task set will be denoted as follows
312. nent compiles the test case and execute on emulator 10 The acquire log and the log analysis component collect logs and make a report via analyzing the logs 3 Implementation of ACSF Many developers use Eclipse with Android Development Tool ADT plugin which help us to develop android software easily via emulator monitoring tool etc Therefore we decide to develop our tool based on Eclipse plug in ACSF consists of five kinds of components like Fig 1 In this paper we concentrates on generating test case auto executing android software on emulate or device and analyzing portability of the software because those components have to considered android environment and vice versa 3 1 Generating test cases process An Android software is GUI based software therefore functions of the software are executed by events generated from users Also events can have sequences or not On the other hands test case may contain sequence of events Consequently we divide manual mode and automatic mode for making test case The manual mode has dependency with user s events or data and vice versa The manual mode is based on improved RPB technique which record user event as a script and execute the script If developer only changes some event in the script developer makes a script again although the script exists Therefore we support sequence concept which is method to modify or arrange a script As making a sequence user can use records as w
313. ng Server Background Server Figure 2 The simulation with Polling Server and Background server Int l Conf Embedded Systems and Applications ESA 12 4 3 Formalization By considering real time operating system OS tasks scheduling let n n n be the number of a mixed workload of periodic and aperiodic tasks in Currentp t The reconfiguration of the system Currentr t means the modification of its implemen tation that will be as follows at t time units Currentr t bnew U Eola Where ola is a subset of n old periodic tasks which are periodic and not affected by the reconfiguration scenario e g they implement the system before the time t and new is a subset of ng new aperiodic tasks in the system We assume that an updated task is considered as a new one at t time units By consider ing a feasible System Sys before the application of the reconfiguration scenario each task of va is feasible e g the execution of each instance is finished before the corresponding deadline 5 EXPERIMENTAL ANALY SIS AND DISCUSSION In this section in order to check the suggested con figurations of tasks allowing the system s feasibility and the response time minimization we simulate the agent s behavior on several test sets in order to rate the performance of the polling server and the back ground server in our hybrid scenario 5 1 Simulation We have conducted several test sets in order to rate the performance o
314. ng a dependability driven Feedback based control scheduling for real time embedded systems 3 Related work For real time computing systems a feedback performance control is presented in 16 which primarily focus on applying control theory to real time scheduling and utilization control A state of the art feedback control scheduling algorithm for real time computing systems with unknown execution time is presented in 17 which provide the performance guarantee for hard real time tasks Feedback Dynamic Voltage Scaling FDVS method to select proper frequency and voltage for Fault tolerant hard real time embedded system is presented in 37 Author also tries to provide QoS by reducing energy consumption and satisfying hard real time constraints in the presence of fault It also provides a technique to integrate DVS with Feedback control theory for hard real time computing systems An analysis of distributed feedback control with shared communication and resources utilization for real time system is addressed in 19 Fault tolerance scheme check pointing for real time embedded systems is integrated in 7 A perspective on integrating feedback control and computing for control scheduling co design is presented 18 Control design for networked control system a novel approach for designing feedback based control scheduling for the networked systems is addressed in 20 Up to date control scheduling algorithms based on Fuzzy logic controlle
315. nment problem In Baruah Buttazo Gorinsky amp Lipari 1999 the authors propose to modify the deadlines of a task set to minimize the output seen as Int l Conf Embedded Systems and Applications ESA 12 secondary criteria of this work In Cervin Lincoln amp G 2004 the deadlines are modified to guarantee close loop stability of a real time control system In Marinca Minet amp George 2004 a focus is done on the deadline assignment problem in the distributed for multimedia flows 15 In the case of a variable speed processor reducing the frequency can create overloads that can result in deadline miss In the second case the task parameters must be adapted on line to cope with the overload The idea is to adapt the periods of the tasks when needed to reduce the processor utiliza tion Other related papers are detailed in Buttazzo amp al 2004 in which they introduce a novel schedul ing framework to propose a flexible workload manage ment at run time They present the concept of elas tic scheduling introduced in Buttazzo G Lipari amp Abeni 1998 In Balbastre amp Ripoll 2002 the au thors show how much a task can increase its compu tation time still meeting the system feasibility when tasks are scheduled EDF They consider the case of only one task increasing its WCET 15 Finally we note that all these related works consider synchronous OS tasks and we are not currently aware of any existing
316. ns for mobile devices demand reconfigurability high performance low consumption and low cost solutions And in order to embedded systems attend efficiently these requirements several studies are being conducted In 1 the authors present an asymmetric MPSoC simulator environment which can be used for the architecture exploration and optimization 2 makes an approach concerning different aspects including general architectural choices and their impact on programmability the requirements of particular application domains as well as programming models In 3 the authors consider the inter processors communication and synchronization as one of the key problems of NoC_ network on chip communication They propose two different models to improve the communication performance And 4 provides an overview of the main MPSoC design challenges Also some applications such as multimedia and wireless communications which demand high complex processing have been solving their constraints of low latency and high throughput exploring the potential provided by embedded multiprocessors systems 4 5 These architectures consist of specialized cores around general purpose processors dedicated to execute sequential tasks And the intensive tasks like loop programs are generally executed on specialized cores also called co processors or accelerators MPSoCs are characterized as a set of different processing elements PEs working together int
317. nsiveness in Hard Real Time Environments Proc IEEE Real Time Systems Symposium San Jose CA pp 261 270 cS Guillem B 1998 Specification and Analysis of Weakly Hard Real Time Systems PhD thesis Departament de Cincies Matematiques and In formatica Universitat de les Illes Balears Spain http www cs york ac uk bernat 171 172 Int l Conf Embedded Systems and Applications ESA 12 5 Burns A and Guillem B 1999 New results 1995 The deferrable server algorithm for en on fixed priority aperiodic servers In 20th IEEE hanced aperiodic responsiveness in hard real time Real Time Systems Symposium RTSS pages environments IEEE Transactions on Computers 6878 Phoenix USA 44 1 7391 6 Sprunt B Sha L and Lehoczky J 1989 Ape 8 Thuel S R and Lehoczky J P 1994 Al riodic task scheduling for hard real time systems gorithms for scheduling hard aperiodic tasks in Real Time Systems 1 1 2760 fixed priority systems using slack stealing In Real Time Systems Symposium pages 2233 San 7 Strosnider J K Lehoczky J P and Sha L Juan Puerto Rico
318. nt to buy vending machine should have ability to record all the items customers want which will be built into an item message queue Selecting an item means en queuing an element to this message queue a successful deal means an item will be de queued from this message queue One requirement for this message queue is that it can be en queued both in the front and in the rear uC OS II supplies a data structure of message queue type as well as some operations on this data structure including OSQPost and OSQPostFront to enqueue in the rear and in the front as well as OSQPend to de queue The total money is also built into a message queue which has only one element in it During the purchase process customers may input money at any time So the total money 47 must be updated in real time So when the total money needs to be updated this message queue will be flushed and then a new element with latest money information will be en queued To do this the framework simply make use of OSQFlush and OSQPost to reach its goal 2 3 2 Tasks Configuration Developing an embedded system based on uC OS II means a multi task system will be designed When developing a multitask system the first thing is to partition functionalities and determine the priorities of the tasks Now we only consider key tasks that are involved in key logic Key tasks involved in key logic including 4 tasks 1 TaskMoney Task for handling money informati
319. ntelligent light control using sensor networks SenSys 05 2005 I F Akyildiz W J Su Y Sankarasubramaniam E Cayirci Wireless sensor networks a survey Computer Networks vol 38 pp 393 422 Oct 2002 Heemin Park Jeff Burke Mani B Srivastava Intelligent Lighting Control using Wireless Sensor Networks for Media Production KSH Transactions on Internet and Information Systems vol 3 no 5 Oct 2009 Changsu Suh Yong Bae Ko Design and Implementation of Intelligent Home Control Systems based on Active Sensor Networks EEE Transactions on Consumer Electronics vol 54 no 3 Aug 2008 M Ilyas I Mahgoub and L Kelly Handbook of Sensor Networks CompactWireless andWired Sensing Systems Boca Raton FL CRC Press 2004 ZigBee Alliance ZigBee Specification version1 1 Nov 2006 Zigbee Alliance Smart Energy Profile Specification version1 0 March 11 2009 Liu Yanfei Wang Cheng Yu Chengbo Qiao Xiaojun Research on ZigBee Wireless Sensors Network Based on ModBus_ Protocol Information Technology and Applications 2009 IFITA 09 International Forum on vol 1 pp 487 490 2009 CS5460A Single Phase Bi directional Power Energy IC data sheet Cirrus Logic Austin Texas USA PIC16F882 data sheet Microchip Chandler Arizona USA AN220 Watt Hour Meter using PIC16C923 and CS5460 application note Microchip Chandler Arizona USA XBee XBee Pro ZB RF Modules data sheet Digi International Inc
320. o tm is a finite set of transition m gt 0 3 B P x T N is the backward incidence function 4 F P xT N is the forward incidence function Each system state is represented by a marking M of the net and defined by M PHN The dPTPN is defined by the 7 tuplet dPTPN PN Top Ts Br Fr coef Mo 4 1 PN is a Petri Net 2 Tep kes Lops cae transition k gt 0 3 Ty T QF is the firing time of a transition Vt T t is a temporal transition gt Ty t 0 If T t 0 then is an immediate transition Each temporal transition t is coupled with a local clock H1 t with HI T Qt 4 Braa P x Tep gt N is the backward incidence function associated with compound transition 5 Fr P x Tep N is the forward incidence function Tep is a finite set of compound Int l Conf Embedded Systems and Applications ESA 12 associated with compound transition 6 coef P x Tep gt Z is the coefficient function associated with compound transition 7 Mo is the initial marking The semantics of firing in dPTPN 1s based on the partial order theory 2 15 6 building on a relation of equiv alence between various sequences of possible crossings starting from the same state In fact when two sequences are found to be equivalent then only one of them is selected This relation of equivalence is based on the notion of independence of transitions The dPTPN
321. o 7 0 volts can be sensed and logged by the DAQ The DAQ that we are using can sense 10 000 signals per second but can only generate signals at a rate of 150 Hz With our limited testing this has not been a problem It is important to have the capability to sense a large number of signals per second so that the paced signals are not lost even with a very narrow pulse width AS on AP og Wr VP ore jes Pemermatenr Figure 4 NI Signal Express 69mV pulse at 1Hz As shown in Figure 4 National Instrument s Signal Express software can be used to simulate a heart beat by generating a square pulse of 69 mV at 1 Hz generated in the top graph sensed in the bottom graph Signals can also be generated by an open source tool built using Python called Python Data Acquisition Tools pydaqtools version 0 2 0 2011 http sourceforge net projects pydaqtools More accurate representations of the ventricular and atrial signals can be generated It is very easy to change the amplitude and rate of each signal generated Also the signals can be easily logged for more careful analysis as shown below in Figure 5 eat hana Virs fe as aroari s Heo BERR Sa e A E Ce FEEFEE TEFEEEYT Figure 5 Output log of signals 17 18 In this case the square wave signal representing a heart beat has it s amplitude reduced from 69 mV to 59 mV Then as the output log shows some of the signals are not sensed
322. o a more robust be implemented by building upon the present algorithm sensor for confirming an emergency situation if necessary subject having to perform a gesture 5 References 1 US Census Bureau The Older population 2010 November 2011 http www census gov prod cen2010 briefs c2010br 09 pdf 2 Alwan M Dalal S Mack D Kell S Turner B Leachtenauer J Felder R Impact of monitoring technology in assisted living outcome pilot IEEE Int l Conf Embedded Systems and Applications ESA 12 Transactions on Information Technology in Biomedicine Volume 10 Issue 1 pp 192 198 2006 3 Hou J C Qixin Wang AlShebli B K Ball L Birge S Caccamo M Chin Fei Cheah Gilbert E Gunter C A Gunter E Chang Gun Lee Karahalios K Min Young Nam Nitya N Rohit C Lui Sha Wook Shin Yu S Yang Yu Zheng Zeng PAS A Wireless Enabled Sensor Integrated Personal Assistance System for Independent andAssisted Living Joint Workshop on High Confidence Medical Devices Software and Systems and Medical Device Plug and Play Interoperability HCMDSS MDPnP 10 1109 HCMDSS MDPnP 2007 13 pp 64 75 2007 4 Doukas C N and Maglogiannis I Emergency Fall Incidents Detection in Assisted Living Environments Utilizing Motion Sound and Visual Perceptual Components IEEE Transactions on Information Technology in Biomedicine Vol 15 No 2 pp 277 289 2011 5 St
323. o replace faulty drive with a new one and starts rebuild but do not attempt a forced rebuild in that case Forced rebuild may cause malfunction If at that time any one of NAS drives stop working your NAS goes off line and all data will lost 5 3 Analysis of double drive failure The NAS was running in RAID degraded mode and unfortunately if second drive crashed during RAID rebuilds or NAS running in normal conditions and its two drives crashed simultaneously The chances of failure of second drive before full redundancy from degraded mode is established are about 6 365 up to 39 365 if it takes 24 hours to replace and reconstruct a failed drive Now NAS will offline one drive fault tolerance capability and it will not show stored data NAS Data recovery on double drive failure 1S explained in section 5 5 1 With RAID 6 or nested raid Configuration that affords multi drives fault tolerance address this problem like previous section 5 4 Applications installation First we install mdadm gparted and xxdiff applications for recovery process You need administrator right to install these applications Find these applications on online Ubuntu Software Centre Follow below steps Application gt Ubuntu Software Centre Search mdadm Click on Install button 53 54 Search gparted Click on Install button Search xxdiff Click on Install button 5 5 NAS data recovery steps During the RAID recovery proce
324. o the same silicon and they can communicate through a bus shared memory or NoC network on chip Generally PEs are based on ASICs Application Specific Integrated Circuits FPGAs Field Programmable Gate Arrays DSPs Digital Signal Processors among others 6 In this context it is possible to find several devices For example the newest cell phones and smart phones has around 4 to 8 dedicated processing elements to control the user interface manager the protocols of communications perform graphics processing digital signal processing coding and decoding voice image and video among others 4 Figure 1 presents a typical structure of smart phones 2D 3D Graphics f Interconnect Fabric t Multicore RISC Baseband Modem Display Controller Memory Controller Figure 1 Typical structure for smart phones reproduced from 7 155 156 The illustration above is a real example of MPSoC architecture which explores the efficiency available by many dedicated cores working together Therefore considering the possibility to compute in parallel a set of instructions between different PEs this study is evaluating the energy consumption and the speedup performance on embedded multiprocessors architectures The main contribution of this summarized as follows paper can be e From simulations it presents the feasibility to off load a critical path to a dedicated processor e It shows a trade off between
325. ocessing pages 272 275 August 1990 C Lu J A Stankovic G Tao S H Son Feedback control real time scheduling framework modeling and algorithms Real time Systems Vol 23 No 1 2 pp 85 126 2002 Sha L T Abdelzaher K E Arz n T Baker A Burns G Buttazzo M Caccamo A Cervin J Lehoczky A Mok Real time scheduling theory A historical perspective Real time Systems Vol 28 2004 A Goel Walpole and M Shor Real rate scheduling in proceedings of the 10th IEEE Real Time and Embedded technology and Applications Symposium RTAS pp 434 441 2004 S Lin and G Manimaran Double Loop Feedback Based scheduling Approach for Distributed Real Time Systems in proceedings of the High Performance Computing HiPC pp 268 278 2003 J A Stankovic T He T F Abdelzaher M Marley G Tao S H Son and C Lu Feedback Control Real TimeScheduling in Distributed Real Time Systems in proceedings of the IEEE Real Time Systems 2001 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 K E Arz n B Bernhardsson J Eker A Cervin K Nilsson P Persson and L Sha ntegrated control and scheduling Technical Report ISRN LUTFD2 TFRT7586SE Lund Institute of Technology Sweden 1999 C L Liu and J W Layland Scheduling Algorithms for Multiprogramming in a Hard Real Ti
326. ocessor using the communication bus network this communication over network is itself a job task which represents a sampling interval at which communication happens over network as shown in Fig 3 No Ty Sampling intervals _ gt Figure 3 Each fault represents one sampling interval the time at which communication occur on network using re execution and replication When a fault is detected SC job is re executed on the same processor and the replicated job is executed on a new processor Again the selection of the network bus communication is flexible Most commonly used bus networks are I2C CAN 23 or Flex Ray 24 These sampling intervals jobs over the network introduces a time delay in the execution overall execution time of the SC tasks Since a fault can occur at any time in the system and the time delay introduced by these faults are modelled as the bounded time varying delays such as O lt x t lt x 7 System Integration System architecture consists of i processors with each processor has some SC tasks to be scheduled on SC core and non SC tasks 26 27 and 28 to be scheduled on non SC core Allocations of the tasks are predefined Each processor has its own FCSA controller to control CPU utilization A CPU utilization monitor continuously monitors the CPU utilization and feeds the output signal to FCSA controller in a closed loop Inter processor communication is done by using a communicati
327. ochip Technology assembly language using the PICkit in circuit debugger and Int l Conf Embedded Systems and Applications ESA 12 programmer In addition MPLAB IDE and MPASM Microchip Technology s integrated development environment and assembler are used to facilitate the development and testing of the source code The use of assembly language to program the microcontroller allowed for a finer control of the device settings and operations The main task of the microcontroller and thus the assembly code is to coordinate the operations of the CS5460A and the XBee module In addition the processing power of the microcontroller is used to calculate full scale data values from the scaled versions recorded by the CS5460A When powered on the PIC microcontroller loads the internally stored variables and definitions The next task of the assembly source code is the initialization of the CS5460A the XBee and the built in peripheral modules Once initialized the CS5460A performs continuous calculations and the XBee module is put to sleep In future project implementations the sleep functions of the CS5460A and the PICI6F882 will be incorporated Further operations of the system are performed by request Using the web interface the system can be asked to cycle the circuit on and off or to report the current data values When a request is made the XBee is awakened from its sleep mode to relay the appropriate messages to and from t
328. oencephalogram EEG The ADS1298 has eight channels with simultaneously sampling and the possibility of using digital analog converters ADCs delta sigma with 24 bit resolution by channel with 32kSPS throughput capability It also integrates programmable gain amplifiers PGAs for signal conditioning internal reference voltage and an oscillator all those inside a single integrated circuit Figure 3 shows the block diagram of the ADS1298 With its high integration degree excellent benefits and exceptional performance the ADS1298 allows the development of medical instrumentation systems by reducing the size power consumption and decreasing development costs 10 102 YY REF ADS1298 PGA1 ADC1 SPI and i Control PGA8 ADC8 Pace Detect Lead Off Temperature Test Respiration Right leg Drive Wilson Figure 3 ADS1298 blocks diagram 10 4 2 Microcontroller Unit Due to unsupported real time operations presented by the Android platform it became necessary to use an auxiliary subsystem in order to accomplish the real time requirements in communication tasks between the host and the data acquisition system We used the Freescale Semiconductor s MC9S08JM60 Microcontroller Unit MCU It is member of the low cost high performance HCS08 family of 8 bit MCUs has a Von Neumann architecture Up to 60 KB of on chip flash memory 4KB of data memory 24 MHz of internal bus frequency two full duplex Ser
329. of the monitoring data Non memory care residents were surveyed and assessed using the Satisfaction With Life Scale SWLS instrument They compared the pre and post installation SWLS scores The older adult participants accepted the monitoring The results showed that monitoring technologies provided care coordination tools that are accepted by residents and positively impacted their quality of life The SWLS is very broad in nature and hence a more directed questionnaire would unearth privacy concerns while being monitored Hou et al presented Personal Assistance System PAS open architecture for assisted living which allowed independently developed third party components to collaborate 3 They also discussed the key technological issues in assisted living systems such as tracking fall detection security and privacy They conducted the pilot study in a real assisted living facility In their system they used a handheld blood oximeter and an IBM Thinkpad T43 with Windows XP Home Edition Java Runtime Environment Standard Edition 1 5 0 06 Bluetooth stack Avetana placed in the resident s room The two residents received alert messages on a flat computer screen twice a day that reminded them to take an oximeter reading The alert times were collaboratively set by the residents and the staff The resident after taking the oximeter reading had to tap the computer to acknowledge the alert message The oximeter reading was then sent
330. of time dependent systems using time petri nets JEEE Trans Softw Eng 17 3 259 273 1991 B Berthomieu F Peres and F Vernadat Bridging the gap between timed automata and bounded time petri nets In FORMATS pages 82 97 2006 B Berthomieu and F Vernadat Time petri nets analysis with tina In QEST pages 123 124 2006 U Buy and R H Sloan Analysis of real time programs with simple time petri nets In ISSTA 94 Proceedings of the 1994 ACM SIGSOFT international symposium on Software testing and analysis pages 228 239 New York NY USA 1994 ACM G Gardey D Lime M Magnin and O H Roux Romeo A tool for analyzing time petri nets In CAV pages 418 423 2005 Joel Goossens Pascal Richard P Richard and Universit Libre De Bruxelles Overview of real time scheduling problems In Euro Workshop on Project Management and Scheduling 2004 Object Management Group UML 2 0 OCL Specification OMG Adopted Specification ptc 03 10 14 Object Management Group October 2003 M Gonzalez Harbour J J Gutierrez Garciia J C Palencia Gutierrez and J M Drake Moyano Mast Modeling and analysis suite for real time applications Real Time Systems Euromicro Conference on 0 0125 2001 J Carpenter S Funk PHolman A Srinivasan J Anderson and S Baruah A categorization of real time multiprocessor scheduling problems and algorithms In Handbook on Scheduling Algorithms Methods and Models Chapman Hall CRC Boca 200
331. oller which means actual execution time for some SC task with dependability integration is 2 40 times more than estimated completion execution time and for some SC tasks executed 0 6 times their estimated time Also there are 10 SC tasks are scheduled on the Master microcontroller On Slave microcontroller g 1 8 2 2 which means that actual execution time for SC tasks with FT scheme is 1 8 2 2 times more than estimated completion execution time Also there are 10 SC tasks are scheduled on the Slave Microcontroller Int l Conf Embedded Systems and Applications ESA 12 Table 3 CPU Utilization with and without dependability integration with FCSA for 10 SC tasks including 30 transient faults SC Non Tasks SC Tasks CPU Type CPU Utilization of dependability driven FCSA CPU Utilizat ion of FCSA SC task execution overhead 10 20 0 8997 0 8461 180 220 Fig 10 shows a variation in CPU utilization At sampling interval 200 g 2 00 shows 200 execution time deviation of SC tasks and at 300 g 0 57 which suggests that some SC tasks have completed their execution time 0 57 times before their estimated execution time and for slave CPU sampling interval 300 g 1 80 shows 180 execution time deviation and at 700 g 2 20 shows 220 execution time deviation and at 800 g 0 6 which shows that SC task has completed before its estimated execution time SC Core CPU 1 SC Core CPU 2 EEE TOE A Uy
332. om one sub application to another this number should be changed 2 init function After the os init function calls functions that need memory allocation may be part of this function The init function in each sub application must be called only once in a large application 3 start function 59 When a sub application starts this function is called The start function may have various initialization functions e g drawing a main GUI picture One purpose of the start function is to activate created threads to run the sub application 4 shutdown function When one sub application switches to another sub application the shutdown function is called This function terminates all the threads which can be in running state or ready state This function may free some allocated resources for sub application such as closing some opened sockets or files 5 callback functions When a sub application registers a callback function for a specific RTOS service the RTOS calls the callback function for the service This callback looks like interrupt service routine in firmware programming There may be several callback functions in each sub application In our model the above five factors will be used to describe the sub application It should be noted that it will be a problem for compilers for duplicated variable and function names without declaring them as static local variable and functions if the same interface function
333. on 2 TaskItem Task for handling items information 3 TaskCheck Task for checkout 4 TaskChange Task for delivery and change return The relative priorities for each task are illustrated in Table 1 This is not the only way to design a humanized vending machine But the different configuration of priority will definitely determine the way that a vending machine acts and the level of its humanized service Tablel Task Priorities Task name TaskItem TaskMone TaskChange TaskCheck 3 3 Communication among key tasks Humanized services from a vending machine partially lie in effective communication among key tasks and among tasks and ISR This thereby relies on the functionalities that uC OS II supports Semaphore message box and message queue All the Semaphore message box and message queue used throughout key tasks are illustrated in Table 2 3 3 1 Synchronization among key tasks Here is a special note Theoretically it should be the memory address used to store money and item information that will be transmitted among key tasks Since those functions we use to transmit information only accept parameters that is of pointer type and integer type is the only type that money information and item information is of we can simply cast integer type into pointer type to satisfy the requirement of uC OS II functions to reach our goal By doing this we simply avoid the complexity of defining unnecessary Priorit High Low
334. on Computer Architecture pp 214 224 2000 5 David A Patterson John L Hennessy Computer organization and design the hardware software interface Morgan Kaufman 2007 4 edition 6 D Patterson and J Hennessy Computer architecture a quantitative approach Morgan Kaufman 2007 4th Edition 7 C Chakrabarti Cache design and exploration for low power embedded systems IEEE International Conference on Performance Computing and Communications pp 135 139 2001 8 D A M Dioquino K J S Rosario H F Supe J V Zarsuela A P Ballesil J A Reyes DLX HOTOKADA A Design and Implementation of a 32 Bit Dual Core Capable DLX Microprocessor with Single Level Cache 15th IEEE Int l Conf Embedded Systems and Applications ESA 12 International Conference on Electronics Circuits and Systems pp 466 469 2008 9 A Gellert G Palermo V Zaccaria A Florea L Vintan C Silvano Energy Performance Design Space Exploration in SMT Architectures Exploiting Selective Load Value Predictions Design Automation amp Test in Europe Conference amp Exhibition DATE pp 271 274 2010 10 V Romanchenko Quad Core Opteron architecture and roadmaps Digital Daily com 2006 11 S K Dash T Srikanthan Instruction Cache Tuning for Embedded Multitasking Applications TEEE TFIP International Symposium on Rapid System Prototyping pp 152 158 2009 12 W T Shiue and C Chakrabarti Memory exploratio
335. on network as shown in Fig 4 Sensors Actuators Sensors Actuators Feedback Control Scheduler O controller Feedback Ram CPU Util RAM lization Scheduler Be a a a pe ee eee eee eee ee es Bus Controller Figure 4 FCSA integration with FT scheme each processor has a feedback based control scheduler and a CPU utilization monitor CPU Utilization Monitor Form the communication network point of view if a SC task has n faults then at each fault the SC task has to replicate on a different processor using communication network represents n sampling intervals or subtasks over network Each subtask sampling interval introduced a delay in the system and that subtask is itself a job for network controller For the stability of the network each job on the network is modelled as a separate subsystem Each subsystem can have a single input single output SISO and is modelled as a SISO impulsive system or it may have multiple inputs and multiple outputs MIMO in that case system can be modelled as a MIMO impulsive system 22 Two kinds of subsystems and the Bus controller are shown in Fig 5 SISO Sir MIMO SISO od TL Figure 5 SISO and MIMO system specifications Network all Bus Controller Delay d introduce by the network is modelled in a closed loop as shown in Fig 6 x t Ax t Bu t Figure 6 SISO system closed loop with sampling interval S and delayd x t 4 sk
336. on the horizontal axis allowing viewing of objects on the side of the module The motion control module is composed by four motors connected at each end This configuration allows a greater The operator module is the interface that displays and allows the remote control of the robotic module The modulus operator is a Java application that connects to the robot and receives the transmitted images and captures user commands torque with less power consumption 2 3 Control 3 Results The control system of actuators and sensors was performed by a small 8 bit microcontroller The microcontroller receives the analog and digital signals and The tests were conducted to evaluate system communicates with the minicomputer eBox to send performance in three key features communication distance commands to the actuators Communication between these two elements is via RS 232 serial communication The command handling protocol is presented in Table 1 between robot and operator autonomy of the equipment and response time a Camera Right po Camera left Communication distance pod Move Front poe Move Right po Light OFF To evaluate the communication distance thirty tests were performed in various open and closed environments It was determined that the maximum communication distance was the one in which the robotic module started to fail to execute commands or to transmit the captured images rather than the point at which the operator
337. ontain caches This concern only grows as the semiconductor industry continues to provide more transistors per chip in pace with Moore s Law Industry has already shifted gears to deploy architectures with multiple cores multiple threads and large caches so that processors can be clocked at a lower frequency and burn less power while still getting better overall performance Controlling power and temperature in future multi core and many core processors will require even more novel architectural approaches In this paper we find out the optimum performance per power consumption points for cache sizes based on design space exploration using a new energy model considering dynamic and leakage energy of cache for embedded applications Full exploration is performed based on different parameters to find out the optimum and best cache configuration Results show that in different feature sizes 30 of static power and 43 of total power of an embedded core is consumed in the cache hierarchy in average It means based on this work in smaller feature sizes and for embedded application that can tolerate performance lose up to 3 we should select smaller cache hierarchy to deliver better performance per power as the most important parameter in designing embedded systems Keywords Embedded processor design space exploration cache power consumption area MIPS 1 Introduction Embedded systems are designed to perform dedicated functions often with
338. orithm http www ietf org rfc rfc4493 2006 136 Int l Conf Embedded Systems and Applications ESA 12 Android Conversion Support Framework for Android Software Won Shin Tae Wan Kim and Chun Hyon Chang Department of Computer Engineering University of Konkuk Seoul Korea Department of Electrical Engineering University of Myongji Gyeonggido Korea Abstract The android software is needed huge test process for many kinds of devices and android platforms because android platform does not support interoperability among various platform versions and it can be modified by device manufacturer To resolve this problem we suggested a new tool named Android Conversion Support Framework ACSF The ACSF has several functions which help to remove some repetitive or unnecessary tasks on the software testing Those functions execute automatically and find some points of software which seem to have problems and need to fix In this paper we show several components of the tool and explain characteristics of the tool in detail Developers who use the tool can fix problems of their software are related with portability on the porting process easily and quickly Framework Keywords Android Software Test case interoperability 1 Introduction We can see lots of android software as known as App easily Manufacturer of device which is based on android platform can modify android platform code for their devices suit
339. osphere and improving error measurement In addition to this proposed system differential GPS can be incorporated to enhance PVT accuracy Int l Conf Embedded Systems and Applications ESA 12 References 1 E D Kaplan C Hegarty Understanding GPS Principles and Appli cations 2nd ed Artech House Publishers 2005 2 H D Young R A Freedman Sears and Zemansky s University Physics 12th ed Pearson Addison Wesley 2008 3 L Rider Analytical Design of Satellite Constellations for Zonal Earth Coverage Using Inclined Orbits The Journal of the Astronautical Sciences vol 34 pp 31 64 Mar 1986 4 J F DeNatale R L Borwick et al Compact Low Power Chip Scale Atomic Clock in Proc IEEE 2008 p 67 5 R E Sorace V S Reinhardt and S A Vaughn High speed digital to RF converter U S Patent 5 668 842 Sept 16 1997 6 2012 The CubeSat website Online http www cubesat org 7 Dec 2010 AMSAT CubeSat Information Online Available http www amsat org amsat new satellites cubesats php 8 J Puig Suari C Turner W Ahlgren Development of the Standard CubeSat Deployer and a CubeSat Class PicoSatellite 2001 9 Jan 2012 NASA Earth s Moon Facts and Figures Online Avail able http solarsystem nasa gov planets profile cfm Object Moon amp Display Facts 10 Nov 2011 NASA The Mystery of the Lunar Ionosphere Online Available http science n
340. other is a callback function distributor CFD which calls every callback functions of each sub application whenever RTOS callback is serviced The connecting program X main CFD is the main function that is necessary for RTOS to be initialized and driven when integrating sub applications plus a set of callback function distributors denoted as CFD where CFD CFD CFD is the total number of callbacks in A There may exist the same callback functions in the sub application Each callback function distributor distributes the RTOS callback to the sub Int l Conf Embedded Systems and Applications ESA 12 application for the corresponding callback In conclusion this X is considered as the shared code for all sub applications When connecting sub applications there are two kinds of dependencies represented as function calls start and terminate The Aj Aj start means that A starts Aj with the start call Ais whereas Aj Ai terminate means that Aj terminates and the program control is back to A with the terminate call in Aj These two are a pair because when one sub application starts the other sub application when the other sub application terminates the program control usually goes back to the original sub application Whenever the program control of sub application is changed the sub application number must be changed This can be simply performed by declaring a global variable and inserting the program statemen
341. ows AesCmacReglIF v generated from a part of AesCmac java This is an on chip bus interface that contains user defined physical base address information and concretized implementations of APB 4 protocol selected from library This description also contains substance of private static fields as setting registers that retain inputs outputs of high level synthesized hardware JNIEXPORT jint JNICALL Java_AesCmac_getMac0O JNIEnv env jclass cls return volatile int BASE 0x00000024 native handshake function JNIEXPORT void JNICALL Java_AesCmac_process JNIEnv env jclass cls assert request volatile int BASE 0x00000000 1 wait for acknowledge while volatile int BASE 0x00000034 0 volatile int BASE 0x00000000 0 while volatile int BASE 0x00000034 0 Fig 10 AesCmacDrv c Fig 10 shows AesCmacDrv c generated from a part of AesCmac java This is a device driver of high level synthesized hardware This source code contains substantial set get method definitions and user defined physical base address information Int l Conf Embedded Systems and Applications ESA 12 AES CMAC Process Ri int req request input int keyO inputs int mac3 outputs int ack acknowledge output target of high level synthesis void process int k 4 GN Ay wait for request while re
342. ple the processes and the data acquisition subsystem The application developed on the Android platform is basically responsible for 3 function receiving storing and displaying information from the data acquisition system The reception is performed via a SPI connection between Android based system and a microcontroller where the first acts as the master and the other one acts as slave Also there is a local repository which collects all necessary information about the application users both medical staff and patients The MCU is responsible of management the data acquisition subsystem using a SPI protocol and implement FIFO policies 6 Results By deploying the application various tests were performed For the sake of evaluating the correct system Operation a sinusoidal wave was sensed and displayed as shown on Figure 8 Notice that the previous exhibited distortions Figure 5 have been fully corrected 104 ES GD 6 36 pm Sistema de Integraci n de Monitoreo M dico e Interoperabilidad para Teleasistencia Create by Eng Jaiber Yepes Figure 8 Sinusoidal signal Thereafter samples were taken from an artificial signal from an ECG signal generator as shown on Figure 9 It can be seen that a continuous signal was obtained without any kind of distortion as required for proper system operation Sampling of this artificial signal contributes to the system validation processes since the displayed signal is precisely the e
343. pplication requests frames of data before the new frames are available then there is an option to choose whether to wait for the next frame or to return immediately and try again later The NUI API never provides the same frame of data more than once The NUI Skeleton API provides information on the location of the subject in front of Kinect sensor bar with detailed position and orientation information This information is provided to application code as a set of points called skeleton positions that composes a skeleton 9 This skeleton represents a subject s current position and pose This system utilizes this feature by enabling skeletal tracking technique during the initialization phase of the system The process flow of the system is shown in Figure 2 Once the co ordinates are retrieved a predictable matching algorithm is implemented to see if there is a match between the gesture performed by the subject and the one that is stored in the system to indicate a danger situation The skeletal data can be retrieved irrespective of the ambient lighting conditions inside the room that the subject is residing The flow of the predictable matching process is shown in Figure 3 Once the skeletal data is obtained for each frame it will be stored in a buffer to perform the predictable matching algorithm The algorithm will determine whether the subject is having a discomfort illness while in bed Initially the joint co ordinates are extracted from
344. press CY7C67300 Datasheet URL http www cypress com docID 30079 9 QIODevice Class Reference URL _http gt project org doc qt 4 8 qiodevice html 10 QudpSocket Class Reference URL _http gt project org doc qt 4 8 qudpsocket html 34 Int l Conf Embedded Systems and Applications ESA 12 Motion Recognition Based Emergency Alarm System J Sasi R Sundaram and Y Jung Electrical and Computer Engineering Gannon University Erie PA USA sasi002 sundaram001 jung002 gannon edu Abstract Elderly people living by themselves or at a senior living community may not have the infrastructure for emergency response in case of discomfort while in bed at night or day Often they have to call for help themselves in case of an emergency situation This problem is resolved by using a new Motion Recognition Based Emergency Alarm System MR BEAS that alerts emergency responders in case of an illness or discomfort based on motion recognition under any ambient lighting conditions A depth sensor is employed that can provide a heat map of the subject that will be used to derive a skeletal frame which will be analyzed for any gesture of interest In addition a novel predictable matching algorithm is designed and implemented to identify pre determined gesture for triggering an alarm using a low cost platform This system can alert responders within the same building or remotely over the internet for added flexibility
345. properly initialized This involves setting the proper control bits and establishing a baud rate to control the flow of data Once the PIC16F882 is configured to communicate with the XBee via USART the system is able to communicate with a local XBee enabled computer The next step establishes communications between the XBee radios and the iDigi gateway This is a matter of identifying the various XBee radios by their serial number and by uploading a driver that receives and transmits serial data The final hardware design is shown in Figure 14 The final aspect of the home automation system is the user friendly frontend The iDigi development kit that accompanies the gateway provides access to the Digi Cloud which allows the use of Google Apps A complete web interface using these resources allows for data logging and plotting as well as a friendly environment for the user to interact with their smart devices m mm i 7 e on XBEE OP r 4A KBEE rR O F CIO OUR O30 424A szoir OF Z 15A 125VAC a g gt g QS Het Ning go a S MADE IN MEXICO snenacecenne ef k ma J a an Daai ES ER EY Figure 14 Final Design PCB 5 Conclusions The proposed home automation system is a new approach to home energy conservation The system enables the consumer to conveniently reduce energy consumption The easily incorporated design will allow consumers to retrofit their homes As the technolog
346. quires power and fuel The fourth is imperative and additional research will need to be conducted to develop an antenna and transceiver for this subsystem 2 2 The Lunar GPS Constellation Design Originally two constellation designs were considered The first would have been derived from the GPS currently functioning for Earth specifically the altitude of the satel lites The second was where the constellation and orbital parameters would have been at a lunar synchronous orbit Although the orbital altitude of the lunar synchronous orbit would have been ideal since relativistic errors and the number of required satellites would have been to a minimum this altitude is too high above the L1 Lagrangian point This would have caused the satellites to be pulled back by the Earth s gravitational field Also even though the altitude for the Earth based constellation is below the L1 point it would be too close to the L1 point causing the circular orbit to perturb which would have greatly increased the orbital complexity This phenomena will be discussed shortly since it affects the orbital altitude of the satellites The proposed GPS constellation design in this paper uses the aforementioned requirements to govern the specific needs for the lunar system along with global coverage and inclined circular orbits Next several major factors were determined for the constellation s design 1 The minimum number of satellites to cover the moon
347. r C Sunder T Strasser A Zoitl O Hummer and G Ebenhofer Zero downtime recon figuration of distributed automation systems The CEDAC approach in Proc 3rd Int Conf Indust Appl Holonic Multi Agent Syst Regensburg Sept 2007 pp 326 337 11 M Khalgui O Mosbahi Z W Li and H M Hanisch Reconfigurable multi agent embedded control systems From modelling to implementation IEEE Trans Comput vol 60 no 4 pp 538 551 Apr 2011 12 Y Al Safi and V Vyatkin An ontology based reconfiguration agent for intelligent mechatronic sys tems in Proc 4th Int Conf Hol Multi Agent Syst Manuf Regensburg Germany 2007 vol 4659 pp 114 126 13 S Baruah and J Goossens Scheduling real time tasks Algorithms and complexity in Joseph Y T Leung ed Handbook of Scheduling Algorithms Models and Performance Analysis 2004 14 X Wang M Khalgui and Z W Li Dynamic low power reconfigurations of real time embedded systems in Proc lst Pervas Embedded Comput Commu Syst Mar 2011 Algarve Portugal 15 L GEORGE P COURBIN Reconfiguration of Uniprocessor Sporadic Real Time Systems The Sensitivity Approach book chapter in IGI Global Knowledge on Reconfigurable Embedded Control Sys tems Applications for Flexibility and Agility Ed Khalgui amp Hanisch ISBN 978 1 60960 086 0 2011 Published by Information Science USA 7 www loria fr nnavet cours DEA 2004 2005
348. r design layered software systems documentation 5 Demonstrate a practical understanding of the PIC32 interrupt system and writing interrupt handler routines 6 Write device driver program to interface a Keypad to a microcontroller 7 Write programs that configure and use the PIC32 core timer module 8 Write programs that configure and use the PIC32 standard timer modules in different ways 9 Write programs for controlling character LCD displays 10 Write programs for interfacing to touch screen graphics displays 11 Write device driver programs for serial interfacing using protocols such as UART SPI and I2C 12 Write programs that configure and use the ADC module 13 Demonstrate practical understanding of the PIC32 Parallel Master PORT PMP and its use for interfacing to peripheral devices 14 Demonstrate basic understanding of CAN 15 Demonstrate basic understanding of low power embedded processor architectures 16 Demonstrate basic understanding of innovation and entrepreneurship concepts Besides course topics addressing the core learning objectives listed above based on the needs of the audience and when time permits other miscellaneous topics are also introduced Common such topics include ZigBee DMA and USB The course is organized to have three hours of lecture meeting 3 days a week for one hour each and two hours of lab that meets once a week We have not yet found a good textbook for the course bu
349. r efficient description and have tried to apply this new method to the subset of AES CMAC algorithm The product works on Java Virtual Machine and high level synthesized hardware connected via Java Native Interface 2 Related works Fleischmann et al reported the principle style of co design environment for Java Virtual Machine in the reference 1 Our suggestion is similar to their idea but we consider high level synthesis and clearly orient our method to it Hwang et al 2 reported the advantage in performance of hardware method invoked via Java Native Interface 3 This result allows us to expect the improvement of performance in our target system 3 Consideration of high level synthesis To determine the weak point of high level synthesis and to concretize the requirements to our co design environment we have to observe high level synthesis co design environment from another viewpoint We present our understanding about them in following subsections 3 1 Granularity of operations and I Os The information processing is constituted of inputting processing and outputting If we have an operation circuit that has enough speed and enough small area power the whole processing must be done in moment However in real circuit we face to the limits of speed area and power Therefore information processing is divided into consecutive units of fine grained processing Fig 1 eed eee Input Proc Output Input Pro
350. r for network control is presented in 12 An adaptive neural network based feedback control scheduling for soft real time embedded systems is addressed in 13 and 14 In 11 author provides an approach to recover system from fault mode for parallel systems using check pointing Fault tolerant scheme and control theory A Trade offs between reliability FT and control theoretical methods are presented in 39 In 15 author uses a double Int l Conf Embedded Systems and Applications ESA 12 feedback based control scheduling approach for real time systems to optimize system performance A feedback based control scheduling for hard real time systems is addressed in 18 but this work doesn t address the Fault detection and Fault recovery mechanism together with feedback control theory Feedback based control scheduling co design approach for real time embedded systems is presented in 20 this work shows that closed loop systems are not hard real time systems although control systems are more robust in nature and uncertain to time variations but they also suffers from time jitters and data loss Author also provides different techniques to model time delays in system suffering from data loss over network In 22 author tires to capture the time variation of Safety Critical SC tasks over network for better resource management and bandwidth utilization in correspondence with sampling intervals and time delays to achieve QoS in terms of
351. r initiating the curriculum improvements were to keep the course up to date enhance the active engagement of the students and provide project opportunities for the students 2 Course Information The MS II course is typically taken at Junior II or Senior I term Students need to have taken MS I or have other similar background in microcontrollers and programming before registering for MS II The course is required for students majoring in Computer Engineering but it is also common among Electrical Engineering and Computer Science majors The course is followed by the elective courses DES IMR and capstone although there is no strict pre requisite relationship Especially students find the material covered in this course quite useful and practically applicable in the capstone design projects as most of the projects end up using some sort of microcontroller based system Course learning objectives By the end of the course students are expected to be able to do the following Int l Conf Embedded Systems and Applications ESA 12 1 Demonstrate practical understanding of the architectures of contemporary 16 and 32 bit microcontrollers such as Microchip PIC24 amp PIC32 2 Write simple assembly language programs for the Microchip PIC24 amp PIC32 3 Demonstrate practical understanding of the PIC24 amp PIC32 Memory organization 4 Demonstrate practical understanding of the software development process abstraction modula
352. r of 4x4 8x8 and 16x16 multipliers The leakage power was calculated for 3 cases The best case is when all the input data bits are 0 the average case is when half of the input data bits are O and half of the input data bits are 1 and the worst case is when all the input data bits are 1 Tables IV through VI show that 3 and 4 consume more leakage power in the best case and average case because they have floating point problems In the average case Table VI shows that the proposed design P1 reduces leakage power consumption by 18 12 and design P2 reduces leakage power consumption by 29 96 TABLE I DYNAMIC POWER Watt of MULTIPLIER 9 18E 06 100 00 3 18E 05 100 00 1 17E 05 127 59 4 04E 05 127 07 1 36E 04 128 56 1 05E 04 100 00 3 17E m TABLE II Area transistors of MULTIPLIER p2 soo rasse on TABLE III Delay ns of MULTIPLIER maana P1 2 27E 10 132 11 2 33E 10 135 76 2 79E 10 144 29 P2 2 33E 10 135 72 2 37E 10 138 27 2 83E 10 146 25 Oo 81 TABLE IV LEAKAGE POWER Watt of 4X4 Bits MULTIPLIER Best Average Worst TABLE V LEAKAGE POWER Watt of 8X8 Bits MULTIPLIER Best Average Worst TABLE VI LEAKAGE POWER Watt of 16X16 Bits MULTIPLIER Best Average Worst Base 4 01E 06 100 00 4 27E 06 100 00 4 18E 06 100 00 9 49E 06 236 63 7 26E 06 169 99 4 87E 06 116 54 4 8 19E 06 204 26 7 33E 06 171 63 4 55E
353. r text with fault GE Ae ip UB ign 1 Generated fault position on 9R of Key generation processing i z E Fixed logic units E Floating logic units Fig 4 Relationship between output cryptogram and fault injection position T HA T L Ss fs gt S amp S E E g a amp a In this figure the output cryptogram is expressed in 16 l byte blocks which are arranged side by side The byte position in the cryptogram where a fault has been generated is highlighted When the inverse operation from the fault I generation position was performed a fault was confirmed to i be generated in the lengthened path with 0 8 16 or 24 bits Thus when the critical path was used for the key generation section a fault was generated in the key generation section and the generated fault was propagated to the cryptogram os 4 3 Key Derivation Experiment a l In an experiment using the AES_KL whether a key Critical path Key generation unit could be derived was determined using a cryptogram where a fault was generated only in the key generation section In the Fig 3 Result of placement of the circuit elements of the experiment the key value was assumed to be unknown It AES KL was also determined whether a key could be derived from the 7 obtained cryptogram Figure 5 shows the experimental results obtained with the use of the AES_KL Fault generation bytes were compa
354. rame Data Frame Length 3 Length 8 Length 8 Length 8 Length 8 Length 8 Length 8 Length 8 Length 8 Length 8 Length 8 Length 8 Length 8 Length 8 Length 8 Length 8 ID 18EEFF80 ID 69F86186 ID 69F86186 ID 69F 86186 ID 69F 86186 ID 69F86186 ID 69F86186 ID 69F86186 ID 69F86186 ID 69F 86186 ID 69F86186 ID 69F86186 ID 69F86186 ID 69F86186 ID 69F 86186 ID 69F86186 CAN2 6B CAN2 6B CAN2 6B CAN2 6B CAN2 6B CAN2 6B CAN2 6B CAN2 6B CAN2 6B CAN2 6B CAN2 6B CAN2 6B CAN2 6B CAN2 6B Data E 07 B1 1C 6E E2 E2 66 Data E7 67 B1 1C 6E E2 E2 66 Data E7 07 B1 1C 6E E2 E2 66 Data 12 66 B1 1C F CA E2 66 Data 12 66 B1 1C F CA E2 66 Data 12 66 B1 1C F CA E2 66 Figure 9 CAN message received by GPS sensor The output window of CAN Pro Analyzer we get the first message data frame in 3 bytes data length and ID Identifier Bit is 18 EA FF FE16 hexadecimal means that this data have Sbit 8bit 8bit 8bit 2 CAN ID and first message define by request for address claimed or request PG is 00EE0016 means that first data PGN is 6092810 15 Second message data frame is 8 bytes data length ID is same as first message data frame Second message define by address claimed and data is NAME which has some fields We can explain all messages that classify by hexadecimal numbers with the help of ISO 11783 standards Figure 10 explain only two messages with some standards So our result shows t
355. ration 1 Create full backup of valuable data before making any major change on NAS If one is not able to gain access of NAS data disk volume s is not showing or facing any other problem on NAS 2 Try to create backup of valuable data as much as possible without modifying the content and configuration Do not format the NAS RAID until you confirm what actual problem is Formatting erases ALL data on the NAS Do not make any major configuration change on NAS Check status of all NAS hard disk drive and NAS logs for software or hardware errors If maintenance work is required on the NAS it may cause total data loss 3 4 5 6 6 Conclusion NAS devices offer Small and medium enterprise a number of important benefits over alternative storage devices NAS devices help to enhances overall network performance providing efficient flexible storage that is accessible independently from a specific network or application server As rich futures like ease of use and flexibility that your business needs and remote management capabilities of a NAS device make it easy to manage the entire storage environment even multiple NAS devices are located in geographically dispersed offices from one central location RAID technology performs a valuable role to increase NAS reliability Furthermore here are some unexpected possibilities that challenge NAS reliability In this paper as reported on the failure destiny of NAS storag
356. rds Robotic hazard terrestrial robotic module 1 Introduction Several robotic applications aim to provide a way of solving tasks in environments that are of difficult access or where there are risks for the human life Within this scope various options for robotic equipments have been shown to perform tasks in terrestrial aquatic mountains air or even in space Mobile robots can be grouped into two distinct groups robots controlled by humans and autonomous robots The autonomous mobile robots have the ability to move in dynamic and known environments without human control however this requires the development of algorithms that allow the definition of their location and movements 1 Other important set of information about the robotic modules is the features and elements inherent in the design In 2 the authors present the development of synthetic adhesives for attachment to robots vehicles allowing them to climb walls and access remote locations that do not allow access through the direct movement to the target The work in 3 presents the development of robots using an approach to sensor network and multi agent systems for movement A particular area for robots application is to perform tasks of preventive or corrective support in critical environments As shown in 4 the use of robots with long distance control enables the human control and the maintenance process in the critical environment without the human presen
357. re in conjunction with a DSP instead of a dedicated processor based on software embedded into the FPGA Therefore optimized codes were conceived for all processors and the performance for the co processor was evaluated considering different aspects such as e Time for parallel processing Int l Conf Embedded Systems and Applications ESA 12 e Mechanisms to connect the cores and the communication latency e Time to synchronize the process which include acknowledgment interrupt service request among others control signals The time for parallel processing besides being related to the frequency of operation is also related to the complexity of the circuit For instance long paths in a circuit design will limit the maximum frequency allowed to run the device In this way a common practice to avoid these problems is to specify the time constraints before hardware synthesis and to insert flip flops between different modules Although this technique increases the latency it generally allows a higher device operation frequency For modern software processors as DSP or ARM the synchronism with other devices can be made easily through interrupt services requests 18 Although these mechanisms allow low latency and can be generated periodically from a timer or from a external pins activated by a external device depending interrupt mapping the interrupt service routine have to handle multiple interrupt status bits to determine
358. red using the difference between the output 14 cryptogram with the fault and the correct cryptogram to examine the state in which data errors occurred Since the fault generation position could not be specified using the obtained cryptogram the algorithm against the key attacks could not be applied and the key could not be derived The above mentioned results indicate that although key attacks are logically efficient their threads against actual cryptographic circuits are low Output cipher text Correct cipher text TT TT TT TTT TI Wrong cipher text with fault ST g No revealed fault position Fig 5 Experimental result of AES_KL on actual LSI 5 Conclusion This study developed an evaluation platform that could verify the tamper resistance property of fault analysis attacks against an actual device using encryption LSI Using the proposed platform a fault could be generated at an arbitrary timing in an actual device A fault could be generated in the key generation section and it could be determined whether a key could be derived from the generated fault In the future we will evaluate resistance when a fault is generated in a cryptographic intermediate value 6 Acknowledgment This research was supported by Japan Science and Technology Agency JST Core Research for Evolutional Science and Technology CREST 7 References 1 S S Ah D Mukhopadhyay A Differential Fault Analysis on AES Key Schedule Using Sing
359. redictors of actual failure rates as seen by consumer in the field 2 In this paper we present one such study depending statics of the data recovery cases handled by Universe Infosoft in last three years We also proposed a data recovery method for some of failure causes 2 NAS RAID Configuration Redundant Array of Independent Inexpensive Disks is a well known technique that provides faster throughput with fault tolerant storage over single hard disk drive RAID appears as one logical drive to the computer appliance within having multiple drives It also used for providing access to larger pools of storage than single drives NAS provide power of various RAID configurations as RAID levels 0 5 5 spare 6 6 spare 10 and more Different different RAID levels have different fault tolerance capability RAID 0 use striping without any parity have no fault tolerance if any one of its drives is crashed then all data will loss Its contrary RAID 6 can afford two drives tolerate and RAID levels 1 2 3 4 5 6 and 7 can afford one hard disk drive crash because these have the one drive fault tolerance capability Nested RAID configuration can afford multiple drive tolerance depending on the number of drives and configuration type 51 52 3 Causes of Data Loss on NAS Device There are a number of conditions that can cause a NAS device failure NAS usually having proprietary operating system and is dedicated only to serving files without hav
360. reviously computed value Coo U O r Roo Co1 oF O Em mmm Ro 1 7 Cini S o E 0 Mm E 7 Rms Figure 2 Sum of absolute difference algorithm computed in parallel The difference between these images corresponds to the movement of elements of the current frame c that follows a reference frame r In order to determine the difference and to eliminate the redundancy between frames during the encoding motion estimation ME vectors are used As some studies has showed the ME module consumes more than 35 of the processing time for the x264 encoder which is one of the most efficient encoders implementation being able to run around 45 times faster 157 158 than the H 264 AVC reference software of the standard 16 17 The algorithm used in this study as reference for performance analysis is the same presented in 13 but optimized for the Blackfin ADSP BF533 processor 18 The code was also developed based on 19 which calculates the entire block of motion estimation for the H 264 AVC standard This code was ported to the Blackfin by using the same programming language However some sections of code were rewritten in order to optimize the performance for this particular digital signal processor The optimization techniques used consist basically in replacing memory pointers by storing data vectors in internal memory L1 which allows higher access speed These changes improved the performance for the a
361. rite Flew Tome onde Weanirer hp di z B tt ee te eph Bid oa a i Figure 10 Output for VVI mode In the future we plan to incorporate the Virtual Heart Model VHM from Dr Rahul Mangharam and colleagues at the University of Pennsylvania to generate a variety of different input signals www seas upenn edu zhihaoj VHM html Another contribution of the framework is to provide a convenient method to illustrate violations of safety and liveness properties discovered using some form of model checking and the model driven approach to safety critical software development For example the pacemaker models developed in 7 can be easily converted into code within the Pulse Generator In 7 the authors show how a transition between VDI and DDD pacing modes can lead to a safety property violation These pacing modes can be incorporated into the framework Then the pacing sequence identified to illustrate the problem can be specified using a simple Python script in pydaqtools Veniicie sense y 0 RI URI hysteresis true y RI VentriclePace y 0 RI LRI hysteresis false WaitVRP ye VRP WaitBeat R imit y VRP y VRP RI URI nysleresis irue VRP Figure 11 Pacemaker model for VVI mode Int l Conf Embedded Systems and Applications ESA 12 Users can also develop their own abstract models for various pacemaker modes For example we developed
362. roiescu F Daly K and Kuris B Event detection in an assisted living environment International Conference of the IEEE Engineering in Medicine and Biology Society 10 1 1O9 IEMBS 2011 6091869 pp 7581 7584 2011 6 Park K Lin Y Metsis V Le Z and Makedon F Abnormal human behavioral pattern detection in assisted living environments International Conference on Pervasive Technologies Related to Assistive Environments PETRA 2010 2010 7 Kinect for Windows http www microsoft com en us kinectforwindows 2012 8 News Bureau University of Missouri Using Kinect to Identify fall risk in seniors Craven Samantha http munews missouri edu news releases 201 1 0906 mu researchers use new video gaming technology to detect illness prevent falls in older adults 2012 9 Kinect SDK Programming guide http www microsoft com enus kinectforwindows develop ov erview aspx 2011 39 40 Int l Conf Embedded Systems and Applications ESA 12 Embedded Workbench Application of GPS Sensor for Agricultural Tractor Md Mostafa Kamal Sarker DongSun Park Woonchul Ham Enkhbaatar Tumenjargal and JaeHwan Lee 1 amp 3 Division of Electronic Engineering Chonbuk National University Jeonju si Jeonbuk Republic of Korea ai Convergence Research Center Chonbuk National University Jeonju si Jeonbuk Republic of Korea Abstract This paper presents a design of an embedded workbench
363. rol of location it is done through the new trajec tory coordinates calculated by the task T11 and through the current robot position The location is computed through task T3 Thereafter T13 controls the motors The dependencies between the 13 studied tasks are defined in Fig 1 as follows As for the system architecture it is com cofeyoope re Fig 1 Task graph of Robot footballer application posed of four processors In addition the robot architecture includes a set of memories cache memory DMA and RAM It also covers a battery and a communication bus The system Q presents the scheduling formal specification of the robot footballer experiment It is defined by the 4 tuplet Q Task Proc Alloc Prec 1 with e Task T1 T2 T13 each Task Task is determined by Task Ris Fy Ci 2 kR the date of the first activation P the period associated with the task C the execution period of the task for the P period e Proc P1 P2 P3 P4 e Alloc Task Proc a function which allocates a task to a processor Alloc is a surjective function In fact a processor is allocated to at least one task But a task must be assigned to only one processor e Prec Task x Task gt 0 1 a function which initializes precedence relations between tasks 3 dynamic Priority Time Petri Nets Preliminaries The integration of the dynamic calculation of priorities in Petri Nets presents
364. rol which deals with widely varying operating conditions can realize excellent system performance The embedded system should be designed carefully in order to have a robust precise fast and consistent performance In our previous work 7 9 we implemented a real time embedded control system to control the force and motion of a prosthetic hand The present work is a step ahead in the same direction where the authors explore the PIC 32 microcontroller as an embedded platform to simultaneously acquire the sEMG and skeletal muscle force sEMG sensors are placed on the ring finger motor point of the dominant hand of a healthy subject and the subject is asked to squeeze a stress ball which has a force sensing resistor attached to it The data is simultaneously captured using the PIC 32 embedded platform with MATLAB SIMULINK real time workshop RTW and regular NI LabVIEW data acquisition Both sEMG and force data is captured at 2000 Hz The sEMG signal is filtered using four different types of filters nonlinear Bayesian filters Exponential Poisson and Half Gaussian filter and wavelet transforms Daubechies 44 filter The corresponding skeletal muscle force is filtered by a Chebyshev type II filter 8 Among these different types of filters the wavelet Daubechies 44 filter 1s giving the best results 10 15 This paper is organized as follows the present section is followed by the Experimental Set Up then the Signal Pre Processing
365. rrect steady state based on the input patterns and their priority assignment at the rising edge of the clock CLK provided the look ahead input signal LS is active high PO_1 PI_1 PO_2 PI_2 PI_1 PO _3 PI_3 PI_2 PI_1 PO_4 PI_4 P1_3 P1_2 PI_1 112 PO_5 PI_5 P1_4 PI_3 PT_2 PI _1 PO_6 P1_6 PI_5 PI_4 Pr_3 PI_2 Pr_1 Po_1 P1_7 PI_6 Pr_5 P1_4 Pr_3 Pr_2 Pr_1 PO _8 PI _8 P1_7 P1_6 Pr_5 Pr_4 Pr_3 Pr _2 Pr _1 gt gt PO 8 PL 8 d pc7 gt gt gt PO7 PL7 O PI 6 gt PL5 cs ev9 PL4 gt PL3 gt PlL2 gt PL1 gt Y R V V l U U k lo D gt PO_1 Clock signal CLK Active high look ahead input signal LS Fig 1 Proposed 8 bit dynamic CMOS priority encoder The 8 bit CMOS priority encoder design portrayed above synthesizes the equations mentioned earlier by way of sharing common logic and corresponds to the domino logic style In Figure 1 the pMOS transistors marked as pcl to pc8 are basically precharge transistors which turn ON remain ON during the falling edge active low state of CLK thereby refreshing the primary outputs PO_1 to PO_8 When CLK makes a low to high transition rising edge and provided LS is active high logic 1 pMOS transistors pcl to pc8 are turned OFF as the evaluation phase commences Now a subset of the nMOS transistors ev to ev15 may turn ON based on the values of primary inputs From the equations listed earlier it can be understood that
366. s IEEE Trans on Parallel and Distributed Systems vol 7 pp 477 485 May 1996 H Kadota J Miyake Y Nishimichi H Kudoh K Kagawa An 8 kbit content addressable and reentrant memory IEEE Jour of Solid State Circuits vol SC 20 pp 951 957 1985 N Mohan W Fung M Sachdev Low power priority encoder and multiple match detection circuit for ternary content addressable memory Proc IEEE International SOC Conference pp 253 256 2006 J G Delgado Frias J Nyathi A VLSI high performance encoder with priority lookahead Proc 8 Great Lakes Symposium on VLSI pp 59 64 1998 J S Wang C S Huang A high speed single phase clocked CMOS priority encoder Proc IEEE International Symposium on Circuits and Systems pp V 537 V540 2000 C Kun S Quan A G Mason A power optimized 64 bit priority encoder utilizing parallel priority look ahead Proc IEEE International Symposium on Circuits and Systems pp U 753 H 756 2004 S W Huang Y J Chang A full parallel priority encoder design used in comparator Proc 53 IEEE International Midwest Symposium on Circuits and Systems pp 877 880 2010 TRUTH TABLE OF THE 8 BIT PRIORITY ENCODER Primary inputs Primary outputs enn nn na mm am mm aa mama mam ae Aa a A a Ee Ee O De JE ae pa fed i ed ae CO ie o o Oe SO 0 05 Os P des ea as ds Oe OO PO OF SOEs Oe 30 0 eT ede i a Oe OO 20 O E d don t care condi
367. s previously developed by the authors 22 VI CONCLUSION AND FUTURE WORK In this paper a real time sEMG acquisition and processing system was designed for the control of a prosthetic hand prototype The proposed design shows the same performance when compared with the standard EMG acquisition system The DE 2 1 electrodes are giving good results when compared to the DE 3 1 electrodes of the Delsys Bangnoli 16 system This proposed acquisition system miniaturizes the size and helps the transmission of the data from the microcontroller to the computer This helps the user to compare the accuracy precision and real time performance of the acquisition system For future work we are planning to implement a real time online model based force estimation along with controller design for position and force control based on this embedded platform 22 It will also be interesting to do the wavelet Daubechies 44 filtration online instead of post processing Finally we expand this sEMG acquisition to all the five fingers of the prosthetic hand prototype Int l Conf Embedded Systems and Applications ESA 12 ACKNOWLEDGMENT This research was sponsored by the US Department of the Army under the award number W81XWH 10 1 0128 awarded and administered by the U S Army Medical Research Acquisition Activity 820 Chandler Street Fort Detrick MD 21702 5014 The information does not necessarily reflect the position or the policy of the Governmen
368. s ago use of control theory in real time embedded systems design has increased massively and this trend keeps on evolving day by day 1 Due to the large number of real time constrains and requirements the complexity of feedback based control co design of embedded systems has increased and over 90 of the embedded controllers are used to control real time processes and deceives 2 Scheduling is the key lever in real time computing system for system performance and resource utilization Classical real time scheduling algorithms used in embedded system design are Rate Monotonic RM and Early Deadline First EDF From the control point of view all these scheduling algorithms are open loop 10 Also these algorithms are designed based on the assumption that mapping of the jobs tasks is predefined and Worst Case Execution Time WCET of jobs is known a priori Due to the open and uncertain environment execution time of both safety critical and non safety critical tasks varies It is very difficult to predict the timing constraints of the task before execution To avoid this uncertainty feedback based control scheduling algorithms are employed in control system co design of real time embedded systems 11 12 13 and 14 FCSA combines the feedback based control theory in hardware software co design of embedded systems so that the available resources can be used optimally and to increase the overall performance of the system Faults assoc
369. sEMG Wavelet Transforms Real time Data Acquisition I INTRODUCTION The functioning human body is one of the most intricate systems available Similarly surface Electromyography SEMG signals are quite complex and challenging to analyze Currently more than 2 million Americans have an amputation and the number of amputees is increasing by approximately 185 000 per year 1 Research related to upper extremity prostheses over the recent past has been focused on increasing function of the user coupled with reducing the psychological and emotional aftermath of dealing with limb loss A robotic prosthetic hand should be autonomous have a high level of functionality comfort and be easy to use 2 From 3 4 it is clear that electromyography EMG signals have sereved as a strong model for prosthetic function The EMG signal is a natural means of communication and can be recorded at the surface of the limb which is known as surface EMG sEMG Chandrasekhar Potluri is with Measurement and Control Engineering Research Center MCERC School of Engineering Idaho State University Pocatello Idaho 83209 USA email potlchan isu edu Madhavi Anugolu is with MCERC School of Engineering Idaho State University Pocatello Idaho 83209 USA email anugmadh isu edu Alex Jensen is with MCERC School of Engineering Idaho State University Pocatello Idaho 83209 USA email jensalex isu edu Girish Sriram is with MCERC School of Engineering
370. sPIC block set generates a hex file and this file is imported by MPLAB to program the PIC32 The sEMG and the corresponding skeletal muscle force data is read by using analog Input module There is an internal analog to digital converter ADC in the PIC 32 It has a 10 bit resolution so that it can differentiate up to 1024 different voltages usually in the range of 0 to 3 3 volts and it gives 3mV resolution The signals from the microcontroller are transmitted to the PC through the UART module in the PIC32 using serial communication In this design a virtual com port is created to feed the data via USB cable to the computer The signals from the ports are read by MATLAB Fig 2 depicts the acquisition system using the PIC 32 micro controller PIC 32 and Embedded Platform DELSYS sEMG System Fig 2 Experimental Set Up with PIC 32 Embedded Platforms and DELSYS EMG System V RESULTS AND DISCUSSION Surface Elecromyography SEMG and the corresponding skeletal muscle force data was acquired from the microcontroller through UART channel 2 of the PIC32MX360F512L by a virtual com port via USB at 57600 baud rate The data from the microcontroller was converted into uintl6 data before it was transmitted through the UART The PIC32 microcontroller is running at 80 million instructions per second MIPS with its phase lock loop PLL activated It was running at an external clock frequency of 8 MHz with internal s
371. satellites needs to be calculated For redundancy usually six visible satellites is deemed satisfactory 1 2 3 Satellite Coverage Determination Since satellites transmit their signals in concentrated bands of energy direct line of sight is required for signal acquisi tion to and from the satellites and the receiver It is obvious that there are a limited number of visible locations where a receiver can be at a given time with correspondence to the position of a satellite For instance a receiver at the south pole does not have line of sight with a satellite in position orbiting above the north pole With line of sight being a pivotal requirement this is used to determine the minimum number of satellites that need to be orbiting within a given orbital plane in order to have line of sight coverage from here on out referred to simply as coverage The first step that was employed to calculate this minimum number uses Rider s method on determining inclined circular orbits 3 Consider the first equation for the Rider method COS Q cos 0 a ema 1 In this equation 0 is the central angle of the body is the elevation angle h is the orbital altitude of the satellites and r is the radius of the body in this case the moon Solving for 0 gives the following equation COS Q Ca at anae i 2 0 arccos 2 Q 2 The next step is to use 0 to calculate the minimum number of satellites for a given plane Below is th
372. satellites per plane with 30 satellites in total Next using equation 8 the time for update was esti mated using the data for the CSAC Assuming a distance tolerance of ten meters the time for an update would be over 55 minutes and 30 seconds This time is a little short but definitely manageable If the distance tolerance is extended to 50 and 100 meters the time for update is a little over approximately 4 hours and 30 minutes and approximately 9 hours and 15 minutes respectively 5 Conclusions and Future Directions This paper presented a constellation design for a Lunar GPS using the CubeSat platform incorporating CSACs This GPS considers a Rider constellations of two orbital planes and eight satellites per plane for minimum position deter mination or fifteen satellites per plane for redundancy at an altitude of 3 34x10 km The CSAC considered is estimated to have an update interval of approximately 55 minutes and 30 seconds for a distance accuracy of 10 m approximately 4 hours and 30 minutes for a distance accuracy of 50 m and approximately 9 hours and 15 minutes for a distance accuracy of 100 m The system is thus feasible and design costs are well within possible ranges Future research will include but not be limited to opti mizing the number of satellites in each plane considering areas of zonal coverage increasing the time between clock updates transceiver and antenna design the possible effects of the lunar ion
373. semantics is presented with a dPTPN firing machine dPFM For each marking M the dpfm initializes a set of transitions dFT composed of enabled temporal transitions FT and enabled compound transitions FT STep d The initializations is called Firiability processing dFTs FT OE Tees 5 let tET tEedFT SteFT Vte Plar 6 th FT teET B t lt M METH ED NE Biel e oe Next valid transitions are selected from FT to VT by applying the Validity processing All urgent transitions must be indicated in VT to be ready for firing VT t FT HI t T t 7 The df T presents all concurrent transitions To solve this conflict the dpfm calculates the priority of each tran sition using the marking M and the coef matrix Then the dF T is filtered to present only the transitions with the highest priority This filtering is made with the Step Selection processing In fact this processing is able to select the Tep transition having the highest priority according to its neighborhood eq 8 Vis Lens Dep Lee 18 neighbor of Te lt gt dp P such that Br P Tep OABr P Tepa 0 8 In this step the proposed dPTPN is able to support a selection policy In 13 the authors have proved that dPTPN can attribute the priorities to transitions sharing the place processor according to the LLF policy In 14 the authors has further proven their extension with the Earliest Deadline First pol
374. ses include activities on low level programming to give insights on how the processor operates manipulates data between different types of storages and see how the compiler manages the hardware resources etc But for the most part the laboratory activities focus on peripheral interfacing techniques to let students explore ways the MCU talks to common input output devices in embedded environments The other elective courses listed above focus on specific application domains of embedded systems The DES course presents embedded system architectures for distributed and networked systems in industrial and automotive application domains It introduces different networking technologies and addresses timing reliability and safety issues in critical applications The IMR course focuses on embedded system application for mobile robotic systems General architecture of mobile robots system components important hardware and software subsystems sensors and actuators localization path planning and navigation techniques are presented 126 All the courses in our curriculum undergo continuous improvement process in attempts to bring the courses up to date in response to technological advancements as well as feedbacks from students and our industry partners For example when the MS II course was first introduced in our Computer Engineering curriculum it was offered based on the Motorola MC68332 microcontroller As this processor was getting dated in
375. specification 2 0A and 2 0B is integrated in STM32F107 and also 2 4 inch TFT LCD Panel 320 240 with touch screen It is composed of CAN kernel with 256KB Flash and 64KB RAM internal memory message processing unit and register CAN controller has 32 message destinations which can be used to send or transmit data Received data message destinations and identification code are storage in Message RAM All the protocol functions such as data transmission and receipt of filter are performed by CAN controller Through Int l Conf Embedded Systems and Applications ESA 12 the special register in the main control chip CAN controller can be configured to visit received data and transmitted data In this way CAN communication can be realized by use of less bandwidth of CPU STM32F107 can perform all the functions of the data link layer and application layer of ISOBUS protocol Figure 5 shows test connection configuration between working PC and test board for checking the ECU of GPS sensor working status Time ACK CE ey i ARM 32 bit AMTEL mini Embedded Cortex M3 sid uses i SCM Workbench with Realsis Application Od e Controller 2 4inch TFT LCD Panel 320 240 with touch screen ee ke USB1 USB1 Test board STM32F107 board Working PC Figure 5 Connection configuration between working PC and test board In this figure test board COM1 port i e name of serial port hardware for input and output is linked with
376. ss you should clones of all hard disk drive to prevent further alteration on original data If you got unaccepted result you can look for data recovery experts You need clone of drives equal to total number of drives less the fault tolerance drive according to RAID current configuration for NAS recovery process 5 5 1 When NAS working drives are not enough If there is the situation of hard disk drive failed more than fault tolerance of configured RAID and not able to make required drives clone then you have to look to a data recovery company for complete required clone If Drive has any electrical component failure on its PCB need to be repaired or there are clicking sound coming from hard drive chamber may need clean room data recovery facilities But generally one has no clean room facilities electronic PCB repairing instruments and experiences to make successful clone To override these situations one can gets required drive clones from a Data Recovery Company And then can start recovery process at his her end 5 5 2 Successful NAS recovery In order to complete successful NAS data recovery you must have in depth knowledge of drive structures hex MFT mount points and partitions offsets to avoid farther data loss while attempting to recover the damaged RAID array Data recovery process Install all cloned drives to installed Ubuntu computer system as according their connecting interface Boot system with Ubuntu Frist get
377. ssor memory Human Machine Interface HMI and interface with the CAN bus Therefore the IsoAgLib is divided into two sections the library itself and HAL The HAL is responsible for communicating with the operating system OS or BIOS device that is running the application as can be seen in Figure 7 We implement CAN bus is real time operating system The application program initialized CAN controller and accessing CAN bus 4 2 Programming methodology For executing our GPS application program we should build some configuration of development board STM32F107 into the IAR embedded C C programming interface We created all configurations by using ARM C C 12 and ISOAgLib libraries and our self what we needed Firstly initializing all peripherals of our test board STM32F107 code main cpp void Init All Periph void RCC Configuration InitDis GPIO configuration NVIC configuration Here RCC Reset and Clock Control configuration RCC Configuration is creating system clock configuration for all peripherals initializing display JnitDis is LCD display configuration GPIO General Purpose function of Input and Outputs configuration GP O_Configuration is creating structure of 43 every pin i e CAN pin RX TX for our development board and setting their mode NVIC Nested vectored interrupt controller configuration NVIC_Configuration is enables low latency interrupt processing and efficien
378. ssor systems and proven it correct Finally our important future work is the generalization of our contributions for the Re configurable real time embedded systems References 1 S Baruah G Koren B Mishra A Raghu nathan L Rosier and D Shasha On line Scheduling in the Presence of Overload Proc of IEEE Symposium on Foundations of Computer Science San Juan Puerto Rico October 2 4 1991 G Buttazzo and J Stankovic RED Robust Earliest Deadline Scheduling 3rd Int Work shop On Responsive Computing Systems Austin 1993 M Dertouzos Control Robotics The Procedu ral Control of Physical Processes Proceedings of the IFIP Congress 1974 4 10 11 12 X Wang M Khalgui and Z W Li Dynamic low power reconfigurations of real time embedded systems in Proc Ist Pervas Embedded Com put Commu Syst Mar 2011 Algarve Portugal C Angelov K Sierszecki and N Marian De sign models for reusable and reconfigurable state machines in L T Yang et al Eds Proc of Embedded Ubiquitous Comput pp 152 163 2005 M N Rooker C Sunder T Strasser A Zoitl O Hummer and G Ebenhofer Zero downtime re configuration of distributed automation systems The CEDAC approach in Proc 3rd Int Conf Indust Appl Holonic Multi Agent Syst Regens burg Sept 2007 pp 326 337 H Gharsellaoui M Khalgui A Gharbi and S Ben Ahmed Feasi
379. st performance best cache size and in this paper we answer to these questions l In which cache sizes embedded applications reach the highest performance in the lowest energy optimum cache size 2 What is the effect of leakage energy on the exploration of the cache size for embedded applications Cache size ranges of 20 have many configurations and their exploration is just based on performance While as mentioned above the power consumption is as important as performance in embedded processors In this paper we reduce the search space and introduce the cache sizes which have the optimum size i e the best performance per power for embedded applications by considering the energy consumption of each introduced configuration of 20 W T Shiue et al 12 introduced an algorithm for finding the optimum cache configuration considering the cache size energy consumption and the cycles required for executing the applications In 13 an analytical model to compute the power consumption of a cache is presented Authors of 16 17 presented a formula to compute the energy consumption of cache but they didn t consider the number of cache accesses There is no parameter that shows the effect of cache misses on the leakage power In 16 the authors have presented a model for exploring energy consumption but just considering hit rate Although 19 20 explored wide ranges of parameters such as size of the cache block size and associatively that
380. sted the feasibility of the same task sets Blackberry Bold 9700 and Volvo by another algorithms so that we can compare the re sults directly 6 1 Discussion and Evaluation The test greatly reduces the processor utilization fac tor U y nD in comparison to the original processor utilization factor so the combination of both three solutions in order to obtain the optimisation of the response time by calculating Lopt leads to an im proved algorithm for the analysis of asynchronous sys tems So we can therefore confirm that this method is nowadays very advantageous given the fast response time and the performance of the RT Reconfiguration tool By applying the three solutions of this tool RT Reconfiguration we can conclude also that our ap proach can allow more reactive and also more efficient feasible systems This advantage was increased and proved clearly with the Blackberry Bold 9700 system proposed by 14 and by the volvo case study proposed by 5 153 154 7 CONCLUSION AND FU TURE WORKS In this paper we propose a new theory for the mini mization of the response time of periodic asynchronous constrained deadline real time tasks with EDF algo rithm that can be applied to uniprocessor systems and proved it correct As future work we are planning to extend our study to the case of FPP scheduling policy and to sporadic task sets with a large size systems the number of tasks is equal to 200 and it can be more an
381. system was same as observed in the well lit room with 800 lumens Since the Danger message is displayed for both scenarios it can be concluded that the performance is not affected by the ambient lighting conditions As is evident from Figure 5 b the color video stream window is dark showing that the room had no ambient lighting ih MainWindow os D Skeleton rendered if full body fits in frame Depth Stream Color Video Stre dy fits in frame 32 fps b 37 Shy MainWindow Fae be U oman sa aes a Skeleton rendered if full body fits in frame Depth Stream Color Video Stream Safe Figure 4 Simulation window for a normal lighting 800 lumens b poorly lit condition 10 lumens and c dark condition 0 lumens ee aaa ih MainWindow a pn e Skeleton rendered if full body fits in frame Depth Stream Danger 31 fps a a a a m eaa ih MainWindow a gt a g noi D B Skeleton rendered if full body fits in frame Depth Stream Color Video Stream b Figure 5 Danger condition in a a well lit room 800 lumens and b a dark room 0 lumens 38 The experiment was performed while holding both arms not perfectly perpendicular to the body The borderline conditions where the system stops to recognize the gesture is shown in Figures 6a and 6b respectively ih Main
382. t Thus those are inserted next instruction which creating and destroying activity and event execution A log which is made by TIA and TIE explain that operation of activity is normal and event has no problem because it is impossible to be generated the log if program is not running well TIC sensor captures a screen in various devices to discern difference Actually to compare two images is a role of developer because they must be too subjective The tool can only give numerical value related to image s color or structure and those value is use to divide into two groups which need to verity and not DIV is monitored values of some variables because variable must have boundary and an error is occurred when the variable has under or upper boundary DIS is to make a log related to system status The reason why gathering system status log is that embedded system like a mobile affects from system a lot It means that it is important a system log to find a bug on software The automatic mode is used for finding unexpected error in software because it generates randomly input in test case Fig 3 illustrate automatic test case generator ACSF Project Editor TestSuite oo Activity List Sensor Type Test Case Information Activity Name Monitoring Sensor Type Testcase Name Description P F HelloAndroid2 y Te A_110000_HelloAndroid Select All insert Delete Figure 3 Automatic Test case Generator 3 2 Automation running the test cases
383. t and no official endorsement should be inferred For purposes of this article information includes news releases articles manuscripts brochures advertisements still and motion pictures speeches trade association proceedings etc Further the technical help from Dr D Subbaram Naidu and Dr Marco P Schoen 1s greatly appreciated REFERENCES 1 ACA News National Limb Loss Awareness Month 2011 http www bocusa org aca news national limb loss awareness month 2 Roth B and Salisbury J Zinn M A new Actuation Approach for Human Friendly Robot Design Int Robot Res pp 379 398 2004 3 N Dechev W L Cleghorn and S Naumann Multiple finger passive adaptive grasp prosthetic hand Mechanism and Machine Theory 36 2001 pp 1157 1173 4 H Kawasaki T Komatsu and K Uchiyama Dexterous Anthropomorphic Robot Hand With Distributed Tactile Sensor Gifu Hand Il IEEE ASME Transactions on Mechatronics Vol 7 No 3 September 2002 pp 296 303 5 M Zecca S Micera M C Carrozza and P Dario Control of Multifunctional Prosthetic Hands by Processing the Electromyographic Signal Critical Reviews in Biomedical Engineering 30 4 6 2002 pp 459 485 6 C Castellini and P van der Smagt Surface EMG in advanced hand prosthetics Biological Cybernetics 2009 100 pp 35 47 7 C Potluri P Kumar J Moliter M Anugolu A Jensen K Hart and S Chiu Multi Level Embedded Motor
384. t and 32 bit PIC microcontrollers respectively 3 Microchip Peripheral Library 8 9 that provides high level C functions to access the microcontroller peripheral features 4 Microchip Graphics Library 10 4 Choice of MCU The main motivations for the choice of PIC24 32 MCUs are listed below The PIC24 and PIC32 processors have rich instruction set architecture ISA featuring 16 and 32 general purpose registers respectively and support for both two operand and three operand instructions Compatibility of the PIC24 and PIC32 family makes it easy to cover both processors in a single course Moreover learning both of these 16 and 32 bit processors makes it easy for the students to make informed optimal choices for given projects Microchip offers a rich set of the processor family members with a range of pins data memory program memory and on chip peripheral devices Since the low cost PIC MCUs have become one of the top choices by faculty and students in capstone and other projects in our department it would be beneficial for the students to have an exposure to such hardware and tools Availability of free academic versions of the compilers and IDE for program development Availability of low cost hardware development kits programmers and debuggers Besides the hardware and software kits described above there are also several additional project specific components Due to our partnership with Microchip we w
385. t of assigning the sub application number to the global variable in the start function of the sub application In this way there exists only one operating mode restricted by the sub application number This plays an important role in implementing the callback distributor The typical callback distributor distributes the OS callback to a specific callback function according to the sub application number though it is up to the developer how to design the callback distributor An example of our model is depicted in Fig 3 Given a large application L which consists of six sub applications from A through A and two callback function distributors In this figure callback function distributor 1 distributes one type of callback to A and A and callback function distributor 2 distributes 2 type of callback to A As and Ag The main function of the L exists in X which starts the RTOS and then the program control moves to A4 Fig 3 An example of an application model The asterisk means the first driven sub application Int l Conf Embedded Systems and Applications ESA 12 With this model we developed after individual testing of sub applications the integrated testing of the large application is performed Each sub application is running and tested by adding the main function If all sub applications are found to be enough reliable and secure with respect to the program function or memory requirements they are ready When they
386. t performance in highest energy dissipation Based on proposed power model 36 cache configurations of 20 will be reduced to 12 by using the overlapping method of fig l a All extracted 12 cache configuration have listed in fig l c and performance penalty of each one related to configuration have shown in figl c in the right most column Configuration number 5 is the best one considering but just performance parameter 4 Analysis of 12 nominated cache configuration Power area and timing need to be studied together more than ever as technology keeps scaling down However our ability to propose design and evaluate new architectures for this purpose will ultimately be limited by the quality of tools used to measure the effects of these changes Accurately modeling these effects also becomes more difficult as we push the limits of technology Future multi many core designs drive the need for new tools to address changes in architecture and technology This includes the need to accurately model multi core and many core architectures the need to evaluate power area and timing simultaneously the need to accurately model all sources of power dissipation and the need to accurately scale circuit models into deep submicron technologies 86 To find the best cache hierarchy for 12 mentioned cache size configurations we have explored some other important parameters using MCPAT 23 tool an integrated power area and timing modeling fram
387. t processing of late arriving interrupts The bxCAN Basic Extended CAN 13 module handles the transmission and the reception of CAN messages fully autonomously Standard identifiers 11 bit and extended identifiers 29 bit are fully supported by hardware Secondly SysTick timer STK configuration SysTick Conf is setup SysTick Timer for interrupts CAN interrupt CAN Interrupt is interrupt mode for CAN The processor has a 24 bit system timer SysTick which counts down from the reload value to zero reloads wraps to the value in the load register on the next clock edge then counts down on subsequent clocks The bxCAN interrupts has four interrupt vectors dedicated Each interrupt source can be independently enabled or disabled by means of the CAN Interrupt Enable Register CAN IER Thirdly Universal synchronous and asynchronous receiver transmitter USARTI_ Configuration configuration is the configuration of the CAN bit timing According to the CAN specification 14 the bit time is divided into four segments see Figure 7 The synchronization segment the propagation time segment the phase buffer segment 1 and the phase buffer segment 2 Each segment consists of a specific programmable number of time quanta see Table 1 The length of the time quantum t which is the basic time unit of the bit time is defined by the CAN controller s system clock fas and the Baud Rate Prescaler BRP tj BRP fos Typical system
388. t start time of task gi 1 e the last time before the current time at which task o gained the processor fi denotes the estimated finishing time of task g i e the time according to the current schedule at which task o should complete its execution and leave the system L denotes the laxity of task o i e the maximum time task g can be delayed before its execution be gins R denotes the residual time of task o i e the length of time between the finishing time of o and its abso lute deadline Baruah et al 1 present a necessary and sufficient feasibility test for synchronous systems with pseudo polynomial complexity The other known method is to use response time analysis which consists of computing the worst case response time WCRT of all tasks in a system and ensuring that each tasks WCRT is less than its relative deadline To avoid these problems and to have a feasible system in this paper our proposed tool RT Reconfiguration can be used For this reason we present the following relationships among the parameters defined above Ly de ae C 2 Ri di fi 3 lieti PHS Larevietl q4 The basic properties stated by the following lemmas and theorems are used to derive an efficient O n m algorithm for analyzing the schedulability of the spo radic task set whenever a new task arrives in the sys tems Lemma 1 Given a set 01 02 0n of ac tive sporadic tasks ordered by increasing deadli
389. t the 13 individual level Figure 7 and Figure 8 show the SPI and USART connections Tek aL Trig d M Pos 0 0005 MEASURE r CHI f ee 15 24 CH2 RMS h 2 CH1 ie Freq SAH CH2 Freq 59 95H MATH Off Mone M 5 00ms CHT Z 0 007 1 0ec 11 12 36 93 3r93HI Center lapped Voltage sense XFMR OUT TAFAJ CHi 5 00 CH 5 00 Figure 4 Voltage Sense Transformer Output two AC waveforms 180 out of phase M Pos 0 0005 MEASURE CH1 RAMs 15 2 CH2 RAMs 18 24 CH 2 7 Freq 60 10H z CH2 Freq 1 667kHz MATH Off None CHI 0 00 Sad JOSHZ Tek N Trig d CH2 5 00 M 5 00nms 1 Dee 11 1241 5 5 Vreg and 3 3 Vreg IN Figure 5 Full Wave Rectifier Output CH 2 CHI 5 00 psv mM 0 J C16 14 U2 3 T tpF K VA VO C25 C24 er CS5460 Se OtpF O1pF Ok 1 R25 9 PFMON Vine NNN e ANN VN 2 ppe 1 301 CPUCLK lt CPUCLK gt 100k RI i 5 2 C15 XOUTI R24 lt 1 k lt lt 24 Y2 10k 100K 301 4700pF XIN lt RI R23 10 b m WN Nv iVa i O96MHz Tass R29 ANN My x IIN 180k ae RESET CSS E SRI Cn 23 Cia gt 7 0 S00 Pa 0 015yF soo So1_ f 1 5 S Q S iw SCLK lt SCLK SR19 mnan int 20 a 10k 1 2 an A verre EDR HZ 4EGIR RAJ q 7a rer out out E EOUT C21 9 ps VA DGND F kol Figure 6 CS5460A Connections and Sense Conditioning Circuits 74
390. t the system s be havior Indeed a hard real time system typically has a mixture of off line and on line workloads and as sumed to be feasible before any reconfiguration sce nario The off line requests support the normal func 161 162 tions of the system while the on line requests are spo radic tasks to handle external events such as operator commands and recovery actions which are usually un predictable For this reason and in this original work we propose a new optimal scheduling algorithm based on the dynamic priorities scheduling Earliest Dead line First EDF algorithm principles and on the dy namic reconfiguration in order to obtain the feasibil ity of the system at run time meeting real time con straints and for the optimization of response time of this system Indeed many real time systems rely on the EDF scheduling algorithm This algorithm has been shown to be optimal under many different con ditions For example for independent preemptable tasks on a uni processor EDF is optimal in the sense that if any algorithm can find a schedule where all tasks meet their deadlines then EDF can meet the deadlines 3 This algorithm assumes that sporadic tasks span no more than one hyperperiod of the peri odic tasks hp 0 2 LCM mazz axz 1 where LCM is the well known Least Common Multiple of all task periods and axz 1 is the earliest activation time of each task 7 The problem is to find which solution
391. t we use a couple of reference books 1 2 device datasheets library reference manuals user guides and application notes from the manufacturers There are a total of six required and two optional lab assignments in the course The list of the 8 lab assignments is given below 1 Familiarization with the MPLAB programming environment Core concepts a Integrated development environment b Code entry compilation and linking c Program debugging using processor simulation environment d Single stepping breakpoints watching variables e Examining and modifying register and memory contents Int l Conf Embedded Systems and Applications ESA 12 f Using the built in Logic Analyzer 2 Assembly language programming on Microchip PIC24 MCU Core concepts a b es d or f Assembly language structure Assembly directives and include files Implementing a task in assembly language Declaring variables and understanding how they are allocated memory Memory organization Instruction cycles and clock cyles 3 Simple Input Output interfacing of the PIC32 to switches and LEDs Core concepts eno Tp f Basic I O port hardware architecture Configuration and status registers Configuring a general purpose I O pin for output Configuring a general purpose I O pin for input Switch de bouncing using hardware and software techniques Timing using software idle loops 4 Interfacing a keypad to the PIC32 and displaying c
392. tUntilCanReceiveOrTimeout 132_idleTimeSpread ecuShutdown return 0 Figure 8 Application program of GPS sensor in IAR Embedded Workbench 5 Workbench Results and Discussion The main task of this work is developing the test board as an ECU for agricultural tractor GPS sensor With following the programming methodology we can build our application program In IAR Embedded Workbench the program should be downloaded to ARM Cortex M3 microcontroller by AMTEL mini JLINK for debugging When debugging is completed then run the program After finishing all the test board is performing as an ECU of GPS sensor Now the CAN messages are frequently received by the test GPS sensor We can easily analysis those messages with standards by CANPro Analyzer v1 0 Figure 9 shows the CANPro Analyzer window define CAN message received by our test GPS sensor CANPro Analyzer V1 0 Ha BAEO HIM xn zz E CAN2 6B CAN2 6B T820 Data 00 EE 66 Data 1B 66 EO FF 61 19 GE AG Data 4C 31 B1 1C 75 E7 E2 66 Data 4C 31 B1 1C 75 E7 E2 66 Data E7 67 B1 1C 6E E2 E2 66 Data E7 67 B1 1C 6E E2 E2 66 Data E7 07 B1 1C 6E E2 E2 66 Data E7 07 B1 1C 6E E2 E2 66 Data E7 67 B1 1C 6E E2 E2 66 Data E7 67 B1 1C 6E E2 E2 66 Data E7 07 B1 1C 6E E2 E2 66 ID 18EAFFFE Data Frame Data Frame Data Frame Data Frame Data Frame Data Frame Data Frame Data Frame Data Frame Data Frame Data Frame Data Frame Data Frame Data Frame Data Frame Data F
393. taah h PA at aaa aa aa a ah a dadada aah Aa GP 1000 1000 500 500 0 0 0 50 100 150 200 0 50 100 150 200 Time interval Time interval b On demand victim selection 600 600 m 400 Hh il il f FAN N 400 i i Aa ai s IAT 200 200 0 0 0 50 100 150 200 0 50 100 150 200 LINK GC g 3 Time interval Time interval c 1000 2 600 ad 400 200 0 0 50 100 150 200 Time interval Time interval d Fig 6 IOPS comparison between the on demand victim selection scheme and the 2LGC scheme a workload 1 b workload 2 c workload 3 and d workload 4 References 1 Sanghyuk Jung Sangyong Lee Hoeseung Jung and Yong Ho Song In page error correction code management for MLC flahs storages Proceedings of the IEEE MWSCAS 2011 2 Sang Won Lee Dong Joo Park Tae Sun Chung Dong Ho Lee Sang Won Park and Ha Joo Song A log buffer based flash translation layer using fully associative sector translation ACM Transactions on Embedded Computing Systems vol 6 no 3 article 18 July 2007 3 Sanghyuk Jung Jin Hyuk Kim and Yong Ho Song Hierarchical architecture of flash based storage systems for high performance and durability Proceedings of the IEEE ACM International Conference on DAC 2009 4 Aayush Gupta Youngjae Kim and Bhuvan Urgaonkar DFTL A flash translation layer employing demand based se lective caching of page level address
394. tates through the use of curPage offsets For example as shown in Figure 3 b the FTL updates the page map table with a new physical page number and erases the block whose physical block number is 5 when page copy operations are finished In this case the FTL needs to copy two pages and erase one block and update the map tables during the single block garbage collection process Compared with on demand victim selection mechanisms 2LGC single block garbage collection is quite effective for supporting a preemptive storage system 4 3 Algorithm Figure 4 shows the two level lists used in the 2LGC algorithm The operational sequence is as follows The FTL continuously checks the number of invalid marked pages for the corresponding block whenever the page validation mark flag of each page map entry is updated If the number of invalid marked pages in that block is over a threshold value the 2LGC stores the block address in the Candidate list The entries in Candidate list are not to be sorted in the initial state The 2LGC can reconstruct the Candidate list only when the following two cases occur 25 1 If the Candidate list is full a block whose entire pages are invalid is demoted into the Garbage block list If user workloads such as file copies and internet explorations are used several blocks can be expected to be demoted into the Garbage block list because they include a large number of sequential program operations However if the
395. ted by R amp DB Support Center of Seoul Development Institute Korea under Seoul R amp BD Program ST100107 6 References 1 Android Testing Framework http developer android com guide topics testing index html 9 2 Curxiong Hu Iulian Neamtiu Automating GUI Testing for Android Applications Proc of International Workshop on Automation of Software Test pp 77 83 2011 3 Doo Ho Park Won Shim Tae Wan Kim Chun Hyon Chang Android Software Test case Generation System using Record PlayBack Proc of the Korea Computer Congress 2011 Vol 38 No 1 B pp 171 174 2011 4 JUnit http www junit org 5 Monkey UI Application Exerciser http developer android com guide developing tools monkey html 6 Robotium http code google com p robotium 7 Wei Hoo Chong MIET RPB in Software Testing Proc of the International Multi Conference on Computing in the Global Information Technology ICCGI pp 8 13 2007 8 Won Shin Tae Wan Kim Chun Hyon Chang Portability Analysis Tool for Android Application Proc of the JCCIS Vol 4 No 2 pp 186 189 2010 9 Won Shin Jung Min Park Tae Wan Kim Chun Hyon Chang Methodology of Automatic Test case Generation for Android Software Proc of the Korea Computer Congress 2011 Vol 38 No 1 A pp 198 201 2011 10 Won Shin Jong Soo Seok Tae Wan Kim Chun Hyon Chang Test Automation System for Android
396. tems and Applications ESA 12 uploaded to the ConnectPortX4 Gateway Creating the project also enables the remote call interface handler presentation to enable the gateway to talk to the iDigi platform READ SDI BADIA je 55460 a picaerse2 XBEE 2 RF were soo wame gt x LOAD VARIABLES amp DEFINITIONS IitPerigh mma bof iitvales MAINLOOP VOLTAGELOOP i CURRENT LOOP iN APPARENT POWER LOOP 5 TRUE POWERLOOP V POWERFACTOR LOOP Figure 9 Assembly Program Flow Chart A Google Appspot account must be established to use the servers After the account is set up the web interface is deployed to Google s servers When the webpage is enabled it is then pointed to the 1Digi developer URL in order to retrieve the serial data from the ConnectPortX4 Gateway Figures 10 and 11 are helpful in understanding how the languages and development environments are associated iDigiDia loud XBEE2RF GatewayVia nen Router local EE A dia py Google Sy Appspot dia zip app yaml t main py t index html Figure 10 Python Program Flow Chart iDigiDia XBEE2RF gt GatewayVia A tee Router local T t i l index html index html Figure 11 HTML CSS Program Flow Chart 75 4 3 Final Design The first step in completing the final design is implementing the Cirrus Logic CS5460A IC and associ
397. the number of invalid marked pages from each block by search ing the entire flash memory space Extracting the number of invalid marked pages will take longer for larger capacity flash storage because flash storage has the same number of block map entries as the number of data blocks Second the FTL continuously compares the number of invalid marked pages from each block until enough victim blocks are select ed in order to select victim blocks having the largest number of invalid marked pages for each block Although it is as sumed that the FTL uses a quick sort algorithm which has the best performing speed among the well known sorting algo rithms the operational delay becomes O NlogN in general case and O N in the worst case 4 2LGC 4 1 Victim Block Selection The 2LGC scheme is able to isolate victim block selec tion from garbage collection In short this scheme maintains the victim priority of target blocks by sorting the blocks by the number of invalid marked pages during run time The two level lists are used to implement the run time victim block searching technique as shown in Figure 4 a candidate list and a garbage block list along with other de tails that are explained in Section IV C In the 2LGC scheme the FTL stores physical block addresses in the two level lists depend ing on the numbers of invalid marked pages and uses them when necessary This allows the flash storage to reduce block searching overheads and vi
398. the case of periodic tasks as it was studied before we have Si ml At Dy I C Now according to the previous three solutions calcu lated by the Intelligent Agent Solution 1 Solution 2 and Solution 3 we define e L according to Solution 1 by the following expres sion L min At gt 0 S1 m 0 At At where S m 0 At ei ca C and M lt m re sulting from the removal tasks generated by the first solution Solution 1 e L according to Solution 2 by the following expres sion Lz min At gt 0 S1 m 0 At At where S1 m 0 At ae E from the new periods generated by the second solution Solution 2 e Ls according to Solution 3 by the following expres sion L3 min At gt 0 S1 m 0 At At where Sy m 0 At hee from the new worst case execution times generated by the third solution Solution 3 L is thus respectively L and L3 the limit when n aims towards the infinity of the suite e e a a E respectively DS Wel S p C and n 1 L5 D Yi L3 4 Vi 8 The obtaining of L respectively L and L3 allows us to build the set D respectively D and D de fined by e For every value of d D respectively D and D3 it is now necessary to calculate the end of the corresponding period of interference Eo 1 d respectively Eo 2 d and Eo 3 d According to f and c Eo d is the limit when n aims towards the infinity of the suite E d E
399. the deadlines for hard deadline aperiodic tasks and provide good average response times for soft deadline aperiodic tasks even though the occurrences of the aperiodic requests are nondeterministic For a detailed analysis of aperiodic servers see 4 and 5 The aperiodic scheduling algorithm must also ac complish these goals without compromising the hard deadlines of the periodic tasks For the aperiodic scheduling authors presented Slack stealing 8 and aperiodic servers such as the sporadic server 6 and the deferrable server 7 allow aperiodic tasks to be 169 170 handled within a periodic task framework Our ap proach try by allowing periodic tasks to be handled with an aperiodic ones by an hybrid approach in the same framework To the author s knowledge no result is available in the state of the art for scheduling both periodic and aperiodic tasks except that we propose in our original work where an approach to deal with complex timing constraints and with minimizing the response time is proposed Int l Conf Embedded Systems and Applications ESA 12 picture Figure 1 4 2 Motivating Example Let us suppose a real time embedded system Sys1 to be initially implemented by 2 characterized tasks as shown in figure 1 These tasks are feasible because the processor utilization factor U 0 7 lt 1 These tasks should meet all required deadlines defined in user re quirements and we have Feasibility Currentgys1
400. the following model for VVI mode as shown in Figures 11 and 12 The pacemaker must wait until the Ventricle Response Period VRP has passed before generating a pulse Then a pulse is only generated if one is not sensed within a given rate interval RI Likewise the pacemaker s environment in this case the heart can be modeled as an automaton that randomly generates heartbeats in the range from MinDelay to MaxDelay as shown below in Figure 12 VentriclePace x 0 eat Q x lt MaxDelay x gt MinDelay VentricleSense x 0 Figure 12 Heart model for ventricle The model can be simulated in UPPAAL as shown below in Figure 13 In this case system declarations are given by P Pacemaker 500 1000 250 and H Heart 200 3000 The pacemaker lower rate interval LRI is 500 upper rate interval URI is 1000 and VRP is 250 all in milliseconds The heart MinDelay is 200 and MaxDelay is 3000 jue dt yew Toot Gptions plp B z El B A A AL E f Figure 13 Simulator output Model checking can be used to verify properties among a wide range of distributed and real time systems In the past we have used UPPAAL to Int l Conf Embedded Systems and Applications ESA 12 verify the correctness of distributed algorithms and real time schedulers 8 9 For this model of the VVI mode a variety of properties can be verified using formal verification All of the following properties are satisfied for the given mode
401. the need approach benefits and competition of their project The audience provides comments and feedback that the project teams may take into account Once the projects are approved by the instructor the students start the design and implementation work At the end of the course all project groups present and demonstrate their work to the class The project grade is made up of project presentation demo peer evaluation and project paper A list of the projects conducted over the last two years include the following 1 Wireless wrist watch as 3D mouse 2 Bio alarm clock with gesture recognition 3 Wireless mesh network for equipment monitoring 4 PIC32 platform for controlling iRobot 5 BrainTrainer v2 0 a game to increase brain s ability in short term memory 6 Human machine interface for home security system 7 Digital bumper sticker 8 Remote pet care and monitoring 9 Home automation 10 Hard drive clock 11 Computerized storage and access system 12 Space Hero Pilot 2011 space adventure game 13 Connect Four 14 Developing a playing agent for Connect 4 15 Micro light bikes multiplayer game with wireless interface between game consoles 16 Wireless patient monitoring with ZigBee 17 Wireless triangulation using WiFi access points 129 6 Peer Teaching To help improve students active engagement in the teaching and learning activities we introduced a peer teaching component in the course This pe
402. the position of the fault which is to be propagated to an intermediate key at 10 R is examined The examined position is classified into types A to F according to the fault transmission Figure 1 shows the procedure of the classification of the fault type between 9R and 10R 4 byte fault injection on 3rd row SubWord 9R TITE LLY RotWord 10R Sub Word E T C ko type AT i pe Cyne D pe E Propagation pattern of the fault from 9R to 1OR Fault on 9R Propagated fault from 9R to 1OR Result of exclusive OR Fig 1 The classification of the fault type between 9R and 1OR Step3 The property that the intermediate value m the correct value is equivalent to m the value with fault is used By applying an intermediate formula that correlates with the intermediate key at 9 R to the value of the cryptogram with the fault the key is specified 3 Evaluation Platform For Key Attacks The proposed evaluation platform is composed of a fault generation block and a key analysis block The fault generation block is for the purpose of generating a fault in the hardware while the analysis block is for analyzing whether keys can be derived from an output cryptogram 3 1 Fault Generation Block This study aims to make a change over on two out of phase clock signals at a specified timing With this a glitch can be inserted in a clock at an arbitrary round Using digital clock manager DCM emb
403. the results of computation but also on the times at which results are produced A real time task is generally placed into one of four categories based upon its arrival pattern and its deadline If meeting a given task s deadline is critical to the system s operation then the task s deadline is considered to be hard If it is desirable to meet a task s deadline but occasionally missing the deadline can be tolerated then the deadline is consid ered to be soft Tasks with regular arrival times are called periodic tasks A common use of periodic tasks is to process sensor data and update the current state of the real time system on a regular basis Periodic tasks typically used in control and signal processing applications have hard deadlines Tasks with irregu lar arrival times are aperiodic tasks Aperiodic tasks are used to handle the processing requirements of ran dom events such as operator requests An aperiodic task typically has a soft deadline Aperiodic tasks that have hard deadlines are called sporadic tasks We as sume that each task has a known worst case execution time In summary we have Hard and soft deadline pe riodic tasks A periodic task has a regular interarrival time equal to its period and a deadline that coincides with the end of its current period Periodic tasks usu ally have hard deadlines but in some applications the deadlines can be soft Soft deadline aperiodic tasks An aperiodic task is a strea
404. the shared processors between Tasks The processor is the resource responsible of the execution of tasks In our study we focus on the partitioned multiprocessor system In fact each task is assigned to one processor and the scheduling analysis of the system corresponds to analyzing each processor The processor is modeled with dPTPN by a place and its state is described by the present marking It is free if a mark exists and occupied otherwise The allocation of the processor depends on the used scheduling strategy In our study we are interested in the strategy based on the Earliest Deadline First EDF We consider two tasks 7 1 and T2 are in the same partition and share the processor P1 Alloc T1 Alloc T2 P1 Fig 6 presents the dPTPN model corresponding to the shared processor P1 between the instances TaskC and TaskC gt of TaskC The current state presents a mark in P Ready P2Ready and Procl to indicate that 7 1 and T2 call for the processor P1 So the event of allocation is modeled by a transition Int l Conf Embedded Systems and Applications ESA 12 P2Deadline P2Remaining T2Allocation P2Received Data P2Release P2getProc P2DataToSend Proc T2Releasing P1UnCreated P1Deadline P41Remaining Proc1 O O TaskC P1Received Data T2Allocation P1getProc P1Release P1DataToSend Proc T1Releasing Fig 6 Allocation processor using the EDF policy T1
405. the ultimate objective of the dPTPN 13 In fact to solve the conflict problem of enabled transitions 115 116 the priority changes at runtime according to the Nets state The dPTPN distinguishes between temporal and concurrent events that are sources of conflict Indeed two types of transitions T temporal transition Fig 2 and Tep compound transition Fig 3 are proposed Coef Firing Time Fig 2 T Transition 13 Fig 3 Tep Transition 13 With respect to temporal transition T Fig 2 is an ordinary PNs transition with a firing date presented with an integer value between braces This presentation of Time is dedicated to deterministic Real Time Systems 12 21 13 As for the second type of transitions Tep Fig 3 is a transition with a preprocessing that precedes the crossing to calculate its priority In fact when two Tep transitions are enabled and share at least a place in entry then the preprocessing is made to determine the transition which will be fired with a priority changing according to the state of the network described by the marking M We start with the presentation of the dPTPN formal defini tion then we explain the semantic of execution Next we have shown the internal behavior of real time task with the dPTPN 3 1 Formal Definition A Petri Net 23 can be defined as 4 tuplet PN P T B F 3 where 1 P p1 pa Pn is a finite set of places n gt 0 2 T ty t
406. this research is to keep the hardware to a volume that will fit within the CubeSat architecture CubeSats are currently designed to dimensions of 10 cm and 1 kg payload constraint with the maximum size being three modules 7 8 Therefore the largest volume allowed would be 10 cm x 10 cm x 30 cm and up to 1 33 kg The compelling reason for considering the CubeSat platform is that it is substantially less costly than current GPS satellites and has already been flight tested on many missions Currently a GPS satellite costs roughly on the order of magnitude of hundreds of millions to billions of dollars to develop and deploy 12 This is due to the cost of the atomic clock size and weight of the satellite CubeSats on the other hand are on the order of tens of thousands to a few million dollars 13 1 2 Lunar GPS System Segments There are three major segments to GPS space systems ground control and the user 1 First the space systems segment includes the satellites and their systems Secondly the ground control segment includes the ground stations that control track and maintain the satellites Finally the user segment is the actual GPS receiver and its systems Another perspective of the segments is that this is the high level design of the GPS system In this paper the space systems segment is the only one considered as the ground control segment and user segment capabilities already exist in many areas 2 Lunar Satellit
407. through the use of software As is often the case economic concerns are a determining factor in system design The costs associated with the process of automating a home currently are much more than the typical household is willing to spend While automating homes during their construction would alleviate much of the cost this does not provide a solution for existing homes A system must be designed that can be easily retrofitted to existing homes Historically standardization has been the key to successful and widespread implementation of new technologies 2 3 The proposed design focuses on making use of an existing wireless standard to develop a system that facilitates the automated metering and control of devices in existing households Through the use of this technology coupled with an easy to use graphical user interface the energy consumption of individual devices can be monitored and automatically controlled via customizable algorithms The most important constraint of the proposed home automation system is the desire to design a product that is price competitive In addition the product will need to be adaptable to varying home designs updating the entire electrical system of an existing home is simply not an option in most cases 2 Embedded System Overview The proposed system is the vision of an energy conservation solution that will provide a user friendly reliable and accessible product that can be adopted and imple
408. tigue Model 32nd Annual International Conference of the IEEE Engineering in Medicine and Biology Society Buenos Aires Argentina Aug 31 Sept 4 2010 13 P Kumar C Potluri A Sebastian S Chiu A Urfer D S Naidu and M P Schoen An Adaptive Multi Sensor Data Fusion with Hybrid Nonlinear ARX and Wiener Hammerstein Models for Skeletal Muscle Force Estimation The 14th World Scientific and Engineering Academy and Society WSEAS International Conference on Systems Corfu Island Greece July 22 24 2010 Int l Conf Embedded Systems and Applications ESA 12 147 14 P Kumar C Potluri A Sebastian S Chiu A Urfer D S Naidu and M P Schoen Adaptive Multi Sensor Based Nonlinear Identification of Skeletal Muscle Force WSEAS Transactions on Systems Issue 10 Volume 9 October 2010 pp 1051 1062 2010 15 P Kumar C Potluri M Anugolu A Sebastian J Creelman A Urfer S Chiu D S Naidu and M P Schoen A Hybrid Adaptive Data Fusion with Linear and Nonlinear Models for Skeletal Muscle Force Estimation 5th Cairo International Conference on Biomedical Engineering Cairo Egypt Dec 16 18 2010 16 P Kumar C Potluri A Sebastian Y Yihun A Ilyas M Anugolu R Sharma S Chiu J Creelman A Urfer D S Naidu and M P Schoen A Hybrid Adaptive Multi Sensor Data Fusion for Estimation of Skeletal Muscle Force for Prosthetic Hand Control The 2011 International Confere
409. timer is used to calculate maximum time elapsed actual execution time between the two sampling intervals CPU utilization is monitored through processor monitoring hardware external hardware contain high resolution oscilloscope both in presence and in absence of FT scheme respectively Estimated values are verified using Matlab Aggregate error for the each CPU utilization is calculated by using the equation below when the system is in steady state 21 E Xeni ef k D2 D1 10 The purpose of second experiment is to investigate the maximum schedulable limit and upper bound of g For this experiment ten SC tasks are considered eight tasks are involved in the telegram construction and two tasks are involved in the telegram mapping Apart from that there are 30 non SC tasks on the Master Processor and 20 non tasks on the Slave processor allocated 97 98 11 Results Table 1 shows the values CPU utilizations of dependability driven feedback based Control scheduling and without dependability integration for experiment 1 CPU utilization value with dependability driven FCSA is more slightly over utilized which suggests that enabling FT schemes re execution and replication SC tasks takes more time to execute than expected Ratio between estimated execution time and actual execution time g is calculate with the help of software timer for Master CPU utilization which turns to be g 1 16 1 40 which means that the actua
410. tion binary 0 or 1 During the falling edge of CLK all the primary outputs are driven to 0 as the precharge pMOS transistors pc1 to pc8 in Figure 1 turn ON During the rising edge of CLK the pMOS transistors are turned OFF When the look ahead input signal LS of the priority encoder is 1 the priority of the inputs is resolved according to the priority assignment to produce an appropriate high primary output 114 Int l Conf Embedded Systems and Applications ESA 12 Hierarchical Modeling with dynamic Priority Time Petri Nets for Multiprocessor Scheduling Analysis Walid Karamti Adel Mahfoudhi and Yessine Hadj Kacem ICES Laboratory ENIS Soukra km 3 5 University of Sfax B P w 1173 3000 Sfax TUNISIA Abstract Dynamic Priority Time Petri Nets dPTPN rep resent a powerful formalism for the scheduling analysis of Real Time Systems running on Multiprocessor architecture The originality of the dPTPN semantics compared to the existing research work is the dynamic calculation of the priority of transitions in conflict The present paper presents a new modeling strategy with dPTPN based on object modeling concept Thus a new component is proposed and the scheduling model is consti tuted with different instances of it The scheduling is assured through the Earliest Deadline First with a set of dependent tasks We prove the capacity of our approach to detect the non schedulable sequences via an experiment
411. tion III presents the state of the art In section IV we define a new theoretical approach In section V our proposed approach is im plemented simulated and analyzed Finally section VI presents a summary and conclusions of this paper 2 SYSTEM MODEL We present the following well known concepts in the theory of aperiodic real time scheduling 2 e An aperiodic task 7 Ci Di is an infinite col lection of jobs that have their request times constrained by a Worst Case Execution Time WCET C and a relative deadline D e Deadline The time when a task must be finished executing e Worst Case Execution Time WCET The longest possible execution time for a task on a particular type of system e Response time The time it takes a task to fin ish execution Measured from release time to execution completes including preemptions e Preemptive scheduling an executing task may be interrupted at any instant in time and have its execution resumed later e Release ready time The time a task is ready to run and just waits for the scheduler to activate it e A busy period is defined as a time interval a b such that there is no idle time in a b the pro cessor is fully busy and such that both a and b are idle times eUs T a is the processor utilization fac tor In the case of synchronous and asyn chronous independent and periodic tasks U a min DD lt 1 is a sufficient condition but not necess
412. tion Platform For Key Attacks 4 1 Experiment Outline In the experiments an AES cryptographic circuit AES_KL was designed so that the operation part in the key generation section uses the critical path In the AES_KL the SubBytes operation used the conflation method Verilog was used for the circuit description and it was embedded in the FPGA Table 1 Case where the fault diffuses in columns Fault position on OR of Key The number of Calculation amount generation section revealed byte for attack aa Obit N A HA L6bit 514 HEI 24bit 716 EES 40bit 18 Int l Conf Embedded Systems and Applications ESA 12 Table 2 Case where the fault diffuses in lines Fault position on OR of Key The number of Calculation amount generation section revealed byte for attack asi Obit N A EH Obit N A EH Obit N A EH Obit N A For the embedding the PlanAhead tool was employed Logic elements used for the cryptographic operation section were arranged near the section and those used for the operation of the key generation section were dispersedly arranged so that the key generation section uses the critical path Figure 3 shows the arrangement of the circuit elements of the AES_KL In the fault generation experiment a glitch below the critical path was generated to specify the glitch width when data errors occur The glitch width was either increased or decreased using the signal phase shift of the DCM parameters Because of signa
413. tion of the non schedulable sequence and request it as a feedback to the partitioning tool to obtain new partitions However as the increasing complexity of the RTS gives birth to a very complex dPTPN model in this paper we present a new modeling technique Based on the object modeling we present a new component TaskC Using different instances of it we obtain the new scheduling model Hence the scheduling policy considered in this paper is the Earliest Deadline First EDF 19 dealing with dependent tasks In future work we are interested in the properties verification such as liveliness and safety to particularly present the behavior of an RTS Furthermore we intend to integrate the dPTPN formalism into a HW SW partitioning approach based on a Model Driven Engineering MDE 25 In fact we aim at showing how the dPTPN can be able to prove an RTS and how it can be useful to reduce the space solutions of the partitioning activity References 1 T Amnell E Fersman L Mokrushin P Pettersson and Yi Wang Times a tool for modelling and implementation of embedded sys tems In TACAS 02 Proceedings of the Sth International Conference on Tools and Algorithms for the Construction and Analysis of Systems pages 460 464 London UK 2002 Springer Verlag V Antti Stubborn sets for reduced state space generation In Applications and Theory of Petri Nets pages 491 515 1989 B Berthomieu and M Diaz Modeling and verification
414. tionality even all hard drives are healthy The stored data on NAS hard disk drives is safe but there is no way to gain data access NAS controller card is like motherboard without any fault tolerance capability might be stop working like other electronics devices 3 5 Disaster and Crime Although rare relatively unlikely occurrence such as an earthquake hurricane flood tornado or fire can become the reason of data loss Electronics devices are a favorite of thieves of high tech equipment Theft causes to a permanent loss of data along with the hardware device Int l Conf Embedded Systems and Applications ESA 12 Increase in hacking incidents that lead to important and sensitive data lost 4 Challenges of NAS Data Recovery NAS devices used sophisticated and complex storage technology When the hard disk drive in NAS system fails all the data stored on the NAS data may get damaged or simply cause to not accessible The higher RAID complexity and number of working disk drive increase the complexity of data recovery process NAS recovery is someway different with other data recovery One is getting the data from every hard disk drive attached in NAS and second make certain of recovered data correctness are two of the most important issues for user Most Experts advise to look instant a Data Recovery Company before try to recover the data yourself Some situations make recovery impossible like swapping failure derive s in a degra
415. tive platform for developers 3 However those facilities are useless if they have not been developing a set of utilities Drivers and APIs that allow design applications since a high level of abstraction In this paper we describe the development of a prototype designed for remote health supervision oriented to capture and display electrocardiograms ECG signals This prototype is a part of the System Integration of Medical Monitoring and Interoperability for Telecare SIMMIT 4 One of the most important objectives of this prototype consists in to develop a real time application aimed to capturing bio signals to be displayed on a system running Android OS called host A dedicated embedded system is responsible for the signal acquisition Such a system consists of two parts An ASIC which performs the capturing of the signals from the human body and a MCU microcontroller unit which acts like a link between the ASIC and the host The results of the implemented system sampling processing and displaying of an ECG Electrocardiogram signal are also present This paper has the following structure Chapter 2 presents related work Chapter 3 describes the hardware architecture used in the implementation of the application Chapter 4 presents a detailed description of the target application and solution strategy regarding software concerns chapter 5 shows the results obtained and finally conclusions and future work in Chapter 6 2 Re
416. to empirically analyze different pacemaker designs The goal of this framework is to provide a convenient platform that can be used for research and teaching in real time embedded system design The framework can also be used for model driven development of pacemaker software and to demonstrate the safety and liveness property violations that may result during the design of real time pacemaker software Keywords Pacemaker empirical analysis real time embedded system design medical devices 1 Introduction A challenge called the Pacemaker Grand Challenge was issued by the Software Certification Consortium SCC Boston Scientific released the complete system requirements for a fully functional previous generation dual chamber pacemaker 1 The goal of releasing this specification was to provide a foundation for future formal methods design challenges therefore only the basic functions were required to be implemented in hardware i e sensing pacing and lead impedance measurement Thus we will refer to the resulting system as an academic pacemaker A group of students from the University of Minnesota accepted the challenge to develop a hardware prototype as their senior design project Based on their design the Software Quality Research Laboratory in the Dept of Computing and Software at McMaster University developed new hardware evaluation boards using the Microchip 18F4520 PIC processor to control the pacing logic This
417. to independent smaller sub applications the process of developing it will be much easier and reduce development time by utilizing the divide and conquer approach In this case sub applications are developed and tested individually and then they are combined to be the large application later This paper introduces a two step model to develop a large application on our RTOS with such an approach With our proposed model we found that a large application is rapidly built with minor modification of sub applications From our experience it is particularly useful for a large application that is independently divided such as menu driven GUI application on RTOS Keywords Application Modeling RTOS Embedded System UML Program Development 1 Introduction Today as embedded systems are more powerful real time operating system RTOS has supported much more functionalities such as networking GUI file system and so on The number of applications is growing and the complexity of application is proportionally increasing As a result writing embedded applications efficiently is a major concern in order to reduce development cost and time 1 Developing a large scale embedded application is difficult because development environment is usually poor compared with developing PC applications In embedded systems many developers are usually faced with cross compile environment and even in some cases without GUI based development tool Cross compi
418. to issue instructions to different equipment to complete some task and management computer interface is used for data exchange between task controller and external management computer Communication is realized between different equipment in the bus network by way of the sending of messages and its typical application is as follows task controller in real time receives information of navigation and location generated by GPS the ECU of the engine provides its current torque curve for transmission gearbox and so on The ECU of the tractor functions as a filter for message transport between the tractor bus and the equipment bus which can avoid the event that the communication task of one bus is so heavy that the other bus is overloaded Application layer module v STM32F107 ARM 32 bit Cortex TM M3 chip CAN bus transceiver RealSYS CANPro ial ISOBUS if Figure 4 Network structure of test GPS sensor Figure 4 show the network structure of test GPS sensor based on STM32F107 ARM Cortex M3 board The main board STM32F107 adopts the ARM 32 bit Cortex M3 SCM Single Chip Microcomputer produced by STMicroelectronics company of French Italy It is a totally integrated mixed signal system on chip which integrates in one chip almost all the analog peripherals digital peripherals and other functional components that are necessary to form a data sampling or control system of a SCM BOTSH CAN controller is compatible with CAN technical
419. toISO 117831s based on the Open system interconnect OSI model layers however the higher functional layers sometimes defined differently Figure 1 schematically illustrates the layer stricter ISO 11783 standard n P Tractor Virtual Task Con File Sequence i T a ECU 9 Terminal 6 troller 10 Server 13 Control 14 Diagnostic Services 12 DIAGNOSIS Physical Layer 2 PHYSICL DATA TRANSMISSION Figure 1 Diagram of the ISO 11783 standard parts own illustration The purpose of ISO 11783 is to provide an open interconnected system for on board electronic systems It is intended to enable electronic control units ECUs to communicate with each other providing a standardized system The tractor ECU shall have at least one node for connection to the implement bus 2 2 CAN networks ISO 11783 standardizes a multiplex wiring system as described above based on the Controller Area Network CAN protocol developed by Bosch Bosch 1991 6 This protocol uses a prioritized arbitration process to allow messages access to the bus When two messages are sent at the same time their identifiers are imposed bit serially onto the bus The bus must be designed to allow dominant bits to overwhelm recessive bits when both are applied simultaneously by different ECUs on the bus No conflict occurs as long as the ECUs are sending the same bits but when one sends a recessive bit while the other sends a dominant bit the bus state is domin
420. tory for Petascale Computing JLPC 2010 C Wilwert N Navet Y Q Song amp F Simonot Lion Design of Automotive X by Wire Systems Jn The Industrial Communication Technology Handbook CRC Press 2004 V Claesson S Poledna amp J Soderberg The XBW Model for Dependable Real Time Systems International Conference on Parallel and Distributed Systems ICPADS pages 130 138 1998 X by Wire Project Brite EuRam 111 Program X By Wire Safety Related Fault Tolerant Systems in Vehicles Final Report 1998 J P Hespanha P Naghshtabrizi and Y Xu Survey of recent results in networked control systems Proc of IEEE vol 95 no 1 pp 138 62 Jan 2007 P Naghshtabrizi Delay impulsive systems A framework for modeling networked control systems Ph D dissertation University of California at Santa Barbara Sep 2007 Renesas V850E2 Mx4 family for microcontrollers Platform and http am renesas com products mpumcu v850 V850e2mx v850e2mx4 1 ndex jsp Stephen J Chapman 2004 MATLAB Programming for Engineers Third edition 2004 Khan A A Yakzan A LE Ali M Radio Frequency Identification RFID Based Toll Collection System Third International Conference on Computational Intelligence Communication Systems and Networks CICSyN pp 103 107 26 28 July 2011 A Jhumka M Hiller amp N Suri Assessing Inter Modular Error Propagation in Distributed Software IEEE Symposium on Reliable Distributed
421. ts if the resulting U t gt 1 we set U t to be 1 We varied the average processor utilization from the light workload 10 tasks to heavy workload 100 tasks generated randomly We observe that our ap proach by the solutions of the OEDF algorithm gives us the minimum bound for response time and utiliza tion factor This observation was proven by the re sults given by OEDF algorithm which are lower bet ter than these of the solutions given by the predic tive system shutdown approach the MIN algorithm the OPASTS algorithm and the HPASTS algorithm Also we observe that when we have no knowledge of the arrival of sporadic tasks our proposed algorithm is optimal and gives better results than others for a big number of arrival sporadic tasks and in overload conditions but in a small number of tasks or light workload OEDF algorithm is optimal but not strictly since it gives results close to that of the solutions of MIN OPASTS and HPASTS algorithms but it is ef ficient and effective 5 CONCLUSION AND FU TURE WORKS This paper deals with reconfigurable systems to be im plemented by an hybrid system composed of a mixture of periodic and sporadic tasks that should meet real time constraints In this paper we propose an optimal scheduling algorithm based on the EDF principles and on the dynamic reconfiguration for the minimization of the response time of sporadic and periodic constrained deadline real time tasks on uniproce
422. ty of a method according to the internal state of the object and indicates the possible sequences of methods execution by the object The interest of Petri nets is to describe the intrinsically competing objects capable of executing several methods at the same time Furthermore certain transitions of the net can remain hidden or protected inside an object and therefore model the internal and spontaneous behavior of an object by contrast to the services it offers to its environment The fundamental concern of such approach is to allow the use of concepts stemming from the objects approach clas sification encapsulation to describe the system structure instead of using a purely hierarchical structuring In the Petri Nets in objects paradigm a system is described as a set of objects which communicate the behavior of each object being described in terms of Petri Nets Mostly these approaches are class based which allows the association of a PNs with a class of objects rather than with an individual object Based on this approach we now present the definition of the new object Task and we specify the communication between the different instances of this object in order to model and analyze the schedulability of the system Q 4 1 Task Component The PNs in objects depends on the encapsulation of the various behaviors of the object in a centenary called PNs component We propose a dPTPN constituent called TaskC to encapsulate the b
423. uired deadlines defined in user requirements and we have Feasibility Currenty olvo t True We suppose that a reconfiguration scenario is ap plied at tl time units to add 3 new tasks C G H The new processor utilization becomes U 1 454 gt 1 time units Therefore the system is unfeasible Feasibility Currenty ovo t False se 20 20 20 aa 2 5 10 40 4 12 12 16 8 10 8 8 56 E E a0 9 c Jo p Je 2 x i e 20 s m0 e e 86 m 20 s eo 8 oa 18 6 Table 1 Volvo Case Study In table 1 U 8 represents the task utilization when scheduled in a static schedule with a period of 100ms and Uasy represents the utilization when tasks are scheduled with their minimal value between their pe riod and deadline in the case of asynchronous tasks The optimal results given by our approach are pre sented in Uopt column Formalization By considering asynchronous real time tasks the schedulability analysis should be done in the Hyper Period hp 0 2 LCM maz Az 1 where LCM is the well known Least Common Multiple and A z 1 is the earliest start time arrival time of each task Tp 11 Let n n ne be the number of a mixed work load with periodic asynchronous tasks in C urrentr t The reconfiguration of the system C urrentp t means the modification of its implementation that will be as follows at t time units Currentp t Enew U Sola Where va is a subset of n
424. uk Jung and Yong Ho Song Department of Electronics Computer Engineering Hanyang University Seoul Korea Abstract In NAND flash memory devices pages marked invalid can remain in blocks and occupy flash space Therefore it is necessary to physically eliminate invalid pages and collect valid pages from the victim blocks in order to sustain flash write performance and storage lifespan Alt hough there have been many research studies on efficient garbage collection techniques research has focused on victim selection methodologies and no solutions have been proposed for the victim selection process cost overhead Indeed the host system quite often suffers unendurable storage access delays because garbage collection produces much computa tional over head when doing victim selection A novel gar bage col lection mechanism called Two Level List based Garbage Collection is proposed in this paper The victim block selection overhead can be efficiently reduced in this scheme hence the responsiveness to host requests is signifi cantly improved Keywords flash memory garbage collection SSD 1 Introduction There has been a revolutionary change in data storage fields since the development of NAND flash memories NAND flash memories have been widely used as the storage media of embedded systems such as MP3 players mobile devices and digital cameras owing to their non volatile high random access performance and low power consu
425. ure issues To overcome the lack of feature problems we propose another approach We segment upward camera images and extract ceiling area using relation rules between camera and ceiling It is simple and less complexity enough to be adopted embedded system The Figure 1 is our mobile robot system embedded the localization module Figure 1 Mobile robot system with the localization modules 2 Localization module The proposed localization module consists of three parts a main board a vision board an I O board as shown in Figure 2 The main board has an ARM11 CPU NAND Flash 64MB and SDRAM 128MB The Operation system is Linux 2 6 22 and the compiler is gcc 4 2 1 The vision board is composed of 1 3 inch 1 3 mega pixel CCD and 1 3 inch exchangeable lens which can adjust field of view The I O board provides TCP IP and JTAG communication and is used for debugging Table 1 shows specification of boards Figure 2 Localization module Int l Conf Embedded Systems and Applications ESA 12 107 Table 1 Board Specifications Specifications CPU MCIMX31 531MHz ARM11 36JF S Core Main 7 Memory NAND Flash 64MB Board mDDR SDRAM 128MB User available memory 50MB Communication Serial Debug 1 Control 2 USB Ween l Sensor MT9M111 1 3 Inch 1 3MP Board 7 Lens 60 90 1 3 Inch exchangeable lens Cable 20 Pin FPC 0 5mm pitch Power DC 5V I O Communication Ethernet TCP IP JTEC Board M
426. uted immediately after its arrival and must be finished by its deadline First at t time unit Sys is feasible because the processor utilization factor U 0 30 lt 1 We suppose after that a reconfiguration scenario is applied at t1 time units to add 3 new sporadic tasks oc op and og The new processor utilization becomes U 1 21 gt 1 time units Therefore the system is unfeasible Table 1 The characteristics of the 5 tasks used to illustrate the motivation for dynamic reconfiguration approach P is the inter arrival time Our optimal earliest deadline first OEDF algorithm is based on the following Guarantee Algorithm which is presented by Buttazo and Stankovic in 2 Indeed OEDF algorithm is an extended and ameliorate ver sion of Guarantee Algorithm that usually guarantee the system s feasibility 2 2 Guarantee Algorithm The dynamic on line guarantee test in terms of resid ual time which is a convenient parameter to deal with both normal and overload conditions is presented here Algorithm GUARANTEE E ca begin t get current time Ro 0 do t Insert ca in the ordered task linked list E EU oa k position of ga in the task set for each task o such that i gt k do Ri Ry 1 di di 1 Ci if Ri lt 0 then return Not Guaranteed return Guaranteed end 3 NEW APPROACH WITH DEADLINE TOLERANCE In this section we will present some prelim
427. valid pages into one free block and invalidates the victim blocks in the on demand victim selection techniques For example the Int l Conf Embedded Systems and Applications ESA 12 FTL updates the page map table with a new physical page number and erases victim blocks whose physical block num bers are 2 4 and 5 when page copy operations are finished as shown in Figure 3 a The FTL needs to copy four pages and erase three blocks as well as to search victim blocks and update map tables during this multiple block garbage collec tion process As seen in this example the on demand victim selection techniques can make relatively more reusable free blocks but may cause a large peak delays within only one garbage collection E Valid Page Invalid Page ___ Free Page PBN 2 Page Map Table Page Map Table PBN 4 PBN 4 Fy EARRA B55 E PBN 5 PBN 1 Victim Blocks Victim Block PBN 2 4 5 PBN 5 a b Fig 3 a An existing garbage collection and b 2LGC mechanism On the other hand the 2LGC scheme can separate a garbage collection sequence into several single block garbage collection operations so it is possible to improve responsiveness and make the flash storage preemptive Note that the 2LGC can implement single block garbage collection mainly because the FTL can use a page offset for each block stored in the curPage offset entries as shown in Figure 2 b All the blocks can be reallocated as non free s
428. vanced Computation and Communication ACC team of the NASA CSULA SPACE Center is focused on design and development of new tools for information dissemination for collaborative education and research The SPACE Center consists of faculty led graduate and undergraduate students which are formed into specific teams based on particular areas of research The current project objective is to design and implement an FPGA based image processor as an embedded system that is able to run certain SIS applications with minimal client computer processing It will initially serve as a modular device via rapid prototyping which provides acceleration to a client machine by offloading specific functions of SIS applications Example such as real time compression is done by utilizing a JPEG encoder to eventually leverage towards motion JPEG for video streams Acknowledgement to NASA University Research Center Program Grant NNXO08BA44A 2 Semantic Information System Network and UVC Overview The SIS Network is intended to target communities with similar interests whether that collective is in industry education facilities or for recreational purposes Combined with Ubiquitous Video Conferencing the SIS framework is designed with flexible GUI Graphical User Interface controls for a wide range of uses to accommodate a broader range of audiences In order to transport video information between UVC participants a video codec is required The UVC
429. velopment process of the real time applications from their design to checking This allows designers to accurately validate systems and check the required properties of their behavior The choice of the adequate formal method from the existing varieties depends on the characteristics of the considered system and the properties to check The technique of model checking is of an irrefutable advantage allowing early and economical detection of errors at an early stage of the design process This explains the growing popularity it enjoys in the industrial world Particularly Petri Nets PNs presents an appropriate model checking thanks to their great expressivity dynamic vision and executable aspect Besides they have been successfully used in RTS specification Thus it is interesting to use the PNs for the scheduling analysis of an RTS running on a Multiprocessor architecture The Multiprocessor scheduling analysis with PNs is a recent research area which explains the scarcity of Petri Nets dealing with it The dynamic priority presents a primor dial factor in the Multiprocessor scheduling 11 but we distinguish a limitation of PNs extensions that support it is distinguished It can be explained by the difficulty to introduce such characteristic in PNs In what follows we present the PNs extensions with fixed priority and next we detail the existing extension with dynamic priority The STPN 24 is a temporal PNs extension dedicated to
430. we applauded for wonderful humanized design of those static products we may ignore that part of dynamic process Currently vending machine is working under the control of a procedure oriented brain we select item and input the money or the other way around then we get the item and change This is not a perfect process What if I don t know which is the right way Or what if I want to buy several items after I input enough money This less humanized service will drive customers to go towards the salesperson Then what is humanized service Humanized service is to meet both the function needs and psychology needs of the customers with convenient service and easy operation according to human s consumption preference So if we want vending machine to serve us with humanized service firstly we will have to inject it a humanized brain which will direct itself to act with a pattern that a salesperson act with enabling them to accept information customers supply and interact with customers and assist customers fulfill their shopping process In this paper a framework for designing such a humanized vending machine based on uC OS II was illustrated in detail including storage of information the functionality of key tasks the synchronization and mutex among key tasks communication among key tasks A vending machine model with basic functionalities based on_ this framework has been implemented based on platform with LPC2470 78
431. wing rapidly As a result countries and institutions around the world are becoming more aware of the need to conserve energy and are actively seeking new methods of decreasing per capita consumption 1 Energy conservation in households begins with the homeowner s understanding of the methods that must be implemented and the sacrifices that must be made Some general examples are turning off unused lights purchasing more energy efficient appliances and unplugging unused devices to prevent idle energy consumption However these methods are often viewed as inconvenient and as having little impact As a result the many small contributions required for energy conservation are often not implemented Presently there are few affordable technologies available to aid consumers in achieving a balance between energy conservation and convenience The key to a solution is the ability to develop and provide the necessary products and methods while also establishing a balance between the many economic social and environmental concerns Environmental concerns lie at the very core of the home automation system discussed in this paper Optimizing energy conservation is directly correlated to decreasing the use of natural resources and reducing the overall impact on the environment By combining the automated control of devices with a system capable of monitoring consumption decreasing energy consumption at the device level can be easily addressed
432. wirelessly and transparently to the resident to an IBM Thinkpad T41 with WindowsXP Professional Java Runtime Environment Standard Edition 1 5 0 09 MySQL Server 5 0 WebServer Apache Tomcat version 5 5 20 in the nurse s station The monitoring interface installed at the nurse s station provided a history of alert adherences and oximeter readings Albeit the PAS was quite well received by the residents they suggested several technical directions for future research This includes suggestions for incorporating robustness in the impasse with a wide range of failure scenarios and enforces reliability in diverse operating conditions In addition they suggested having a secure communication interface with third party service providers respecting the privacy of its users and providing Quality of Service QoS even in the presence of wireless interference and other environmental effects Doukas and Maglogiannis presented the implementation details of a patient status awareness system that has human activity interpretation capability and emergency detection of patient collapses 4 This system utilized video audio and motion data captured from the patient s body using appropriate body sensors and the surrounding environment using overhead cameras and microphone arrays The limitation of this system is that all the equipment needs to be installed within the monitored area and sensors have to be Int l Conf Embedded Systems and Applicat
433. xpected ES GD 6 32 em Sistema de Integraci n de Monitoreo M dico e Interoperabilidad para Teleasistencia Create by Eng Jaiber Yepes Figure 9 Artificial ECG signal The main test was conducted by connecting the System to a patient as shown in Figure 10 7 08 pm Sistema de Integraci n de Monitoreo M dico e Interoperabilidad para Teleasistencia Figure 10 Real ECG signal Int l Conf Embedded Systems and Applications ESA 12 7 Conclusions A real time embedded system was designed for capturing processing storing and displaying an ECG signal For this purpose a platform based on Android OS a conventional 8 bit microcontroller and data acquisition system were used Proposed strategy provides a wide running flexibility mainly because the application acquires independency from the specific Android device that executes it It s important to remark the fact that it s not required to make any modification on the Android s standard architecture for adding real time features In other hand adding new hardware to the system has any significant increase in system complexity because extra hardware is quite simple low cost and totally transparent to the application DM3730 processor with Android OS provide an excellent solution for applications requiring joint user interface connectivity and complex applications 8 Acknowledgments We would thank to microelectronics and control group researchers

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