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Wei_Xiaoyun_55 - Auburn University

1. 22 33 DUT T DUT Tm 1I e S e555 646A oorr 3 10 ese S2 DUT aDUT s l es e5 5 e4654A aur 5 n 3 11 56 Fig 3 15 Normalized 6 term error model for reverse mode Fig 3 14 and Fig 3 15 give the complete 12 term model With 12 forward and reverse measurements 3 8 3 11 give 12 equations The 12 unknowns can be determined by solving the 12 equations simultaneously Once the 12 error terms are determined the S parameters of the unknown two port can be calculated as 80 83 Se fos E P S a 5 RE 22 22 rs gor C1001 43 39 19 3 53 91 3 12 D se Jis 8 en SDUr i0832 43 39 3 13 21 D Coe te fis 4 53 91 jo o BT D 3 14 ora fist g ze 52 C3 m T rs sour _ 53 35 jo 9 19 3 53 91 3 15 D e 5 e D oct x fe Su es 3 i Jes 3 16 jo 9 53 3 C1932 53 91 57 Note that all four measured S parameters are used to calculate any one S parameter in S and each of the equations in 3 12 3 15 contains error terms calculated under forward and reverse mode Thus both the forward 6 term and the reverse 6 term affect the results of S since essentially the forward error terms and the reverse error terms y describe the same VNA system 3 4 4 SOLT calibration The classical 12 term model has been widely
2. 045 Pool ss dededesdse E besieteieen 4 le rJ dq 2 i ne 4 amp Q 1 See a Se Lo aa i ee Sich ae E 78 n N EVA Y o l T mi I wn V v 0 05 A APA Ag frequency GHz Fig H 4 The three error terms solved using OPEN SHORT and LOAD standards The relationship between I and L in H 2 is a nonlinear function in terms of the error terms e een and e Due to the difficulty in solving nonlinear equations a linear equation in terms of the error terms is developed next as a generalized interpretation which can be easily extended to two port system H 3 A generalized interpretation The linear equation is derived from the transmission parameters T parameters of the two port error adapter In matrix the T parameters of the error adapter is written as tot AHL ela oue 204 Similarly denoting I b a and I a b T and F are related through tL pH ph t ps 0 H 5 This is a linear equation in terms of the elements in 7 Since T parameters represent the S parameters of the same error adapter H 5 can be rewritten in a similar format as H 2 f pou p t por b pM H 6 t 4 ty t Comparing H 2 and H 6 the elements in T can be related to the elements in E as t t t 1001 oo 11 gt E115 g H 7 t t t Note that all of the unknown terms are normalized to t and the equation is
3. 0 2 0 4 0 6 0 8 1 Ves V Fig 7 13 Measured and simulated IIP3 versus V at multiple frequencies for N 10 W 20um 130 N 64 W 2um L 90nm Af 100KHz 15 T T T E 5 f0 2GHz i f0 5GHz RE E TEE frequency increase f0 10GHz g 5 m eo 2 0 a Symbol Measurement ee MELLE r Line Simulation i gs l 0 2 0 4 0 6 0 8 1 Ves V Fig 7 14 Measured and simulated IIP3 versus V at multiple frequencies for N 64 W 128um 7 4 Summary This chapter evaluates the BSIM4 model of the NMOS transistor for linear and nonlinear performance using a set of DC S parameter and power spectrum measurements especially in the moderate inversion region The results demonstrate good fittings on both DC and AC characteristics Despite its interpolating nature of moderate inversion modeling the BSIM4 model can accurately describe I V and Y parameters in moderate inversion region The subcircuit based BSIM4 model can predict the distortion behavior of a CMOS transistor correctly which enables distortion optimization of RFIC circuits using mathematical models and simulators The linearity sweet spot is investigated to be deviated significantly from the widely accepted zero K3g point for a practically large device size found in LNAs 131 CHAPTER 8 MODELING OF INTERMODULATION LINEARITY An important consideration in RFIC design is linearity which sets the u
4. H M short 11 o IS 0 05 frequency GHz Fig 3 3 The magnitude of the measured S of an ideal a LOAD and b SHORT 3 2 Error adaptor concept In general all of the linear errors of the imperfect reflectometers including directivity errors frequency response errors and port match errors can be lumped into an error adaptor This fictitious error adaptor is a four port network containing 16 error terms since four port network is presented as a 4x4 matrix mathematically Fig 3 4 shows the two port system with a four port error adaptor inserted between the perfect reflectometer and the unknown DUT Port 0 and Port 3 are the two perfect measurement ports inside the VNA while Port 1 and Port 2 are the two terminals of the unknown two port a is the incident wave to the four port error adaptor while b is the reflected wave to the error adaptor Without specification the directions of the waves in error models and calibration techniques are all defined in the same manner The subscript is 49 the port number where the wave is monitored A 0 1 2 3 Note that the two bias tees are three port components The return losses and insertion losses of the bias tee are included in the four port error adapter but the leakage errors to the DC power supply are not However the leakages to the DC power supply do not affect the main signal path and it is safe to ignore these leakages without any
5. Sy IIP3 8 3 m 8 3 S The derivation is detailed in Appendix J Fig 8 1 The small signal equivalent circuit used for IP3 analysis When K3 0 first order IP3 gives the maximum IIP3 which is the well known IP3 sweet spot used to improve linearity in circuit designs Fig 8 2 plots g K3 and the first order IP3 calculated using 8 3 A sharp IIP3 peak is observed near the threshold voltage during the transition from subthreshold to strong inversion when K3zg becomes zero However the sweet spot IIP3 is not necessarily the highest The calculated IIP3 can be higher in strong inversion since g saturates and K3 is very 134 small as V increases Experimental results also show that IIP3 varies strongly with Vj at sweet spot position and high V as detailed in Section 9 2 N 264 W 2um L 90nm Va 0 8V f0 5GHz f f DS 20 10 a icd o 0 aoe 0 10 0 2 0 4 0 6 0 8 1 Ves V Fig 8 2 First order IP3 with a sweet spot at Ks 0 8 2 Complete IP3 expression An IP3 expression including all of the nonlinear coefficients of order 3 and below is derived using Volterra series The nonlinear current source method together with the small signal equivalent circuit in Fig 8 1 is used to calculate the Volterra kernels 24 Although C is not included in Fig 8 1 Volterra series analysis with C can also be done The expression with C is too com
6. 1 75854E0 5 03784 3 19091E0 3 386471 6 30932E0 4 04101E0 1 53857E1 3 04736E1 END BEGIN 3 03686 6 72070 4 4291 E0 7 43920 0 3 75439 E0 5 9064 EO F E EO E E EO EO 9E E0 3 51220 9 8 03173 E1 0 71484 2 052341 5 20507E0 1 4399 4E En F I Lm F in 2 87963 3 16540 3 81811 END BEGIN 1 07403E0 6 15478 E0 3 32666 E0 2 25952E E0 4 58984E a 3 EO ji 1 En kF In m F I 3 27758E 1 1 4631 1 61621E 1 1 29162 7 56713E 1 1 140 9 71008E 1 7 046501 4 18945E 1 9 37377 E 1 3 74939 5 19653E 1 1 14196 0 25878E 1 5 13000 3 78418 EO 01 E 1 EO F E E 1 E E E 1 E E E 1 E E E 1 E E 3 73977E 1 2 49313 END BEGIN 1 68396 2 12471E 1 0 45509 0 3302E 1 2 361981 E 1 0 82214 E 1 F E m kF a p F a E 1 E E 2 22015E 1 0 30609 1 02417E 1 1 53465l 0 18722E 1 1 90048 1 18751E 1 1 549071 0 9021E 1 1 97334 0 75592E 1 1 50070 0 871421 END E 1 3 28628 E 1 E E E 2 E E E 1 E E E 1 E E E 1 E E E 1 E E E 1 E E 187 APPENDIX E CALIBRATION KIT SETUP This is a step by step tutorial for calibration kit setup on Agilent VNA 8510C ISSN means the block s name of a group of the keys which is printed on the front panel of the equipment CAL means hard
7. 9 10 11 12 BIBLIOGRAPHY W Liu X Jin X Xi et al BSIM3V3 3 MOSFET Model User s Manual University of California Berkeley http www device eecs berkeley edu bsim3 get html M V Dunga W Yang X Xi et al BSIM4 6 1 MOSFET Model User s Manual University of California Berkeley http www device eecs berkeley edu bsim3 bsim4 get html R van Langevelde A J Scholten and D B M Klaassen MOS model 11 Level 1102 Philips Electronics N V 2003 2004 http www nxp com acrobat download other models nltn2004 00085 pdf X Li W Wu G Gildenblat et al PSP 102 3 NXP Semiconductors http www nxp com acrobat download other models psp102p3 summary pdf R van Langevelde A J Scholten and D B M Klaassen MOS Model 11 in Compact Model Council Meeting 2000 C Galup Montoro and M C Schneider MOSFET modeling for circuit analysis and design Singapore World Scientific Publishing Company 2007 M Golio and J Couie Who Pays for Characterization The Final Dilemma for MESFET Modeling in Dig 48th ARFTG Conference Fall pp 87 93 1996 F Sischka Applying Nonlinear RF Device Modeling To Verify S Parameter Linearity in European Microwave Week 2001 J Civello Adressing the challenges of RF device modeling for successful high frequency design Microwave Engineering Europe pp 21 28 2004 R van Langevelde L F Tiemeijer R J Havens e
8. can be related through a nonlinear equation in terms of E as S EXE s PoE li E 3 22 or sour z SRNE E 3 23 It can also be written as E EE E JS S EE JS EE S E 0 24 It is difficult to solve E from the nonlinear relationship in 3 22 and 3 23 However using transmission parameters T parameters S and S can be related through a linear relation in terms of error matrix 35 In that case error terms can be solved using linear algebra algorithms 36 3 18 can be rewritten using T parameters b T T aq es bel H 63 as where d dek det det gy L 6 t dg bo f bo he Recall that b S a and a SPb 3 25 can be rewritten as 36 LS SU S DES e This is equivalent to 35 su Pur n yr gn ey 6 Or s n s r s T 1 Comparing 3 27 and 3 24 the elements in E and 7 can be related through T E E EE E T 1 4 T E E E T and Dir E T LT T Ds E T T 3 26 3 27 3 28 3 29 3 30 Since the matrices in 3 27 are 2x2 matrices each two port measurement will give four linear equations in terms of T Four calibration standard measurements seem to give enough linear equations to solve the 16 elements in T but in fact this is not true Only 14 parameters can be solved by making four measurements for two reasons 41 First of all the set of equations is homogeneous and the maximum number of nonzero unkn
9. max Extracted parameters for three NMOS transistors with different gate patterns and multiplier factors usos seme eost s ii Nee UNES Ode I que qud 39 Layout for three NMOS transistors with same total channel width but different finger width and finger number Wiota 4OUM sss 40 Extracted parameters for three NMOS transistors with same total channel width but different finger width and finger number Woeota 40um ueste ueexsessezeectsse cuvesese i elds ola ce E wa aa e ne e Hec ssecvas nee e ce e TUE re x 41 Block diagram for two port S parameter measurement using Agilent SS LOC Sy Stent desee ure Se tun ciae ca ao ate uE 45 A two port VNA system with four receivers ssssssseeeeee 46 The magnitude of the measured S of an ideal a LOAD and b SHORT is adi aei aon Mo rm Rol set Mdb E oe phates Reino 49 The four port system error adaptor for two port S parameter MICAS UE CIE o oce eaten dite Ceteri asl e tud nad ahead eost cass 50 Signal flow graph of 8 term error model for a two port system 51 The modified 10 term error model with two leakage errors added 51 A two port S parameter measurement system configured for forward modena e a alent ian uitis ti a aa aun tdeo ode 52 Forward mode signal flow graph for two port system including non ideal Zo termingtlofis aaa qiti t ar ed ERR RIS eR RARIOR RAUS 53 Simplified forward mode signal flow graph 53 A two port S paramete
10. 20 Ln Shift casued by A1 A2 A3 A4 First order IP3 K3 m Im M K3 9 1 3 m K3 Ou AT A2 A3 A4 _ 10 Shift casued by 1 H 4 Simulation E L m e b Q ERU 10 a 0 2 0 3754 0 7 Ves V Fig 8 5 IIP3 versus V from simulation first order IP3 expression in 8 3 and complete IP3 expression in 8 5 with different nonlinearities included V 0 8V 8 4 Device width scaling The linear and nonlinear coefficients in 8 5 all scale by a factor of K as device size scales by K The scaling factors of the Z terms are complicated For very small devices Z is approximately R and Y is approximately 1 R Therefore the scaling factors for Ai As and A4 are K K K and K respectively In the extreme case if Z and Y are dominated by g C and C Ai A A3 and A do not scale as device gs size scales For the device sizes and frequencies examined in this work the C and C terms are relatively small and the scaling factors for Aj A As and A are close to K K Kk and K This indicates that the impact of Aj A As and A4 on IP3 sweet spot is 142 much stronger for large devices As N increases a decrease of IP3 sweet spot Vos is expected Fig 8 6 shows the calculated IIP3 using 8 5 versus J for devices with multiple finger numbers Drain current density J is defined as W First order IIP3 is shown for comparison As J V is nearly identical f
11. b a and b are close to unity with zero imaginary part and all of the other 86 elements are close to zero in both real and imaginary part This indicates that A and B are both identity matrices and open short is valid within this frequency range As frequency goes above 50 GHz the deviation of A and B from identity matrix becomes noticeable and open short loses its accuracy 3 a amp saa E 0 a t l 65 4e 3 o tete x e ef me amp Cao 22 0 08 a S a 2 amp S b k Ria amp R b l l t 0 04 42 2 1 f Ohne sehe d ME LL I UR lw S l Kd l Uv l o5 Qon 105 z s 2 0 Eu _ lt 0 05 _ Li amp Uv ly R a amp Rba Ian amp Sba i 0 04 l 0 1 0 50 100 0 50 100 frequency GHz frequency GHz Fig 4 6 The elements of A and B versus frequency 4 2 7 Reciprocity and symmetry of the four port parasitics It was observed in board measurement that non idealities in the OPEN and SHORT standards can lead to non reciprocal parameters for passive structures 46 Ideal OPEN and SHORT however are necessary in all de embedding methods to achieve analytical solution It is therefore necessary to check if the solved four port parasitics is still reciprocal or not and significant deviation from reciprocity would indicate significant 87 e
12. con ree en e eie ea opes aed 191 Nonsingular combinations of five two port calibration standards for 16 term error model Assuming one standard is a zero length THRU 199 xix CHAPTER 1 INTRODUCTION The growth of wire line and wireless communication demands RF integrated circuits RFIC on CMOS technologies because of the low cost and the eligibility for high volume integration As well known the RF section is the biggest challenge in CMOS transceiver designs due to the lack of accurate RF CMOS models This demands reliable RF measurements which are mainly done on wafer with the advent of coplanar probes The measured data must reflect the intrinsic transistor without the effects of the surrounding environment The notable available models for a bulk MOSFET Metal Oxide Silicon Field Effect Transistor are BSIM3V3 1 BSIMA 2 MODEL 11 3 PSP 4 BSIM3V3 BSIMA are charge based models while MODEL 11 and PSP are surface potential based models 5 6 Usually a set of DC CV and S parameter measurements are carefully designed to evaluate the performance of a technology and extract the unknown model parameters 7 8 For example from DC measurement one can have an idea of the mathematical relationship between the voltages and currents at each terminal and the operating limits of the transistor e g threshold voltage breakdown voltage The accuracy of DC measurement is determined by the DC probes and the equipments
13. 1 0V a representative moderate inversion bias Fig 7 8 shows all Y parameters at 5 GHz versus V for V 1 0V Both simulation and measurement data are shown in Fig 7 3 Fig 7 8 The Y parameters here include pad parasitics by design as IP3 is measured on wafer including probing pads Overall the BSIM4 based subcircuit model does a good job in modeling 5 V 15 V5 S parameters fr and both frequency and bias dependence of most Y parameters over the whole V region including the moderate inversion region 121 N 64 W 2um L 90nm 90 Symbol Measurement Line Simulation np gov log scale linear scale los mA V s increase 30 4399 n D a Vos 0 6 0 8 1 0V i 54 eis i 0 0 2 0 4 0 6 0 8 Vas V Fig 7 3 Measured and simulated V for V 0 6 0 8 and 1 0V N 64 W 2um L 90nm 60 T T T T T Symbol Measurement Line Simulation Ibs mA Fig 7 4 Measured and simulated V for V 0 4V and 0 8V 122 L T l f o l c l 56 SEa U36 4 EE as l ot Ew l Ho H m if l l l l l RCNH E ERN PME l gt Q II PNEU REUS A EM a gt gt E x c e S h 4 o i 8 m gt E i 5 N I nop TO OT a l z f e l z l LL zi Nu EN e e e N T 30 35 40 25 frequency GHz 10 0 4 0 5 0 6 0 7 0
14. 77 78 79 80 81 82 N R Franzen and R A Speciale A New Procedure for System Calibration and Error Removal in Automated S Parameter Measurements in Proc of 5th European Microwave Conf pp 69 73 1975 H V Shurmer Calibration procedure for computer corrected s parameter characterisation of devices mounted in microstrip Electronics Letters vol 9 no 14 pp 323 324 1973 D F Williams R B Marks and A Davidson Comparison of On Wafer Calibrations in Dig 38th ARFTG Conference Winter pp 68 81 1991 R B Marks J A Jargon and J R Juroshek Calibration Comparison Method for Vector Network Analyzers in Dig 48th ARFTG Conference Fall pp 38 45 1996 R B Marks Formulations of the basic vector network analyzer error model including switch terms in ARFTG Conference Digest Fall 50th pp 115 126 1997 S Vandenberghe D Schreurs G Carchon et al Identifying error box parameters from the twelve term vector network analyzer error model in Dig 60th ARFTG Microwave Measurements Conf pp 157 165 2002 K H Wong Characterization of Calibration Standards by Physical Measurements in ARFTG Conference Digest Spring 39th pp 53 62 1992 Cascade Microtech Impedance standard substrates to support all of your high frequency probing applications Data Sheet 2005 H J Eul and B Schiek A generalized theory and new calibration procedures for network analyzer
15. Essential to obtaining a good RF model is the accuracy of on wafer scattering parameter S parameter measurements S parameter measurement gives an 1 idea of the RF performance of the transistor e g cut off frequency power gain The accuracy of measured S parameters directly affects high frequency model parameters e g gate source capacitance The accuracy of the model determines the time to market of any RFIC designs 1 The system setup and the techniques to remove errors in S parameter measurement will be detailed later in Section 1 1 However S parameter describes the RF performance of transistors in linear mode only because VNA is operated in linear mode and the measured S parameters only include small signal information of the transistor at the excitation frequency 9 The real world transistor characteristics are nonlinear that the transistor will generate harmonics and intermodulation products in addition to the stimulus signal 9 8 The higher order harmonics and intermodulation products become apparent when the input power is significant The 1dB compression point and the two tone third order intermodulation IM3 distortion are the most widely used figure of merit to evaluate the linearity of transistors For a nonlinear system the IM3 products are the remixed products when the input signal contains two adjacent channels Fig 1 1 illustrates the impact of the IM3 product on the desired signals The spacing between the tw
16. Note that the direction of the a and b waves at the probes are defined differently for the four port error adapter and the four port on wafer parasitics to keep the rules that all a waves are incident waves entering the four port and all of the b waves are the reflected waves leaving the four port For simplicity the following S parameters are defined 68 1 S is the measured S parameter of the unknown two port without switch error 2 5 is the measured S parameter of the unknown two port after ISS calibration The on wafer parasitics probing pads and interconnects is still involved in S 3 S is the actual S parameter of the unknown two port without system errors and on wafer parasitics which means the S parameter after two step calibration or single step calibration S and S can be easily defined using waves with directions shown in Fig 3 19 as Deed e b a a b S When applied for systematic error calibration ai apur b E li uin since b b are the incident waves to DUT and a a are the reflected waves to DUT It is a little complicated to defining When applied for on wafer parasitics de embedding b _ eDur areleh 036 because now b b leave DUT and a a enter DUT When applied for single step calibration it does not matter because SP do not show up in the calibration procedures 69 3 7 Summary Error adaptor concept for two port S parameter measureme
17. Second TS apple assess rti Die ah ga pA iota do Tad oid aes 114 Comparison of the single step four port calibrated results with and without switching error correction The SVD based numerical four port solution in Section 5 2 is applied ier e tt eta tectae 115 The magnitude of the solved 16 error terms of the combined four port MOUW OU eM DET 116 Block diagram for two tone intermodulation linearity measurement 119 Schematic for two tone intermodulation linearity simulation in Cadence Ce cR m AME Mur PEE DE 120 Measured and simulated V for Vps 0 6 0 8 and 1 0V 122 Measured and simulated V for V 0 4V and 0O 8V ssuus 122 a S21 in dB versus frequency at V 0 4V and V 1 0V b S in dB versus V at 5GHz and T 4 I 0V iecore ere Ott eid us 123 fr extracted from measured and simulated S parameters 123 Y parameters versus frequency at V 0 4V and V 1 0V R and 3 stand for real and imaginary parts sssssssssseseeeeenees 124 Y parameters at 5GHz versus V Vps 1 0V R and 3 stand for real dnd imaginary Darts 5 osscpa e o ee ep Da did ise ne bebo asd ue 125 The amplitude of the fundamental output signal versus input power level at Ve OAV VY pc HU B VL Seti uiii eet bete ree ped e IE 126 The amplitude of the fundamental output signal and the third order intermodulation product versus Jpg i et hiat dor dedo den
18. by gate source and drain source voltages which can be approximately calculated as the sum of a series containing powers of the control voltages The i expression limited to first second and third order nonlinear behavior is m EnV PY ROCK RE Re DA Co oc SE Ie P ROCCO RR X OUR ERE OCC d first order linear K2 enV as K2 V TA Dee Ku A e een second order J 1 TK32 V K3e vi F K322 p8 Va Vas K3s 2g Va Va third order 210 Fig J 1 The small signal equivalent circuit used for IP3 analysis Applying Kircoff s current law at node 1 and 2 in Fig J 1 yield d 0 1 y 3 n R J 2 S 1 V Em R g sC L The voltages above are Laplace transforms Denoting Y s g sC 1 R and Y s U R5 5C zs J 2 can be rewritten as l s 0 Ix ra 13 gr P S The 2x2 matrix in the left hand side is the admittance matrix of the circuit V V and V are Laplace transforms J 1 First order kernels The first order kernels are calculated from the response of the linearized circuit to external input V Fig J 2 gives the linearized equivalent circuit The voltage source is converted to a current source which is the only excitation of the circuit when 211 calculating the first order kernels V and V reduce to the first order transfer functions of the voltages at node 1 and 2 when V is set to one The transfer functions at node 1 and 2 are denoted as Hi s and Hi s The first subscri
19. data and device small signal parameters are extracted from DC and S parameter simulations using the BSIM4 model validated in Chapter 7 The IP3 expression can accurately predict the biasing and device size dependence of IP3 sweet spot The frequency dependence of IP3 is determined by the small signal capacitance Thus the frequency dependence is very weak and negligible for small device For large device not only gate source capacitance and drain bulk capacitance but also gate drain capacitance are important To determine the value of IP3 accurately more complete equivalent circuit of MOS transistor must be used in Volterra series analysis 149 9 1 Power gain measurement Of particular interest to linearity measurement is the power gain Since 50Q source and load are used in IP3 measurement at low input power the power gain obtained from sweeping input power linearity measurement should agree with the small signal power gain S from S parameter measurement which involves much more systematic error correction Therefore the power gain at low P from linearity measurement using spectrum analyzer with S from S parameter measurement using VNA are compared in Fig 9 1 as a means of assuring power calibration accuracy for linearity measurement The power gains extracted from intermodulation measurement are close to S from S parameter measurement within 0 5dB for most measurements in this dissertation N 64 W 2um L 90n
20. if a 2 0 matched Z termination then the calculated S and S are the measured S and 7 of the two port If a 0 not matched Z termination the S parameters of the two port are defined using ahe sle Similarly under reverse mode if a 2 0 the calculated S and S are the measured SH and S of the two port If a 0 the S parameters of the two port are defined bj 5 Salla Combining the forward and reverse mode configurations using b by _ Su S UA ay D 3 b b 3 Sali a Therefore the S parameter of the two port S is calculated as 7 73 1 Si Si b by Ap d l D 4 S5 5 b b ja a which can be rewritten as b a bya bya b a I E b a b a bja b a A A A dd 4 4 D 5 Substituting S b a S3 b a S b a and S b a into D 5 S with switch error removed is calculated from the raw S parameters exported from VNA as 183 S S55 4l 3p S45 s D AE 4 p9 1 2 i S SST Soo S S 1 b forward 0 reverse D D T and T are user functions defined above for forward and reverse mode which can only be measured using four receiver VNA D21 S S I L S is the measured S parameters of the DUT after removing switch errors while S S S and S are the raw S parameters directly saved from the VNA without switch error removal D 2 Step by step guide to measure the switch errors 1 Setup VNA Define the frequency list
21. m cet aa n eo rey S N uA e 28 mM Ed mone e20 ole Por gmet 60 TPO 1 l 0 50 100 frequency GHz frequency GHz Fig 6 7 The magnitude of the solved 16 error terms of the combined four port network 116 6 4 Summary The accuracy of single step calibration using two general four port solutions is experimentally investigated on a 0 13um RF CMOS process In contrast to popular belief single step four port calibration produces reasonably accurate and acceptable transistor Y parameters from 2GHz to 110GHz despite the less accurate on wafer standards compared to precision ISS standards which facilitates production testing and process monitoring The distributive nature of on wafer parasitics is also naturally included due to the four port description of the combined error adaptor The single step approach to transistor measurements is thus valuable as it does not require ISS calibration and thus facilitates production testing The impact of switch errors on single step measurement is also investigated After removing switch error single step calibration provides practically the same results as two step calibration for both the analytical four port solution which was first developed for on wafer parasitics and the numerical four port solution based on SVD 117 CHAPTER 7 VALIDITY OF BSIM4 MODEL FOR NONLINEAR RF MODELING Once the model parameters are extracted from a set of DC CV and S parameter measurements it is important
22. mS f GHz Fig 2 12 Extracted parameters for three NMOS transistors with same total channel width but different finger width and finger number Wiota 40um 2 4 Summary The layout rules concerning reliable on wafer probing are detailed It is recommended to use all metal layers for ground pad and more than one top layer for signal pads Ground shield need to be carefully designed The transistor characteristic fluctuation caused by layout variation is examined Double sided gate contact does not necessarily provide lower gate resistance The gate pattern needs to be optimized Otherwise the metal lines connecting out can have considerable impact on gate resistance On the other hand the selection of reference plane is of great important for transistor characterization 41 CHAPTER 3 ERROR MODELS FOR TWO PORT S PARAMETER MEASUREMENT Of paramount importance in on wafer transistor characterization at RF frequencies is to properly correct the errors introduced by the VNA system and on wafer parasitics 66 13 21 12 The demand for increased measurement accuracy in on wafer S parameter measurement can be achieved by improving the hardware the models used for characterizing measurement errors the calibration methods used for calculating these errors and the definitions of calibration standards 34 The type of the error model depends on the hardware topology of the VNA There are three receiv
23. s2 00 o o o Sh 0 Si5n S082 Sz O SaS SaS 00 0 O 10 9 S2 0 0 S SEST SAST 0 sus un T s4s27 o0 o 0 01 887 es AUCI I o 14 ts Lhe mn S and S2 are the elements of S and S m n 1 2 t is the elements of T k 1 16 Written in matrix the above four linear equations are C 7 0 aa Cage TS the coefficient matrix for each two port measurement For two two port standards 2x4 equations will be obtained and the coefficient matrix will be C For n two port standards nx4 equations will be obtained and the coefficient matrix will be C In nx4 x16 principle four two port standards are sufficient to solve the 16 unknowns However in practice five on wafer standards are required and only 15 unknowns can be fully determined 5 2 SVD based four port Solution Given the four linear equations in 5 3 four on wafer measurements give 16 linear equations which can be rewritten in matrix as C 7 0 oa It seems like that the 16 unknowns can all be fully determined using the 16 equations However the only possible 16 term solution is an all zero solution because the set of equations is homogenous In linear algebra the rank of the coefficient matrix determines the number 94 of the unknowns can be solved If C is full rank the only possible solution is fn 0 64 Since it is impossible that the error terms are all zero the rank of the coefficient matrix is les
24. 0 3 1 becomes b S a and b a Therefore the measured S parameters S are the wave ratios calculated 46 eM M S5 S Sy If Z is not a perfect matched load or the switch is nonideal i e a 0 in forward mode and a 0 in reverse mode The waves measured under forward mode and reverse mode can be combined as b by 7 Si Si a 4 3 3 b b S5 Salla a The superscript differs the waves measured in reverse mode from the waves measured in forward mode S can be calculated from the wave ratios as 39 S S S T S S SL eg 18 r E 3 4 1 J S5 SSI 5 Sy SV b forward 0 reverse D D Dz1 S S I D I and EL are the two additional wave ratios measured under forward and reverse mode while probing a THRU standard which can only be measured by four receiver VNAs The process to remove the switch errors caused by the non ideal switch and imperfect Z load is called switch error removal which can only be performed on four receiver VNAs Fortunately most of the modern VNAs are four receiver VNA The derivation of the equations and a step by step guide to measure T and T are detailed in Appendix D Denote 7 as the S parameters of the unknown two port The directions of the waves in Fig 3 2 are defined in a manner that simplifies the error adapter description in Section 3 2 Thus the directions of a b a and b give 47 Q QDUT b ARRA
25. 10 W 20um Analytical IIP3 without C is calculated using E Rel qe eee nt errr 156 The output power amplitude for fundamental and 3 order intermodulation products versus input power seen 157 Contour of 3 order intermodulation output power with sweeping gate bias and input POWET ien sesini bI QU bU ease 158 Equivalent circuit of on wafer parasitics for open short de embedding 173 Equivalent circuits and layouts of a OPEN and b SHORT standards e cata edema 173 Equivalent circuit for pad open short de embedding 175 Equivalent circuits and layouts of PAD OPEN and SHORT standards for pad opene sHort auessoec render IR ROME Re EEEE e bQ GE DEM Xr TEE 175 Equivalent circuit for improved three step de embedding 177 Equivalent circuits and layouts of OPEN SHORTI SHORT2 and THRU standards for improved three step sees 177 Equivalent circuit for transmission line de embedding 180 Equivalent circuits and layouts of THRUI and THRU2 for transmission line de embedding The length of transmission line is not uci 181 A two port S parameter measurement system with four receivers 182 Block diagram of the 4 port network for on wafer parasitics using I V Inv rise cien oi MR 193 Condition number minimum and ma
26. 127 Measured and simulated IIP3 versus V at multiple V 128 XV Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig 7 12 7 13 7 14 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 1 9 2 9 3 9 4 Measured and simulated IIP3 versus J for devices with N 10 20 BING GA REEE E T 129 Measured and simulated IIP3 versus V at multiple frequencies for N IO W520 Hasse cipio eien erena puso EAEE E 130 Measured and simulated IIP3 versus V at multiple frequencies for B SOT W128 EI socis chest aite terque n ae a eR nuce niii esos 131 The small signal equivalent circuit used for IP3 analysis 134 First order IP3 with a sweet spot at K3e O ceeeceeeeceeeecsseeeeeeeeeees 135 The nonlinear coefficients versus Fosse iiiter aper SIR EHE IER 137 a The denominator in 8 5 versus V b Each term in the denominator of 8 5 versus V Vis 0 8V lisse 141 IIP3 versus V from simulation first order IP3 expression in 8 3 and complete IP3 expression in 8 5 with different nonlinearities included lr f E 142 IIP3 calculated using 8 5 and 8 3 versus Jj for devices with multiple finger numbers s eooss si poc ie bU nibU tme bona I Dt EIE PIS BDa M Nonaa Dd 143 a Ips b K3g versus V at multiple V for simulation with and without V shift due to AV DIBL us
27. 212 J 3 Third order kernels 5 5 oer vote edhe eee eee 214 J 4 Input EP ss oen i oerte dad t eere tue ev Seto cho E E AE 215 xi Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig 1 1 1 2 1 3 1 4 1 5 1 6 ie 1 8 1 9 2 1 2D 23 2 4 2494 2 6 2 7 2 8 LIST OF FIGURES The power spectrum at the drain of a single transistor under a two tone excitation measured by a 50Q spectrum analyzer sss 3 A typical two port system for on wafer S parameter measurement 4 On wafer parasitics and reference planes for system error calibration and on wafer parasitics de embedding sssssssss 5 The lumped equivalent circuits for a open short b pad open short and c three step de embedding ssssssseeeneee 7 The equivalent input resistance and capacitance extracted from open short pad open short and improved three step de embedded results 9 An on wafer intermodulation linearity measurement system 11 The fundamental and IM3 output products versus input power for a two tone excited system is cise aii a e dede t n ete Un CX dE Rx 12 IIP3 versus V from first order IP3 theory linearity simulation and two tone measurement eeseeeeeeeeete eene hhehete eese etin esses sesenta eese 14 a The four port network for
28. 6 b 33 c SHORT THRU f and the on wafer standards OPEN e RIGHT Fig 2 6 Layout for the desired transistor d LEFT NMOS LEFT RIGHT and THRU gt SHORT The OPEN structure in Fig 2 6 b just takes the transistor out together with the in Fig 2 6 c shorts the metal at the Port 1 and Port 2 reference plane to ground using substrate ring and the necessary lowest layer metal connections The SHORT structure short and wide metal lines Multiple metal layers can be used if necessary LEFT RIGHT structure in Fig 5 structure in Fig 2 6 d has two 100Q metal resistors connected to Port 1 in parallel to provide balanced signal flow at the GSG probe In like manner 2 6 e has the same two 100Q resistors connected to Port 2 in parallel One end of the 34 resistors is connected to the reference metal as close as possible to Port 1 or Port 2 The other end is terminates to ground However it is hard to connect this end to the same ground plane as the SHORT structure because of the size limitation of this back end of line BEOL resistor So there is a reference plane variation between OPEN SHORT and LEFT RIGHT Assuming the ground plane is very well connected throughout the whole structure this variation is negligible The THRU structure in Fig 2 6 f simply shorts Port 1 reference to Port 2 reference in the shorted way Since the metal line used to short Port 1 an
29. By comparing the calibrated VNA results with the reference S parameters the performance of VNAs can be verified With on wafer standards the S parameters of these standards are determined by the technology which can very a lot from process to process It is hard to provide reference standards and 19 verification kits Fortunately the measurement comparison programs MCP provide another way to assure measurement accuracy MCP compares the results of the same device that travel between the participating laboratories to avoid serious errors or provide verification on areas without reference standards The MCP program illuminate us that the single step calibrated results can be verified using two step results for several on wafer reference standards Although ISS calibration is still necessary for verification purpose it still greatly reduces the measurement time since these reference results just need to be measured once for one wafer It does not need to be repeated for every test structure Secondly it is hard to accurately model the on wafer standards The standards on ISS substrate are modeled using non ideal capacitance inductance and delay time based on physical analysis and verified using reference values The accuracy of the on wafer standards affects the accuracy of the error corrected S parameters The experimental results in Chapter 6 indicate that assuming ideal on wafer standards leads to reasonably accurate results in the advan
30. ISS to solve the error terms between the probe tips and the perfect ports inside VNA a step called system error calibration After system error calibration the 4 test system ends at the probe tips which is then defined as the reference plane for systematic error removal Reference plane is a factitious separation which defines where the test system ends and the device under test DUT begins 13 Fig 1 3 illustrates the reference planes defined for on wafer S parameter measurement The reference plane at the probe tips is the reference plan defined for system error calibration reference plane ZZ ae gt i 7777 Pot A thle J j p Wa SS lt Probe Tip gt Device Terminal reference plane Fig 1 3 On wafer parasitics and reference planes for system error calibration and on wafer parasitics de embedding Besides the systematic errors on wafer parasitics including the probing pads and the interconnections need to be removed secondly a process called on wafer de embedding As shown in Fig 1 3 the probing pads and interconnections often have much larger dimensions when compared with the intrinsic transistor due to the size limitations of RF probes Thus a second reference plane is defined at the very end of the interconnections from probing pads to device terminals which is the device terminal reference plane in Fig 1 3 The standards used to solve error terms are fabricated on the same wa
31. J T Colvin S S Bhatia and K K O A bond pad structure for reducing effects of substrate resistance on LNA performance in a silicon bipolar technology in Proc of IEEE Bipolar BiCMOS Circuits and Technology Meeting pp 109 112 1998 J d Cressler and G Niu Silicon germanium heterojunction bipolar transistors Boston MA USA Artech House INC 2002 K Ickjin J Minkyu L Kwyro et al A simple and analytical parameter extraction method of a microwave MOSFET JEEE Trans Microwave Theory and Techniques vol 50 no 6 pp 1503 1509 2002 J Tabuchi B Hughes and J Perdomo On Wafer Millimeter Wave Nework Analysis for Device and Circuit Design in Dig 38th ARFTG Conference Winter pp 53 61 1991 S Rehnmark On the Calibration Process of Automatic Network Analyzer Systems JEEE Trans Microwave Theory and Techniques vol 22 no 4 pp 457 458 1974 D K Rytting Network Analyzer Error Models and Calibration Methods RF amp Microwave Measurements for Wireless Applications ARFTG NIST Short Course Notes 1996 R A Hackborn An automatic network analyzer system Microwave Journal vol 11 pp 45 52 1968 W Kruppa and K F Sodomsky An Explicit Solution for the Scattering Parameters of a Linear Two Port Measured with an Imperfect Test Set Correspondence IEEE Trans Microwave Theory and Techniques vol 19 no 1 pp 122 123 1971 165 71 72 73 74 75 76
32. Since the real world measurement system is not perfect there are random errors and systematic errors contributing to the measurement of the unknown two port S M load i e S z S For example Fig 3 3 a shows the magnitude of the measured S of an ideal resistive termination with S7 0 Se has 0 01 peak to peak M sh Sie for an variations with respect to frequency Fig 3 3 b shows the measured ideal short with S7 1 Ist sorl has an obvious frequency dependence and the values are far away from one These ideal devices are fabricated on Alumina substrate modeled based on physical parameters and verified by National Institute of Standards and Technology NIST 77 78 12 So the variations are not in the ideal load or short Instead these errors are introduced by the measurement system The random errors e g thermal drift can only be described statistically which cannot be systematically corrected The systematic errors are reproducible and can be corrected using computational techniques However full correction is impossible due to superimposed random fluctuations in the measured results 12 The linear systematic errors introduced by the imperfect reflectometer can be modeled by a fictitious two port error adapter between the reflectometer and the unknown one port This results in a perfect reflectometer with no loss no mismatch and no frequency response errors 48 0 015
33. Y and the right half as Y Y and Y are calculated as M thrul _ M thrul ves 2 M thrul 11 12 12 js AZ y z C 30 sthru y S M thrul Ipon i 2y 4Z OUT IN 0 1 y pPY P P j C 31 Ze and y are extracted from Ans ag cosh Aj 5 C32 7 8 C 32 Thus the ABCD parameters of the input and output networks are then given by AN A Al s and 4907 49U7 4575 The ABCD parameters of the desired device is obtained as acc amp am C 33 LlI 4 a 4 Fig C 7 Equivalent circuit for transmission line de embedding 180 a THRU1 b THRU2 Fig C 8 Equivalent circuits and layouts of THRU1 and THRU2 for transmission line de embedding The length of transmission line is not to scale 181 APPENDIX D SWITCH ERROR REMOVAL D 1 Switch error removal equations Fig 3 2 shows a two port measurement system with four receivers The characteristics of the switch can be removed by making no assumption of Z For each two port measurement S b a and S b a are calculated in forward mode while S 2 5 a and S b a are calculated in reverse mode The subscript is the 66 p port number where the wave is monitored while the superscript means reverse mode AX Poti b Dual 0 Reflectometer Sweep Oscillator Switch N Wd Pot2 5 a b Fig D 1 A two port S parameter measurement system with four receivers 182 Under forward mode
34. a SIO lo e g a a a zu Jali NIN N N 4 nt on aie hs N z N A NIS a a c NE a aA E J YIN alg si eg NN NIN N vhs als ores lada tbe v gt zo gt r a a Qo Gal SIS P PEG PE PEDES a g ves oa alee ee te ee ep Des Se Em Q4pmouwim UPR PR TS T 2 A EE Se tee Bla ee os a lg laff ats v4 mx s E gt N e lt H Hy HH Ay Yn Yoh Az 212 ZZ A48 AD BC Ay 171 APPENDIX C REVIEW OF ON WAFER DE EMBEDDING METHODS C Open Short de embedding Fig C 1 shows the equivalent circuit for open short de embedding Fig C 2 shows the equivalent circuits and layouts of the OPEN and SHORT standards Denoting Y Y Y js n 3 Pee thy C 1 y P F and Z Z Z Zo g 6 6 C 2 Zi Z tZ the measured Y parameters of OPEN and SHORT are Y Y and y y Z That leads to Z Y yov Using the properties of shunt and series connected two port networks the measured Y parameter of any DUT Y in Fig C 1 is i l Y Y zs L l C 3 Thus the actual Y parameters Y can be obtained as y r ye ye aay eee l C 4 172 Open short de embedding is valid as long as the parallel parasitics is mainly located at the probing pads It is still an industry standard de embedding method and can provide valuable device parameters below 30GHz Fig C 1 Equivalent circuit of on wafer parasitics for open short de embedding a OPEN
35. a contour plot for sweeping gate bias and input power The deep valley marked using square symbols are the IM3 sweet spots 90 Below 10dBm input power the sweet spots appear at around gate bias 0 33V which is the IP3 sweet spot As the input power increases the IM3 sweet spot shifts to lower gate bias voltage obviously 0 T T T T T 1 ON fet os 10 N 64 W 2um L 100nm Vps 0 8V ATTN 0dB f0 5GHz Af 100KHz 10 20 or imas 24 32 15 50 20 eee P dBm L I I 1 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Ves V Fig 9 9 Contour of 3 order intermodulation output power with sweeping gate bias and input power 9 3 Summary In this chapter the measured IIP3 is compared with calculated IIP3 using I V and S parameters from BSIMA based simulation The complete IP3 expression can correctly model the biasing frequency and device size dependence of IIP3 even with simulated I V and S parameters as long as the model is valid in DC I V and S parameters In the 158 90nm CMOS technology used the sweet spot J decreases from 40 to 20 wA um as gate width increases from 2 to 128um The V dependence and its device width dependence are also investigated using experimental results These results provide useful guidelines to linearity characterization simulation as well as optimal biasing and sizing for high linearity in RFIC design 159 1 2 3 4 5 6 7 8
36. coefficient matrix The condition number is defined as the ratio of the largest singular value over the smallest singular value of the matrix For T B If the four standards there are 16 equations written in matrix as 4 7 4 B 16x15 coefficient matrix 4 has zero singular values 4 is not full rank and the number 6x15 of unknowns can be solved equals to the number of non zero singular values If A is full rank but has extremely small singular values which leads to an extremely large condition number the set of equation is ill conditioned singular and the validity of the solution is questionable Assuming THRU is taken as one of the four standards and the other three standards are chosen from the pairs consisting O S or M i e O O S S M M O S S O O M M O S M M S there are 84 different combinations Fig G 1 compares the condition number the minimum singular value and the maximum singular value for four sets of standards The coefficient matrix A are all 16x15 singular since the condition numbers are extremely large for all cases For five standards the coefficient matrix is A and there are 126 possible combinations if THRU is chosen 46 combinations was shown to be singular in the reference The nonsingular combinations are listed in Table G 1 Fig G 2 compares condition number minimum and maximum singular values for five sets of standards The results indicate that these combination
37. daughter of Xinli Wei and Xinye Wang spouse of Tong Zhang was born on December 15 1978 in Xinxiang Henan Province P R China She received her BS degree from Huazhong University of Science and Technology in 2000 majoring in Communication Engineering She received her MS degree from Huazhong University of Science and Technology in 2003 majoring in Circuit and Signal In Fall 2004 She was accepted into the Electrical and Computer Engineering Department of Auburn University Auburn Alabama where she has pursued her Ph D degree DISSERTATION ABSTRACT ON WAFER S PARAMETER MEASUREMENT USING FOUR PORT TECHNIQUE AND INTERMODULATION LINEARITY OF RF CMOS Xiaoyun Wei Doctor of Philosophy December 19 2008 M S Huazhong University of Science and Technology 2003 B S Huazhong University of Science and Technology 2000 236 Typed Pages Directed by Guofu Niu Accurate on wafer characterization of CMOS transistors at extremely high frequencies e g above 60GHz becomes critical for RFIC designs and CMOS technology development for millimeter wave applications Traditional two step error calibration lumps the linear systematic errors as a four port error adaptor between the perfect VNA receivers and the probe tips and the distributive on wafer parasitics as equivalent circuits with shunt and series elements However the distributive nature of on wafer parasitics becomes significant and the lumped equivalent circuits fail at frequencies abo
38. have four options to solve 4 yh Iyo ya Lya OS thru S thru bs thru 21 oH ae and py The de embedded transistor Y parameters are practically the same for all four choices in our experiment Below is obtained from a as a M M acm 4 29 1 N IN 7L OS thru TON IN Ju This general four port solution here is much simpler than that of 19 4 2 4 Summary of general four port de embedding To summarize for two step four port parasitics de embedding the main procedures are 1 Perform VNA system error calibration using Impedance Standard Substrate ISS 2 Measure S parameters of on wafer standards and the desired transistor or any two port DUT The S parameters are transformed to Y and Z parameters using equations in Appendix B 88 3 Perform open short de embedding on measured LEFT RIGHT THRU and the DUT to obtain YSP Yr oer and yes 4 Extract G G C and C from Y and Y2 at low frequencies e g below 30 GHz 5 Calculate M and N using 4 15 and 4 16 6 Solve 4 from open short de embedded THRU Y using 4 29 7 Find out the elements of A and B from M N and 4 using 4 25 83 1 l M 8 Calculate Y for the examined transistor using Y 4 you 8 4 2 5 Impact of non ideal load in LEFT and RIGHT In 20 and 19 on wafer load resistor was assumed to be purely resistive However open short de embedded Y parameters of LEFT and RIGHT sh
39. in Section 3 4 However both the 8 10 term model and the 12 term model make an arbitrary assumption that the leakage terms bypassing the unknown two port are negligible Further measurement experiments and practical experiences reveal that the leakage terms can have a very complicated nature A much more general concept of error model was introduced by Speciale and Franzen in 1977 37 35 The systematic errors of a n port VNA are represented by a 2n port virtual error adapter with its n port connected to the n port unknown network and its other n port connected to the ideal error free VNA The error adapter consists of 2nx2n coefficients and describes all possible paths between the 2n receivers For two port measurement the error adapter is a four port network which involves 4x4 error coefficients i e a 16 term model The 16 term model is only solvable for four receiver 2n receiver VNA However it is also possible to define a full error model for three receiver n 1 receiver VNA This includes significantly more error coefficients for example the 22 term model for a three receiver two port VNA compared with the 16 term model for four receiver two port VNA 42 The four port error adapter can not only be applied on systematic error removal but also be used to remove on wafer parasitics as it does not make any 43 assumptions of the error network The four port error network is described in Section 3 5 There are also techniques
40. loss in accuracy 68 79 B n NEN Perfect Reflectometer L Reverse m da Port 3 switch Fig 3 4 The four port system error adaptor for two port S parameter measurement 3 3 The simplest 8 term error model The 8 term model simply doubles the 4 term model for a one port system at the two ports 70 80 The signal flow graph for the whole error adapter and the DUT is illustrated in Fig 3 5 The two error adapters at the two ports are named as X adapter and Y adapter The error terms are represented using S parameters Two additional leakage terms are added to the 8 trem model which turn it to a 10 term model as shown in Fig 3 6 67 The first explicit solution for 8 term model was introduced in 1971 by Kruppa and Sodomsky Three reflection standards open short matched load and one through standard with the two ports connected together are used to calculate the error terms in S parameters 70 The error terms can be either solved using S parameters or T parameters and modified approaches for different test structures are developed in 67 50 68 69 71 72 79 81 82 The solution is not shown here as it is not used during transistor characterization in this dissertation Fig 3 6 The modified 10 term error model with two leakage errors added 3 4 The classical 12 term error model The classical 12 term model handles the switch error problem by using two separate error
41. lumped circuits fail at higher frequencies Our results strongly suggest that for higher frequency transistor measurements four port is necessary and superior to pad open short despite the need for on wafer load resistors 89 Open Short Pad Open Short 0 2 Reciprocal 4 port solution EM i BENED gt 0 1 0 T 01 were A i LIPPE gt 9 05 4 0 0 50 100 frequency GHz Fig 4 7 Reciprocal four port de embedded transistor Y parameters versus the results using open short and pad open short de embedding 4 4 Summary A new general four port solution for on wafer transistor measurements is developed and its utility is demonstrated on a 0 13um RF CMOS process The impact of non ideal on wafer load resistor is examined and can be accounted for by including the parallel parasitic capacitances Through proper normalization easy to use new criteria are developed for quantifying the difference between open short and four port as well as for examining reciprocity and symmetry of the four port parasitics Despite the assumption of ideal OPEN and SHORT as was done in all de embedding methods for achieving analytical solution the solved four port network for on wafer parasitics is 90 shown to be reciprocal Comparison with pad open short shows that for transistor measurements pad open short does not p
42. match errors e and e The transmission from measurement ports to DUT terminals introduces four frequency response error terms e gt e and e The coupling between the four ports adds eight leakage error terms marked with dash lines in Fig 3 18 When the couplings are negligible it will be reduced to the 8 term model in Section 3 3 61 Fig 3 18 Signal flow graph of the 16 term model for a two port system The 16 error terms are actually the S parameters of the four port network which can be defined using the incident and reflected waves at each port as by Eoo amp o3 o1 o b a 5 30 5 31 32 4 3 17 b eo 13 en b ez en ta For simplicity the above expression is rewritten using 2x2 matrices as b E E a pehla nj e E E E and E are 2x2 matrices defined as e es e e o f _ o amp 3 an i z EI EE EE 3 19 239 3 4 M DUT DUT b The vectors b a and a are 2x wave vectors defined at the perfect VNA side Port 0 and Port 3 and the DUT side Port 1 and Port 2 62 pu HM pP a H aP h 3 20 b b a a Based on the directions of the waves in Fig 3 18 the S parameters measured by the VNA S and the S parameters of the unknown DUT are defined as Dee b a a b ie b 2 S aq and a SP 5P Thus S and S
43. models for forward and reverse mode This error model can be applied for both four receiver VNA and three receiver VNA The switch errors no longer need 5 to be removed using 3 4 This error model is still widely used in error correction techniques e g short open load thru SOLT calibration 3 4 1 Forward mode Under forward mode the incident wave a the reflected wave 5 and the 0 transmitted wave b can be measured by both three receiver VNA and four receiver VNA Fig 3 7 shows the block diagram of a two port VNA configured for forward measurement Fig 3 8 illustrates the possible signal paths using a signal flow graph for forward mode operation based on 8 10 term model e represents the leakage path between the incident signal receiver a and the transmission receiver b T lumps the impact of non ideal switch or non ideal Z termination Using signal flow graph analysis the a node can be removed and the signal flow graph in Fig 3 9 is equivalent to the signal flow graph in Fig 3 8 with 1 e a en e e EE I 2 3 6 l el i l el Directional Couplers Fig 3 7 A two port S parameter measurement system configured for forward mode 52 Fig 3 8 Forward mode signal flow graph for two port system including non ideal Zo termination Fig 3 9 Simplified forward mode signal flow graph 3 4 2 Reverse mode Fig 3 10 shows the block diagram for reverse
44. of harmonics and intermodulation products are higher order functions of the amplitude of the input signal and the amplitude of the fundamental signal is a linear function of the input power level the amplitudes of the harmonics and intermodulation products increase in a much faster way than the fundamental signal amplitudes as input power increases Fig 7 9 compares the amplitudes of the measured and simulated output signals at the fundamental frequency The transistor is biased in moderate inversion 125 region with V 0 4V V 0 8V At low input power the higher order products are much less than the fundamental signal so the power gain from measurement and simulation are both approximately constant As Pin increases power gain starts to drop because of the amplitude of the harmonics and intermodulation products added to the desired signal are negative The gain drop in the simulated result is clearly observed in Fig 7 9 Because of the limitation of the maximum power level that can be generated by the signal generators the Pin in measurement is not high enough to show this gain drop obviously The 1dB compression point where power gain drops by 1dB can be determined as illustrated in Fig 7 9 N 64 W 2um L 90nm Ves 0 4V Vos 0 8V eee ee LoS a a lom ean Power gain 12 5dB Estimated 1dB n T I T PF Line simulation oa 5 Power gain 14 2dB ee 1dB compression point 13 2dBm or i Sy
45. particular I must acknowledge my husband and best friend Tong Zhang Without whose love and encouragement I would not have finished this dissertation In conclusion I recognize that this research would not have been possible without the financial assistance of the Intel Corporation and Vodafone US foundation I also would like to thank IBM Microelectronics for fabrication on various technologies vii Style manual or journal used Transactions of the Institute of Electrical and Electronics Engineers Computer software used The document was prepared using Microsoft Word The plots were generated using Microsoft Visio and Matlab The Bibliography was generated using EndNote viii TABLE OF CONTENTS TABLE OF CONTENTS 555 three otis tue E a AE QUAS res DH SUR Se RT Re ede PLU COURS E E IX EISDOF EIGURES cadence nad avi Pila abet RDUM EST uq h ESL autc ed NOM SUA NE E ds DARE XII LIST OF TABLES conecte mtb rae ie tette e ap es tar e dr ef deus XIX CHAPTERS INTRODUCTION 5 desacuerdo ebat i id a inei ii ee 1 1 1 Scattering parameter measurement essesssessesseesresresseesresetesresressressesresseesse 3 1 2 Intermodulation linearity measurement sess 10 1 3 Motivation and objectives 5o eee n pue tende ifo a tcp ie tape cate dies 14 1 3 1 High frequency RF CMOS characterization sese 14 1 3 2 Four port network for on wafer parasitiCs ce ceeeeseeseereeeeeeeeeeeees 15
46. self calibration JEEE Trans Microwave Theory and Techniques vol 39 no 4 pp 724 731 1991 D K Rytting An Analysis of Vector Measurement Accuracy Enhancement Techniques Hewlett Packard RF amp Microwave Measurement Symposium and Exhibition 1987 H Heuermann and B Schiek Robust algorithms for Txx network analyzer self calibration procedures JEEE Trans Instrumentation and Measurement vol 43 no 1 pp 18 23 1994 H Heuermann Calibration procedures with series impedances and unknown lines simplify on wafer measurements IEEE Trans Microwave Theory and Techniques vol 47 no 1 pp 1 5 1999 166 83 84 85 86 87 88 89 90 W R Deal and D S Farkas A simple CAD based method to develop and evaluate calibration standards JEEE Microwave Magazine vol 7 no 3 pp 70 84 2006 S Padmanabhan P Kirby J Daniel et al Accurate broadband on wafer SOLT calibrations with complex load and thru models in Dig 61st ARFTG Conference Spring pp 5 10 2003 D Blackham and K Wong Latest advances in VNA accuracy enhancements Microwave Journal vol 48 no 7 pp 78 94 2005 F Williams Characterization of Thin Film Calibration Elements in Dig 38th ARFTG Conference Winter pp 25 35 1991 D K Rytting Appendix to An Analysis of Vector Measurement Accuracy Enhancement Techniques Hewlett Packard RF amp Microwave Measurement Symposium and Exhibit
47. size of Cascade infinity probes is 12um 12um To achieve reliable contact it is recommended to further bring the probe down by 50 75um after the probe tip has made initial contact with the wafer surface which leads to a 25 40um lateral skating Thus the minimum probing area recommended for general use is 50umx50um 55 And the minimum center to center space between pads is 100um The sizing and spacing requirements for on wafer probing make it impossible to place the probes directly on the terminals of a modern MOS transistor since the dimension of a typical MOS transistor is only several microns big Probing pads and interconnect lines leading to the terminals of the transistor are necessary for on wafer transistor characterization The GSG probing pads designed for on wafer characterization are illustrated in Section 2 2 Ground shield was proved to be able to improve noise performance and on wafer de embedding 56 57 58 The first metal layer is used to build the ground shield metal plane as detailed in Section 2 2 It was shown that different gate geometry can affect the DC and RF performance 56 59 60 61 An array of CMOS transistors with different gate pattern are carefully designed and fabricated Several parameters that 25 are critical to RF and noise performance of CMOS transistors are extracted and compared for different gate pattern in Section 2 3 2 Typical on wafer transistor test structure Fig 2 1 a is the
48. step Not all of the general four port solutions can be used for single step calibration For instance the solution of 20 can be used while the solution of 19 cannot be used The four port de embedding algorithms of 20 and 19 make no assumption of the nature of on wafer parasitics while the algorithm of 17 assumes that the four port network for on wafer parasitics is reciprocal and symmetric In this dissertation two general four port solutions that can be applied as single step calibration are developed 1 a Y parameter based analytical solution and 2 a singular value decomposition SVD based numerical solution With five on wafer standards both of them solve a generic four port network and can be applied on the measured raw S parameters without ISS calibration The results were presented in 2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems 19 2007 IEEE Trans On Electron Devices 45 and 2007 IEEE MTT S International Microwave Symposium 47 The analytical four port solution in 45 is much simpler than 20 and 19 and considers the parasitic capacitance of the non ideal on wafer load resistors An added advantage of this solution is its intimate relation with open short which is then used to quantify the errors left after open short de embedding However the Y parameter analytical solutions in 20 19 and 45 are all limited by specified on wafer standards and cannot take advantage of the red
49. the 8 error terms are ey e 4 035 and e as shown in Section 3 3 Because SVD solves the T parameters of the four port on wafer parasitics the 8 term E matrix is transformed to T matrix using 102 I lt 2 ee hs l 4 T EHE hs 1 T E hs 5 10 If only 8 error terms the diagonal elements of E E E and E are involved the non diagonal elements of the corresponding 7 T 7 and T matrices calculated using 5 10 are all zero ey 0 e 0 0 e D e m eo 0 e 0 0 e 0 e The four linear equations for each measurement are A S Si 0 A DUT S S A DUT S555 A qDUT S hS A DUT 555 Q ST Sj SaS Qr ipie S5 SaS 201 ES 0 EIE t 0 4 0 05 0 f fs 0 f 0 A 0 l f m 5 11 0 0 our 6 12 12 ger 22 Three standards give 12 equations which are sufficient to solve the 7 unknown elements in 5 12 However the set of non singular standards need to be carefully chosen Some of on wafer standards may lead to unphysical results For example with a 103 perfect matched load at Port 1 the second equation in 5 12 is S4 t 2 0 which is obviously not true in practice The singularity of the standards can be verified using condition number of the coefficient matrix Considering the 5 available standards fabricated there are six possible combinations of three standards if THRU is chosen as
50. the comparison between analytical four port solution and numerical four port solution easier the same NMOS transistor and OPEN SHORT LEFT RIGHT and THRU standards used for the analytical four port solution in Section 4 2 are used here as a demonstration Back end of line resistors are used as on wafer load in LEFT and RIGHT Imperfect on wafer load resistors are still modeled as Y G joC and Y Gk j C as shown in Fig 4 2 d and e The value of Gz C Gr and Cr are determined from low frequency open short de embedding According to analytical four port solution neglecting the capacitance does not introduce significant errors in most parameters The above process can be directly applied to solve for the combined four port network including both system errors and on wafer parasitics The S will be replaced by the measured raw S parameters S The results will be show in Section 6 2 5 3 Experimental results for on wafer parasitics de embedding Fig 5 2 shows typical de embedding results on a 32 finger N type MOS transistor at one typical bias V 1 5V V 1 5V Each finger has a gate width of 5um and a length of 0 13um S parameters are measured using a HP 8510XF system from 2GHz 97 to 110GHz ISS calibration using SOLT is first performed The ISS calibrated S parameters of the five on wafer standards shown in Fig 2 6 are then used to determine the four port T matrix 15 independent terms The transis
51. the input power level and the averaging factor as the same as the setup used for on wafer standards and transistor measurement 2 Define user functions in VNA Press the MENU key in IANEWISINSH block to bring the user parameter menu onto the CRT LCD screen Define T a b under forward mode first a and b are the waves monitored by the receivers at Port 2 Thus in VNA they are named as a2 and b2 Select USERI Press REDEFINE PARAMETER Press DRIVE PORTI Press PHASE LOCK al Press NUMERATOR b2 Press DENOMINATOR a2 184 Press CONVERSION I S Press PARAMETER LABEL then enter a2 b2 then press TITLE DOWN REDEFINE DONE Define T 2a b under reverse mode a and b are the waves monitored by the receivers at Port 1 Thus in VNA they are named as al and bl Select USER2 Press REDEFINE PARAMETER Press DRIVE PORT2 Press PHASE LOCK a2 Press NUMERATOR bl Press DENOMINATOR al Press CONVERSION l S Press PARAMETER LABEL then enter al bl then press TITLE DOWN REDEFINE DONE 3 Measure I and T Display all of the four S parameters on the screen first Press the DISPLAY key in IVISMEN block Select DISPLAY MODE FOUR PARAM SPLIT All of the four S parameters S11 S21 S12 and S22 are displayed on the screen Then replace two of the S parameters with the defined user fun
52. the single step calibrated results with and without switch error removal for the two four port solutions The two step four port calibrated results are also shown for comparison Fig 6 5 compares results using analytical four port while Fig 6 6 compares results using SVD based numerical four port Both of them indicate that switch errors are the most important reason for the ripples in single step calibration 113 Switch error terms T and T are determined by the load impedance connected to the switch inside the VNA system which does not change a lot even for months Adding switch error removal will not cost a lot of labor for large volume measurements ISS Calibration analytical 4 port Single step analytical 4 port with switch error Single step analytical 4 port without switch error frequency GHz frequency GHz Fig 6 5 Comparison of the single step four port calibrated results with and without switching error correction The analytical four port solution in Section 4 2 is applied 114 ISS Calibration SVD 4 port Single step SVD 4 port with switch error Single step SVD 4 port without switch error RY RY RY 42 0 01 0 02 0 04 0 02 10 frequency GHz frequency GHz Fig 6 6 Comparison of the single step four port calibrated resul
53. top view of an on wafer test structure for a MOS transistor with probing pads and interconnections GSG probing pads are designed for the GSG Cascade infinity probes which can shield the signal path between two balanced ground paths and provide tight control on the fields around the signal probe The dimension of the probing pads and interconnections are much larger than the transistor Fig 2 1 b gives a closer view of the MOS transistor under test The four terminal MOS transistor is connected as a two port system with source and substrate tied together to ground The MOS transistor in general has multiple gate fingers to reduce gate resistance and a substrate ring around the whole active area to provide better shielding from adjacent structures The channel width of MOS transistors can be modified by either changing the width of each finger or changing the number of fingers 26 100 150um Gate Fingers a MOS PAD b MOS only Fig 2 1 The top view of an on wafer test structure for transistors a The whole test structure including probing pads b The MOS transistor under test only The dimension is not to scale Fig 2 2 shows the pictures of the chips taken under the microscope Fig 2 2 a shows the chip fabricated on a 0 13um RF CMOS technology for developing four port calibration techniques Each column contains five on wafer standards and a 0 13pm NMOS transistor An array of 90nm NMOS test structures with different gate
54. 007 163 48 49 50 51 52 53 54 55 56 57 58 59 V Aparin G Brown and L E Larson Linearization of CMOS LNA s via optimum gate biasing in Proc of Int Symp on Circuits and Systems pp IV 748 51 2004 D Linten L Aspemyr W Jeamsaksiri et al Low power 5 GHz LNA and VCO in 90 nm RF CMOS in Dig of IEEE Symp on VLSI Circuits pp 372 375 2004 R Sung P Bendix and M B Das Extraction of high frequency equivalent circuit parameters of submicron gate length MOSFET s JEEE Trans Electron Devices vol 45 no 8 pp 1769 1775 1998 C Fager J C Pedro N B de Carvalho et al A comprehensive analysis of IMD behavior in RF CMOS power amplifiers JEEE J Solid State Circuits vol 39 no 1 pp 24 34 2004 V Aparin and L E Larson Modified derivative superposition method for linearizing FET low noise amplifiers JEEE Trans Microwave Theory and Tech vol 53 no 2 pp 571 581 2005 X Wei G Niu Y Li et al Experimental characterization and simulation of RF intermodulation linearity in a 90 nm RF CMOS technology in Dig of IEEE Radio Frequency Integrated Circuits Symp pp 251 254 2008 X Wei G Niu Y Li et al Modeling and characterization of intermodulation linearity on a 90nm RF CMOS technology JEEE Trans Microwave Theory and Techniques submitted Cascade Microtech Mechanical Layout Rules for Infinity Probes
55. 1 3 3 General TOUT port SONI ON is ss ad coed cts at esanectect aap andeeted detaedewuenetnnals 17 1 3 4 Single step calibration iei ciet s tos reti eid 19 1 3 5 Validity of BSIM4 model for nonlinear RF modeling 21 1 3 6 Third order intercept point modeling sss 2 1 3 7 Third order intermodulation distortion characterization 22 1 4 Outline of Contributions o ce Dee vni Rate uo dat n RE eun ta cg 23 CHAPTER 2 ON WAFER TEST STRUCTURE sce isto cig ustedes tere etia e Tria ise dedncdis 25 2 1 Typical on wafer transistor test structure sssssseeeeeneenneee 26 2 2 Probing pad design considerations 28 2 3 CMOS transistor design considerations essere 32 2 3 1 Gate pattern and multiplier factor 35 2 3 2 Gate finger configuration s istos Creed cepi iere Bier sed muse 39 2 4 NI DEM SRI Aaa Saag david nd Ava waaes dascea Ata cacvesvaaune E a taacnt Ata EA E Ata eee 41 CHAPTER 3 ERROR MODELS FOR TWO PORT S PARAMETER MEASUREMENT 42 3 1 Two port S parameter MeasureMent eeeceeececeeseceeeeeeeceteeeceteeeesteeeeeaeeees 44 3 2 Error adaptor CONCEP accen o eve neg b uS ean ent ddp eidem deae 49 3 3 The simplest 8 term error model sca eret rre tr ne terere 50 3 4 The classical 12 term error model ee tetti eta taque tata Put honte Plon 51 3 4 1 Forward MOE crede ne E EE ca EO E E etd obs reas 52 242v ARGV CESS mode forsset ea e a
56. 2 Intermodulation linearity measurement The third order intercept point IP3 is defined as the point where the 3 order intermodulation IM3 product equals the fundamental frequency product for a two tone excited system To extract IP3 the power levels of the fundamental and the IM3 products at the output have to be measured using a spectrum analyzer Fig 1 6 shows a two tone intermodulation linearity measurement system with two identical Agilent performance signal generators PSG E8247 at the input and an Agilent 8563EC performance spectrum analyzer PSA at the output 22 The signals generated by the two PSGs have the same power level the same phase but different frequencies A power combiner with good isolation is required to combine the two signals Otherwise the power combiner itself may produce extra intermodulation products The products will be amplified by the DUT which leads to a much larger intermodulation product at the output and thus introduce undesired errors when extract IP3 of the DUT Proper attenuators maybe included before the power combiner to provide low enough input power level DC bias circuits at the input and output are necessary for transistor 10 linearity characterization The power spectrum is measured at the output by a PSA and output IP3 OIP3 is calculated by an Agilent 85672A spurious response utility installed in the PSA This utility can give not only the amplitude of the fundamental and IM3 product
57. 7 no 4 pp 734 740 2000 A Rumiantsev and N Ridler VNA calibration JEEE Microwave Magazine vol 9 no 3 pp 86 99 2008 R A Speciale A Generalization of the TSD Network Analyzer Calibration Procedure Covering n Port Scattering Parameter Measurements Affected by Leakage Errors JEEE Trans Microwave Theory and Techniques vol 25 no 12 pp 1100 1115 1977 J V Butler D K Rytting M F Iskander et al 16 term error model and calibration procedure for on wafer network analysis measurements IEEE Trans Microwave Theory and Techniques vol 39 no 12 pp 2211 2217 1991 162 37 38 39 40 41 42 43 44 45 46 47 R A Speciale and N R Franzen Super TSD A Generalization of the TSD Network Analyzer Calibration Procedure Covering n Port Measurements with Leakage in Dig IEEE MTT S Int Microwave Symp pp 114 117 1977 A Gronefeld and B Schiek Network analyzer self calibration with four or five standards for the 15 term error model in Dig IEEE MTT S Int Microwave Symposium vol 3 1997 pp 1655 1658 vol 3 K Silvonen LMR 16 a self calibration procedure for a leaky network analyzer IEEE Trans Microwave Theory and Techniques vol 45 no 7 pp 1041 1049 1997 R A Pucel W Struble R Hallgren et al A general noise de embedding procedure for packaged two port linear active devices JEEE Trans Microwave Theory and Techn
58. 8 0 9 Vas V 0 3 a S2 in dB versus frequency at Vgs 0 4V and V 1 0V b S in dB versus V at SGHz and V 1 0V Fig 7 5 90nm 2um L 64 W N 150 zu9 5 V Ves Fig 7 6 fr extracted from measured and simulated S parameters 123 N 64 W 2um L 90nm Simulation 0 02 0 1 Measurement Vas 0 4V Vos 1 0V 0 02 0 04 0 01 0 02 0 05 0 10 20 30 40 frequency GHz frequency GHz Fig 7 7 Y parameters versus frequency at V 0 4V and V 1 0V R and 3 stand for real and imaginary parts 124 x 10 N 64 W 2um L 90nm Simulation 1 0 01 Measurement f0 5GHz Vos 1 0V oe amp 5p besnchenee miei gt 0 005 amp Lua a RR RC eS U 0 0 2 ur an PERENNE S aede eee eee S atn 5 x 10 iene Df Pnanannupnnunnnnnnnnn 2 L 2 L 0 05 0 01 l i A I G s y 0 005 aa EST T ai ett see co i I gt S i as n l 0 0 5 1 0 0 5 1 Ves V Ves V Fig 7 8 Y parameters at 5GHz versus V Vps 1 0V R and 3 stand for real and imaginary parts 7 3 Nonlinear characteristics In real applications the nonlinearities of the transistors and other components can introduce undesired harmonic products to the output signal Since the amplitudes
59. A M M A B M A A THRU M M A A A B M A THRU A M M B B M A A THRU M M A A A B M B THRU A M B A B M A A THRU M M A A AM M A THRU A M B A M B A A THRU M M A A A M M B THRU A M B A A B B B THRU M M A A BM M B THRU A M M A A B B B THRU M M A B A M B A THRU A M B M A B B B THRU M M A B AM M A THRU A M M B B A B B THRU M M A B A M M B THRU A M M B B M B B THRU M M A B BM M A THRU A M M A B M B B THRU A M M A B M A B THRU A M M A B M B A THRU A M M B A B B A THRU A M M B B M A B THRU A M M B B M B A THRU A M B M A B B A A open B short or A short B open Reference K J Silvonen Calibration of 16 term error model Electronics Lett vol 29 no 17 pp 1544 1545 1993 199 condition number 0 5 S l l i LLLI a ao n n a e e e D m aS n a l ll minimum singular value maximum singular value 3 6 T l frequency GHz Fig G 2 Condition number minimum and maximum singular value for five standards Dash Line 5 standards M M Dot Line 5 standards M M amp L 400um transmission line N oa N e condition number e co oa 0 20 40 60 80 100 frequency GHz Fig G 3 Condition number for multiple number of standards 200 APPENDIX H ONE PORT ERROR CORRECTION Fig H 1 shows the block diagram for a one port system The system consists of a sweep oscillator a dual reflect
60. Application Note 2004 C S Kim J W Park H K Yu et al Gate layout and bonding pad structure of a RF n MOSFET for low noise performance IEEE Electron Device Lett vol 21 no 12 pp 607 609 2000 T E Kolding O K Jensen and T Larsen Ground shielded measuring technique for accurate on wafer characterization of RF CMOS devices in Proc of IEEE Int Conf on Microelectronic Test Structures pp 246 251 2000 T E Kolding Shield based microwave on wafer device measurements EEE Trans Microwave Theory and Techniques vol 49 no 6 pp 1039 1044 2001 H Tsuno K Anzai M Matsumura et al Advanced Analysis and Modeling of MOSFET Characteristic Fluctuation Caused by Layout Variation in JEEE Symp on VLSI Technology pp 204 205 2007 164 60 61 62 63 64 65 66 67 68 69 70 T Tanaka A Satoh M Yamaji et al Fully considered layout variation analysis and compact modeling of MOSFETs and its application to circuit simulation in ZEEE Int Conf on Microelectronic Test Structures pp 223 227 2008 T E Kolding Test structure for universal estimation of MOSFET substrate effects at gigahertz frequencies in Proc of IEEE Int Conf on Microelectronic Test Structures pp 106 111 2000 A Cathignol S Mennillo S Bordez et al Spacing impact on MOSFET mismatch in JEEE Int Conf on Microelectronic Test Structures pp 90 95 2008
61. D based four port Solution 25i ears d etate tail es etd Be ab A Yu Pata 94 5 3 Experimental results for on wafer parasitics de embedding 97 5 4 Reduction of Error Terms and Number of Standards 100 5 4 1 Quantify error terms for four port on wafer parasitics 100 5 4 2 8 term solution using three on wafer standards 102 5 5 NITIDIS ET 106 CHAPTER 6 SINGLE STEP CALIBRATION sg esten Up nee ADAE Nep t e ae RE ede 107 6 1 X Analytical four port single step calibration see 108 6 2 Numerical four port single step calibration sess 111 6 3 Impact of switch errors ees eoe dris eA c remite UNS eat ed 113 6 3 1 Quantify error terms using S parameters sssssseese 115 6 4 sunt EEE 117 CHAPTER 7 VALIDITY OF BSIM4 MODEL FOR NONLINEAR RF MODELING 118 7 1 Linearity measurement and simulation esee 119 7 2 DCandlimneateldractetistiGsos soie dated toa cp Eia pedi RISE Y GARE 121 7 3 Nonlinear cHaractentsties erroe n arie qd eH reda e EH qd er beca ds 125 7 4 SURE TAIL HE oso estet as tame cca stata cited aate co P uLos e c e La peel s 131 CHAPTER 8 MODELING OF INTERMODULATION LINEARITY eene 132 8 1 First order IP3 160b ss Dateate ato qe Pd Di Ie pit ga du REO n ed Ire E OMEN 133 8 2 Complete IPI expression oeste al
62. DATA E 9 RI DATA E 10 RI DATA E 11 RI DATA E 12 RI NA SWEEP TIME 1 839999E 1 NA POWER1 2 5E1 NA POWER2 2 5E1 NA PARAMS 30 NA CAL TYPE 5 NA DOMAIN TYPE 0 NA POWER SLOPE 0 0E0 NA POWER SLOPE2 0 0E0 Fig 3 17 show S and S of a 0 13um NMOS transistor for 2 110 GHz Raw data is the measured S parameters without any error calibration Corrected data is the data with system error calibrated using SOLT calibration For parameter extraction and device modeling both real part and imaginary part of the S parameters are important Error correction is necessary at all frequencies 60 N 30 W pi L 130nm Ves 0 6V Vos 1 5V 2 51 Raw Data Corrected Data atatum m 4a oe 5 4 P 1 5 r T os i cc Wee even eee o M DOG MM Um __ T if aon U ib v Arm de l f C4 e o 0 L 0 50 100 frequency GHz frequency GHz Fig 3 17 Raw and corrected data for S and S ofa 0 13um NMOS transistor 3 5 The most complete 16 term error model The most complete mathematic model for a four port network is 16 term model since four port network is essentially a 4x4 matrix Fig 3 18 shows the signal flow graph of the four port error adaptor containing 16 error terms The reflection at each port contributes four error terms including two directivity errors ey and e and two port
63. DUT open T E y PUT short _ y DUT open eh l F 11 Substituting F 9 and F 10 into the Y expression above VOUT _ yPUT open _ yei yi B yay j l ye F 12 y DUT short y DUT open _ yei y y Y F 13 and thus yer Jr e aet T r G bal i F 14 The equation is too complicated to give any clue of the relationship between Y and Y It must be simplified The first thing can be done is taking the Y and Y out y y i ra Y zd y F 15 It is difficult to further simplify the equation because of the plus minus operators inside the brace To eliminate the plus minus operations two identity matrices v Y Y Y and v v are added to F 15 194 y y c H ys ie E rad v j Sis Ly v yr o Y F 16 Taking the common elements Y 4 y and Y s out of the square brackets leads to yo y TOET Y Y rr yid F 17 which is equivalent to y y n gr y4p ys 3 ae F 18 This gives a very simple relationship between Y and Y yecye cal a ye F 19 Although F 19 is derived for on wafer parasitics and starts from open short de embedding the solution is general to single step calibration as long as Y 0 2x2 and Y QUU p 0 a2 The only difference is that when it is applied on the measured raw S parameters without ISS calibration Y Y and Y do not have their physical meanings as what they have in two step calibration 195 APPENDIX G
64. EN a THRU a SHORTI and a SHORT2 are necessary for three step de embedding 15 16 Pad open short lumps the parallel parasitics at the pads and the interconnect lines separately Three shunt elements are used to represent the parallel parasitics at the pads which can be evaluated from a PAD standard without any interconnect lines The distributive parallel parasitics along the interconnect lines is lumped as three series elements and three shunt elements at the end of interconnect lines Although pad open short lumps on wafer parasitics as nine 6 elements it only need three standards a PAD an OPEN and a SHORT 17 Pad open short was shown to be better than open short for on wafer inductor structures measured above 10GHz However this improvement to a large extent depends on the layout design 17 For on wafer transistor structures the interconnect lines are not as long and wide as the interconnect lines for the conductor structures in 17 and the parallel parasitics along the interconnect lines is not comparable to the pad parasitics In this case pad open short will not show great advantage over open short a Open short b Three step c Pad open short Fig 1 4 The lumped ene circuits for a open short b pad open short and c three step de embedding Fig 1 5 shows the equivalent input resistance and capacitance AR and C extracted from two step calibration results 18 19 The system errors are ca
65. Ke point increases as device size increases W 2um L 90nm Vos 0 8V f0 5GHz Af 100KHz 20 j I I mE pp N MO 15 Number of finger Z K3 20 757 7 N 20 increase N64 dU oer eee ee de Medo ee ee ee eee eee dudes A t D 5X REI 97349 ee pe peperere fess eo 0 Laie i ke OE as I agi VEL TENERE ERI DI ee ee ee eG eee lace d i acd xal EE Symbol Measurement a ae Line Simulation 10 i 0 10 20 30 40 50 60 70 80 90 100 Jpg uAlum Fig 7 12 Measured and simulated IIP3 versus Jp for devices with N 10 20 and 64 Fig 7 13 and Fig 7 14 show the measured IIP3 at 2 5 and 10GHz for devices with N 10 and 64 a total width of 20um and 128um For N 10 IIP3 at 2 5 and 10GHz are practically identical For N 64 IIP3 increases as frequency increases This frequency dependence can be attributed to capacitive components in the transistor as 129 detailed in Section 9 2 3 The frequency dependence of simulated IIP3 in Fig 7 13 and Fig 7 14 is similar to the frequency dependence of measured IIP3 N 10 W 2um L 90nm Af 100KHz 20 i f0 2GHz f0 5GHz dor nossssssed a sai hatalare earececetetena M f0 10GHz d 5cebcecbre ey Oona ee Soe ag E Lor B 5 gf 5G e Q i 0 y p a fa MET Symbol Measurement Line Simulation i 3m
66. Linearity analysis of CMOS for RF application JEEE Trans Microwave Theory and Tech vol 51 no 3 pp 972 977 2003 B Toole C Plett and M Cloutier RF circuit implications of moderate inversion enhanced linear region in MOSFETs IEEE Trans Circuits Syst I Reg Papers vol 51 no 2 pp 319 328 2004 L Tzung Yin and C Yuhua High frequency characterization and modeling of distortion behavior of MOSFETs for RF IC design JEEE Journal of Solid State Circuits vol 39 no 9 pp 1407 1414 2004 C H Doan S Emami D A Sobel et al Design considerations for 60 GHz CMOS radios JEEE Communications Magazine vol 42 no 12 pp 132 140 2004 T Yao T Yao M Gordon et al 60 GHz PA and LNA in 90 nm RF CMOS in Dig of IEEE Radio Frequency Integrated Circuits RFIC Symposium 2006 pp 4 pages T LaRocca and M C F Chang 60GHz CMOS differential and transformer coupled power amplifier for compact design in Dig IEEE Radio Frequency Integrated Circuits Symp pp 65 68 2008 S T Nicolson A Tomkins K W Tang et al A 1 2V 140GHz receiver with on die antenna in 65nm CMOS in Dig IEEE Radio Frequency Integrated Circuits Symp pp 229 232 2008 B Oldfield Wafer Probe Calibration Accuracy Measurements in Dig 48th ARFTG Conference Fall pp 54 58 1996 T E Kolding A four step method for de embedding gigahertz on wafer CMOS measurements JEEE Trans Electron Devices vol 4
67. ON WAFER S PARAMETER MEASUREMENT USING FOUR PORT TECHNIQUE AND INTERMODULATION LINEARITY OF RF CMOS Except where reference is made to the work of others the work described in this dissertation is my own or was done in collaboration with my advisory committee This dissertation does not include proprietary or classified information Xiaoyun Wei Certificated of approval Richard C Jaeger Distinguished University Professor Electrical and Computer Engineering Guofu Niu Chair Alumni Professor Electrical and Computer Engineering Fa Foster Dai Professor Electrical and Computer Engineering Stuart Wentworth Associate Professor Electrical and Computer Engineering George T Flowers Dean Graduate School ON WAFER S PARAMETER MEASUREMENT USING FOUR PORT TECHNIQUE AND INTERMODULATION LINEARITY OF RF CMOS Xiaoyun Wei A Dissertation Submitted to the Graduate Faculty of Auburn University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy Auburn Alabama December 19 2008 ON WAFER S PARAMETER MEASUREMENT USING FOUR PORT TECHNIQUE AND INTERMODULATION LINEARITY OF RF CMOS Xiaoyun Wei Permission is granted to Auburn University to make copies of this dissertation at its discretion upon request of individuals or institutions and at their expense The author reserves all publication rights Signature of Author Date of Graduation ill VITA Xiaoyun Wei
68. SINGULARITY OF LINEAR EQUATION SET G 1 Typical calibration standards The most common calibration standards used for S parameter measurement are two port standards through THRU and delay DELAY and one port standards match M short S and open O The one port standards are used in pairs to build a two port standard for two port system calibration For example the LEFT standard used for four port calibration can be viewed as a M O standard which means a matched load at Port 1 and an open standard at Port 2 A zero length THRU is kept for all of the combinations examined below for two reasons First the set of standards must includes a two port standard to measure the transmission errors That means a THRU or DELAY standard must be included Secondly the ends of the interconnects of Port 1 and Port 2 are very close for on wafer transistor structures Thus a zero length THRU structure is the one of the simplest structures to be built on wafer The results shown below are from Cadence simulation The parasitic network is built using ideal resistor capacitor and inductors with values close to the values extracted from measurement The M standard is an ideal 50 resistor since the VNA system is a 50Q system 196 G 2 Singularity of on wafer standards An analytical proof for the singularity of the combinations of standards is complicated However it can be easily examined by numerical simulation examples using condition number of the
69. a Duas uM Utd e Es 33 343 l2 term modelna eree e dolemue O icta qp mnes AND eq na 1E 55 3 44 SOL Cali Orato ot ro erc e i atra dels ERA Pen 58 3 5 The most complete 16 term error model ssesseeeee 61 3 6 Error adaptor for single step calibration essseeeeee 66 3 7 vun 70 CHAPTER 4 GENERIC ANALYTICAL FOUR PORT SOLUTION ccssceccccescececceseecenteeecees 71 4 1 Four port network in Y parameters cccccscccesecesecceseceeeeeeseeeeaeceeeeeeeenseees 73 4 2 General four port SOIUTOTI eo eicere cett dicent oe tds 74 4 2 1 Relationship between open short and four port ssse 74 4 2 2 Open short de embedded LEFT RIGHT and THRU TI 4 2 3 Analytical solution of A and B ou ce ceccesceeeeececeeeceteceeeeeeaeeeaeees 78 4 2 4 Summary of general four port de embedding 83 4 2 5 Impact of non ideal load in LEFT and RIGHT 84 4 2 6 Quantifying errors of open short essen 86 4 2 7 Reciprocity and symmetry of the four port parasitics 87 4 3 Reciprocal four port solution and pad open short sss 88 4 4 Munt e 90 CHAPTER 5 NUMERICAL FOUR PORT SOLUTION eese nnne 92 5 1 Four port parasitic network in T parameters sse 93 5 2 SV
70. ables and connectors must be calibrated using a power meter The power loss on the input and the output route must be calibrated using 1 1 in P L dBm 1n dBm 1n dB 1 2 out L dBm out qgy out 12 dB P is the power level generated by the signal generator P n gt 1 the output power level monitored at the spectrum analyzer P is the actual input power level at the gate of the NMOS transistor Pou is the actual output power level at drain terminal of the transistor Lin and Louw are the power losses on the input and output routes Lin and Lou are frequency dependent and need to be determined for each frequency before measurement In practice Lin is much larger than Lou which can lead to a several dB shift on IIP3 and power gain Relatively speaking the value of OIP3 is much less sensitive to power calibration Instead of using two tone measurement IIP3 can also be determined using simulated or measured I V data and small signal parameters of the transistor which just requires DC and S parameters measurement For both measurement and simulation DC and S parameters are much easier to obtained and much less time consuming Fig 1 8 compares first order IP3 with measured and simulated IP3 The derivation of first order IIP3 is detailed in Appendix I K3z is calculated using the 3 order derivative of I with respect to V only The first order IIP3 expression fails in modeling the pos
71. ails Even though system errors are removed more accurately with ISS standards when compared with single step calibration the failure of open short on wafer de embedding makes the final result invalid The added advantage of using SVD is that it not only solves the system equations but also gives valuable information about the system 36 89 The condition number of 112 the coefficient matrix is an indicator of the error sensitivity For the same inaccurate on wafer standards the condition number is noticeably higher for single step four port calibration as shown in Fig 6 4 indicating less tolerance to measurement errors This is another reason for the less accurate single step result compared to the two step result with ISS calibration 30 T T T T T i i n d amp 25 ere m a ra SSS 455 Hapasaa ELE 2 I i 1 i n A iy Without ISS calibration amp IV IM 320 dore De EISE Ne AES ur Let eve SSeS f A I v i z I I Vul a I Ss 9 l I yf l l BAS ese poses ae ee P EGS a L xd B dde eT i x Lacan NWith ISS calibration 0 20 40 60 80 100 Frequency GHz Fig 6 4 Condition numbers of the coefficient matrix in on wafer parasitics de embedding and single step calibration 6 3 Impact of switch errors One possible reason for the ripples is the switch errors To investigate this the switch errors are removed using the algorithm in Section 3 1 80 Fig 6 5 and Fig 6 6 compare
72. alibration can provide the most accurate system error information as long as the ISS standards are accurate The disadvantage is that the system error calibration step is time consuming and need to be rechecked several times for hourly measurement Also two step calibration involves a process to switch between the ISS substrate and the wafer Another approach the so called single step calibration defines only one reference plane which is the reference plane at the device terminals On wafer standards are used to determining the error terms The systematic errors and on wafer parasitics are removed in a single step The difficulty is that most IC processes cannot deposit a precision resistive load with good repeatability 21 Due to the less accurate on wafer standards single step calibration are expected to provide less accurate S parameters when compared with two step calibration and thus not widely 9 used for on wafer characterization However the same on wafer standards are used for on wafer de embedding and these standards are assumed to be ideal for simplicity in two step calibration There is no occasion to have a huge difference between two step calibration and single step calibration using the same non ideal n wafer standards With appropriate error calibration techniques single step calibration may be able to provide reasonably accurate results This issue should be examined experimentally on advanced silicon technologies 1
73. allow signal propagation from T input to output As a result the s and terms used to represent the non ideal THRU in 19 are close thus only a single Y term is used here which helps to considerably simplify the general four port solution and make the new solution applicable to single step calibration Y does not need to be known as it will be cancelled out during de embedding 4 2 3 Analytical solution of A and B The open short de embedded Y parameters of LEFT and RIGHT Y and y 5 can be related to elements of A and B by substituting Y and Y in 4 14 into 4 9 Both Y and Y have 3 zero elements thus the final product of AY B only contains simple product of the elements in A and B For convenience we use M and N defined below instead of Y 5 and y 5 9 M 2 y99 jy ab d 4 15 a 45b db N 2 yos py a b 2 4 16 db anba and N are the i j elements of A B M and N i j 1 2 Note ip i where a b M that M and N are known matrices for the following procedures At first glance one may attempt to solve the 8 elements of A and B from the 8 equations provided by LEFT and RIGHT 4 each in 4 15 and 4 16 This however is not the case as only three of the 4 equations provided by each measurement are independent For example the ratios of M M and M M both give a a 78 Thus only three unknowns can be solved as a function of the fourth unknown
74. ally five on wafer standards are necessary when the standards are combinations of Y ie open short matched load in addition to a through line Once Y Y ee ei and Y are known the actual Y parameters Y of any transistor can be easily retrieved from the p y y DUT measured Y 4 2 General four port Solution 4 2 1 Relationship between open short and four port Substituting the Y parameters of an ideal OPEN and an ideal SHORT into 4 3 i e y 0 and Y xu EE the measured Y parameters of OPEN and 2x2 SHORT can be obtained as 20 1 y PUT open Y Y D Y S 4 5 y PUT short Y i 4 6 74 Note that ideal OPEN and SHORT are used in all analytical de embedding methods to achieve an analytical solution The equivalent two port networks of ideal OPEN and SHORT standards are shown in Fig 4 2 b and c The SHORT measurement directly yields Y However solving Y Y and Y proves difficult because of the nonlinear le L DUT relationship between Y and Y due to matrix inversion and multiplication Emm E ES zi af pet kan NONEM a a NMOS b OPEN c SHORT Tr bo of rpm o I L o l l Y l l T eg Ic Eug 3 ro of t d LEFT e RIGHT f THRU Fig 4 2 The equivalent two port network of the intrinsic NMOS transistor and the five on wafer standards OPEN SHORT LEFT RIGHT and THRU Recall that the open short de embedde
75. an accurately describe the distributive nature of on wafer parasitics are urgently needed 1 3 2 Four port network for on wafer parasitics As discussed in Chapter 2 the accuracy of error calibration is determined by the error model calibration standards and calibration techniques A unified 12 term model was developed in 1970s and became a standard model for two port VNAs The SOLT calibration technique is implemented in all modern VNAs to solve the 12 error terms 34 However the 12 term error model was shown to be insufficient for high frequency 15 measurement since the leakage errors were modeled using only two error terms in the 12 term model 35 36 Same problem exists for error calibration techniques using 8 10 term model The most complete error model for two port system is a 4x4 matrix a 16 term error model which is essentially a four port error network relating four known waves and four unknown waves 35 36 Several advanced techniques solving the four port network have been developed over the years 36 37 38 39 The 16 term model and the calibration techniques can in general be applied to remove both systematic errors and on wafer parasitics This leads to an idea of describing everything between the probe tips and the device terminals as a four port network instead of using lumped equivalent circuits 40 20 an idea that is similar to the 16 term error adaptor in system error correction 36 at least math
76. arameters for evaluating the RF max and noise performances of a MOS transistor 56 SOLT calibration is used for system error calibration Since the parameters examined here are extracted at frequencies below 10GHz open short is valid in this frequency range 14 45 f is extracted using the 20dB dec extrapolation method from the H versus frequency curve at each bias point Fux 1 extracted using the 20dB dec extrapolation method from the Mason s unilateral 36 gain MUG versus frequency curve at each bias point 64 An example of f and Fox xtraction is shown in Fig 2 8 and Fig 2 9 Maximum available gain MAG and maximum stable gain MSG do not follow the 20dB dec slope and thus are not used and g are extracted using 65 g for f a extraction R 2 1 lowest frequency R Ya and Em low frequency 10 10 frequency Hz 10 ap IZH Fig 2 8 An example for f extraction aP SSI 2 9viN ap SN frequency Hz Fig 2 9 An example for f a extraction 37 Fig 2 10 compares R Zm f and f extracted for the three NMOS transistors Fig 2 10 a and c show that the transconductance and the cut off frequency for the three transistors are approximately the same Fig 2 10 b shows that the transistor with double sided gate contact and M 4 has the smallest gate resistance and thus the best noise performance theoreticall
77. art of four port de embedded y using different a a choices The a a defined from M M is clearly nosier and should not b used Rr 82 The four port de embedded transistor Y parameters with and without including parasitic capacitance in Y and y For comparison open short de embedded results are also plotted No reciprocal assumptions are made for four port parasitics de embedding sss 85 Effective gate resistance and capacitance extracted from four port de embedded results with and without parasitic capacitance included in LEFT and RIGHT Open short de embedded results are also shown for comparison No reciprocal assumptions are made ssessss 86 The elements of A and B versus frequency sse 87 Reciprocal four port de embedded transistor Y parameters versus the results using open short and pad open short de embedding 90 The four port error adaptor for on wafer parasitics in wave representation zm doces evt oe reir a a lire ERO RR EP E E AR ER HR NE dooce 93 Comparison of Y parameters between open short pad open short SVD based numerical four port solution and analytical four port SOl ti oM in aiae tuti Ro nud E A aa AA er E A esie ha ee ro 98 Comparison of effective gate resistance and capacitance between open short pad open short SVD based four port solution and analytical fo r port SONMMION sis rensa e ys
78. as sideo bobus et oia ERR ad ER RA 145 th IIP3 calculated using 8 5 versus V at multiple V for simulation with and without AV DIBL eeeeeeseeeeeeeene nnne 145 th a Ke g tAitArtA3t Ag b K3e g and c Art A versus Vos at multiple V for Cadence simulation with and without AV DIBL 147 Gain from linearity measurement P P and gains parameter measurement 5 VErSUS E accessi coke neo seein 150 Measured and analytical IIP3 versus V at multiple V Analytical IIP3 is calculated using 8 5 e eure retra eene thinner n etn Fori o cri ende 152 K3g g and K3 g Ap Az A3 A versus V at multiple V 153 Measured and analytical IIP3 versus J for devices with N 10 20 and 64 Analytical IIP3 is calculated using 8 5 sss 154 xvi Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig 9 5 9 6 9 7 9 8 9 9 C 1 C2 C 3 C 4 C 5 C 6 Ca C 8 D 1 F 1 G 1 G 2 G 3 H 1 Measured IIP3 versus J at multiple frequencies for N 10 and 64 W 20um and 128 771 E 155 Analytical IIP3 a without C and b with C at multiple frequencies for N 64 W 128um Analytical IIP3 without C is COGIC NAGE using 8 9 ose nona RUNE Res inanimate IUD uS uU Ocud UU Mab ERN DIRE 156 Analytical IIP3 with and without C at multiple frequencies for N
79. ature of S parameters 35 36 41 42 Since T parameters represent the same four port network as the E matrix the same singularities exist in T and E matrices although they are not that obvious in T matrix By numerical simulation it was shown in 39 that the equations are singular for any four standards The condition numbers of several sets of four standards are shown in Appendix G There must be additional assumptions of the four port network if 15 unknowns are solved using four standards 39 41 Five on wafer standards are strictly needed for a general four port solution One of the standards should be a two port standard or a though connection e g THRU in Fig 2 6 There is no upper limit for the number of standards However if the five standards chosen are nonsingular adding more standards will not greatly improve the de embedded results as shown in Appendix G Given pairs of S and S of five known standards the elements of T can be determined from twenty 5x4 linear equations using 5 6 The set of linear equations can be written as 454 7 Bx The set of equations 454 7 Bx is over 96 Aos B2ox1 gt Where determined and can be solved using SVD The solution is 7 Ajas is the pseudo inverse of A The 15 term solution 7 45 4 B is sufficient for calculating actual S from measured S for any unknown DUT using an alternative expression of 5 1 as g4 7 s py Seer si 5 7 To make
80. b SHORT Fig C 2 Equivalent circuits and layouts of a OPEN and b SHORT standards 173 C 2 Pad open Short de embedding Fig C 3 shows the equivalent circuit for pad open short de embedding Fig C 4 shows the equivalent circuits and layouts of the PAD OPEN and SHORT standards Denoting Y as C 1 Z as C 2 and Y as Y Y Y a es NN C 5 X Thus YO Sy ye oy Zend Ya Zee Zand ean be solved as 1 Z ees _ yMpad C 6 a E rona io y pad ig EE ene a y M74 yy i yM pen oo y pad j C 7 The equivalent circuit that shown in Fig C 3 gives 011 Y Y Z Y Y C 8 Y can then be obtained as 1 y r En A Y C 9 Pad open short de embedding lumps the distributive parasitics along the connections at the pad and the end of connections which can work up to 50GHz 174 a PAD b OPEN c SHORT Fig C 4 Equivalent circuits and layouts of PAD OPEN and SHORT standards for pad open short 175 C 3 Three step de embedding Fig C 5 shows the equivalent circuit for three step de embedding Fig C 6 shows the equivalent circuits and layouts of the OPEN SHORTI SHORT2 and THRU standards Denoting Y 0 Y 0 Y 7 Jod Z S Zo WW Io h Y C 10 C 11 C 12 Y and Y can be related through C 8 and C 9 The elements of Y Z and Y can be solved from on wafer standards since y sor Y 3 Zi 2 ZO HY We d Soc
81. b The four port network for on wafer parasitics 4 port error adaptor 1 3 3 General four port solution Even though on wafer parasitics is passive and the associated four port network should be reciprocal there are two practical reasons to seek for a solution for generic four port network which we will refer to as general four port solution First in order to arrive at an analytical solution a must for real time fast measurement on wafer OPEN and SHORT standards are assumed to be ideal in all of the de embedding algorithms while the fabricated standards always have parasitics In board measurements inaccuracies of standards are known to lead to nonreciprocal S parameters for physically passive structure 46 A general four port solution will allow us to examine the reciprocity of the four port parasitics experimentally The second reason for seeking a general four port solution is to directly obtain transistor S parameters from the measured raw S parameters without having to perform 17 system error calibration using ISS This can result in significant saving in time and effort as ISS calibration is time consuming and needs to be repeated frequently even during a day of measurement Also physical change of substrate is involved Ideally the same general four port solution obtained for on wafer parasitics de embedding can be applied to raw S parameters as is to remove VNA system errors and on wafer parasitics in a single
82. b e e 3 30 31 3 32 b i 5 b 50 Cy en Lh For reverse mode it is 65 by 3 o1 o b e e e a 5 33 31 amp 32 3 ML IE 3 33 b n b 5 LAr There are 12 error terms in forward mode and 12 error terms in reverse mode if all leakages are considered It is published in 1997 as a 22 term model because only 11 of the 12 error terms can be solved for either forward or reverse mode 42 Six standards will be wanted to solve this 22 term model 42 As long as two separate error matrices are used for forward and reverse mode switch error is naturally removed as discussed in Section 3 4 3 6 Error adaptor for single step calibration Not only systematic errors but also on wafer parasitics can be described as a four port network On wafer parasitics are the probing pads and interconnect lines leading to the device terminals which actually connects the two ports at the two signal pads Port 1 and Port 2 to the two ports at the gate and drain of the desired CMOS transistor That essentially defines a four port network between the two probes and the two transistor terminals Fig 1 9 a and b show the two four port networks for systematic errors and on wafer parasitics The four port relations derived in Section 3 5 do not make any assumption about the properties of the four port network So the same equations can be applied on system error f
83. calculated from an approximate drain current function instead of a complete MOSFET model Here the numerical results are all calculated using the complete IIP3 expression in 8 5 and all of the derivatives are calculated using simulated I V data from a BSIM4 model 139 An inspection of 8 6 8 9 shows that A1 A As and A4 depend on Z and Y as well The load impedance will thus affect IP3 sweet spot when it dominates Z In this work IP3 is only examined for a 50 load due to its practical relevance and straightforward measurement When A A A3 A 4 0 the complete IP3 expression of 8 5 reduces to the first order IP3 of 8 3 First order IP3 does not scale as device size scales because the scaling factors of K3 and g are cancelled and 9C R is much smaller than 1 for the devices used Ai Ao As and A4 have quite different scaling factors as device size scales as shown in Section 8 4 8 3 Impact of the additional terms Instead of the zero Kse point in 8 3 IIP3 peaks at the point where the denominator of 8 5 is zero Fig 8 4 a shows the denominator in 8 5 versus V which is the sum of K3 g Ai Ao As and Ag while Fig 8 4 b shows K3 g Ai 2 As and A4 as a function of V individually V 0 8V The IP3 sweet spot from 8 5 0 327V is much lower than the zero K3 point 0 3754V A and A are the two largest terms that affect the shift of the IP3 sweet spot A3 and A4 have ver
84. ce CMOS technology examined The open capacitance the short inductance and the through delay are negligible because of the small dimension of the transistors The non ideality of on wafer load resistor can be modeled using a parasitic capacitor in parallel with a perfect resistor The experimental results in Chapter 6 indicate that single step four port calibrated results are practically identical to the two step four port calibrated results after switch error removal 20 1 3 5 Validity of BSIM4 model for nonlinear RF modeling The model parameters extracted from DC CV and S parameters are based on a small signal schematic and accurate for small signal modeling of transistors For transistor modeling at signals higher than certain value they do not represent the real transistor performance In general the linear model need to be verified using nonlinear simulation 8 The intermodulation linearity simulation accuracy of the BSIM4 model a widely used model for RF design is examined against measurement particularly in the moderate inversion region where a linearity sweet spot exists and can be utilized for high linearity RF circuit design 48 49 In BSIM4 the moderate inversion region is modeled by mathematical smoothing functions interpolating between physics based approximations in the weak and strong inversion regions instead of physics based surface potential approximation that can cover all levels of inversion Its accuracy in lin
85. configuration Under reverse mode the incident wave a the reflected wave 5 and the transmitted wave b are measured by a three receiver VNA or a four receiver VNA Fig 3 11 illustrates the signal flow graph for reverse mode operation using S parameters e represents the leakage path between the incident signal receiver a and the transmission receiver b I lumps the impact of non ideal switch or non ideal Z termination Similarly the a node can be removed using signal flow graph analysis and the signal flow graph in Fig 3 12 is equivalent to the signal flow graph in Fig 3 11 with 53 e el e e gj r 3 7 el eolo Directional Couplers Fig 3 11 Reverse mode signal flow graph for two port system including non ideal Zo termination Fig 3 12 Simplified reverse mode signal flow graph for two port system 54 3 4 3 12 term model Fig 3 13 redraws the signal flow graph for forward mode in Fig 3 9 Note that e and e in Fig 3 13 are not the same e and e that defined in 8 term model instead they are the e and e calculated in 3 6 which involve the impact of switch errors since separate error adaptors are used for forward and reverse mode This does not affect the error calibration procedures at all Based on signal flow graph analysis the measured wave ratios S and S are functions of the unknown S as 80 DUT ev si yA sour DUT DUT lI ejS ej
86. connections and different layouts is fabricated on the 90nm chip in Fig 2 2 b The measured S parameters are used for characterizing the effects of different gate patterns on small signal parameter extraction The chip in Fig 2 2 c contains an array of devices for intermodulation linearity characterization on 90nm CMOS technology The necessary de embedding standards are also included in Fig 2 2 b and c which are laid close to the transistor structures to avoid space variation 62 The small signal parameters for the equivalent circuit used to calculate IP3 can be extracted from the measured S parameters 27 E L wee Ore BEFETTET ETS AE 3 i occu 2 7 2 8 953 es emp ese Iz t C Li ELI E EE e 35e sc u is sty Get 20 BESLE E 9 6 9 5 c Iz s ts e Soc o c 4 ce e2 gt es csa ese 5 n asn 56 dd EE afe E a 3c jas ER SAE HOE 2 8 8 8 8 S LIES IEEE IEEE le em uum 34 9 6 2 099 ee es es e232 2 e 34 31 31 SSG S26 3 cm m wa 3 akataa Bis Jac See I L 2 1 3 0 8 8 8 83 I E S ee s t3 t ot 3 6 E5 zc 2 ce ee o2 ca cacar 5 Sc 25 3 c 3 c e an ataa e 37g afp 37c 3i gh jit aa as Gest ELE oe ES ES E3 C E et gee yee 2 0 c 2 ce 8 gt es ca e232 m c ic Uc CELEJ ee E 3 6 EA E 5 gc 3 c GJG DJG 2 0 8 8 O28 LCS LALA Oc O c 4 3 jcc o 2 ca ee 83 s ca ac i57 re 6 O20 ERIRIEIA ES catcac 3 3 13 3 1 ge Ne b 90nm CMOS c 90nm CMOS Fig 2 2 Chip pictures of t
87. ctions USER1 and USER2 Press the MENU key in VAS block select USER1 and USER2 The four parameters displayed on the screen are now 1 USER1 1 USER2 S12 and S22 185 Probe THRU standard on the Cascade ISS 101 190 substrate Press the MENU key in MENISIBEN block to bring the stimulus control menu onto the CRT LCD screen Select the MORE then SINGLE to make a single measurement Wait until the measurement is finished and HOLD is marked with underline 4 Export data as a CITI file Insert a floppy disk Press the DISK key in the BNUPSIBENISVTISNUN block Press STORE MORE DATA enter the name of the file DD ERR and then press STORE FILE 5 Example CITI file exported CITIFILE A 01 01 DATA S 1 2 DATA S 2 2 NA DUPLICAT NA VERSION HP8510XF 01 02 NAME RAW DATA NA REGISTER 6 VAR FREQ MAG 35 DATA USER 1 RI DATA USER 2 RI RI RI ES 0 NA ARB SEG 2000000000 70000000000 35 VAR LIST BEGIN 2000000000 4000000000 6000000000 8000000000 10000000000 12000000000 64000000000 66000000000 68000000000 70000000000 VAR LIST END COMMENT CONSTANT TIM BEGIN YEAR MONTH DAY HOUR MINUTE SECONDS E 2007 08 10 15 00 03 0 2 35986E0 1 20932E1 7 40478E0 3 54687E0 6 18872E0 6 42651E0 6 24414E0 1 01318E1 2 61523E1 9 20996E0 2 70185E1 1 02001E1 186
88. d Port 2 are wide and very short comparable to the pattern of gate fingers THRU standard can be considered as ideal THRU without delay and loss 2 3 1 Gate pattern and multiplier factor Fig 2 7 shows the layout for three NMOS transistors with the same gate length and total gate width but different gate patterns and multiplier factors M The three transistors have a double sided gate contact with M 1 b single sided gate contact with M 1 and c double sided gate contact with M 4 Note that the C look gate metal connection is used for double sided gate contact to balance the current flow at the two ends The transistor with single sided gate contact is directly connected to Port 1 using wide metal lines This set of layout is used to investigate the impact of the C look gate metal and the multiplier factor on the RF and noise performance 35 _ 5 C look Gate Single sided Gate Contact Fig 2 7 Layout for factors Double sided Gate Contact Substrate Ring Double sided Gate Contact WSS 1 c S C look Gate Metal 7 I n 2 ES DIIIS IIS ay Yy Lop A ML v A xr Substrate Ring tied with Source GY N i NMOS transistors with different gate patterns and multiplier The gate resistance R linear transconductance g cut off frequency fp and maximum oscillation frequency f are the critical p
89. d Technology NIST LRM LRRM calibration 77 78 12 a OPEN b SHORT c LOAD d THRU probes in air Fig 3 16 a OPEN b SHORT c LOAD and d THRU standards for SOLT calibration on Cascade ISS 101 190 A significant assumption of SOLT calibration is that the calibration standards must be well known In practice the internal routine of VNAs uses simple models defined by several coefficients for each standard 83 The coefficients of the four standards and the RF probes must be well defined in the VNA calibration kit for SOLT calibration The accuracy of calibration significantly depends on the accuracy of these coefficients Appendix E provides a table of the calibration coefficients for Cascade RF infinity probe with 100um pitch size and Cascade ISS 101 190 with 1 pico second delay VNAS8510C can store two CalKits in the system The Calibration coefficients can be loaded into VNA system from a floppy disk that came with calibration standards or manually entered into VNA following the steps in Appendix E The 12 error terms 59 determined from SOLT calibration can be saved as a CalSet Below are the headlines of a CalSet file CITIFILE A 01 01 NA VERSION HP8510C 07 16 NAME CAL SET NA REGISTER 5 VAR FREQ MAG 93 DATA E 1 RI DATA E 2 RI DATA E 3 RI DATA E 4 RI DATA E 5 RI DATA E 6 RI DATA E 7 RI DATA E 8 RI
90. d Y parameters Y is given by 14 1 y La Ly DUT open m d aod _ y DUT open a 4 7 Substituting 4 3 4 5 and 4 6 into 4 7 leads to a simple relationship between Y and Y 17 Yardy 4 3 4 8 75 1 Derivation details can be find in Appendix F Denoting A Y z Ne and B Y Yos 4 8 can be rewritten as y AY B 4 9 Or Y 4y BT 4 10 A and B are 2x2 matrices which relate to the Y parameters of the four port error adaptor through NR BE am det Y E Mam Savi Yn MENTRE RN det Y Lyin Mila ceu yon Yn Vans and yh are m n elements of the 2x2 matrices Y Y and Y m n 1 2 Expanding the matrices in 4 9 the elements of open short de embedded Y parameters are A A A A A A A A y E ay Y b zt AY 2 a Yb ae ay Y CAP ATED E ap Y b Es a Yzb c3 CRA Dy 4 13 A A A A A A A A ay Y b 22 a Yab P a Yaba E ay Yab Ay Y b n an Y b zd a Y b ly Ay Yodo a and b are i j elements of A and B i j 1 2 Y Instead of directly solving the 16 unknowns in Y Y Y and Y as was done in 20 only the 8 elements in A and B need to be solved after performing open short de embedding 17 Strictly speaking only 15 of the 16 unknowns can be solved due to the ratio nature of S parameter measurements similar to the situation in 16 term error calibration 41 80 For the same reason only 7 of the 8 unknowns in 4 and B can be 76 fully solv
91. d open Short de embedditig e eer eren ra nen eon eg nd 174 C3 Three step de embeddimp uoa ir oid eet echt ies ipto texit 176 C 4 Transmission line de embedding sse 178 APPENDIX D SWITCH ERROR REMOVAL eeeeeeeeeen eene enne nen nennen eren t eterne seen 182 D 1 Switch error removal equations eese eee ette tenete neenon tenus 182 D 2 Step by step guide to measure the switch errors sessssssss 184 APPENDIX E CALIBRATION KIT SETUP ccsessccscesccecsessssceeesecsceesesssaeceseceesesensnteaeeeeecs 188 APPENDIX F THE RELATIONSHIP BETWEEN OPEN SHORT AND FOUR PORT 192 APPENDIX G SINGULARITY OF LINEAR EQUATION SET sse 196 G 1 Typical calibration standards usse eee eoe eer ex i pb Pee eee ae uela duda 196 G 2 Singularity of on wafer standards 2 senti esee epe dct no qub ni rand eg 197 APPENDIX H ONE PORT ERROR CORRECTION c cessere eene nennen ennt nnne nen 201 H Error adaptor for one port system eese nennen tentent 202 H 2 Relationship between I and LP uus 203 H 3 A generalized interpretationis wai ete cedem dadas 204 APPENDIX I DERIVATION OF FIRST ORDER INPUT IP3 sese 207 APPENDIX J DERIVATION OF INPUT IP3 BASED ON VOLTERRA SERIES 210 J 1 FEirstorderkernels utto dit ena eise 211 J 2 Second order kernel s 0cccccccccccsessssscsscsccesssssesssssssccsessecssssssssssceveeesesseaees
92. de and 90nm long For N 64 the total width is 128um which is close to those found in 5GHz low power 90nm CMOS LNAs 49 Therefore the analysis will be focused on this device size In practice because of low gain and low levels of intermodulation products in small width transistors as well as dynamic range limits of the spectrum analyzer the minimum gate width that IP3 can be measured reliably is 10x2um for this 90nm CMOS technology IIP3 OIP3 and power gain are measured at different Ves Vps and fundamental frequencies to examine the biasing and frequency dependence of IP3 sweet spot For each measurement the power amplitude at the signal generators Pin is swept and the 120 output power level for the 1 order output and the 3 order intermodulation product are monitored Pout 1st and Pour3ra After power calibration the third order intercept point is obtained using linear extrapolation illustrated in Section 1 2 P 25dBm 7 2 DC and linear characteristics Fig 7 3 shows J V curves for V 0 6 0 8 and 1 0V and Fig 7 4 shows 71 Vj curves for V 0 4 and 0 8V Fig 7 5 a shows S2 versus frequency at one fixed biasing point V 0 4V and Vps 1 0V while Fig 7 5 b shows S versus gate biasing voltage at a fixed frequency 5GHz Fig 7 6 compares the cut off frequency fr extracted from S parameters versus gate voltage Fig 7 7 shows all Y parameters versus frequency at V 0 4V and V
93. e de embedded results Although the set of standards can be any non singular combination of five standards the same OPEN SHORT LEFT RIGHT and THRU standards as used in analytical solution is used for comparison Chapter 6 demonstrates the application of the two four port solutions in Chapter 4 and Chapter 5 on single step calibration Another topic that draws the attention of circuit designers is the linearity nonlinearity of the transistors which determines upper limit of the spurious dynamic range of transistors or circuits Chapter 7 evaluates the BSIM4 model for a 90nm RF CMOS technology which is later used to generate the I V and small signal parameters needed to calculate IP3 analytically Chapter 8 develops a valuable analytical IP3 expression for MOS transistor nonlinearity modeling The expression is developed based on Volterra series theory using simulated I V and S parameters Biasing channel width and frequency dependence of IP3 are well understood using this analytical expression Chapter 9 compares the calculated IP3 with experimental IP3 for the 90nm RF CMOS technology Guidelines for optimizing high linearity applications are given based on experimental results and calculated IP3 24 CHAPTER 2 ON WAFER TEST STRUCTURE Since a pair of Cascade infinity probes are used to contact the on wafer test structure there are several layout rules regarding probe pad placement and sizing that must be followed 55 Typical contact
94. e frequencies for N 10 W 20um Analytical IIP3 without C is calculated using 8 5 156 9 2 4 Large signal linearity The solid lines in Fig 9 8 represents the typical fundamental frequency output power Pout st and the third order intermodulation IM3 output power Pout3ra versus input power Pin curves for a moderate inversion gate bias By observing the two curves an unexpected minimum IM3 output power point at certain input power level is investigated A better output signal power to distortion ratio can be achieved by selecting this Pin level as the circuits working point 23 This large signal IM3 sweet spot is not defined for small signal operation and cannot be evaluated using the extrapolated IP3 point Note that instead of a gain compression at certain input power as shown in Fig 1 7 the output signal first linearly follows the input power then it experiences a faster rate of rise before it saturates This phenomena is named as gain expansion and can be observed sometimes 23 N 64 W 2um L 100nm 0 f T T Ves 0 3V Vos 0 8V a f0 SGHz Af 100KHZz ATIN 0dB e Pout dBm 60 Yf x large signal sweet spot P out 3rd P nd l 90 L li L 30 20 10 0 5 Pin dBm Fig 9 8 The output power amplitude for fundamental and 3 order intermodulation products versus input power 157 Fig 9 9 shows
95. e results with d a M M The other unknowns are all determined based on the same principle as shown in 4 19 and 4 20 A and B can be rewritten using 4 19 4 20 and A A Gy a as N l m 1 Mj My A 4M 35 B N Ny 4 25 A EU SENE M 11 is the only unknown left which relates the unknowns solved from the open short de embedded LEFT and RIGHT and can be solved using the THRU standard 8l 4 port de embedded result with a a M 2294 0 11 noisy and less accurate result 4 57 0 1 9M ht o SUD Ed ir Te DP S 0 07 4 port de embedded result with Nasua a5 847 MM l Sus 0 20 40 60 80 100 120 frequency GHz Fig 4 3 The real part of four port de embedded y using different a a choices The a a defined from M M is clearly nosier and should not be used The open short de embedded Y parameters of THRU Y can be calculated by substituting Y in 4 14 into Y 4y B as yo _ oy ai a bi b a a biz b 4 26 24 dy By b a a b b By taking ratios of the elements of Y the equations including A can be constructed as OS thru OS thru d a M M 2 a s m A E al gt 4 27 Yu Jio a a 1 ANS No B yt y Dy tb M Ny A 4 28 OS thu OS thru Ju X b tb M N 4 82 2 OS th OS th OS th OS th Therefore we
96. earity simulation particularly in moderate inversion therefore needs to be experimentally evaluated as linearity simulation requires not only accurate modeling of the first order I V relations but also higher order derivatives Note that we do not address simulation of harmonic or intermodulation distortion at V 0V a known problem for BSIMA 50 1 3 6 Third order intercept point modeling The nonlinear performance of transistors is typically measured by the 1dB compression point and the third order intercept point IP3 Using either measured or simulated I V data IP3 sweet spot biasing current can be determined from zero K3z point based on first order IP3 theory 11 51 Circuits have been published to utilize 21 this zero Ke point for high linearity LNA designs 48 52 However experimental IP3 results indicate that the actual IP3 sweet spot V is lower than the zero K3e Vos by a noticeable amount as already shown in Fig 1 8 53 More accurate analytical IP3 expressions for CMOS devices involving more nonlinearities have been developed recently 22 25 26 The complete IP3 expression developed in this dissertation considers not only transconductance nonlinearities but also output conductance nonlinearities and cross terms This expression is used to quantify the impact of these nonlinearities and explain the biasing device size and frequency dependence of IP3 Furthermore guidelines for optimal biasing and s
97. ed which is sufficient for de embedding purpose 19 Three additional on wafer standards LEFT RIGHT and THRU are used in this dissertation to find out the 8 7 solvable unknowns left after open short de embedding 4 2 2 Open short de embedded LEFT RIGHT and THRU We now examine the three additional standards LEFT RIGHT and THRU as illustrated in Fig 4 2 d f The Y parameters for actual LEFT RIGHT and THRU standards are modeled by y zx Y 0 y Aright 0 0 RS iiu Y h 4 14 0 0 0 Yk e E T T Note that the on wafer load resistor in LEFT and RIGHT which are assumed to be purely resistive in 20 and 19 are represented as Y and Y to account for non idealities of on wafer resistors The primary non ideality is a parallel capacitance as shown by their open short de embedded Y parameters at relatively low frequencies where open short is accurate Thus Y and Y are modeled as Y G joC and Y G joC as shown in Fig 4 2 d and e The admittance and parasitic capacitance G G C and C are extracted from open short de embedded LEFT and RIGHT below 30 GHz If high precision low parasitics resistors are used which are increasingly available in RF SiGe BiCMOS and RF CMOS processes one may determine G and G from DC measurements and neglect C and C The Y in Y becomes infinity for an ideal through line with zero length A small length THRU is typically used in transistor measurement to
98. ee oc bes ERROR Qd inas 135 8 2 1 Two dimension nonlinear current source 136 8 2 2 Input IPS expressION eese De tiroteo tue m e ei ett aig mi duds 138 8 3 Impact of the additional terms essssssssssseeeeeenen 140 84 Device widthascalings uides pi ib IN DA Ud PATE vet cn xb MU Ma 142 8 5 DIBESGI Tee en e cata Eb btc dei teet eed tetuer LIS oM RUE 144 8 6 SS ULIMIT ATW GN RM AS HUNE EN UR 147 CHAPTER 9 CHARACTERIZATION OF RF INTERMODULATION LINEARITY 149 9 Power gain measure melle tisch eite dtr eb e Shae rd oy 150 92 Linearity Characteristics o estie o or ea diebus i eade 151 9 2 1 Drain voltage depenuenbe eoo estos Rare ne nen et a e de HEY Ra 151 92 2 Finger number dependence s eed eaae piii etd e EUN 153 92 3 Frequency dependence i es t e ete ede nea tete es 154 9 2 4 Large signal linearity aiunt bets marte id No xt aT RENS 157 9 3 SUMMAY eee Ac e UE UNT E CLAN pepe ou ECL Le 158 BIBLIOGRAPHY 2h tra aset diese m niii telas eb eot Stile feto ise 160 APPENDICES APPENDIX A ABBREVIATIONS AND SYMBOLS eee nere en entere enne 168 AG Abbreviations cutter tees te eee h tet ores sce bed dose 168 A 2 Matrix symbols and matrix index sessssssseeeeeeeenn 168 APPENDIX B TWO PORT NETWORK REPRESENTATIONS eene eene ener 170 APPENDIX C REVIEW OF ON WAFER DE EMBEDDING METHODS een 172 C 1 OpensShorcde embedding oua o Veces ec ttu HN idend ed 172 2 Pa
99. em involving a four receiver VNA and an unknown two port The two bias tees are assumed to be ideal for AC signals and thus not included In Section 3 2 it will be shown that the errors introduced by the bias tees are actually included in the four port error adapter A dual reflectometer is attached to the input of the unknown two port DUT and another one is attached to the output Thus the VNA has four receivers two at each port to capture the incident and reflected waves at each port A switch changes the direction of the incident power to the unknown DUT for forward and reverse measurements and terminates the unknown DUT at an impedance Z The four S parameters exported by 45 the VNA are actually the ratios of the incident and reflected waves monitored by the two dual reflectometer S b a and S b a are calculated when the switch is at forward position as a is the incident signal and b and b are the reflected waves S b a and S b a are calculated when the switch is at reverse position as a is now the incident signal D pd Porti Dual Reflectometer Switch X X Pota 5 a b 3 3 Fig 3 2 Atwo port VNA system with four receivers If Z is a perfect matched load and the switch is ideal the waves and the S parameters can be related through b Sa 8 24 3 1 b 34 5 Under forward mode a 0 the equation reduces to b S a and b S a Under reverse mode a
100. ematically Fig 1 9 a illustrates the four port network for system errors with two ports inside VNA and two ports at probe tips which was described as 16 term or 15 term error model frequently 36 38 39 41 42 43 Fig 1 9 b shows the four port network for on wafer parasitics with two ports at probe tips and two ports at device terminals e g gate and drain for MOS transistors 20 Note that all of the a waves are incident waves which entering the four port network at each port while all of the b waves are reflected waves which leaving the four port network at each port Therefore the S parameters of the four port networks in Fig 1 9 can be easily defined using the a and b waves Analytical solutions of the four port parasitic network were developed in 19 17 20 and 44 using three four and five on wafer standards with varying degree of assumptions For example with reciprocal assumption the number of unknowns is reduced to ten and only four on wafer standards are necessary 45 With 16 reciprocal and symmetric assumptions the number of unknowns is reduced to six and only three on wafer standards are necessary 17 Port 0 Port 1 Port 1 Port 1 VNA Probe Probe Gate gt b 4 port a on wafer rsa a 4 parasitics a b b b Port 3 Pot2 Port2 Port 2 VNA Probe Probe Drain a b Fig 1 9 a The four port network for systematic errors
101. en frequency GHz Fig 5 6 Comparison of Y parameters between solution and SVD based 8 term solution 105 frequency GHz open short SVD based 16 term 5 5 Summary On wafer parasitics de embedding using a SVD based numerical four port solution is demonstrated on a 0 13um RF CMOS process The SVD four port results are shown to be close to the analytical four port results in Section 4 2 Redundancy and singularities are naturally handled by SVD The leakage errors are much smaller than the directivity errors frequency response errors and port match errors 8 term error model is sufficient for on wafer parasitics de embedding Three standards are necessary for solving the 8 term error matrix Non singular standards must be carefully designed The condition number of the coefficient matrix can be used as an indicator of the singularity of the sets of standards and thus the validity of the de embedded results 106 CHAPTER 6 SINGLE STEP CALIBRATION As discussed in Section 3 6 both system errors and on wafer parasitics can be described as a four port network A significant difference between the four port system error adaptor and the four port on wafer parasitics network is that system errors drift over time and for this reason ISS calibration must be performed at least once a day and validated often e g before measurement of each wafer lot This inevitably requires an op
102. ence The closeness is expected as open short is valid below 30 GHz The C extracted from open short gives a very strong and unphysical frequency dependence while the C extracted from general four port is almost frequency independent no matter C and C are included or not In strong inversion for an oxide 85 thickness of only a few nanometers the effective gate capacitance is expected to be approximately constant even at 100 GHz for a MOSFET of such short channel length Fig 4 5 Rin 4 port without C amp c 99 ESSR 0 Eee Med ES reasetavandntau sa ed antran aaaunpaonasn oou R 30 S C 210fF 0 20 40 60 80 100 120 frequency GHz Effective gate resistance and capacitance extracted from four port de embedded results with and without parasitic capacitance included in LEFT and RIGHT Open short de embedded results are also shown for comparison No reciprocal assumptions are made 4 2 6 Quantifying errors of open short By examining the elements in A and B the errors remaining after open short can be quantified because Y 4 Y B Clearly only when A and B are both identity matrices open short will be the same as four port i e Y Y The deviation of A and B from identity matrix is thus an indicator of the in validity of open short Fig 4 6 plots the real and imaginary parts of the 8 elements in A and B At low frequencies a
103. ension is to scale Fig 2 4 shows the cross section view of three cuts along the test structure in Fig 2 a The maximum pad height variation in a row of pads contacted by one GSG probe is 0 5um To avoid pad height variation the top metal layer for all ground pads and signal pads are the same To support the overtravel of probe tips while probing the pads are built using multiple metal layers since even the thickest metal layer is less than 29 10um thick Fig 2 4 a is just a copy of Fig 2 1 a with three cut lines for the cross sections in Fig 2 4 b d The cross section of the GSG pads is shown in Fig 2 4 b The ground pad is built using all metal layers and the signal pad is built using the top two thick metal layers The number of metal layers used for signal pads depends on the number of layers available and the metal layer thickness The ground pads are all tied to the same metal ground plane built using the first metal layer to provide an as ideal as possible connection between the four ground pads The metal ground plane exceeds the dimension of the signal pad by a size comparable to the total thickness of all metal layers to provide good electromagnetic isolation from the silicon substrate 58 57 A large number of substrate contacts are scattered over the wafer to provide good substrate connection and meet the requirement of doping and active area density Fig 2 4 c shows the cross section of the cut along the m
104. eory and Techniques vol 53 no 2 pp 723 729 2005 X Jin J J Ou C H Chen et al An effective gate resistance model for CMOS RF and noise modeling in Dig Int Electron Device Meeting pp 961 964 1998 X Wei K Xia G Niu et al An Improved On chip 4 Port Parasitics De embedding Method with Application to RF CMOS in Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems pp 24 27 2007 Q Liang J D Cressler G Niu et al A simple four port parasitic deembedding methodology for high frequency scattering parameter and noise characterization of SiGe HBTs IEEE Trans Microwave Theory and Techniques vol 51 no 11 pp 2165 2174 2003 S A Wartenberg Selected topics in RF coplanar probing IEEE Trans Microwave Theory and Techniques vol 51 no 4 pp 1413 1421 2003 G Niu J Pan X Wei et al Intermodulation linearity characteristics of CMOS transistors in a 0 13um process in Dig of IEEE Radio Frequency Integrated Circuits Symp pp 65 68 2005 N B De Carvalho and J C Pedro Large and small signal IMD behavior of microwave power amplifiers JEEE Trans Microwave Theory and Techniques vol 47 no 12 pp 2364 2374 1999 P Wambacq and W Sansen Distortion Analysis of Analog Integrated Circuits Kluwer Academic Publisher 2001 161 25 26 27 28 29 30 31 32 33 34 35 36 S Kang B Choi and B Kim
105. ependence of measured IIP3 154 For small devices C C and C are small and thus the terms containing these capacitances are relatively small For frequencies below 10GHz the IIP3 calculated are practically the same for different frequencies Fig 9 7 shows IIP3 calculated using 8 5 and Volterra series with C for N 10 at 2 5 and 10GHz The results are overlapped W 2um L 90nm Af 100KHz 20 i f0 2GHz f0 5GHz i 0 10GHz I li I I I I I IIP3 dBm Fig 9 5 Measured IIP3 versus J at multiple frequencies for N 10 and 64 W 20um and 128m 155 N 64 W 2um L 100nm V ps7 0 8V Af 100KHz 18 N 764 d Analitical IP3 without C a E Bp A A e ase sees T EA A IAI EEE a f 2 D ce a 0 HI c M QU EON EMI peg MAN Phe eta OS f0 2GHz 5 f0 5GHz com f0 10GHz IIP3 dBm 0 200 400 600 Jps uA um Fig 9 6 Analytical IIP3 a without C and b with C at multiple frequencies for N 64 W 128um Analytical IIP3 without C is calculated using 8 5 N 710 W 2um L 100nm Vpg70 8V Af 100KHz 20 Symbol Analitical IP3 without Cou N 10 Line Analitical IP3 with Cou E 10 Pt mm Kk e Lt f0 2GHz 0 IX un ARE es ees f0 5GHz __ oo e 1 0 200 400 600 Jog AM um Fig 9 7 Analytical IIP3 with and without C at multipl
106. equency dependence of the effective gate capacitance In strong inversion for an oxide thickness of only a few nanometers the value of the effective gate capacitance 1s expected to be approximately constant even at 100GHz for a MOSFET of such short channel length Open Short 6l mara ___ J Pad Open Short g i Do eee 4 port SVD solution E 4X MES ae 4 port analytical solution wz i T Dm 2L ico do Pausen vctus Neuen d 0 1 1 1 1 1 0 20 40 60 80 100 400 l l i 4L E 300 Jenseni E ul ead pases o lt 200 pr TT UM ie een a rii PUE TTT ey exe 100 1 1 1 1 0 20 40 60 80 100 frequency GHz Fig 5 3 Comparison of effective gate resistance and capacitance between open short pad open short SVD based four port solution and analytical four port solution 99 5 4 Reduction of Error Terms and Number of Standards Using SVD the relevant importance of different error terms can be examined efficiently For both the parasitics four port and the combined four port used in single step calibration only 12 terms of the full 16 terms are important as shown below This reduces the number of standards from 5 to 4 SHORT LEFT RIGHT and THRU are a good combination needed for the final 7 solution One may then omit the OPEN structure The saving in chip area is not significant and it does not allow the use of open short de embedding at lower frequenci
107. er VNA and four receiver VNA for two port measurement The three receiver VNA has one reference receiver for detecting the incident signal and two measurement receivers one at each port The corresponding error model is a 12 term error model 6 for forward direction 6 for reverse direction 67 68 For double reflectometer VNA with four receivers a 8 term error model was introduced and solved in S parameters and T parameters 69 70 71 The leakage terms can be added to the to the 8 term error model one for each measurement direction increasing the number of error coefficients to 10 72 Both the 8 10 term model and the 12 term models are used for four receiver VNA which even have their calibration procedures embedded in modern VNAs The error models and their corresponding calibration techniques are compared in 73 74 68 75 If required several techniques with different conversion 42 equations can be used to convert the 12 term model into a 8 10 term model 75 76 These equations are slightly different but are based on the same physical principle One may also apply the 8 10 term model for the three receiver VNA with an assumption that the source match equals the load match of the test set which holds only in the case of an ideal switch For a real system this may lead to intolerable measurement inaccuracy Only the 12 term model guarantees the entire description of three receiver VNA 34 The reasons will be detailed
108. erator to load a special ISS holder on the wafer prober making measurement time consuming and impossible to automate in production testing A solution to this problem is to combine the four port system error adaptor and the four port on wafer parasitics into one four port network and directly solve the combined four port network without ISS calibration using the same on wafer standards previously used for on wafer four port parasitics de embedding In practice this single step approach is rarely used particularly for transistor measurements for various reasons the most important being that on wafer standards are less accurately known compared to precision ISS calibration standards In this work we will compare the results from the two step approach i e ISS calibration plus four port on wafer parasitics de embedding and the results from the single step approach to quantify the errors introduced in the much simpler and easier to automate single step approach on a 0 13um RF CMOS process This is facilitated for two four port de embedding approaches the analytical four port solution in Section 4 2 107 and the numerical four port solution in Section 5 2 We will show that the single step approach can give as accurate transistor Y parameters as two step calibration from 2GHz to 110GHz However switch errors must be removed first since switch errors are not involved in the four port network Switch errors are introduced by non ideal Z or
109. erefore the deviation of IP3 sweet spot from zero Ke point is the largest and IP3 sweet spot J is the lowest for the largest device In the 90nm CMOS technology used the sweet spot Jp decreases from 40 to 20uA um as gate width increases from 2 to 128 um For large devices of interest to RFIC design simulation using a good model and measurement of IP3 must be used to accurately identify the sweet spot biasing current density Simulation results without AV DIBL indicate that the Vp dependence of IP3 sweet spot V is dominated by the threshold voltage shift caused by DIBL effect 148 CHAPTER 9 CHARACTERIZATION OF RF INTERMODULATION LINEARITY After developing the complete IP3 expression in Section 8 2 IP3 sweet spot of single transistor and simple circuits can be estimated using measured I V and S parameters of single transistor instead of two tone intermodulation measurement However because of the I V data measured using Agilent 4155 only has 5 digits which is not sufficient to provide smooth 2 and 3 order nonlinearity coefficients in Table 8 1 the calculated IP3 are all from simulated I V and S parameters using the BSIMA model examined in Chapter 7 The same set of equations can be applied on measured I V and S parameters once the measured data has enough digits This chapter compares the measured and calculated IP3 results for a 90nm RF CMOS technology The complete IP3 expression developed in Section 8 2 is used I V
110. es for extraction of capacitive parasitics of the left and right loads Having open short can be useful as this serves as the reference from traditional on wafer de embedding and open short is known to be accurate at lower frequencies when used with ISS calibration Comparison with open short can prove useful at the algorithm development stage as consistency of four port with open short at low frequencies indicates a correct four port solution 5 4 1 Quantify error terms for four port on wafer parasitics To quantify the impact of the 16 error terms the SVD solved T parameters are transferred to S parameters since S parameters give straightforward physical meanings of the signal paths Because the solved T terms are normalized the relationship between the normalized T terms and the S parameters of the four port network need to be developed first Using the relationship between the E and T elements in 3 30 the E elements calculated from the normalized T elements are 100 5 8 E E E E represent the four port network after normalization The S parameters of the four port network without normalization is E E Eoo 1 hPa 39 3 3 y E 1 TEL A BR A eo g p e z 5 9 Although E E E and E are no longer the original S parameters of the four port network it does not affect the relative importance of the error terms Fig 5 4 shows the mag
111. esults are similar to open short results and thus not repeated here Similar to the single step calibration using analytical four port solution the Y parameters from single step SVD four port are noisier than the Y parameters from two step SVD four port To summarize single step calibration using four port techniques has led to reasonably accurate transistor Y parameters despite the less accurate on wafer standards compared to precision ISS standards The ability to avoid ISS calibration makes this attractive for production testing as ISS calibration needs to be performed and checked often and involves a separate manual step of loading ISS holder 111 ISS Calibration Open Short ISS Calibration 4 port SVD 0 2 lt Single step 4 port SVD T EE gt 04 00 50 100 0 50 1 frequency GHz frequency GHz Fig 6 3 Comparison between two step open short and four port on wafer parasitics de embedding results with ISS calibration and single step four port calibration results without any ISS calibration Another advantage of using single step calibration is that the distributive nature of on wafer parasitics is naturally included as evidenced by the closeness of the single step results to the two step results Above 50GHz the open short results are much less accurate simply because the lumped equivalent circuit used for open short de embedding f
112. ete IP3 expression is developed using Volterra series analysis and nonlinear current source method The investigation indicates that not only the 2 and 3 order nonlinear output conductance but also the cross terms are important for IP3 sweet spot and high Vas IP3 modeling Guidelines to identify the IP3 sweet spot for large devices used in RFIC designs are provided vi ACKNOWLEDGEMENTS I would like to express my gratitude to me supervisor Dr Guofu Niu Without him this dissertation would not have been possible His patience and encouragement carried me on through difficult times I appreciate his vast knowledge and skill in many areas and his valuable feedback that greatly contributed to this dissertation I would like to thank the other members of my committee Dr Foster Dai Dr Stuart M Wentworth and Dr Richard C Jaeger for the assistance they provided Several people deserve special recognition for their contributions to this work I would like to thank Qingqing Liang for his help with de embedding techniques I would like to thank Ying Li for her help with device measurement I would like to thank Susan Sweeney of IBM Microelectronics for her help with 110GHz S parameter measurement and noise measurement I would like to thank Dr Stewart S Taylor of Intel Corporation for discussions on device and circuit characterization Finally I am forever indebted to my parents for the support they provided me through my entire life In
113. fer as the desired device The same probing pads and interconnections are shared by the desired device and the on wafer standards to keep the reference plane consistent Since systematic errors and on wafer parasitics are removed in two steps this approach is identified as two step calibration in the dissertation Open short developed in 1991 lumps on wafer parasitics as three shunt and three series elements which is still the industrial standard on wafer de embedding technique until now Fig 1 4 a shows the equivalent circuit for open short Two on wafer standards an OPEN and a SHORT are necessary to remove the six lumped elements 14 Fig 1 4 b and c give the equivalent circuits for two alternatives to open short three step and pad open short which make different assumptions of on wafer parallel parasitics Open short assumes that the large probing pads are the only source of parallel parasitics and thus the three shunt elements are representing the parasitics at the pads 14 Three step also lumps the parallel parasitics as three shunt elements but the third one is between the two series elements instead of the two parallel elements 15 16 This assumes that the parasitics between the two pads can be ignored while the parasitics between the ends of the two interconnect lines are considerable because of the smaller distance between the two ends when compared with the distance between the two pads Four on wafer standards an OP
114. for a LEFT or a RIGHT measurement Using the relationship between the elements of M and N and the unknowns in A and B some of the unknowns can be solved first To make the solution easier and clearer A and B are normalized to A and B using A kA B k B by a constant k As we still have Y A Y B and Y 4 yes B we can replace A and B by A and B respectively for de embedding purpose The normalization factor k is chosen based on multiple considerations First it must not affect the accuracy of the de embedded results Second the errors remaining after open short can be easily examined from the elements of the normalized matrices Third it will reduce to unity if the four port network is reciprocal A choice satisfying these requirements is k 2 Jb a 1 a A eA UB aA ab and 4 17 21 a a a 1 B k B Ja 5 B a b E a 4 18 aba auba After normalization there are only 7 elements that need to be solved in A and B We first solve as many terms of A and B as possible from M and N using 4 15 and 4 16 a M a b 7 Mj aj b M and NS UE 4 19 7 n 79 a a a N a m 11 X 11 12 12 22 Bio ES Nai gt Biss NA Na and N M a az au 22 au 4 20 6 of the 7 elements are now solved as functions of the 7 a a which we define as Aula For a given set of measured data a a can be calculated in two ways either as M M or as M M from 4 15 The analysis bel
115. he SVD based solution in Section 6 2 may give some information of the ripples 109 Two step 4 port with SOLT calibration 0 05 Single step 4 port calibration frequency GHz frequency GHz a Fig 6 1 Single step versus two step four port using the analytical four port solution with data measured using a HP 8510XF system from 2 GHz to 110 GHz Two step 4 port with SOLT calibration 0 01 Single step 4 port calibration 0 02 frequency GHz b frequency GHz Fig 6 2 Single step versus two step four port using the analytical four port solution with data measured using a HP 8510C system from 2 GHz to 26 5 GHz 110 6 2 Numerical four port single step calibration The same four port SVD algorithm in Section 5 2 is applied on the raw S parameters without ISS calibration to remove the combined four port network including both system errors and on wafer parasitics S in 5 1 and 5 7 is replaced by S Again the on wafer standards are all assumed to be ideal e g ideal open and short relatively ideal resistor loads with a capacitive parasitics Fig 6 3 compares the single step SVD four port results with the two step SVD four port results Also shown are the open short results with ISS calibration the most popular practice today The pad open short r
116. he fabricated transistor structures on three RF CMOS technologies b and c are fabricated at different foundries 2 2 Probing pad design considerations Fig 2 3 illustrates the cross section of a modern RF CMOS technology It starts with a silicon substrate which is normally lightly p type doped Active devices including diodes bipolar transistors and CMOS transistors and some of the passive devices like poly resistors are built on the very surface of the silicon substrate using doped materials 1 4 thin metal layers about 30nm thick either aluminum or copper will be used for connections close to device terminals These connections are thin and narrow which can only handle low current and has a higher resistance Besides the first metal layer is usually used as a metal ground plane under the probing pads and the interconnections to prevent the signal paths from coupling to the substrate 58 63 2 4 thick metal layers about 50nm thick with low sheet resistance will be used for long 28 and high current connection The RF layer normally composing two thick aluminum metal layers several micron thick is used to build the probing pads A passivation layer is used to protect the whole structure and opening must be made on top of the probing pads Pad opening EOI JH EJS UIYL e e _ EJ9IN YOU L eue gd PUNOIN e3e N ansans IG Fig 2 3 Cross section view of an advanced RF CMOS technology The dim
117. iddle between Port 1 and Port 2 pads which shows that the connections between opposing ground pads Port 1 to Port 2 side are built using all available metal layers This helps to provide an ideal and unified ground connection The source is tied to the substrate ring locally while the substrate ring is connected to the metal ground plane using short and wide metal lines The grounded substrate ring can isolate the transistor from adjacent structures Fig 2 4 d is along a cut across the signal pads at Port 1 and Port 2 Not only the signal pads but also the interconnect lines to the transistor terminals are built using more than one metal layer This will evidently reduce series parasitics of the leads and increase the accuracy of the SHORT standard but introduce coupling to the ground shield thereby increase the loss In general it is safe to apply at least a few of the metal layers 57 30 Cut 1 a i Ground shield Source amp Substrate Ring tied extension c Cut 2 to metal ground plane Metal on drain finger Substrate Ring Fig 2 4 The cross section view of GSG pads and MOS transistor along three cuts 31 2 3 CMOS transistor design considerations Fig 2 5 gives the layout of a MOS transistor with 10 gate fingers Each finger has a channel length of 0 13um and a channel width of 5um with double sided gate contact This leads to a C look gate metal connection to Port 1 Port 2 is connected to the d
118. ig J 3 The equivalent circuit for solving the second order kernels 213 J 3 Third order kernels Similarly the third order kernels are calculated using the equivalent circuit shown in Fig J 4 inz3 is the third order virtual nonlinear current source Denoting the third order kernels at node 1 and 2 as H3 51552353 and H EUN these transfer functions can be solved from Y s 5 5 0 rl 0 1 11 Zn Y s s s AETA INL3 iNL3 is determined by the third order coefficients in J 1 and the first and second order kernels of their corresponding controlling voltages iNL3 K3z H1 s i s Hr s eS Kae ni s ra sss tr stra sess tr s 2 sss eK ni s ims mas 5 Kos ers s tros S208 tr ss ros sos tr stro ss 1 Hi s H2 s 5 Hi s H2 s 5 Hi s H2 s 5 TIK2s 2 3 H1 s Ha s 8 Hu s H2 s 8 Hi s H2 s 85 Hi s ri s eri s3 ex Koreys m s mn s n s eH s Hi s Hs s J 12 Hi s m s H1 s ex Kanon H sss s iss TH s H1 s m s Solving J 11 gives the third order kernels at node 1 and 2 as 214 7 13 J 14 Fig J 4 The equivalent circuit for solving the third order kernels J 4 Input IP3 For a nonlinear system described using Volterra kernels the amplitude of the fundamental output product is VH L ja or Vp jo and the amplitude of the 3 order i
119. imulation for multiple V N 64 With Vps increasing from 0 6 to 1 0V 7 increases only slightly but IIP3 increases by a much larger factor particularly at higher V when the device is biased closer to linear operation region And the IP3 sweet spot V decreases as Vps increases The V dependence of IP3 sweet spot is determined by the threshold voltage change due to DIBL which will be verified using simulation results with and without DIBL induced V change in Section 8 5 N 64 W 2um L 90nm f0 5GHz Af 100KHz 10 m me D Sym bol Measurement Line Simulation IIP3 dBm e Vos 0 6 0 8 1 0V 10 0 2 0 4 0 6 0 8 1 Fig 7 11 Measured and simulated IIP3 versus V at multiple Vps Fig 7 12 shows IIP3 from measurement and simulation versus J for N 10 20 and 64 The peak of measured IIP3 is not perfect because IP3 is not measured in a very fine biasing step Linearity simulation can predict IP3 sweet spot accurately for devices with N 10 20 and 64 Note that the sweet spot J decreases from 35uA um for 128 N 10 to 20uA um for N 64 Note that the zero Kse point is marked as it is the IP3 sweet spot estimated using first order IP3 theory The zero K3e points for the three transistors are practically the same since the devices scale well So just the zero Ks point for N 64 is shown in Fig 7 12 The deviation between the actual IP3 sweet spot and the zero
120. ion 1987 D A Frickey Conversions between S Z Y H ABCD and T parameters which are valid for complex source and load impedances IEEE Trans Microwave Theory and Techniques vol 42 no 2 pp 205 211 1994 G A Forsythe Computer Methods for Mathmatical Computations Englewood Cliffs NJ Prentice Hall 1977 L Seung Yup J Kye Ik L Yong Sub et al The IMD sweet spots varied with gate bias voltages and input powers in RF LDMOS power amplifiers in Proc 33rd European Microwave Conf pp 1353 1356 Vol 3 2003 167 APPENDIX A ABBREVIATIONS AND SYMBOLS A l Abbreviations DUT device under test Everything probed by the probes is a DUT GSG ground signal ground IM3 third order intermodulation IP3 third order intercept point IIP3 input IP3 and OIP3 output IP3 ISS impedance standard substrate PSA performance spectrum analyzer PSG performance signal generator SOLT short open load thru SVD singular value decomposition TRL thru reflection line VNA vector network analyzer A 2 Matrix symbols and matrix index Y Y parameters of LEFT after open short de embedding y95 7 Y parameters of RIGHT after open short de embedding S Measured S parameter without switch errors 168 S S parameter of the whole on wafer test structure being probed S The actual S parameter of the desired two port Comments 1 If Q is a two dimension matrix Q or q is the m n ele
121. ion in 17 showed that the parasitic capacitance associated with this load resistor can affect the de embedding results for on wafer inductor measurements In this solution we first determine the parasitic capacitance of the load resistor using low frequency open short de embedding e g below 30 GHz and then include its effect in four port de embedding procedures The relationship between open short de embedding and four port de embedding derived in 17 is further examined using two matrices of the general four port solution which reduce to identity matrices at low frequencies where open short is valid New criteria for examining reciprocity and symmetry of the solved four port network are developed Using a reciprocal and symmetric solution four port de embedding and pad open short de embedding were previously shown to be close for inductors and pad open short was concluded to be superior to four port due to better tolerance to parasitic capacitance in 17 We examine this issue for transistor measurements and show that these conclusions cannot be generalized at least to this experiment Instead pad open short gives inaccurate results at high frequencies that are close to open short This chapter details the derivation of an analytical four port solution for on wafer parasitics using Y parameters With five on wafer standards OPEN SHORT LEFT RIGHT and THRU the 16 error terms in Y format can be determined Experimental results are prese
122. iques vol 40 no 11 pp 2013 2024 1992 K J Silvonen Calibration of 16 term error model Electronics Lett vol 29 no 17 pp 1544 1545 1993 H Heuermann and B Schiek Results of network analyzer measurements with leakage errors corrected with direct calibration techniques IEEE Trans Instrumentation and Measurement vol 46 no 5 pp 1120 1127 1997 H Heuermann and B Schiek 15 term self calibration methods for the error correction of on wafer measurements JEEE Trans Instrumentation and Measurement vol 46 no 5 pp 1105 1110 1997 Q Liang W Kuo J D Cressler et al Accurate AC transistor characterization to 110 GHz using a new four port self calibrated extraction technique in Dig 2004 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems vol 51 2004 pp 282 285 X Wei G Niu S Sweeney et al A general 4 port solution for 110 GHz on wafer transistor measurements with or without impedance standard substrate ISS calibration IEEE Trans Electron Devices vol 54 no 10 pp 2706 2714 2007 T Jamneala D A Feld D Blackham et al Why Reciprocal Procedure Works in Dig IEEE Radio Frequency Integrated Circuits Symposium 2006 pp 465 469 X Wei G Niu S L Sweeney et al Singular Value Decomposition Based Four Port De embedding and Single step Error Calibration for On chip Measurement in JEEE MTT S Int Microwave Symposium pp 1497 1500 2
123. is E EE EA 99 The magnitude of the S parameters for the four port on wafer parasitics Comparison of Y parameters between open short SVD based 16 term solution and SVD based 8 term solution esee 105 Comparison of Y parameters between open short SVD based 16 term solution and SVD based 8 term solution esse 105 Single step versus two step four port using the analytical four port solution with data measured using a HP 8510XF system from 2 GHz to JOG HZ tease at eoo A ene daliens Mta usd suat ad 110 Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig 7 10 Fig 7 11 6 2 6 3 6 4 6 5 6 6 6 7 7 1 7 2 7 3 7 4 7 5 7 6 d 7 8 7 9 Single step versus two step four port using the analytical four port solution with data measured using a HP 8510C system from 2 GHz to 2D c OAA d d c a a P du tec E btc aes 110 Comparison between two step open short and four port on wafer parasitics de embedding results with ISS calibration and single step four port calibration results without any ISS calibration 112 Condition numbers of the coefficient matrix in on wafer parasitics de embedding and single step calibration eee 113 Comparison of the single step four port calibrated results with and without switching error correction The analytical four port solution in
124. is was verified using simulation results with and without DIBL induced V change in Section 8 5 At high V so K3e g are close while K3g g tA Azt A3 Ay split for different V ps Both K3z and g do not show great 151 Vps dependence at high V because the transistor is biased in saturation region for all three V However the V dependence of the 2 and 3 order output conductance nonlinearities and cross terms is noticeable This directly leads to highly V dependent A terms at high V Therefore the denominator of 8 5 and thus the calculated IIP3 are V dependent at high V N 64 W 2um L 90nm f0 5GHz Af 100KHz 10 T i Vps70 6V 3 Vps70 8V as l Vos 1 0V E a S Bee i e r 4 Line Analytical IIP3 Symbol Measurement 10 0 2 0 4 0 6 Ves V Fig 9 2 Measured and analytical IIP3 versus V at multiple V Analytical IIP3 is calculated using 8 5 152 N 64 W 2um L 90nm f0 5GHz Af 100KHz Nonlinear Terms K3 m Imt41 A2 A3 IP3 sweet spot 10 l l 0 2 0 327 0 3754 0 7 Ves V Fig 9 3 Kse g and K3e 8 TAtA2 A3 A3 versus Vos at multiple Vps m 9 2 2 Finger number dependence To verify the analysis of device scaling in Section 8 4 Fig 9 4 shows IIP3 from measurement and 8 5 versus J for N 10 20 and 64 The peak of meas
125. istors and standards Carefully designed GSG probing pads metal ground plane and shielding structures can help on wafer parasitics de embedding and transistor characteristics Transistors with different gate connection topologies are compared The accuracy of S parameters is determined by error models and correction techniques Chapter 3 presents the four port error adaptor concept the classical 12 term model and the most complete 16 term model for a two port system As a widely used system error calibration method short open load thru SOLT calibration is demonstrated in details And the idea of performing single step calibration is introduced Starting from Chapter 4 the concept of four port error adapter is extended to on wafer parasitics de embedding from systematic error calibration A generic analytical four port solution for on wafer parasitics using Y parameters is developed in Chapter 4 Five specified on wafer standards OPEN SHORT LEFT RIGHT and THRU are necessary for solving the four port network A numerical way to evaluate the errors remaining after open short de embedding and to examine the reciprocity and symmetry of on wafer parasitics is given using experimental results Chapter 5 presents a 23 numerical four port solution for on wafer parasitics using singular value decomposition SVD Although it does not give insight views of on wafer parasitics the SVD based solution is easy to apply and gives the most accurat
126. ition of the IP3 sweet spot and the gate voltage dependence of IIP3 in strong inversion region Analytical IIP3 expressions containing more nonlinearities have been published 11 22 23 24 25 26 However the results are mainly for 0 13um and older technologies and the MOS model focused is BSIM3V3 10 22 27 Experimental results on 90nm technology and simulation results using BSIM4 model need to be examined as they become the main stream for RFIC designs 13 N 64 Wi 2um L 90nm Vos 0 8V f0 5GHz Af 100KHz 0 First order IP3 Laer Simulation Measurement 20 IIP3 dBm p m ms OO 4 lt Lr e ee Fig 1 8 IIP3 versus V from first order IP3 theory linearity simulation and two tone measurement 1 3 Motivation and objectives 1 3 1 High frequency RF CMOS characterization Emerging gigabit wire line and wireless communication applications require integrated circuits operating at frequencies above 60GHz 28 29 30 31 This demands accurate characterization and modeling of transistors at even higher frequencies Essential to obtaining a good high frequency model is the accuracy of the S parameter measurement VNA and RF probes capable of 110GHz S parameter measurements are commercially available over 10 years 32 However very few results at such high frequencies are published This is to a large extent due to the i
127. izing for high linearity are developed 1 3 7 Third order intermodulation distortion characterization Experimental IP3 results of CMOS devices have been examined using two tone IP3 measurement 22 However the results were primarily for 0 13um and older technologies and the model examined is BSIM3V3 10 22 27 This dissertation presents experimental characterization of IP3 in a 90nm RF CMOS process as well as comparing measured IP3 with simulated IP3 using a BSIM4 model For practical linearity characterization as well as optimal transistor sizing and biasing in circuit design the linearity is examined as a function of biasing voltages and device sizes An array of devices with different finger numbers are designed fabricated and characterized as a function of Vgs and Vps at multiple frequencies 2GHz 5GHz and 10GHz are selected because most current RFIC applications fall in this range In particular the sweet spot biasing current for practical large device sizes of interest to RFIC is investigated The results were presented in 2008 IEEE Radio Frequency 22 Integrated Circuits Symposium 53 and the extended paper was accepted by 2008 IEEE Trans Microwave and Techniques 54 1 4 Outline of Contributions Chapter 1 gives an overview of topics related to on wafer transistor characterization including linear and nonlinear performance and gives the motivation of this research Chapter 2 presents layout details of on wafer trans
128. key which is the button on the front panel under each block The number and unit keys on the right side of the screen are not included MORE means softkey on the screen which can be selected using the buttons on the right side of the screen The following steps are for Cascade RF infinity probe with pitch size of 100um and Cascade ISS 101 190 substrate The values entered are from the data sheet of the probes and the substrate which are also listed in Table E 1 1 Modify CalKit Press hardkey CAL in the MWURNIGN block then select MORE MODIFY 1 to modify the calibration coefficients for CalKit 1 Select MODIFY 2 to modify the calibration coefficients for CalKit 2 2 Define calibration standards Select DEFINE STANDARD Press 1 x1 Make sure the OPEN is underlined Press OPEN Select CO enter 6 5 x1 Enter 0 x1 for C2 C3 and C4 Select SPECIFY OFFSET enter 0 x1 188 Press STD OFFSET DONE Press LABEL STD enter the name of the standard e g OPEN 6 5 Press TITLE DONE Press STD DONE Repeat Step 2 for SHORT LOAD and THRU standards SHORT Press DEFINE STANDARD enter 2 x1 and then select SHORT LOAD Press DEFINE STANDARD enter 3 x1 and then select LOAD THRU Press DEFINE STANDARD enter 4 x1 and then DELAY THRU Class assignment Press SPECIFY CLASS Select S11A enter 1 x1 OPEN is defined as standard 1 in step 2 Select S11B enter 2
129. l IP3 analysis vy mE cos cos ot is the two tone input signal 22zf and w 27 f R is the source resistance while R is the load resistance C and C are small signal gate to source capacitance and drain to substrate capacitance First order IP3 theory considers the small signal nonlinear current source i as a function of v only With small signal input it can be approximated by the first three order Taylor expansion as lag Eg Kep V K3s V 1 1 Zn K2g and K3 are the first three order nonlinearity coefficients of i which can be calculated as _ Aps EU lO EU er 6 Dp 1 2 207 Fig L1 The small signal equivalent circuit used for IP3 analysis For a two tone input signal v A cos t cos o The amplitudes of v and v are related by V All JjoC R The two frequencies are f and f gs 2zf and w 27 f Therefore the output drain current in L1 contains components at frequencies mo n m and n are integers The magnitude of the fundamental components at and c are g 449 4K3 4 and the 3 order intermodulation components at 2 c and 20 are 3 4K3 4 Under small signal excitation the magnitude of the fundamental components are approximately g 4 since the second term can be ignored when compared with the g A term The 3 order intermodulation distortion IM3 is defined as the ratio of the 3 order intermodu
130. lated as l A Ur A r 49 because the ABCD parameters of a transmission line of length are given by Ze sinh yl AB cosh vy C 26 C D z sinh yl coshy C 178 where Zo is the characteristic impedance and y is the propagation constant Zo and y are the same for THRUI and THRU2 Denoting 4 s 447 une one will have AMotints PADI gsls arn C 27 In special case 2 the ABCD parameters of symmetric pads can be determined from THRUI and THRU2 4 AM qum 3 P ruat qua E ms it is hard to solve the ABCD parameters without a PAD standard However it is not necessary to solve PAD parameters for de embedding purpose because the PAD parameters are cancelled out during de embedding as shown below To solve A4 s without solve 4 and A 4 s is transformed to Y s using equations in Appendix B From pad open short de embedding the Y parameters of a symmetric PAD standard can be represented as Y 0 eel A C 28 P Thus using Y parameter representation we have y s LyMu s Y 0 C 29 0 Y Because transmission line is a symmetric structure the Y parameters of PAD can be cancelled out using Y std swap Y pa swap Y 75 swaps the two ports of Y 5s 4 1 5 can then be obtained from Y 5 p 179 The Y parameters of the left and right half of THRUI both contains one probing pad and a transmission line with length 2 Denoting the left half as
131. lation components and the fundamental components 3 Kao A 4 Ju ee 13 gt og A 2 The 3 order intercept point is the point where the fundamental and the 3 order intermodulation components are equal which is M 1 in 1 3 The amplitude of v at the 3 order intercept point is calculated as 208 A 4 Sn 1 4 3 K3z Therefore V at the 3 order intercept point is 2 _ En The corresponding maximum available power at the power source v is defined as input referred IP3 IIP3 as 2 2 14 oC R eee l 1 6 8Rs 6R K3s Em 209 APPENDIX J DERIVATION OF INPUT IP3 BASED ON VOLTERRA SERIES Volterra Series approximates the output of a nonlinear system in a manner similar to Taylor series approximation For sufficiently small inputs the output of a nonlinear system can be described as the sum of the transfer functions below order three The first order transfer function H1 s is essentially the transfer function of the linearized circuit The 2 and 3 order transfer functions H 2 s 35 and H 3 s 555385 can be solved in increasing order by repeatedly solving the same linear circuit using different order excitations Fig J 1 shows the small signal equivalent circuit for a MOS transistor excited by a voltage source with source resistance R and loaded with a resistance R C and C are the gate source and drain bulk capacitance The nonlinear current i is controlled
132. librated using SOLT while the on wafer parasitics are removed using three different techniques open short pad open short and the improved three step The de embedding procedures are detailed in Appendix C As compared in Fig 1 5 the three methods give approximately the same R and C for the examined NMOS transistor and all of them show an unphysical frequency dependence of C This indicates that for transistor measurement these three de embedding methods all fail at frequencies above 50GHz even though they are using different lumped equivalent circuit with different complexities A four port de embedding technique which describes the on wafer parasitics as a four port network was developed in 20 with applications on SiGe HBTs Advantages over open short at frequencies above 30GHz were illustrated using simulated results However the math is complex and no experimental results are presented Furthermore pad open short was shown to be more accurate than four port for on wafer inductor characterization in 17 These issues need to be examined on CMOS technologies 1 2 T T T 10f KELLLLIIOCTTIPPPOPETPY P ue xe S S E 4f pad open short _____ kcal improved three step TOO 0 L L frequency GHz Fig 1 5 The equivalent input resistance and capacitance extracted from open short pad open short and improved three step de embedded results Two step c
133. m V ps70 8V f0 5GHz 20 Gain dB Fig 9 1 Gain from linearity measurement P P and gains parameter measurement S versus Vos 150 9 2 Linearity Characteristics From analysis in Section 8 3 the IP3 sweet spot is not only determined by Ks but also the 2 and 3 order cross terms through A and A in 8 5 Here the accuracy of 8 5 is examined against measured IP3 for different biasing voltages different device sizes and different fundamental frequencies to further verify the impact of the additional terms Overall the analytical expression is not bad for this 90nm RF CMOS technology 9 2 1 Drain voltage dependence Fig 9 2 shows IIP3 from measurement and 8 5 for multiple Vps N 64 With Vps increasing from 0 6 to 1 0V 7 increases only slightly IIP3 increases by a much larger factor particularly at higher V and the IP3 sweet spot V decreases To explain the V dependence of IP3 sweet spot and high V IP3 K3z g and K3 g Ar Az Ast A4 are plotted in Fig 9 3 The zero K5 point shifts to lower Vos asV increases because of the threshold voltage change due to DIBL The V gaps between IP3 sweet spot and zero Ke point for different V are approximately the same Thus the Vps dependence of IP3 sweet spot is determined by the threshold voltage change due to DIBL and the impacts of the terms on IP3 sweet spot are similar for different V Th
134. matic measurement errors These issues are ideally handled with a singular value decomposition SVD based solution which solves the 4x4 S and T parameters of the parasitics four port Experimental results are demonstrated on a 92 0 13um RF CMOS process Note that SVD was first used to solve for the T parameters of the 16 term error model in 36 On wafer Parasitics Fig 5 1 The four port error adaptor for on wafer parasitics in wave representation 5 1 Four port parasitic network in T parameters Fig 5 1 illustrates the four port error adaptor for on wafer parasitics a and b are the incident and reflected waves at each port Port 1 and Port 2 are the two probe tips while Port 1 and Port 2 are the two device terminals The linear equation relationship in 3 27 can also be applied for on wafer parasitics Rewrite the equation as below T S S T S 7 S T 0 5 1 f t ly f 3 T E T l ts bio m 5 2 b L UT hs Un fg Ur f 6 ger S is the S parameter of the internal transistor itself and is the S parameter of the transistor plus the probing pads and interconnects as defined in Section 3 6 Each 93 measurement on a known two port standard gives a pair of known S and S and four linear equations in terms of T as expanding 5 1 gives kd b I 7 7 F 5 L SA 0 SiS S452 SA 0 SiSp SAST 10 527 s7 00 o o J 0 63 J 4 7 f 7 3 7 7 7 4 0 Sj SSR SAST 0 SA SASE S452 01 sR
135. mbol measurement mE wk i ME point 11 4dBm Pout dBm S 30 40 Pin dBm Fig 7 9 The amplitude of the fundamental output signal versus input power level at Vos 0 4V Vps 0 8V 126 Fig 7 10 shows the power level for the fundamental signal and the third order intermodulation product versus drain current density for multiple drain biasing voltages Due to the limitation of the maximum power level can be generated in experiments the results are for P 28dBm which means the transistor is operated in linear mode Only when Pin is larger than 10dBm the transistor is driven into nonlinear mode However as shown in Fig 7 9 it is hard to realize in experiments Therefore the nonlinear RF modeling performance is not directly evaluated by comparing the output power level Instead IP3 is extracted from low P measurement and used as an indicator for the linearity of the transistor N 64 W 2um L 90nm f0 5GHz Af 100KHz ce PE l I T F mi EX E 45 Ie m ep E t S3 i rd T 20 r sosy Cri a Symbol measurement Mi Vos 0 8V E Pin 28dBm iu Cri Vos 1 0V L L E 3d dBm P oit Jps mA um Fig 7 10 The amplitude of the fundamental output signal and the third order intermodulation product versus J p 127 Fig 7 11 shows input IP3 IIP3 from measurement and s
136. ment in the matrix The subscript is the row and column index of the element 2 If Q is the name of a test structure or a multi port network then S E Y Z T and A are the S Y Z T and ABCD parameters of the structure or the network The transformation between them is listed in Appendix B 169 APPENDIX B TWO PORT NETWORK REPRESENTATIONS Two port network can be represented using S H Y Z and ABCD parameters The transformation between these representations is important for system error calibration on wafer parasitics de embedding and model parameter extraction Table B 1 gives the transformation between H Y Z and ABCD parameters The transformation from S to Y and Z are given as ifi Y YX 1 S S e S Y v B 1 1 1 Z Z 1 S I S lt S Z Z Z Z B 2 where Z is system characteristic impedance Z 50Q Y Z The 2x2 matrices for the transformation from S to Y and Z are listed below I5 tSn As Y 2255 E a 14S 5 A C RSS A ba Y Y 2S7 Y 1 S8 Sy As TES 4S tA 148 15A z SuSa 7 28 E 2 I S S2 As 81 8 Sats ms Za Za 28 Z 1 5 S As PASS Sa SA 417193 eS A where A SS 8 170 Transformation between two port H Y Z and ABCD representations Table B 1 Q Q Q Q A avila Jma sSoal aa amp a SOIN lt aja TIa ala T
137. ncreased difficulty of error calibration for both system errors and on wafer parasitics The industry practice is a two step approach which first correct the VNA system errors using well established calibration standards on an impedance standards substrate 14 ISS a process known as system error calibration and then subtract the on wafer pads and interconnect lines using on wafer standards a process known as on wafer de embedding Short open load thru SOLT calibration is one of the system error calibration methods embedded in all modern VNAs e g VNA8510C and is used in this dissertation where two step calibration is involved The de facto standard technique of on wafer de embedding is open short 14 which however fails for frequencies above 20 40 GHz depending on layout design and process technology Various alternatives to open short have been proposed including three step 15 improved three step 16 four step 33 and pad open short 17 These methods use more complicated but still lumped equivalent circuits and hence require more on wafer standards For instance the three step methods of 15 and 16 require four on wafer standards However due to the lumped nature of the equivalent circuits used these methods cannot capture the distributive nature of on wafer parasitics and fail above 50 GHz as already shown in Fig 1 5 For transistor characterization at extremely high frequencies on wafer de embedding methods that c
138. ng frequency increases the distributive nature of on wafer parasitics becomes significant The de embedding techniques based on lumped equivalent circuit for probing pads and interconnections fail including open short pad open short and three step in Appendix C The distributive nature of on wafer parasitics is naturally accounted for by describing the on wafer parasitics as a four port network i e a 4x4 matrix The four port network is located between the two external ports at the two probe tips and the two internal ports at the two port device terminals 20 This four port parasitics network was shown to be solvable using five on wafer standards 20 19 These solutions however are complicated and involve taking square roots and thus choice of positive and negative signs Furthermore the solution in 20 does not give insight into the relationship between open short and four port solutions while the solution in 19 cannot be applied for single step calibration The solution developed below retains the open short relation of 17 is much simpler mathematically than both 20 and 19 does not involve taking square root and is applicable to both two step and single step calibration All of these improvements are achieved without loss of accuracy One of the standards used is an on wafer load resistor which was assumed to be ideal in 20 and 19 but always has parasitics in reality The reciprocal and symmetric 71 four port solut
139. nitude of the error terms in E E E and E The normalization factor tg does not affect the comparison between the diagonal elements and the non diagonal elements in each 2x2 matrix In Section 3 3 the 8 term model assumes that the leakage terms 645 64 6 65 6 and e 6 are negligible From Fig 5 4 it is clear that this assumption works well for the whole frequency range as the magnitude of the non diagonal elements of each 2x2 matrix is at least 20dB lower than the magnitude of the diagonal elements Note that although the magnitude of the diagonal elements of E and E are much larger than the diagonal elements of E and E4 it cannot be concluded that the diagonal elements of E and E3 are dominant elements because the elements in E and E are normalized S parameters 101 0 i i 0 ee i 220 o een Sen ite NN efle m a 901 v S 3 MSS Pas w e e ni 32 e ul ul 40H 0 ee en QR Li ry e02 d 60 Le E2 dB E4 dB 50 100 frequency GHz frequency GHz Fig 5 4 The magnitude of the S parameters for the four port on wafer parasitics 5 4 2 8 term solution using three on wafer standards Since the non diagonal elements of E E E and E are much less than the diagonal elements it is possible that 8 error terms is sufficient for on wafer de embedding Note that here
140. non ideal switch The four port error adaptor only lumps the linear errors between the measured four waves the four receivers and the four desired waves 6 1 Analytical four port single step calibration Although the combined four port network is no longer reciprocal the intrinsic device parameters can still be retrieved from measured raw S parameters using the general four port solution in Section 4 2 as is without performing ISS calibration For best accuracy the parasitic capacitance of the load resistor in LEFT and RIGHT can be included in the same way as in the two step four port calibration described in Section 4 2 The parasitic capacitance needs to be determined from ISS calibrated LEFT and RIGHT measurement As the on wafer parasitics do not drift a lot as the VNA system errors do the capacitance only needs to be determined once The value can then be used for all measurements sharing the same load resistor It does not need to be frequently verified or recalibrated as VNA system error calibration does which in general will cost at least 30 minutes for one full two port calibration Moreover poor calibration associated with less accurate calibration standards can also degrade the overall accuracy of the measured results Single step calibration results using the general four port solutions can save a lot of time and effort during RF on wafer measurements 108 To perform single step calibration the measured raw S parameters wi
141. ns internal ports Based on the definition of Y parameters the voltages and currents can be related through the Y parameters of the four port network as VN adr 30 V s y y5 yi I jia ioe E V Ju Xo n Voll A V yn Yo Yn Voll To make the following derivations easier to read voltage and current vectors are L Wet Ls pas opea F 2 V I V I The superscript e means external ports while i means internal ports The relationship in I Y XE Ee d PP F 3 I ye y V defined as F 1 can be rewritten as where 192 I d Ya Yn pfi Ei Yn fe z Ya Yz Ya Yn Ya Y The two port network between the external ports gives Vo xn ya A pour Ya F 5 V Xn ya jh Yn Yn With the direction of currents defined in Fig 4 1 the two port network between the ae EI E yz d E A A d V Ya Yn 1 Ya Y Through the Y parameters of the four port network Y and Y are related as internal ports gives your y y Y 4 yi Y F 7 or y 2 y y s Lye J ye F 8 I I V V Fig F 1 Block diagram of the 4 port network for on wafer parasitics using I V representation 193 Since the Y parameters of ideal OPEN and SHORT are Y 0 and rese 0 using F 7 y PUT oren and y DUT short are y Dur open _ Y Y Y n Y F 9 u y PUT short Y F 10 ee Recall the open short de embedded Y parameters of the device Y y VOUT _ y
142. nt is introduced The error adaptor is a fictitious linear network that is inserted between the measurement ports and the unknown two port For two port measurement the error adaptor is a four port network which is described using a 4x4 matrix or 16 error terms since there are four waves at the two measurements ports and four waves at the DUT terminals The 16 term error model is the most complete error model for two port S parameter measurement 8 term and 12 term error model can be viewed as special cases of 16 term The advantage of 12 term model is that switch error is naturally removed because the two error adapters for forward and reverse mode are completely separated Thus 12 term model can be applied on three receiver VNA and four receiver VNA SOLT calibration is based on the 12 term error model and implanted in all modern VNAs For high frequency applications especially when the leakage errors are not negligible when compared with other error terms 16 term error model is needed The complete 16 error model can be used to describe both system errors and on wafer parasitics since both of them are four port networks Single step calibration combines the two four port networks into one with two ports inside VNA and two ports at the transistor terminals When on wafer standards are available systematic errors and on wafer parasitics can be removed in a single step 70 CHAPTER 4 GENERIC ANALYTICAL FOUR PORT SOLUTION As the operati
143. nted and compared with de embedding methods using lumped equivalent circuits on 0 13um RF CMOS technology An indicator to quantify the validity of open short de embedding is given 72 4 Four port network in Y parameters Fig 4 1 illustrates the four port description of on wafer parasitics using port currents and voltages Port 1 and port 2 are formed by the two probe tips i e the two GSG pads of the whole DUT Port 1 and 2 are terminated at the two terminals of the two port device e g the gate and drain of the examined NMOS transistor We define current and voltage vectors J V J and V as follows y I Ve I I ue mx L 4 1 V I V I Fig 4 1 Block diagram of the on wafer parasitics four port network using I V representation The subscript e means external while the subscript i means internal These voltage and Y ei Y ie current vectors can be related through four 2x2 admittance matrices Y and ee Y as Hu V V 4 2 73 Denoting the two port Y parameters of the whole DUT as Y and the actual two port Y parameters of the intrinsic transistor as Y we have I Y V and I Y V Y can then be related to Y as 20 l PESERTA Mes 4 3 or y Y Y v v x 44 The 16 unknowns in Y Y Y and Y can be determined by measuring at least four on wafer standards with known Y since each measurement gives four equations Actu
144. ntermodulation product is iy i 35 jo jo j or Aris ie jon jo where V is the amplitude of the two tone input signal at v Then the input IP3 IIP3 is calculated as H1 jo H3 ja je je 1 6R HP3 J 15 where 215 f g 1 Hijo J 16 Un x a jr Gen B iNL3 H3 jo ja je 1 17 LE Ciera Substituting J 16 and J 17 into J 15 we have Ip3 UR Es J 18 6R Y j fines since Y 2jo jo Y jo for A020 0 0 Denoting s j s j and s jq iNL3 can be solved from J 4 J 12 The complete IIP3 expression for J 18 is 1 C RY IIP3 OC eK f J 19 6R Ksg pem cte A A tA En where 1 Koe 1 A coy Ens E 73s zs m 2 1 l 2 A E Kog KZ Eon Ronan Ze i 1 A K3e 8 s NUTS i 7 A Kas y 8A The impedance elements Z elements above are calculated as 216 Z Z 20 2Z e o Z Z Ys CY a 2 Z 2Z 0 Z Z 20 Z Z Zi 0 2Y 5 1 Z 2Z Z Z 2 Z Z Zi a Z 7o Z Zi Z Qa 2Z eZ Z Qo 6Z Z Z e o Z Z Z Qo 2Z Qa 6Z e o Z Zi Z Z 2a 2Z a 0 1 1 1 with Y jo g jaC Z 9 and Y jo jac a R d L Y jo S R g 217
145. nujs dI QYHL y mS 1S9 JOJSISULI I0 uo ounjonuss 489 OY jo oouejsip ped peusis 03 eUSIS oy uo spuodap SEDE 4 ees yorym uopuodopur ozis youd st Aepop NAHL v dI NAHL Y SBESHSHEI ESSA 07 amp e op 600 Z YIM S0 OUT uorssrur dI NYHL v UOISSIUISUEJ pJEM0O J SULI oouepodurr qan B SB po ppo q WILI d avo LYOHS T as 9 NddO I vs 0 dVOT o s t LHOHS c gs Hdr HdcC8 4JL9 wings 9 NHdO I v s Hdp 0 Hdct ds ungor Gees A a9 o Sw peso ow wL T uoys T uedo 9 youd sjuouiugiss y sse pepuejsg 2 soqoJd HSH Ajurur JY 9peose 107 juejsuo q dI NYHL xvod 666 0 OS 0 I NAHL rt 0 dVOT X 0 666 0 006 0 180000 P9XIT qvoTl LYOHS Xt0 666 0 OS 0 0 C E LWMOHS C 9 NddO X 0 666 0 OS 0 0 0 0 0 9 NHdO I XVIN STRIS S OM ME ndis SdAL ON 138v1 3din93AvM Z SSO1 AVI3G ONIGITS ZH 4g 0b ZH Alge OL ZH 3 0L 35 01 dHYANYLS 10 XVOO 10 qaXl4 9 ZO LD 09 ZH9 AON3hO3MJ 13S4JO QSVONVLS Table E 1 061 101 SSI opeose pue youd umo oqod NSH Augur qp opeose Joy suoniutjop prepuejs uoneuqieo LTOS v APPENDIX F THE RELATIONSHIP BETWEEN OPEN SHORT AND FOUR PORT Fig 4 1 illustrates the four port network for on wafer parasitics There are two V and I m m m external ports and two internal ports V I are the voltages and currents at each port The subscript m is the port number m 1 2 The superscript mea
146. o tone input signals f and fo is Af The two components at 2fj and 2 f are the IM3 products induced by the nonlinear drain current to gate bias function which are Af away from the two tone signals Since the frequency step for mobile communication channels ranges from 30KHz to 200K Hz Af 100KHz is chosen for the two tone intermodulation measurement in Fig 1 1 If the transistor is not very linear the amplitude of the two IM3 products can be comparable to the amplitude of the desired signals And thus the information you received can be 2 way off if the filter s roll off is not narrow enough The third order intercept point IP3 is usually used to quantify the third order intermodulation distortion 10 11 The details of IM3 measurement and IP3 extraction are presented in Section 1 2 The 1dB compression point can be simultaneously extracted while extracting IP3 20 Fundamental frequency products P 17dBm in 0 a l l Ves 0 6V E Third order Vps 10V intermodulation products A D 40 3 a 60 i i E i f f f i i 100 I Af 21 Af 1 ks 211 f2 f1 5GHz f2 5GHz 100KHz 2f2 f1 Fig 1 1 The power spectrum at the drain of a single transistor under a two tone excitation measured by a 50Q spectrum analyzer 1 1 Scattering parameter measurement Fig 1 2 illustrates a typical two port system for on wafer S parameter measurement It includes a two port vector network anal
147. ometer consisting of two couplers connected back to back and the unknown one port DUT L The direction of power flow through the system is indicated using arrows a and b are the incident and reflected waves measured by the VNA The measured reflection coefficient of the unknown one port is defined as I b a The linear errors introduced by the imperfect reflectometer can be modeled by a fictitious two port error adapter between the reflectometer and the unknown one port This results in a perfect reflectometer with no loss no mismatch and no frequency response errors Incident Reflected x 1 lt _ a Reflectometer T by pour ae a b Fig H 1 The block diagram for a one port measurement 201 H 1 Error adaptor for one port system Fig H 2 shows the fictitious two port error adaptor for a one port system The error adapter has four error terms Defining incident waves to the error adapter as a and a the reflected waves to the error adapter as b and b a means incident wave b means reflected wave The subscript is the port number The measured and the actual reflection coefficients of the unknown one port are T b a and L a b Written in matrix the S parameters of the two port error adapter can be defined using the waves as Hee b eo Bd eo i The 2x2 matrix E is the S parameters of the two port error adapter The same relation can be equivalently represented using the signal flo
148. one standard Among the six combinations only three of them are non singular i e 1 SHORT THRU LEFT 2 SHORT THRU RIGHT and 3 THRU LEFT RIGHT Fig 5 5 shows the condition number of the coefficient matrix built using the six combinations of three standards The condition number for 5 standards is also shown as reference Fig 5 6 compares the de embedded Y parameters using open short SVD based 16 term and 8 term solution The 5 standards used to solve the 16 term solution are OPEN SHORT THRU LEFT and RIGHT The 3 standards used for 8 term solution are SHORT THRU and LEFT With non singular standards 8 term model can provide reasonably accurate results 104 300 X OPEN SHORT THRU OPEN THRU LEFT OPEN THRU RIGHT 200 ey L4 RR E 400 boo 5 2 Pe taharet TE et 2 l xxx 1 V l SAX VA E 20 i Diinan nca coc i B 2 i l o SHORT THRU LEFT 16 term T i i 8 term model 15 with three standards SHORT THRU RIGHT THRU LEFT RIGHT 5 standards 10L L l rreren oe Bee Teo ere eee eens e MM TT 0 0 20 40 60 80 100 frequency GHz Fig 5 5 Comparison of Y parameters between solution and SVD based 8 term solution 120 open short SVD based 16 term open short 16 term 5 stadnards 8 term 3 standards vimm vt apet
149. or varying N the calculated first order IP3 for varying N are perfectly overlapped For N 1 IP3 from 8 5 is almost the same as first order IP3 and the sweet spot is at the zero K3z point As device size increases the deviation between IP3 calculated using 8 5 and first order IP3 increases J ofthe IP3 sweet spot is the lowest for the largest N W 2um L 90nm Vos 0 8V f0 5GHz Af 100KHz Number of finger N 7 1 5 10 20 64 15r increase UE uu MMC IMEEM MM M MU Ai Line First order IIP3 K3 g H gm m 10 tee PER Symbol IIP3 calculated using 5 7 bx H K3 g ATFA2 A3 A4 I 2 gm m IIP3 dBm ou I I I I I I I I I n I R 10 0 Jps A m Fig 8 6 IIP3 calculated using 8 5 and 8 3 versus J for devices with multiple finger numbers 143 8 5 DIBL effect The V dependence of IP3 sweet spot V is a direct result of the DIBL introduced threshold voltage change from previous analysis The threshold voltage change caused by DIBL is modeled using AV DIBL in BSIM4 model 2 To further investigate the impact of DIBL simulation results with and without AV DIBL are compared AV DIBL is turned off by setting corresponding model parameters to zero Fig 8 7 a shows J V results from simulation with and without AV DIBL Without AV DIBL Ip at low Vos for different V are close The zero Ke points are therefore clo
150. our port or on wafer parasitics four port Since the two ports at the probe tips are shared by the two four port networks it is possible to combine the two four port networks into one Fig 3 19 shows the combined four port network The technique that solves the combined four port network between the perfect VNA and the 66 transistor terminals using on wafer standards is called single step calibration The error models and calibration techniques discussed above can be applied without modification However single step calibration is not widely used in the past because of traceability issue and less accurate on wafer standards compared with ISS standards 34 86 Combined 4 port for system error amp on wafer parasitics 4 port 4 port Error on wafer Adaptor parasitics SM S DUT 54 Fig 3 19 The combined four port network including system errors and on wafer parasitics For transistor characterization purpose S parameters are usually measured on a large number of transistors which may take hours or days For two step calibration the accuracy of ISS calibration need to be rechecked frequently as systematic errors may drift during hourly measurements e g temperature changes This is time consuming and requires a manual switch of the test wafer and the ISS substrate This problem is naturally solved with single step calibration However as mentioned in Section 1 3 4 67 there are two problems need to be solved The firs
151. ow that there is parasitic capacitance in parallel with the resistance The parasitic capacitance C and C can be extracted from open short de embedded LEFT and RIGHT y 7 and y2 The impact of these capacitances is examined by setting C C 0 during de embedding procedures Fig 4 4 plots the general four port de embedded Y parameters with and without including C and C The transistor Y parameters are noticeably different especially for the input admittance y and the effective transconductance Rf yy This difference indicates that the extracted small signal parameters can be affected for example the effective gate resistance extracted using R SHY and the effective gate capacitance extracted using C 1 2 f3 1 Y 18 84 lt open short 4 port with CL amp CR 4 port without CL amp C frequency GHz frequency GHz Fig 4 4 The four port de embedded transistor Y parameters with and without including parasitic capacitance in y and y For comparison open short de embedded results are also plotted No reciprocal assumptions are made for four port parasitics de embedding Fig 4 5 compares AR and C extracted from Y in Fig 4 4 The R extracted without C and C is 2Q larger than the R extracted with C and C The general four port R with C and C is close to the open short AR but shows improved frequency depend
152. ow will show that a a calculated from M M gives better error tolerance Assuming the actual LEFT is not ideal there will be small error term added to Y as Y y L il 4 21 E E The M matrix which involves the measurement errors in the LEFT measurement and the calculation errors during open short de embedding can be written as M Y jy BA SD a 4 22 ab ab A A A combines the non ideality factor the measurement errors and the calculation errors The physical nature of the LEFT and RIGHT standards dictates that M and N are the largest elements in M and N and close to one respectively as confirmed by measurements Hence A a b and M M can be calculated as M5 db TA AU ab d A Ay Mj a b A ab ab a O A 4 23 As O A is a very small number M M is relatively accurate even with non ideal LEFT structure However M M is calculated as 80 M ab A z A i 4 24 My ab A a Since ab and a b are close to zero from the physics nature of LEFT and can be comparable to A M M may give inaccurate a a A similar situation exists for a a Hence solutions with M and N as denominators should be used to obtain better error tolerance Fig 4 3 plots the real part of de embedded y as a function of frequency from which g is extracted The g extracted from the results with a a M M is much smoother and more accurate then the one extracted from th
153. owns can be solved is 15 because the only possible solution will be an all zero solution if the coefficient matrix is full rank Therefore 15 error terms can be solved as a function of the 16 no matter how many standards are measured Secondly because of the singularity conditions besides the freely chosen 16 parameter one error term 64 remains unknown and it can be solved using the fifth measurement Numerical examples in Appendix G show that the set of equations is ill conditioned for any four passive standards The previous 8 term model and 12 term model can also be represented using the four port network as they are actually describing the same set of systematic errors The 8 term model is just a special case of 16 term model with negligible leakage terms Only directivity port match and frequency response terms are considered in 8 term model The leakage terms e and e in Fig 3 13 and Fig 3 15 can be added to the signal flow graph which increases the number of error terms to 10 and can be determined individually using LOAD standard Thus the 4x4 error matrix for 8 10 term model in defined as b Eoo 0 ej e 0 a b Olen e 0 e lla 3 30 33 32 3 3 3 1 b eo 0 e O0 lla b 0 e 0 e a The 12 term error model in Section 3 4 is equivalent to two error matrices one for forward mode one for reverse mode 87 For forward mode a is not available so the matrix becomes by 0 Eo E do
154. plicated and thus not shown The IP3 expression without C is sufficient for understanding the biasing and device size dependence of IP3 Only when frequency is high and device size is large C is needed as illustrated in Section 9 2 3 135 8 2 1 Two dimension nonlinear current source The nonlinear current source i in Fig 8 1 controlled by gate source and drain source voltages is written as 24 2 3 Las EmV gs t K2g V K3s V 2 3 g Vy K22 V K3g Vi 8 4 2 2 HK 2e pgo Vgs Vas K322 8 V Vas 2 K3s 28 Va Vds g and g are the linear transconductance and output conductance K2g and Ke are the 2 and 3 order nonlinear transconductance while K2z and Ksg are the 2 and d 3 order nonlinear output conductance K2 2 Kxe and Kse are the 2 and 3 order cross terms The nonlinearity coefficients are defined in Table 8 1 Table 8 1 Definition of nonlinearity coefficients of nonlinear drain current Transconductance Output Conductance Cross term gi Aps 8 _ Ans K2 2 EL OV s OV ns OV AOV 2 2 3 I I I K2s 1 0 Ds Ke zs l 7 Ds K325 5 ae 2 V s 2 OV 5 OV OV ps 1I 18 I 32m ane es 3g EC Bs K 32 22 zc in e 6 OVE 6 0Vy OV 5OV 55 Fig 8 3 shows all of the nonlinear coefficients versus V at V 0 8V for a large device width used in practical circuits W 128um The zero Kss V is marked because it is the IP3 sweet spo
155. pper limit of spurious free dynamic range Among various linearity measures the two tone third order intermodulation distortion IM3 is the most widely used and is typically characterized by the third order intercept point IP3 11 Using either measured or simulated I V data IP3 sweet spot biasing current can be determined from zero K3z point based on first order IP3 theory 11 Kse is defined as the 3 order coefficient of the nonlinear transconductance Circuits have been published to utilize this zero Ke point for high linearity LNA designs 48 52 However it was shown in 53 that the IP3 sweet spot from measurement and simulation both shift to a lower V than the zero K3 point and the first order IP3 theory cannot correctly model the biasing and device scaling dependence of IIP3 More accurate analytical IP3 expressions need to be developed The complete IP3 expression in this work is developed using the nonlinear current source method based on Volterra series The nonlinear drain current source includes nonlinear transconductance output conductance and the cross terms The IP3 expression published in 22 25 26 are just special cases of this complete IP3 expression It will be shown later that the cross 132 terms ignored in 22 25 are important for accurate IP3 modeling and are responsible for the V dependence of IP3 sweet spot V to drain induced barrier lowering DIBL Linearity simulation results
156. pt indicates the order of the transfer functions while the second subscript corresponds to the number of the node Hence the transfer functions can be solved from the matrix equation below 1 s 0 Js d da 14 g YX s Hi s n Solving J 4 gives the first order transfer functions at node 1 and 2 as 1 1 H J 5 li s Y s R g 1 Mi s 1 6 Fig J 2 The linearized equivalent circuit for solving first order kernels J 2 Second order kernels The second order kernels are calculated from the response of the linearized circuit to the second order virtual nonlinear current source iNL2 as shown in Fig J 3 The 212 virtual excitation iNZ2 is placed in parallel with the corresponding linearized element and is the only excitation applied to the circuit when calculating second order kernels The external excitation V is grounded Denoting the second order kernels at node 1 and 2 as H2 s 5 and H2 s a these transfer functions can be solved from the matrix equation as 3 7 Zn Y s 5 Ho sis N s 5 0 H2 s 82 E INL2 iNL2 1s determined by the second order coefficients in J 1 and the first order kernels of their corresponding controlling voltages INL2 K2g H1 s m s TK2 amp g Hl s FA s J 8 FL Kiss n s in s H1 s n s Solving J 7 gives the second order kernels at node 1 and 2 as H2 s 8 0 J 9 J 10 F
157. published to solve the 16 term model in S or T parameters using five standards 35 37 36 41 43 39 Two general approaches to solve the four port error network using five standards are developed in this dissertation an analytical solution based on Y parameters in Chapter 4 and a numerical solution using SVD and T parameters in Chapter 5 3 1 Two port S parameter measurement Fig 3 1 is the block diagram for the two port S parameter measurement system in Fig 1 2 which includes VNA8510C system DC power supply and a control computer The measurement is controlled by a MATLAB program on the computer through a USB to GPIB controller For each measurement the program first biases the DUT by sending GPIB commands to the DC power supply then starts one single frequency sweep by sending GPIB commands to the VNA s processor The DC voltage is added to the DUT through two bias tees inside the VNA test set Two DC cables connect the outputs of the DC power supply to the test set from the backside of the two equipments which are illustrated using dash lines in Fig 3 1 44 Agilent 8510C system Computer Display amp Processor GPIB pep Be ap BE BH Controller IV Ae El o00 DC power supply n lt on m w C 7 Test Set Synthesized Sweeper Fig 3 1 Block diagram for two port S parameter measurement using Agilent 8510C system Fig 3 2 shows the simplified block diagram of a two port syst
158. r measurement system configured for reverse IBOdBC arse ted b ated sao atus NC ct d ia or A 54 Reverse mode signal flow graph for two port system including non ideal Zo termination eoo sakes desee e e tH aa tuts aie en efe E eu et 54 Simplified reverse mode signal flow graph for two port system 54 Forward mode signal flow graph for two port system suse 56 Normalized 6 term error model for forward mode 56 Normalized 6 term error model for reverse mode sssse 57 a OPEN b SHORT c LOAD and d THRU standards for SOLT calibration on Cascade ISS 101 190 oet e deep a RU tn tage 29 Raw and corrected data for S and S of a 0 13um NMOS transistor 61 Signal flow graph of the 16 term model for a two port system 62 xiii Fig 3 19 Fig 4 1 Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig 4 2 4 3 4 4 4 5 4 6 4 7 5 1 5 2 5 3 5 4 5 5 5 6 6 1 The combined four port network including system errors and on wafer PAT diuo oh a a RM M MT CERNERET NR 67 Block diagram of the on wafer parasitics four port network using I V representation man ue As esce eoi Soc ed detur e e eet Cs 73 The equivalent two port network of the intrinsic NMOS transistor and the five on wafer standards OPEN SHORT LEFT RIGHT and THRU The real p
159. rain terminal of the transistor The source terminal is tied to the substrate terminal and grounded Multiple thick metal layers are used to connect the source and substrate to the ground pads to reduce substrate effect and nonidealities of on wafer standards Source Metal 2 Tied to Substrate Ring Contacts to Ground NS GAG i J Substrate Ring Ta AY WW ate Meta C look OOO LLL 5 e PS T Ga 7277 BE UB A Gate Fingers with Double sided Gate Contact Nr 10 CM HYEE JIL ii RNS GE Fig 2 5 Layout for one cell of the desired transistor MUM Yt rears NS 32 Fig 2 6 gives the layout of the desired NMOS transistor and the five on wafer standards used to solve four port error adaptors OPEN SHORT LEFT RIGHT and THRU Fig 2 6 a is the desired NMOS transistor without pads and most of the interconnect lines The total channel width of the transistor is 150um and the channel length is 0 13pm The transistor contains three identical cells i e multiplier factor 3 Each cell has the same layout as shown in Fig 2 5 Without specification the S Y and Z parameters used to perform error correction from Chapter 4 to Chapter 6 are measured on this set of test structures fabricated on the 0 13um chip in Fig 2 2 a The reference plane is selected to be as close as possible to the gate and drain terminals of the transistor which is marked out on the OPEN structure in Fig 2
160. ram for this 50 system The gate and the drain of the NMOS transistor in linearity simulation are also terminated at 50 2 ports Fig 7 2 shows the schematic for two tone intermodulation distortion simulation A psin component from the analoglib of Cadence generates the two tone excitation at the gate Since linearity measurement is made at the probe tips and it is impossible to calibrate on wafer parasitics a passive RLC network which models the low frequency on wafer parasitics is inserted between bias tees and device terminals to make the environment as close as possible to real measurement An array of transistors with number of fingers N ranging from 5 to 64 are measured and simulated with sweeping biasing voltages at different fundamental frequencies Although QPSS analysis is selected to speed the linearity simulation it may still take days even with a high performance computer P f f Pah fo Af Fig 7 1 Block diagram for two tone intermodulation linearity measurement 119 r 5 vaDBm 2 Pin freq2 fO df vaDEm Bin a freq f 1 Qo psin Eo a Lfaad num 1 wv A T G vdc Vos gnd w g P6 P1 r 5 6 i pein 5n parasitics nonsym ETT PS Pe g r5 3 I Lfeed IG FA nur P adeb b GND COM N vdo VDS Fig 7 2 Schematic for two tone intermodulation linearity simulation in Cadence Each finger of the NMOS transistor is 2um wi
161. rovide significant improvement over open short and four port is necessary despite the need to use on wafer load resistors 9 CHAPTER 5 NUMERICAL FOUR PORT SOLUTION On wafer transistor S parameter measurement is fundamentally important in both laboratory and production testing The most complete system error model is the 16 term model 36 which accounts for all of the possible signal paths between the four waves measured inside the VNA and the four waves at the two terminals of the DUT as illustrated in Section 3 5 The idea of describing everything between the probe tips and the device terminals as a four port network 17 20 is essentially the same as the 16 term error adaptor concept in system error calibration at least mathematically as illustrated in Fig 5 1 Analytical equations for determining the 4x4 Y parameters of the four port network are developed in Chapter 4 and 19 20 using five on wafer standards However these analytical solutions can only be applied if the specified five standards OPEN SHORT LEFT RIGHT and THRU are available Once other standards are used new equations need to be derived Also due to its analytical nature the solutions cannot take advantage of the redundancy available from the measurements of five on wafer standards and does not provide information on the relevant importance of the 16 terms of the parasitic four port Furthermore analytical solutions do not provide information on syste
162. rror in the analytical solution Here we propose a simple criterion to examine reciprocity From Fig 4 6 we notice that a a b aj b and a b i e A B Although a b is always true as a result of our choice of normalization the agreement of the other 3 6 elements suggests that the solved four port parasitics is reciprocal and the on wafer OPEN and SHORT standards may indeed be viewed as ideal Accordingly the de embedded Y parameters using reciprocal assumption are almost identical to the general four port results However both A and P are clearly not symmetric matrices which is a direct result of our asymmetric layout design necessitated by our choice of the desired reference planes 4 3 Reciprocal four port solution and pad open short Reciprocal four port network means Y 2Y Y Y ee ei ie and Y Y 20 Thus we will have 42 B and k b a 1 from 4 11 and 4 12 Therefore the number of unknowns can be reduced to 4 All of them can be directly solved from open short de embedded LEFT and RIGHT as x NUN M 12 521 Ny A A _B B 4 4 30 because we have a b aj bn 4p b and a b in 4 15 and 4 16 and k 4b a 1 in 4 17 and 4 18 The de embedded results using general four port solution and reciprocal four port solution for on wafer parasitics are very close and can 88 be viewed as identical Given that only one THRU structure is saved we
163. ry little impact on IP3 sweet spot The variation of A A2 with Vps is approximately the same for simulation with and without AV DIBL Thus the impact of A1 A on the V dependence of the deviation of IP3 sweet spot V from zero Kss point is approximately the same for simulation with and without AV DIBL The V dependence of IP3 sweet spot V is thus mainly a result of the V dependence of the Zero K3e 146 N 64 W 2um L 90nm Ig ATFAZ A3 AA gm K3 E o E o e x 0 e a i a 3 e S N RENE ae poe eie cajus Eoo 5L MEER TIL n En PI em m ug dem die a tt eee eee ae m m 15 0 2 0 4 0 6 Fig 8 9 a Ks g Art Az Ast Aa b Kss g and c AtA versus V at multiple V for Cadence simulation with and without AV DIBL 8 6 Summary This chapter develops a complete analytical IP3 expression which involves not only nonlinear transconductance but also nonlinear output conductance and cross terms The deviation of the sweet spot V from the widely accepted zero K3 point for a practically large device size found in LNAs is attributed to output conductance nonlinearities and cross terms through this expression The impacts of these additional terms added to K3z g are examined individually to figure out the dominant factor for IP3 sweet spot shift The significance of the additional terms scales with device 147 width Th
164. s but also the OIP3 value for the IM3 products 3 F ey di A E ae 8 DC f1 f2 DC DC RF Fig 1 6 An on wafer enned e measurement system Fig 1 7 shows the fundamental and IM3 output products as a function of input power level P in dBm for a typical MOS transistor measurement The solid lines are the measured power values in dBm for the fundamental output product and the IM3 output product P and P 5 4 The dash straight lines are linear extrapolations of Poutise and Po 5 4 at a very low reference Pin The reference P for extrapolation must be well below the 1dB compression point which is 25dBm in Fig 1 7 The 1 dB compression point is the input power level where the small signal gain drops by 1 dB which sets the upper limit for small signal linearity analysis The intercept point of the 11 two dash straight lines is the third order intercept point IP3 The input power level at the IP3 point is IIP3 and the output power level at the IP3 point is OIP3 In Fig 1 7 the IdB compression point is 12dBm IIP3 1 8dBm OIP3 18dBm and power gain 16 2 dB 30 3rd order Intercept Point E OIP3 IP3 e dBm 30 out P P out 3rd 60 30 25 20 15 40 5 0 5 P dBm Fig 1 7 The fundamental and IM3 output products versus input power for a two tone excited system Before extracting IIP3 OIP3 and power gain the power loss on the input and the output route including RF c
165. s are nonsingular and can provide valuable T solutions Among the five sets of standards the combination of 197 THRU O O S S S M M S gives the smallest condition number and thus the best tolerance to measurement errors If the five standards are nonsingular then adding more standards will not help to improve the validity of the 7 solution Fig G 3 compares the condition number minimum and maximum singular values for 5 6 and 7 standards Two sets of nonsingular five standards are compared Both of them show that adding more standards do not reduce the condition number of the coefficient matrix o Q E 3 c c 9 c 9 S S 9 107 THRU M M O O S eX sss THRU O M M 0 S S L z ae o Less THRU S M M S 0 0 I ia T mY FN A 3 4L IN p A aA NC AUN An A 31 A 2 iM M Aye PAS Bw NJ o I AY I 1 E 2 MS l J 5 a l M Fe E 0 an aare L f E v T 3 T T T T T gt 5 onznssnnEnunnnzonal 3 5 E minim o l c O E 3 E x E frequency GHz Fig G 1 Condition number minimum and maximum singular value for four standards 198 Table G 1 Nonsingular combinations of five two port calibration standards for 16 term error model Assuming one standard is a zero length THRU THRU A M M A A A B B THRU M M A A B B A B THRU A M B A A A B B THRU M M A A B B AM THRU A M B M A A B B THRU M M A A A B B A THRU
166. s than 16 that is to say that the maximum number of unknowns can be determined is 15 no matter how many on wafer standards are measured The equations may be solved by normalizing the unknowns to one of the unknown terms preferable one whose magnitude is close to unity In Appendix H the term was used as normalization factor for one port error correction essentially because the frequency response e can only be solved as product Since T Ej and Ti Ts T4 are functions of E in 3 30 and the diagonal elements of E e and e are related to frequency response the diagonal elements of T4 t and are good choices for normalization 4 is used as the normalization factor in this dissertation The normalized 7 matrix is hod h hy T 7 i t I Un m 5 4 T T E t bii Ls Itb b 1l t t t k 1 15 After normalization 5 1 can be rewritten as DS S TS eS 1 Pha 5 5 The four linear equations for each measurement is then rewritten as 95 Si 0 SiSU SiSE sj 0 sis sise 10 5 00 0 r o GO 0 SA sAsP SASZ Q st SASD S48D 01 S27 SP 00 0 _ 0 Si 0 SSK SoS Sa O SS S28p 00 0 0 LOSI J Sp 0 Sj SSP S4SD 0 S SASRYT S s 00 0 0 01 s37 SUME ond Denoting the 15 normalized unknowns as Tga Cui 0 64 can be rewritten as AasTis4 Bisa where C ET By As discussed in Section 3 4 the e and e error terms cannot be measured independently because of the ratio n
167. se for different Vp as shown in Fig 8 7 b Fig 8 8 shows simulated IIP3 with and without AV DIBL for N 64 Without DIBL the Vps dependence of IP3 sweet spot V is dramatically reduced 144 N 64 W 2um L 90nm 10 I Simulation with AV DIBL 1 1 10 zzz 4 T z Vps 0 6V i V__ 0 8V A C V S 24 0V 10 G l me pgs 4 i 1 a Simulation without AV DIBL a 10 L 0 2 0 4 0 6 _ 500 z OE desosa nO b 4 d z 3 t 2 N E O X GQ M bone a E o g gm n zl Es tod IC ar P ae AAAA m 500F Simulation with AV p DIBL te b eg Lg L 0 2 0 4 0 6 Ves V Fig 8 7 a Iy b Kse versus V at multiple Vps for simulation with and without V shift due to AV DIBL N 64 W 2um L 90nm 10 f f Simulation with AV DIBL eee a a Am V U Map IIP3 dBm eo I li li I I I i hen Simulation without AV DIBL 1 L 0 2 0 4 0 6 Ves V Fig 8 8 IIP3 calculated using 8 5 versus V at multiple Vps for simulation with and without AV DIBL 145 Fig 8 9 a compares the denominator of 8 5 for simulations with and without AV DIBL Fig 8 9 b and c compare the most important terms in the denominator of 8 5 K3z g and A Az individually A3 and A are not shown here because they have ve
168. still a linear equation of the unknown terms After normalization only three unknowns need to be solved Three standards e g OPEN SHORT and LOAD can be used to solve the three equations as below por spp ap dos d v ae pU seer ee s pus 8 8 P5 pepesr t t De Once the three error terms are solved the system errors of any measured I can then be calibrated using an alternative of H 6 as py 5 peur fy H 9 f pH Db 7 205 Considering the linear equation in H 5 at first glance one may think with four measurements f f f and can be completely solved without normalization However the resulting linear matrix problem is homogenous For four measurements the four linear equations written in matrix are peu E a 1 p t 0 28 2pHepbsP 1 EE t 0 DUT3 M3T DUT3 M3 i H 10 T pier E pter Pura zpM4pBUurA4 1 cp t 0 If the four unknowns can all be solved the coefficient matrix must be full rank This leads to an all zero solution of 7 So the rank of the coefficient matrix must be smaller than 4 which means in maximum only three of the unknowns can be solved This is theoretically attributed to the ratio nature of S parameters and the inability to solve e and e independently The normalization of T elements will not affect error calibration at all 206 APPENDIX I DERIVATION OF FIRST ORDER INPUT IP3 Fig 8 1 shows the small signal equivalent circuit used for analytica
169. suggest that the general four port solution to be used as consistency between reciprocity and ideal OPEN and SHORT can be checked and single step calibration can be made Note that with reciprocity there are only 10 independent terms left in the original 4x4 matrix describing the four port on wafer parasitics On the other hand the pad open short of 17 uses a 9 element equivalent circuit It was then suggested and concluded in 17 with inductor data that pad open short is better than four port as it gives comparable results but does not require using on wafer load resistors We reexamine this issue for active RF CMOS transistors in Fig 4 7 where open short pad open short and reciprocal four port results are compared The Y parameters of PAD is estimated from layout using extraction tools as was done in 17 Above 50 GHz open short is much less accurate as the lumped equivalent circuit with 6 elements fails Although pad open short includes 9 elements in the lumped equivalent circuit the improvement over open short is very limited The reciprocal four port with 10 error terms does a much better job particularly above 50 GHz The main reason for the success of the 10 term reciprocal four port method we believe is that it does not rely on lumped equivalent circuit and has little to do with the use of one more term than pad open short One may use an equivalent circuit with more than 10 elements and still obtain less accurate results as
170. systematic errors b The four port network for on wafer parasitics sess 17 The top view of an on wafer test structure for transistors a The whole test structure including probing pads b The MOS transistor under test only The dimension is not to scale 5 ee nce i e rhere ees 27 Chip pictures of the fabricated transistor structures on three RF CMOS technologies b and c are fabricated at different foundries 28 Cross section view of an advanced RF CMOS technology The dimienstondsd0 36816 s teet No RN D even sv uate UH D MN S 29 The cross section view of GSG pads and MOS transistor along three GUE sic ne tice cating E E Rc Df E E D deb ALLEE 31 Layout for one cell of the desired transistor sss 32 Layout for the desired transistor NMOS and the on wafer standards OPEN SHORT LEFT RIGHT and THRU eere 34 Layout for NMOS transistors with different gate patterns and multiplier TaCtOE S5 e Gu hoe n t ed a n seas tee aes di pma aA o 36 An example for fp extraction a toi tete tabe dete oit utet asd 37 Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig 2 9 2 10 2 11 2 12 3 1 32 3 3 3 4 3 5 3 6 3 7 3 8 3 9 3 10 3 11 3 12 3 13 3 14 3 15 3 16 3 17 3 18 An example for f extTactlOni sie tene Lei tee qi ecce tin pas 37
171. t al RF distortion in deep submicron CMOS technologies in Tech Dig of Int Electron Devices Meeting IEDM 2000 pp 807 810 P H Woerlee M J Knitel R v Langevelde et al RF CMOS performance trends JEEE Trans Electron Devices vol 48 no 8 pp 1776 1782 2001 M Hiebel Fundamentals of vector network analysis Germany Rohde amp Schwarz 2007 160 13 14 15 16 17 18 19 20 21 22 23 24 S A Wartenberg RF measurements of Die and Packages Boston USA Artech House 2002 M C A M Koolen J A M Geelen and M P J G Versleijen An improved de embedding technique for on wafer high frequency characterization in Proc of IEEE Bipolar Circuits and Technology Meeting pp 188 191 1991 H Cho and D E Burk A three step method for the de embedding of high frequency S parameter measurements IEEE Trans Electron Devices vol 38 no 6 pp 1371 1375 1991 E P Vandamme D M M P Schreurs and G Van Dinther Improved three step de embedding method to accurately account for the influence of pad parasitics in silicon on wafer RF test structures JEEE Trans Electron Devices vol 48 no 4 pp 737 742 2001 L F Tiemeijer R J Havens A B M Jansman et al Comparison of the pad open short and open short load deembedding techniques for accurate on wafer RF characterization of high quality passives JEEE Trans Microwave Th
172. t estimated from first order IP3 theory All of the 136 derivatives are calculated from simulated I V data The I V data are simulated using BSIMA model in Cadence and exported with 12 digits to ensure accurate numerical evaluation of 2 and 3 order derivatives Fig 8 3 a and d show the linear transconductance and output conductance versus V Fig 8 3 b and c show the a and 3 order nonlinear transconductance while Fig 8 3 e and f show the 24 and 34 order nonlinear output conductance Fig 8 3 g i are the 2 and 3 order cross terms Compared with the cross terms the output conductance nonlinearities are much smaller especially at the sweet spot The impact of cross terms on IIP3 sweet spot location should be negligible which is evaluated numerically in Section 8 3 N 64 W 2um L 90nm Vos 0 8V e 0 X 400 0 2 0 3754 0 7 0 2 0 3754 0 7 0 2 0 3754 0 7 Vos V Ves V Vas V Fig 8 3 The nonlinear coefficients versus V 137 8 22 Input IP3 expression Using Volterra series analysis the complete IIP3 expression with i in 8 4 is derived as 1 1 C R Y Se aE 8 5 6R Ken pA A 4 A Em The derivation of 8 5 is detailed in Appendix J The first term in the denominator K3z g is due to the 3 order transconductance as found in first order IP3 expression 8 3 The other terms containing nonlinear o
173. t is how to verify the accuracy of the results The second is how to model the non ideal parasitics of on wafer standards This dissertation uses two step calibration results as a reference to evaluate the accuracy of single step calibration Since the verification only need to be done for several reference test structures before large amount of measurements it can still reduce the time for measurement and help automation of large volume measurements The non ideal parasitics of on wafer standards is also examined in this dissertation First of all OPEN SHORT standards can be assumed to be ideal from the experimental results in Section 4 2 The same assumption is applied in on wafer de embedding step for two step calibration Secondly the length of on wafer THRU is much shorter than the THRU on ISS substrate because the dimension of the transistor is usually much less than the distance between the two signal pads Thirdly on wafer resistor standard can be modeled using a similar mathematical model as ISS calibration does The parasitics of on wafer resistor can be lumped as a parallel capacitance whose value is determined from low frequency measurement Since the parasitic capacitance will not drift a lot for a fixed process the value just need to be checked once for one process Fig 3 19 shows the two four port error adapters for systematic errors on wafer parasitics and the four port network combining systematic errors and on wafer parasitics
174. th different gate patterns and multiplier factors 2 3 2 Gate finger configuration Fig 2 11 shows the layout for three NMOS transistors with the same gate length and total gate width but different number of fingers Nr and finger width Ws The number of fingers and the finger width of the three transistors are a N 20 W 2 um b N 10 We 4um c Ne 5 We 8um All of the transistors are laid out using double sided gate contact and C look gate metal connection Fig 2 12 a d compare A g Jfr and f extracted from open short de embedded Y parameters Again SOLT calibration and open short are used for system error calibration and on wafer parasitics de embedding The first two transistors with N20 Wi 2um and N 10 WS4um are 39 practically the same for the four parameters extracted The transistor with the longest We Wr 8um has the largest R and thus the lowest f as expected However the R value difference does not follow ideal scaling rules of CMOS transistors The reason may also lies on the narrow metal connection to the double sided gate contact The R value extracted is dominated by the resistance on the metal lines instead of the gate fingers AEA Wr 8um Fig 2 11 Layout for three NMOS transistors with same total channel width but different finger width and finger number Wiota 40pm 40 40 N 20 Wz2um N 10 W 4um 30 e ween N 5 W 8um Ne g
175. thout ISS calibration are directly used for all of the calculations from step 2 to step 8 in Section 4 2 4 As the on wafer standards are all assumed to be ideal e g ideal OPEN and SHORT relatively ideal on wafer load resistor with a capacitive parasitics the single step calibration results are expected to be less accurate than the two step calibration results Fig 6 1 compares single step and two step four port calibration results for the HP 8510XF system from 2 GHz to 110 GHz As expected the Y parameters from single step calibration are not as well behaved as the Y parameters from two step calibration However the overall values of Y parameters are still fairly accurate particularly for critical parameters like imaginary part of Y which indicates the gate capacitance To further analysis the source of the small ripples the same measurements are repeated using another system a HP 8510C system from 2 GHz to 26 GHz The results are shown in Fig 6 2 The 8510C results are much less noisy than the 8510XF result even when compared over the same frequency range Given the measurement system dependence and the frequency dependence these ripples in single step calibration are believed to be due to the system errors that are not calibrated out by the on wafer standards Since the SVD based numerical four port solution can give information of the singularity of the solution examining the condition number during single step calibration using t
176. to verify the developed model by performing model validation experiments The idea is to provide an environment as close as possible to the real measurement and to verify whether the model can predict the measured results Only after the model passes the validation test the model can be transferred to designers Note that the measurements used for model parameter extraction can be quite different from the measurements used for model validation For example distortion measurement with high input power is not used for parameter extraction but it is necessary for verifying the linear model developed as distortion exists in real applications In this chapter the DC AC and nonlinear performance of a BSIM4 model is verified BSIMA model is one of the widely used MOS transistor model for RF designs In BSIMA the moderate inversion region is modeled by mathematical smoothing functions interpolating between physics based approximations in the weak and strong inversion regions instead of physics based surface potential approximation that can cover all levels of inversion Its accuracy in linearity simulation particularly in moderate inversion region needs to be experimentally evaluated since an IP3 sweet spot exists in this region 118 7 Linearity measurement and simulation The two tone on wafer system in Fig 1 6 is used to measure the output spectrum at the drain of the examined NMOS transistor 22 Fig 7 1 shows the simplified block diag
177. tor S parameters S are obtained using 5 7 and converted to Y parameters The de embedded results using the popular open short 14 pad open short 17 both of which are based on lumped equivalent circuits are compared with the analytical four port solution in Section 4 2 Open Short Pad Open Short 02 nma 4 port SVD solution 4 port analytical solution 0 L 0 50 100 0 50 100 frequency GHz frequency GHz Fig 5 2 Comparison of Y parameters between open short pad open short SVD based numerical four port solution and analytical four port solution The SVD results are practically identical to the analytical four port results in Section 4 2 which are carefully chosen among several possible solutions based on 98 singularity considerations With SVD singularity is naturally handled 36 and no special measurements need to be taken Redundancy is handled by SVD as well 81 The SVD and analytical four port results are significantly different from the open short and pad open short results The frequency dependence of Y from four port results is more physical To observe this better we plot out the effective gate resistance R R 1 and effective gate capacitance C 1 2a fS UY 27 in Fig 5 3 While open short and pad open short give the same R as four port solutions they give a very strong and unphysical fr
178. ts with and without switching error correction The SVD based numerical four port solution in Section 5 2 is applied 6 3 1 Quantify error terms using S parameters As discussed in Section 5 4 although E E E and E are no longer the original S parameters of the four port network it does not affect the relative importance of the error terms Fig 6 7 shows the magnitude of the error terms in E E E and E The normalization factor t does not affect the comparison between the diagonal elements and the non diagonal elements in each 2x2 matrix From Fig 6 7 it is clear that this assumption limits the application of 8 term model on single step calibration First amp 4 are not that small when compared with e e even at low frequencies 115 Similar situation exist when evaluating the elements in E4 Secondly as frequency increases the difference between the diagonal elements and the non diagonal elements in E and E reduces which means the leakage errors become comparable to the dominant errors Note that although the magnitude of the diagonal elements of E and E are 10dB larger than the diagonal elements of E and E4 it cannot be concluded that the diagonal elements of E and E are dominant elements because the elements in E2 and E are normalized S parameters e mo E g e ul ul 0 n
179. undancy available from the 18 measurements of five on wafer standards e g singularities 36 These issues are ideally handled with the SVD based numerical solution in 47 Although the SVD based four port solution cannot give insight views of the parasitic network it is easy to apply with multiple combinations of on wafer standards and provides an indication of the validity of the solution This dissertation presents detailed derivation of the analytical solution and the numerical solution and demonstrates their utility on a 0 13um RF CMOS technology from 2 to 110GHz for both two step calibration and single step calibration 1 3 4 Single step calibration With a general four port solution it is possible to solve the four port network between the two ports inside VNA and the two ports at the device terminals The known standards are fabricated on the same wafer as the desired device This idea of utilizing on wafer standards to remove systematic errors and on wafer parasitics in a single step was not new Actually it was introduced at the very beginning of VNA error correction However it is not widely used for transistor characterization for several reasons First error calibration using ISS standards are repeatable and traceable which can be verified using stated references For example National Institute of Standards and Technology NIST in USA and the National Physical Laboratory NPL in UK provide and maintain reference standards
180. ured IIP3 is not perfect because IP3 is not measured in a very fine biasing step 8 5 can predict IP3 sweet spot accurately for devices with N 10 20 and 64 Note that the sweet spot Jy decreases from 35uA um for N 10 to 20uA um for N 64 Kss g for N 10 20 and 64 are so close that only the zero Ks point for N 64 is shown in Fig 9 4 for reference 153 W 2um L 90nm Vps 0 8V f0 5GHz Af 100KHz N e oa e IIP3 dBm 5 lcu ao e ciu a Symbol Measurement Line Analytical IIP3 did 0 20 40 60 80 100 Jog rAlum Fig 9 4 Measured and analytical IIP3 versus J for devices with N 10 20 and 64 Analytical IIP3 is calculated using 8 5 9 2 3 Frequency dependence Fig 9 5 shows measured IIP3 at 2 5 and 10GHz for devices with N 10 and 64 a total width of 20um and 128um For N 10 IIP3 at 2 5 and 10GHz are practically identical For V 64 IIP3 increases as frequency increases This frequency dependence can only be attributed to C and C in 8 5 However IIP3 calculated using 8 5 does not show a strong frequency dependence for N 64 as shown in Fig 9 6 a To further explore this C is added to the small signal equivalent circuit Fig 9 6 b shows IIP3 calculated using Volterra series with C added at multiple frequencies The strong frequency dependence of calculated IIP3 with C is similar to the frequency d
181. used for over 10 years One of its well established technique is the so called short open load through SOLT calibration or thru open short match TOSM calibration which is implemented on all modern VNAs 34 During SOLT calibration 12 measurements on four standards are done to solve the 12 error terms 6 from forward mode and 6 from reverse mode The 6 forward measurements are three forward reflection measurements on OPEN SHORT and LOAD standards S one forward isolation measurement on two port LOAD S one forward match and one forward transmission measurements on two port THRU S and S Similarly the 6 reverse measurements are S on OPEN SHORT and LOAD S on two port LOAD S and S on two port THRU The accuracy of SOLT calibration depends critically on the fabrication and modeling tolerance of the standards Additional procedures such as improving the calibration standard models or the use of standards initially characterized with respect to the reference calibration can enhance the accuracy of the SOLT calibration 84 85 Fig 3 16 shows the SHORT LOAD THRU standards on a Cascade impedance standard substrate ISS 101 190 58 OPEN is defined as an open in air with a minimum distance of 250um above the chuck surface LOAD is built using two thin film 100 Q resistors in parallel 86 13 78 The four standards are characterized using physical measurements and verified by National Institute of Standards an
182. using BSIM4 model are compared with calculated results For the frequencies examined in this work 2GHz 5GHz and 10GHz open short de embedding is valid for the layout design used Thus the pads and interconnections are modeled using open short equivalent circuit consisting of three series and three shunt elements in Cadence However this added parasitics network does not affect IIP3 that much 8 1 First order IP3 theory Fig 8 1 shows the small signal equivalent circuit used for analytical IP3 analysis vy V cos c t cos e t is the two tone input signal e 27f and 2z f fi and are the frequencies of the two tone excitation spacing by Af 100KHz R is the source resistance while R is the load resistance Here R and R are both 509 C and C are the small signal gate to source capacitance and drain to substrate capacitance with values extracted from S parameters First order IP3 theory considers nonlinear transconductance only The linear and the second and third order nonlinear transconductance can be identified with the coefficients of Taylor expansion as _ Aps EU Ll DOU as 6 Ve 8 1 The small signal nonlinear current source i can then be approximated by the first three order nonlinearities as 133 gt 2 3 Las S nVgs K22 V es K3s V 8 2 The first order input referred IP3 IIP3 for the small signal equivalent circuit in Fig 8 1 is then calculated as 1 1 C R
183. utput conductance and cross terms are grouped as Aj A A3 and A4 1 Kg 1 A 7K reqs Pw 73 9 8 6 2 1 1 2 A KeK 28 2 tas 285 42 3 Koss zo 8 7 2 l A K32 287 26 03 Fs Ei Bus gt 8 8 2 2 A 5 gis 8 9 where Z Z 20 2Z amp v Z Z Y CY a 2 Z 2Z 0 Z Z 2 Z 0 Z Zi e 2Y Co Y 0 1 138 Z Zi Z Z Z Z 20 2Z Z Z 20 6Z Z Z e v Z Z Z Qa 2Z Qa 6Z e Z Z Z Co Z 2 2Z a Q 1 Y o Z 0m D a Oa g joC l R 3 Ai Ao As and Ay are functions of the 2 and 3 order nonlinear output conductance and cross terms The values of the cross terms especially K2 and Kxg g in Aj are comparable to g in moderate inversion region as shown in Fig 8 3 In strong inversion region g saturates and K3z reduces to zero A1 Ao As and A4 will be comparable to K3 g even if they are close to zero as we will show below This indicates that Aj A As and A4 are all important for IP3 modeling Therefore the IP3 expressions without cross terms in 22 25 are not accurate enough Note that the complete IP3 expression derived in 26 is a special case of 8 5 at low frequencies Furthermore the numerical results in 26 were calculated by neglecting various nonlinear terms and the derivatives in the nonlinear coefficients were
184. ve 50GHz The distributive on wafer parasitics is essentially a four port network between the probe tips and the transistor terminals This dissertation develops two general four port techniques that can solve the on wafer parasitics four port network and demonstrates their utility on a 0 13um RF CMOS technology One is an analytical solution solving V the Y parameters of the four port parasitics network The other one is a numerical solution solving the T parameters of the four port parasitics network Even though the two four port solutions are developed for on wafer parasitics de embedding at the very beginning the two solutions do not make any reciprocal and symmetric assumptions of the solved four port network and can be used for single step calibration which solves the four port network between perfect VNA receivers and transistor terminals In this case both systematic errors and on wafer parasitics are included in one four port network and can be removed in a single step With switch error removed single step calibration can provide as accurate results as two step calibration from 2 110GHz Another topic that draws the attention of RFIC designers is the linearity nonlinearity of CMOS transistors Experimental IP3 results on a 90nm RF CMOS technology are presented at different biasing voltages different device width and different fundamental frequencies To understand the biasing device width and frequency dependence of IP3 a compl
185. w graph in Fig H 3 The system directivity ex can be best understood when an ideal match load is under test Part of the incident a is reflected back to 5 through the branch labeled e independent of the L Thus when measuring I there must be some residual signals measured 2 port Error Perfect Adaptor Sweep Reflectometer Oscillator 4 error terms Fig H 2 The combined two port error adaptor for one port S parameter measurement 202 Fig H 3 Signal flow graph of the two port error adaptor in one port measurement H 2 Relationship between I and L 7 Denoting T b a and I a b in H 1 T and L can be related through even exei Er r e T7 e T H 2 By measuring three standards with known T three equations containing the unknown error terms are built Then the error terms ey Een and e can be solved After that I for any measured T can be obtained using T e poe TE EEUU H 3 Je t i yi Note that only three error terms e evea and e need to be solved for error correction purpose This is because of the ratio nature of S parameter measurement The most widely used standards are OPEN SHORT and LOAD Without specification LOAD standard in this work means matched Z load Fig H 4 show the magnitude of the solved error terms 5 Coo gt er0 o1 and lei 203 0 2 T T j T F a
186. x1 SHORT is standard 2 in step 3 Select S11C enter 3 x1 LOAD is standard 3 in step 3 MATCH REV MATCH FWD ISOL N REV ISOL N using the corresponding class assignment values from Table E 1 c Press SPECIFY CLASS DONE Label classes Press LABEL CLASS Select S11A enter OPEN 6 5 and then LABEL DONE Select S11B enter SHORT 3 3 and then LABEL DONE Select S11C enter LOAD 50 and then LABEL DONE 189 Do the same for S22A S22B S22C FWD TRANS REV TRANS FWD MATCH REV MATCH FWD ISOL N REV ISOL N using the corresponding standard labels from Table E 1 c Press LABEL CLASS DONE 6 Label the calibration kit Press LABEL KIT enter the title of the calibration kit e g ISSI00UM and then TITLE DONE KIT DONE MODIFIED 7 Save calibration kit in VNA and floppy disk Press SAVE To save the calibration kit to CALKIT 1 in the VNA memory Press DISCI in the MORSIAN AVIDON block the select STORE CALKITI 2 CALKIT 1 enter a filename e g CK 100 The calibration kit will be saved on a floppy disk with name CK_ 100 which can be loaded into VNA later using LOAD CALKIT1 2 CALKIT 1 190 Calibration Kit Coefficients 191 0 GVO uoHejos es19 8s pesn skemye SI Aejop os GVO I UORneJOS pJeMJOJ oosd pue qsue unoozc GUM nH L soTnjo
187. ximum singular value for four standard T SE EE ES EEEREN E 198 Condition number minimum and maximum singular value for five standards NT 200 Condition number for multiple number of standards 200 The block diagram for a one port measurement seeesss 201 xvii Fig H 2 Fig H 3 Fig H 4 Fig I 1 Fig J 1 Fig J 2 Fig J 3 Fig J 4 The combined two port error adaptor for one port S parameter Ifie d SUT CHIC Ho o coca aab usq tiM CUR MM dioe qr de 202 Signal flow graph of the two port error adaptor in one port Measurement ao owes Ee secre Saddle Fete taii edd edite dee 203 The three error terms solved using OPEN SHORT and LOAD sj efi oa MN MID NE E HEN 204 The small signal equivalent circuit used for IP3 analysis 208 The small signal equivalent circuit used for IP3 analysis 211 The linearized equivalent circuit for solving first order kernels 212 The equivalent circuit for solving the second order kernels 213 The equivalent circuit for solving the third order kernels 215 xvili Table 8 1 Table B 1 Table E 1 Table G 1 LIST OF TABLES Definition of nonlinearity coefficients of nonlinear drain current 136 Transformation between two port H Y Z and ABCD representations 171 Calibration Kap Coefficients
188. y Noise parameters are not measured due to lack of equipments The transistor with single sided contact and M 1 does not have the largest R as expected Instead the transistor with double sided contact and M 1 gives the largest R The reason may lies on the narrow metal connection from the reference plane to the double sided gate contact while a much wider metal connection is used in single sided gate contact transistor in Fig 2 7 b However it is not possible to move the reference plane to the end of the narrow gate metal inside the substrate ring as it is impossible to layout de embedding standards in such small area Fortunately this problem can be solved by using different metal connections to the gate For example the transistor layout with M 4 greatly reduces the resistance on the narrow metal lines because it has four similar parallel connections Fig 2 10 d shows that f max IS quite different for the three transistors The device with single sided gate contact and M 1 and the transistor with double sided contact and M 4 gives the highest f This max agrees with the lowest R of these two transistors 38 150 T double gate M71 single gate M21 double gate M 4 100 J mS N 50 u u pl SSS 6t lj e g LE t a ta f GHz Fig 2 10 Extracted parameters for three NMOS transistors wi
189. y 5 or S Coo 3 8 ees JS S e M 21 30 DUT DUT l es Tens pur 3 9 where A por aa ras 5 Sper Sets The 6 5 after normalization error terms for forward mode are directivity error e port match error e and e frequency response error ee and epez The leakage errors ep and e cannot be completely determined because they can only be measured as products as shown in 3 8 and 3 9 Thus only e and epe can be solved which is sufficient for calibration This is equivalent to normalizing the error terms by e as illustrated in Fig 3 14 with the normalized values on the branches The 6 error terms for reverse mode are directivity error amp port match error e and e frequency response error e e and e e 55 Fig 3 14 Normalized 6 term error model for forward mode Since the 6 term model in Fig 3 14 involves lumped error terms these error terms no longer represent signal paths instead they are just mathematical coefficients To ce p separate the error terms in forward mode and reverse mode a superscript is used to identify the waves and error terms in reverse mode The normalized 6 term model for reverse mode is illustrated using the signal flow graph in Fig 3 15 The measured wave rations S and S are related to S as 80 R d p r 3 exe s2 eA cour S e
190. y M thru k Yy Y i h Y The elements of Y Z and Y are v M open M open Kay h v M open M open n h 176 C 13 C 14 C 15 C 16 C 17 C 18 y BE TR p C 19 Z lz ME j n C 20 Z l Zub Zt prr C 21 Y x ye een C 22 men a OPEN b SHORT1 c SHORT2 d THRU Fig C 6 Equivalent circuits and layouts of OPEN SHORTI SHORT2 and THRU standards for improved three step 177 C 4 Transmission line de embedding The on wafer parasitics and the desired device can be represented as a cascade of several two port networks as shown in Fig C 7 The input and output networks which are composed of the probe pads and the interconnections leading to the device are represented using ABCD parameters A and 49 A4 4 4 and AO A 4777 where 4 and A are the ABCD parameters of the probe pads at input and output 4 and A are ABCD parameters of input and output interconnections Fig C 8 shows the equivalent circuits and layouts for the THRUI and THRUZ2 standards The two transmission line structures have different length and The measured ABCD parameters of the desired device is AM Ag gu AUT C 23 Thus the measured ABCD parameters of THRUI and THRU2 are AMA n AN gAsthrul OUT 4PADI 44 65 A PAD C 24 AM diria n GIN gAsthiru2 JOUT _ PADI ul gPAD2 C 25 The ABCD parameters of a transmission line with length can be calcu
191. y little impact on IP3 sweet spot since they are much smaller than A and A near the zero K3g point Since A is negative and A is positive around the zero Kse Vos the impact of A and A on the shift of IP3 sweet spot are opposite A moves IP3 sweet spot 140 to lower V and A moves IP3 sweet spot to higher V when compared with the zero K3g Vos The A and A terms however are important at higher V N 64 W 2um L 90nm Vos 0 8V gm m K3 lg ATtA2 A3 A4 A1 A2 A3 and A4 1 1 0 2 0 327 0 3754 0 7 Ves V Fig 8 4 a The denominator in 8 5 versus V b Each term in the denominator of 8 5 versus V Vps 0 8V Fig 8 5 shows the impacts of Ai A As and A4 on IIP3 Since A is much larger than A a V lower than the zero K3z V is observed at IP3 sweet spot Although the deviation between IP3 sweet spot V and zero K3 V is dominated by Ai adding the other three elements can model IP3 sweet spot better At high V K3 g is close to zero and is comparable with the value of Ai A As and A4 as shown in Fig 8 4 b Thus Ai A A3 and A all affect the value of IP3 at high V 141 significantly as shown in Fig 8 5 Therefore all of the nonlinear coefficients are important for IP3 modeling including cross terms N 64 W 2um L 90nm Vos 0 8V f0 5GHz Af 100KHz
192. yzer VNA several RF cables and connectors two RF probes and a probe station The Agilent VNA8510C system in Fig 1 2 consists of four equipments and can work up to 50GHz with proper configuration The VNA8510C system is mainly used to measure 26 5GHz and 40GHz S parameters in this dissertation due to the limitation of RF cables and connectors The 110GHz data is measured by an Agilent VNA 8510XF system with helps from IBM Essex Junction One of the most accurate coplanar ground signal ground GSG probes 3 the Cascade RF infinity probe is used to contact the on wafer structures An Alessi manual probe station with a round 6 chuck is used to provide mechanical support and motorization controls of the wafer Two magnetic positioners are stuck to the metal top plate of the probe station to support the RF probes and provide motorization controls of the probes E Probe2 e mma a Power Supply Aro A ZA v EX Probe Stationge wee Fig 1 2 A typical two port system for on wafer S parameter measurement However the system is not perfect Random and systematic measurement errors are involved in the measured S parameters 12 The random errors e g thermal drift cannot be removed systematically but the systematic errors can VNA usually provides several standard techniques for correcting systematic errors e g short open load thru SOLT These techniques utilize accurate standards on an impedance standard substrate

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