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V5100A/PG2

1. 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 Off 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 INT SRC 5 VECTOR PRIORITY REGISTER 100a0 INT SRC 5 DESTINATION REGISTER 100b0 INT SRC 6 VECTOR PRIORITY REGISTER 100c0 INT SRC 6 DESTINATION REGISTER 100d0 INT SRC 7 VECTOR PRIORITY REGISTER 100e0 INT SRC 7 DESTINATION REGISTER 100f0 INT SRC 8 VECTOR PRIORITY REGISTER 10100 INT SRC 8 DESTINATION REGISTER 10110 INT SRC 9 VECTOR PRIORITY REGISTER 10120 INT SRC 9 DESTINATION REGISTER 10130 INT SRC 10 VECTOR PRIORITY REGISTER 10140 INT SRC 10 DESTINATION REGISTER 10150 INT SRC 11 VECTOR PRIORITY REGISTER 10160 INT SRC 11 DESTINATION REGISTER 10170 INT SRC 12 VECTOR PRIORITY REGISTER 10180 INT SRC 12 DESTINATION REGISTER 10190 INT SRC 13 VECTOR PRIORITY REGISTER 101a0 INT SRC 13 DESTINATION REGISTER 101b0 INT SRC 14 VECTOR PRIORITY REGISTER 101c0 INT SRC 14 DESTINATION REGISTER 101d0 INT SRC 15 VECTOR PRIORITY REGISTER 101e0 INT SRC 15 DESTINATION REGISTER 101f0 HAWK INTERNAL ERROR VECTOR PRIORITY REGISTER 10200 HAWK INTERNAL ERROR DESTINATION REGISTER 10210 IPI 0 DISPATCH REGISTER PROC 0 20040 IPI 1 DISPATCH REGISTER PROC 0 20050 IPI 2 DISPATCH REGISTER PROC 0 20060 2 112 Computer Gr
2. Writes to this register must be enveloped by a period of time in which no accesses to SDRAM occur The requirements of the envelope are that all SDRAM accesses must have completed before the write starts and none should begin until after the write is done A simple way to do this is to perform at least two read accesses to this or another register before and after the write Additionally sometime during the envelope before or after the write all of the SDRAMs open pages must be closed and the Hawk s open page tracker reset The way to do this is to allow enough time for at least one SDRAM refresh to occur by waiting for the 32 bit Counter see section further on to increment at least 100 times The wait period needs to happen during the envelope 3 66 Computer Group Literature Center Web Site Programming Model ram e f g h en ram e f g h en enables accesses to the corresponding block of SDRAM when set and disables them when cleared Note that ram a b c d en are located at FEF80010 refer to the section on SDRAM Enable and Size Register Blocks A B C D in a previous section They operate the same for blocks A D as these bits do for blocks E H ram e f g h siz0 3 These control bits define the size of their corresponding block of SDRAM Note that ram a b c d siz0 3 are located at FEF80010 They operate identically for blocks A D as these
3. FEF80070 DPE A FEF80078 DPE DH FEF80080 DPE DL FEF80090 I2 PRESCALE VAL FEF80098 3 3 3 5 FEF800A0 el el el el FEF800A8 12 DATAWR 800 0 12 DATARD 5 8 8 5 FEF800C0 2 517 SIZ 2 SIZ SIZ 8 8 8 8 FEF800C8 RAM E BASE RAM F BASE RAM G BASE RAM H BASE FEF800D0 ol FEF800E0 i APE TT APE AP B S 8 FEF800E8 APE_A FEF80100 CTR32 gs FEF88300 88000 EXTERNAL REGISTER SET FEFS8FFF8 gt 5 lale sulele salS zi98 9 x 9 9559 8s SX http www motorola com computer literature 3 37 System Memory Controller SMC Notes 1 All empty bit fields are reserved and read as zeros 2 All status bits are shown in italics 3 All control bits are shown with underline 4 control and status bits are shown with italics and underline Detailed Register Bit Descriptions The following sections describe the registers and their bits in detail The possible operations for each bit in the register set are as follows R The bit is a read only status bit R W The bit is readable and writable R C The bit is cleared by writing a one to itself The possible states of the bits after local and power up reset are as defined below P The bit is affected by power up reset PURST
4. A gt K A ACK from Slave Devic BEGIN e READ STATUS REG LOAD 09 START CONDITION CONTROL REG LOAD DEVICE ADDR WR BIT TO TRANSMITTER DATA REG Y LOAD DATA1 DATA n TO PC TRANSMITTER DATA REG READ PC STATUS REG LOAD WORD ADDR 1 2 TRANSMITTER DATA REG READ FC STATUS REG READ PC STATUS REG LOAD 05 STOP CONDITION CONTROL REG LOAD DUMMY DATA TO PC TRANSMITTER DATA REG READ FC STATUS REG Stop condition should be generated to abort the transfer after a software wait loop 1ms has been expired Figure 3 8 Programming Sequence for 2 Page Write 3 30 Computer Group Literature Center Web Site Functional Description 2 Sequential Read The PC sequential read can be initiated by either an PC random read described here or an current address read The first step in the programming sequence of an PC random read initiation is to test the 2 cmplt bit for the operation complete status The next step is to initiate a start sequence by first setting the 12 start and 12 enbl bits in the IC Control Register and then writing the device address bits 7 1 and write bit bit 020 to the IC Transmitter Data Register The i2 cmplt bit is
5. Writes to this register must be enveloped by period of time in which no accesses to ROM Flash Block A occur A simple way to provide the envelope is to perform at least two accesses to this or another of the SMC s registers before ROM A BASE rom a 64 and after the write These control bits define the base address for ROM Flash Block A ROM A BASE bits 0 11 correspond to PPC60x address bits 0 11 respectively For larger ROM Flash sizes the lower significant bits of ROM A BASE are ignored This means that the block s base address will always appear at an even multiple of its size ROM A BASE is initialized to FFO at power up or local bus reset Note that in addition to the programmed address the first 1Mbyte of Block A also appears at FFF00000 FFFFFFFF if the rom a rv bitis set and the rom b rv bit is cleared Also note that the combination of ROM A BASE and rom a siz should never be programmed such that ROM Flash Block A responds at the same address as the CSR SDRAM External Register Set or any other slave on the PowerPC bus rom a 64 indicates the width of ROM Flash being used for Block A When rom 64 is cleared Block is 16 bits wide where each half of SMC interfaces to 8 bits When rom a 64 is set Block A is 64 bits wide where http www motorola com computer literature 3 53 System Memory Controller SMC each half of the SMC interfaces to
6. 332222222222111111111 1 Off 1098765 43 21098765 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 SP REGISTER 010e0 TIMER FREQUENCY REPORTING REGISTER 010f0 TIMER 0 CURRENT COUNT REGISTER 01100 TIMER 0 BASE COUNT REGISTER 01110 TIMER 0 VECTOR PRIORITY REGISTER 01120 TIMER 0 DESTINATION REGISTER 01130 TIMER 1 CURRENT COUNT REGISTER 01140 TIMER 1 BASE COUNT REGISTER 01150 TIMER 1VECTOR PRIORITY REGISTER 01160 TIMER 1DESTINATION REGISTER 01170 TIMER 2 CURRENT COUNT REGISTER 01180 TIMER 2 BASE COUNT REGISTER 01190 TIMER 2 VECTOR PRIORITY REGISTER 011a0 TIMER 2 DESTINATION REGISTER 011b0 TIMER 3 CURRENT COUNT REGISTER 011c0 TIMER 3 BASE COUNT REGISTER 011d0 TIMER 3 VECTOR PRIORITY REGISTER 011e0 TIMER 3 DESTINATION REGISTER 011f0 INT SRC 0 VECTOR PRIORITY REGISTER 10000 INT SRC 0 DESTINATION REGISTER 10010 INT SRC 1 VECTOR PRIORITY REGISTER 10020 INT SRC 1 DESTINATION REGISTER 10030 INT SRC 2 VECTOR PRIORITY REGISTER 10040 INT SRC 2 DESTINATION REGISTER 10050 INT SRC 3 VECTOR PRIORITY REGISTER 10060 INT SRC 3 DESTINATION REGISTER 10070 INT SRC 4 VECTOR PRIORITY REGISTER 10080 INT SRC 4 DESTINATION REGISTER 10090 http www motorola com computer literature 2 111 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Table 2 19 MPIC Register Map Continued
7. S S S S Name al al Sj o NNNNA Operation READ ZERO READ ZERO READ ZERO z 55 Reset X X X Jalala xxx i2 start When set the master controller generates a start sequence on the C bus on the next write to the I7C Transmitter Data Register and clears the i2 cmplt bit in the Status Register After the start sequence and the PC Transmitter Data Register contents have been transmitted the PC master controller will automatically clear the 12 start bit and then set the 12 cmplt bit in the Status Register http www motorola com computer literature 3 63 System Memory Controller SMC i2 stop i2 ackout i2 enbl 2 Status Register When set the C master controller generates a stop sequence on the C bus on the next dummy write data don t care to the PC Transmitter Data Register and clears the 12 bit in the C Status Register After the stop sequence has been transmitted the 2 master controller will automatically clear the 12 stop bit and then set the 12 cmplt bit in the Status Register When set the C master controller generates an acknowledge on the C bus during read cycles This bit should be used only in the PC sequential read operation and must remain cleared for all other I C operations For PC sequential read operation this bit should be set for every single byte received excep
8. 1 25 Table 1 13 MODRST DIERGSISIBE 1 26 Table t 14 TREN Bit lt iride dix iae b boton 1 27 Fable 1 15 MAST37V Access Registers uses etti be rk per Pope dE Re ree 1 28 Table 1 16 Extended Features Register 1 31 Table 1 17 Extended Features Register 2 cea rrr tris eR RS VERE VUES 1 33 Table 2 1 Slave Response Command 2 0222 2 8 Table 2 2 PPC Master Transaction Profiles and Starting Offsets 2 11 Table 2 3 PPC Master Write Posting enar anes etes 2 12 Table 2 4 Master Read Ahead eios rae reet tis oberen E 2 12 Table 2 3 PPL Master Transiter Types is snivewaissshesessteiaptvcabee pecie t etie t eapite 2 14 Table 2 6 PPC Arbiter Pin 2 15 Table 2 7 PCI Slave Response Command 2 23 Table 2 8 PCI Master Command Codes Lii iecore tope qe Re LAE RE DEP 2 27 Table 2 9 PCI Arbiter Pin Descciptlon 2 34 Table 2 10 Fixed Mode Priority Level Setting iue petro Reb Erbe 2 35 Table 2 11 Mixed Mode Priority Level Setting ees
9. SMC SDRAM Speed Attributes 3 68 SMC tben 3 73 SMC Vendor Device Register 3 39 Spurious Vector MPIC 2 118 Timer Basecount MPIC 2 120 Timer Current Count MPIC 2 119 Timer Destination 2 122 Timer Frequency MPIC 2 118 Timer Vector Priority 2 121 Vendor Identification MPIC 2 116 WDTXCNTL 2 92 WDTXxSTAT 2 96 writing to the control registers 3 74 related documentation ordering B 1 RESET and ABORT Switch 1 2 Revision ID 3 40 Revision ID Register 2 70 Revision ID Class Code Registers 2 101 Revision ID General Control Register 3 39 ROM Block A Size Encodings 3 54 Block B Size Encoding 3 57 Flash 3 14 Flash A Base Address control bits 3 53 Flash A size encoding 3 54 Flash A Width control bit 3 53 Flash B Base Address control bits 3 56 Flash B Width control bit 3 57 ROM Block B Size Encoding 3 57 ROM Speed Attributes Register SMC 3 58 ROM Flash A Base Size Register SMC 3 53 ROM Flash B Base Size Register SMC 3 56 rom a 64 3 53 ROM A BASE 3 53 rom a en 3 55 rom a rv 3 54 rom a rv and rom b rv encoding 3 54 rom 512 3 54 rom a we 3 55 IN 8 Computer Group Literature Center Web Site rom b 643 57 ROM B BASE 3 56 rom b en 3 57 rom b rv 3 57 rom b siz 3 57 rom b we 3 58 Row Address 3 52 rwcb 3 45 S SBC mode 1 11 SBE COUNT 3 50 scb0 scb1 3 51 scien 3 47 scof 3 50 scrub counter 3 51 Scrub Write Enable control bit 3 51 Scrub Refresh Register SMC 3 51
10. trc0 1 2 Minimum Clocks for Trc 26000 8 26001 9 26010 10 26011 11 100 reserved 26101 reserved 26110 6 26111 7 tras0 1 Together tras0 1 determine the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its tRAS parameter These bits are encoded as follows Table 3 17 tras Encoding tras0 1 Minimum Clocks for tras 00 4 01 5 10 6 11 7 http www motorola com computer literature 3 69 System Memory Controller SMC swr dpl swr causes the SMC to always wait until four clocks after the write command portion of a single write before allowing a precharge to occur This function may not be required If such is the case swr be cleared by software 8 tdp determines the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its Tdp parameter When tdp is 0 the minimum time provided for Tdp is 1 clock When tdp is 1 the minimum is 2 clocks trp trp determines the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its Trp parameter When trp is 0 the minimum time provided for Trp is 2 clocks When trp is 1 the minimum is 3 clocks trcd determines the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its Trcd parameter When tred is 0 the minimum time provided for Tred is 2 clocks When tred is 1 the minimu
11. URSUS 3 14 ROMPI nesen EARE 3 19 TA III UI IT a a E 3 22 E yee whan 3 23 pue Ronda REDE MERE REUS 3 25 3 27 PCG iu 3 29 BC Sequential REAd 3 31 BLE CHD SN E 3 34 CSR ACCC SSCS r Vries HI e FER eV UE eC DER PES RIA bL REESE IHE PAESE 3 34 3 34 Chip CoS PAO vps T 3 35 lassus iieri dies m sack 3 35 CSR iuis 3 35 Register C I 3 36 Detailed Register Bit Descriptions repe ttt reete Deere nde 3 38 Vendor Device Beplstet us eeu HM PEN 3 39 Revision ID General Control Register emere in 3 39 SDRAM Enable and Size Register Blocks A B C D 3 41 SDRAM Base Address Register Blocks A B C D 3 43 CLK Prequency BESIDE aue topo napon prep ipte Rob Ripe piri d 3 44 EOC C apnd Dic 3 45 Eror Loser RU RI SR
12. Offset 01090 Bit 3 3 2 2 2 2 2 272 2 2 2 1 1 1 1 1 1 1 1 1 I 1 0 9 8 7 6 5 493 2 1 0 9 8 7 OF 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Name PROCESSOR INIT fy ro Operation R R R R 5 E Reset 00 00 00 00 OP P1 PROCESSOR 1 Writing a 1 to P1 will assert the Soft Reset input of processor 1 Writing a 0 to it will negate the SRESET signal PO PROCESSOR 0 Writing a 1 to PO will assert the Soft Reset input of processor 0 Writing a 0 to it will negate the SRESET signal The Soft Reset input to the 604 is negative edge sensitive 2 116 Computer Group Literature Center Web Site Registers IPI Vector Priority Registers Offset 0 010A0 1 010B0 2 5010 0 IPI 3 801000 Bit Name UJ 2 2 2 2 2 2 9 8 7 6 5 4 2 2 2 31241 2 1 1 1 I1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 IPI VECTOR PRIORITY PRIOR VECTOR Operation R W R R W Reset L MA ASYN 000 0 00 00 MASK ACT PRIOR VECTOR MASK Setting this bit disables any further interrupts from this source If the mask bit is cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated ACTIVITY The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to a one when its associated
13. 3 20 Table 3 7 PPC60x Bus to ROM Flash Access Timing Bi SP TOO TELS c 3 20 Table 3 8 PPC60x Bus to ROM Flash Access Timing NIS 3 21 Table 3 9 SU Y ao oo bd Heide eee Ml pe MAE 3 36 Table 3 10 Block A B C D E F G H Configurations eese 3 42 Table 35 11 ROM Block A Size Encoding iios EH eati ues ide teeth baee 3 54 Table 3 12 rom ry and rom ry encoding 3 54 Table 3 13 Bead Wote ROMP lashes naue aab 3 55 Table 3 14 ROM Black B Size Encoding eene tipi ederet 3 57 Table 3 13 Speed Bit Encodings iuuenes oe 3 59 Table 3 16 Tre Encoding DRE EARS QUAE 3 69 ras SO T 3 69 Table 3 18 Deriving tras trp trcd and trc Control Bit Values SPD DTM sro Em 3 78 Table 3 19 Programming SDRAM SIZ Bus erret taken 3 81 Table 3 20 Address Lists for Different Block Size 3 85 Table 3 21 Syndrome Codes Ordered by Bit m Error auis ette re 3 86 Table 3 22 Single Bit Errors Ordered by Syndrome 3 87 Table 4 1 MPIC Interrupt ASSIEBIDEDE eo renes 4 1 Table 4 2 PRC TSA Inte
14. Writes to this register must be enveloped by a period of time in which no accesses to ROM Flash Block B occur simple way to provide the envelope is to perform at least two accesses to this or another of the SMC s registers ROM B BASE before and after the write These control bits define the base address for ROM Flash Block B ROM B BASE bits 0 11 correspond to PPC60x address bits 0 11 respectively For larger ROM Flash sizes the lower significant bits of ROM B BASE are ignored This means that the block s base address will always appear at an even multiple of its size ROM B BASE is initialized to FF4 at power up or local bus reset Note that in addition to the programmed address the first 1Mbyte of Block B also appears at FFF00000 FFFFFFFF if the rom b bit is set Also note that the combination of ROM B BASE and rom b 517 should never be programmed such that ROM Flash Block B responds at the same address as the CSR SDRAM External Register Set or any other slave on the PowerPC bus Computer Group Literature Center Web Site Programming Model rom b 64 rom b 64 indicates the width of ROM Flash device devices being used for Block B When rom b 64 Is cleared Block B is 16 bits wide where each half of the SMC interfaces to 8 bits When rom b 64 is set Block B is 64 bits wide where each half of the SMC interfaces to 32 bits rom b 64 matches the value that was on the RD3 pin at power u
15. 2 64 Dynamically Changing I O Interrupt Configuration 2 64 POIROT SE 2 65 Interropt Acknowledge 2 65 Bed DUE ooi pcd pa db Hed ca pd Expte 2 65 Ciment Task Priority e ipt 2 65 tc eter Serene ncn ener ee 2 66 Effects Interrupt eps nab des Sisco 2 66 ines ek eee 2 67 REGIS CIs assed N A 2 68 Vendor ID Device ID Besistefs 2 70 Revision ID BOglstet tenes 2 70 General Control Status Feature Registers eie etre erba 2 71 Arbiter PClI Arbiter Control Registers erts 2 73 Hardware Control Status Prescaler Adjust 2 77 TesUError Enable Register oer erret 2 79 Error Status Ree Stet nosne eenen esenee e EE E HU tips 2 82 PPC Error Address be roi Ub 2 84 Error 2 85 PCI Interrupt Acknowledge Register onere reps 2 87 PPG Slave Address 0 1 and 2 Registers
16. PPC FIFO A 64 bit by 8 entry FIFO 2 cache lines total is used to hold data between the PPC Slave and the PCI Master to ensure that optimum data throughput is maintained The same FIFO is used for both read and write transactions A 46 bit by 4 entry FIFO is used to hold command information being passed between the PPC Slave and the PCI Master If write posting has been enabled then the maximum number of transactions that may be posted is limited by the abilities of either the data FIFO or the command FIFO http www motorola com computer literature Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PPC Master For example two burst transactions make the data FIFO the limiting factor for write posting Four single beat transactions make the command FIFO the limiting factor If either limit is exceeded then any pending PPC transactions is delayed AACK and TA are not asserted until the PCI Master has completed a portion of the previously posted transactions and created some room within the command and or data FIFOs The PHB does not support byte merging or byte collapsing Each and every single beat transaction presented to the PPC Slave is presented to the PCI bus as a unique single beat transfer The PPC Master can transfer data either in 1 to 8 byte single beat transactions or 32 byte four beat burst transactions This limitation is strictly imposed by the PPC60x bus protocol The PPC
17. 3 1 Bit Ordonuo Conventio ipee cuero ite pi Se cao ru ed Rx lab M DE 3 1 e M 3 1 Or EI dI ETE 3 2 gni dr m E 3 6 JE T nue n o eT 3 6 Fon ben Reade WOES desea 3 6 GAL Reads WIS aR apia aria casts pete ate 3 6 SP Ue Lai 3 6 dem 3 7 SDRAM SPEE 3 7 SORAN BID TP R asd abate 3 9 EPC SUE Bue penas 3 9 Respondine to Address Transfers uenis se aR 3 9 Compeuns Data 3 9 I e p gi Misi pice 3 10 3 10 Ro EIN xd eni e ER 3 11 Cache Cohersney Ke SIC 3 11 Lot ache SHOE cepta ep D MM MD MEI Vn N 3 11 SORAM ECE ee 3 M etre 3 11 E 3 12 cag ro E 3 13 ROMPEI i
18. 110 PARB4 PARB3 PARB2 PARBO HAWK 6 5 111 PARB5 PARB4 PARB3 PARB2 PARBO HAWK PARB6 Notes 1 000 is the default setting in fixed mode 2 The HEIR setting only covers a small subset of all possible combinations It is the responsibility of the system designer to connect the request grant pair in a manner most beneficial to their design goals http www motorola com computer literature 2 35 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller When the arbiter is programmed for round robin priority mode the arbiter maintains fairness and provides equal opportunity to the requestors by rotating its grants The contents in HEIR field are don t cares when operated in this mode When the arbiter is programmed for mixed mode the 8 requestors are divided up into 4 groups and each groups is occupied by 2 requestors PARB6 and PARBS are defined in groupl PARB4 and PARB3 are defined in group 2 PARB2 and are defined in group 3 PARBO and are defined in group 4 Arbitration is set for round robin mode between the 2 requestors within each group and set for fixed mode between the 4 groups The levels of priority for each group are programmable by writing the HEIR field in the PCI Arbiter control register Table 2 11 describes all available setting for the HEIR field in mixed mode Ta
19. sng X090dd L 3 8pooeg Odd 51 616 Odd 1 r 1 Odl3 ed 1 sr d NEIS Odd 44 1eseu 500 0 lt lt Odld 519 51 Od e Eve IOd Odd PARIS 24 __ 2 aoe Hau Old 1S0H 12 ZN sng Od Figure 2 1 Hawk PCI Host Bridge Block Diagram 2 3 http www motorola com computer literature Hawk PCI Host Bridge amp Multi Processor Interrupt Controller 2 Functional Description Architectural Overview A functional block diagram of the Hawk s PCI Host Bridge PHB is shown in Figure 2 1 The PHB control logic is subdivided into the following functions PCI Slave PCI Master PPC Slave and PPC Master The PHB data path logic is subdivided into the following functions PCI FIFO PPC FIFO PCI Input PPC Input PCI Output and PPC Output Address decoding is handled in the PCI Decode and PPC Decode blocks The control register logic is contained in the PCI Registers and PPC Registers blocks The clock phasing and reset control logic is contained within the PPC PCI Clock block The FIFO structure implemented within PHB was selected to allow independent da
20. READ ONLY Reset 0 PL APE A is the address of the last PPC60x address bus parity error that was logged by the Hawk It is updated only when apelog goes from 0 to 1 http www motorola com computer literature 3 71 System Memory Controller SMC 32 Bit Counter Address FEF80100 PPP eee o ss e es Name CTR32 Operation READ WRITE Reset 0 PL CTR32 CTR32 is a 32 bit free running counter that increments once per microsecond if the FREQUENCY register has been programmed properly Notice that CTR32 is cleared by power up and local reset Note External Register Set When the system clock is a fractional frequency such as 66 67 MHz CTR32 will count at a fractional amount faster or slower than 1 MHz depending on the programming of the CLK FREQUENCY Register Address FEF88000 SFEF8FFF8 Bit seep s On 1 00 em EXTERNAL REGISTER SET Operation READ WRITE Reset XPL EXTERNAL REGISTER SET EXTERNAL REGISTER SET is user provided and is external to the Hawk It is enabled only when the tben en bit is cleared When the tben en bit is set the EXTERNAL REGISTER SET is disabled and the Hawk does not respond in its range except for the tben register at FEF88300
21. Sete ee rere 3 72 auri luigi c M 3 72 Dc P 3 73 DOR ans Considerations 3 74 Programming ROM Flash Devices occorre terret ron trennt e eei rr 3 74 Witting to the Contre ROO US StS A PON 3 74 Initializing SDRAM Related Control Registers 221421 3 75 SDRAM Speed 2 3 75 SDRAM ie PARURE 3 76 PE EEPROM e P 3 76 SDRAM Base Address and Enable eret eren 3 76 SDRAM Control Registers Initialization Example 3 77 Optional Method for Sizing SDRAM 3 83 ECC rd o E 3 86 CHAPTER4 Hawk Programming Details eee a es 4 1 PCI SEDIPS E OE NU HD 4 1 Hawk MPIC External o Ip EE RR EE 4 1 xs NIU Cm E 4 3 Ee M H 4 5 enis a 4 5 GE CSET E T 4 5 JH A 4 5 Emor and Handing Lucas ie 4 6 A A Oe it 4 7 Processa Memory DOIISID 4 9 MPK s curi e c 4 9 AME
22. 32 index cro flipped Oxfffffiff return crc http www motorola com computer literature B 13 MVMES100 VPD Reference Information B Configuration Checksum Calculation Code cssect checksum section description This component s purpose is to checksum the buffer pointed to x by the buffer pointer notes argument 1 buffer section to checksum argument 2 number of bytes in buffer return OxXX checksum UCHAR cssect nvram ptr count register UCHAR nvram ptr NVRAM buffer pointer register UINT count count number of bytes register UCHAR y isum sum for sum 0 count count 1 y nvram_ptrt t isum sum y if isum y isum sum isum 1 sum isum return sum return calculated checksum B 14 Computer Group Literature Center Web Site Vital Product Data VPD Introduction Serial Presence Detect SPD Checksum Calculation The checksum field Byte 63 designates the checksum for checking data integrity similar to parity for bytes 0 62 It is written during board production and can be used to verify the data integrity for these bytes The process for calculating the Checksum includes the following 1 Convert the binary information in byte locations 0 62 to decimal
23. B 8 Computer Group Literature Center Web Site Vital Product Data VPD Introduction VPD Definitions FLASH Memory Configuration Data The FLASH memory configuration data packet consists of byte fields which indicate the size organization type of the FLASH memory array The following table s further describe the FLASH memory configuration VPD data packet Table B 3 FLASH Memory Configuration Data Byte Field Field Field Description Offset Size Mnemonic Bytes 00 2 FMC MID Manufacturer s Identifier FFFF Undefined Not Applicable 02 2 FMC_DID Manufacturer s Device Identifier FFFF Undefined Not Applicable 04 1 FMC_DDW Device Data Width e g 8 bits 16 bits 05 1 FMC_NOD Number of Devices Sockets Present 06 1 FMC_NOC Number of Columns Interleaves 07 1 FMC_CW Column Width in Bits This will always be a multiple of the device s data width 08 1 FMC_WEDW Write Erase Data Width The FLASH memory devices must be programmed in parallel when the write erase data width exceeds the device s data width 09 1 FMC_BANK Bank Number of FLASH Memory Array 0 A 1 0A 1 FMC SPEED ROM Access Speed in Nanoseconds OB 1 FMC_SIZE Total Bank Size Should agree with the physical organization above 00 256K 01 512K 02 1M 03 2M 04 4M 05 8M A product may contain multiple FLASH memory configuration packets http www motorola com computer literature B 9
24. http www motorola com computer literature 3 65 System Memory Controller SMC I C Receiver Data Register Address FEF800BO0 Bit 1 1 12 11 eene IRIRI 8815 12 DATARD Operation READ ZERO READ ZERO READ ZERO READ Reset X X X 0 PL I2 DATARD The I2 DATARD contains the receive byte for data transfers During PC sequential read operation the current receive byte must be read before any new one can be brough in A read of this register will automatically clear the i2 datin bit in the I C Status Register SDRAM Enable and Size Register Blocks E F G H Address FEF800CO Bit 0 10 11 2 3 14 15 8 9 19 21 4 25 26 27 g 5120 20 5171 ram g 5122 22 Operation R W ram g siz3 23 R W ram h 5120 28 R W ram h siz1 29 R W ram h siz2 30 R W ram h 5123 31 R W R W R W Reset 0 PL ram e en R W ramesizO 4 R W rame 5121 5 R W ram e 5122 6 R W rame siz3 7 0 PL R W ram f en 0 0 0 R W ramfsizO 21 R W ramf siz2 R W ramf siz3 0 PL R W R R R ram h en X X X 0 0 0
25. 2 18 PCI Bos MENI 2 19 Address NISBpINE 2 19 M T M 2 22 I enis T nets 2 26 PCT MOSTON HU 2 26 Generating PEIC yels cie 2 29 Per Eu lbs HR 2 34 Pel Eel pas sace ELE 2 38 When PPC Devices are ig Encehsni u ues ee n iq 2 38 viii When Devices are Litle 2 39 PHB 2 40 Eror Handing ee a 2 41 hus I Er 2 42 PCUPPC Contention Handling ceret ers eite DER LEUR 2 45 TRANS AGING M D 2 48 PHB Hardware tug HERR 2 49 Multi Processor Interrupt Controller 1 2 0 0 00 000 000000000 000000000000 2 51 MPIC sacri ius 2 51 Arete p 2 51 External interrupt Int tfage a eese ertet 2 52 CSR s Readability m I 2 5
26. The base address for each block is software programmable At reset Block A s base address is FF000000 if Bank A is less than or equal to 8MB otherwise it is OxXF4000000 Block B s base address is FF800000 As noted above in addition to appearing at the programmed base address the first IMB of Block A B also appears at SFFF00000 FFFFFFFF if the reset vector enable bit is set The assumed size for each block is software programmable It is initialized to its smallest setting at reset The access time for each block is software programmable The assumed width for Block A B is determined by an external jumper at reset time It also is available as a status bit and cannot be changed by software Computer Group Literature Center Web Site Functional Description When the width status bit is cleared the block s ROM Flash is considered to be 16 bits wide where each half of the SMC interfaces to 8 bits In this mode the following rules are enforced a only single byte writes are allowed all other sizes are ignored and b all reads are allowed multiple accesses are performed to the ROM Flash devices when the read is for greater than one byte When the width status bit is set the block s ROM Flash is considered to be 64 bits wide where each half of the SMC interfaces with 32 bits In this mode the following rules are enforced a only aligned 4 byte writes should be attempted all other sizes a
27. Writes to this register must be enveloped by a period of time in which no accesses to SDRAM occur The requirements of the envelope are that all SDRAM accesses must have completed before the write starts and none should begin until after the write is done A simple way to do this is to perform at least two read accesses to this or another register before and after the write Additionally sometime during the envelope before or after the write all of the SDRAMs open pages must be closed and the Hawk s open page tracker reset The way to do this is to allow enough time for at least one SDRAM refresh to occur by waiting for the 32 Bit Counter described further on in this chapter to increment at least 100 times The wait period must happen during the envelope RAM A B C D BASE These control bits define the base address for their block s SDRAM RAM A B C D BASE bits 0 7 8 15 16 23 24 31 correspond to PPC60x address bits 0 7 For larger SDRAM sizes the lower significant bits of A B C D BASE are ignored This means that the block s base address will always appear at an even multiple of its size Remember that bit 0 is MSB Note that RAM E E G H BASE are located at FEF800C8 refer to the section on SDRAM Base Address Register Blocks E F G H They operate the same for blocks E H as these bits do for blocks A D Also note that the combination of RAM X BASE and ram x siz should never be programmed such that SDRAM responds
28. FUN Function Number Configuration Cycles Identifies a function number within a target s configuration space This field is copied to the PCI AD bus during the address phase of a Configuration cycle Special Cycles This field must be written with all ones DEV Device Number Configuration Cycles Identifies a target s physical PCI device number Refer to the section on Generating PCI Cycles for a description of how this field is encoded Special Cycles This field must be written with all ones BUS Bus Number Configuration Cycles Identifies a targeted bus number If written with all zeros a Type 0 Configuration Cycle will be generated If written with any value other than all zeros then a Type 1 Configuration Cycle will be generated Special Cycles Identifies a targeted bus number If written with all zeros a Special Cycle will be generated If written with any value other than all zeros then a Special Cycle translated into a Type 1 Configuration Cycle will be generated EN Enable Configuration Cycles Writing a one to this bit enables CONFIG DATA to Configuration Cycle translation If this bit is a zero subsequent accesses to CONFIG DATA will be passed though as I O Cycles Special Cycles Writing a one to this bit enables CONFIG DATA to Special Cycle translation If this bit is zero subsequent accesses to CONFIG DATA will be passed though as I O Cycles 2 108 Computer Group Literature Center Web Site Re
29. L The bit is affected by local reset RST_ X The bit is not affected by reset V The effect of reset on the bit is variable 3 38 Computer Group Literature Center Web Site Programming Model Vendor Device Register Address FEF80000 Bit Sa A TY QP EH COLD SO SILA Of SO I eee Ganl bani Ganl Gan bani pal RIN NI NI NIN NIN VENDID DEVID Operation READ ONLY READ ONLY Reset 1057 4803 VENDID This read only register contains the value 1057 It is the DEVID vendor number assigned to Motorola Inc This read only register contains the value 4803 It is the device number for the Hawk Revision ID General Control Register Address FEF80008 Bit eo SP A eg afro 1 e e eS SI SL SL A NL ALA A A e Name Su 555 21 REVID 212 8 gs SLO Oo oO OL ol ols ecjo ojo o og is ojo oc o s S SJ S Operation READ ONLY ed aax c ed aal ec 24 ed Reset 01 z Halala Pg gt g xxx d Sol gt gt gt gt controls the enable for the p1_tben and pO output signals When tben en is set the Pelm_ input pin
30. rwcb rwcb when set causes reads and writes to SDRAM from the PPC60x bus to access check bit data rather than normal data The data path used for reading and writing check bits is DO D7 Each 8 bit check bit location services 64 bits of normal data Figure 3 10 shows the relationship between normal data and check bit data http www motorola com computer literature 3 45 System Memory Controller SMC Normal View of Data rwcb 0 64 bits 012 34 5 6 7 Check bit View rwcb 1 Figure 3 10 Read Write Check bit Data Paths Note that if test software attempts to force a single bit error to a location using the rwcb function the scrubber may correct the location before the test software gets a chance to check for the single bit error This can be avoided by disabling scrub writes Also note that writing bad check bits can set the elog bit in the Error Logger Register The writing of check bits causes the SMC to perform a read modify write to SDRAM If the location to which check bits are being written has a single or double bit error data in the location may be altered by the write check bits operation To avoid this it is recommended that the derc bit also be set while the rweb bit is set A possible sequence for performing read write check bits is as follows 1 Disable scrub writes by clearing the swen bit if it is set 2 Make sure software is not using DRAM at
31. Functional Description Table 2 4 PPC Master Read Ahead Options Continued RED SET RAEN Rod Continuation pen 00 XX 1 Read 4 cache FIFO lt 0 FIFO gt 4 Read Line lines cache lines cache lines XX 00 Read Mul tiple 01 XX 1 Read 4 cache FIFO lt 1 FIFO gt 4 Head Line lines cache line cache lines XX 01 Read Mul tiple 10 XX 1 Read 4 cache FIFO lt 2 FIFO gt 4 Bead rane lines cache lines cache lines XX 10 Read Mul tiple 11 1 Read 4 cache FIFO lt 3 FIFO gt 4 Read Line lines cache lines cache lines XX 11 x Read Mul tiple Upon completion of a prefetched read transaction any residual read data left within the PCI FIFO will be invalidated discarded The PHB does not have a mechanism for snooping the PPC60x bus for transactions associated with the prefetched read data within the PCI FIFO Therefore caution should be exercised when using the prefetch option within coherent memory space The PPC Master never performs prefetch reads beyond the address range mapped within the PCI Slave map decoders As an example assume PHB has been programmed to respond to PCI address range 10000000 through 1001FFFF with an offset of 2000 The PPC Master performs its last read on the PPC60x bus at cache line address 3001FFFC or word address 3001FFF8 http www motorola com computer literature 2 13 Hawk PCI Host Bridge amp Mult
32. GA2 GAIH OPER READ ONLY RESET X X X X X X X X REQUIRED REQUIRED ON MODULE WITH VME OR OPTIONAL 1 30 Computer Group Literature Center Web Site PCI Local Bus Extended Features Register 1 This register is used to read if a PMC board is present or if a PCI expansion slot is present Exceptions to the PowerPlus II Programming Specification are included in the following table Table 1 16 Extended Features Register 1 REG Extended Features Register 1 Offset 80F0h RDO RDI RD2 RD3 RD4 RD5 RD6 RD7 A 2 E a E n cO m 2 a gc P4 P 12 eGc5 5 e m 5 praet gt 2 ti ze IZB 19s m m 54 gt gt OPER R R R R R R R R RESET x x x x x x x x REQUIRED O O OR OPTIONAL L PMC Module 1 Present If set there is no PMC module installed in position 1 If cleared the PMC module is installed PMC2P PMC Module 2 Present If set there is no PMC module installed in position 2 If cleared the PMC module is installed MMEZI P L Memory Mezzanine 1 present When set there is no memory mezzanine 1 present When cleared there is a memory mezzanine present MMEZ2 P L Memory Mezzanine 2 present When set there is no memory mezzanine 1 present When cleared there is a memory mezzanine 2 present http www motorola com computer literature 1 31 Product Data and
33. RJ45 PCI Expansion 10 100 RJ45 5 Aa SLotl Front Panel PMC Front hs R R M s S E amp 5 VME P2 761 or PMC VME Figure 1 1 MVME5100 Block Diagram http www motorola com computer literature 1 3 Product Data and Memory Maps Memory maps The following sections describe the memory maps for the MVMES100 Processor Memory Map The processor memory map configuration is under the control of the PCI Host Bridge PHB and System Memory Controller SMC portions of the Hawk ASIC The Hawk adjusts system mapping to suit a given application via programmable map decoder registers At system power up or reset a default processor memory map takes over Following a reset the memory map presented to the processor is identical to the CHRP memory map described in this document The MVMES100 is fully capable of supporting both the PREP and the CHRP processor memory maps with ROM FLASH size limited to 16 and RAM size limited to 2GB Default Processor Memory Map The default processor memory map that is valid at power up or reset remains in effect until reprogrammed for specific applications Table 1 2 defines the entire default map 00000000 to FFFFFFFF Table 1 2 Default Processor Memory Map Processor Address Size Definition Start End 0000 0000 7FFF 2GB Not Mapped 8000 0000 8080 FFFF 8M
34. Fully PCI Rev 2 1 compliant 32 bit addressing 32 or 64 bit data bus Support for accesses to all three PCI address spaces Multiple level write posting buffers for writes to the PPC bus 2 1 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Read ahead buffer for reads from the PPC bus Four independent software programmable slave map decoders Interrupt Controller MPIC compliant MPIC programming model Support for 16 external interrupt sources and two processors Supports 15 programmable Interrupt and Processor Task priority levels Supports the connection of an external 8259 for ISA AT compatibility Distributed interrupt delivery for external I O interrupts Multiprocessor interrupt control allowing any interrupt source to be directed to either processor Multilevel cross processor interrupt control for multiprocessor synchronization Four Interprocessor Interrupt sources Four 32 bit tick timers Processor initialization control Two 64 bit general purpose registers for cross processor messaging Computer Group Literature Center Web Site Block Diagram Block Diagram i 2 2910 Odd Odd Odd JejseJ Odd Jase T Xi 2 PUNO odd 1 T indino 2d Aed egg lod 124 E
35. The on board Hawk ASIC provides the bridge function between the processor s bus and the PCI bus It provides 32 bit addressing and 64 bit data however 64 bit addressing dual address cycle is not supported The ASIC also supports various processor external bus frequencies up to 100 MHz Note Unless otherwise specified the designation MVMES100 refers to all models of the MVME5100 series Single Board Computers The following table lists the key features of the 5100 Table 1 1 MVME Key Features Feature Microprocessors and MPC7400 400 MHz Internal Clock Frequency Bus Clock Frequency e MPC750 9450 MHz Internal Clock Frequency Specification Bus Clock Frequency up to 100 MHz L2 Cache Optional e IMB MPC750 or 2MB MPC7400 using burst mode SRAM modules Memory EEPROM on board programmable via two 32 pin PLCC CLCC sockets 16MB Surface Mount 1 1 Product Data and Memory Maps Table 1 1 MVME Key Features Continued Feature Specification Main Memory PC100 ECC SDRAM with 100 MHz bus SDRAM 32MB to 512MB on board expandable to 1GB via RAM500 memory mezzanine NVRAM 32KB available for users Memory Controller PCI Host Bridge Hawk System Memory Controller SMC Hawk PCI Host Bridge PHB Interrupt Controller Hawk Multi Processor Interrupt Controller MPIC Peripheral Support Dual 16550 Compatible Asynchronous Serial Port
36. a S Writing a ONE to this field sets this field a C Writing a ONE to this field clears this field MPIC Registers The MPIC register map is shown in Table 2 19 The Off field is the address offset from the base address of the MPIC registers in the PPC IO or PPC Memory space Note that this map does not depict linear addressing The PCI SLAVE of the PHB has two decoders for generating the MPIC select These decoders will generate a select and acknowledge all accesses which are in a reserved 256K byte range If the index into that 256K block does not decode a valid MPIC register address the logic will return 00000000 The registers are 8 16 or 32 bits accessible Table 2 19 MPIC Register Map 3 3 2 2 2 2 2 2 2 2 2 2 1 11 1 11 1 1 1 1 Off 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 FEATURE REPORTING REGISTER 0 01000 GLOBAL CONFIGURATION REGISTER 0 01020 MPIC VENDOR IDENTIFICATION REGISTER 01080 PROCESSOR INIT REGISTER 01090 IPIO VECTOR PRIORITY REGISTER 010a0 VECTOR PRIORITY REGISTER 010b0 VECTOR PRIORITY REGISTER 010c0 IPI3 VECTOR PRIORITY REGISTER 010d0 2 110 Computer Group Literature Center Web Site Registers Table 2 19 MPIC Register Map Continued
37. rd9 46 rd23 66 86 22 A6 06 E6 07 21 27 47 67 87 A7 rd52 C7 E7 08 28 48 68 54 88 A8 51 C8 rd47 E8 09 29 rd48 49 rd24 69 89 25 A9 9 E9 rd4 0A 2A 4A 0 6A 8A rdi9 AA 0B rd18 2B 4B 6B 8B AB CB 0 2C rd2 4C 6 8C rdi5 CC 0D 414 2D 4D 6D 8D AD ED 90 rd13 2 4 6E 8E AE CE 0F 2F 4F rd44 6F 8F AF bEF 10 ckd4 30 50 70 453 90 BO rd50 DO rd46 FO 11 31 449 51 rd43 71 91 rd39 B1 D1 F1 12 32 rd63 52 rd40 72 92 rd16 B2 D2 F2 13 rd17 33 53 73 93 B3 D3 rd60 F3 14 34 462 54 rd59 74 94 56 B4 04 F4 rd12 15 1411 35 55 75 95 B5 D5 F5 16 1410 36 56 76 96 B6 D6 F6 17 37 57 77 97 B7 D7 F7 18 38 rd61 58 rd58 78 98 57 B8 D8 F8 19 rd7 39 59 79 99 B9 D9 F9 1A rd6 3A 5A 7A rd20 9A BA 1 3B 5
38. 8070 Scratch UART 2 Registers 8200 Receiver Buffer Read Transmitter Holding Write 8210 Interrupt Enable 8220 Interrupt Identification Read FIFI Control Write 8230 Line Control 8240 MODEM Control 8250 Line Status 8260 MODEM Status 8270 Scratch http www motorola com computer literature 1 23 Product Data and Memory Maps Status Register The 5100 implementation of this Register is fully compliant with the PowerPlus II programming model with exceptions to bits RD5 RD6 and RD7 An 8 bit as identified in the following table status register accessible through the External Register Set port defines the status of the Module Table 1 11 MVME5100 Status Register REG Status Register FEF88080h BIT RDO RD1 RD2 RD3 RD4 RDS RD6 RD7 FIELD m 2 es ME OPER R R R R R RESET X X X 0 REQUIRED R R OR OPTIONAL SYSCON System Controller Mode bit If this bitis set the module is not the master of its PCI bus PCI bus If this bit is cleared the module is the master of its PCI bus PCI bus 0 This bit always reads as cleared 0 BAUDOUT This is the baud output clock of the TL16C550 UART referenced to the 1 8432 MHz UART oscillator This signal can be used as a timing reference FUSE This bit provides the current state of the FUSE signal If set at least one of the planar fuses or polyswitches is open Comput
39. MVMES100 VPD Reference Information B VPD Definitions L2 Cache Configuration Data The L2 cache configuration data packet consists of byte fields that show the size organization and type of the L2 cache memory array Note The PPMCBASE does not contain L2 Cache The following table s further describe the L2 cache memory configuration VPD data packet Table B 4 L2 Cache Configuration Data Byte Field Field Mnemonic Field Description Offset Size Bytes 00 2 L2C MID Manufacturer s Identifier FFFF Undefined Not Applicable 02 2 2 DID Manufacturer s Device Identifier FFFF Undefined Not Applicable 04 1 L2C DDW Device Data Width e g 8 bits 16 bits 32 bits 64 bits 128 bits 05 1 L2C NOD Number of Devices Present 06 1 L2C NOC Number of Columns Interleaves 07 1 L2C CW Column Width in Bits This will always be a multiple of the device s data width 08 1 L2C TYPE L2 Cache Type 00 Arthur Backside 01 External 02 In Line 09 1 L2C ASSOCIATE Associative Microprocessor Number If Applicable 0A 1 L2C OPERATIONMODE Operation Mode 00 Either Write Through or Write Back S W Configurable 01 Either Write Through or Write Back H W Configurable 02 Write Through Only 03 Write Back Only B 10 Computer Group Literature Center Web Site Vital Product Data VPD Introduction Table B 4 L2 Cache Configuration Data Continued Byte Offset
40. SDRAM block organization 3 9 connections block diagram 3 4 Operational Method for Sizing 3 83 registers initializing 3 75 sizing 3 76 speed attributes 3 75 speeds 3 7 SDRAM Attributes Register SMC 3 41 SDRAM Base Address Register SMC 3 67 SDRAM Base Address Enable 3 76 SDRAM Base Register SMC 3 43 SDRAM Control Registers Initialization Example 3 77 SDRAM Enable and Size Register SMC 3 66 SDRAM Speed Attributes Register SMC 3 68 Serial Presence Detect SPD 3 76 Serial Presence Detect SPD Definitions 1 12 sien 3 48 Single Bit Error Counter 3 50 single beat reads writes 3 6 single bit error 3 12 single bit errors ordered by syndrome code 3 87 sizing SDRAM 3 76 SMC 32 Bit Counter 3 72 address parity 3 10 Address Parity Error Address Register 3 71 Address Parity Error Log Register 3 70 cache coherency 3 11 CLK Frequency Register 3 44 CSR Accesses 3 34 cycle types 3 11 data parity 3 10 Data Parity Error Upper Data Register 3 61 data transfers 3 9 ECC Control Register 3 45 Error Address Register 3 51 error correction 3 11 Error Logger Register 3 49 error logging 3 13 External Register Set 3 34 General Control Register 3 39 Hawk 1 4 L2 cache support 3 11 on Hawk 3 1 refresh scrub 3 34 ROM A Base Size Register 3 53 ROM B Base Size Register 3 56 ROM Speed Attributes Register 3 58 Scrub Refresh Register 3 51 SDRAM Base Address Register 3 43 3 67 SDRAM Enable and Size Register 3 41 3 66 http www
41. With 256 Mbit 8 bit data devices a block can be populated for 256MB When populated the planar memory blocks appear as Block A and Block B to the Hawk The optional mezzanine memory blocks appear as Block C and Block E to the Hawk The optional memory mezzanine can configure the planar local bus frequency upon power up This will reduce the planar local bus frequency of 100 MHz to 83 33 MHz when mezzanines are used Either one or two mezzanines can be installed Each mezzanine will add one bank of SDRAM memory of either 32MB 64MB 128MB or 256MB A total of 512MB of mezzanine memory can be added Refer to the MVME5100 Single Board Computer Installation and Use manual for installation and configuration instructions for the 500 memory mezzanine board and refer to Chapters 2 and 3 of this manual for additonal programming information on programming the memory mezzanines using the Hawk ASIC P2 Modes The MVMES100 has two P2 I O modes SBC and PMC that are user configurable with 4 jumpers on the planar refer to the jumper settings in the MVME5100 Single Board Computer Installation and Use manual The jumpers route the on board Ethernet Port 2 to Row C of the P2 http www motorola com computer literature 1 11 Product Data and Memory Maps connector The SBC mode also know as 761 mode or IPMC mode is backwards compatible with the MVME761 transition card and P2 adapter card excluding PMC IO routing used on MVME2
42. bits four times When the 60 bus master requests a single beat write to SDRAM the SMC performs a full width read cycle to SDRAM merges in the appropriate PPC60x bus write data and writes full width back to SDRAM http www motorola com computer literature 3 11 System Memory Controller SMC Error Reporting The SMC checks data from the SDRAM during single and four beat reads during single beat writes and during scrubs Table 3 2 shows the actions it takes for different errors during these accesses 60x Note that the SMC does not assert on double bit errors In fact the SMC does not have a TEA_ signal pin and it assumes that the system does not implement The SMC can however assert machine check MCHKO on double bit error Table 3 2 Error Reporting Error Type Single Bit Error Single Beat F our Beat Read Terminate the PPC60x bus cycle nor mally Provide corrected data to the PPC60x bus master Single Beat Write Terminate the PPC60x bus cycle nor mally Correct the data read from SDRAM merge Four Beat Write Scrub This cycle is not seen on the PPC60x bus Write corrected data back to SDRAM if so enabled with the write data and N A write the corrected merged data to SDRAM Assert Hawk s internal Assert Hawk s internal error interrupt if so Assert Hawk s internal error interrupt if so enabled 2 error interrupt if
43. cl3 bit is to be cleared Do not update the cl3 bit at this point You will use the information from this step later 4 Determine the values to use for tras trp trcd and trc The values to use for tras trp trcd and trc can be obtained from the SPD The tras bits determine the minimum tRAS time produced by the Hawk The trp bit determines the minimum tRP time produced by the Hawk etc Each set of bits should accommodate the slowest block of SDRAM The SPD parameters are specified in nanoseconds and have to be converted to 60x clock periods for the Hawk Use the following table to convert SPD bytes 27 29 and 30 to the correct values for tras trp tred and trc Do not actually update these bits in the Hawk at this time You will use the information from this step later Table 3 18 Deriving tras trp trcd and trc Control Bit Values from SPD Information Control Bits Parameter Parameter Expressed Possible Control Bit Values in CLK Periods 0 0 lt tRAS_CLK lt 4 0 tras 00 4 0 tRAS lt 5 0 tras 01 0 tRAS lt 6 tras 1 FEF800D1 tRAS tRAS_CLK 1tRAS T 20 lt 5 lt 60 10 bits 2 3 SPD Byte T CLK Period 90 tRAS 70 11 tras 30 in nanoseconds 7 0 lt tRAS_CLK Illegal See Notes 1 2 and 9 3 78 Computer Group Literature Center Web Site Software Considerations Table 3 18 Deriving tras trp trcd and trc Cont
44. time out length is encoded as follows MBT Time Out Length 00 256 msec 01 64 msec 10 8 msec 11 disabled 64 bit PCI Mode If set the PHB is connected to a 64 bit PCI bus Refer to the section titled PHB Hardware Configuration for more details of how this bit is set OpenPIC Interrupt Controller Enable If set the PHB detected errors are passed on to the MPIC If cleared PHB detected errors are passed on to the processor 0 INT pin PPC ID This field is encoded as shown below to indicate who is currently the PPC bus master This information is obtained by sampling the XARBO thru XARB3 pins when in external PPC arbitration mode When in internal PPC arbitration mode this information is generated by the PPC Arbiter In a multiprocessor environment these bits allow software to determine on which processor it is currently running MID Current PPC Data Bus Master 00 device on ABGO 01 device on ABGI 10 device on ABG2 11 Hawk Computer Group Literature Center Web Site Registers Arbiter PCI Arbiter Control Registers The PPC Arbiter Register XARB provides control and status for the PPC Arbiter Refer to the section titled PPC Arbiter for more information The bits within the XARB register are defined as follows Address Bit N oo o EN N oo N o A ON N oo 000
45. 0 9 REGISTER 1 FEF88100 EXTENDED FEATURES REGISTER 2 FEF88200 UART 2 RBR THR FEF88210 UART 2 IER FEF88220 UART 2 IIR FCR FEF88230 THIS GROUP UART 2 LCR FEF88240 OPTIONAL UART 2 MCR FEF88250 UART 2 LSR FEF88260 UART 2 MSR FEF88270 UART 2 SCR 1 22 Computer Group Literature Center Web Site PCI Local Bus Dual TL16C550 UARTs The MVMES100 implementation of the Dual TL16C550 UARTS are fully compliant with the PowerPlus II Programming Model for UART Registers The following tables reflect this model The MVMES100 uses UART 1 and UART 2 for asynchronous serial debug ports four are allowed by the PowerPlus II Programming Model The first UART UART 1 is addressed at External Register Set Address Offset 8000 8 8000 The second UART 2 is addressed at offset 8200 FEF8 8200 The UART 8 bit data port RDO RD7 is connected to the most significant bits of the 64 bit External Register Set The UART port addressing occurs on 16 byte address boundaries and are backward compatible with the PPMC750 Table 1 10 16550 Access Registers Required or External Register Function Optional Set Address Offset UART 1 Registers 8000 Receiver Buffer Read Transmitter Holding Write 8010 Interrupt Enable 8020 Interrupt Identification Read FIFO Control Write 8030 Line Control 8040 MODEM Control 8050 Line Status 8060 MODEM Status
46. 10 FIFO full 11 FIFO full RLRTx Read Lock Resolution Threshold This field is used by the PHB to determine a PPC bound read FIFO threshold at which a bridge lock resolution will create a retry on a pending PCI bound transaction The encoding of this field is shown in the following table RLRT Read lock resolution threshold 00 Match read threshold mode i e PSATTx RXFT or RMFT 01 Immediate 10 FIFO less than 1 cache line 11 FIFO less than 1 cache line The PPC Prescaler Adjust Register XPAD is used to specify a scale factor for the prescaler to ensure that the time base for the bus timer is The scale factor is calculated as follows XPAD 256 where 1 is the frequency of the CLK input in MHz The following table shows the scale factors for some common CLK frequencies Frequency XPAD 100 83 AD 66 BE 50 CE 2 78 Computer Group Literature Center Web Site Registers Error Test Error Enable Register The Error Test Register ETEST provides you with a way to send certain types of errors to test the PHB error capture and status circuitry The bits within the ETEST are defined as follows Address 0020 eremreerPescppeESSESERERSRERSE EESEEFEm ame eim EB i FS ISIS FERRE EEE SERE BEBERE BEERS be p As EB Pe A e R Operati
47. 3 26 Figure 3 7 Programming Sequence for I2C Current Address Read 3 28 Figure 3 8 Programming Sequence Tor 2C Page Witte iae eter te ates 3 30 Figure 3 9 Programming Sequence for I2C Sequential Read 3 33 Figure 3 10 Read Write C heck bit Data t tutes 3 46 Pigiwe 4 1 Bis Endisn Mod cass casas or hie eie pri as p abe ka pras pe REID VIS Rer 4 7 Fiame 4 2 Litke Endiin NEG aec oa qe EUR OR 4 8 XV List of Tables Table t i M Y ME Key Be stares eint oeste dede 1 1 Table 1 2 Default Processor Memory Map iie ueste ptr apte 1 4 Table 1 3 Suggested CHRP Memory lt etes Ha es 1 6 Table 1 4 Hawk PPC Register Values for Suggested Memory Map 1 7 Table 1 5 RG Device Adare seine iue deca REA CER bea dd ops 1 14 Table 1 6 PCI Arbitration Assignments 1 15 Table 1 7 IDSEL Mapping for PCI 1 19 Table 1 8 On Board PCI Device Identification eere trees 1 20 Table 1 9 Hawk External Register Bus Summary 1 21 Table 1 10 165530 Access Bestell 1 23 Table 1 11 Status Register ninin i npani ie 1 24 Table 1 13 MODEAJTL Bit
48. 32 bits rom a 64 matches the value that was on the RD2 pin at power up reset It cannot be changed by software rom asiz The rom a siz control bits are the size of ROM Flash for Block A They are encoded as shown in Table 3 11 Table 3 11 ROM Block A Size Encoding rom a siz E IIR SIZE 26000 1 001 2 010 4 011 8 100 16 101 32 20110 64MB 111 Reserved rom a rv rom ry and rom b rv determine which if either of Blocks A and B is the source of reset vectors or any other access the range FFF00000 FFFFFFFF as shown in the table below Table 3 12 rom a rv and rom b rv encoding rom a rv rom b rv Result 0 0 Neither Block is the source of reset vectors 0 1 Block B is the source of reset vectors 1 0 Block A is the source of reset vectors 1 1 Block B is the source of reset vectors 3 54 Computer Group Literature Center Web Site Programming Model rom a en rom a we rom a rv is initialized at power up reset to match the value on the RDO pin When rom a en is set accesses to Block A ROM Flash in the address range selected by ROM A BASE are enabled When rom a en is cleared they are disabled When rom a we is set writes to Block A ROM Flash are enabled When rom a we is cleared they are disabled Note that if rom 64 is cleared only 1 byte writes are allowed If rom a 64 is set on
49. Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Motorola Inc Computer Group 2900 South Diablo Way Tempe Arizona 85282 Contents About This Manual Summary Of Ri xxiv POR T WI E t o IS Xxiv Comments and SuggeslloflB rcv ar XXV Conventions Used an This Mannal ass xxvi ua E DON A 1 CHAPTER1 Product Data and Memory Maps nri Mer 1 1 Nemon map SR PA PT Won VM pH RR E ERR EHE ae 1 4 Processar Memory IMEI ici bibet ied rbi poH 1 4 Default Processor Memory 1 4 Processor Memor IV TD 1 5 PEDM DON 1 7 YME Momory Map 1 7 PCI Local Bus Memory MBD uester tap pet VEPRERARURFERUE VERRE RS FERE PR 1 8 Memory MAAR T 1 8 System BU cei rer tror rs einen FERT 1 8 acl T M 1 9 Processor Type deni cations rre crate riae rap Re RED moots 1 9 Processor PLL Gomis oration cocci eonna e E E 1 9 ELO T
50. Front Panel Request 6 PARBI6 Ethernet Port 2 Front Panel or P2 Refer to the PMC712 761 I O Module Installation and Use manual The Ethernet Controller The MVMES100 provides dual Ethernet interfaces Port 1 and Port 2 via two pairs of Intel GD82559ER Fast Ethernet PCI controller chips Port 176 10BaseT 100BaseTx interface is routed through the front panel Port 276 Ethernet interface is routed to either the front panel or the P2 connector as configured by jumpers The front panel connectors are RJ 45 Every MVMES100 board is assigned two Ethernet Station Addresses The address is 0001 AFxxxxxx where xxxxxx is the unique number assigned to each interface The higher Ethernet Station Address corresponds to Port 1 and the lower Ethernet Station Address corresponds to Port 2 The Ethernet Station Addresses are displayed on labels attached to the PMC front panel keep out area In addition the presence of the Ethernet device can be positively determined by reading the Vital Product Data VPD Serial EEPROM which provides storage of MVMES100 hardware configuration Refer to Appendix 5100 VPD Reference Information for more information on VPD Refer to the Intel GD82559ER Reference Manual and Data Sheet as referenced in Appendix A Related Documentation for additional details on the Ethernet controller Computer Group Literature Center Web Site PCI Local Bus PMC PCI Expansion Slots Up to tw
51. Hawk PCI Host Bridge amp Multi Processor Interrupt Controller WDTXxSTAT Registers Address WDTISTAT FEFF0064 WDT2STAT FEFF006C Bit es obo rco o o Name COUNT Operation R R R Reset 00 00 FF The Watchdog Timer Status Registers WDTISTAT and WDT2STAT are used to provide status information from the watchdog timer functions within the PHB The field within WDTxSTAT registers is defined as follows COUNT Count This read only field reflects the instantaneous counter value of the WDT General Purpose Registers Address GPREGO Upper FEFF0070 GPREGO Lower SFEFF0074 Upper SFEFF0078 GPREGI1 Lower SFEFF007C Bit 1111 11 1 1 1 111 22 2 292 2 2 2 2 2 343 0 1 2 3 4 5 6 7F8 9 Of 1 2 3 4 5 6 7 8 9 0 112 3141567 8 9 0 1 Name GPREGx Operation R W Reset 00000000 The General Purpose Registers GPREG0 GPREG2 and are provided for inter process message passing or general purpose storage They do not control any hardware 2 96 Computer Group Literature Center Web Site Registers PCI Registers The PCI Configuration Registers are compliant with the configuration register set described in the PCI Local Bus Specification Revision 2 1 The CONFIG ADDRESS and DATA registers described in this section are accessed from the PPC bus within PCI I O space write operations
52. Ide bote isorinis 2 88 Slave Offset Attribute 0 1 and 2 Registers 2 89 PPC Slave Address 43 Regit 2 90 PPC Slave OffsettAttribute 3 RegiSfetsu aeuo x 2 91 purge gue CT s e m 2 92 E 2 96 General Purpose Registers cose percipi cU TAPER MPs 2 96 EA a E 2 97 Vendor M3 Device UD oe pre RAPERE 2 98 PUP Commands 2 99 Revision Class Code Registers 12 e taret ertt nt bee Ms era 2 101 Heuer Type tet 2 101 MPIC DUO Base Address Register Ribera pne 2 102 MPIC Memory Base Address 2 102 PCI Slave Address 0 1 2 and 3 Registers ise rrt re terr 2 103 PCI Slave Attribute Offset 0 1 2 and 3 Registers 2 104 CONFIG ADDR BSS epee sane 2 106 CONPIG DATA a 2 109 MPIC REEI Locri nrbe eR REAREA 2 110 ET 2 110 Feature eoii antes 2 113 Global Contguration 2 114 Vendo
53. If set the PHB may act as a master on PCI If cleared the PHB may not act as a PCI Master PERR Parity Error Response If set the PHB willcheck parity on all PCI transfers If cleared the PHB will ignore any parity errors that it detects and continue normal operation SERR System Error Enable This bitenables the SERR output pin If clear the PHB will never drive SERR_ If set the PHB will drive SERR_ active when a system error is detected http www motorola com computer literature 2 99 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller The Status Register STATUS is used to record information for PCI bus related events The bits within the STATUS register are defined as follows P66M PCI66 MHz This bit indicates the PHB is capable of supporting a 66 67 MHz PCI bus FAST Fast Back to Back Capable This bit indicates that the PHB is capable of accepting fast back to back transactions with different targets DPAR Data Parity Detected This bitis set whenthree conditions are met 1 the PHB asserted PERR itself or observed PERR_ asserted 2 the PHB was the PCI Master for the transfer in which the error occurred 3 the PERR bit in the PCI Command Register is set This bit is cleared by writing it to 1 writing a 0 has no effect SELTIM DEVSEL Timing This field indicates that the PHB will always assert DEVSEL_ as a medium responder SIGTA Signalled Target Abort This bit is set by the PCI Slave
54. Low ABORT Switch RTC IRQ8 4 IRQ9 Level Low Watch Dog 1 2 5 PIRQA 10 Level Low LAN on front 6 IRQ11 Level Low Internal USB controller 2 7 MSDT 12 Edge High Not Used IRQI2 8 PIRQC_ IRQ13 LAN to rear http www motorola com computer literature 4 3 Hawk Programming Details Table 4 2 PBC ISA Interrupt Assignments Continued PRI PSIO Routed to 5 Edge b Interrupt Source IRQ ISA Level 5 Input IRQ Z E 2 9 IRQ14 IRQ14 Edge High Primary IDE interface 10 15 15 Level Low or PMC2 Interrupt 11 IRQ3 IRQ3 INTI Level Low COM2 or COMA Interrupt 12 4 4 Level Low COMI or Interrupt 13 PIRQB IRQ5 Level Low 21554 Secondary Interrupt 14 IRQ6 IRQ6 Edge High Not Used 15 IRQ7 IRQ7 Edge High Not Used Notes 1 Internally generated by the PBC 2 These interrupt sources must be routed to the appropriate ISA IRQ using the PBC interrupt routing registers 4 4 Computer Group Literature Center Web Site Exceptions Exceptions Sources of Reset There are five potential reset sources on the 5100 series They are as follows 1 Power On Reset 2 RESET Switch 3 Watchdog Timer Reset 4 Software generated Module Reset using MODRST Bit Register 5 Reset generated from system bus Each source of reset will result in a reset of the processor Hawk ASIC and all other on boar
55. MVMES101 2143 128MB ECC SDRAM IEEE 1101 handles 2MB L2 Cache MVMES101 2161 512MB ECC SDRAM SCANBE handles 2MB L2 Cache MVMES101 2163 512MB ECC SDRAM IEEE 1101 handles 2MB L2 Cache xxii T O Modules MVMET712M Compatible I O IPMC712 001 Multifunction rear I O PMC module Ultra Wide SCSI one parallel port three sync and one sync async serial ports MVME712M Transition module connectors One DB 25 sync async serial port three DB 25 async serial port one AUI connector one D 36 parallel port and one 50 pin 8 bit SCSI includes 3 row DIN P2 adapter module and cable MVME761 Compatible IPMC761 001 Multifunction rear I O PMC module Ultra Wide SCSI one parallel port two async and two sync async serial ports MVME761 001 Transition module Two DB 9 async serial port connectors two HD 26 sync async serial port connectors one HD 36 parallel port connector one RJ 45 10 100 Ethernet connector includes 3 row DIN P2 adapter module and cable for 8 bit SCSI MVME761 011 Transition module Two DB 9 async serial port connectors two HD 26 sync async serial port connectors one HD 36 parallel port connector and one RJ 45 10 100 Ethernet connector includes 5 row DIN P2 adapter module and cable for 16 bit SCSI requires backplane with 5 row DIN connectors SIM232DCE or DTE EIA 232 DCE or DTE Serial Interface Module SIMS30DCE or DTE EIA 530 DCE or
56. Master attempts to move data using burst transfers whenever possible If a transaction starts on a non cache line address the PPC Master performs as many single beat transactions as needed until the next highest cache line boundary is reached If a write transaction ends on a non cache line boundary then the PPC Master finishes the transaction with as many single beat transactions as needed to complete the transaction Table 2 2 shows the relationship between the starting addresses and the PPC60x bus transaction types when write posting and read ahead are enabled Computer Group Literature Center Web Site Functional Description Table 2 2 PPC Master Transaction Profiles and Starting Offsets Start Offset i e from 0x00 0x20 0x40 etc Ox 00 gt Ox 07 Write Profile Burst 0x00 Burst 0x20 Read Profile Burst 0x00 Burst 0x20 Notes Most efficient Single 0x08 Burst 0x00 Burst 0x20 Ox 08 gt Ox 0f Discard read beat 0x00 Single 0x10 Burst 0x20 Single 0x18 Burst 0x20 Ox 10 gt Ox 17 Single 0x10 Burst 0x00 Discard read beat 0x00 Single 0x18 Burst 0x20 and 0x08 18 gt 0 1 Single 0x18 Burst 0x20 Single 0x18 Burst 0x20 While the PCI Slave is filling the PCI FIFO with write data the PPC Master can be moving previously posted write data onto the PPC60x bus In general the 60 bus
57. Memory Bank C and AC Memory Bank E for mezzanine 2 The IPMC761 VPD address is A4 A digital thermometer DS1621 PC address is A6 Some configuration options in the Hawk ASIC must be configured at power up reset time before software performs any accesses http www motorola com computer literature 1 13 Product Data and Memory Maps to it Other configuration information is needed by software to properly configure the Hawk s control registers This information can be obtained from devices connected to the IC bus Table 1 5 2 Device Addressing Device Function Size Device Software Address Address A2A1A0 Onboard Configuration VPD 256x8 000b A0 Onboard User Configuration Data UPD 256x8 001b A2 IPMC761 Onboard Configuration VPD 256x8 010b A4 Digital Thermometer DS1621 256x8 011b A6 Onboard Memory Bank SPD Bank A and B 256x8 100b A8 Optional Memory Mezzanine Banks C D 256x8 101b AA Optional Memory Mezzanine 2 Banks 256x8 110b AC Unpopulated SROM device 256x8 111b AE Vital Product Data VPD and Serial Presence Detect SPD Data Vital Product Data VPD and Serial Presence Detect SPD information consists of data items that are pertinent to board configuration and operation For information on the VPD and SPD data formats and defintions refer to Appendix B MVME5100 VPD Reference Information The registers related to this information is accessed thro
58. Memory Maps PCI Local Bus Memory Map The PCI memory map is controlled by the MPU PCI bus bridge controller portion of the Hawk ASIC and by the Universe PCI VME bus bridge ASIC The Hawk and Universe devices adjust system mapping to suit a given application via programmable map decoder registers No default PCI memory map exists Resetting the system turns the PCI map decoders off and they must be reprogrammed in software for the intended application For detailed PCI memory maps including suggested CHRP and PREP compatible memory maps refer to the Hawk portion of this manual Chapters 2 and 3 VMEbus Memory Map The map of the VMEbus is programmable Like other parts of the MVMES10x memory the mapping of local resources as viewed by VMEbus masters varies among applications The Universe PCI VME bus bridge ASIC includes a user programmable map decoder for the VMEbus to local bus interface The address translation capabilities of the Universe enable the processor to access any range of addresses on the VMEbus Recommendations for VMEbus mapping including suggested CHRP and PREP compatible memory maps can be found in the Hawk portion of this manual Chapters 2 and 3 System Bus The following sections describe the processor system bus for the MVMES100 Only the PPC60x bus interface is supported 1 8 Computer Group Literature Center Web Site System Bus Processors The 5100 has the BGA foo
59. Not Used Header Type Register Offset 0C as HEADER Operation R R R R Reset 00 00 00 00 The Header Type Register Header identifies the PHB as the following Header Type 00 Single Function Configuration Header http www motorola com computer literature 2 101 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Base Address Register Offset 10 Bit 3 312 212 2 2 2 2 2 22 1 1 1 I1 1 1 1 1 1 1 1 0 9 8 7 6 5 493 2 1 0 9 8 7 654 3 2 1 0 9 8 76 5 4 3 2 10 Name MIBAR BASE ac ale m E Operation R W R Reset 0000 0000 MPIC I O Base Address Register MIBAR controls the mapping of the MPIC control registers in PCI I O space IO MEM IO Space Indicator This bit is hard wired to a logic one to RES BASE indicate PCI I O space Reserved This bit is hard wired to zero Base Address These bits define the I O space base address of the MPIC control registers The MIBAR decoder is disabled when the BASE value is zero MPIC Memory Base Address Register Offset 14 Bit 3 3 2 2 2 2 2 292 2 2 2 1 1 1 I1 1 1 1 1 1 1 1 0 9 8 7 6 5 49 3 2 1 O 9 8 7 OF 5 4 3 2 1 0 9 8f 7 6 5 4 32 1 0 Name MMBAR BASE 4852 z Operation R W R olol 50 Reset 0000 00
60. Note that the Hawk does not check parity during cycles in which there is a qualified ARTRY_ at the same time as the TA When dpe me 15 set the transition of the dpelog bit from false to true causes the Hawk to pulse its machine check interrupt request pin MCHKO true When dpe me is cleared the Hawk does not assert its MCHKO pin based on the dpelog bit The GWDP0 GWDP bits are used to invert the value that is driven onto DPO DP7 respectively during reads to the Hawk This allows test software to generate wrong even parity on selected byte lanes For example to create a parity error on DH24 DH31 and DP3 during Hawk reads software should set GWDP3 Computer Group Literature Center Web Site Programming Model Data Parity Error Address Register Address FEF80070 21141 12111 152181585 _ READ ONLY Reset DPE A DPE is the address of the last 60 data bus parity error that was logged by the Hawk It is updated only when dpelog goes from 0 to 1 Data Parity Error Upper Data Register Address FEF80078 Bit lo m e meme eme eee lm m Name DPE DH Operation READ ONLY Reset DPE DH DPE DH is the value on the upper half of the PPC60x data bus at the time of the last logging of a PPC60x data bus parity error by the Hawk It is updated only when dpelog goes from 0 to 1 http www motorola
61. PCI bus 0 Accesses that are to be performed on the PCI bus connected to the PHB must have zero programmed into the Bus Number If the configuration access is targeted for another PCI bus then that bus number should be programmed into the Bus Number field The PHB will detect a non zero field and convert the transaction to a Type 1 Configuration cycle Generating PCI Special Cycles The PHB supports the method stated in PCI Local Bus Specification 2 1 using Configuration Mechanism 1 to generate special cycles To prime the PHB for a special cycle the host processor must write a 32 bit value to the CONFIG_ADDRESS register The contents of the write are defined later in this chapter under the CONFIG_ADDRESS register definition After the write to CONFIG_ADDRESS has been accomplished the next write to the CONFIG_DATA register causes the PHB to generate a special cycle on the PCI bus The write data is driven onto AD 31 0 during the special cycle s data phase http www motorola com computer literature 2 33 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Generating PCI Interrupt Acknowledge Cycles Performing a read from the PIACK register will initiate a single PCI Interrupt Acknowledge cycle Any single byte or combination of bytes may be read from and the actual byte enable pattern used during the read will be passed on to the PCI bus Upon completion of the PCI interrupt acknowledge cycle the PHB will present
62. PPC Master will assert the GBL_ pin for each PPC transaction originated by the corresponding PCI Slave RAEN Read Ahead Enable If set read ahead is enabled for the corresponding PCI Slave WPEN Write Post Enable If set write posting is enabled for the corresponding PCI Slave WEN Write Enable If set the corresponding PCI Slave is enabled for write transactions REN Read Enable If set the corresponding PCI Slave is enabled for read transactions RMFTx Read Multiple FIFO Threshold This field is used by the PHB to determine a FIFO threshold at which to continue prefetching data from local memory during PCI read multiple transactions This threshold applies to subsequent prefetch reads since all initial prefetch reads will be four cache lines This field is only applicable if read ahead has been enabled The encoding of this field is shown in the table below RMFT RXFT Subsequent Prefetch FIFO Threshold 00 0 Cache lines 01 1 Cache line 10 2 Cache lines 11 3 Cache lines Read Any FIFO Threshold This field is used by the PHB to determine a FIFO threshold at which to continue prefetching data from local memory during PCI read and read line transactions This threshold applies to subsequent prefetch reads since all initial prefetch reads http www motorola com computer literature 2 105 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller will be four cache lines This field is only applicable if rea
63. The tben register which is internal to Hawk responds only when is set Computer Group Literature Center Web Site Programming Model tben Register The Hawk s EXTERNAL REGISTER SET interface is similar to that for ROM Flash Block A and B In fact another name for the External Register Set is ROM Flash Block C The differences between Blocks A B and C are that the following parameters are fixed rather than programmable for Block C 1 The device speed for Block C is fixed at 11 Clocks 2 The width for Block C is fixed at 64 bits 3 The address range for Block C is fixed at SFEF88000 FEF8FFF8 FEF98000 FEF9FFF8 when Hawk is configured for the alternate CSR base address 4 Block C is never used for reset vectors 5 Block C is always enabled unless the tben en bit is set 6 Writes to Block C cannot be disabled Address FEF88300 Bit Alen eim gt i aS oo Operation 2 2 READ ZERO READ ZERO READ ZERO A Ia 4 R eset gi gi X X X pl tben The tben Register is only enabled when the tben en bit in the Revision ID General Control Register is set When tben en is cleared the External Register Set interface is enabled and appears in its designated range When tben enis set the External Register Set interface is disabled and the SMC does not respond
64. Time Out Store Discard write data and terminate bus cycle normally Load Present undefined data to the MPC master Generate interrupt via MPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled PCI Target Abort Store Discard write data and terminate bus cycle normally Load Return all 1s and terminate bus cycle normally Generate interrupt via MPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled PCI Master Abort Store Discard write data and terminate bus cycle normally Load Return all 1s and terminate bus cycle normally Generate interrupt via MPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled PERR Detected Generate interrupt via MPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled SERR Detected Generate interrupt via MPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled 4 6 Computer Group Literature Center Web Site Endian Issues Endian Issues The MVMES100 series supports both Little and Big Endian software Because the PowerPC processor is inherently big endian and PCI is inherently Little Endian it is easy to misinterpret the processing scheme For that reason provisions have been made to accommodate the handling of endian issues within the MVMES100 The following figures show how the MVMES100 series handles the endian issue in B
65. a fixed priority will be established between CPUO and CPUI grants with CPUO having a higher priority than CPUI Parking This field determines how the PPC Arbiter will implement CPU parking The encoding of this field is shown in the table below PRK CPU Parking 00 None 01 Park on last CPU 10 Park always on CPUO 11 Park always on CPUI ENA Enable This read only bit indicates the enabled state of the PPC Arbiter If set the PPC Arbiter 1s enabled and is acting as the system arbiter If cleared the PPC Arbiter is disabled and external logic is implementing the system arbiter Refer to the section titled PHB Hardware Configuration for more information on how this bit gets set The PCI Arbiter Register PARB provides control and status for the PCI Arbiter Refer to the section titled PCI Arbiter for more informatiion The bits within the PARB register are defined as follows PRIx Priority This field is used by the PCI Arbiter to establish a particular bus priority scheme The encoding of this field is shown in the following table PRI Priority Scheme 00 Fixed 01 Round Robin 10 Mixed 11 Reserved Computer Group Literature Center Web Site Registers PRKx Parking This field is used by the PCI Arbiter to establish a particular bus parking scheme The encoding of this field is shown in the following table Parking Scheme 0000 Park on last mast
66. address 80000013 80000014 Generating PCI Configuration Cycles The PHB uses configuration Mechanism 1 as defined in the PCI Local Bus Specification 2 1 to generate configuration cycles Please refer to this specification for a complete description of this function Configuration Mechanism 1 uses an address register data register format Performing a configuration access is a two step process The first step is to place the address of the configuration cycle within the ADDRESS register Note that this action does not generate any cycles on the PCI bus http www motorola com computer literature 2 31 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller The second step is to either read or write configuration data into the CONFIG DATA register If the CONFIG ADDRESS register is set up correctly the PHB will pass this access on to the PCI bus as a configuration cycle The addresses of the CONFIG ADDRESS and DATA registers are actually embedded within PCI I O space If the CONFIG ADDRESS register has been set incorrectly or the access to either the CONFIG ADDRESS or CONFIG DATA register is not 1 2 or 4 bytes wide the PHB will pass the access on to PCI as a normal I O Space transfer The CONFIG ADDRESS register is located at offset CF8 from the bottom of PCI I O space The CONFIG DATA register is located at offset CFC from the bottom of PCI I O space The PHB address decode logic
67. amp Multi Processor Interrupt Controller DFLT XBTOM XDPEM PPERM PSERM PSMAM PRTAM Default PPC Master ID This bit determines which MCHK will be asserted for error conditions in which the PPC Master ID cannot be determined or the PHB was the PPC Master For example in the event of a PCI parity error for a transaction in which the PHB s PCI Master was not involved the PPC Master ID cannot be determined When DFLT is set 15 used When DFLT is clear MCHKO will be used PPC Address Bus Time out Machine Check Enable When this bit is set the XBTO bit in the ESTAT register will be used to assert the MCHK output to the current address bus master When this bit is clear MCHK will not be asserted PPC Data Parity Error Machine Check Enable When this bit is set the XDPE bit in the ESTAT register will be used to assert the MCHK output to the current address bus master When this bit is clear MCHK will not be asserted PCI Parity Error Machine Check Enable When this bit is set the PPER bit in the ESTAT register will be used to assert the MCHK output to bus master When this bit 16 clear MCHK will not be asserted PCISystem Error Machine Check Enable When this bit is set the PSER bit in the ESTAT register will be used to assert the MCHK output to bus master 0 When this bit is clear MCHK will not be asserted PCI Signalled Master Abort Machine Check Enable When this bit is set the PSMA bi
68. an error during a PowerPC access to SDRAM They reflect the value of the SCRUB ADDRESS counter if the error was logged during a scrub cycle Address FEF80040 Bit re sola la lania p rn Joo DJF Fe 0 111 a PS AQ IAAI e e eoe e Name ol 5 SCRUB FREQUENCY a ojooioliloco ae Operation 2 READ ZERO READ ZERO READ WRITE ARARA Reset x gt lt x X X 00 P scb0 scb1 swen SCRUB_FREQUENCY These bits increment every time the scrubber completes a scrub of the entire SDRAM When they reach binary 11 they roll over to binary 00 and continue These bits are cleared by power up reset When set swen allows the scrubber to perform write cycles When cleared swen prevents scrubber writes Determines the rate of scrubbing by setting the roll over count for the scrub prescale counter Each time the SMC performs a refresh burst the scrub prescale counter increments by one When the scrub prescale counter reaches the value stored in this register it clears and resumes counting starting at 0 http www motorola com computer literature 3 51 System Memory Controller SMC Note that when this register is all 07 the scrub prescale counter does not increment disabling any scrubs from occurring Since SCRUB FREQUENC
69. and synchronized to the clock by the IPR If the interrupt source is internal to the Hawk ASIC or external with their Sense bit 0 edge sensitive a bit is set in the IPR That bit is cleared when the interrupt associated with that bit is acknowledged If the interrupt source is external and level activated the output from the IPR is not negated until the level into the IPR is negated Externally sourced interrupts are qualified based upon their Sense and or Pol bits in the Vector Priority register IPI and Timer Interrupts are generated internally to the Hawk ASIC and are qualified by their Destination bit Since the internally generated interrupts use direct delivery mode with multicast capability there are two bits in the IPR one for each processor associated with each IPI and Timer interrupt source The MASK bits from the Vector Priority registers are used to qualify the output of the IPR Therefore if an interrupt condition is detected when the MASK bit is set that interrupt will be requested when the MASK bit is lowered Interrupt Selector IS There is a Interrupt Selector IS for each processor The IS receives interrupt requests from the IPR If the interrupt requests are from an external source they are qualified by the destination bit for that interrupt and processor If they are from an internal source they have been qualified The output of the IS will be the highest priority interrupt that has been qualified This outpu
70. associated with Pin 1 and Pin 16 of the SRH and SRH Register Bit 7 is associated with Pin 8 and Pin 9 of the SRH The following table and switch settings depict the aforementioned configuration REG Software Readable Header Switch Register Offset 80 0 BIT RDO RD2 RD3 RD4 RDS RD6 RD7 FIELD SRH7 SRH6 5 5 SRH4 SRH3 SRH2 5 SRHO R R R R R R R R RESET N A N A N A N A N A N A N A N A REQUIRED O OPTIONAL 1 ON 16 1 ON 16 SRHO 0 SRHO 1 D SRH1 0 M SRH1 1 SRH2 0 SRH2 1 SRH3 0 A SRH3 1 bs SRH4 0 o SRH4 1 2 SRH5 0 SRH5 1 SRH6 0 ar SRH6 1 eo SRH7 20 SRH7 1 http www motorola com computer literature 1 29 Product Data and Memory Maps Geographical Address Register VME board The following register provides geographical address status The Geographical Address Register is an 8 bit read only register This register reflects the states of the geographical address pins on the 5 row 160 pin P1 connector REG Geographical Address Register Offset 80E8h BIT RDO RDI RD2 RD3 RD4 RD5 RD6 RD7 FIELD GAP 4
71. automatically cleared with the write cycle to the Transmitter Data Register The Status Register must now be polled to test the i2 cmplt and i2 ackin bits The i2 cmplt bit becomes set when the device address and write bit are transmitted and the i2 ackin bit provides status as to whether or nota slave device acknowledged the device address With the successful transmission of the device address the initial word address 15 loaded into the I C Transmitter Data Register to be transmitted to the slave device Again i2 and i2 ackin bits must be tested for proper response At this point the slave device is still in a write mode Therefore another start sequence must be sent to the slave to change the mode to read by first setting the 12 start 12 ackout and i2 enbl bits in the Control Register and then writing the device address bits 7 1 and read bit bit 0 1 to the PC Transmitter Data Register After i2 cmplt and i2 ackin bits are tested for proper response the master controller writes dummy value data don t care to the Transmitter Data Register This causes the PC master controller to initiate a read transmission from the slave device After the 2 master controller has received byte of data indicated by i2_datin 1 in the PC Status Register and the i2_cmplt bit has also been tested for proper status the master controller responds with an acknowledge and the system software ma
72. bus PSMA From PCI bus PPER Invalid PSER Invalid Each ESTAT error bit may be programmed to generate a machine check and or a standard interrupt The error response is programmed through the PPC Error Enable Register EENAB on a source by source basis When a machine check is enabled either the XID field in the EATTR Register or the DFLT bit in the EENAB Register determines the master to which the machine check is directed For errors in which the master who originated the transaction can be determined the XID field is used For errors not associated with a particular PPC master or associated with masters other than processor 0 1 or 2 the DFLT bit is used One example of an error condition which cannot be associated with a particular PPC master would be a PCI system error Watchdog Timers PHB features two watchdog timers called Watchdog Timer 1 WDT1 and Watchdog Timer 2 WDT2 Although both timers are functionally equivalent each timer operates completely independent of each other WDT1 and WDT 2 are initialized at reset to a count value of 8 seconds and 16 seconds respectively The timers are designed to be reloaded by software at any time 2 42 Computer Group Literature Center Web Site Functional Description When not being loaded the timer will continuously decrement itself until either reloaded by software or a count of zero is reached If a timer reaches count of zero an output signal w
73. com computer literature System Memory Controller SMC Data Parity Error Lower Data Register Address FEF80080 Bit ales DPE DL Operation READ ONLY Reset DPE DL DPE DL is the value on the lower half of the PPC60x data bus at the time of the last logging of a PPC60x data bus parity error by the Hawk It is updated only when dpelog goes from 0 to 1 3 62 Computer Group Literature Center Web Site Programming Model Clock Prescaler Register Address FEF80090 Bit e a e heres eme AS Jes Name I2 PRESCALE VAL Operation READ ZERO READ ZERO READ WRITE Reset X X 01F3 P I2 PRESCALE VAL 12 PRESCALE VAL is a 16 bit register value that will Control Register be used in the following formula for calculating frequency of the gated clock signal PC CLOCK SYSTEM CLOCK I2 PRESCALE VAL 1 2 After power up I2 PRESCALE VAL is initialized to 1F3 which produces a 100 KHz PC gated clock signal based on a 100 0 MHz system clock Writes to this register will be restricted to 4 bytes only Address FEF80098 Bit
74. computer literature System Memory Controller SMC IC Interface The ASIC has an C Inter Integrated Circuit two wire serial interface bus Serial Clock Line SCL and Serial Data Line SDA This interface has master only capability and may be used to communicate the configuration information to a slave device such as serial EEPROM The 2 interface is compatible with these devices and the inclusion of a serial EEPROM in the memory subsystem may be desirable The EEPROM could maintain the configuration information related to the memory subsystem even when the power is removed from the system Each slave device connected to the 2 bus is software addressable bya unique address The number of interfaces connected to the PC bus is solely dependent on the bus capacitance limit of 400pF For bus programming the ASIC is the only master on the bus and the serial EEPROM devices are all slaves The bus supports 7 bit addressing mode and transmits data one byte at a time in a serial fashion with the most significant bit MSB being sent out first Five registers are required to perform the bus data transfer operations These are the PC Clock Prescaler Register PC Control Register Status Register PC Transmitter Data Register and Receiver Data Register The PC SDA is an open drain bi directional line on which data can be transferred at a rate up to 100 Kbits s in the standard mode or up to 400 kbits s in t
75. control register bits in Hawk that affect each SDRAM block s speed size base address and enable The SDRAM speed attributes are the same for all blocks and are controlled by one 32 bit register The size base address and enable can be different for each block and are controlled in individual 8 bit registers SDRAM Speed Attributes The SDRAM speed attributes come up from power up reset initialized to the slowest settings that Hawk is capable of This allows SDRAM accesses to be performed before the SDRAM speed attributes are known An example of a need for this is when software requires some working memory that it can use while gathering and evaluating SDRAM device data from serial EEPROM s Once software knows the SDRAM speed parameters for all blocks it should discontinue accessing SDRAM for at least one refresh period before and after it programs the SDRAM speed attribute bits http www motorola com computer literature 3 75 System Memory Controller SMC SDRAM Size The SDRAM size control bits come up from power up reset cleared to zero Once software has determined the correct size for an SDRAM block it should set the block s size bits to match The value programmed into the size bits tells the Hawk how big the block is for map decoding and how to translate that block s 60x addresses to SDRAM addresses Programming a block s size to non zero also allows it to participate in scrubbing if scrubbing is enabled After
76. e EE pond ies teres aan A A Nee 4 9 APPENDIX Related Documentation Motorola Computer Group Docusents axe 1 NMianortactarers Docume A 2 Related AEE A N A 4 APPENDIX B MVME5100 VPD Reference Information Vital Product Data VPD tQoQlUclboli E dE B 1 How to Read the VPD Information ario eae eano B 1 How to Modify the VPD 2 What Happens if VPD Information is B 3 How to Fix Comupted VPD Information erret rne reines B 3 What if Your Board Has the Wrong VPD tiec B 3 xiii How to Fix Wrong VPD Problems 3 Packet Vy Pes 4 VPD Definitions Product Configuration Options Data sss B 7 VPD Definitions FLASH Memory Configuration Data B 9 VPD Definitions L2 Cache Configuration Data 24242444 B 10 VPD Definitions V PD Revision Dali srasni B 12 Configuration Checksum Calculation Code sess B 14 Serial Presence Detect SPD Checksu
77. has been designed such that XSADD3 and XSOFF3 must be used for mapping to PCI Configuration consequently I O space The XSADD3 XSOFF3 register group is initialized at reset to allow PCI I O access starting at address 80000000 The powerup location Little Endian disabled of the CONFIG_ADDRESS register is 80000CF8 and the CONFIG_DATA register is located at 80000CFC The CONFIG_ADDRESS register must be prefilled with four fields the Register Number the Function Number the Device Number and the Bus Number The Register Number and the Function Number get passed along to the PCI bus as a portion of the lower address bits When performing a configuration cycle the PHB uses the upper 20 address bits as IDSEL lines During the address phase of a configuration cycle only one of the upper address bits will be set 2 32 Computer Group Literature Center Web Site Functional Description The device that has its IDSEL connected to the address bit being asserted is selected for a configuration cycle The PHB decodes the Device Number to determine which of the upper address lines to assert The decoding of the five bit Device Number is show as follows Device Number Address Bit 00000 AD31 00001 01010 All Zeros 01011 ADII 01100 AD12 etc etc 11101 AD29 11110 AD30 11111 All Zeros The Bus Number determines which bus is the target for the configuration read cycle The PHB will always host
78. have completed before the write starts and none should begin until after the write is done A simple way to do this is to perform at least two read accesses to this or another register before and after the write Additionally sometime during the envelope before or after the write all of the SDRAMs open pages must be closed and the Hawk s open page tracker must be reset The way to do this is to allow enough time for at least one SDRAM refresh to occur by waiting for the 32 bit counter see register description further on in this chapter to increment at least 100 times The wait period needs to happen during the envelope ram a b c d en ram a b c d en enables 60x accesses to the corresponding block of SDRAM when set and disables them when cleared Note that ram e f g h en are located at SFEFS00CO refer to the section on SDRAM Enable and Size Register Blocks E F G H further on in this chapter for more information They operate the same for blocks E H as these bits do for blocks A D ram a b c d siz0 3 These control bits define the size of their corresponding block of SDRAM Table 3 10 shows the block configuration assumed by the SMC for each value of ram siz0 ram siz3 Note that ram e f g h size0 3 are located at SFEF800CO They operate identically for blocks E H as these bits do for blocks A D http www motorola com computer literature 3 41 System Memory Controller SMC Table 3 10 Block A B C D E F G H C
79. into two major sections VPD Data Definitions which define VPD packet formats and VPD Content Information which includes information on what is actually contained in the VPD VPD Definitions Packet Types The following table describes and lists the currently assigned packet identifiers Note Additional packet identifiers may be added to this list as future versions of the VPD are released Table B 1 VPD Packet Types ID Size Description Data Notes Type 00 N A Guaranteed Illegal N A 01 Variable Product Identifier e g PrPMC800 750 ASCII 1 5100 750 2 PRPMCCR etc 02 Variable Factory Assembly Number e g 01 W3403F01x ASCII 1 03 Variable Serial Number e g 3383185 etc ASCII 1 04 10 Product Configuration Options Data Binary The data in this packet further describes the board configuration e g header population I O routing etc Its exact contents is dependent upon the product configuration type A following table describes this packet 05 04 MPU Internal Clock Frequency in Hertz e g Integer 4 2 350 000 000 decimal etc byte B 4 Computer Group Literature Center Web Site Vital Product Data VPD Introduction Table B 1 VPD Packet Types Continued ID Size Description Data Notes Type 06 04 MPU External Clock Frequency i
80. is handled by the PCI Arbiter block Parity checking and generation is handled within the PCI Parity block PPC Bus Interface The PPC Bus Interface connects directly to one MPC750 or MPC7400 microprocessor and one peripheral PPC60x master device It uses a subset of the capabilities of the PPC bus protocol http www motorola com computer literature 2 5 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PPC Address Mapping The PHB will map either PCI memory space or PCI I O space into PPC address space using four programmable map decoders These decoders provide windows of access to the PCI bus from the PPC bus The most significant 16 bits of the PPC address are compared with the address range of each map decoder and if the address falls within the specified range the access is passed on to the PCI An example of this is shown in Figure 2 2 PPC Bus Address 8 0 804123 4 151 6 31 1 4 Decodeis gt lt d na D XSADDx Register 7 0 8 0 9 0 0 0 1 31 Figure 2 2 PPC to PCI Address Decoding There are no limits imposed by the PHB on how large of an address space a map decoder can represent There is a lower limit of a minimum of 64KB due to the resolution of the address compare logic For each map there is an associated set of attributes These attributes are used to enable read accesses enable write accesses enable write posting and define the PCI transfer char
81. is running at a higher clock rate than the PCI bus which means the PCI bus can transfer data at a continuous uninterrupted burst while the PPC60x bus transfers data in distributed multiple bursts The PHB write posting mechanism has been tuned to create the most efficient possible data transfer between the two busses during typical operation It is conceivable that some non typical conditions could exist that would upset the default write post tuning of the PHB For example if a PPC60x master is excessively using PPC60x bus bandwidth then the additional latency associated with obtaining ownership of the PPC60x bus might cause the PCI Slave to stall if the PCI FIFO gets full If the PCI Slave is continuously stalling during write posted transactions then further tuning might be needed This can be accomplished by changing WXFT Write Any Fifo Threshold field within the PSATTx registers to recharacterize PHB write posting mechanism The FIFO http www motorola com computer literature 2 11 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller threshold should be lowered to anticipate any additional latencies incurred by the PPC Master on the PPC60x bus Table 2 3 summarizes the PHB available write posting options Table 2 3 PPC Master Write Posting Options WXFT WPEN PPC60x Start PPC60x Continuation XX 0 FIFO 1 dword FIFO 1 dword 00 1 FIFO gt 4 cache lines FIFO gt 1 cache line 01 1 FIFO
82. lock sequence between the times the two locks are released on the PCI bus and the PPC bus accesses to the PCI Slave regardless of who is master is will be retried Delayed Transactions The PCI Slave does not participate in the delayed transaction protocol 2 24 Computer Group Literature Center Web Site Functional Description Fast Back to Back Transactions The PCI Slave supports both of the fundamental target requirements for fast back to back transactions The PCI Slave meets the first criteria of being able to successfully track the state of the PCI bus without the existence of an IDLE state between transactions The second criteria associate with signal turn around timing is met by default since the PCI Slave functions as a medium responder Latency The PCI Slave does not have any hardware mechanisms in place to guarantee that the initial and subsequent target latency requirements are met Typically this is not a problem since the bandwidth of the PPC bus far exceeds the bandwidth of the PCI bus Exclusive Access The PCI Slave fully supports the PCI lock function From the perspective of the PPC bus the PHB enables a lock to a single 32 byte cache line When a cache line has been locked the PHB snoops all transactions on the PPC bus If a snoop hit happens the PHB retries the transaction Note that the retry is benign since there is no follow on transaction after the retry is asserted The PHB contiues t
83. lt DP 0 7 Figure 3 2 Hawk s System Memory Controller Internal Data Paths http www motorola com computer literature 3 3 System Memory Controller SMC DO D1 CS C0 C1 CS BO B1 CS 1 CS BA RA RAS CAS DOM DE gt L SDRAM SDRAM SDRAM SDRAM BLOCK A BLOCK B BLOCK C BLOCK D Figure 3 3 Overall SDRAM Connections 4 Blocks using Register Buffers 3 4 Computer Group Literature Center Web Site Block Diagrams PPC60x Ctrl PPC60x SDRAM MEM Ctrl SLAVE amp INTERFACE ROM Flash CONTROL REFRESHER PPC60x PPC60x SCRUBBER SDRAM MEM Adar y ADDRESS ARBITER ADDRESS DECODER MULTIPLEXOR PPC60x Addr STATUS CONTROL REGISTERS Le 4 INTERFACE 2805 Dats DATA MULTIPLEXOR Figure 3 4 Hawk s System Memory Controller Block Diagram http www motorola com computer literature 3 5 System Memory Controller SMC Functional Description The following sections describe the logical function of the SMC The SMC has interfaces between the PowerPC bus and SDRAM ROM Flash and its Control and Status Register sets CSR SDRAM Accesses Four beat Reads Writes The SMC performs best when doing bursting 4 beat accesses This is made possible by the burst nature of synchronous DRAMs When the PPC60x
84. multiple of its size Remember that bit 0 is MSB http www motorola com computer literature 3 67 System Memory Controller SMC Note that RAM A B C D BASE are located at FEF80018 refer to the section titled SDRAM Base Address Register Blocks A B C D for more information They operate the same for blocks A D as these bits do for blocks E H Also note that the combination of RAM X BASE and ram x siz should never be programmed such that SDRAM responds at the same address as the CSR ROM Flash External Register Set or any other slave on the PowerPC bus SDRAM Speed Attributes Register Address FEF800D0 Bit 10 11 12 en wo vo 20 21 22 23 24 25 26 27 28 29 30 31 19 0 0 tras trasI 0 0 0 0 0 0 0 0 0 0 0 Operation R 2 R 24 04 04 24 04124 04 04 24 24 4 Reset X I P R W cB R W tcO 1 P R W tcI 1 P R W 2 I P R W I P R W 1 P R W swr dplI 14 tdp X IR I P R W 0 1 P R W trcd X IR X p lt MPS P P lt lt OS The SDRAM Speed Attributes Register should be programmed based on the SDRAM device characteristics and the Hawk s operating frequency to ensure reliable operation In order f
85. non processor VPD 02 Transition module VPD 01 1 VR ARCH Vital Product Data Architecture Revision currently at 2 02 1 BUILD Vital Product Data Board Build Revision starts at 0 03 1 VR REASON Vital Product Data Revision Flags 00 Initial release A product must have exactly one VPD revision packet B 12 Computer Group Literature Center Web Site Vital Product Data VPD Introduction SROM CRC C srom crc generate CRC description This function s purpose passed buffer call argument 1 buffer argument 2 number return data unsigned int data for the passed buffer is to generate the CRC for the pointer of elements crc elements p elements n register unsigned char elements p buffer pointer register unsigned int elements n number of elements register unsigned int crc register unsigned int cro flipped register unsigned char cbyte register unsigned int index dbit msb crc Oxffffffff for index 0 index elements n index cbyte elements for dbit 0 dbit 8 dbit crc gt gt 31 crc lt lt 1 amp 1 if msb cbyte amp 1 crc 0 04 11 6 crc 1 cbyte gt gt 1 crc flipped 0 for index 0 index lt crc flipped lt lt 1 dbit cre amp 1 cre gt gt 1 crc_flipped dbit
86. not enable interrupts VECTOR This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgment of the interrupt associated with this vector http www motorola com computer literature 2 123 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller External Source Destination Registers Offset Int Src 0 10010 Int Src 1 gt Int 15 10030 gt 101F0 Bit 3 3 2 2 2 2 2 272 2 2 2 1 1 1 1 1 1 1 1 1 H 10191817165 493 2 1 0 9 8 7 6F 5 4 3 2 1 0 9 871654 3 2 1 0 Name EXTERNAL SOURCE DESTINATION HIS Operation R R R R E E Reset 00 00 00 00 olo This register indicates the possible destinations for the external interrupt sources These interrupts operate in the Distributed interrupt delivery mode P1 PROCESSOR 1 The interrupt is pointed to processor 1 0 PROCESSOR 0 The interrupt is pointed to processor 0 2 124 Computer Group Literature Center Web Site Registers Hawk Internal Error Interrupt Vector Priority Register Offset 10200 Bit 3 3 22 2 2 2 2 2 2 22 1 1 1 1 1g 1 1 i 1 1 1 0 9 8 7 6 5 493 2 1 0 9 8 7 6F 5 4 3 2 110 918 7 6 5 4 3 2 110 Name HAWK INTERNAL ERROR INTERRUPT VECTOR PRIORITY n PRIOR VECTOR E 5 2 fes Operation E R zs R R W Reset lo 000 50 00 00 MASK MASK Setting this bit disab
87. occur A simple way to provide the envelope is to perform at least two accesses to this or another of the SMC s registers before and after the write ank http www motorola com computer literature System Memory Controller SMC Data Parity Error Log Register Address FEF80068 Bit 0 1 2 3 4 5 6 7 10 1 12 13 twp 18 19 20 21 23 24 25 26 27 28 29 30 31 11 2 tt4 dpelog 0 0 tt DPE DP GWDP dpe me Operation READ ONLY READ WRITE PA o Reset R C R R R OP m 0 PL 0 0 0 0 0 0 0 PL R W dpe ckall 22 PS PS lt dpelog dpe tt0 4 DPE DP dpe ckall GWDP dpelog is set when parity error occurs on the PPC60x data bus during a PPC60x data cycle whose parity the SMC is qualified to check It is cleared by writing a one to it or by power up reset dpe tt is the value that was on the TTO TT4 signals when the dpelog bit was set DPE DP is the value that was on the DPO DP7 signals when the dpelog bit was set When dpe ckall is set the Hawk checks data parity on all cycles in which TA is asserted When dpe_ckall is cleared the Hawk checks data parity on cycles when TA_ is asserted only during writes to the Hawk
88. of a PPC60x address parity error causes the int bit to be set if it is not already When the int bit is set the Hawk s internal error interrupt is asserted scien When scien is set the rolling over of the SBE COUNT register causes the int bit to be set if it is not already When the int bit is set the Hawk s internal error interrupt is asserted dpien When dpien is set the logging of a PPC60x data parity error causes the int bit to be set if it is not already When the int bit is set the Hawk s internal error interrupt is asserted http www motorola com computer literature 3 47 System Memory Controller SMC sien When sien is set the logging of a single bit error causes the int bit to be set if it is not already When the int bit is set the Hawk s internal error interrupt is asserted mien When mien is set the logging of a non correctable error causes the int bit to be set if itis not already When the int bit is set the Hawk s internal error interrupt is asserted int int is set when one of the SMC s interrupt conditions occurs It is cleared by reset or by software writing a one to it The Hawk s internal error interrupt tracks int When int is set Hawk s internal error interrupt is asserted When int is cleared Hawk s internal error interrupt is negated mbe When mbe me is set the detection of a multiple bit error during a PowerPC read or write to SDRAM causes the SMC to pulse its machine check inter
89. perform a read access to the Hawks PIACK Register at OXFEFF0030 5 VME should be placed at toe top of PCI memory space Computer Group Literature Center Web Site Memory maps The following table shows the programmed values for the associated Hawk PCI Host Bridge Registers for the suggested Processor Memory Map Table 1 4 Hawk PPC Register Values for Suggested Memory Map Address Register Name Register Name FEFF 0040 MSADDO X000 F3FF X 1 8 FEFF 0044 MSOFFO amp MSATTO 0000 00C2 FEFF 0048 MSADDI FE00 FE7F FEFF 004C MSOFF1 amp MSATTI 0200 00 0 FEFF 0050 MSADD2 0000 0000 FEFF 0054 MSOFF2 amp MSATT2 0000 0000 FEFF 0058 MSADD3 0000 0000 FEFF 005C MSOFF3 amp MSATT3 0000 0000 PCI Memory Map Following a reset the Hawk ASIC disable s all PCI slave map decoders The MVMES100 is fully capable of supporting both PREP and CHRP PCI Memory Maps with RAM size limited to 2GB The default values for the PCI Slave Image registers are listed in Chapter 3 PPCBug of the MVMES100 Single Board Computer Installation and Use manual VME Memory Map The MVMES100 is fully capable of supporting both the PREP and the CHRP VME Memory Maps with RAM size limited to 2GB The default values for the VME Slave Image registers are listed in Chapter 3 PPCBug of the 5 100 Single Board Computer Installation and Use manual http www motorola com computer literature 1 7 Product Data and
90. priority interrupt requests if any from the 8259 If none of the nested interrupt modes of the 8259 are enabled the interrupt handler issues an EOI request to the 8259 2 62 Computer Group Literature Center Web Site Multi Processor Interrupt Controller MPIC The device driver interrupt service routine associated with this interrupt vector is invoked If the interrupt source was not the 8259 the interrupt handler issues an EOI request for this interrupt vector to the MPIC If the interrupt source was the 8259 and any of the nested interrupt modes of the 8259 are enabled the interrupt handler issues an EOI request to the 8259 Normally interrupts from ISA devices are connected to the 8259 interrupt controller ISA devices typically rely on the 8259 Interrupt Acknowledge to flush buffers between the ISA device and system memory If interrupts from ISA devices are directly connected to the MPIC bypassing the 8259 the device driver interrupt service routine must read status from the ISA device to ensure buffers between the device and system memory are flushed Reset State After power on reset the MPIC state is Current task priority for all CPUs set to 15 All interrupt source priorities set to zero All interrupt source mask bits set to a one All interrupt source activity bits cleared Processor Init Register is cleared All counters stopped and interrupts disabled Controller mode
91. s Routed to the Front Panel RJ 45 Connnector COM1 and On Board Header COM2 Dual Ethernet Interfaces one routed to the Front Panel RJ 45 one routed to the Front Panel RJ 45 or optionally routed to P2 RJ 45 on MVME761 Tundra Universe Controller 64 bit PCI Programmable Interrupter amp Interrupt Handler Programmable DMA Controller With Link List Support Full System Controller Functions Two 32 64 bit PMC Slots with Front Panel I O Plus P2 Rear I O MVME2300 Routing One PCI Expansion Connector for the PMCSpan Combined RESET and ABORT Switch Status LEDs VME VMEbus PCI PMC Expansion Miscellaneous Form Factor 1 2 Computer Group Literature Center Web Site Introduction The following block diagram illustrates the architecture of the MVMES100 Single Board Computer L2 Cache 1 2 Mezzanine SDRAM 2 32MB to 512MB x SDRAM 3 32MB to 512MB Processor 5 750 Max S M T Hawk Asic Clock System Memory Controller SMC Generator E and PCI Host Bridge PHB ES Hawk X bus System Registers TL16C550 UART 9pin RTC NVRAM WD M48T37V 33 MHz 32 64 bit PCI Local Bus P 2 64 bit PMC Slots TL16C550 UART DEBUG RJ45 Ethernet 1 Ethernet 2 VME Bridge 10 100TX 10 100TX Universe 2 10 100
92. section titled Vendor Device Register for more information b Make sure the CLK Frequency Register matches the operating frequency c Waitfor atleast one SDRAM refresh to complete A simple way to do this is to wait for the 32 bit counter to increment at least 100 times refer to the section on 32 Bit Counter for more information Note that the refdis control bit must not be set in the ECC Control Register d Make sure that the SDRAM Speed Attributes Register contains its power up reset values If not make sure that the values match the actual characteristics of the SDRAM being used e Make sure the following bits are initialized as follows refdis 0 rwcb 0 derc scien 0 dpien 0 sien 0 mien 0 SCRUB FREQUENCY 00 Refer to the ECC Control Register section and the Scrub Refresh Register section for more information f Make sure that ROM Flash banks A and B are not enabled to respond in the range 00000000 20000000 Refer to the section on ROM A Base Size Register and ROM B Base Size Register for more information g Make sure that no other devices are set up to respond in the range 00000000 20000000 http www motorola com computer literature 3 83 System Memory Controller SMC 2 For each of the Blocks A through H a Set the block s base address to 00000000 Refer to the sections titled SDRAM Base Address Register Blocks A B C D and SDRAM Enable and Size Register Block
93. set to 8259 pass through http www motorola com computer literature 2 63 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Operation Interprocessor Interrupts Four interprocessor interrupt IPI channels are provided for use by all processors During system initialization the IPI vector priority registers for each channel should be programmed to set the priority and vector returned for each IPI event During system operation a processor may generate an IPI by writing a destination mask to one of the IPI dispatch registers Note that each IPI dispatch register is shared by both processors Each IPI dispatch register has two addresses but they are shared by both processors That is there is a total of four IPI dispatch registers in the MPIC The IPI mechanism may be used for self interrupts by programming the dispatch register with the bit mask for the originating processor Dynamically Changing Interrupt Configuration The interrupt controller provides a mechanism for safely changing the vector priority or destination of I O interrupt sources This is provided to support systems which allow dynamic configuration of I O devices In order to change the vector priority or destination of an active interrupt source the following sequence should be performed Mask the source using the MASK bit in the vector priority register Wait for the activity bit ACT for that source to be cleared Make the desi
94. software programs the size bits it should wait for a refresh to happen before beginning to access SDRAM 12 EEPROMs Most of the information needed to program the SDRAM speed attributes and size is provided by EEPROM devices that are connected to Hawk s bus The EEPROM devices contain data in a specific format called Serial Presence Detect SPD SDRAM Base Address and Enable Each block needs to be programmed for a unique base address that is an even multiple of its size Once a block s speed attributes size and base address have been programmed and time for at least one refresh has passed it can be enabled 3 76 Computer Group Literature Center Web Site Software Considerations SDRAM Control Registers Initialization Example The following is a possible sequence for initializing SDRAM control registers 1 Get a small piece of SDRAM for software to use for this routine optional This routine assumes that SDRAM related control bits are still at the power up reset default settings We will use a small enough piece of SDRAM that the address signals that are affected by SDRAM size will not matter For each SDRAM block a Set the block s base address to some even multiple of 32MB refer to the section titled SDRAM Base Address Register Blocks A B C D for more information b Set the block s size to 4Mx16 and enable it refer to the section titled SDRAM Enable and Size Register Blocks A B C D for more
95. the CONFIG ADDRESS register are not subject to the Endian function The data associated with PIACK accesses is subject to the Endian swapping function The address of a PIACK cycle is undefined therefore address modification during Little Endian mode is not an issue Error Handling The PHB is capable of detecting and reporting the following errors to one or more PPC masters XBTO PPC address bus time out XDPE PPC data parity error PSMA PCI master signalled master abort PRTA PCI master received target abort PPER PCI parity error PSER PCI system error Each of these error conditions will cause an error status bit to be set in the PPC Error Status Register ESTAT If a second error is detected while any of the error bits is set the OVFL bit is asserted but none of the error bits are changed Each bit in the ESTAT may be cleared by writing a 1 to it writing a 0 to it has no effect New error bits may be set only when all previous error bits have been cleared http www motorola com computer literature 2 41 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller When any bit in the ESTAT is set the PHB will attempt to latch as much information as possible about the error in the PPC Error Address EADDR and Attribute Registers EATTR Information is saved as follows Error Error Address and Status Attributes XBTO From PPC bus XDPE From PPC bus PRTA From PCI
96. the current bus master to recover from a potential lock up condition caused when there is no response to a transfer request The time out length of the bus timer is determined by the XBT field within the GCSR The PPC Timer is designed to handle the case where an address tenure is not closed out by the assertion of AACK The PPC Timer will not handle the case where a data tenure is not closed out by the appropriate number of TA assertions The PPC Timer starts timing at the exact moment when the PPC60x bus pipeline has gone flat In other words the current address tenure is pending closure all previous data tenures have completed and the current pending data tenure awaiting closer is logically associated with the current address tenure The time out function is aborted if AACK is asserted anytime before the time out period has passed If the time out period reaches expiration then the PPC Timer asserts AACK to close the faulty address tenure If the transaction was an address only cycle then no further action is taken If the faulty transaction was a data transfer cycle then the PPC Timer asserts the appropriate number of TA signals to close the pending data tenure Error information related to the faulty transaction will be latched within the ESTAT EADDR and EATTR registers and an interrupt or machine check will be generated depending on the programming of the ESTAT register There are two exceptions that dynamically disable the PPC Ti
97. this point because while rwcb is set DRAM will not function as normal memory 3 Set the derc and rwcb bits in the Data Control register 4 Perform the desired read and or write check bit operations 3 46 Computer Group Literature Center Web Site Programming Model 5 Clear the dere and rweb bits in the Data Control register 6 Perform the desired testing related to the location locations that have had their check bits altered 7 Enable scrub writes by setting the swen bit if it was set before derc Setting derc to one alters SMC operation as follows 1 During reads data is presented to the PPC60x data bus uncorrected from the SDRAM array 2 During single beat writes data is written without correcting single bit errors that may occur on the read portion of the read modify write Check bits are generated for the data being written 3 During single beat writes the write portion of the read modify write happens regardless of whether there is a multiple bit error during the read portion No correction of data is attempted Check bits are generated for the data being written 4 During scrub cycles if swen is set a read writes to SDRAM happens with no attempt to correct data bits Check bits are generated for the data being written derc is useful for initializing SDRAM after power up and for testing SDRAM but it should be cleared during normal system operation apien When apien is set the logging
98. whenever it terminates a transaction with a target abort It is cleared by writing it to 1 writing a 0 has no effect RCVTA Received Target Abort This bit is set by the PCI Master whenever its transaction is terminated by a target abort It is cleared by writing it to 1 writing a 0 has no effect RCVMA Received Master Abort This bitis set by the PCI Master whenever its transaction except for Special Cycles is terminated by a master abort It is cleared by writing it to 1 writing a 0 has no effect SIGSE Signaled System Error This bit is set whenever the PHB asserts SERR It is cleared by writing it to 1 writing a 0 has no effect RCVPE Detected Parity Error This bit is set whenever the PHB detects a parity error even if parity error checking is disabled see bit PERR in the PCI Command Register It is cleared by writing it to 1 writing a 0 has no effect 2 100 Computer Group Literature Center Web Site Registers Revision ID Class Code Registers Offset Bit Name CLASS REVID Operation R R Reset 060000 01 REVID Revision ID This register identifies the PHB revision level This register is duplicated in the PPC Registers CLASS X Class Code This register identifies PHB as the following Base Class Code 06 PCI Bridge Device Subclass Code 00 PCI Host Bridge Program Class Code 00
99. will be loaded into the 2 Transmitter Data Register to be transmitted to the slave device Again i cmplt 2 ackin bits must be tested for proper response At this point the slave device is still in a write mode Therefore another start sequence must be sent to the slave to change the mode to read by first setting the i start and 12 enbl bits in the Control Register and then writing the device address bits 7 1 and read bit bit 021 to the PC Transmitter Data Register After i cmplt and i ackin bits have been tested for proper response the master controller writes a dummy value data don t care to the Transmitter Data Register This causes the PC master controller to initiate a read transmission from the slave device Again i2_cmplt bit must be tested for proper response After the rc master controller has received a byte of data indicated by i7_datin 1 in Status Register the system software may then read the data by polling the I C Receiver Data Register The master controller does not acknowledge the read data for a single byte transmission on the PC bus but must complete the transmission by sending a stop sequence to the slave device This can be accomplished by first setting the 12 stop and 12 enbl bits in the I7C Control Register and then writing a dummy data data don t care to the Transmitter Data Register The PC Status Register must now be polled to test i cmplt bit for th
100. www motorola com computer literature 2 21 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PCI Slave MPIC Control Registers The MPIC control registers are located within either PCI Memory or PCI I O space using traditional PCI defined base registers within the predefined 64 byte header Refer to the section titled Multi Processor Interrupt Controller MPIC for more information The PCI Slave provides the control logic needed to interface the PCI bus to the PCI FIFO The PCI Slave can accept either 32 bit or 64 bit transactions however it can only accept 32 bit addressing There is no limit to the length of the transfer that the PCI Slave can handle During posted write cycles the PCI Slave will continue to accept write data until the PCI FIFO is full If the PCI FIFO is full the PCI Slave will hold off the master with wait states until there is more room in the FIFO The PCI Slave will not initiate a disconnect If the write transaction is compelled the PCI Slave will hold off the master with wait states while each beat of data is being transferred The PCI Slaveissues TRDY only after the data transfer has successfully completed on the PPC bus If a read transaction is being performed within an address space marked for prefetching the PCI Slave in conjunction with the PPC Master attempts to read ahead far enough on the PPC bus to allow for an uninterrupted burst transaction on the PCI bus Read transactions within ad
101. 0 9 1 O 9 877 6 5 4 Name EOI Operation R R R R W Reset 00 00 00 0 0 EOI END OF INTERRUPT There is one EOI register per processor EOI Code values other than 0 are currently undefined Data values written to this register are ignored Zero is assumed Writing to this register signals the end of processing for the highest priority interrupt currently in service by the associated processor The write operation will update the In Service register by retiring the highest priority interrupt Reading this register returns zeros 2 128 Computer Group Literature Center Web Site System Memory Controller SMC Introduction The SMC in the Hawk ASIC is equivalent to the former Falcon Pair portion of a Falcon Raven chipset The SMC has interfaces between the PPC60x bus and SDRAM ROM Flash and its Control and Status Register sets CSR Note that the term SDRAM refers to Synchronous Dynamic Random Access Memory and is used throughout this document Overview This chapter provides a functional description and programming model for the SMC portion of the Hawk Most of the information for using the device in a system programming it in a system and testing it is contained here Bit Ordering Convention SMC bused signals are named using Big Endian bit ordering bit 0 is the most significant bit except for the RA signals which use Little Endian bit ordering bit 0 is the least significant bit Features SDRAM In
102. 00 2 102 Computer Group Literature Center Web Site Registers The MPIC Memory Base Address Register MMBAR controls the mapping of the MPIC control registers in PCI memory space IO MEM IO Space Indicator This bit is hard wired to a logic zero to indicate PCI memory space MTYPx Memory Type These bits are hard wired to zero to indicate that the MPIC registers can be located anywhere in the 32 bit address space PRE Prefetch This bit is hard wired to zero to indicate that the MPIC registers are not prefetchable BASE Base Address These bits define the memory space base address of the MPIC control registers The MBASE decoder is disabled when the BASE value is zero PCI Slave Address 0 1 2 and 3 Registers Offset PSADDO 80 PSADDI 88 2 90 PSADD3 98 Bit 3 3 2 2 2 2 2 272 2 2 2 1 1 1 1 1g 1 1 i 1 1 1 0 9 8 7 6 5 43210987 675 4 3 2 1 0 9 8F 7 6 54 3210 Name PSADDx START END Operation R W R W Reset 0000 0000 http www motorola com computer literature 2 103 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller The PCI Slave Address Registers PSADDx contain address information associated with the mapping of PCI memory space to PPC memory space The fields within the PSADDx registers are defined as follows START Start Address This field determines the start address of a parti
103. 00 8 no change Note only legal data lengths supported in Little Endian mode are 1 2 4 or 8 byte aligned transfers Since this method has some difficulties dealing with unaligned PCI originated transfers the PPC master of the PHB will break up all unaligned PCI transfers into multiple aligned transfers into multiple aligned transfers on the PPC bus PHB Registers The PHB registers are not sensitive to changes in Big Endian and Little Endian mode With respect to the PPC bus but not always the address internal to the processor the PPC registers are always represented in Big Endian mode This means that the processor s internal view of the PPC registers appears different depending on which mode the processor operates With respect to the PCI bus the configuration registers are always represented in Little Endian mode 2 40 Computer Group Literature Center Web Site Functional Description The ADDRESS and CONFIG DATA registers are actually represented in PCI space to the processor and are subject to the Endian functions For example the powerup location of the CONFIG ADDRESS register with respect to the PPC bus is 80000cf8 when the PHB is in Big Endian mode When the PHB is switched to Little Endian mode the CONFIG ADDRESS register with respect to the bus 15 80000cfc Note that in both cases the address generated internal to the processor will be 80000cf8 The contents of
104. 00002 2 1 EFF007C FFFFFFFE FFFFFFFF EEERBFIBEN aree PC6 Bug mw feff0068 55 b Effective address FEFF0068 Effective data 55 o Hj Hj Hj UU ou B Hj 2 94 Computer Group Literature Center Web Site Registers PPC6 Bug mw feff0068 aa88 h Effective address FEFFO0068 Effective data AA88 PPC6 Bug md feff006c 0000000 m 80 EFFOO06C 0000B26D 03 4000 00000000 EFF007C FFFFFFFE FFFFFFFF EFEFEREN ER PC6 Bug md feff006c EFFOO6C 00006145 03 4000 0000000 aE Q FFFFFFFFT 000 00000 EFF007C FFFFFFFE FFFFFFFE nr UR PC6 Bug md feff0068 EFF0068 0088FFFF 00000000 4000 EFF0078 00000000 FFFFFFFE PERRREE 242554 ee wee PC6 Bug md feff006c EFFO06C 00000000 03 4000 0000000 65 000 00000 EFF007C FFFFFFFE PEPPER PC6 Bug md feff0068 EFF0068 0088FFFF 00000000 0000000 65 6 FFFFFFFFT 4000 0 0 F E P 00000000 Quos E F P F 0 E 0 FEFFFEPP PPC6 Bug EFF0078 00000000 FFFFFFFE FFFFFFFE http www motorola com computer literature 2 95
105. 0011 Write Unsupported 0100 Reserved Unsupported 0101 Reserved PPC Mapped PCI Space Read 1 1 0110 Memory Read Write 1 011 Memory Write Unsupported 1000 Reserved Unsupported 1001 Reserved CONADD CONDAT Read X 1010 Configuration Read CONADD CONDAT Write 1011 Configuration Write Unsupported 1100 Memory Read Multiple http www motorola com computer literature 2 27 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Table 2 8 PCI Master Command Codes Continued Entity Addressed PPC TBST MEM PCI Command Transfer Type Unsupported 1101 Dual Address Cycle PPC Mapped PCI Space Read 0 1 1110 Memory Read Line Unsupported 1111 Memory Write and Invalidate Addressing The PCI Master generates all memory transactions using the Linear Incrementing addressing mode Combining Merging and Collapsing The PCI Master does not participate in any of these protocols Master Initiated Termination The PCI Master can handle any defined method of target retry target disconnect or target abort If the target responds with a retry the PCI Master waits for the required two clock periods and attempts the transaction again This process continues indefinitely until the transaction is completed the transaction is aborted by the target or if the transaction is aborted due to a PHB detected bridge lock The same happe
106. 0044 XSOFFO XSATTO Computer Group Literature Center Web Site Registers Table 2 16 PPC Register Map for PHB Continued Bit gt 1111111011 2121212121233 011213 4560789012345 617 8 4 5 6 7 8 9 0 1 FEFF0048 XSADDI FEFF004C XSOFFI XSATTI FEFF0050 XSADD2 FEFF0054 XSOFF2 XSATT2 FEFF0058 XSADD3 FEFF005C XSOFF3 XSATT3 FEFF0060 WDTICNTL FEFF0064 WDTISTAT FFEF0068 WDT2CNTL FEFF006C WDT2STAT FEFF0070 GPREGO Upper FEFF0074 GPREGO Lower FEFF0078 GPREGI Upper FEFF007C GPREGI Lower http www motorola com computer literature 2 69 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Vendor ID Device ID Registers Address FEFF0000 Bit 1 1 1 1 1 1 2 1 1 1 2 2 2 272 2 2 2 2 2 3 3 0111213141516 7181910112134 5161718901112 39 4 5 6 7 8 9 0 1 Name VENID DEVID Operation R R Reset 1057 4803 VENID Vendor ID This register identifies the manufacturer of the device This identifier is allocated by the PCI SIG to ensure uniqueness 1057 has been assigned to Motorola and is hardwired as a read only value This register is duplicated in the PCI Configuration Registers DEVID Device ID This register identifies this particular device The Hawk will always return 4803 This register is duplicated in the PCI Configuration Registers Revision ID Regi
107. 1 9 E2 Cache SRAM SESE eiennenn E 1 10 1 10 PLAS EL oi poeta aad P 1 10 uu T 1 11 P2 VO tol T 1 11 Serial Presence Detect SPD 1 12 lc P NI a Q 1 12 Hawk I2C interface and configuration information sees 1 13 Vital Product Data VPD and Serial Presence Detect SPD Data 1 14 PCI EP INL T iene 1 15 PCI Arbitration Assignments for Hawk ASIC 2 2 22 2 1 15 The Ethernet Controller 1 16 PNICIPCT EXpansiODn Slots eed a E 1 17 vii ed nen nO eer eer 1 17 PET COMTEP UPSETS o T 1 19 Hawk External Register Bus Address Assignments sees 1 21 MVMES100 Hawk External Register Bus Summary 1 21 Dynal UNT Bes LEUR 1 23 BR COSTER qe 1 24 MODPAIL Bit 1 25 MODEST Bit 1 26 Dali Gu 1 27 NVRAMI
108. 14 H Hardware Control Status Register 2 77 Hawk address parity 3 10 as MPU PCI bus bridge controller ASIC 1 15 block diagram 2 3 configuration options 3 35 data parity 3 10 ECC Codes 3 86 Error Correction Codes 3 86 error notification and handling 4 6 I2C Byte Write 3 23 I2C Current Address Read 3 27 I2C Page Write 3 29 I2C Random Read 3 25 I2C Sequential Read 3 31 MPIC control registers 2 22 MPIC interrupt assignments 4 1 MPIC interrupts 4 1 MPIC register map 2 110 PCI Host Bridge amp Multi Processor In terrupt Controller chip 2 1 programming details 4 1 programming ROM Flash devices 3 74 SMC 3 1 software considerations 3 74 System Memory Controller block dia gram 3 3 used with DRAM in a system 3 2 writing to the control registers 3 74 Hawk ASIC 1 12 Hawk External Register Bus Summar 1 21 Hawk I2C interface and configuration infor mation 1 13 Hawk PCI Host Bridge 1 2 Hawk System Memory Controller 1 2 Hawk s DEVSEL pin as criteria for PHB config mapping 2 19 Hawk s I2C bus 3 76 Hawk s PCI arbiter priority schemes 2 35 Hawk s SMC overview 3 1 HCSR Hardware Control Status Register 2 77 Header Type Register 2 101 Base Register MPIC 2 102 Dc Byte Write Hawk 3 23 Current Address Read Hawk 3 27 EEPROMs 3 76 Page Write Hawk 3 29 Random Read Hawk 3 25 Sequential Read Hawk 3 31 I2C Receiver Data Register 3 66 IDSEL Mapping for PCI Devices 1 19 initializing SDRAM related control registers 3 75 Inter
109. 2 Add together sum all decimal values for addresses 0 62 3 Divide the sum by 256 4 Convert the remainder to binary will be less than 256 5 Store the result single byte in address 63 as Checksum Note same result can be obtained by adding the binary values in addresses 0 62 and eliminating all but the low order byte The low order byte is the Checksum http www motorola com computer literature B 15 MVMES100 VPD Reference Information Example of a Checksum Calculation SPD Byte Address Serial PD Convert to Decimal 00 0x00 0010 0100 gt 36 01 0 01 11111110 gt 254 02 0 02 0000 0000 gt 0 03 0 03 0000 0000 gt 0 gt 0 gt 60 0 3 0000 0000 gt 0 61 0x3D 0000 0000 gt 0 62 Ox3E 0000 0000 gt 0 SPD Byte Address Serial PD Convert to Decimal Decimal Total 290 Divide by 256 1 Remainder 34 Convert to binary 0010 0010 lt 34 63 0x3F Checksum 0010 0010 B 16 Computer Group Literature Center Web Site Index Numerics 32 Bit Counter 3 72 SMC 3 72 8259 Interrupts 4 3 A A0 A31 3 4 AACK as used with PPC Slave 2 7 access timing ROM 3 19 3 20 address Address Parity Error Address Register 3 71 Address Parity Error Log Register SMC 3 70 data stepping 2 29 decoders PCI to PPC 2 6 decoders PPC to PCI 2 7 limits on PHB map decoding 2 6 mapping PPC 2 6 modification for little endian t
110. 2 16 prioritization schemes 2 16 PPC Arbiter Control Register 2 73 PPC Error Address Register 2 84 PPC Error Attribute Register EATTR 2 85 PPC Error Enable Register 2 79 PPC Error Status Register 2 82 PPC Slave Address 0 1 and 2 Registers 2 88 PPC Slave Address 3 Register 2 89 PPC Slave Address Register 2 90 PPC Slave Offset Attribute 0 1 and 2 Reg isters 2 91 PPC60x Bus Interface SMC 3 9 PPC60x Data Parity 3 10 Prescaler Adjust Register 2 77 priority schemes described PCI arbiter 2 35 PRK as used in arbitration parking 2 37 Processor Init Register 2 116 processor internal clock frequenc 1 9 Processor Memory Map 1 4 Processor PLL Configuration 1 9 Processor Type Identification 1 9 Processor Version Register PVR 1 9 processor memory domain MPC750 4 9 Processors 1 9 programmable DMA Controller 1 2 Programmable Lock Resolution 2 46 programming details 1 1 4 1 programming information added resources xxi programming ROM Flash devices 3 74 PVR value 1 9 R RAM A BASE 3 43 3 67 RAM B BASE 3 43 3 67 RAM C BASE 3 43 3 67 RAM D BASE 3 43 3 65 3 66 3 67 read ahead mode in PPC Master 2 12 Read Write Checkbits control bit 3 45 Read Write to ROM Flash 3 55 refdis 3 45 refresh scrub 3 34 SMC 3 34 Refresh Scrub Address Register SMC 3 52 register Status 1 24 register bit descriptions SMC 3 38 register map 2 68 PCI 2 97 PPC 2 68 register summary 3 36 registers CLK Frequency 3 44 CONFIG_ADDRESS 2 106 CONFIG_DAT
111. 2 8 transfer types generated by PPC Master 2 13 PCI command code dependent 2 13 PPC60x bus 2 13 triple or greater bit error 3 12 Tundra Universe Controller 1 2 U Universe ASIC 1 17 Universe chip problems after a PCI reset 4 5 Universe VMEbus interface ASIC 1 8 1 15 User configuration Data 1 13 Vendor ID Device ID Registers 2 98 Vendor ID Device ID Registers 2 70 Vendor Identification Register 2 116 Vendor Device Register SMC 3 39 Vital Product Data 1 10 1 13 Vital Product Data VPD B 1 VME Processor Module MVMES510x 1 1 VMEbus 1 2 memory map 1 8 memory maps 1 8 IN 10 Computer Group Literature Center Web Site VPD B 1 VPD FLASH Memory Configuration Data B 9 VPD L2 Cache Configuration Data B 10 VPD Product Configuration Options B 7 VPD Revision Data B 12 VPD definitions B 4 VPD SROM 1 10 VPD SPD explained 1 14 Watchdog Timer registers 2 43 watchdog timers as part of PHB 2 42 WDTXxCNTL register 2 43 WDTXCNTL Registers 2 92 WDTXxSTAT Registers 2 96 write posting as part of PHB tuning 2 11 writing to the control registers 3 74 http www motorola com computer literature IN 11 lt moz Index IN 12 Computer Group Literature Center Web Site
112. 2 bit crc protection Base address information for various components Direct Memory Addresses Interrupt resources How to Read the VPD Information There are several ways to read VPD information Q Version command ver B 1 MVMES100 VPD Reference Information Displays most of the identification strings and hardware clock frequencies Serial EEPROM command srom i Can be used as a byte viewer Indirect block move command ibm addr i Reads the entire SROM block to memory Memory display command md lt addr gt Can be used to display a VPD block which has been copied to memory Network I O physical command niop Can be used to upload a VPD block from memory to a network file How to Modify the VPD Information The following commands can be used to modify the VPD information in various Ways Serial EEPROM command srom i Can be used as a byte editor Network I O physical command niop Can be used to download a VPD block from a network file to memory Indirect block move command ibm lt addr gt iw Writes a block of memory into the SROM SROM update command update Updates each SROM on the board to the current revision using network files B 2 Computer Group Literature Center Web Site Vital Product Data VPD Introduction What Happens if the VPD Information is Corrupted If for some reason the VPD information becomes co
113. 3 2A rd19 8A rd35 A2 rd51 A8 ckd3 08 rd4 E9 rd20 7A rd36 9E rd52 A7 ckd4 10 rd5 1C rd21 07 rd37 1 rd53 70 ckd5 20 rd6 1A rd22 86 rd38 AI rd54 68 ckd6 40 rd7 19 rd23 46 rd39 91 rd55 64 ckd7 80 rd8 25 rd24 49 rd40 52 rd56 94 rd9 26 rd25 89 rd41 62 rd57 98 410 16 rd26 85 rd42 61 rd58 58 11 15 rd27 45 rd43 51 rd59 54 rd12 F4 rd28 3D rd44 4F rd60 D3 rd13 0E rd29 83 rd45 EO rd61 38 rd14 0D rd30 43 rd46 D0 rd62 34 rd15 8C rd31 23 rd47 C8 rd63 32 3 86 Computer Group Literature Center Web Site ECC Codes Table 3 22 Single Bit Errors Ordered by Syndrome Code Syn Bit Syn Bit Syn Bit Syn Bit Syn Bit Syn Bit Syn Bit Syn Bit drome drome drome drome drome drome drome drome 00 20 5 40 ckd6 60 80 7 00 EO rd45 01 ckdO 21 41 61 42 81 A1 rd38 C1 rd37 1 02 22 42 62 41 82 A2 rd35 C2 rd34 2 03 23 rd31 43 63 83 29 A3 C3 04 2 24 44 64 rd55 84 A4 rd32 C4 rd33 4 05 25 45 rd27 65 85 26 A5 C5 E5 06 26
114. 3 Interrupt Some iso ent up 2 53 Processar Current Task PUOPIE oe ieri RN REP RUE 2 54 or Intent EXE d retire baie d aes 2 54 Spurious Vector sese ape RR MED Uv ipe 2 54 Interprocessor Interropts IPU bur tt mater eres A ANI IUS 2 55 Db us apis ipe ipt ees a 2 55 Hawk Miena Error 2 55 BL IIT ET 2 56 luca Delivery oor 2 56 Block Diagram Description uas pec 2 57 Program Visible RESIS 2 59 Interrupt Pending Register 2 59 2 59 Interrupt Request Register 2 60 2 60 cuui deii e 2 60 NODBRL i oeil cece Ema bd 2 62 Interrupt SEUyIPBgs usuras ceu Ce edite rud Hep ir plor 2 62 D Me Lm 2 63 ASOT ANTON MP 2 64 aae uitio ap ope last ede vede iq ed
115. 3 49 Error Address U RSEN ARIA 3 51 Seno Registe aao eeepc erteilen sep DARE i pert 3 51 Senb Address e Eie qeu 3 52 ROM A Register ui odo eae Gabi BIER S bee 3 53 ROM B pb pe RUM I See 3 56 ROM Speed Attributes Remsters ones Rape penis 3 58 Data Parity Emor Log Gather socane ER UHR 3 60 Data Panty Error Address Register iuste t ep anpe 3 61 Data Panty Error Upper Data Registet cue iecore aet ebd tede 3 61 Data Parity Error Lower Data Register icm emite 3 62 LC C Ine Prosesler acing ied aea atado dete 3 63 DC Control Basler o cose iode pH n UI pi ie Pie ea 3 63 M rou MR 3 64 DC Transmitter Data Register RAV EM Ee 3 65 PE Recemer Data Be esters Uia I 3 66 SDRAM Enable and Size Register Blocks E F G H 3 66 SDRAM Base Address Register Blocks 3 67 SDRAM Speed Attributes Rester oie e ett sense ten ran kenne teens 3 68 Address Panty Error Log Register sau eus tre ett tb EI Uniti ie qon Eos eges 3 70 Address Parity Exror Address Register eene 3 71 Ec dpA n
116. 5 RD6 RD7 FIELD Jd gt lt oO a OPER R R R R R R R R RESET x x x x x x x x REQUIRED OPTIONAL PCIXP L PCI Expansion Slot Present If set there is no PCIX device installed If cleared the PCIX slot contains a PCI Mezzanine Card http www motorola com computer literature Product Data and Memory Maps 1 34 Computer Group Literature Center Web Site Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Introduction Overview Features This chapter describes the architecture and usage of the PowerPC to PCI Host Bridge PHB and the Multi Processor Interrupt Controller MPIC portion of the Hawk ASIC The Hawk is intended to provide PowerPC 60x PPC60x bus compliant devices access to devices residing on the PCI Local Bus In the remainder of this chapter the PPC60x bus is referred to as the PPC bus and the PCI Local Bus as PCI PCI is a high performance 32 bit or 64 bit burst mode synchronous bus capable of transfer rates of 132M B sec in 32 bit mode or 264MB sec in 64 bit mode using a 33 MHz clock Bus Interface Direct interface to MPC750 or MPC7400 processor 64 bit data bus 32 bit address bus Four independent software programmable slave map decoders Multi level write post FIFO for writes to PCI Support for PPC bus clock speeds up to 100 MHz Selectable big or little endian operation 33 signal levels PCI Interface
117. 600 2700 models PMC mode is backwards compatible with the MVME2300 and MVME2400 models The SBC mode is accomplished by configuring planar jumpers and attaching an IPMC761 PMC card in PMC slot 1 of the 5100 Refer to the 712 761 I O Module Installation and Use manual for additional installation and programming information PMC mode is accomplished by configuring planar jumpers The P2 IO mode jumper configuration for the SBC and PMC modes are described in the MVME5100 Single Board Computer Installation and Use manual Serial Presence Detect SPD Definitions The MVMES100 SPD uses the SPD JEDEC standard definition On board SPD for SDRAM Bank A or both A and B of the Hawk is accessed at Address A8 Only Bank A or Banks A and B may be populated If both Banks A and B are populated they will be of the same speed and memory size Memory Mezzanine 1 SPD for SDRAM Bank C of the Hawk is accessed at Address AA Memory Mezzanine 2 SPD for SDRAM Bank E of the Hawk is accessed at address AC The SPD format conforms to the JEDEC industry standard JESD21 C Hawk ASIC The Hawk ASIC provides the bridge function between the 60 bus and the PCI local bus It provides 32 bit addressing and 64 bit data The 64 bit addressing capability dual address cycle is not supported The Hawk supports various PowerPC processor external bus frequencies up to 100M Hz There are four programmable map decoders for each direction to provide fl
118. 64K Zero based PCI ISA I O Space 8081 0000 FEF7 FFFF 2GB 24MB 576KB_ Not Mapped FEF8 0000 FEF8 64KB System Memory Controller Registers 1 4 Computer Group Literature Center Web Site Memory maps Table 1 2 Default Processor Memory Map Continued Processor Address Size Definition Start End FEF9 0000 FEFE FFFF 384KB Not Mapped FEFF 0000 FEFF FFFF 64KB PCI Host Bridge PHB Registers 00 0000 15 Not Mapped FFFO 0000 FFFF FFFF 1 ROM FLASH Bank or Bank B See Note Note The first IMB of ROM FLASH Bank A soldered Flash up to 8MB appears in this range after a reset if the rom b rv control bit in the SMC s ROM B Base Size register is cleared If the rom b rv control bit is set this address range maps to ROM FLASH Bank B socketed 1MB Flash For an example of the CHRP memory map refer to the following table For detailed processor memory maps including suggested CHRP and PREP compatible memory maps refer to the Hawk related portion of this manual Processor Memory Map The following table describes a suggested CHRP Memory Map from the point of view of the processor This memory map is an alternative to the PREP memory map Note in all recommended CHRP maps the beginning of PCI Memory Space is determined by the end of DRAM rounded up to the nearest 256MB boundry as required by CHRP For example if memory was 1G on the baseboar
119. 8 16Mx4 00000000 00000000 00000000 00000000 00000000 00000000 00008000 00004000 00008000 04000000 00004000 00004000 10000000 08000000 64MB 64MB 32MB 8Mx16 8Mx8 4Mx16 00000000 00000000 00000000 00002000 00002000 00001000 Notes 1 16 8 and 16Mx4 are the same If the real size is either one of these this algorithm will program for 16Mx8 regardless of whether the SDRAM size is 16Mx8 or 16Mx4 This is not a problem because the Hawk behaves identically when programmed for either size 2 8Mx16 and 8 8 are the same The same idea that applies to 16Mx8 and 16Mx4 applies to them 3 This needed only to check for non zero size 3 Wait enough time to allow at least 1 SDRAM refresh to occur before beginning any SDRAM accesses http www motorola com computer literature System Memory Controller SMC ECC Codes When the Hawk reports a single bit error software can use the syndrome that was logged by the Hawk to determine which bit was in error Table 3 2 shows the syndrome for each possible single bit error Table 3 22 shows the same information ordered by syndrome Table 3 21 Syndrome Codes Ordered by Bit in Error Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome 0 4 416 592 rd32 A4 rd48 29 0 01 rdl 4C rd17 13 rd33 4 rd49 31 ckdl 02 rd2 2C rd18 0B rd34 C2 rd50 BO ckd2 04 rd
120. 86 error detection 3 11 error handling 2 41 Error Logger Register 3 49 SMC 3 49 error logging 3 13 SMC 3 13 error notification and handling 4 6 Hawk 4 6 error reporting 3 12 ERROR ADDRESS 3 51 ERROR SYNDROME 3 50 esbt 3 50 escb 3 49 3 49 Ethernet Controller 1 16 Ethernet Interfaces 1 2 exceptions when programming MVMES100 4 5 exclusive access 2 29 PCI Slave 2 25 Extended Features Register 1 1 30 Extended Features Register 2 1 32 External Register Set SMC 3 34 3 72 external register set reads and writes 3 35 External Source Destination Registers 2 124 External Source Vector Priority Registers 2 122 F fast back to back transactions 2 29 PCI Slave 2 25 Feature Reporting Register 2 113 features 2 1 SMC 3 1 FIFO from PPC Slave to PCI Master 2 9 structure explained 2 4 with PCI Slave 2 26 Flash see ROM Flash 3 14 Flash Blocks A and B 1 10 FLASH Memory 1 1 Flash Memory 1 10 Form Factor MVMES100 1 2 four beat reads writes 3 6 functional description Hawk PHB 2 4 SMC 3 6 FUSE signal 1 24 G General Control Register SMC 3 39 General Control Status Feature Registers 2 71 General Purpose Registers 2 96 generating PCI configuration cycles 2 31 PCI cycles 2 29 PCIinterrupt acknowledge cycles 2 34 PCI memory and I O cycles 2 30 PCI special cycles 2 33 Geographical Address Register 1 30 http www motorola com computer literature IN 3 lt moz xXmoz Index Global Configuration Register 2 1
121. A 2 109 Current Task Priority 2 127 End of Interrupt 2 128 External Source Destination 2 124 External Source Vector Priority 2 122 Feature Reporting 2 113 General Purpose 2 96 Global Configuration 2 114 Hardware Control Status Register 2 77 Header Type 2 101 Interprocessor Interrupt Dispatch 2 126 Interrupt Acknowledge 2 127 http www motorola com computer literature IN 7 lt moz lt moz Index IPI Vector Priority MPIC 2 117 MPIC 2 110 MPIC I O Base Address 2 102 MPIC Memory Base 2 102 PCI 2 97 PCI Interrupt Acknowledge 2 87 PCI Slave Address 2 103 PCI Slave Attribute 2 104 PHB Detected Errors Destination 2 126 PHB Detected Errors Vector Priority 2 125 PPC Error Address 2 84 PPC Error Attribute 2 85 PPC Error Enable 2 79 PPC Error Status 2 82 PPC Slave Address 2 90 PPC Slave Offset Attribute 2 89 2 91 Processor Init MPIC 2 116 SMC Address Parity Error Address 3 71 MC 32 Bit Counter 3 72 MC Address Parity Error Log 3 70 MC Base Address 3 67 MC Data Parity Error Address 3 61 MC Data Parity Error Log 3 60 MC Data Parity Error Lower Data 3 62 MC Data Parity Error Upper Data 3 61 MC ECC Control 3 45 MC Error Address 3 51 MC Error Logger 3 49 SMC External Register set 3 72 SMC General Control Register 3 39 SMC ROM A Base Size 3 53 SMC ROM B Base Size 3 56 SMC ROM Speed Attributes 3 58 SMC Scrub Address 3 52 SMC Scrub Refresh 3 51 SMC SDRAM Base Address 3 43 SMC SDRAM Enable and Size 3 41 3 66
122. AM refresh does not get behind It is okay for the software then to take some time to CLK FREQUENCY to the correct value Refresh will get behind only when the actual CLK pin s frequency is lower than the value programmed into CLK FREQUENCY por is set by the occurrence of power up reset It is cleared by writing a one to it Writing a 0 to it has no effect 3 44 Computer Group Literature Center Web Site Programming Model ECC Control Register Address FEF80028 Bit JH J 1 1 1 1 Pe 1 fe Je ftp r2 fo r2 JN Jw Jo SI J o B fin 2 00 o O JF o 3 00 o Fr Name ooooommbPeesEWEIEI EE E qu Em BS E N Operation amp READ ZERO da add A Reset S S ISIS d Cer eie er p refdis When set refdis causes the refresher and all of its associated counters and state machines to be cleared and maintained that way until refdis is removed cleared If a refresh cycle is in process when refdis is updated by a write to this register the update does not take effect until the refresh cycle has completed This prevents the generation of illegal cycles to the SDRAM when refdis is updated
123. B 7B 9B BB DB 1 rd5 3C 5C 7 9C BC DC 10 3D rd28 5D 7D 9D BD 8DD FD 1E 3E 5E 7E 9E rd36 BE DE FE 1F 3F 5F 7F 9F BF DF FF http www motorola com computer literature 3 87 System Memory Controller SMC 3 88 Computer Group Literature Center Web Site Hawk Programming Details Introduction This chapter contains details of several programming functions associated with the Hawk ASIC chip PCI Arbitration PCI arbitration must be provided by the host board Hawk MPIC External Interrupts The MVMES5100 Hawk MPIC is fully compliant with the industry standard Multi Processor Interrupt Controller Specification Following a power up reset the MPIC is configured to operate in the parallel interrupt delivery mode the MVMES5100 series Table 4 1 MPIC Interrupt Assignments MPIC Edge Polarity Interrupt Source Notes IRQ Level IRQO Level High PIB 8259 from IPMC761 in PMC Slot 1 3 IRQI Level Low TL16C550 UART Serial Port 1 2 1 4 IRQ2 Level Low PCI Ethernet Device Port 1 Front panel IRQ3 Level Low Hawk WDTIO L WDT20 L 5 IRQ4 Level Low Thermal Alarm output TOUT of Dallas 6 Semiconductor DS1621 5 Level Low PCI VME INT 0 Universe LINTO 2 IRQ6 Level Low PCI VME IN
124. Controller MPIC CSR s Readability Unless explicitly specified all registers are readable and return the last value written The exceptions are the IPI dispatch registers and the EOI registers which return zeros on reads the interrupt source ACT bit which returns current interrupt source status the interrupt acknowledge register which returns the vector of the highest priority interrupt which is currently pending and reserved bits which returns zeros The interrupt acknowledge register is also the only register which exhibits any read side effects Interrupt Source Priority Each interrupt source is assigned a priority value in the range from 0 to 15 where 15 is the highest In order for delivery of an interrupt to take place the priority of the source must be greater than that of the destination processor Therefore setting a source priority to zero inhibits that interrupt http www motorola com computer literature 2 53 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Processor s Current Task Priority Each processor has a task priority register which is set by system software to indicate the relative importance of the task running on that processor The processor will not receive interrupts with a priority level equal to or lower than its current task priority Therefore setting the current task priority to 15 prohibits the delivery of all interrupts to the associated processor Nesting of Interrup
125. DTE Serial Interface Module SIMV35DCE or DTE V 35 DCE or DTE Module SIMX2IDCE or DTE X21 DCE or DTE Serial Interface Module xxiii Related Products Part Number Description Primary 32 bit PCI expansion mates directly to the PMCSPAN 002 MVMES100 providing slots for either two single wide or one double wide PMC cards optional PMCSPAN 010 PMCSPAN 010 Secondary 32 bit PCI expansion plugs directly into PMCSPAN 002 providing two additional PMC slots RAMS500 004 Stackable top 64MB ECC SDRAM mezzanine RAMS500 006 Stackable top 256MB ECC SDRAM mezzanine RAMS500 016 Stackable bottom 256MB ECC SDRAM mezzanine Summary of Changes The following changes were made for the 2nd revision of this manual Date Doc Rev Changes 09 2001 V5100A PG2 Memory Maps and additional register information was added to Chapter 1 Corrections were made to Table 4 1 in Chapter 4 Additions were made to Appendix A Releated Documentation Appendix B VPD Information was added This section titled About this Manual was also added Overview of Contents The following paragraphs briefly describe the contents of each chapter Chapter 1 Product Data and Memory Maps provides a description of the MVMES100 tables of specific memory maps and other control registers XXIV Chapter 2 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller provides a description
126. Figure 2 4 PCI to Address Decoding There are no limits imposed by the PHB on how large of an address space a map decoder can represent There is a lower limit of a minimum of 64KB due to the resolution of the address compare logic For each map there is an independent set of attributes These attributes are used to enable read accesses enable write accesses enable write posting and define the PPC bus transfer characteristics 2 20 Computer Group Literature Center Web Site Functional Description Each map decoder also includes a programmable 16 bit address offset The offset is added to the 16 most significant bits of the PCI address and the result is used as the PPC address This offset allows devices to reside at any PPC address independent of the PCI address map An example of this is shown in Figure 2 5 PCI Bus Address 8 0 8 01 2 3 4 T 4 A PSOFFx Register 9000 y Bus Address 1 0 8 0 1 2 9 4 1 Figure 2 5 PCI to Address Translation PHB address decoders are prioritized so that programming multiple decoders to respond to the same address is not a problem When the PCI address falls into the range of more than one decoder only the highest priority one will respond The decoders are prioritized as shown below Decoder Priority PCI Slave0 highest PCI Slave 1 PCI Slave 2 Y PCI Slave 3 lowest http
127. I Interrupt Acknowledge Register The PCI Interrupt Acknowledge Register PIACK is a read only register that is used to initiate a single PCI Interrupt Acknowledge cycle Any single byte or combination of bytes may be read from and the actual byte enable pattern used during the read will be passed on to the PCI bus Upon completion of the PCI interrupt acknowledge cycle the PHB will present the resulting vector information obtained from the PCI bus as read data Address FEFF0030 Bit 1 1 1 111 pty 11 11 dy 2 2 2 272 2 2 2 2 2 313 0 1 2 3 4 5 6 77 8 9 OF 1 2 3 4 SP 6 7 8 9 O 1 2 37 4 5 6 7 8 9 OF 1 Name PIACK Operation R Reset 00000000 http www motorola com computer literature 2 87 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PPC Slave Address 0 1 and 2 Registers The PPC Slave Address Registers XSADD0 XSADDI and XSADD2 contains address information associated with the mapping of PPC memory space to PCI memory I O space The fields within the XSADDx registers are defined as follows Address XSADDO FEFF0040 XSADDI FEFF0048 XSADD2 SFEFF0050 Bit Name o emeermeeszLissxmmEemy mayen Ci eol XSADDx START END Operation R W R W Reset 0000 0000 START Start Address This field determines the start address of a particular memory area on the PPC bus which will be used to access PC
128. I bus resources The value of this field will be compared with the upper 16 bits of the incoming PPC address END End Address This field determines the end address of a particular memory area on the PPC bus which will be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming PPC address 2 88 Computer Group Literature Center Web Site Registers PPC Slave Offset Attribute 0 1 and 2 Registers Address XSOFFO XSATTO SFEFF0044 XSOFFI XSATTI SFEFF004C XSOFF2 XSATT2 FEFFO054 BO XSOFFx XSATTx z A 2 a g 2 z x zT Operation R W R zx 22424144155 Reset 0000 00 olololololololo The PPC Slave Offset Registers XSOFF0 XSOFF1 and XSOFF2 contains offset information associated with the mapping of PPC memory space to PCI memory I O space The field within the XSOFFx registers is defined as follows XSOFFx PPC Slave Offset This register contains a 16 bit offset that is added to the upper 16 bits of the PPC address to determine the PCI address used for transfers from the PPC bus to PCI This offset allows PCI resources to reside at addresses that would not normally be visible from the PPC bus The PPC Slave Attributes Registers XSATT1 and XSATT2 contain attribute information associated with the mapping of PPC memory space to PCI mem
129. IOR VECTOR gt Q 2 6 t Operation 5 R E xu R W R R W Reset lo 000 50 500 00 2 122 Computer Group Literature Center Web Site Registers MASK ACT POL SENSE PRIOR VECTOR MASK Setting this bit disables any further interrupts from this source If the mask bit is cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated ACTIVITY The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In Service Register is set POLARITY This bit sets the polarity for external interrupts Setting this bit to zero enables active low or negative edge Setting this bit to one enables active high or positive edge Only External Interrupt Source 0 uses this bit in this register For external interrupts 1 through 15 this bit is hard wired to 0 SENSE This bit sets the sense for external interrupts Setting this bit to zero enables edge sensitive interrupts Setting this bit to one enables level sensitive interrupts For external interrupt sources 1 through 15 setting this bit to zero enables positive edge triggered interrupts Setting this bit to one enables active low level triggered interrupts PRIORITY Interrupt priority 0 is the lowest and 15 is the highest Note that a priority level of 0 will
130. Integrated Circuit 1 13 Internal Clock Frequency 1 1 Interprocessor Interrupt Dispatch Registers 2 126 Interrupt Acknowledge Registers 2 127 Interrupt Controller 1 2 features 2 2 Interrupt Enable control bits 3 47 interrupts 8259 4 3 Hawk MPIC 4 1 introduction 1 1 Hawk PHB MPIC 2 1 PHB MPIC 2 1 programming details for Hawk 4 1 SMC 3 1 IPI Vector Priority Registers 2 117 L L2 Cache 1 1 1 9 IN 4 Computer Group Literature Center Web Site L2 Cache SRAM Size 1 10 L2 cache support SMC 3 11 L2CLK bits 1 10 L2CLM 3 11 latency PCI Slave 2 25 Little Endian mode of PPC devices 2 39 little endian mode 4 8 Lock Resolution programmable 2 46 Main Memory 1 2 map decoders PPC to PCI 2 7 mapping PPC address 2 6 master initiated termination 2 28 mcken 3 48 memory ECC 1 11 Memory Base Register 2 102 Memory Controller 1 2 memory map CHRP 1 5 PCI local bus 1 4 1 8 processor default 1 4 Memory maps 1 4 memory maps 1 4 VMEbus 1 8 Memory Subsystem Data 1 13 mien 3 48 Miscellaneous MVMES100 features 1 2 MODFAIL Bit Register 1 25 MODRST Bit Register 1 26 arbiter 2 15 MPC bus address space 2 19 MPC slave 2 7 MPC slave response command types 2 8 MPC to PCI address decoding 2 6 MPC750 processor memory domain 4 9 MPIC 2 1 interface with PHB 2 5 MPIC Registers 2 110 MPIC registers 2 110 MPIC s involvement 4 9 Multi Processor Interrupt Controller 2 1 MVME Key Features 1 1 MVMES5100 endian is
131. LT DATIN 1 7 READ RECEIVER DATA REG LOAD 05 STOP CONDITION CONTROL REG LOAD DUMMY DATA TO TRANSMITTER DATA REG READ C STATUS REG Stop condition should be generated to abort the transfer after a software wait loop 1ms has been expired Figure 3 7 Programming Sequence for 2 Current Address Read 3 28 Computer Group Literature Center Web Site Functional Description Page Write The PC page write is initiated the same as the PC byte write but instead of sending a stop sequence after the first data word the master controller will transmit more data words before a stop sequence is generated The first step in the programming sequence should be to test the i2 cmplt bit for the operation complete status The next step is to initiate start sequence by first setting the 12 start and 12 enbl bits in the PC Control Register and then writing the device address bits 7 1 and write bit bit 020 to the Transmitter Data Register The i2 cmplt bit will be automatically clear with the write cycle to the Transmitter Data Register The PC Status Register must now be polled to test the i2_cmplt and i2_ackin bits The i2_cmplt bit becomes set when the device address and write bit have been transmitted and the i2_ackin bit provides status as to whether or not a slave device acknowledged the device address With the successful transmission of the
132. MVME5100 Single Board Computer Programmer s Reference Guide V5100A PG2 September 2001 Edition Copyright 2001 Motorola Inc rights reserved Printed in the United States of America Motorola and the Motorola logo are registered trademarks and AltiVec is a trademark of Motorola Inc PowerPC and the PowerPC logo are registered trademarks and PowerPC 750 is a trademark of International Business Machines Corporation and are used by Motorola Inc under license from International Business Machines Corporation other products mentioned in this document are trademarks or registered trademarks of their respective holders Safety Summary The following general safety precautions must be observed during all phases of operation service and repair of this equipment Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment The safety precautions listed below represent warnings of certain dangers of which Motorola is aware You as the user of the product should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment Ground the Instrument To minimize shock hazard the equipment chassis and enclosure must be connected to an electrical ground If the equipment is supplied with a three conductor AC power cable the power cable must be plugged into an ap
133. Master begins a burst read to SDRAM the SMC starts the access and when the access time is reached the SDRAM provides all four beats of data one on each clock Hence the SMC can provide the four beats of data with zero idle clocks between each beat Single beat Reads Writes Because of start up addressing and completion overhead single beat accesses to and from the PPC60x bus do not achieve data rates as high as do four beat accesses Single beat writes are the slowest because they require that the SMC perform a read cycle then a write cycle to the SDRAM in order to complete Fortunately in most PPC60x systems single beat accesses can be held to a minimum especially with data cache and copyback modes in place Address Pipelining The SMC takes advantage of the fact that PPC60x processors can do address pipelining Many times while a data cycle is finishing the PPC60x processor begins a new address cycle The SMC can begin the next SDRAM access earlier when this happens thus increasing throughput 3 6 Computer Group Literature Center Web Site Functional Description Page Holding Further savings comes when the new address is close enough to a previous one that it falls within an open page in the SDRAM array When this happens the SMC can transfer the data for the next cycle without having to wait to activate a new page in SDRAM In the SMC this feature is referred to as page holding SDRAM Speeds The SDRAM that the Ha
134. Memory Maps Board Last Reset Register This register is used to retain the source of the most recent reset REG Board Last Reset Register Offset 80F8h BIT RDO RDI RD2 RD3 RD4 RD5 RD6 RD7 FIELD NE e eee 24 24 24 E 2 m 5 R R R R R R R RESET X X X X X X x x REQUIRED X X OR OPTIONAL PWRON Power On Reset If set a power on reset has occurred or an undervoltage reset has occurred on 3 3V or 5V FPBTN Front Panel Push Button Reset If set a front panel push button reset has occurred WDT2 Watchdog Timer Level 2 Reset If set a level 2 Watchdog timer reset has occurred CPCIRST CompactPCI Reset If set a CompactPCI RST reset has occurred Not applicable for the MVMES100 CMDRST CompactPCI Command Reset If set a software reset command has been issued to the 21554 bridge from the CompactPCI bus Not applicable for MVMES100 SWHRST Software Hard Reset If set a software initiated hard reset has occurred via the PBC Port 92 Fast Reset bit of the SA Test Mode register Computer Group Literature Center Web Site PCI Local Bus Extended Features Register 2 This register is used to read if a PMC board is present or if a PCI expansion slot is present Table 1 17 Extended Features Register 2 REG Extended Features Register 2 Offset 80F0h RDO RD1 RD2 RD3 RD4 RD
135. N Serial device 1 connector present 25 PCO SERIAL2 CONN Serial device 2 connector present 26 PCO SERIAL3 CONN Serial device 3 connector present 27 SERIALA4 CONN Serial device 4 connector present 28 PCO FLOPPY CONNI Floppy device connector 1 present 29 PCO FLOPPY CONN2 Floppy device connector 2 present 30 PCO PARALLEL CONN Parallel device 1 connector present 31 PCO PARALLEL2 CONN Parallel device 2 connector present 32 PCO PMCI IO CONN PMC slot 1 I O connector present 33 PCO PMC2 IO CONN PMC slot 2 I O connector present 34 PCO USBO CONN USB channel 0 connector present 35 PCO_USB1_CONN USB channel 1 connector present 36 PCO_KEYBOARD_CONN Keyboard connector present 37 PCO_MOUSE_CONN Mouse connector present 38 PCO_VGA1_CONN VGA device 1 connector present 39 PCO_SPEAKER_CONN Speaker connector present 40 PCO_VME_CONN VME backplane connector present 41 PCO_CPCI_CONN Compact PCI backplane connector present 42 PCO_ABORT_SWITCH Abort switch present 43 PCO_BDFAIL_LIGHT Board fail light present 44 PCO_SWREAD_HEADER Software readable header present 45 PCO_MEMMEZ_CONN Memory mezzanine connector present 46 PCO_PCIO_EXP_CONN PCI bus 0 expansion connector present 47 Reserved for future configuration options 48 PCO_DIMM1_CONN DIMM slot 1 connector present 49 PCO_DIMM2_CONN DIMM slot 2 connector present 50 PCO_DIMM3_CONN DIMM slot 3 connector present 51 PCO_DIMM4_CONN DIMM slot 4 connector present 52 127 Reserved for future configuration options
136. OB Field Size Bytes 1 Field Mnemonic L2C_ERROR_DETECT Field Description Error Detection Type 00 None 01 Parity 02 ECC 0C L2C SIZE L2 Cache Size Should agree with the physical organization above 00 256K 01 512K 02 IM 03 2M 04 AM 0 L2C TYPE BACKSIDE L2 Cache Type Backside Configurations 00 Late Write Sync 115 Hold Differential Clock Parity 01 Pipelined Sync Burst 0 5nS Hold No Differentia Clock Parity 02 Late Write Sync 1nS Hold Differential Clock No Parity 03 Pipelined Sync Burst 0 5nS Hold No Differential Clock No Parity L2C RATIO BACKSIDE L2 Cache Core to Cache Ration Backside Configurations 00 Disabled 01 1 1 1 02 3 2 1 5 03 2 1 2 04 5 2 2 5 05 3 1 3 A product may contain multiple L2 cache configuration packets This product the PPMCBASE does not contain a L2 Cache device http www motorola com computer literature MVMES100 VPD Reference Information VPD Definitions VPD Revision Data The VPD revision data packet consists of byte fields that indicate the type version and revision of the vital product data The following table s further describe the VPD revision data packet Table B 5 VPD Revision Data Byte Field Field Mnemonic Field Description Offset Size Bytes 00 1 _ Vital Product Data Type 00 Processor board VPD 01 Baseboard
137. ORD ADDR TO TRANSMITTER DATA REG READ PC STATUS REG Y LOAD DATA TO IC TRANSMITTER DATA REG READ PC STATUS REG Y LOAD 05 STOP CONDITION TO CONTROL REG LOAD DUMMY DATA TO TRANSMITTER DATA REG READ PC STATUS REG Y END Stop condition should be generated to abort the transfer after a software wait loop 1ms has been expired Figure 3 5 Programming Sequence for Byte Write 3 24 Computer Group Literature Center Web Site Functional Description I C Random Read The I C random read begins in the same manner as the PC byte write The first step in the programming sequence should be to test the i2 cmplt bit for the operation complete status The next step is to initiate a start sequence by first setting the i start and 12 enbl bits in the C Control Register and then writing the device address bits 7 1 and write bit bit 0 0 to the C Transmitter Data Register The i cmplt bit will be automatically clear with the write cycle to the Transmitter Data Register The Status Register must now be polled to test the i cmplt and ij ackin bits The i cmplt bit becomes set when the device address and write bit have been transmitted and the i ackin bit provides status as to whether or not a slave device acknowledged the device address With the successful transmission of the device address the word address
138. PC bus s perspective This association is true regardless of whether the transaction originates on the PCI bus or the PPC bus This is shown in Figure 2 7 2 38 Computer Group Literature Center Web Site Functional Description a a a Ce os oe Tor ce D7 D6 D5 D4 D3 D2 D1 DO sci PCI 8 9 89 83 5 8 8 o g 8 amp 8 2 5 e 1O e e a a 8 a Q lt lt lt lt 8 8 9 amp n eo To dp ou de a Om 0 m a a a a a a a a DO D1 D2 D3 D4 D5 D6 D7 32 bit PCI 1916 9610 Figure 2 7 Big to Little Endian Data Swap When PPC Devices are Little Endian When all PPC devices are operating in little endian mode the originating address is modified to remove the exclusive ORing applied by PPC60x processors Note that no data swapping is performed http www motorola com computer literature 2 39 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Address modification happens to the originating address regardless of whether the transaction originates from the PCI bus or the PPC bus The three low order address bits are exclusive ORed with a three bit value that depends on the length of the operand as shown in Table 2 13 Table 2 13 Address Modification for Little Endian Transfers Data Address Length Modification bytes 1 XOR with 111 2 XOR with 110 4 XOR with 1
139. PCI bus 2 106 Computer Group Literature Center Web Site Registers Conceptual perspective from the PCI bus Offset CFB CFA CF9 Bit 3 3 2 2 2 2 2 272 2 2 2 1 I D I 1 1 1 1 1 1 0 9 8 7 6 5 493 2 I Name CONFIG_ADDRESS e BUS DEV FUN REG Operation E R R W R W R W R W bilis Reset 00 00 00 0 00 olo Perspective from the PPC bus in Big Endian mode Offset CF8 CF9 CFA CFB Bit DH 111 111 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 12345678901 Name CONFIG ADDRESS REG DEV FUN BUS z Operation R W R W R W R W R A gt Reset 00 ojo 00 0 00 _ 00 Perspective from the bus in Little Endian mode Offset CFC CFD CFE CFF Bit DL 1 1 1 1 1 dpa 11 1 112 21 2 272 21 2 2 2 2 3 3 1 2 3 4 5 6 7 8 9 0 1 Name CONFIG_ADDRESS gt BUS DEV FUN REG Operation x R R W R W R W R W 2 AW z Reset 00 00 00 0 00 oo http www motorola com computer literature 2 107 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller The register fields are defined as follows REG Register Number Configuration Cycles Identifies a target double word within a target s configuration space This field is copied to the PCI AD bus during the address phase of a Configuration cycle Special Cycles This field must be written with all zeros
140. PCI request mode that helps the processor complete read cycles from PCI space If a bridge lock resolution cycle happens when the PPC Slave is hosting a compelled cycle the PCI Master will speculatively assert a request on the PCI bus Sometime later when the processor comes back and retries the compelled cycle the results of the PCI Master holding will increase the chance of the processor successfully completing its cycle http www motorola com computer literature 2 47 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PCI speculative requesting will only be effective if the PCI arbiter will at least some times consider the PHB to be a higher priority master than the master performing the PPC60x bound write cycles The PCI Master obeys the PCI specification for benign requests and will unconditionally remove a speculative request after 16 clocks The PHB considers the speculative PCI request mode to be the default mode of operation If this is not desired then the speculative PCI request mode can be disable by changing the SPRQ bit in the HCSR Transaction Ordering All transactions will be completed on the destination bus in the same order that they are completed on the originating bus A read or a compelled write transaction will force all previously issued write posted transactions to be flushed from the FIFO write posted transfers will be completed before a read or compelled write begins to ensure that all tr
141. PL rom b spd0 30 0 PL R W rom b spdT 51 rom a spd0 1 a spd0 1 determine the access timing used for ROM Flash Block A The encoding of these bits are shown in Table 3 15 The device access times shown in the table are conservative and allow time for buffers on address control and data signals For more accurate information see the section entitled Timing Specifications for ROM Flash Signals further on in this manual along with the section titled ROM Flash Read Timing Diagram 3 58 Computer Group Literature Center Web Site Programming Model Writes that change these bits must be enveloped by a period of time in which no accesses to ROM Flash Block A occur simple way to provide the envelope is to perform at least two accesses to this or another of the SMC s registers before and after the write Table 3 15 ROM Speed Bit Encodings rom a b spd0 1 Approximate ROM Block A B Device Access Time 2600 12 Clock Periods 120ns 100 MHz 180ns 66 67 MHz 2001 8 Clock Periods 80ns 100 MHz 120ns 66 67 MHz 10 5 Clock Periods 50ns 100 MHz 75ns 66 67 MHz 9611 3 Clock Periods 30ns 9400 MHz 45ns 66 67 MHz rom b spd0 1 b lt 40 1 determine the access timing used for ROMp Flash Block B Refer to the table above Writes that change these bits must be enveloped by a period of time in which no accesses to ROM Flash B B
142. Priority and Destination registers for interrupt source 0 are used to control the delivery mode for all 8259 generated interrupt sources Table 2 20 Cascade Mode Encoding TIE M Mode 0 Pass Through 1 Mixed Tie Mode Writing a one to this register bit will cause a tie in external interrupt processing to swap back and forth between processor 0 and 1 The first tie in external interrupt processing always goes to Processor 0 after a reset When this register bit is set to 0 a tie in external interrupt processing will always go to processor 0 Mode used on Version 02 of MPIC Table 2 21 Tie Mode Encoding T Mode Processor 0 always selected Swap between Processor s http www motorola com computer literature 2 115 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Vendor Identification Register Offset 01080 Bit 3 3 2 2 2 2 2 292 2 2 2 1 1 1 I 1 1 1 1 1 1 1 O 9 8 7 6 5 49 3 2 1 Of 9 8 7 GF 5 4 32 10 9 8f 7 6 5 4 3 2 1 0 Name VENDOR IDENTIFICATION STP Operation R R R R Reset 00 00 00 00 There are two fields in the Vendor Identification Register which are not defined for the MPIC implementation but are defined in the MPIC specification They are the vendor identification and device ID fields STP STEPPING The stepping or silicon revision number of Hawk s MPIC Processor Init Register
143. RESET Clearing this bit causes the RST REQ signal to be asserted This bit will automatically deassert following reset The host board is expected to assert a PCI reset when this signal is cleared 1 26 Computer Group Literature Center Web Site PCI Local Bus TBEN Bit Register The 5100 implementation of this register is fully compliant with the PowerPlus II Programming Specification with exceptions to Bit RD6 as indicated in the following table The TBEN Bit register provides the means to control the Processor Timebase Enable input Table 1 14 TBEN Bit Register REG TBEN Bit Register Offset 80COh BIT RDO RD2 RD3 RD4 RD5 RD6 RD7 FIELD amp ZB 2 Eg Z OPER R R R R R R R W R W RESET X X X X X X 1 1 REQUIRED X X X X X X R OR OPTIONAL TBENO Processor O Time Base Enable When this bit is cleared the TBEN pin of Processor 0 will be driven low When this bit is set the TBEN pin is driven high TBENI This bit is not used http www motorola com computer literature 1 27 Product Data and Memory Maps NVRAM RTC amp Watchdog Timer The MVME5100 s NVRAM RTC and Watchdog Timer functions supplied by an M48T37V device and is fully compliant with the PowerPluslIl internal programming configuration The M48T37V provides 32K of non volatile SRAM a time of day clock and a watchdog timer Accesses to the M48T37V is accomplished v
144. RIC amp Watchdog TINDET uice tiro ratto eR RE UE EE IER 1 28 Software Readable Header Switch Register S1 sss 1 29 Geographical Address Register VME board esses 1 30 Extended Featutes Register e SA HER VER EDU ERE 1 31 Board Last Reset E 1 32 Extended RECIEN R 1 33 CHAPTER2 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Diodi BHM a ord E d Re Fe ASA LU RUD M UIN QE Lp eR IG V ln 2 1 SPRY MWY depre wagon DAP HERE DINER dU tapas 2 1 PS AUTOS e 2 1 Block M Me 2 3 Puncta Deser imini to Up past HIA Ev qe iar an ERES M ER AERE UR 2 4 actes CER Ce W acie HERE twas ants UE Pe ERATEEHDr ue E a POORNA 2 4 PPC Eus Mia LEER Le reo RECIEN Eq D re 2 5 Sudress Mapping Lise cese eee uud tant He A ERU 2 6 T M 2 7 PPC rr v 2 9 PPE ITS cas PH 2 10 5b 2 15 PPG a arbe bU A AA 2 17 PFC Bus l UE auos nU apnea desea EP IU IER PIER RHET
145. RT CONDITION CONTROL REG LOAD DEVICE ADDR WR TO IC TRANSMITTER DATA REG READ STATUS REG Y ACK and DATA from Slave Device LOAD DUMMY DATA TO TRANSMITTER DATA REG READ STATUS REG 4 MPLT DATIN 12 READ RECEIVER DATA REG LOAD WORD ADDR 1 TO TRANSMITTER DATA REG READ STATUS REG Y LOAD 0B REPEATED START CONDITION TO C CONTROL REG LOAD DEVICE ADDR RD BIT TO TRANSMITTER DATA REG READ FC STATUS REG LOAD 01 TO CONTROL REG kj LOAD 05 STOP CONDITION TO 2 CONTROL REG LOAD DUMMY DATA TO IC TRANSMITTER DATA REG READ C STATUS REG lt lt Stop condition should be generated to abort the transfer after a software wait loop 1ms has been expired Figure 3 9 Programming Sequence for 2 Sequential Read http www motorola com computer literature 3 33 System Memory Controller SMC Refresh Scrub The SMC performs refresh by doing a burst of 4 CAS Before RAS CBR refresh cycles to each block of SDRAM once every 60 microseconds It performs scrubs by replacing every 128th refresh burst with a read cycle to 8 bytes in each block of SDRAM If during the read cycle the SMC detects a single bit error it performs a write cycle ba
146. SDRAM block that has the slowest tRC 8 tRC_CLK is tRC expressed in CLK periods 9 Remember that CLK is the Hawk s 60x clock input pin 5 Determine the size for each block that is present Do not actually program the Hawk s size bits at this point You use this information to program them later Each block s size can be determined using the following algorithm a Calculate the number of rows in each device using SPD byte 3 If the number of rows is ROWS and the value in SPD byte 3 is R then ROWS 2 Calculate the number of columns in each device using SPD byte 4 If the number of columns is COLUMNS and the value in SPD byte 4 is C then COLUMNS 2 Calculate the total number of addresses within each device If the total number of addresses in a device is A then A ROWS X COLUMNS Calculate the total number of locations in the block using the results of step 3 and SPD byte 17 If the total number of locations in the block is L and the value in byte 17 is 4 then L Ax4 or L 2 x2 x4 Note that the Hawk only works if byte 17 is 4 Obtain the primary device width from SPD byte 13 Determine the size bits based on the results of steps d and e using the table on the next page Computer Group Literature Center Web Site Software Considerations Table 3 19 Programming SDRAM 517 Bits Total Number of Primary Block Size 2 Value to be Locations within Device Width prog
147. T 1 Universe 2 IRQ7 Level Low PCI VME INT 2 Universe LINT2 2 IRQ8 Level Low PCI VME INT 3 Universe LINT3 2 4 1 Hawk Programming Details Table 4 1 MPIC Interrupt Assignments Continued MPIC IRQ IRQ9 Edge Level Level Polarity Interrupt Source Notes Low INTA PMC2 INTB PCIX INTA IRQ10 Level Low INTB PMC2 INTC PCIX INTB IRQ11 Level Low PCI PMC1 INTC PMC2 INTD PCIX INTCH IRQI2 Level Low PCI PMC1 INTD PMC2 INTA PCIX INTD IRQ13 Level Low PCI Ethernet Device Port 2 Front panel or P2 18014 Level Low ABORT L 15 Level Low RTC Alarm 1 Notes 1 2 Interrupting device is addressed from Hawk External Register Bus The mapping of interrupt sources from the VMEbus and Universe internal interrupt sources are programmable via the Local Interrupt Map 0 Register and the Local Interrupt Map 1 Register in the Universe ASIC This interrupt is provided for software compatibility with the MVME2700 This is the logical OR of the two UART s This is the wired OR of the two watch dog interrupts The DS1621 Digital Thermometer and Thermostat provides 9 bit temperature readings that indicate the temperature of the device The thermal alarm output TOUT is active when the temperature of the device exceeds a user defined temperature TH Com
148. TION This field determines the resolution of the timer The RES field may only be modified on the second step of a successful two step arming process The following table shows the different options associated with this bit RES 0000 Timer Resolution Approximate Max Time us 64 msec 0001 2 us 128 msec 0010 4 us 256 msec 0011 8 us 512 msec http www motorola com computer literature 2 93 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller RES Timer Resolution Approximate Max Time 0100 16us 1 sec 0101 32 us 2 0110 64 us 4 0111 128 us 8 sec 1000 256 us 16 sec 1001 512 us 32 sec 1010 1024 us min 1011 2048 us 2 min 1100 4096 us 4 min 1101 8192 us 8 min 1110 16 384 us 16 min 1111 32 768 us 32 min RELOAD Reload This field is written with a value that will be used to reload the timer The RELOAD field may only be modified on the second step of a successful two step arming process Note An R206 resistor must be installed if a board reset is the result of a timeout of Watchdog Timer 2 See the attached sample for an example of PPCBug setting WDT2 PC6 Bug md feff0068 EFF0068 000 0000FFFF 03 4000 0000000 S Livret vet EFF0078 00000000 FFFFFFFE 9 el ele PC6 Bug md feff006c EFF006C 0000FFFF 03 4000 00000000 000
149. Tadd TASH Id Operation A A Ma 0 Oad AVI M A 0 0 M a A A A Reset ojojo 0 0 FSRx FBWx FSWx Flatten Burst Read This field is used by the PPC Arbiter to control how bus pipelining will be affected after all burst read cycles The encoding of this field is shown in the table below Flatten Single Read This field is used by the PPC Arbiter to control how bus pipelining will be affected after all single beat read cycles The encoding of this field is shown in the table below Flatten Burst Write This field is used by the PPC Arbiter to control how bus pipelining will be affected after all burst write cycles The encoding of this field is shown in the table below Flatten Single Write This fieldis used by the PPC Arbiter to control how bus pipelining will be affected after all single beat write cycles The encoding of this field is shown in the table below FBR FSR FBW FSW 00 Effects on Bus Pipelining None 01 None 10 Flatten always 11 Flatten if switching masters http www motorola com computer literature Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PRI PRKx Priority If set the PPC Arbiter will impose a rotating between CPUO grants If cleared
150. Y is cleared to 0 at power up reset scrubbing is disabled until software programs a non zero value into it Scrub Address Register Address FEF80048 Bit N Name SCRUB ADDRESS 24 READ WRITE Reset gt lt gt lt d lt OP co Operation E X 29 SCRUB ADDRESS These bits form the address counter used by the scrubber for all blocks of SDRAM The scrub address counter increments by one each time a scrub to one location completes to all of the blocks of SDRAM When it reaches all 1s it rolls back over to all Os and continues counting The SCRUB ADDRESS counter is readable and writable for test purposes Note that for each block the most significant bits of SCRUB ADDRESS COUNTER are meaningful only when their SDRAM devices are large enough to require them Computer Group Literature Center Web Site Programming Model ROM A Base Size Register Address FEF80050 Bit J o fin 23 o o FB LA o Fr Name ROM A BASE 6 le Ie B ls Je le MIS l le Ie EE Ie S e ti 2 1a Operation READ WRITE 222 READ ZERO oo Reset FF0 PL S rg X saan
151. ace Configuration Registers The PHB Configuration registers are mapped within PCI Configuration space according to how the system connects Hawk s DEVSEL_ The PHB provides a configuration space that is fully compliant with the PCI Local Bus Specification 2 1 definition for configuration space There are two base registers within the standard 64 byte header that are used to control the mapping of MPIC One register is dedicated to mapping MPIC into PCI I O space and the other register is dedicated to mapping MPIC into PCI Memory space The mapping of PPC address space is handled by device specific registers located above the 64 byte header These control registers support a mapping scheme that is functionally similar to the PCI to PPC mapping scheme described in the section titled PPC Address Mapping http www motorola com computer literature 2 19 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PPC Bus Address Space The PHB maps PPC address space into PCI Memory space using four programmable map decoders The most significant 16 bits of the PCI address is compared with the address range of each map decoder and if the address falls within the specified range the access is passed on to the PPC bus An example of this is shown in Figure 2 4 PCI Bus Address 18 0 8 0 1 2 3 4 1615 0 1 1 7 Decodeis gt lt C Y Y PSADDx Register 7 0 8 0 0 0 0
152. acteristics 2 6 Computer Group Literature Center Web Site Functional Description PPC Slave Each map decoder also includes a programmable 16 bit address offset The offset is added to the 16 most significant bits of the PPC address and the result is used as the PCI address This offset allows PCI devices to reside at any PCI address independent of the PPC address map An example of this is shown in Figure 2 3 PPC Bus Address 8 0 8 0 1 2 9 4 1 A V PEE EN XSOFFx Register 9 00 0 al M Y PCI Bus Address 1 0 8 0 1 2 9 4 1 Figure 2 3 PPC to PCI Address Translation Care should be taken to ensure that all programmable decoders decode unique address ranges since overlapping address ranges will lead to undefined operation The PPC slave provides the interface between the PPC bus and the PPC FIFO The PPC slave is responsible for tracking and maintaining coherency in the PPC60x processor bus protocol The actions taken by the PPC Slave to service a transaction are dependent upon whether the transaction is posted or compelled During compelled transactions such as a read or a non posted single beat write the PPC Slave will hold off asserting AACK TA until after the transaction has completed on the PCI bus This has the effect of removing all levels of pipelining during compelled PHB accesses The interdependency between the assertion of http www motorola com co
153. ansfer TSIZx Transfer Size This field contains the transfer size of the PPC transfer in which the error occurred TTx Transfer Type This field contains the transfer type of the PPC transfer in which the error occurred http www motorola com computer literature 2 85 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller If the PSMA or PRTA bit are set the register is defined by the following table Address FEFF002C 1 1 11 0 112 3 4 5 617f8 9 0 112 3 4 56 7 8 9 OF 112 37 4 5 6 7 8 9 0 Name EATTR g zizal ws x SISO OI OKIKIKIKIKIKIKIK 582282558448 WIN R R PESESIESIESIESIESIES ESIESESESESESIESIES Reset 00 00 o o e e e e s e e e e see WP Write Post Completion This bit is set when the PCI master detects an error while completing a write post transfer XIDx PPC Master ID This field contains the ID of the PPC master which originated the transfer in which the error occurred The encoding scheme is identical to that used in the GCSR register COMMx PCI Command This field contains the PCI command of the PCI transfer in which the error occurred BYTEx PCI Byte Enable This field contains the PCI byte enables of the PCI transfer in which the error occurred A set bit designates a selected byte 2 86 Computer Group Literature Center Web Site Registers PC
154. ansfers are completed in the order issued PCI Configuration cycles intended for internal PHB registers will also be delayed if PHB is busy so that control bits which may affect write postings do not change until all write posted transactions have completed For the same reason all PPC60x write posted transfers will also be completed before any access to the PHB PPC registers begins The PCI Local Bus Specification 2 1 states that posted write buffers in both directions must be flushed before completing a read in either direction PHB supports this by providing two optional FIFO flushing options The XFBR PPC60x Flush Before Read bit within the GCSR register controls the flushing of PCI write posted data when performing PPC originated read transactions The PFBR PCI Flush Before Read bit within the GCSR register controls the flushing of PPC write posted data when performing PCI originated read transactions The PFBR and XFBR functions are completely independent of each other however both functions must be enabled to guarantee full compliance with PCI Local Bus Specification 2 1 When the XFBR bit is set the PHB will handle read transactions originating from the PPC bus in the following manner 2 48 Computer Group Literature Center Web Site Functional Description Write posted transactions originating from the processor bus flushed by the nature of the FIFO architecture The PHB will hold the processor with wa
155. aster to get an early enough start at prefetching read data to keep the PCI Slave from starving for read data From the perspective of the PPC bus a selective FIFO threshold will make the PPC Slave release the PPC bus at an earlier time thereby reducing wasted PPC bus bandwidth PHB offers an option to have the PPC Slave remove a stalled transaction immediately upon detecting any PCI Slave activity This option would help in the case where distributing PPC60x bus bandwidth between multiple masters is of the utmost importance The PHB is tuned to provide the most efficient solution for bridge lock resolution under normal operating conditions If further fine tuning is desired the WLRT RLRT Write Lock Resolution Threshold Read Lock Resolution Threshold fields within the HCSR can be adjusted accordingly Note that the FIFO full option exists mainly to remain architecturally backwards compatible with previous bridge designs Speculative PCI Request There is a case where the processor could get starved for PCI read data while the PCI Slave is hosting multiple PPC60x bound write cycles While attempting to perform a read from PCI space the processor would continually get retried as a result of bridge lock resolution Between PCI writes the PPC Master will be taking PPC60x bus bandwidth trying to empty write posted data which will further hamper the ability of the processor to complete its read transaction PHB offers an optional speculative
156. at the same address as the CSR ROM Flash External Register Set or any other slave on the PowerPC bus http www motorola com computer literature 3 43 System Memory Controller SMC CLK Frequency Register Address FEF80020 Bit Je 1 Pe J Fe J J J JN JN t2 r2 92 W B fie 2 oo O J r2 o FB I 100 J Name CLK FREQUENCY pb Operation READ WRITE READ ZERO READ ZERO E Reset 64 P X X PS P lt CLK FREQUENCY These bits should be programmed with the hexadecimal value of the operating CLOCK frequency in MHz i e 42 for 66 MHz When these bits are programmed this way the chip s prescale counter produces a 1 MHz approximate output The output of the chip prescale counter is used by the refresher scrubber and the 32 bit counter After power up this register is initialized to 64 for 100 MHz The formula is Counter Output Frequency Clock Frequency CLK FREQUENCY For example if the Clock Frequency is 100 MHz and CLK FREQUENCY is 64 then the counter output frequency is 100 MHz 100 1 MHz When the CLK pin is operating slower than 100MHZz software should program CLK FREQUENCY to be at least as slow as the CLK pin s frequency as soon as possible after power up reset so that SDR
157. ation in PDF or HTML format visit http www motorola com computer literature Manufacturers Documents Manufacturers Documents For additional information refer to the following table for manufacturers data sheets or user s manuals As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table A 2 Manufacturers Documents Document Title MPC750 RISC Microprocessor Users Manual Motorola Literature Distribution Center Telephone 800 441 2447 or 303 675 2140 WebSite http e www motorola com webapp DesignCenter E mail ldcformotorola hibbertco com Publication Number MPC750UM AD 8 97 MPC7400 RISC Microprocessor Users Manual Motorola Literature Distribution Center Telephone 800 441 2447 or 303 675 2140 WebSite http e www motorola com webapp DesignCenter E mail IdcformotorolaQ hibbertco com MPC7400UM D Universe II User Manual CA91C142 Tundra Semiconductor Corporation 603 March Road Kanata ON Canada K2K 2M5 1 800 267 7231 613 592 0714 Fax 613 592 1320 http www tundra com page cfm tree_id 100008 Universe II 9000000 MD303 01 Dallas Semiconductor DS1621 Digital Thermometer and Thermostat Dallas Semiconductor http www dalsemi com DS1621 Intel LXT970 Fast Ethernet Transceiver Data Sheet Intel Corporation http developer int
158. be transmitted to the slave device Again i and i2 ackin bits must be tested for proper response After the word address is successfully transmitted the next data loaded into 2 Transmitter Data Register will be transferred to the address location selected previously within the slave device After i cmplt and i ackin bits have been tested for proper response a stop sequence must be transmitted to the slave device by first setting the i stop and i7enbl bits in the Control Register and then writing a dummy data data don t care to the PC Transmitter Data Register The Status Register must now be polled to test i cmplt bit for the operation complete status The stop sequence will initiate a programming cycle for the serial EEPROM and also relinquish the ASIC master s possession of the bus Figure 3 5 shows the suggested software flow diagram for programming the PC byte write operation http www motorola com computer literature 3 23 System Memory Controller SMC DEVICE ADDR WORD ADDR DATA M w A A SDA START S R STOP K K A from Slave Device BEGIN 1 Por READ PC STATUS REG LOAD 09 START CONDITION TO CONTROL REG LOAD DEVICE ADDR WR TO TRANSMITTER DATA REG READ PC STATUS REG Y LOAD W
159. becomes the p1_tben output pin and the ercs_output pin becomes the pO tben output pin Also the SMC does not respond to accesses that fall within the external register set address range except for the address FEF88300 When tben en is cleared the I2clm and ercs_ pins retain their normal function and the SMC does respond to external register set accesses http www motorola com computer literature 3 39 System Memory Controller SMC REVID aonly en isa hole pu_stat0 pu_stat3 Software should only set the tben_en bit when there is no external L2 cache connected to the I2clm_ pin and when there is no external register set The REVID bits are hard wired to indicate the revision level of the SMC The value for the first revision is 01 Normally the SMC responds to address only cycles only if they fall within the address range of one of its enabled map decoders When the aonly_en bit is set the SMC also responds to address only cycles that fall outside of the range of its enabled map decoders provided they are not acknowledged by some other slave within 8 clock periods aonly_en is read only and reflects the level that was on the RD4 pin at power up reset time When it is set isa_hole disables any of the SDRAM or ROM Flash blocks from responding to PowerPC accesses in the range from 000A0000 to 000BFFFF This has the effect of creating a hole in the SDRAM memory map for accesses to ISA Whenisa hole is cleared t
160. bit for each possible interrupt priority and one bit for each possible interrupt source Interrupt Router The Interrupt Router monitors the outputs from the ISR s Current Task Priority Registers Destination Registers and the IRR s to determine when to assert a processor s INT pin When considering the following rule sets it is important to remember that there are two types of inputs to the Interrupt Selectors If the interrupt is a distributed class interrupt there is a single bit in the IPR associated with this interrupt and it is delivered to both Interrupt Selectors This IPR bit is qualified by the destination register contents for that interrupt before the Interrupt Selector compares its priority to the priority of all other requesting interrupts for that processor If the interrupt is programmed to be edge sensitive the IPR bit is cleared when the vector for that interrupt is returned when the Interrupt Acknowledge register is examined On the other hand if the interrupt is a direct multicast class interrupt there are two bits in the IPR associated with this interrupt One bit for each processor 2 60 Computer Group Literature Center Web Site Multi Processor Interrupt Controller MPIC Then one of these bits is delivered to each Interrupt Selector Since this interrupt source can be multicast each of these IPR bits must be cleared separately when the vector is returned for that interrupt to a particular processor I
161. bit in the Interrupt Pending Register or In Service Register is set PRIORITY Interrupt priority 0 is the lowest and 15 is the highest Note that a priority level of 0 will not enable interrupts VECTOR This vector is returned when the Interrupt Acknowledge register is examined during a request for the interrupt associated with this vector http www motorola com computer literature 2 117 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Spurious Vector Register Offset 010E0 Bit 3 3 2 2 2 2 2 292 2 2 2 1 1 1 1p 1 1 1 1 1 1 1 OJ 9 8 7 6 5 49 3 2 1 0 9 8 7 OF 5 4 3 2 1 0 9 8f 7 6 5 4 3 2 110 Name VECTOR Operation R R R R W Reset 00 00 00 FF VECTOR This vector is returned when the Interrupt Acknowledge register is read during a spurious vector fetch Timer Frequency Register Offset 010 0 3 3 2 2 2 2 2 12 2 22 2 1 JI JL 1 1 1 110 9 8 7 16 5 14 B 211 0 09 8 17 6 5413 12 1 0 9 807 6 5 4 312 11 0 TIMER FREQUENCY Operation R W Reset 00000000 This register is used to report the frequency in Hz of the clock source for the global timers Following reset this register contains zero The system initialization code must initialize this register to one eighth the MPIC clock frequency For the PHB implementation of the MPIC atypical value would be 7de290 which
162. bit is set after the I7C master controller has successfully completed the requested I C operation and cleared at the beginning of every valid PC operation This bit is also set after power up 2 Transmitter Data Register Address FEF800A8 Bit o a Ol foo a S S 2 NESNA a Name I2 DATAWR Operation READ ZERO READ ZERO READ ZERO READ WRITE Reset X X 0 PL 12 DATAWR The I2 DATAWR contains the transmit byte for PC data transfers If a value is written to I2 DATAWR when the 12 start and 12 enbl bits in C Control Register are set a start sequence is generated immediately followed by the transmission of the contents of the I2 DATAWR to the responding slave device The I2 DATAWR 24 30 is the device address and the I2 DATAWR 31 is the WR RD bit OZWRite 1 ReaD After a start sequence with 12 DATAWR 31 0 subsequent writes to the PC Transmitter Data Register will cause the contents of I2 DATAWR to be transmitted to the responding slave device After a start sequence with I2 DATAWR 31 1 subsequent writes to the Transmitter Data Register data don t care will cause the responding slave device to transmit data to the re Receiver Data Register If a value is written to 12 DATAWR data don t care when the i2 stop and i2 enbl bits in the PC Control Register are set a stop sequence is generated
163. bitration signals and their functions are summarized in Table 2 6 Table 2 6 PPC Arbiter Pin Assignments Pi Internal Arbiter External Arbiter T Reset Direction Function Direction Function XARBO BiDir Tristate Output CPUO Grant Input CPUO Grant XARBI BiDir Tristate Output CPUI Grant Input CPUI Grant XARB2 BiDir Tristate Output EXTL Grant Input EXTL Grant XARB3 BiDir Tristate Input CPUO Request Output HAWK Request 4 Input Input Request Input HAWK Grant XARB5 Input Input EXTL Request Input http www motorola com computer literature 2 15 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller While is asserted XARBO through XARBA is held in tri state If the internal arbiter mode is selected then XARBO through XARB3 is driven to an active state no more than ten clock periods after PHB has detected a rising edge on RST If the external arbiter mode has been selected then XARBA is driven to an active state no more than ten clock periods after PHB has detected a rising edge on RST The PPC Arbiter implements the following prioritization scheme HAWK Highest Priority a EXTL a CPUx CPUy Lowest Priority The PPC Arbiter is controlled by the XARB register within the PHB PPC60x register group The PPC Arbiter supports two prioritization schemes Both schemes affect the prio
164. bits do for blocks E H The table associated with the previous section on blocks A B C D shows how these bits relate to the block configuration SDRAM Base Address Register Blocks E F G H Address FEF800C8 Bit Name RAM E BASE RAM F BASE RAM G BASE RAM H BASE Operation READ WRITE READ WRITE READ WRITE READ WRITE Reset OPL OPL OPL OPL Writes to this register must be enveloped by a period of time in which no accesses to SDRAM occur The requirements of the envelope are that all SDRAM accesses must have completed before the write starts and none should begin until after the write is done A simple way to do this is to perform at least two read accesses to this or another register before and after the write Additionally sometime during the envelope before or after the write all of the SDRAMs open pages must be closed and the Hawk s open page tracker reset The way to do this is to allow enough time for at least one SDRAM refresh to occur by waiting for the 32 Bit Counter to increment at least 100 times The wait period needs to happen during the envelope RAM E F G H BASE These control bits define the base address for their block s SDRAM BASE bits 0 7 8 15 16 23 24 31 correspond to PowerPC60x address bits 0 7 For larger SDRAM sizes the lower significant bits of RAM E F G HBASE are ignored This means that the block s base address will always appear at an even
165. ble 2 11 Mixed Mode Priority Level Setting HEIR PRIORITY Levels Setting Highest Lowest 000 group 1 group 2 group 3 group 4 PARB6 amp 5 PARB4 amp 3 2 amp 1 PARBO amp HAWK 001 group 4 group 1 group 2 group 3 PARBO amp PARB6 amp 5 PARB4 amp 3 PARB2 amp 1 HAWK 010 group 3 group 4 group 1 group 2 PARB2 amp 1 PARBO amp PARB6 amp 5 PARB4 amp 3 HAWK 011 group 2 group 3 group 4 group 1 PARB4 amp 3 PARB2 amp 1 PARBO amp PARB6 amp 5 HAWK Computer Group Literature Center Web Site Functional Description Notes 1 000 is the default setting in mixed mode 2 The HEIR setting only covers a small subset of all possible combinations and the requestors within each group is fixed and cannot be interchanged with other groups It is the responsibility of the system designer to connect the request grant pair in a manner most beneficial to their design goals 3 All other combinations in the HEIR setting not specified in the table are invalid and should not be used Arbitration parking is programmable by writing to the PRK field of the PCI arbiter control register Parking can be programmed for any of the requestors last requestor or none The default setting for parking is Park on HAWK Table 2 12 describes all available settings for the PRK field Table 2 12 Arbitration Setting PRK setting Functi
166. cess time equal to 8 clock periods Table 3 7 PPC60x Bus to ROM Flash Access Timing 50ns 100 MHz CLOCK PERIODS REQUIRED FOR Total 1st Beat 2nd Beat 3rd Beat 4th Beat Clocks ACCESS TYPE 16 64 16 64 16 64 16 64 16 64 Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits 4 Beat Read 42 15 36 9 36 9 36 9 150 42 4 Beat Write N A N A 1 Beat Read 1 byte 15 15 15 15 1 Read 2 to 8 42 15 42 15 bytes 1 Beat Write 21 21 21 21 3 20 Computer Group Literature Center Web Site Functional Description Note The information in Table 3 7 applies to access timing when configured for devices with an access time equal to 5 clock periods Table 3 8 PPC60x Bus to ROM Flash Access Timing 30ns 100 MHz CLOCK PERIODS REQUIRED FOR Total Ist Beat 2ndBeat 3rdBeat 4th Beat Clocks ACCESS TYPE 16 64 16 64 16 64 16 64 16 64 Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits 4 Beat Read 34 13 28 7 28 7 28 7 118 34 4 Beat Write N A N A 1 Beat Read 1 byte 13 13 13 13 1 Beat Read 2 to 8 34 13 34 13 bytes 1 Beat Write 21 21 21 21 Note The information in Table 3 8 applies to access timing when configured for devices with an access time equal to 3 clock periods http www motorola com
167. cessor has a separate Current Task Priority Level register The system software uses this register to indicate the relative priority ofthe task running on the corresponding processor The interrupt controller will not deliver an interrupt to a processor unless it has a priority level which is greater than the current task priority level of that processor This value is also used in determining the destination for interrupts which are delivered using the distributed deliver mode http www motorola com computer literature 2 65 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Architectural Notes The hardware and software overhead required to update the task priority register synchronously with instruction execution may far outweigh the anticipated benefits of the task priority register To minimize this overhead the interrupt controller architecture should allow the task priority register to be updated asynchronously with respect to instruction execution Lower priority interrupts may continue to occur for an indeterminate number of cycles after the processor has updated the task priority register If this is not acceptable the interrupt controller architecture should recommend that if the task priority register is not implemented with the processor the task priority register should only be updated when the processor enters or exits an idle state Only when the task priority register is integrated within the processor su
168. ch that it can be accessed as quickly as the MSRee bit for example should the architecture require the task priority register be updated synchronously with instruction execution Effects of Interrupt Serialization external interrupt sources that are level sensitive must be negated at least N PCI clocks prior to doing an EOI cycle for that interrupt source where N is equal to the number of PCI clocks necessary to scan in the external interrupts In the example shown 16 external interrupts are scanned in N 16 Serializing the external interrupts causes a delay between the time that the external interrupt source changes level and when MPIC logic actually sees the change Spurious interrupts can result if an cycle occurs before the interrupt source is seen to be negated by MPIC logic 2 66 Computer Group Literature Center Web Site Registers Registers This section provides a detailed description of all PHB registers The section is divided into two parts the first covers the PPC Registers and the second covers the PCI Configuration Registers The PPC Registers are accessible only from the PPC bus using any single beat valid transfer size The PCI Configuration Registers reside in PCI configuration space These are primarily accessible from the PPC bus by using the ADDRESS and CONFIG DATA registers PPC Registers are described first the PCI Configuration Registers are described next A complete di
169. ck to SDRAM using corrected data providing the SWEN control bit is set It does not perform the write if the SWEN bit is cleared If the SMC detects a double bit error it does not perform a write If so enabled single and double bit scrub errors are logged and the PPC60x bus master is notified via interrupt CSR Accesses The SMC has a set of control and status registers CSR that allow software to control certain functions and to monitor some status External Register Set The SMC has an external register chip select pin which enables it to talk to an external set of registers This interface is like the ROM Flash interface but with less flexibility It is intended for the system designer to be able to implement general purpose status control signals with this external set Refer to the section on External Register Set further on in this chapter for a description of this register set The SMC has a mode in which two of its pins become control register outputs When the SMC is to operate in this mode the External Register Set cannot be implemented The two control bits appear in the range where the External Register Set would have been had it been implemented Computer Group Literature Center Web Site Programming Model Chip Configuration Some configuration options in the Hawk must be configured at power up reset time before software performs any accesses to it The Hawk obtains this information by latching the value on s
170. cular memory area on the PCI bus which will be used to access PPC bus resources The value of this field will be compared with the upper 16 bits of the incoming PCI address END End Address This field determines the end address of a particular memory area on the PCI bus which will be used to access PPC bus resources The value of this field will be compared with the upper 16 bits of the incoming PCI address PCI Slave Attribute Offset 0 1 2 and 3 Registers Offset PSOFFO PSATTO 84 PSOFFI PSATTI 8C PSOFF2 PSATT2 94 PSOFF3 PSATT3 9C eu amp Name PSOFFx EE EEREEEASA lee Ke EZ 22 102122 24 24 Operation R W MM SS Reset 0000 lelelei ei esleieeoeoeeee The PCI Slave Attribute Registers PSATTx contain attribute information associated with the mapping of PCI memory space to PPC memory space The fields within the PSATTx registers are defined as follows 2 104 Computer Group Literature Center Web Site Registers INV Invalidate Enable If set the PPC Master will issue a transfer type code which specifies the current transaction should cause an invalidate for each PPC transaction originated by the corresponding PCI Slave The transfer type codes generated are shown in Table 2 3 GBL Global Enable If set the
171. d ahead has been enabled The encoding of this field is shown in the table above WXFT Write FIFO Threshold 00 4 Cache lines 01 3 Cache lines 10 2 Cache lines 11 1 Cache lines WXFTx Write Any FIFO Threshold This field is used by the PHB to determine a FIFO threshold at which to start writing data into local memory during any PCI write transaction Once the threshold is exceeded and the write has begun the PHB will continue to empty its FIFO until it can no longer create a cache line This field is only applicable if write posting has been enabled The encoding of this field is shown in the above table The PCI Slave Offset Registers PSOFFx contain offset information associated with the mapping of PCI memory space to PPC memory space The field within the PSOFFx registers is defined as follows PSOFFx PCISlave Offset This register contains a 16 bitoffset that is added to the upper 16 bits of the PCI address to determine the PPC address used for transfers from PCI to the PPC bus This offset allows PPC resources to reside at addresses that would not normally be visible from PCI CONFIG ADDRESS Register The description of the CONFIG ADDRESS register is presented in three perspectives from the PCI bus from the PPC bus in big endian mode and from the PPC bus in little endian mode Note that the view from the PCI bus is purely conceptual since there is no way to access the CONFIG ADDRESS register from the
172. d and 192MB on a mezzanine the beginning of PCI memory would be rounded up to address 0x50000000 1G 256M http www motorola com computer literature 1 5 Product Data and Memory Maps Table 1 3 Suggested CHRP Memory Map 1 Programmable via Hawk ASIC Processor Address Size Definition Notes Start End 0000 0000 top dram dram size System Memory onboard DRAM 1 top dram 4G dram size PCI Memory Space 1 5 F400 0000 F7FF FFFF 64MB FLASH Bank A optional 12 F800 0000 64MB FLASH Bank B optional 1 2 00 0000 FDFF FFFF 32MB Reserved FE00 0000 FFFF 8MB PCI ISA I O Space 1 FE80 0000 FFFF 7 5MB Reserved FEF8 0000 FEF8 FFFF 64KB System Memory Controller Registers FEF9 0000 FEFE FFFF 384KB Reserved FEFF 0000 FEFF FFFF 64KB Processor Host Bridge Registers 4 00 0000 FF7F FFFF 8MB FLASH Bank A preferred 1 2 FF80 0000 FF8F FFFF IMB FLASH Bank B preferred 1 2 FF90 0000 FFEF FFFF 6MB Reserved FFFO 0000 FFFF FFFF IMB Boot ROM 3 Notes 2 The actual PowerPlus II size of each ROM FLASH bank may vary 3 The first IMB of ROM FLASH Bank A appears at this range after a reset if the rom_b_rv control bit is cleared If the rom b rv control bit is set this address maps to ROM FLASH Bank B 4 The only method to generate a PCI Interrupt Acknowledge cycle 8259 is to
173. d cycles The PHB checks data parity whenever it is sinking PPC data This happens during PPC Master read cycles and PPC Slave write cycles Data parity is considered valid anytime has been asserted If a data parity error is detected then the PHB will latch address and attribute information within the ESTAT EADDR and EATTR registers and an interrupt or machine check will be generated depending on the programming of the ESTAT register The PHB has a mechanism to purposely induce data parity errors for testability The DPE field within the ETEST register can be used to purposely inject data parity errors on specific data parity lines Data parity errors can only be injected during cycles where PHB is sourcing PPC data The PHB will generate address parity whenever it is sourcing a PPC address This will happen for all PPC Master transactions Valid address parity will be presented when ABB 15 being asserted The PHB has a mechanism to purposely inject address parity errors for testability The APE field within the ETEST register can be used to purposely inject address parity errors on specific address parity lines Address parity errors can only be injected during cycles where PHB is sourcing a PPC address The PHB does not have the ability to check for address parity errors http www motorola com computer literature 2 17 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PPC Bus Timer The PPC Timer allows
174. d cycles that access the SMC the Hawk generates the correct value on DPO DP7 so that each data byte lane along with its corresponding DP signal has odd parity This can be changed on a lane basis to even parity by software bits that can force the generation of wrong even parity During write cycles to the SMC the SMC checks each of the eight PPC60x data byte lanes and its corresponding DP signal for odd parity If any of the eight lanes has even parity the SMC logs the error in the CSR and can generate a machine check if so enabled While normal default operation is for the SMC to check data parity only on writes to it it can be programmed to check data parity on all reads or writes to any device on the PPC bus Refer to the Data Parity Error Log Register section further on in this document for additional control register details PPC60x Address Parity The Hawk has four AP pins for generating and checking PPC60x address bus parity During any address transfer cycle on the PPC60x the SMC checks each of the four 8 bit PPC60x address lanes and its corresponding AP signal for odd parity If any of the four lanes has even parity the SMC logs the error in the CSR and can generate a machine check if so enabled Note that the SMC does not generate address parity because it is not a PPC60x address master Refer to the Address Parity Error Log Register section further on in this document for additional control register details Com
175. d error was multiple bit then these bits are meaningless Refer to the section on SDRAM ECC Codes for a decoding of the syndromes Together these three bits indicate which block of SDRAM was being accessed when the SMC logged a scrub error esblk0 esblk1 esbik2 are 0 0 0 for Block 0 0 1 for Block B 0 1 0 for Block C and 0 1 1 for Block D etc scof is set by the SBE COUNT register rolling over from FF to 00 It is cleared by software writing a 1 to it SBE COUNT keeps track of the number of single bit errors that have occurred since it was last cleared It counts up by one each time it detects a single bit error independent of the state of the elog bit The SBE COUNT is cleared by power up reset and by software writing all zeros to itself When SBE COUNT rolls over from FF to 00 the SMC sets the scof bit The rolling over of SBE COUNT pulses the Hawk s internal error interrupt low if the scien bit is set Computer Group Literature Center Web Site Programming Model Error Address Register Address FEF80038 Bit ER ERROR ADDRESS ooo Operation READ ONLY 24 nA Reset P lt P lt P lt ERROR_ADDRESS Scrub Refresh Register These bits reflect the value that corresponds to bits 0 28 of the PPC60x address bus when the SMC last logged
176. d logic The PMC RESETOUT_L pin will also be activated by all reset sources except for the PMC PCI RST input Soft Reset Software can assert the SRESET pin of the processor by appropriately programming the PO bit in the Processor Init Register of the Hawk MPIC CPU Reset The Hawk SRST1_L output is connected to the CPU reset logic Setting the P1 bit in the Hawk Processor Init register will result in the local processor being held in reset Clearing the P1 bit will release the reset This feature can be used by a processor on the host board to disable the local processor while the host processor programs the Bank A on board FLASH http www motorola com computer literature 4 5 Hawk Programming Details Error Notification and Handling The Hawk ASIC can detect certain hardware errors and can be programmed to report these errors via the MPIC interrupts or the Machine Check Interrupt The following table summarizes how the hardware errors are handled by the MVMES100 series Table 4 3 Error Notification and Handling Cause Action Single bit ECC Store Write corrected data to memory Load Present corrected data to the MPC master Generate interrupt via MPIC if so enabled Double bit ECC Store Terminate the bus cycle normally without writing to SDRAM Load Present uncorrected data to the MPC master Generate interrupt via MPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled MPC Bus
177. da eS sd Sega emm WDTxCNTL Name m gt RES RELOAD jaa Operation W R R W R W 2 Reset 00 l gt 00 7 8 FF The Watchdog Timer Control Registers WDT1CNTL and WDT2CNTL are used to provide control information to the watchdog timer functions within the PHB The fields within WDTxCNTL registers are defined as follows 2 92 Computer Group Literature Center Web Site Registers KEY ENAB ARM RES Key This field is used during the two step arming process of the Control register This field is sensitive to the following data patterns PATTERN 1 55 PATTERN 2 AA The Control register will be in the armed state if PATTERN 1 is written to the KEY field The Control register will be changed if in the armed state and PATTERN 2 is written to the KEY field An incorrect sequence of patterns will cause the Control register to be in the unarmed state A value of all zeros will always be returned within the KEY field during read cycles ENAB This field determines whether or not the WDT is enabled If a one is written to this bit the timer will be enabled A zero written to this bit will disable the timer The ENAB bit may only be modified on the second step of a successful two step arming process ARMED This read only bit indicates the armed state of the register If this bit is a zero the register is unarmed If this bit is a one the register is armed for a write RESOLU
178. device address the initial word address will be loaded into the C Transmitter Data Register to be transmitted to the slave device Again i2 cmplt and 12 ackin bits must be tested for proper response After the initial word address is successfully transmitted the first data word loaded into the C Transmitter Data Register will be transferred to the initial address location of the slave device After i2 cmplt and 12 ackin bits have been tested for proper response the next data word loaded into the C Transmitter Data Register will be transferred to the next address location of the slave device and so on until the block transfer is complete A stop sequence then must be transmitted to the slave device by first setting the 12 stop and i2 enbl bits in the PC Control Register and then writing a dummy data data don t care to the PC Transmitter Data Register The PC Status Register must now be polled to test i2 cmplt bit for the operation complete status The stop sequence will initiate a programming cycle for the serial EEPROM and also relinquish the ASIC master s possession of the bus Figure 3 8 shows the suggested software flow diagram for programming the PC page write operation http www motorola com computer literature 3 29 System Memory Controller SMC DEVICE ADDR WORD ADDR 1 DATA 1 DATAn M SDA START S B STOP 25 gt
179. dition should be generated to abort the transfer after a software wait loop 1ms has been expired Figure 3 6 Programming Sequence for 2 Random Read 3 26 Computer Group Literature Center Web Site Functional Description I C Current Address Read slave device should maintain the last address accessed during the last IC read or write operation incremented by one The first step in the programming sequence should be to test the i2 cmplt bit for the operation complete status The next step is to initiate a start sequence by first setting the i2 start and 12 enbl bits in the Control Register and then writing the device address bits 7 1 and read bit bit 0 1 to the VC Transmitter Data Register The 12 bit will be automatically clear with the write cycle to the Transmitter Data Register The Status Register must now be polled to test the 12 cmplt and 12 ackin bits The 12 bit becomes set when the device address and read bit have been transmitted and the i2 ackin bit provides status as to whether or not a slave device acknowledged the device address With the successful transmission of the device address the master controller writes a dummy value data don t care to the Transmitter Data Register This causes the PC master controller to initiate a read transmission from the slave device Again i2_cmplt bit must be tested for proper response After the master contr
180. dress spaces marked for no prefetching receive a TRDY indication on the PCI bus only after one burst read has successfully completed on the PPC bus Each read on the PPC bus is only started after the previous read is acknowledged on the PCI bus and there is an indication that the PCI Master wishes for more data to be transferred The following paragraphs identify some associations between the operation of the PCI slave and the PCI 2 1 Local Bus Specification requirements Computer Group Literature Center Web Site Functional Description Command Types Table 2 7 shows which types of PCI cycles the slave has been designed to accept Table 2 7 PCI Slave Response Command Types Command Type Slave Response Interrupt Acknowledge No Special Cycle No I O Read Yes I O Write Yes Reserved No Reserved No Memory Read Yes Memory Write Yes Reserved No Reserved No Configuration Read Yes Configuration Write Yes Memory Read Multiple Yes Dual Address Cycle No Memory Read Line Yes Memory Write and Yes Invalidate Addressing The PCI Slave will accept any combination of byte enables during read or write cycles During write cycles a discontinuity 1 a hole in the byte enables forces the PCI Slave to issue a disconnect During all read cycles the PCI Slave returns an entire word of data regardless of the byte enables During I O read cycles the PCI Slave performs int
181. e PCI Slave places command information into the PCI FIFO The PPC Master draws this command information from the PCI FIFO when it is ready to process the transaction During write transactions write data is captured from the PCI bus within the PCI Input block This data is fed into the PCI FIFO The PPC Output block removes the data from the FIFO and presents it to the PPC60x bus During read transactions read data is captured from the PPC60x bus within the Input block From there the data is fed into the PCI FIFO The PCI Output block removes the data from the FIFO and presents it to the PCI bus The MPIC is hosted by the PHB A custom MPIC Interface is provided to allow write data and control to be passed to the MPIC and to allow read data to be passed back to the PHB The MPIC Interface is controlled exclusively by the PCI Slave The data path function imposes some restrictions on access to the MPIC the PCI Registers and the PPC Registers The MPIC and the PCI Registers are only accessible to PCI originated transactions The PPC Registers are only accessible to PPC originated transactions The PHB has several small blocks that support various PPC functions Arbitration is provide by the PPC Arbiter block Cache line locking via PCI Lock is handled by the PPC Lock block Finally a timer function is implemented in the PPC Timer block The PHB also provides miscellaneous support for various PCI functions Arbitration on the PCI bus
182. e defined as follows Address FEFF0010 iis peregi Po e s Name HCSR XPAD alo mn o cc 4 2 414 4542 Vi E x zd rd Operation R R W B ec ec 120222 2 Reset ololoe xoe o oeeo eie 00 9C XPRx PPC PCI Clock Ratio This is a read only field that is used to indicate the clock ratio that has been established by the PHB at the release of reset The encoding of this field is shown in the following table XPR PPC60x PCI clock ratio 000 Undefined 001 1 1 010 2 1 011 3 1 100 32 101 Undefined 110 5 2 111 Undefined SPRQ Speculative PCI Request If set the PHB PCI Master will perform speculative PCI requesting when a PCI bound transaction has been retried due to bridge lock resolution If cleared the PCI Master will only request the PCI bus when a transaction is pending within the PHB FIFOs http www motorola com computer literature 2 77 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller WLRTx Write Lock Resolution Threshold This field is used by the PHB to determine a PPC bound write FIFO threshold at which a bridge lock resolution will create a retry on a pending PCI bound transaction The encoding of this field is shown in the following table WLRT Write lock resolution threshold 00 Match write threshold mode 1 PSATTx WXFT 01 Immediate
183. e operation complete status The stop sequence will relinquish the ASIC master s possession of the PC bus Figure 3 6 shows the suggested software flow diagram for programming the random read operation http www motorola com computer literature 3 25 System Memory Controller SMC DEVICE ADDR WORD ADDR x DEVICE ADDR M w A A M R SDA START S RIC C START S D K K B DATA x A N STOP K A i DATA from Slave Device BEGIN READ STATUS REG LOAD 09 START CONDITION C CONTROL REG LOAD DEVICE ADDR WR BIT TO y TRANSMITTER DATA REG READ STATUS REG READ STATUS REG N N Y M LOAD DUMMY DATA TO LOAD WORD ADDR x TO TRANSMITTER DATA REG TRANSMITTER DATA REG READ STATUS REG lt lt READ STATUS REG j MPLT DATIN 12 N Y READ RECEIVER DATA REG LOAD 09 REPEATED START CONDITION TO 2 CONTROL REG LOAD 05 STOP CONDITION TO CONTROL REG LOAD DEVICE ADDR RD BIT TRANSMITTER DATA REG LOAD DUMMY DATA TO TRANSMITTER DATA REG READ STATUS REG 4 N Y END Stop con
184. e rere 2 36 Table 2 12 Arbitration SONNE aiiora E EOE 2 37 Table 2 13 Address Modification for Little Endian Transfers 2 40 Table 2 14 WDTXCNTL Programin i sis inttr pri 2 44 Table 2 15 PHB Hardware a esaet a aos 2 50 Table 216 PPC Register Map for PHB ea uius peut pr SPI ance aati Fate aed Bien 2 68 Table 2 T T PCI Conn cure tint ReSISEBE 2 07 xvii Table 2 18 PCI VO ReglSlaf tien t 2 08 Table 2 19 MPIC Register one nie Ar REPRE ERIS EODD oii 2 110 Table 2 20 Cascade Mode Encoding 2 115 Table 2 21 Tie Mode Encoding sos oe bip Hosp KI Re pigs 2 115 Table 3 1 60x Bus to SDRAM Estimated Access Timing at 100 MHz with PC100 SDRAMs CAS ape OF urs dq ve i PHI REA ne kasd AMPH Pepe 3 7 Tale 3 2 Emor ROBORIS S poil D et aed 3 12 Table 3 3 PPC60x to ROM Flash 16 Bit Width Dun 3 16 Table 3 4 PPC60x to ROM Flash 64 Bit Width Paddress IMPO equi ep eti E E Eb Mer bled Urea ER ci td 3 17 Table 3 5 PPC60x Bus to ROM Flash Access Timing ins ilo 3 19 Table 3 6 PPC60x Bus to ROM Flash Access Timing pU A NUI lr c
185. ead data in the FIFO Non posted write cycle Posted write cycle and FIFO full http www motorola com computer literature 2 45 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller A simultaneous indication of a stall from both slaves means that a bridge lock has happened To resolve this one of the slaves must back out of its currently pending transaction This will allow the other stalled slave to proceed with its transaction When the PCI Master detects bridge lock it will always signal the PPC Slave to take actions to resolve the bridge lock If the PPC bus is currently supporting a read cycle of any type the PPC Slave will terminate the pending cycle with a retry Note that if the read cycle is across a mod 4 address boundary i e from address 0 02 3 bytes it is possible that a portion of the read could have been completed before the stall condition was detected The previously read data will be discarded and the current transaction will be retried If the PPC bus is currently supporting a posted write transaction the transaction will be allowed to complete since this type of transaction is guaranteed completion If the PPC bus is currently supporting a non posted write transaction the transaction will be terminated with a retry Note that a mod 4 non posted write transaction could be interrupted between write cycles and thereby results in a partially completed write cycle It is recommended that w
186. egister identifies the manufacturer of the device This identifier is allocated by the PCI SIG to ensure uniqueness 1057 has been assigned to Motorola This register is duplicated in the PPC Registers DEVID Device ID This register identifies the particular device The Hawk will always return 4803 This register is duplicated in the PPC Registers 2 98 Computer Group Literature Center Web Site Registers PCI Command Status Registers The Command Register COMMAND provides coarse control over the PHB ability to generate and respond to PCI cycles The bits within the COMMAND register are defined as follows Offset 04 Bit olo STATUS COMMAND gm x e e e la SIZ eS 0 2 ES s 442022 z el le Operation Oo SIS SIS S Co aca n ua et ea ne na oe ea SS Reset ololoocoo o o o o ololoeloeloiloooo eie ejlooo o ie eo IOSP IO Space Enable If set the PHB will respond to PCI I O accesses when appropriate If cleared the PHB will not respond to PCI I O space accesses MEMSP Memory Space Enable If set the PHB will respond to PCI memory space accesses when appropriate If cleared the PHB will not respond to PCI memory space accesses MSTR Bus Master Enable
187. egister is set the assertion of this bit will assert MCHK to the master designated by the XID field in the EATTR register When the XBTOI bit in the EENAB register is set the assertion of this bit will assert an interrupt through the MPIC XDPE PPC Data Parity Error This bit is set when the PHB detects a data bus parity error It may be cleared by writing a 1 to it writing a 0 to it has no effect When the XDPEM bit in the EENAB register is set the assertion of this bit will assert MCHK to the master designated by the XID field in the EATTR register When the XDPEI bit in the EENAB register is set the assertion of this bit will assert an interrupt through the MPIC 2 82 Computer Group Literature Center Web Site Registers PPER PCI Parity Error This bitis set when the PCI PERR_ is asserted It may be cleared by writing it to a 1 writing it toa O has no effect When the PPERM bit in the EENAB register is set the assertion of this bit will assert MCHK to the master designated by the DFLT bit in the EATTR register When the PPERI bit in the EENAB register is set the assertion of this bit will assert an interrupt through the MPIC PSER PCI System Error This bit is set when the PCISERR_ pin is asserted It may be cleared by writing it to a 1 writing it to aO has no effect When the PSERM bit in the EENAB register is set the assertion of this bit will assert MCHK to the master designated by the DFLT bit in the EATTR reg
188. egister per processor Priority levels from 0 lowest to 15 highest are supported Setting the Task Priority Register to 15 masks all interrupts to this processor Hardware will set the task register to F when it is reset or when the Init bit associated with this processor is written to a one TP Task Priority of processor Interrupt Acknowledge Registers Offset Processor 0 200A0 Processor 1 210A0 Bit 3 1 Name VECTOR Operation R R R R Reset 00 00 00 FF On PowerPC based systems Interrupt Acknowledge is implemented as a read request to a memory mapped Interrupt Acknowledge register Reading the Interrupt Acknowledge register returns the interrupt vector corresponding to the highest priority pending interrupt Reading this register also has the following side effects Reading this register without a pending interrupt will return a value of FF hex The associated bit in the Interrupt Pending Register is cleared Reading this register will update the In Service register VECTOR Vector This vector is returned when the Interrupt Acknowledge register is read http www motorola com computer literature 2 127 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller End of Interrupt Registers Offset Processor 0 200 0 Processor 1 210B0 Bit 3 3 2 2 2 2 2 272 2 2 2 1 1 1 1 1 1 1 i 1 I 1 0 9 8 7 6 5 443 2 1
189. egrity checking of the byte enables against the address being presented and assert SERR in the event there is an error http www motorola com computer literature 2 23 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller The PCI Slave only honors the Linear Incrementing addressing mode The PCI Slave performs a disconnect with data if any other mode of addressing is attempted Device Selection The PCI slave will always respond valid decoded cycles as a medium responder Target Initiated Termination The PCI Slave normally strives to complete transactions without issuing disconnects or retries There are four exceptions where the PCI Slave performs a disconnect All burst configuration cycles are terminated with a disconnect after one data beat has been transferred All transactions that have a byte enable hole are disconnected All transactions attempting to perform non linear addressing mode are terminated with a disconnect after one data beat is transferred A transaction that crosses from a valid PHB decode space to an invalid PHB decode space is disconnected Note that this does not include crossing contiguous multiple map decoder space in which case PHB does not issue a disconnect There are two exceptions where the PCI Slave performs a retry disconnect with no data transfer While within a lock sequence the PCI Slave retries all non locking masters a Atthe completion of a
190. el com design network LXT970 Intel GD82559ER Fast Ethernet PCI Controller Datasheet Intel Corporation http developer intel com design network 714682 001 Rev 1 0 March 1999 Computer Group Literature Center Web Site Related Documentation A Table A 2 Manufacturers Documents Continued Document Title Publicauon Number Texas Instruments TL16C550C UART Data Sheet TL16550 Texas Instruments http www ti com M48T37V CMOS 32Kx8 Timekeeper SRAM Data Sheet M48T37V SGS Thomson Microelectronics tap us st com 2 Wire Serial CMOS EEPROM Data Sheet AT24C04 Atmel Corporation http www atmel com atmel support http www motorola com computer literature A 3 Related Specifications Related Specifications For additional information refer to the following table for related specifications As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table A 3 Related Specifications Document Title and Source Peripheral Component Interconnect PCI Interface Specification Revision 2 1 PCI Special Interest Group P O Box 14070 Portland Oregon 97214 4070 Marketing Help Line Telephone 503 696 6111 Document Specification Ordering Telephone 1 800 433 5177 or 503 797 4207 FAX 503 234 6762 http www pcisig com Publicat
191. er 0001 Park always on PARB6 0010 Park always on PARB5 0011 Park always on PARB4 0100 Park always on PARB3 0101 Park always on PARB2 0110 Park always on PARBI 0111 Park always on PARBO 1000 Park always on HAWK 1111 None HIERx Hierarchy This field is used by the PCI Arbiter to establish a particular priority ordering when using a fixed or mixed mode priority scheme When using the fixed priority scheme the encoding of this field is shown in the table below HIER Priority ordering highest to lowest 000 PARB6 gt PARB5 gt PARBA gt PARB3 gt PARB2 gt PARBI gt PARBO gt HAWK 001 HAWK gt PARB6 gt PARB5 gt PARB4 gt PARB3 gt PARB2 gt PARBI gt PARBO 010 PARBO gt HAWK gt PARB6 gt PARB5 gt PARB4 gt PARB3 gt PARB2 gt PARBI 011 PARBI gt PARBO gt HAWK PARB6 gt PARBS gt PARB4 gt PARB3 gt PARB2 100 PARB2 PARBI gt gt HAWK PARB6 gt 5 PARBA gt PARB3 101 PARB3 PARB2 PARBI PARBO gt HAWK gt PARB6 PARBS 4 110 PARBA gt PARB3 gt PARB2 gt PARBI gt PARBO gt HAWK gt PARB6 gt 5 111 5 gt PARB4 gt PARB3 gt PARB2 gt PARBI gt PARBO gt HAWK gt PARB6 http www motorola com computer literature 2 75 Hawk PCI Host Bridge amp Multi Processor Interrupt Contro
192. er Group Literature Center Web Site PCI Local Bus MODFAIL Bit Register The 5100 implementation of this register is fully compliant with the PowerPlusII programming specification with exceptions to bit RDS as indicated in the following table The MODFAIL Bit Register provides the means to illuminate the module s Board Fail LED Table 1 12 MODFAIL Bit Register REG Module Fail Bit Register FEF88090h BIT RDO RDI RD2 RD3 RD4 RD5 RD6 RD7 FIELD amp lt tA E lt 2 o R W R R W RESET 0 1 REQUIRED X X X X OR OPTIONAL MODFAIL Setting this bit will illuminate the Board Fail LED Clearing this bit will turn off the LED ABORT This bit provides the current state of the ABORT signal If set is not active If cleared the ABORT signal is active GREEN LED This bit not used http www motorola com computer literature Product Data and Memory Maps MODRST Bit Register The MODRST Bit register provides the means to reset the board Table 1 13 MODRST Bit Register REG Module Reset Bit Register FEF880A0h BIT DO DI D2 D3 D4 D5 D6 D7 FIELD Q mc E 24 9 E s 5 Z OPER R R R R R R R RESET X X X X X X X 0 MODRST Setting this bit resets the module This bit will automatically clear following the reset This bit is undefined when reading
193. errupt controller This value reports what level of the specification is supported by this implementation Version level of 02 is used for the initial release of the MPIC specification Global Configuration Register Offset 01020 Bit 3 2 2 2 2 2 272 22 2 1 1 1 I1 1 1 I 1 1 1 09 8 7 6 5 49 3 2 1 0 9 8 7 GF 5 4 3 2 1 0 9 81 7 6 5 4 3121 1 O Name GLOBAL CONFIGURATION d m z RIP m Operation Z zm R R R R zz Reset 00 00 00 00 RESET RESET CONTROLLER Writing one to this bit forces the controller logic to be reset This bit is cleared automatically when the reset sequence is complete While this bit is set the values of all other register are undefined EINTT External Interrupt Type This read only bit indicates the external interrupt type serial or parallel mode When this bit is set MPIC is in serial mode for external interrupts 0 through 15 When this bit is cleared MPIC is in parallel mode for external interrupts 2 114 Computer Group Literature Center Web Site Registers CASCADE MODE Allows cascading of an external 8259 pair connected to the first interrupt source input pin 0 In the pass through mode interrupt source 0 is passed directly through to the processor 0 INT pin MPIC is essentially disabled In the mixed mode 8259 interrupts are delivered using the priority and distribution mechanism of the MPIC The Vector
194. ery mode P1 PROCESSOR 1 The interrupt is pointed to processor 1 0 PROCESSOR 0 The interrupt is pointed to processor 0 Interprocessor Interrupt Dispatch Registers Offset Processor 0 20040 20050 20060 20070 Processor 1 21040 21050 21060 21070 Bit 3 2 2 2 2 2 292 2 2 2 1 1 1 1 1 1 1 1 1 H 019181716 5144312111019 817 6 5 4 3 2111019 8 7 6 5 4 3121110 DISPATCH Operation R R R R gz Reset 00 00 00 00 oo There are four Interprocessor Interrupt Dispatch Registers Writing to an IPI Dispatch Register with the PO and or P1 bit set causes an interprocessor interrupt request to be sent to one or more processors Note that each IPI Dispatch Register has two addresses These registers are considered to be per processor registers and there is one address per processor Reading these registers returns zeros P1 PROCESSOR 1 The interrupt is directed to processor 1 PO PROCESSOR 0 The interrupt is directed to processor 0 2 126 Computer Group Literature Center Web Site Registers Current Task Priority Registers Offset Processor 0 20080 Processor 1 21080 Bit 3 3 2 2 2 2 2 272 2 22 1 1 1 I 1 1 1 1 1 H 1 O 9 8 7 6 5 47 3 2 1 Of 9 8 7 6F 5 4 3 2 1 Of 9 877 6 5 4 3 2 1 0 Name CURRENT TASK PRIORITY TP Operation R R R R R W Reset 00 00 00 0 F There is one Task Priority R
195. ess when the PSMA or PRTA bits are set in the ESTAT register The register s contents are not defined when the XDPE PPER or PSER bits are set in the ESTAT register Address FEFF0028 Bit 1 1 1 1 1 1 1 1 1 12 2 2 2 2 21 2 2 2 2 3 3 0 1 2 3 4 5 6 79 8 9 OF 1121314 5617 8 9 0 1 2 30 4 5 6 7 8 9 0 1 Name EAADR Operation R Reset 00000000 2 84 Computer Group Literature Center Web Site Registers PPC Error Attribute Register The Error Attribute Register EATTR captures attribute information on the various errors that the PHB can detect If the XDPE PPER or PSER bits are set in the ESTAT register the contents of the EATTR register are zero If the XBTO bit is set the register is defined by the following table Address FEFF002C Bit 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 3 0 1 2 3 4 5 6 7 8 9 0 1 2 3 gt lt gt lt E 2 5 N Operation R R Reset 00 00 XIDx PPC Master ID This field contains the ID of the PPC master which originated the transfer in which the error occurred The encoding scheme is identical to that used in the GCSR register TBST Transfer Burst This bit is set when the transfer in which the error occurred was a burst tr
196. exible address mappings between the MPC and the PCI local bus Refer to Chapters 2 and 3 in this manual for more programming information on the Hawk Computer Group Literature Center Web Site Hawk ASIC The Hawk ASIC also provides an Multi Processor Interrupt Controller MPIC to handle various interrupt sources The interrupt sources are Four MPIC Timer Interrupts the interrupts from all PCI devices and the two software interrupts Hawk 12 interface and configuration information The Hawk ASIC has an C Inter Integrated Circuit two wire serial interface bus Serial Clock Line SCL and Serial Data Line SDA composed of two 256 x 8 Serial EEPROM s This interface has master only capability and is used to communicate the configuration information to a slave serial EEPROM A separate EEPROM is used to maintain the configuration information related to the board Vital Product Data VPD User Configuration Data UCD and a separate EEPROM for on board Memory Subsystem Data MSD If an optional memory mezzanine is used that mezzanine shall contain a separate EEPROM with its own memory subsystem data Each slave device connected to the 2 bus is software addressable by a unique address There be seven slave devices connected to the IC bus on the MVMES100 VPD address is A0 The UPD address is A2 The on board MSD address Memory Bank A and B is A8 The optional Memory Mezzanine 1 MSD addresses is AA
197. f one of the following sets of conditions is true the interrupt pin for processor 0 is driven active Setl The source ID in IRR 015 from an external source The destination bit for processor 1 is 0 for this interrupt The priority from IRR 0 is greater than the highest priority in ISR 0 The priority from IRR 0 is greater than the contents of task register 0 Set2 The source ID in IRR 015 from an external source The destination bit for processor 1 is a 1 for this interrupt The source ID in IRR 0 is not present is 5 1 The priority from IRR 0 is greater than the highest priority in ISR 0 The priority from IRR 0 is greater than the Task Register 0 contents The contents of Task Register 0 15 less than the contents of Task Register 1 Q Set3 The source ID in IRR 0 is from an internal source The priority from IRR 0 is greater than the highest priority in ISR 0 The priority from IRR 0 is greater than the Task Register 0 contents There is a possibility for a priority tie between the two processors when resolving external interrupts In that case the interrupt will be delivered to processor 0 or processor 1 as determined by the TIE mode bit This case is not defined in the above rule set http www motorola com computer literature 2 61 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Programming Notes External Interrupt Service The following summarizes how an ex
198. g model Supports two processors Supports 16 external interrupts L DL D Supports 15 programmable Interrupt amp Processor Task priority levels Supports the connection of an external 8259 for ISA AT compatibility Distributed interrupt delivery for external I O interrupts Direct Multicast interrupt delivery for Interprocessor and timer interrupts Four Interprocessor Interrupt sources Four timers Q Processor initialization control Architecture The PCI Slave of the PHB implements two address decoders for placing the MPIC registers in PCI IO or PCI Memory space Access to these registers requires PPC and PCI bus mastership These accesses include interrupt and timer initialization and interrupt vector reads The MPIC receives interrupt inputs from 16 external sources four interprocessor sources four timer sources and one Hawk internal error interrupt source The externally sourced interrupts 1 through 15 have two modes of activation low level or active high positive edge External interrupt 0 can be either level or edge activated with either polarity The Hawk internal error interrupt request is an active low level sensitive interrupt The Interprocessor and timers interrupts are event activated http www motorola com computer literature 2 51 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller If the OPIC bit refer to the General Control Status Feature Registers section for m
199. g of the associated cache line and works its way up to but not including the word addressed by the CWF request 2 26 Computer Group Literature Center Web Site Functional Description It should be noted that even though the PCI Master can support burst transactions a majority of the transaction types handled are single beat transfers Typically PCI space is not configured as cacheable therefore burst transactions to PCI space would not naturally occur It must be supported since it is conceivable that bursting could happen For example nothing prevents the processor from loading up a cache line with PCI write data and manually flushing the cache line The following paragraphs identify some associations between the operation of the PCI Master and the PCI 2 1 Local Bus Specification requirements Command Types The PCI Command Codes generated by the PCI Master depend on the type of transaction being performed on the PPC bus Please refer to the section on the PPC Slave earlier in this chapter for a further description of PPC bus read and PPC bus write Table 2 8 summarizes the command types supported and how they are generated Table 2 8 PCI Master Command Codes Entity Addressed PPC TBST PCI Command Transfer Type Read 0000 Interrupt Acknowledge CONADD CONDAT Write 0001 Special Cycle Mapped PCI Space Read X 0 0010 I O Read Write x 0
200. gisters CONFIG DATA Register The description of the CONFIG DATA register is also presented in three perspectives from the PCI bus from the PPC bus in Big Endian mode and from the PPC bus in Little Endian mode Note that the view from the PCI bus is purely conceptual since there is no way to access the DATA register from the PCI bus Conceptual perspective from the PCI bus Offset CFF CFE CFD CFC Bit 3 3 2 2 2 2 2 272 2 2 2 1 1 1 I 1 1 1 1 1 1 1 O 9 8 7 6 5 49 3 2 1 01 9 8 7 6 5 4 Name CONFIG_DATA Data D Data Data Data A Operation R W R W R W R W Reset n a n a n a n a Perspective from the PPC bus in Big Endian mode Offset CFC CFD CFE CFF Bit DL 1 1 1 1 1 1 Name CONFIG_DATA Data A Data Data Data D Operation R W R W R W R W Reset n a n a n a n a Perspective from the PPC bus in Little Endian mode Offset CF8 CF9 CFA CFB Bit DH DATA Data D Data C Data Data A Operation R W R W R W R W Reset n a n a n a n a http www motorola com computer literature 2 109 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller MPIC Registers The following conventions are used in the Hawk register charts R Read Only field R W Read Write field
201. gt 3 cache lines FIFO gt 1 cache line 10 1 FIFO gt 2 cache lines FIFO gt 1 cache line 11 1 FIFO gt cache lines FIFO gt 1 cache line The PPC Master has an optional read ahead mode controlled by the RAEN bit in the PSATTX registers that allows the PPC Master to prefetch data in bursts and store it in the PCI FIFO The contents of the PCI FIFO is then used to satisfy the data requirements for the remainder of the PCI read transaction The PHB read ahead mechanism is tuned for maximum efficiency during typical operation conditions If excessive latencies are encountered on the PPC60x bus it may be necessary to tune the read ahead mechanism to compensate for this Additional tuning of the read ahead function is controlled by the RXFT RMFT Read Any FIFO Threshold Read Multiple FIFO Threshold fields in the PSATTX registers These fields can be used to characterize when the PPC Master continues reading ahead with respect to the PCI FIFO threshold The FIFO threshold should be raised to anticipate any additional latencies incurred by the PPC Master on the PPC60x bus Table 2 4 summarizes the PHB available read ahead options Table 2 4 PPC Master Read Ahead Options PCI Initial Subsequent dee Command Read Size i Read Size 0 Read 1 cache PCI received 1 cache line Read Line line data and FRAME_ asserted 2 12 Computer Group Literature Center Web Site
202. handling PCI I O addressing contiguous or spread address modes When the MEM bit 16 cleared the bit is used to select between these two modes whenever a PCI I O cycle is to be performed The PHB performs contiguous I O addressing when the MEM bit is clear and the IOM bit is clear The PHB takes the PPC address apply the offset specified in the XSOFFx register and map the result directly to PCI The PHB performs spread I O addressing when the MEM bit is clear and the IOM bit is set The PHB takes the PPC address applies the offset specified in the MSOFFx register and maps the result to PCI as shown in Figure 2 6 Computer Group Literature Center Web Site Functional Description PPC Address Offset 31 12 11 54 0 V J 31 25 24 54 0 0000000 PCI Address 1915 9702 Figure 2 6 PCI Spread Address Translation Spread I O addressing allows each PCI device s I O registers to reside on a different PPC memory page so device drivers can be protected from each other using memory page protection All I O accesses must be performed within natural word boundaries Any I O access that is not contained within a natural word boundary results in unpredictable operation For example an I O transfer of four bytes starting at address 80000010 is considered a valid transfer An I O transfer of four bytes starting at address 8000001 1 is considered an invalid transfer since it crosses the natural word boundary at
203. he fast mode The 2 serial clock SCL is programmable via I2 PRESCALE VAL bits in the Clock Prescaler Register The PC clock frequency is determined by the following formula CLOCK SYSTEM CLOCK I2 PRESCALE VAL 1 2 The C bus has the ability to perform byte write page write current address read random read and sequential read operations 3 22 Computer Group Literature Center Web Site Functional Description 2 Byte Write The C Status Register contains the i cmplt bit which is used to indicate if the PC master controller is ready to perform an operation Therefore the first step in the programming sequence should be to test the i cmplt bit for the operation complete status The next step is to initiate a start sequence by first setting the 12 start and 12 enbl bits in the PC Control Register and then writing the device address bits 7 1 and write bit bit 020 to the Transmitter Data Register The i cmplt bit will be automatically clear with the write cycle to the Transmitter Data Register The PC Status Register must now be polled to test the i cmplt and i ackin bits The i cmplt bit becomes set when the device address and write bit have been transmitted and the i ackin bit provides status as to whether or not a slave device acknowledged the device address With the successful transmission of the device address the word address will be loaded into the 2 Transmitter Data Register to
204. he interrupt is greater than any interrupt which is in service for that processor An interrupt is considered to be in service from the time its vector is returned during an interrupt acknowledge cycle until an EOI is received for that interrupt The EOI cycle indicates the end of processing for the highest priority in service interrupt 2 56 Computer Group Literature Center Web Site Multi Processor Interrupt Controller MPIC In the distributed delivery mode the interrupt is pointed to one or more processors but it will be delivered to only one processor Therefore for externally sourced or I O interrupts multicast delivery is not supported The interrupt is delivered to a processor when the priority of the interrupt is greater than the priority contained in the task register for that processor when the priority of the interrupt is greater than any interrupt which is in service for that processor when the priority of that interrupt is the highest of all interrupts pending for that processor and when that interrupt is not in service for the other processor If both destination bits are set for each processor the interrupt will be delivered to the processor that has a lower task register priority Note due to a deadlock condition that can occur when the task register priorities for each processor are the same and both processors are targeted for interrupt delivery the interrupt will be delivered to processor or processor 1 as de
205. here is no hole created in the memory map pu_stat0 pu stat1 stat2 and pu stat3 are read only status bits that indicate the levels that were on the RD13 RD14 RD15 and RD16 signal pins respectively at power up reset They provide a means to pass information to software using pull up pull down resistors on the RD bus or on a buffered RD bus 3 40 Computer Group Literature Center Web Site Programming Model SDRAM Enable and Size Register Blocks A B C D Address FEF80010 Bit e SLAY NY SPP OY D OS A AQ alalt l a a a SRS PS Se A A A A A Name All wv v Al Al Al vi o al All Al Al a s ol col epo 299 9 ol ol ol mers g gg S SPE gi Si g EIE g Si S EIE g Si S o ol SI Si Si of ol SI Si Si Si Si SI ss Mund EPP EEE n4 cd m 24 c m 24 c Reset a a al hj al Ax alal AY Ay Ay Oy Ay ajala cisla amp x xX x x Writes to this register must be enveloped by a period of time in which no accesses to SDRAM occur The requirements of the envelope are that all SDRAM accesses must
206. i contention between PCI and PPC 2 45 handling explained PHB 2 45 control bit descriptions 3 38 core frequency 1 9 Critical Word First CWF as supported by PCI Master 2 26 CSR accesses to SMC 3 34 architecture of SMC 3 35 base address 3 35 reads and writes 3 35 Current Task Priority Register 2 127 CWE burst transfers explained 2 26 cycle types SMC 3 11 D data discarded from prefetched reads 2 13 data parity PPC 2 17 Data Parity Error Address Register SMC 3 61 Data Parity Error Log Register SMC 3 60 Data Parity Error Lower Data Register SMC 3 62 Data Parity Error Upper Data Register SMC 3 61 data throughput PPC Slave to PCI Master 2 9 data transfer PPC Master rates 2 10 relationship between PCI Slave and PPC60x bus 2 11 data transfers SMC 3 9 decoder priorities 2 21 decoders address PCI to PPC 2 6 for PCI to PPC addressing 2 20 PPC to PCI 2 7 delayed transactions PCI Slave 2 24 derc 3 47 device selection 2 24 Disable Error Correction control bit 3 47 documentation related B 1 DRAM connection diagram 3 4 enable bits 3 41 size control bits 3 41 IN 2 Computer Group Literature Center Web Site Codes Hawk 3 86 SMC 3 11 ECC Control Register SMC 3 45 ECC memory 1 11 EEPROM 1 1 EEPROM access 3 76 elog 3 49 embt 3 49 endian conversion 2 38 endian issues MVMES100 4 7 End of Interrupt Registers 2 128 Error Address Register SMC 3 51 error correction 3 11 Error Correction Codes Hawk 3
207. i Processor Interrupt Controller The PPC60x bus transfer types generated by the PPC Master depend on the PCI command code and the INV GBL bits in the PSATTx registers The GBL bit determines whether or not the GBL_ signal is asserted for all portions of a transaction and is fully independent of the PCI command code and INV bit The following table shows the relationship between the PCI command codes and the INV bit Table 2 5 PPC Master Transfer Types PCI Command Code INV Transfer Type Transfer Size 0 4 Memory Read 0 Read Burst Single Beat 01010 Memory Read Multiple Memory Read Line Memory Read 1 Read With Intent to Burst Single Beat 01110 Memory Read Multiple Modify Memory Read Line Memory Write Write with Burst 00110 Memory Write and Invalidate Memory Write Write with Flush Single Beat 00010 Memory Write and Invalidate The PPC Master incorporates an optional operating mode called Bus Hog When Bus Hog is enabled the PPC Master continually requests the PPC bus for the entire duration of each PCI transfer When Bus Hog is not enabled the PPC Master structures its bus request actions according to the requirements of the FIFO The Bug Hog mode was primarily designed to assist with system level debugging and is not intended for normal modes of operation It is a brute force method of guaranteeing that all PCI to PPC60x transactions will be performed without an
208. ia three registers the NVRAM RTC Address Strobe 0 Register the NVRAM RTC Address Strobe 1 Register and the NVRAM RTC Data Port Register The NVRAM RTC Address Strobe 0 Register latches the lower 8 bits of the address and the NVRAM RTC Address Strobe 1 Register latches the upper 5 bits of the address Table 1 15 M48T37V Access Registers Required of Offset Address Function Optional 80C8 NVRAM RTC Address Strobe 0 7 0 This Group 8000 NVRAMIRTC Address Strobe 1 15 8 HORAE 80D8 NVRAMIRTC Data Register The NVRAM and RTC is accessed through the above three registers When accessing an NVRAM RTC location perform the following procedure 1 Write the low address 7 0 of the to the NVRAM RTC STBO register 2 Write the high address A15 A8 of the NVRAM to the NVRAM RTC STBI register and 3 Then read or write the NVRAM RTC Data Port Refer to the M48T37V Data Sheet for additional details and programming information Computer Group Literature Center Web Site PCI Local Bus Software Readable Header Switch Register S1 The MVMES100 s use of this register is fully compliant with the PowerPlus II internal programming configuration 1x8 header switch S1 is provided as the Software Readable Header Switch SRH A logic 0 means the header switch is in the on position for that particular bit and alogic 1 means the header switch is in the off position SRH Register Bit 0 is
209. idth Address Mapping PPC60x A0 A31 ROM Flash A22 A0 ROM Flash Device Selected X0000000 000000 Upper X0000001 000000 Upper X0000002 000000 Upper X0000003 000000 Upper X0000004 000000 Lower X0000005 000000 Lower X0000006 000000 Lower X0000007 000000 Lower X0000008 000001 Upper X0000009 000001 Upper X000000A 000001 Upper X000000B 000001 Upper X000000C 000001 Lower X000000D 000001 Lower X000000E 000001 Lower X000000F 000001 Lower X3FFFFFO 7FFFFE Upper X3FFFFFI 7FFFFE Upper X3FFFFF2 7FFFFE Upper X3FFFFF3 7FFFFE Upper X3FFFFFA 7FFFFE Lower X3FFFFFS 7FFFFE Lower X3FFFFF6 7FFFFE Lower X3FFFFF7 7FFFFE Lower X3FFFFF8 7FFFFF Upper X3FFFFF9 7FFFFF Upper http www motorola com computer literature System Memory Controller SMC Table 3 4 PPC60x to ROM Flash 64 Bit Width Address Mapping Continued PPC60x A0 A31 ROM Flash A22 A0 ROM Flash Device Selected X3FFFFFA 7FFFFF Upper X3FFFFFB 7FFFFF Upper X3FFFFFC 7FFFFF Lower X3FFFFFD 7FFFFF Lower X3FFFFFE 7FFFFF Lower X3FFFFFF 7FFFFF Lower Computer Group Literature Center Web Site Functional Description ROM Flash Speeds The SMC provides the interface for two blocks of ROM Flash Access times to ROM Flash are programmable for each block Access times are also affected by bloc
210. ig Endian and Little Endian modes Big Endian PROGRAM 60X System Bus Hawk N way Byte Swap Big Endian Little Endian PCI Local Bus Figure 4 1 Big Endian Mode http www motorola com computer literature 4 7 Hawk Programming Details Little Endian PROGRAM Little Endian 4 Big Endian EA Modification XOR 60X System Bus Hawk EA Modification Big Endian Little Endian PCI Local Bus Figure 4 2 Little Endian Mode 4 8 Computer Group Literature Center Web Site Endian Issues Processor Memory Domain The MPC750 processor can operate in both Big Endian and Little Endian modes However it always treats the external processor memory bus as Big Endian by performing address rearrangement and reordering when running in Little Endian mode The MPIC registers inside the Hawk the registers inside the SMC the SDRAM the ROM FLASH and the system registers always appear as Big Endian MPIC s Involvement Since PCI is Little Endian the MPIC performs byte swapping in both directions from PCI to memory and from the processor to PCI This is in order to maintain address invariance when it is programmed to operate in Big Endian mode with the processor and the memory sub system In Little Endian mode it reverse rearranges the address for PCI bound accesses and rearranges the address for memory bound accesses from In this case no byte swapping is done PCI D
211. ill be asserted and the count will remain at zero until reloaded by software or PHB reset is asserted External logic can use the output signals of the timers to generate interrupts machine checks etc Each timer is composed of a prescaler and a counter The prescaler determines the resolution of the timer and is programmable to any binary value between 1 microseconds and 32 768 microsecons The counter counts in the units provided by the prescaler For example the watchdog timer would reach a count of zero within 24 microseconds if the prescaler was programmed to 2 microseconds and the counter was programmed to 12 The watchdog timers are controlled by registers mapped within the PPC control register space Each timer has a WDTxCNTL register and a WDTXxSTAT register The WDTxCNTL register can be used to start or stop the timer write a new reload value into the timer or cause the timer to initialize itself to a previously written reload value The WDTxSTAT register is used to read the instantaneous count value of the watchdog timer Programming of the Watchdog Timers is performed through the WDTXCNTL register and is a two step process Step 1 is to arm the WDTxCNTL register by writing PATTERN 1 into the KEY field Only the KEY byte lane may be selected during this process The WDTxCNTL register will not arm itself if any of the other byte lanes are selected or the KEY field is written with any other value than PATTERN 1 The ope
212. information Test the first of the block d If the test fails disable the block clear its size to OMB disable it and then repeat steps 1 through 5 with the next block If the test passes go ahead and use the first 1M of the block 2 Using the bus determine which memory blocks are present Using the addressing scheme established by the board designer probe for SPD s to determine which blocks of SDRAM are present SPD byte 0 could be used to determine SPD presence SPD Byte 5 indicates the number of SDRAM blocks that belong to an SPD 3 Obtain the CAS latency information for all blocks that are present to determine whether to set or to clear the cl3 bit For each SDRAM block that is present a Check SPD byte 18 to determine which CAS latencies are supported b Ifa CAS latency of 2 is supported then go to Step 3 Otherwise a CAS latency of 3 is all that is supported for this block http www motorola com computer literature 3 77 System Memory Controller SMC c If a CAS latency of 2 is supported check SPD byte 23 to determine the CAS latency _2 cycle time If the CAS latency 2 cycle time is less than or equal to the period of the system clock then this block can operate with a CAS latency of 2 Otherwise a CAS latency of 3 is all that is supported for this block If any block does not support a CAS latency of 2 then 3 is to be set If all of the blocks support a CAS latency of 2 then the
213. ion Number PCI Local Bus Specification Common Mezzanine Card Specification IEEE Standards Department 445 Hoes Lane P O Box 1331 Piscataway NJ 08855 1331 http standards ieee org catalog P1386 Draft 2 0 PCI Mezzanine Card Specification IEEE Standards Department 445 Hoes Lane P O Box 1331 Piscataway NJ 08855 1331 http standards ieee org catalog P1386 1 Draft 2 0 Computer Group Literature Center Web Site MVME5100 VPD Reference Information Vital Product Data VPD Introduction Vital Product Data VPD consists of data items that are pertinent to board configuration and operation This appendix includes information on how to perform various tasks to read modify and correct Vital Product Data as well as general format and content information for this product For more detailed instructions refer to the PPCBug Firmware User s Manual as referenced in the Motorola Computer Group Documents section of Appendix A of this manual Information that is contained in the VPD includes a a Marketing Product Number e g MVME5100 013x Factory Assembly Number e g 01 W3403F01 Serial number of the specific 5100 Processor family number e g 750 7410 etc Hardware clock frequencies internal external fixed PCI bus Component configuration information connectors Ethernet addresses FLASH bank ID L2 cache ID Security information VPD type version and rev data 3
214. ion registers mapped in PCI Configuration space 2 19 configuration type 2 31 contention handling explained 2 45 endian conversion 2 38 error types described 2 41 Hawk 1 4 PPC register map 2 68 Registers described 2 40 retuning write thresholds 2 11 spread I O addressing 2 30 watchdog timers 2 42 PHB Detected Errors Destination Register 2 126 PHB Detected Errors Vector Priority Regis ter 2 125 pipelining removing 2 7 Planar PCI Device Identification 1 20 PMC slot 1 arbiter 1 15 slot 2 arbiter 1 15 PMC mode 1 11 PMC PCI Expansion Slots 1 17 PowerPC 60x address to ROM Flash address mapping with 2 32 bit or 1 64 bit 3 17 PowerPC 60x bus to ROM Flash access tim ing using 32 64 bit devices 3 19 PowerPC 60x bus to ROM Flash access tim ing using 8 bit devices 3 20 PowerPC 60x to 16bit wide ROM Flash ad dress mapping 3 16 PowerPlus II architecture 1 1 Power Up Reset status bit 3 44 PPC address mapping 2 6 Bus Address Space 2 20 bus arbiter 2 15 Bus connections 2 5 Bus features 2 1 bus interface explained 2 5 bus timer 2 18 contention with PCI 2 45 devices as little endian 2 39 devices when Big Endian 2 38 Master 2 10 Master Bug Hog 2 14 IN 6 Computer Group Literature Center Web Site Master doing prefetched reads 2 13 Master read ahead mode 2 12 parity 2 17 register map 2 68 registers 2 68 slave s role 2 7 to PCI address translation 2 7 write posting 2 9 PPC Arbiter debug functions 2 16 parking modes
215. is 66 8 MHz or 8 25 MHz 2 118 Computer Group Literature Center Web Site Registers Timer Current Count Registers Offset Timer 0 01100 Timer 1 01140 Timer 2 01180 Timer 3 011CO Bit Name 2 2 1 1 1 I I I H 1 1 1 1 0 9 8 7 GF 5 4 3 2 1 Of 9 877 6 5 4 3 2 1 0 TIMER CURRENT COUNT W N NN CC Operation R Reset 00000000 CC TOGGLE This bit toggles whenever the current count decrements to zero The bit is cleared when a value is written into the corresponding base register and the CI bit of the corresponding base register transitions from a 1 to a0 CURRENT COUNT The current count field decrements while the Count Inhibit bit is the Base Count Register is zero When the timer counts down to zero the Current Count register is reloaded from the Base Count register and the timer s interrupt becomes pending in MPIC processing http www motorola com computer literature 2 119 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Timer Basecount Registers Offset Timer 0 01110 Timer 1 01150 Timer 2 01190 Timer 3 01100 2 1212 2 1 1 1 IJ 1 1 1 1 1 I 3 2111019 817 6 514131211101918 7 6 5 413 21110 TIMER BASECOUNT BC R W UJ Bit EV aN UA AN Operation I MA IO Reset 00000000 CI COUNT INHIBIT Set
216. ister When the PSERI bit in the EENAB register is set the assertion of this bit will assert an interrupt through the MPIC PSMA PCI Master Signalled Master Abort This bitis set when the PCI master signals master abort to terminate a PCI transaction It may be cleared by writing it to a 1 writing it to a 0 has no effect When the PSMAM bit in the EENAB register is set the assertion of this bit will assert to the master designated by the XID field in the EATTR register When the PSMAI bit in the EENAB register is set the assertion of this bit will assert an interrupt through the MPIC PRTA PCI Master Received Target Abort This bit is set when the PCI master receives target abort to terminate a PCI transaction It may be cleared by writing itto a 1 writing it to a O has no effect When the PRTAM bit in the EENAB register is set the assertion of this bit will assert MCHK to the master designated by the XID field in the EATTR register When the PRTAI bit in the EENAB register is set the assertion of this bit will assert an interrupt through the MPIC http www motorola com computer literature 2 83 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PPC Error Address Register The Error Address Register EADDR captures addressing information on the various errors that the PHB can detect The register captures the PPC address when the XBTO bit is set in the ESTAT register The register captures the PCI addr
217. it states until the PCI bound FIFO is empty Write posted transactions originated from the PCI bus are flushed whenever the PCI slave has accepted a write posted transaction and the transaction has not completed on the PPC bus The PPC Slave address decode logic settles out several clocks after the assertion of TS at which time PPC Slave can determine the transaction type If it is a read and XFBR is enabled the PPC Slave will look at the ps fbrabt signal If this signal is active the PPC Slave will retry the processor When the PFBR bit is set PHB will handle read transactions originating from the PCI bus in the following manner Write posted transactions originating from the PCI bus are flushed by the nature of the FIFO architecture The PHB will hold the PCI Master with wait states until the PPC bound FIFO is empty Write posted transactions originated from the PPC60x bus are flushed in the following manner The PPC Slave will set a signal called xs fbrabt anytime it has committed to performing a posted write transaction This signal will remain asserted until the PCI bound FIFO count has reached zero The PCI Slave decode logic settles out several clocks after the assertion of FRAME at which time the PCI Slave can determine the transaction type If it is aread and PFBR is enabled the PCI Slave will look at the xs fbrabt signal If this signal is active the PCI Slave will retry the PCI Master PHB Hardware Config
218. k width Refer to Table 3 5 Table 3 6 Table 3 7 and Table 3 8 for specific timing numbers Table 3 5 PPC60x Bus to ROM Flash Access Timing 120ns 100 MHz CLOCK PERIODS REQUIRED FOR Total 1st Beat 2nd Beat 3rd Beat 4th Beat Clocks ACCESS TYPE 16 64 16 64 16 64 16 64 16 64 Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits 4 Beat Read 70 22 64 16 64 16 64 16 262 70 4 Beat Write N A N A 1 Read 1 byte 22 22 22 22 1 Read 2 to 8 70 22 70 22 bytes 1 Write 21 21 x 21 21 Note The information in Table 3 5 applies to access timing when configured for devices with an access time equal to 12 clock periods http www motorola com computer literature System Memory Controller SMC Table 3 6 PPC60x Bus to ROM Flash Access Timing 80ns 100 MHz CLOCK PERIODS REQUIRED FOR Total 1st Beat 2nd Beat 3rd Beat 4th Beat Clocks 16 64 16 64 16 64 16 64 16 64 Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits 4 Beat Read 54 18 48 12 48 12 48 12 198 54 4 Beat Write N A N A 1 Read 1 byte 18 18 18 18 1 Beat Read 2 to 8 54 18 54 18 bytes Beat Write 21 21 21 21 Notes information in Table 3 6 applies to access timing when configured for devices with an ac
219. l describe in detail the Hawk External Register Bus Address Assignments on MVMES5100 The address range for the External Register Set on MVMES5100 is fixed at FEF88000 FEF8FFFF MVME5100 Hawk External Register Bus Summary The Hawk External Register Summary of the MVMES100 is shown in the table below Table 1 9 Hawk External Register Bus Summary Bits REQUIRED r madness E 2 Ns Register Name 0 12 34 5 67 FEF88000 UART 1 RBR THR 88010 1 IER FEF88020 UART 1 IIR FCR FEF88030 THIS GROUP UART 1 LCR FEF88040 REQUIRED UART 1 MCR FEF88050 UART 1 LSR 88060 UART 1 MSR FEF88070 UART 1 SCR FEF88080 STATUS REGISTER FEF88090 MODFAIL REGISTER FEF880A0 MODRST REGISTER FEF880C0 TBEN REGISTER http www motorola com computer literature Product Data and Memory Maps Table 1 9 Hawk External Register Bus Summary Continued Address Bits REQUIRED r OPTIONAL o by PowerPlus II Register Name 0 1 2 3 4 5 6 7 FEF880C8 NVRAM RTC ADDR THIS GROUP FEF880D0 NVRAM RTC ADDR FEF880D8 NVRAMIRTC DATA FEF880E0 SOFTWARE READABLE 9 HEADER SWITCH FEF880E8 REOUIRED GEOGRAPHIC Address REGISTER FEF880F0 EXTENDED FEATURES 979 9 9
220. le When this bit is set the PSMA bit in the ESTAT register will be used to assert an interrupt through the MPIC interrupt controller When this bit is clear no interrupt will be asserted PCI Master Received Target Abort Interrupt Enable When this bit is set the PRTA bit in the ESTAT register will be used to assert an interrupt through the MPIC interrupt controller When this bit is clear no interrupt will be asserted http www motorola com computer literature 2 81 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PPC Error Status Register The Error Status Register ESTAT provides an array of status bits pertaining to the various errors that the PHB can detect The bits within the ESTAT are defined in the following paragraphs Address FEFF0024 Bit 11 11 11 1 1 1112 2 2 272 2 2 2 21213 O 1 2 3 4 5 6 7F 8 9 Of 1 2 3 4 5 6 7 8 9 0 112 34 5 6 7 8 910 1 Name ESTAT 3 eel E Operation R R R olala uu Ja ean Reset 00 00 00 oo oo oooe OVF Error Status Overflow This bit is set when any error is detected and any of the error status bits are already set It be cleared by writing a 1 to it writing a 0 to it has no effect XBTO PPC Address Bus Time out This bitis set when the PPC timer times out It may be cleared by writing a 1 to it writing a 0 to it has no effect When the XBTOM bit in the EENAB r
221. les any further interrupts from this source If the mask bit 15 cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated ACT ACTIVITY The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to one when its associated bit in the Interrupt Pending Register or In Service Register is set SENSE SENSE This bit sets the sense for Hawk s internal error interrupt It is hardwired to 1 to enable active low level sensitive interrupts PRIOR PRIORITY Interrupt priority 0 is the lowest and 15 is the highest Note that a priority level of 0 will not enable interrupts VECTOR VECTOR This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgment of the interrupt associated with this vector http www motorola com computer literature 2 125 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Hawk Internal Error Interrupt Destination Register Offset 10210 Bit 3 2 2 2 2 2 292 222 1 1 1 IB I i i J 1 1 0 9 8 7 6 5 49 3 2 1 0 9 8 7 6F 5 4 3 2 1 0 9 817165 4 3 2 1 0 Name HAWK INTERNAL ERROR INTERRUPT DESTINATION XS Operation R R R R EU zz Reset 00 00 00 00 olo This register indicates the possible destinations for the Hawk internal error interrupt source These interrupts operate in the Distributed interrupt deliv
222. ller When using the mixed priority scheme the encoding of this field is shown in the following table HIER Priority ordering highest to lowest 000 Group gt Group 2 gt Group 3 gt Group 4 001 Group 4 gt Group 1 gt Group 2 Group 3 010 Group 3 gt Group 4 gt Group 1 gt Group 2 011 Group 2 gt Group 3 gt Group 4 gt Group 1 100 Reserved 101 Reserved 110 Reserved 111 Reserved POL Park on lock If set the PCI Arbiter will park the bus on the master that successfully obtains a PCI bus lock The PCI Arbiter keeps the locking master parked and does not allow any non locked masters to obtain access of the PCI bus until the locking master releases the lock If this bit is cleared the PCI Arbiter does not distinguish between locked and non locked cycles ENA Enable This read only bit indicates the enabled state of the PCI Arbiter If set the PCI Arbiter 15 enabled and is acting as the system arbiter If cleared the PCI Arbiter is disabled and external logic is implementing the system arbiter Please refer to the section titled PHB Hardware Configuration for more information on how this bit gets set 2 16 Computer Group Literature Center Web Site Registers Hardware Control Status Prescaler Adjust Register The Hardware Control Status Register HCSR provides hardware specific control and status information for the PHB The bits within the HCSR ar
223. ly 4 byte writes are allowed The SMC ignores other writes If a valid write is attempted and rom a we is cleared the write does not happen but the cycle is terminated normally See Table 3 13 for details of ROM Flash accesses Table 3 13 Read Write to ROM Flash Cycle Alignment rom x 64 rom x we Hawk Response write 1 byte X 0 0 Normal termination but no write to ROM Flash write 1 byte X 0 1 Normal termination write occurs to ROM Flash write 1 byte X 1 X No Response write 4 byte Misaligned X X No Response write 4 byte Aligned 0 X No Response write 4 byte Aligned 1 0 Normal termination but no write to ROM Flash write 4 byte Aligned 1 1 Normal termination write occurs to ROM Flash write 2 3 5 6 7 X X X No Response 8 32 byte read X X X X Normal Termination http www motorola com computer literature System Memory Controller SMC ROM B Base Size Register Address FEF80058 Bit ec c ve c 01 L 91 91 61 02 ROM B BASE q uio 0 SM Q UJOJ 16 Operation READ WRITE Y 79 q READ ZERO Reset FF4 PL Xx X Xx X 174 001 6c 140 0215 9001 ei 140 TZS q WOI vi 1d 0 WH 2215 9 001 190 MH 190 MH X
224. m Calculation B 15 List of Figures Figwe 1 L MVMES100 Elpek DRRSUBIVE erat tabe 1 3 Figure 1 2 Master Mapping esee doses ee x pet beer epe 1 18 Figure 2 T Hawk PCI Host Bridge Block kn aerae qo 2 3 Figure 2 2 PPC to PCI Address Decoding iee err tre aportes 2 6 Figure 2 3 PPC to PCI Address Translation iuret reto debole 2 7 Pigure 2 4 PCI to PPC Address Decodilg i eere 2 20 Figure 2 5 PCI to PPC Address Trans ation uec tuper PR Rte rip 2 21 Figure 2 6 PCI Spread I O Address Translation eee 2 31 Figure 2 7 Big to Little Endian Data Swap eee entree 2 39 Figure 2 8 Serial Mode Interrupt Start aeo bete edet oe eee bs ibas tabes 2 52 piguce 2 9 MPIC Block DIEI uie Moe EN ER 2 58 Figure 3 1 Hawk Used with Synchronous DRAM in a System 3 2 Figure 3 2 Hawk s System Memory Controller Internal Data Paths 3 3 Figure 3 3 Overall SDRAM Connections 4 Blocks using Register Buffers 3 4 Figure 3 4 Hawk s System Memory Controller Block Diagram 3 5 Figure 3 5 Programming Sequence for I2C Byte Write 22222 2 3 24 Figure 3 6 Programming Sequence for I2C Random Read
225. m is 3 clocks Address Parity Error Log Register Address FEF800E0 Bit SFIS 414 maus sss RES E al a ws Golo S S S S S 9 S 8 Operation READ ZERO ES E Reset X A ajajaja ajala apelog apelog is set when a parity error occurs on the PPC60x address bus during any PPC60x address cycle TS asserted to AACK_ asserted It is cleared by writing a one to it or by power up reset ape tt0 4 ape tt is the value that was on the TTO TTA4 signals when the apelog bit was set 3 70 Computer Group Literature Center Web Site Programming Model ape 0 3 AP is the value that was on the APO AP3 signals when the apelog bit was set ape me When ape me is set the transition of the apelog bit from false to true causes the Hawk to pulse its machine check interrupt request pin MCHKO true When ape me is cleared apelog does not affect the MCHKO pin Address Parity Error Address Register Address FEF800E8 Bit DRAIN ea st oo S hani hani hani hani hanl kani hani bami _
226. mer If the transaction is PCI bound then the burden of closing out a transaction is left to the PCI bus Note that a transaction to the PPC60x registers is considered to be PCI bound since the completion of these types of accesses depends on the ability of the PCI bus to empty PCI bound write posted data A second exception is the assertion of the XTOCLM signal This is an open collector wired OR bi directional signal that is used by a bridge to indicate the burden of timing a transaction has been passed on to another bus domain The PHB asserts this signal whenever it has determined that a transaction is being timed by its own PCI bus Any other bridge devices listening to this signal understand that the current pending cycle should not 2 18 Computer Group Literature Center Web Site Functional Description be subject to a time out period During non PCI bound cycles the PPC Timer aborts the timing of the transaction any time it detects XTOCLM has been asserted PCI Bus Interface The PCI Interface of the PHB is designed to connect directly to a PCI Local Bus and supports Master and Target transactions within Memory Space I O Space and Configuration Space PCI Address Mapping The PHB provides three resources to the PCI Configuration registers mapped into PCI Configuration space bus address space mapped into PCI Memory space MPIC control registers mapped into either PCI I O space or PCI Memory sp
227. mments to the following e mail address reader comments mcg mot com In all your correspondence please list your name position and company Be sure to include the title and part number of the manual and tell how you used it Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements Conventions Used in This Manual The following typographical conventions are used in this document bold is used for user input that you type just as it appears it is also used for commands options and arguments to commands and names of programs directories and files italic is used for names of variables to which you assign values Italic is also used for comments in screen displays and examples and to introduce new terms courier is used for system output for example screen displays reports examples and system prompts Enter Return or CR CR represents the carriage return or Enter key CTRL represents the Control key Execute control characters by pressing the Ctrl key and the letter simultaneously for example Ctrl d Terminology A character precedes a data or address parameter to specify the numeric format as follows if not specified the format is hexadecimal Ox Specifies a hexadecimal number xxvi Specifies a binary number amp Specifies a decimal number An asterisk following a signal name for signals that are level significant deno
228. motorola com computer literature IN 9 lt moz lt SDRAM Speed Attributes Register 3 68 Vendor Device Register 3 39 SMC Data Parity Error Address Register 3 61 SMC Data Parity Error Log Register 3 60 SMC Data Parity Error Lower Data Register 3 62 SMC External Register Set 3 72 SMC Scrub Address Register 3 52 SMC tben Register 3 73 soft reset MPIC 4 5 software considerations 3 74 Hawk 3 74 Software Readable Header Register 1 28 sources of reset MVMES100 4 5 SPD 3 76 SPD JEDEC standard definition 1 12 Speculative PCI Request 2 47 spread I O addressing as function of PHB 2 30 Spurious Vector Register 2 118 SRAM base address 3 35 status bit descriptions 3 38 Status Register 1 23 1 24 swen 3 51 syndrome codes ordered by bit in error 3 86 System Bus 1 8 System Controller Mode bit 1 24 System Memory Controller SMC 3 1 T TA as used with PPC Slave 2 7 Table 2 10 Table 2 2 2 10 target initiated termination 2 24 TBEN Bit Register 1 27 tben Register SMC 3 73 Timer Basecount Registers 2 120 Timer Current Count Registers 2 119 Timer Destination Registers 2 122 Timer Frequency Register 2 118 Timer Vector Priority Registers 2 121 timing ROM Flash access 3 19 transaction s burst 2 8 compelled 2 7 instance of interrupt 2 8 ordering 2 48 PCI originated PPC bound described 2 5 posted 2 7 PPC originated PCI bound described 2 4 transactions PPC Slave limits 2 8 unable to retry
229. mputer literature 2 7 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller AACK and TA allows the Slave to assert a retry to the processor in the event that the transaction is unable to complete on the PCI side It should be noted that any transaction that crosses a PCI word boundary could be disrupted after only having a portion of the data transferred The PPC Slave cannot perform compelled burst write transactions The PPC bus protocol mandates that the qualified retry window must occur no later than the assertion of the first of a burst transaction If the PHB was to attempt a compelled linkage for all beats within a burst write there is a possibility that the transaction could be interrupted The interruption would occur at a time past the latest qualified retry window and the PPC Slave would be unable to retry the transaction Therefore all burst write transactions are posted regardless of the write posting attribute within the associated map decoder register If the PPC Slave is servicing a posted write transaction and the PPC FIFO can accept the transaction the assertion of AACK occurs as soon as the PPC Slave decode logic settles out and the PPC bus protocol allows for the assertion If the PPC FIFO is full the PPC Slave holds the processor with wait states AACK will not be asserted until there is room within the PPC FIFO to store the pending transaction The PPC Slave divides PPC command type
230. n Hertz e g Integer 4 2 100 000 000 decimal etc byte This is also called the local processor bus frequency 07 04 Reference Clock Frequency in Hertz e g 32 768 Integer 4 2 decimal etc This value is the frequency of the byte crystal driving the OSCM 08 06 Ethernet Address e g 08003E26A475 etc Binary 3 4 09 Variable MPU Type e g 601 602 603 604 750 801 821 ASCII 1 823 860 860DC 860DE 860DH 860EN 860 etc OA 04 EEPROM CRC Integer 4 2 This packet is optional This packet would be utilized byte in environments where CRC protection is required When computing the CRC this field i e 4 bytes is set to zero This CRC only covers the range as specified the size field OB 0 FLASH Memory Configuration Binary A table found later in this document further describes this packet OC TBD VLSI Device Revisions Versions Binary OD 04 Host PCI Bus Clock Frequency in Hertz e g Integer 4 2 33 333 333 decimal etc byte OE OF L2 Cache Configuration Binary A table found later in this document further describes this packet http www motorola com computer literature B 5 MVMES100 VPD Reference Information Table B 1 VPD Packet Types Continued ID Size Description Data Notes Type OF 04 VPD Revision A table found later in this section Binary further describes this packet 10 Reserved BF C0 User Defined FE An example of a user defined packe
231. ndian mode and all data to from PCI is swapped as described in the section titled When PPC Devices are Big Endian on page 2 38 PCI Flush Before Read If set the PHB guarantees that all PPC initiated posted write transactions are completed before any PCI initiated read transactions are allowed to complete When PFBR is clear there is no correlation between these transaction types and their order of completion Refer to the section on Transaction Ordering for more information PPC Master Bus Hog If set the PPC master of the PHB operates in the Bus Hog mode Bus Hog mode means the PPC Master continually requests the PPC bus for the entire duration of each transfer If Bus Hog is notenabled the PPC master requests the bus in a normal manner Refer to the section titled PPC Master for more information http www motorola com computer literature 2 71 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller XFBR XBTx P64 OPIC XIDx PPC Flush Before Read If set the PHB will guarantee that all PCI initiated posted write transactions will be completed before any PPC initiated read transactions will be allowed to complete When XFBR is clear there is no correlation between these transaction types and their order of completion Refer to the section titled Transaction Ordering for more information PPC Bus Time out This field specifies the enabling and PPC bus time out length to be used by the PPC timer The
232. ng Register or In Service Register is set PRIORITY Interrupt priority 0 is the lowest and 15 is the highest Note that a priority level of 0 will not enable interrupts VECTOR This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgment of the interrupt associated with this vector http www motorola com computer literature 2 121 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Timer Destination Registers Offset Timer 0 01130 Timer 1 01170 Timer 2 011B0 Timer 011F0 Bit 3 3 2 22 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 49 3 2 1 Of 9 8 7 6F 5 4 3 2 11 01 9 817165 41312110 Name TIMER DESTINATION S Operation R R R R E E Reset 00 00 00 00 oo This register indicates the destinations for this timer s interrupts Timer interrupts operate in the Directed delivery interrupt mode This register may specify multiple destinations multicast delivery P1 PROCESSOR 1 The interrupt is directed to processor 1 PO PROCESSOR 0 The interrupt is directed to processor 0 External Source Vector Priority Registers Offset Int Src 0 10000 Int Src 1 gt Int Src15 10020 gt 101E0 Bit 3 3 2 2 2 2 2 272 2 2 2 1 1 1 111 1 1 1 1 1 1 0 9 8 7 6 5 493 2 1 0 9 8 7 615 4 3 2 1 O 9 8 7 16 5 4 3 2 1 0 Name EXTERNAL SOURCE VECTOR PRIORITY E mn PR
233. nk Active Page Hit write after idle 2 1 1 1 for subsequent burst writes 1 Beat Read after idle 10 SDRAM Bank Inactive 1 Beat Read after idle 12 SDRAM Bank Active Page Miss 1 Beat Read after idle 7 SDRAM Bank Active Page Hit 1 Beat Read after 1 Beat Read 8 SDRAM Bank Active Page Miss 1 Beat Read after 1 Beat Read 5 SDRAM Bank Active Page Hit 1 Beat Write after idle 5 SDRAM Bank Active or Inactive 1 Beat Write after 1 Beat Write 13 SDRAM Bank Active Page Miss 1 Beat Write after 1 Beat Write 8 Notes 1 SDRAM speed attributes are programmed for the following CAS latency 2 tRCD 2 CLK Periods tRP 2CLK Periods tRAS 5 CLK Periods tRC 7 CLK Periods tDP 2 CLK Periods and the swr dpl bit is set in the SDRAM Speed Attributes Register 2 The Hawk is configured for external registers on the SDRAM control signals 3 8 Computer Group Literature Center Web Site Functional Description SDRAM Organization The SDRAM is organized as 1 2 3 4 5 6 7 or 8 blocks 72 bits wide with 64 of the bits being normal data and the other 8 being checkbits The 72 bits of SDRAM for each block can be made up of x4 x8 or x16 components or of 72 bit DIMMs that are made up of x4 or x8 components The 72 bit unbuffered DIMMs can be used as long as AC timing is met and they use the components listed All components must be organized with 4 internal banks 60 Bus In
234. nowledged only one will be generated The IPI channels deliver interrupts in Direct Mode and can be directed to more than one processor 8259 Compatibility The MPIC provides a mechanism to support PC AT compatible chip sets using the 8259 interrupt controller architecture After power on reset the MPIC defaults to 8259 pass through mode In this mode if the OPIC is enabled interrupts from external source number 0 the interrupt signal from the 8259 is connected to this external interrupt source on the MPIC are passed directly to processor 0 If the pass through mode is disabled and the OPIC is enabled the 8259 interrupts are delivered using the priority and distribution mechanisms of the MPIC MPIC does not interact with the vector fetch from the 8259 interrupt controller Hawk Internal Errror Interrupt Hawk s PHB and SMC detected errors are grouped together and sent to the interrupt logic as a singular interrupt source Hawk internal error interrupt This Hawk internal error interrupt request is an active low level sensitive interrupt The interrupt delivery mode for this interrupt is distributed When the OPIC is disabled the Hawk internal error interrupt will be passed directly on to processor 0 INT pin For system implementations where the MPIC controller is not used the Hawk internal error condition will be made available by a signal which is external to the Hawk ASIC Presumably this signal will be connected to an exte
235. ns if the target responds with a disconnect and there is still data to be transferred If the PCI Master detects a target abort during a read any untransferred read data is filled with ones If the PCI Master detects a target abort during a write any untransferred portions of data will be dropped The same rule applies if the PCI Master generates a Master Abort cycle Arbitration The PCI Master can support parking on the PCI bus There are two cases where the PCI Master continuously asserts its request If the PCI Master starts a transaction that is going to take more than one assertion of FRAME the PCI Master continuously asserts its request until the transaction has completed For example the PCI Master continuously asserts requests during the first part of a two part critical word first transaction Ifat least one command is pending within the FIFO 2 28 Computer Group Literature Center Web Site Functional Description The PCI Master always removes its request when it receives a disconnect a retry There is a case where the PCI Master could assert a request but not actually perform a bus cycle This may happen if the PCI Master is placed in the speculative request mode Refer to the section titled Contention Handling for more information In no case will the PCI Master assert its request for more than 16 clocks without starting a transaction Fast Back to Back Transactions The PCI Mas
236. nt CSR write accesses are restricted to a size of 1 or 4 bytes and they must be aligned http www motorola com computer literature 3 35 System Memory Controller SMC Register Summary Table 3 9 shows a summary of the internal and external register set Table 3 9 Register Summary BIT4 _ _ Jelelalela FEF80000 REVID 5 2 PU STAT FEF80008 EE E 8 8 RAMA 8 RAMB 8 RAMC 8 RAM D FEF80010 517 E SIZ 2 SIZ E SIZ FEF80018 RAM A BASE RAM B BASE RAM C BASE RAM D BASE FEF80020 CLK FREQUENCY S FEF80028 ag 9 ag A E FEF80030 3 s FIR ERR SYNDROME E 3 SBE COUNT wl S o v v v 9 g FEF80038 ERROR ADDRESS FEF80040 E SCRUB FREQUENCY 518 FEF80048 SCRUB ADDRESS ROM A BASE ROM Bl slg FEF80050 A SIZ EB Bl 2 8s ROM B BASE 5 ROM FEF80058 S BSIZ ee 8 5185 ei EE FEF80060 al ol E 21 5 All GWDP FEF80068 1 DPE TT DPE DP 1 2 D el si al 3 3 36 Computer Group Literature Center Web Site Programming Model Table 3 9 Register Summary Continued
237. o Appendix A Related Documentation PPCBug Firmware Package User s Manual PPCBug Diagnostics Manual 750 RISC Microprocessor User s Manual MPC7400 RISC Microprocessor User s Manual a a a Universe II User Manual The 5100 is a high performance VME single board computer featuring the Motorola Computer Group MCG PowerPlus II architecture with a choice of PowerPC processors either Motorola s MPC7400 with AltiVec technology for algorithmic intensive computations or the low power MPC750 As of the printing date of this manual the 5100 is available in the configurations shown below Model Description MPC750 configurations with 450 MHz MPC750 17MB Flash and 1MB L2 Cache MVMES100 0131 64MB ECC SDRAM SCANBE handles MVMES100 0161 512MB ECC SDRAM SCANBE handles MVMES100 0133 64MB ECC SDRAM IEEE 1101 handles MVMES100 0163 512MB ECC SDRAM IEEE 1101 handles MPC 7400 configurations with 400 MHz MPC7400 and 17MB Flash MVMES101 0131 64MB ECC SDRAM SCANBE handles IMB L2 Cache MVMES101 0161 512MB ECC SDRAM SCANBE handles L2 Cache MVMES101 0133 64MB ECC SDRAM IEEE 1101 handles L2 Cache MVMES101 0163 512MB ECC SDRAM IEEE 1101 handles L2 Cache MVMES101 2131 64MB ECC SDRAM SCANBE handles 2MB L2 Cache MVMES101 2133 64MB ECC SDRAM IEEE 1101 handles 2MB L2 Cache MVMES101 2141 128MB ECC SDRAM SCANBE handles 2MB L2 Cache
238. o PMC slots and one PCIX slot may be present The presence of the PMCs and or PCIX can be positively determined by reading the Base Module Feature Register The INTA INTB INTC and INTD from the three PMC PCIX slots are routed by the MVMES100 as follows PMC Slot 1 PMC Slot 2 PCIX Slot INTA INTB INTC INTD INTA INTB INTC INTD INTA INTC INTD i T i m T i IRQ9 IRQ10 IRQ11 IRQ12 Hawk MPIC The Universe ASIC The VMEbus interface is provided by the Universe ASIC Refer to the Universe II User Manual as listed in Appendix A Related Documentation for more information http www motorola com computer literature 1 17 Product Data and Memory Maps PROCESSOR PCI MEMORY VMEBUS 4 ONBOARD MEMORY PROGRAMMABLE SPACE NOTE 2 PCI MEMORY NOTE SPACE M 55 VME A24 VME A16 NOTE 3 VME A24 My VME 16 NOTE 1 PCI ISA VME A24 MEMORY SPACE VME A16 5 VME 24 VME 16 V MPC RESOURCES NOTES 1 Programmable mapping done by Hawk ASIC 11553 00 9609 2 Programmable mapping performed via PCI Slave images in Universe ASIC 3 Programmable mapping performed via Special Slave image SLSI in Universe ASIC Figure 1 2 VMEbus Master Mapping 1 18 Computer Group Literature Center Web Site PCI Local Bus PCI Configuration Space Acce
239. o snoop and retry all accesses to the locked cache line until a valid unlock is presented to the PHB and the last locked cache line transaction is successfully executed Note that the PHB locks the cache line that encompasses the actual address of the locked transaction For example a locked access to offset 0x28 creates a lock on the cache line starting at offset 0x20 From the perspective of the PCI bus the PCI Slave locks the entire resource Any attempt by a non locking master to access any PCI resource represented by the PHB results in the PCI Slave issuing a retry Parity The PCI Slave supports address parity error detection data parity generation and data parity error detection Cache Support The PCI Slave does not participate in the PCI caching protocol http www motorola com computer literature 2 25 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PCI FIFO PCI Master A 64 bit by 16 entry FIFO 4 cache lines total is used to hold data between the PCI Slave and the PPC Master to ensure that optimum data throughput is maintained The same FIFO is used for both read and write transactions A 52 bit by 4 entry FIFO is used to hold command information being passed between the PCI Slave and the PPC Master If write posting is enabled then the maximum number of transactions that may be posted is limited by the abilities of either the data FIFO or the command FIFO For example one burst transac
240. of the Hawk s PowerPC to Local Bus Bridge PHB and the Multi Processor Interrupt Controller MPIC including a list of features a block diagram a functional description and corresponding register tables Chapter 3 System Memory Controller SMC provides an explanation of the System Memory Controller SMC portion of the Hawk ASIC including a features list block diagrams functional descriptions and an explanation and description of all corresponding registers Chapter 4 Hawk Programming Details procides a summary of the Hawk programming details that are relevant to every day programming functions including a listing of the Hawk MPIC External Interrupts the 8259 Interrupts and a description of certain exceptions such as sources of reset error notification and handling endian issues and processor Hawk relationships Appendix A Related Documentation provides a listing of related Motorola manuals vendor documentation and industry specifications Appendix B MVME5100 VPD Reference Information provides an explanation of the VPD reference information including certain How to info as well as specific VPD Data Definitions Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation We want to know what you think about our manuals and how we can make them better Mail comments to Motorola Computer Group Reader Comments DW164 2900 S Diablo Way Tempe Arizona 85282 You can also submit co
241. oller has received byte of data indicated by i2_datin 1 in the C Status Register the system software may then read the data by polling the Receiver Data Register The master controller does not acknowledge the read data for a single byte transmission on the bus but must complete the transmission by sending a stop sequence to the slave device This can be accomplished by first setting the 12 stop and 12 enbl bits in the I7C Control Register and then writing a dummy data data don t care to the C Transmitter Data Register The PC Status Register must now be polled to test i2 cmplt bit for the operation complete status The stop sequence will relinquish the ASIC master s possession of the bus Figure 3 7 shows the suggested software flow diagram for programming the current address read operation http www motorola com computer literature 3 27 System Memory Controller SMC DEVICE ADDR DATA of last ADDR 1 M R A N SDA START S D O STOP K A A K ACK and DATA from Slave Device BEGIN READ STATUS REG LOAD 09 START CONDITION TO CONTROL REG LOAD DEVICE ADDR RD BIT TRANSMITTER DATA REG READ STATUS REG Y LOAD DUMMY DATA TO 2 TRANSMITTER DATA REG READ C STATUS REG MP
242. omain The PCI bus is inherently Little Endian and all devices connected directly to PCI will operate in Little Endian mode regardless of the mode of operation in the processor s domain http www motorola com computer literature 4 9 Hawk Programming Details 4 10 Computer Group Literature Center Web Site Related Documentation Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual You can obtain paper or electronic copies of Motorola Computer Group publications by Contacting your local Motorola sales office Visiting Motorola Computer Group s World Wide Web literature site http www motorola com computer literature Table A 1 Motorola Computer Group Documents Document Title Motorola Publication Number MVMES100 Single Board Computer Installation and Use V5100A IH MVME761 Transition Module Installation and Use VME761A IH MVME762 6 Channel Serial Transition Module Installation VME762A UM and Use MVME762 6 Channel Serial Transition Module Installation VME762A UMIAI and Use Supplement IPMC712 761 I O Module Installation and Use VIPMCA IH PMCspan PMC Adapter Carrier Module Installation PMCSPANA IH and Use PPCBug Firmware Package User s Manual Part 1 of 2 PPCBUGAI UM PPCBug Firmware Package User s Manual Part 2 of 2 PPCBUGA2 UM PPCBug Diagnostics Manual PPCDIAA UM To obtain the most up to date product inform
243. ome of the upper RD signals just after the rising edge of the PURST signal The recommended way to control the RD signals during reset is to place pull up or pull down resistors on the RD bus If there is a set of buffers between the RD bus and the ROM Flash devices it is best to put the pull up pull down resistors on the far side of the buffers so that loading will be kept to a minimum The Hawk s SDRAM buffer control signals cause the buffers to drive toward the Hawk during power up reset Other configuration information is needed by software to properly configure the Hawk s control registers This information can be obtained from devices connected to the I C bus Programming Model CSR Architecture The CSR control and status register set consists of the chip s internal register set and its external register set The base address of the CSR is hard coded to the address FEF80000 or FEF90000 if the RD 5 pin is high at reset To remain backwards compatible with older Raven Falcon designs Hawk offers two options RD 5 20 PHB is at OXFEFF0000 SMC is at OxFEF80000 default RD 5 1 gt PHB is at OXFEFE0000 SMC is at OXFEF90000 Accesses to the CSR are performed on the upper 32 bits of the PPC60x data bus Unlike the internal register set data for the external register set can be writen and read on both the upper and lower halves of the PPC60x data bus CSR read accesses can have a size of 1 2 4 or 8 bytes with any alignme
244. on x x x E E E E lx E E E E E E E lx x E E E E E E ez zeree 22 22 2 2 Reset clolololelolelolelelelololololololololololololololololololololo DPEx Data Parity Error Enable These bits are used for test reasons to purposely inject data parity errors whenever the PHB is sourcing PPC data A data parity error will be created on the corresponding PPC data parity bus if a bit is set For example setting DPEO will cause DPO to be generated incorrectly If the bit is cleared the PHB will generate correct data parity APEx Address Parity Error Enable These bits are used for test reasons to purposely inject address parity errors whenever the PHB is acting as a PPC bus master An address parity error will be created on the corresponding PPC address parity bus if a bit is set For example setting APEO will cause APO to be generated incorrectly If the bit is cleared the PHB will generate correct address parity The Error Enable Register EENAB controls how the PHB is to respond to the detection of various errors In particular each error type can uniquely be programmed to generate a machine check generate an interrupt generate both or generate neither The bits within the ETEST are defined as follows http www motorola com computer literature 2 79 Hawk PCI Host Bridge
245. on 0000 Park on last requestor 0001 Park on PARB6 0010 Park on PARB5 0011 Park on PARBA 0100 Park on PARB3 0101 Park on PARB2 0110 Park on PARBI 0111 Park on PARBO 1000 Park on HAWK 1111 Parking disabled http www motorola com computer literature 2 37 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Notes 1 1000 is the default setting 2 Parking disabled is a test mode only and should not be used since no one will drive the PCI bus when in an idle state 3 All other combinations in the PRK setting not specified in the table are invalid and should not be used A special function is added to the PCI arbiter to hold the grant asserted through a lock cycle When the POL bit in the PCI arbiter control register is set the grant associated with the agent initiating the lock cycle will be held asserted until the lock cycle is complete If this bit is clear the arbiter does not distinguish between lock and non lock cycle Endian Conversion The PHB supports both big and little endian data formats Since the PCI bus is inherently little endian conversion is necessary if all devices are configured for big endian operation The PHB may be programmed to perform the endian conversion described below When PPC Devices are Big Endian When all PPC devices are operating in big endian mode all data to from the PCI bus must be swapped such that the PCI bus looks big endian from the P
246. onfigurations ram a h Component Number of Block SDRAM siz0 3 Configuration SDRAM SIZE Technology Components In the Block 260000 OMBytes 0001 4Mx16 5 32MBytes 64Mbit 0010 8Mx8 9 64MBytes 64Mbit 0011 8Mx16 5 64MBytes 128Mbit 0100 16Mx4 18 128MBytes 64Mbit 0101 16Mx8 9 128MBytes 128Mbit 0110 16 16 5 128MBytes 256Mbit 200111 32Mx4 18 256MBytes 128Mbit 1000 32Mx8 9 256MBytes 256Mbit 1001 64Mx4 18 512MBytes 256Mbit 261010 Reserved 261111 Notes 1 SDRAM components should be organized with 4 internal banks 2 When DIMMs are used the Component Configuration refers to the configuration of the devices used on the DIMMs 3 It is important that all of the ram a b c d e f g h siz0 3 bits be set to accurately match the actual size of their corresponding blocks This includes clearing them to binary 00000 if their corresponding blocks are not present Failure to do so will cause problems with addressing and with scrub logging 3 42 Computer Group Literature Center Web Site Programming Model SDRAM Base Address Register Blocks A B C D Address FEF80018 Bit TPR PONT JG S FSIS ID IRIN fF Name RAM A BASE RAM B BASE RAM C BASE RAM D BASE Operation READ WRITE READ WRITE READ WRITE READ WRITE Reset 0 PL 0 PL 0 PL 0 PL
247. or 2 present 2 PCO PCIO CONN3 PCI PMC bus 0 connector 3 present 3 PCO CONNA PCI PMC bus 0 connector 4 present 4 PCO CONNI PCI PMC bus 1 connector 1 present 5 PCO CONN2 PCI PMC bus 1 connector 2 present 6 PCO CONN3 PCI PMC bus 1 connector 3 present 7 PCO CONNA PCI PMC bus connector 4 present 8 PCO ISA CONNI ISA bus connector 1 present 9 PCO 5 CONN2 ISA bus connector 2 present 10 PCO ISA CONN3 ISA bus connector 3 present 11 PCO_ISA_CONN4 ISA bus connector 4 present 12 PCO_EIDE1_CONN1 IDE EIDE device 1 connector 1 present 13 PCO EIDEI CONN2 IDE EIDE device 1 connector 2 present 14 PCO EIDE2 CONNI IDE EIDE device 2 connector 1 present 15 PCO EIDE2 CONN2 IDE EIDE device 2 connector 2 present 16 PCO_ENET1_CONN Ethernet device 1 connector present 17 PCO_ENET2_CONN Ethernet device 2 connector present 18 PCO_ENET3_CONN Ethernet device 3 connector present 19 PCO_ENET4_CONN Ethernet device 4 connector present 20 PCO_SCSI1_CONN SCSI device 1 connector present 21 PCO_SCSI2_CONN SCSI device 2 connector present 22 PCO_SCSI3_CONN SCSI device 3 connector present 23 PCO_SCSI4_CONN SCSI device 4 connector present http www motorola com computer literature MVMES100 VPD Reference Information Table B 2 MCG Product Configuration Options Data Continued Bit Number Bit Mnemonic Bit Description 24 PCO SERIAL1 CON
248. or writes to this register to work properly they should be separated from any SDRAM accesses by a refresh before the write and by another refresh after the write The refreshes serve two purposes 1 they make sure that all of the SDRAMs are idle ensuring that mode register set operations for cl3 updates work properly and 2 they make sure that no SDRAM accesses happen during the write A simple way to meet these requirments is to use the following sequence 1 2 Make sure all accesses to SDRAM done Wait for the 32 Bit Counter refer to section further on to increment at least 100 times Perform the write writes to this register and other SMC registers if desired Wait again for the 32 Bit Counter to increment at least 100 times before resuming accesses to SDRAM Computer Group Literature Center Web Site Programming Model When cl3 is cleared the SMC assumes that the SDRAM runs with a CAS latency of 2 When cl3 is set the SMC assumes that it runs with a CAS latency of 3 Note that writing so as to change cl3 from 1 to 0 or vice versa causes the SMC to perform a mode register set operation to the SDRAM array The mode register set operation updates the SDRAM s CAS latency to match cl3 trc0 1 2 Together trc0 1 2 determine the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its Trc parameter These bits are encoded as follows Table 3 16 Trc Encoding
249. ore information is enabled the Hawk detected errors will be passed on to MPIC If the OPIC bit is disabled Hawk detected errors are passed directly to the processor 0 interrupt pin External Interrupt Interface The external interrupt interface functions as either a parallel or a serial interface depending on the EINTT bit in the MPIC Global Configuration Register If this bit is set MPIC is in serial mode Otherwise MPIC operates in the parallel mode In serial mode all 16 external interrupts are serially scanned into MPIC using the SI STA and SI DAT pins as shown in Figure 2 8 In parallel mode 16 external signal pins are used as interrupt inputs interrupts 0 through 15 IVAN SISTA y No a A SI DAT Jexiol ExrExraY T Figure 2 8 Serial Mode Interrupt Scan Using PCLK as a reference external logic will pulse SI STA one clock period indicating the beginning of an interrupt scan period On the same clock period that SI STA is asserted external logic will feed the state of EXTO on the SI DAT pin External logic will continue to sequentially place EXTI through EXT15 on SI DAT during the next 15 clock periods This process may be repeated at any rate with the fastest possible next assertion of SI STA on the clock following the sampling of EXT15 Each scan process must always scan exactly 16 external interrupts Computer Group Literature Center Web Site Multi Processor Interrupt
250. ory I O space The bits within the 5 registers are defined as follows REN Read Enable If set the corresponding PPC Slave is enabled for read transactions WEN Write Enable If set the corresponding PPC Slave is enabled for write transactions WPEN Write Post Enable If set write posting is enable for the corresponding PPC Slave http www motorola com computer literature 2 89 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller MEM PCI Memory Cycle If set the corresponding PPC Slave will generate transfers to or from PCI memory space When clear the corresponding PPC Slave will generate transfers to or from PCI I O space using the addressing mode defined by the IOM field IOM PCI I O Mode If set the corresponding PPC Slave will generate PCI I O cycles using spread addressing as defined in the section titled Generating PCI Cycles When clear the corresponding PPC Slave will generate PCI I O cycles using contiguous addressing This field only has meaning when the MEM bit is clear PPC Slave Address 3 Register Address MSADD3 5 0058 Bit 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 0111213141516 7181901121314 SP 6 7 8 9 OF 112 34 4 5 6 7 8 9 OF 1 Name XSADD3 START END Operation R W R W Reset Regbase Oxfeff0000 gt 8000 Regbase Oxfeff0000 gt 8080 Regbase Oxfefe0000 gt 9000 Regbase 0000 gt 9080 The PPC Sla
251. oup Literature Center Web Site Registers Table 2 19 MPIC Register Map Continued 3322222222221111111111 Off 10998765 4321098765 4321098765 4 3 21 1 0 IPI 3 DISPATCH REGISTER PROC 0 20070 CURRENT TASK PRIORITY REGISTER PROC 0 20080 IACK REGISTER 200a0 PO EOI REGISTER 200b0 PO IPI 0 DISPATCH REGISTER PROC 1 21040 IPI 1 DISPATCH REGISTER PROC 1 21050 IPI 2 DISPATCH REGISTER PROC 1 21060 IPI 3 DISPATCH REGISTER PROC 1 21070 CURRENT TASK PRIORITY REGISTER PROC 1 21080 IACK REGISTER 210a0 P1 EOI REGISTER 210b0 P1 Feature Reporting Register Offset 01000 Bit 3 3 2 22 2 2 2 2 2 2 2 1 1 11 1f 1 1019187165 493 2 1 0 9 8 7 6F 5 4 3 2 1 0 9 817 6 5 4 3 2 110 Name FEATURE REPORTING NIRQ NCPU VID Operation R R R R R Reset 0 00F 0 01 03 http www motorola com computer literature 2 113 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller NIRQ NUMBER OF IRQs The number of the highest external IRQ source supported The IPI Timer and PHB Detected Error interrupts are excluded from this count NCPU NUMBER OF CPUs The number of the highest physical CPU supported There are two CPUs supported by this design CPU 0 and CPU 1 VID VERSION ID Version ID for this int
252. p Literature Center Web Site Functional Description PPCl Bug md feff0000 uu uou n EFF0000 10574801 00030000 00A0FFF6 00000000 W EFF0010 000000BE 00000000 00000000 00000000 PCl Bug md feff0060 0060 000FFFFF 0000 OOO0FFFFF EFF0070 03 0000 00000000 00000000 FFFFFFFF PPC1 Bug gt mw feff0068 55 b Effective address FEFF0068 Effective data 55 PPC1 Bug gt md feff0060 FEFF0060 OOOFFFFF OOOOFFFF OO4FFFFF FEFF0070 03 0000 00000000 00000000 FFFFFFFE PPCl Bug mw feff0068 0 5555 Effective address FEFF0068 Effective data AA0F5555 PPCl Bug md feff0060 FEFF0060 OOOFFFFF 0000 000F5555 00005555 FEFF0070 03 0000 00000000 00000000 FFFFFFFE PPCl Bug PCI PPC Contention Handling The PHB has a mechanism that detects when there is a possible resource contention problem i e deadlock as a result of overlapping PPC and PCI initiated transactions The PPC Slave PCI Slave and PCI Master functions contain the logic needed to implement this feature The PCI Slave and the PPC Slave contribute to this mechanism in the following manner Each slave function will issue a stall signal to the PCI Master anytime it is currently processing a transaction that must have control of the opposing bus before the transaction can be completed The events that activate this signal are Readcycle with no r
253. p reset It cannot be changed by software b siz rom b siz control bits are the size of ROM Flash for Block B They are encoded as shown in Table 3 14 Table 3 14 ROM Block B Size Encoding rom b siz SIZE 20000 1 001 2 010 4 01 8 100 16 101 32 110 64 111 Reserved rom b rv rom b rv and rom a rv determine which if either of Blocks A and B is the source of reset vectors or any other access in the range FFFO0000 SFFFFFFFF as shown in Table 3 12 rom b rv is initialized at power up reset to match the value on the RD1 pin When rom b is set accesses to Block B ROM Flash in the address range selected by ROM B BASE are enabled When rom b en is cleared they are disabled http www motorola com computer literature 3 57 System Memory Controller SMC rom b we When rom b we is set writes to Block B ROM Flash are enabled When rom b we is cleared they are disabled Refer back to Table 3 13 for more details ROM Speed Attributes Registers Address FEF80060 Bit uo ae a 18 19 20 24 25 21 22 23 27 28 29 Name Operation READ ZERO READ ZERO READ ZERO 144 Reset X X X 0 0 0 PL rom a spd0 26 PL rom a spd1 0 0 0
254. proved three contact electrical outlet with the grounding wire green yellow reliably connected to an electrical ground safety ground at the power outlet The power jack and mating plug of the power cable meet International Electrotechnical Commission IEC safety standards and local electrical regulatory codes Do Not Operate in an Explosive Atmosphere Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage Keep Away From Live Circuits Inside the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries such personnel should always disconnect power and discharge circuits before touching components Use Caution When Exposing or Handling a CRT Breakage of a Cathode Ray Tube CRT causes a high velocity scattering of glass fragments implosion To prevent CRT implosion do not handle the CRT and avoid rough handling or jarring of the equipment Handling of a CRT should be done only by qualified service pe
255. puter Group Literature Center Web Site Functional Description Cache Coherency The SMC supports cache coherency to SDRAM only It does this by monitoring the ARTRY control signal on the PPC60x bus and behaving appropriately when itis asserted When ARTRY is asserted if the access is a SDRAM read the SMC does not source the data for that access If the access is a SDRAM write the SMC does not write the data for that access Depending upon when the retry occurs the SMC may cycle the SDRAM even though the data transfer does not happen Cache Coherency Restrictions The PPC60x GBL_ signal must not be asserted in the CSR areas L2 Cache Support The SMC provides support for a look aside L2 cache only at 66 67 MHz by implementing a hold off input L2CLM On cycles that select the SMC the SMC samples L2CLM on the second rising edge of the CLK input after the assertion of TS If L2CLM is high the SMC responds normally to the cycle If it is low the SMC ignores the cycle SDRAM ECC The SMC performs single bit error correction and double bit error detection for SDRAM across 64 bits of data using 8 check bits No checking is provided for ROM Flash Cycle Types To support ECC the SMC always deals with SDRAM using full width 72 bit accesses When the PPC60x bus master requests any size read of SDRAM the SMC reads the full width at least once When the PPC60x bus master requests a four beat write to SDRAM the SMC writes all 72
256. puter Group Literature Center Web Site PCI Arbitration 8259 Interrupts There are 15 interrupt requests supported by the Peripheral Bus Controller PBC which is only available if an IPMC761 or IPMC712 is installed These 15 interrupts are ISA type interrupts that are functionally equivalent to two 82C59 interrupt controllers Except for IRQ0 IRQ1 IRQ2 IRQS and IRQ13 each of the interrupt lines can be configured for either edge sensitive mode or level sensitive mode by programming the appropriate ELCR registers in the PBC There is also support for four PCI interrupts PIRQA through PIRQD The PBC has four PIRQ route control registers to allow each of the PCI interrupt lines to be routed to any of twelve ISA interrupt lines 1600 IRQ2 IRQ8_ and IRQ13 are reserved for ISA system interrupts These active low inputs are used for some of the on board PCI devices Since PCI interrupts are defined as level sensitive software must program the selected IRQ s for level sensitive mode The assignments of the ISA interrupts supported by the PBC as shown in the following table Table 4 2 PBC ISA Interrupt Assignments PRI PSIO Routed to 5 Edge E Interrupt Source IRQ ISA Level T 2 Input IRQ E 2 E 1 IRQO INTI Edge High Timer 1 Counter 0 1 2 MSK IRQI Edge High Not Used IRQI 3 10 IRQ2 Edge High Cascade Interrupt from INT2 3 IRQ8 INT2 Edge
257. r Dispose of used batteries according to the manufacturer s instructions Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du m me type ou d un type quivalent recommand par le constructeur Mettre au rebut les batteries usag es conform ment aux instructions du fabricant Explosionsgefahr bei unsachgem Dem Austausch der Batterie Ersatz nur durch denselben oder einen vom Hersteller empfohlenen Typ Entsorgung gebrauchter Batterien nach Angaben des Herstellers CE Notice European Community Motorola Computer Group products with the CE marking comply with the EMC Directive 89 336 EEC Compliance with this directive implies conformity to the following European Norms EN55022 Limits and Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment this product tested to Equipment Class B EN55024 Information technology equipment Immunity characteristics Limits and methods of measurement Board products are tested in a representative system to show compliance with the above mentioned requirements A proper installation in a CE marked system will maintain the required EMC performance In accordance with European Community directives a Declaration of Conformity has been made and is available on request Please contact your sales representative Notice While reasonable efforts have been made to assure the accuracy of
258. r Identification Registers pep pete ies guerre ek 2 116 Frocessor asas 2 116 IPI Verto Parity h Aana 2 117 Spurnons Vector BEEHSIBE eein 2 118 Timer Frequency Rea tet RED tede Miro 2 118 Tiner Curent Count Kees te is 2 119 Timer Bausecount enit 2 120 Timer Vector PEOPLES consi cal tel Oed 2 121 Timer Destination Stes us e ie iei RRAPI 2 122 External Source Vector Priority Registers eere 2 122 External Source Destination Registers eee ret 2 124 Hawk Internal Error Interrupt Vector Priority Register 2 125 Hawk Internal Error Interrupt Destination Register 2 126 Interprocessor Interrupt Dispatch Registers 22 2 126 Current Task Priority bare pae e EI 2 127 Interrupt Acknowledge ReglBlets aeocee ip reete tren 2 127 Ead ot Intertipt esito ED Ue DET ERR GE PUDE CREE 2 128 CHAPTER3 System Memory Controller SMC P I 3 1 lc
259. rammed into the Block L the Block s ram x siz bits 4 4M 16 32MB 0001 8M 8 64MB 0010 8M 16 64MB 0011 16 4 128 0100 16 8 128 0101 16 16 128 0110 32M 4 256MB 260111 32M 8 256MB 261000 64M 4 512MB 261001 Notes 1 Total Number of block Locations L is 2 x 2 x 4 where R is the value in SPD byte 3 and C is the value in SPD byte 4 2 Primary Device Width is from SPD byte 13 3 Block Size 1s the total number of block locations L x 8 bytes 4 ram x siz refers to ram a siz ram b siz ram c siz etc Refer to the sections titled SDRAM Enable and Size Register Blocks A B C D and SDRAM Enable and Size Register Blocks E F G H for more information 6 Make sure the software is no longer using SDRAM and disable the block that was being used 7 Wait for at least one SDRAM refresh to complete A simple way to do this is to wait for the 32 bit counter to increment at least 100 times Refer to the section titled 32 Bit Counter for more information Note that the refdis control bit must not be set in the ECC Control Register http www motorola com computer literature 3 81 System Memory Controller SMC 8 Now that at least one refresh has occurred since SDRAM was last accessed it is okay to write to the SDRAM control registers a Program the SDRAM Speed Attributes Register using the information obtained in steps 3 and 4 and the fact that the swr dp and tdp bit
260. ransfers 2 40 offsets as part of map decoders 2 21 parity PPC60x 3 10 pipelining 3 6 transfers 3 9 addressing mode for PCI Master 2 28 to PCI Slave 2 23 addressing mode PCI Slave limits 2 24 arbiter as controlled by the XARB register 2 16 Hawk s internal 2 34 PPC 2 15 2 16 arbitration from PCI Master 2 28 latency 2 29 parking 2 37 architectural overview 2 4 ARTRY 3 11 big to little endian data swap 2 39 big endian mode 4 7 bit descriptions 3 38 bit ordering convention SMC 3 1 block diagram 1 3 2 3 Hawk SMC 3 3 Hawk used with SDRAM 3 2 block diagrams Hawk with SDRAMs 3 2 Board Last Reset Register 1 31 bridge PHB 2 1 PowerPC to PCI Local Bus Bridge 2 1 burst write bandwidth 1 1 Bus Clock Frequency 1 1 bus cycle types on the PCI bus 2 29 Bus Hog PPC master device 2 14 bus interface 60x to SMC 3 9 IN 1 lt moz Index coherency restrictions 3 11 coherency SMC 3 11 support 2 25 2 29 Cache Control Register 1 10 Cache Speed 1 10 CHRP memory 1 4 CHRP Memory Maps suggested 1 6 CLK FREQUENCY 3 44 CLK Frequency Register SMC 3 44 clock frequency 3 44 combining merging and collapsing 2 28 command types 2 23 from PCI Master 2 27 PPC slave 2 8 CONADD and CONDAT Registers 1 19 CONFIG ADDRESS Register 2 106 CONFIG DATA Register 2 109 configuration options on Hawk 3 35 registers 2 19 requirements on Hawk 3 35 type as used by PHB 2 31 configurations MVME2Ixx xxi
261. ration of the timer itself remains unaffected by this write Step 2 is to write the new programming information to the WDTXCNTL register The KEY field byte lane must be selected and must be written with PATTERN 2 for the write to take affect The effects on the WDTxCNTL register depend on the byte lanes that are written to during step 2 and are shown in Table 2 14 http www motorola com computer literature 2 43 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Table 2 14 WDTxCNTL Programming Byte Lane Selection Results KEY ENAB RELOAD WDT WDTXxCNTL Register RES 0 7 8 15 16 23 24 31 Prescaler Counter RES ENAB RELOAD Enable No No Change No Change No Change Change Yes No Update Update No Change No Change from from RES ENAB RELOAD Yes Yes No Update Update Update No Change from data from from data bus RELOAD bus Yes Yes Update Update Update No Change from data from from data bus RELOAD bus Yes Yes Yes Yes Update Update Update Update from data from data from data from bus bus bus data bus The WDTxCNTL register will always become unarmed after the second write regardless of byte lane selection Reads may be performed at any time from the WDTxCNTL register and will not affect the write arming sequence The following example displays the PPCBug commands which arm the disarm the Watchdog timer 2 2 44 Computer Grou
262. re ignored and b all reads are allowed multiple accesses to the ROM Flash device are performed for burst reads More information about ROM Flash is found in the following sections in this chapter In order to place code correctly in the ROM Flash devices address mapping information is required Table 3 3 shows how PPC60x addresses map to the ROM Flash addresses when ROM Flash is 16 bits wide Table 3 4 shows how they map when Flash is 64 bits wide http www motorola com computer literature 3 15 System Memory Controller SMC Table 3 3 PPC60x to ROM Flash 16 Bit Width Address Mapping PPC60x A0 A31 ROM Flash A22 A0 ROM Flash Device Selected XX000000 000000 Upper XX000001 000001 Upper XX000002 000002 Upper XX000003 000003 Upper XX000004 000000 Lower XX000005 000001 Lower XX000006 000002 Lower XX000007 000003 Lower XX000008 000004 Upper XX000009 000005 Upper XX00000A 000006 Upper XX00000B 000007 Upper XX00000C 000004 Lower XX00000D 000005 Lower XX00000E 000006 Lower XX00000F 000007 Lower XXFFFFF8 7FFFFC Upper XXFFFFF9 7FFFFD Upper XXFFFFFA 7FFFFE Upper XXFFFFFB 7FFFFF Upper XXFFFFFC 7FFFFC Lower XXFFFFFD 7FFFFD Lower XXFFFFFE 7FFFFE Lower XXFFFFFF 7FFFFF Lower 3 16 Computer Group Literature Center Web Site Functional Description Table 3 4 PPC60x to ROM Flash 64 Bit W
263. red changes Unmask the source This sequence ensures that the vector priority destination and mask information remain valid until all processing of pending interrupts is complete 2 64 Computer Group Literature Center Web Site Multi Processor Interrupt Controller MPIC EOI Register Each processor has a private EOI register which is used to signal the end of processing for a particular interrupt event If multiple nested interrupts are in service the EOI command terminates the interrupt service of the highest priority source Once an interrupt is acknowledged only sources of higher priority will be allowed to interrupt the processor until the EOI command is received This register should always be written with a value of zero which is the nonspecific EOI command Interrupt Acknowledge Register 8259 Mode Upon receipt of an interrupt signal the processor may read this register to retrieve the vector of the interrupt source which caused the interrupt The 8259 mode bits control the use of an external 8259 pair for PC AT compatibility Following reset this mode is set for pass through which essentially disables the advanced controller and passes an 8259 input on external interrupt source 0 directly through to processor zero During interrupt controller initialization this channel should be programmed for mixed mode in order to take advantage of the interrupt delivery modes Current Task Priority Level Each pro
264. rite cycles to write sensitive non posted locations be performed on mod 4 address boundaries The PCI Master must make the determination to perform the resolution function since it must make some decisions on possibly removing a currently pending command from the PPC FIFO There are some performance issues related to bridge lock resolution PHB offers two mechanism that allow fine tuning of the bridge lock resolution function Programmable Lock Resolution Consider the scenario where the PPC Slave is hosting a read cycle and the PCI Slave is hosting a posted write transaction If both transactions happen at roughly the same time then the PPC Slave will hold off its transaction until the PCI Slave can fill the PCI FIFO with write posted data Once this happens both slaves will be stalled and a bridge lock resolution cycle will happen The effect of this was to make the PPC Slave waste PPC bus bandwidth In addition a full PCI FIFO will cause the PCI Slave to start issuing wait states to the PCI bus 2 46 Computer Group Literature Center Web Site Functional Description From the perspective of the PCI bus a better solution would be to select a PCI FIFO threshold that will allow the bridge lock resolution cycle to happen early enough to keep the PCI FIFO from getting filled A similar case exists with regard to PCI read cycles Having the bridge lock resolution associated with a particular PCI FIFO threshold would allow the PPC M
265. rity of the CPU s with respect to each other The CPU fixed option always places the priority of CPUO over CPUI The CPU rotating option gives priority on a rotational basis between CPUO and CPUI In all cases the priority of the CPUs remains fixed with respect to the priority of HAWK and EXTL with HAWK always having the highest priority of all The PPC Arbiter supports four parking modes Parking is implemented only on the CPUs and is not implemented on either HAWK or EXTL The parking options include parking on CPUO parking on CPUI parking on the last CPU or parking disabled There are various system level debug functions provided by the PPC Arbiter The PPC Arbiter has the optional ability to flatten the PPC60x bus pipeline Flattening can be imposed uniquely on single beat reads single beat writes burst reads and burst writes It is possible to further qualify the ability to flatten based on whether there is a switch in masters or whether to flatten unconditionally for each transfer type This is a debug function only and is not intended for normal operation 2 16 Computer Group Literature Center Web Site Functional Description PPC Parity The PHB generates data parity whenever it is sourcing PPC data This happens during PPC Master write cycles and PPC Slave read cycles Valid data parity is presented when DBB is asserted for PPC Master write cycles Valid data parity is presented when TA is asserted for PPC Slave rea
266. rnally sourced interrupt input of an MPIC controller of a different device Since the MPIC specification defines external I O interrupts to operate in the distributed mode the delivery mode of this error interrupt should be consistent http www motorola com computer literature 2 55 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Timers There is a divide by eight pre scaler which is synchronized to the PCI clock The output of the pre scaler enables the decrement of the four timers The timers may be used for system timing or to generate periodic interrupts Each timer has four registers which are used for configuration and control They are Current Count Register Base Count Register Vector Priority Register a Destination Register Interrupt Delivery Modes The direct and distributed interrupt delivery modes are supported Note that the direct delivery mode has sub modes of multicast or non multicast The IPIs and Timer interrupts operate in the direct delivery mode The externally sourced or I O interrupts operate in the distributed mode In the direct delivery mode the interrupt is directed to one or both processors If it is directed to two processors i e multicast it will be delivered to two processors The interrupt is delivered to the processor when the priority of the interrupt is greater than the priority contained in the task register for that processor and when the priority of t
267. rol Bit Values from SPD Information Continued Control Bits Parameter Parameter Expressed Possible Control Bit Values in CLK Periods 0 0 lt tRP lt 2 0 FEF800D2 tRP tRP T 2 0 tRP lt 3 trp 1 bit PD Byt T CLK Period dd SED Byte E CLK Perio 3 lt tRP_CLK Ilegal trp 27 in nanoseconds See Notes 3 4 and 9 0 0 lt tRCD_CLK lt 2 tred 0 FEF800D2 tRCD tRCD CLK tRCD T 2 0 lt tRCD_CLK 3 tred 1 bit 7 SPD Byte T CLK Period tRCD_CLK Illegal trcd 29 in nanoseconds eee ega See Notes 5 6 and 9 0 0 lt tRC_CLK lt 6 0 tre 110 6 0 lt tRC lt 7 0 tre 111 7 0 lt tRC_CLK lt 8 0 tre 000 8 0 lt tRC_CLK lt 9 0 tre 001 FEF800D0 tRC tRC_CLK tRAS 9 0 tRC lt 10 0 tre 010 bits 5 6 7 SPD Bytes IET 10 0 tRC lt trc 011 trc 30 and 27 T CLK Period 110 nanoseconds See Notes 7 8 and 9 11 0 lt tRC_CLK illegal http www motorola com computer literature 3 79 System Memory Controller SMC Notes Use tRAS from the SDRAM block that has the slowest tRAS 2 tRAS_CLK is tRAS expressed in CLK periods 3 Use tRP from the SDRAM block that has the slowest tRP 4 tRP CLK is tRP expressed in CLK periods 5 Use tRCD from the SDRAM block that has the slowest tRCD 6 tRCD_CLK is tRCD expressed in CLK periods 7 Use tRC from the
268. rrupt Assis Metis ette aerae dba 4 3 Table Emor and Hand IE aote tee 4 6 Table A 1 Motorola Computer Group Documents eene 1 Table A 2 Manufacturers icio ch ice A 2 xviii Table A 3 Related Specifications 4 Table Bel VPD Packet Types conciernen oere ERU Ib IR B 4 Table B 2 MCG Product Configuration Options Data esee B 7 Table B 3 FLASH Memory Configuration Data iiec B 9 Table B A L2 Cache Contisurabonm Data tbe ri B 10 VPD Revision DEus decus ese anon AR o B 12 xix About This Manual The MVMES100 Single Board Computer Programmer s Guide provides the information you will need to program and configure your MVME5100 Single Board Computer It provides specific programming information and data applicable to this board This guide provides programming information and other data applicable to the MVME5100 As an added convienience it also provides details of the chip set Hawk programming functions It is important to note that much of the board s programming functionality is associated with the Hawk ASIC Additional programming information can also be found in the following manuals refer t
269. rrupted the following occurs A warning is displayed in the startup banner The firmware ignores the VPD contents and attempts to acquire information from other sources Q Some device drivers will not work Some diagnostic tests fail The board runs much slower than usual How to Fix Corrupted VPD Information The firmware is designed to reach the prompt with bad Use the srom ibm or update command to fix the VPD What if Your Board Has the Wrong VPD If for some reason your board has the wrong VPD information the following occurs a No warning is displayed a The firmware believes the incorrect VPD information The board may hang during startup no start condition a The board may be very unstable if it reaches the prompt Device drivers diagnostic tests and firmware commands may hang or fail in unexpected ways How to Fix Wrong VPD Problems If you suspect that your board has problems as a result of wrong VPD information perform the following http www motorola com computer literature B 3 MVMES100 VPD Reference Information Press the abort switch during startup double button reset reset abort to enter the safe mode at this point the firmware will ignore all SROM contents and reset Use the srom ibm or update command to change the VPD to the correct parameters The data listed in the following tables are for general reference information It is divided
270. rsonnel using approved safety mask and gloves Do Not Substitute Parts or Modify Equipment Do not install substitute parts or perform any unauthorized modification of the equipment Contact your local Motorola representative for service and repair to ensure that all safety features are maintained Observe Warnings in Manual Warnings such as the example below precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment caution when handling testing and adjusting this equipment and its Warning components To prevent serious injury or death from dangerous voltages use extreme Flammability Motorola PWBs printed wiring boards are manufactured with a flammability rating of 94V 0 by UL recognized manufacturers Caution EMI Caution This equipment generates uses and can radiate electromagnetic energy It may cause or be susceptible to electromagnetic interference if not installed and used with adequate EMI protection Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry Caution Attention Vorsicht Danger of explosion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacture
271. rupt request pin true When me is cleared the SMC does not assert its MCHKO pin on multiple bit errors SMC never asserts its MCHKO in response to a multiple bit error detected during a scrub cycle The Hawk s internal error interrupt and the MCHKO pin are the only non polled notification that a multiple bit error has occurred The SMC does Caution not assert as a result of a multiple bit error In fact the SMC does not a TEA_ signal pin and it assumes that the system does not implement TEA 3 48 Computer Group Literature Center Web Site Programming Model Error Logger Register Address FEF80030 Bit Name 0 Ojo uoso 1 9 Sc 9c 0 Le ve 20 8 6c 0 0 0 1025 ez SBE COUNT Operation 40596 v d u r9 5 2 S 0 5 TZ 45 81 12 959 f 61 READ ONLY READ WRITE Reset d0 9 H Td 0 VH oP dO e escb esen embt When set elog indicates that a single or a multiple bit error has been logged by the SMC If elog is set by a multiple bit error then no more errors will be logged until software clears it If elog is set by a single bit error then no more single bit errors will be logged until software clears it however if elog is set by a
272. s of two 32 pin devices that can be populated with 1MB of FLASH memory Only 8 bit writes are supported for this bank Bank A has 4 16 bit Smart Voltage FLASH SMT devices With the 16 Mbit FLASH devices the FLASH size is SMB With 32 Mbit FLASH devices the FLASH size is 16MB Only 32 bit writes are supported for this bank of FLASH There is a jumper to tell the Hawk ASIC where to fetch the reset vector When the jumper is installed the Hawk ASIC maps Oxfff00100 to these sockets Bank B Flash memory characteristics are fully compatible with those specified further on in this programmer s guide for Flash Blocks A and B Computer Group Literature Center Web Site System Bus ECC Memory The on board and optional memory mezzanines allow a variety of memory size options i e memory size can be 32MB 64MB 128MB 256MB or 512MB for a total of up to IGB of planar and mezzanine ECC memory The SDRAM memory is controlled by the Hawk ASIC which provides single bit error correction and double digit error detection ECC is calculated over 72 bits Refer to the Hawk portion of this manual Chapters 2 and 3 for additional programming information Memory block size is dependent upon the SDRAM devices installed Installing five 64 Mbit 16 bit data devices provide 32MB of memory With 64 Mbit 8 bit data devices each block consists of 9 devices that total 64MB per block With 128 Mbit 8 bit data devices a block can be populated for 128MB
273. s E F G H Enable the block and make sure that the other seven blocks are disabled Refer to the same sections as referenced in the previous step Setthe block s size control bits Start with the largest possible 512 Refer to the same sections as referenced in the previous step Wait for at least one SDRAM refresh to complete Write a unique 64 bit data pattern to each one of a specified list of addresses The list of addresses to be written varies depending on the size that is currently being checked The address lists are shown in the table below Read back all of the addresses that have been written If all of the addresses still contain exactly what was written then the block s size has been found It is the size for which it is currently programmed If any of the addresses do not contain exactly what was written then the block s memory size is less than that for which it is programmed Sizing needs to continue for this block by programming its control bits to the next smaller size waiting for at least one refresh to complete and repeating steps e and f If no match is found for any size then the block is unpopulated and has a size of OMB Its size should be programmed to 0 Computer Group Literature Center Web Site Software Considerations Table 3 20 Address Lists for Different Block Size Checks 512MB 256MB 256MB 128MB 128MB 128MB 64Mx4 32Mx8 32Mx4 16 16 46Mx
274. s into three categories address only write and read If a command type is an address only and the address presented at the time of the command is a valid PHB address the PPC slave will respond immediately by asserting AACK The PHB will not respond to address only cycles where the address presented is not a PHB address The response of the PPC Slave to command types is listed in Table 2 1 Table 2 1 PPC Slave Response Command Types PPC Transfer Type bend Transaction Clean Block 00000 Addr Only Flush Block 00100 Addr Only SYNC 01000 Addr Only Kill Block 01100 Addr Only EIEIO 10000 Addr Only 2 8 Computer Group Literature Center Web Site Functional Description Table 2 1 PPC Slave Response Command Types Continued PPC Transfer Type 2 Transaction ECOWX 10100 No Response TLB Invalidate 11000 Addr Only ECIWX 11100 No Response LWARX 00001 Addr Only STWCX 00101 Addr Only TLBSYNC 01001 Addr Only ICBI 01101 Addr Only Reserved 1 01 No Response Write with flush 00010 Write Write with kill 00110 Write Read 01010 Read Read with intent to modify 01110 Read Write with flush atomic 10010 Write Reserved 10110 No Response Read atomic 11010 Read Read with intent to modify atomic 11110 Read Reserved 00011 No Response Reserved 00111 No Response Read with no intent to cache 01011 Read Reserved 01111 No Response Reserved Ixx11 No Response
275. s should be set to 175 b Program the SDRAM Base Address Register Blocks A B C D and the SDRAM Base Address Register Blocks E F G H Each block s base address should be programmed so that it is an even multiple of its size The size information was obtained in step 5 If the isa hole bit is to be set this may be a good time to do that also Refer to the Revision ID General Control Register section for more information c Program the SDRAM Enable and Size Register Blocks A B C D and the SDRAM Enable and Size Register Blocks E F G H Use the information from step 5 for this Only those blocks that exist should be enabled Also only those that exist should be programmed with a non zero size 9 Wait for at least one SDRAM refresh to complete A simple way to do this is to wait for the 32 bit counter to increment at least 100 times refer to the section on the 32 Bit Counter for more information Note that the refdis control bit must not be set in the ECC Control Register 10 SDRAM is now ready to use 3 82 Computer Group Literature Center Web Site Software Considerations Optional Method for Sizing SDRAM Generally SDRAM block sizes can be determined by using SPD information refer to the previous section on SDRAM Control Registers Initialization example Another method for accomplishing this is as follows 1 Initialize the SMC s control register bits to a known state a Clear the isa hole bit refer to the
276. scussion of the MPIC registers can be found later in this chapter It is possible to place the base address of the PPC registers at either SFEFF0000 or SFEFE0000 Having two choices for where the base registers reside allows the system designer to use two of the Hawk s PCI Host Bridges connected to one PPC60x bus Please refer to the section titled PHB Hardware Configuration for more information references to the PPC registers of PHB within this document are made with respect to the base address FEFFO000 The following conventions are used in the Hawk register charts aR Read Only field R W Read Write field S Writing a ONE to this field sets this field C Writing a ONE to this field clears this field mi mi http www motorola com computer literature 2 67 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PPC Registers The PPC register map of the PHB is shown in Table 2 16 Table 2 16 PPC Register Map for PHB Bit gt FEFF0000 ar ae om on t AN IN on v w DEVID FEFF0004 REVID FEFF0008 FEFF000C PARB FEFF0010 XPAD FEFF0014 FEFF0018 FEFF001C FEFF0020 ETEST EENAB FEFF0024 ESTAT FEFF0028 EADDR FEFF002C EATTR FEFF0030 PIACK FEFF0034 FEFF0038 FEFF003C FEFF0040 XSADDO FEFF
277. sed through a dedicated 72 bit wide 64 bits of data and 8 bits of address L2 cache port on the processor The L2 cache normally operates in copyback modes and supports system cache coherency through snooping Parity generation and http www motorola com computer literature 1 9 Product Data and Memory Maps checking may be disabled by programming Max accordingly Refer to the MPC750 or the MPC7400 RISC Microprocessor Users Manual and Chapter 3 of this manual for more information on programming cache L2 Cache SRAM Size The L2 cache port will support SRAM configurations of IMB or 2MB The L2 cache size is defined by reading the Vital Product Data VPD SROM and programming the L2SIZ bits in the processor s Cache Control Register L2CR Cache Speed The MPC7400 and the MPC750 cache port provides the clock for the synchronous SRAMs This clock is generated by dividing the processor core frequency Available core to cache dividers range from 1 to 4 in 5 steps for the MPC7400 For the MPC750 the core to cache dividers range from 1 to 3 in 5 steps The core to cache ratio is selected by reading the VPD SROM and programming the L2CLK bits of the processor s Cache Control Register Refer to the MPC7400 RISC Microprocessor Users Manual or the MPC750 RISC Microprocessor Users Manual as listed in Appendix A Related Documentation for more information FLASH Memory The MVMES100 contains two banks of FLASH memory Bank B consist
278. single bit error and a multiple bit error occurs the multiple bit error will be logged and the single bit error information overwritten elog can only be set by the logging of an error and cleared by the writing of a one to itself or by power up reset escb indicates the entity that was accessing SDRAM at the last logging of a single or multiple bit error by the SMC If escb is 1 it indicates that the scrubber was accessing SDRAM If escb is 0 it indicates that the PPC60x bus master was accessing SDRAM When set esen allows errors that occur during scrubs to be logged When cleared esen does not allow errors that occur during scrubs to be logged embt is set by the logging of a multiple bit error It is cleared by the logging of a single bit error It is undefined after power up reset The syndrome code is meaningless if its embt bit is set http www motorola com computer literature 3 49 System Memory Controller SMC esbt ERR SYNDROME esblk0 esblk1 esbik2 scof SBE COUNT esbt is set by the logging of a single bit error It is cleared by the logging of a multiple bit error When the SMC logs a single bit error the syndrome code indicates which bit was in error Refer to the section on SDRAM ECC Codes ERR SYNDROME reflects the syndrome value at the last logging of an error This eight bit code indicates the position of the data error When all the bits are zero there was no error Note that if the logge
279. so enabled 2 enabled Double Bit Terminate the Terminate the This cycle is not seen on Error PPC60x bus cycle nor PPC60x bus cycle nor the PPC60x bus mally mally Do not perform the Provide miss corrected Do not perform the write write portion of the raw SDRAM data to the portion of the read mod read modify write cycle PPC60x60x bus master ify write cycle to to SDRAM SDRAM Assert Hawk s internal Assert Hawk s internal error interrupt if so Assert Hawk s internal error interrupt if so enabled error interrupt if so enabled Assert MCHKO if so enabled 2 enabled Assert MCHKO if so enabled Triple or Some of these errors are detected correctly and are treated the same as double bit errors The rest could greater show up as error or single bit error both of which are incorrect Bit Error 3 12 Computer Group Literature Center Web Site Functional Description Notes 1 No opportunity for error since no read of SDRAM occurs during a four beat write 2 The SMC asserts Hawk s internal error interrupt output upon detecting an interrupt qualified error condition The potential sources of Hawk s internal error interrupt assertion are single bit error multiple bit error and single bit error counter overflow Error Logging ECC error logging is facilitated by the SMC because of its internal latches When an error single or double bit occurs the SMC records the address and syndrome bits associa
280. ss to PCI configuration space is accomplished via the Hawk ASIC using the CONADD and CONDAT Registers The location and operation of these registers is fully described in the section titled Generating PCI Configuration Cycles in Chapter 2 The IDSEL assignments for MVMES100 are shown on the following table Table 1 7 IDSEL Mapping for PCI Devices Device PCI Number Address IDSEL Connection Field Line 050 0000 AD31 Hawk ASIC 1011 ADII PCI ISA Bridge on IPMC761 1100 AD12 Not used 1101 AD13 Universe VME Bridge ASIC ObO 1110 AD14 Ethernet Device Port Front Panel 051 0000 AD16 PMC Slot 1 SCSI Device on IPMC761 0b1_0001 AD17 PMC Slot 2 0b1_0011 AD19 Ethernet Device Port 2 Front Panel or P2 0b1_0100 AD20 PCI Expansion PMCspan Note AD20 connection to IDSEL is made on the PMCspan http www motorola com computer literature Product Data and Memory Maps The following table shows the current Vendor ID the Device ID and the Revision ID for each of the on board PCI devices on the MVMES100 Table 1 8 On Board PCI Device Identification Device Device Vendor ID Device ID Revision ID 5 Hawk ASIC 1057h 4803h 01h VME Universe ASIC 10E3h 0000h XXh Ethernet Intel 8086h 1209h 09h GD82559ER 1 20 Computer Group Literature Center Web Site PCI Local Bus Hawk External Register Bus Address Assignments This section wil
281. ssociated with the mapping of PPC memory space to PCI I O space The field within the XSOFF3 register is defined as follows XSOFFx PPC Slave Offset This register contains a 16 bit offset that is added to the upper 16 bits of the PPC address to determine the PCI address used for transfers from the PPC bus to PCI This offset allows PCI resources to reside at addresses that would not normally be visible from the PPC bus It is initialized to 8000 to facilitate a zero based access to PCI space http www motorola com computer literature 2 91 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller The PPC Slave Attributes Register 3 XSATT3 contains attribute information associated with the mapping of PPC memory space to PCI I O space The bits within the XSATT3 register are defined as follows REN Read Enable If set the corresponding PPC Slave is enabled for read transactions WEN Write Enable If set the corresponding PPC Slave is enabled for write transactions WPEN Write Post Enable If set write posting is enabled for the corresponding PPC Slave IOM PCI I O Mode If set the corresponding PPC Slave generates PCI I O cycles using spread addressing as defined in the section on Generating PCI Cycles When clear the corresponding PPC Slave generates PCI I O cycles using contiguous addressing WDTXxCNTL Registers Address WDTICNTL FEFF0060 WDT2CNTL FEFF0068 P Sf in Gad cd el doen
282. ster Address FEFF0004 Bit 1 1 1 1 1 pay 1111 1 2 2 2 272 2 2 2 2 2 313 0 1 2 3 4 5 6 718 9 OF 1 2 3 4 5617 8 9 0 1 2 30 4 5 6 7 8 9 OF 1 Name REVID Operation R R R R Reset 00 01 00 00 REVID Revision ID This register identifies the PHB revision level This register is duplicated in the PCI Configuration Registers 2 70 Computer Group Literature Center Web Site Registers General Control Status Feature Registers The General Control Status Register GCSR provides miscellaneous control and status information for the PHB The bits within the GCSR are defined as follows Address Bit EN wo N Co 0008 A Aa A OdIxX Operation Ydsd 4 d d d d d d d d d d d d d d d d d d d Reset 0 0 0 Wu H8JX 0 0 0 LE 2 PFBR XMBH Endian Select If set the PPC bus is operating in little endian mode The PPC address is modified as described in the section titled When PPC Devices are Little Endian on page 2 39 When LEND is clear the PPC bus is operating in Big E
283. sues 4 7 sources of reset 4 5 MVMES100 Block Diagram 1 3 MVMES10x VME Processor Module 1 1 N NVRAM 1 2 NVRAM RTC amp Watchdog Timer 1 27 overview 2 1 5 3 1 P2 I O modes 1 11 parity 2 29 PCI Slave 2 25 Parity checking 1 9 PC100 ECC 1 2 PCI address mapping 2 19 arbiter Hawk internal version 2 34 arbitration 4 1 Configuration Register map 2 97 contention with PPC 2 45 domain 4 9 FIFO 2 26 FIFO as used with PCI Slave 2 22 functions of Master 2 26 Interface features 2 1 http www motorola com computer literature IN 5 lt moz xXmoz Index Master Command Codes 2 27 Master explained 2 4 purpose of interface 2 19 registers 2 07 slave 2 22 Slave disconnect scenarios 2 24 slave response command types 2 23 Slave with PCI Master 2 26 speculative requests 2 47 spread I O address translation 2 31 to MPC address decoding 2 20 to MPC address translation 2 21 write posting 2 26 PCI VME Memory Map 1 7 PCI Arbitration Assignments for Hawk ASI 1 15 PCI bus 1 8 PCI Command Status Registers 2 99 PCI Configuration Space 1 19 PCI Expansion Connector 1 2 PCI expansion slot arbiter 1 15 PCI Host Bridge 1 2 PCIInterrupt Acknowledge Register 2 87 PCI Local Bus 1 15 PCI Slave Address 0 1 2 and 3 Registers 2 103 PCI Slave Attribute Offset 0 1 2 and 3 Registers 2 104 PCI PMC Expansion 1 2 PCIX slot 1 17 performance SMC 3 6 Peripheral Support 1 2 PHB 2 1 address mapping 2 6 Configurat
284. t Events A processor is guaranteed never to have an in service interrupt preempted by an equal or lower priority source An interrupt is considered to be in service from the time its vector is returned during an interrupt acknowledge cycle until an EOI End of Interrupt is received for that interrupt The EOI cycle indicates the end of processing for the highest priority in service interrupt Spurious Vector Generation Under certain circumstances the MPIC will not have a valid vector to return to the processor during an interrupt acknowledge cycle In these cases the spurious vector from the spurious vector register will be returned The following cases would cause a spurious vector fetch INT is asserted in response to an externally sourced interrupt which is activated with level sensitive logic and the asserted level is negated before the interrupt is acknowledged INT is asserted for an interrupt source which is masked using the mask bit in the Vector Priority register before the interrupt is acknowledged 2 54 Computer Group Literature Center Web Site Multi Processor Interrupt Controller MPIC Interprocessor Interrupts IPI Processors and 1 can generate interrupts which are targeted for the other or both processors There are four Interprocessor Interrupts channels The interrupts are initiated by writing a bit in the IPI dispatch registers If subsequent IPI s are initiated before the first is ack
285. t could be the type of LCD panel connected in an MPC821 based application FF N A Termination Packet follows the last initialized data N A packet Notes 1 Data size varies depending on the product configuration type 2 Integer values are formatted stored in big endian byte ordering 3 This packet may be omitted if the ethernet interface is non existent or the ethernet interface has an associative SROM e g DEC21x4x 4 This packet may contain an additional byte following the address data This additional byte indicates the ethernet interface number and is specified in applications where the host product supports multiple ethernet interfaces For each ethernet interface present the instance number is incremented by one starting with zero B 6 Computer Group Literature Center Web Site Vital Product Data VPD Introduction VPD Definitions Product Configuration Options Data The product configuration options data packet consists of a binary bit field The first bit of the first byte is bit O 1 PowerPC bit numbering option is present when the assigned bit is a one the following table further describes the product configuration options VPD data packet Table B 2 MCG Product Configuration Options Data Bit Number Bit Mnemonic Bit Description 0 PCO PCIO CONNI PCI PMC bus 0 connector 1 present 1 PCO PCIO CONN2 PCI PMC bus 0 connect
286. t in the ESTAT register will be used to assert the MCHK output to the bus master which initiated the transaction When this bit is clear MCHK will not be asserted PCI Master Received Target Abort Machine Check Enable When this bit is set the PRTA bit in the ESTAT register will be used to assert the MCHK output to the bus master which initiated the transaction When this bit is clear MCHK will not be asserted 2 80 Computer Group Literature Center Web Site Registers XBTOI XDPEI PPERI PSERI PSMAI PRTAI PPCAddress Bus Time out Interrupt Enable Whenthis bit is set the XBTO bit in the MERST register will be used to assert an interrupt through the MPIC interrupt controller When this bit is clear no interrupt will be asserted PPC Data Parity Error Interrupt Enable When this bitis set the XDPE bit in the ESTAT register will be used to assert an interrupt through the MPIC When this bit is clear no interrupt will be asserted PCIParity ErrorInterruptEnable Whenthisbitisset the PPER bit in the ESTAT register will be used to assert an interrupt through the MPIC interrupt controller When this bit is clear no interrupt will be asserted PCI System Error Interrupt Enable When this bit is set the PSER bit in the ESTAT register will be used to assert an interrupt through the MPIC interrupt controller When this bit is clear no interrupt will be asserted PCI Master Signalled Master Abort Interrupt Enab
287. t is the priority of the selected interrupt and its source identification The IS will resolve an interrupt request in two PHB clock ticks The IS also receives a second set of inputs from the ISR During the End Of Interrupt cycle these inputs are used to select which bits are to be cleared in the ISR http www motorola com computer literature 2 59 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Interrupt Request Register IRR There is a Interrupt Request Register IRR for each processor The IRR always passes the output of the IS except during Interrupt Acknowledge cycles This guarantees that the vector which is read from the Interrupt Acknowledge Register does not change due to the arrival of a higher priority interrupt The IRR also serves as a pipeline register for the two tick propagation time through the IS In Service Register ISR There is a In Service Register ISR for each processor The contents of the ISR are the priority and source of all interrupts which are in service The ISR receives a bit set command during Interrupt Acknowledge cycles and a bit clear command during End Of Interrupt cycles The ISR is implemented as a 40 bit register with individual bit set and clear functions Fifteen bits are used to store the priority level of each interrupt which is in service Twenty five bits are used to store the source identification of each interrupt which is in service Therefore there is one
288. t on the last byte in which case it should be cleared When set the master interface will be enabled for PC operations If clear reads and writes to all PC registers are still allowed but no C bus operations will be performed Address FEF800A0 Bit Sf cn sole Joo a 5 2 FPS m SIS el ed e e e qi e Ala Name B E 8 Susc mq wea Operation READ ZERO READ ZERO READ ZERO 24 24 24 Reset X X X gi gi atalala kea 12 datin This bit is set whenever the master controller has successfully received a byte of read data from an bus slave device This bit is cleared after the 12 Receiver Data Register is read i2 err This bit is set when both i2 start and 12 stop bits in the rc Control Register are set at the same time The PC master controller will then clear the contents of the IC Control 3 64 Computer Group Literature Center Web Site Programming Model i2 ackin i2 cmplt Register and further writes to the PC Control Register will not be allowed until after the IC Status Register is read A read from the C Status Register will clear this bit This bit is set if the addressed slave device is acknowledged to either a start sequence or data writes from the PC master controller and cleared otherwise The C master controller will automatically clear this bit at the beginning of the next valid PC operation This
289. t print that supports the MPC750 and MPC7400 processors The maximum external processor bus speed is 100 MHz Parity checking is supported for the system address and data busses Processor Type Identification The processor version can be determined by reading the Processor Version Register PVR The PVR version number value for the MPC750 processor is 0x0008 The processor revision level starts at 0x0100 and is updated for each silicon revision For example revision 1 of the MPC750 is 0x00080100 Revision 2 is 0x00080200 and so on Incremental revisions such as 2 1 are identified as 0x00080201 and so on For the MPC7400 the PVR version number value is 0x000C and the revision levels use the same nomenclature as the MPC750 e g 0x0100 and so on Processor PLL Configuration L2 Cache The processor internal clock frequency core frequency is a multiple of the system bus frequency The processor has four configuration pins PLL CFG 0 3 for hardware strapping of the processor core frequency between 2x and 8x the system bus frequency in 0 5 steps The PLL configuration is dynamic at power up and varies depending upon the existence of a memory mezzanine attached to the host board The 5100 SBC uses a back door L2 cache structure via the Max processor chip Max s L2 cache is implemented with an onchip 2 way set associative tag memory and external direct mapped synchronous SRAMs for data storage The external SRAMs are acces
290. ta transfer operations to occur between PCI bound transactions and PPC bound transactions The PCI FIFO is used to support PPC bound transactions while the PPC FIFO is used to support PCI bound transactions Each FIFO supports a command path and a data path The data path portion of each FIFO incorporates a multiplexer to allow selection between write data and read data as well as logic to handle the PPC PCI endian function All PPC originated PCI bound transactions utilize the PPC Slave and PCI Master functions for maintaining bus tracking and control During both write and read transactions the PPC Slave places command information into the PPC FIFO The PCI Master draws this command information from the PPC FIFO when it is ready to process the transaction During write transactions write data is captured from the PPC60x bus within the PPC Input block This data is fed into the PPC FIFO The PCI Output block removes the data from the FIFO and presents it to the PCI bus During read transactions read data is captured from the PCI bus within the PCI Input block From there the data is fed into the PPC FIFO The PPC Output block removes the data from the FIFO and presents it to the PPC60x bus 2 4 Computer Group Literature Center Web Site Functional Description PCI originated PPC bound transactions utilize the PCI Slave and PPC Master functions for maintaining bus tracking and control During both write and read transactions th
291. ted with the data in error Once the error logger has logged an error it does not log any more until the elog control status bit has been cleared by software unless the currently logged error is single bit and a new double bit error is encountered The logging of errors that occur during scrub can be enabled disabled in software Refer to the Error Logger Register section in this chapter for more information http www motorola com computer literature 3 13 System Memory Controller SMC ROM Flash Interface The SMC provides the interface for two blocks of ROM Flash Each block provides addressing and control for up to 64MB Note that no ECC error checking is provided for the ROM Flash The ROM Flash interface allows each block to be individually configured by jumpers and or by software as follows 1 Access for each block is controlled by three software programmable control register bits an overall enable a write enable and a reset vector enable The overall enable controls normal read accesses The write enable is used to program Flash devices The reset vector enable controls whether the block is also enabled at SFFF00000 SFFFFFFFF The overall enable and write enable bits are always cleared at reset The reset vector enable bit is cleared or set at reset depending on external jumper configuration This allows the board designer to use external jumpers to enable disable Block A B ROM Flash as the source of reset vectors
292. ter does not generate fast back to back transactions Arbitration Latency Because a bulk of the transactions are limited to single beat transfers on PCI the PCI Master does not implement a Master Latency Timer Exclusive Access The PCI Master 1s not able to initiate exclusive access transactions Address Data Stepping The PCI Master does not participate in the Address Data Stepping protocol Parity The PCI Master supports address parity generation data parity generation and data parity error detection Cache Support The PCI Master does not participate in the PCI caching protocol Generating PCI Cycles There are four basic types of bus cycles that can be generated on the PCI bus Memory and Configuration Special Cycle Interrupt Acknowledge http www motorola com computer literature 2 29 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Generating PCI Memory and I O Cycles Each programmable slave may be configured to generate PCI I O or memory accesses through the MEM and IOM fields in its XSATTx register as shown below MEM IOM PCI Cycle Type 1 X Memory 0 0 Contiguous I O 0 1 Spread If the bit is set the PHB performs Memory addressing on the PCI bus The PHB takes the PPC bus address applies the offset specified in the XSOFFx register and maps the result directly to the PCI bus The IBM CHRP specification describes two approaches for
293. terface Double bit error detect Single bit error correct on 72 bit basis Two blocks with up to 256MB each at 100 MHz Eight blocks with up to 256MB each at 66 67 MHz Uses 8 10 or PC100 SDRAMs Programmable base address for each block Built in Refresh Scrub Error Notification for SDRAM Software programmable Interrupt on Single Double Bit Error Error address and Syndrome Log Registers for Error Logging Does not provide on Double Bit Error Chip has no TEA pin 3 1 System Memory Controller SMC ROM Flash Interface Two blocks with each block being 16 or 64 bits wide Programmable access time on a per block basis PC master interface External status control register support Block Diagrams Figure 3 1 depicts a Hawk as it would be connected with SDRAMs in a system Figure 3 2 shows the SMC s internal data paths Figure 3 3 shows the overall SDRAM connections Figure 3 4 shows a block diagram of the SMC portion of the Hawk ASIC PowerPC Data 04 Bits PowerPC Data Parity 8 Bits PPC60x Bus PowerPC Address Parity 4 bits Figure 3 1 Hawk Used with Synchronous DRAM a System 3 2 Computer Group Literature Center Web Site Block Diagrams Latched D 64 Bits 64 Bits 8 5 o o o 8 5 8 hr a gt o 8 Bits g m to 8 Uncorrected Data 64 Bits 2
294. terface The SMC has a PowerPC slave interface only It has no PowerPC master interface The slave interface is the mechanism for all accesses to SDRAM ROM Flash and the internal and external register sets Responding to Address Transfers When the SMC detects an address transfer that it is to respond to it asserts AACK immediately if there is no uncompleted PPC60x bus data transfer in process If there is one in process then the SMC waits and asserts coincident with the uncompleted data transfer s last data beat if the SMC is the slave for the previous data If it is not it holds off AACK_ until the CLK after the previous data transfer s last data beat Completing Data Transfers If an address transfer to the SMC will have an associated data transfer the SMC begins a read or write cycle to the accessed entity SDRAM ROM Flash Internal or External Register as soon as the entity is free If the data transfer will be a read the SMC begins providing data to the PPC60x bus as soon as the entity has data ready and the PPC60x data bus is granted If the data transfer will be a write the SMC begins latching data from the PowerPC data bus as soon as any previously latched data is no longer needed and the PPC60x data bus is available http www motorola com computer literature 3 9 System Memory Controller SMC PPC60x Data Parity The Hawk has 8 DP pins for generating and checking PPC60x data bus parity During rea
295. termined by the TIE mode Additionally if priorities are set the same for competing interrupts external int 0 is given the highest priority in hardware followed by external interrupt 1 through 15 and then followed by timer 0 through timer 3 and followed by IPI 0 and 1 For example if both ext0 and ext1 interrupts are pending with the same assigned priority during the following interrupt acknowledge cycles the first vector returned shall be that of extO and then ext1 This is an arbitrary choice Block Diagram Description The description of the MPIC block diagram shown in Figure 2 9 focuses on the theory of operation for the interrupt delivery logic http www motorola com computer literature 2 57 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Int signals Program Visible Y Registers IPR Interrupt Interrupt Selector 1 Selector 0 IRR 1 IRR 0 Y Y ISR 1 ISR 0 c p 8 Y Y Interrupt Router gt INT I WA b INT 0 Figure 2 9 MPIC Block Diagram 2 58 Computer Group Literature Center Web Site Multi Processor Interrupt Controller MPIC Program Visible Registers These are the registers that software can access They are described in detail in the MPIC Registers section Interrupt Pending Register IPR The interrupt signals to MPIC are qualified
296. ternal interrupt is serviced a m An external interrupt occurs The processor state is saved in the machine status save restore registers A new value is loaded into the Machine State Register MSR The External Interrupt Enable bit in the new MSR MSRee is set to zero Control is transferred to the O S external interrupt handler The external interrupt handler calculates the address of the Interrupt Acknowledge register for this processor MPIC Base Address 0x200A0 processor ID shifted left 12 bits The external interrupt handler issues an Interrupt Acknowledge request to read the interrupt vector from the Hawk s MPIC If the interrupt vector indicates the interrupt source is the 8259 the interrupt handler issues a second Interrupt Acknowledge request to read the interrupt vector from the 8259 The Hawk s MPIC does not interact with the vector fetch from the 8259 The interrupt handler saves the processor state and other interrupt specific information in system memory and re enables for external interrupts the MSRee bit is set to 1 MPIC blocks interrupts from sources with equal or lower priority until an End of Interrupt is received for that interrupt source Interrupts from higher priority interrupt sources continue to be enabled If the interrupt source is the 8259 the interrupt handler issues an EOI request to the MPIC This resets the In Service bit for the 8259 within the MPIC and allows it to recognize higher
297. tes that the signal is true or valid when the signal is low An asterisk following a signal name for signals that are edge significant denotes that the actions initiated by that signal occur on high to low transition In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used independently of the voltage level high or low that they represent Data and address sizes are defined as follows Byte 8 bits numbered 0 through 7 with bit 0 being the least significant Half word 16 bits numbered 0 through 15 with bit 0 being the least significant Word 32 bits numbered 0 through 31 with bit 0 being the least significant Double word 64 bits numbered 0 through 63 with bit 0 being the least significant xxvii xxviii Product Data and Memory Maps Introduction The 5100 is a state of the art Single Board Computer It incorporates Motorola s PowerPlus II architecture with a choice of PowerPC processors either Motorola s MPC7400 with AltiVec technology for algorithmic intensive computations or the low power 750 The 5100 incorporates a highly optimized PCI interface and memory controller enabling up to 582MB s memory read bandwidth and 640MB s burst write bandwidth
298. the resulting vector information obtained from the PCI bus as read data PCI Arbiter The Hawk s internal PCI arbiter supports up to 8 PCI masters This includes Hawk and 7 other external PCI masters The arbiter can be configured to be enabled or disabled at reset time by strapping the rd 9 bit either high for enabled or low for disabled Table 2 9 describes the pins and its function for both modes Table 2 9 PCI Arbiter Pin Description Pin Name Pin Reset Internal Arbiter External Arbiter Type Direction Function Direction Function PARBIO Input Input extreqd_ input HAWKgnt PARBII Input Input extreql Input NA PARBI2 Input Input ext req2_ Input NA PARBI3 Input Input ext req3 _ Input NA PARBIA Input Input ext req4 Input NA PARBIS5 Input Input extreq5 Input NA PARBI6 Input Input ext req6 Input NA PARBOO Output Tristate Output ext _ Output HAWK req PARBOI Output Tristate Output ext gntl Output NA PARBO2 Output Tristate Output ext gnt2 Output NA Output Tristate Output ext gnt3_ Output NA 4 Output Tristate Output ext gnt4_ Output NA PARBOS Output Tristate Output ext gnt5 __ Output NA PARBOG Output Tristate Output ext gnt6 Output NA 2 34 Computer Group Literature Center Web Site Functional Description The Hawk s PCI arbiter has various programming options It s
299. this document Motorola Inc assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to the Motorola Computer Group website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Limited and Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Motorola Inc Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial
300. ting this bit to one inhibits counting for this timer Setting this bit to zero allows counting to proceed BC BASE COUNT This field contains the 31 bit count for this timer When a value is written into this register and the CI bit transitions from a 1 to a 0 it is copied into the corresponding Current Count register and the toggle bit in the Current Count register is cleared When the timer counts down to zero the Current Count register is reloaded from the Base Count register and the timer s interrupt becomes pending in MPIC processing 2 120 Computer Group Literature Center Web Site Registers Timer Vector Priority Registers Offset Timer 0 01120 Timer 1 01160 Timer 2 011A0 Timer 3 011E0 Bit Name UJ ON 1 N aN N AN 2 1212 2 I 1 1 IJ I I1 1 I 1 I 3 2 1 0 9 8 7 6F 5 4 3 2 1 O 9 877 6 5 4 3 2 1 0 TIMER VECTOR PRIORITY PRIOR VECTOR Operation R W R R W Reset T MA ASYN 000 0 00 00 MASK ACT PRIOR VECTOR MASK Setting this bit disables any further interrupts from this source If the mask bit is cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated ACTIVITY The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to a one when its associated bit in the Interrupt Pendi
301. tion 16 double words long would make the data FIFO the limiting factor for write posting Four single beat transactions would make the command FIFO be the limiting factor If either limit is exceeded then any pending PCI transactions are delayed TRDY is not asserted until PPC Master has completed a portion of the previously posted transactions and created some room within the command and or data FIFOs The PCI Master in conjunction with the capabilities of the PPC Slave attempts to move data in either single beat or four beat burst transactions The PCI Master supports 32 bit and 64 bit transactions in the following manner All PPC60x single beat transactions regardless of the byte count are subdivided into one or two 32 bit transfers depending on the alignment and the size of the transaction This includes single beat 8 byte transactions All PPC60x burst transactions are transferred in 64 bit mode if the PCI bus has 64 bit mode enabled If at any time during the transaction the PCI target indicates it can not support 64 bit mode the PCI Master continues to transfer the remaining data within that transaction in 32 bit mode The PCI Master can support Critical Word First CWF burst transfers The PCI Master divides this transaction into two parts The first part starts on the address presented with the CWF transfer request and continues up to the end of the current cache line The second transfer starts at the beginnin
302. to accesses in its designated range except that it responds to the address of this tben register When the en bit is set the L2CLM input pin becomes the TBEN output pin and it tracks the value on p1 tben When pl tben is 0 the TBEN pin is low and when p1 tben is 1 the TBEN pin is high http www motorola com computer literature 3 73 System Memory Controller SMC When the en bit is cleared 1 tben has no effect on any pin pO tben When the tben en bit is set the ERCS output pin becomes the TBEN output pin and it tracks the value on 0 When pO tben is 0 the TBEN pin is low and when p1 is 1 the TBEN pin is high When the en bit is cleared 0 tben has no effect on any pin Note that when enishigh L2CLM_ cannot be driven by an external L2 cache controller and no External Register Set devices can be controlled Software Considerations This section contains information that will be useful in programming a system that uses the Hawk Programming ROM Flash Devices Those who program devices to be controlled by the Hawk should make note of the address mapping that is shown in Table 3 3 and in Table 3 4 For example when using 8 bit devices the code will be split so that every other 4 byte segment goes in each device Writing to the Control Registers Software should not change control register bits that affect SDRAM operation
303. to reserved registers will be treated as no ops That is the access will be completed normally on the bus and the data will be discarded Read accesses to reserved or unimplemented registers will be completed normally and a data value of 0 will be returned The PCI Configuration Register map of the PHB is shown in Table 2 17 The PCI I O Register map of the PHB is shown in Table 2 18 Table 2 17 PCI Configuration Register 3 3 2 2 2 2 2 2 2 27 272 11 1098765432109 7 65 3431 2109576542210 DEVID VENID 500 STATUS COMMAND 04 CLASS REVID 08 HEADER 0 10 MMBAR 14 18 7C PSADDO 580 PSOFFO PSATTO 84 PSADDI 88 PSOFFI PSATTI 8C PSADD2 90 PSOFF2 PSATT2 94 PSADD3 98 PSOFF3 PSATT3 9 http www motorola com computer literature 2 97 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Table 2 18 PCI I O Register 3 3 2 2 21 2 2 2 2 2 2 2 1 1 11 111 11 1 zm 1 0l 9 8 71 6 5 4 3 2 1 ol 9 8 7 6 5 4 3 2 1 ol 9 8 7 6 5 4 3l 2110 CONFIG ADDRESS CFS CONFIG_DATA CFC Vendor ID Device ID Registers Offset 00 Bit 3 3 2 2 2 2 2 202 2 2 2 1 1 1 I 1 1 1 1 1 1 10987654 32 109 8 7 65 4 3 2 1 0 9 817 6 54 32 1 0 Name DEVID VENID Operation R R Reset 4803 1057 VENID Vendor ID This r
304. ugh the PC interface of the Hawk ASIC Computer Group Literature Center Web Site PCI Local Bus PCI Local Bus There are eight potential PCI bus masters on the MVMES510x a a Hawk ASIC MPU PCI bus bridge controller Intel GD82559ER Ethernet controller Port 1 Intel GD82559ER Ethernet controller Port 2 Universe II ASIC PCI VME bus bridge controller PMC Slot 1 SCSI device on IPMC761 in PMC Slot 1 PIB device on IPMC761 in PMC Slot 1 PMC Slot 2 PCI mezzanine card PCI Expansion Slot PCI Arbitration Assignments for Hawk ASIC The PCI arbitration is performed by the Hawk ASIC which supports seven external PCI masters in addition to itself Details on PCI arbitration can be found futher on in this chapter PCI Arbitration Assignments for Hawk ASIC The arbitration assignments for the MVME510x are shown in the following table Table 1 6 PCI Arbitration Assignments PCI Bus Request PCI Master s Request 0 PARBIO Universe ASIC VMEbus PARBIO Request 1 PARBII PMC Slot 1 SCSI device on IPMC761 in PMC Slot 1 Request 2 PARBI2 PIB device on IPMC761 in PMC Slot 1 http www motorola com computer literature 1 15 Product Data and Memory Maps Table 1 6 PCI Arbitration Assignments Continued PCI Bus Request Request 3 PARBI3 PCI Master s PMC Slot 2 Request 4 PARBIA PCIX Slot PCI Expansion via PMCSPAN Request 5 PARBI5 Ethernet Port 1
305. upports 3 different priority schemes fixed round robin and mixed mode It also allows various levels of reprioritization programming options within fixed and mixed modes Parking can be programmed to any of the requestors the last requestor or none A special bit is added to hold grant asserted for an agent that initiates a lock cycle Once a lock cycle is detected the grant is held asserted until the PCILOCK pin is released This feature works only when the bit is enabled The priority scheme can be programmed by writing the field in the PCI Arbiter control register The default setting for priority scheme is fixed mode The Fixed mode holds each requestor at a fixed level in its hierarchy The levels of priority for each requestor are programmable by writing the HEIR field in the PCI Arbiter control register Table 2 10 describes all available settings for the HEIR field in fixed mode Table 2 10 Fixed Mode Priority Level Setting HEIR Priority Levels Setting Highest Lowest 000 PARB6 5 PARB4 PARB3 PARB2 PARBI PARBO HAWK 001 HAWK PARB6 PARBS PARB4 PARB3 PARB2 PARBO 010 PARBO HAWK 6 5 PARB4 PARB3 PARB2 PARBI 011 PARBO HAWK PARB6 PARBS PARBA PARB3 PARB2 100 PARB2 PARBO HAWK PARB6 PARBS PARB4 PARB3 101 PARB3 PARB2 PARBO HAWK PARB6 5
306. uration Hawk has the ability to perform custom hardware configuration to accommodate different system requirements The PHB has several functions that may be optionally enabled or disabled using passive hardware external to Hawk The selection process occurs at the first rising http www motorola com computer literature 2 49 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller edge of CLK after RST has been released of the sampled pins are cascaded with several layers of registers to eliminate problems with hold time Table 2 15 summarizes the hardware configuration options that relate to the PHB Table 2 15 PHB Hardware Configuration Function Sample Pin s Sampled Meaning State PCI 64 bit Enable REQ64 0 64 bit PCI Bus 1 32 bit PCI Bus PPC Register Base RD 5 0 Register Base FEFF0000 1 Register Base FEFE0000 MPIC Interrupt Type RD 7 0 Parallel Interrupts 1 Serial Interrupts PPC Arbiter Mode RD 8 0 Disabled 1 Enabled PCI Arbiter Mode RD 9 0 Disabled 1 Enabled PPC PCI Clock Ratio RD 10 12 000 Reserved 100 1 1 010 2 1 110 3 1 001 3 2 101 Reserved 011 5 2 111 Reserved 2 50 Computer Group Literature Center Web Site Multi Processor Interrupt Controller MPIC Multi Processor Interrupt Controller MPIC The MPIC is a multi processor structured intelligent interrupt controller MPIC Features MPIC programmin
307. ve Address Register 3 XSADD3 contains address information associated with the mapping of PPC memory space to PCI I O space XSADD3 in conjunction with XSOFF3 XSATT3 is the only register group that can be used to initiate access to the PCI CONFIG ADDRESS 80000CF8 and DATA 80000CFC registers The power up value of XSADD3 and XSOFF3 XSATT3 are set to allow access to these special register spaces without PPC register initialization 2 90 Computer Group Literature Center Web Site Registers The fields within XSADD3 are defined as follows START Start Address This field determines the start address of a particular memory area on the PPC bus which will be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming PPC address END End Address This field determines the end address of a particular memory area on the PPC bus which will be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming PPC address PPC Slave Offset Attribute 3 Registers Address XSOFF3 XSATT3 FEFFOOSC Bit gt zz p z ga E gt mm gx gre Reset Regbase Oxfeff0000 8000 Regbase Oxfefe0000 7000 1 1 0 0 0 0 0 0 Slave Offset Register 3 XSOFF3 contains offset information a
308. while SDRAM is being accessed Because of pipelining software should always make sure that the two accesses before and after the updating of critical bits are not SDRAM accesses A possible scenario for trouble would be to execute code out of SDRAM while updating the critical SDRAM control register bits The preferred method is to be executing code out of ROM Flash and avoiding SDRAM accesses while updating these bits Computer Group Literature Center Web Site Software Considerations Some registers have additional requirements for writing For more information refer to the register sections in this chapter titled SDRAM Enable and Size Register Blocks A B C D SDRAM Base Address Register Blocks A B C D SDRAM Enable and Size Register Blocks E F G H SDRAM Base Address Register Blocks E F G H and SDRAM Speed Attributes Register Since software has no way of controlling refresh scrub accesses to SDRAM the hardware is designed so that updating control bits coincidentally with refreshes is not a problem As with SDRAM control bits software should not change control bits that affect ROM Flash while the affected Block is being accessed This generally means that the ROM Flash size base address enable write enable etc are changed only while executing initially in the reset vector area SFFF00000 FFFFFFFF Initializing SDRAM Related Control Registers In order to establish proper SDRAM operation software must configure
309. wk ASIC controls use the 60x clock SMC can be configured to operate at several different 60x clock frequencies using SDRAMs that have various speed characteristics The bits that control this configuration are located in the SDRAM Speed Attributes Register which is described in the Register portion of this section Refer to Table 3 1 for some specific timing numbers Table 3 1 60x Bus to SDRAM Estimated Access Timing at 100 MHz with PC100 SDRAMs CAS latency of 2 Access Type Access Time Comments 4 Beat Read after idle 10 1 1 1 SDRAM Bank Inactive 4 Beat Read after idle 12 1 1 1 SDRAM Bank Active Page Miss 4 Beat Read after idle 7 1 1 1 SDRAM Bank Active Page Hit 4 Beat Read after 4 Beat Read 5 1 1 1 SDRAM Bank Active Page Miss 4 Beat Read after 4 Beat Read 2 5 1 1 1 2 5 1 1 1 is an average of 2 SDRAM Bank Active Page Hit 1 1 1 half of the time and 3 1 1 1 the other half 4 Beat Write after idle 4 1 1 1 SDRAM Bank Active or Inactive 4 Beat Write after 4 Beat Write 6 1 1 1 SDRAM Bank Active Page Miss http www motorola com computer literature 3 7 System Memory Controller SMC Table 3 1 60x Bus to SDRAM Estimated Access Timing at 100 MHz with PC100 SDRAMs CAS latency of 2 Continued SDRAM Bank Active Page Hit Access Type Access Time Comments 4 Beat Write after 4 Beat Write 3 1 1 1 3 1 1 1 for the second burst SDRAM Ba
310. y intervention by host CPU transactions Caution should be exercised when using this mode since the over generosity of bus ownership to the PPC Master can be detrimental to the host CPU s performance The Bus Hog mode can be controlled by the XMBH bit within the GCSR The default state for XMBH is disabled 2 14 Computer Group Literature Center Web Site Functional Description PPC Arbiter The PHB has an internal PPC60x bus arbiter The use of this arbiter is optional If the internal arbiter is disabled then the PHB must be allowed to participate an externally implemented PPC60x arbitration mechanism The selection of either internal or external PPC arbitration mode is made by sampling an RD line at the release of reset Refer to the section titled PHB Hardware Configuration in this chapter for more information The PHB has been designed to accommodate up to four PPC60x bus masters including itself HAWK two processors CPU0 CPU1 and external PPC60x master EXTL EXTL can be a L2 cache a second bridge chip etc When the PPC Arbiter is disabled PHB generates an external request and listen for an external grant for itself It also listens to the other external grants to determine the PPC60x master identification field XID within the GCSR When the PPC Arbiter is enabled the PHB receives requests and issue grants for itself and for the other three bus masters The XID field is determined by the PPC Arbiter The PPC60x ar
311. y then read the data by polling the I C Receiver Data Register http www motorola com computer literature 3 31 System Memory Controller SMC As long as the slave device receives an acknowledge it will continue to increment the word address and serially clock out sequential data words The PC sequential read operation is terminated when the PC master controller does not respond with an acknowledge This can be accomplished by setting only the i2 enbl bit in the PC Control Register before receiving the last data word A stop sequence then must be transmitted to the slave device by first setting the 12 stop and 12 enbl bits in the C Control Register and then writing a dummy data data don t care to the C Transmitter Data Register The Status Register must now be polled to test i2 cmplt bit for the operation complete status The stop sequence will relinquish the ASIC master s possession of the PC bus Figure 3 9 shows the suggested software flow diagram for programming the PC sequential read operation Computer Group Literature Center Web Site Functional Description SDA DEVICE ADDR WORD ADDR 1 DEVICE ADDR DATA 1 M w A A M R A START S R 5 5 K K B BEGIN READ STATUS REG i LOAD 09 STA

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