µPD720112 - Renesas Electronics
Contents
1. A Downstream Hub Delay with Cable B Downstream Hub Delay without Cable Downstream Port of Hub Crossover Point Vss __ Upstream Port Crossover or End of Cable tiom Vs toa yA C Upstream Hub Delay with or without Cable Upstream end of cable Upstream port Downstream port Function Downstream signaling Upstream signaling D Measurement Points Hub Differential Jitter tHDJ1 tHDDx J or tHoox J Consecutive Transitions tHDDx J tuppx J or Paired Transitions Bit after SOP Width Distortion same as data jitter for SOP and next J transition trsoP tuppx next J tHppx SOP Low speed timings are determined in the same way for tLHDD tLbJH2 tLuHJ1 tLUJH2 and tLsoP 24 Data Sheet 16616EJ3VODS NEC Upstream End of Cable Ves Downstream Port of Hub 50 Point of Initial Swing 720112 Figure 2 14 Hub EOP Delay and Skew Upstream Crossover Port of Hub Point Extended Ou LJ Vss m Downstream PortofHub PFr 4F A Downstream EOP Delay with Cable B Downstream EOP Delay without Cable d Downstream oo Port of Hub d Extended Vss b Upstream Port Crossover Or Point End of Cable Extend2. Indicates the current that can flow into an output pin in the low level state without raising the output voltage above the specified VoL High level output current 2 3 Electrical Specifications Absolute Maximum Ratings Parameter Power supply voltage Indicates the current that can flow out of an output pin in the high level state without reducing the output voltage below the specified Vou A negative current indicates current flowing out of the pin Condition Input output voltage 2 5 V input output voltage 3 3 V input output voltage 5 V input out voltage 2 3 V lt Vos lt 2 7 V Vi Vo lt 25 0 9 V 3 0 V 3 6 V Vi Vo lt 1 0 V 3 0 V 3 6 V Vi Vo lt 3 0 V Output current lo 3 mA 10 lo 6 mA 20 lo 12 mA 40 Operating temperature 0 to 70 Storage temperature 65 to 150 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation
3. NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction If the input of the CMOS device stays in the area between MAX and MIN due to noise etc the device may malfunction Take care to prevent chattering noise from entering the device when the input level is fixed and also the transition period when the input level passes through the area between MAX and Vin MIN HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction If an input pin is unconnected it is possible that an internal input level may be generated due to noise etc causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using pull up or pull down circuitry Each unused pin should be connected to or GND via a resistor if there is a possibility that it will be an output pin All handling related to unused pins must be judged separately for each device and according to related specifications governing the device PRECAUTION AGAINST ESD A strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it when it has occurred Environmental control must be adequat
4. Pin Name Pin Name Pin Name NEC 720112 Pin Name O aINI Vss 25 PPB4 N CSB3 7 TEST PPB3 A SCAN MODE CSB2 a BUS_SELF PPB2 x LPWRM CSB1 EXROM EN PPB1 SCL SYSRSTB lt SDA GANG_B VBUSM N Vss Remark AVss R should be used to connect RREF through 1 precision reference resistor 2 43 Data Sheet S16616EJ3VODS NEC 1 PIN INFORMATION Pin Name X1_CLK Buffer Type 2 5 V input 720112 Function Crystal oscillator in or clock input X2 2 5 V output Oscillator out SYSRSTB 5 V tolerant Schmitt input Asynchronous chip reset RPU USB pull up control External 1 5 pull up resistor control DP 4 1 USB D signal I O USB s downstream facing port D signal DM 4 1 USB D signal I O USB s downstream facing port D signal DPU USB D signal I O USB s upstream facing port D signal DMU USB D signal I O USB s upstream facing port D signal BUS SELF 3 3 V Schmitt input Power mode select LPWRM 3 3 V Schmitt input Local power monitor RREF Analog Reference resistor CSB 4 1 5 V tolerant input Port s over current status input PPB 4 1 5 V t
5. V low level output current Vo 0 4 V 5 0 V low level output current Vo 0 4 V High level output current 3 3 V high level output current 2 4 V 3 3 V high level output current 2 4 V 5 0 V high level output current 2 4 Input leakage current 3 3 V buffer or Vss 5 0 V buffer or Vss Note The output short circuit time is measured at one second or less and is tested with only one pin on the LSI Data Sheet 16616EJ3VODS 11 NEC uPD720112 USB Interface Block Parameter Conditions Output pin impedance ZHSDRV Includes Rs resistor Bus pull up resistor on upstream facing Bus pull up resistor on downstream Rep facing port Termination voltage for upstream facing port pullup full speed Input Levels for Low full speed High level input voltage drive High level input voltage floating Low level input voltage Differential input sensitivity D D Differential common mode range Includes range Output Levels for Low full speed High level output voltage Ri of 14 25 to GND Low level output voltage of 1 425 to 3 6 V SE1 Output signal crossover point voltage Input Levels for High speed High speed squelch detection threshold Vussa differential signal High speed disconnect detection Vuspsc threshold differential s
6. buffer PPB 4 1 LED4 LED3 LED1 e USB2 0 interface RPU DPU DMU DP 4 1 DM 4 1 RREF Above 5 V refers to a 3 V input buffer that is 5 V tolerant has 5 V maximum input voltage Therefore it is possible to have a 5 V connection for an external bus Data Sheet S16616EJ3VODS 7 NEC uPD720112 2 2 Terminology Terms Used in Absolute Maximum Ratings Parameter Meaning Power supply voltage Indicates voltage range within which damage or reduced reliability will not result when power is applied to a pin Input voltage Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin Output voltage Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin Output current Indicates absolute tolerance values for DC current to prevent damage or reduced reliability when current flows out of or into an output pin Operating temperature Indicates the ambient temperature range for normal logic operations Storage temperature Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device Terms Used in Recommended Operating Range Parameter Meaning Power supply voltage Indicates the voltage range for normal logic operations to occur when Vss 0 V High level input voltage Indicates t
7. certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Elect
8. 720112 System Clock Ratings Parameter Condition Clock frequency X tal Oscillator block Clock Duty cycle Remarks 1 Recommended accuracy of clock frequency is 100 ppm 2 Required accuracy of X tal or oscillator block is including initial frequency accuracy the spread of X tal capacitor loading supply voltage temperature and aging etc AC Characteristics VDD 3 14 to 3 46 V TA 0 to 70 C System Reset Timing Figure 2 6 System Reset Timing trst SYSRSTB 16 Data Sheet 16616EJ3VODS NEC uPD720112 Over current Response Timing Over current response time from CSB toc 500 625 Ls low to PPB high Figure 2 7 Figure 2 7 Over current Response Timing CSB 4 1 PPB 4 1 Figure 2 8 CSB PPB Timing 500us 500 us 500us 500 us meja e Hub power supply TT Up port D line PPB pin output Yo VEE LA Output cut off OSB pin input Port power ion Overcurrent supply ON inrush current generation Bus power Up port connection CSB detection CSB active Self power Power supply ON delay time period Remark The active period of the CSB pin is in effect only when the PPB pin is ON There is a delay time of approximately 500 ws duration at the CSB pin Data Sheet S16616EJ3VODS 17 NEC uPD720112 External Serial ROM Timing Parameter Condition Cl
9. 80 Mbps full speed 12 Mbps and low speed 1 5 Mbps transaction Endpoint 0 controller Endpoint 1 controller Manages hub s synchronization by using micro SOF which is received at upstream port and generates SOF packet when full low speed device is attached to downstream facing port Full low speed repeater is enabled when the 4 PD720112 are worked at full speed mode Oscillator Block Interface block for external Serial ROM which contains user defined descriptors Serializer and Deserializer Serial Interface Engine SIE controls USB2 0 and 1 1 protocol sequencer Upstream Transceiver supports high speed 480 Mbps full speed 12 Mbps transaction Upstream Port Controller handles Suspend and Resume Data Sheet S16616EJ3VODS NEC PIN CONFIGURATION TOP VIEW 80 pin plastic TQFP Fine pitch 12 x 12 uPD720112GK 9EU 4PD720112GK 9EU A ag X 2998028892024 OOOOOOOOOOOOO 25 Vss TEST SCAN_MODE BUS SELF LPWRM EXROM EN SCL SDA GANG B Vss lt 7 OOOOOOOOOOOOOOOOOOOO Vss Voos PPB4 OO T 2m lt LED4 GREEN LED3 LED2 LED1 CSB4 CSB3 PPB3 4 Data Sheet S16616EJ3VODS DP2 CSB2 O PPB2 O DM2 O Vss CSB1 SYSRSTB O DM1 VBUSM 720112 NEC
10. Data Sheet S16616EJ3VODS 9 NEC uPD720112 Recommended Operating Ranges Parameter Condition Operating voltage 3 3 V for pins 2 5 V for pins 2 5 V for AVpp pins High level input voltage 2 5 V High level input voltage 3 3 V High level input voltage 5 0 V High level input voltage Low level input voltage 2 5 V Low level input voltage 3 3 V Low level input voltage 5 0 V Low level input voltage Hysteresis voltage 5 V Hysteresis voltage 3 3 V Hysteresis voltage Input rise time for SYSRSTB Input rise time Normal buffer Schmitt buffer Input fall time Normal buffer Schmitt buffer Two power supply rails limitation The 720112 has two power supply rails 2 5 V 3 3 V The uPD720112 requires that Vpp25 should be stable before Vpp33 becomes stable The system will require the time when power supply rail is stable at level And there will be difference between the time of 25 and Vpp33 At any case the system must ensure that the absolute maximum ratings for Vi Vo not exceeded System reset signaling should be asserted more than specified time after both Vpp2s and Vppss are stable 10 Data Sheet S16616EJ3VODS NEC uPD720112 DC Characteristics Parameter Condition Off state output leakage current Vppss Vpp2s or Vss Output short circuit current Low level output current 3 3 V low level output current 0 4 V 3 3
11. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 5 5 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is g
12. am facing port facing port UP PHY SERDES uec rs CDR AA DP 1 _PHY 1 Downstream facing port 1 9 EUH ee upstream facing port 4 DP 2 PHY External l To Hub Function Serial ROM upstream facing port lt gt DP 3 PHY Hub Function Downstream facing 3 upstream facing port APLL DP 4 PHY _ Downstream facing port 4 9 Hub Function upstream facing port X1_CLK X2 gt OSB A 7 950 L p Hdd 2 Data Sheet S16616EJ3VODS NEC APLL ALL_TT CDR DPC DP n _PHY EPO EP1 F_TIM Frame Timer FS_REP OSB ROM I F SERDES SIE_2H UP_PHY UPC 720112 Generates all clocks of Hub Translates the high speed transactions split transactions for full low speed device to fulllow speed transactions TT buffers the data transfer from either upstream or downstream direction For OUT transaction ALL_TT buffers data from upstream port and sends it out to the downstream facing ports after speed conversion from high speed to full low speed For IN transaction ALL_TT buffers data from downstream ports and sends it out to the upstream facing ports after speed conversion from full low speed to high speed Data amp clock recovery circuit Downstream Port Controller handles Port Reset Enable Disable Suspend and Resume Downstream transceiver supports high speed 4
13. but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers off
14. d and low speed transaction on downstream facing ports when Hub controller is working in high speed mode e One Transaction Translator per Hub and supports four non periodic buffers e Supports self powered and bus powered mode e Supports Over current detection and Individual or ganged power control e Supports configurable vendor ID product ID string descriptors and others with external Serial ROM e Supports non removable attribution on individual port e Uses 30 MHz X tal or clock input e Supports downstream port status with LED e 2 5 V and 3 3 V power supplies The information in this document is subject to change without notice Before using this document please confirm that this is the latest version Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information Document No 16616EJ3V0DS00 3rd edition Date Published March 2005 NS CP N Printed in Japan The mark shows major revised points NEC Electronics Corporation 2003 NEC uPD720112 ORDERING INFORMATION Part Number Package Remark uPD720112GK 9EU 80 pin plastic TQFP Fine pitch 12 x 12 uPD720112GK 9EU A 80 pin plastic TQFP Fine pitch 12 x 12 Lead free product BLOCK DIAGRAM To Host Hub downstream 9 Upstre
15. e When it is dry a humidifier should be used It is recommended to avoid using insulators that easily build up static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON devices with reset functions have not yet been initialized Hence power on does not guarantee output pin levels I O settings or contents of registers A device is not initialized until the reset signal is received A reset operation must be executed immediately after power on for devices with reset functions 5 POWER ON OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface as a rule switch on the external power supply after switching on the internal power supply When switching the power supply off as a rule switch off the external power supply and then the internal power supply Use of the reverse power on off sequences may result in the application of an overvoltage to the internal elements of t
16. e 2 18 Duration of driving resume to a DRSMDN downstream port only from a controlling hub Time from detecting downstream resume to rebroadcast Duration of driving reset to a downstream Only for a SetPortFeature facing port Figure 2 20 PORT RESET request Time to detect a long K from upstream turLk Time to detect a long SEO from upstream tuRL sEO Duration of repeating SEO upstream for tuRPsEO low full speed repeater Inter packet delay for high speed of tHsiPDsD packets traveling in same direction Inter packet delay for high speed of tHsiPDoD packets traveling in opposite direction Inter packet delay for device root hub tHsRsPIPD1 response with detachable cable for high speed Time of which a Chirp J or Chirp K must be continuously detected filtered by hub or device during Reset handshake Time after end of device Chirp K by which hub must start driving first Chirp K in the hub s chirp sequence Time for which each individual Chirp J or Chirp in the chirp sequence is driven downstream by hub during reset Time before end of reset by which a hub tocHsEo must end its downstream chirp sequence Time from internal power good to device tSIGATT pulling D beyond Vinz Figure 2 20 Debounce interval provided by USB system software after attach Figure 2 20 Maximum duration of suspend averaging tsusavel interval Period of idle bus bef
17. ed C Upstream EOP Delay with or without Cable EOP Delay tFEOPD tHDDx tEoPy means that this equation applies to teoP and EOP Skew tFHESK tEOP Low speed timings are determined in the same way for tLEoPp and tLHESK Data Sheet S16616EJ3VODS 25 NEC Figure 2 15 USB Differential Data Jitter for Low full speed PERIOD Differential Data Lines Crossover Points oe Consecutive Transitions x tPERIOD Paired Transitions N x tPERIOD 2 720112 Figure 2 16 USB Differential to EOP Transition Skew and EOP Width for Low full speed H Differential Data Lines Figure 2 17 USB Receiver Jitter Tolerance for Low full speed tPERIOD Differential je Data Lines 26 E Crossover P nd Point Diff Data to SEO Skew x tPERIOD Crossover Point Extended Consecutive Transitions N x tPERIOD bunt Paired m Transitions N x tPERIOD txuR2 Data Sheet S16616EJ3VODS a Source EOP Width treort Receiver EOP Width treorr tLEOPR NEC uPD720112 Figure 2 18 Low full speed Disconnect Detection D D min Vit Vss lt topis Device Disconnect Disconnected D
18. etected Figure 2 19 Full high speed Device Connect Detection D e rt Se erecta D Vss Device Connect Connected Detected Figure 2 20 Power on and Connection Events Timing time Hub port power on an a en 10857 USB system software reads device speed Attatch detected Reset recovery power Veus min D or D Eo OE tRSTRCY Data Sheet S16616EJ3VODS 27 NEC 3 PACKAGE DRAWING 80 PIN PLASTIC TQFP FINE PITCH 12x12 28 NOTE Each lead centerline is located within 0 08 mm of its true position at maximum material condition Data Sheet S16616EJ3VODS 720112 detail of lead end r A A2 Y A3 64 i Lp A1 UNIT mm ITEM DIMENSIONS D 12 00 0 20 E 12 00 0 20 A2 1 00 HD 14 00 0 20 14 00 0 20 A 1 10 0 10 A1 0 10 0 05 0 25 Lp 0 605015 b 0 22 0 05 c 0 50 0 08 0 08 ZD 1 5 ZE 125 L 0 50 L1 1 00 0 20 K80GK 50 9EU NEC uPD720112 4 RECOMMENDED SOLDERING CONDITIONS The PD720112 should be solde
19. he device causing malfunction and degradation of internal elements due to the passage of an abnormal current The correct power on off sequence must be judged separately for each device and according to related specifications governing the device INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I O pull up power supply while the device is not powered The current injection that results from input of such a signal or I O pull up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device Data Sheet S16616EJ3VODS 31 NEC uPD720112 USB logo is a trademark of USB Implementers Forum Inc The information in this document is current as of March 2005 The information is subject to change without notice For actual design in refer to the latest publications of NEC Electronics data sheets or data books etc for the most up to date specifications of NEC Electronics products Not all products and or types are available in every country Please check with an NEC Electronics sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics NEC Electronics assumes no re
20. he voltage applied to the input pins of the device which indicates the high level state for normal operation of the input buffer f a voltage that is equal to or greater than the MIN value is applied the input voltage is guaranteed as high level voltage Low level input voltage Indicates the voltage applied to the input pins of the device which indicates the low level state for normal operation of the input buffer f a voltage that is equal to or less than the MAX value is applied the input voltage is guaranteed as low level voltage Hysteresis voltage Indicates the differential between the positive trigger voltage and the negative trigger voltage Input rise time i Indicates allowable input signal transition time from 0 1 x Voo to 0 9 x Input fall time i Indicates allowable input signal transition time from 0 9 x Voo to 0 1 x 8 Data Sheet S16616EJ3VODS NEC Terms Used in DC Characteristics Parameter Off state output leakage current 720112 Meaning Indicates the current that flows into a 3 state output pin when it is in a high impedance state and a voltage is applied to the pin Output short circuit current Indicates the current that flows from an output pin when it is shorted to GND while it is at high level Input leakage current Indicates the current that flows into an input pin when a voltage is applied to the pin Low level output current
21. ice equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under
22. ignal High speed data signaling common mode voltage range High speed differential input signaling See Figure 2 4 levels Output Levels for High speed High speed idle state Vusoi High speed data signaling high VHsoH High speed data signaling low VHsoL Chirp J level different signal VCHIRPJ Chirp K level different signal VcHIRPK 12 Data Sheet 16616EJ3VODS NEC uPD720112 Figure 2 1 Differential Input Sensitivity Range for Low full speed Differential Input Voltage Range Differential Output Crossover Voltage Range dO eee 00 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30 32 Input Voltage Range Volts Figure 2 2 Full speed Buffer Characteristics for High speed Capable Transceiver 3 3 Vpp 2 8 2 3 Vpp 1 8 1 3 0 8 0 3 0 20 40 lout mA 60 80 Vout Figure 2 3 Full speed Buffer Characteristics for High speed Capable Transceiver 80 60 40 lout MA 20 Vout V Data Sheet S16616EJ3VODS 13 720112 NEC Figure 2 4 Receiver Sensitivity for Transceiver at DP DM 400 mV Differential Level 1 OV Differential Point 1 400 mV Differential Unit Interval 100 0 Figure 2 5 Receiver Measurement Fixtures Test Supply Voltage High Speed Differential Osc
23. illoscope or 50 Q Outputs of a High Speed Differential Data Generator To 50 Q Inputs of a 500 Coax 500 Coax 1580 AAA o a gt m z 59806 020 2825 gt 143 0 Data Sheet S16616EJ3VODS 14 NEC Power Consumption Parameter Power Consumption Condition The power consumption under the state without suspend All the ports do not connect to any function Hub controller is operating at full speed mode Hub controller is operating at high speed mode 720112 The power consumption under the state without suspend The number of active ports is 2 Hub controller is operating at full speed mode Hub controller is operating at high speed mode The power consumption under the state without suspend The number of active ports is 3 Hub controller is operating at full speed mode Hub controller is operating at high speed mode The power consumption under the state without suspend The number of active ports is 4 Hub controller is operating at full speed mode Hub controller is operating at high speed mode The power consumption under suspend state The internal clock is stopped Note When any device is not connected to all the ports the power consumption does not depend on the number of active ports Data Sheet S16616EJ3VODS 15 NEC uPD
24. nics willingness to support a given application Note 1 NEC Electronics as used in this statement means NEC Electronics Corporation and also includes its majority owned subsidiaries 2 NEC Electronics products means any product developed or manufactured by or for NEC Electronics as defined above M8E 02 11 1
25. ock frequency Clock pulse width low Clock pulse width high Clock low to data out valid Time the bus must be free before a new transmission can start Start hold time tHD sTA Start setup time tsu sTa Data in hold time tHD DTA Data in setup time tsu DTA Stop setup time tsu sro Data out hold time toH Write cycle time Figure 2 9 External Serial ROM Bus Timing SCL 0 5 THD DAT SDA Output taa a BUF SDA Input Figure 2 10 External Serial ROM Write Cycle Timing Word m twR Stop Start condition condition 18 Data Sheet S16616EJ3VODS NEC uPD720112 USB Interface Block 1 4 Parameter Conditions Low speed Electrical Characteristics Rise time 10 to 90 Ci 200 pF to 600 pF 75 Fall time 90 to 10 r Ci 200 pF to 600 pF 75 Differential rise and fall time matching tiRFM tir tr Note 80 Low speed data rate tLDRATHS Average bit rate 1 49925 Downstream facing port source jitter total including frequency tolerance Figure 2 15 To next transition For paired transitions Downstream facing port differential receiver jitter total including frequency tolerance Figure 2 17 To next transition For paired transitions tuur2 Source SEO interval of EOP Figure 2 16 tleopT Receiver SEO interval of EOP Figure 2 16 tleo
26. olerant N ch open drain Port s power supply control output VBUSM 5 V tolerant Schmitt input Vsus monitor SCL 3 3 V output External serial ROM clock out SDA GANG_B 3 3 V Schmitt I O External serial ROM data IO or power management mode select EXROM EN 3 3 V Schmitt input External serial ROM input enable AMBER 5 V tolerant output Amber colored LED control output GREEN 5 V tolerant output Green colored LED control output LED 4 1 5 V tolerant output LED indicator output for downstream port status TEST 3 3 V input Test signal SCAN_MODE 3 3 V input Test signal 3 3 25 2 5 AVDD 2 5 V Voo for analog circuit Vss Vss for analog circuit Vss for reference resistor Connect to AVss Remark 5 V tolerant means that the buffer is 3 V buffer with 5 V tolerant circuit Data Sheet S16616EJ3VODS NEC uPD720112 2 ELECTRICAL SPECIFICATIONS 2 4 Buffer List e 2 5V Oscillator interface X1_CLK X2 e 5V Schmitt input buffer SYSRSTB CSB 4 1 VBUSM e 3 3 V Schmitt input buffer BUS_SELF LPWRM e 3 3 V input buffer EXROM_EN TEST SCAN_MODE e 3 3 V lot 3 bi directional Schmitt input buffer with input enable OR type SDA GANG 3 3 V loL 3 mA output buffer SCL e 5V lo 12 mA output buffer AMBER GREEN LED2 e 5V lo 12 N ch open drain
27. ore device can initiate resume Duration of driving resume upstream torsmuP Data Sheet 16616EJ3VODS 21 NEC uPD720112 4 4 Parameter Conditions Hub Event Timings Continued Resume recovery time tRsmMRcY Remote wakeup is enabled Time to detect a reset from upstream for DETRST non high speed capable devices Reset recovery time Figure 2 20 trsTRCY Inter packet delay for full speed tipp Inter packet delay for device response with trspipp1 detachable cable for full speed SetAddress completion time tosETADDR Time to complete standard request with no tbRaCMPLTND data Time to deliver first and subsequent tDRETDATA1 except last data for standard request Time to deliver last data for standard toRETDATAN request Time for which a suspended hub will see a triLTSEO continuous SEO on upstream before beginning the high speed detection handshake Time a hub operating in non suspended twrRsTFS full speed will wait after start of SEO on upstream before beginning the high speed detection handshake Time a hub operating in high speed will wait after start of SEO on upstream before reverting to full speed Time a hub will wait after reverting to full twrRsTHS speed before sampling the bus state on upstream and beginning the high speed will wait after start of SEO on upstream before reverting to full speed Minimum duration of a Chirp K on upstream f
28. ource SEO interval of EOP Figure 2 16 Receiver SEO interval of EOP Figure 2 16 treopr Width of SEO interval during differential trsr transition Hub differential data delay Figure 2 13 with cable without cable Hub differential driver jitter including cable Figure 2 13 To next transition For paired transitions Data bit width distortion after SOP Figure 2 13 Hub EOP delay relative to Figure trEoPD 2 14 Hub EOP output width skew Figure 2 14 High speed Electrical Characteristics Rise time 1096 to 9096 tHsR Fall time 90 to 10 tusr Driver waveform See Figure High speed data rate tHsDRAT 479 760 480 240 Microframe interval tHsFRAM 124 9375 125 0625 Consecutive microframe interval difference tHSRFI 4 high speed Data source jitter See Figure 2 11 Receiver jitter tolerance See Figure 2 4 Hub data delay without cable tHsHDD 36 high speed 4 ns Hub data jitter See Figure 2 4 Figure 2 11 Hub delay variation range tHsHDv 5 high speed Note Excluding the first transition from the Idle state 20 Data Sheet 16616EJ3VODS NEC uPD720112 3 4 Parameter Conditions Hub Event Timings Time to detect a downstream facing port connect event Figure 2 19 Awake hub Suspended hub Time to detect a disconnect event at a hub s downstream facing port Figur
29. pr Width of SEO interval during differential transition Hub differential data delay Figure 2 13 Hub differential driver jitter including cable Figure 2 13 Downstream facing port To next transition For paired transitions 2 Upstream facing port To next transition For paired transitions tluHv2 Data bit width distortion after SOP Figure 50 2 13 EOP delay relative to Figure 1 2 14 Hub EOP output width skew Figure 2 14 Full speed Electrical Characteristics Rise time 10 to 90 C 50 pF 20 Rs 36 0 Fall time 90 to 10 Ci 50 pF 20 Rs 36 0 Differential rise and fall time matching trRFM 90 111 11 Full speed data rate trDRATHS Average bit rate 11 9940 12 0060 Frame interval FRAME 0 9995 1 0005 Note Excluding the first transition from the Idle state Data Sheet S16616EJ3VODS 19 NEC uPD720112 2 4 Parameter Conditions Full speed Electrical Characteristics Continued Consecutive frame interval jitter tnri No clock adjustment Source jitter total including frequency Note tolerance Figure 2 15 To next transition For paired transitions tpu2 Source jitter for differential transition to SEO transition Figure 2 16 Receiver jitter Figure 2 17 To Next Transition For Paired Transitions tur2 S
30. ranted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document
31. red and mounted under the following recommended conditions For soldering methods and conditions other than those recommended below contact an NEC Electronics sales representative For technical information see the following website Semiconductor Device Mount Manual http www necel com pkg en mount index html PD720112GK 9EU 80 pin plastic TQFP Fine pitch 12 x 12 Soldering Method Soldering Conditions Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or higher IR35 103 3 Count Three times or less Exposure limit days after that prebake at 125 C for 10 hours Partial heating Pin temperature 300 C max Time 3 seconds max per pin row Note After opening the dry pack store it at 25 C or less and 65 RH or less for the allowable storage period PD720112GK 9EU A 80 pin plastic TQFP Fine pitch 12 x 12 Lead free product Soldering Method Soldering Conditions Infrared reflow Package peak temperature 250 C Time 60 seconds max at 220 C or higher IR50 103 2 Count Two times or less Exposure limit 3 days after that prebake at 125 C for 10 hours Partial heating Pin temperature 300 C max Time 3 seconds max per pin row Note After opening the dry pack store it at 25 C or less and 65 RH or less for the allowable storage period Data Sheet S16616EJ3VODS 29 NEC uPD720112 MEMO 30 Data Sheet 16616EJ3VODS NEC uPD720112
32. rom a hub within the reset protocol Time after start of SEO on upstream by tucHEND which a hub will complete its Chirp K within the reset protocol Time between detection of downstream chip and entering high speed state Time after end of upstream Chirp at which hub reverts to full speed default state if no downstream Chirp is detected 22 Data Sheet 16616EJ3VODS NEC uPD720112 Figure 2 11 Transmit Waveform for Transceiver at DP DM Level 1 400 mV Differential EET EP d OV Differential 400 mV Level 2 Differential Unit Interval 0 100 Figure 2 12 Transmitter Measurement Fixtures T Test Supply Voltage 15 80 USB Veus 30 To 50 Inputs of a Connector pe Coax High Speed Differential Nearest D Oscilloscope or 50 Q i 15 8 Q Outputs of a High Speed D 500 d TAN Coax Differential Data Generator Sun Data Sheet S16616EJ3VODS 23 NEC uPD720112 Timing Diagram Figure 2 13 Hub Differential Delay Differential Jitter and SOP Distortion Upstream Crossover Cable 50 Point of Tn _ Initial Swing 50 Point of Hub Delay Downstream Hub Delay Downstream Initial Swing Port of Hub m Downstream Port of Hub Downstream AY VSS
33. ronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics DATA SHEET 5 5 MOS INTEGRATED CIRCUIT uPD720112 USB 2 0 HUB CONTROLLER The 2 0720112 is a USB 2 0 hub device that complies with the Universal Serial Bus USB Specification Revision 2 0 and works up to 480 Mbps USB 2 0 compliant transceivers are integrated for upstream and all downstream ports PD720112 works backward compatible either when any one of the downstream ports is connected to a USB 1 1 compliant device or when the upstream port is connected to a USB 1 1 compliant host Detailed function descriptions are provided in the following user s manual Be sure to read the manual before designing 720112 User s Manual S16617E FEATURES e Compliant with Universal Serial Bus Specification Revision 2 0 Data Rate 1 5 12 480 Mbps e Certified by USB implementers forum and granted the USB 2 0 high speed Logo e High speed or full speed packet protocol sequencer for Endpoint 0 1 e 4 Max downstream facing ports e All downstream facing ports can handle high speed 480 Mbps full speed 12 Mbps and low speed 1 5 Mbps transaction e Supports split transaction to handle full spee
34. sponsibility for any errors that may appear in this document e NEC Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Electronics or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of a customer s equipment shall be done under the full responsibility of the customer NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure fea
35. tures NEC Electronics products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to NEC Electronics products developed based on a customer designated quality assurance program for a specific application The recommended applications of an NEC Electronics product depend on its quality grade as indicated below Customers must check the quality grade of each NEC Electronics product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC Electronics products is Standard unless otherwise expressly specified in NEC Electronics data sheets or data books etc If customers wish to use NEC Electronics products in applications not intended by NEC Electronics they must contact an NEC Electronics sales representative in advance to determine NEC Electro
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