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DRM035 - Freescale Semiconductor

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1. Motorola Inc c Copyright 2001 Motorola Inc ALL RIGHTS RESERVED kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk FILE NAME scicomm h DESCRIPTION A header file for scicomm c MODULES INCLUDED None ifndef SCICOMM H define SCICOMM H S EE KK K k k KR KR k k RR RRR KK KR k k k k k k k k k k k k RR k k KK k k k k k RR RR RR k k k k KK INCLUDES x S EE KK K k KR RR k k RR RR RK KK kk k k k k k k k k ck ck ck kckckckckckckckckckckckckckck ck k k RR ck kc k k ck ck k k k ck ck ck ck kk include types h BRR RR K k RRR RRR RR RK KK RR k k k k k k k k k k k k k k k k k k k KK KK k k k RR RRR RR k k ck ck ck ck k k PROTOTYPES S EE KK K K k RK k k RR RR RK KK k k k k k k k k k k k k RR RK RK KR k k RR RR RR k k k k RK KK void scicommTxEmpISR void void scicommRxErrISR void void scicommRxFullISR void endif C 1
2. Module void scicommRxFullISR void Description This function is the ISR of the SCI Rx Full It reads the new data save them to the pl RxFromSCI buffer There are two way how this SCI Receive could be finished either it fills up the whole pl RxFromSCI buffer or communication Timeout generated by Timeout Tmr TmrD3 occurs Returns None Global Data pl Flags flag pl FlgModeOfModem if the Mode was set to STATE1 SCI reception could be started the SCI Rx is started and mode is switched to STATE2 SCI reception in progress When SCI Rx is finished the mode is set to STATE3 SCI reception has been finished The codeSCItoPL prepares the data for PL Tx packet and mode is set to STATEA PL transmission could be started pl RxFromSCI a buffer of SCI reception For the global data description of the codeSCItoPL routine see the description of the routine itself FRAME HEADER a symbolic constant descriing the header value of packet over the transmission is NOT performed Arguments None Range Issues Only when pl FlgModeOfModem is equal to STATE1 or STATE2 the SCI reception is performed
3. asm void slidAverage Wordl6 Si Word16 lambi Word16 f r2 Si yO lambi yl f move x r2 x0 x0 Si mpy y0 x0 a a lambi Si add 32768 y0 yO 1 lambi macr yl y0 a move a x r2 store result rts BRR RR KR RRR RR RR RR RK kk kk kk kckckckckckckck ck ck kckckckckckckck ck ckckckckck ck ck RR ck ck ck ck ck RR RR RK KK Module UWord16 numOnes UWord32 tempVar Description Function returns the number of ones in lower 24 bits of parameter tempVar Returns Number of ones in lower 24 bits of parameter tempVar Global Data None Arguments tempVar variable where to calculate Range Issues none Special Issues none KR KR RK KR KR KR RK KK RR RK RRR OR k k k k k k k k k k k k k k k k k k ck ck ck k k ck k k kk UWord16 numOnes UWord32 tempVar asm A tempVar YO result clr b elr yo clr yl do 24 END asr a adc y b END move bo y0 DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 127 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files C 8 demfsk h BRR RRR KR KR KR RR KR RRR kk kk Sk kk kk kckckckckckckckck ck kckckckckckck ck ckckckck ck c
4. void codePLtoSCI void Designer Reference Manual DRM035 Rev 0 134 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files coderoutines c UWordl6 i temp deintrleave demfsk MSGBuf pl RxFromPL Array Byte FRAME TOTALLEN PL FECTYPE do the complete deinterleaving of the demfsk MSGBuf for i 0 i lt FRAME TOTALLEN i align the RxFromPl buffer if PL FECTYPE PL 1STFEC if 1st method of FEC coding pl RxFromPL Array Byte i 2 elif PL FECTYPE PL NOFEC if NO FEC coding pl RxFromPL Array Byte i 8 endif if NO FEC correction type is set do nothing because Data in a buffer are in a non coded form Hif PL FECTYPE PL 1STFEC if 1st method of FEC coding chosen for i 0 i lt FRAME TOTALLEN i FEC Decoder temp FECtableDecoder pl RxFromPL Array Byte i amp Ox3F80 gt gt 7 pl RxFromPL Array Byte i temp lt lt 4 FECtableDecoder pl RxFromPL Array Byte i amp 0x007F endif ifdef PL TEACRYPT decrypt the Rx buffer teaDecryptBuff pl RxFromPL Array Byte FRAME TOTALLEN endif if pl RxFromPL Struct Cntrl gt 1 amp amp if length is OK pl RxFromPL Struct Cntrl
5. PROTOTYPES BR RRR k k KR k RR RRR RK KK kk KK RR k k KK KKK k k k RR RR k k k k RK asm Wordl6 calcDTFT Wordl6 pCoeff asm void slidAverage Wordl6 Si Word16 lambi Word16 f UWord16 numOnes UWord32 tempVar BR RR RK KR RR k k RR RR KK KK kk kk k k k k k k k ck ck ck kckckckckckckckckckckckckckck ck ck RR ck ck ck k k ck ck ck ck ck k GLOBAL VARIABLES BR KK K K k RR k k RR RR RK KK kk KK RR RK KK KK RRR ck ck ckck k k k k k k k k k k k ck ck ck ck k k k ck ck ck k volatile Wordl6 demfsk NewFrmCounter used as a counter in ADCEndOfScanISR UWord32 demfsk MSGBuf DEMFSK MSGBUFLEN buffer of received message of FSK demodulation routine extern volatile pl sFlags pl Flags contains the state and another flags of PL modem device BRR RR K k KR RK RR RRR kk kk KK kk kk kc kckckckckck ck ck ck kckckckckckckckckckckckckckck ck ck k k k k k k k k k k k k k k ck ck ck k k ck ck ck ck kk LOOK UP TABLE GLOBAL VARIABLES S EE RRR KR k k k k k RR RR kk kk k k KR kk k k k k k k k ck ck ck k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ck ck ck ck ckck ck ck ck ck k extern const Wordl6 K100 2 DEMFSK FRAMELEN FSK demodulator const of 100kHz extern const Wordl6 K105 2 DEMFSK FRAMELEN FSK demodulator const of 105kHz extern const Wordl6 K110 2 DEMFSK FRAME
6. Module void plProjectInit void Description This function initializes the core peripherals static configuration is taken from the appconfig h file generated by config tool Note that some core peripheral parameters depend on the global defines situated in pl h file It initialises global variables as well Returns None Global Data pl Flags flag pl FlgModeOfModem is set to STATE O No operation flag pl FlgDataError is cleared For the global data description of the demfskInit routine see the description of the routine itself i PL COPINUSE is a symbolic constant it defined the Watch Dog is used DSP56F803 is a symbolic constant if defined the 56F803 core is used DSP56F801 is a symbolic constant if defined the 56F801 core is used PL PLBAUDRATE is a symbolic constant which controls the PL x communication speed PL CARRIERLOW is a symbolic constant which controls the frequecy of one of PL carrier PL TIMEOUTVALUE is a symbolic constant which controls the time out value of TimeOut timer TmrD3 DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 95 For More Information On This Product Go to www freescale com Source Code Files PL SCIBAUDRATE is a symbolic constant which controls the SCI communicat Arguments None t Ro X o Range Issue
7. Interrupt vectors definition Example of interrupt vector definition extern void userISRFunction void prototype of the ISR must be placed in your code DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 163 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files define INT VECTOR ADDR yy userlISRFunction define ITCN INT PRIORITY yy value 0 7 0 disabled 1 lowest interrupt priority 7 highest interrupt priority where yy is interrupt vector number s Default components initialization values HR KK KR KR RK KR RK k kk kckckckckckckckckckckckckckckckckckckckckckck ck k k k k k k k k k k k k k k k k k k k k k ck ck ck ck kk Example of initialization values definition for GPIO define GPIO x PERIPHERAL ENABLE REG 0x0000 define GPIO x DA
8. FILE NAME CRCtable c DESCRIPTION This file contains table of the 16bit CRC codes Linker command file locates this file either into the XFlash data memory area 56F801 source or FLASH target in 56F803 source or to internal RAM data memory area RAM target in 56F803 source MODULES INCLUDED None Ro FF FF OR FF FF F FF X HF F HR RR KK KK RR a KK k k A RRR RRR RR RRR RR RR RK ck ck KK BR RRR K k k RR RR RR RR KK RK k k k k k k k k k k k k KK KKK k k RR RRR RR ck ck k k ck ck ck ck RK INCLUDES BRR RR k k RR k k RR RR RK KK kk KK RR k k KK KKK k k k RRR RR k k k k ck ck k k include types h S EE RR KR K k RR KR RR RRR KK KK KR RK RR KK k k k k k k RRR RR ck ck ck ck KK CRC Constants Look up table located at XFlash or XRAM data memory area BR RR K k RRR k k RRR RR KK k k KR KK KK RRR k k k k k k k k k k k ck k k ck ck k k ck ck ck ck KK CRC Berechnung und Implementierungstips Dies ist nicht der richtige Ort um die Theorie der zyklischen Redundanz berpr fung cyclic redundancy check CRC zu erl utern Hierzu sei auf die Arbeit von Michael R hner DC40X 2 verwiesen Dieser Abschnitt schildert nur die f r eine Implementierung notwendigen Details Als Pr fpolynom wird das CRC16 Polynom verwendet Dieses hat die Gestalt 16 15 2 DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 149 For More Information On This Produc
9. Motorola Inc c Copyright 2001 Motorola Inc ALL RIGHTS RESERVED 4 x kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk FILE NAME scicomm c DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 137 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files DESCRIPTION This file consists of all SCI based routines needed for the PL modem such as SCI Rx Full ISR and SCI Tx Empty ISR MODULES INCLUDED ScicommRxErrISR i ScicommRxFullISR ScicommTxEmpISR HR KR KK KR KK RR A KK KKK RK KKK RR ck ck k k k k k k k k k k k k k k k k k k k k k ck ck ck kk SEE KK K k k k k k k RR RRR RK k k kk k k k k k k k k k k k ck ck ck kckckckckckckckckckckckckckck ck ck k k k k k kk kk k k k k k ck k k k k ck ck ck ck k k INCLUDES r S EE RR KR KR KR RR k k RR kk kk Sk KK kk k k k k k k k k ck ck ck ck k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ck ck ck k k ck ck ck ck kk include types h include arch h include periph h include appconfig h include sci h include gpio h include scicomm h include tmrfsk h include demfsk h include coderoutines h include pl h S EEK K K k k RR RRR ck RK k k kk kk k k k k k k k k ck ck ck kckckckckckckckckckckckckckc
10. V 8 bits no FEC A1 B1 16 24 32 pl RxFromPL buffer depending on chosen length of the frame Figure 4 9 Detailed information about the buffers used Designer Reference Manual 78 8 with no FEC chosen 14 with FEC DRM035 Rev 0 Software Module Descriptions For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Software Module Descriptions PLM Implementation 4 6 11 Main loop description The flowchart of the main loop is shown in Figure 4 10 Abbreviations in this figure are described here e pl FlgModeofModen variable gt MODE demfsk NewFrmCounter Counter e powerline reception gt PL Rx e serial communication reception gt SCI Rx start Counter OK for PL Rx MODE equal to PL Rx v Call demfskDem demodulation routine SCI Receiver Full flag MODE equal to SCI Rx Stop data sampling demfskStopADCRxFromPL Set MODE to SCI Rx v Clear SCI Rx Full flag Enable SCI Rx IRQ Figure 4 10 Main loop flowchart NOTE The main routine is not written according to the coding rules such as no function calling in the interrupt service routines ISR short ISRs testing of global flags in the main loop etc It has one and only one reason it is optimized for the speed and efficiency of the PL algorithm For example almost
11. This table is valid for both PL FECTYPE possible values see next chapter When it is equal to PL NOFEC just the lower 8 bits are stored in each word of the buffer otherwise 14 bit long values are used 6 bits of redundant information added by FEC There are other symbolic constants defines to be set according to the application requirements in pl c file the following setting allows the user to control the FEC technique used during the communication switched FEC on or off define PL FECTYPE PL 1STFEC choose PL NOFEC or PL 1STFEC For more information about FEC see 4 6 4 FEC calculation e inorder to perform TEA encryption over the buffers this line should be placed in pl h file define PL TEACRYPT 1 if defined perform TEA encryption asmentioned in 4 5 6 Communication parameters chapter there are several f and f possible signaling frequency combinations the following conditional macro definition placed in pl h allows the user to choose one of them Choose the carrier frequencies dif O define PL CARRIERLOW CARRIERLOW 110KHZ10KBPS define PL CARRIERHGH CARRIERHGH 100KHZ10KBPS Fendif dif 1 define PL CARRIERLOW CARRIERLOW 115KHZ10KBPS define PL CARRIERHGH CARRIERHGH 105KHZ10KBPS dendif Hif O define PL CARRIERLOW CARRIERLOW 120KHZ10KBPS define PL CARRIERHGH CARRIERHGH 110KHZ10KBPS Designer Reference Manual MOTOROLA Software Module Descriptions 61 For Mor
12. 0 and 1 calculation saturation mode must be off 0 calcDTFT pK0Base fl calcDTFT pKlBase 0 1 comparison and store decoded bit to bBuf buffer last24SubBits lt lt 1 last24SubBits amp OxOOFFFFFF if f1 f0 demfsk NewFrmCounter DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 119 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files pbBuf 1 save subbit value to bBuf last24SubBits 1 save subbit value to last24SubBits else pbBuf 0 pbBuf modulo addressed buffer if pbBuf gt bBuf BBUFLENGTH modulo addressing pbBuf bBuf asm calculation 0 1 move fl a saturation mode must be off add f0 a asr a rnd a move a f0 slidAverage amp SB lambB fO short term sliding average calcul if SB DEMFSK SAMULTIPLE SA amp amp demState 2 if SB lt 2 DEMFSK SAMULTIPLE SA switch demState slidAverage amp SA lambA 0 long term sliding average calcul case 0 wait state until f0 or f1 is present if SB gt gt DEMFSK SAMULTIPLE gt SA if SB 2 DEMFSK SAMULTIPLE SA demState 1 minSync 24 demCount 0 break case 1 0 or f1 is present find synchronization pattern state demCount actualSync numOnes last24SubBits DEMFSK
13. DRM035 Rev 0 Designer Reference Manual MOTOROLA References 81 Go to www freescale com Freescale Semiconductor Inc References Designer Reference Manual DRM035 Rev 0 82 References MOTOROLA Go to www freescale com Freescale Semiconductor Inc Designer Reference Manual PLM Appendix B Bill of Materials and Schematics B 1 Contents This section includes e PLM 5 board bill of materials Table B 1 e PLM 5 board schematics PLM BLOCKS Figure B 1 Power Stage amp Coupling Figure B 2 Output Filter Figure B 3 Input Stage Figure B 4 Microcontroller Figure B 5 RS232lnterface Figure B 6 Power Figure B 7 Table B 1 PLM 5 board bill of materials Part Value C1 C2 C4 C20 2 2uF 10V C3 6 8nF C13 5 6nF C5 C9 C11 C12 10nF C6 C8 680pF C14 330pF C7 C24 C31 C32 C33 C34 C35 100nF C37 C43 C44 C45 C46 C47 C49 C10 3 3nF C18 C19 C36 33uF 16V DRM035 Rev 0 Designer Reference Manual MOTOROLA Bill of Materials and Schematics 83 For More Information On This Product Go to www freescale com Designer Reference Manual Freescale Semiconductor Inc Bill of Materials and Schematics Table B 1 PLM 5 board bill of materials C22 100pF C23 220uF 16V C25 100uF 16V C26 47pF C27 39pF C28 2
14. MODULES INCLUDED None HR RR KKK RR RK kk A A k k kk kk kc kckckckckckck ck ck ck kckckckckckckckckckckckck ck k k k k k k k k k k RR k k k k RK ck k ifndef TEA H define TEA H S EE KK K KR k k k k k RR KR KKK k k KR k k k k k k k k k k k k k k RR RK KKK RRR k k k RR ck ck ck RR ck ck ck ck k k INCLUDES S EE KK K K k KR k k k k kk Sk k k k KR k k k k k k k k k k ck ck ck kckckckckckckckckckckckckckck k k k k k k k k k kk k k k k k ck k k k k k k k ck ck k include pl h include types h S EE KK K K k KR k k RR RRR KKK k k k k k k k k k k k k k k ck ck ck kckckckckckckckckckckckckckck k k k k k k k k k k k k k k ck ck ck ck k k k k k k ck k k STRUCTURES S EE KK K k k KR k k KR RR k k kk k k k k k k k k k k k k k k ck ck ck kckckckckckckckckckckckckckckck k k k k k k k k k k k k k ck ck ck ck k k k ck k ck ck k k typedef union TEA buffer UWordi16 w 4 UWord32 dw 2 tea uIO typedef union TEA Encryption key UWordi16 w 8 UWord32 dw 4 tea uKey BR RR KR K k RRR RRR KK RK KK KK KR kc kckckckckckck ck ck kckckckckckckckckckckckckckck ck ck ck ck k k k k ck k k k k k k ck ck ck ck ck k k k ck ck ck kk LOCAL DEFINES BR K K K K KR RRR RR k k RR KK k k kk k A k k kckckckckck ck ck ck kckckckckckckckckckckckckck ck ck k k k k k k k k k k k k k ck ck ck ck k k ck ck ck ck ck kk define TeaDelta 0x9E3779B9 TEA constant chosen to be the real part of the
15. Size of the Gata and stack memory areas were modified Designer Reference Manual DRM035 Rev 0 62 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions PLM Implementation 4 5 8 Memory usage The following table shows the PLM software memory allocation Table 4 6 Memory usage Type of memory Total size w Used memory w Free memory program flash P FLASH 2000 9F1h approx 6996 data X RAM for stack 1004 data X RAM 2C0h 1E1 approx 3296 data flash X FLASH 800 3844 approx 56 4 6 PLM Implementation In this section the complete descriptions of the key software modules of the PLM are given 4 6 1 Modulation The theoretical introduction of this topic is presented in 4 3 1 FSK modulation All FSK modulation coding can be found in tmrfsk c and tmrfsk h files As mentioned in 3 4 1 3 Power stage the FSK modulation output of the DSP is in a square wave form and it became a harmonic signal after the HW filtration The CarrierTmr Quad Timer D2 see 4 5 3 Used DSP peripherals is dedicated to carrier generation It is configured to Count repeatedly Count Once ONCE bit is cleared and Count until compare then re initialize Count Length LENGTH bit is set The Output Mode is set to Toggle OFLAG output on successful compare while the OFLAG output
16. A10 A9 A8 A3 A2A1 B16 B10 B9 B8 B3B2B1 C16 C10C9 C8 C3C2C1 J SENI direction val for reading NNN V V Xi6 Xxi0xox8s xaxexi Y Y YY AllB1C1 X1A2B2 c2 xzAsBasical led is t Figure 4 7 Interleaving technique of PL transmission NOTE The Header part is sent in a normal linear way there is no interleaving used 4 6 7 States of the PL modem State diagram of the PLM software is shown in Figure 4 8 State diagram of the Power Line Modem Abbreviations used in the figure pl FlgModeOfModenm variable gt MODE demState variable gt state e powerline reception gt PL Rx powerline transmission gt PL Tx serial communication reception gt SCI Rx serial communication transmission gt SCI Tx Designer Reference Manual DRM035 Rev 0 72 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions PLM Implementation MODE 0 no operation demfskStartADCRxFromPL MODE 7 SCI data received PL Rx has been started Rx Full IRQ enabled otherwise MODE 8 PL Rx in progress state O waiting for FO F1 signals SCI data received Rx Full IRQ enabled MODE 1 SCI Rx could be started SCI data received signals are present Rx Full IRO enabled first SCI Rx ISR occurred MODE 9 PL Rx in progres
17. MODULES INCLUDED None BOR RR K k KR KR RR RR k k RR KK KK KK k k k RR RK KKK RRR RR k k k k k k k RR k k k k k k k k RK INCLUDES include types h include demfsk h BOR RR K K KR KR RR RR RR RR KK KK kk kc kckckckckckck ck ck ck kckckckckckckckckckckckckckck ck ck k k k k k k k k k k kc k k k ck ck ck RR ck ck ck ck kk Coefficient Look up tables located at XFlash or XRAM data memory area BR RRR KR RRR RR RR RK kk kc kk k k kk kc kckckckckck k ck ck ck kckckckckckck ck kckckckckckck ck RRR ck ck ck k k ck ck ck ck kk Omega 2 pi fsamp e j Omega n where f is the nominal frequency fsamp is the sample frequency n is the integer number from range 0 49 BR RRR k k KR RR RR RR ke kk kk k k KR kk kc kckckckckckck ck ck ck kckckckckckck ck kckckckckckck ck ck k k k k k ck kk kk ck k ck ck ck ck ck k k ck ck ck ck c
18. for i 0 i lt FRAME PRELEN i transfer the header part of frame pl TxToPL Array Byte i pl RxFromSCI Array Byte il if fec Mode PL NOFEC 8 data bits represents ONE byte transfer packet tor i FRAME PRELEN i length FRAME PRELEN i pl TxToPL Array Byte i pl RxFromSCI Array Byte il else if fec Mode PL 1STFEC 14 coded bits represents ONE byte transfer amp FEC packet for i FRAME PRELEN i length FRAME PRELEN i temp pl RxFromSCI Array Byte i gt gt 4 amp OxOF temp FECtableCoder temp 7 temp FECtableCoder pl RxFromSCI Array Byte i amp Ox0F pl TxToPL Array Byte i temp DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 133 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files BR RRR KR KR RR KR RR RR RK KK kk kk kk kc kckckckckckck ck ck ck ck kckckckckckckckckckckck ck ck RR RR ck ck ck ck ck RR RRR RK KK Module void codePLtoSCI void Description This routine completely transfer the data from the PL Rx buffer side to SCI Tx side it call the de interleaving routine align the PL Rx buffer if FEC is used then perform the de FEC algorithm check the consistency of the received packet using the lengt
19. pl Flags flag pl FlgModeOfModem the Mode is inicially set to STATE3 SCI reception has been finished but after the routine the data for PL transmission is ready so it switches to STATE4 PL transmission could For the global data description of the codeSCItoPL routine see the description of the routine itself HR KR RR KK RR RR RR KK ck ck k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ck ck k k ck ck ck ck kk pragma interrupt void tmrfskTimeOutISR void UWordl6 temp archPushAllRegisters ioctl QTIMER D3 QT CLEAR FLAG QT COMPARE FLAG clear the flag pl FlgModeOfModem STATE3 set Mode of Modem ioctl SCI 0 SCI RX FULL INT SCI DISABLE disable interrupt if ioctl SCI 0 SCI GET RX FULL NULL clear flag temp ioctl SCI 0 SCI READ DATA NULL codeSCItoPL pl FlgModeOfModem STATE4 tmrfskSetTxEnable tmrfskStartCarrierTmr archDelay Ox1FFF archDelay Ox1FFF archDelay Ox1FFF archDelay Ox1FFF tmrfskStartBitTmr archPopAllRegisters Designer Reference Manual prepare data from SCI to PL set Mode of Modem switch on the transmitter Start generation of FSK carrier Tx of the carrier before the header and data part transmission total 0 8ms start FSK transmission DRM035 Rev 0 110 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freesc
20. EQ 4 15 Aa and Ag are Forgetting factors which are less than but close to 1 AA gt Ag makes the S4 value a long term sliding average and Sga short term sliding average To achieve a synchronization of the signal windows and the signal elements a synchronization byte called a Header is transmitted in the pre control initial part of each data burst packet The synchronization Designer Reference Manual DRM035 Rev 0 50 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com DRMO035 Rev 0 Freescale Semiconductor Inc Software Module Descriptions Theory byte is formed by a bit sequence 10 1 00 10 1 The transmitter and receiver clocks are supposed to be precise enough to keep the synchronization during the whole data burst The best fit of the synchronization sequence is computed as the position where the divergence between the sequence of b i coming from the Fo i and F i comparison and interpolated synchronization bit sequence interpolated Header is minimal idx index of min SYN EQ 4 1 6 where SYN i b XOR 111000111000000111000111 EQ 4 17 The incoming signal is windowed with 33 overlap For this overlap the synchronization bit sequence has to be interpolated by a 3 1 ratio Due to this overlap each signal element received bit stored in the MSG output buffer is calculated from 3 values of the comparison results bfi so called s
21. FRAME DATALEN temp pl RxFromPL Struct CRC 1 lt lt 8 pl RxFromPL Struct CRC 0 original CRC value if codeCRCCalc pl RxFromPL Array Byte pl RxFromPL Struct Cntrl 1 temp if calculated CRC value is equal to the original the packet is OK store only CNTRL and DATA for i 0 i lt pl RxFromPL Struct Cntrl 1 i pl TxToSCI Array Byte i pl RxFromPL Array Byte il else pl_FlgDataError 1 set bad data consistency Data Error flag bad CRC else pl FlgDataError 1 set bad data consistency Data Error flag bad length DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 135 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files BRR RR RR RR RR RRR RR KR kk kk kckckckckck ck ck ck ck kckckckckckckckckckckckck RRR RRR ck ck ck ck ck ck k k k k k k k Module asm void deintrleave UWord32 pInput UWordl6 pOutput x UWordi6 numRows UWord16 numColumns Description Function performes de intearleaving of input data pInput and returns de interleaved data in buffer pOutput The 14 8 data bits with FEC or without FEC are located in upper 14 8 bits of words in pOutput buffer Returns None Global Data None Arguments Inputs pInput pointer to input buffer pOutput pointer to output buffer numRows 16 24 or 32 number of tran
22. Sons 1 Initial Release N A Designer Reference Manual DRMOS35 Rev 0 4 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Designer Reference Manual PLM DRMO035 Rev 0 List of Sections Section 1 Introduction 15 Section 2 Quick Start 17 Section 3 Hardware Description 21 Section 4 Software Module Descriptions 43 Appendix A References 81 Appendix B Bill of Materials and Schematics 83 Appendix C Source Code Files 93 Appendix D Glossary 167 Designer Reference Manual MOTOROLA 5 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Sections Designer Reference Manual DRM035 Rev 0 6 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Designer Reference Manual PLM DRMO035 Rev 0 LE 1 3 2 1 2 2 2 3 2 4 3 1 3 2 3 3 3 4 3 5 3 6 3 7 4 1 4 2 Table of Contents Section 1 Introduction COMETS Le e zoe sb doter O PO Oe Gee 15 Application intended functionality 15 Benefits of our solution 0 0 0 00 eee eee ee eee 15 Section 2 Quick Start E RME KI ee enh TTE 17 n
23. UWord16 backPtr pointer for back transfer backPtr ptr save a pointer do for i 0 i lt 4 i 8bit gt 16bit tea IO w i ptr ptr lt lt 8 just 8bit values at Ptr teaCode perform an encryption for i 0 i lt 4 i 16bit gt 8bit backPtr tea_IO w i amp OxOOFF backPtr tea IO w i amp OxFF00 gt gt 8 while 8 j lt roundLen the length is a multiple of 8 The sequence of transmitted bits is modified in a way shown in Figure 4 7 Interleaving technique of PL transmission The depth of interleaving is therefore equal to the length of the frame to be transmitted The de interleaving procedure during the PL reception phase is similar The interleaving algorithm is implemented directly in the tmrfskBitISR routine placed in tmrfsk c see 4 3 1 FSK modulation for more details just by changing the order of transmitted bits The de interleaving routine is called deinterleave and is located in coderoutines c More details about the implementation itself can be found in Figure 4 9 Designer Reference Manual MOTOROLA Software Module Descriptions 71 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions prepared data for transmission TXToPL buffer A16
24. symbolic constant scaling factor Arguments pCoeff pointer to table of coefficients coefficients must be in the order real0 imag0 reall imagl Range Issues None Special Issues saturation mode must be off DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 125 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files Others buffer of input samples should be in internal data RAM memory tables of coefficients should be in XFlash data memory area 56F801 source or FLASH target in 56F803 source or in internal RAM data memory area RAM target in 56F803 source asm Wordl6 calcDTFT Wordl6 pCoeff move m01 r1 store value of m01 move pInFrame r0 r0 address of input samples move XBUFLENGTH 1 m01 r0 modulo addressing in xBuf xBuf address must be multiple of 2 k move r2 r3 r3 address of coefficients calculation of real and imag part of F0 no pipeline dependency clr a x r0 yl a real part of FO yl input sample err b x r3 x0 b imag part of FO x0 real part
25. the non inverting configuration of the amplifier is used The open loop voltage gain of the LF351 at a frequency 100 kHz is less than 40 dB 100 Note that the gain of the closed loop should be small compared to the open loop gain to get the accurate output driven by external components The closed loop gain is set up to 100 then the gain in the band is limited by the open loop gain The input amplifier is followed by a diode limiter to keep the amplitude of the signal in the range suitable for the A D converter input Next a low pass filter created by inductor L3 and capacitor C8 with cut off frequency of 110 kHz is used to eliminate high frequency components from the signal prior to sampling The Designer Reference Manual MOTOROLA Hardware Description 33 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Description 3 4 4 Microcontroller Designer Reference Manual measured frequency response of the Input Amplifier can be seen in Figure 3 8 45 0 40 0 35 0 30 0 25 0 20 0 15 0 10 0 a o 1000 10000 Frequency Hz 100000 1000000 Figure 3 8 Frequency Response of the Input Amplifier Motorola 16 bit DSP56F801 U20 is the main component of the PLM board The schematic diagram can be seen in Figure B 5 The output FSK modulated signal is provided from the Timer D Channel 2 pin and the input sign
26. 1 mask lt lt 1 index FRAME PRELEN else index delse PL Tx with NO INTERLEAVING if pl FlgModeOfModem STATE4 test Mode of Modem condition pl FlgModeOfModem STATES set Mode of Modem index 0 dif PL FECTYPE PL NOFEC mask 1 Mask for 8bit Header with no FEC else pl TxToPL Array Byte 0 lt lt 6 vight shift of Header mask 0x40 Mask for 8bit Header with FEC endif if pl FlgModeOfModem STATES test Mode of Modem condition Designer Reference Manual DRM035 Rev 0 108 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files tmrfsk c if index lt FRAME TOTALLEN FRAME PRELEN if mask amp pl TxToPL Array Byte index if ioctl QTIMER D2 QT READ COMPARE REG1 NULL PL CARRIERLOW if previous value was logical 0 while ioctl QTIMER D2 QT READ COUNTER REG NULL gt PL CARRIERHGH TMRFSK SAFETYRESERVE tmrfskSetCarrierHigh set logical 1 carrier tmrfskTxDLEDOn Set the transmit LED indication else if ioctl QTIMER D2 QT READ COMPARE REG1 NULL PL CARRIERHGH if previous value was logical 1 while ioctl OQTIMER D2 OT READ COUNTER REG NULL gt PL CARRIERHGH TMRFSK SAFETYRESERVE tmrfskSetCarrierLow set logical 0 carrier tmrfskTxDLEDOff Clear the transmit LED
27. Freescale Semiconductor Inc Software Module Descriptions PLM project introduction Table 4 2 ADC A Sample Input Time Slot analog pin Purpose ISR function data collection for FSK demfskEndOfScanISR demodulation Sample 0 AN 0 NOTE NOTE 4 5 4 Used interrupts DRMO035 Rev 0 Data sampling PL reception is controlled started and stopped via the TriggerTmr C2 A list and description of the GP O pins used is given in the following table Table 4 3 GPIO GPIO Direction Symbolic Purpose contol name signal GPIOB4 output TXENABLE enable disable Ihe jeme control amplifier GPIOB5 output TXD transmitted data signalization signal GPIOB6 output RXD received data signalization signal GPIOB7 output CD carrier detection signalization signal The control signal influences the behavior of the Power Line Modem the signaling ones are used just for the LED indications For the DSP56F803 project the table would be exactly the same with the only exception that there is the GPIOD port used instead of the GPIOB which is not available on the DSP56F801 core For a description of the SCI periphery module see Table 4 4 All interrupts of the Power Line Modem peripherals which are used are briefly detailed in this section Designer Reference Manual MOTOROLA Software Module Descriptions 57 For More Information On This Product Go to www freescale c
28. UWord16 length Designer Reference Manual DRM035 Rev 0 132 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files coderoutines c Description This routine moves the pl RxFromSCI to pl TxToPL buffer and also perform the FEC coding if required Returns None Global Data i pl RxFromSCI a buffer of SCI received data x pl TxToPL a buffer of data prepared for PL transmission FECtableCoder table of the coding part of the linear block Forward i error correction FRAME PRELEN a symbolic constant describing the length in B pre control header part of packet PL NOFEC and PL 1STFEC symbolic constants defining the type of used FEC coding Arguments FEC Mode either PL NOFEC no FEC correction or PL 1STFEC FIRST version of FEC correction length an actual length of the pl RxFromSCI pl TxToPL buffer Range Issues None Special Issues None Others look up table called FECtableCoder could be located in XFlash data memory area 56F801 source or FLASH target in 56F803 source or in internal or external RAM data memory area RAM target in 56F803 source RRR RK KK KK RR A KK ck kckckckckckckckckckckckckckckck ck k k k k k k k k k k k k k k k RR k k k k KKK void codeMoveAndFECBuff UWord16 fec Mode UWordi6 length UWordl6 i temp
29. buffer amp Oxff BOR K K RRR KR RR RR RRR RR KK RR RR KKK KR RRR RR RR ck ck ck ck k k RR k k RR KK Module void codeSCItoPL void Description This routine completely prepare the data from the SCI Rx buffer side to PL Tx side it clears the rest of data bytes of pl RxFromSCI buffer calculate the CRC of the frame call the TEA encyption algorith and finally call the routine that moves the pl RxFromSCI buffer to pl TxToPL buffer and perform FEC during this move Returns None DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 131 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files Global Data pl RxFromSCI a buffer of SCI received data pl TxToPL a buffer of data prepared for PL transmission FRAME DATALEN a symbolic constant describing the data length in B of packet For the global data description of the codeCRCCalc routine see the description of the routine itself PL TEACRYPT a symbolic constant if defined the Tiny Encryption is processed over the packets For the global data description of the teaEncryptBuff routine see the description of the routine itself FRAME TOTALLEN a symbolic constant describing the total length of the whole packet in B to be sent For the global data description of the codeMoveAndFE
30. frame AS ARRAY of the SCI transmission UWordl6 Byte FRAME CNTRLLEN FRAME DATALEN 2 minus 2B of CRC pl sArrayTxToSCI typedef union complete union of the SCI transmission pl sStructTxToSCI Struct frame AS STRUCTURE of the SCI transmission pl sArrayTxToSCI Array frame AS ARRAY of the SCI transmission pl uTxToSCI BOR KK K KR KR KR KR k k RR RK RK KK KR RK ck ck ck ckckckckckckckckckckckckckckck ck k k k k k k k k k k k ck k k k ck ck ck k k ck ck ck ck kk typedef struct UWord16 ModeOfModem 4 Mode of the modem Here are the possible states of pl FlgModeOfModem variable State Description of PL Modem Mode STATEO No operation no communication of modem STATEL SCI reception could be started RxFromSCI buffer is ready STATE2 SCI reception in progress STATE3 SCI reception has been finished STATE4 PL transmission could be started TxToPL buffer is ready STATES PL transmission in progress STATE6 PL SCI transmission has been finished Designer Reference Manual DRM035 Rev 0 104 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files tmrfsk c STATE7 L reception has been started STATE8 L reception in progress FSK demodulation in emstate 0 waiting until FO or Fl is present P P D STATES PL reception in progress FSK demodu
31. serial communication interface module SCI serial Pertaining to sequential transmission over a single line serial communications interface module SCI A module that supports asynchronous communication serial peripheral interface module SPI A module that supports synchronous communication set To change a bit from logic O to logic 1 opposite of clear Designer Reference Manual DRM035 Rev 0 174 Glossary MOTOROLA Go to www freescale com Freescale Semiconductor Inc Glossary shift register A chain of circuits that can retain the logic levels logic 1 or logic 0 written to them and that can shift the logic levels to the right or left through adjacent circuits in the chain signed A binary number notation that accommodates both positive and negative numbers The most significant bit is used to indicate whether the number is positive or negative normally logic O for positive and logic 1 for negative The other seven bits indicate the magnitude of the number software Instructions and data that control the operation of a microcontroller software interrupt SWI An instruction that causes an interrupt and its associated vector fetch SPI See serial peripheral interface module SPI stack A portion of RAM reserved for storage of CPU register contents and subroutine return addresses stack pointer SP A 16 bit register in the CPU containing the address of the
32. the PL reception needs the interleaving BR RRR KR RRR RR RR RR RK k k k k kk kk k k k k k k k ck ck ck kckckckckckckckckckckckckckck ck ck ck ck k k k k k k k k k k k k ck ck ck k k ck ck ck ck kk PRIVATE DEFINES S EE KK K k KK RRR RR RR RK KK RR RK KK KR RRR RR RR k k ck ck ck ck k k NOTE when carrier is called low gt frequencies are higher and vice versa define CARRIERLOW_110KHZ10KBPS define CARRIERHGH 100KHZ10KBPS define CARRIERLOW_115KHZ10KBPS define CARRIERHGH 105KHZ10KBPS define CARRIERLOW_120KHZ10KBPS define CARRIERHGH 110KHZ10KBPS define SHORT 0 define MEDIUM 1 define LONG 2 define PL NOFEC 8 define PL 1STFEC 14 dif PL FECTYPE PL NOFEC define PL TXMASK 0x00 Designer Reference Manual 182 200 174 190 167 182 80 used for log 0 half half half half half half period of period of period of period of period of period of 110kHz 100kHz 115kHz 105kHz 120kHz 110kHz 10kBps 10kBps 10kBps 10kBps 10kBps 10kBps n T RE ud DRM035 Rev 0 102 For More Information On This Product Source Code Files Go to www freescale com MOTOROLA Freescale Semiconductor Inc Source Code Files pl h delse define PL TXMASK 0x2000 endif define PL HEADERTXMASK 0x0080 define FRAME P
33. the packet is received through the mains the data are checked and if there is no inconsistency error they are sent through the SCI to an appliance or a control terminal This approach is called the transparent channel or transparent mode of the frame packet oriented protocol and it is shown in Figure 4 1 len frame 1 CRC data 1 PLM gt PLM data 1 Dm p lt SCI PL PL SCI data 2 ien trame 2 CRC data 2 Figure 4 1 Block diagram of the communication system 4 2 3 Over the data operations basics It is necessary to process the transmitted data packet before it can be sent out The following operations have to take place e Cyclic Redundancy Code CRC computation is used to generate the CRC field which contains information that is added to any transmitted frame The CRC field is used to verify the integrity of every transmitted frame since this information is checked and compared to a recalculated CRC field on the recipient s side e Encryption technique ensures the security of the transmitted data This PLM board software utilizes the Tiny Encryption Algorithm TEA by David Wheeler and Roger Needham TEA is a Feistel cipher with XOR and and addition as the non linear mixing functions e Forward Error Correction FEC uses added redundancy information in order to correct errors which occurred during the transmis
34. then pin TxD is set to 1 and LED is switched off define tmrfskTxDLEDOn ioctl GPIO E GPIO CLEAR PIN TXD define tmrfskTxDLEDOFf ioctl GPIO E GPIO SET PIN TXD Note that RxD output pin is only for signalization If the PowerLine modem reception data value Rx is logical 1 then pin RxD is cleared to 0 and LED is switched on logical 0 then pin RxD is set to 1 and LED is switched off define tmrfskRxDLEDOn ioctl GPIO E GPIO CLEAR PIN RXD define tmrfskRxDLEDOFf ioctl GPIO E GPIO SET PIN RXD Note that CD output pin is only for signalization If the PowerLine modem reception is processing then pin CD is cleared to 0 and LED is switched on not processing then pin CD is set to 1 and LED is switched off define tmrfskCDLEDOn ioctl GPIO E GPIO CLEAR PIN CD define tmrfskCDLEDOfFf ioctl GPIO E GPIO SET PIN CD endif ifdef DSP56F801 DRMO035 Rev 0 Note that TxEnable output pin control the function of the modem If the PowerLine modem should perform a transmission then pin TxENABLE is cleared and the indication LED is switched on not perform a transmission then pin TxENABLE is set and the indication LED is switched off See that signal TxEnable is inverted to enable it has to be cleared and vice versa define tmrfskSetTxEnable ioctl GPIO B GPIO CLEAR PIN TXENABLE define
35. 17 FRAC16 0 425779 FRAC16 0 904827 18 FRAC16 0 929776 FRAC16 0 368125 19 FRAC16 0 309017 FRAC16 0 951057 20 FRAC16 0 968583 FRAC16 0 248690 21 FRAC16 0 187381 FRAC16 0 982287 22 FRAC16 0 992115 FRAC16 0 125333 23 FRAC16 0 062791 FRAC16 0 998027 24 FRAC16 1 000000 FRAC16 0 000000 25 FRAC16 0 062791 FRAC16 0 998027 26 FRAC16 0 992115 FRAC16 0 125333 27 FRAC16 0 187381 FRAC16 0 982287 28 FRAC16 0 968583 FRAC16 0 248690 29 FRAC16 0 309017 FRAC16 0 951057 30 FRAC16 0 929776 FRAC16 0 368125 31 FRAC16 0 425779 FRAC16 0 904827 32 FRAC16 0 876307 FRAC16 0 481754 33 Designer Reference Manual DRM035 Rev 0 158 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files appconfig h FRAC16 0 535827 FRAC16 0 844328 34 FRAC16 0 809017 FRAC16 0 587785 35 FRAC16 0 637424 FRAC16 0 770513 36 FRAC16 0 728969 FRAC16 0 684547 37 FRAC16 0 728969 FRAC16 0 684547 38 FRAC16 0 637424 FRAC16 0 770513 39 FRAC16 0 809017 FRAC16 0 587785 40 FRAC16 0 535827 FRAC16 0 844328 41 FRAC16 0 876307 FRAC16 0 481754 42 FRAC16 0 425779 FRAC16 0 904827 43 FRAC16
36. 684547 44 FRAC16 0 587785 FRAC16 0 809017 45 FRAC16 0 876307 FRAC16 40 481754 46 FRAC16 0 368125 FRAC16 40 929776 47 FRAC16 0 968583 FRAC16 0 248690 48 FRAC16 0 125333 FRAC16 0 992115 49 j S EE RRR KR RK k k RR RRR RK k k kk RK k k RR KKK KR k k RR RRR RR k k k k k k k k 120kHz x BRR RR KR KR RR k k RRR RR RK KR kk k k k k k k k ck ck ck kckckckckckckckckckckckckckckckckckck ck k k k k k k k k k k k k ck ck ck ck ck ck ck ck kk const Wordl6 K120 2 DEMFSK FRAMELEN real part imag part FRAC16 1 000000 FRAC16 0 000000 O FRAC16 0 062791 FRAC16 0 998027 1 FRAC16 0 992115 FRAC16 0 125333 2 FRAC16 0 187381 FRAC16 0 982287 3 FRAC16 0 968583 FRAC16 0 248690 4 FRAC16 0 309017 FRAC16 0 951057 5 FRAC16 0 929776 FRAC16 0 368125 6 FRAC16 0 425779 FRAC16 0 904827 7 FRAC16 0 876307 FRAC16 0 481754 8 FRAC16 0 535827 FRAC16 0 844328 9 FRAC16 0 809017 FRAC16 0 587785 10 FRAC16 0 637424 FRAC16 0 770513 11 FRAC16 0 728969 FRAC16 0 684547 12 FRAC16 0 728969 FRAC16 0 684547 13 FRAC16 0 637424 FRAC16 0 770513 14 FRAC16 0 809017 FRAC16 0 587785 15 FRAC16 0 535827 FRAC16 0 844328 16 FRAC16 0 876307 FRAC16 0 481754
37. Bill of Materials and Schematics 89 For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc W o G o o en 2 G imd W e m J9 o1uoD013W G g 91NBI sseuisng EJeuec smejS dod LOOZ BIOJOIOW juBuAdo5 1 p S jeeus L00z Lz 1equieideg Repu ereq KIPON NSC S0 08100180 OELOOWMHITEINNODMUSALYT NaIA Wid 0lszdydowood OWEN JI uDiseq NOLAN vo M 869 000VY ABY JelloquoooloIN OWEN PWYS szs 000 Vt DEJOUDOUJ JiLuOJe JOUINY S Wd en adoing ojgnd9y uoezo ud AoUZOY L9 997 6001 efeui AOUZOY SOW 08v4L08JoSdsa AO0VJnz Z MOL 09H MOL 9SH PSSA AOL ANZ Z ESSA e ZSSA LOdVOA LSSA ZOdVON YOGA AUOOL 640 ean LOGA MOL 693 av3g aliia VSSA TESS VaGA SOL 6 aa AG e voll JIYA SWL LSI C ZNV LSL Z 9NY Yor 9 SNV oar S YNY IaL GNOW k ENY ZNV c LNV u viva ONV 8OldA 1v LX3 ZAOIdW IVIX ovi1nv4 e L 13S3M 49 moviva ZWOIdW ZOL sc LVOIdW LGL VON o OVOIdW OGL 9k FSi Sasa LgOIdW 0gXy SvWMd 09OldN 0qXL Ek AC et PYWMd 8 ZXO0L H3avaH EVWMd 180ldW sS MOL ESH ZVAMd POIdA MTDS ax LYNMd 98OIdW OSIIN OVI AMd S8OIdW ISON axy ajgeus 1 er du001 8 e ML LL Kw XL ZH jo viva K ML OSH Slqeus XL ea MOTOROLA DRMOS35 Rev 0 Bill of Mat
38. EUROPE LOCATIONS NOT LISTED Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 303 675 2140 or 1 800 441 2447 JAPAN Motorola Japan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 TECHNICAL INFORMATION CENTER 1 800 521 6274 HOME PAGE http motorola com semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters
39. More Information On This Product Go to www freescale com NOTE DRMO035 Rev 0 Freescale Semiconductor Inc Software Module Descriptions PLM project introduction pl sStructRxFromSCI Struct frame AS STRUCTURE pl sArrayRxFromSCI Array rame AS ARRAY pl uRxFromSCI Note thatthepl uRxFromSCI data type is used forpl RxFromSCI as well as forpl TxToPL variables e Word16 xBuf XBUFLENGTH declared in demfsk c is a circular buffer of samples as they are read from the ANO pin of the ADC A module during its ADCEndOfScanISR routine e Wordl6 demfsk NewFrmCounter declared in demfsk c is a counter for the ADCEndOfScanISR routine it is decremented each time the function is performed e UWord32 demfsk MSGBuf DEMFSK MSGBUFLEN declared in demfsk c is another buffer aimed at FSK demodulation and therefore PL reception Rough binary data before any manipulation is done with them are stored there as a result of the FSK demodulation routine e pl sFlags pl Flags is a following structure which contains the state and another error flag of the PL modem device taken from pl h typedef struct STATE11 emstate 2 data reception L reception in progress FSK demodulation in UWordi6 ModeOfModem 4 Mode of the modem Here are the possible states of pl FlgModeOfModem variable State Description of PL Modem Mode STATEO No operation no communication of modem STATE1 SC
40. RR ck ck ck ke ke ek CGP Initially the COP module is disabled by startup asm code but when there is the global define define PL COPINUSE if defined the Watch Dog is used placed in the pl h file it finally switch the COP on TMR Du There is no definition for TmrD1 Compare register 1 value in appconfig h configuration it depends on the global define placed in the pl h file define PL PLBAUDRATEPL 10000BPS choose PL 10000BPS TMR D2 There is no valid definition of TmrD2 Compare register 1 value in appconfig h configuration it depends on the global define placed in the pl h file define PL CARRIERLOW CARRIERLOW 110KHZ10KBPS TMR D 3 There is a zero value of TmrD3 Compare register 1 written in appconfig h configuration this register is filled according the global define define PL TIMEOUTVALUE 1000 time out of SCI receive placed in the pl h file SCI There is no definition for SCI baudrate value in appconfig h configuration it depends on the global define placed in the pl h file define PL SCIBAUDRATE SCI BAUD 38400 choose SCI BAUD 38400 not tested SCI BAUD 4800 SCI BAUD 9600 SCI BAUD 19200
41. SCI transmission has been finished Than the ADC data sampling is started and mode is set to STATE7 PL reception has been started pl TxToSCI a buffer to be sent Arguments None Range Issues Only when pl FlgModeOfModem is equal to STATE12 or STATE13 the SCI transmission is performed Special Issues None HR KR KK KR KR RR A A A KK k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k RR k k ck ck kk pragma interrupt void scicommTxEmpISR void UWordl6 temp static UWord16 index pl FlgModeOfModem STATE12 pl TxToSCI is ready pl FlgModeOfModem STATE13 set Mode of Modem index 0 pl FlgModeOfModem STATE13 pl TxToSCI is being processed temp ioctl SCI 0 SCI GET STATUS REG NULL clear Transmit Register Empty Flag ioctl SCI 0 SCI WRITE DATA pl TxToSCI Struct Data index l SCI Tx index if index gt pl TxToSCI Struct Cntrl whole packet was transmitted ioctl SCI 0 SCI TX EMPTY INT SCI DISABLE disable SCI Tx IRQ pl FlgModeOfModem STATE6 set Mode of Modem demfskStartADCRxFromPL start PL data sampling PL reception pl FlgModeOfModem STATE7 set Mode of Modem DRMO035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 141 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files C 12 scicomm h
42. STATES 5 PL transmission in progress define STATE6 6 PL SCI transmission has been finished define STATE7 7 PL reception has been started define STATES 8 PL reception in progress FSK demodulation in Demstate 0 waiting until FO or Fl is present define STATE9 9 PL reception in progress FSK demodulation in Demstate 1 finding synchronization pattern define STATE10 10 PL reception in progress FSK demodulation in Demstate 2 data reception define STATE11 11 PL reception in progress FSK demodulation in Demstate 3 data reception finished define STATE12 12 SCI transmission could be started TxToSCI buffer is ready define STATE13 13 SCI transmission in progress S EE KK K KR RRR k k RR RR RK KK k k k k k k k k k k ck ck ck ckckckckckckckckckckckckck k k k RRR RR k k ck ck ck ck k k GLOBAL DEFINES BR RRR K k KR k RR k k RR KK RR k k k k k k k ck ck ck ck kckckckckckckckckckckckckck ck ck k k k k k k k k k k k k RR ck k k ck ck ck ck kk define PL SCIBAUDRATE SCI BAUD 38400 choose SCI BAUD 38400 not tested SCI BAUD 4800 SCI BAUD 9600 SCI BAUD 19200 define PL PLBAUDRATE TMRFSK 10000BPS choose TMRFSK 10000BPS define PL FRAMETYPE LONG choose SHORT MEDIUM LONG if SHORT type is used length of the data part of packet is 13 words if MEDIUM type is used length of the data part of packet is 21 words if LONG type is us
43. SYNCPATTERN correlation with the synchronization header pattern if actualSync lt minSync minSync actualSync pidx pbBuf if SB gt gt DEMFSK SAMULTIPLE lt SA low 0 or 1 level Designer Reference Manual DRM035 Rev 0 120 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files demfsk c if SB lt 2 DEMFSK SAMULTIPLE SA if demCount 72 stop looking for the Sync header pattern demState 0 if minSync lt 8 the Sync header pattern was found pMSGBuf demfsk MSGBuf demState 2 eachThird 1 demCount 0 numBitsReceived 0 numBitsMSGBufDWord FRAME TOTALLEN set counter pMSGBuf 0 clears the MSGBuf else the Sync header pattern was not found break end case 1 demState 0 start from the demodulation state 0 again case 2 synchronization pattern was found data reception state if eachThird 3 3 frames subbits carry just 1 bit info numBitsReceived eachThird 1 asm calculate tempBit111 pidx pidx 1 pidx 2 pidx 3 move m01 rl store value of m01 move pidx r0 r0 address of actual bit move BBUFLENGTH 1 m01 r0 modulo addressing in bBuf bBuf address must be multiple of 2 k nop move x r0 a a pidx move x r0
44. a 50 Ohms spectrum analyser should be done The CISPR16 network provides an attenuation of 6 dB due to its structure The maximum rms voltage measured on the analyser must then be max 122 dBuV that equals 3 56 V peak to peak The test set up for output voltage measurement can be seen in Figure 3 4 Designer Reference Manual DRM035 Rev 0 28 Hardware Description MOTOROLA For More Information On This Product Go to www freescale com 3 4 1 3 Power stage DRMO035 Rev 0 Freescale Semiconductor Inc Hardware Description Power Line Modem Architecture 230V corr 230V Modem S r NETWORK t 50 OHM SPECTRUM ANALYZER Figure 3 4 Test set up for output voltage measurement The impedance of the mains network at the signalling frequencies is relatively low and varies in a wide range 1 Q to 100 Q This circuit has been designed to drive a 4 O mains line over the 95 kHz to 125 kHz bandwidth The signalling impedance of the mains network fluctuates as different loads are switched on or off during the day When transmitting the transmitter appears as a low impedance signal source on the mains network If the transmitter was left in the active mode whether or not transmitting this load would reduce the mains impedance and a signal arriving from a distant transmitter would be severely attenuated To overcome this problem the transmitter needs to present a high impedance to the mains network w
45. all global flags are tested in respective ISRs since there is no PL computation at that time If these tests were done in the main loop it would be too time consuming during the PL reception phase DRM035 Rev 0 Designer Reference Manual MOTOROLA Software Module Descriptions 79 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions Designer Reference Manual DRM035 Rev 0 80 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Designer Reference Manual PLM Appendix A References 1 MOTOROLA INC DSP56F80x User s Manual Motorola User s Manual 2000 http e www motorola com 2 MOTOROLA INC DSP56800 Family Manual Motorola Family Manual 2000 http e www motorola com 3 CENELEC EN 50065 1 Signaling on low voltage electrical installations in the frequency range 3 kHz to 148 5 kHz 1991 4 EEE Micro magazine A Tutorial on CRC Computations article in IEEE Micro magazine August 1988 5 Lee Charles Error control block codes for communication engineers Artech House inc 2000 6 David Wheeler and Roger Needham TEA a Tiny Encryption Algorithm Computer Laboratory Cambridge University 1994 ftp ftp cl cam ac uk papers djw rmn djw rmn tea html 7 MOTOROLA INC AN2262 D Wireless HC08 Modem 2002
46. bit is enabled by setting the Output Enable OEN bit These settings prepare the timer for autonomous FSK generation its frequency is given by the value CarrierTmr Qtimer D2 Compare Register 1 DRM035 Rev 0 Designer Reference Manual MOTOROLA Software Module Descriptions 63 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions The BitTmr Quad Timer D1 see 4 5 3 Used DSP peripherals is aimed for the bit rate generation of the PL transmission It simply means that during its Output compare ISR the proper value of the CarrierTmr s Compare Register 1 is loaded according to the current bit value Two function style macros are used for this purpose taken from tmrfsk c tmrfskSetCarrierHigh set logical 1 carrier tmrfskSetCarrierLow set logical 0 carrier The used modulation technique is shown in Figure 4 4 CarrierTmr Output CarrierTmr output compare ISR compare lt r AY x x Y bit period 1 with fo signal bit period 2 with f signal BitTmr um BitTmr V BitTmr ur compare ISR compare ISR compare ISR Figure 4 4 FSK generation principle Here is the main part of the tmrfskBitISR routine of the BitTmr timer tmrfsk c if mask amp pl TxToPL Array Byte index current bit is 1 if ioctl QTIMER D2 OT READ COMPARE REG1 NULL PL CARRIERLOW if previous value was logical 0 while ioctl OTIMER D2 QT READ C
47. ck kk void teaEncryptBuff UWordl6 ptr UWordl6 roundLen UWord16 i UWord16 j 1 UWord16 backPtr pointer for back transfer backPtr ptr save a pointer do for i 0 i lt 4 i 8bit gt 16bit tea IO w i ptr ptr lt lt 8 just 8bit values at Ptr teaCode perform an encryption for i 0 i lt 4 i backPtr tea IO w i amp OxOOFF 16bit gt 8bit backPtr tea IO w i amp OxFF00 gt gt 8 Designer Reference Manual DRM035 Rev 0 146 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files tea c while 8 j lt roundLen the length is a multiple of 8 BOR RRR KR KR RR RR RR RRR kk kk k kk kk kc kckckckckck ck ck ck kckckckckckckckckckckckckck ck RRR ck ck ck RR RR RRR RK KK o FF FF F HF F HF X Module void teaDecryptBuff UWord16 ptr UWord16 roundLen Description This function calls the TEA decryption algorithm and move the data to and back to the temp buffer Returns None Global Data tea IO 64bits long buffer for TEA computation For the global data description of the teaCode routine see the description of the routine itself Arguments ptr pointer to the data buffer roundLen the length of the buffer to be encrypted must be a multiple of 8 this project uses following length values
48. com Freescale Semiconductor Inc Designer Reference Manual PLM C 1 Contents C 2 Introduction DRMO035 Rev 0 C 2 C 3 C 4 C 5 C 6 C 7 C 8 C 9 C 10 C 11 0 12 C 13 C 14 C 15 C 16 C 17 C 18 C 19 Appendix C Source Code Files BO ATL KOR aad ee donc hu dE kd Pac aes do 93 BEG R R T TEE 94 100 DE a doped dd ardor i aa i o d d e 105 DII EIS a acaata nd dcc odd a Reid od dia dod od o B AA o iia 111 SEO Eo ie nic dole plo M A ee eet 114 eee Ne ok keke SRA ae ees KO ee ee 128 OE POUM ELE ui c 29 dr oe ew eee RC MCI dk k d 129 GT ES 137 zk ve ja ja P E O are We 137 cc s uq NE 142 hk P O O ARS ee es PUN em 142 148 Ia 149 PERI Ead dad dodo et E GR d LAGE Re RE eee Cede 151 n dro o T PM t 153 B PT DEC a dead acie ied Soi Sd A A Va dpa deere nbn 159 linker R SPM o de oa k d kok de E k 164 This subsection is comprised of the source code used by this design reference Designer Reference Manual MOTOROLA Source Code Files 93 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files C 3 pl c BRR RR RR KR KR KR RR RRR k kk kk Sk kk kc kckckckckckckckckckckckckckckckckckckckckckck ck k k k k k k k k k k k k ck kk ck ck ck ck ck RR KK KK KK Motorola Inc c ALL RIGHTS RESERVED Copyright 2001 Motorola Inc kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk
49. counter of received bits of message is compared with this value and if it is equal the reception is finished Arguments None Range Issues None Special Issues None void demfskDem void volatile UWord16 tempBit111 bit value result calculated from 3 subsequent frames subbits Static UWordl6 minSync minimal number of errors in comparison with Header Sync pattern static UWord16 demCount used as a counter of frames as soon as FO or F1 appeared static UWord16 numBitsReceived counter of received bits of message static UWordl6 numBitsMSGBufDWord counter of bits in one 32 bit long word of the MSGBuff since the number of bits saved in 1 Dword depends on the data length in B of transmitted interleaved packet Word16 0 fl 0 determines the level of frequency 0 component in sampled signal 1 determines the level of frequency 1 component in sampled signal UWordl6 actualSync actual number of errors in comparison with the Header Sync pattern demfsk NewFrmCounter 16 set the condition for next FSK Dem calling if jj amp 1 it is called in the way 17 16 17
50. for subbit A2 demodul 3415 32us 100us bit period bit B of message lt Figure 4 5 Scheme of demfskDem function calling When a given number of bits see 4 3 2 4 State model of the PLM FSK demodulation of the message is received stored in the resulting demfsk_MSGBuf message buffer the PL reception phase is stopped e UWordl16 demState variable is used as a State variable mentioned in 4 3 2 4 4 6 3 CRC calculation The Cyclic Redundancy Code CRC method is used to verify the integrity of every frame sent An additional field is added to every data block at the time of transmission and then it is checked at the time of reception for correctness One of the well known 16 bit CRC polynoms called CRC 16 is used in this Power Line Modem application x16 x154 X2 1 Further mathematical details can be found in 4 IEEE Micro magazine A Tutorial on CRC Computations article in IEEE Micro magazine August 1988 A lookup table computation algorithm has been chosen to implement the CRC calculation A table const UWord16 CRCtable 256 located in CRCtable c file is stored in the data flash memory area The CRC calculation routine taken fromcoderoutines c is as follows DRM035 Rev 0 Designer Reference Manual MOTOROLA Software Module Descriptions 67 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions 4 6
51. from the 14 bit long block 4 6 5 Encryption Decryption The Encryption technigue ensures the security of the transmitted data This PLM board software utilizes The Tiny Encryption Algorithm TEA by David Wheeler and Roger Needham For more information see 6 David Wheeler and Roger Needham TEA a Tiny Encryption Algorithm Computer Laboratory Cambridge University 1994 ftp ftp cl cam ac uk papers djw rmn djw rmn tea html TEA is a Feistel cipher with XOR and and addition as the non linear mixing functions It uses a 128 bit long encryption key stored in pl TeaKey and a 64 bit long temporary buffer called tea IO for calculation This is the reason for the frame length restriction mentioned in 4 2 4 Packet format basics Designer Reference Manual DRM035 Rev 0 70 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com 4 6 6 Interleaving DRMO035 Rev 0 Freescale Semiconductor Inc Software Module Descriptions PLM Implementation The encryption decryption implementation simply divides the whole packet into parts 8 Bytes long performs the encryption decryption over each of these parts and then forms them back to the frame As an example here is a teaEncryptBuff routine taken from the tea c for the reverse decryption approach the principle is analogous void teaEncryptBuff UWordl6 ptr UWordl6 roundLen UWord16 i UWord16 j 1
52. golden ratio Sqrt 5 4 1 2 0 618034 multiplied by 2 32 define y tea IO dw 0 a short cut define for tea IO define z tea IO dw 1 a short cut define for tea IO define k pl TeaKey dw a short cut define for pl TeaKey Designer Reference Manual DRM035 Rev 0 148 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files CRCtable c S EE RR K K KR KR RR RR RRR RK KK kk k k k k k k k ck ck ck kckckckckckckckckckckckckckck ck ck k k k k k k k k ck RR k k ck ck ck ck kk PROTOTYPES x void teaEncryptBuff UWord16 Ptr UWordl6 RoundLen void teaDecryptBuff UWord16 Ptr UWordl6 RoundLen dendif C 15 CRCtable c BRR RRR KR KR KR RR RR RR RK KR kc kc kckckckckck ck ck ck kckckckckckckckck ck ck KR RRR RRR ck ck ck ck ck k k RR RK KKK Motorola Inc c Copyright 2001 Motorola Inc ALL RIGHTS RESERVED
53. k KKK RR k k RR RR RR ck ck ck ck k k 105kHz S EE KK K K k KR RR RR k k RR KK KK KR k k k k k k k k k k RR RK KKK RRR RR RR RR k k k k ck ck ck k const Wordl6 K105 2 DEMFSK FRAMELEN real part imag part FRAC16 1 000000 FRAC16 0 000000 O Designer Reference Manual DRM035 Rev 0 154 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files demfskconst c FRAC16 0 248690 FRAC16 0 968583 1 FRAC16 0 876307 FRAC16 0 481754 2 FRAC16 0 684547 FRAC16 0 728969 3 FRAC16 0 535827 FRAC16 0 844328 4 FRAC16 0 951057 FRAC16 0 309017 5 FRAC16 0 062791 FRAC16 0 998027 6 FRAC16 0 982287 FRAC16 0 187381 7 FRAC16 0 425779 FRAC16 0 904827 8 FRAC16 0 770513 FRAC16 0 637424 9 FRAC16 0 809017 FRAC16 0 587785 10 FRAC16 0 368125 FRAC16 0 929776 11 FRAC16 0 992115 FRAC16 0 125333 12 FRAC16 0 125333 FRAC16 0 992115 13 FRAC16 0 929776 FRAC16 0 368125 14 FRAC16 0 587785 FRAC16 0 809017 15 FRAC16 0 637424 FRAC16 0 770513 16 FRAC16 0 904827 FRAC16 0 425779 17 FRAC16 0 187381 FRAC16 0 982287 18 FRAC16 0 998027 FRAC16 0 062791 19 FRAC16 0 309017 FRAC16
54. k k k k k RR k k k k ck ck KK Designer Reference Manual DRM035 Rev 0 94 Source Code Files For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Source Code Files pl c GLOBAL VARIABLES S EE KK K KR KR KR k k k RRR RR ik kk k kk kk k k k k k k k ck ck ck kckckckckckckckckckckckckckck ck ck k k k k k k k k k k k k k k k k k k k k k KK k k Note that structure type pl uRxFromSCI is used for the RxFromSCI as well as for the TxToPL buffers pl uRxFromSCI pl RxFromSCI Buffer dedicated for SCI reception pl uRxFromSCI pl TxToPL Buffer dedicated for Power Line transmission pl uRxFromPL pl RxFromPL Buffer dedicated for Power Line reception pl uTxToSCI pl TxToSCI Buffer dedicated for SCI transmission volatile pl sFlags pl Flags contains the state and another flags of PL modem device const tea uKey pl TeaKey 1 2 3 4 5 6 7 8 Key for TEA Tiny Encryption Algorithm computation extern of SW FSK Demodulation variable taken from the demfsk c file extern volatile Wordi6 demfsk NewFrmCounter used as a counter in ADCEndOfScanISR extern UWord32 demfsk MSGBuf DEMFSK MSGBUFLEN buffer of received message of FSK demodulation routine
55. noisy and harsh environment like a power line e the output of the algorithm is the transferred message not only a binary signal 4 3 2 2 Main idea of algorithm The DTFT computes a continual frequency function of a given discrete time signal Here the DTFT is used to compute the values Fo and F of the frequency function at 2 discrete points only at frequencies Designer Reference Manual DRM035 Rev 0 48 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions Theory fo and f4 Where fois the frequency of a signal element corresponding to bit O and f is the frequency of a signal element corresponding to bit 1 N 1 N 1 Fo yos em Fi se EQ 4 5 n 0 n 0 where fi f 2n T and n7 EQ 4 6 and s n is the signal element sample f is the sampling frequency By the comparison between Fg and F values it is decided if the signal element transfers a bit with a logical O or 1 value Let s establish a binary vector MSG as the received message Then MSGO Fi Fg EQ 4 7 where jis index of an actual bit element Further tasks are required to establish synchronization to the signal element within the coming FSK signal and to suppress noise influence 4 3 2 8 Synchronization and windowing In correspondence with the rule of digital signal minimal frequency differentiation the signal el
56. on low voltage electrical installations in the frequency range of 3kHz to 148 5kHz Part 1 General requirements frequency bands and electromagnetic disturbances the communication frequencies are allocated as shown in Figure 3 2 North America FCC 100 200 300 400 500 600 700 KHe frequency Dm Band Designations Europe G Bectricity Suppliers CENELEC and Their Licensies 20 4D 60 80 100 120 140 160 kHz fequency Figure 3 2 Regulatory Considerations 3 4 Power Line Modem Architecture Designer Reference Manual Schematics of the PLM board are provided in Appendix B Bill of Materials and Schematics The Power Line Modem block diagram can be seen in Figure B 1 The PLM is a flexible system designed to demonstrate the communication capability through the power line The electrical circuitry can be logically divided into following basic blocks Power Stage amp Coupling module e Output Filter Input Stage e Microcontroller DRMOS35 Rev 0 26 Hardware Description MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Description Power Line Modem Architecture e RS232 interface e Power module 3 4 1 Power Stage amp Coupling module 3 4 1 1 Coupling with the Power Line DRMO035 Rev 0 The coupling network is the interface between the power line and the low voltage transmitter output and receiver input p
57. paden Reference ECC index html but this page is probably no longer available However similar tables can be found for example in above mentioned book const UWord16 FECtableCoder 16 is the look up table dedicated to the FEC encoder e const UWordl16 FECtableDecoder 128 is the look up table of the FEC decoder DRM035 Rev 0 Designer Reference Manual MOTOROLA Software Module Descriptions 69 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions The following piece of code taken from the codeMoveAndFECBuff routine in demfsk c is responsible for the FEC coding for i FRAME PRELEN i lt length FRAME PRELEN i temp pl RxFromSCI Array Byte i gt gt 4 amp Ox0F temp FECtableCoder temp 7 temp FECtableCoder pl RxFromSCI Array Byte i amp Ox0F pl TxToPL Array Byte i temp Fog For FEC decoding the following code is used taken from the codePLtoSCI routine in demfsk c for i 0 i lt FRAME TOTALLEN i FEC Decoder temp FECtableDecoder pl RxFromPL Array Byte i amp 0x3F80 gt gt 7 pl RxFromPL Array Byte i temp lt lt 4 FECtableDecoder pl RxFromPL Array Byte i amp 0x007F To summarize the idea the FEC coding routine replaces the two nibbles of data to be sent by the two 7 bit long blocks taken from the look up table while the FEC decoding generates two nibbles back
58. phase of the mains 2 4 3 Demo configuration There are several possible Power Line Modem connections The most typical one is shown in Figure 2 1 where the End device sits on one side of the communication channel on the other side the Client control terminal or host computer for example personal computer is located Power socket Power socket DC12V for end device pen PLC modem End device Client control terminal Figure 2 1 Scheme of PLM connections For demonstration purposes personal computers with HyperTerminal programs running are used on both sides of the communication channel the first one as an end device while the second one acts as a control terminal For this configuration either one PC with two serial COM ports or two PCs have to be used Designer Reference Manual DRM035 Rev 0 20 Quick Start MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Designer Reference Manual PLM 3 1 Contents 3 2 Introduction DRMO035 Rev 0 3 2 3 3 3 3 1 3 3 2 3 3 3 3 4 3 4 1 3 4 2 3 4 3 3 4 4 3 4 5 3 4 6 3 5 3 6 3 6 1 3 6 2 3 6 3 3 7 Section 3 Hardware Description PEs eshte he s ce a heed Be ped odb bo E Rane war ago ad a 21 Technical Do O O O O O 22 DSP56F801 Processor 22 PLM Board ee 6 60 k oh hx x RR E RR Radon 24 PLM hal rci C P IT na 25 Power Line Modem Archi
59. reject the 50 Hz for more than 80 dB For the frequency band 95 kHz to 125 kHz which is quite wide the quality factor Q of the coupling filter needs to be low Otherwise an unacceptably large attenuation at the band edges would result that would avoid good coupling performances sensitive to a wide range of loads For a band pass filter of this configuration the quality factor is proportional to the reciprocal of the coupling capacitance For low Q the value of C30 needs to be large On the other hand the capacitance should not be too large in order to limit significantly 50 Hz mains current passing through the transformer The coupling capacitor C30 is used to couple the PLM with the power line and it must be a X2 type rated for mains voltage The transformer possesses leakage inductance that can be tuned with the coupling capacitor to form a band pass filter Because the leakage inductance of the transformer 78250 is small 2 uH some external inductance should be added to create a band pass filter Resistor R28 serves to discharge C30 when the device is disconnected from the power line Varistor D9 provides protection against high voltage transients on the power line 3 4 1 2 Modem output voltage The maximum output voltage of a power line modem is defined by the CENELEC norm EN50065 1 and should be 116 dBuV maximum in the frequency range 95 kHz to 148 5 kHz A measurement of the carrier amplitude on a standard CISPR16 load with
60. system that uses the digits 0 through 9 and the letters A through F high byte The most significant eight bits of a word illegal address An address not within the memory map illegal opcode A nonexistent opcode Designer Reference Manual DRM035 Rev 0 170 Glossary MOTOROLA Go to www freescale com Freescale Semiconductor Inc Glossary index registers IX and IY Two 16 bit registers in the CPU In the indexed addressing modes the CPU uses the contents of IX or IY to determine the effective address of the operand IX and IY can also serve as a temporary data storage locations input output I O Input output interfaces between a computer system and the external world A CPU reads an input to sense the level of an external signal and writes to an output to change the level on an external signal instructions Operations that a CPU can perform Instructions are expressed by programmers as assembly language mnemonics A CPU interprets an opcode and its associated operand s and instruction inter IC bus I C A two wire bidirectional serial bus that provides a simple efficient method of data exchange between devices interrupt A temporary break in the sequential execution of a program to respond to signals from peripheral devices by executing a subroutine interrupt request A signal from a peripheral to the CPU intended to cause the CPU to execute a subroutine VO See inpu
61. unit of any computer system The CPU controls the execution of instructions CGM See clock generator module CGM clear To change a bit from logic 1 to logic 0 the opposite of set clock A square wave signal used to synchronize events in a computer clock generator module CGM The CGM module generates a base clock signal from which the system clocks are derived The CGM may include a crystal oscillator circuit and or phase locked loop PLL circuit Designer Reference Manual DRM035 Rev 0 168 Glossary MOTOROLA Go to www freescale com Freescale Semiconductor Inc Glossary comparator A device that compares the magnitude of two inputs A digital comparator defines the equality or relative differences between two binary numbers computer operating properly module COP A counter module that resets the MCU if allowed to overflow condition code register CCR An 8 bit register in the CPU that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed control bit One bit of a register manipulated by software to control the operation of the module control unit One of two major units of the CPU The control unit contains logic functions that synchronize the machine and direct various operations The control unit decodes instructions and generates the internal control signals that perform the requested operations The outputs of the con
62. www freescale com Freescale Semiconductor Inc Source Code Files je OCCS COP amp External interrupts configuration Core freq 80 000 MHz IPBus freq 40 000 MHz COP disabled COP period 838 86 ms External interrupts None define COP TIMEOUT REG OxOfff extern void Start void define INT VECTOR ADDR 1 Start f Quad Timer C2 configuration Count mode No operation Primary count source Prescaler IP BUS clock divide by 1 Secondary count source Counter 0 input pin Input polarity True polarity Output polarity True polarity Input capture mode Capture disabled input edge flag INTdisabled Output capture mode Toggle OFLAG output on succesful compare Count once Count repeatedly Count direction Count up Coinit disabled Master mode disabled Output disabled Interrupts None define QT C2 CONTROL REG 0x1023 define OT C2 COMPARE REG1 0x0027 ee Quad Timer D1 configuration Count mode No operation Primary count source Prescaler IP BUS clock divide by 1 Secondary count source Counter 0 input pin Input polarity True polarity Output polarity True polarity Input capture mode Capture disabled input edge flag INTdisabled Output capture mode Asserted while counter is active Count once Count repeatedly Count direction Count up Coinit disabled Master mode disabled Output disabled Interrupts Compare interrupt define QT D1 CONTROL REG 0x1020 define OT D1 STATUS CONTROL REG 0x4000 extern void tmrfskBitIS
63. x0 x0 pidx 1 add x0 a x r0 x0 add x0 a a pidx pidx 1 pidx 2 move r0 pidx store updated pidx pointer move a tempBit111 store result move rl m01 restore value of m01 nop due to pipelining pMSGBuf 1 MSG result buffer if tempBit111 gt 1 DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 121 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files pMSGBuf 1 write a bit value into Dword MSG tmrfskRxDLEDOn RxD LED control else tmrfskRxDLEDOff RxD LED control numBitsMSGBufDWord if numBitsMSGBufDWord Dword of MSGBuf is full received numBitsMSGBufDWord FRAME TOTALLEN set counter pMSGBuf next Dword of MSGBuf is empty pMSGBuf 0 clears the MSGBuf else eachThird 1 if numBitsReceived FRAME TOTALBITS whole message received demfskStopADCRxFromPL stop PL data sampling stop Rx from the PL side demState 3 whole message received if SB gt gt DEMFSK SAMULTIPLE SA amp amp numBitsReceived FRAME TOTALBITS 4 if noise detected F0 or F1 is not present now demCount if demCount gt 5 if noise detected F0 or F1 was not 5 times present demState 0 break end case 2 end switch asm Update pointer pI
64. 0 Freescale Semiconductor Inc Source Code Files tmrfsk c over the transmission is NOT performed PL TXMASK is a symbolic constant which controls the mask of the PL transmission PL HEADERTXMASK is a symbolic constant which controls the mask of the PL transmission of the Header PL CARRIERLOW and PL CARRIERHGH are symbolic constants describing both carrier frequencies PL FECTYPE is a symbolic constant describing the type of used FEC correction FRAME TOTALLEN is a symbolic constant describing the total length of the whole packet in B to be sent FRAME PRELEN is a symbolic constant describing the length of header part of the packet Arguments None Range Issues Only when pl FlgModeOfModem is equal to STATE4 or STATE5 the PL transmission is performed Rok FF FF F FF HF FF FF X HF F 0X HF F Special Issues None HR KR KKK RR RK KK KR KKK RR RRR RRR RR k k k RR RK pragma interrupt void tmrfskBitISR void static UWordl6 mask mask in array of transmit frame static UWordl6 index index in array of transmit frame static bool txHeader Tx of header part in prograss yes no ioctl QTIMER D1 OT CLEAR FLAG QT COMPARE FLAG ifndef PL NOINTERLEAVING PL Tx with INTERLEAVING if pl FlgModeOfModem STATE4 test Mode of Modem condition pl FlgModeOfModem STATES set Mode of Modem index 0 mask 1 txHeader 1 send Header part now if pl FlgModeOfModem STATES test M
65. 0 929776 FRAC16 0 368125 44 FRAC16 0 309017 FRAC16 0 951057 45 FRAC16 0 968583 FRAC16 0 248690 46 FRAC16 0 187381 FRAC16 0 982287 47 FRAC16 0 992115 FRAC16 0 125333 48 FRAC16 0 062791 FRAC16 0 998027 49 C 18 appconfig h Motorola Inc c Copyright 2000 Motorola Inc ALL RIGHTS RESERVED kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk File Name appconfig h Description file for static configuration of the application initial values interrupt vectors Modules Included o FF FF F FF X HF F F HF F K K RK RR KR KR A A KK ck kckckckckckckckckckckckckck RR RRR RR k k ck ck KK ifndef APPCONFIG H define APPCONFIG H KR RRR kk RRR RR RK KK KR RR kc kckckckckckckckckckckckckckck ck ckckckck ck RR ck k k ck k k kk RADEGAST configuration file generated by Hawk Configuration Tool kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkxk define DSP56F801 define EXTCLK 8000000L DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 159 For More Information On This Product Go to
66. 0 951057 20 FRAC16 0 844328 FRAC16 0 535827 21 FRAC16 0 728969 FRAC16 0 684547 22 FRAC16 0 481754 FRAC16 0 876307 23 FRAC16 0 968583 FRAC16 0 248690 24 FRAC16 0 000000 FRAC16 1 000000 25 FRAC16 0 968583 FRAC16 0 248690 26 FRAC16 0 481754 FRAC16 0 876307 27 FRAC16 0 728969 FRAC16 0 684547 28 FRAC16 0 844328 FRAC16 0 535827 29 FRAC16 0 309017 FRAC16 0 951057 30 FRAC16 0 998027 FRAC16 0 062791 31 FRAC16 0 187381 FRAC16 0 982287 32 FRAC16 0 904827 FRAC16 0 425779 33 FRAC16 0 637424 FRAC16 0 770513 34 FRAC16 0 587785 FRAC16 0 809017 35 FRAC16 0 929776 FRAC16 0 368125 36 FRAC16 0 125333 FRAC16 0 992115 37 FRAC16 0 992115 FRAC16 0 125333 38 FRAC16 0 368125 FRAC16 0 929776 39 FRAC16 0 809017 FRAC16 0 587785 40 FRAC16 0 770513 FRAC16 0 637424 41 FRAC16 0 425779 FRAC16 0 904827 42 FRAC16 0 982287 FRAC16 0 187381 43 FRAC16 0 062791 FRAC16 0 998027 44 FRAC16 0 951057 FRAC16 0 309017 45 FRAC16 0 535827 FRAC16 0 844328 46 FRAC16 0 684547 FRAC16 0 728969 47 FRAC16 0 876307 FRAC16 0 481754 48 FRAC16 0 248690 FRAC16 0 968583 49 W DRM035 Rev 0 Designer Reference Manual MOTOROLA Sour
67. 01 Motorola Inc ALL RIGHTS RESERVED kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk FILE NAME demfsk c DESCRIPTION Source file for the SW FSK demodulator MODULES INCLUDED demfskInit demfskDem demfskEndOfScanISR calcDTFT slidAverage numOnes Eckckckckckckck ck RR RR A KK KK ck k k A k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ck ck kk S EE KK K K k RRR RR k kk k k kk KR k k k k k k k k k k ck ck ck k RR k k KKK KK k k k k k k k k k kk k k k k k k k k k k k k ck ck ck ck k k INCLUDES S EE KKK k k KR k k RR kk k k k k k kk kk kc kckckckckck ck ck ck ck kckckckckckckckckckckckckckck ck k k k k k k k k k k k k k k k ck ck ck ck ck ck ck ck ck kk include types h include arch h include periph h include appconfig h include qtimer h include gpio h include adc h include sci h include demfsk h include tmrfsk h include coderoutines h include pl h undef add Designer Reference Manual DRM035 Rev 0 114 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files demfsk c dundef sub
68. 0x42c0 C 16 FECtable c Freescale Semiconductor Inc Oxcb81 0x1980 Oxdf81 0xd581 0x1380 0x3180 Oxf781 Oxfd81 0x3b80 0xe981 Ox2f80 0x2580 0xe381 0x6180 0xa781 Oxad81 Ox6b80 0xb981 Ox7f80 0x7580 0xb381 0x9181 0x5780 0x5d80 Ox9b81 0x4980 Ox8f81 0x8581 0x4380 0x0b40 0xd941 Ox1f 40 0x1540 0xd341 Oxf141 0x3740 0x3d40 Oxfb41 0x2940 Oxef41 0xe541 0x2340 0xa141 0x6740 0x6d40 Oxab41 0x7940 Oxbf41 Oxb541 0x7340 0x5140 0x9741 0x9d41 0x5b40 0x8941 OxAfA0 0x4540 0x8341 0xc901 Ox1boo0 Oxdd01 0xd701 0x1100 0x3300 Oxf501 Oxff01 0x3900 Oxeb01 0x2d00 0x2700 0xe101 0x6300 Oxa501 Oxaf01 0x6900 Oxbb01 0x7d00 0x7700 Oxb101 0x9301 0x5500 Ox5f00 0x9901 0x4b00 0x8d01 0x8701 0x4100 0x09cO0 Oxdbc1 OxldcO 0x17c0 Oxdicl Oxf3c1 0x35c0 Ox3fcO0 Oxf9c1 0x2bco Oxedcl Oxe7c1 0x21c0 Oxa3cl Ox65c0 Ox6fcO0 Oxa9cl 0x7bco Oxbdc1 Oxb7c1 0x71c0 0x53c0 Ox95c1 Ox9fcl 0x59c0 Ox8bc1 Ox4dcO 0x47c0 0x81c1 0x0880 0xda81 0x1c80 0x1680 Oxd081 Oxf281 0x3480 0x3e80 Oxf881 0x2a80 Oxec81 0xe681 0x2080 0xa281 0x6480 Ox6e80 0xa881 0x7a80 Oxbc81 Oxb681 0x7080 0x5280 0x9481 0x9e81 0x5880 0x8a81 0x4c80 0x4680 0x8081 0xc84 Ox1la4 Oxdc4 Oxd64 0x104 0x324 Oxf44 Oxfe4 0x384 Oxea4 Ox2c4 0x264 Oxe04
69. 0x624 Oxa44 Oxae4 0x684 Oxba4 Ox7c4 0x764 Oxb04 0x924 0x544 Ox5e4 0x984 0x4a Ox8c4 0x864 0x40 OPPOPOOPPOOPOPPOPOOPOPPOOPPOP Source Code Files FECtable c BR RR KR KK KR KR RR RR RR KK KK RRR RK KK RRR RR RR RR RR RR k k k k k FILE NAME t FF FF F FF HF FF HF F F Motorola Inc c Copyright 2001 Motorola Inc ALL RIGHTS RESERVED FECtable c correction codes XFlash data memory area or to internal RAM area DRMO035 Rev 0 MODULES INCLUDED None kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk DESCRIPTION This file contains table of the linear block Forward error Linker command file locates this file either into the 56F801 source or FLASH target in 56F803 source RAM target in 56F803 source Designer Reference Manual MOTOROLA Source Code Files For More Information On This Product Go to www freescale com 151 Freescale Semiconductor Inc Source Code Files BOR KK K K k RRR RRR RRR KK KK KK k k k RRR KKK KKK RR R
70. 16 24 and 32 Range Issues roundLen value has to be a multiple of 8 Special Issues None HR RR RK KKK RK A a KK KA kckckckckckckckckckckckckckck k k RRR ck k k k k k ck kk void teaDecryptBuff UWordl6 ptr UWordl6 roundLen UWord16 i UWord16 j 1 UWord16 backPtr pointer for back transfer backPtr ptr save a pointer do for i 0 i lt 4 i 8bit gt 16bit tea IO w i ptr ptr lt lt 8 just 8bit values at Ptr teaDecode perform an encryption for i 0 i lt 4 i backPtr tea IO w i amp OxOOFF 16bit 8bit backPtr tea IO w i amp OxFF00 gt gt 8 while 8 j lt roundLen the length is a multiple of 8 DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 147 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files C 14 tea h Motorola Inc c Copyright 2001 Motorola Inc ALL RIGHTS RESERVED kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk FILE NAME tea h DESCRIPTION This file is a header file for tea c
71. 16 40 000000 20 FRAC16 0 309017 FRAC16 0 951057 21 FRAC16 0 809017 FRAC16 0 587785 22 FRAC16 0 809017 FRAC16 40 587785 23 FRAC16 0 309017 FRAC16 40 951057 24 FRAC16 1 000000 FRAC16 40 000000 25 FRAC16 0 309017 FRAC16 0 951057 26 FRAC16 0 809017 FRAC16 0 587785 27 FRAC16 0 809017 FRAC16 40 587785 28 FRAC16 0 309017 FRAC16 40 951057 29 FRAC16 1 000000 FRAC16 40 000000 30 FRAC16 0 309017 FRAC16 0 951057 31 FRAC16 0 809017 FRAC16 0 587785 32 FRAC16 0 809017 FRAC16 40 587785 33 FRAC16 0 309017 FRAC16 40 951057 34 FRAC16 1 000000 FRAC16 40 000000 35 FRAC16 0 309017 FRAC16 0 951057 36 FRAC16 0 809017 FRAC16 0 587785 37 FRAC16 0 809017 FRAC16 40 587785 38 FRAC16 0 309017 FRAC16 40 951057 39 FRAC16 1 000000 FRAC16 40 000000 40 FRAC16 0 309017 FRAC16 0 951057 41 FRAC16 0 809017 FRAC16 0 587785 42 FRAC16 0 809017 FRAC16 40 587785 43 FRAC16 0 309017 FRAC16 40 951057 44 FRAC16 1 000000 FRAC16 40 000000 45 FRAC16 0 309017 FRAC16 0 951057 46 FRAC16 0 809017 FRAC16 0 587785 47 FRAC16 0 809017 FRAC16 40 587785 48 FRAC16 0 309017 FRAC16 40 951057 49 BOR RR K K k KR KR k k RR RRR RK k k KR RK ck ck k k k k k k
72. 20pF C29 470nF C30 47nF X2 C38 4 7uF 10V D1 D2 D3 D4 D5 LED 3mm D7 D8 Diode P6KE10A D9 V275LA4 D10 Diode BAV99LT1 D11 D12 D14 Diode 1N4148 F1 Fuse JP1 Connector 2 screws J2 Connector Cannon 9 J3 Header 10x2 J29 Header 10x2 L1 L5 Inductor 0 33mH L2 L3 L6 Inductor 3 3mH L4 Inductor 47uH L102 L103 L104 Ferrite Bead R1 R2 R8 R9 R18 R24 R27 R29 10k R30 R53 R55 R56 R59 R60 R4 R5 100R R6 R7 R11 R20 R50 R54 R112 1k R19 R12 4 7k R16 18k R23 33R DRM035 Rev 0 84 Bill of Materials and Schematics For More Information On This Product Go to www freescale com MOTOROLA DRM035 Rev 0 Freescale Semiconductor Inc Bill of Materials and Schematics Table B 1 PLM 5 board bill of materials Contents R25 100k R26 4 7R R28 1M R45 10M R101 47R 4W S1 Pushbutton T1 Trafo 78250 U1 LF351 U4 TLE2301 U5 MAX3232ECAE U8 MC33269DT_3 3 U20 DSP56F801FA80 U23 74AC00 Y1 Xtal 8MHz Designer Reference Manual MOTOROLA Bill of Materials and Schematics For More Information On This Product Go to www freescale com 85 Freescale Semiconductor Inc Bill of Materials and Schematics Sseuisng e1aua9 SnjelS IdOd S42018 Wld 1 9 enbig BjOIO OW 1UBUAdo9 L002 0 Jequisjdes Aepsunu 3 eqd APON NSQ S0 0 L00180 O LOOMHVIdINNOONLS3LVT MAIN Wid Z01824M4OMDDVO Sx9018 Wid edoung ojgndsy uoaza yd o
73. 29 R30 create a Butterworth second order low pass filter with cut off frequency 110 kHz Capacitor C28 provides a positive feedback path The operation can be described qualitatively e At low frequencies where C22 and C28 appear as open circuits the signal is simply buffered to the output e At high frequencies where C22 and C28 appear as short circuits the signal is shunted to ground at the amplifier s input When f gt gt fc signals are attenuated by 40 dB dec e Near the cut off frequency where the impedance of C22 and C28 is on the same order as R29 and R30 positive feedback through C28 provides Q enhancement of the signal The measured frequency response of the Output amplifier can be seen in Figure 3 5 DRMOS35 Rev 0 30 Hardware Description MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Description Power Line Modem Architecture 5 0 10 0 15 0 20 0 25 0 Gain dB 30 0 35 0 40 0 45 0 T i 1000 10000 Frequency Hz 100000 1000000 Figure 3 5 Frequency Response of the Output Amplifier 3 4 1 4 Transient and Overvoltage Protections 3 4 2 Output Filter DRMO035 Rev 0 The Power stage of the modem has to be protected against many risks of damage mainly due to the direct connection to the mains Some protection against a transient overstress during power up
74. 3 tea c BOR RRR RR KR RR RRR RR KK KR kc kc kckckckckck ck kckckckckckckckckck ck ck ckckck ck ck RR RR RR ck ck ck k k k k k k k k Motorola Inc c Copyright 2001 Motorola Inc ALL RIGHTS RESERVED kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk FILE NAME tea c Designer Reference Manual DRM035 Rev 0 142 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files DESCRIPTION This file contains the complete Tiny Encryption Algorithm TEA implementation MODULES INCLUDED teaCode teaDecode teaEncryptBuff teaDecryptBuff t OR F FF HF FF HF F S EEK K K K k KR k k RR RRR KK KK KK k k RR KKK KR k k k RRR RR k k k k k k k k INCLUDES include pl h include tea h include types h S EE KK K k KR RRR RR RRR
75. 4 FEC calculation Designer Reference Manual Wordi6 codeCRCCalc UWord16 buffer UWord16 n Word16 crc 0 while n crc crc gt gt 8 amp Oxff CRCtable crc buffer amp Oxff return crc The same routine is used for both CRC field computations before the transmission as well as after the data reception The CRC field is generated from the cntrl part and the data part of the packet see 4 2 4 Packet format basics If the received frame is correct the result of the CRC computation of this packet has to be equal to the CRC field that was generated and added to the CRC part of the frame during transmission As mentioned in 4 2 3 Over the data operations basics the Forward Error Correction FEC technique is using added redundancy information in order to correct the errors of transmission During transmission the redundancy data are calculated and added into a data stream while during reception this added information is used for error detection and correction This reference design uses quite a straightforward method of FEC called Linear Block Codes In general block codes break up the data stream into k bit blocks and n k check parity bits are added to these blocks In the literature it is referred as a n k block code A FEC coder outputs a unique n bit codeword v for each of the 2k possible input k bit blocks called messages u on the other hand the FEC decoder generates k bit long de
76. 56F801 Program Memory Map 40 DSP56F801 Data Memory Map cc csc ei cca en eher 40 56 OO 57 DERI eh oer mpra SS EEEE P EO PV 57 I 58 Length of the communication packets 60 BM USAGE Los a oer dr Oed er ed dE ale oleo va OR GR od 63 PLM 5 board bill of materials i 83 Designer Reference Manual MOTOROLA 13 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Tables Designer Reference Manual DRM035 Rev 0 14 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Designer Reference Manual PLM 1 1 Contents 12 1 3 Section 1 Introduction Application intended functionality 44 15 Benefils Of our SOIUNION lt lt s lt a aw A kr ak RR eae es ee 15 1 2 Application intended functionality Power Line Modem PLM is a device designed to communicate through the power line mains This PLM implementation is using the frequency band B of the CENELEC EN 50065 1 regulation frequency band 95 to 125 kHz Device is based on the Motorola DSP56F801 Hawk 1 family and is capable of performing using European 230 V as well as US 110 V voltage FSK modulation technique is used for communication 1 3 Benefits of our solution DRMO035 Rev 0 Both FSK modulation demodulation routines are fully handled by the DSP s w Low cost low speed solution wit
77. 90 18 FRAC16 0 425779 FRAC16 0 904827 19 FRAC16 0 809017 FRAC16 0 587785 20 FRAC16 0 728969 FRAC16 0 684547 21 FRAC16 0 535827 FRAC16 0 844328 22 FRAC16 0 929776 FRAC16 0 368125 23 FRAC16 0 187381 FRAC16 0 982287 24 FRAC16 1 000000 FRAC16 0 000000 25 FRAC16 0 187381 FRAC16 0 982287 26 FRAC16 0 929776 FRAC16 0 368125 27 FRAC16 0 535827 FRAC16 0 844328 28 FRAC16 0 728969 FRAC16 0 684547 29 FRAC16 0 809017 FRAC16 0 587785 30 FRAC16 0 425779 FRAC16 0 904827 31 FRAC16 0 968583 FRAC16 0 248690 32 FRAC16 0 062791 FRAC16 0 998027 33 FRAC16 0 992115 FRAC16 0 125333 34 FRAC16 0 309017 FRAC16 0 951057 35 FRAC16 0 876307 FRAC16 0 481754 36 FRAC16 0 637424 FRAC16 0 770513 37 FRAC16 0 637424 FRAC16 0 770513 38 FRAC16 0 876307 FRAC16 0 481754 39 FRAC16 0 309017 FRAC16 0 951057 40 FRAC16 0 992115 FRAC16 0 125333 41 FRAC16 0 062791 FRAC16 0 998027 42 FRAC16 0 968583 FRAC16 0 248690 43 FRAC16 0 425779 FRAC16 0 904827 44 FRAC16 0 809017 FRAC16 0 587785 45 Designer Reference Manual DRM035 Rev 0 156 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconduct
78. C register holds the address of the next instruction or operand that the CPU will use pull An instruction that copies into the accumulator the contents of a stack RAM location The stack RAM address is in the stack pointer pullup A transistor in the output of a logic gate that connects the output to the logic 1 voltage of the power supply pulse width The amount of time a signal is on as opposed to being in its off state pulse width modulation PWM Controlled variation modulation of the pulse width of a signal with a constant frequency push An instruction that copies the contents of the accumulator to the stack RAM The stack RAM address is in the stack pointer PWM period The time required for one complete cycle of a PWM waveform RAM Random access memory All RAM locations can be read or written by the CPU The contents of a RAM memory location remain valid until the CPU writes a different value or until power is turned off RC circuit A circuit consisting of capacitors and resistors having a defined time constant read To copy the contents of a memory location to the accumulator register A circuit that stores a group of bits reserved memory location A memory location that is used only in special factory test modes Writing to a reserved location has no effect Reading a reserved location returns an unpredictable value reset To force a device to a known condition SCI See
79. CBuff routine see the description of the routine itself PL FECTYPE a symbolic constant describing the type of used FEC correction Arguments None Range Issues None Special Issues None void codeSCItoPL void UWordl6 temp for temp pl RxFromSCI Struct Cntrl temp lt FRAME DATALEN emp pl RxFromSCI Struct Data temp 0 clear the rest of the data CRC calculation 1B of CNTRL Data temp codeCRCCalc amp pl RxFromSCI Struct Cntrl pl RxFromSCI Struct Cntrl 1 CRC is calculated only over the really used data pl RxFromSCI Struct CRC 0 UWord16 OxOOFF amp temp low CRC byte pl RxFromSCI Struct CRC 1 UWordi6 0xFF00 amp temp gt gt 8 high CRC byte ifdef PL TEACRYPT ENCRYPT teaEncryptBuff amp pl RxFromSCI Struct Cntrl FRAME TOTALLEN endif codeMoveAndFECBuff PL FECTYPE FRAME TOTALLEN Move amp perform FEC if required from pl RxFromSCI to pl TxToPL buffer BR K K RK KR KR RRR RRR RR RK kk kk kk kc kckckckckckck ck ck ck kckckckckckckckckckckckckck ck ckckck ck kk kk kk ck kc kc k ck ck ck ck k ck RK RK RK KK Module void codeMoveAndFECBuff UWordl16 fec Mode
80. D1 can alternately TD1 Outp Input be used as GPIOA1 After reset the ut default state is the quad timer input FAULTAO This Fault input pin is used for disabling selected PWMA outputs in FLT Input Input cases where fault conditions originate off chip AN1 AN3 Input Input Analog inputs to ADCA channel 1 AN4 AN7 Input Input Analog inputs to ADCA channel 2 1 More details in chapter 11 of DSP56F801 803 805 807 16 Bit Digital Signal Processor User s Manual 3 4 4 2 In circuit JTAG OnCE Port A standard JTAG pin header connector is present on the PLM board to provide access from a host computer to the JTAG OnCE port signals on the DSP device Table 3 2 shows the required signals It is DRM035 Rev 0 Designer Reference Manual MOTOROLA Hardware Description 35 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Description recommended to use a standard command converter to interface to the JTAG signals and the CodeWarrior tool to download the program Table 3 2 JTAG OnCE Signals Signal Signal Description TDI Test Data Input This input provides a serial data stream to the JTAG and the OnCE module It is sampled on the rising edge of TCK and has an on chip pull up resistor TDO Test Data Output This tri stateable output provides a serial data stream from the JTAG and the OnCE module It is driven in the Shift I
81. EndofScanISR void if 1 version without highpass filter lea sp saving registers move y0O x sp saving registers move r0 xX SP saving registers move m01 x sp saving registers move X addrPXBUF r0 r0 pointer to xBuf buffer moves pxBuf r0 move XBUFLENGTH 1 m01 modulo addressing move X 0x0e89 y0 yO input sample amp ArchIO AdcA ResultReg 0 move yO x r0 input sample to xBuf buffer move r0 x lt addrPXBUF store pointer to xBuf move r0 pxBuf decw x lt addrNEWFRMCOUNTER decw demfsk NewFrmCounter a counter in ADCEndOfScanISR bfset 40x800 x 0x0e86 clear EOSI flag amp ArchIO AdcA ControllReg move x sp m01 restoring registers move x sp r0 restoring registers move x sp yO0 restoring registers rti else version with added highpass filter y n x n x n 1 lea sp saving registers move yO x sp saving registers move r0 xX SP saving registers move m01 x sp saving registers move x addrPXBUF rO0 r0 pointer to xBuf buffer moves pxBuf r0 move XBUFLENGTH 1 m01 modulo addressing Designer Reference Manual DRM035 Rev 0 124 Source Code Files For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Source Code Files demfsk c move X 0x0e89 y0 yO input sample
82. FRAC16 0 770513 18 FRAC16 0 684547 FRAC16 0 728969 19 FRAC16 0 809017 FRAC16 0 587785 20 FRAC16 0 481754 FRAC16 0 876307 21 FRAC16 0 929776 FRAC16 0 368125 22 FRAC16 0 248690 FRAC16 0 968583 23 FRAC16 0 992115 FRAC16 0 125333 24 FRAC16 0 000000 FRAC16 1 000000 25 FRAC16 0 992115 FRAC16 0 125333 26 FRAC16 0 248690 FRAC16 0 968583 27 FRAC16 0 929776 FRAC16 0 368125 28 FRAC16 0 481754 FRAC16 0 876307 29 FRAC16 0 809017 FRAC16 0 587785 30 FRAC16 0 684547 FRAC16 0 728969 31 FRAC16 0 637424 FRAC16 0 770513 32 FRAC16 0 844328 FRAC16 0 535827 33 FRAC16 0 425779 FRAC16 0 904827 34 FRAC16 0 951057 FRAC16 0 309017 35 FRAC16 0 187381 FRAC16 0 982287 36 FRAC16 0 998027 FRAC16 0 062791 37 FRAC16 0 062791 FRAC16 40 998027 38 FRAC16 0 982287 FRAC16 0 187381 39 DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 157 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files FRAC16 0 309017 FRAC16 0 951057 40 FRAC16 0 904827 FRAC16 0 425779 41 FRAC16 0 535827 FRAC16 40 844328 42 FRAC16 0 770513 FRAC16 40 637424 43 FRAC16 0 728969 FRAC16 0
83. FlgModeOfModem STATE7 set Mode of Modem if demState 0 PL reception LED signalization tmrfskCDLEDOff CD LED control tmrfskRxDLEDOff RxD LED control else tmrfskCDLEDOn CD LED control BRR RR KR RRR RR KR RRR RR KR kk kk kckckckckckck ck ck kckckckckckckckck ck ck ck ck ck ck ck k k k k k k k k k k k k k ck ck ck ck ck ck RR RR RK KK Module demfskEndOfScanISR Description ADC A End of Scan ISR Interrupt Service Routine First version reads sample from ADC A and stores it in circular xBuf buffer Second version adds highpass filter saved value y n equal to actual sample x n minus the previous sample x n 1 DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 123 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files Returns None Global Data addrPXBUF symbolic constant address of pxBuf pointer addrNEWFRMCOUNTER symbolic constant address of the demfsk NewFrmCounter variable input samples read from ADC Arguments None Ox A OR OR X F o X Range Issues None Special Issues None addrPREVSAMPLE symbolic constant address of prevSample variable XBUFLENGTH symbolic constant length of xBuf circular buffer of HR KR KK KK RR RR A A KK A A k RR RK RK RR k k k k k k k k k k k k k k k k k k k ck ck k k ck ck ck kk asm void demfsk
84. Freescale Semiconductor Inc ef oye mE digital dna intelligence everywhere Power Line Modem Reference Design Designer Reference Manual 56800 Hybrid Controller Rev 0 03 2003 MOTOROLA COM SEMICONDUCTORS For More Information On This Product Go to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Power Line Modem Reference Design Designer Reference Manual Rev 0 by Zdenek Kaspar Jaromir Chocholac portions by Milan Brejl PhD and Frantisek Dobes MCSL Motorola Czech Systems Laboratories Roznov p Radhostem Czech Republic zdenek kaspar motorola com jaromir chocholac motorola com DRM035 Rev 0 Designer Reference Manual MOTOROLA 3 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Revision history To provide the most up to date information the revision of our documents on the World Wide Web will be the most current Your printed copy may be an earlier revision To verify you have the latest information available refer to http www motorola com semiconductors The following revision history table summarizes changes contained in this document For your convenience the page number designators have been linked to the appropriate location Revision history Revision mee Page Date Level Description Number s January
85. I reception could be started RxFromSCI buffer is ready STATE2 SCI reception in progress STATE3 SCI reception has been finished STATE4 PL transmission could be started TxToPL buffer is ready STATES PL transmission in progress STATE6 PL SCI transmission has been finished STATE7 PL reception has been started STATE8 PL reception in progress FSK demodulation in Demstate 0 waiting until FO or Fl is present STATES PL reception in progress FSK demodulation in Demstate 1 finding synchronization pattern STATE10 PL reception in progress FSK demodulation in D P Designer Reference Manual MOTOROLA Software Module Descriptions 59 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions NOTE Demstate 3 data reception finished STATE12 SCI transmission could be started TxToSCI buff is ready STATE13 SCI transmission in progress UWordl6 DataError 1 Data Error occured in Rx PL frame bad CRC code or bad data length 0 no error 1 error occured pl sFlags If desirable extra application flags can be added by user very easily into this bit array structure const tea uKey pl TeaKey 1 2 3 4 5 6 7 8 is an encryption key for the TEA Tiny Encryption Algorithm computation 4 5 6 Communication parameters Desig
86. IV PL SCIBAUDRATE There is no definition for SCI baudrate value in appconfig h configuration it depends on the global define placed in the pl h file define PL SCIBAUDRATE SCI BAUD 38400 choose SCI BAUD 38400 not tested SCI BAUD 4800 SCI BAUD 9600 SCI BAUD 19200 Enable Interrupts in three steps first set interrupt priorities in Group Priority Registers GPR according to defined ITCN INT PRIORITY xx in appconfig h ioctl ITCN ITCN INIT GPRS NULL second in Interrupt Priority Register IPR enable interrupt channels according to defined ITCN INT PRIORITY xx in appconfig h configure external interrupts according to defined config items in appconfig h ioctl ITCN ITCN INIT IPR NULL third enable maskable interrupts in Status Register SR bits I1 and IO archEnablelInt Enable maskable Level 0 interrupts BR RRR KR KR RRR RR RRR RK KK kk k k k k k k k k ck ck ck ck ckckckckckckckckckckckckckckckckckckck k k k k k kk k k k k k ck k k k ck ck ck ck ck ck k VARIABLES INITIALIZATION BOR RRR KR RK RR RR RRR RR KK k k kk RR k k KK KKK k k RR RRR RR k k k k ck ck KK pl FlgModeOfModem STATEO set mode No operation pl FlgDataError 0 clear the flag demfskInit BRR RRR KR RK RRR RRR KK KK kk k KK ck ck kckckckckckckckckckckckck ck ck RR RR kc kc k ck ck ck ck ck ck RR k k RK RK Module void main DRM035 Rev 0 Designer Reference Manual MOTOR
87. LEN FSK demodulator const of 110kHz extern const Wordl6 K115 2 DEMFSK FRAMELEN FSK demodulator const of 115kHz extern const Wordl6 K120 2 DEMFSK FRAMELEN FSK demodulator const of 120kHz GLOBAL VARIABLES OF THE FILE BRR RR KR KR RRR RR RRR RK k k kk k k k k k k k k ck ck ck kckckckckckck ck k k k k k k k k k k k k k k k k k k k k k k k ck ck ck k k ck ck ck ck kk Wordl6 SA long term sliding average of F0 F1 Wordl6 SB short term sliding average of F0 F1 Wordl6 lambA forgetting factor for long term Wordl6 lambB forgetting factor for short term UWordl6 demState state of demodulation process volatile UWord16 jj step 17 16 17 variable for proper demfsk NewFrmCounter computation UWordl6 pidx pointer to the subbit where the synchronization pattern was detected UWord16 eachThird help counter variable since 1bit of message is derived from 3 subsequent frames subbits UWord32 last24SubBits last 24 received subbits LSB is the newest one it is used for header pattern synchronization Word16 xBuf XBUFLENGTH circular buffer of input samples from ADC xBuf base addr
88. LEN FRAME CNTRLLEN pl sArrayRxFromSCI typedef union complete union of the SCI reception pl sStructRxFromSCI Struct frame AS STRUCTURE of the SCI reception pl sArrayRxFromSCI Array frame AS ARRAY of the SCI reception pl uRxFromSCI DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 103 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files S EE RR RK KR KR k k RR k k ke k k kk KK kk kckckckckckck ck ck ck kckckckckckckckckckckckckckck ck k k k k k k k k k k k k k k k ck ck ck ck ck ck ck ck ck kk typedef struct rame AS STRUCTURE of the PL reception UWord16 Cntrl len UWordl6 Data FRAME DATALEN data part UWord16 CRC 2 2B of CRC low byte first pl_sStructRxFromPL typedef struct frame AS ARRAY of the PL reception UWordl6 Byte FRAME CNTRLLEN FRAME DATALEN pl sArrayRxFromPL typedef union complete union of the PL reception pl sStructRxFromPL Struct frame AS STRUCTURE of the PL reception pl sArrayRxFromPL Array rame AS ARRAY of the PL reception pl uRxFromPL BOR RR RR KR KR KR KR RR RRR RK k k kk kk kckckckckckck ck ck ck ckckckckckckckckckckckckckckck ck ck k k k k k k k k k k k k k k ck ck k k k k ck ck ck ck k typedef struct rame AS STRUCTURE of the SCI transmission UWordl6 Cntrl len UWordl6 Data FRAME DATALEN data part pl sStructTxToSCI typedef struct
89. OLA Source Code Files 99 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files ua else Bad data consistency pl FlgDataError 0 clear flag pl FlgModeOfModem STATE6 set Mode of Modem demfskStartADCRxFromPL start PL data sampling start Rx from the PL side pl FlgModeOfModem STATE7 set Mode of Modem IMPORTANT NOTE Although this condition should be placed here in main loop it is situated at the end of TxToPL and TxToSCI routines because of the main loop speed optimalization if pl FlgModeOfModem STATE6 pl TxToPL or pl TxToSCI finished demfskStartADCRxFromPL start PL data sampling PL reception pl FlgModeOfModem STATE7 set Mode of Modem C 4 pl h Oo FF FF FF F 0X HF F kk Hi kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Motorola Inc c Copyright 2001 Motorola Inc ALL RIGHTS RESERVED FILE NAME pl h DESCRIPTION Header file for Powerline modem main routine pl c MODULES INCLUDED None HR KKK KR KR KR aK ck kck
90. OLA Source Code Files 97 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files Description Main routine of the PowerLine modem project Returns None Arguments None Range Issues None Special Issues None void main void UWord16 temp plProjectInit initializes the core peripherals and variables demfskStartADCRxFromPL start PL data sampling PL reception pl FlgModeOfModem STATE7 set Mode of modem flag S EE RRR KR k KR KR k k RR RR KKK k k kk kk kc k k k k k k k ck ck ck k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ck ck k k ck ck ck ck kk IMPORTANT NOTE S EE KK K K KR KR RR RR RRR kk Sk kk Sk kk Sk kk kc kckckckck ck ck ck ck RRR KK RRR k k k k k k k k k k k k ck ck k k k ck k k ck kk This main loop is very critical because of its speed Call demfskDem routine as frequently as possible while 1 if demfsk NewFrmCounter lt 0 amp amp condition for the SW FSK Demodul pl FlgModeOfModem STATE7 amp amp mode equal to PL reception pl FlgModeOfModem STATE10 demfs
91. OUNTER REG NULL gt PL CARRIERHGH TMRFSK SAFETYRESERVE tmrfskSetCarrierHigh set logical 1 carrier tmrfskTxDLEDOn Set transmit LED indication else current bit is 0 if ioctl QTIMER D2 OT READ COMPARE REG1 NULL PL CARRIERHGH if previous value was logical 1 while ioctl OTIMER D2 QT READ COUNTER REG NULL gt Designer Reference Manual DRM035 Rev 0 64 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions PLM Implementation PL CARRIERHGH TMRFSK SAFETYRESERVE tmrfskSetCarrierLow set logical 0 carrier tmrfskTxDLEDOff Clear transmit LED indication NOTE Anewvalue of the Compare Register 1 of the CarrierTmr is not loaded immediately when the counter is too close to the compare value For this purpose two while conditions are in the code A slight delay less than or equal to 0 75us is added to the bit period 100us for the 10kbps which does not have any negative influence on the result NOTE Avalue of the Compare Register 1 is not modified when the current bit value is equal to the prior one 4 6 2 Demodulation The theory behind the FSK demodulation is given in 4 3 2 FSK demodulation section All FSK demodulation routine can be found in demfsk c and demfsk h files 4 6 2 1 Data sampling The ADCA module is used see 4 5 3 Used DSP per
92. On Chip Core Configuration Registers For a detailed description of the DSP56F801 memory map refer to the DSP58680 1 803 805 807 User s Manual Motorola document order number DSP56F801 7UM D Rev 3 0 Designer Reference Manual MOTOROLA Hardware Description For More Information On This Product Go to www freescale com 41 Freescale Semiconductor Inc Hardware Description Designer Reference Manual DRM035 Rev 0 42 Hardware Description MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Designer Reference Manual PLM 4 1 Contents DRMO035 Rev 0 Section 4 Software Module Descriptions 4 2 4 2 1 4 2 2 4 2 3 4 2 4 4 3 4 3 1 4 3 2 4 4 4 5 4 5 1 4 5 2 4 5 3 4 5 4 4 5 5 4 5 6 4 5 7 4 5 8 4 6 4 6 1 4 6 2 4 6 3 4 6 4 4 6 5 4 6 6 4 6 7 4 6 8 4 6 9 OE 3 jode AGE EU SR cr eta pb kee eae Baers 44 B R yin 44 Application DEBIDO Lau d doped der deiade o Rede ek Ro 44 Over the data operations basics 45 Packet el DaslOB zzz dodo kd c obice odor oae dio on 46 TEO dao adr dd o NOR OR o E d del dod ROE 47 FSK modulation ien nnne roh ram RR OR ERR 47 FSK demodulation MT 48 FSK communication parameters i 53 PLM project introduction uc ac aci k k ek o dk o c 6 54 Coding O ROTY eo o do ed EE eR o V 54 List of the project files iaa ee bk dro deed dca otn 55 Used DSP peripher
93. OnCE interface for in system programming and debugging e RS232 interface for connection to PC or a similar host e Push button for IRQA User defined function e Application dedicated DSP pins accessible via a 20 pin header connector The PLM board is shown in Figure 3 1 Designer Reference Manual DRM035 Rev 0 24 Hardware Description MOTOROLA For More Information On This Product Go to www freescale com iconductor Inc emico Freescale S Freescale Semiconductor Inc Hardware Description Technical Data Figure 3 1 PLM Board 3 3 3 PLM Functionality DRMO035 Rev 0 The PLM is dedicated for use in the low cost Home Interconnectivity market The transceiver meets the regulations for AC mains signalling of CENELEC European Committee for Electrotechnical Standardization FCC Federal Communication Commission and Industry Canada formerly DOC Under FCC Section 15 107 Limits for carrier current systems as well as Industry Canada guidelines communication frequencies are allocated as shown in Figure 3 2 To protect aircraft radio navigation systems that operate between 190kHz and 525kHz restrictions on power line communication above 185kHz have to be considered Designer Reference Manual MOTOROLA Hardware Description 25 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Description In conformity with CENELEC EN 50065 1 Signalling
94. OutISR void define INT VECTOR ADDR 33 tmrfskTimeOutISR define ITCN INT PRIORITY 33 0x0001 m Analog to digital converter A configuration Clock frequency 5 000 MHz Trigger source SYNC input Scan mode Triggered Sequential Sample 0 mapped to ANO zero crossing disabled DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 161 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files Interrupts End of scan define ADC A CONTROL REG1 0x1804 Stop off define ADC A CONTROL REG2 0x0003 define ADC A CHANNEL LIST REG1 0x3210 define ADC A CHANNEL LIST REG2 0x7654 define ADC A SAMPLE DISABLE REG 0x00fe only Sample 0 is enabled define ADC A OFFSET REGO Ox3ffc Offset for signed results extern void demfskEndOfScanISR void define INT VECTOR ADDR 55 demfskEndOfScanISR define ITCN INT PRIORITY 55 0x0005 p Serial communication interface 0 configuration Baud rate Not defined Bd Receiver enabled Transmitter enabled Data word length 8 bits Parity None Polarity True polarity Wake up condition By idle Wait mode function SCI disabled in Wait Mode Loop mode Disabled Interrupts None define SCI 0 CONTROL REG 0x000c SCI Rx Full ISR disabled extern void scicommTxEmpISR void define INT VECTOR ADDR 51 scicommTxEmpISR define ITCN INT PRIORITY 51 0x0001 extern void scicommRxF
95. R RR k k RR k k k k k INCLUDES BRR RR KR KR KR KR RR RRR kk kk k k kk kk kckckckckckck ck ck ck ckckckckckckckckckckckckckckck ck ck k k k k k k k k k k k k k k ck ck k k k ck ck k k kk include types h 4 S EE KK K k KR RR k k RR RRR RK KR KR RK ck ck ck k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ck ck k k ck ck ck ck kk FEC Constants Look up table located at XFlash or XRAM data memory area BR RR K K KR RR KR RR RRR k k kk k k k k k k k k k k k k k ck ck ck ck kckckckckckckckckckckckckckck ck k k k ck k k k k k k k k k k k ck ck ck k k ck ck ck ck kk Linear Block Code taken from the following address http www tisl ukans edu paden Reference ECC linear index html const UWordl6 FECtableCoder 16 hi const UWordl16 FECtableDecoder 128 0x00 0x51 02322 0x23 0x34 0x65 0x46 0x17 0x68 0x39 Ox1A Ox4B Ox5C OxOD Ox2E Ox7F OxO OxO OxO OxA OxO 0x8 0x4 0x9 0x0 0x8 0x1 OxC 0x8 0x8 0x2 0x8 0x0 OxD 0x1 0x9 0x3 0x9 0x9 0x9 0x1 OxB 0x1 0x1 0x5 0x8 0x1 0x9 Hj Ej OO OQ UD 00 JOU A UN Ho 0x0 OxA OxA OxA 0x3 OxE Ox2 OxA 0x6 OxB 0x2 OxA Ox2 0x8 0x2 0x2 Designer Reference Manual 0x3 OxB OXT OxA 0x3 0x3 0x3 0x9 OxB OxB 0x1 OxB 0x3 OxB 0x2 OxF 0x0 OxD 0x4 OxC 0x4 OxE 0x4 0x4 0x6 O
96. R and Shift DR controller states of the JTAG state machine and changes on the falling edge of TCK TCK Test Clock Input This input proves a gated clock to synchronize the test logic and shift serial data through the JTAG OnCE port The maximum frequency for TCK is 1 8 the maximum frequency of the DSP56F801 The TCK pin has an on chip pull down resistor TMS Test Mode Select Input This input sequences the TAP controllers state machine It is sampled on the rising edge of TCK and has an on chip pull up resistor TRST Test Reset This input provides a reset signal to the TAP controller This pin has an on chip pull up resistor 3 4 5 RS232 Interface The PLM board provides an RS 232 interface for connection to PC or a similar host Refer to the RS 232 schematic diagram in Figure B 6 The RS 232 level converter U5 transitions the SCI 3 3 V signal levels to RS 232 compatible signal levels and connects to the host s serial port via connector J2 Flow control is not provided 3 4 6 Power Supply A schematic of the power supply is shown in Figure B 7 Power can be supplied to the PLM board by using an external 12 Vac dc convertor or via the AC DC convertor mounted on the PLM board The power supply provides 12 VDC for analog circuits and 3 3 VDC for the microcontroller and the RS232 interface LED D5 indicates the power on state Designer Reference Manual DRMOS35 Rev 0 36 Hardware Description MOTO
97. R and Timeout ISR MODULES INCLUDED tmrfskBitISR tmrfskTimeOutISR ok FF FF O OR RR O F FF X HF F S EE RRR K k k k k RR k k ke k k kk KKK k k kc kckckckckckck ck ck ck RR RK KKK KR k k k RRR ck ck ck k k ck ck ck ck kk INCLUDES DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 105 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files x include include include include include include include include include include include RRR k kkk x exte exte k Module Descri Return Global Rok FF FF F FF HF FF FF F FF HF HF Xo Designer Reference Manual HK KKK KK a KK kckokckckckckckckckckckck ck RRR RR k k k RR KKK types h arch h periph h appconfig h qtimer h gpio k h sci h tmrfsk h demfsk h coderoutines h pl N h K K KKK k A A k k A k k A Sk k k A k k A k k A k k k k ck ck ck k kckck k kckckckckckckckck k ckckckckck k k k k k k k k k ck k k k k k ck KK GLOBAL VARIABLES HK KK KKK K A k k A k k A KR RK KKK RRR RR
98. R void define INT VECTOR ADDR 31 tmrfskBitISR Designer Reference Manual DRM035 Rev 0 160 Source Code Files For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Source Code Files appconfig h define ITCN INT PRIORITY 31 0x0002 Quad Timer D2 configuration Count mode No operation Primary count source Prescaler IP BUS clock divide by 1 Secondary count source Counter 0 input pin Input polarity True polarity Output polarity True polarity Input capture mode Capture disabled input edge flag INTdisabled Output capture mode Toggle OFLAG output on succesful compare Count once Count repeatedly Count direction Count up Coinit disabled Master mode disabled Output enabled Interrupts None define QT D2 CONTROL REG 0x1023 define OT D2 STATUS CONTROL REG 0x0001 PR Quad Timer D3 configuration Count mode No operation Primary count source Prescaler IP BUS clock divide by 128 Secondary count source Counter 0 input pin Input polarity True polarity Output polarity True polarity Input capture mode Capture disabled input edge flag INTdisabled Output capture mode Asserted while counter is active Count once Count until compare and stop Count direction Count up Coinit disabled Master mode disabled Output disabled Interrupts Compare interrupt define OT D3 CONTROL REG 0xle60 define OT D3 STATUS CONTROL REG 0x4000 extern void tmrfskTime
99. RELEN 1 length of pre control part of packet in bytes 1B of header define FRAME HEADER 0xA5 this is the header of the frame define FRAME CNTRLLEN 3 length of the non data part of packet in bytes 1B of length 2B of CRC dif PL FRAMETYPE SHORT define FRAME DATALEN 13 length of the data part of packet in bytes elif PL FRAMETYPE MEDIUM define FRAME DATALEN 21 length of the data part of packet in bytes delse define FRAME DATALEN 29 length of the data part of packet in bytes endif define FRAME TOTALLEN FRAME DATALEN FRAME CNTRLLEN length of the data and CNTRL part of packet Kif PL FECTYPE PL NOFEC define FRAME TOTALBITS FRAME TOTALLEN 8 total number of bits for Rx delse define FRAME TOTALBITS FRAME TOTALLEN 14 total number of bits for Rx endif S EE KK K KR KR KR KR RR RR RRR KK k k kk RR RK KKK OR k k k RRR RR RR ck ck k k k STRUCTURES BR RR K K KR RK KR RR RR RK KR kk kc k k k k k k k ck ck ck kckckckckckckckckckckckckckck ck k k k k k k k k k k k k k k k ck ck ck ck ckock ck kk kk typedef struct rame AS STRUCTURE of the SCI reception Note that this structure is used also for PL transmission UWordl6 Header FRAME PRELEN header UWordl6 Cntrl len UWord16 Data FRAME DATALEN data part UWord16 CRC 2 2B of CRC low byte first pl sStructRxFromSCI typedef struct frame AS ARRAY of the SCI reception UWordl6 Byte FRAME PRELEN FRAME DATA
100. RK KK KR kk kc kckckckckckck ck ck ck ck kckckckckckckckckckckckckck ck ck k k k k k k k k k k k k k k ck ck k k k k k ck ck ck k PROTOTYPES BR RR K K KR k k RR RRR RK KK k k kc kckckckckckck ck ck ck ckckckck kckckckckckckckckckckckckckckckck ck k k k k k k k ck ck ck ck ck ck ck ck ck RK ck k void teaCode void void teaDecode void S EE RR K K KK k k KR RR RR RK kk k k kk kk k k k k k k k ck ck ckckckckckckckckckckckckckckckck ck k k k k k k k k k k k k k k k ck ck ck k k ck ck ck ck ck k GLOBAL VARIABLES S EE KK K k KR RR KR k k RR KK KK kk kk k k k k k k k ck ck ck kckckckckckckckckckckckckckck ck RRR ck ck k k RK k k ck ck k extern const tea uKey pl TeaKey Key for TEA Tiny Encryption Algorithm computation S EE RRR K k RR k k RRR kk KK k k k kk kk kckckckckckck ck ck ck kckckckckckckckckckckckckckckckck ck k k k k k k k k k k k k k ck ck ck ck ckock ck ck ck ck k LOCAL VARIABLES OF THE FILE S EE RR RR k RR k k RR KR RK KK RK ck ck k k k k k k k k k k k k k k k k k k k k k k kk kk RR ck ck k k ck ck ck ck kk tea uIO tea IO own buffer for TEA computation 64bits long S EE KKK K k KR RK RR k k RR KK KK kk k k k k k k k k ck ck ck ckckckckckckckckckckckckckck ck ck k k k k k k k k k k k k k k k ck kock ck ck ck ck ck ck kk TEA The Tiny Encryption Algorithm authors description S EEK K K k k RR k k RR ck kk kk k k k k kk kk k k k k k k k ck ck ck kckckckckckckckckckckckckckck ck
101. ROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Description Board Layout 3 5 Board Layout A detailed layout plans of the PLM board with the names of all components are shown in Figure 3 9 component side and Figure 3 10 solder side in O O O I enable Figure 3 9 PLM Component Side Layout DRM035 Rev 0 Designer Reference Manual MOTOROLA Hardware Description 37 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Description R29 C28 p18 pyy eL E I k I CJ Al cio Ci R53 TH ras pt ci CI ks L RA C44 cz Ciscy2 Figure 3 10 PLM Solder Side Layout Designer Reference Manual DRM035 Rev 0 38 Hardware Description MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 3 6 Connectors 3 6 1 Expansion Connector J3 Hardware Description Connectors VCC 1 2 MGND TD1 3 4 TDO A5 5 6 A4 A3 7 8 A2 A1 9 10 A0 VA 11 12 GND AN7 13 14 AN6 AN5 15 16 AN4 AN3 17 18 AN2 AN1 19 20 FLT 3 6 2 JTAG OnCE Connector J29 TDI 1 2 GND TDO 3 4 GND TCK 5 6 GND N C 7 8 KEY RESET 9 10 TMS 3 3V 11 12 N C N C 13 14 J_TRST DRM035 Rev 0 Design
102. RRR RR RR ck ck ck ck kk The Tiny Encryption Algorithm TEA by David Wheeler and Roger Needham of the Cambridge Computer Laboratory Placed in the Public Domain by David Wheeler and Roger Needham ftp ftp cl cam ac uk papers djw rmn djw rmn tea html ANSI C VERSION New Variant Authors notes TEA is a Feistel cipher with XOR and and addition as the non linear tea c DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files For More Information On This Product Go to www freescale com 143 Freescale Semiconductor Inc Source Code Files mixing functions Takes 64 bits of data in tea IO dw 0 and dw 1 and returns the 64 bits long result again into tea IO Takes 128 bits of key in k 0 k 3 TEA can be operated in any of the modes of DES Cipher Block Chaining is for example simple to implement n is the number of iterations 32 is ample 16 is sufficient as few as eight may be OK The algorithm achieves good dispersion after six iterations The iteration count can be made variable if required Note this is optimised for 32 bit CPUs with fast shift capabilities It can very easily be ported to assembly language on most CPUs teaDelta is chosen to be the real part of the golden ratio Sqrt 5 4 1 2 0 618034 multiplied by 2 32 This version has been amended to foil two weaknesses identified by David A Wagner dawGcs berkeley edu 1 effective key length of old varia
103. SCI 0 pl FlgModeOfModem STATE3 SCI RX FULL INT SCI DISABLE Source Code Files pl c the COP service sequence routine as frequently as possible condition for the SW FSK Demodul mode equal to PL reception call SW FSK Demodulation routine it is situated because of the main loop pl RxFromSCI buff is full disable interrupt clear flag prepare data from SCI to PL set Mode of Modem switch on the transmitter Start generation of FSK carrier Tx of the carrier before the header and data part transmission total 0 8ms if ioctl SCI 0 SCI GET RX FULL NULL Dummy ioctl SCI 0 SCI READ DATA NULL codeSCItoPL pl FlgModeOfModem STATE4 tmrfskSetTxEnable tmrfskStartCarrierTmr archDelay OxlFFF archDelay OxlFFF archDelay OxlFFF archDelay Ox1FFF tmrfskStartBitTmr IMPORTANT NOTE Although this condition should be placed here in main loop routine because of the main loop speed at the end of demfskDem optimalization if pl FlgModeOfModem STATE11 Z codePLtoSCI if pl FlgDataError 0 pl FlgModeOfModem STATE12 ioctl SCI 0 SCI TX EMPTY INT DRMO035 Rev 0 start FSK transmission it is situated pl RxFromPL finished prepare data from PL to SCI check the data consistency set Mode of Modem SCI ENABLE enable SCI Tx IRQ Designer Reference Manual MOTOR
104. Special Issues None DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 139 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files pragma interrupt void scicommRxFullISR void static UWord16 index UWordl6 temp archPushAllRegisters tmrfskClearTimeOutTmr reset the time out timer if pl FlgModeOfModem STATE1 test Mode of Modem condition pl_FlgModeOfModem STATE2 set Mode of Modem index 0 pl RxFromSCI Struct Cntrl 0 clear the Control of the frame pl RxFromSCI Struct Header 0 FRAME HEADER set header tmrfskStartTimeOutTmr start the time out timer if pl FlgModeOfModem STATE2 test Mode of Modem condition temp ioctl SCI 0 SCI GET STATUS REG NULL pl RxFromSCI Struct Data index ioctl SCI 0 SCI READ DATA NULL index pl RxFromSCI Struct Cntrl index set Length if index FRAME DATALEN the RxFromSCI buffer is full tmrfskStopTimeOutTmr stop the time out timer pl FlgModeOfModem STATE3 set Mode of Modem ioctl SCI 0 SCI RX FULL INT SCI DISABLE disable
105. TA DIRECTION REG 0x0000 where X is GPIO port s endif C 19 linker flash cmd MEMORY pflash RX ORIGIN 0x0000 LENGTH 0x2000 program flash memory pram RWX ORIGIN 0x7C00 LENGTH 0x0400 program ram memory bflash RX ORIGIN 0x8000 LENGTH 0x0800 boot flash memory avail RW ORIGIN 0x0000 LENGTH 0x0030 available cwregs RW ORIGIN 0x0030 LENGTH 0x0010 C temp registrs in CodeWarrior data RW ORIGIN 0x0040 LENGTH 0x02C0 data stack RW ORIGIN 0x0300 LENGTH 0x0100 stack regs RW ORIGIN 0x0C00 LENGTH 0x0400 periperal registers xflash R ORIGIN 0x1000 LENGTH 0x0800 flash memory to place constant and initialized values for data onchip RW ORIGIN OxFF80 LENGTH 0x0080 on chip core configuration registers FORCE ACTIVE FconfigInterruptVector boot start Designer Reference Manual DRM035 Rev 0 164 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc FORCE ACTIVE FK100 FK105 FK110 FK115 FK120 FORCE ACTIVE FprevSample FpxBuf Fdemfsk NewFrmCounter SECTIONS main Application code config c text Startup text Main text rtlib text fp engine text text gt pflash flash booting Boot text gt bflash internal memory 30 OBJECT FprevSample demfsk c OBJECT FpxBuf demf
106. a c Arguments None Range Issues Note that it performs the encryption over the 64 bits so the final buffer to be encrypted should be a multiple of this value Special Issues None okckckckckck ck KR RR A A k k ck ck kckckckckckckckckckckckckckckckck k k k k k k k kk k k k k k ck ck ck k k ck ck ck ck ck k void teaCode void Wordl6 i 32 UWord32 sum 0 while i 0 y t z lt lt 4 z gt gt 5 z sum k sum amp 3 sum TeaDelta z y lt lt 4 y gt gt 5 y sum k sum gt gt 11 amp 3 BOR RR KR KR KR KR KR RR RRR RK KK KR KK ck ck kckckckckckckckckckckckckckckckckckckckckckckckckckckckck ck ck ck ck ck ck RR k k RK RK Module void teaDecode void Description This function perform the TEA decryption over the own 64 bit long buffer Returns None Global Data tea_IO 64bits long buffer for TEA computation y a short cut define for tea_IO dw 0 i z a short cut define for tea IO dw 1 pl TeaKey Key for TEA Tiny Encryption Algorithm computation k 4 a short cut define for pl TeaKey dw 4 x TeaDelta TEA constant chosen to be the real part of the golden ratio Sqrt 5 4 1 2 0 618034 multiplied by 2 32 Arguments None Range Issues Note that it performs the decryption over the 64 bits so the final buffer to be encrypted should be a multiple of this value Special Issues None HR RR KK RR RR RR KK ck ck kckckckckckckckckckckck
107. actor for short term average pbBuf pointer is set to the bBuf circular buffer of decoded subbits from frames calculations pxBuf pointer pointer for saving the ADC samples is set to the xBuf circular buffer of samples read from ADC pInFrame pointer reading data pointer for DTFT calculations is initially set near the xBuf circular buffer of samples read from ADC buffer end pMSGBuf pointer is set to the demfsk MSGBuf buffer of received message of FSK demodulation routine demState state of demodulation process is set to 0 last24SubBits last 24 received subbits is cleared jj step 17 16 17 variable is cleared demfsk NewFrmCounter a counter in ADCEndOfScanISR is cleared pK0Base set base address of the e j Omega0 n coefficients pKlBase set base address of the e j Omegal n coefficients K100 2 DEMFSK FRAMELEN array of FSK dem coefficients for 100kHz K105 2 DEMFSK FRAMELEN array of FSK dem coefficients for 105kHz K110 2 DEMFSK FRAMELEN array of FSK dem coefficients for 110kHz K115 2 DEMFSK FRAMELEN array of FSK dem coefficients for 115kHz K120 2 DEMFSK FRAMELEN array of FSK dem coefficients for 120kHz PL CARRIERLOW and PL CARRIERHGH are symbolic constants describing both carrier frequencies CARRIERLOW 110KHZ10KBPS CARRIERLOW 115KHZ10KBPS CARRIERLOW 120KHZ10KBPS CARRIERHGH 100KHZ10KBPS CARRIERHGH 105KHZ10KBPS and CARRIERHGH 110KHZ10KBPS are symbo
108. actor for short term average demState state of demodulation process as described above pidx pointer is set to the subbit where the synchronization pattern was detected demfsk MSGBuf DEMFSK MSGBUFLEN is a buffer of received message of the FSK demodulation routine pMSGBuf pointer to the demfsk MSGBuf buffer of received message eachThird help counter variable since 1bit of message is derived from 3 subsequent frames subbits pInFrame data reading pointer in xBuf for DTFT calculations For the global data description of the codePLtoSCI routine see the description of the routine itself DEMFSK SAMULTIPLE a symbolic constant describing the multiple of SA sliding average for comparison if SB 2 DEMFSK SAMULTIPLE SA BBUFLENGTH a symbolic constant describing the length of the bBuf DEMFSK SYNCPATTERN is a symbolic constant describing the synchronization STATE10 Designer Reference Manual DRM035 Rev 0 118 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files demfsk c pattern FRAME TOTALLEN a symbolic constant describing the total length in B of transmitted interleaved packet The numBitsMSGBufDWord variable counter of bits in one 32 bit long word uses this constant FRAME TOTALBITS a symbolic constant describing the data length in bits of transmitted packet The numBitsReceived variable
109. al is read by A D converter channel 0 Free pins of the DSP are connected to the Extension Connector J3 for use by an user designed application The External Interrupt Request A IRQA input is dedicated for any user specified purpose It can be programmed to be level sensitive or negative edge triggered The push button S1 is connected to the IRQA pin and it is bridged with capacitor C37 to avoid noise Pushing the button is an input event that results in the generation of an interrupt by the DSP This interrupt can then be used by the program DRMOS35 Rev 0 34 Hardware Description MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Description Power Line Modem Architecture For communication status optical signalling four LEDs D1 D2 D3 D4 are attached to port B The JTAG OnCE interface signals are connected to a JTAG Connector J29 for reprogramming and debugging purpose 3 4 4 1 Extended Signals Table 3 1 Extended Signals Signal Signal Siate During Signal Description Name Type R eset PWMA0 5 Six PWMA output pins Setting an output control enable bit enables software to drive the PWM outputs instead of the PWM generator 1 A0 A5 Output Output Input Timer D Channel 0 TDO can alternately TDO Outp Input be used as GPIOAQ After reset the ut default state is the quad timer input Input Timer D Channel 1 T
110. al to 100 us bit rate is therefore f 10 000 bps e foand f signaling frequencies can be set to these values 100 kHz 105 kHz 110 kHz 115 kHz and 120 kHz e but possible fg and f signaling frequency combinations are only the following since the af condition validity and because of the bandwidth a 100 kHz and 110 kHz with centre frequency f 105 kHz b 105 kHz and 115 kHz with centre frequency 110 kHz c 110 kHz and 120 kHz with centre frequency f 115 kHz lower frequency called f signals the binary 1 value e rough bandwidth calculation Bags is equal to 20 kHz which is an appropriate value for all three chosen centre frequencies f in the CENELEC B band e ADC Analog to Digital Converter sampling frequency f is set to 500 kHz sampling period 7 is therefore 2 us Designer Reference Manual MOTOROLA Software Module Descriptions 53 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions e therefore the length N of the rectangular window is equal to 50 samples 4 5 PLM project introduction This section gives the introductory information and a description of the software part of the Power Line Modem project 4 5 1 Coding convention All source codes were written using several rules and guidelines which make the final product more readable reusable and portable Here is the list of the most important ones File pre
111. ale Semiconductor Inc Source Code Files tmrfsk h C 6 tmrfsk h BOR RRR KR KR KR KR RR RR Sk kk kk k A kckckckckckckck ck ck ck kckckckckckckckckckckckckck ck k k k k k k k k k k k k k k ck ck ck ck ck RR RR KK RK Motorola Inc c Copyright 2001 Motorola Inc ALL RIGHTS RESERVED kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk FILE NAME tmrfsk h DESCRIPTION This file consists of all timer based macro defines needed for i the PL modem It also incorporates the GPIO based macro defines MODULES INCLUDED None HR KR RR KK KR RR RK kk kk kckckckckckck ck ck ck kckckckckckckckckckckckckckck ck k k k k k k k k k k k k k ck ck ck ck ck ck ck RR ck ck kk ifndef TMRFSK H define TMRFSK H BOR KK K KR KR KR k k RRR ck kk Sk KK KK kk kc kckckckck ck k ck ck ck kckckckckckckckckckckckckckck ck ck ck ckck ck ck kk kk RR k k k k ck ck kk INCLUDES include types h include arch h include periph h include qtimer h include gpio h S EE RRR K k KR k k RR RRR KK k k KK k k k k k k RR RK RRR RR RR RRR RR k k k k k k PROTOTYPES S EE KK K K k KK KR RR k k RK KK kk
112. als 56 Used WN k o oN ES r ERa 57 Main variables of the project 58 Communication parameters 60 Linker command file modifications 62 Memory usage 0 63 PLM Implementation i 63 lue M ul PORS RA S O O seemed 63 ele PMP P edi EC ode co oi dedo ood 65 CRO CIUS Lis dud dax dor ted ida est ene anne dica 67 PED calculati n 5 6 0684 45 404 Ole edad aeo 68 Encryption Decryption 226 dde o ive ee ako od de eis 70 71 States of the PL modem 0 72 SCI reception PL transmission phase 74 PL reception SCI transmission phase 76 Designer Reference Manual MOTOROLA Software Module Descriptions 43 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions 4 2 Introduction 4 2 1 Software basics 4 6 10 Buffer details 9 77 4 6 11 Main loop description suse ka sho o RERO RR 79 This section of the reference design provides complete documentation of the Power Line Modem PLM software As described before PLM is a device designed to communicate through the power line mains This implementation of PLM operates in band B of the CENELEC EN 50065 1 regulation in half duplex mode using Frequency Shift Keying FSK modulation and a communication speed equal to 10 kbps The PLM board is based on the Motorola 16 bit Digita
113. amp ArchIO AdcA ResultReg 0 sub x lt addrPREVSAMPLE yO yO actual sample previous sample sub prevSample y0 move yO x r0 input sample to xBuf buffer move r0 x lt addrPXBUF store pointer to xBuf move r0 pxBuf move X 0x0e89 y0 yO input sample amp ArchIO AdcA ResultReg 0 move y0 x lt addrPREVSAMPLE store actual sample move y0 prevSample decw X addrNEWFRMCOUNTER decw demfsk NewFrmCounter a counter in ADCEndOfScanISR bfset 40x800 x 0x0e86 clear EOSI flag amp ArchIO AdcA ControllReg move x sp m01 restoring registers move x sp r0 restoring registers move x sp y0 restoring registers rti endif BRR RR KK RRR RR RR KK KK RK ck kckckckckckckckckckck KK KR RRR RRR kk ck ck ck ck ck ck RR k k KKK Module asm Wordl6 calcDTFT Word16 pCoeff Description Calculation of DTFT coefficient Fi i 0 1 abs Fi 2 sum Input n CoeffReal n sum Input n CoeffImag n for n 0 to 49 2 DEMFSK FSCALE 2 2 DEMFSK FSCALE 2 2 Returns Function returns abs Fi 2 Global Data pInFrame pointer reading data pointer for DTFT calculations to the sample buffer xBuf modulo in xBuf XBUFLENGTH symbolic constant length of xBuf circular buffer of input samples read from ADC DEMFSK FRAMELEN symbolic constant length of frame in samples DEMFSK FSCALE
114. and Schematics For More Information On This Product MOTOROLA Go to www freescale com Freescale Semiconductor Inc Bill of Materials and Schematics Jellld 1ndino g e4n iJ4 sseulsngleleus9 sniejs dOd LOOZ elololoN 1UBU dOJ DRM035 Rev 0 adoin3 ojgndsy uoez yd Aouzou 1 9 957 6001 afew AOUZOY ISOW QNS mano ys Hut 91 tdl 310 2 30 210 XC Ob yo viva Designer Reference Manual MOTOROLA Bill of Materials and Schematics For More Information On This Product 88 Go to www freescale com Freescale Semiconductor Inc Bill of Materials and Schematics Contents Sseuisng EJeuec NSQ S0 0 100180 0 LO0WHVTIdINNOOIUS31VT MIIA Wid 20 82HoIHOMOOVG SnlelS IdO jeeus apels Indul p g a4n61J d L007 eloioloN 3uBu Ado L007 LL 1990190 epsunu ejeq MpoW ea6els ndul 9WeN sl UBiseg 9WeN eweuyos 5elodoodD woer JoUINY edoun3 ojgndsy UoezD yd Aouzo 9 997 6001 afew QN9 ul v1V O 8 8 edl 0L 614 0L dd AOUZOY 1S dd089 89 A440 69 ON Edl AL 024 Huge l 8v NL za MOL 198d U 1 SVL DNL du00 H Wa 19 101 X0 98 400 9 dufe 019 OL 64 AOWANC S v9 2 duo GO Z dugg Huge a jd089 99 LLIG6AVE 010 HuW88 0 V aoo P VA QN9 indur ys VA Designer Reference Manual DRMO035 Rev 0
115. and an overvoltage on the power line is done The fast recovery diodes D7 D8 are used to clamp the surge voltage of the secondary windings and to avoid any stress and reverse voltage at the output pin of the operational amplifier See Figure B 2 The output filter is a simple two stage LC low pass filter with cut off frequency of 110 kHz The schematic of the output stage can be seen in Figure B 3 The filter is created by inductors L5 L6 and capacitors C13 C14 The measured frequency response of the Output Filter can be seen in Figure 3 6 and measured frequency response of the entire Output Stage can be seen in Figure 3 7 Designer Reference Manual MOTOROLA Hardware Description 31 For More Information On This Product Go to www freescale com Designer Reference Manual Freescale Semiconductor Inc Hardware Description Gain dB 10 0 20 0 30 0 40 0 50 0 60 0 70 0 80 0 90 0 0 0 1000 10000 Frequency Hz 100000 1000000 Figure 3 6 Frequency Response of the Output Filter Gain dB 100 0 1 T 0 0 10 0 20 0 30 0 50 0 60 0 40 0 70 0 80 0 90 0 B 1000 10000 Freguency Hz 100000 1000000 Figure 3 7 Freguency Response of the Output Stage DRMOS35 Rev 0 32 Hardware Description MOTOROLA For More Information On This Product Go to www free
116. arrier detection pin S EE KK K K k RRR KR k k RK kk k k k kk kk k k k k k k k ck ck ck k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ck ck ck k k ck ck ck ck kk MACROS BR RR K k KR RR KR RRR RR RK KK k k kk KK k k k k k k k k k KK k k RR k k k RR RR RR k k k k k Timer D1 section define tmrfskStartBitTmr ioctl QTIMER D1 QT WRITE COUNTER REG 0 ioctl QTIMER D1 QT SET COUNT MODE QT COUNT RISING EDGES MODE clear and start the Bit Timing Tmr D1 define tmrfskStopBitTmr ioctl QTIMER D1 QT SET COUNT MODE OT NO OPERATION stop the Bit Timing Tmr D1 Timer D2 section define tmrfskSetCarrierHigh X ioctl QTIMER D2 QT WRITE COMPARE REG1 PL CARRIERHGH switch tmr D2 oscillation to High transmit frequency define tmrfskSetCarrierLow N ioctl OTIMER D2 QT WRITE COMPARE REG1 PL CARRIERLOW switch tmr D2 oscillation to Low transmit frequency define tmrfskStartCarrierTmr N ioctl QTIMER D2 QT WRITE COUNTER REG 0 N ioctl QTIMER D2 QT SET COUNT MODE QT COUNT RISING EDGES MODE clear and start the Carrier Timing Tmr D2 define tmrfskStopCarrierTmr X ioctl QTIMER D2 QT SET COUNT MODE QT NO OPERATION N ioctl QTIMER D2 QT FORCE OFLAG 0 N ioctl QTIMER D2 QT EXT OFLAG FORCE QT ENABLE stop the Carrier Timing Tmr D2 force the OFLAG bit to be logic 0 Timer D3 se
117. c UWord16 Buffer UWord16 n void codeMoveAndFECBuff UWordl6 fec Mode UWord16 Length Designer Reference Manual DRM035 Rev 0 130 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files coderoutines c asm void deintrleave UWord32 pInput UWordl6 pOutput UWord16 numRows UWordi6 numColumns BRR RR KK RR RR RRR RR RK KK kk kk kc kckckckckckck ck ck ck kckckckckckckckckckckckck ck ck k k k k k k k k k k kc kc kc k ck ck ck ck ck ck ck RRR RK KK Module Word16 codeCRCCalc UWord16 buffer UWord16 n Description This function generates the 16 bit CRC 16 15 2 using the following polynom X X X 41 Returns calculated CRC value Global Data CRCtable 256 look up table for 16 bit CRC computation Arguments buffer pointer to buffer to be calculated n length of the buffer Range Issues None Special Issues None Others look up table called CRCTable should be located in XFlash data memory area 56F801 source or FLASH target in 56F803 source or in internal or external RAM data memory area RAM target in 56F803 source Ro FF FF FH FF FF F FF HF HF F FF X HF Ro Xo HR RK RR KK RR RR RR KK ck ck kckckckckckckckckckckckckckck ck RRR RR k k ck ck KK Word16 codeCRCCalc UWord16 buffer UWord16 n Wordl16 crc 0 while n crc crc gt gt 8 amp Oxff return crc CRCtable crc
118. ce Code Files 155 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files S EEK RR k k RR RRR RRR kk KK KK k k kc k k k k k k k ck ck ck kckckckckckckckckckckckck ck ck k k k k k k k k k k k k k k k k ck ck ck k k ck ck ck ck kk 110kHz BR RRR KR KR RR k k RR RR kk kk RR kc k k k k k k k ck ck ck kckckckckckckckckckckckck ck ck ck ck k k k k k k k k k k k k k k ck ck ck ck ck ck ck ck ck kk const Wordl6 K110 2 DEMFSK FRAMELEN real part imag part FRAC16 1 000000 FRAC16 0 000000 O FRAC16 0 187381 FRAC16 0 982287 1 FRAC16 0 929776 FRAC16 0 368125 2 FRAC16 0 535827 FRAC16 0 844328 3 FRAC16 0 728969 FRAC16 0 684547 4 FRAC16 0 809017 FRAC16 0 587785 5 FRAC16 0 425779 FRAC16 0 904827 6 FRAC16 0 968583 FRAC16 0 248690 7 FRAC16 0 062791 FRAC16 0 998027 8 FRAC16 0 992115 FRAC16 0 125333 9 FRAC16 0 309017 FRAC16 0 951057 10 FRAC16 0 876307 FRAC16 0 481754 11 FRAC16 0 637424 FRAC16 0 770513 12 FRAC16 0 637424 FRAC16 0 770513 13 FRAC16 0 876307 FRAC16 0 481754 14 FRAC16 0 309017 FRAC16 0 951057 15 FRAC16 0 992115 FRAC16 0 125333 16 FRAC16 0 062791 FRAC16 0 998027 17 FRAC16 0 968583 FRAC16 0 2486
119. ckckckckck RR ck ck ck ck ck ck ck ck kk void teaDecode void Wordl6 i 32 UWord32 sum OxC6EF3720 sum teaDelta lt lt 5 DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 145 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files in general sum teaDelta n while i gt 0 z y lt lt 4 y gt gt 5 y sum k sum gt gt 11 amp 3 sum TeaDelta y z lt lt 4 z gt gt 5 z sum k sum amp 3 BR RRR KR KR RR RR RRR RK kk kk kk kc kckckckckckck ck ck ck kckckckckckckckckckckckckckckckckckckckckckckckck RR RR k k RK KK Module void teaEncryptBuff UWordl6 ptr UWordl6 roundLen Description This function calls the TEA encryption algorithm and move the data to and back to the temp buffer Returns None Global Data k tea IO 64bits long buffer for TEA computation For the global data description of the teaCode routine see the description of the routine itself Arguments x ptr pointer to the data buffer x roundLen the length of the buffer to be encrypted must be a multiple of 8 this project uses following length values 16 24 and 32 Range Issues roundLen value has to be a multiple of 8 Special Issues None HR RR KK KR RK RR kk kc kckckckckckckckckckckckckckckckck ck kckckckck ck ck ck k k k k k k k k k k k k k k k k k ck ck k k k ck
120. ckckckckckck ck k k k k k k k k k k k k k k k k k k k k k k k k ck ck ck ck k k k ck kk fndef _PL H define PL H S EE KK K K k k k k k RR k ck k KKK k k k k k k k k k k k k k ck ck ck k k k k k k k k k RR k k k k k k k k k k k kk k k k k k k k k ck k k k ck ck ck ck k k INCLUDES S EE KK K K k RK k k RR kk ke kk k k KR kk kc kckckckckck ck ck ck kckckckckckckckckckckckckckck RR RR ck k k k k ck ck ck ck ck k include types h Designer Reference Manual DRM035 Rev 0 100 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files pl h BOR RRR KR KR k k k RRR RR RK KK KK k k k k k k k k k k k ck ck ck kckckckckckckckckckckckckckckckck RR ck ck ck k k ck ck ck ck ck k GLOBAL PL MODEM STATE MACHINE DEFINES S EE KK K K KR KR RR RR RRR RK kk kk k k k k k k k ck ck ck kckckckckckckckckckckckck ck ck ckck k k ck k k k k k k k RR k k ck ck ck ck ck k NOTE These defines are used for the pl FlgModeOfModem variable definition state description of PL Modem Mode define STATEO 0 No operation no communication of modem define STATE1 1 SCI reception could be started RxFromSCI buffer is ready define STATE2 2 SCI reception in progress define STATE3 3 SCI reception has been finished define STATE4 4 PL transmission could be started TxToPL buffer is ready define
121. ckckckckckckckckckckckckckckckckckckckckckckckck kc kc k ck ck ck ck ck ck RR k k RK KK Module void demfskDem void Description This function performs the FSK demodulation routine It processes one frame of data samples saved in xBuf and perform the DTFT Discrete time Fourier transformation calculation over them It determines if samples contain the valid PL data or not There are four possible states of the PL reception stored in demState variable 0 waiting state until FO or Fl frequency components is present FO or Fl present finding the synchronization pattern state 2 synchronization pattern was found data reception state 3 whole message received and saved demState value is cleared immediately to 0 so this state is not treated by switch condition DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 117 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files RR FF FF FF HF HF FF FF HF HF HF HF HF HF FF HF FF HF HF HF HF F FF KF FF HF FF FF HF HF F HF F X HF Ro 0X HF F The resulting message is stored to demfsk MSGBuf variable Note that 1 bit value is calculated from 3 subsequent frames so lets call the demodulation result coming from one frame subbit Returns None Global Data pl Flags flag pl FlgModeOfModem there are 5 possible modes of PL reception Note that these modes are controle
122. coded received sequence u for each of the 2 possible n bit inputs so called received sequences r The following Figure 4 6 Error control coding path gives a graphical explanation of the current chapter DRMOS35 Rev 0 68 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions PLM Implementation Transmitter Encoder Modulator Noise Transmission PENES path Receiver 4 Decoder lt Demodulator Discrete noisy channel Figure 4 6 Error control coding path Added redundancy and therefore the quality of the used FEC technique is defined by the expression 7 4 It means that each codeword has 4 data bits and 3 redundant parity bits The minimal Hamming distance dmin the minimal distance between two codewords of this configuration is dmin 3 Knowing that dmin gt 2t 1 where t is the number of errors that can be corrected the used FEC algorithm is able to correct one bit error in a block of 7bits More details about this topic can be found in 5 Lee Charles Error control block codes for communication engineers Artech House inc 2000 Implementation of the FEC algorithm is based on two look up tables placed in FECtable c file These tables were taken from the http www tisl ukans edu
123. ction define tmrfskStartTimeOutTmr N ioctl QTIMER D3 QT SET COUNT MODE QT COUNT RISING EDGES MODE start the Time Out Timer D3 define tmrfskStopTimeOutTmr ioctl QTIMER D3 QT SET COUNT MODE OT NO OPERATION N ioctl QTIMER D3 QT WRITE COUNTER REG 0x0000 stop the Time Out Timer D3 and write a start value into define tmrfskClearTimeOutTmr ioctl QTIMER D3 QT WRITE COUNTER REG 0x0000 set TimeOut Tmr to a start value D3 GPIO section ifdef DSP56F803 Note that TxEnable output pin control the function of the modem If the PowerLine modem should perform a transmission then pin TxENABLE is cleared and the indication LED is switched on not perform a transmission then pin TxENABLE is set and the indication LED is switched off Designer Reference Manual DRM035 Rev 0 112 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files tmrfsk h See that signal TxEnable is inverted to enable it has to be cleared and vice versa define tmrfskSetTxEnable ioctl GPIO E GPIO CLEAR PIN TXENABLE define tmrfskClearTxEnable ioctl GPIO E GPIO SET PIN TXENABLE Note that TxD output pin is only for signalization If the PowerLine modem transmission data value Tx is logical 1 then pin TxD is cleared to 0 and LED is switched on logical 0
124. d RA URR RES 129 COSI TUMOR DI auda eda ded k Bd dud rdi 137 SOIL 137 SOONG fi ohh noe eRe den 189 RA Ee 142 0212 To cea Eee ae ede UR 142 I oo 148 149 PEL D a uiam ace dede e ko ok di e Me 6 dn da 151 acre s PT 153 CGI 159 lnker EBD cunda eq de a ee career Qd a OP aos 164 DRMOS35 Rev 0 8 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Appendix D Glossary DRM035 Rev 0 Designer Reference Manual MOTOROLA 9 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table of Contents Designer Reference Manual DRM035 Rev 0 10 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Designer Reference Manual PLM DRMO035 Rev 0 List of Figures Figure Title Page 2 1 Scheme of PLM connections 20 2 PLM ROA onsen 25 3 2 Regulatory Considerations lt 26 3 3 The Coupling Network lt oss ned dd dno RE wees 27 3 4 Test set up for output voltage measurement 29 3 5 Frequency Response of the Output Amplifier 31 3 6 Frequency Response of the Output Filter 32 3 7 Frequency Response of the Output Stage 32 3 8 Frequency Response of the Input Amplifier 34 3 9 PLM Component Side Layout 37 3 10 PLM Solder Side Lay
125. d by the demState variable described above STATE7 PL reception has been started S PL reception in progress FSK demodulation in Demstate 0 waiting until FO or Fl is present STATE9 PL reception in progress FSK demodulation in Demstate 1 finding synchronization pattern PL reception in progress FSK demodulation in Demstate 2 data reception STATE11 PL reception in progress FSK demodulation in Demstate 3 data reception finished flag pl FlgDataError modified by codePLtoSCI routine is checked and if set it is cleared demfsk NewFrmCounter a counter in ADCEndOfScanISR set either to 16 or 17 This demfskDem routine is called when this variable is equal to 0 the frame is ready for computation since it is decremented each time the ADCEndOfScanISR routine is performed jj step 17 16 17 variable for proper demfsk NewFrmCounter settings pK0Base base address of the e j Omega0 n coefficients pKlBase base address of the e j Omegal n coefficients last24SubBits each calculated subbit is stored into this variable which is used for the header pattern synchronization pbBuf each calculated subbit is stored into bBuf circular buffer of decoded subbits from frames calculations SA updated long term sliding average of FO F1 is stored here SB updated short term sliding average of FO F1 is stored here lambA constant value of forgetting factor for long term average lambB constant value of forgetting f
126. e Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions endif 4 5 7 Linker command file modifications Several linker command file modifications were done in the original Low level drivers stationary template during development see linker_flash cmd for the whole file listing e look up table variables taken from CRCtable c FECtable c and demfskconst c files are placed in the x 1ash data flash memory area main Application constants consts start Hplace your constants here const c data FECtable c data place constants into the XFlash area CRCtable c data demfskconst c data consts size consts start F Xdata start in ROM gt xflash e 3variables of the demfsk c demfsk NewFrmCounter pxBuf and prevSample are stored in the very beginning of the internal data memory area called avail They are used in the ADCA End Of Scan interrupt service routine demf skEndOf ScanISR The reason why they are placed there is the cycle time reduction internal memory 30 OBJECT FprevSample demfsk c OBJECT FpxBuf demfsk c OBJECT Fdemfsk NewFrmCounter demfsk c gt avail e two circular buffers of the FSK demodulation routine have to be aligned properly in the data memory area ALIGN 0x80 these definitions must be above bss OBJECT FxBuf demfsk c ALIGN 0x80 OBJECT FbBuf demfsk c
127. e packet Although the Cntr value usually carries just the frame length information it can be easily modified when necessary For example an extra application or protocol flags could be added to it Designer Reference Manual DRMOS35 Rev 0 46 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions Theory n length of the data part of the frame N total length of the frame N 2 n 3 Data part 1 n in B CRClow CRChigh Figure 4 2 Format of the packet Since the TEA encryption algorithm is implemented in the Power Line Modem there is a restriction of the total length N of the frame The restriction is the following the total length N must be a multiple of 8 and therefore the length of the data part n is equal to n N 3 For more information see 4 5 6 Communication parameters and 4 6 5 Encryption Decryption NOTE Anextra part called Header is transmitted before each packet it is not shown in Figure 4 2 This extra part of the packet allows the bit synchronization of the FSK demodulation see 4 3 2 3 Synchronization and windowing for more details 4 3 Theory In this section of the reference design document the theory behind the Power Line Modem implementation is given and explained The first part provides the FSK Modulation principles in the second part the FSK Demodulation algorithm is fu
128. eception SCI transmission phase CAUTION Designer Reference Manual The PL reception algorithm pl FlgModeofModem in the range from 7 to 11 shown in Figure 4 8 is detailed in 4 3 2 4 State model of the PLM FSK demodulation When the whole received message is stored in the demfsk MSGBuf buffer pl FlgModeOfModenm 12 the codePLtoSCI routine is called It then performs de interleaving data are moved from the demfsk MSGBuf buffer to pl RxFromPL during this operation see 4 5 5 Main variables of the project FEC decoding if enabled TEA decryption if enabled check the length and the CRC of the received message If there were data consistency errors the received data are then thrown out SCI transmission is omitted pl F1gModeOfModenm set to 6 and PL reception is restarted pl F1gModeOfModen set to 7 otherwise e data are moved to the pl TxToSCI buffer pl FlgModeOfModen is set to 12 SCI Tx Empty IRQ is enabled e when the first SCI Tx ISR occurred pl F1gModeOfModenmis set to 13 and the SCI transmission is in progress e when the whole pl TxToSCI buffer is sent pl FlgModeOfModen is set to 6 and PL reception is restarted pl FlgModeOfModenm is equal to 7 During PL reception pl FlgModeoOfModen in the range from 7 to 11 there should not be any ISR activated except the ADCA End of scan since almost all computation power is consumed by the PL demodulation algorithm This is the reason why there is a cond
129. ed length of the data part of packet is 29 words Note when FEC is OFF just lower 8 bits of the word are used Tf ON lower 14bits of the word carry the data define PL FECTYPE PL 1STFEC choose PL NOFEC PL 1STFEC define PL TEACRYPT 1 if defined perform TEA encryption DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 101 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files define PL TIMEOUTVALUE 1000 define PL COPINUSE Choose the carrier frequencie dif 0 s time out of SCI receive 1000 is tested for SCI BAUD 38400 if defined the Watch Dog is used define PL CARRIERLOW CARRIERLOW 110KHZ10KBPS define PL CARRIERHGH CARRIERHGH 100KHZ10KBPS dendif dif 1 define PL CARRIERLOW CARRIERLOW 115KHZ10KBPS define PL CARRIERHGH CARRIERHGH 105KHZ10KBPS endif dif 0 define PL CARRIERLOW CARRIERLOW 120KHZ10KBPS define PL CARRIERHGH CARRIERHGH 110KHZ10KBPS dendif BOR RRR k k KR k k k RR RR RK KK kk kc kckckckckckck ck ck ck ckckckckckckckckckckckckckckck ck RRR RR ck k k k ck ck ck kk DEBUG DEFINES 2 BRR RR K k RR k k RR RK RK KK KR RR RK KKK RRR RRR RR k k k k KR KK define PL NOINTERLEAVING NOTE only the PL Tx routine if defined the PL transmission didn t perform the interleaving use this define just for testing of PL transmission because it modifies
130. ement length Tis chosen 1 1 f A4 EQ 4 8 to obtain the maximum bit rate Then the number of samples is N feT EQ 4 9 This requirement modifies the equation for the frequency separation Af as defined in 4 3 1 FSK modulation into the form Ar EQ 4 10 DRM035 Rev 0 Designer Reference Manual MOTOROLA Software Module Descriptions 49 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions An incoming signal is windowed by a rectangular window of length N The rectangular window shape and the window length N are necessary to accomplish maximum frequency differentiation Let s establish an index for indexing each signal window and corresponding variables The computation of Fo and F i and the consequential comparison is done for each signal window b i F i gt Fg EQ 4 11 The approximate beginning of the data burst is set from the signal window where the instantaneous value Sp i of a short term sliding average of the Fo and Fy sum crosses the doubled value S i of a long term sliding average of the Fg and Fy sum Sa i 2 S C EQ 4 12 The sliding averages S4 i and Sg i are computed in each step as follows Sali AgSg i 1 1 Ag LFC FI EQ 4 13 if Sali lt 2S i then S4G A4S G 1 L2 A4 F FO EQ 4 14 otherwise the S4 long term sliding average value is not updated S8 5 0 1
131. er Reference Manual MOTOROLA Hardware Description 39 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Description 3 6 3 RS232 Interface Connector J2 N C 1 6 Jumperto 4 Rx 2 7 Jumper to 8 Tx 3 8 Jumper to 7 Jumperto6 4 9 N C GND 5 3 7 Memory Map The DSP56F801 has a dual Harward memory architecture with separate program and data memory spaces Table 3 3 DSP56F801 Program Memory Map From To Size Content 0x0000 0x0003 4 bytes On Chip Boot Flash 0x0004 OxiFFF 8k 4 On Chip Program Flash 0x2000 Ox7BFF 22k Reserved 0x7C00 Ox7FFF 1k Program RAM 0x8000 Ox87FF 2k Boot Flash 0x8800 OxFFFF 30k Reserved Table 3 4 DSP56F801 Data Memory Map From To Size Content 0x0000 OxOSFF 1k On Chip Dual Port Data RAM 0x0400 OxOBFF 2k Reserved 0x0C00 OxOFFF 1k On Chip Peripheral Registers 0x1000 0x17FF 2k On Chip Flash 0x1800 0x1 FFF 2k Reserved Designer Reference Manual DRM035 Rev 0 40 Hardware Description MOTOROLA For More Information On This Product Go to www freescale com DRMO035 Rev 0 Freescale Semiconductor Inc Hardware Description Memory Map Table 3 4 DSP56F801 Data Memory Map 0x2000 OxFFF7F 56k 128 Not supported external memory access OxFF80 OxFFFF 128bytes
132. erials and Schematics For More Information On This Product Designer Reference Manual 90 Go to www freescale com Freescale Semiconductor Inc Bill of Materials and Schematics Contents aoejialul ZEZSU 9 g eJnBiJ sseuisng Ejeuec SnjelS IdOd 100Z e101010W 1UBuAdo3 jeeus 100Z EZ 190000 Aepsen eie APON NSQ S0 0100150 081O0WHVIdNNOOIS3LVT MIIA Wid Z01874M4OMDDVA OWEN lld uBiseq ZETSU 3WwWeN oheuedoS DE OUDOUJ JIWOJer JOUINY edon3 olqndey uoezo d Aouzoy 19 9G 600 efeu AOUZOY TSON xL xy GNOW 4uool AVOACECEXVN SEO deu OL L NILL EEE rho LNOLY 9 pe ee LNOLL vb ano E pu Pon z O 9L Ju001 cc JU00 Zeo SN 0 LED Merl Designer Reference Manual DRMO035 Rev 0 91 Go to www freescale com Bill of Materials and Schematics For More Information On This Product MOTOROLA Freescale Semiconductor Inc Bill of Materials and Schematics Jemod 9 a1nbi4 sseulsnglelesus9 SNjelS dOd LOOZ elololoN JUBUAdOD edoun3 ollqndey UoezD yd Aouzos 19 987 600 afew OUZOH ISON Uonoeuuo punos anon ee LOGELIN Jamo A9V3nee 9 9 Qv38 318334 Nee CLLOL dl WaLNAN 8r NI A9Hdng8 va Mylaly 819 LOY Qv38 31833 DRMOS35 Rev 0 Designer Reference Manual MOTOROLA Bill of Materials and Schematics For More Information On This Product 92 Go to www freescale
133. ess must be multiple of 2 k defined in linker command file UWordi16 bBuf BBUFLENGTH circular buffer of decoded subbits from frames calculations bBuf base address must be multiple of 2 k defined in linker command file Wordl6 pxBuf pointer to the xBuf buffer used when sample read DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files from ADC is stored to xBuf UWordl6 pbBuf pointer to the bBuf buffer Wordl16 pK0Base base address of the e j Omega0 n coefficients Wordl6 pKlBase base address of the e j Omegal n coefficients Wordl6 pInFrame pointer reading data pointer for DTFT calculations to the sample buffer xBuf modulo in xBuf Wordl6 prevSample previous input sample UWord32 pMSGBuf pointer to the MSGBuf buffer BOR K K RRR RR KR RR ck RK KK KK ck kckckckckckckckckckckckck ck ck k k k k k k k k k k k kc kck ck ck ck ck ck ck RR k k RK KK Module void demfskInit void Description Initialization of FSK demodulation Returns None Global Data SA set initial value to long term sliding average of F0 F1 SB set initial value to short term sliding average of FO F1 lambA set const value to forgetting factor for long term average lambB set const value to forgetting f
134. etic is convenient in digital circuit design because digital circuits have two permissible voltage levels low and high The binary digits O and 1 can be interpreted to correspond to the two digital voltage levels binary coded decimal BCD A notation that uses 4 bit binary numbers to represent the 10 decimal digits and that retains the same positional structure of a decimal number For example 234 decimal 2 0010 0011 0100 BCD bit A binary digit A bit has a value of either logic O or logic 1 branch instruction An instruction that causes the CPU to continue processing at a memory location other than the next sequential address break module The break module allows software to halt program execution at a programmable point in order to enter a background routine breakpoint A number written into the break address registers of the break module When a number appears on the internal address bus that is the same as the number in the break address registers the CPU executes the software interrupt instruction SWI break interrupt A software interrupt caused by the appearance on the internal address bus of the same value that is written in the break address registers bus A set of wires that transfers logic signals bus clock See CPU clock byte A set of eight bits CAN See Motorola scalable CAN CCR See condition code register central processor unit CPU The primary functioning
135. fix is used in each identifier that is used globally it gives a very quick cross reference mechanism from identifier to definition and implementation variables are named in the form fileprefix NameOfVar for functions the form is ileprefixNameOfFunc fora symbolic constant the form is FILEPREFIXCONST all written in upper case e Special prefix characters are used to further identify attributes associated with the type being specified sg for struct type u for union type p for pointer variable All advantages mentioned above are also ensured by using the Low level drivers architecture dependent routines and on chip peripheral drivers The general form of the Low level drivers command is the following ioctl peripheral module identifier command command Specific parameter Designer Reference Manual DRM035 Rev 0 54 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions PLM project introduction This approach makes the final source code even more readable and also shortens development time 4 5 2 List of the project files Here is a list of all source code files of the Metrowerks CodeWarrior project DRMO035 Rev 0 pl c contains the periphery initialization global variables declaration and the main PLM routine pl h is theheader file of the main PLM routine it contai
136. h and CRC values and finally move the pl RxFromPL to the pl TxToSCI buffer Returns None Global Data For the global data description of the deintrleave routine see the description of the routine itself demfsk MSGBuf buffer of received message of FSK demodulation routine pl RxFromPL is a buffer of received data from the PL side FECtableDecoder table of the decoding part of the linear block Forward error correction For the global data description of the teaDecryptBuff routine see the description of the routine itself pl Flags flag pl FlgDataError is set if either CRC or length error occured FRAME TOTALLEN a symbolic constant describing the total length of the whole packet in B to be sent PL FECTYPE a symbolic constant describing the type of used FEC correction PL NOFEC and PL 1STFEC symbolic constants defining the type of used FEC coding PL TEACRYPT a symbolic constant if defined the Tiny Encryption is processed over the packets FRAME DATALEN a symbolic constant describing the data length in B of packet Arguments None Range Issues None Special Issues None Others look up table called FECtableDecoder could be located in XFlash data memory area 56F801 source or FLASH target in 56F803 source or in internal or external RAM data memory area RAM target in 56F803 source
137. h baudrate 10 kbps Communication according to the CELENEC EN 50065 1 Signaling on low voltage electrical installations in the frequency range 3 kHz to 148 5 kHz regulation Transmitted data encrypted by Tiny Encryption Algorithm Data consistency is secured by FEC Forward Error Correction 16 bit CRC Cyclic Redundancy Check and interleaving technigue Designer Reference Manual MOTOROLA Introduction 15 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Introduction Designer Reference Manual DRM035 Rev 0 16 Introduction MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Designer Reference Manual PLM 2 1 Contents 2 2 Introduction DRMO035 Rev 0 Section 2 Quick Start 17 2a Mam PLM TioatyreS na 18 24 PLM demonstratiOn oe a k Eod eoe dee deba s 18 2 4 1 HyperTerminal settings iasasenisekerkrkbrbx ua n dd RC as 19 2 4 2 Connecting the PLM boards to the PC 19 2 4 3 Demo conii dI ico c dere eee od keel SCR end 20 In this reference design a complete description of software and hardware of the Power Line Modem PLM based on the DSP56F801 is given The PLM board is a hardware platform of the Power Line Modem reference design The PLM is a device designed to communicate through the power line mains DSP56F801 is a member of Motorola s Hawk V1 family of 16 bit Dig
138. hen it is not transmitting The TLE2301 amplifier has a 1 A output drive capability with short circuit protection Hence it carries out the requirements The TLE2301 incorporates an output 3 state facility and in addition it has a low standby current in the 3 state mode The Frequency Shift Keying FSK modulated output signal is created by the general DSP output in form of a square wave signal To meet CENELEC regulation some filtering has to be done to convert the signal to a sine wave From the harmonics point of view only odd harmonics are contained in the square wave signal Any frequency components above transmission band must be eliminated by a low pass filter The attenuation of the third harmonic must be more than 56 dB to meet Designer Reference Manual MOTOROLA Hardware Description 29 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Description Designer Reference Manual CENELEC regulation Concerning this fact we need a low pass filter with an attenuation slope of 120 dB dec The chosen solution is to use a two stage passive LC low pass filter 80 dB dec and output amplifier as an active second order low pass filter 40 dB dec in cascade The schematic of the output stage can be seen in Figure B 2 The output passive LC low pass filter is described in section 3 4 2 The output amplifier U4 and external components capacitors C22 C28 and resistors R
139. ic 1s odd for odd parity or even for even parity A parity checker in the receiver counts the number of logic 1s in each byte The parity checker generates an error signal if it finds a byte with an incorrect number of logic 1s PC See program counter PC peripheral A circuit not under direct CPU control phase locked loop PLL A clock generator circuit in which a voltage controlled oscillator produces an oscillation which is synchronized to a reference signal PLL See phase locked loop PLL pointer Pointer register An index register is sometimes called a pointer register because its contents are used in the calculation of the address of an operand and therefore points to the operand polarity The two opposite logic levels logic 1 and logic 0 which correspond to two different voltage levels Vpp and Vss polling Periodically reading a status bit to monitor the condition of a peripheral device port A set of wires for communicating with off chip devices prescaler A circuit that generates an output signal related to the input signal by a fractional scale factor such as 1 2 1 8 1 10 etc program A set of computer instructions that cause a computer to perform a desired operation or operations DRM035 Rev 0 Designer Reference Manual MOTOROLA Glossary 173 Go to www freescale com Freescale Semiconductor Inc program counter PC A 16 bit register in the CPU The P
140. in the frequency range 3 kHz to 148 5 kHz 1991 It operates in half duplex mode using a Frequency Shift Keying FSK modulation with a communication speed of 10 kbps For more information regarding this topic see 4 4 FSK communication parameters and 4 5 6 Communication parameters 2 4 PLM demonstration Designer Reference Manual In this section the connection and startup of the Power Line Modem PLM board demo application is described PLM serves as a transparent channel This means that data coming in from the SCI Serial Communication Interface module are received formatted to a packet or frame processed and then sent to the mains power line For return communication the process is analogue This means that the only thing needed for the PLM demonstration is the controlled dataflow of the serial data The easiest way is to use two HyperTerminal programs since this is a standard part of the MS Windows Microsoft and Windows are registered trademarks of Microsoft Corporation The settings for HyperTerminal for this kind of demonstration can be found in 2 4 1 HyperTerminal settings DRMOS35 Rev 0 18 Quick Start MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Quick Start PLM demonstration On the other hand there are a lot of other possibilities which can be used One of the most exciting is a system like emWare s Embedded Micro Interworking Techn
141. including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA Motorola and the Stylized M Logo are registered in the U S Patent and Trademark Office digital dna is a trademark of Motorola Inc All other product or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 2003 DRM035 D For More Information On This Product Go to www freescale com
142. indication if mask PL TXMASK mask 1 index else mask lt lt 1 endif else end of frame tmrfskClearTxEnable Disable the transmit amplifier tmrfskStopCarrierTmr Stop the carrier generation Tmr tmrfskStopBitTmr Stop the Bit period Tmr tmrfskTxDLEDOff set initial pin value archDelay OxlFFF wait a while after the transmission archDelay OxlFFF in order to settle the line pl FlgModeOfModem STATE6 set Mode of Modem demfskStartADCRxFromPL start PL data sampling PL reception pl FlgModeOfModem STATE7 set Mode of Modem BRR RR RK RR KR RR RRR KK kk kk kc kckckckckckck ck ck ck kckckckckckckckckckckckckckck ck ckckck ck k k k k k k k k k ck ck ck ck ck RR RR KR KKK DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 109 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files Module void tmrfskTimeOutISR void Description Returns None Global Data codeSCItoPL be started Arguments None Rok FF FF F FF HF HF F HF HF F FF X HF F Xo Range Issues None Special Issues None This function is the ISR of the TimeOut Timer TmrD3 It generates the timeout to indicate that the SCI reception was stopped before fulfilling the whole SCI Rx buffer It simply gives the order to stop the SCI reception and start the PL transmission part
143. ins of the modem For low cost applications when the insulation with the mains is not required a double LC network can be used For home applications where insulation is mandatory then an HF transformer should be used Apart from the insulation with the power line the transformer has also to perform the appropriate filtering for both the transmission and the reception The Newport s 78250 converter transformer can be used for this application The basic coupling network can be seen in Figure 3 3 PHASE F1 E Tr_78250 Fuse D9 V275LA4 C30 47uH 47nF X2 T1 Figure 3 3 The Coupling Network To provide an efficient transmission coupling a 1 1 winding ratio is used An extra LC serial filter is needed to provide rejection of unexpected harmonics in order to comply with standards In fact the behavior of the 1 1 winding is mainly a high pass filter and does not provide efficient filtering of high frequency harmonics In reception mode the 1 1 winding ratio fitted with the tuning capacitor provides a high pass filter with an efficient rejection of the 50 Hz signal For instance the 50 Hz amplitude is 230 V rms or 167 dBuV and the Designer Reference Manual MOTOROLA Hardware Description 27 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Description maximum sensitivity of the modem is 80 dBuV To take advantage of the detection performance the filter must
144. interrupt ioctl SCI 0 SCI RX ERROR INT SCI DISABLE disable interrupt codeSCItoPL prepare data from SCI to PL pl FlgModeOfModem STATE4 set Mode of Modem tmrfskSetTxEnable switch on the transmitter tmrfskStartCarrierTmr start generation of FSK carrier archDelay OxlFFF Tx of the carrier before the archDelay OxlFFF header and data part transmission archDelay OxlFFF total 0 8ms archDelay Ox1FFF tmrfskStartBitTmr start FSK transmission archPopAllRegisters BOR K K RK KR KR RR RR RRR KK KK kk kk kckckckckck ck ck ck kckckckckckckckckckckckckck ck A k k k k k k k k k k k kk ck ck ck ck k ck RR k k RR RK Module void scicommTxEmpISR void Description This function is the ISR of the SCI Transmitter empty It sends the Designer Reference Manual DRM035 Rev 0 140 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Rok FF FF F FF HF FF FF HF HF F X HF F Freescale Semiconductor Inc Source Code Files scicomm c data part of packet The length of data part is taken from the pl TxToSCI variable itself Returns None Global Data pl Flags flag pl FlgModeOfModem if the Mode was set to STATE12 SCI transmission could be started the SCI Tx is Started and mode is switched to STATE13 SCI transmission in progress When whole packet was transmitted the mode is set to STATE6 PL
145. ion style macro the BitTmr QTimer D1 see 4 5 3 is enabled for the bit rate generation during the PL transmission Please notice that the interleaving is implemented in this part of the code as mentioned in 4 6 6 tmrfskBitISR routine of the BitTmr see 4 6 1 Modulation is used during the PL transmission of the pl TxToPL data buffer pl FlgModeOfModenm 5 when the whole pl TxToPL buffer is sent transmission is finished tmrfskClearTxEnable switches off the transmit amplifier tmrfskStopCarrierTmr stops the CarrierTmr timer tmrfskStopBitTmr stops the BitTmr timer pl FlgModeOfModenmis set to 6 then by calling the demfskStartADCRxFromPL function style macro the PL data sampling whole PL reception is started as shown in Figure 4 8 State diagram of the Power Line Modem The pl FlgModeOfModenm variable value is set to 7 A delay included before the PL transmission is necessary for the proper data demodulation on the reception side The algorithm can be easily rewritten by the user when necessary using the current state diagram structure Most probably a built in application itself would generate the data for PL transmission in such a case the SCI reception routines would be omitted Designer Reference Manual MOTOROLA Software Module Descriptions 75 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions 4 6 9 PL r
146. ipherals for more details for data sampling during the PL reception phase It is triggered by the TriggerTmr therefore the ADC module samples each 2 us with the End of scan interrupt enabled EOSIE bit set The ADCA demf skEndof ScanISR routine stores the analog values of its ANO pin into a dedicated xBuf circular buffer and also decrements the demfsk_NewFrmCounter counter variable see 4 5 5 Main variables of the project NOTE There are two versions of the demf skEndOfScanISR function made by conditional compilation The first one as described in the previous paragraph is used in the project and therefore primary recommended The second one adds a highpass filter in the form y n x n x n 1 to the functionality of the former one Although it is probably not so suitable for such a well filtered input signal as is present in this PLM board design DRM035 Rev 0 Designer Reference Manual MOTOROLA Software Module Descriptions 65 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions see 3 4 3 Input Stage according to the tests it is possible to use it as well 4 6 2 2 Demodulation algorithm As shown in the code listing containing the demodulation part of the main loop from pl c file the demodulation routine demfskDem is called when the demfsk NewFrmCounter variable crosses a value of zero while 1 if demfsk_NewFrmCounter lt 0 am
147. ital Signal Processors DSP The result of this reference design is a protocol independent media access interface for the connection of different devices coupled through a power line The functionality of the PLM design is demonstrated by the provided application demo stored in the internal FLASH memory of the DSP Beyond that the PLM board enables the implementation and testing of the user software For this purpose the board is equipped with a JTAG OnCE interface for flash reprogramming and debugging In Section 2 a brief introduction to the project is given together with a description of the connection and startup of the Power Line Modem demo application Section 3 details the PLM board as the hardware part Designer Reference Manual MOTOROLA Quick Start 17 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc of an implementation of the PLM design A full scale description of the PLM software is presented in section 4 In section 5 a bill of materials and schematics of the PLM board is given and finally in section 6 the complete source code of the PLM can be found 2 3 Main PLM features This chapter describes some of the most important features and parameters of the designed solution The Power Line Modem presented in this reference design operates in the band B of the CENELEC EN 50065 1 regulation see 3 CENELEC EN 50065 1 Signaling on low voltage electrical installations
148. ition testing of the SCI Receiver Data Register Full Flag bit RDRF in the main loop see 4 6 11 Main loop description DRMOS35 Rev 0 76 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions PLM Implementation 4 6 10 Buffer details In the following figure detailed parameters of the used communication buffers such as ranges options can be found For more information see also 4 5 5 Main variables of the project 4 5 6 Communication parameters and also 4 6 6 Interleaving DRMO035 Rev 0 Designer Reference Manual MOTOROLA Software Module Descriptions 77 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions T 14 bits with FEC 8 bits lt gt no FEC A1 B1 pl TxToPL buffer array of words 16 24 32 depending on chosen length of the frame Vv PL transmission Vv PL reception 16 24 32 depending on chosen length of the frame 1 Jl yl HM VE Vy hyd yl Ly ly NN U YYYY direction of transmission due to the interleaving start mains B1A1 demfsk MSGBuf buffer array of dwords Vv de interleaving routine 14 bits with FEC m array of words
149. itrogduectiom O O R O EARR 17 Main PLM Ieaturee p ak v ac po a ERG Roa 18 PLM demonstration de dd ko de ode e o 18 Section 3 Hardware Description rojo PCM 21 COUN qu d o eae RRR d Rd oc RR RICE 21 Technical Dala cuaderno ode eR cede eee eee CR 22 Power Line Modem Architecture i 26 Board Davo 44 idocb ee OP Oboe o Re ed 37 39 Memory Map cis odes Oh cb dO dock FER HORE OR de God 40 Section 4 Software Module Descriptions 43 Ds 2 ed ox rn dU adeat Doce Red dob ak ke ew ace bdo 44 Designer Reference Manual MOTOROLA 7 For More Information On This Product Go to www freescale com Designer Reference Manual Freescale Semiconductor Inc Table of Contents 4 3 4 4 4 5 4 6 B 1 C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 C 9 C 10 C 11 C 12 C 13 C 14 415 C 16 C 17 C 18 C 19 TACO bua aa dos ck a ha ot at e dc i ksh der ing chee ds o Mode d 47 FSK communication parameters L 53 PLM project introduction a aae e doma madd ado cs 54 PLM Implementation sade Chee eed Rer k i eee R Rd 63 Appendix A References Appendix B Bill of Materials and Schematics 83 omene ome ea 93 93 DLE ah PR EMP PO debba ci eir L aH dE ddr cde dod oe Qo 94 2 PPOR NY MP K V O P a E RE 100 IRI PP E RERO eR E PP dba Rari eR P 105 HESS a VE V o EE eS ee KEE eee O E 111 11 114 UTE Doa id dd d COD UR RR OR EA EQ e e e d ON rand 128 coderoutines c n de RR RRA
150. k KKK KK RR KKK KK k k k RRR RR k k k k k k RK void tmrfskBitISR void void tmrfskTimeOutISR void BRR RR K k RR k k kk kk kk k k kk kk kc kckckckckckck ck ck kckckckckckck ck kckckckckckckck ck k k k k k k ck k k k k ck k ck ck ck ck k k ck ck k k ck kk PL Transmission And Baudrate Speed Defines define TMRFSK 10000BPS 4000 1 10000pbs define TMRFSK 19200BPS 2084 1 19200pbs define TMRFSK SAFETYRESERVE 30 BOR RRR k k RRR RRR ck kk kk k k k k kk k k k k k k k ck ck ck kckckckckckckckckckckckckckckck ck ck k k k k k k k k k RR k k ck ck ck kk k GPIO Mapping Defines BOR KK K k k k RR KR KR RRR KK k k kk kc kckckckckckck ck ck ck ckckckckckckckckckckckckckckck ck k k k k k k k k k k k k k k k ck ck ck k k k ck k k ck k define TXENABLE 0x0010 bit No 4 transmission disabled enabled pin define TXD 0x0020 bit No 5 transmission data pin DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 111 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files define RXD 0x0040 bit No 6 reception data pin define CD 0x0080 bit No 7 c
151. k ck ck ck RR RR KK KK Motorola Inc c Copyright 2001 Motorola Inc ALL RIGHTS RESERVED kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk FILE NAME coderoutines h DESCRIPTION A header file for coderoutines c MODULES INCLUDED None HR RK KR RR RR RR a k k ck ck kckckckckckckckckckckckck ck ck k k k k k k k k k k k k k k k k k ck ck k k ck ck ck ck kk ifndef CODEROUTINES H define CODEROUTINES H S EE KK K k k k KR k RR RR RR k k k k kk k k k k k k k k k ck ck ck RR k k KK KKK k k k k k k k k k ck k k k k k k k k k k k k k ck ck k k k k INCLUDES S EE RRR K k KR k k k RR RRR kk kk kk k k k k k k k ck ck ck kckckckckckckckckckckckckckck ck ck k k k k k k k k k k k k k k k k k k RR k k k k k include types h S EE KK K k k k k k RR k k RR k kk k k KK k k k k k k k k k k ck ck ck k k k k k k k RK KKK RR RRR k k k k k k k k k k k k k k ck ck k k k ck ck ck ck k k PROTOTYPES BOR RRR KR KR RR k k RR RR RK KK KK kk KK k k k k k k k RR RK KR KKK k k k RR RR k k ck ck KK void codeSCItoPL prepare data from SCI to PL void codePLtoSCI prepare data from PL to SCI ttendif C 11 scicomm c
152. k ck k k k k k k k k RR ck ck ck ck k k s GLOBAL VARIABLES S EE RRR KR RRR k k RRR RR RK k k KK kk kc k k k k k k k ck ck ck k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ko k k k k ck ck ck ck kk extern pl uRxFromSCI pl RxFromSCI Buffer dedicated for SCI reception extern pl uTxToSCI pl TxToSCI Buffer dedicated for SCI transmission extern volatile pl sFlags pl Flags contains the state and another flags of PL modem device BRR RR KK RRR RR RRR RK k kk a RR RR KKK KKK RR RR RR k k RR k k RK KK Module void scicommRxErrISR void Description flag OR whenever it is needed Returns None ox FF X Ro X Global Data None Designer Reference Manual This function is the ISR of the SCI Receiver error It clears the Noise flag NF Parity error flag PF Framing error flag FE and Overrun DRM035 Rev 0 138 Source Code Files For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Source Code Files scicomm c Arguments None Range Issues None Special Issues None HR RR RK KR KR RR KK k k ck ck kckckckckckckckckckckckckckck ck ck k k k k k k k k k k k k k k k RR ck ck ck ck kk pragma interrupt void scicommRxErrISR void UWordl6 temp temp ioctl SCI 0 SCI GET STATUS REG NULL ioctl SCI 0 SCI CLEAR STATUS REG NULL
153. k k 100kHz BRR RR K k RRR RR RR ck kk kk k k k k kk kc kckckckckckck ck ck k k k k k k k k k k k k k k k k k k k k k k k k k k RR k k k ck ck ck ck k const Wordl6 K100 2 DEMFSK FRAMELEN real part imag part FRAC16 1 000000 FRAC16 0 000000 0 FRAC16 0 309017 FRAC16 0 951057 1 FRAC16 0 809017 FRAC16 0 587785 2 FRAC16 0 809017 FRAC16 0 587785 3 FRAC16 0 309017 FRAC16 0 951057 4 FRAC16 1 000000 FRAC16 0 000000 5 FRAC16 0 309017 FRAC16 0 951057 6 DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 153 For More Information On This Product Go to www freescale com y Freescale Semiconductor Inc Source Code Files FRAC16 0 809017 FRAC16 0 587785 7 FRAC16 0 809017 FRAC16 40 587785 8 FRAC16 0 309017 FRAC16 0 951057 9 FRAC16 1 000000 FRAC16 40 000000 10 FRAC16 0 309017 FRAC16 0 951057 11 FRAC16 0 809017 FRAC16 0 587785 12 FRAC16 0 809017 FRAC16 40 587785 13 FRAC16 0 309017 FRAC16 40 951057 14 FRAC16 1 000000 FRAC16 40 000000 15 FRAC16 0 309017 FRAC16 0 951057 16 FRAC16 0 809017 FRAC16 0 587785 17 FRAC16 0 809017 FRAC16 40 587785 18 FRAC16 0 309017 FRAC16 40 951057 19 FRAC16 1 000000 FRAC
154. k k k ck kk GLOBAL VARIABLES rn pl uRxFromSCI pl RxFromSCI Buffer dedicated for SCI reception rn pl uRxFromSCI pl TxToPL Buffer dedicated for Power Line transmission rn pl uRxFromPL pl RxFromPL Buffer dedicated for Power Line reception rn pl uTxToSCI pl TxToSCI Buffer dedicated for SCI transmission rn volatile pl sFlags pl Flags contains the state and another flags of PL modem device n of SW FSK Demodulation variable taken from the demfsk c file rn UWord32 demfsk MSGBuf DEMFSK MSGBUFLEN buffer of received message of FSK demodulation routine HK KKK KK KKK A KK k k kckckckckckckckckckckckckckckckckckckckck ck ck k k k k k RR ck ck ck k LOOK UP TABLE GLOBAL VARIABLES HR RK KKK KKK A ck ck ck kckckck ck kckckckckckckckck ck k k k k k k k k RR k k k ck ck k rn const UWord16 CRCtable 256 table of the 16bit CRC codes rn const UWordl6 FECtableCoder 16 able of the linear block Forward error correction coding part rn const UWord16 FECtableDecoder 128 able of the linear block Forward error correction decoding part K K KK KK aK RR RR KK KK KR ck ck RR RR RR ck ck kk PROTOTYPES ee Wordl6 codeCRCCal
155. k k k k k k k k k k k k k k ck ck ck ck ck ck RR RR RK KK Motorola Inc c Copyright 2001 Motorola Inc ALL RIGHTS RESERVED kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk FILE NAME demfsk h DESCRIPTION Header file for the SW FSK demodulator MODULES INCLUDED None HR KR RR KR KR RR kk kk kckckckckckckckckckckckckckckckckckckckckck ck ck ck k k k k k k k k k k k k k k k k ck ck ck ck ckck ck ck kk ifndef DEMFSK H define DEMFSK H BOR KR RR k k KR KR RRR RRR RK KK KK k k kk k k k k k k k ck ck ck kckckckckckckckckckckckckckck k k k RR ck ck ck ck ckock ck ck ck ck k INCLUDES x S EE RRR K k RR k k RR RR RK KK KK KR kk k k k k k k k k ck ck ck kckckckckckckckckckckckckckck ck ck k k k k k k k k ck RR k k k ck ck ck kk include pl h S EE KK K K k RR k k RR ck KKK k kk kk k k k k k k k k ck ck ckckckckckckckckckckckckckckck k ck k k k k k k kk k k k k k ck ck ck ck k k k k k k ck ck k Defines for SW FSK Demodulation BR KK K k k KR RRR RRR kk kk k k kk kk kckckckckckck ck ck ck k k k k k k k k k k k k k k k k k k k k k k k k k k k ck k ck ck ck ck ck k k ck ck ck ck ck k define DEMFSK MSGBUFLEN 14 length of MSGBuf buffer for the FRAME TOTALLEN equal to 16 24 or 32 and PL FECTYPE equal to PL NOFEC the length should be 8 for the FRAME TOTALLEN equal to 16 24 or 32 and PL FECTYPE equal to PL 1STFEC the leng
156. k k k k k k kk k k k k k k ck k k k k k RR K rn pl uRxFromSCI pl TxToPL Buffer dedicated for Power Line transmission rn volatile pl sFlags pl Flags contains the state and another flags of PL modem device kkkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk void tmrfskBitISR void ption This function is the ISR of the Bit Timer TmrD1 It is used during the PL transmission it generates the interrupt each bit period After each bit period it is necessary to set the proper timing values for FSK carrier generation This FSK carrier generation is done by CarrierTmr TmrD2 Note that transmission consists of two steps 1 Tx of HEADER part which is sent in normal non interleaved way 2 Tx of the rest of the packet is sent using the interleaving technique when PL_NOINTERLEAVING is not defined or without the interleaving PL_NOINTERLEAVING is defined s None Data pl Flags flag pl FlgModeOfModem if the Mode was set to STATE4 PL transmission could be started then it is switched to STATE5 PL transmission in progress When PL Tx is finished it is set to STATE6 PL SCI transmission has been finished and then to STATE7 PL reception has been started pl TxToPL is a buffer to be sent PL NOINTERLEAVING is a symbolic constant if defined the interleaving 106 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com DRM035 Rev
157. k kk PROTOTYPES S EEK K K K k RRR RR ke k k kk k k k k k k k k k k k k k k ck ck ck kckckckckckckckckckckckckckck ck k k k k k k kk k k k k k k k k ck k k k ck ck k ck k k void demfskInit void void demfskDem void asm void demfskEndOfScanISR void BOR K K K KR KR RR RRR RRR KK kk RR KK RK KK KR k k k k k k k k k k k k ck ck ck k k ck ck ck ck RK MACROS S EE KK K KR KR RR RR RR RRR KK k k k k k kk k k k k k k k ck ck ck ckckckckckckckckckckckckckckck ck k k k k k k k k k k k k k k k ck ck k k k ck ck ck ck ck k Timer C2 section define demfskStartADCRxFromPL ioctl QTIMER C2 QT SET COUNT MODE QT COUNT RISING EDGES MODE start the Tmr C2 which triggers the ADC conversion gt it starts the data sampling for the SW FSK Demodulation routine define demfskStopADCRxFromPL ioctl QTIMER C2 QT SET COUNT MODE OT NO OPERATION N ioctl ADC A ADC CLEAR STATUS EOSI NULL stop the Tmr C2 which triggers the ADC conversion gt it stops the data sampling for the SW FSK Demodulation routine and clears the ADC End of Scan Interrupt flag as well dendif C 9 coderoutines c BOR RRR KR RR RR RR RR RK KK kk kk kk kckckckckckck ck ck ck kckckckckckckck ck ck ck ck ck ck k k k k k k k k k k k k ck kck ck ck ck ck ck RR RR KR KK Motorola Inc c Copyright 2001 Motorola Inc ALL RIGHTS RESERVED kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk
158. kDem call SW FSK Demodulation routine if ioctl SCI 0 SCI GET RX FULL NULL SCI Rx is full if pl_FlgModeOfModem gt STATE6 amp amp SCITx or PLTx is finished or pl FlgModeOfModem lt STATEQ PLRx is started in demState 0 or 1 demfskStopADCRxFromPL stop PL data sampling stop Rx from the PL side pl FlgModeOfModem STATE1 set Mode of modem flag ioctl SCI 0 SCI RX ERROR INT SCI ENABLE enable interrupt ioctl SCI 0 SCI RX FULL INT SCI ENABLE enable interrupt else if ioctl SCI 0 SCI GET RX FULL NULL clear flag temp ioctl SCI 0 SCI READ DATA NULL if ioctl SCI 0 SCI GET ERROR NULL clear flags ioctl SCI 0 SCI CLEAR STATUS REG NULL Designer Reference Manual DRM035 Rev 0 98 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com bud Freescale Semiconductor Inc ifdef PL COPINUSE ioctl COP dendif IMPORTANT NOTE Call this condition with demfskDem if demfsk NewFrmCounter lt 0 pl FlgModeOfModem STATE7 COP CLEAR COUNTER NULL Ta amp amp amp amp pl FlgModeOfModem STATE10 demfskDem IMPORTANT NOTE Although this condition should be placed here in main loop at the end of SCI Rx routine tmrfskTimeOutISR t Speed optimalization if ioctl
159. kkkkkkkkkkkkkkkk FILE NAME coderoutines c DESCRIPTION This file contains the routines of data coding decoding specifically FEC code decode CRC computation MODULES INCLUDED a codeCRCCalc codeSCItoPL codeMoveAndFECBuff DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 129 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files k AE kk kkk include include include include include include include include x k exte exte exte exte exte exter exte x RR KK KKK exte exte P exte fe RRR kkk k codePLtoSCI deintrleave K K A K KK KK a ck ck ck kckckck ck RK k k k k k RRR RR RR RR ck ck KK INCLUDES kkkkkk eK kckckckckckckckckckckckckckckck ck ck k k k k k k k k k k k k k ck ck k k k ck ck ck k types h arch h periph h sci h pl p h tea h coderoutines h demfsk h K K KK KKK a ck kckckckckckckckckckckckckck ck k k k k k k k k k k k k k k k ck ck ck c
160. kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk FILE NAME pl c DESCRIPTION MODULES INCLUDED main plProjectInit Powerline modem main routine HR KR KR KK KR KR RR RK kk kk kckckckckckck ck ck ck kckckckckckckckckckckckckckck ck ck k k k k k k k k ck kckck ck ck ck ck ck RR k k ck ck ck k BOR K K KR KR RR RK RRR RK RK KK kk kc kckckckckckckck ck kckckckckckckckckckckckckckckck ck k k ck ck k k k k k k k k k k k ck ck ck ck ckock ck k k ck k INCLUDES S EE KK K K k RRR RR RRR KR KK k k KR RR kckckckckckck ck ck ck k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ck ck ck ck ck k k ck ck ck ck kk din din din din Hin din din din din din din din din din din din din c c c c c c c c c c c 0 RR Rana lude lude lude lude lude lude lude lude lude lude lude lude lude lude lude lude lude types h arch h periph h mc h appconfig h adc h cop h gpio h itcn h qtimer h sci h pl E h tea h scicomm h tmrfsk h demfsk h coderoutines h ef S EE RR K K k KR k k RR RR RK k k KK RK ck ck k k RR RK KKK RR RR RRR ck ck ck ck k k ck ck ck ck ck ck k PROTOTYPES S EE KK K KR k k k k k KR RR k k KK k k KR KK RR k k KK k k KR k k RRR RRR k k KK k k void plProjectInit void f BR RR RR KR RRR RR RRR RK KK k RK k k ck ck ckckckckckckckckckckckckckckck ck k k k k k
161. l Signal Processor DSP56F801 which is a member of Motorola Hawk V1 family All embedded software of this project was written using CodeWarrior version 4 0 2 by Metrowerks Corporation http www metrowerks com Low level drivers for direct peripheral access were used through the development For more information see 4 5 2 List of the project files Although this software is dedicated to the PLM board based on the DSP56F801 code is written in the way that it is fully applicable for the other member of the Motorola DSP family the DSP56F803 device The only necessary change is to modify the appconfig h and linker flash cmd files and add the linker ram cmd if an external RAM target is required Note that the last mentioned file is not present in the PLM DSP56F801 project since this core does not allow external memory addressing 4 2 2 Application basics Designer Reference Manual The communication itself is performed in a very straightforward way Serial data coming into the PLM board through the SCI Serial Communication Interface module are received then they are formatted DRMOS35 Rev 0 44 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions Introduction to the packet frame processed and then sent out to the mains power line For the opposite direction of communication the process is equivalent
162. lation in Demstate 1 finding synchronization pattern STATE10 PL reception in progress FSK demodulation in Demstate 2 data reception STATE11 PL reception in progress FSK demodulation in Demstate 3 data reception finished STATE12 SCI transmission could be started TxToSCI buff is ready STATE13 SCI transmission in progress UWord16 DataError 1 Data Error occured in Rx PL frame bad CRC code or bad data length 0 no error 1 error occured pl sFlags BOR RRR k k k k k RR RRR RK KR kk k k k k k k k k ck ck ck ckckckckckckckckckckckckckckck ck k k k k k k k k k k k k k k k ck ck ck k k ck ck ck ck kk SHORT CUT DEFINES S EE KK K K k k k k k RR RR RK KK k kk kk k k k k k k k k ck ck ck k k k k k k k k k KKK k k k k k k k k k k kk k k k k k k k k ck k k k ck ck ck ck k k define pl FlgModeOfModem pl Flags ModeOfModem define pl FlgDataError pl Flags DataError endif C 5 tmrfsk c BOR RRR KR KR KK KR RR kk KK RK kckckckckckckck ck ck ck ck ck ck ck ckck ck k k k k k k k k k k k ck ck ck ck ck k k RR RR KK Motorola Inc c Copyright 2001 Motorola Inc ALL RIGHTS RESERVED kkkkkkkkkkkkkkkkkkkkkkkk che khe ke che khe ke che khe ck che khe che kk kkk kkk kkk kk kkk kk kk k k k k k ck ck ck ck kk kk k k k k FILE NAME tmrfsk c DESCRIPTION This file consists of all timer based routines needed for the PL modem such as FSK bit rate IS
163. lic constants describing each carrier frequency in term of number Ro FF FF Ok FF HF F FF HF HF F FF HF HF F FF F FF X F x Designer Reference Manual DRM035 Rev 0 116 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files demfsk c Arguments None Range Issues None Special Issues None Eckckckckckck ck RK RR AK k k ck k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ck k k k ck ck k k ck ck ck kk void demfskInit void SA FRAC16 0 002 SB FRAC16 0 0004 lambA FRAC16 1 0 0 01 lambB FRAC16 1 0 0 2 pbBuf bBuf pxBuf xBuf pinFrame xBuf XBUFLENGTH 33 pMSGBuf demfsk MSGBuf demState zs last24SubBits 0 j3 Sil demfsk NewFrmCounter 17 dif PL CARRIERLOW CARRIERLOW 110KHZ10KBPS set FSK Dem freguencies pK0Base Wordi6 K110 for FO calculation Helif PL CARRIERLOW mE CARRIERLOW 115KHZ10KBPS pKOBase Wordi16 K115 Helif PL CARRIERLOW CARRIERLOW 120KHZ10KBPS pKOBase Wordi16 K120 endif dif PL CARRIERHGH CARRIERHGH 100KHZ10KBPS set FSK Dem freguencies pKiBase Wordi6 K100 or F1 calculation Helif PL CARRIERHGH CARRIERHGH 105KHZ10KBPS pKlBase Wordi16 K105 Helif PL CARRIERHGH CARRIERHGH 110KHZ10KBPS pKlBase Wordi16 K110 endif BR RR RRR RRR RR RRR RK KK kk kk KK ck kck
164. lly explained 4 3 1 FSK modulation A subset of 2 state Frequency Shift Keying FSK called Minimal Shift Keying MSK was chosen for the Power Line Modem implementation A typical feature of this kind of modulation is the fact that a bit period Tp of the FSK modulated signal is equal to a multiple of the halves of two periods Tg and T standing for two discrete frequencies fg and f representing logic states 0 and 1 T T T af on and T H1 2f rien 2 EQ 4 1 DRMO035 Rev 0 Designer Reference Manual MOTOROLA Software Module Descriptions 47 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions Solving these two equations the frequency separation Af is defined as E EO 4 2 and then using a carrier frequency f the signaling frequencies fp and f can be written in the following form feat mi Ast EQ 4 3 For the approximate bandwidth calculation of such a signal both FSK and MSK modulation we can write this equation Borsx 2 amp Af EQ 4 4 4 3 2 FSK demodulation 4 3 2 1 Introduction The approach of the software FSK demodulation algorithm has the following advantages e number of hardware components is reduced to a minimum since they are replaced by software e frequency of a signal element can be determined by mathematical computation using DTFT Discrete Time Fourier Transformation that is an ultimate solution for such a
165. ment number indicates the sign of the number 1 indicates negative The two s complement negative of a number is obtained by inverting each bit in the number and then adding 1 to the result unbuffered Utilizes only one register for data new data overwrites current data unimplemented memory location A memory location that is not used Writing to an unimplemented location has no effect Reading an unimplemented location returns an unpredictable value variable A value that changes during the course of program execution VCO See voltage controlled oscillator vector A memory location that contains the address of the beginning of a subroutine written to service an interrupt or reset voltage controlled oscillator VCO A circuit that produces an oscillating output signal of a frequency that is controlled by a dc voltage applied to a control input waveform A graphical representation in which the amplitude of a wave is plotted against time wired OR Connection of circuit outputs so that if any output is high the connection point is high Word A set of two bytes 16 bits write The transfer of a byte of data from the CPU to a memory location Designer Reference Manual DRM035 Rev 0 176 Glossary MOTOROLA Go to www freescale com Freescale Semiconductor Inc For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOW TO REACH US USA
166. n init TmrC2 TriggerTmr for ADC ioctl QTIMER C2 QT INIT NULL init TmrD1 Bi tTmr ioctl QTIMER D1 OT INIT NULL ioctl QTIMER D1 OT WRITE COMPARE REGI value value value value PL PLBAUDRATE There is no valid definition of TmrD1 Compare register 1 value in appconfig h configuration it depends on the global define placed in the pl h file define PL PLBAUDRATE Designer Reference Manual PL 10000BPS choose PL 10000BPS DRM035 Rev 0 96 For More Information On This Product Go to www freescale com Source Code Files MOTOROLA Freescale Semiconductor Inc Source Code Files pl c init TmrD2 CarrierTmr ioctl QTIMER D2 QT INIT NULL ioctl OTIMER D2 QT WRITE COMPARE REG1 PL CARRIERLOW There is no valid definition of TmrD2 Compare register 1 value in appconfig h configuration it depends on the global define placed in the pl h file define PL CARRIERLOW CARRIERLOW 110KHZ10KBPS init TmrD3 TimeOutTmr ioctl OTIMER D3 QT INIT NULL ioctl OTIMER D3 OT WRITE COMPARE REG1 PL TIMEOUTVALUE There is a zero value of TmrD3 Compare register 1 written in appconfig h configuration this register is filled according the global define define PL TIMEOUTVALUE 1000 time out of SCI receive placed in the pl h file init SCI ioctl SCI 0 SCI INIT NULL ioctl SCI 0 SCI SET BAUDRATE D
167. nFrame 17 16 17 using modulo arithmetic move m01 r1 store value of m01 move pInFrame r0 r0 address of input frame move 16 n move XBUFLENGTH 1 m01 r0 modulo addressing in xBuf xBuf address must be multiple of 2 k bftstl 40x1 jj if jj amp 1 bcs NO17 lea 0 plnFrame xy NO17 lea r0 n pInFrame 16 move rO plInFrame store updated pInFrame pointer Designer Reference Manual DRM035 Rev 0 122 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files demfsk c move rl m01 restore value of m01 nop due to pipelining jj if jj amp 4 jj is from the range 1 3 jj 1 pl FlgModeOfModem demState 8 set Mode of modem flag if demState 3 whole message received demState 0 pl_FlgModeOfModem STATE11 set Mode of modem flag codePLtoSCI prepare data from PL to SCI if pl FlgDataError 0 check the data consistency pl_FlgModeOfModem STATE12 set Mode of Modem ioctl SCI 0 SCI TX EMPTY INT SCI ENABLE enable SCI Tx IRQ else Bad data consistency pl FlgDataError 0 clear flag pl_FlgModeOfModem STATE6 set Mode of Modem demfskInit reinitialise FSK demodulator demfskStartADCRxFromPL start PL data sampling start Rx from the PL side pl
168. nal In response to the read signal the selected memory location places its data onto the data bus memory map A pictorial representation of all memory locations in a computer system MI Bus See Motorola interconnect bus microcontroller Microcontroller unit MCU A complete computer system including a CPU memory a clock oscillator and input output I O on a single integrated circuit modulo counter A counter that can be programmed to count to any number from zero to its maximum possible modulus most significant bit MSB The leftmost digit of a binary number Motorola interconnect bus MI Bus The Motorola Interconnect Bus MI Bus is a serial communications protocol which supports distributed real time control efficiently and with a high degree of noise immunity Motorola scalable CAN msCAN The Motorola scalable controller area network is a serial communications protocol that efficiently supports distributed real time control with a very high level of data integrity msCAN See Motorola scalable CAN MSI See multiple serial interface multiple serial interface A module consisting of multiple independent serial MO sub systems e g two SCI and one SPI multiplexer A device that can select one of a number of inputs and pass the logic level of that input on to the output nibble A set of four bits half of a byte object code The output from an assembler or compiler
169. ner Reference Manual As mentioned in 4 2 4 Packet format basics there is a length limitation of the data part of the packet due to the TEA algorithm usage Moreover the FSK demodulation routine requires that the length of the frame to be received is known In order to choose the proper length of the packet from the application point of view Table 4 5 Length of the communication packets the following symbolic constant should be set correctly in pl h define PL FRAMETYPE LONG choose SHORT MEDIUM LONG if SHORT is used length of the data part of packet is 13w if MEDIUM is used length of the data part of packet is 21w if LONG is used length of the data part of packet is 29w Note when FEC is OFF just lower 8 bits of the word are used ON lower 14bits of the word carry the data Table 4 5 Length of the communication packets PL FRAME Length of Length of data Length of Total length TYPE cntrl part w part w cnc part w w SHORT 1 13 2 16 MEDIUM 1 21 2 24 DRMOS35 Rev 0 60 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com NOTE DRMO035 Rev 0 Freescale Semiconductor Inc Software Module Descriptions PLM project introduction Table 4 5 Length of the communication packets PL FRAME Length of Length of data Length of Totallength TYPE cntrl part w part w cnc part w w LONG 1 29 2 32
170. next available storage location on the stack start bit A bit that signals the beginning of an asynchronous serial transmission status bit A register bit that indicates the condition of a device stop bit A bit that signals the end of an asynchronous serial transmission subroutine A sequence of instructions to be used more than once in the course of a program The last instruction in a subroutine is a return from subroutine RTS instruction At each place in the main program where the subroutine instructions are needed a jump or branch to subroutine JSR or BSR instruction is used to call the subroutine The CPU leaves the flow of the main program to execute the instructions in the subroutine When the RTS instruction is executed the CPU returns to the main program where it left off synchronous Refers to logic circuits and operations that are synchronized by a common reference signal timer A module used to relate events in a system to a point in time toggle To change the state of an output from a logic O to a logic 1 or from a logic 1 to a logic O tracking mode A mode of PLL operation with narrow loop bandwidth Also see acquisition mode DRM035 Rev 0 Designer Reference Manual MOTOROLA Glossary 175 Go to www freescale com Freescale Semiconductor Inc two s complement A means of performing binary subtraction using addition techniques The most significant bit of a two s comple
171. ns whole set of PLM related symbolic constants as well as the structure definition tmrfsk c consists of two main timer based routines bit rate generation for the FSK transmission and the timeout indication of the SCI reception both done as interrupt service routines tmrfsk h is a header file which includes all timer periphery related project macros the GPIO related symbolic defines and function style macros are located here as well demfsk c and demfsk h contain the whole routines of the FSK demodulation demodulation initialization FSK demodulation itself ADC End Of Scan interrupt service routine and a couple of other support routines the header file includes demodulation related symbolic constants and also function style macros for ADC management using the Timer C2 as the ADC A TriggerTmr scicomm c and scicomm h include all SCI periphery basis routines Interrupt service routines for both transmission ISR Transmitter Empty and reception ISR Receiver Full and ISR Receiver Error coderoutines c and coderoutines h incorporate all data coding and decoding routines such as FEC coding and decoding CRC computation and the de interleaving algorithm tea c and tea h hold the implementation of all Tiny Encryption Algorithm routines for both encryption and decryption demfskconst c is a look up table used for FSK demodulation Designer Reference Manual MOTOROLA Software Module Descriptions 55 For More Information On This P
172. nt TEA was 126 not 128 bits 2 a related key attack was possible although impractical xf BR RRR KR KR RR k k RR RR kk kk KK RK ck ck kckckckckckckckckckckckckckck ck ck k k k k k k k k k k k k k k ck ck ck k k k ck ck ck ck k NOTES S EEK RR K k RR k k RRR RRR kk KK k k kc kckckckckckck ck ck ck kckckckckckckckckckckckckckck ck RRR RR k k ck ck ck ck ck kk The Tiny Encryption Algorithm operates over its own 64bit long buffer so the final buffer to be encrypted decrypted has to be multiple of the 8B value i BRR RR KR RR RR RR RRR kk kk kk kk kc kckckckckckck ck ck ck kckckckckckckckckckckckck ck ck RR RRR ck ck ck ck ck ck RR k k KK KK Module void teaCode void Description This function perform the TEA encryption over the its own 64 bit long buffer Returns None Global Data ox FF X Ro ox tea IO 64bits long buffer for TEA computation y a short cut define for tea IO dw 0 z a short cut define for tea IO dw 1 pl TeaKey Key for TEA Tiny Encryption Algorithm computation k 4 a short cut define for pl TeaKey dw 4 TeaDelta TEA constant chosen to be the real part of the golden ratio Sqrt 5 4 1 2 0 618034 multiplied by 2 32 Designer Reference Manual DRM035 Rev 0 144 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files te
173. ode of Modem condition if mask lt PL TXMASK if mask amp pl_TxToPL Array Byte index currect bit is 1 if ioctl QTIMER D2 OT READ COMPARE REG1 NULL PL CARRIERLOW if previous value was logical 0 while ioctl OTIMER D2 OT READ COUNTER REG NULL PL CARRIERHGH TMRFSK SAFETYRESERVE tmrfskSetCarrierHigh set logical 1 carrier DRM035 Rev 0 Designer Reference Manual MOTOROLA Source Code Files 107 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files tmrfskTxDLEDOn Set the transmit LED indication else currect bit is O0 if ioctl QTIMER D2 QT READ COMPARE REG1 NULL PL CARRIERHGH if previous value was logical 1 while ioctl QTIMER D2 QT READ COUNTER REG NULL gt PL CARRIERHGH TMRFSK SAFETYRESERVE tmrfskSetCarrierLow set logical 0 carrier tmrfskTxDLEDOff Clear the transmit LED indication if txHeader 1 Header part just 8bits is beeing transmited in linear way no interleaving mask lt lt 1 movement in packet array in a row direct if mask gt PL HEADERTXMASK check the 8bit length txHeader 0 Header part has been transmitted index FRAME PRELEN mask 1 else Interleaving of the data packet part movement in packet array in a column direction if index FRAME TOTALLEN FRAME PRELEN
174. ode register cycle time The period of the operating frequency tcvc 1 fop D See accumulators A and B or D decimal number system Base 10 numbering system that uses the digits zero through nine duty cycle A ratio of the amount of time the signal is on versus the time it is off Duty cycle is usually represented by a percentage ECT See enhanced capture timer EEPROM Electrically erasable programmable read only memory A nonvolatile type of memory that can be electrically erased and reprogrammed EPROM Erasable programmable read only memory A nonvolatile type of memory that can be erased by exposure to an ultraviolet light source and then reprogrammed enhanced capture timer ECT The HC12 Enhanced Capture Timer module has the features of the HC12 Standard Timer module enhanced by additional features in order to enlarge the field of applications exception An event such as an interrupt or a reset that stops the sequential execution of the instructions in the main program fetch To copy data from a memory location into the accumulator firmware Instructions and data programmed into nonvolatile memory free running counter A device that counts from zero to a predetermined number then rolls over to zero and begins counting again full duplex transmission Communication on a channel in which data can be sent and received simultaneously hexadecimal Base 16 numbering
175. of coeff do DEMFSK FRAMELEN END mac x0 yl a x r3 x0 x0 imag part of coeff mac x0 y1 b x r0 yl x r3 x0 yl input sample x0 real part of coeff END do DEMFSK FSCALE END1 scaling asr a a a 2 DEMFSK FSCALE asr b b b 2 DEMFSK FSCALE __END1 rnd a move a y0 mpy y0 y0 a a real part of F0 2 rnd b move b y0 mac y0 y0 a a real part imag part of F0 2 asr a a a 2 scaling rnd a move a y0 the return value to y0 move rl m01 restore value of m01 rts BR RRR RR KR RR RR RR RK KK k kk k kk kc kckckckckckckckckckckckckckckckckck ck ckckck ck ck k k k k k A k k k k k k k k k ck ck ck ck ck ck RK k k KKK Module asm void slidAverage Word16 Si Wordl6 lambi Word16 f Description Calculation of Si i A B Si lambi Si 1 lambi f Returns Result is returned in Si Global Data None Arguments Designer Reference Manual DRM035 Rev 0 126 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files demfsk c Si pointer to Si SA or SB sliding average lambi forgetting factor lambA or lambB f new value for sliding average calculation Range Issues None Special Issues None
176. ology known as EMIT software It is a complete communication and device information management solution for connecting numerous embedded devices to the Internet For more information see http www emware com 2 4 4 HyperTerminal settings There are several parameters to be set in HyperTerminal e proper serial port COM1 COM2 COM3 communication speed bit rate of the PLM demonstration is 38400 bps e 8 data bits per character none parity e 1 stop bit e no flow control 2 4 2 Connecting the PLM boards to the PC DRMO035 Rev 0 The board supply current can be delivered by the AC DC convertor mounted on the PLM board or by an external 12V AC DC convertor Perform the following steps to connect the PLM board cables 1 Connect the serial extension cable to the selected serial port of the host computer or end device 2 Connect the other end of the serial extension cable to J2 on the PLM board This provides the connection which allows the host computer end device to communicate with the PLM board 3 Connect the power supply plug to a 230V 120V AC power source The red Power On LED will illuminate when the power is correctly applied 4 Follow steps 1 to 3 for the second PLM board Designer Reference Manual MOTOROLA Quick Start 19 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc NOTE Itis necessary that both PLM s are connected to the same
177. om Freescale Semiconductor Inc Software Module Descriptions Table 4 4 Interrupts Symbolic name ISR function Typeofthe Priorityof INTR enabled periphery module interrupt the INTR after start BitTmr D1 tmrfskBitISR QUID 2 yes compare TimeOutTmr D3 tmrfskTimeOutISR S 1 yes compare ADC A demfskEndOfScanISR snd olsoan 5 yes interrupt SCIO transmitter Eo scicommTxEmptISR 1 no transmission empty SCIO reception ScicommRxFullISR receiver full 1 no SCIO reception ScicommRxErrISR pesos 2 no 4 5 5 Main variables of the project In this section an enumeration of the most important variables is given together with brief descriptions The four main communication buffers variables are declared in pl c data structure in pl h are pl uRxFromSCI pl RxFromSCI is a buffer dedicated to SCI reception operations e pl uTxToSCI pl TxToSCI serves for the SCI transmission operations pl uRxFromPL pl RxFromPL stores the final data frames received from the Power Line e pl uRxFromSCI pl TxToPL is a buffer dedicated to Power Line transmission Data types of all buffer variables are defined as unions of two structure types a dedicated structure and a simple array This approach makes the operations over the buffers very flexible typedef union complete union of the SCI reception Designer Reference Manual DRM035 Rev 0 58 Software Module Descriptions MOTOROLA For
178. on MSG buffer repetitions S and S i computation full b i F i lt F i subbit calculation circular buffering b i to bBuf in each third repetition MSG i b idx 1 b idx 2 b idx 3 gt 2 Figure 4 3 State model of the FSK demodulation Designer Reference Manual DRM035 Rev 0 52 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com NOTE Freescale Semiconductor Inc Software Module Descriptions FSK communication parameters Values of parameters given in the previous figure were set during the tresting phase of the Power Line Modem development These tests were carried out in the noisy office environment of our lab However some values should be changed by the user if necessary Very important is a value of the multiplier in the s i gt 2 S i sliding average comparison Depending on the ratio of signal to noise its value may be changed if necessary The source code allows you to set a value such as 1 2 4 very easily using the symbolic constant DEMFSK SAMULTIPLE Which in the source code is used in the way 2 DEMFSK SAMULTIPLE 4 4 FSK communication parameters DRMO035 Rev 0 Some of the most important parameters and the respective values of the implemented FSK algorithm are shown here calculated and commented if necessary communication is held in the CENELEC B band 95 kHz 125 kHz e bit period Tpis equ
179. or Inc Source Code Files demfskconst c FRAC16 0 728969 FRAC16 0 684547 46 FRAC16 0 535827 FRAC16 0 844328 47 FRAC16 0 929776 FRAC16 0 368125 48 FRAC16 0 187381 FRAC16 0 982287 49 h S EE KK K K k RR RRR RRR RK KK k k k k k k k k k k k k k k ck ck k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ck ck ck ck ck ck ck ck kk 115kHz S EE RRR K k RRR RR k k RR KK k kk RR k k KKK KR k k k RRR RR k k k k k k const Wordl6 K115 2 DEMFSK FRAMELEN real part imag part FRAC16 1 000000 FRAC16 0 000000 O FRAC16 0 125333 FRAC16 0 992115 1 FRAC16 0 968583 FRAC16 0 248690 2 FRAC16 0 368125 FRAC16 0 929776 3 FRAC16 0 876307 FRAC16 0 481754 4 FRAC16 0 587785 FRAC16 0 809017 5 FRAC16 0 728969 FRAC16 0 684547 6 FRAC16 0 770513 FRAC16 0 637424 7 FRAC16 0 535827 FRAC16 0 844328 8 FRAC16 0 904827 FRAC16 0 425779 9 FRAC16 0 309017 FRAC16 0 951057 10 FRAC16 0 982287 FRAC16 0 187381 11 FRAC16 0 062791 FRAC16 40 998027 12 FRAC16 0 998027 FRAC16 0 062791 13 FRAC16 0 187381 FRAC16 0 982287 14 FRAC16 0 951057 FRAC16 0 309017 15 FRAC16 0 425779 FRAC16 0 904827 16 FRAC16 0 844328 FRAC16 0 535827 17 FRAC16 0 637424
180. ors A and B or D Two 8 bit A and B or one 16 bit D general purpose registers in the CPU The CPU uses the accumulators to hold operands and results of arithmetic and logic operations acquisition mode A mode of PLL operation with large loop bandwidth Also see tracking mode address bus The set of wires that the CPU or DMA uses to read and write memory locations addressing mode The way that the CPU determines the operand address for an instruction The M68HC12 CPU has 15 addressing modes ALU See arithmetic logic unit ALU analogue to digital converter ATD The ATD module is an 8 channel multiplexed input successive approximation analog to digital converter arithmetic logic unit ALU The portion of the CPU that contains the logic circuitry to perform arithmetic logic and manipulation operations on operands asynchronous Refers to logic circuits and operations that are not synchronized by a common reference signal ATD See analogue to digital converter B See accumulators A and B or D baud rate The total number of bits transmitted per unit of time BCD See binary coded decimal BCD binary Relating to the base 2 number system DRM035 Rev 0 Designer Reference Manual MOTOROLA Glossary 167 Go to www freescale com Freescale Semiconductor Inc binary number system The base 2 number system having two digits O and 1 Binary arithm
181. out 0 38 4 1 Block diagram of the communication system 45 4 2 Format ofthe packet i 47 4 3 State model of the FSK demodulation 52 4 4 FSK generation principle i 64 4 5 Scheme of demfskDem function calling 67 4 6 Error control coding path za u ip siz add ke d na z E E hard 69 4 7 Interleaving technique of PL transmission 12 4 8 State diagram of the Power Line Modem T3 4 9 Detailed information about the buffers used 78 4 10 Main loop flowchart ea aw dI ERR Ie Rok RC RIC o 79 P PLM BLOCKS Leda d d irits OR ak 86 B 2 Power Stage amp Coupling i 87 B ODD FERA ic Rr ke Ee dO Id vind Pe RR EC UH ERROR 88 B 4 nput StagB PO ndn a E 89 po Microcontroller bcs bs dos dro E REOR dann Raw eR RR EXE 90 B6 232 INTO usse ad dei ero OC k k dk eer ee ROO 91 Br PONE SL ad add dV baba ad Wei dida dad pq ad ed Eg 92 Designer Reference Manual MOTOROLA 11 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc List of Figures Designer Reference Manual DRM035 Rev 0 12 MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Designer Reference Manual PLM DRMO035 Rev 0 Table B 1 List of Tables Title Page Extended Signals ss vd k op e RR Rae e DRE dod 35 JTAG ONCE CAN uaa qeu dci ERE RR RAE E ikkini 36 DSP
182. p amp condition for the SW FSK Demodul pl FlgModeOfModem gt STATE7 amp amp mode equal to PL reception pl FlgModeOfModem lt STATE10 demfskDem call SW FSK Demodulation routine The demfskDem routine contains the complete implementation of the algorithm shown in 4 3 2 4 State model of the PLM FSK demodulation As any other source codes of the project the demf skDem routine is commented very precisely so just a couple of additional notes can be mentioned regarding the implementation itself e As described in 4 3 2 3 Synchronization and windowing each signal element received bit is calculated from the 3 results subbits of the demfskDem routine When 2 or 3 of the subbit values belonging to one particular bit indicate a logical 1 that bit is equal to one Otherwise 2 or 3 subbits indicate a logical O bit 0 is added to the MSG buffer The variable demfsk NewFrmCounter is set to 17 16 and then to 17 in order to have 17 16 17 7 17 16 17 2us 100us time period equal to bit period T of the signal with a 10 kbps bitrate The technique used here is shown in the following figure Designer Reference Manual DRM035 Rev 0 66 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions PLM Implementation pe 100us bit period bit A of message buffer
183. r Algorithmus in der Programmier sprache C angegeben der den CRC eines Puffers buf der L nge n berechnet snip Literatur 1 Karn Phil KA9Q Proposed Raw TNC Functional Spec 6 8 1986 ver ffentlicht in den USENET News 2 R hner Michael DC40X Was ist CRC ver ffentlicht im Packet Radio Mailbox Netz Mai 1988 3 FTP Software Inc PC TCP Version 1 09 Packet Driver Specification Wakefield MA 1989 4 Schiefer Jan DL5UE WAMPES Weiterentwicklung Vortrags Skriptum des 5 berregionalen Packet Radio Treffens Frankfurt 1989 const UWordl16 CRCtable 256 0x0000 OxcOc1 0xc181 0x0140 0xc301 0x03c0 0x0280 0xc241 Oxc601 Ox06c0 0x0780 0xc741 0x0500 0O0xc5c1 0xc481 0x0440 OxccO1 0Ox0ccO 0x0d80 Oxcd41 OxOf00 Oxcfcl Oxce81 0x0e40 Designer Reference Manual DRM035 Rev 0 150 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com 0x0a00 0xd801 Oxle00 0x1400 0xd201 Oxf001 0x3600 0x3c00 Oxfa01 0x2800 OxeeOl Oxe401 0x2200 0Oxa001 0x6600 0x6c00 Oxaa01 0x7800 Oxbe01 0xb401 0x7200 0x5000 0x9601 0x9c01 0x5a00 0x8801 Ox4e00 0x4400 0x8201 Oxcacl 0x18c0 Oxdecl Oxd4cl 0x12c0 0x30c0 Oxf6c1 Oxfccl 0x3acO0 Oxe8c1 Ox2ecO0 0x24c0 Oxe2c1 0x60c0 Oxa6c1 Oxaccl Ox6acO0 Oxb8c1 0x7ec0 0x74c0 0xb2c1 0x90c1 0x56c0 Ox5ccO 0x9ac1 0x48c0 Ox8ecl1 0x84c1
184. roduct Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions e FECtable c is a look up table for Forward Error Correction algorithm implementation e CRCtable c is a look up table for CRC computation e appconfig h is the header file of the static periphery configuration made by the Low level drivers suite linker flash cmd is the linker command file of the Metrowerks CodeWarrior project The complete source code routines of the Low level drivers is stored in src subdirectory of the project 4 5 3 Used DSP peripherals This section briefly describes all used DSP peripheral components used in the project A list and short description of the Quad Timer modules used is given in the following table Table 4 1 Quad Timers QTimer Symbolic name Purpose ISR function C2 TriggerTmr trigger for ADC a bit rate generation timer D1 BitTmr for the FSK modulation tmrfskBitISR carrier generation timer for _ De the FSK modulation D3 TimeOutTmr SCI reception timeout tmr tmrfskTimeOutISR NOTE Thededicated input output pin TD2 GPIOA2 of the QTimer D2 is used for the carrier frequency generation set as an output Usage of the Analog to Digital Converter ADC is given in a next table Designer Reference Manual DRMOS35 Rev 0 56 Software Module Descriptions For More Information On This Product Go to www freescale com MOTOROLA
185. s None Special Issues None Freescale Semiconductor Inc ion speed void plProjectInit voi d S EE KK K k RRR k k RR RRR KR KK k ck ck RR KKK KK k k ck ck RR RR ck ck ck ck k k PERIPHERY INITIALI ZATION s S EE RRR KR KR RK KR KR RR RR RK KK kk kk k k k k k k k ck ck ck ck ck kckckckck ck kckckckckckck ck RRR RR ck ck ck ckock ck ck ck kk init COP if des ifdef PL COPINUSE ioctl COP COP INI ioctl endif T ioctl COP COP DEVICE COP COP CLEAR COUNTER NULL ired T NULL COP_ENABLE the COP service sequence Initially the COP module is disabled by startup asm code but if there is the global define define PL COPINUSE placed in the pl h init GPIO Hifdef DSP56F803 file it finally switch the COP on if defined the Watch Dog is used ioctl GPIO E GPIO INIT NULL endif ifdef DSP56F801 ioctl GPIO B GPIO INIT NULL endif tmrfskClearTxEnabl tmrfskTxDLEDOff tmrfskRxDLEDOff tmrfskCDLEDOff init ADCA e0 set set set set ioctl ADC A ADC INIT NULL initial pin initial pin initial pin initial pi
186. s state 1 looking for synchro MODE 2 SCI Rx in progress SCI Rx finished either SCI Rx timeout occurred or SCI Rx buffer is full synchro found MODE 10 PL Rx in progress state 2 duis MODE 3 reception in progress SCI Rx finished whole msg received amp checked MODE 11 PL Rx in progress state 3 reception finished data prepared data bad MODE 4 PL Tx could be started BitT mr started MODE 12 first BitTmr ISR occurred SCI Tx could be started MODE 5 SCI Tx Empty IRQ enabled first SCI Tx ISR occurred MODE 13 SCI Tx in progress PL Tx in progress PL Tx finished MODE 6 sels nshed PL SCI Tx is finished demfskStartADCRxFromPL Figure 4 8 State diagram of the Power Line Modem DRM035 Rev 0 Designer Reference Manual MOTOROLA Software Module Descriptions 73 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions NOTE NOTE The left column of the state diagram describes the whole PL reception SCI transmission phase see 4 6 9 the right one the SCI reception PL transmission part see 4 6 8 for more details By calling the demfskStartADCRxFromPL function style macro PL data sampling is started and therefore the whole PL reception phase is activated 4 6 8 SCI reception PL transmission phase Designer Reference Manual As itis shown in Fig
187. scale com 3 4 3 Input Stage 3 4 3 1 Input Filter Freescale Semiconductor Inc Hardware Description Power Line Modem Architecture As was described in section 3 4 1 1 the transformer T1 fitted with the tuning capacitor C30 see Figure B 2 provides a high pass filter with an efficient rejection of the 50 Hz signal Since the input signal is read by A D converter aliasing can be a problem when the input signal contains frequency components above half the A D sampling rate These higher frequencies can fold over into the lower frequency spectrum and appear as erroneous signals that cannot be distinguished from valid sampled data By limiting the input signal bandwidth we can avoid this problem A low pass input filter is used to eliminate unwanted high frequency noise and interference introduced prior sampling Figure B 4 shows the schematic for an Input Stage The inductors L1 L2 and capacitors C3 C6 create the input high pass filter with a cut off frequency of 110 kHz 3 4 8 2 Transient and Overvoltage Protections The dual diode D10 serves to clamp the voltage level applied to the input of the input amplifier to the power supply range of the device 3 4 3 3 Input Amplifier amp Limiter DRMO035 Rev 0 The schematic diagram of the input amplifier and limiter can be seen in Figure B 4 The LF351 high speed JFET input operational amplifier U1 is used to amplify the input signal To achieve a high input impedance
188. sfered bytes in one packet numColumns 14 or 8 with FEC or without FEC Range Issues None Special Issues None Others routine doesn t require linear addressing i e m01 to be SFFFF okckckckckckck KK RR A K k A A k A A k k A k k A A k k A k a KK ck k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ck ck kk asm void deintrleave UWord32 pInput UWordl6 pOutput UWordl16 numRows UWordi16 numColumns r2 pInput r3 pOutput yO numRows yl numColumns move y0 n calculate end address of Output buffer nop pipeline dependency lea r3 n lea r3 move r3 r0 r0 pOutput numRows r0 and r3 changed because r3 uses always linear addressing and enables index by short displacement addressing mode _ OUTER move Y0 r3 r3 pointer to output buffer move x r241 a move x r2 a0 lea r2 do yO INNER move x r3 x0 asr a c LSB ror x0 x0 shift right move x0 x r3 _ INNER decw yl decrement outer loop count bgt OUTER branch to top of OUTER loop if not done rts Designer Reference Manual DRM035 Rev 0 136 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files coderoutines h C 10 coderoutines h BRR RR KR RRR KR RR RR KK kk kk kckckckckckckck ck ck k k K k k A k k k k k k k k k k k k k k k k k k k k k k k ck c
189. sion Since the Power Line Modem operates in a very harsh and noisy environment it is necessary to use some kind of DRM035 Rev 0 Designer Reference Manual MOTOROLA Software Module Descriptions 45 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions error detection correction technique This PLM implementation uses a quite straightforward method of error detection correction called the Linear Block Codes with added redundancy characterized by the expression 7 4 Interleaving is another technique which assures better consistency of the transmitted data when combined with FEC It simply modifies the sequence of bits of the frame to be transmitted in a defined way NOTE Encryption Decryption and Interleaving routines do not modify the length of the final frame packet On the other hand the CRC and FEC routines add redundancy and therefore modify the length of the packet 4 2 3 1 Processing order of operations on the PL transmission side l 2 3 4 CRC computation TEA encryption FEC coding Interleaving 4 2 3 2 Processing order of operations on the PL reception side 1 2 3 4 4 2 4 Packet format basics De interleaving FEC decoding TEA decryption CRC check Figure 4 2 shows the format of the transferred packet frame before it undergoes any of the operations described above except the CRC calculation last 2 characters of th
190. sk c OBJECT Fdemfsk NewFrmCounter demfsk c avail main Application constants consts start place your constants here const c data Source Code Files linker flash cmd FECtable c data place constants into the XFlash area CRCtable c data demfskconst c data consts size consts start F Xdata start in ROM gt xflash main application data AT ADDR xflash consts size init values of global variables are placed in xflash after constants F StackAddr ADDR stack F StackEndAddr ADDR stack SIZEOF stack 2 F Xdata start in RAM data start data fp state data rtlib data DRMO035 Rev 0 1 Designer Reference Manual MOTOROLA Source Code Files For More Information On This Product Go to www freescale com 165 Freescale Semiconductor Inc Source Code Files ALIGN 0x80 these definitions must be above bss OBJECT FxBuf demfsk c ALIGN 0x80 OBJECT FbBuf demfsk c bss rtlib bss lo F Xdata size data start gt data FArchIO ADDR regs FArchCore ADDR onchip Designer Reference Manual DRM035 Rev 0 166 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Designer Reference Manual PLM Appendix D Glossary A See accumulators A and B or D accumulat
191. t Go to www freescale com Freescale Semiconductor Inc Source Code Files X X X 1 Der CRC Generator wird mit 0 vorbesetzt Berechnet wird der CRC ber alle Datenbytes einschlieflich des Kommandobytes 0x80 Bekanntlich wird im KISS Protokoll die Abgrenzung der Rahmen mit dem FEND Zeichen 0xc0 durchgef hrt Der Fall da dieses Zeichen im Datenstrom vorkommt wird gesondert behandelt Dieser Vorgang wird SLIP Encoding genannt Der CRC muf berechnet werden bevor das SLIP Encoding stattfindet und ueberpr ft werden nachdem das SLIP Decoding stattgefunden hat Daf r gib es mehrere Gr nde Die CRC Bytes k nnten FESC TFEND FEND usw enthalten Der SLIP En Decoder wird in manchen Host Implementierungen z B WAMPES auch unabh ngig von KISS benutzt um beispielsweise die Verbindung zum Unix Kernel herzustellen In diesem Fall w ren CRC berpr fungen zwar auch w nschenswert werden aber von der anderen Seite nicht verstanden Die CRCs geh ren also logisch zum KISS Layer Die Berechnung findet wie folgt statt CRC Generator mit 0 vorbesetzen Alle Datenbytes nacheinander in den Algorithmus hineintun einschlieflich der beiden CRC Bytes Am Ende mu wieder 0 im CRC Generator stehen Ist der Wert ungleich 0 so ist ein bertragungsfehler aufgetreten und der Rahmen mu verworfen werden Verschiedene Algorithmen f r den CRC Generator werden in 2 beschrieben Hier sei ein einfacher tabellengesteuerte
192. t output 1 0 jitter Short term signal instability latch A circuit that retains the voltage level logic 1 or logic O written to it for as long as power is applied to the circuit latency The time lag between instruction completion and data movement least significant bit LSB The rightmost digit of a binary number logic 1 A voltage level approximately equal to the input power voltage Vpp logic 0 A voltage level approximately equal to the ground voltage Vss low byte The least significant eight bits of a word M68HC12 A Motorola family of 16 bit MCUs mark space The logic 1 logic O convention used in formatting data in serial communication mask 1 A logic circuit that forces a bit or group of bits to a desired state 2 A photomask used in integrated circuit fabrication to transfer an image onto silicon MCU Microcontroller unit See microcontroller DRM035 Rev 0 Designer Reference Manual MOTOROLA Glossary 171 Go to www freescale com Freescale Semiconductor Inc memory location Each M68HC12 memory location holds one byte of data and has a unique address To store information in a memory location the CPU places the address of the location on the address bus the data information on the data bus and asserts the write signal To read information from a memory location the CPU places the address of the location on the address bus and asserts the read sig
193. tecture 26 Power Stage amp Coupling module 27 CANON gll SEMPER ch cutee TS 31 la d PRA X Per OS Ree Rd ree OR D ee 33 Microcontroller uus uu Shee eee ko ee eee ee Ro ed 34 RS232 ete ce wee on bo oe Oh SA ee ee 36 Power Supply ooo ekk od hook ek er nb 36 M rapa a doped doctori apad pied lbs 37 LOB EIER oa ESSE Ru an Ea iod duin dios tpa debebit ded ing 39 Expansion Connector J3 uus aa cio a kok kk 39 JTAG OnCE Connector J29 s sva d ddd da 39 RS232 Interface Connector J2 s 40 Mono Ka AP R EORR eee ORAL RAE P 40 This reference design of the Power Line Modem PLM provides a modem able to transmit data through a power line mains with a transmission speed up to 10 kbps The PLM is based on a DSP56F801 a 16 bit Digital Signal Processor DSP The result of the reference design is a protocol independent media access interface for the Designer Reference Manual MOTOROLA Hardware Description 21 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Description connection of different devices For example connection between appliances or connection appliances to a PC or a similar host The PLM board is the hardware platform for the power line modem reference design The board supports the provided demo application which is stored in the integrated FLASH memory of the DSP56F801 Beyond that the PLM board enables
194. th should be 14 define DEMFSK FRAMELEN 50 length of frame in samples define DEMFSK SYNCPATTERN 0x00E381C7 synchronization pattern is equal to 1110 0011 1000 0001 1100 0111 define XBUFLENGTH 100 length of xBuf buffer define BBUFLENGTH 100 length of bBuf buffer define DEMFSK FSCALE 4 both real and imag parts of FO and F1 are scalled down by 2 DEMFSK FSCALE define DEMFSK SAMULTIPLE 1 SA multiple for comparison SB lt 2 DEMFSK SAMULTIPLE SA S EE KK K k KR k k k RR k k RK KK k k kk RK k k ck ck ckckckckckckck ck kckckckckckckck k k k k k k k k k k ck k k ck ck ck ck ck k k ck ck ck ck kk Defines for memory mapping used in ADC End Of Scan ISR routine BR K K K K k RR k k RR RRR KK k kk kc kckckckckckck ck ck ck kckckckckckckckckckckckckck ck ck ck k k k k k k k k ck k k k k k ck ck ck k k ck ck ck ck ck k Designer Reference Manual DRM035 Rev 0 128 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files coderoutines c Note that the sequence of these defines has to be identical with the sequence as defined in linker ram and linker flash command files define addrPREVSAMPLE 0x0 define addrPXBUF 0x1 define addrNEWFRMCOUNTER 0x2 S EE RR K K k KR k k RR RRR RK KK kk k kc kckckckckck ck ck ck ck ck k k k k k k k k k k k k k k k k k k k k k ck k k k k k k k k k ck ck k k ck ck ck c
195. that is itself executable machine code or is suitable for processing to produce executable machine code opcode A binary code that instructs the CPU to perform an operation open drain An output that has no pullup transistor An external pullup device can be connected to the power supply to provide the logic 1 output voltage Designer Reference Manual DRM035 Rev 0 172 Glossary MOTOROLA Go to www freescale com Freescale Semiconductor Inc Glossary operand Data on which an operation is performed Usually a statement consists of an operator and an operand For example the operator may be an add instruction and the operand may be the quantity to be added oscillator A circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference OTPROM One time programmable read only memory A nonvolatile type of memory that cannot be reprogrammed overflow A quantity that is too large to be contained in one byte or one word page zero The first 256 bytes of memory addresses 0000 00FF parity An error checking scheme that counts the number of logic 1s in each byte transmitted In a system that uses odd parity every byte is expected to have an odd number of logic 1s In an even parity system every byte should have an even number of logic 1s In the transmitter a parity generator appends an extra bit to each byte to make the number of log
196. the implementation and testing of the user software For that purpose the board is equipped with a JTAG OnCE interface for reprogramming and debugging 3 3 Technical Data This subsection provides technical data for both the DSP56F801 processor and the PLM board 3 3 1 DSP56F801 Processor The main component of the PLM board is the DSP56F801 a Motorola 16 bit DSP Features of the DSP56F801 include DSP Core Features Designer Reference Manual 16 bit DSP56800 family DSP engine with dual Harvard architecture As many as 40 MIPS at 80 MHz core frequency Single cycle 16 x 16 bit parallel Multiplier Accumulator MAC Two 36 bit accumulators including extension bits 16 bit bidirectional barrel shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses Four internal data buses Instruction set supports both DSP and controller functions DRM035 Rev 0 22 Hardware Description MOTOROLA For More Information On This Product Go to www freescale com DRMO035 Rev 0 Freescale Semiconductor Inc Hardware Description Technical Data Controller style addressing modes and instructions for compact code Efficient C Compiler and local variable support JTAG OnCE Debug Programming Interface DSP Memory Features Harvard architecture permits as many as three simultaneous accesses to program and data memory On chip memory including a low cost high
197. tmrfskClearTxEnable ioctl GPIO B GPIO SET PIN TXENABLE Note that TxD output pin is only for signalization If the PowerLine modem transmission data value logical 1 then pin TxD is logical 0 then pin TxD is Hdefine tmrfskTxDLEDOn define tmrfskTxDLEDOff Note that RxD output pin is only If the PowerLine modem reception logical 1 then pin RxD is logical 0 then pin RxD is define tmrfskRxDLEDOn define tmrfskRxDLEDOff Tx is cleared to 0 and LED is switched on set to 1 and LED is switched off ioctl GPIO B GPIO CLEAR PIN TXD ioctl GPIO B GPIO SET PIN TXD for signalization data value Rx is cleared to 0 and LED is switched on set to 1 and LED is switched off ioctl GPIO B GPIO CLEAR PIN RXD ioctl GPIO B GPIO SET PIN RXD Note that CD output pin is only for signalization If the PowerLine modem reception is processing then pin CD is cleared to 0 and LED is switched on not processing then pin CD is set to 1 and LED is switched off Designer Reference Manual MOTOROLA Source Code Files 113 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files define tmrfskCDLEDOn ioctl GPIO B GPIO CLEAR PIN CD define tmrfskCDLEDOff ioctl GPIO B GPIO SET PIN CD endif endif C 7 demfsk c BOR RRR KR KR RR RR RRR RK kk k kk KR RR RK KKK OR RRR RRR ck ck ck ck ck ck RR k k RK KK Motorola Inc c Copyright 20
198. trol unit drive the execution unit which contains the arithmetic logic unit ALU CPU registers and bus interface COP See computer operating properly module COP CPU See central processor unit CPU CPU12 The CPU of the MC68HC12 Family CPU clock Bus clock select bits BCSP and BCSS in the clock select register CLKSEL determine which clock drives SYSCLK for the main system including the CPU and buses When EXTALi drives the SYSCLK the CPU or bus clock frequency f is equal to the EXTALi frequency divided by 2 CPU cycles A CPU cycle is one period of the internal bus clock normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal The length of time required to execute an instruction is measured in CPU clock cycles CPU registers Memory locations that are wired directly into the CPU logic instead of being part of the addressable memory map The CPU always has direct access to the information in these registers The CPU registers in an M68HC12 are e A 8 bit accumulator e B 8 bit accumulator D 16 bit accumulator formed by concatenation of accumulators A and B e IX 16 bit index register e Y 16 bit index register DRM035 Rev 0 Designer Reference Manual MOTOROLA Glossary 169 Go to www freescale com Freescale Semiconductor Inc e SP 16 bit stack pointer e PC 16 bit program counter e CCR 8 bit condition c
199. ubbits When 2 or 3 of the subbit values b i belonging to one particular bit indicate a logical 1 that bit equal to one is added to the MSG output sequence buffer Otherwise 2 or 3 subbits indicate logical 0 bit O is added into the MSG buffer Designer Reference Manual MOTOROLA Software Module Descriptions 51 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Software Module Descriptions 4 3 2 4 State model of the PLM FSK demodulation Initialization state prepare sequences eio ln e iom are sync pattern 111000111000000111000111 buffers bBuf for b i received message MSG S 0 0 002 S 0 0 0004 2 0 99 A 0 8 State 0 No transmission signal windowing Fi and F i computation S i and S i computation b i F i lt F i subbit calculation circular buffering b i to bBuf S i gt 284 State 1 Looking for the sync pattern signal windowing Fi and F i computation SG lt 28 i S i and S i computation b i F i lt F i subbit calculation circular buffering b i to bBuf actualSync sum b XOR 111000 000111 if actualSync minSync then minSync actualSync idx i No data false reception Packet received Times done amp minSync lt 8 State 2 Data reception 5209294 signal windowing for each in last 5 Fo and F 7 computati
200. ullISR void define INT VECTOR ADDR 53 scicommRxFullISR define ITCN INT PRIORITY 53 0x0001 extern void scicommRxErrISR void define INT VECTOR ADDR 52 ScicommRxErrISR define ITCN INT PRIORITY 52 0x0002 a GPIO B configuration Pin 0 Direction Input Mode Peripheral Pull up Disable Pin 1 Direction Input Mode Peripheral Pull up Disable Pin 2 Direction Input Mode Peripheral Pull up Disable Pin 3 Direction Input Mode Peripheral Pull up Disable Pin 4 Direction Output Mode GPIO Pull up Disable Pin 5 Direction Output Mode GPIO Pull up Disable Pin 6 Direction Output Mode GPIO Pull up Disable Pin 7 Direction Output Mode GPIO Pull up Disable GPIO interrupt disabled Designer Reference Manual DRM035 Rev 0 162 Source Code Files MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Source Code Files appconfig h define GPIO B DATA DIRECTION REG 0x00f0 define GPIO B PERIPHERAL ENABLE REG 0x000f End of autogenerated code kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkxkxk NOTES HR KK KR KR KR KR A A KK KK k RR ck ckckckck RR RRR
201. ure 4 8 State diagram of the Power Line Modem this phase is started by the SCI reception located in scicommRxFullISR routine pl FlgModeOfModem 1 and 2 The SCI reception data stored in pl RxFromSCI buffer is finished pl FlgModeOfModem 3 when e the pl RxFromsCI buffer is full orifan SCI reception time out occurs by the tmrfskTimeOutISR routine of the TimeOutTmr QTimer D3 see the timer section in 4 5 3 Used DSP peripherals When SCI reception is over then a codeSCItoPL routine coderoutines c is called It is aimed for data preparation before the PL transmission specifically it performs CRC calculation TEA Encryption if enabled FEC coding if enabled prepared data are stored in the pl TxToPL buffer pl FlgModeOfModenmis set to 4 And then the PL transmission part itself can be started It goes through the following steps e by calling the function style macro tmrfskSetTxEnable the output amplifier is switched on DRMOS35 Rev 0 74 Software Module Descriptions MOTOROLA For More Information On This Product Go to www freescale com NOTE NOTE NOTE DRMO035 Rev 0 Freescale Semiconductor Inc Software Module Descriptions PLM Implementation by calling the function style macro tmr skStartCarrierTmr the CarrierTmr QTimer D2 see 4 5 3 Used DSP peripherals is started as the FSK carrier generator delay approx 0 8 ms by the tmrfskStartBitTmr funct
202. uzos 1 9 997 6001 slew L AOUZOM ISON AG E 9WeN 914 uBiseq 9WeN oneuieuos 5eloUoodD JIWoJer JOUJNMY JelloquoooolN do Jej NANO ano Evy 31VW33 93806 6NONNVO NOO 1ndino VS li jno viva jno viva VA GND YA Big swe1oSz NOO eiqeue XL T a6els jnduj 6ulldnoD8e6elSs Jewmod a v GND GND Ru tdr A ai 2 S ojgeus XL S E ax Bg B ax TWYLNAN Bo axu 4 4 ox indui MS indui ys Od 3 g 3SVHd Z nA i o Z o lt Uu vlva u viva lt VA WA o o Zecsy OYIN eDejs Jewod Jewod QN9 2 3 anon S 2 Wana o o AG e 3SVHd JeNod DRM035 Rev 0 Designer Reference Manual MOTOROLA Bill of Materials and Schematics For More Information On This Product 86 Go to www freescale com Freescale Semiconductor Inc Bill of Materials and Schematics Contents Budno399Bejs Jamog Z g ainbi4 sseulsngleleus9 SNelS dOd LOOZ elololoN 1UBu do3 edoJun3 oyqndey uoezo yd Aouzos 19 9G 600 slew OUZOH ISON QN9d ano h 8a alqeua XL ndno ySJL M0 08 vAL A9VI3n001 e Sco wzo AQLANOZZ oo ezo Jndul 4 Y a VO 3M9d 302v O kal 9 V0L3y9d 0S28 1L exIAUZv Hy 0 9 TVYLNAN TV ISZCA 6d ASVHd Designer Reference Manual DRMO035 Rev 0 87 Bill of Materials
203. volume flash solution 8K x 16 bit words of Program Flash 1K x 16 bit words of Program RAM 1K x 16 bit words of Data RAM 1K x 16 bit words of Data Flash 2K x 16 bit words of BootFLASH DSP Peripheral Circuit Features 12 bit Analog to Digital Convertors ADCs which support two simultaneous conversions with two 4 pin multiplexed inputs General Purpose Quad Timer Serial Communication Interface SCIO Pulse Width Modulator module PWMA with 6 PWM outputs Serial Peripheral Interface SPI with configurable four pin port Computer Operating Properly COP Watchdog timer Two dedicated external interrupt pins Eleven multiplexed General Purpose I O GPIO pins External reset pin for hardware reset JTAG OnCE for unobtrusive processor speed independent debugging Software programmable Phase Lock Loop based frequency synthesizer for the DSP core clock Designer Reference Manual MOTOROLA Hardware Description 23 For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Hardware Description e Oscillation flexibility between external crystal oscillator or on chip relaxation oscillator for lower system cost and two additional GPIO lines 3 3 2 PLM Board Features of the PLM board include e DSP56F801FA80 DSP packaged in a 48 pin Plastic Quad Flat Pack LQFP Five Light Emitting diodes LED Power ON Tx_enable Data out Data in CD out e JTAG
204. xC OxC OxC 0x5 0x8 0x4 OxC 0000000 10100 1 qa bp Qe 0 0 1 0011 0110100 1100101 1000110 0010111 1101000 0111001 0011010 1 0 1 011 1011100 9 50 07 XL E 10 A 0101110 p Lobo I DL IO OxD OxD Ox7 OxD 0x5 OxD 0x4 0x9 0x5 OxD 0x1 OxC 0x5 0x5 0x5 OxF ED TD 1 0x6 OxE Ox7 OxA OxE OxE 0x4 OxE 0x6 0x6 0x6 OxC 0x6 OxE 0x2 OxF BE EF F O OOo Oo HH gt o o o o m l FPFOOF F OGC m H e oo FOrRPOrRPOrROrFRFOrFOFrFOF p H 0x7 OxD Ox7 Ox7 0x3 OxE Ox7 OxF 0x6 OxB Ox7 OxF 0x5 OxF OxF OxF DRM035 Rev 0 152 Source Code Files For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Source Code Files demfskconst c C 17 demfskconst c BRR RR KR KR KR KR RRR RRR KK kk kk kc kc kckckckckckckckckckckckckckckckck ck ckckckckck ck k k k k k k k k k k k k k k ck ck ck ck RR RR k k KKK Motorola Inc c Copyright 2001 Motorola Inc ALL RIGHTS RESERVED kkkkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk FILE NAME demfskconst c DESCRIPTION This file contains the FSK demodulator constants Linker command file locates this file either into the XFlash data memory area 56F801 source or FLASH target in 56F803 source or to internal RAM data memory area RAM target in 56F803 source ox OR RR OR F FF HF o

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