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1. 33 V 0 5 W SOD 123 ON Semiconductor MMSZ33T2 Inrush 1 8 Amax through hole EPCOS B57153S0150M000 Current Limiter 1 500V SMD 1206 various various Capacitors discharge resistor Current 80 mQ 1 3 W through hole Vishay LVRO3R0800FE12 sense resistor L ee resistor 1 1 1 4 W SMD 1206 1206 vaious various apa i hal i kid k R8 R22 SMD 560 kQ 1 1 4 W SMD 1206 various various resistor 1206 1 4 W http onsemi com 16 NCP1612GEVB Reference Description Value Tolerance Part number Constraints ht 27 O IKR 1 1 4 W SMD 1206 1206 various various R13 R15 5 resistor 120 kQ 10 1 4 W SMD 1206 various various R16 R17 R26 La P em rar aes aia wen es C15 c6 ee 470pF 470pF 25V 10 V 10 SMD 1206 1206 various various O s Capacitor 10nF O nF 100 V 10 EULER 10 ES 1206 various various fhe per ere ef oe diode oo es MMSZ22T1 22 V 0 5 W SOD 123 ON Semiconductor MMSZ22T1 iode PFC NCP1612 SOIC 8 ON Semiconductor NCP1612B Controller NOTE Applications require the use of Y1 capacitors In this case CD12 E2GA102MYNSA from TDK or DE1E3KX102MA5B01 from muRata may be a good option for C1 and C2 REFERENCES 1 Joel Turchi S key steps to design a compact high efficiency PFC Stage Using The NCP1612 Application note AND9065 D http www onsemi com pub_link Collateral AND9065 D PDF 2 Joel Turchi Safety test
2. body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 f Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email or
3. case of the operation at 265 V and 20 of the load Is nonexistent or very short at low line heavy load Is longer when the load diminishes and the line magnitude Let us remind that the skip function optimizes the efficiency but this is at the cost of a limited current distortion If superior power factor is needed forcing a minimum 0 75 V voltage on the FFcontrol pin inhibits this function Refer to the data sheet for a detailed explanation of the CCFF operation and of its implementation in the NCP1612 3 http onsemi com 4 NCP1612GEVB Leak El ma Le Z Spend digii rates KHz 037 4517 i 90 44 value 1 AFETE Tah AS 4d ps 0940 ps 28 35084 kH F ri R stat j I x F x Thais LE us BE EET TET are m 2 p ami ee camme zmay R uadh Antier AOA lune Tal no f imi iiin i sno TOI pai Honra pa ov 490i 00K 20MES Edge Higain i Paay ae Boo id us Wis PO ys a0 iw LOOKS tig WES Foge Y Te 137 a5 foe 1 75ddome A I i 4 Tt ort a Soft Skip Beginning b Soft Operation Recovery Figure 6 The NCP1612 Enters and Leaves Skip Mode in a Soft Manner As illustrated by Figure 6 the circuit does not abruptly periods typically Similarly the circuit recovers operation in interrupt the switching when it enters skip mode Instead the a soft manner on time is gradually decreased to zero in 3 to 4 switching NO LOAD LOSSES The input power is measured no load being connected An external 15 V Vcc is applied Resistors R15 R
4. frequency at a lower level of the sinusoid Figure 5 CCFF Operation 230 V 0 2 A Load Current Figure 5 illustrates the CCFF operation at 230 V 200 mA loading the PFC stage 1 At the top of the sinusoid the FFcontrol pin voltage that is representative of the line current exceeds 2 5 V and the circuit operates in critical conduction mode see Figure 5a 2 As the input voltage decays so do the line current and the FFcontrol pin voltage The FFcontrol being lower than 2 5 V the circuit starts to reduce the frequency see Figure 5b 3 Near the zero crossing the frequency is further decreased see Figure 5c In all cases the circuit turns on at a valley At the first valley as classically done in CrM operation Or at the first valley following the completion of the dead time generated by the CCFF function to reduce the frequency The circuit nicely stays locked on to valley n until it needs to jump to either valley n 1 or valley n 1 In other words there is no inappropriate transition between two valleys One can also note that the switching frequency being less when the line current is low the frequency is particularly low at light load high line CrM operation being more likely to occur at heavy load low line Experience shows that this behavior helps optimize the efficiency in all conditions Similarly the skipping period of time near the line zero crossing visible in Figure 9 for the particular
5. operating stress or of other troubles In particular adjacent pins of controllers can be shorted a pin grounded or badly connected It is often required that such open short situations do not cause fire smoke nor loud noise The NCP1612 integrates functions that help meet this requirement for instance in case of an improper pin connection including GND or of a short of the boost or bypass diode Application note AND9079 D details the behavior of a NCP1612 driven PFC stage under safety tests 2 As an example we will illustrate here the circuit operation when the PFC bypass diode is shorted When the PFC stage is plugged in a large in rush current takes place that charges the bulk capacitor to the line peak voltage Traditionally a bypass diode D2 in the application schematic of Figure 2 is placed between the input and output high voltage rails to divert this inrush current from the inductor and boost diode When it is shorted the bulk voltage being equal to the input voltage the inductor cannot demagnetize but only by virtue of the inductor and boost diode conduction losses This is generally far insufficient to prevent a cycle by cycle cumulative rise of the inductor current and an unsafe heating of the inductor of the MOSFET and of the boost diode http onsemi com 14 NCP1612GEVB 10 0 Vitiey Tay 27 mia 100 Widi 15 0 gA BY Tam i Tah ar omy ay E00 mi a General view SidHor vake Slates 4100
6. sd Ig td ee ed ee 46 0 We os ea A Aa Meaaume Start a Dunen mY oF PASS me FMa Lra TH O V Funa 115 V 60 Hz 20 load Beal Henmenic Mearuremenl Panel wi Chrom Regulation Parameters Kapina rii feeqees va Seren E Curren Lica Fali Class O Parameters giz gt Maacurad Bio Curent Tae Ourend Graph Voll Tae 9 Vaes Graph Son Pane Version 1 036ebe1 00 j pest eea a aaa e orl Pagel bey re 4 E amp 10 12 4 B WH Dt MH Me RT MN BS Bieasure Start D Dun nt Fitz 1 Farmed pd THES Vo Fume ivi off PASS PASS 230 V 50 Hz 20 load Figure 11 Performance with respect to IEC61000 3 2 Class C Requirements http onsemi com 9 NCP1612GEVB bt Harmonic Measurement Panel vi Chroma Regulation Parameters Regulation Current Tes Cured Graph Volege Tale inlbage raph Son Pome Version 1 07 6epa1 00 IE CE 10 055 045 Chti A N a k Sy eee ee o3 Class D Parameters i i Os input Parer k E erea T T Beti z Measurement k Bent Mie bb D Tahe i i i i ry i E i i i i i i E i i i i i i Mai E z d4 6 8 WM 1 i i Hh MOR N j HD M BH d l wivi HAJ PW PF 114 65 gJ 165 82 0 9939 Fal FdHzh _Fundity THOH Y Fumi a Cam icml Toa of PASS PASS 115 V 60 Hz full load 2 Harmonic Measuremeni Panel vi ETE E ee f
7. 0 die 100 Wide 1 000 Are b Magnified view Figure 18 Shorting the Bypass Diode and the NTC The NCP1612 incorporates a second over current comparator that trips whenever the MOSFET current happens to exceed 150 of its maximum level Such an event can happen when the current slope is so sharp that the main over current comparator cannot prevent the current from exceeding this second level as the result of the inductor saturation for instance In this case the circuit detects an overstress situation and disables the driver for an 800 us delay This long delay leads to a very low duty ratio operation to dramatically limit the risk of overheating Figure 18 illustrates the operation while the bypass diode and the NTC are both shorted at 115 V with a 0 1 A load current the NCP1612 being supplied by a 15 V external power source Two drive pulses occur every 800 us The first pulse is limited by the over current protection Since the input and output voltages are equal the inductor has not demagnetized when the next pulse is generated and the MOSFET turns on while the boost diode is still conducting a large current see Figure 18b Hence the MOSFET closing causes the second over current comparator to trip and an overstress situation is detected As the consequence no DRV pulse can occur until an 800 us delay has elapsed The very low duty ratio operation prevents the application from heating up Please note that we
8. 16 Soft Over Voltage Protection pfcOK FUNCTION The NCP1612 is particularly interesting in applications where the downstream converter is of the forward or half bridge type i e a converter that takes advantage of a narrow input voltage range As aforementioned both the dynamic response enhancer and the soft OVP are of great help in this case by drastically minimizing the bulk voltage deviation under line load changes In addition an optimum sequencing for this application type consists of having the PFC stage started first the downstream converter entering operation afterwards when the bulk voltage is nominal The pfcOK pin of the NCP1612 has been designed with the goal of controlling the downstream converter operation The pfcOK pin is grounded when the downstream converter should be disabled The pfcOK pin is in high impedance state otherwise That is why a portion of Vcc is generally applied to this pin to fix the high state level In our application the portion of Vcc is controlled by resistors R32 and R33 of Figure 3 http onsemi com 13 NCP1612GEVB Typically the pfcOK pin drives the feedback pin of the downstream converter controller or its brown out pin when available It is recommended to protect the pfcOK pin from surrounding noise This is the goal of Cig of Figure 3 In our application the Vcc latched off level is 33 Figure 17a shows the circuit latching off An external Vcc power source was applie
9. 16 and R17 of Figure 3 that are implemented to charge the Vcc capacitor at start up draw a large bias current Vin Vec Ris T Rie T Ry In these conditions we measured from the input voltage They are disconnected for this test 115 V 60 Hz 230 V 50 Hz nenw Ooo e o o oom o a The Vcc consumption is almost constant over the Vcc range e g 2 2 mA at 30 V low line It must be noted that the input power mainly results from static losses 2 e Discharge resistors for X2 capacitors R4 and R32 of Figure 2 consume ae that is about 7 mW at 115 V and 1 2 26 mW at 230 V e Two resistors sensing networks are implemented to sense the bulk voltage redundant bulk voltage monitoring At both 2 2 V puik Ta V puik Ret Rot Ry Ry Ro Ro3 Ryt Ros easily reduced if needed by using one single resistors divider for pins 1 and 2 and or by increasing the impedance of the sensing networks line voltages they consume that is about 72 mW These losses can be These static losses cost 79 mW at low line and 98 mW at used in accumulation mode W h measurement over high line As a matter of fact the losses linked to the PFC 6 minutes the result being multiplied by 10 to obtain the stage operation are very small averaged power The measurements were made at 25 C ambient temperature by means of a power meter CHROMA 66202 http onsemi com 5 NCP1612GEVB POWER FACTOR AND EFFICIENCY The NCP1612 evaluation board embeds a NTC to
10. NCP1612GEVB 160 W Wide Mains PFC Stage Driven by the NCP1612 Evaluation Board User s Manual Introduction Housed in a SO 10 package The NCP1612 is designed to drive PFC boost stages in so called Current Controlled Frequency Fold back CCFF In this mode the circuit classically operates in Critical conduction Mode CrM when the inductor current exceeds a programmable value When the current is below this preset level the NCP1612 linearly decays the frequency down to about 20 kHz when the current is nearly zero CCFF maximizes the efficiency throughout the load range Incorporating protection features for rugged operation it is furthermore ideal in systems where cost effectiveness reliability low stand by power and high efficiency are the key requirements Extremely slim the NCP1612 evaluation board is designed to be less than 13 mm high This low profile PFC Table 1 ELECTRICAL SPECIFICATIONS ON Semiconductor http onsemi com EVAL BOARD USER S MANUAL Stage is intended to deliver 160 W under a 390 V output voltage from a wide mains input This is a PFC boost converter as used in Flat TVs High Power LED Street Light power supplies and all in one computer supplies The demo board embeds the NCP1612 B version which is best appropriate for the self biased configuration The board is also configurable to have the NCP1612 powered from an external power source In this case apply a Vcc voltage that exceeds t
11. cy is not significantly reduced by CCFF that is above 20 load at low line and above 50 at high line see previous section the CCFF and CrM curves matches At lighter loads the efficiency is much improved with CCFF 20 27 51 76 100 Efficiency at 115 V Let s remind that CCFF works as a function of the instantaneous line current when the signal representative of the line current generated by the FFcontrol pin is lower than 2 5 V the circuit reduces the switching frequency This is the case near the line zero crossing whatever the load is Hence the switching frequency reduces at the lowest values of the line sinusoid even in heavy load conditions That is why the efficiency is also improved when the load is high This is particularly true at high line where CCFF has more effect than at low line since the line current is less 95 00 y d 87 00 85 00 9 20 27 51 76 100 Efficiency at 230 V Figure 8 Efficiency versus Load of the Evaluation Board red solid line of the Evaluation Board Operated in Full CrM purple dotted line In both Cases the NTC is Shorted Skip Mode When the instantaneous line current tends to be very low below about 5 of its maximum level in our application refer to 1 the circuit enters a skip cycle mode In another words the circuit stops operating at a moment when the power transfer is particularly inefficient This improves the efficiency in light load as
12. d and Vcc was externally raised until the pfcOK signal exceeds 7 5 V As a consequence the NCP1612 stops operating no drive pulse and pfcOK pin voltage is grounded No operation recovery is possible until either a brown out condition is detected or Vcc is decreased below the reset F a A A at A Pa 7 r 10 0 vidir a ieii 4000 Ward SO rath Ae EY 3000 V A 1O0 eft i fege bigaan HEIN TE a IT BBO 7030 pret LSTI re i Go ed T i r j Ey H ui iy a pfcOK being pulled up above 7 5 V the part latches off Rz T Rz If the pfcOK pin is pulled up above 7 5 V the NCP1612 latches off until a brown out situation is detected or Vcc is dropped below its reset level 5 V typically x 75y 32kK 120k gt 75V 306V 39k level 5 V typically Figure 17b shows operation recovery A 80 ms mains interruption was produced to trigger the brown out protection Vcc having been previously decreased below 30 V that is below the level leading the part to latch off The pfcOK signal turns high back when the bulk voltage has reached its regulation level 1 DD ii H7 ggi iaa li Akad AyD Homa Hy iach Sie Gage Parma ay Te y Wai w ir TIN y b the part recovers operation as a result of a mains interruption Figure 17 NCP1612 Latch Off Function BEHAVIOR UNDER FAILURE SITUATIONS Elements of the PFC stage can be accidently shorted badly soldered or damaged as a result of manufacturing incidents of an excessive
13. derlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2051 D
14. do not guarantee that a NCP1612 driven PFC stage necessarily passes all the safety tests and in particular the bypass diode short one since the performance can vary with respect to the application or the test conditions The reported results are intended to illustrate the typical behavior of the part in one particular application highlighting the protections helping pass the safety tests The reported tests were made at 25 C ambient temperature http onsemi com 15 NCP1612GEVB BILL OF MATERIALS Reference Qty Description Value Tolerance Part number Constraints Heatsink COLUMBIA TP207ST 120 12 5 STAVER NA SP 03 ane 680 nF through hole EPCOS B32922C3684K Es 220nF nF 277 ear through hole through hole EPCOS B32922C3224K Filtering 470 Eaa 450 E through hole E oa capacitor Bulk 68 uF 450 V through hole Rubycon 450QXW68M12 5X40 capacitor Electrolytic 22 uF 50 V through hole various various capacitor Diodes GBU406 4 A 600 V through hole LITE ON GBU406 Bridge me DM Choke 117 uH 75mQ mQ through hole through hole Pulse Engineering Pulse Engineering PH9OBINL NL Common 8 5 mH is mQ through hole Pulse Engineering a Mode Filter Lo 1 Boost 200 uH 6 Apk through hole Wurth Elektronik 750370081 EFD30 inductor Power IPA50R250 550 V TO220 Infineon IPA50R250CP MOSFET as MUR550 5 A 520 V ON Semiconductor MURSSOAPFG Bypass 1N5406 3 A 600 V Axial ON Semiconductor ee diode MMSZ33T2
15. e oe Current Table Current Graph Woss Table Vollage Graph Son Pane Version 1 038er 00 Chron Regulation Parameters is j5 230 V 50 Hz full load n Harmen Moaguremant Panel Yi Chin Regulation Pieypuied eat ET IE 000a Percent Ola Carri Lind Hiii Class D Parameters Fone Oye GH T save Report Save as f open ff rac _ Gurari Tobit Curio iraph Wobigi Tabit Valiy raph Soh Panel varaia 1 a Of oz ead Mirer i Messed kain Memes Hmi Cmr Vote L PASS PASS l Funny THD 115 V 60 Hz 20 load ack EZH CE Volege Gragh Soft Panel Version 1 030ta 00 i Harmonic Measurement Panel vi Chiro Regulation Parameters retis Current orig Region 012 5 1000 3 2 Vae pi Lia 00 Css Qarert Lind Ratio Class D Parameters al Seve Repot f Seve As Votege Tate 0 06 05 Ops 003 om 0f1 0 i i i i i i 7 i 7 2 4 8 8 0 12 14 6 18 DD 2 M2 2 0 2 OM 8 40 vV HA PA PF Cren VoRage Fain Fundy THOI V_Fund V w PASS PASS 230 V 50 Hz 20 load Figure 12 Performance with respect to IEC61000 3 2 Class D Requirements In the light of Figure 11 and Figure 12 we can see that the NCP1612 board easily passes the standard requirements in the considered conditions The least margin is observed at 230 V 20 of the load for class C for which harmonic 11 is closed to the limit We cou
16. en AMchege Curseurs Mecum Line Current 5 A div SidHar value x Tey cy Flt ir TOLD rein 10 0 Were 1 00 vd Bo mit 21r V ofa 73 i iz iTi us 186 my e 714 28805 Vi he 367 9 W a Load abrupt rise 100 Vite Momeni Amber FAT F Sahi w FAA OW ofst 110i Ake Fage Ndgatiwe the line current to about 3 A This sharp reaction dramatically limits the bulk voltage decay VpuLk stays above 365 V and recovers within about 15 ms One can further note that the VCONTROL rapidly decreases back to its new steady state level This is allowed by the use of a type 2 compensation DRE leads to the charge of the C10 capacitor to the high VcontTRoL level but Co is partly charged only Our compensation reduces to nearly zero the overshoot that can follow the fast response to an under voltage Fithier Werteal Bast aetnins Ceelenchemont Achage Curdirs Hra Line Current 5 A div Thea Pe ET k k k pa maae MH Thasa AT Jb ma ER 1 0 mividy 10 0 Vey 1 00 Ware 100 Wad TOs arer TIRY El 2270Y ohi PASO PAE AVAA 10i k Mis 1744 SU MHS Eazi H fi iiri IR 1A pii l tarv S226 mit LELE J EREET b Load abrupt decay Figure 15 Bulk Voltage Variations when the Load Changes from 100 to 400 mA 2 A us slope http onsemi com NCP1612GEVB Figure 15b shows the other transition from 400 mA to 100 mA Again the bulk voltage deviation is very small VBULK remains below 410 V This is because the soft Over Voltage Protection s
17. er They were measured at low and high line 1 e with respectively HA Harmonic Measurement Panel wi Save n on Piel verti 1 ia iG Dumei Tabish lurend Gah itibage T atii Waliy Garih ia Es Bee o i ad ce Os eiar B Se eae Hohe Bi i ay A 6E EJ INS BAENA Maarne Eut ur peri of PASS PASS Woe Ie ghee lier yi orl 2 4 amp 10 2 14 PAN PF _ Fiore 4p THD g s W Fomdivi 115 V 60 Hz full load Bi Harmonic Measurement Panel wi Ch ESS ES ESS Regulation Current Table Curent Graph Vobage Table weep Greph Soft Panel Version 4 03Betn 00 Regulation ls Vie HE is 1000 3 2 feo ars a Chiti Quant Lind Hilti a i75 3 15 1 heel Insel Tete sod et eed Te aed Vd ed ed ee Wt WM wa a Ha tet Ae ww wiv HAJ Py PF THE ob Jen 8 2 4 amp 10 12 Meane Start 3 Curioni ny o PASS we Funnel ip Vo Faredivi 230 V 50 Hz full load 115 V 60 Hz and 230 V 50 Hz being applied to the board and at two power levels full load and 20 of max load that could be considered as a worst case of this type of application Beal Harmonic Measurement Panel i GE Pe MGR ERE Current Table Current Groph Wete Table Votage Graph Version 1 00 amp ete 00 Bagai LECH 1000 32 o ae ne Piria a 2 r F oral 5 eset ast kar hd eed
18. h When this current is lower than a preset level the frequency linearly decays to about 20 kHz CCFF maximizes the efficiency at both nominal and light loads In particular stand by losses are minimized To further optimize the efficiency the circuit skips cycles near the line zero crossing where the power transfer is particularly inefficient This is at the cost of some current distortion If superior power factor is needed forcing a minimum 0 75 V voltage on the FFcontrol inhibits this function Practically the FFcontrol pin of the NCP1612 generates a voltage representative of the instantaneous line current When this voltage exceeds 2 5 V the circuit operates in CrM If the FFcontrol voltage is below 2 5 V the circuit forces a delay or dead time before re starting a DRV cycle which is proportional to the difference between 2 5 V reference and the FFcontrol voltage This delay is maximum when the FFcontrol voltage is 0 75 V about 45 us so that a nearly 20 kHz operation is obtained Below this 0 75 V level the circuit skips cycles Like in FCCrM controllers internal circuitry allows near unity power factor even when the switching frequency is reduced http onsemi com NCP1612GEVB 10 0 mvd 32 300 mv SOU u7 li SOO pehin Noma 7Imy 0 GS Luge 100 Wore EOD rev View 342 0 V ofa 1 9750 3 s00 kS 1 406V 2 1006 Vv 410 nv ls 27496 49 c Low frequency near the line zero crossing Poutwe b Reduced
19. he NCP1612B start up level 18 2 V max to ensure the circuit start of operation or solder the NCP1612A instead The low Vcc start up level of the A version 11 25 V max allows the circuit powering from a 12 V rail Both versions feature a large Vcc operating range from 9 5 V up to 35 V esto t tne FewenoyRawe E a Minimum Efficiency At 20 Load 115 Vims 93 Minimum PF Over The Line Range At Full Load Hold Up Time the output voltage remaining above 300 V Peak To Peak Low Frequency Output Ripple H Z dc dc S S Publication Order Number EVBUM2051 D Semiconductor Components Industries LLC 2012 1 April 2012 Rev 1 NCP1612GEVB THE BOARD HIGH VOL TAGE HOT PARTS NCP161 DEMO A 1LS Figure 1 A Slim Board Height lt 13 mm APPLICATION SCHEMATIC ut gt D2 eee 1N5406 Rth1 B57153S150M 4 L2 D1 200 uH np ns 10 MUR550 C4 220nF Type X2 D3 1N4148 pe Q1 IPA50R250 Q2 R4 CM1 MMBT589LT1G 10k C6b so 3 68uF 450V Ly c3 680nF Type X2 C7 D4 22uF 50V N Fi 1N4148 L N Earth l H Socket for 90 265 Vrms External VCC Power Source Figure 2 Application Schematic Power Section If an external Vcc voltage is applied to the board as allowed by the socket for external Vcc power sourcing it should be noted that the NCP1612 latches off if this voltage exceeds about 30 V see pfcOK section In this ca
20. imum load point and decays when the power demand diminishes due to the increasing impact of the switching losses Curves of Figure 7 meet this behavior in the right hand side where our demo board resembles a traditional CrM PFC stage In the left hand side the efficiency normally drops because of the switching losses until an inflection point where it rises up again as a result of the CCFF operation As previously detailed CCFF makes the switching frequency decay linearly as a function of the instantaneous line current when it goes below a preset level As detailed in 1 the CCFF threshold is set to 17 of the line maximum current Hence the PFC circuit switching frequency is permanently reduced when the power is below 17 of its maximum level at 90 V and below about 50 at 265 V That is why the aforementioned inflection point is around 20 of the load at low line and 50 of the load at high line as confirmed by the curves of Figure 8 http onsemi com 6 NCP1612GEVB Efficiency comparison to a traditional CrM operation 3 V have been forced on the FFcontrol pin of the NCP1612 so that the circuit CCFF function is disabled Hence the PFC Stage operates in a traditional critical conduction mode CrM in all conditions Figure 8 compares the efficiency with CCFF evaluation board to that without CCFF Otherwise said CCFF operation is compared to the traditional critical mode solution As expected as long as the switching frequen
21. ld check that inhibiting the skip mode forcing a 0 75 V minimum voltage on the FFcontrol significantly increases the headroom PROTECTION OF THE PFC STAGE The NCP1612 protection features allow for the design of very rugged PFC stages Brown out An external 15 V Vcc power source is applied to the board The load is 100 mA The rms input voltage is decreased with 0 1 V steps Vin ms BOL 71 3 V rms line voltage below which the circuit stops operating Vin rms BOH 78 6 V rms line voltage above which the circuit starts to operate http onsemi com 10 NCP1612GEVB a Start of operation when Vin rms exceeds Vin rms BOH NCP1612B ram r mo rive iain ried 5 Mi rey 4 00 Wie E RLY a LiD Y PA Oy mial T0 ke Tia prey ae 1465 be CEEE b Start of operation when Vin rms exceeds Vin rms BOH NCP1612A ETE aS tT UTE rob GERI 0 Greia Homa MUY Le ks Eje Miji VcoNTROL gradual decrease j i 50 ms blanking time Ott ta lL Moms Norm Fay 100 Via m 70 GY otal COU ES JU DE Laje Migi c Abrupt line drop 90 V to 70 V Figure 13 Brown Out Operation Figure 13a shows the re start when the input voltage exceeds the 78 6 V BOH level with the NCP1612B The circuit sharply restarts for a minimized recovery time Figure 13b shows the same when the NCP1612A is used instead of the NCP1612B In this case the circuit smoothly recovers operation soft start Figure 13c shows
22. limit the in rush current that takes place when the PFC stage is plugged in The NTC placed in series with the boost diode This location is rather optimum in term of efficiency since it is in the in rush current path at a place where the rms 99 00 98 00 97 00 96 00 94 00 E 93 00 y m 92 00 91 00 90 00 9 0 27 1 76 100 Efficiency at 90 V 99 00 98 00 97 00 ee a 96 00 e AES EE ERE unt i 95 00 A 94 00 93 00 92 00 91 00 90 00 9 0 27 1 76 100 Efficiency at 230 V current is less compared to the input side However this component still consumes some power That is why the efficiency is given with the NTC and with the NTC being shorted 99 00 98 00 97 00 96 00 95 00 94 00 93 00 92 00 91 00 90 00 95 00 94 00 93 00 92 00 91 00 90 00 Efficiency at 265 V Figure 7 Efficiency versus Load of the Evaluation Board blue dotted line of the Evaluation Board where the NTC is shorted red solid line Figure 7 displays the efficiency versus load at different line levels When considering efficiency versus load we generally think of the traditional bell shaped curves At low line the efficiency peaks somewhere at a medium load and declines at full load as a result of the conduction losses and at light load due to the switching losses At high line the conduction losses being less critical efficiency is maximal at or near the max
23. load A 15 V Vcc power source was applied to the board http onsemi com 11 NCP1612GEVB Fichier Vertical Base detemps Declenchement Affichage Curseurs Mesure Math Analyse Utilitaires Aide C4 P2 mean t 3 Tay toy Measure P1 pkpk C2 value 4g status Y BEMO DC IM 10 0 m idiv 50 0 Vidiv 60 0 Vidiv 3 260 5 ofst 5 501 mY 1 I 385 0 Y 5 999 mY f 149 382 6 Y 11 501 mi Ay 900 mv lA 3 A 2 4V 9 800 mY 114 0 ofst P3 period C1 19 977411 ms VBULK P4 fregiC1 PS width C1 P width C1 50 05654 Hz 10 022719 ms 10 022719 ms vd ma av ma Thase 17 6ms8 Declenc iii 5 00ms div Unique 362 0 Y 00 ks 2 0MSis Edge Positive TIS 3 ign 1 Waiting for Trigger Figure 14 Over Current Situation 85 V 0 5 A Load Current DYNAMIC PERFORMANCE The NCP1612 features the dynamic response enhancer DRE that increases the loop gain by an order of magnitude when the output voltage goes below 95 5 of its nominal level This function dramatically reduces undershoots in case of an abrupt increase of the load demand As an example Figure 15a illustrates a load step from 100 to 400 mA 2 A us slope at 115 V One can note that as a result of the DRE function the control signal VCONTROL steeply rises when the bulk voltage goes below 370 V leading to a sudden increase of the line current in our case this is so sharp that the over current protection trips to limit tf Seer se tomos COCrcham
24. oftOVP triggers when VguLK exceeds 105 of its nominal voltage and prevents the DRV from pulsing until VpuLK has dropped down to a safe level 103 of its nominal voltage Figure 16 shows a magnified view of Figure 15b It illustrates the gradual interruption of the drive pulses flow for a reduced acoustic noise The circuit reduces the power delivery by smoothly decaying the on time to zero within Fichier Yertical Base detemps Declencherment Affichage Pi crisetc 20 731 us P2 falliC value status Gey 7 Od Vv T 2 99 10 my 19 ry 296 W 10 0 pS i 4055Y CUrseurs P3 periodici 10 0 ps about 50 us that is 2 to 10 switching periods according to the conditions of a typical application If the output voltage rise is so fast that VBuLK still significantly increases during this braking phase the fast OVP protection FOVP immediately disables the driver when the pin1 voltage exceeds 107 of the 2 5 V voltage reference In other words if as generally done pin1 and the feedback pin receive the same portion of the bulk voltage the FOVP comparator triggers when the bulk voltage is 107 above the regulation level Mesure Math Analyse Utilitaires Aide V CONTROL ten eee eae eee P4treqie 1 22 604659 kHz Poswidth il 1 2 407 Us PB dutyict Z4 Declench ieee 50 0 4 1 00 rmesidiv Arr ter 10 0 ps 100 kS 10 MWErsl Width d 14 8200 ms 4 10 0 ps Neqativ SO082011 18 20 31 Figure
25. s on a NCP1612 driven PFC stage Application note AND9079 D http www onsemi com pub_link Collateral AND9079 D PDE 3 NCP1612 Data Sheet http www onsemi com pub_link Collateral NCP1612 D PDF 4 NCP1612 design worksheet http www onsemi com pub Collateral NCP1612 20DWS XLS 5 NCP1612 evaluation board documents http www onsemi com PowerSolutions supportDoc do type boards amp rpn NCP1612 ON Semiconductor and uD are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the
26. se unplug the PFC stage to recover operation In all events do not apply more than 33 V to the Vcc socket not to exceed the DZ reverse ZENER voltage see Figure 2 http onsemi com 2 NCP1612GEVB Viine Vbulk R8 560k R29 R28 R27 R17 R16 R15 1800k 1800k 560k 120k 120k 120k R22 WN NWN WN Vin 560k R9 R30 1800k 27k 017 inF v R23 cc 1800k BUY R32 D5 R10 120k D6 ia nF 1N4148 R11 1800k 1N4148 10nF 27 27k yv R24 N pfcOK I aux 1800k ca y 10 T T R20 1nF 7 7 4 7k i I R7 R25 s 1800k 3 8 DRV 4 7 R21 4 7k _ cto 5 a l sense R2 T 220nF 27k y C11 R26 R33 DZ1 120k C16 ice bee e C18 lL 39k G15 bane T 470pF T 2 2uF 270k 120k 10nF T T 220nF 4 4 e GND Figure 3 Application Schematic Control Section GENERAL BEHAVIOR TYPICAL WAVEFORMS s1uaT ii p r i Fit elie ay RFR LED IMON pitisi TANMEN AN Hy 20 800 red 4 j x ika 10ko Rage Fons z 600 rel i T T T MERT Hi iJ Figure 4 General Waveforms at Full Load CCFF OPERATION The NCP1612 operates in so called Current Controlled Frequency Fold back CCFF where the circuit operates in Critical conduction Mode CrM when the instantaneous line current is medium or hig
27. shown by Figure 10 The dotted line portrays the efficiency when skip mode is inhibited by forcing a 0 75 V minimum voltage on the FFcontrol pin The efficiency is improved below 20 of the load at low line while some benefit is visible starting from 50 of the load at 230 V http onsemi com 7 Fichier Vertical Base de temps D clenchement Affichage Curseurs Measure value status ci GEG C2 10 0 midi NCP1612GEVB Line Current 2 hav DCM i 100 Widiv SOO miviciv 10 0 Viiv 5 1 9750 9 30 Y offset j 10 mi 320 m Mesure Thase 3 4m 5 WU rs Magativ 14 454 ms ree en pao qe o7 l he oa x 310 mi 191 272011 16 45 04 Figure 9 The Circuit Skips Cycle Near the Line Zero Crossing 265 V 20 Load 99 00 99 00 98 00 98 00 97 00 97 00 96 00 96 00 95 00 95 00 94 00 94 00 93 00 93 00 92 00 92 00 91 00 91 00 iii 90 00 9 20 27 51 76 100 9 20 27 51 76 100 Efficiency at 115 V Efficiency at 230 V Figure 10 Efficiency versus Load of the Evaluation Board red solid line and of the Evaluation Board where Skip Mode is Disabled green dotted line In both Cases the NTC is Shorted http onsemi com 8 NCP1612GEVB POWER FACTOR PF AND TOTAL HARMONIC DISTORTION THD Figure 11 Figure 12 reports the NCP1612 board performance with respect to the IEC61000 3 2 class C class D standards requirements These results were obtained by means of a CHROMA 66202 Digital Power Met
28. the NCP1612 behavior when the line voltage becomes too low NCP1612A or NCP1612B The line is abruptly changed from 90 V to 70 V at full load As a line drop result the bulk voltage decreases and in response Over Current Protection OCP The NCP1612 is designed to monitor the current flowing through the power switch A current sense resistor R3 of Figure 2 is inserted between the MOSFET source and ground to generate a positive voltage proportional to the MOSFET current Vcs When Vcs exceeds a 500 mV internal reference the circuit forces the driver low A 200 ns blanking time prevents the OCP comparator from tripping because of the switching spikes that occur when the MOSFET turns on the circuit increases the control signal VcoNTROL This lasts for the 50 ms blanking time of the brown out function At the end of the 50 ms delay a brown out situation is detected VCONTROL is gradually reduced down to its bottom clamp value 0 5 V leading the line current to steadily decay as well When VCONTROL has reached 0 5 V the circuit stops pulsing and grounds the VconTROL pin to ensure a clean resumption including soft start with the NCP1612 A version when the line is brought back to a level allowing operation In our application the theoretical maximal line current is 1 300 mV l XxX LA k x 80 mO that is about 3 Figure 14 shows the line current when clamped The over current situation was obtained at 85 V with a 500 mA

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