AN10535 LPC2138 extreme power down application note
Contents
1. L y Loy xa GND LA 74LS244DW 74LS244DW U3B C22 C21 10uf d Y GND GND eo gt eo T x Ri x 2L VIN GND RAPC712 J1 power supply Fig 9 Detailed schematics LPC2138 EEPROM l meter page 4 AN10535 1 NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 23 of 27 900c Jequieoeg 9 L0 Agen 91ou uoneoijddy Le JO ve L SESOLNV peniesed sjuDu Iv 9002 A9 dXN O GND 81 82 82 83 89 84 94 7 85 85 86 86 87 Sf x 88 98 Ze 89 89 90 90 c 91 G 92 2 ecc 93 3 g4 4 95 96 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 66 e BI 68 68 69 69 70 JU em 71 Tq 72 yo 73 13 74 714 75 a 76 dr gt 77 4 i 78 1B me 79 ar 80 ue TJ 71 al Pd AE PS Pd O O50 O5 O9 Ch Co AO Co jp cO CO on 79 50 ay aL 5 52 53 53 54 54 55 55 56 56 57 57 58 D I 59 59 60 60 61 61 62 62 63 SS ed 64 C D O D C On Cn Cni cn ja an On n cn on B Aji BO co 100 pu Cn JS to RSS CO eo Fig 10 Detailed schematics LPC2138 EEPROM l meter page 5 ap Y 19 36 20 s 21 38 22 39 SI 23 40 49 24 49 747 SHUT DOWN2. else printr s2u local hour display minute s if local min 10 printr s1uslu 0 local min else printr 2u locgal mim display second s if local_sec lt 10 printf 1u 1u 0 local sec else printf 2u local sec Application note Rev 01 6 December 2006 LPC2138 extreme power down erase EEPROMO status response ee 0 reading of status write data in EEPROMO NXP B V 2006 All rights reserved 19 of 27 900z 1equie eg 9 L0 Aen 9jou uoneorddy Ze JO 0c SESOLNV pamasa sjuDu iv 9002 A9 dXN 11 Appendix C EXTERNAL EEPROM MICROCHIP_25AA 5V_SUPPLY CJINPUT LO N C JINPUT HI 5V RETURN ANALOG COMM DP3 BAR N C BACKLIGHT GND DP2 BAR REF OUT DP1 BAR REF IN R21 1k 1k Q PRIME R22 R30 1k Q OUT VIN Fig 6 Detailed schematics LPC2138 EEPROM l meter page 1 MEMORY Ie WV GND gt CURRENT_METER_OUT CURRENT METER CIRCUIT R29 1k NY GND GND MAX4544CPA in D e R31 10 WV GND GND C23 0 1uF GND MAX4172EUA I SENSE me BCX71SMD T2 CURRENT METER OUT UMOP 49Mod euiaJ1xe geLzod 1 SESOLNV SJOJONPUODIWIS dXN NXP Semiconductors AN1 0535 LPC2138 extreme power down n LL E u 2 2 2 T Izo o a 165 z z gt D E ii Os 0 227 E gt z a Ojo O MS SAS MS CAE a gt d Y xool sea A c o2 S dv AYM
3. LPC2138 extreme power down 126 197 Initialize Initialize EEPROM 128 IODIRO 0x00000080 Initialize chip select 129 130 init SOSPSR Initialize status 131 init S0SPDR Initialize data reg E 133 IOCLRO 0x00000080 Initialize write enable 134 135 SOSPDR 0x06 Write latch enable command 136 while SOSPSR SOSPIF 0 Check if command is sent 137 138 IOSETO 0x00000080 Complete write enable 139 IOCLRO 0x00000080 Enable chip select 140 141 SOSPDR 0x02 Write command 142 while S0SPSR amp SOSPIF 0 Check if command is sent 143 144 S0SPCR 0x24 Enable 16 bit 145 146 SOSPDR writeloc Write location 147 while SOSPSR SOSPIF 0 Check 1f command 1s sent 148 149 SOSPCR 0x20 Enable 8 bit 150 151 for 2 0 2 lt 25 9 zezt8 Write loop for 4 cycles of 32 bit data 152 153 shiftvar shiftvar gt gt z 154 byte var amp shiftvar 155 byte byte gt gt 24 2 156 157 S0SPDR byte 158 while SOSPSR SOSPIF 20 159 160 161 IOSETO 0x00000080 Disable chip select 162 163 164 s imitializing EEPROM for first LE AH D HDEBRDDADEREB E A IAEA 165 void initread int readloc 166 167 Initialize Initialize EEPROM 168 IODIRO 0x00000081 Initialize chip select and test pin p0 0 169 170 init SOSPSR Initialize status 171 init SOSPDR and data register 172 173 IOCLRO 0x00000080 Enable chip select
4. 1 Shifts to next LED bit 84 if mask 0x01000000 checks if last location 85 86 IOSET1 mask blinks next LED 87 for cnt Us cnt ns cater Delay 88 89 else 90 mask 0x00010000 T1f LED was last bit this will set to first 91 92 93 94 95 96 Checking the nemory T A I HH P P HT E P P P P HH ARENA TTL 97 void memcheck void 98 99 inc 0 100 initial 0x00010000 101 for p p 9 ptt 102 103 m Var 104 m m amp initial 105 initial initial lt lt 1 106 m m gt gt 164p 107 if m 0x00000001 108 109 1nc 110 111 112 113 Memory Check Initialize Initialize Loops through all 8 bits essential to LED Stores EEPROM data into new variable Bitwise add Shifts reference bit to next Checks if bit in new variable is 1 Increments 119 EE SPL ATT ASA AOS 115 void Initialize 116 4 117 PINSELO 0x1500 118 VPBDIV 0x1 119 SOSPCCR 0x6 120 SOSPCR 0x20 121 122 Configure Pin Connect Block Set pclk to same as cclk Set to highest speed for SPI at 10 MHz Device selected as master 123 Writing to EEPROM EULA TP HE E HE EET P P P HH HP P T P P P PH P P B B MU HH E T P P P P HH T T T T T P TL TL 124 void write int var int writeloc 125 4 AN10535 1 NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 13 of 27 NXP Semiconductors AN1 0535
5. 0x0D if IOPINO amp 0x00004000 220x00000000 ee temp id EE REC ID user s code MUST provide valid record ID ee temp ee id 0 ee temp count loop cnt ee temp SEC SEC ee temp MIN MIN ee temp HOUR HOUR status response ee 0 command ee unsigned int amp ee0 temp ee write 0 command ee response ee write data in EEPROMO status response ee 0 NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 18 of 27 NXP Semiconductors AN10535 102 103 104 105 106 107 108 109 110 111 112 LES 114 EL 116 if status NO SPACE IN EEPROM ee erase 0 command ee response ee command ee unsigned int amp ee0 temp ee write 0 command ee response ee status response ee 0 printf n nData saved Power down mode entered An while UOLSR amp 0x60 20x60 PCON 0x02 while 1 117 void display time short int count 118 119 120 121 122 123 124 125 126 121 128 129 130 131 132 133 134 L35 136 137 138 133 140 14 142 AN10535 1 unsigned long int time capture local hour local min local sec time capture CTIME0 local hour time_capture gt gt 16 amp 0x0000001F local min time capture 8 amp 0x0000003F local sec time capture amp 0x0000003F printf count 34u time count display hour s if local hour 10 printr sluslu 0 lo06al hour
6. 174 175 SOSPDR 0x03 Read command 176 while SOSPSR SOSPIF 0 Check if command is sent AN10535_1 O NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 14 of 27 NXP Semiconductors AN10535 17 178 179 180 181 182 183 184 185 186 187 188 Log 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 Al SE AR 2 13 216 211 218 219 220 221 222 223 224 229 226 221 SOSPCR 0x24 SOSPDR readloc while SOSPSR SOSPIF 0 SOSPCR 0x20 SOSPDR 0x0 while S0SPSR SOSPIF 0 READ SOSPDR Var READ 24 SOSPDR 0x0 while SOSPSR SOSPIF 0 READ SOSPDR READ READ 16 Var Var OxFF000000 READ READ amp 0x00FF0000 Var Var READ SOSPDR 0x0 while S0SPSR SOSPIF 20 READ SOSPDR READ READ 8 Var Var OxFFFF0000 READ READ amp 0x0000FF00 Var Var READ S0SPDR 0x0 while S0SPSR SOSPIF 0 READ SOSPDR READ READ 0 Var Var OxFFFFFFO0 READ READ amp 0x000000FF Var Var READ IOSETO 0x00000081 LPC2138 extreme power down Enable 16 bit Read location Check if command is Enable 8 bit Read first 8 bits Check if command is Store into read variable Shift to next 8 bits Read Second 8 bits Check if command is Store into read variable Read Second 8 bits C
7. 49 command_ee unsigned int amp ee0 ini 50 ee write 0 command ee response ee AN10535 1 Application note Rev 01 6 December 2006 NXP B V 2006 All rights reserved 17 of 27 NXP Semiconductors AN10535 5l 02 Sm 54 55 56 94 58 S 60 61 62 63 64 65 66 67 68 69 10 71 12 13 14 19 16 n 18 19 80 81 02 83 84 85 86 81 88 89 90 91 92 23 94 23 96 21 98 23 100 101 AN10535 1 xe ee Y stat ee ee ee ee ee0_ ee ee0_ in CCR CCR CCR CCR ILR CIIR AMR SEC MIN HOUR CCR se loop prin whil LPC2138 extreme power down Status response ee 0 ad the last Flash entry ead 0 command ee response ee us response ee 0 pnt struct ee data response ee l read id ee0 pnt 1d read ee id ee0 pnt ee id read count reel pnt count read SEC ee0 pnt SEC read MIN ee0 pnt MIN read HOUR reel pnt HOUR itialize the RTC 0x00 0x02 0x00 0x10 0x03 Clear the Interrupt Location Register 0x01 Increment of seconds generates an interrupt OxFF Alarm interrupts are not allowed ee read SEC ee read MIN Gel read HOUR 0x11 t the time and counter Cnt ee read count EEUU um nuns el if ILR amp 0x01 0x01 ILR 0x01 loop_cnt loop_cntt 1 amp 0x3FF display time loop cnt putchar
8. When the LPC2138 is switched off using the external control circuit the following currents were measured Room temp current 100 nA 125 C data 200 nA 3 2 Startup time As shown in the Fig 2 below the start up time is 856 us 2 96 The power signal is the top signal shown labeled POWER followed by the RESET which rises with an RC constant As a sufficient number of cycles are counted from the crystal the microcontroller will start the execution of a stored code as shown by the P0 0 output pin set high AN10535 1 NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 4 of 27 NXP Semiconductors AN10535 LPC2138 extreme power down 2 00V E 200v RH 2 00V B AX 856 000000us a Mode Normal 200 08 Trigd 4 1 40V y 404 08 BAY 0 0V _ SE 856 000us m 1 AX 1 1682kHz a Source X Y X1 POWER PICA 0 0s Fig 2 Time to start up AN10535 1 3 3 3 4 3 5 Current drawn The measured current into the system during normal operation with the MCU working at 60 MHz is between 60 mA to 68 mA During extreme power down mode the system draws less than 100 nA Transistor voltage drop The voltage drop between the emitter and collector of the PNP transistor is 42 mV during normal operation while 2 9 V during extreme power down GPIO pins When using this method to conserve power it is important to make sure the alway
9. 01 Turning off test pin to show in shutdown write mask 0x0 Store data to external EEPROM IODIRO 0x00800000 set port 0 23 as an out IOCLRO 0x00800000 Sets extreme power down mode IOSET1 mask Continue blinking where it left off for ent Ds cone ni antes Delay IOCLR1 0Ox00FF0000 Turns off LED for ant 0 cnt lt ne ont Delay mask mask lt lt 1 Shifts to next LED bit if mask 0x01000000 IOSET1 mask blinks next LED tor cnt 0 ent lt ne antri Delay checks if last location else mask 0x00010000 1f LED was last bit this will set to first mask 0x00010000 If external EEPROM was empty this will initialize first bit while 1 if IOPINO 0x00004000 0x00000000 check p0 14 is pushed Looks for the interrupt button to be pushed IOCLRO 0x00000001 Turning off test pin to show in shutdown NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 12 of 27 NXP Semiconductors AN10535 LPC2138 extreme power down 15 write mask 0x0 Store data to external EEPROM 16 IODIRO 0x00800000 set port 0 23 as an out Zi IOCLRO 0x00800000 Sets extreme power down mode 18 19 IOSET1 mask Continue blinking where it left off 80 for cnt 0 cnt lt n entt4 Delay 81 IOCLR1 0x00FF0000 Turns off LED 82 for cnt 0 cnt lt n entt4 Delay 83 mask mask lt lt
10. 33 P0 26 94 P0 27 a 38 P0 31 25 e zs SEH SS SN Ge 42 26 43 27 _ 44 28 45 29 46 30 47 GO I5 TD N2 ND N2 S2 TR RO R2 RO QC o o JO On Lo TN ff O0 amp C2 109 KS h5 h5 TRO TRO RO ho RO ho ho M co C0 Go N2 9 31 OO OO JO anh wh A 00 JO om P oh A co co 4 D Cr Co Ro e lolo E Go po C cm 3V3 PO O PO 1 P0 2 P0 3 PO A P0 5 P0 6 P0 7 P0 8 P0 9 P0 10 P0 11 P0 12 P0 13 P0 14 P0 15 P0 16 GND UMOP JOMOd euiaJ1Xe 8 12d SESOLNV SJOJONPUODIWIS dXN NXP Semiconductors AN10535 12 References AN10535 1 1 2 3 4 5 6 7 LPC2138 extreme power down UM10120 LPC2138 User manual EEPROM emulation application note BCX71 datasheet 25AA160A datasheet Kemet Ceramic capacitors datasheet ERJ Precision Thick Film Chip Resistors datasheet 74LVC1G74 datasheet NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 25 of 27 NXP Semiconductors AN10535 13 Legal information 13 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herei
11. AN10535 LPC2138 extreme power down application note Rev 01 6 December 2006 Application note Document information Info Content Keywords LPC2138 extreme power down Abstract This document describes a method to power down the LPC2138 so the power down current is less than 1 WA This method requires a few simple external components founded by Philips NXP Semiconductors AN1 0535 LPC2138 extreme power down Revision history Rev Date Description 01 20061206 Initial version Contact information For additional information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com AN10535 1 NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 2 of 27 NXP Semiconductors AN1 0535 LPC2138 extreme power down 1 Introduction The LPC2138 is a high performance single supply ARM7 microcontroller which has several power down modes that are used to conserve power when the microcontroller is waiting for something to do In power down mode the LPC2138 consumes about 60 uA from the 3 3 V supply at room temperature with the brown out enabled and around 30 uA when the brown out is disabled This is relatively good considering that this part is constructed using a deep sub micron process However at high temperatures the leakage current increases significantly The purpose of this app note is to describe a low cost m
12. Initialize read memcheck void Memory check function counts number of bits in location 16 23 of the first four bytes t byte var z init writevar currentloc loc limit initialize variables t shiftvar OxFF000000 t inc initial m p II to kyle po nsigned int j pon O NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 11 of 27 NXP Semiconductors AN1 0535 A A CO CO CO CO CO CO CO CO WH U PR PS P5 YH PL P O WO OO DW Ol A WH PO RP DW oO OO DBD OO A me FP He He LHe LHe 4 co u cC Q1 GO 5 LP Ot gl A kA CG WJ Ov A DW OO CO OF OF OF OQ OFT OT N FR DW WYO OO DW O1 A WW DP 63 64 65 66 67 68 69 10 71 12 13 14 LPC2138 extreme power down int ent n 300000 int mask set READ recall Var readloc CG void main void IODIRO 0x00000081 P0 1 amp P0 7 are output pins IOSETO 0x00000001 Testing pin when data will first come out IODIRI 0x00FF0000 Initializing LEDs initread 0x0 Calling function to initialize EEPROM for reading read 0x0 Reading current data in external EEPROM memcheck memory check it ine 13 checks 1f memory has valid data mask Var Restores into internal RAM data from external EEPROM while 1 else AN10535_1 if IOPINO amp 0x00004000 0x00000000 check p0 14 is pushed Looks for the interrupt button to be pushed IOCLRO 0x000000
13. Ol c e Es rm O a o Lo z ES E O E _ E MS Et 1NOTYILINTIN3YENO D z a Q e MS CAE EN 7 d a el O C Wal 6 LL 3 en oso 2 THIN27MS el th s E S 3OVIT1O A MS O L E O e e al zd ai o INIH O aWsLzxoa e aD LINO YSLAW INS LL O a ER z Lu a co r S oF wa A T N 2 S E X o Tgr z 6 pm CAE 3 S Y N 3 x g z One S ig De O c My 74 Er zZ 5 Su Oo or O o S e E O E E m o A TE D S e O iL AN10535 1 NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 21 of 27 9002 Jequie28g 9 LO Aen 9jou uoneoijddy Le JO cC SESOLNV pamasa sjuDu ilv 9002 A9 dXN Si a gt e UP_RESET H Tr a gt C14 0 1uF VDDA3 GND VREF x BAT uii 5 XTAL1 B o XTAL2 C1 C2 D RTCX1 22pf 22pf RTCX2 GND C3 C4 GND 22pf gt GND GND RTCK TDO TDI TCK TMS TRST o Cn Iho O M a co da C2 63 I e o NO o 3 5 B3 Cn cn Od Mo IS 62 C2 s la on QN IO A 00 hw C CO co MJE LO d GND VDD3 2 VDD3 3 VSS VSS VSS VSS VSS VDDA3 VSSA VREF VBAT XTAL1 XTAL2 LPC213X RTCX1 RTCX2 P1 16 PU TRACEPKTO P1 17_PU TRACEPKT1 P1 18 PU TRACEPKT2 P1 19 PU TRACEPKT3 P1 20 PU TRACESYNC P1 21 PU PIPESTATO P1 22 PU PIPESTAT1 P1 23 PU PIPESTAT2 P1 24 PUTRACECLK P1 25 PU EXTINO P1 26
14. PU RTCK P1 27 PU TDO P1 28 PU TDI P1 29 PU TCK P1 30 PU TMS P1 31_PU TRST Fig 8 Detailed schematics LPC2138 EEPROM l meter page 3 TXDO PWM1 P0 0 End RXDO PWMS EINTO PO 1 25 50 2 SCLOICAPO OPO2 k H SDAO MATO O EINT1 P0 3 k SCKO CAPO 1 AD0 6 P0 4 k 50 4 MISOO MATO 1 80 7 P05 55 neS MOSIO CAPO 2 AD1 0 P0 8 37 50 8 SSELO PWM2 EINT2 P0 7 3V3_SW TXD1 PWM4 A1 1 P0 8 Go RXDPWMB EINTSPOS 35 ES RTS1 CAP1 0 AD1 2 P0 10 k EE CTSWCAP1 115CL1 P0 11 59 11 DSR1 MAT1 0 AD1 3 P0 12 k DO 12 DTRIMAT1 1 AD1 4 P0 13 k F013 DCD1 EINT1 SDA1 P0 14 4 DO 14 RH EINT2 AD1 5 P0 15 R17 47k P0 14 EINTO MATO 2 CAPO 2 P0 16 45 ae CAP1 2 SCK1 MAT1 2 P0 17 k 50 17 CAP1 3 MISO1MATI 3 P0 18 27 G MAT1 2 MOSI1 CAP1 2 P0 19 ze G MAT1 3 SSEL1 EINT3 P0 20 a PWMS AD1 6 CAP1 3 P0 21 ee AD1 TICAPO OIMATO O P022 58 SHUT DOWN CURRENT METER OUT R23 INT_JMP ADO 4 AOUT PO 25 25 P0 25 ADO 5 P0 26 E P0 26 ADO O CAPO 1 MATO 1 P0 27 Es P0 27 ADO 1 CAPO 2 MATO 2 P0 28 P0 28 INT JMP ADO 2 CAPO 3 MATO 3 P0 29 e P0 29 K ADO 3 EINT3 CAPO 0 P0 30 P0 30 zZ P0 31_PU 17 P0 31 Q 01uF aie GND GND T 3V3 SW R16 Es LU LO LU c 0 01uF T GND GND UMOP JOMOd euiaJ1Xe 8 12d SESOLNV SJOJONPUODIWIS dXN NXP Semiconductors AN1 0535 LPC2138 extreme power down 089 Ok Idd iS 089 MM d AE
15. SPDR 0x0 25 while SOSPSR SOSPIF 0 260 READ SOSPDR 261 READ READ 0 262 Var Var OxFFFFFFO0 263 READ READ amp 0x000000FF 264 Var Var READ 265 266 IOSETO 0x00000081 204 268 LPC2138 extreme power down Check if command is sent Enable 16 bit Read location Check if command is sent Enable 8 bit Read first 8 bits Check if command is sent Store into read variable Shift to next 8 bits Read Second 8 bits Check if command is sent Store into read variable Read Second 8 bits Check if command is sent Store into read variable Read Second 8 bits Check if command is sent Store into read variable Disable chipselect ZOD JL RUNE TCU TU T E TUE EPI TT PI UC UC e a ur TUI Iu AN10535 1 NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 16 of 27 NXP Semiconductors AN10535 LPC2138 extreme power down 10 Appendix B 1 xx kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkK i 3 EE demo C Use of LPC213x on chip Flash as an EEPROM St 4 For details on an EEPROM specifications see LPC2k_ee h file 5 ju d 6 Following functions are specified in LPC2k ee c file xy 7 e d 8 ee erase command ee result ee erases all EEPROM 9 ee write command ee result ee writes record of ee data defined in LPC2k ee h zi 10 ee rea
16. To GND uA p0 0 0 0 p0 16 0 0 pO 1 0 0 p0 17 0 0 p0 2 11 0 p0 18 0 0 p0 3 11 0 p0 19 0 0 p0 4 0 0 p0 20 0 0 p0 5 0 0 p0 21 0 0 p0 6 0 0 p0 22 0 0 pO 7 0 0 p0 23 0 0 p0 8 0 0 p0 25 j p0 9 0 0 p0 26 0 0 p0 10 0 0 p0 27 0 0 p0 11 11 0 p0 28 0 0 p0 12 0 0 p0 29 0 0 p0 13 0 0 p0 30 0 0 p0 14 0 0 p0 31 0 0 p0 15 0 0 p0 32 0 0 NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 6 of 27 NXP Semiconductors AN10535 LPC2138 extreme power down 4 Example programs and types of storage 4 1 External EEPROM An external EEPROM using the SPI interface may be used to store state information in the case of an extreme power down mode Essential information that is stored into the EEPROM before shut down and at startup will be recalled and written into the internal RAM in order to continue where it left off The setup connection is as shown in the detailed schematics see Section 11 Size The EEPROM used for this application note is 16 kbit However common sizes on the market can range from 1 kbit to 256 kbit An appropriate size of the external EEPROM should be used to store essential data for resuming normal operation Speed The writing and reading speed to the external EEPROM is important because information needs to be transferred quickly to reduce turn off and start up times The EEPROM in this application note has a maximum operating frequency of 10 MHz Fig 4 shows some operating wav
17. d command ee result ee reads the last record added into EEPROM ii NI ee readn command ee result ee reads the n th record in EEPROM i 12 ee count command ee result ee counts records of ee data type in EEPROM S 13 ye i 14 RRR RRR RRR RRR KK RR KR RK RK RR RK RK RR KR RK KR RR KR KK RK KR RK AA 15 16 include lt LPC213x h gt LPC213x definitions 17 Finclude LPC2K EE H LPC2000 EEPROM definitions 18 include lt stdio h gt 19 20 void display time short int 21 Zi void main void 23 24 volatile unsigned int status records0 loop cnt 25 26 struct ee0 data ee0 temp sel read ee0 pnt 21 const struct ee data ee ini EE REC ID 0 0x0000 0x00000000 0x00000000 0x00000000 28 29 unsigned int command_ee response_ee 2 30 Jl pin configuration section ER PINSELO PINSELO OxOFFFFFF0 0x00000005 P0 01 RxD0 P0 00 TxD0 Se 34 UARTO setup PC communication 35 UOLCR 0x80 enable latch register access 36 UODLL 0xC3 UARTO operates at the Sal UODLM 0x00 19200 60 MHz 60000000 16 19200 0x00C3 38 UOLCR 0x03 no parity 8 data 1 stop 39 UOFCR 0x07 1 char trigger enable and reset Rx amp Tx FIFO 40 41 count records in EEPROMO 42 ee count 0 command ee response ee 43 status response ee 0 44 records0 response ee l 45 46 if the Flash is blank initialize it 47 if records0 0 48 copy initial data into EEPROMO
18. ding support COITIDOTIOTIIS eu ce oe donus cu sio ssa oou cie Esame sE p UsEa a conu us UDE 9 Stress analysis vacila 10 Tips to achieve lowest power down currents 11 Append A E 11 jsp d 17 hine 20 SE aiii 25 Legal information 26 IB UNO NS NEC ER ERROR RR 26 M 26 Trademarks ooccccccocccnccconnnononnnnonononononnnnnnononononenoss 26 CONTENTS sans 27 founded by LPC2138 extreme power down Please be aware that important notices concerning this document and the product s described herein have been included in the section Legal information NXP B V 2006 All rights reserved For more information please visit http www nxp com For sales office addresses email to salesaddresses nxp com Date of release 6 December 2006 Document identifier AN10535 1
19. eforms 1 0005 Trigd D Freq D 10 00MHz 44 Source Select _ SSELO d Freq Clear Meas Measure Freq Thresholds Y Fig 4 Speed of the SPI SCK signal AN10535_1 O NXP B V 2006 All rights reserved 7 of 27 Application note Rev 01 6 December 2006 NXP Semiconductors AN1 0535 4 1 3 4 2 4 2 1 1 4 2 1 2 4 2 2 LPC2138 extreme power down Example C program The example C program in Section 9 shows the basic steps to use the SPI interface for storing essential information to an external EEPROM on demand During the next start up the previous conditions are restored into the internal RAM so the microcontroller can continue processing The simple C program blinks and increments eight LEDs continuously in a loop If the interrupt button is pressed the current LED which corresponds to a bit is stored into the external EEPROM During startup this bit which determined which LED the program was blinking last is restored into the internal RAM and the program will continue where it left off This small program demonstrates the basic procedures for storing and loading conditions that would work for even larger programs with more variables and conditions Internal EEPROM emulation EEPROM emulation can be used to store startup information into the FLASH before the part is put into the powered down mode with the existing flash memory This will all
20. emiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification 13 3 Trademarks Notice All referenced brands product names service names and trademarks are property of their respective owners NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 26 of 27 NXP Semiconductors AN10535 14 Contents 4 1 3 4 2 1 1 4 2 1 2 4 2 2 6 1 6 2 Ge 10 11 12 13 13 1 13 2 13 3 14 INTFOQUCIION ER 3 o A E 3 mere derzeit AA 3 Measured data 4 Off current data sr dee sale 4 SIAM UMC RR censores 4 Current EEN urinaria aaa 5 Transistor voltage drop 5 al 16 De rtorras 5 Example programs and types of storage 7 External EEPDROM 7 EE 7 ST Gf o Pe E RR ERROR 7 Example C program sesnoannnnsenonnnnnnnnnnsnnnnnnennnne 8 Internal EEPROM emulation 8 Example C program ccccccsssseseeeeeeeeeeeeseeeeees 8 Tmeisettmge onnnannnannnannnannnnnnnennnnnnnnnnnnnnnnnnne 8 Esc 8 BOM costs for power down components 8 Board area required 9 Estimated square surface area for components zl m ere 9 Surface area for demo board inclu
21. ethod to have extremely low leakage currents over temperature when using an LPC2138 This method requires a few external components but it provides significant leakage current reduction This app note will discuss two methods that restore the microcontroller s state previous to power down One method uses an inexpensive external EEPROM and the other uses an existing sector of the internal flash that can be reserved for EEPROM emulation Both methods will store the microcontroller s state into the non volatile memory before shutdown and will restore the information back into the internal RAM so the microcontroller may resume processing were it left off before power down 2 Description As stated in the introduction the lowest possible leakage current of the LPC2138 is about 30 uA at room temperature with the brown out disabled By itself there is not much else the user can do to improve this without external components One solution is to disconnect the power source from the LPC2138 using an external switch which the LPC2138 controls The concept would be to have an inexpensive PNP transistor control the power to the LPC2138 and flip flop that the LPC2138 can control to turn the power off 2 1 Block diagram Fig 1 shows a simplified diagram of the circuit concept When power is first applied the flip flop is reset via an RC time constant on the reset pin This insures that the LPC2138 comes up with the power applied The LPC2138 can shut itse
22. gnals that drive into the switch domain make sure there are no current paths into the switched domain that can increase power consumption when the switched domain is turned off For signals that drive out of the switched domain make sure that the signals to the on domain are controlled When the switched domain is turned off these signals will be left floating As an example if an always on domain SPI ram is being driven by the always off domain make sure that the chip select signals are pulled high to the always on domain or this pin will be left floating when the switched domain is turned off causing the SPI ram to draw current Appendix A RRR RRR RRR RK RK RK RK RK RK RK RK RK RK RK RK RK RR RK RK KR RK KR RK RK RR KR KR KR RK RK RK SS shut down c Program for 213x Cycles the blinking of the 8 LEDS and di CS if interrupt is detected stores the current bit into external EEPROM A pa and goes into extreme power down mode During the next startup ii ES the EEPROM data is restored into RAM and continues to where the i CS program left off di I gt x kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkKkkkkKKKKKkk include lt LPC213x H gt LPC213x definitions define SOSPIF 1 lt lt 7 void void void void void Nn Nn AN10535 1 D i i in i u Initialize void Initialize SPI EEPROM write int int Write function read int Read function initread int
23. heck if command is Store into read variable Read Second 8 bits Check if command is Store into read variable Disable chipselect sent sent sent sent sent Reading from EEPROM dd dd dd dd dd dd dd dd dd dd dd dd dd d dd d dd ddddddd P P P B B g RTT HH T ETT TET T T B 1g void read int readloc Initialize IODIRO 0x00000081 init SQSPSR init SOSPDR TOCLRO 0x00000080 SOSPDR 0x03 AN10535_1 Initialize EEPROM Initialize chip select and test pin Initialize status and data register Enable chip select Read command Application note Rev 01 6 December 2006 NXP B V 2006 All rights reserved 15 of 27 NXP Semiconductors AN10535 228 while SOSPSR amp SOSPIF 0 229 230 S0SPCR 0x24 291 232 S0SPDR readloc 233 while S0SPSR amp SOSPIF 0 234 230 SUSPER 0x20 230 237 S SPDR 0x0 238 while SOSPSR amp SOSPIF 0 239 READ SOSPDR c Var READ 24 SOSPDR 0x0 while S0SPSR SOSPIF 0 READ SOSPDR READ READ 16 Var Var OxFF000000 READ READ amp 0x00FF0000 Var Var READ DN BRO BO BP KY MKU PY PY P2 Ho Fe FE FP He He LHe LHe 4 CO DD O1 A W HL Fe 249 250 S0SPDR 0x0 294 while SOSPSR SOSPIF 0 GK READ SOSPDR ds READ READ 8 254 Var Var OxFFFF0000 259 READ READ amp 0x0000FF00 256 Var Var READ 251 258 SO
24. lf off through a port pin This example uses port P0 23 Note that the port pins of the LPC2138 come up in a high impedance state Therefore the set of the flip flop is pulled high by a pull up resistor so there is no conflict at power up with the reset pin Once the LPC2138 shuts itself down an external event can wake the part back up In this case it is a push of a switch The concept is to have the microcontroller turn off its own power and then have an external event reapply power One key requirement is to have the microcontroller store its state in non volatile memory before power is removed and have the microcontroller restore its state after power is reapplied and continue on where it was before it went into deep power down AN10535 1 NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 3 of 27 NXP Semiconductors AN1 0535 LPC2138 extreme power down 3 3 V always on domain 3 3 V switch domain I 47 ko i 47 i kQ T WW 0 1 4 47 kQ i 47 KQ RESET INT N Vdd Vref WAKEUP H 74LVC1G74 SHUTDOWN P0 23 T 1 05 LPC213X always on domain 33V VBAT RTCX1 XTAL1 32 kHz 12 MHz RTCX2 XTAL2 22 p 22p T 22p T 22p Tm T Fig 1 Block diagram For detailed schematics see Section 11 appendix C 3 Measured data A board was produced according to the schematics in Section 11 and was used to take the following measurements 3 1 Off current data
25. n and shall have no liability for the consequences of use of such information 13 2 Disclaimers General Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof AN10535 1 LPC2138 extreme power down Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is for the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP S
26. ow the part to start up in a known state after power is applied Example C program An example C program for the internal Flash storage is shown in Appendix B Section 9 The program is initialized by the reorganization of the Flash to emulate an EEPROM Time settings The program shows that after the initialization of the real time clock information such as seconds minutes and hours can be stored in to the portion of the internal flash and can be recalled and stored into ram when necessary This shows how registers can be stored and recalled using this method Log information A counter is used to increment each time the system is shutdown and restarted which keeps a log of the number of times the cycle occurs 5 BOM costs for power down components Shown in Table 2 are the components needed to create an external circuitry for extreme power down mode The total additional cost is about 13 cents Table 2 Component costs Quantity Component Value Device Package Price 1 D type flip flop 74LVC1G74 SOT765 1 0 05 1 Diode MMSD4148T1 SOD123 0 03 3 Resistor 47 k H US R0805 R0805 0 001 1 Resistor 1k R US_R0805 R0805 0 001 1 Capacitor 0 01 uF C USC0805 C0805 0 01 1 Capacitor 0 1 uF C USC0805 C0805 0 01 1 PNP Transistor BCX71SMD SOT23 0 03 Total cost 0 132 AN10535 1 NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 8 of 27 NXP Semiconductors AN1 0535 LPC2138 extreme powe
27. r down 6 Board area required AN10535 1 6 1 Estimated square surface area for components alone Table 3 shows the estimated square surface area for components only to which a small margin needs to be added to meet the bare minimum area required to comply with DRC rules Table 3 Estimated square surface area for components only Component Surface Area Quantity Package D type flip flop 3 2 X 2 4 mm 1 SOT765 1 Diode 3 85 x 1 8 mm 1 SOD123 Resistor 4 0 x 2 02 mm 3 R0805 Resistor 4 0 x 2 02 mm 1 R0805 Capacitor 4 0 x 2 02 mm 1 C0805 Capacitor 4 0 x 2 02 mm 1 C0805 PNP Transistor 3 61 x 8 mm 1 SOT23 6 2 Surface area for demo board including support components An example using the support components for extreme power down mode is shown in Fig 5 However a current sensing circuit is also included along with a LCD and LEDs The actual circuitry for the extreme power down mode consists of D1 R8 C12 R9 H7 C11 R13 C6 R17 R23 C16 T1 the DFF and the two switches which all take up a relatively small area considering the area of the total number of components on this demo board Application note NXP B V 2006 All rights reserved Rev 01 6 December 2006 9 of 27 NXP Semiconductors AN10535 LPC2138 extreme power down Sacer sa 225 d p ak z D 5 5 d 100mm m t AM TTT ry Ti ka n Li CODICODO Fig 5 Example board surface area including suppo
28. rt components 7 Stress analysis In order to prevent damage to the components the stress with respect to the given ranges are checked to be reasonable as shown in Table 4 Table 4 Stress analysis Id Component Value Device Package Description Range Actual D type flip 74LVC1G74 SOT765 1 1 65 V to flop Vcc supply 5 5 V 3 29 V D input 0 V to 5 5 V 3 28 V D1 Diode MMSD41T1 SOD123 ReverseVolt 100 V 20 mV R8 Resistor 47k R R0805 Voltage US_R0805 drop 20 mV Current 0 425 uA Power 100 mW 8 5 nW R9 Resistor 47k R R0805 Voltage US_R0805 drop 3 28 V Current 69 uA Power 100 mW 0 23 mW C12 Capacitor 0 01 uF C USC0805 C0805 Voltage 0 V to 50V 3 29 V AN10535 1 Application note Rev 01 6 December 2006 NXP B V 2006 All rights reserved 10 of 27 NXP Semiconductors AN1 0535 LPC2138 extreme power down H7 C1 1 Component Value Device Package Description Range Actual rating PNP collector Transistor BCX71SMD SOT23 current 500 mA 68 mA Resistor 1k R R0805 Voltage US_R0805 drop 2 482 V Current 2 48 mA Power 100 mW 6 2 mW Voltage Capacitor 0 1 uF C USC0805 C0805 rating 0 V to 50V 3 29 V 8 Tips to achieve lowest power down currents OO DD OT A Oo Ph Lr do a NO 10 11 12 la 14 15 16 i 18 19 20 21 22 23 When mixing an always on domain with a switched domain it is important to look at all signals that cross the boundaries For si
29. s on domains and the switched domains are isolated properly If they are not then current can flow from the always on domain to the switched domain and increase power consumption The LPC2000 port pins do not have diodes to VDD so the always on domain can drive them with the LPC2138 powered off without drawing any current from the always on domain However the port pins are not 5 V tolerant when VDD is not present NXP B V 2006 All rights reserved Application note Rev 01 6 December 2006 5 of 27 NXP Semiconductors AN1 0535 LPC2138 extreme power down To determine the characteristics of the GPIO port pins during extreme power down a current meter is used in between the GPIO port pin and a short to 3 3 V to determine sinking current Also the current meter checks the source current by shoring to ground as shown in Fig 3 Source sink MICROCONTROLLER MICROCONTROLLER GPIO PIN CURRENT GPIO PIN CURRENT METER METER Fig 3 Testing for sourcing and sinking at GPIO port pins During power down mode the GPIO port pins should not source or sink any current except for the IC pins on the DAC pin Pins p0 2 p0 3 p0 11 are IC pins which will sink roughly 11 uA of current due to the open drain nature of the pins P0 25 noted by is the DAC output and cannot be driven when the part is turned off Table 1 Checking GPIO pins for current in power down mode To VDD LWA To GND UA To VDD HA
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