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1. EIM CHIP SELECTS EBI QSPI V2 ColdFire CPU BDM TAP JTAG EN To From PADI lt gt 4 CH PWM To From PADI Watchdog Timer EMAC DIV SDRAMC t 64 Kbytes SRAM 8Kx16 x4 16 Kbytes CACHE 1Kx32 x4 To From Arbiter backdoor MDHA RNGA SKHA USB 2 0 Full Speed PORTS GPIO L PADI Pin Muxing M amp DDR amp QSPI 12C SDA 12C SCL TXDx lt gt RXDx lt gt RTSx lt gt CTSx lt _ gt DTOUTx lt lt gt DTINx lt gt FECO FEC1 lt gt USB PWMx gt D 31 16 lt gt 23 0 9 RW CS 3 0 lt gt TA JTAG EN lt gt TRST TCLK lt gt TMS gt TDI TDO lt gt TSIZ 1 0 lt gt TEA lt gt BS 3 2 CIM Edge PITO PIT2 PIT1 PIT3 PLL CLKGEN Port Cryptography Modules 3 Features To From PADI To From INTC Figure 1 MCF5275 Block Diagram For a detailed feature list see the MCF5275 Reference Manual MCF5275RM MCF5275 Integrated Microprocessor Family
2. System Clock up to 166 MHz Performance Dhrystone 2 1 MIPS up to 159 Instruction Data Cache 16 Kbytes configurable Static RAM SRAM 64 Kbytes Interrupt Controllers INTC 2 2 2 2 Edge Port Module EPORT e e External Interface Module EIM 4 channel Direct Memory Access DMA e DDR SDRAM Controller Fast Ethernet Controller FEC 1 1 2 2 Watchdog Timer Module WDT 4 channel Programmable Interval Timer Module PIT 32 bit DMA Timers 4 4 4 4 USB QSPI e UART s 3 3 3 3 PC PWM 4 4 4 4 General Purpose I O Module GPIO e CIM Chip Configuration Module Reset Controller Module Debug BDM e JTAG IEEE 1149 1 Test Access Port e Hardware Encryption e Package 196 MAPBGA 256 MAPBGA MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 2 Freescale Semiconductor 2 Block Diagram Block Diagram The superset device in the MCF5275 family comes in a 256 Mold Array Plastic Ball Grid Array MAPBGA package Figure shows a top level block diagram of the MCF5275 the superset device To From SRAM backdoor f y Arbiter INTCO INTC1 A To From PADI FAST ETHERNET CONTROLLER FECO To From PADI lt gt FAST ETHERNET CONTROLLER FEC1 To From PADI JTAG lt 4 CH DMA DREQ 1 0 DACK 3 0 A
3. 9 ns B12 CLKOUT high to data output D 31 16 invalid icupoi 1 0 ns B13 CLKOUT high to data output D 31 16 high impedance tcupoz 9 ns S BS and OE transition after the falling edge of CLKOUT Read write bus timings listed in Table 13 are shown in Figure 8 Figure 9 and Figure 10 so S1 S2 S3 S4 S5 SO S1 S2 S3 S4 S5 A 23 0 TSIZ 1 0 TS BS 3 2 Dt91 16 Figure 8 Read Write Internally Terminated SRAM Bus Timing MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 26 Freescale Semiconductor Electrical Characteristics Figure 9 shows a bus cycle terminated by TA showing timings listed in Table 13 SO S1 S2 S3 S4 S5 SO S1 A 23 0 TSIZ 1 0 TS d v Figure 9 SRAM Read Bus Cycle Terminated by TA MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 27 Electrical Characteristics Figure 10 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 13 So S1 S2 S3 S4 S5 SO S1 2 AMNEM ee MM Bins 6 BS 3 2 D 31 16 eee oe me a erecta eee pa ee ee eee aiaiai TAH f 0000 1 oL L MN PE eel ees etal eee te eee les TEA B2a lt Figure 10 SRAM Read Bus Cycle Terminated by TEA MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 28 Freescale Semiconductor
4. Mechanicals Pinouts 6 3 196 MAPBGA Pinout Figure 5 is a consolidated MCF5274L 75L pinout for the 196 MAPBGA package Table 2 lists the signals by group and shows which signals are muxed and bonded on each of the device packages BREGRUECEUEOCBNOENENE eS ee ee mE fm Pale Tell S seme mr sesele e e e e eet spepmemm vo eels ERE d el fol F r ah ran f DT3IN VSS VSS VSS SD_VDD2 es amp nm VSS VSS VSS OVDD USB RN ZEN SD VDD1 SD VDD1 VSS VSS OVDD USB TN eeen e fel gt S f ES ac A2 E e N ce DTOIN DT1IN m DT3OUT D SRAS SD CKE SD DQS3 EIL PST2 DDATAO dus QSPI CLK RSTOUT VSSPLL USB RXD QSPI_ SD CS0 DDATA3 PST1 CSO QSPI_DIN CLKMOD1 TDI DSI VDDPLL EXTAL QSPI_ QSPI_ USB_ SD_A10 JEE TEST DDATA2 PSTO CLKMODO TMS BKPT SUSP XTAL DDR CLK JR CLK DDR CLK QSPI_ TCLK PST TRST DSC RARE pepe pp qe Figure 5 MCF5274L and MCF5275L Pinout 196 MAPBGA 8 ce ep 9l S S amp m 92 T MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 16 Freescale Semiconductor 6 4 Package Dimensions 196 MAPBGA Figure 6 shows MCF5275 196 MAPBGA package dimensions 9 1 Laser mark for pin 1 2 identification in is area ge m V M 1 Os A E SJ p A 0 15 N 0 08 N M Metalized mark for pin 1 identification in
5. N11 RCON P8 M6 External Memory Interface and Ports A 23 21 PADDR 7 5 CS 6 4 O A11 B11 C11 A8 B8 C8 A 20 0 O A12 B12 C12 B9 D9 C9 A13 B13 C13 C10 B10 A11 A14 B14 C14 C11 B11 A12 B15 C15 B16 D11 C12 B13 C16 D14 D15 C13 D12 E11 E14 16 F14 16 D13 E12 F11 D14 E13 F13 MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor Signal Descriptions Table 2 MCF5274 and MCF5275 Signal Information and Muxing continued MCF5274 MCF5274L Signal Name GPIO Alternate Alternate2 Dir MCF5275 MCF5275L 256 MAPBGA 196 MAPBGA D 31 16 O M1 N1 N2 N3 J3 L1 K2 K3 P1 P2 R1 R2 M1 L2 L3 L4 P3 R3 T3 N4 K4 J4 M2 N1 P4 R4 T4 N5 N2 M3 M4 N3 BS 3 2 PBS 3 2 CAS 3 2 O M3 R5 K1 L5 OE PBUSCTI 7 O K1 H4 TA PBUSCTL 6 L13 K14 TEA PBUSCTL 5 DREQ1 l T8 RW PBUSCTL 4 O P7 L6 TSIZ1 PBUSCTL 3 DACK1 O D16 B14 TSIZO PBUSCTL 2 DACKO Oo G16 E14 TS PBUSCTI 1 DACK2 O L4 H2 TIP PBUSCTL 0 DREQO O P6 Chip Selects CS 7 1 PCSI 7 1 O D10 13 E13 D8 A9 A10 F13 N7 D10 B12 C14 P4 CSO O R6 N5 DDR SDRAM Controller DDR_CLKOUT O
6. QSPI DIN to QSPI_CLK Input setup 9 ns QS5 QSPI DIN to QSPI CLK Input hold 9 ns MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 39 Electrical Characteristics KORI QSPI CLK S X QSPI DOUT QSPI_DIN X Figure 22 QSPI Timing QSPI CS 3 0 8 15 JTAG and Boundary Scan Timing Table 27 JTAG and Boundary Scan Timing Num Characteristics Symbol Min Max Unit J1 TCLK Frequency of Operation fjcvc DC 1 4 fsys 2 J2 TCLK Cycle Period tucyc 4xlcvc ns J3 TCLK Clock Pulse Width tycw 26 ns J4 TCLK Rise and Fall Times tJCRF 0 3 ns J5 Boundary Scan Input Data Setup Time to TCLK Rise tBspsT 4 ns J6 Boundary Scan Input Data Hold Time after TCLK Rise tBspHT 26 E ns J7 TCLK Low to Boundary Scan Output Data Valid tBspv 0 33 ns J8 TCLK Low to Boundary Scan Output High Z tBspz 0 33 ns J9 TMS TDI Input Data Setup Time to TCLK Rise trAPBST 4 ns J10 TMS TDI Input Data Hold Time after TCLK Rise tTAPBHT 10 Az ns J11 TCLK Low to TDO Data Valid ttpopv 0 26 ns J12 TCLK Low to TDO High Z trpopz 0 8 ns J13 TRST Assert Time tTRSTAT 100 ns J14 TRST Setup Time Negation to TCLK High trrastst 10 ns JTAG EN is expected to be a static signal Hence it is not associated with any timing MCF5275 Integrated Microprocessor Fam
7. 8 8 DDR SDRAM AC Timing Characteristics Electrical Characteristics The DDR SDRAM controller uses SSTL2 and I O drivers Class I or Class II drive strength is available and is user programmable DDR Clock timing specifications are given in Table 14 and Figure 11 Table 14 DDR Clock Timing Specifications Symbol Characteristic Min Max Unit Vup Clock output mid point voltage 1 05 1 45 Vout Clock output voltage level 0 3 SDVpp 0 3 V Vip Clock output differential voltage peak to peak swing 0 7 SDVpp 0 6 V Vix Clock crossing point voltage 1 05 1 45 V SD Vpp is nominally 2 5V SDCLK E RE Vix I Jj d Vyp Vip E i a du SDCLK Figure 11 DDR Clock Timing Diagram When using the DDR SDRAM controller the timing numbers in Table 15 must be followed to properly latch or drive data onto the memory bus All timing numbers are relative to the two DQS byte lanes Table 15 DDR Timing NUM Characteristic Symbol Min Max Unit Frequency of operation TBD 83 MHz DD1 Clock Period DDR CLKOUT tck 12 TBD ns DD2 Pulse Width High toKH 0 45 0 55 tek DD3 Pulse Width Low tok 0 45 0 55 tck DD4 DDR CLKOUT high to DDR address SD_CKE tomv 0 5xtek 1 ns SD CS 1 0 SD SCAS SD SRAS SD WE valid DD5 DDR CLKOUT high to DDR address SD CKE SD CS tomH 2 ns SD SCAS SD SRAS SD WE invalid DD6
8. DT1OUT PTIMERL 2 PWM1 O H2 F2 DTOIN PTIMERL 1 DTOOUT H3 E1 DTOOUT PTIMERL O PWMO O G3 E2 BDM JTAG DSCLK TRST P14 P13 PSTCLK TCLK O P16 P12 BKPT TMS R15 N12 DSI TDI l R16 M12 DSO TDO O P15 K11 JTAG_EN l R14 P11 DDATA 3 0 O P10 N10 P11 M7 N7 P8 L9 N11 PST 3 0 O T10 R10 T11 P7 L8 M8 N8 R11 Test TEST N9 N6 PLL TEST l M14 Power Supplies VDDPLL M15 M13 MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor Design Recommendations Table 2 MCF5274 and MCF5275 Signal Information and Muxing continued 5 5 1 5 2 MCF5274 MCF5274L Signal Name GPIO Alternate1 Alternate2 Dir MCF5275 MCF5275L 256 MAPBGA 196 MAPBGA VSSPLL K16 L13 VSS A1 A10 A16 F7 F8 G6 9 E5 E12 F6 H6 9 J7 J8 F11 G7 10 H7 10 J1 J7 10 K7 10 L6 L11 M5 N16 R7 T1 T16 OVDD E6 8 F5 F7 F8 E5 7 F5 F6 G5 G6 H5 H6 H10 J9 J10 J11 J12 K11 K8 10 K12 L9 L10 L12 M9 11 VDD D8 H13 K4 N8 D6 G5 G12 L7 SD_VDD ER E9 11 F9 F10 E8 10 F9 F10 F12 G11 G12 G10 H5 J5 J6 H11 H12 J5 K5 7 J6 K5 K6 L5 L7 L8 M6 V7 M8 Refers to pin s primary function All pins which
9. Figure 19 MII Serial Management Channel Timing Diagram FECn MDIO output MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 36 Freescale Semiconductor Electrical Characteristics 8 11 5 USB Interface AC Timing Specifications Table 22 lists USB Interface timings Table 22 USB Interface Timing Num Characteristic Min Max Units US1 USB CLK frequency of operation 48 48 MHz US2 USB CLK fall time Vi 2 4 V to Vi_ 0 5 V m 2 ns US3 USB CLK rise time Vij 0 5 V to Vy 2 4 V 2 ns USA USB CLK duty cycle at 0 5 x O Vpp 45 55 96 Data Inputs US5 USB RP USB HN USB RXD valid to USB CLK high 6 ns US6 USB CLK high to USB RP USB HN USB RXD invalid 6 ns Data Outputs US7 USB CLK high to USB TP USB TN USB SUSP valid 12 ns US8 USB CLK high to USB TP USB TN USB SUSP invalid 3 ns Figure 20 shows USB interface timings listed in Table 22 lt si gt ma NN EN CN ee T USB Outputs XXX XXX USB Inputs Input Rise Time Input Fall Time Figure 20 USB Signals Timing Diagram MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 37 Electrical Characteristics 8 12 C Input Output Timing Specifications Table 23 lists specifications for the PC input timing parameters shown in Figure 21 Table 23 I2C Input Timing Specif
10. Hardware Specification Rev 4 Freescale Semiconductor Signal Descriptions 4 Signal Descriptions This section describes signals that connect off chip including a table of signal properties For a more detailed discussion of the MCF5275 signals consult the MCF5275 Reference Manual MCF5275RM Table 2 lists the signals for the MCF5275 in functional group order The Dir column is the direction for the primary function of the pin Refer to Section 6 Mechanicals Pinouts for package diagrams NOTE In this table and throughout this document a single signal within a group is designated without square brackets i e A24 while designations for multiple signals within a group use brackets 1 e A 23 21 and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon NOTE The primary functionality of a pin is not necessarily its default functionality Pins that are muxed with GPIO will default to their GPIO functionality Table 2 MCF5274 and MCF5275 Signal Information and Muxing MCF5274 MCF5274L Signal Name GPIO Alternate1 Alternate2 Dir MCF5275 MCF5275L 256 MAPBGA 196 MAPBGA Reset RESET N15 K12 RSTOUT O N14 L12 Clock EXTAL L16 M14 XTAL O M16 N14 CLKOUT O T12 P9 Mode Selection CLKMOD 1 0 N13 P13 M11
11. Table 10 Corrected maximum Input High Voltage 3 3V I O Pads Vi specification 4 Table 10 added PLL supply voltage row MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 43 How to Reach Us Home Page www freescale com E mail support Q freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Document Number MCF5275EC R
12. are configurable for GPIO have a pullup enabled in GPIO mode with the exception of PBUSCTL 7 PBUSCTL 4 0 PADDR PBS PSDRAM f JTAG_EN is asserted these pins default to Alternate 1 JTAG functionality The GPIO module is not responsible for assigning these pins Design Recommendations Layout Use a 4 layer printed circuit board with the VDD and GND pins connected directly to the power and ground planes for the MCF5275 See application note AN1259 System Design and Layout Techniques for Noise Reduction in MCU Based Systems Match the PC layout trace width and routing to match trace length to operating frequency and board impedance Add termination series or therein to the traces to dampen reflections Increase the PCB impedance if possible keeping the trace lengths balanced and short Then do cross talk analysis to separate traces with significant parallelism or are otherwise noisy Use 6 mils trace and separation Clocks get extra separation and more precise balancing Power Supply 33uF 0 1 uF and 0 01 uF across each power supply MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 9 Design Recommendations 5 2 1 Supply Voltage Sequencing and Separation Cautions Figure 2 shows situations in sequencing the I O Vpp OVpp SDRAM Vpp SDVpp PLL Vpp PLLV pp and Core VDD Vpp A o 93V gt OVpp SDVpp PLLVpp o Supplies Stable a S 25V SDVpp 2
13. may flow out of Vpp and could result in external power supply going out of regulation Ensure the external Vpp load shunts current greater than maximum injection current This is the greatest risk when the MCU is not consuming power Examples are if no system clock is present or if clock rate is very low which would reduce overall power consumption Also at power up system clock is not present during the power up sequence until the PLL has attained lock MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 22 Freescale Semiconductor 8 5 Electrical Characteristics Oscillator and Phase Lock Loop PLLMRFM Electrical Specifications Table 11 PLL Electrical Specifications Characteristic Symbol Min Max Unit PLL Reference Frequency Range MHz Crystal reference fret crystal 8 25 External reference fret ext 8 25 1 1 Mode NOTE fsys 2 2 x tret 1 1 fret 14 24 83 Core frequency fcore 166 MHz CLKOUT Frequency External reference 0 83 MHz On Chip PLL Frequency fsys 2 fref 32 83 MHz Loss of Reference Frequency 3 flor 100 1000 kHz Self Clocked Mode Frequency 5 fsom TBD TBD MHz Crystal Start up Time gt 6 tsi 10 ms EXTAL Input High Voltage VIHEXT V Crystal Mode VIHEXT TBD TBD All other modes Dual Controller 1 1 Bypass External TBD TBD EXTAL Input Low Voltage VILEXT V Crystal Mode VILEXT TBD TBD All other modes Dual Controlle
14. 0 3 0 35 x OVpp V Output High Voltage 3 3V I O Pads Vou OVpp 0 5 V lou 2 0 mA Output Low Voltage 3 3V I O Pads VoL 0 5 V lo 2 0mA Input Hysteresis 3 3V I O Pads Vuys 0 06 x Vpp mV Input High Voltage SSTL 3 3V 2 5V Vin Vngr 0 3 SDVpp 0 3 V Input Low Voltage SSTL 3 3V 2 5V Vit Vss 0 3 Vner 0 3 Output High Voltage SSTL 3 3V 2 5V4 Vou SDVpp 0 25V V lou 5 0 mA Output Low Voltage SSTL 3 3V 2 5V VoL 0 35 V lo 5 0 mA Input Leakage Current lin 1 0 1 0 uA Vin Vpp or Vss Input only pins High Impedance Off State Leakage Current loz 1 0 1 0 uA Vin Vpp OF Vss All input output and output pins Weak Internal Pull Up Device Current tested at Vy Max lAPU 10 130 pA Input Capacitance 9 Cin pF All input only pins mE 7 All input output three state pins 7 MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 21 Electrical Characteristics Table 10 DC Electrical Specifications continued Characteristic Symbol Min Max Unit Load Capacitance pF Low Drive Strength C 25 High Drive Strength 50 Core Operating Supply Current lop Master Mode m 175 mA WAIT 15 mA DOZE 10 mA STOP 100 pA I O Pad Operating Supply Current Olpp Master Mode 250 mA Low Power Modes 250 uA DC Injection Current 3 9 10 11 lic mA VNuEacLAMP 7 Vss 0 3 V VboscrAMP Vpp 0 3 Single Pin Limi
15. 10 QSPI CSO PQSPI 3 O P12 M9 QSPI_CLK PQSPI 2 I2C_SCL Z O T15 L11 QSPI_DIN PQSPI 1 I2C_SDA l T13 M10 QSPI_DOUT PQSPI 0 m m O R12 L10 UARTs U2RXD PUARTH 3 l T9 U2TXD PUARTH 2 O R9 U2CTS PUARTH 1 PWM1 l P9 U2RTS PUARTH 0 PWMO O R8 U1RXD PUARTL 7 l A9 A6 U1TXD PUARTL 6 O B9 D7 U1CTS PUARTL 5 l c9 C7 U1RTS PUARTL 4 O D9 B6 UORXD PUARTL 3 l A8 A4 UOTXD PUARTL 2 O B8 A5 UOCTS PUARTL 1 l C8 C6 UORTS PUARTL O O D7 B5 USB USB_SPEED PUSBH 0 y o G14 G11 USB CLK PUSBL 7 l G15 F12 MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor Signal Descriptions Table 2 MCF5274 and MCF5275 Signal Information and Muxing continued MCF5274 MCF5274L Signal Name GPIO Alternate1 Alternate2 Dir MCF5275 MCF5275L 256 MAPBGA 196 MAPBGA USB_RN PUSBL 6 J16 H13 USB_RP PUSBL 5 J15 J11 USB RXD PUSBL 4 l L15 L14 USB_SUSP PUSBL 3 O M13 N13 USB_TN PUSBL 2 O K14 J14 USB_TP PUSBL 1 O K15 J12 USB_TXEN PUSBL O O L14 K13 Timers and PWMs DT3IN PTIMERH 3 DTSOUT U2RTS J4 G2 DT3OUT PTIMERH 2 PWM3 U2CTS O K3 G1 DT2IN PTIMERH 1 DT2OUT J2 F3 DT2OUT PTIMERH O PWM2 O J3 F4 DT1IN PTIMERL 3 DT1OUT l H1 F1
16. 5V gt Q 3 O asv Of WIL C INI VDD o z o amp O 0 Notes Time 1 VDD should not exceed OVDD SDVDD or PLLVDD by more than 0 4 V at any time including power up 2 Recommended that VDD should track OVDD SDVDD PLLVDD up to 0 9 V then separate for completion of ramps 3 Input voltage must not be greater than the supply voltage OVDD SDVDD VDD or PLLVDD by more than 0 5 V at any time including during power up 4 Use 1 ms or slower rise time for all supplies Figure 2 Supply Voltage Sequencing and Separation Cautions The relationship between SDVpp and OVpp is non critical during power up and power down sequences SDVpp 2 5V or 3 3V and OVpp are specified relative to V pp 5 2 1 1 Power Up Sequence If OVpp SDVpp are powered up with Vpp at 0 V then the sense circuits in the I O pads cause all pad output drivers connected to the OVpp SDVpp to be in a high impedance state There is no limit on how long after OVpp SDV pp powers up before Vpp must powered up Vpp should not lead the OVpp SDV pp or PLLVpp by more than 0 4 V during power ramp up or high current will be in the internal ESD protection diodes The rise times on the power supplies should be slower than 1 us to avoid turning on the internal ESD protection clamp diodes The recommended power up sequence is as follows 1 Use 1 us or slower rise time for all supplies 2 Vpp PLLV pp and OVpp SDVpp should track up to 0 9 V then sep
17. 8 signals These are shown in Table 4 Table 4 MII Mode Signal Description MCF5275 Pin Transmit clock FECn_TXCLK Transmit enable FECn_TXEN Transmit data FECn_TXD 3 0 Transmit error FECn_TXER MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor Table 4 MII Mode continued Signal Description MCF5275 Pin Collision FECn COL Carrier sense FECn CRS Receive clock FECn RXCLK Receive enable FECn RXDV Receive data FECn RXD 3 0 Receive error FECn RXER Management channel clock FECn MDC Management channel serial data FECn MDIO Design Recommendations The serial mode interface operates in what is generally referred to as AMD mode The MCF5275 configuration for seven wire serial mode connections to the external transceiver are shown in Table 5 Table 5 Seven Wire Mode Configuration Signal Description MCF5275 Pin Transmit clock FECn TXCLK Transmit enable FECn TXEN Transmit data FECn TXD O0 Collision FECn COL Receive clock FECn RXCLK Receive enable FECn RXDV Receive data FECn RXD 0 Unused configure as PB14 FECn RXER Unused input tie to ground FECn CRS Unused configure as PB 13 11 FECn RXD 3 1 Unused output ignore FECn TXER Unused configure as PB 10 8 FECn TXD 3 1 Unused configure as PB15 FECn MDC Input after reset connect to ground FECn MDIO Refer to th
18. ECn RXER to FECn RXCLK 5 ns setup M2 FECn_RXCLK to FECn RXD 3 0 FECn_RXDV FECn RXER 5 ns hold M3 FECn RXCLK pulse width high 3596 65 FECn_RXCLK period M4 FECn_RXCLK pulse width low 35 65 FECn_RXCLK period Figure 16 shows MII receive signal timings listed in Table 18 FECn_RXCLK input FECn RXD 3 0 inputs FECn RXDV FECCRXER 2S AA NX AK comics Figure 16 MII Receive Signal Timing Diagram 8 11 2 MII Transmit Signal Timing FECn_TXD 3 0 FECn TXEN FECn_TXER FECn TXCLK Table 19 lists MII transmit channel timings The transmitter functions correctly up to a FECn_TXCLK maximum frequency of 25 MHz 1 The processor clock frequency must exceed twice the FECn_TXCLK frequency MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 34 Freescale Semiconductor Electrical Characteristics Table 19 MII Transmit Channel Timing Num Characteristic Min Max Unit M5 FECn TXCLK to FECn_TXD 3 0 FECn TXEN FECn TXER 5 ns invalid M6 FECn TXCLK to FECn_TXD 3 0 FECn TXEN FECn TXER 25 ns valid M7 FECn TXCLK pulse width high 35 65 FECn_TXCLK period M8 FECn TXCLK pulse width low 3596 65 FECn_TXCLK period Figure 17 shows MII transmit signal timings listed in Table 19 PEO FECn_TXCLK input FECn_TXD 3 0 outputs FECn_TXEN p E s 4 FECn_TXER lt gt Figure 17 MII Transmit Signal
19. Electrical Characteristics This appendix contains electrical specification tables and reference timing diagrams for the MCF5275 microcontroller unit This section contains detailed information on power considerations DC AC electrical characteristics and AC timing specifications of MCF5275 NOTE The parameters specified in this appendix supersede any values found in the module specifications 8 1 Maximum Ratings Table 7 Absolute Maximum Ratings 2 Rating Symbol Value Unit Core Supply Voltage Vpp 0 5 to 42 0 V I O Pad Supply Voltage 3 3V OVpp 0 3 to 44 0 V Memory Interface SSTL 2 5V Pad Supply Voltage SDVpp 0 3 to 2 8 V Memory Interface SSTL 3 3V Pad Supply Voltage SDVpp 0 3 to 44 0 V PLL Supply Voltage VppPLL 0 8 to 44 0 V Digital Input Voltage ViN 0 3 to 4 0 V EXTAL pin voltage VEXTAL 0 to 3 3 V XTAL pin voltage VxTAL 0 to 3 3 V Instantaneous Maximum Current Single pin limit applies to all pins 5 Ip x mA Operating Temperature Range Packaged Ta 40 to 85 C TL Tg Storage Temperature Range Tstg 65 to 150 C Functional operating conditions are given in DC Electrical Specifications Absolute Maximum Ratings are stress ratings only and functional operation at the maxima is not guaranteed Stress beyond those listed may affect device reliability or cause permanent damage to the device MCF5275 Integrated Microprocessor Family H
20. Freescale Semiconductor Data Sheet Technical Data Document Number MCF5275EC Rev 4 02 2009 V RoHS MCF5275 Integrated Microprocessor Family Hardware Specification by Microcontroller Solutions Group The MCF5275 family is a highly integrated implementation of the ColdFire family of reduced instruction set computing RISC microprocessors This document describes pertinent features and functions characteristics of the MCF5275 family The MCF5275 family includes the MCF5275 MCF5275L MCF5274 and MCF5274L microprocessors The differences between these parts are summarized in Table 1 This document is written from the perspective of the MCF5275 and unless otherwise noted the information applies also to the MCF5275L MCF5274 and MCFS5274L The MCF5275 family delivers a new level of performance and integration on the popular version 2 ColdFire core with up to 159 Dhrystone 2 1 MIPS 166MHz These highly integrated microprocessors build upon the widely used peripheral mix on the popular MCF5272 ColdFire microprocessor 10 100 Mbps Ethernet MAC and USB device by adding a second 10 100 Mbps Ethernet MAC MCF5274 and MCF5275 and hardware encryption MCF5275L and MCF5275 Freescale Semiconductor Inc 2009 All rights reserved SF OONOOAHRWN o Contents MCF5275 Family Configurations 2 Black DIBO SIL seas pur E pb PE REP ORE NECS 3 FeglUt GB aae gp bor oie nese Log Ros ooi d i OR vao P ouk a 3
21. OL 3 1 D5 C5 D6 D4 B1 B2 FECO_RXER PFECOL O0 C4 E4 FEC1 FEC1_MDIO PFECI2C S3 mE mx 1 0 G1 E FEC1 MDC PFECI2C 2 O G2 E FEC1 TXCLK PFEC1H 7 mE C1 FEC1 TXEN PFEC1H 6 mE O D2 FEC1_TXD 0 PFEC1H 5 mE O F1 FEC1 COL PFEC1H 4 ES A5 FEC1_RXCLK PFEC1H 3 m B4 FEC1_RXDV PFEC1H 2 mE A3 FEC1_RXD 0 PFEC1H 1 B3 FEC1_CRS PFEC1H 0 l A4 FEC1_TXD 3 1 PFEC1L 7 5 as O E1 E2 F2 FEC1_TXER PFEC1L 4 mE O D1 FEC1_RXD 3 1 PFEC1L 3 1 l B1 B2 A2 FEC1_RXER PFEC1L 0 E C2 MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor Signal Descriptions Table 2 MCF5274 and MCF5275 Signal Information and Muxing continued MCF5274 MCF5274L Signal Name GPIO Alternate1 Alternate2 Dir MCF5275 MCF5275L 256 MAPBGA 196 MAPBGA PC I2C_SDA PFECI2C 1 U2RXD 1 0 B10 B7 l2C SCL PFECI2C 0 U2TXD y o C10 A7 DMA DACK 3 0 and DREQ 3 0 do not have a dedicated bond pads Please refer to the following pins for muxing PCSS3 PWMS for DACK3 PCS2 PWM2 for DACK2 TSIZ1 for DACK1 TSIZO for DACKO IRQ3 for DREQS IRQ2 and TA for DREQ2 TEA for DREQ1 and TIP for DREQO QSPI QSPI_CS 3 2 PQSPI 6 5 PWM 3 2 DACK 3 2 O R13 N12 P10 N9 QSPI_CS1 PQSPI 4 O T14 N
22. OUT Valid tcHROV 10 ns R5 RSTOUT valid to Config Overrides valid trovcv 0 ns R6 Configuration Override Setup Time to RSTOUT invalid ticos 20 tcyc R7 Configuration Override Hold Time after RSTOUT invalid tcoH 0 ns R8 RSTOUT invalid to Configuration Override High Impedance tRoicz 1xtcvc ns All AC timing is shown with respect to 50 OVpp levels unless otherwise noted During low power STOP the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system Thus RESET must be held a minimum of 100 ns cour Lez RE Te eel RESET RSTOUT Configuration Overrides y RCON Override pins 1 Refer to the Coldfire Integration Module CIM section for more information MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 33 Electrical Characteristics 8 11 Fast Ethernet AC Timing Specifications MII signals use TTL signal levels compatible with devices operating at 5 0 V or 3 3 V 8 11 1 MII Receive Signal Timing FECn RXD 3 0 FECn RXDV FECn RXER and FECn RXCLK The receiver functions correctly up to a FECn_RXCLK maximum frequency of 25 MHz 1 The processor clock frequency must exceed twice the FECn_RXCLK frequency Table 18 lists MII receive channel timings Table 18 MII Receive Signal Timing Num Characteristic Min Max Unit M1 FECn RXD 3 0 FECn RXDV F
23. PT input data hold time to PSTCLK Rise 1 5 ns D8 PSTCLK high to BKPT high Z 0 0 10 0 ns DSCLK and DSI are synchronized internally D4 is measured from the synchronized DSCLK input relative to the rising edge of PSTCLK Figure 27 shows real time trace timing for the values in Table 28 pasek NX gt lt 2 Figure 27 Real Time Trace AC Timing PST 3 0 DDATA 3 0 Figure 28 shows BDM serial port AC timing for the values in Table 28 emu f f T L S VS VS XL p DSCLK 24 M ae DSI P Current X Next DSO X Past I Current Figure 28 BDM Serial Port AC Timing MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 42 Freescale Semiconductor Documentation 9 Documentation Documentation regarding the MCF5275 and their development support tools is available from a local Freescale distributor a Freescale semiconductor sales office the Freescale Literature Distribution Center or through the Freescale web address at http www freescale com coldfire 10 Revision History Table 29 provides a revision history for this hardware specification Table 29 Document Revision History Rev No Substantive Change s 0 Initial release 1 Added Figure 6 1 1 Removed duplicate information in the module description sections The information is all in the Signals Description Table 1 2 Remo
24. Q C 100 pF MM Circuit Description Reeries 0 Q C 200 pF Number of pulses per pin HBM positive pulses 1 negative pulses 1 Number of pulses per pin MM positive pulses 3 negative pulses 3 Interval of Pulses mz 1 sec All ESD testing is in conformity with CDF AEC Q100 Stress Test Qualification for Automotive Grade Integrated Circuits A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature unless specified otherwise in the device specification MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 20 Freescale Semiconductor Electrical Characteristics 8 4 DC Electrical Specifications Table 10 DC Electrical Specifications Characteristic Symbol Min Max Unit Core Supply Voltage Vpp 1 4 1 6 V I O Pad Supply Voltage OVpp 3 0 3 6 PLL Supply Voltage VppPLL 3 0 3 6 V SSTL I O Pad Supply Voltage SDVpp 2 3 2 7 V SSTL I O Pad Supply Voltage SDVpp 3 0 3 6 V SSTL Memory pads reference voltage SD Vpp 2 5V VREF 0 5 SD Vpp V SSTL Memory pads reference voltage SD Vpp 3 3V VREF 0 45 SD Vpp V Input High Voltage 3 3V I O Pads Vin 0 7 x OVpp OVpp 0 3 V Input Low Voltage 3 3V I O Pads Vi Vss
25. Signal Descripliols uuizosesihirksenirnirexreikbes 4 Design Recommendations seuseue 9 Mechanicals Piribuls 2 2 soi n mh 14 Ordering InIoniattort user ei ew PPP ERRE EY 18 Electrical Character Gnesi in ici s sitne Rd diras 18 Bosufientalle 33 eb Cb e ODE ep RaORE 43 REVISION HISIODy cvs rh pera eie Res 43 Vey oe Z freescale semiconductor MCF5275 Family Configurations In addition the MCF5275 family features an enhanced multiply accumulate unit EMAC large on chip memory 64 Kbytes SRAM 16 Kbytes configurable cache and a 16 bit DDR SDRAM memory controller These devices are ideal for cost sensitive applications requiring significant control processing for file management connectivity data buffering and user interface as well as signal processing in a variety of key markets such as security imaging networking gaming and medical This leading package of integration and high performance allows fast time to market through easy code reuse and extensive third party tool support To locate any published errata or updates for this document refer to the ColdFire products website at http www freescale com coldfire 1 MCF5275 Family Configurations Table 1 MCF5275 Family Configurations Module MCF5274L MCF5275L MCF5274 MCF5275 ColdFire Version 2 Core with EMAC Enhanced Multiply Accumulate Unit
26. T7 P6 DDR_CLKOUT O T6 P5 SD_CS 1 0 PSDRAM 7 6 CS 3 2 O M2 T5 H3 M5 SD SRAS PSDRAM 5 O L2 H1 SD SCAS PSDRAM 4 O L1 G3 SD_WE PSDRAM 3 O K2 G4 SD_A10 O N6 N4 SD_DQS 8 2 PSDRAM 2 1 O M4 P5 J2 P3 SD CKE PSDRAM 0 O L3 J1 SD_VREF A15 T2 A13 P2 External Interrupts Port IRQ 7 5 PIRQ 7 5 G13 H16 H15 F14 G13 G14 IRQ 4 PIRQ 4 DREQ2 H14 H11 IRQ 3 2 PIRQ 3 2 DREQ 3 2 J14 J13 H14 H12 MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor Signal Descriptions Table 2 MCF5274 and MCF5275 Signal Information and Muxing continued MCF5274 MCF5274L Signal Name GPIO Alternate1 Alternate2 Dir MCF5275 MCF5275L 256 MAPBGA 196 MAPBGA IRQ1 PIRQ 1 K13 J13 FECO FECO MDIO PFECI2C 5 Il2C SDA U2RXD y o A7 A3 FECO MDC PFECI2C 4 I2C_SCL U2TXD O B7 C5 FECO TXCLK PFECOH 7 mE C3 C1 FECO_TXEN PFECOH 6 E O D4 C3 FECO TXD O PFECOH 5 mE O G4 D2 FECO COL PFECOH 4 l A6 B4 FECO_RXCLK PFECOH 3 B6 B3 FECO_RXDV PFECOH 2 mE B5 C4 FECO RXD O0 PFECOH 1 mE m C6 D5 FECO CRS PFECOH 0 mE C7 A2 FECO TXD 3 1 PFECOL 7 5 mE O E3 F3 F4 D1 E3 D3 FECO_TXER PFECOL 4 P O D3 C2 FECO RXD 3 1 PFEC
27. TRST TDO TCLK QSP QSPI_ To TMS SD DDR CLK DDR CLK QSPI_ asPl QsPl_ Figure 3 MCF5274 and MCF5275 Pinout 256 MAPBGA MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 14 Freescale Semiconductor Mechanicals Pinouts 6 2 Package Dimensions 256 MAPBGA Figure 6 shows MCF5275 256 MAPBGA package dimensions X D Y LASER MARK FOR PIN A1 M rig aga TUN os A k 1 A2 Z 030 Z I l A i l N A1 EE 7 256X Z4 4 N OQ 0 15 Z DETAIL K ROTATED 90 CLOCKWISE NOTES DIMENSIONS ARE IN MILLIMETERS INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14 5M 1994 DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO DATUM PLANE Z DATUM Z SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE 25ex Ob e 0 25 Z XY MILLIMETERS DIM MIN MAX 0 10 9 Z 125 1 60 0 27 0 47 1 16 REF 0 40 0 60 17 00 BSC 17 00 BSC 1 00 BSC 0 50 BSC M METALIZED MARK FOR PIN A1 IDENTIFICATION IN THIS AREA gt pese dEuWZZcgmR mOw6mucowW VIEW M M ulo m o o 52 Figure 4 256 MAPBGA Package Dimensions MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 15
28. Timing Diagram 8 11 3 MII Async Inputs Signal Timing FECn_CRS and FECn COL Table 20 lists MII asynchronous inputs signal timing Table 20 MII Asynchronous Input Signal Timing Num Characteristic Min Max Unit M9 FECn CRS FECn COL minimum pulse width 1 5 FECn_TXCLK period Figure 18 shows MII asynchronous input timings listed in Table 20 Figure 18 MII Async Inputs Timing Diagram FECn CRS FECn COL MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 35 Electrical Characteristics 8 11 4 MII Serial Management Channel Timing FECn MDIO and FECn MDC Table 21 lists MII serial management channel timings The FEC functions correctly with a maximum MDC frequency of 2 5 MHz Table 21 MII Serial Management Channel Timing Num Characteristic Min Max Unit M10 FECn MDC falling edge to FECn MDIO output invalid minimum 0 E ns propagation delay M11 FECn_MDC falling edge to FECn MDIO output valid max prop delay 25 ns M12 FECn_MDIO input to FECn_MDC rising edge setup 10 ns M13 FECn MDIO input to FECn MDC rising edge hold 0 m ns M14 FECn MDC pulse width high 40 60 MDC period M15 FECn_MDC pulse width low 40 60 MDC period Figure 19 shows MII serial management channel timings listed in Table 21 FECn_MDC output uns mu 2 FECn MDIO input A x AK xx oa
29. Write command to first SD DQS Latching Transition tpass 1 25 ick DD7 SD_DQS high to Data and DM valid write setup tas 1 5 ns DD8 SD DOS high to Data and DM invalid write hold tou 1 ns DD9 SD_DQS high to Data valid read setup tis 1 ns DD10 SD DQS high to Data invalid read hold tin 0 25 x tox 1 ns DD11 SD DGS falling edge to CLKOUT high setup ipss 0 5 ns DD12 SD DGS falling edge to CLKOUT high hold tosH 0 5 ns MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 29 Electrical Characteristics Table 15 DDR Timing continued NUM Characteristic Symbol Min Max Unit DD13 DQS input read preamble width tapng tRPRE 0 9 1 1 tek DD14 DQS input read postamble width taps tapst 0 4 0 6 tek DD15 DQS output write preamble width twpre tWPRE 0 25 ick DD16 DQS output write postamble width typsr twest 0 4 0 6 tek o AOON All timing specifications are based on taking into account a 25pF load on the SDRAM output pins DDR_CLKOUT operates at half the frequency of the PLLMRFM output and the ColdFire core tek tex must be less than or equal to tox D 31 24 is relative to SD_DQS3 and D 23 16 is relative to SD_DQS2 The first data beat is valid before the first rising edge of SD_DQS and after the SD_DQS write preamble The remaining data beats are valid for each subsequent SD_DQS edge Data input skew is de
30. arate for the completion of ramps with OVpp SD Vpp going to the higher external voltages One way to accomplish this is to use a low drop out voltage regulator MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 10 Freescale Semiconductor Design Recommendations 5 2 1 2 Power Down Sequence If Vpp is powered down first then sense circuits in the I O pads cause all output drivers to be in a high impedance state There is no limit on how long after Vpp powers down before OVpp SDVpp or PLLVpp must power down Vpp should not lag OVpp SDVpp or PLLVpp going low by more than 0 4 V during power down or undesired high current will be in the ESD protection diodes There are no requirements for the fall times of the power supplies The recommended power down sequence is as follows 1 Drop Vpp to 0 V 2 Drop OVpp SDV pp PLLV py supplies 5 3 Decoupling e Place the decoupling capacitors as close to the pins as possible but they can be outside the footprint of the package e 0 1 uF and 0 01 uF at each supply input 5 4 Buffering e Use bus buffers on all data address lines for all off board accesses and for all on board accesses when excessive loading is expected See electricals 5 5 Pull up Recommendations Use external pull up resistors on unused inputs See pin table 5 6 Clocking Recommendations e Use a multi layer board with a separate ground plane Place the crystal and all other associated compone
31. ardware Specification Rev 4 18 Freescale Semiconductor Electrical Characteristics This device contains circuitry protecting against damage due to high static voltage or electrical fields however it is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level e g Vss or O Vpp Input must be current limited to the value specified To determine the value of the required current limiting resistor calculate resistance values for positive and negative clamp voltages then use the larger of the two values All functional non supply pins are internally clamped to Vss and O Vpp Power supply must maintain regulation within operating O Vpp range during instantaneous and operating maximum current conditions If positive injection current Vi gt O Vpp is greater than Ipp the injection current may flow out of O Vpp and could result in external power supply going out of regulation Ensure the external O Vpp load shunts current greater than maximum injection current This is the greatest risk when the MCU is not consuming power ex no clock Power supply must maintain regulation within operating Vpp range during instantaneous and operating maximum current conditions 8 2 Thermal Characteristics Table 8 lists thermal resistance values Table 8 Thermal chara
32. cteristics Characteristic Symbol 256MBGA 196MBGA Unit Junction to ambient natural convection Four layer board 2s2p OMA 2612 3212 C W Junction to ambient 200 ft min Four layer board 2s2p OJMA 2312 2912 C W Junction to board 0 B 153 208 C W Junction to case Me 104 104 C W Junction to top of package Natural convection Yi 215 215 C W Maximum operating junction temperature Tj 105 105 C 1 0 uA and Yj parameters are simulated in conformance with EIA JESD Standard 51 2 for natural convection Freescale recommends the use of 0 4 and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices Conformance to the device junction temperature specification can be verified by physical measurement in the customer s system using the parameter the device power dissipation and the method described in EIA JESD Standard 51 2 Per JEDEC JESD51 6 with the board horizontal Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51 8 Board temperature is measured on the top surface of the board near the package Thermal resistance between the die and the case top surface as measured by the cold plate method MIL SPEC 883 Method 1012 1 Thermal charac
33. d by the SDRAM SD SCAS should be connected to the corresponding signal labeled SD WE DRAM read write Asserted for write operations and negated for read operations SD CS 1 0 Row address strobe Select each memory block of SDRAMs connected to the MCF5275 One SDRAM CS signal selects one SDRAM block and connects to the corresponding CS signals SD CKE Synchronous DRAM clock enable Connected directly to the CKE clock enable signal of SDRAMs Enables and disables the clock internal to SDRAM When CKE is low memory can enter a power down mode where operations are suspended or they can enter self refresh mode SD CKE functionality is controlled by DCR COC For designs using external multiplexing setting COC allows SD CKE to provide command bit functionality BS 3 2 Column address strobe For synchronous operation BS 3 2 function as byte enables to the SDRAMs They connect to the DQM signals or mask qualifiers of the SDRAMs DDR_CLKOUT Bus clock output Connects to the CLK input of SDRAMs 5 7 1 2 Address Multiplexing See the SDRAM controller module chapter in the MCF5275 Reference Manual for details on address multiplexing 5 7 2 Ethernet PHY Transceiver Connection The FEC supports an MII interface for 10 100 Mbps Ethernet and a seven wire serial interface for 10 Mbps Ethernet The interface mode is selected by R CNTRL MII MODE In MII mode the 802 3 standard defines and the FEC module supports 1
34. e M5275EVB evaluation board user s manual for an example of how to connect an external PHY Schematics for this board are accessible at the MCF5275 site by navigating to http www freescale com coldfire 5 7 3 BDM Use the BDM interface as shown in the M5275EVB evaluation board user s manual The schematics for this board are accessible at the MCF5275 site by navigating to http www freescale com coldfire MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 13 Mechanicals Pinouts 6 Mechanicals Pinouts 6 1 256 MAPBGA Pinout Figure 3 is a consolidated MCF5274 75 pinout for the 256 MAPBGA package Table 2 lists the signals by group and shows which signals are muxed and bonded on each of the device packages STO SL Mm BOGE os sa es om ms mm mle 4r Ps LPL _ BOOD JEE E FEC1_ FEC1_ FECO_ USB_ USB_ DTOOUT OVDD OVDD SD VDD SD VDD IRQ7 SPEED CLK MDIO MDC TXDO G DT1IN DT1OUT DTOIN OVDD ovop EYS HEU MEN SD VDD SD VDD IRO4 IRQS EIU VS DT2IN DT2OUT DT3IN SD VDD SD VDD VSS OVDD OVDD iRQ2 iRQ3 USB_RP USB E D SD WE DT3OUT SD VDD SD VDD VSS VS OVDD OVDD IRQI USB_TN USB_TP VssPLL K SD SD USB USB BRE SD CKE SD_VDD VSSM SD VDD SD VDD OVDD OVDD OVDD M TXEN EXTAL USB PLL D31 SD CS1 SD DQS3 SD VDD SD VDD SD VDD OVDD OVDD OVDD VDDPLL XTAL SUSP TEST QSPI_ CLK QsPL CLK
35. e fsys 2 maximum specified value Modulation range determined by hardware design fsys 2 fico 2 2RFD 8 6 External Interface Timing Characteristics Table 12 lists processor bus input timings NOTE All processor bus timings are synchronous that is input setup hold and output delay with respect to the rising edge of a reference clock The reference clock is the CLKOUT output All other timing relationships can be derived from these values Table 12 Processor Bus Input Timing Specifications Name Characteristic Symbol Min Max Unit BO CLKOUT teyc 12 ns Control Inputs Bla Control input valid to CLKOUT high tcvcH 9 ns Bib BKPT valid to CLKOUT high iBKVCH 9 ns B2a CLKOUT high to control inputs invalid tcuci 0 ns B2b CLKOUT high to asynchronous control input BKPT invalid tBKNCH 0 ns Data Inputs B4 Data input D 31 16 valid to CLKOUT high tpivcH 4 ns B5 CLKOUT high to data input D 31 16 invalid icupii 0 ns 1 Timing specifications have been indicated taking into account the full drive strength for the pads 2 TEA and TA pins are being referred to as control inputs 3 Refer to figure A 19 MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 24 Freescale Semiconductor Timings listed in Table 12 are shown in Figure 7 The timings are also valid for inputs sampled on the n
36. ead BDY DQS Read SD DQS 3 2 Preamble Postamble N DD10 3 lt l o D 31 16 WD1 WD2 WD3 WD4 DQS Read DQS Read Sh DOS Preamble Postamble SD DQS 3 2 N LL l o pau XO WD1 WD2 WD3 WD4 Figure 14 DDR Read Timing General Purpose I O Timing GPIO can be configured for certain pins of the QSPI DDR control timers UARTS FECO FECI Interrupts and USB interfaces When in GPIO mode the timing specification for these pins is given in Table 16 and Figure 15 Table 16 GPIO Timing NUM Characteristic Symbol Min Max Unit G1 CLKOUT High to GPIO Output Valid tcHPov a 10 ns G2 CLKOUT High to GPIO Output Invalid tcHPo 1 0 ns G3 GPIO Input Valid to CLKOUT High tpycH 9 ns G4 CLKOUT High to GPIO Input Invalid tcupi 1 5 ns MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 32 Freescale Semiconductor Electrical Characteristics acu fA _f N N ne GPIO Outputs XXX 69 GPIO Inputs a Figure 15 GPIO Timing 8 10 Reset and Configuration Override Timing Table 17 Reset and Configuration Override Timing Vpp 2 7 to 3 6 V Vss 0 V T T to Ty NUM Characteristic Symbol Min Max Unit R1 RESET Input valid to CLKOUT High tavcH 9 ns R2 CLKOUT High to RESET Input invalid tcHRI 1 5 ns R3 RESET Input valid Time taivt 5 icvc R4 CLKOUT High to RST
37. egative clock edge CLKOUT 83MHz FJ UM EB Tsetup Input Setup And Hold Invalid Valid Invalid tise Input Rise Time tral Input Fall Time Figure 7 General Input Timing Requirements 8 7 Processor Bus Output Timing Specifications Table 13 lists processor bus output timings Table 13 External Bus Output Timing Specifications Electrical Characteristics TSIZ 1 0 TIP R W invalid MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Name Characteristic Symbol Min Max Unit Control Outputs B6a CLKOUT high to chip selects CS 7 0 valid tcoHcv 0 5tcyc 5 5 ns B6b CLKOUT high to byte enables BS 3 2 valid tcHBv 0 5tcyc 5 5 ns B6c CLKOUT high to output enable OE valid tcHov O 5tpyc 5 5 ns B7 CLKOUT high to control output BS 3 2 OE invalid tcHcol O 5tcyc 1 0 ns B7a CLKOUT high to chip selects invalid tcuci 0 5tcyc 1 0 ns Address and Attribute Outputs B8 CLKOUT high to address A 23 0 and control TS lcHAV 9 ns TSIZ 1 0 TIP R W valid B9 CLKOUT high to address A 23 0 and control TS toHal 1 0 ns Freescale Semiconductor 25 Electrical Characteristics Table 13 External Bus Output Timing Specifications continued Name Characteristic Symbol Min Max Unit Data Outputs B11 CLKOUT high to data output D 31 16 valid icupov
38. ev 4 02 2009 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in
39. ications between I2C SCL and I2C SDA Num Characteristic Min Max Units H Start condition hold time 2 x tcyc ns 12 Clock low period 8 x tcyc ns I3 I2C SCL I2C SDA rise time Vij 20 5 V to Vy 2 4 V 1 ms 14 Data hold time 0 ns I5 I2C SCL I2C SDA fall time Vj 2 2 4 V to Vij 0 5 V 1 ms l6 Clock high time 4 x tcyc ns I7 Data setup time 0 m ns 18 Start condition setup time for repeated start condition only 2 x tcyc ns 19 Stop condition setup time 2 x teye ns Table 24 lists specifications for the PC output timing parameters shown in Figure 21 Table 24 IC Output Timing Specifications between I2C_SCL and I2C_SDA Num Characteristic Min Max Units 11 Start condition hold time 6 Xtcyc m ns I2 Clock low period 10 x tcyc ns 13 12C_SCL I2C_SDA rise time us Vi 0 5 V to Vj 2 4 V I4 Data hold time 7 Xicvc ns I5 I2C SCL I2C SDA fall time 3 ns Vin 2 4 V to Vj 0 5 V l6 Clock high time 10 x tcyc ns I7 Data setup time 2 x tcvc ns lg Start condition setup time for repeated start 20 x tcyc ns condition only I9 Stop condition setup time 10 x tcvc ns Output numbers depend on the value programmed into the IFDR an IFDR programmed with the maximum frequency IFDR 0x20 results in minimum output timings as shown in Table 24 The C interface i
40. ily Hardware Specification Rev 4 40 Freescale Semiconductor Electrical Characteristics TCLK ViH input Figure 23 Test Clock Input Timing TCLK vl Vii Q5 Data Inputs s F Input Data Valid f Data Outputs 37 Data Outputs Output Data Valid Data Outputs Output Data Valid Figure 24 Boundary Scan JTAG Timing TCLK v j Vii zl TDI TMS s Input Data Valid a ond TDO ff Output Data Valid PEEL MEM TDO Y a TDO f Output Data Valid Figure 25 Test Access Port Timing TCLK gt Figure 26 TRST Timing MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 41 Electrical Characteristics 8 16 Debug AC Timing Specifications Table 28 lists specifications for the debug AC timing parameters shown in Figure 28 Table 28 Debug AC Timing Specification 166 MHz Num Characteristic Units Min Max DO PSTCLK cycle time 0 5 tcvc D1 PST DDATA to PSTCLK setup 4 ns D2 CLKOUT to PST DDATA hold 1 0 ns D3 DSI to DSCLK setup 1 x tcyc ES ns D4 DSCLK to DSO hold 4 x tcvc ns D5 DSCLK cycle time 5 x tcyc zm ns D6 BKPT input data setup time to PSTCLK Rise 4 ns D7 BK
41. nts as close to the EXTAL and XTAL oscillator pins as possible e Do not run a high frequency trace around crystal circuit Ensure that the ground for the bypass capacitors is connected to a solid ground trace Tiethe ground trace to the ground pin nearest EXTAL and XTAL This prevents large loop currents in the vicinity of the crystal e Tie the ground pin to the most solid ground in the system e Do not connect the trace that connects the oscillator and the ground plane to any other circuit element This tends to make the oscillator unstable Tie XTAL to ground when an external oscillator is clocking the device MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 11 Design Recommendations 5 7 Interface Recommendations 5 7 1 DDR SDRAM Controller 5 7 1 1 SDRAM Controller Signals in Synchronous Mode Table 3 shows the behavior of SDRAM signals in synchronous mode Table 3 Synchronous DRAM Signal Connections Signal Description should not be interfaced to the SDRAM SD_SRAS signals SD_SRAS Synchronous row address strobe Indicates a valid SDRAM row address is present and can be latched by the SDRAM SD_SRAS should be connected to the corresponding SDRAM SD SRAS Do not confuse SD_SRAS with the DRAM controllers SDRAM CS 1 0 which SD SCAS on the SDRAM SD SCAS Synchronous column address strobe Indicates a valid column address is present and can be latche
42. on rather than 100 tested Proper PC board layout procedures must be followed to achieve specifications Load capacitance determined from crystal manufacturer specifications and includes circuit board parasitics This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register SYNCR 9 Assuming a reference is available at power up lock time is measured from the time Vpp and VpppL are valid to RSTOUT negating If the crystal oscillator is being used as the reference for the PLL then the crystal start up time must be added to the PLL lock time to determine the total start up time tipi 64 4 5 5 xX 1 X Tret where Trot 1 Fret crystal 1 Fret_ext 1 Fret 4 4 and t 1 57x10 x 2 MFD 2 11 PLL is operating in 1 1 PLL mode 12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys 2 Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal Noise injected into the PLL circuitry via Vppp and Vgsp and variation in crystal oscillator frequency increase the jitter percentage for a given interval 13 Based on slow system clock of 33MHz maximum frequency 14 Modulation percentage applies over an interval of 10us or equivalently the modulation rate is 100KHz 15 Modulation rate selected must not result in fsys 2 Value greater than th
43. r 1 1 Bypass External TBD TBD XTAL Output High Voltage Vou V lou 1 0 mA TBD XTAL Output Low Voltage VoL V lo 1 0 mA TBD XTAL Load Capacitance 5 30 pF PLL Lock Time tipi 750 us Power up To Lock Time 9 9 tipik With Crystal Reference 11 ms Without Crystal Reference 750 us 1 1 Mode Clock Skew between CLKOUT and EXTAL 11 kew 1 1 ns Duty Cycle of reference tdc 40 60 fsys 2 Frequency un LOCK Range fuL 3 8 4 1 fsys 2 Frequency LOCK Range fi ck 1 7 2 0 fsys 2 CLKOUT Period Jitter 5 6 9 12 13 Measured at fsys 2 Max Ciitter Peak to peak Jitter Clock edge to clock edge 5 fsys 2 Long Term Jitter Averaged over 2 ms interval 01 Frequency Modulation Range Limit 4 15 Crea 0 8 2 2 fsys 2 fsys 2Max must not be exceeded ICO Frequency fico fret 2 MFD 2 fico 48 83 MHz All values given are initial design targets and subject to change All internal registers retain data at 0 Hz Loss of Reference Frequency is the reference frequency detected internally which transitions the PLL into self clocked mode MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 23 Electrical Characteristics Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f og with default MFD RFD settings Oo O0 This parameter is guaranteed by characterization before qualificati
44. rived from each SD_DQS clock edge It begins with a SD_DQS transition and ends when the last data line becomes valid This input skew must include DDR memory output skew and system level board skew due to routing or other factors Data input hold is derived from each SD DQS clock edge It begins with a SD_DQS transition and ends when the first data line becomes invalid Figure 13 shows a DDR SDRAM write cycle DDR CLKOUT DDR CLKOUT Figure 12 DDR CLKOUT and DDR CLKOUT Crossover Timing MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 30 Freescale Semiconductor DDR CLKOUT DDR CLKOUT WS X Electrical Characteristics lt DD1 gt DD2 m DD3 F DD5 SG SHAS SD SCAS Mmmm CMD gt DD4 DD6 lt A 13 0 gt ROW K co y r DD7 DM 3 2 ie SD DQS 3 2 N N LZ DD7 D 31 16 XND1XWD2XWD3 NDA DD8 Figure 13 DDR Write Timing MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 31 Electrical Characteristics 8 9 F DD1 gt lt DD2 CLKOUT DD3 am WN _ _ gt lt DD5 r CL 2 gt SD_CSn SD_WE nm SD_SRAS SD_SCAS CMD gt DD4 lt lt _ CL 2 5 _ gt A 13 0 ROW COL X gt DQS R
45. s designed to scale the actual data transition time to move it to the middle of the I2C SCL low period The actual position is affected by the prescale and division values programmed into the IFDR however the numbers given in Table 24 are minimum values Because I2C_SCL and I2C_SDA are open collector type outputs which the processor can only actively drive low the time I2C SCL or I2C SDA take to reach a high level depends on external signal capacitance and pull up resistor values Specified at a nominal 50 pF load MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 38 Freescale Semiconductor Electrical Characteristics Figure 21 shows timing for the values in Table 23 and Table 24 gt O lac l peg 5 9 SY oe X ee Ss NP ee Figure 21 I2C Input Output Timings 8 13 DMA Timers Timing Specifications Table 25 Timer Module AC Timing Specifications Name Characteristic Min Max Unit T1 TOIN T1IN T2IN T3IN cycle time 3 x tcyc m ns T2 TOIN T1IN T2IN T3IN pulse width 1xtcvc ns 1 All timing references to CLKOUT are given to its rising edge 8 14 QSPI Electrical Specifications Table 26 QSPI Modules AC Timing Specifications Name Characteristic Min Max Unit QS1 QSPI CS 3 0 to QSPI_CLK 1 510 tcyc QS2 QSPI CLK high to QSPI_DOUT valid 10 ns QS3 QSPI CLK high to QSPI DOUT invalid Output hold 2 ns QS4
46. t 1 0 1 0 Total MCU Limit Includes sum of all stressed pins 10 10 Referto Table 11 for additional PLL specifications WVner is specified as a nominal value only instead of a range so no maximum value is listed 3 This specification is guaranteed by design and is not 100 tested The actual Voy and Vo values for SSTL pads are dependent on the termination and drive strength used The specifications numbers assume no parallel termination 5 Referto the MCF5274 signals chapter for pins having weak internal pull up devices 6 This parameter is characterized before qualification rather than 10096 tested pF load ratings are based on DC loading and are provided as an indication of driver strength High speed interfaces require transmission line analysis to determine proper drive strength and termination Current measured at maximum system clock frequency all modules active and default drive strength with matching load 9 All functional non supply pins are internally clamped to Vgg and their respective Vpp 19 Input must be current limited to the value specified To determine the value of the required current limiting resistor calculate resistance values for positive and negative clamp voltages then use the larger of the two values 11 Power supply must maintain regulation within operating Vpp range during instantaneous and operating maximum current conditions If positive injection current Vin gt Vpp is greater than Ipp the injection current
47. terization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51 2 When Greek letters are not available the thermal characterization parameter is written in conformance with Psi JT The average chip junction temperature Ty in C can be obtained from Ty Tat Pp x Oya 1 Where Ta Ambient Temperature C OJMA Package Thermal Resistance Junction to Ambient C W Pp Pint Pyo MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor 19 Electrical Characteristics Pint lpp x Vpp Watts Chip Internal Power Pio Power Dissipation on Input and Output Pins User Determined For most applications Pyo lt Pint and can be ignored An approximate relationship between Pp and T if Pio is neglected is Py K T 2739 Solving equations 1 and 2 for K gives K Pp x Ta 273 C OJMA x Pp 3 where K is a constant pertaining to the particular part K can be determined from equation 3 by measuring Pp at equilibrium for a known T4 Using this value of K the values of Pp and T can be obtained by solving equations 1 and 2 iteratively for any value of T4 8 3 ESD Protection Table 9 ESD Protection Characteristics Characteristics Symbol Value Units ESD Target for Human Body Model HBM 2000 V ESD Target for Machine Model MM 200 V HBM Circuit Description Reeries 1500
48. this area A e B ee c DI D e E rr e F AM t G e H e J Hd K e L E M o N e P View M M Figure 6 196 MAPBGA Package Dimensions Mechanicals Pinouts NOTES Dimensions are in millimeters Interpret dimensions and tolerances per ASME Y14 5M 1994 Dimension b is measured at the maximum solder ball diameter parallel to datum plane Z Datum Z seating plane is defined by the spherical crowns of the solder balls Parallelism measurement shall exclude any effect of mark on top surface of package Millimeters DIM Min Max A 1 25 1 60 A1 0 27 0 47 A2 1 16 REF b 0 45 0 55 D 15 00 BSC E 15 00 BSC 1 00 BSC 0 50 BSC A Z o 2o z A1 IA zs 196X Detail K Rotated 90 Clockwise MCF5275 Integrated Microprocessor Family Hardware Specification Rev 4 Freescale Semiconductor Ordering Information 7 Ordering Information Table 6 Orderable Part Numbers Freescale Part Y Number Description Package Speed Temperature MCF5274LVM166 0 to 70 C MCF5274L RISC Microprocessor 196 MAPBGA 166 MHz MCF5274LCVM166 40 to 85 C MCF5274VM166 0 to 70 C MCF5274 RISC Microprocessor 256 MAPBGA 166 MHz MCF5274CVM166 40 to 85 C MCF5275LCVM166 MCF5275L RISC Microprocessor 196 MAPBGA 166 MHz 40 to 85 C MCF5275CVM166 MCF5275 RISC Microprocessor 256 MAPBGA 166 MHz 40 to 85 C 8
49. ved Overview Features Signal Descriptions Modes of Operation and Address Multiplexing sections This information can be found in the MCF5275 Reference Manual Removed list of documentation in Section 9 Documentation An up to date list is always available on our web site Changed CLKOUT gt PSTCLK in Section 8 16 Debug AC Timing Specifications Table 10 Update Vpp spec from 1 35 1 65 to 1 4 1 6 Table 13 Timings B6a B6b B6c B7 B7a B9 B12 updated B6a B6b B6c maximum changed from 0 5tcyc 5 to 0 5tcyc 5 5 B7 B7a minimum changed from 0 5tcyc 1 5 to O 5tcy 1 0 B9 B11 minimum changed from 1 5 to 1 0 1 3 Added Section 5 2 1 Supply Voltage Sequencing and Separation Cautions Added thermal characteristics for 196 MAPBGA in Table 8 Updated package dimensions drawing Figure 6 2 Removed second sentence from Section 8 11 1 MII Receive Signal Timing FECn_RXD 3 0 FECn_RXDV FECn RXER and FECn RXCLK and Section 8 11 2 MII Transmit Signal Timing FECn TXD 3 0 FECn TXEN FECn TXER FECn TXCLK regarding no minimum frequency requirement for TXCLK Removed third and fourth paragraphs from Section 8 11 2 MII Transmit Signal Timing FECn TXD 3 0 FECn TXEN FECn TXER FECn TXCLK as this feature is not supported on this device 3 Corrected Ordering Information Table 6 Figure 2 Moved PLLVpp from 1 5V to 3 3V supply line and corrected relevant text in sections below table
50. which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2009 All rights reserved RoHS compliant and or Pb free versions of Freescale products have the functionality and electrical characteristics as their non RoHS compliant and or non Pb free counterparts For further information see http www freescale com or contact your Freescale sales representative For information on Freescale s Environmental Products program go to http www freescale com epp t 2 freescale semiconductor

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